repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in_inst.vhd | 1 | 472 | component pr_region_default_reset_in is
port (
clk : in std_logic := 'X'; -- clk
in_reset : in std_logic := 'X'; -- reset
out_reset : out std_logic -- reset
);
end component pr_region_default_reset_in;
u0 : component pr_region_default_reset_in
port map (
clk => CONNECTED_TO_clk, -- clk.clk
in_reset => CONNECTED_TO_in_reset, -- in_reset.reset
out_reset => CONNECTED_TO_out_reset -- out_reset.reset
);
| mit |
pdt/ttask | test/ghdl/lib/my_lib/sim/and_gate_test.vhdl | 3 | 989 | --
-- and_gate_test.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
library my_lib;
use work.tbmsgs.all;
entity and_gate_test is
end entity;
architecture sim of and_gate_test is
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic;
begin
uut : entity my_lib.and_gate port map (
a => a,
b => b,
c => c
);
test : process
begin
testcase("and gate", 4);
wait for 1 us;
check(c = '0', "output should be '0'");
tested("inputs set to 00");
a <= '1';
wait for 1 us;
check(c = '0', "output should be '0'");
tested("inputs set to 01");
b <= '1';
wait for 1 us;
check(c = '1', "output should be '1'");
tested("inputs set to 11");
a <= '0';
wait for 1 us;
check(c = '0', "output should be '0'");
tested("inputs set to 10");
testcase_complete;
wait;
end process;
end;
| mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/road/simulation/road_tb.vhd | 1 | 4331 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: road_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY road_tb IS
END ENTITY;
ARCHITECTURE road_tb_ARCH OF road_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
road_synth_inst:ENTITY work.road_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit |
capitanov/Stupid_watch | src/top/top_xc3s500e_ex.vhd | 1 | 14017 | --------------------------------------------------------------------------------
--
-- Title : top_xc3s500e_ex.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Top level for timer based on Spartan3E Starter Kit
--
-- Xilinx Spartan3e - XC3S500E-4FG320C
-- Switches, LEDs, TIMER (ds1302), display (lcd1602)
--
-- SW<0> - RESET
-- SW<1> - ENABLE
-- SW<2> - PWM
-- SW<3> - START
--
--
--------------------------------------------------------------------------------
library IEEE; --! main standard libs
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UNISIM; --! xilinx unusim libs
use UNISIM.VCOMPONENTS.ALL;
library WORK; --! user work libs
use WORK.ctrl_types_pkg.all;
entity top_xc3s500e_ex is
generic (
TD : in time := 1 ns ; --! simulation time;
DIV_SCL : in integer := 100 --! clock division for logic counters
);
port(
---- SWITCHES ----
RESET : in std_logic; --! asycnchronous reset: SW(0)
PWM : in std_logic; --! PWM Enable : SW(1)
LCD : in std_logic; --! LCD/LED Switch : SW(2)
START : in std_logic; --! LCD Controller Start : SW(3)
RESTART : in std_logic; --! RESTART Timer DS1302
TEST_LCD : in std_logic; --! TEST LCD DISPLAY
---- PS/2 IO ----
PS2_CLK : in std_logic; --! PS/2 clk (keyboard)
PS2_DATA : in std_logic; --! PS/2 data (keyboad)
---- CLOCK 50 MHz ----
CLK : in std_logic; --! main clock 50 MHz
---- VGA SYNC ----
VGA_HSYNC : out std_logic; --! horiztonal sync
VGA_VSYNC : out std_logic; --! vertical sync
VGA_R : out std_logic; --! VGA Red
VGA_G : out std_logic; --! VGA Green
VGA_B : out std_logic; --! VGA Blue
---- LED DISPLAY ----
LED_X : out std_logic_vector(7 downto 3); --! LEDs Y
--LED_Y : out std_logic_vector(7 downto 0); --! LEDs X
---- BUTTONS ----
KB : in std_logic_vector(5 downto 1); --! Five Buttons
---- SERIAL TIMER ----
T_DT : inout std_logic; --! timer serial data
T_CK : out std_logic; --! timer serial clock (~1 MHz)
T_CE : out std_logic; --! timer serial enable
-- LCD1602 INTERFACE
LCD_DT : out std_logic_vector(7 downto 0); --! LCD Data
LCD_EN : out std_logic; --! LCD Enable
LCD_RW : out std_logic; --! LCD R/W (write - '0', read - '1')
LCD_RS : out std_logic; --! LCD RS (command - '0', data - '1')
-- TEST POINTS
TST : out std_logic_vector(2 downto 0); --! Test points
---- DOORBELL ----
BELL : out std_logic --! BELL (tie to VCC)
);
end top_xc3s500e_ex;
architecture top_xc3s500e_ex of top_xc3s500e_ex is
---------------- SIGNALS DECLARATION ----------------
signal ps2_clock : std_logic;
signal ps2_din : std_logic;
signal sys_reset : std_logic;
signal reset_v : std_logic_vector(6 downto 0);
signal rst : std_logic;
signal rstz : std_logic;
signal RGB : std_logic_vector(2 downto 0);
signal clk_fb : std_logic;
signal clk0 : std_logic;
signal clk_in : std_logic;
signal locked : std_logic;
signal clk_dv : std_logic;
signal rst_dcm : std_logic;
signal v, h : std_logic;
--signal leds : std_logic_vector(8 downto 1);
signal led_hearty : std_logic_vector(7 downto 0);
signal led_heartx : std_logic_vector(7 downto 0);
signal pwm_ena : std_logic;
signal button : std_logic_vector(5 downto 1);
signal switch_lcd : std_logic;
signal time_addr : std_logic_vector(7 downto 0);
signal time_data_i : std_logic_vector(7 downto 0);
signal time_data_o : std_logic_vector(7 downto 0);
signal time_data_v : std_logic;
signal time_rdy : std_logic;
signal time_enable : std_logic;
signal disp_dt : std_logic_vector(7 downto 0);
signal disp_en : std_logic;
signal disp_rw : std_logic;
signal disp_rs : std_logic;
signal disp_start : std_logic;
signal disp_rdy : std_logic;
signal disp_init : std_logic;
signal disp_data : std_logic_vector(7 downto 0);
signal disp_com : std_logic:='0';
signal disp_ena : std_logic;
signal buff_dt : std_logic_vector(7 downto 0);
signal buff_en : std_logic;
signal buff_rw : std_logic;
signal buff_rs : std_logic;
signal buff_xx : std_logic_vector(7 downto 3);
--signal cnt : std_logic_vector(5 downto 0):="000000";
signal rstart : std_logic;
signal disp_rdyz : std_logic;
signal disp_rdyt : std_logic;
signal ds_data_i : std_logic;
signal ds_data_o : std_logic;
signal ds_data_t : std_logic;
signal ds_data_tn : std_logic;
signal load_ena : std_logic;
signal load_dat : std_logic_vector(7 downto 0);
signal load_addr : std_logic_vector(4 downto 0);
signal test_mode : std_logic;
begin
disp_rdyz <= not disp_rdy after td when rising_edge(clk_in);
disp_rdyt <= disp_rdyz and disp_rdy after td when rising_edge(clk_in);
---------------- TIMER TRANSFER ----------------
x_SET_TIME: cl_timer_data
generic map (
TIME_SECS => 47, -- seconds
TIME_MINS => 59, -- minutes
TIME_HRS => 13, -- hours
TIME_DTS => 19, -- dates
TIME_MTHS => 09, -- months
TIME_DAYS => 06, -- days
TIME_YRS => 15, -- years
TD => TD -- simulation time;
)
port map(
---- Global signals ----
reset => reset_v(0), -- asycnchronous reset
clk => clk_in, -- clock 50 MHz
restart => rstart, -- restart timer
---- DS1302 signals ----
addr => time_addr, -- address for timer
data_o => time_data_i, -- input data (to timer)
data_i => time_data_o, -- output data (from timer)
data_v => time_data_v, -- valid data (from timer)
ready => time_rdy, -- timer is ready for data
enable => time_enable, -- timer enable
---- LCD1602 signals ----
load_ena => load_ena, -- enable writing to LCD RAM
load_dat => load_dat, -- data to LCD RAM
load_addr => load_addr -- address to LCD RAM
);
---------------- LCD1602 TRANSFER ----------------
x_LCD_TST: cl_lcd_data
generic map (
TD => TD -- simulation time;
)
port map(
reset => reset_v(1), -- system frequency (50 MHz)
clk => clk_in, -- '0' - negative reset
test_mode => test_mode, -- select mode: test message or timer
load_ena => load_ena, -- load new data
load_dat => load_dat, -- new data;
load_addr => load_addr, -- new address;
disp_data => disp_data, -- data to display
disp_ena => disp_ena, -- enable for data
disp_init => disp_init, -- ready for data
disp_rdyt => disp_rdyt -- valid pulse for data
);
---------------- LCD1602 CONTROLLER ----------------
x_LCD1602: rtl_lcd1602
generic map (
TD => TD, -- simulation time;
DIV_SCL => 5000 -- clock division for SCL: clk50m/DIV_SCL
)
port map(
-- global ports
clk50m => clk_in, -- system frequency (50 MHz)
rstn => reset_v(2), -- '0' - negative reset
-- main interface
start => disp_start, -- start
data_ena => disp_ena, -- data enable (S)
data_int => disp_data, -- data Tx
data_sel => disp_com, -- select: '0' - data, '1' - command
data_rw => '0', -- WRITE ONLY;
lcd_ready => disp_rdy, -- ready for data
lcd_init => disp_init, -- lcd initialization complete
-- lcd1602 interface
lcd_dt => disp_dt, -- lcd data
lcd_en => disp_en, -- lcd clock enable
lcd_rw => disp_rw, -- lcd r/w: write - '0', read - '1'
lcd_rs => disp_rs -- lcd set: command - '0', data - '1'
);
---------------- DS1302 CONTROLLER ----------------
x_DS1302: rtl_ds1302
generic map (
TD => TD, -- simulation time;
DIV_SCL => DIV_SCL -- clock division for SCL: clk50m/DIV_SCL
)
port map(
-- global ports
clk50m => clk_in, -- system frequency (50 MHz)
rstn => reset_v(3), -- '0' - negative reset
-- main interface
enable => time_enable, -- i2c start (S)
addr_i => time_addr, -- address Tx: 7 bit - always '1', 0 bit - R/W ('0' - write, '1' - read)
data_i => time_data_i, -- data Tx
data_o => time_data_o, -- data Rx
data_v => time_data_v, -- valid Rx
ready => time_rdy, -- ready
-- serial interface
--ds_data => T_DT,--ds_data, -- serial data
ds_data_i => ds_data_i, -- serial data input
ds_data_o => ds_data_o, -- serial data output
ds_data_t => ds_data_t, -- serial data enable
ds_clk => T_CK, -- serial clock
ds_ena => T_CE -- clock enable for i2c
);
---------------- MINESWEEPER GAME ----------------
x_MAIN_BLOCK : rtl_game_int
port map(
clk => clk_dv, -- 25 MHz freq;
reset => reset_v(4), -- GLOBAL RESET
ps2_clk => ps2_clock, -- PS/2 CLOCK
ps2_data => ps2_din, -- PS/2 SERIAL DATA
h_vga => H, -- HORIZONTAL
v_vga => V, -- VERTICAL
rgb => RGB -- (R-G-B)
--leds => LEDS -- LEDs
);
---------------- HEART XY 8X8 ----------------
pr_lcd_sw: process(clk_in, reset_v(5)) is
begin
if (reset_v(5) = '0') then
buff_dt <= x"00";
buff_en <= '0';
buff_rw <= '0';
buff_rs <= '0';
elsif rising_edge(clk_in) then
if switch_lcd = '1' then
buff_dt <= disp_dt;
buff_en <= disp_en;
buff_rw <= disp_rw;
buff_rs <= disp_rs;
else
x_rev: for ii in 0 to 7 loop
buff_dt(ii) <= led_hearty(7-ii);
end loop;
buff_rs <= led_heartx(0);
buff_rw <= led_heartx(1);
buff_en <= led_heartx(2);
buff_xx <= led_heartx(7 downto 3);
end if;
end if;
end process;
ds_data_tn <= ds_data_t;
---------------- I/O BUFFERS ----------------
TST(0) <= ds_data_o;
TST(1) <= ds_data_tn;
TST(2) <= ds_data_i;
xDSIO: iobuf port map(i => ds_data_o, o => ds_data_i, io => T_DT, t => ds_data_tn);
xPS2C: ibuf port map(i => ps2_clk, o => ps2_clock);
xPS2D: ibuf port map(i => ps2_data, o => ps2_din);
xRESET: ibuf port map(i => RESET, o => rst);
xPWM: ibuf port map(i => PWM, o => pwm_ena);
xSTART: ibuf port map(i => START, o => disp_start);
xRESTART: ibuf port map(i => RESTART, o => rstart);
xBELL: obuf port map(i => '1', o => BELL);
xVGA_v: obuf port map(i => v, o => VGA_VSYNC);
xVGA_h: obuf port map(i => h, o => VGA_HSYNC);
xVGA_R: obuf port map(i => RGB(2), o => VGA_R);
xVGA_G: obuf port map(i => RGB(1), o => VGA_G);
xVGA_B: obuf port map(i => RGB(0), o => VGA_B);
xLCD_EN: obuf port map(i => buff_en, o => LCD_EN);
xLCD_RW: obuf port map(i => buff_rw, o => LCD_RW);
xLCD_RS: obuf port map(i => buff_rs, o => LCD_RS);
xLCD_DT: for ii in 0 to 7 generate
xLCD_DATA: obuf port map(i => buff_dt(ii), o => LCD_DT(ii));
end generate;
xLCD_SW: ibuf port map(i => LCD, o => switch_lcd);
xLCD_TST: ibuf port map(i => TEST_LCD, o => test_mode);
xBUTS: for ii in 1 to 5 generate
xswitch: ibuf port map(i => KB(ii), o => button(ii));
end generate;
-- LEDS:
xLED_XY: for ii in 3 to 7 generate
ledx: obuf port map(i => buff_xx(ii), o => LED_X(ii));
-- ledy: obuf port map(i => led_hearty(ii), o => LED_Y(ii));
end generate;
---------------- DEBOUNCE ----------------
xCTRL_8x8 : ctrl_leds
port map (
-- System signals:
clk => clk0,
clk_dv => clk_dv,
reset => reset_v(6),
pwm_ena => pwm_ena,
-- Buttons:
cbut => button,
-- Leds vectors:
led_x => led_heartx,
led_y => led_hearty
);
---------------- DCM CLOCK ----------------
xCLKFB: bufg port map(i => clk0, o => clk_fb);
xCLKIN: ibufg port map(i => clk,o => clk_in);
sys_reset <= (rstz and locked) after td when rising_edge(clk_in);
xFD_RST: ctrl_fanout
generic map(
FD_WIDTH => 7)
port map(
clk => clk_in,
data_in => sys_reset,
data_out => reset_v
);
--xgen_rst: for ii in 0 to 7 generate
--reset_v(ii) <= sys_reset after td when rising_edge(clk_in);
--end generate;
xSRL_RESET: srlc16
generic map (
init => x"0000"
)
port map(
Q15 => rstz,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CLK => clk_in,
D => rst -- '1',
);
rst_dcm <= not rst;
---------------- CLOCK GENERATOR - DCM ----------------
xDCM_CLK_VGA : dcm
generic map(
--DCM_AUTOCALIBRATION => FALSE, -- DCM ADV
CLKDV_DIVIDE => 2.0, -- clk divide for CLKIN: Fdv = Fclkin / CLK_DIV
CLKFX_DIVIDE => 2, -- clk divide for CLKFX and CLKFX180 : Ffx = (Fclkin * MULTIPLY) / CLKFX_DIV
CLKFX_MULTIPLY => 2, -- clk multiply for CLKFX and CLKFX180 : Ffx = (Fclkin * MULTIPLY) / CLKFX_DIV
CLKIN_DIVIDE_BY_2 => FALSE, -- divide clk / 2 before DCM block
CLKIN_PERIOD => 20.0, -- clk period in ns (for DRC)
CLKOUT_PHASE_SHIFT => "NONE", -- phase shift mode: NONE, FIXED, VARIABLE
CLK_FEEDBACK => "1X", -- freq on the feedback clock: 1x, 2x, None
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- clk delay alignment
DFS_FREQUENCY_MODE => "LOW", -- freq mode CLKFX and CLKFX180: LOW, HIGH
DLL_FREQUENCY_MODE => "LOW", -- freq mode CLKIN: LOW, HIGH
DUTY_CYCLE_CORRECTION => TRUE, -- 50% duty-cycle correction for the CLK0, CLK90, CLK180 and CLK270: TRUE, FALSE
PHASE_SHIFT => 0 -- phase shift (with CLKOUT_PHASE_SHIFT): -255 to 255
)
port map(
clk0 => clk0,
-- clk180 => clk180,
-- clk270 => clk270,
-- clk2x => clk2x,
-- clk2x180 => clk2x180,
-- clk90 => clk90,
clkdv => clk_dv,
-- clkfx => clkfx,
-- clkfx180 => clkfx180,
locked => locked,
-- status => status,
-- psdone => psdone,
clkfb => clk_fb,
clkin => clk_in,
-- dssen => dssen,
-- psclk => psclk,
psen => '0',
psincdec => '0',
rst => rst_dcm
);
end top_xc3s500e_ex; | mit |
laurocruz/snakes_vhdl | src/snake_lib/make_map.vhd | 1 | 2607 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
-- controlador do mapa do jogo
ENTITY make_map IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
-- clock do jogo
PORT (clock : IN STD_LOGIC;
-- reseta o jogo
reset : IN STD_LOGIC;
-- aumento do tamanho
eaten : IN STD_LOGIC;
snake_size : IN INTEGER RANGE 0 TO N*M;
-- direcao para onde a cobra esta se movendo
-- 11 : cima
-- 00 : baixo
-- 10 : esquerda
-- 01 : direita
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-- posicoes da cobra no mapa
snake_body : OUT int_array);
END make_map;
ARCHITECTURE Behavior OF make_map IS
-- Vetor de estruturas de dois inteiros que representam a posição de cada parte da cobra (l,c)
--TYPE snake_body IS array (0 to N*M-1) OF INTEGER RANGE 0 TO N*M-1;
--SIGNAL snake : snake_body;
SIGNAL snake : int_array;
SIGNAL dir_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
snake_body <= snake;
dir_s <= dir;
PROCESS (clock, reset, eaten)
VARIABLE j : INTEGER RANGE 0 TO N*M;
VARIABLE DIF : INTEGER RANGE 0 TO M;
--VARIABLE index : INTEGER RANGE 0 TO N*M;
--VARIABLE map_s : STD_LOGIC_VECTOR(0 TO N*M-1);
BEGIN
IF (reset = '1') THEN
FOR i in 0 to INITIAL_SIZE-1 LOOP
snake(i) <= (N/2) + (i+M/2)*M;
END LOOP;
FOR i in INITIAL_SIZE to N*M-1 LOOP
snake(i) <= -1;
END LOOP;
ELSIF (eaten = '1') THEN
DIF := snake(snake_size-1) - snake(snake_size-2);
snake(snake_size) <= snake(snake_size-1) + DIF;
ELSIF (clock'EVENT and clock = '1') THEN
j := 0;
WHILE (j+1 < M*N and not(snake(j+1) = -1)) LOOP
snake(j+1) <= snake(j);
j := j + 1;
END LOOP;
--FOR i IN 0 TO snake_size-2 LOOP
-- snake(i+1) <= snake(i);
--END LOOP;
IF (dir_s = "00") THEN
snake(0) <= snake(0) + M;
ELSIF (dir_s = "01") THEN
snake(0) <= snake(0) + 1;
ELSIF (dir_s = "10") THEN
snake(0) <= snake(0) - 1;
ELSE
snake(0) <= snake(0) - M;
END IF;
--map_s := (OTHERS => '0');
--j := 0;
--WHILE (j < M*N and not(snake(j) = -1)) LOOP
-- index := snake(j);
-- map_s(index) := '1';
-- j := j + 1;
--END LOOP;
END IF;
--gmap <= map_s;
END PROCESS;
END Behavior;
| mit |
IamVNIE/Hardware-Security | Interfaces/UART_Version_3/Uart_working/des_decrypt_wit_out - Copy.vhd | 2 | 15062 | ------------------------------------------
--------------PACKET----------------------
----MSB--- EN G1 G2 G3 G6 G7 ---LSB-------
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DISPLAY_UNIT is
generic (N: integer := 20; M: integer:= 5);--- N = No of Bits in Test vector + 1 (For Enable)
--- M = No of Bits Reuired to count the N
port(
TXD : out std_logic := '1';RXD: in std_logic := '1';
st_indicator: OUT std_logic_vector(2 downto 0);
--DU : in STD_LOGIC; EN : in STD_LOGIC;
ROC : in STD_LOGIC;REF : in STD_LOGIC;
--G1,G2,G3,G6: in STD_LOGIC;
LEDS: out std_logic_vector(7 downto 0) := "11111111";
clk : in std_logic; OUTDIGIT: out STD_LOGIC_VECTOR (7 downto 0);
seg_out: out std_logic_vector(6 downto 0);
dis: out std_logic_vector(7 downto 0);
ANODE : out STD_LOGIC_VECTOR (3 downto 0);RST: in std_logic := '0'
);
end DISPLAY_UNIT;
architecture behavior of DISPLAY_UNIT is
component Dec2LED
port (CLK: in STD_LOGIC; X: in STD_LOGIC_VECTOR (3 downto 0); Y: out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal DIGIT : STD_LOGIC_VECTOR(7 downto 0) :="00000000";
type arr is array(0 to 15) of std_logic_vector(7 downto 0);
signal NAME: arr;
type ARR2 is array(0 to 3) of std_logic_vector(7 downto 0);
signal TMPDGT: ARR2;
signal TEMP: STD_LOGIC_VECTOR(3 downto 0) :="0111";
signal CLKM : STD_LOGIC :='0';
signal Z : integer :=0;
signal G : integer :=30;
signal NAMEA : integer :=3;
signal NAMEB : integer :=2;
signal NAMEC : integer :=1;
signal NAMED : integer :=0;
signal pt1:STD_LOGIC_VECTOR(32 downto 0);
COMPONENT Circuit17
PORT(
TE,ROSEL : IN std_logic;
G1 : IN std_logic;
G2 : IN std_logic;
G3 : IN std_logic;
G6 : IN std_logic;
G7 : IN std_logic;
G22 : OUT std_logic;
G23 : OUT std_logic;
GEX: OUT std_logic
);
END COMPONENT;
component RS232RefComp
Port ( TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic;
DBIN : in std_logic_vector (7 downto 0);
DBOUT : out std_logic_vector (7 downto 0);
RDA : inout std_logic;
TBE : inout std_logic := '1';
RD : in std_logic;
WR : in std_logic;
PE : out std_logic;
FE : out std_logic;
OE : out std_logic;
RST : in std_logic := '0');
end component;
COMPONENT HEX2ASC
PORT(
VAL : IN std_logic_vector(3 downto 0);
CLK : IN std_logic;
Y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
component ascii_hex
Port ( clk : in std_logic; ascii : in std_logic_vector(7 downto 0);hex : inout std_logic_vector(3 downto 0)
);
end component;
type StateType is (Idle, cnt, receive,Decide, send1, send2,
stInput,stOutput,Test_vector,DisplayI );
signal dbInSig : std_logic_vector(7 downto 0);
signal dbOutSig, dbOutSig2, dbOutSig3: std_logic_vector(7 downto 0);
signal hex0, hex1, hex2, hex3, hex4, hex5 : std_logic_vector(3 downto 0);
signal rdaSig : std_logic;
signal tbeSig : std_logic;
signal rdSig : std_logic;
signal wrSig : std_logic;
signal peSig : std_logic;
signal feSig : std_logic;
signal oeSig : std_logic;
signal state : StateType;
signal RST_TEMP: Std_logic;
signal reg_in : std_logic_vector(7 downto 0);
signal count : std_logic_vector(3 downto 0);
signal ro : std_logic_vector(63 downto 0);
signal St_indic: std_logic_vector(2 downto 0);
signal Rflag : std_logic_vector(M-1 downto 0);
Signal Shift_Length: std_logic_vector(M-1 downto 0);
signal tv : std_logic_vector(N-1 downto 0);
signal i_cntx: std_logic_vector(2 downto 0);
signal big_counter: std_logic_vector(31 downto 0);
signal temps: std_logic_vector (3 downto 0);
signal osc,out1,GEX : std_logic;
signal G1,G2,G3,G6,G7,EN,D: std_logic;
--signal G1,G2,G3,G6,G7,DU,EN,D: std_logic;
signal ROSEL,DU: std_logic:='1';
signal countR,count_RO,count_RO_t,count1: std_logic_vector(31 downto 0);
signal packet: std_logic_vector(N-1 downto 0);
begin
st_indicator<=St_indic;
PROCESS(clk) BEGIN
IF(clk'EVENT AND clk='1') THEN
big_counter<=big_counter+'1';
END IF;
END PROCESS;
i_cntx <= big_counter(13 downto 11);
with temps select
seg_out <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when "1111",
"1111110" when others;
with i_cntx select
dis<= "11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
"01111111" when "111",
"11111111" when others;
with i_cntx select
temps <= dbOutSig(3 downto 0) when "000",
dbOutSig(7 downto 4) when "001",
dbOutSig2(3 downto 0) when "010",
dbOutSig2(7 downto 4) when "011",
dbOutSig3(3 downto 0) when "100",
dbOutSig3(7 downto 4) when "101",
--dbOutSig2(11 downto 8) when "110",
x"0" when others;
Shift_Length<= std_logic_vector( to_unsigned( N,M ));
-- LEDS(7) <= Count_RO_t(0);
-- LEDS(6) <= Count_RO_t(1);
-- LEDS(5) <= Count_RO_t(2);
-- LEDS(4) <= Count_RO_t(3);
-- LEDS(3) <= Count_RO_t(4);
-- LEDS(2) <= Count_RO_t(5);
-- LEDS(1) <= Count_RO_t(6);
-- LEDS(0) <= OSC;
G7<=Packet(N-6);
G6<=Packet(N-5);
G3<=Packet(N-4);
G2<=Packet(N-3);
G1<=Packet(N-2);
EN<=Packet(N-1);
LEDS(7) <= G7;
LEDS(6) <= G6;
LEDS(5) <= G3;
LEDS(4) <= G2;
LEDS(3) <= G1;
LEDS(2) <= Du;
LEDS(1) <= En;
LEDS(0) <= OSC;
UART: RS232RefComp port map ( TXD => TXD,
RXD => RXD,
CLK => CLK,
DBIN => dbInSig,
DBOUT => dbOutSig,
RDA => rdaSig,
TBE => tbeSig,
RD => rdSig,
WR => wrSig,
PE => peSig,
FE => feSig,
OE => oeSig,
RST => RST);
--------------RO1------------------
RO2: Circuit17 PORT MAP(EN,ROSEL,G1,G2,G3,G6,G7,GEX,out1,osc);
-------------REFERENCE COUNT-------
process(clk,en)
Begin
if en ='0' then
countR <= (others=>'0');
elsif clk='1' and clk'event then
if countR<x"40000000" then
countR <= countR +'1';
end if;
end if;
end process;
-------------RO COUNT-------------
process(osc,en,countR,clk)
Begin
if en ='0' then
count_RO_t <= (others=>'0');
elsif osc='1' and osc'event then
if countR<x"40000000" then
count_RO_t <= count_RO_t +'1';
elsif countR=x"40000000" then
count_RO<= count_RO_t;
count1<= countR;
end if;
end if;
end process;
----------------------------------
-----------------------------CONVERSION TO ASCII----------------------------
--D1: HEX2ASC PORT MAP(count_RO(31 DOWNTO 28),CLK,RO(63 downto 56));
--D2: HEX2ASC PORT MAP(count_RO(27 DOWNTO 24),CLK,RO(55 downto 48));
--D3: HEX2ASC PORT MAP(count_RO(23 DOWNTO 20),CLK,RO(47 downto 40));
--D4: HEX2ASC PORT MAP(count_RO(19 DOWNTO 16),CLK,RO(39 downto 32));
--D5: HEX2ASC PORT MAP(count_RO(15 DOWNTO 12),CLK,RO(31 downto 24));
--D6: HEX2ASC PORT MAP(count_RO(11 DOWNTO 8),CLK,RO(23 downto 16));
--D7: HEX2ASC PORT MAP(count_RO(7 DOWNTO 4),CLK,RO(15 downto 8));
--D8: HEX2ASC PORT MAP(count_RO(3 DOWNTO 0),CLK,RO(7 downto 0));
----------------------------------------------------------------------------
H1: ascii_hex port map(clk=>clk, ascii=>dbOutSig, hex=>hex0);
--H1: ascii_hex PORT MAP(CLK,RO(63 downto 56),count_RO(31 DOWNTO 28));
--H2: ascii_hex PORT MAP(CLK,RO(55 downto 48),count_RO(27 DOWNTO 24));
--H3: ascii_hex PORT MAP(CLK,RO(47 downto 40),count_RO(23 DOWNTO 20));
--H4: ascii_hex PORT MAP(CLK,RO(39 downto 32),count_RO(19 DOWNTO 16));
--H5: ascii_hex PORT MAP(CLK,RO(31 downto 24),count_RO(15 DOWNTO 12));
--H6: ascii_hex PORT MAP(CLK,RO(23 downto 16),count_RO(11 DOWNTO 8));
--H7: ascii_hex PORT MAP(CLK,RO(15 downto 8),count_RO(7 DOWNTO 4));
--H8: ascii_hex PORT MAP(CLK,RO(7 downto 0),count_RO(3 DOWNTO 0));
process(clk, rst)
begin
if(rst = '1')then
state <= idle;
rdSig <= '0';
wrSig <= '0';
RST_TEMP <='1';
reg_in <= (others =>'0');
dbInSig <= (others =>'0');
count <= "1111";
Rflag<=(Others=>'0');
tv<=(Others=>'0');
elsif(clk'event and clk = '1')then
case state is
when idle => rdSig <= '0';
wrSig <= '0';
RST_TEMP <='0';
Rflag<=(Others=>'0');
count<= "0000";
St_indic<= "111";
if(rdaSig = '1')then
state <= receive;
end if;
when receive => reg_in <= dbOutSig;
state <= decide;
when decide => St_indic<="100";
if (dbOutSig = x"49") then
state <= StInput;
elsif (dbOutSig<=x"69") then
state <= StInput;
elsif (dbOutSig = x"4F") then
state <= StOutput;
elsif (dbOutSig<=x"6F") then
state <= StOutput;
else
state<= Idle;
End if;
when StInput =>
St_indic<="000";
rdsig <= '0';
wrsig <= '0';
if (rdaSig = '1') then
state<= test_vector;
end if;
when test_vector =>
-- if (dboutsig > x"2F" and dboutsig < x"3A") then
-- tv<=tv(N-5 downto 0) & hex0;
-- Rflag<= Rflag +'1';
-- state<= displayI;
-- elsif (dboutsig > x"60" and dboutsig < x"67") then
-- tv<=tv(N-5 downto 0) & hex0;
-- Rflag<= Rflag +'1';
-- state<= displayI;
if dboutsig = x"30" then
tv<=tv(N-2 downto 0) & '0';
Rflag<= Rflag +'1';
state<= displayI;
elsif dboutsig = x"31" then
tv<=tv(N-2 downto 0) & '1';
Rflag<= Rflag +'1';
state<= displayI;
elsif (dboutsig = x"72") then
tv<=(Others=>'0');
state<= Idle ;
elsif (dboutsig = x"52") then
tv<=(Others=>'0');
state<= Idle;
elsif (dbOutSig = x"4F") then
state <= StOutput;
elsif (dbOutSig<=x"6F") then
state <= StOutput;
else
tv<= tv;
state<= idle;
end if;
state<= displayI;
St_indic<="110";
When displayI =>
St_indic<="001";
wrsig<='1'; rdsig<='1';
dbInsig<=dbOutsig;
If Rflag =Shift_length then
state<= Idle;
else
state <= StInput;
end if;
when stoutput =>
if count = "0001" then
dbInSig <=x"20";
ELSif count = "1010" then
dbInSig <=x"0A";
elsif count = "0010" then
dbInSig <=ro (63 downto 56);
elsif count = "0011" then
dbInSig <=ro (55 downto 48);
elsif count = "0100" then
dbInSig <=ro (47 downto 40);
elsif count = "0101" then
dbInSig <=ro (39 downto 32);
elsif count = "0110" then
dbInSig <=ro (31 downto 24);
elsif count = "0111" then
dbInSig <=ro (23 downto 16);
elsif count = "1000" then
dbInSig <=ro (15 downto 8);
elsif count = "1001" then
dbInSig <=ro (7 downto 0);
end if;
rdsig<='0'; wrsig<='0';
if TBEsig='1' then
state <= send1;
end if;
when send1 => rdSig <= '1';
wrSig <= '1';
state <= cnt;
when cnt => count <= count +'1';
state<= send2;
when send2 => if (count > "1010") then
state <= idle;
rdsig<= '0';
wrsig<='0';
else
-- count <= "0000";
state <= stOutput;
end if;
end case;
end if;
end process;
Packet <=TV(N-1 Downto 0);
HCONV1: HEX2ASC port map (CLK => CLK, VAL =>packet(3 downto 0), Y =>ro(7 downto 0));
HCONV2: HEX2ASC port map (CLK => CLK, VAL =>packet(7 downto 4), Y =>ro(15 downto 8));
HCONV3: HEX2ASC port map (CLK => CLK, VAL =>packet(11 downto 8), Y =>ro(23 downto 16));
HCONV4: HEX2ASC port map (CLK => CLK, VAL =>packet(15 downto 12), Y =>ro(31 downto 24));
--Packet <= '0' & hex0 & hex1 ;
-----INTERFACING TO FPGA-------
----- 7 SEGMENT CLOCK----------
process (CLK)
begin
if CLK'event and CLK='1' then
if Z=200000 then
CLKM <= '1';
elsif Z=400000 then
CLKM <= '0';
Z <= 0;
end if;
if Z /=400000 then
Z <= Z+1;
end if;
end if;
end process;
NAME(14)<= "11111111";
NAME(13)<= "11111111";
NAME(12)<= "11111111";
NAME(15)<= "11111111";
process(ROC,REF,EN,DU,countR,count_RO)
begin
if REF='1' and DU='1' then
pt1(32 downto 1)<= countr;
NAME(0)<= "10101111";
NAME(1)<= "10000110";
NAME(2)<= "10001110";
NAME(3)<= "10111111";
elsif ROC='1' then
pt1(32 downto 1)<= count_RO;
NAME(0)<= "10101111";
NAME(1)<= "11000000";
NAME(2)<= "11000110";
NAME(3)<= "10111111";
else
pt1(32 downto 1)<= "00000000000000000000000000000" & GEX & out1 & osc;
NAME(0)<= "10111111";
NAME(1)<= "10111111";
NAME(2)<= "10111111";
NAME(3)<= "10111111";
end if;
end process;
CONV1: Dec2LED port map (CLK => CLK, X => pt1(32 downto 29), Y => NAME(4));
CONV2: Dec2LED port map (CLK => CLK, X => pt1(28 downto 25), Y => NAME(5));
CONV3: Dec2LED port map (CLK => CLK, X => pt1(24 downto 21), Y => NAME(6));
CONV4: Dec2LED port map (CLK => CLK, X => pt1(20 downto 17), Y => NAME(7));
CONV5: Dec2LED port map (CLK => CLK, X => pt1(16 downto 13), Y => NAME(8));
CONV6: Dec2LED port map (CLK => CLK, X => pt1(12 downto 9), Y => NAME(9));
CONV7: Dec2LED port map (CLK => CLK, X => pt1(8 downto 5), Y => NAME(10));
CONV8: Dec2LED port map (CLK => CLK, X => pt1(4 downto 1), Y => NAME(11));
process (CLKM)
begin
if CLKM'event and CLKM='1' then
if DU='1' then
if G=60 then
TMPDGT(0) <= NAME(NAMEA);
if NAMEA=15 then
NAMEA <= 0;
else
NAMEA <= NAMEA + 1;
end if;
TMPDGT(1) <= NAME(NAMEB);
if NAMEB=15 then
NAMEB <= 0;
else
NAMEB <= NAMEB + 1;
end if;
TMPDGT(2) <= NAME(NAMEC);
if NAMEC=15 then
NAMEC <= 0;
else
NAMEC <= NAMEC + 1;
end if;
TMPDGT(3) <= NAME(NAMED);
if NAMED=15 then
NAMED <= 0;
else
NAMED <= NAMED + 1;
end if;
G <= 0;
else
G <= G + 1;
end if;
end if;
end if;
end process;
process (CLKM)
begin
if CLKM'event and CLKM='1' then
if DU='1' then
if TEMP="0111" then
TEMP <= "1110";
DIGIT <= TMPDGT(0);
elsif TEMP="1110" then
TEMP <= "1101";
DIGIT <= TMPDGT(1);
elsif TEMP="1101" then
TEMP <= "1011";
DIGIT <= TMPDGT(2);
else
TEMP <= "0111";
DIGIT <= TMPDGT(3);
end if;
end if;
end if;
end process;
ANODE <= TEMP;
OUTDIGIT <= DIGIT;
end behavior; | mit |
pdt/ttask | test/fpga-sim/lib/my_lib/sim/or_gate_test.vhdl | 3 | 984 | --
-- or_gate_test.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
library my_lib;
use work.tbmsgs.all;
entity or_gate_test is
end entity;
architecture sim of or_gate_test is
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic;
begin
uut : entity my_lib.or_gate port map (
a => a,
b => b,
c => c
);
test : process
begin
testcase("or gate", 4);
wait for 1 us;
check(c = '0', "output should be '0'");
tested("inputs set to 00");
a <= '1';
wait for 1 us;
check(c = '1', "output should be '1'");
tested("inputs set to 01");
b <= '1';
wait for 1 us;
check(c = '1', "output should be '1'");
tested("inputs set to 11");
a <= '0';
wait for 1 us;
check(c = '1', "output should be '1'");
tested("inputs set to 10");
testcase_complete;
wait;
end process;
end;
| mit |
capitanov/Stupid_watch | src/rtl/chips/cl_lcd_data.vhd | 1 | 3302 | -------------------------------------------------------------------------------
--
-- Title : cl_lcd_data
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : kapitanov@insys.ru
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Data for testing LCD Display LCD1602
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cl_lcd_data is
generic (
TD : in time --! simulation time;
);
port(
reset : in std_logic; --! system reset
clk : in std_logic; --! clock 50 MHz
test_mode : in std_logic; --! select mode: test message or timer message
load_ena : in std_logic; --! load new data
load_dat : in std_logic_vector(7 downto 0); --! new data;
load_addr : in std_logic_vector(4 downto 0); --! new address;
disp_data : out std_logic_vector(7 downto 0); --! data to display
disp_ena : out std_logic; --! enable for data
disp_init : in std_logic; --! ready for data
disp_rdyt : in std_logic --! valid pulse for data
);
end cl_lcd_data;
architecture cl_lcd_data of cl_lcd_data is
signal cnt : std_logic_vector(4 downto 0):="00000";
--signal data : std_logic_vector(7 downto 0);
type ROM is array (integer range 0 to 31) of std_logic_vector(7 downto 0);
-- MEMORY for TIMER:
signal mem_test : ROM:=( x"21", x"21", x"A5", x"A5", x"A5", x"A5", x"A5", x"2F", x"A5", x"A5", x"2F", x"A5", x"A5", x"A5", x"A5", x"A5",
x"21", x"21", x"A5", x"A5", x"A5", x"A5", x"A5", x"2F", x"A5", x"A5", x"2F", x"A5", x"A5", x"A5", x"A5", x"A5");
-- HELLO HABR: www.habrahabr.ru
signal mem_habr : ROM:=( x"2A", x"2A", x"A5", x"A5", x"48", x"65", x"6C", x"6C", x"6F", x"A0", x"48", x"41", x"42", x"52", x"A5", x"A5",
x"2A", x"2A", x"46", x"72", x"6F", x"6D", x"A0", x"4B", x"61", x"70", x"69", x"74", x"61", x"6E", x"6F", x"76");
attribute RAM_STYLE : string;
attribute RAM_STYLE of mem_test: signal is "DISTRIBUTED";
attribute RAM_STYLE of mem_habr: signal is "DISTRIBUTED";
begin
pr_rom8x32: process(clk) is
begin
if(rising_edge(clk)) then
if (load_ena = '1') then
mem_test(conv_integer(unsigned(load_addr))) <= load_dat after td;
end if;
--data <= mem_test(conv_integer(unsigned(load_addr)));
end if;
end process;
-- display 2x16 on LCD
pr_2to8: process(clk, reset) is
begin
if (reset = '0') then
disp_data <= x"00";
disp_ena <= '0';
cnt <= "00000";
elsif (rising_edge(clk)) then
if (disp_init = '1') then
if (disp_rdyt = '1') then
disp_ena <= '1' after td;
if (test_mode = '0') then
disp_data <= mem_test(conv_integer(cnt)) after td;
else
disp_data <= mem_habr(conv_integer(cnt)) after td;
end if;
if (cnt = "11111") then
cnt <= "00000" after td;
else
cnt <= cnt + 1 after td;
end if;
end if;
else
disp_data <= x"00" after td;
disp_ena <= '0' after td;
end if;
end if;
end process;
end cl_lcd_data; | mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/roundfunc.vhd | 2 | 2695 | ----------------------------------------------------------------------------------
-- Company: Hardware Security
-- Designer: Vinayaka Jyothi
--
-- Create Date: 18:42:44 11/28/2016
-- Design Name: DES Round Function
-- Module Name: des_roundfunc - Structural
-- Project Name: DES Crypto Core
-- Target Devices: ANY FPGAs
-- Tool versions: ISE, Vivado
-- Description: Implements round function of DES - Complete Structural Modelling
-- The final outputs are swap left and right 32 bits using registers
-- User may want to just without using registers
--
-- Dependencies: Modules :-> XP- Expansion; DESXOR1,DESXOR2 - XOR; S1..S8 - S-Boxes;
-- PP - Permutation; REG32 - 32 bit register
-- Files :-> xp.vhd,desxor1.vhd,desxor2.vhd, s1.vhd...s8.vhd,pp.vhd
-- reg32.vhd
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity roundfunc is port
(
clk : in std_logic;
reset : in std_logic;
li,ri : in std_logic_vector(1 to 32); --- Left and right 32 bits in
k : in std_logic_vector(1 to 48); -- Round key
lo,ro : out std_logic_vector(1 to 32) --Left and right 32 bits out (After swapping)
);
end roundfunc;
architecture behaviour of roundfunc is
signal xp_to_xor : std_logic_vector(1 to 48);
signal b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x: std_logic_vector(1 to 6);
signal so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x: std_logic_vector(1 to 4);
signal ppo,r_toreg32,l_toreg32 : std_logic_vector(1 to 32);
begin
xpension: entity work.xp port map ( ri=>ri,e=>xp_to_xor );
des_xor1: entity work.desxor1 port map ( e=>xp_to_xor,k=>k,b1x=>b1x, b2x=>b2x, b3x=>b3x, b4x=>b4x, b5x=>b5x, b6x=>b6x,b7x=>b7x, b8x=>b8x);
s1a: entity work.s1 port map ( clk=>clk, b=>b1x, so=>so1x);
s2a: entity work.s2 port map ( clk=>clk, b=>b2x, so=>so2x);
s3a: entity work.s3 port map ( clk=>clk, b=>b3x, so=>so3x);
s4a: entity work.s4 port map ( clk=>clk, b=>b4x, so=>so4x);
s5a: entity work.s5 port map ( clk=>clk, b=>b5x, so=>so5x);
s6a: entity work.s6 port map ( clk=>clk, b=>b6x, so=>so6x);
s7a: entity work.s7 port map ( clk=>clk, b=>b7x, so=>so7x);
s8a: entity work.s8 port map ( clk=>clk, b=>b8x, so=>so8x);
pperm: entity work.pp port map ( so1x=>so1x, so2x=>so2x, so3x=>so3x, so4x=>so4x, so5x=>so5x, so6x=>so6x, so7x=>so7x, so8x=>so8x,
ppo=>ppo );
des_xor2: entity work.desxor2 port map ( d=>ppo,l=>li, q=>r_toreg32 );
l_toreg32<=ri;
register32_left: entity work.reg32 port map ( a=>l_toreg32, q=>lo,reset=>reset, clk=>clk );
register32_right: entity work.reg32 port map ( a=>r_toreg32, q=>ro,reset=>reset, clk=>clk );
end;
| mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/startBtn/simulation/bmg_stim_gen.vhd | 1 | 12585 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (9999 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"startBtn.mif",
DEFAULT_DATA,
12,
10000);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>10000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 10000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/background/simulation/addr_gen.vhd | 101 | 4409 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/side/example_design/side_exdes.vhd | 1 | 4312 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: side_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY side_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END side_exdes;
ARCHITECTURE xilinx OF side_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT side IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : side
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/explosion/example_design/explosion_exdes.vhd | 1 | 4342 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: explosion_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY explosion_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END explosion_exdes;
ARCHITECTURE xilinx OF explosion_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT explosion IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : explosion
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit |
capitanov/Stupid_watch | src/rtl/game_cores/ctrl_rounds_rom.vhd | 1 | 7130 | --------------------------------------------------------------------------------
--
-- Title : ctrl_rounds_rom
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Description : ROM generator for new rounds
--
-- Rules for ROM generator:
-- 1) 0-6 - number of mines, 7 - a mine; 8-9 - forbidden combinations
-- 2) 8x8 block with "mine" or "number of mines"
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ctrl_rounds_rom is
port(
clk : in std_logic; --! clock
addr : in std_logic_vector(7 downto 0); --! ROM address 2^8
data : out std_logic_vector(23 downto 0) --! ROM data
);
end ctrl_rounds_rom;
architecture ctrl_rounds_rom of ctrl_rounds_rom is
signal addr_reg : std_logic_vector(7 downto 0);
constant N8x8 : integer:=8;
constant Ngames : integer:=32;
type round_array_3x64xN is array (Ngames*N8x8*N8x8-1 downto 0) of integer range 0 to 7;
constant mem_init0: round_array_3x64xN:=(
-- game 0:
0,0,0,0,0,0,1,7,
0,0,0,1,1,1,2,2,
0,0,0,1,7,2,2,7,
0,0,0,1,2,7,2,2,
0,1,1,1,1,1,1,0,
0,1,7,2,7,1,1,1,
0,1,1,2,2,2,2,7,
0,0,0,0,1,7,2,1,
-- game 1:
1,1,2,7,0,0,0,0,
1,7,3,3,2,1,0,0,
2,3,7,2,7,1,0,0,
7,3,2,3,1,1,0,0,
1,2,7,2,1,1,1,0,
0,1,1,2,7,7,1,0,
0,0,0,1,2,2,1,0,
0,0,0,0,0,0,0,0,
-- game 2:
1,1,1,1,1,1,0,0,
1,7,1,1,7,1,0,0,
1,1,2,2,2,1,0,0,
0,0,1,7,1,0,0,0,
0,1,3,3,2,0,0,0,
0,1,7,7,2,1,1,0,
0,2,4,4,3,7,1,0,
0,1,7,7,2,1,1,0,
-- game 3:
1,1,1,0,0,1,1,1,
1,7,2,2,1,2,7,1,
1,2,7,2,7,3,2,1,
0,2,2,3,2,7,1,0,
0,1,7,2,2,1,1,0,
1,2,3,7,1,0,0,0,
1,7,2,1,1,0,0,0,
1,1,1,0,0,0,0,0,
-- game 4:
0,0,0,0,0,0,0,0,
0,0,1,1,1,0,0,0,
0,1,2,7,2,1,0,0,
1,2,7,3,7,2,1,0,
1,7,3,4,3,7,1,0,
1,2,7,3,7,2,1,0,
0,1,2,7,2,1,0,0,
0,0,1,1,1,0,0,0,
-- game 5:
0,2,7,2,0,0,0,0,
0,3,7,3,0,0,0,0,
0,3,7,3,0,0,0,0,
0,3,7,3,0,0,0,0,
0,3,7,3,0,0,0,0,
0,3,7,3,0,0,0,0,
0,3,7,3,0,0,0,0,
0,2,7,2,0,0,0,0,
-- game 6:
0,0,0,0,0,0,0,0,
0,0,1,1,1,1,1,0,
0,0,2,7,4,7,2,0,
0,0,3,7,6,7,3,0,
0,0,3,7,6,7,3,0,
0,0,2,7,4,7,2,0,
0,0,1,2,3,2,1,0,
0,0,0,0,0,0,0,0,
-- game 7:
0,0,0,0,0,0,0,0,
0,1,1,1,1,1,1,0,
0,2,7,2,2,7,2,0,
0,3,7,3,3,7,3,0,
0,3,7,3,3,7,3,0,
0,2,7,2,2,7,2,0,
0,1,1,1,1,1,1,0,
0,0,0,0,0,0,0,0,
-- game 8:
7,2,1,0,0,0,0,0,
2,7,2,1,0,0,0,0,
1,2,7,2,1,0,0,0,
0,1,2,7,2,1,0,0,
0,0,1,2,7,2,1,0,
0,0,0,1,2,7,2,1,
0,0,0,0,1,2,7,2,
0,0,0,0,0,1,2,7,
-- game 9:
0,0,0,0,0,0,0,0,
0,1,1,1,1,1,1,0,
0,1,7,3,3,7,1,0,
0,1,3,7,7,3,1,0,
0,1,3,7,7,3,1,0,
0,1,7,3,3,7,1,0,
0,1,1,1,1,1,1,0,
0,0,0,0,0,0,0,0,
-- game A:
1,2,1,1,0,0,0,0,
7,2,7,1,0,0,0,0,
2,4,2,2,0,0,0,0,
7,2,7,1,1,1,2,1,
1,2,1,1,1,7,2,7,
0,0,0,0,2,2,4,2,
0,0,0,0,1,7,2,7,
0,0,0,0,1,1,2,1,
-- game B:
0,0,0,0,0,0,0,0,
0,1,2,3,3,2,1,0,
0,1,7,7,7,7,2,0,
0,1,2,4,5,7,2,0,
0,0,1,2,7,2,1,0,
0,1,2,7,2,1,0,0,
0,1,7,2,1,0,0,0,
0,1,1,1,0,0,0,0,
-- game C:
0,0,0,0,0,1,1,1,
0,1,1,1,1,2,7,1,
0,1,7,2,2,7,2,1,
0,1,2,7,3,2,1,0,
0,1,2,3,7,2,1,0,
1,2,7,2,2,7,1,0,
1,7,2,1,1,1,1,0,
1,1,1,0,0,0,0,0,
-- game D:
0,0,0,0,0,0,0,0,
0,0,1,2,3,2,1,0,
0,0,1,7,7,7,1,0,
0,0,1,4,7,4,1,0,
0,0,1,4,7,4,1,0,
0,0,1,7,7,7,1,0,
0,0,1,2,3,2,1,0,
0,0,0,0,0,0,0,0,
-- game E:
1,2,2,1,1,7,1,0,
1,7,7,1,1,1,1,0,
1,2,2,1,0,0,0,0,
0,0,0,1,1,1,1,1,
0,1,1,2,7,1,1,7,
0,1,7,2,1,1,1,1,
0,1,1,2,2,2,1,0,
0,0,0,1,7,7,1,0,
-- game F:
1,1,1,0,0,0,0,0,
1,7,1,0,0,0,0,0,
3,4,3,1,0,0,0,0,
7,7,7,1,1,2,3,2,
2,3,2,1,1,7,7,7,
0,0,0,0,1,3,4,3,
0,0,0,0,0,1,7,1,
0,0,0,0,0,1,1,1,
-- game 10:
7,2,1,0,0,1,2,7,
1,7,1,0,0,1,7,2,
1,1,1,0,0,1,1,1,
0,0,0,1,1,1,0,0,
0,0,0,1,7,2,1,0,
1,1,1,1,2,7,1,0,
2,7,1,0,1,1,1,0,
7,2,1,0,0,0,0,0,
-- game 11:
0,0,0,0,1,1,1,0,
0,1,1,1,1,7,1,0,
1,2,7,1,2,2,2,0,
2,7,3,1,2,7,2,0,
2,7,3,1,2,7,2,0,
1,2,7,1,2,2,2,0,
0,1,1,1,1,7,1,0,
0,0,0,0,1,1,1,0,
-- game 12:
7,1,0,0,0,1,1,1,
1,1,0,0,0,2,7,3,
0,0,1,1,1,2,7,7,
0,0,1,7,1,1,2,2,
0,1,2,2,1,0,0,0,
0,1,7,2,0,1,1,1,
0,1,7,2,0,1,7,1,
0,1,1,1,0,1,1,1,
-- game 13:
2,7,2,1,0,0,0,0,
7,4,7,1,0,0,0,0,
2,7,2,1,0,0,0,0,
1,1,1,1,1,2,1,1,
0,0,0,1,7,3,7,1,
0,0,0,1,3,7,2,1,
0,0,0,1,7,2,1,0,
0,0,0,1,1,1,0,0,
-- game 14:
0,0,1,1,1,1,0,0,
0,0,1,7,7,1,0,0,
1,1,3,4,4,3,1,1,
1,7,2,7,7,2,7,1,
1,1,3,4,4,3,1,1,
0,0,1,7,7,1,0,0,
0,0,1,1,1,1,0,0,
0,0,0,0,0,0,0,0,
-- game 15:
0,0,0,0,0,0,0,0,
0,0,1,2,3,2,1,0,
0,0,2,7,7,7,1,0,
0,0,2,7,4,2,1,0,
1,1,2,1,1,0,0,0,
1,7,2,1,1,1,1,1,
1,1,2,7,2,2,7,1,
0,0,1,1,2,7,2,1,
-- game 16:
1,2,2,1,0,0,0,0,
2,7,7,1,0,0,0,0,
3,7,5,2,0,0,0,0,
3,7,7,1,0,0,0,0,
3,7,5,2,0,0,0,0,
2,7,7,1,0,0,0,0,
1,2,2,1,0,0,0,0,
0,0,0,0,0,0,0,0,
-- game 17:
1,1,1,0,0,1,1,1,
1,7,2,1,1,2,7,1,
1,2,7,3,3,7,2,1,
0,2,3,7,7,3,2,0,
0,1,7,3,3,7,1,0,
0,1,1,1,1,1,1,0,
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
-- game 18:
0,0,0,0,0,1,1,1,
0,0,0,1,1,2,7,1,
0,0,0,2,7,4,2,1,
0,1,1,2,7,7,1,0,
0,2,7,4,3,2,1,0,
0,2,7,7,1,0,0,0,
1,2,2,2,1,0,0,0,
7,1,0,0,0,0,0,0,
-- game 19:
0,0,0,0,0,0,0,0,
0,1,2,3,2,1,0,0,
0,2,7,7,7,1,0,0,
0,3,7,6,2,1,0,0,
0,3,7,7,1,0,0,0,
0,3,7,3,1,0,0,0,
0,2,7,2,0,0,0,0,
0,1,1,1,0,0,0,0,
-- game 1A:
0,0,0,0,0,0,0,0,
0,1,1,1,1,1,1,0,
0,1,7,1,1,7,1,0,
0,1,2,3,3,2,1,0,
0,0,1,7,7,1,0,0,
0,1,2,5,5,2,1,0,
0,1,7,7,7,7,1,0,
0,1,2,3,3,2,1,0,
-- game 1B:
0,0,1,2,2,1,0,0,
0,1,2,7,7,1,0,0,
1,2,7,3,2,1,0,0,
2,7,3,1,0,0,0,0,
2,7,3,1,0,0,0,0,
1,2,7,3,2,1,0,0,
0,1,2,7,7,1,0,0,
0,0,1,2,2,1,0,0,
-- game 1C:
0,0,0,0,0,0,0,0,
1,2,3,2,1,0,0,0,
1,7,7,7,4,3,2,1,
1,2,5,7,7,7,7,1,
0,0,2,7,4,3,2,1,
0,0,1,1,1,0,0,0,
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
-- game 1D:
0,0,0,0,0,0,0,0,
0,0,0,1,2,2,1,0,
0,0,0,2,7,7,2,0,
0,1,2,4,7,7,2,0,
0,2,7,7,4,2,1,0,
0,2,7,7,2,0,0,0,
0,1,2,2,1,0,0,0,
0,0,0,0,0,0,0,0,
-- game 1E:
7,1,0,0,0,1,1,1,
1,1,1,1,0,1,7,1,
1,1,7,2,1,2,1,1,
0,1,1,2,7,2,0,0,
0,1,1,3,7,2,0,0,
0,1,7,3,2,1,0,0,
0,1,2,7,1,1,1,1,
0,0,1,1,1,1,7,1,
-- game 1F:
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
2,3,3,3,3,3,3,2,
7,7,7,7,7,7,7,7
);
type array_3x8 is array (N8x8-1 downto 0) of std_logic_vector(2 downto 0);
type array_3x8xN is array (Ngames*N8x8-1 downto 0) of array_3x8;
type array_24xN is array (Ngames*N8x8-1 downto 0) of std_logic_vector(23 downto 0);
function read_file return array_24xN is
variable mem_inis : round_array_3x64xN;
variable data3x8xN : array_3x8xN;
variable data24xN : array_24xN;
begin
mem_inis := mem_init0;
x_loop8: for jj in 0 to Ngames*N8x8-1 loop
for ii in 0 to N8x8-1 loop
data3x8xN(jj)(ii) := std_logic_vector(to_unsigned(mem_init0(ii+jj*8),3));
end loop;
end loop;
x_loop24: for jj in 0 to Ngames*N8x8-1 loop
data24xN(jj) := data3x8xN(jj)(7) & data3x8xN(jj)(6) & data3x8xN(jj)(5) & data3x8xN(jj)(4) & data3x8xN(jj)(3) & data3x8xN(jj)(2) & data3x8xN(jj)(1) & data3x8xN(jj)(0);
end loop;
return data24xN;
end read_file;
constant rom_data : array_24xN:=read_file;
begin
addr_reg <= addr when rising_edge(clk);
data <= rom_data(to_integer(unsigned(addr_reg)));
end ctrl_rounds_rom; | mit |
Yuriu5/MiniBlaze | src/hw1/ALU_pkg.vhd | 1 | 5786 | -- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : ALU_pkg
-- Date : 07/07/2016
--
-- Description : Arithmetic Logic Unit Package
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/07/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/07/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ALU_pkg is
type t_status_alu_out is
record
carry : std_logic; -- Carry resulting from an addition or a subtraction operation
zero : std_logic; -- All bits of the result (operandC) are logic zero
negative : std_logic; -- The result of the arithmetic operation if negative
overflow : std_logic; --
parity : std_logic; -- Indicates whether an even or odd number of bits on the Y bus are logic one
end record;
constant c_status_alu_out_null : t_status_alu_out := ('0','0','0','0','0');
type t_opcode_alu is (
OP_PTA, -- Pass through reg A
OP_PTB, -- Pass through reg B
OP_ADD, -- Add
OP_AND, -- And
OP_OR, -- Or
OP_SHIFT, -- Right shift
OP_XOR, -- Xor
OP_SEXT8, -- Sign extend Byte
OP_SEXT16, -- Sign extend Word
OP_MULT, -- Multiplication
OP_BS -- Barrel Shift
);
type t_type_carry is (
CARRY_INPUT,
CARRY_ONE,
CARRY_ZERO,
CARRY_ARITH
);
type t_type_shift is (
LEFT_SHIFT,
RIGHT_SHIFT_ARITH,
RIGHT_SHIFT_LOGIC
);
type t_type_mult is (
LSW,
HSW
);
type t_ctrl_op_alu is
record
keepCarry : std_logic;
negOperandB : std_logic;
negOperandA : std_logic;
whichCarry : t_type_carry;
ctrlShift : t_type_shift;
multType : t_type_mult;
end record;
constant c_ctrl_op_alu_null : t_ctrl_op_alu := ('0', '0', '0', CARRY_INPUT, LEFT_SHIFT, LSW);
type t_param_alu is
record
operation : t_opcode_alu;
ctrl_op : t_ctrl_op_alu;
end record;
constant c_param_alu_null : t_param_alu := (OP_PTA, c_ctrl_op_alu_null );
function is_zero(a : std_logic_vector) return std_logic;
function is_negative(a : std_logic_vector) return std_logic;
function add(a,b : std_logic_vector; c : std_logic) return std_logic_vector;
function multiply(a, b : std_logic_vector) return std_logic_vector;
end ALU_pkg;
package body ALU_pkg is
function is_zero(a : std_logic_vector) return std_logic is
variable tmp : std_logic_vector(a'range);
begin
tmp := (others => '0');
if tmp = a then
return '1';
else
return '0';
end if;
end function;
function is_negative(a : std_logic_vector) return std_logic is
begin
if a(a'left) = '1' then
return '1';
else
return '0';
end if;
end function;
function add(a,b : std_logic_vector; c : std_logic) return std_logic_vector is
variable CBIT : std_logic := c;
variable RESULT : std_logic_vector(a'left + 1 downto a'right) := (others => '0');
alias XA : std_logic_vector(a'range) is a;
alias XB : std_logic_vector(a'range) is b;
begin
for i in 0 to a'left loop
RESULT(i) := CBIT xor XA(i) xor XB(i);
CBIT := (CBIT and XA(i)) or (CBIT and XB(i)) or (XA(i) and XB(i));
end loop;
RESULT(a'left + 1) := CBIT;
return RESULT;
end add;
-- a & b same size
function multiply(a, b : std_logic_vector) return std_logic_vector is
variable A_LEFT : integer := a'length-1;
variable result : std_logic_vector(2*A_LEFT+1 downto 0);
begin
result := std_logic_vector(signed(a)*signed(b));
return result;
end multiply;
end;
| mit |
Luisda199824/ProcesadorMonociclo | SignExtender.vhd | 1 | 471 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SignExtender is
Port ( A : in STD_LOGIC_VECTOR (12 downto 0);
SEOut : out STD_LOGIC_VECTOR (31 downto 0));
end SignExtender;
architecture Behavioral of SignExtender is
begin
process(A)
begin
if (A(12) = '0') then
SEOut <= "0000000000000000000"&A;
else
SEOut <= "1111111111111111111"&A;
end if;
end process;
end Behavioral; | mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/keysched.vhd | 2 | 5134 | --******************************************************************************
-- Copyright (c) 2017 Vinayaka Jyothi
-- All rights reserved.
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject
-- to the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--******************************************************************************
--------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Designer: Vinayaka Jyothi
--
-- Create Date: 20:45:11 02/14/2010
-- Design Name:
-- Project Name: DES_Fully_Pipelined
-- Target Device:
-- Tool versions:
-- Description:
--
--
-- Dependencies: DES_Fully_Pipelined
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity keysched is port
(
key : in std_logic_vector(1 to 64);EN,CLK: in std_logic;
k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x
: out std_logic_vector(1 to 48)
);
end keysched;
architecture behaviour of keysched is
signal k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16: std_logic_vector(1 to 48);
signal
c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16 :std_logic_vector(28 downto 1);
signal
d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16 :std_logic_vector(28 downto 1);
component pc1
port (
key : in std_logic_vector(1 TO 64);
c0x,d0x : out std_logic_vector(1 TO 28)
);
end component;
component pc2
port (
c,d : in std_logic_vector(1 TO 28);
k : out std_logic_vector(1 TO 48)
);
end component;
begin
pc_1: pc1 port map ( key=>key, c0x=>c0, d0x=>d0);
C1 <= C0(27 DOWNTO 1) & C0(28);
D1 <= D0(27 DOWNTO 1) & D0(28);
C2 <= C1(27 DOWNTO 1) & C1(28);
D2 <= D1(27 DOWNTO 1) & D1(28);
C3 <= C2(26 DOWNTO 1) & C2(28 DOWNTO 27);
D3 <= D2(26 DOWNTO 1) & D2(28 DOWNTO 27);
C4 <= C3(26 DOWNTO 1) & C3(28 DOWNTO 27);
D4 <= D3(26 DOWNTO 1) & D3(28 DOWNTO 27);
C5 <= C4(26 DOWNTO 1) & C4(28 DOWNTO 27);
D5 <= D4(26 DOWNTO 1) & D4(28 DOWNTO 27);
C6 <= C5(26 DOWNTO 1) & C5(28 DOWNTO 27);
D6 <= D5(26 DOWNTO 1) & D5(28 DOWNTO 27);
C7 <= C6(26 DOWNTO 1) & C6(28 DOWNTO 27);
D7 <= D6(26 DOWNTO 1) & D6(28 DOWNTO 27);
C8 <= C7(26 DOWNTO 1) & C7(28 DOWNTO 27);
D8 <= D7(26 DOWNTO 1) & D7(28 DOWNTO 27);
C9 <= C8(27 DOWNTO 1) & C8(28);
D9 <= D8(27 DOWNTO 1) & D8(28);
C10 <= C9(26 DOWNTO 1) & C9(28 DOWNTO 27);
D10 <= D9(26 DOWNTO 1) & D9(28 DOWNTO 27);
C11 <= C10(26 DOWNTO 1) & C10(28 DOWNTO 27);
D11 <= D10(26 DOWNTO 1) & D10(28 DOWNTO 27);
C12 <= C11(26 DOWNTO 1) & C11(28 DOWNTO 27);
D12 <= D11(26 DOWNTO 1) & D11(28 DOWNTO 27);
C13 <= C12(26 DOWNTO 1) & C12(28 DOWNTO 27);
D13 <= D12(26 DOWNTO 1) & D12(28 DOWNTO 27);
C14 <= C13(26 DOWNTO 1) & C13(28 DOWNTO 27);
D14 <= D13(26 DOWNTO 1) & D13(28 DOWNTO 27);
C15 <= C14(26 DOWNTO 1) & C14(28 DOWNTO 27);
D15 <= D14(26 DOWNTO 1) & D14(28 DOWNTO 27);
C16 <= C15(27 DOWNTO 1) & C15(28);
D16 <= D15(27 DOWNTO 1) & D15(28);
pc2x1: pc2 port map ( c=>c1, d=>d1, k=>k1 );
pc2x2: pc2 port map ( c=>c2, d=>d2, k=>k2 );
pc2x3: pc2 port map ( c=>c3, d=>d3, k=>k3 );
pc2x4: pc2 port map ( c=>c4, d=>d4, k=>k4 );
pc2x5: pc2 port map ( c=>c5, d=>d5, k=>k5 );
pc2x6: pc2 port map ( c=>c6, d=>d6, k=>k6 );
pc2x7: pc2 port map ( c=>c7, d=>d7, k=>k7 );
pc2x8: pc2 port map ( c=>c8, d=>d8, k=>k8 );
pc2x9: pc2 port map ( c=>c9, d=>d9, k=>k9 );
pc2x10: pc2 port map ( c=>c10, d=>d10, k=>k10 );
pc2x11: pc2 port map ( c=>c11, d=>d11, k=>k11 );
pc2x12: pc2 port map ( c=>c12, d=>d12, k=>k12 );
pc2x13: pc2 port map ( c=>c13, d=>d13, k=>k13 );
pc2x14: pc2 port map ( c=>c14, d=>d14, k=>k14 );
pc2x15: pc2 port map ( c=>c15, d=>d15, k=>k15 );
pc2x16: pc2 port map ( c=>c16, d=>d16, k=>k16 );
process(EN,KEY,CLK)
begin
if EN='0' then
k1x<=k16;k2x<=k15;k3x<=k14;k4x<=k13;k5x<=k12;k6x<=k11;k7x<=k10;k8x<=k9;
k9x<=k8;k10x<=k7;k11x<=k6;k12x<=k5;k13x<=k4;k14x<=k3;k15x<=k2;k16x<=k1;
else
k1x<=k1;k2x<=k2;k3x<=k3;k4x<=k4;k5x<=k5;k6x<=k6;k7x<=k7;k8x<=k8;
k9x<=k9;k10x<=k10;k11x<=k11;k12x<=k12;k13x<=k13;k14x<=k14;k15x<=k15;k16x<=k16;
end if;
end process;
end behaviour; | mit |
IamVNIE/Hardware-Security | RC5 CryptoCore/Rc5 Codes/RC5encryptAllSteps.vhd | 2 | 6997 | Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use Work.RC5_Pkg.all;
Entity rc5_enc Is
Port
(
clr : in std_logic;
clk : in std_logic;
din : in std_logic_vector(63 downto 0);
di_vld : in std_logic;
key_rdy : in std_logic;
skey : in rom;
dout : out std_logic_vector(63 downto 0);
do_rdy : out std_logic
);
End rc5_enc;
Architecture rtl of rc5_enc is
signal i_cnt : Std_logic_vector(3 downto 0); --Signals
signal ab_xor : Std_logic_vector(31 downto 0);
signal a_rot : Std_logic_vector(31 downto 0);
signal a : Std_logic_vector(31 downto 0);
signal a_pre : Std_logic_vector(31 downto 0);
signal a_reg : Std_logic_vector(31 downto 0);
signal ba_xor : Std_logic_vector(31 downto 0);
signal b_rot : Std_logic_vector(31 downto 0);
signal b : Std_logic_vector(31 downto 0);
signal b_pre : Std_logic_vector(31 downto 0);
signal b_reg : Std_logic_vector(31 downto 0);
--RC5 State Machine
Type StateType is --Type for state machine
(
ST_idle,
ST_pre_round,
ST_round_op,
ST_ready
);
Signal state_en : StateType; --Signal type of state machine
Begin
ab_xor <= a_reg XOR b_reg; --A_reg _reg XOR
With b_reg(4 downto 0) Select --Rotate left XOR result
a_rot <= ab_xor(30 downto 0) & ab_xor(31) when "00001",
ab_xor(29 downto 0) & ab_xor(31 downto 30) when "00010",
ab_xor(28 downto 0) & ab_xor(31 downto 29) when "00011",
ab_xor(27 downto 0) & ab_xor(31 downto 28) when "00100",
ab_xor(26 downto 0) & ab_xor(31 downto 27) when "00101",
ab_xor(25 downto 0) & ab_xor(31 downto 26) when "00110",
ab_xor(24 downto 0) & ab_xor(31 downto 25) when "00111",
ab_xor(23 downto 0) & ab_xor(31 downto 24) when "01000",
ab_xor(22 downto 0) & ab_xor(31 downto 23) when "01001",
ab_xor(21 downto 0) & ab_xor(31 downto 22) when "01010",
ab_xor(20 downto 0) & ab_xor(31 downto 21) when "01011",
ab_xor(19 downto 0) & ab_xor(31 downto 20) when "01100",
ab_xor(18 downto 0) & ab_xor(31 downto 19) when "01101",
ab_xor(17 downto 0) & ab_xor(31 downto 18) when "01110",
ab_xor(16 downto 0) & ab_xor(31 downto 17) when "01111",
ab_xor(15 downto 0) & ab_xor(31 downto 16) when "10000",
ab_xor(14 downto 0) & ab_xor(31 downto 15) when "10001",
ab_xor(13 downto 0) & ab_xor(31 downto 14) when "10010",
ab_xor(12 downto 0) & ab_xor(31 downto 13) when "10011",
ab_xor(11 downto 0) & ab_xor(31 downto 12) when "10100",
ab_xor(10 downto 0) & ab_xor(31 downto 11) when "10101",
ab_xor(9 downto 0) & ab_xor(31 downto 10) when "10110",
ab_xor(8 downto 0) & ab_xor(31 downto 9) when "10111",
ab_xor(7 downto 0) & ab_xor(31 downto 8) when "11000",
ab_xor(6 downto 0) & ab_xor(31 downto 7) when "11001",
ab_xor(5 downto 0) & ab_xor(31 downto 6) when "11010",
ab_xor(4 downto 0) & ab_xor(31 downto 5) when "11011",
ab_xor(3 downto 0) & ab_xor(31 downto 4) when "11100",
ab_xor(2 downto 0) & ab_xor(31 downto 3) when "11101",
ab_xor(1 downto 0) & ab_xor(31 downto 2) when "11110",
ab_xor(0) & ab_xor(31 downto 1) when "11111",
ab_xor when others;
a_pre <= din(63 downto 32) + skey(0); --A_pre output after add din and skey
a <= a_rot + skey(CONV_INTEGER(i_cnt & '0')); --A output after add left rotate and skey
ba_xor <= b_reg XOR a; --B_reg XOR with A
with a(4 downto 0) Select --Rotate left result of XOR
b_rot <= ba_xor(30 downto 0) & ba_xor(31) when "00001",
ba_xor(29 downto 0) & ba_xor(31 downto 30) when "00010",
ba_xor(28 downto 0) & ba_xor(31 downto 29) when "00011",
ba_xor(27 downto 0) & ba_xor(31 downto 28) when "00100",
ba_xor(26 downto 0) & ba_xor(31 downto 27) when "00101",
ba_xor(25 downto 0) & ba_xor(31 downto 26) when "00110",
ba_xor(24 downto 0) & ba_xor(31 downto 25) when "00111",
ba_xor(23 downto 0) & ba_xor(31 downto 24) when "01000",
ba_xor(22 downto 0) & ba_xor(31 downto 23) when "01001",
ba_xor(21 downto 0) & ba_xor(31 downto 22) when "01010",
ba_xor(20 downto 0) & ba_xor(31 downto 21) when "01011",
ba_xor(19 downto 0) & ba_xor(31 downto 20) when "01100",
ba_xor(18 downto 0) & ba_xor(31 downto 19) when "01101",
ba_xor(17 downto 0) & ba_xor(31 downto 18) when "01110",
ba_xor(16 downto 0) & ba_xor(31 downto 17) when "01111",
ba_xor(15 downto 0) & ba_xor(31 downto 16) when "10000",
ba_xor(14 downto 0) & ba_xor(31 downto 15) when "10001",
ba_xor(13 downto 0) & ba_xor(31 downto 14) when "10010",
ba_xor(12 downto 0) & ba_xor(31 downto 13) when "10011",
ba_xor(11 downto 0) & ba_xor(31 downto 12) when "10100",
ba_xor(10 downto 0) & ba_xor(31 downto 11) when "10101",
ba_xor(9 downto 0) & ba_xor(31 downto 10) when "10110",
ba_xor(8 downto 0) & ba_xor(31 downto 9) when "10111",
ba_xor(7 downto 0) & ba_xor(31 downto 8) when "11000",
ba_xor(6 downto 0) & ba_xor(31 downto 7) when "11001",
ba_xor(5 downto 0) & ba_xor(31 downto 6) when "11010",
ba_xor(4 downto 0) & ba_xor(31 downto 5) when "11011",
ba_xor(3 downto 0) & ba_xor(31 downto 4) when "11100",
ba_xor(2 downto 0) & ba_xor(31 downto 3) when "11101",
ba_xor(1 downto 0) & ba_xor(31 downto 2) when "11110",
ba_xor(0) & ba_xor(31 downto 1) when "11111",
ba_xor when others;
b_pre <= din(31 downto 0) + skey(1); --B output when add din and skey 1
b <= b_rot + skey(CONV_INTEGER(i_cnt & '1')); --B output when add left rotate and skey
--Register A --Register A
Process(clr, clk) Begin
If(clr='0') Then
a_reg <= (Others => '0');
elsif(clk'Event and clk='1') Then
If (state_en=ST_pre_round) Then
a_reg <= a_pre;
Elsif (state_en=ST_round_op) Then
a_reg <= a;
End if;
End If;
End Process;
--Register B --Register B
Process(clr, clk) Begin
If(clr='0') Then
b_reg <= (Others => '0');
Elsif(clk'Event and clk='1') Then
If (state_en=ST_pre_round) Then
b_reg <= b_pre;
Elsif (state_en=ST_round_op) Then
b_reg <= b;
End if;
End If;
End Process;
Process (clr, clk) --State Machine
Begin
If (clr='0') Then
state_en <= ST_idle;
Elsif (clk'Event And clk = '1') Then
Case state_en is
When ST_idle => If (di_vld='1' and key_rdy='1') Then state_en <= ST_pre_round; End If;
When ST_pre_round => state_en <= ST_round_op;
When ST_round_op => If (i_cnt="1100") Then state_en <= ST_ready; End If;
When ST_ready => state_en <= ST_idle;
End Case;
End If;
End Process;
Process(clr, clk) Begin --Round Counter
If(clr='0') Then
i_cnt <= "0001";
Elsif(clk'Event And clk='1') Then
If (state_en = ST_round_op) Then
If(i_cnt="1100") Then
i_cnt <= "0001";
Else
i_cnt <= i_cnt + '1';
End If;
End If;
End If;
End Process;
dout <= a_reg & b_reg;
With state_en Select
do_rdy <= '1' When ST_ready,
'0' When Others;
End rtl; | mit |
Yuriu5/MiniBlaze | src/hw1/ALU.vhd | 1 | 8041 | -- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : ALU
-- Date : 07/07/2016
--
-- Description : Arithmetic Logic Unit
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/07/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/07/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ALU_pkg.all;
entity ALU is
generic(
DATA_WIDTH : natural := 32
);
port(
param_i : in t_param_alu;
carry_i : in std_logic;
operandA_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
operandB_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
operandD_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
status_o : out t_status_alu_out
);
end ALU;
architecture rtl of ALU is
begin
p_alu : process(param_i, carry_i, operandA_i, operandB_i)
variable result : signed(DATA_WIDTH downto 0) := (others => '0');
variable result_add : signed(DATA_WIDTH downto 0) := (others => '0');
variable result_mult : signed(2*(DATA_WIDTH-1)+1 downto 0) := (others => '0');
variable carry_in : std_logic := '0';
variable carry_out : std_logic := '0';
variable zero_out : std_logic := '0';
variable negative_out : std_logic := '0';
variable overflow_out : std_logic := '0';
variable parity_out : std_logic := '0';
variable result_out : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandA_sext8 : std_logic_vector(DATA_WIDTH - 9 downto 0) := (others => '0');
variable operandA_signed : signed(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandB_signed : signed(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandA_unsigned : unsigned(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandB_unsigned : unsigned(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandA : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandB : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
variable dbg : std_logic_vector(0 downto 0);
begin
operandA_sext8 := (others => operandA_i(7));
operandA_signed := signed(operandA_i);
operandB_signed := signed(operandB_i);
operandA_unsigned := unsigned(operandA_i);
operandB_unsigned := unsigned(operandB_i);
operandA := operandA_i;
operandB := operandB_i;
-- Chose carry in
case param_i.ctrl_op.whichCarry is
when CARRY_INPUT =>
carry_in := carry_i;
when CARRY_ONE =>
carry_in := '1';
when CARRY_ZERO =>
carry_in := '0';
when CARRY_ARITH =>
carry_in := operandA(operandA'left);
end case;
if param_i.ctrl_op.negOperandA = '1' then
operandA := not operandA;
end if;
if param_i.ctrl_op.negOperandB = '1' then
operandB := not operandB;
end if;
result_add := signed(add(operandA, operandB, carry_in));
result_mult := signed(multiply(operandA, operandB));
case param_i.operation is
when OP_PTA =>
result := operandA_signed(31) & operandA_signed;
when OP_PTB =>
result := operandB_signed(31) & operandB_signed;
when OP_ADD =>
result := result_add;
when OP_AND =>
result := signed('0' & (operandA and operandB));
when OP_OR =>
result := signed('0' & (operandA or operandB));
when OP_SHIFT =>
result := operandA_signed(0) & carry_in & operandA_signed(operandA_signed'left downto 1);
when OP_XOR =>
result := signed('0' & (operandA xor operandB));
when OP_SEXT8 =>
result := '0' & signed(operandA_sext8) & signed(operandA(7 downto 0));
when OP_SEXT16 =>
result := '0' & resize(operandA_signed(15 downto 0), DATA_WIDTH);
when OP_MULT =>
case param_i.ctrl_op.multType is
when LSW => result := result_mult(DATA_WIDTH downto 0);
when HSW => result := result_mult(2*(DATA_WIDTH-1)+1) & result_mult(2*(DATA_WIDTH-1)+1 downto DATA_WIDTH);
end case;
when OP_BS =>
case param_i.ctrl_op.ctrlShift is
when LEFT_SHIFT => result := '0' & shift_left(operandA_signed, to_integer(operandB_unsigned(4 downto 0)));
when RIGHT_SHIFT_ARITH => result := '0' & shift_right(operandA_signed, to_integer(operandB_unsigned(4 downto 0))); -- Insert left most b
when RIGHT_SHIFT_LOGIC => result := '0' & signed(shift_right(operandA_unsigned, to_integer(operandB_unsigned(4 downto 0)))); -- Insert 0
when others => result := (others => '0');
end case;
when others =>
result := (others => '0');
assert false report "Unknown operation for ALU" severity error;
end case;
carry_out := result(DATA_WIDTH);
result_out := std_logic_vector(result(DATA_WIDTH-1 downto 0));
zero_out := is_zero(result_out);
negative_out := is_negative(result_out);
overflow_out := (not carry_out and result_out(result_out'left)) or (carry_out and not result_out(result_out'left));
parity_out := '0'; -- TODO
-- Mapping output
status_o.carry <= carry_out;
status_o.zero <= zero_out;
status_o.negative <= negative_out;
status_o.overflow <= overflow_out;
status_o.parity <= parity_out;
operandD_o <= result_out;
end process;
end rtl;
| mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/police/simulation/police_tb.vhd | 1 | 4343 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: police_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY police_tb IS
END ENTITY;
ARCHITECTURE police_tb_ARCH OF police_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
police_synth_inst:ENTITY work.police_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/s2.vhd | 2 | 3979 | library ieee;
use ieee.std_logic_1164.all;
entity s2 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s2;
architecture behaviour of s2 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
end case;
end process;
end; | mit |
laurocruz/snakes_vhdl | src/snake_lib/snake_pack.vhd | 1 | 2402 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
PACKAGE snake_pack IS
--TYPE int_s IS INTEGER RANGE -20 TO 255;
TYPE int_array IS array (0 to 127) OF INTEGER RANGE -20 TO 255;
COMPONENT conv_7seg IS
PORT (digit : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
seg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;
END COMPONENT;
COMPONENT create_food IS
-- Altura e comprimento do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
width : INTEGER := 6);
PORT (reset : IN STD_LOGIC;
eaten : IN STD_LOGIC;
gmap : IN STD_LOGIC_VECTOR(0 TO N*M-1);
new_food : OUT INTEGER RANGE 0 TO N*M-1);
END COMPONENT;
COMPONENT gclock IS
-- Frequencia de 1Hz
-- clock do hardware
PORT (CLOCK_27 : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
clock_out : OUT STD_LOGIC) ;
END COMPONENT;
COMPONENT make_map IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
-- clock do jogo
PORT (clock : IN STD_LOGIC;
-- reseta o jogo
reset : IN STD_LOGIC;
-- aumento do tamanho
eaten : IN STD_LOGIC;
snake_size : IN INTEGER RANGE 0 TO N*M;
-- direcao para onde a cobra esta se movendo
-- 11 : cima
-- 00 : baixo
-- 10 : esquerda
-- 01 : direita
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-- posicoes da cobra no mapa
snake_body : OUT int_array);
END COMPONENT;
COMPONENT size_counter IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
PORT (reset : IN STD_LOGIC;
food_pos : IN INTEGER RANGE -20 TO 255;
--food_pos : IN INTEGER RANGE 0 TO N*M-1;
snake_head : IN INTEGER RANGE -20 TO 255;
snake_size : OUT INTEGER RANGE 0 TO N*M;
eaten : OUT STD_LOGIC);
END COMPONENT;
COMPONENT colision IS
-- Dimensoes do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10);
PORT (snake_body : IN int_array;
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
reset : IN STD_LOGIC;
gmap : OUT STD_LOGIC_VECTOR(0 to N*M-1);
lost : OUT STD_LOGIC);
END COMPONENT ;
COMPONENT snake_dir IS
PORT (reset : IN STD_LOGIC;
snake_turn : IN STD_LOGIC_VECTOR(1 downto 0);
dir : BUFFER STD_LOGIC_VECTOR(0 to 1));
END COMPONENT;
END snake_pack;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/zynq_design_1_system_ila_0_0_stub.vhdl | 1 | 2560 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:31:54 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/zynq_design_1_system_ila_0_0_stub.vhdl
-- Design : zynq_design_1_system_ila_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zynq_design_1_system_ila_0_0 is
Port (
clk : in STD_LOGIC;
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
SLOT_0_AXI_awvalid : in STD_LOGIC;
SLOT_0_AXI_awready : in STD_LOGIC;
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
SLOT_0_AXI_wvalid : in STD_LOGIC;
SLOT_0_AXI_wready : in STD_LOGIC;
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
SLOT_0_AXI_bvalid : in STD_LOGIC;
SLOT_0_AXI_bready : in STD_LOGIC;
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
SLOT_0_AXI_arvalid : in STD_LOGIC;
SLOT_0_AXI_arready : in STD_LOGIC;
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
SLOT_0_AXI_rvalid : in STD_LOGIC;
SLOT_0_AXI_rready : in STD_LOGIC;
resetn : in STD_LOGIC
);
end zynq_design_1_system_ila_0_0;
architecture stub of zynq_design_1_system_ila_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,SLOT_0_AXI_awaddr[8:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[8:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,resetn";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "bd_c3fe,Vivado 2017.2";
begin
end;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/vhdl/convolve_kernel.vhd | 1 | 39161 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
generic (
C_S_AXI_CONTROL_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CONTROL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_EN_A : OUT STD_LOGIC;
bufw_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_Clk_A : OUT STD_LOGIC;
bufw_Rst_A : OUT STD_LOGIC;
bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_EN_A : OUT STD_LOGIC;
bufi_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_Clk_A : OUT STD_LOGIC;
bufi_Rst_A : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC;
s_axi_control_AWVALID : IN STD_LOGIC;
s_axi_control_AWREADY : OUT STD_LOGIC;
s_axi_control_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_WVALID : IN STD_LOGIC;
s_axi_control_WREADY : OUT STD_LOGIC;
s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);
s_axi_control_ARVALID : IN STD_LOGIC;
s_axi_control_ARREADY : OUT STD_LOGIC;
s_axi_control_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_RVALID : OUT STD_LOGIC;
s_axi_control_RREADY : IN STD_LOGIC;
s_axi_control_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_control_BVALID : OUT STD_LOGIC;
s_axi_control_BREADY : IN STD_LOGIC;
s_axi_control_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.174000,HLS_SYN_LAT=25351,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=5,HLS_SYN_FF=1218,HLS_SYN_LUT=1185}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (17 downto 0) := "000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (17 downto 0) := "000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (17 downto 0) := "000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (17 downto 0) := "000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (17 downto 0) := "000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (17 downto 0) := "000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (17 downto 0) := "000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (17 downto 0) := "000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (17 downto 0) := "000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (17 downto 0) := "001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (17 downto 0) := "010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal row_b_cast6_cast_fu_169_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal row_b_cast6_cast_reg_503 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal row_b_1_fu_179_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal row_b_1_reg_511 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_1_cast_fu_193_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_1_cast_reg_516 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_fu_173_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_b_cast5_cast_fu_197_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal col_b_cast5_cast_reg_521 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal col_b_1_fu_207_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_b_1_reg_529 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_4_cast_fu_221_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_4_cast_reg_534 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_2_fu_201_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_cast_fu_247_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_12_cast_reg_539 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal bufo_addr_reg_544 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_1_fu_284_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal to_b_1_reg_552 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_19_fu_315_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_reg_557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_22_fu_345_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_22_reg_562 : STD_LOGIC_VECTOR (5 downto 0);
signal ti_b_1_fu_357_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal ti_b_1_reg_570 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_25_fu_388_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_25_reg_575 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal i_1_fu_404_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_583 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_29_fu_448_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_29_reg_588 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_9_fu_398_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal j_1_fu_478_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_601 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_3_fu_472_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal bufw_load_reg_611 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal bufi_load_reg_616 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_165_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_reg_621 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal bufo_load_reg_626 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_161_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_reg_631 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal row_b_reg_95 : STD_LOGIC_VECTOR (1 downto 0);
signal col_b_reg_106 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_5_fu_278_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal to_b_reg_117 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_7_fu_351_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ti_b_reg_128 : STD_LOGIC_VECTOR (1 downto 0);
signal i_reg_139 : STD_LOGIC_VECTOR (2 downto 0);
signal j_reg_150 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_state18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
signal tmp_16_cast_fu_273_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_30_cast_fu_463_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_cast_fu_498_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal tmp_1_fu_185_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_4_fu_213_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_11_fu_229_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal p_shl1_cast_fu_237_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_cast4_cast_fu_225_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_12_fu_241_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_13_fu_251_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_14_fu_256_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_15_fu_262_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_16_fu_268_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal ti_b_cast3_cast_fu_290_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_17_fu_294_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_18_fu_303_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_17_cast_fu_299_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_shl4_fu_311_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_321_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_21_fu_333_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal p_shl3_cast_fu_341_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl2_cast_fu_329_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal i_cast2_fu_363_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_fu_367_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_fu_376_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_24_fu_372_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl5_cast_fu_380_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal i_cast_fu_394_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_s_fu_410_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_cast_cast_fu_415_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_26_fu_419_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_28_fu_424_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_32_fu_436_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal p_shl6_cast_fu_432_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal p_shl7_cast_fu_444_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal j_cast1_cast_fu_454_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_30_fu_458_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal j_cast_fu_468_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_6_fu_484_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_6_cast_cast_fu_489_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_31_fu_493_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (17 downto 0);
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_control_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
convolve_kernel_control_s_axi_U : component convolve_kernel_control_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CONTROL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CONTROL_DATA_WIDTH)
port map (
AWVALID => s_axi_control_AWVALID,
AWREADY => s_axi_control_AWREADY,
AWADDR => s_axi_control_AWADDR,
WVALID => s_axi_control_WVALID,
WREADY => s_axi_control_WREADY,
WDATA => s_axi_control_WDATA,
WSTRB => s_axi_control_WSTRB,
ARVALID => s_axi_control_ARVALID,
ARREADY => s_axi_control_ARREADY,
ARADDR => s_axi_control_ARADDR,
RVALID => s_axi_control_RVALID,
RREADY => s_axi_control_RREADY,
RDATA => s_axi_control_RDATA,
RRESP => s_axi_control_RRESP,
BVALID => s_axi_control_BVALID,
BREADY => s_axi_control_BREADY,
BRESP => s_axi_control_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
convolve_kernel_fbkb_U0 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => bufo_load_reg_626,
din1 => tmp_8_reg_621,
ce => ap_const_logic_1,
dout => grp_fu_161_p2);
convolve_kernel_fcud_U1 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => bufw_load_reg_611,
din1 => bufi_load_reg_616,
ce => ap_const_logic_1,
dout => grp_fu_165_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
col_b_reg_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = tmp_5_fu_278_p2))) then
col_b_reg_106 <= col_b_1_reg_529;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_173_p2 = ap_const_lv1_0))) then
col_b_reg_106 <= ap_const_lv2_0;
end if;
end if;
end process;
i_reg_139_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_7_fu_351_p2))) then
i_reg_139 <= ap_const_lv3_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_3_fu_472_p2 = ap_const_lv1_1))) then
i_reg_139 <= i_1_reg_583;
end if;
end if;
end process;
j_reg_150_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = tmp_9_fu_398_p2))) then
j_reg_150 <= ap_const_lv3_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then
j_reg_150 <= j_1_reg_601;
end if;
end if;
end process;
row_b_reg_95_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_2_fu_201_p2 = ap_const_lv1_1))) then
row_b_reg_95 <= row_b_1_reg_511;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
row_b_reg_95 <= ap_const_lv2_0;
end if;
end if;
end process;
ti_b_reg_128_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = tmp_5_fu_278_p2))) then
ti_b_reg_128 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (tmp_9_fu_398_p2 = ap_const_lv1_1))) then
ti_b_reg_128 <= ti_b_1_reg_570;
end if;
end if;
end process;
to_b_reg_117_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_7_fu_351_p2))) then
to_b_reg_117 <= to_b_1_reg_552;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = tmp_2_fu_201_p2))) then
to_b_reg_117 <= ap_const_lv2_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
bufi_load_reg_616 <= bufi_Dout_A;
bufw_load_reg_611 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
bufo_addr_reg_544 <= tmp_16_cast_fu_273_p1(5 - 1 downto 0);
tmp_12_cast_reg_539 <= tmp_12_cast_fu_247_p1;
to_b_1_reg_552 <= to_b_1_fu_284_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
bufo_load_reg_626 <= bufo_Dout_A;
tmp_8_reg_621 <= grp_fu_165_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
col_b_1_reg_529 <= col_b_1_fu_207_p2;
col_b_cast5_cast_reg_521(1 downto 0) <= col_b_cast5_cast_fu_197_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
i_1_reg_583 <= i_1_fu_404_p2;
tmp_25_reg_575 <= tmp_25_fu_388_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
j_1_reg_601 <= j_1_fu_478_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
row_b_1_reg_511 <= row_b_1_fu_179_p2;
row_b_cast6_cast_reg_503(1 downto 0) <= row_b_cast6_cast_fu_169_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ti_b_1_reg_570 <= ti_b_1_fu_357_p2;
tmp_19_reg_557 <= tmp_19_fu_315_p2;
tmp_22_reg_562(5 downto 1) <= tmp_22_fu_345_p2(5 downto 1);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state17)) then
tmp_10_reg_631 <= grp_fu_161_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_173_p2 = ap_const_lv1_0))) then
tmp_1_cast_reg_516(2 downto 1) <= tmp_1_cast_fu_193_p1(2 downto 1);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = tmp_9_fu_398_p2))) then
tmp_29_reg_588(9 downto 1) <= tmp_29_fu_448_p2(9 downto 1);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = tmp_2_fu_201_p2))) then
tmp_4_cast_reg_534(2 downto 1) <= tmp_4_cast_fu_221_p1(2 downto 1);
end if;
end if;
end process;
row_b_cast6_cast_reg_503(5 downto 2) <= "0000";
tmp_1_cast_reg_516(0) <= '0';
tmp_1_cast_reg_516(3) <= '0';
col_b_cast5_cast_reg_521(5 downto 2) <= "0000";
tmp_4_cast_reg_534(0) <= '0';
tmp_4_cast_reg_534(3) <= '0';
tmp_22_reg_562(0) <= '0';
tmp_29_reg_588(0) <= '0';
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_fu_173_p2, ap_CS_fsm_state3, tmp_2_fu_201_p2, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, tmp_9_fu_398_p2, ap_CS_fsm_state7, tmp_3_fu_472_p2, tmp_5_fu_278_p2, tmp_7_fu_351_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_173_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_2_fu_201_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = tmp_5_fu_278_p2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_7_fu_351_p2))) then
ap_NS_fsm <= ap_ST_fsm_state4;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (tmp_9_fu_398_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_3_fu_472_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state17 <= ap_CS_fsm(16);
ap_CS_fsm_state18 <= ap_CS_fsm(17);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_173_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_173_p2 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_173_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_173_p2 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
bufi_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_31_cast_fu_498_p1),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_Clk_A <= ap_clk;
bufi_Din_A <= ap_const_lv32_0;
bufi_EN_A_assign_proc : process(ap_CS_fsm_state7)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
bufi_EN_A <= ap_const_logic_1;
else
bufi_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_Rst_A <= ap_rst_n_inv;
bufi_WEN_A <= ap_const_lv4_0;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_544),32));
bufo_Clk_A <= ap_clk;
bufo_Din_A <= tmp_10_reg_631;
bufo_EN_A_assign_proc : process(ap_CS_fsm_state18, ap_CS_fsm_state11)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state18) or (ap_const_logic_1 = ap_CS_fsm_state11))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst_n_inv;
bufo_WEN_A_assign_proc : process(ap_CS_fsm_state18)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state18)) then
bufo_WEN_A <= ap_const_lv4_F;
else
bufo_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufw_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_30_cast_fu_463_p1),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_Clk_A <= ap_clk;
bufw_Din_A <= ap_const_lv32_0;
bufw_EN_A_assign_proc : process(ap_CS_fsm_state7)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
bufw_EN_A <= ap_const_logic_1;
else
bufw_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_Rst_A <= ap_rst_n_inv;
bufw_WEN_A <= ap_const_lv4_0;
col_b_1_fu_207_p2 <= std_logic_vector(unsigned(col_b_reg_106) + unsigned(ap_const_lv2_1));
col_b_cast5_cast_fu_197_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_reg_106),6));
i_1_fu_404_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(i_reg_139));
i_cast2_fu_363_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_139),32));
i_cast_fu_394_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_139),4));
j_1_fu_478_p2 <= std_logic_vector(unsigned(j_reg_150) + unsigned(ap_const_lv3_1));
j_cast1_cast_fu_454_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_reg_150),9));
j_cast_fu_468_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_reg_150),4));
p_shl1_cast_fu_237_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_fu_229_p3),5));
p_shl2_cast_fu_329_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_20_fu_321_p3),6));
p_shl3_cast_fu_341_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_21_fu_333_p3),6));
p_shl4_fu_311_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_18_fu_303_p3),32));
p_shl5_cast_fu_380_p3 <= (tmp_27_fu_376_p1 & ap_const_lv2_0);
p_shl6_cast_fu_432_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_28_fu_424_p3),10));
p_shl7_cast_fu_444_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_32_fu_436_p3),10));
row_b_1_fu_179_p2 <= std_logic_vector(unsigned(row_b_reg_95) + unsigned(ap_const_lv2_1));
row_b_cast6_cast_fu_169_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_reg_95),6));
ti_b_1_fu_357_p2 <= std_logic_vector(unsigned(ti_b_reg_128) + unsigned(ap_const_lv2_1));
ti_b_cast3_cast_fu_290_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ti_b_reg_128),6));
tmp_11_fu_229_p3 <= (to_b_reg_117 & ap_const_lv2_0);
tmp_12_cast_fu_247_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_12_fu_241_p2),6));
tmp_12_fu_241_p2 <= std_logic_vector(unsigned(p_shl1_cast_fu_237_p1) - unsigned(to_b_cast4_cast_fu_225_p1));
tmp_13_fu_251_p2 <= std_logic_vector(unsigned(row_b_cast6_cast_reg_503) + unsigned(tmp_12_cast_fu_247_p1));
tmp_14_fu_256_p2 <= std_logic_vector(shift_left(unsigned(tmp_13_fu_251_p2),to_integer(unsigned('0' & ap_const_lv6_2(6-1 downto 0)))));
tmp_15_fu_262_p2 <= std_logic_vector(unsigned(tmp_14_fu_256_p2) - unsigned(tmp_13_fu_251_p2));
tmp_16_cast_fu_273_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_16_fu_268_p2),32));
tmp_16_fu_268_p2 <= std_logic_vector(unsigned(col_b_cast5_cast_reg_521) + unsigned(tmp_15_fu_262_p2));
tmp_17_cast_fu_299_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_17_fu_294_p2),32));
tmp_17_fu_294_p2 <= std_logic_vector(signed(tmp_12_cast_reg_539) + signed(ti_b_cast3_cast_fu_290_p1));
tmp_18_fu_303_p3 <= (tmp_17_fu_294_p2 & ap_const_lv2_0);
tmp_19_fu_315_p2 <= std_logic_vector(signed(tmp_17_cast_fu_299_p1) + signed(p_shl4_fu_311_p1));
tmp_1_cast_fu_193_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_fu_185_p3),4));
tmp_1_fu_185_p3 <= (row_b_reg_95 & ap_const_lv1_0);
tmp_20_fu_321_p3 <= (ti_b_reg_128 & ap_const_lv3_0);
tmp_21_fu_333_p3 <= (ti_b_reg_128 & ap_const_lv1_0);
tmp_22_fu_345_p2 <= std_logic_vector(unsigned(p_shl3_cast_fu_341_p1) + unsigned(p_shl2_cast_fu_329_p1));
tmp_23_fu_367_p2 <= std_logic_vector(unsigned(tmp_19_reg_557) + unsigned(i_cast2_fu_363_p1));
tmp_24_fu_372_p1 <= tmp_23_fu_367_p2(9 - 1 downto 0);
tmp_25_fu_388_p2 <= std_logic_vector(unsigned(tmp_24_fu_372_p1) + unsigned(p_shl5_cast_fu_380_p3));
tmp_26_fu_419_p2 <= std_logic_vector(unsigned(tmp_cast_cast_fu_415_p1) + unsigned(tmp_22_reg_562));
tmp_27_fu_376_p1 <= tmp_23_fu_367_p2(7 - 1 downto 0);
tmp_28_fu_424_p3 <= (tmp_26_fu_419_p2 & ap_const_lv3_0);
tmp_29_fu_448_p2 <= std_logic_vector(unsigned(p_shl6_cast_fu_432_p1) + unsigned(p_shl7_cast_fu_444_p1));
tmp_2_fu_201_p2 <= "1" when (col_b_reg_106 = ap_const_lv2_3) else "0";
tmp_30_cast_fu_463_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_30_fu_458_p2),32));
tmp_30_fu_458_p2 <= std_logic_vector(unsigned(tmp_25_reg_575) + unsigned(j_cast1_cast_fu_454_p1));
tmp_31_cast_fu_498_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_fu_493_p2),32));
tmp_31_fu_493_p2 <= std_logic_vector(unsigned(tmp_29_reg_588) + unsigned(tmp_6_cast_cast_fu_489_p1));
tmp_32_fu_436_p3 <= (tmp_26_fu_419_p2 & ap_const_lv1_0);
tmp_3_fu_472_p2 <= "1" when (j_reg_150 = ap_const_lv3_5) else "0";
tmp_4_cast_fu_221_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_fu_213_p3),4));
tmp_4_fu_213_p3 <= (col_b_reg_106 & ap_const_lv1_0);
tmp_5_fu_278_p2 <= "1" when (to_b_reg_117 = ap_const_lv2_3) else "0";
tmp_6_cast_cast_fu_489_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_fu_484_p2),10));
tmp_6_fu_484_p2 <= std_logic_vector(unsigned(tmp_4_cast_reg_534) + unsigned(j_cast_fu_468_p1));
tmp_7_fu_351_p2 <= "1" when (ti_b_reg_128 = ap_const_lv2_3) else "0";
tmp_9_fu_398_p2 <= "1" when (i_reg_139 = ap_const_lv3_5) else "0";
tmp_cast_cast_fu_415_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_fu_410_p2),6));
tmp_fu_173_p2 <= "1" when (row_b_reg_95 = ap_const_lv2_3) else "0";
tmp_s_fu_410_p2 <= std_logic_vector(unsigned(i_cast_fu_394_p1) + unsigned(tmp_1_cast_reg_516));
to_b_1_fu_284_p2 <= std_logic_vector(unsigned(ap_const_lv2_1) + unsigned(to_b_reg_117));
to_b_cast4_cast_fu_225_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(to_b_reg_117),5));
end behav;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 16 | 94635 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eQ6nhT7GLP5MtXb+fBlbtE9CmT+npnamn5AXBYnTqfyjeOq6DAIwn6lQgTicnJ/7b8vS/pIqFxJ5
z65AlaBqqQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ePvgcUCXHdPAno8UEDNV9Pww4PHTFcoymZ491nBzb8ykBBL6o6NnFLuEgwxxviKgq0H7FWPEEF5y
7ZLIJXzda1ao2w72+vmvWH2EZiuCaN2z3rPNz+DrfsXwAzGb1OH4/Iehy3XvXtGI+zucH7hSsj6a
Sc9vBvA8dBIKfwHll8M=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
dQdlOZYXt9reqa5XybzLiaJAnC7PUoDuampMZ06ce/L/c63q0Q1KHkbmXMSMS6lB0N1ReSUcbWpj
LRlGAf54lf/vI0hCDUKC9qOMkfB3es/YMzriqQ5y3aqWB2iF40eOUGfvVNgW3SNszF46OzwxnUyy
6s7ae4HTuu6Oqwopmts=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ulzmoAatkfiB21vOKwcHgYwoa7BgjojqhgHDogYEawtrOHEVucioVeg/09JBXSV1+1CMAQE+o+xo
TYQoBFTxNbgb/B+5EnCgrZE1BiPORtAC5hOAj+HPBOOVm2mKA+QWDGunM6eHx7nJAgBSZg9T1kSP
eDygE/deOV+bjrO3rpg4lYTj1uDBc/gqNdTHFpKqxuyoxNx8OcaKnKuxzrW35ZhUKqACkp5kC+kG
KelDgsp53UW2XScy3KdDdEl006PI5yNCmgbk4S5iqeSNRQ7MMmIg6hix2Vt3lFOSl5HmwiP8A5BE
3f1x2AvKprXs7WCGiBI+NJqQkbQovB3T0ml7CA==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OGtogh+d5rJyPeZ2theFRbW3DATHEGeseww+Pf16AFQWeesc5Ps2gR6yhoEW66CSwrYkGfxk/+bn
0YrsH/HdQo70gaMKCUlaK5kI+6BRzwRPhe6gK2gUTfsBGgUKmCYt5HOyc6kfC3EA07RqlEl+KnDn
Z+Vweg+pNPisU/C5h2GCwOrJBgyua2qstCNZXCViH/oG68/+0B6OVtP6FsYMQ6Ffyj9IhOPe+Qzi
ntX+aTvvTuNEKh9H7VaMej/Av88br6g8iPHrBXcroKOfuGf4CpdRfQGJ4hrUodXcFZY69Z0DvEuI
tAtNz/BCE9leHmEs8edC31wz/asz8IjBnNwWrw==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
YN7C0KuBvDQtiCpi8qP6cS4kuAQsZBZ/QATwixLjifIRlVF4p+2Wq+vgTTFt5C76A6zV5MlkSu1P
De/LheUyN0bIlepSnrBXYk5bHJ/wtCKf2eL52S5bBQV4hSrTHSUf/DuCmWsO6nYRhOobBBh+wc+B
hQWuxi63uOR3qpe2uUP0VjroyoJ8au72wQAUSpLYpOGiUdHScchVkm4TZ481JZSNyPMnPorDUQZL
jGs3VLfQblegSlnSPlyLBb+vrttOFNzLspmj1i1Jv+DKfUhvr3MLnUyGGg4iqNgBY0huFW8bIOHG
f/mM6bayCz0lG2m/RFEyhjemIQSpglaRAHB99w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
hatu1u1ZcAW+FJ1F1qIzVd8M+jrmpd23JO0sQ8zKAqrAfC0aTwA8JxGlgNuDtl4dBtHwl4mPL3Ei
ukxGIC35Vheg5Tv8KRq3KVpRUJ0D+I07Zfu5iZSP73RgPlR5umqeXbcapJ10PYPrVHlAE4Gnshyz
+CebUS4gcBdkkpfJYIfEckmylDrwGt+FQeJdkNsFAWBLQszh9Inb6+tpsiHQrlG17OrmPQZnzvVy
UuSiuxJTj5TEorqFfTxjR63TpGOqBkqOX8Yo2cp0WVFWnDbTd/tuhUbgGinebdLp2RbY3cQfWtfo
pbfom9sGNKFME7KjcYn8afh99AGrEcQm9Wox/VDBiSl6W+C96ur0fJB6AedAyIclLQzOshQP9/PW
va7N3n7eY6P+TIyUTpZWWvofhx5hURk3b7PAlBtYfmApp5v2pu/qSrDenvFNOOmaEvmIkNgqHw2U
g+va71Eqc0spz5PAS9cTC5ipVbf0fCLhRyIwhr9QpmRJkqDzwD6W9+Nr6Rm+FNlhMZm/hmpUoFhV
w19PVNGraBy28H0eqHcuf8NGhAje/CrfD5XQAyCkD1mlbmwddwhHCDkXwmsj65p7yT2gNLy7bAGV
CMga9uCAoP7M+YP/kSaAFYEZN0REjug7BCN09kn71DzL+idq+l7oNkBa1Tp0ZeCVDOpdqGj2kNNw
XzM0Q+tu4U63XuK5fPLGEFyJy/BHYSsl4j/ox6UzimytSMkvF10/nacuK83L2DGZTj6ZOessuNQY
GNw3F+kBSZCJcIUcKm462c+XifZXUm9LTHO3iDBTodK2pz4a0pT5KNBHTw72mbc7+MfPkZPtz+Aw
km3UzPP6cX/I+s8RIGQiJhZy2wXyU+FOsYt+4cu4G8sMOAMlNyX1OUJrjRN1V3Ip7olYSZ2ZWZNJ
582gpngwHypkR1Q3q/RAmpH4mvSSp9gT7dE5Pe2fSZw2Bjo5UhhpzTFVNqFHyCsOH4EIwau9d1fa
3yj3F5Dyk36moL2VpEqBC81ZYAOICrjqlVmAjVkD9Rg4IRDK+BgfZpJgUFP+i+TdADgoTt4ngU5W
89Rsi6onDiRhWUQSMCbdc8dzvYd/U1Beqk6YcA5oUvd2KgjTj8ruQq+uOwA5rohHYRqpfEojxEpF
eiIkrgao20ZwsmxBGuKb11K1Ps76GlsFmljHMx5Lfgljd21/lAKFa4/4XXqAeIwXRlLlGoSTtXgQ
fU+c56ltPrOgQURlVR4eVVtYaYdocq69zy2rpK5NTvs1Wh/Du5y6BO6FcUTFJyGqqxr1ljyGhlAM
pzZi691jEY8Ck0ogk5GRRvrUOipqBWwzqbzm9p1t+e5Qua+LVouFUc+SSV372zw4Jk7XVPCxUA+H
B3ZWK2LfalyvlHDtOBheXAL9mysRu5jB0H9MM2CPPzlX4OXZyjhMdxRzcphHUZV0QIhxdZ1pN+hX
oB36w9/9ib0cmslRx6Ot60t3ivfqTKzmrsY32d2/EXTthgbVhBX2/rXNTuLLAQGJMuGrQLgVul1v
EwrIwJBE8HE9/S8TBmddP0lHLrzWk7Lj8nZFb0VURWoqwz+oHFwH9i4J2yJap/2MpH+Wpq0duTDS
/UYqt1BfSI7yxciu0S9tsi6BmvYpQ92Nm1OOZ086cEbV9vPOJzg7Pd+oB1UppyVY7zdxGXNpc6+b
M++F6Qc/iFM4brEKeJUVMM75Im9XzmiH8UMoB1k8p8Q3pu1YO6YV5JtOFHREVHnXEsuWxkwUfz6D
kd7R0w2z57kUmhBCl8UQ2Gl8jyPKwJN13p682wf6o3Ah900UBPThNMySiu091hNByVz0lrFoIoxd
wNYu6veB5qX7IFAF+HQJiFkvC7RfI3rjYh/TwurNBfXQDGEy/GQvdVCi5BC/KyAG4fVuEnmpp80i
SBBKz8w8Vu1zyiYRN3rf7LCvalLZDR33HUgjoHiztEKEeNGy1tdgXSJEGFKT+U9fgu6vf7vDOp2K
D5dbqaDzWmXsmPW/5Isyl7G73gtu5zyxqhWVUUmzxCilvpIEm6WnHRR04KldrvRVWf+2xUH5NAyO
KROR7YGAVRIwU8FNfTM9WQWIo9QQiAWcfdC2WAcJ287ycgYj07RyYfzhohZ/Bvl5pFTKpB5bwFTF
6HcSPuVDL7ade4G0jD4dUSQCc20kVBPq7eoiJl6zKXHrYsPosz7L7MHSWhvHfmGr0WNPxiBvfNTP
VZXikghW6lrAx7+Z3iCtEq6RTk/Rh2l7zuR4TQsjoV9yl7DTB10Qtl5nx9/vJXF2CIcoV0RdTZtO
9eoCvxV8d0soMR6I1oe2kYr6UyLbtyQYgrZsAqtjTGOkbFfLqWxQnI9ooHyidT5G6vM2KTN6FwJn
vXesayVB6hGMdB9lladRLqcIIXoJFNHbxLzlO+ZB3hbc7wtoEw45wrN5tXMktBD5Jtn6OrWWbqT2
WZvwtxzWikruLG0a6m0XSQVya6DHNT0oRzcD6MxzkmVgKg8YQEfwVjH4v23AWWBd4mcl3GsMADlq
iDK7tdS3TIpacVsWhjZOXw4xmBqWbGV/ystel528hquS8Ny9ZG/vBDi3AQuqbF1RaqwTE7Aplewd
9vNIGsrvsgX/NQ4UIsEgoWFd+sF1gIQag8dke7h/fQt9wWLhZD9m3UnTdsqWWD2hurg8C9wCxYb+
9HnyLdRNEbbC8OnJp/dIrGTd0Z99kEspEFfBTDf77praWc1UIsMCvUjn1rlOWNfV8Kv5krAYK6sA
oEuFlIznWUcn98u71kvUAdQ3Gwx7pdmHy2IsbjhuxhJi9thqbeIbTZMlB47onhPYWN0PONc8aAcf
NEUTaUL1JVYFQsUQw+aS2NeitXBVAoUiue61nMeeda2nAa88OFNDzYnCCKsgnwyG5eNGxgYS0UtF
XVgsNqAT7tnNYiCUq2c0fauJPDT/5by2r4Sa0LcJhivXcBekEe0BMGME3uzG5Iqd6LT6Hf+A6ijf
Gt9abIA8UzA8y66AV84zbmeRWupsSUhqVvhcD4uiIHvO9f3Z2RRJag7d5GQRzvC/1n2rn12XGvyG
90NGI+FjAS2s5BH7qR3n0g6S+9mowMsWWQ9HaG7ULBgzuBo73m8B8IsT/3Dg+sM3WQS7NI88cbTk
gGFEB6E4/OWSbz2azeTdJ1NVcNXdrArqSoezPAjco9W9+psc5AR3nEI/MESAbejCIkpeApRc7oQP
do2pbUM46436OYAvJH8tA5K0ZdTyyE75tgusL8kkgju9wd9IhhNCfPxYnWd3JjsBmXfa8W1AzeNt
T5yUJbsLcLJn9W7oM6NKlgZW9poqodkdzdbjeB5Qwh8RFowX6oke4Cjs6S4hzG3Z2A2JyBqhoXYV
0wOa6DdGl12P8UGNrYAy6gnKkSMgbQ9WFbm4Ju0v+mjLDO0DCCWBZKgf3ENHk5oGwcunf01DrsZK
dsKyqITLuGxwNum64KSk45ptl4XErbNRcMMLKNk6F1iSd44FqgHcaq3+V7nHawyGGl/UicwXGqf9
TYUHaSyBARN6oZuUkeZsOr6BBqCpWUwMWBLJZkNON35iykZdR1Xb4sf2IZ4PgXvlndCiMeGcVsfN
3YBlHxac9930Gk/Lw+svfMzta8JO138q8ROBmnmYRsOyIPhQ6o9gt5cO3bOs2PCp5FEd2hG1Iwg2
C2wWAGknXbIv4LNbybLRzRNpDMx8sxjFO6DN3xagbCnmMkQt4NLyiRlZWdt0/0joNx/inEIIATQv
hNMUytRM2SQ/B1/Z+5buu87rjaCOxk7VgZRgrsui6UpMr6Qc68T8FwzDhXwR6V/wVfrNyAeQ9g6M
ogB6JZrAo7WWwc3LkAGOxVKOsi5LrmYpQ/VFzQ93tEcCAyxLXinkSpaBzTc1vTnA4fBljLUnvrbg
kf8JdUSFzHOxWMeGci94C6e+R9GHb8zk9CIFw81TEiVTA+aY+9DvbLATYNHbTCZSfubSnBABxNBO
dArHPCDw1w4UycA6N9rHsr/fxw2HC2s3rsfm0dV4eYHyEChW3JdJ5RTDvPWykPxpcIz0yZHdQQuj
48ThWjT7mitpX7NHjsgJ7+sQCmMJ7suWJpzr37SIKWQO+KLKQiRHcCfcSzepZpfqfH+ZFUf5yK4Z
zBJATxksdWMakwkJMoDasC0WlrtM3/P6p44FQGbpngbBOtaFYEKBcMw2EVIFWSnzN1L2nzySL6HD
fBjNFLuVEKkh3IgoCVVa5aWSAHPx7dexgRnra6pzQh9Mw9XVoFJB7lUUdER1w/a5KDLsQEw6gWxS
MQG6c6/T3xB7d58sfbeR7Nxqg17SpbLnJiuaRAwSnWHcJavpr8CEtBD3ONQbJd2I4gzfTcVr63QM
w+Nkxmi5dJGqulzS+v2Jbnf7KFO3XbEzX3PX6B6EurnXiz/L2PBPG4s0tXMFfez3KJDydBJ3nVGx
Rwjt2sYHIDnoye1bNYhdfrT2tgS1COiraWN6l8Bw1YKG4isNq7KQG52vx+KfmreL/DEidrkO41Li
d8osaFTPjT2o9OyXLQf5n2V3/+yPDfFMpxjEEcenUCMeMC1kZaAXPddaJInbfUdKJ3cgFPsMNL/I
uqy6RLAEZCit63iZbIGn14kKnzwpeUrS0fL5F3OvpCmqvveCdzJscx0x/eqyEk3gWPEbHBUHqelp
7ZUGoQU4dkUIbfsXvN1OVtiLWJPDSf3w3oXwmo6dYOeDemVo4v4b/kNwbI3/MrbKzDE5jMLHQ5Mc
6lBdixtTwUuyppwb9U7w2Rp5qxPRGTtqXs9FQzwDRmBxCbIsmueHYysjuCtwMERioWpH7QxHdc0B
5p6TaSRlRCDF9jbeSftZPTTmWOaB82orBXz9JnIdXwnP4Sg511vXeT0vRz+cn1p2qoP9U1eyxec3
o9LQgWtVGN7oabOZltNNVeSlmdyo00I+ICc65VQeUYJZkMoKwBJEksl1ZfEan9IBaeLjC9zVz2vP
Z08V+/vG8jusojakwnCWJFznrmYQGjSiqlRAwPxhA22rf419sbn8BJATXjZNG8LpD8KzAVm8wEjg
XWW3k6HVPDVc9p7aVaBFDtjag91uPxB7rHcWBrb8aw99sGmAM/bA3sHK943cWTejGEY5Sd50toUc
dyjGus90zUeiyzDTeTHYcIzuTiOKByvoVC4KnWadWdcD5m88UI7H6dfCHWmds9WVLe0Usr1lDCJ1
ySiZviePoN6i4ftctju+FnuBXUd3fgUt3ve0C6iPaj0FodbiCeFmjvF3d3R8W2UYElONuy+7bpS+
cRfnWaF5Efw9q6+Py8PRN5NDwpdHYuJY7/9oHY8/We4tVTiitQ9r8N0gkDmDq+qK3v2fAMFVhL0o
UpN+Fkyw0qg65ph8cohQvsUeHInzFq1UFv5LLVd8OHZ5UR5JGxFd1nQS3S1K6UWtSDdJjBnKzfeB
oO+2cjjvY+FLZ2rLC8q9gCwKnJ6Qh6qRubhZDFJujqOcBrAxWhQuBtVle1+7I15n0pX5V1dDBSCS
7OPZxOBINNeqC5yHNw502K327L6ZyIL1YbE9u9Qn+nbutBfMenzC5/dzz+hF1esBzsvHwnCPKCbx
+pboxmfjuuG3tuBcFWtCVofAH4OrNpfURN2pi2V3VCVZYmN5oq8jiIE7KK1fKObHnVzbZpiCUSGf
T2HCDExtUNOqAmA2584Nr7d8o3P3XwfhECLP0p0BSpDdGlXxMOpOXqWkceEgpyntJtebJWX4icEi
ne0KMGgMQj1Ouc4AfJ4uAXRWj75iulpGZW0++cYozzI7VOxs4w8oPYHVfvk7zdB6+DAnkRGYKxi1
o72sgnUsnmm3wekKep7xZZQ5EYukIJ4v9OraSVBjBt8N/4DcDaVCN0QKSRc2wvnkOzFXATXY5P0A
y2b7yhDU2Oa9Fy2rNEdMlW0e4tNGLdY0jOZj5ot9ZgxzWxQ0Fty/SMAsb9reBHY6pjPGUdRVUbE7
c8/jqNcAwaxQTzIPcFfdRaRVFVUJqvUMJOJ00HNW58A7xH//OS7JqAv6vc7hAJkzEwnU7k/sreUf
UP9R5UzXwGxWtjDQEYsW7M6fOom2Y0RjbOim8+z7j79sSeH5G4j1k4H300FjPQnZ+n4ReRCyzGpG
9IXFt5CST1BPSElRhQxTIpmHFyPNbWjxTdGZNeq5u7MeRNNF6b4pMnLTqwZ2KINiDry7VLZi7QWU
eaOCKF/WheX//W/QKNsp1u71e13tR6FbOmY5jLrgqT2QgUu6k7dRJdv5hgwWGkpE/8pjk/m5T7Zs
MFf4I/Yvt1btPk6K+XbSIZHXE4zZmT7qNgm7EWzAqB3C7WFgIZbXWR+yoF1Nd0s+x1DckcMcCD/0
PQIdw9dpyoxrtddn73YneQkcxlDoUQKi7Z0EiLmtV3NLyECGTf0AubBr0H2Uicb7UAGvNML/Rn2t
AQpS0aHs3rpQkxVOUXKwARnJQpI8t7Rszj7IjdOaNUuHSgxEhDXl7eRGTpMKNrD1zmTMJDcaOZ7T
jDsgfpts5wmm96hCOY/8Gr/JMg3jE0ELzov8O9RHnvR/bds8NVI6k8/XUPN3uTyemAybD2+Tx4M6
XsUMWBJpTQM2dD2u8hbSbCnoS0GR1mlari3W/D1ue9gRoFrl+dZgK3Lzau5DERRaFZI3VeqZVjkA
KCWppDWSmEiw9FSf55es2CrL5uJ0olKRBIc2m3WIKK8U+8hcgIU1RMJEDWH6vLCcIED7NtcUsM4s
Sc4axZXBEOpiQC5+5L5aCyy6Di0ZN8xmfbVM2PjvmSDGocmkdrhyjZYaytwyH0Cutn/JovJA8OrJ
jJqVFdILOqq1bctrFfI3YLH1PRZVvuNOx/HPBrn8/SRIk2MJdQnENquF2APwvIgJ8H5dYTKvSYOM
A+CFkMcFUkhSPYjjhsEs2VMQKk3Osb+i4f3wbso5LnnyWyDPiVMpahVg2mSQWuCW0W/mgdT7GiIz
3z3jX7qboZiJxIaV+OqfjNbGk5S5G0X4qKqqyauX8dhzLVFw/oWwqxtJXVI//KFqQzeZa25UyAfL
mdn7wbWXgSeniJ8wY/WPczLquy25bVkQzy8DCiuFSoG8YSJGnvQ1MOGwSNkF5kfXCOdLNGjA/LQj
sReoMelZzzbIL2FYaZyywb4xRIL4eww6+N1+QbKukx7I5iD1W1HxPfvJhTAVzSNIDHlBOi8GEVWy
Ke8vjfj8DrgvOouYfj3oNPuPjF3Sw6w598xPeD+Gjx4U+muFHIYVoZdB+bFK8KKXaVRhdqtMq+7O
TrYYp2KQIaZBCkehLRIWe0VrZk4E/hvG1joc6/4WikUqPLcG65YDNoDqU79IBIBlA6hm5oSU1nQI
o/0bnC1/AXsgJLuTdvEhgtvYPQq20M3DZz5Fsp7n+9TV1G75z8EkFtF6ekPjIfR18M5x9SkpKj7q
hxrISgdlaxj517ncJT51BhMNlZBeKtGgFIV4T+56EcaRlDCk/5XKDgKegHRGDD2gY1E4uTCtzW+Y
rarTQ0oSW8R03Qg+5QMttDB5WGFdDZSAwAgNJ+MbnwLx6Id0h4WJczmn/kEain3bWjjvHLOBEtDi
3tSEFMJrGtFngYwO7hhsfs3UecwAtsSEk3H170mUd3oQ2vLl0a0CI26rXbPmgrzBhVCnfuNiudyR
glbn82eemq5U3BqcdUGHKGyML79w8rFOm6U6L0hoBxL1nq4Smx4biZ4owpP/EL2ybVxMetIYDO9j
nd1PHmjY29lrCEtDweQC7wxRd8qMU8KE3ePt5T5nNkEnlW/RBIIl6ae+Qq952Fvm2s1p5dmigVro
5Ma1WHisnZjwP2OuK4zzsWwvTNnbUUyAF0IY/6zJUIrl70vHh1upjLH0098pgh+6h0vJo1It7Usd
aziE3cLYkQ5Rg+22PkqnJ+qyZzywmvzN+LvdaxenQIQsfgkfaqQzym0qYhR98q+rNzSG0k7iU/bT
MCppUB/X6OlND/65I+RSxgLHjF8gt7gcNXNi8od4dVwYhxte0Jdtjvd49rvOP8w7iXfclIMFsmKZ
mf/cCqwK9+P8bZidvOeuJC8fiDqc+wgAy7gOhC+63r8+tb8HLVXBnNn4NL+8ub7XTuhkFOBdbfUD
z4tFxBWkqaFBjC6agRtbkgnSRAhx2l2OukgWMO67aG3oMPH2MGEKuZsXk4FF0v1Gxu1FvlGneYrS
sY1qiRWX5BuLglkjZtyxJv49vLa8TvishzZV9ygWqmoJ+jw78lIrTXORIDI1xwy6hUlar6aKJIiU
FlHvjlBh8myPV+pkG/b6CSlNSNErZr29KabXQUiOaYkAJTXqT8ot5XRoyAAjlgJaXl1MM44zXsiE
ii7TfXweDBcBdDUtboMqJClN8eO7zfsYN/OcN7Awc8lqhLZjL1sDYeviqpflwfHAK47WVVySGz1u
ahRgVqkXzYja3uU9N+FDhtyJB6CCylX0FYw1eBEW90gfHEnxZYTNYq0osQVtGNMt1DSrauhEibE3
XLMwucKHDOLLAr2kNDTU1L9h+U/BNe+588xD5re+azXDEFLrtahp69n50gxTfIcxy5Dq1i5eTVAk
K6+PZfbC1qjwpVLnazPdAhkKzNtvnMnsUGTPg4S/ehVnoqDNfvrYjFLy44uMkbbeEMKHxyfPpsfc
TuUlu4C3160m5CPUuSE4QSwhsia4Yw4Dzdvruaz45YW0i42RPYF8PHS7RU+y7WU9klyhQKl6CkVU
NDqgu+EzsgxKDtFUaRmapjePNVtyd7HdJDdUfbx0N6BBJ9NgmM7XSOUlX9WVNRzKnksnnhogYHzn
P3wkyWuqlbnSVovKHrx4/ECC2EhuBwAh4GzojwzvOsVtm4x6Ua2J6/DiQsVO/GZ36pl8vGIzB1eh
AmnMOrQo3RMLzJVMDn6uZCWONZEweasDi1CCvSN5F1sAFsvimnSHDrcVE54u5o931B6CvB7wcgXU
r1+hVkMfm2wC86eV6AopplPL988uS1TUZtXmbHpZnzF+s422VszwYag5FkjkeUzCz9KraVPRlk2c
9WqmVRcELTEpEzIACtlH8cNPvlNyq6Idbq3Z2E4FZCNHI+Sxf8h5i/yP6cHHs+fcC6NIAg+0enGu
W02N9u1zOqXIy4bWQOTeSOtaIFN5AenMKEQz34FD+8cTTVvNvtvLyXGVKXZl614mxPh6OcExBmST
51b6x4QQwnc+rpwPc/+CCEn07AH1urp+Bdn5kFzKw4uOqUkc1ZmjwKw1HK/ln8abL0coddLovcDc
F/reGzGYazDVS0QNBx8PE6uDRhSvndmTcsJKMk4L7akeQppNpVPpayPeEb3nVTz0GyaPPIW0gXYg
w4AKNfhcD5uy7oPJu/VSYENrfyud58dFD1UhK14DHReNZDohrFS89hU6DWm722gFNewy8iwYjuY0
fQZJYV18Qta2baXL6WBOlAIck1elIOl/lQQ2ek9pMCQ9iTJ4MmMW4Ff9EOLa2APo1OvkrkI1oGAW
od947drlNdHGG/3MF4xcNcvoHNWpg/1I+FWvi98SoKNXTP8IkyygCrEKFdwNKcxkMqMOPHl6zkxv
ayPUNQnA+szsc7G1oNsd2htFJZNHrvO4R7FKcc2j8YsfxUuUV2K6k8mVQaoPxBR81UnCaghRsEe8
smnKUM1oBlIdy/ZYVznvO+g7kyDqkNEFLw2b1+KkI8dxNrkk4Y3XjZhHFTZr+6w595/irVKvvq0N
N3OIvuALhYKT+ALqXbOYchT0Xmq7znRGN/IMAJNgaHRfYmoFJ5RoV4x6ZjwzQ6gXmzRT+2IFoK0G
nlPmR90HaU11ToDdceLTkyPS1arbRE3VwfYnecQ4HldwySQLJJKWGdvG/Bpv4G2oycG+M4gVpDo8
RYP2YJxJNFzOtpr7W4A1524QZ2aLOBsVGg12An8A1SPhEZX/OqkxC5FwfBnxhKkAhCLzths4r8ri
k9ivlO6Iq8dfM/xGDaRxXlQeYRskzaNRmXl0rsbGuXtoOneJKr19oq12XIv469/q5nn/nP4TeLvM
paM2uBvNlnPLn1Ft78xq6izjbHj6yrOveSDGNX7zvbxYE/DiW/4mwAYmnodeFwirTHWdLTT++LYs
0F+bcASYi7J8aR1Quzsc75TP5YKC1x6VmU2S/l22/hjeSFrzbN3X8NBg+Da4de5auA4tkZYANbDo
2J3YUpif6KFftjRzv2jFBtJA3T9zub9jkQThIUoVcm7z+OVyQp20molcV80VXhv8NnmMt2NGR8K0
i5uRFTqmAdgYGFdhzv2dnuXRGD6zx3+sluQ8jXIMNyURdb+hBWrqBDsLyy/5mXQuTbW1Dl6UH6Sm
YZHrZvNiQ45fk43spbZToTBBJ0Y8iZtVaAgFozkxcQ0vNv1h0fD2+xi8c7KZUikbrzZlceRN6ITY
ry4u9c5zxo6pVx+0NXxNGVb7vKC4+MpIxCPynhcUKx2Zc8cfWC/T8/HyMpPa7L75Jipph7l2fSLp
3OuqDGe8mypF+DLDGnfeOi+ijvg0vp8eUWIS3gVeWQgwUIkCT3SpD9A75eGRhbmXiLRmCSeHJE67
SJ1cN2q3ve17nBPOmxHrGS2A/DaXH2rsQdtq4uaQtsrMsOLETpCfyhQ1l5JX9QmZS7vYNEbCWL2P
PmkrR7+J9Cj9Uk7T3Az3rH1HvTn/HToFABDaUsQ5F3uAeQHVHoRc6HxI2Aat8yoA2ruSlQwt245M
G62ru9jAdGBmcYUDNSnimsOgRE36TEiyI/OP8T5UHIU2C9h6hizpa8LuZ+yg+RCZ5VBhSwdWM2cV
d+C3YTeLBP3oUIm0InxYBxF2t2hKtjIvWawNducYQ53JWK+CkEFaS9b15uci7jUij8pgmeUy12Ft
g7WyDq8YeMxhVF6fWSK+53kkY8h3GXGKBFb8zHx3rVgbdZZCONKN44gDUGqrPVLKfT0aaR+HGNU9
ESUMHAGgtgU0E4Siow3N4lOa69B7npu/7ogFens3o+uSzfMNFDYWq8vd69+LTzwOZPGURfT/KIIY
Gt7UPek+ovfsKmNR2IbVzZO5WiFDcnmA5wWzRRya/OBe97jk6uwdmuwUCjjtbhVsayrzkl4PYC7A
L2zGesmKTRX7KqHQZMC98ivw13rqJJGydQqw/785T2Es/d5qTHUwr/Vbdml2wb3dLWNkLPJDAGTi
vtb4Ys7MQinTRSmcdhEOpOw4GYRa+fO20DmmPj2pv5psxMCtmXO61K80EuR+kVIPr9KD3OFB/hi8
dPlniXaDKWBPy8Cs4khmreMOZY50LndcQxzQnvUMe2PMcOJQ6LhKa6H1OsSKDzqIFSVJV4Sds0ir
emogBKgC8lDnrSuoCsrS/qdtSswlHvMlNgt42jn0T/7Jz84opVqk9jp6bNRh+UTZ30GLKYEpCXMh
YZjqKC+cOFETH0HvIP5vjS7DEdfE2F0dYVir9ZeJ2SeffB8Vcw7SQ0NWc/gQ40y5mfSW0sLFirfN
fbhAlBDVTtP7fxKwt8DfVU9B8DZA1RKZePZQLbEXcjG2bwJtwsVtGF7//9YG6lqN5pM6lGrym8ge
qxxQsdlRCH6TK/ct/g7cKWCB7noMOQewBIjKmfxOCEncZWapCyEXvRPEHE4en/zuM3L/MieIPW6C
005ADVbCteWe+CqEIj8zmoZsTxZpmmR/E/TdH16UnhlaJusa2BZORlKfCw48DchLNQV+RsMDeU/u
gzP6UhQfe7moPdczvGbOZsJzx+Z36p2DbmCZE3cmBJuu8iEq4sQEV8YOhOOFJDTDeFvJJw0mQhkx
zSQRooBErKa+HqAfo4+wnw0aleUKtbrc/BCqD+A0aqAxsVdoTsNvzhY9cnlskZ7KE+GI3dNREVp5
M3Fak68iZ88OffL2u/D2IouSUToqudIzv7H1HBzIik42HQcgI6szE5DO/EuCBxlGlwCJBv/CesNw
EgtPtglYx3S2VqqBT2td292ysqxi+wQ1e8yJZhNLi9aPjOtGESlkhJX9Xv4CqHnQFGREcOzM1Az/
28F+xGAmRKvXb3ajcnfNKbvAyGkYL9yxnGhJ69f712zXyvQB4Uk3Fc3r6G4LNhAvg7XIEEzcSc2T
JyDCu14Dosj1/dTj1raTDRqexi3aurIl2cvFw4sDkNAbLHe4tJXDwb/Ie2Mboj7Y4Vdiv1nWhwO3
TAzFxcInSF5PvulfmI7Wu23JaeEV5B3sl0nNokbe1bPZLoGm3WkgR8weNyL+J9JBtr23sXbQLsvl
K0xlIQmbVhy9onx1f0uNVSFKmUxTpTFYa9KKmy8kwHxOWb6za9eGm73ghmZfoJRtIdQXf5QUqcJ0
9q4/4ATa+PPQOHetzO9zHVw5xE+7QcXIEOCrNLgCfQ9Icsymta7vyEnlfVHuANiT+s8XG2Bs4CDI
aj/S+72rMRQTZNiQauGJAEfCrCvupE2mPdG198F7Gfp/jw+JRjjjboTpIxQzWTcsLJXkmrp1DidN
hZObCXTcg86cePZu/rvZ7icGCn9R7ToxizTyRkxCxI9naUU4RPixfnNKWQEqwGenJlIk5d8/AeZy
L2OO6ry2aGKmpIEtetkYjI5gI/VFTSODrbyQ5zuJO1Hooi07GwsxciYp2HG31vjfbvxWlVy7vw7q
FknblNM2BYREPXDI7ZQPrNeyS6FF7rXz4W1S7QR2RkFURVhK0dSKpH7Eo8I1ePEjXyfE4msaL1wn
oy7Vw8d303+JvtOQL6pXnrThZ9GHGBRwC7Eu3FLQKvU0a3JerJ6BxlUKeKOSLnZJC+yuCE0ygd1S
MG7x0BNiiln313URLUzREmC5VTFfkV2DzejCg9xHoZfE92E95SnvAb9t8ujn1KgRWOwZDKexZRAv
rXqR0/9fiXTcvRhCk9Rz2BleIWU23DEpKQrAc3HGt+eoPbihDgc+PwGqvzDdSOAE9BpDNEs/UQC+
0qNQXBMmjSgP+4YTn+7sBkPOTKfgWX3CUFJDGyES7vT+pBl6q+NmtVOPGk2nBcGNMEpKZqfvGfT9
N4LZt+10vZj/TV3d6RSibTQKEXfpKwACMcen1Dmm84pHNJ7Deq0st3TgRRMBGaWb9WWaW+8tLmLZ
W/fRANUYRHjGnJgMkWYYOBHrt9qbYe7Hx/h4Mq/9r4Kp7n9kBcnDgaVXByLgUxzOt8EhqcYi1TCr
7B82S1b1qECELuSwv2SLds9/I8f2gwrBlben8Nx2DSffzgs40bABAwtF6q6LZg/nnpXMTSoXSHSZ
SK4ftMzTyGtnQeewvUdyxV3PZrhbBU2grMsY1JtIZ1q9TYB9P3gm3NGTcMEm6WWxHNMdMtPDPnUT
+OF9+3s2EHi6Hiy1gGcpB9Hk2O235751acG272iLtDNmBYRYmZ5aAfWo4B3YZtW4Mopd8iBYStgm
T3VOLaYy+LJ59gRSCW9JfApZPwVF6xK7BNRphS6DY2/PrSgav2PntCFi7Mvx0ClGE4uwkfJNMAD+
Pe5RjqYQQpr1ThgggVByn3YhiEup1GRWySxNULA/+yiUHDYr9STqQQoSavnqBZ1iZhaJjfCYli9y
ow4o07v86rPOO4vXOv/ohkaI4+SE9rq0vgkSTRiQ+EWIA6BcXzA/QfvtzFgLSIv5kc2Ic7emRLBF
OumCpuGZFYV61VPdAPSMoZ44cwh/qNB1zmObPAWBlwVxa966Jh0BNTPOQN2UGQEUBGU7j7f0o/2t
+ASM9yhK3QeahVWSpKqEW88A1baPvKgTWqHvwedkM6p7TgOTY9A2ql2Hg+uGKFdlkzsQSG4wUiRJ
TtVDXVGa9xTfR7lsVWGlaRbQVZyGHuYxngU77RHp1ummSH5/oigOiDJS2sDS1hDNF0Aa9z10jLX0
j85YNnRmNNe3TKfJC1rTCnwaLs6jj7VQwRhNdykIQrcCCcnAAYxrrdevs/eKKoEFJ+WLZ6uUZpak
BZQ5r7iGlk0QpsyeM3YJLjrxpmFrHjXtZpeo9+cP28se7zpyF6LbzXxhvuO9NtAOz7hohi8M9N3Q
jYlw70JEiULzFuFOj6/wHwhGBBthLWdcyLY/0i/vCRmquMDvOYfJhHO7gWeZE1e1xoIR2JwQ8da2
LhnVk+hp1rqgvF/RfeY2KpdNl+dwj/AV+Dq9O/2b2fFSzKYmJkCJ5fBLXRFUyX9qPt4oIcQSt+qb
iKoDPsqkpAXesGBQZYLTVXF9QgkxNwNNhzkslzydzjYCmzslQ8HUuphgpYwhb7r49RzkAY1Q+eva
dueB50ABCJTg8ALnJy0IlUibVNmyzI9eb+jx8bUBjtYDoP2OnyBbfaNfz9MMNgTsqXvtHquMzxCT
KKwDQN4QJnUnyk290gH+kjD3pDMvxsDCzdzfmGL7zkf4SkOd8Jkf+tjwX160JBvCGLZC4X+y2KTS
KBH0HUs3vTpWo7KcTZALv49kc02tSzEKYu+hrp69pn6iEa9A2sybCCR9SNsihuz1rAf1gx3PPLUb
VMvXcqicg4hPJ0jxKpT9utfa7rAobKrGufx97qJauBEXEaNITLB/qwG2ehDDLgnaSV3l41+rNS4j
rudPSH5z6IVLC2P3w/nftv4Zvz3dVma93fjnKjyRvoCTCgokdUvC4EBMXJURG2TAuWnrOUIDiBS0
mvdNr1Hi7hf7/h/pG6hdUJZaSMT8GVaMEKi9utogM0Kyssv0jTfMal+5j2AfGwvUAHG33xkLEheA
bnI/qgw7t99/ukbzs/Z5UEdIHFf5tDuDv4zbYFwLD8SZ+yLF1/S5ALbeSO1BgnO+7SBhTdNh0ZaN
CAuGvry29lE9jWAM3XgnKEEJbIbwJj7EIDYiJudrA66nmGpSx3lNdwBpLTPCASB8eYzvhLeJoT87
fOgNbIJ4p8KmrHHiBv6XKIB6PhFGVB12NsYrtcv0OECi4j/etW4DGkEfbbv3SCUi6nNuk9lf3Ono
IHCoEjOU83aNGFXYbu5ouNOPX3nqP71IJnG/weWfXusLm6NJuBYCeKPd6yE3bWhcv+dkajvJ1KCb
44Cl31f9Ivn1mGOK91dM+awAW3ncodUulwqSulV/B+Xo4jykSaIdIjsreZz0e2GPxxPKXENvcdx2
HWKStJaYjLDNMvW0ywdw3jCCwLBMSBg92rNHwRwn+SvpyH9osY3Q+aG3tvybO4T4mgGvGI0zwDCA
l/lMq5TX/pqA0gPlakPnRHc+UJYLj23/ulJHSq4bAYlYNuVzY23vaKlL5q7ANd/bQgJQOOZPxymO
1AJzkwbdATO46eOxK0wVi4UioVB8OpqhpC1M5ItSoudLU3BVmtfK24S4Pe/QLCaAASzy9bjuu0xw
ENE3W0B1Da8qTiHh5xYYoGQ4Tgqaf1H8VE7Adxbf0zEa7YghrR1LFvuFbZBgxbd0dhqL7OAbY2EA
nWyA+bsyh2S51x3b5SSiWVCqX9IEw0YK9A24VRkgjkpw+hBcURyEZot6Y65ST+oMHbOImf7+UIIp
H1D8Brx1nW+36x5cc699nxrxpV6xjFsMe6kCfu5h2NCEtGpquNyFLcvc7RxmbaNf6kexMQZhcqDw
Bes2HJqt/Q32kdZnjIFj7dCNcFKk34g9n3BRS9TFXeYG7mLRxntEoih+dOSfNnRi22Rpdqey25Gm
ZgHrSGp3nlsvwMUx2k5N79QLfHy6oQmZKzXyI1KFKlHIkqMkqQxHxUIFHv3NE42ZfIEgMBL18OGu
cLI9OjM4CQ2DS1RHqaWbvZ3dEawNsjpNS1zezwlWYlZN6u1MH3EigSh7bM03X+ZsvcPxElSJkJ5z
CZoWf2/cokV01cfvrIX6uxdoP7nVLZ3goLU4IJKldf/fMiFAn+TINTzGUj35KhSCbb9FTTWuoXGe
YIRUuznHLMnJiN7gK3KbxfqJBPJ9Zy2yzKdiO95IxIllg1DpvkE0ZiHYXOqANoDfY72aYQGPigY6
rxU4P4m+BUTqqqLijoPOOD5ozMEo0gmkqKMnitJrES+7FsxykcssDhHqU6yuUk1XT/IJgmike53E
+jrquTRHrjnApoqa2jD1ZgGNWQqdaOho3mR8od3HurptPAbF72XEQQL0f3YNRh77uusNH9HfGUKH
D+nuPINJMS5cUZEk5rHxwXBfk1O0gl4YmrBLvFAiFZO//f3dSTaAsp0fV49JbMN73UoXS33fg0YC
CHwFf3fvErhbGTfKIdN4aF999sRJnw/De4p4ziE1YQjfM1Ox3IDWbrpemgseJhXnbV9eUhzBTanF
4SCkLNE5aqwli3qX4fzkhvi6QtYUsdr1V+38e3PmAgoaOymBt5gxWOylEnkhROFIMmj0uQZ8gL0b
F3/SqOBYc8hDDyM/5PAUlBGwzsGVJq4FCI5ksMfnp/Y3deipPT4+41Vg3G7JSnhqMM6hdcWsjNHQ
/IdUeQ42P57AADMrfZYpseRfn4Vd6JyAZIUllQUjVD8kAVxbkU9vwIqPDfr2mdW73BcYgw+loK2r
g4TJTS1MG8+pRVtqYICpSnmlsoMe5YSTJHx/MPQeDLXpI1K3/ACMX0nb0D2wZLhP1ZvGNRu0cZBL
jSHVBOIh1WOlhkOPbewUH2N196mognXplz23hMrJyeq6sZTpTBX5fR64WTouEoqHma5GwW7KktQ4
6GUmopNJOFKM/qQUnDUKgwmIXQ9pJCt6zSsNhgRLwPNWFXtb0jhNgF774kusKxBacMQ6SIDMA1Vj
UP00qUG6vMd9H3wKEspyKstmoIhPSIatrwtBqxrj9e6UxMc5Tp+Y7db5++bpnPZrEzr56jr3QiWm
KC6X5Krszj7mWmuyZjz2nGYiQVavoPeNt3FSK1b3/4LXsq6plnjjSIlQ2wkWfHuMy8JcmzPoxQI1
/M8Xgy84ch5voWOZRXe9e6KJf7Yq3+H1ymd6tb0CZs8FYmL3WaFAoTCbFMZRIMllUdgPANhrO7kO
/hsz6O5Sf5pezNH2XsL789mu6BSteD92k1CpgY4sLWreXFrkzLle18YLbUJH9NjnawOPv8Stu36F
OE+2IFoQMl41IGrg7H7iveYMOLhAmrpnnTVnNlTok9l6H9MD4EzFAf9Q5iyjxBCPXhShwOd2DvjT
bZcr96Cl6+DChRotWuxkysx7q/keWYfg76EgF3cCengtGXCmHz0fFX44i0EZPQJcBPYghVybycd3
VE0VHYmcqh7aZ6ITRwbp3FWt+PlysAa19VCiEtvyioc7r0LEg3N5nTkaDMbIYk21E9/2bQkfzYSS
U80W/1cRsdxaVmmOeT78/1AAtI6B4rwsbb6ALOM4Z0haT0ulzDDXSzhT5tZWUqDkLHHbqBzyHPWP
D9ww+qeRjhhFYcAv3bZyStPEnvKx52Af+9+Jth5OcOcZkyezYDRopHMzQwidBqL+Mq3MGnYLTkgv
hk5CnSqL78ifcXcmTS+qVgx4WtMZ3bMe3+FGsz8bu47c5A079UW1VC33ToiYOJ4bR3mjNVKyNw+E
jJCduRBPMVHDdAWgMGD2sOOeFXXW4q+YD7qoCoSmYP2XjgEbW5Maf3X0DVv1NEyCpoBm7vwUhaX5
DIdF0hrprjipTFeVwqAXDU8LgdXTDFsMX5BxNB/BXfl2Pw10QAfrZhYdnopwu5IVa50bc7fFdxzp
TnO2PWky4QMDdpjg4sSWwdrA1sEO2ziAKM6Zn7LHs28NdSkgAqZwSQ37B+mFJ661rp71aTyyJmOl
zi0+MmfDUy7puezINaapgPbcpmFKOWTq4QFQJipQR5Lmu72nmYujMgOVUnoZmO+Npd/+MFpshsgm
eFpSG7z45PqRbZicrGOiT+VUqlHtwF8bueIOzErb6hMZcOitdpVQep2XgFGYWwX8dS9e79v6jCCS
bbc07cacBPZ+x7VUd1l7P8qbCQMZ/t3nEUQ2hXtzLQkEbgj80ETD7Mevotvug6gqVCQ0SYkofN6G
MwD0UthpUpD++olI6jJWBg2V/ovQH/JN3ZIjlXJgSuDCtFDyIbH7IRd3q2Cp7QiZbhnku97EmxA/
qR+U7b7+V+Ep6ERtRPFhxPbeJ4GfddK0zhpquwgou+O5FymJ8eIlm13YX0EeezP5unlL9SNSBcyn
K3VzBTwN8ibMDa6y6y8UNj8UXIVXJXlmqu7T8uJAfJtvWBRF4LilSXKFqOEoJc4DpQOxmQkoy42b
872texpp359AWNhH09AZT0AnlmcpXBIk/cIhFQFsFiOMq2P6EHmlgqVINAyoYdXc/rYVoSEH3PU5
Z1b/XxHBCEFvopnGh7W5qiexaZzZ3Rjc6MrzJIH5H5gFP2BBHSdMBku01c+wLh8+jd7DqaxLcRmR
Qd7/fKd9g4mY7DcEWo0hXNQDTzDpVatIfeYgHhYXYO9oLvV5GkiO1zLreXIQezyUHsLB9r1syvgv
jY/jJzFv8RTl3+ncOvlRl4ONd2OePxBEecaCTXwK3BdQoTnVnC0K7vahx/lsm1xvlPvNrtVh9qmZ
gElwiz6a6J55c1LoLQrUlqVBGgBs3KxoqiSdTR4nkISP8KHHZzAZ22i0mpK/ajDoPWk2OLsIpXeq
6jGi8j5OWhGLlUQOuoO6e5S7GK6W7mC7H8JPWXyiW/V0EdEExmXlHS1stNaexTJYUDHrrBa6LI08
bamb2cgj8/b3kUz5+iQloG09Dhv33edA6nXCV0EgbvOw3jHj7/GukSRwLjPq2aM2W5Asa0w/al22
+eGIDK2n6+o8xKFnby/HxWUxWon1ob9l7ubOJtz8k3N/2fcW4yAzNm9iYB/7LwOBav8R28Q9t+bk
Fg17bm5VcE5Ss8iyzalheK3dujdAQnOydNHuWZ8RXB0mFDVXO4ug5sJQxeHZbCBGhxLCZ7jIygbT
010c9rY5Eh5idS58C1XNJpEMm0Qu0niZMzgW1O1iw+Z0b2WSu57SvGQNET0jAPmC0+nJj+s1sWVR
fQySCbXtRdfxderxCqixBs5N/VRI40EoLG/JsdvppEyQuaV2DZy/FTBF6Dq13R8ZTPpFRedE/YMA
wbM3w2umNhwkxu14xlmgp0ZmgddG2nAAqWZqrDsXWHNSK4SnAcJ+GuDkz/729v5/bI/JJmGu49kT
wWF5C0SxNyUa/Il90Jyja4/a74Fp7c+n3L8QQLHTTSIBz0InKUnK1z2kSLLWb/w5EEhg5VdP8LkF
5v602ns/gqkTaF7um/4VBh9OvOP5CF+qPyVUXVS5zJj9NtarmKPEHJVwA7xBQPUBCwNoJFXSEyvs
eOiPjD7UvZ2hTkyTp36J3kH1SlPS0tKYFprv9YZu5uhOBS+GGZVj3QDrP30YJzDxm9M8Tm0xblMJ
TnGATeTScqKtrFCiOD8QgSAkSN4B1PqYIzNZtifCrRXQhRn4cRHxy6gPTGoPCzjaJXXan6q79Q+b
c2A0XkdKfccTs53h9Dm2/MYs8z1cMuzCpZWvdm+ujdcEiohHHMmYPay6qgqlGdwlen3Qs3/CoZ/4
SrUmCUlUavuh503j562msuRjkpaXOQ/nkmq4L1iYW6PPjva8kshJ+jVOShxlLAZThe3fcl+Pf5Vp
kXFlSr/P16l/HuhDIZIdK8LMrDxWBm9l3svNeQ8gCPwPnEV4UnY2q9lS3t/zSiZmUUxLqj78Vkcy
ddjl0mQI5hlD4o6ZQBXD3RJIH3HAquYSsnq4ZYKuX+y5Cv6DWuWkMfZBCAttp9VeB0D+rMaFrGyF
MHHE+2mcEDyjI35ZXjsNo42X80FLCdmIQbrjbWSUU82fNTmABofVBuJ6JlVY2noWNbfDK/VETgxp
gx9cZ+JNPUHj8LJK61b/8xz/Qx69wckrJXBsx6rYZpzQg11zJs3fiaFhhPLMXN+sgaMz+e0QcZLm
K2XM/leCJ5xzD3vnK3EAsEH3AWoS3t/DeYX7iGZY4+gh7nklOZR7C2qUb90Tj41MC35cKFyJGb7k
Zt0flxrPR177xxBMo64tjcenXBE0NmSoJ59DrXXI0LTGBd+2p9+8e27wXk5c3dhwBfwfmfEAKeGc
1Q4x9bjPbSazS3haGHgDLLuHaJPlMsZKCXzHRR8SuM+yNGEBsgML5gBR0tHSTCm2cbLm+ivuFVuR
ncSBY9q0I+iCgS6K6lAqZ+IUpeYlPh1V5/6ElsSsFul+EvKqNt5Itgd+0OokhJp7MNM8QZOOME43
6qdgAjJ78h665ST6YsVW7px17R2x/IMFjqYLB9V0svTuipRmmRknHdaZN+X0qm3Qtd3D16iZNyuE
FR/3GclgFXLEIqLGf6rj0iGH53Y4pUK9aRH0Wx4oYCcavl5EiQUR0oUrCorlY8QulUUCzRiX3LsI
b5lLSC2UT1OInp0YTBSFY06+EdiT/zguuN+6sk9W62hOXPwieFUSgBr8VWD6vYfAo1r0B+rJ5GGJ
ivcOl/OFNLZp9srKEdVlWpADHj2nld9eFxztj216pWZ/zl+Fgx3Aw/ii6JnACMPjdqRyDkeoOjA2
Y3Slu2AB/tukScn/Fz8ByNI8NSFuBOxd1NqBPVj4JhMGUJzluZoQU9d18yud18H/Uz9tYAw4yqV5
pwTOll+YEOJ408SBHK9tQzjZSpZyiALLYXrJiPJhg6ibnog+CZbXNjaFsEc6v0kt7EC0N5p5ZDOL
XPyYxl57DBxH9c4UfvVWYg7uxrEkQdJFKBeLFCtsTs44U9H1azu/k3bZZvGMSI2BoJ5FswkUnQSy
VlTWiEaSrCEMQSWZIRLQmZF/Lfh6Bgy3SpTWSbAXdRk7UvQM0EQgvje+LaaeBRo6JPeW2Pti9/rA
atnsq6URNNA0UG1fX7grPxCB/nAifF6v26aZvmkxnxWArHRTaKMuQrxQM3a5NI5WOeN5pMxxXVAe
IvEp4DsKI8hBCv91eN8juWMRuAWJIz3AqA96msBlfiBH9IY944okTEIcTqWerAqm+FWe9hj4jCqr
NE30lGMzj6nxmWJkqTaDbsCn0l0h/o5H9TCE2Ba86I/nFeL3tsSZERmy8Vs+cD4lW866YgpRAEda
o8mL6o1p4UhV8HqL+WhLoOeJFIpzYc8kmS7qSQQQmews6LLvpEmYVfKpAGsfUgqsYvrAUhMdRsgd
8CkJZgguaaQdYNqqycPT/znOBZgofDI45VCwi/X89rWbpt/duPU4BGfpzQMNYWC48rmpICHXlBG7
t2LVznhQW/XhP3BefAM83R3bfBW2JspuWvmhuy9OECK5dmt32aSmq3G3DrPiqy4+m67ux7lmArVm
3XQczzwenCHDGasIkQVnKFP0j+wKyQREq3LdEmHrD4stFext42q1xpN9U7m1lYJNL3RpSFchEMJk
a6+/3aZ6v2LY3zPikwBZNfi6/R/plBc9FJVcL7GWTu4Y4fzDqwj65WMTa/HUQiw9MYXboaQTHGyy
zOgBnBu8oCtKTrKSR3/BDGFbIADgkczL/EhQyQyxZJyRPrJScMBTA9ofs7dQFzrLZbbwUjEC0DfW
+6LiZK2HoG50UV3F8IvSmjZy6T8+Q0t3jECNoVkT+U80vhfKYuu+jwG7pe5e/DQ01moajr0+4Vmn
W7j5KXAnAv0yNgVUgQUvL+g8n+Ct9Patmms1XUrqXGgCGSEm0Z+8auU7Qq9pyhMl3s3HZPuWq33X
k92J+TxEWfG3JUIByItFRn8hMPajXEWP2pa0SZNObYRMUAglKK0sHqwl22m1qzJRHoTOMrl5qVzj
pRXFIdDPnZeZq92mABASCvI2tNS1A3Zs9HsAFoy00NR0c/58BEF6+Md+yMmNG7VXDxsNuVUaOfJ2
bhd8z3cISzSotmKxfEu1241TqlydhYZpAqFR0cWOSleqYjArZ3Z7pQGF5cIbeL79a/O8ytpKf0bc
QED1PudzyTc37zNDE+ciq0/KEMT7MepInllPAQ/7PvPFbq9hnb+77vk2dt1xiuTOrWIR+9wfj3Hr
RlukoaZItzboDR8NAMnh6IJLrs4OcDJ7kzjqlX1/AiiSra7yJlYoxlBN3EghqTFmB9EzeH6uzrkK
WXWumV2FZMzDQKBoSziEwQpQ8YytS3U/bEMt8/5HkaHSk8KYKSOTuqBEJ1sFsLNGkZTCbc5VQ64B
A6az8BjrZuoHIoUcCNKl3AwOfiXGbHXTdPYHQn1hpLQvIpxV9nBVo/W1aMsPq74ORH/hiQFPmVct
kDrCuKC+JowyOJJKs90YHVNFJ3eKbYzWre8CUpuRLeX8z0BfedDw5PHcjzWu6h5gMcQ0/sJnsz4N
tnVwqIoSWEN3cpobgK2lC3n+FiDGED5rXs//wyGaU5eEoSKYk+Ha7BDVCl0MNGy1/JOK6eFhEOeu
rw7MJuMbQ86Bgd3eHZqhfj8tIVI/O+oDYnWa/w1Mn6rO7R/SVLu4AMKa+h3StM67UWXSOf+cNodj
zlzwEsEQ0AjorL2yDe0slgm8fEBk/VfszNW3eYosz08n6L5njMXexbL47vN1FI5xMR8DfsdLMZf1
bfGni4R99jarBv6t84k4gxRIPba9jBi6I69V3BIPjdeNWAb/hoc7c0ldyRxo5HFIuFn3auvGD4z5
seBjxPo180nWk+imu7QshoAYwQb9p0QxiR/sLxVHZERqJI0Xf9SngWvmRngE+65W7AK+ezDjgwWp
f40IvTx2kROk6dUfLjrd7hFTmjFU4vYbW3HHnoxCZ1udG9A4LTDxCMnBHbFq2Wufqh3etygYXP24
cFS2ccra9wD0O9BWku+V3YzDaNslF7KRj5vwnDCXDnszO15SQHGJk8uS8XW8TghPnFkG4RADIW8s
gGCj+HyZ9U4o9Q9ncHMIAhPY0LxnMytVPDG7QdDPpMsHLuKH9LJpYO4742OQocnl8EHFw/1tm/El
+kwLZM9LtKr/8WqLqyvPK6igBDgMMEPNfZD7r/A+etwGUZsaxtyzWnvyxpyiGdkekAwCYqHPULF7
8D9Gy/4SzGaoKF/OHslRPraytT+VQheJJd+sZVXXoGZ4/JdqhdTEYaE13/RmplEw1Oz01m0h6HR7
RTnWy6ezVhVhvhpYT/TBCBxQ1SH2ms30OcuTGyAaP5ipBO43akkIoJQR/iwbz382+ho3YrZe/QiN
SL6i8a2oBGoFxGhnLgGTYev1JI2nnz2LF/F8q9uglaM+wzMJaG905fHP1cScIFpOJcmnXFDlVw/e
J3sbUtMjhucIpByfHR2wlvC+0MOR/9HPpjw5vnmiTXaKDSilF0k991XFpPuwNQxZYhw4LCVklCeX
mn/fdE2NbFcX0Kqej+jCIbvimFJmHL4JzcrFiRo3nwtwfssRo0GBC0E0GRfVbx2NxkCe/Outkjc4
3QXcLLtMaxafX6fMLHSLLbSiVjVNqdu7PL+ALx9/Ak8MgY+YtZiS11D5B9U55vaVzCpb1rIqUtDU
U2aC6vctQyd1aAy3IgttcSJRJGJrmcniaewDcrVnwfOEVBonbmLK+RXuQGShvNlljOIibGM+QF1q
R5d+8/1Um568Xei4Xrlb1rI6obOfrVwgARDtHl7jhQtCnIkEL90/M4swCtIWqAik9GAHBBpozVR3
SWKRcpLXMd6+KWaiEjm5QnwyRbMgwtn/HKFr139wqRNKnMe7gxVSJTkdQeaKwcwVT+C3zZRDr25o
uzOVhQHFFzHk0TkoF7lsJlb9XaXC/LflrjnJF1tMcaldR+Pir5ehSC6KmKrHodDc+2QfwjOccvPH
Mc7Xt695k+fO3LOyJ0ncOHoDHgzEVVL8swesHi0In53mSHhQZSUlOo4CFtdzI2p7Nz35VCEkVogp
IU0T0BDadwJySy075XSWtUmBnlPe8TErOI4dR5Jmk3GYjU6CbjOK1LOLUwESn84AP3vifHzYkeUL
TFUc7OqQIVWVuVf+YLmeQI1VyswyfuyQhmSRYI27Ke9kKNDTopU1oSex2jWYG4yc/BWsLXYYP/te
tc47RXMSeMKAYdhfYbocCs0Szgq8hZmwp7dkZgOhdZMOyyhkKOLVc6wpE2xrdjFvLog6VJVWCHub
CEOboYiaQG8kJA+OTFlCj1CeDtbyjzPbCS16m9uOYvHTIQ6VH1VWr8V2gruU+aaIXIafSTOMmjJb
gTDHE4klKG7eHB8nBU7YHDeHrbZ/5TGONjefesuv7CFLysyPfv00ttpLzCQw07I8ndAzeiiLGwO2
gmJBSeAUQ0Ui2CX04OepRlZKdlxcE8qZAprtOmbXbKL9++FhzIN1aTqiCXWIVFEBgvUxwea+lY+I
O+nvRvGT5iN3oNQkBohES236S4amttAj+PB4ptIBtZbKFw1PA4pzxPSRbAeSFjpUlIhev37JRNq1
TQ64yv4fw2Gy3EYW2nw9LDqRfl+lQSV36lSrPOJlpsDR4Cac1SuwXYeVvt2885N+bnWC0Q04MKin
PxVG7WEhfquK16Dmreryae9l2R9RsQmrWq33tf6UNpeYEKzRuNJU3lqpOwXnDyBPQYrPcI7K4sef
WSfxjtTq3oDDz70QhkNCiS97oTvwPIUEsHOHR+ptNi/xX4rOmSLvNH6hMXi83dioDZ/DyRz4Id7K
+A7oQPdxh7MZT82bFmn+mTrCnSE68tkX1K+6rKp42dLMTCmDfZjOwkfYRS9+Y10cE7lFYbHpGOfT
+0JnJ0CKDGD2vSB0TJcnJtDXmNcLZMayzQxG/yHpwGeS8GouKdXqhentVw9Q3L8TBnmIkLSiq82L
40a7PaLjdzO98rLq+2Y6bqCr88TO/75eDrAVJJyLlEhHhdumx/dqNEe1NuHpAya2/XKoLWhDB5m3
95HIojplh91gFcYC1qnrqJa1JI3NtfsOzj4KCTTIy6poW7bi9BJQL7rfolBn97VzpRZO/kiei9qa
dyAjI+MD4mwjEw2TKOKRUu1qN/9Wd1A1Zy9V9sqDnY38cz3EVV0UE/sb7sP79RWmW7d2W8hx+n2B
1d1SjRb1IQObbdl60R2RBF8xmogSMQ2eCiBBLWvtSSgrCrJue55oPmJ8uk0Er6oQ1wJKt9ABh2Pn
9AnorRwTo2Wrp7Z72pI/xHowKprpRvAR3c1GaxevhfernUYt4159aQRTUfqjQoem6rHL0pf03rPO
p/U/g+VUus5IXLIcSyL4xyeFoe+ujodtE+GjnhkxjB+T4ptvfIQWNkbf442b/1hEyTcGAY+GDfe+
nCuW+gJBmu2yrm22VRzQaeC9wEdo+E7kqlt12cers0drJ7apiakn59YvpYrQaZmyGzXaCibrQol6
m82CVpHzZ88yY+bbHLy1N81PxGjmqMLvVHnLPkMFACQZcLplUHReuiPyFwDG+4V4nS7HX4VyHYHE
Nzkn3SJX/1WAYWvwXw00ue6ZubU2Nuy6Ax5vKMsDGxjGHHMv+KJ8YpYnwH1D5ZwF1zvdo+NIiaHZ
8zArw5Nw2Yel1RqmAG4zqS3+wTm/ejHgd0JwZap7GCIX/S0hBU6hFpsaIFFC5/ejedhTEUeS2Y/Y
r43VaTmA8f5AxZpNgBBbICVmlDhV6tIPmN5pfimDOcQI4w0LnTQkpIMNnWY/iwridgov7vH9IhmV
BRftQ3EfP3tcJ7wQWM80sGs2jTEM1o8aa7OFkn5opofDbWB32gg2f6Bz53RemWd+axtGOMIYCFSz
Mf1TrwKY1mbQV/GrwnS3+TsVY9jAGwC/+2OtEM4PMJdnTlG3ygvGYDnVUENQ9MmhVhJ4micnpBFl
5aw8mWkCjTZXYhGJU+N6jxlqA9O2jq/8uUarYd/KfEi4DxU8ceAhbgDpknStkNaCejvlDuOmg3BJ
GYkQ3cGXouQ2+/pk/9HenrumR2jEU8ydNSqlmeVOm2Dnab1+83dLdWjU1EVWqD7WHWEl74Dg2yo4
EwHo3buhduZXc8SlKEydyfgx1aTEvnDJCB77JTqWuoaSz5x67Kr+Soywyk1w9bzLskZgAJhPfXzS
HdnJ/Ip5mDEO+L65iRHYTzZ/lcMUuQ9Gga90oL5N2xSRY1j5BqdiuQjaEAu+xVYyalwkJXDT9Pyv
/qBGlzyZO3ma41BhkRIHyp1T6uGGvCIDIB9NFBsD4tu5JYD82LNDXGQvnsxkY9QX/WiWDVi57xVR
ApfDPgmlGlvKL+H6nHJTaZjUyk96Ihp5NNU59f/i1dlyxmU9oL+WE2sRs6xBNdqK9G7YtGh1FlOp
wECfQR5iGVnlQkjZ9qrwtyGku6yhQ72uuOOtBELPJDrh3TrQO+P9eh0wNlaZSsEKXmerEPheFDN6
4bXkHUunR08D//3fFrbTm6jE4fjZYgUT/4MaeSLbh9c9GzWecjjWSVPhCf7jZpPHoIOfq7vtFPU9
rTga4DxecRb9FLPTbIb6o8/Jeq5t1ESVklOz178KDV2LGfRigy9BxU/JlJPOT9T8PkjA6oJZmlCp
jf21OiCRtoHtpmBcvWh1jCXThUxIcAoWpg1d26Q7nDu7LNDGNmjMdtCu7x4fJysVR1qKxSdSBasS
FvMr9cW2qom1FCUEhV6SMPpswmaI6/KLOCUh9FnC0srZSA3ifa16tx/PS/bUUOqmaaA+x5jHcg7f
2L5zifmJZXz4uksUL6ufk1vK1gpSQHSEV/XNklFUYEw+Gh5tQ3xSboBC6b2g35OtJNEclVriW4g6
gkQlfFNZm8VfaWXiN8oZ6yPrbVU+ADUaSKyMD2cI95g6hu6HUhC+PAtONrEmqOUnwSLGPVCN+v50
kFJQV3k9kJ6AfKx5uolbD4Ni1m8KBXocij79Ix0516T5Ly+sZooZhUuZZzJnMyojSeowQJKY2TvE
+JsNwMxGvI0zskZ3d3BaxUmnyyp+KLVauYJF6bOggycZP3+m5NosQzkOKOhZt5QMkMlq1v5mLow8
Ci5MKpoZ5XAukQM9T6iR+onv6NY1eotb39i9UDD20yYs4PoMom7bFESzvYGsiStcFma1XN83j7GD
hO4rKMvsyIOc+UBvqUQpoyscTF4Binvjl2rWIK9xPI3NB/2xs7RXxJ1gZA+X5ZNc9dlQR39E7qI0
FPJU7b43XGqMZX55bSnAvwW3hCQbC7hsE+Hta9QfrtzF+7LkYHpeNstzZLx1VjvUTQxtDV5YDKGJ
vlEtpptL3rTiDQOXvZBVZrpNE0i+dERhtsxshUY3ckLaVPP4uCjBds3Cxh2QnGhF335+pfAoLy3p
Q2SL+rnED8nY/YOmSnG4zoEpJctOjjx5ZVhPfMV0b4YogaYZHz3Xf9Csv/RBXq55Uf2ImdTdmCJ8
M0nqYxCJm9OPJLgHZgAhRZNyHwJ0+DfXEaPQHcLdxKNOY67kiOlV3ofZM3ICP7cQs2M6jRoqYzsW
swEZlwZbqXzsFzNfVhkLi8n63JLqOfJhKndzFyCiHPxQ/3XAiP2JPxJyFfB6NpTw+IJfgsI0NbEi
fjWFdhMuHf1Lj2QUAccfFgLy+SJWtfs2A7K6L3paciE506rCLD9NNX8XUwjeMXoheBUk0nSK1bqX
eqp5k/kd+e5n1nFX+WUg0cN0XQlTyYSnX3Qzl0NA2SEcckaUrSjF64BkuABJm4+bJ4+9QQaR5DgT
GO5kGPOcymmIrp3EBnJEl6RbQJMPot7miqXN83IVZ3j1sGUjMEZDeTf7ke0q185qjoIGcwTr6pAS
R66kSbHt+QhdOKkt5JC8wSVQ1Uz3y8JN5+xguJHJ0iNuQzRwo8qpFgOtuvB4ny/ac8nygBbEKwlS
5frjlDnVEHnRy7CzXXuy6DQ8BWYeV9qFfw3t+FYIpP13P0vgpZ7fuVS5J2PprHOVoarbcc7nkI3T
QEjiJ9k9Ss6EHQSs9n1QxiiFM9PZgwl4QKEb1r95Qits1LJzvyKQL67Gv0N7QTbh+GoJcOjdfZl8
vSyKJ1IGZTRiO9/MM/ElR5mztwNRKaQvrTuP9/dEn9rrLFCUheaeJz5C3QU57lMKirxy0orPooyo
SPL5sjAGNEaludFkN7/BW/tYZZgj0VYFiWZVBKr+G/fEpky7sjJ5qN2meiTHVLFNeOMo+xqj1o21
dahhCBf4Oko78d1u19/fgxwucEvrmAm88Wc4qzCSvwi8hj3cM/NkaXBlBzwNWxh8NgKokNeNJC4d
ARi3NXtT1mrTZOakbv5sAGx5ioBh3+9h3qbTaE/nzNR3vFo6pmzrpygs+5YiBcIQdcgt316O6fUe
+oaUCKyXM0sXDHMCtIAk1YdValPs2dY4HJo3R1fCgaO+dC5Vm3vYhuyReP0DbEdJD1ZXDT10ina6
fwq/yHkuBojQtwYTqW6OMu7lTXtwSk+GrrJEIDa4mgPq6ilFP3qDH2Ru+MaR1jOrQyCOZV1wa3g1
zqWG04ZXeIf8/eLBSTWyl97ul07cEN3vOtYFBzZd+jpM3xH3Y4ogsTfk4/wZz9YXH+obdUXiuuEa
Iw3q1Z3XZzZ5PkA0mFNfHK+YjA1Mh6PGjNpZ6KU2/9MftUCLHXjRZGGdx4uniUQGMX+6kRj23yj2
SrSgZWM+DQGLuDaEz3lMShPn2qediDzUNFRY+fcw4H3NIuFxLPQhhQwwcacZgyhZadj/8EAya8lY
rwF2QnA2d4+8vZ2CCLBglFqGG7J3Z22CIukBerXu06DrcEWnBSumS/bRuMur3J3hl2kN1E1Q7SWw
vBrCTLIrqEaoNTKDaLytO9VGUwWa7RCmbM+zrcb5kccjRv6MNXILvCQ3qLPoIsR9Q2nt+bmdecvb
7Muni+CpRT1AXt6pbm8fKGfJ4e4xiPQk6jZWdORz7Nr63zwMKOf4bAKpUtUaYQhL5gyyEleYY/0c
mYWf2Vv8O/xu8qDWwr5qB3RznPOKC31pQpRd278pKIzbUzjTu8RxIICpt5d3w30EKwiNcEC7WcVn
m5xLUnZAJPhSwpXMihJoPocFt8oOBvVWPwqiwUIyfTJmWn7EnmbPlf7MkMGVJknnp1ooEvgu/aXb
JaWon+JANK9iOccKe4G2ovlf2bjlYy+W65r4Lq26ywkarfykNKUyMqR5XFJChsw65T5xSaFoTuYA
PtweKLawYKbLoQ4kWOWSAFXLjmy22wJ0/lHoHno/1Tl/zCn4Z4ghDdEJSdujGjFv77vULAfguMHI
BpGWIUKT5LwN5uWkmksJ1/s8be8KM9y2hEixNWLeX47OQjVm7ZfKkZ1ClBGKWYOudishxy0++0Bn
N2D0AWCXLkRKLmEEL4uZlNMg4ikpH4UBFik8/v3ZLJjdURKMvUZ4s1zGXQ4vIHh32ERYED7b8vCi
JIgKr/63Wj3cN1M4ZOeIEHDpsJXeUwurI1MPrymzEN6gCXDwj7IOJcshma+klq3uUiHjyz2PSp/k
wI1YrKVjzOUQHdq706syT1/tjJk8FjhphTs1t7QzjCMNLKMrsrhxi+FOaHUohun7B1yK1l3dEeZu
o+N2SgFkEc0PWlzG2vaEfa87CFDFXvI+iJMnQt0cUEXDbokSLnss2TV366ukNZt7pKKjLcergU/t
aGtkc/NdzvSDo6dVJEjgYZ+qAcVnHw45Sdrxd04y82DjHNc063gMmZkgDIaCH8o0T4mheH4k+dXe
G3bgp5g4L1NORUmVXk3ZMJsrEl+uJmIMgom43FCHMFesMK+tJU5ZQtAJbm35FuaRag/7rE32jMG3
Be/uOoQfg7bMqPUBNyoLg0isKTjHYArylCQOAVtDZS5QJCsnXS1w+4NI5C15+ZyYKYou+orBGVRc
ZHhsVUKz9+P8cCJ4QrbYOhr8VAM9CMZIhntgbUR4P7vRm3rHho/ky9tSY6reRDPwgOgXcu8bSxAC
tVxp0n30uDFu3/w5a6K3qKuwAJ+vARuGa8lMSjhpgQ2Tmp6Q0BefM5UHSGFocSnZR0g+nHoBCvRW
s9A1iwKOt13L9QOy7E9yuXPEdfR1fHdyW2PqxRXe7Ow2awY+e2qt/2tsfd5S2LUJiytZqpjZpe7E
RI+qS7Qcg/PnXlbee6c0n+KdiSHH3heusstYVM1HWQ5/dWKI2dI9GPlRXMal6dDYrA7bnCb0Ospu
O9ysGfgdfdqOYVnfujNA4/R5mr7wlaN9t05rUmNfZLwTXH1NvOh0X4rOcYTve3hPSL8VizaeorV4
YBRfHb4g+thip3K2eBL0jBfEoBTgrY7EVnY/vOWOOgFtqi6eDBSIZv5deRVmsqX9zyX7qi44gZre
mgDqc5PWpFv4t5RQ9o/g5R//GqQZDSPI1oYTDKqaK3wQ/aMKmVp9kwAvPgJ3dnlbUPKGK8is8Tb9
H/yqkUBr11aJ2HV0lU94Abvf2h2XniJgS3JMVsXcJ+K6g1m/JMXYjwpTHgnIEJ1kQjhIzD9o+CEa
Fclsub/4MNI63MDUvdsPj6Q5I0tYt6B1M9PNqlvHDI6IwisU+SevOW2k//UstusVoE4l9p8sJHKQ
EVPnveuyxFtFuf8BL6LZWr3tY0cASPGvtCRDSr3vhQ56L6TzELbwzts6tf76uKL735euzPqYdB8T
63+gbVmUtLTdtNlTKIlM1HMpv8C1NpajKX3kiAsQum5nqkyZd6P9LU3241Ev2VyUQ4VfcEx0WDiD
XMO5QzFnW1aJXFE1WQZPLA+6s6n078SahmnTiLOmxUuEEvWxDzyRPBmh0s/izlwH51xhl/2EI+PF
XPs+aJIAAtxL55HefUdc7z+sNpuzBhVLrd0gH/3wyZeLfIeLQjbwJzTYC2yRFQwvVgF3rF6PUNEH
gVk81+3MaU1vyXbPW7DdCvOTIvtSdG+31D2wE1oyYvVDxuAb+PmZEO2exl3YtpSPrL+eSeAHscU5
gGyC7EgMKPt6+m1vz5qmwIYma/8+vGs1opbQHRiG3CCnyLZ+dUsPkjnQKQIRMCwjD3kJogDVUd0I
dWLtDBuDfM0KAKlaRN4W7NH/p3DJNuzFoGjHNJmyjiwczZSzXj+POvvzX/I8Kxs06oDfEYKXQQl3
e4CIk14q2oXD4zywhViK4HWp9mI1diOWDKCwGCkL8a96bG5sWLmpn6VrgwtpcY3DLQd4ZH0bImLe
HtIPq+pHceuLd41VeIkSF/mehHqLPahjVf0eFzMbD8zOCV8JCIywtAucjoDJc0xbFhOzA0PhyBAY
W4VRefmUXMUBrK0ChaImfoq55/za7a8nebXCJ7Pfjvw6U7LYoE7GQBs2fLxrbMG9ySREoBtRDzkd
yUfAohAh7wBExtaM8m1V9EYv098umDtrjnXCyFbiFaP8Fq13y/3X07kWnWpbFM+VwJs9uolTck5g
fLjIeGZ9JQbH5KkNz/ltaxv5Ktbh3o98CktrCCqFJsdtMobXPwz766FFUIGOQljNV67JJYGiRf4c
5EVei6H+z7Kb71Z2xq0ALqIdti5UKbHZdVdQ/AUAKfDyL7yMleln2YVo4Iek5LCm8AcJUEmyca+0
ePAhbVAlPVgb5yVBQ4zeeF1l7AZW7lXWfytHJwVvX7e8lXZH/Ty16bugBv+H1hriUqDiMBf6glST
dEhSh9ziTbA0TDBFAVZQxB54vOp5ELJuXJKPB8Ba/EW6iO1UuSrhxN2gWW/JDRlKoradEAPopjyC
uBjkzrCsAiWHaHw27yj4/7OaEla7Fb0sd7aSD4NQ12PHedonGFGz3lCL/espRe5HN7fRAbjtuhgm
aGNA7l3oNHqoBpt2jgUVuUE4xf5J3OXHP5h82EabuVweRi7KmBZeVzNvkGx4HYpCgyf/Nx8CUbyA
V93jZIKYjczmbXucF21oXrLnpNLh9qI21KDenmClpFvPSCgr1e2w4plW6cxLO2sv4BzDzYKqdOAr
AygyiVAzrZL7eaTGBuf++zrcrfznqpXp+pcXm0Jp+8d37HJ5JT9AIXBzailrp17u3fInPh3TtbmL
ICltdsJzCIlVAGeazbMM5lRlaLD+D7Cttv/S//mFsXtERPs7A2Jf8b5FjEKX9ccw4xWChxEsytld
EnkWktIRN9S0N5rIX2X/Z0MaDxhZ2d4Ym06exJ1HOX2JauRsuEpdKUPd62/qUBKk5SasJZh4Ce2N
4dQVSnVaWtxUtKYMMmUDabTu3p9za0XzJiPgJu0h3dHcbjhrAgBjz1AEtbHYEJHIPdJNejZqmQpq
h07RychOpo6ObFycYTl17z3cVxXDRKRoG2svaw02Z7qDHiGS5Y80Mkv3M66VfAVMTMUVBHzaUkNH
0X3u4EhB2Odx/wgNji5coHhvnw57YhJMhUspIfqqcX1UjHUYiLeWEwsq9elC5AWqK38iuOicHsaV
EIzsVriDErdx/LQKsbAPydsrQI1SLRR87NwcDYnPuCZT6Qx+FcJS8rm13Pw6XvgH30804ILRU8uv
96LUUYOw43hEXdhmiMCr+kpZcWaH6J5Hpb2UVBbbzmqb8StqffPnZc9LMP30K9dAmQexd9oaw1q6
GPrHaWUCjA21FwbVnQyMpjUTcDWGSY1xXWc3xynRqSjdegljt0Hslq1P9CsnBhfCZ30ONyFuQ7i/
eupXRwbUx7P34vuw7uJQvvMNeKcfi+b3+U/LQwEE1woog0i2XxGdG1N/tI3YHpFCXy+BybErRWI1
uFowlzgaM/GrwKjiGqGBspwEIjOlzFXPESpdgykC3ZOs0smsfDKTd4ifVeEquEOGKi1LrlboAeKn
o7fsgMiAgO2HXclpunaetFOvSygT2Sx48vFlruF0GLDiJixft35+eTzPkaB2In79xxcV6YfPhyrC
NCFZiukvSUaRaKotSySYbnfxEs+jFdQmPdBCncXgQGeObW7L1vN7uVxwFtazASmbqLHayFd/rjvx
P+nKmVVpqVuHRq59dffYfZpYwyC+xk6VRj+9L+NdFheDSA/5fh3VrZ8PNrqF0VtuNV9P+asydNVt
6mEPcODB3IA54s8LsuoxjVYhC0mre8P1efYstY3w9T7F+OGb7KTsL4UuAIKMYPHAWDHOf5qhNR7r
MgTP7k5JH9TuK3drskEscUYqAMlD/J7yvfG9lM9HrrM5ES/43i9u4YMLew5kCpurC+FvJKBqE+bW
KumszayP0ImQC35Fxsm6xQ2FsJi43A+JJvz79sUovZ8Bav2tM2awEPF/qtiKZ8djxDVrWIIE9vmL
K68ArqHrU5HpLoFsepacl34ixeKEuyFRYWYBgg0hGYmxmuxi7i3hSd931V9uKC3KH/cXFj9tpx8m
htbR/A2NjluJrWWYqW4N+IXNOovNDHGTp2Kn8yN2JZUITqboaUO3QZzXvqMcwTcFXBNlUGlUELX7
2PJfKNdyjfMxNX6Y9ROHXAZk0k0jIeethqb1f0ivrF4pZmbb0Ua7U3u6kxLH/MYFYmhadKQmzI9A
ieHtvaYroNihV7wXDp3LGDzITyy7dX6MeVP2f10vHDiEB1ByZ3xVkWXMxk08E/306BD3DR/dhnN3
t3ktz/HUN1cVVvt01lPh3WSBFp+coImss9yuUx5vFma6DvIRUfhdALPL5jZ6L++xlrhlgjkYTY2y
MWKzE8wy/HolHlLS09UZD29cYIMo2YQ9jLP1+17U56RC6wYZcuGd8l8oK4TNXqRWhOPBWDeMMt6X
QuiTl/ZgZOKxvDEUzsrxjg7yj/WnLH1r0hU/ecFk/6cB8pvoe3maTgySB9XVoUiwYgHRigrwEMt8
dDBVJe3e36yuQMp7lbx8sgIlrQtk+SgPaCdcudjq9ta+nAbv/vZdXTwODLU2Z1/zrT0qeky/24Ld
oafRNYWAtI8O1NZn6N6mO6wi29wJy8kMcNm1QebN5/5yEIrs8QeL8iuMzm0dUFqjxsRrSTOwCQwn
YCEAhMKkMf1R4RjYjOt9q/GCBspxCMtCZG5Y/5F+eNXp29OBtfVWESOl1HUIdDQ/pITZo/R3+il/
/tDryr5Uw1c7iKFHlQt2juaZXyMNQmH8zxGj5oPIowgR5d1dzSuAjiR436taU7dMA7Gy7nlSnXzz
umhq+XGtSJYld2t5h5VwlXnjGJmnla1i2cUKlqeAObqBht2nThq4fUYzpwVrPOUDjKowBr+hnWtg
xiIhbU9DpaWmzAFfeOJON5N9Sc+PgdS1gnyZSJSJqE5FlVLpntqAsEHp2DWzNgQM+auooM0/f0ky
HXSnXl3t6gkIzp0BA/wFLDoMOnOG8oqpvSCc3ts5Z4i/13eLb+7qhFtdZF/dTxc6aeqZ8dwb5fdq
7MwU7D2CLGEzynXpHJHn2corwoQ/7Dcj8SNRZ3P3V+GInmOVQGIfPzZh81KIrHB39j06kTnLiIDy
0AYC3QCHNKfm8L0lrc/+5rmpvOzCSQLiW2H/JTVZJpX1LbDS9VW6tZH1eByQPGA2DqLYuIgRtqPY
lFR4ueX2/klVG5H9F7WwkURYOQEtRETA+qm1xgXDhiYL1r8/kHEansQfXcNchXCdMNfJGSJCnI1P
i1nUdM2XVQBIPEEjbfMy8cTZoV8mDYES3vZ4gYZLiQTIms0Oc4P502uR9m1hO3F/ldetSnkUlhlE
Mi0KKwM2Wi1ScQZcDiZJfnWJs4DkQZzTib87wF8Zfamkm6YOpXWnCo9WkyqbOFXrwSYOZ9KsnFpU
vQfiloOMQ8B/DsiZ2ejy5bUXZMYcY3ct6AlQZ3FBb6+25dWAPSI5H1jbYvVfZyVLOAi2R8JkWo+I
QXXtS7zvfgaSBbaJSgPBe5VaudhAkcvo8Yrine992kyo5bgT2pUg050dhhs5N8ywD2VULwfRv8EB
K2m/38wcs4lJhjwcMo3sJ8elNILd19HHY/C/ngi51HMGKD9STD+f+e1Kncptbk2SAzuNulyOXJM0
qmjUtzEb4yjb6aK+49N56SWTUQ0NtO29dPbKJ4gIEy9UTYIlASvBVqzlyOf+cAPGFNWo2UT8YCkR
o3TnlZ3513yzgANHOP493HyHaWv/gskIcycYOMfXJGVI8GPy0/GKOftLjxgzA6jJD9qVGQUAsBca
eHn0iVUZ3mqdMxdP08k6gRNYwshkGveaqF+CgUarTmXLMsqaUdImJehqrgfi0fYI7yIjNexjVVO2
MCJzOdiA1Cco5KvTuJtLRC8FYotzoTQU3d4//65Kxqmwi2KQJNteDPzl2AzB6K0/u2XLwkOwRkU9
b9Y32oTzbS3x/8H9yNb4rDWmuPJQs2/dqXh6kHiaMo5MQXZBX1xt2Yj0xCIPsvuBOoEysL//TPyF
BfU+e4rEkhecKvqPjAm0qxVNgT1DOjY9C5BbUNw35VfFsqLQFlPrEgA0sT8866NQaW1msWpi5Sak
7pUye0+pB8bNg/oW3jGhTyBj/dipYrOY2i5wDLq5eBcPZUhtm/yIEFnOlh+SN6tLYEukX5YRu208
gKj8pQq5ex81VLh109u7YuKBcT/ttz0jDaYdbGofT6nR2iAPNt5Ryn/REB+0dYAULDd2qHmIdc/c
thNBsqfPj1EnxDfyiGSaSpQWpQoRlJr3DMDYUkcPgNa0Me1HtvIdcanFUmsH0R25A7aLWSi31oX1
h92cuifmzgB1nA/ItyBYiwXo+2yUTLzmz4q2RYv0M0Q0OLwsYfS0brWJVQ/mjdoF5KW/6uJiQ4td
Ty6Iro6bqTk9Thexs5Spqtw/ck5KDVjJQrS2/dLLToklNSddnMLP3kuUVqRK2xC1cJMLj4UoRLz1
ABYzWR2Lmk9MVV8KK6mmbMJzCeMPQ1DpucGOy0NtWyjZRghxgKacQCVECMu0ce8jahdYlPrv+Vzx
Y8B+AvmZIlsveu/giSRmVBVDKhDvvHr1ZOB5ioGxbp0gLHguyTJuCGs+gfeItigq/A48jhQ5v9bZ
f1qXN6xXxEtTCi7VaVpdO3an9Rda0Pxs0Gg03WhzQpCxukdoxfaI4egtOn8dL8YveFX7hLwrqWF3
8NGIjS3tSjCK1uHvv6KMv3I2GNv4Br0tdcfMPKMgEtJarm90uanCNCVZbnQigP3w9Bh+nh4zcO3o
ugSR2vit+WezMoOLnehllj/6woMEL7LRSGZz4O4EEx3qrZOkuqdEdc3YBK1TSnbpSCbezVh4h0k+
artske4esVk/7mrO7dABABQfeFFNSgrugnR6EYn3to+e7ugv2PFnURbGLl46VKIq+fMgvUdan0Ph
f8h9V6vzjyAMmdH7AASB/Xa/wDEmwSxG7rn0RwnScaGG/LYXOrz19buv9pHA1/5xPWA5elYVmViK
OO/PaW5Mn9rg6FDrMNlA39vMpnn1OvZidjbs+dgPqrPDErlrcxt98Hg1tUAPQOpQI2SlofYL92GY
MVGfYQDl+KI66M8WzDKL3yl/R3VkRmmwXJudbyjtCu3RCyItQhkdbMUGazp+QD3VBBPjJtAVI1b0
M7zj/g5EEooZyS8OlvzqJl3JL1Hb4BEg9uuJkByC/ArVYL0k9SkovXum//Adqh0jTw4CZwxA3CWT
vawfTFBnxhKTEkFkfxlk2lMoUgvtHwKbt7O9T1Pek6hQpOEBjB8zPAQg5ola74A3lUEJhxaTOIfz
ZK+giutc7MTjwxVeBoxbHIX6k0YTdy38EJ4HZIjd5DX4NjzIeyk8RgJ2D34voriopbDybbtn7RUD
clxKL1GLGKkFev2gtZ38fE8y666xlgePlNqYoBeIZzKP7EmCoSl7acoKls8ylu+y9xWXAx5ZF7xH
rtuVyWXnSD2yWDPabtlepW1ZvgyovD38wK950xe3hjDsB5TdFfZEdhiWL6paNIisgqhrjXY9M/RL
s09lqjI+Pi8vCWDVB7e2+gVS9p0E5b/DuVb3qvaInOlyx9o1wpx5EDd4MPWsy4mJOEhlAI+pr3/D
5zBdRVjXyycNmgTk1IWKSfTGlR0TGU5xnaD6SMTnOGsF3yJpLAPfBN33aCPUxRw1mQJ71XdO17e8
Mdsipzb06oMzTjlA0HTvjXgXX2a5tCUyT6nRDPDsmNaJYDQUsNjtI2z5lkMnqsPuBEZzHjh+1Ael
vn0MYaa3FTmaGT14FmUAh+iyqmudbgDl2RpRWvFVx1KxVsSleOQK67/YU9F0GLOUzXXdc4ilXm3i
D/4JSnm+jYG/ZetkjAEQkLvbd1rrshvbUSZbeOHL5cwpd3Uf/jOnlOvVR7RrhHpls2+2kNx8pcBe
4QW0AD+/jjB5j0QwtAbmcAUXMr8OeqJ2quiyE5y7e4AiR2wJmvi/NlBjf0fhUT+urduayCYtsB56
jH5UncYnGp2on8d2ERYaIiaYXRzhlYGFmx3iVWqmjlpX70pXZFcm/gYQg074+nKvdNeYaD7Q6oIh
Skq+TXeeYVGOWzvoGxOP7Kckkjuq74WckuclFYfUSBJPAsmwu7fbmzrSXS+lvCKW7KUeEONKOOTC
485PfhohrYo0QUasluJWaUptfMjSN4Y8Vy5rp9yKgAf4r+lWcnfalePbKn36A3GaB/E8h53+SMZ0
AJ0x+soaDZOFmHeXIT8hKTUW0mDYs5krcgd/AFMIwNF3N93td86JzA1vpPdRz4YhnP1iEX+pQEvI
CwKexZfxcLRqbE0OjJ0axloHJQ4KsLxi7MLp2xBKCWn5X3cbphJypdztvH/vOwIzswkMLTuF87iB
BHoNMVzOe9lya7OxfWXN0TqDe+wgi65Jg/7iHuA+WhHRT903werlm60Jd3LR4YYxOegEvj8EKhpW
hiv4mHhUnNLASXZXbm/CphOhWzNkVlGPn9qK5S/lS4fEOz6rFJ/a/foO6eKRD1lynIwjw5VpCqD2
0YAkMMfvxoPGJrHJAm3MgyfwCLEKeqim8QdQUI7IXlqrIYU5GdmEqz3Y0HBEuvhbfZZ3Bfvhq6M1
IRPp8+FpxGnLFVJ7BROTHX/rDhaQxi0mkKfFj/oP1vKHOS/S4+QWPtRjHm3jeqYZu8rWBkSRYvJO
k1jo7a8fM9VMSEs5KM/Mt4DnA0utBTrGBEaUelS+UR3stzfGMqaKzbfRAoN5TUBsFQR1CE/+Uqxg
ZBrQc4XIgp5n4lFG8z+jK1aLBhAxWGd7bZs7C2i8wfg2ur998tZ9Ee0aBPOkSqYEU0YO5byr3rfh
wk65euCfFE6oQ5/lG88Fy6ozWah3U4xwBgm7+LOuEOGoUoqwRCQMeCadHvFkgtxFO684flgEEo4Q
MA+sEyx6zEsyOpJa9GhY0QcpEXxGVTqCTeV8P4TuLGkAq2BGGU/59hg0WraCteK7sVf5kVigGThQ
bGanTtNoLzfcp+fWUsJjR+Eayesi7KSr7dTSK0H0QsMFKPHQKecjYQpLNCrKRZWwAlG8K0IMjEYk
dMVxdzt0Sd95WGRZvxumFtgpSEtjprmxLSLCTEi2tzTgOnmmfN7Cs+QvNqp3iAypU26NUGuCxH2S
FqUOCh3sSESWJzh6o/vW8M/EpXzqAYCik1zCTyPkQIZrnT4cz4tuC6fh6mj0rW6DRq5FsO0xFzAK
knwwFqmMAMveVbsfLb/+pFlyiEw+NxNK27tktnKnQOAO9OeBgqpoKvQmo9VIUTtm9jOvJVrcaotQ
xnGrUnd+b5pS7cRfYhtqcPexKX/OIWhg2GF8ao7UbDNjg3O4SwzgrUbDgPkb1T/ABw4qN0i6YsP4
n26K6gMlAaca6fp64+A9jPb6+HI+zmY+h0HN/jB1do3QssKUbW/H5jPw4NcH49s1yqzulhoIAlNw
xo0dvuK76yrJuSAH6hgMLJuwIr6UB3R8Z1jlURkrgN4Z/asu3aTiFA5yTAF4nQEkxXzbcLrZPZWX
nLRPUXML8lW+0QGLWOYwtWKyfxSxhdKp+DZmASxpPqBDPwnonxbgwbZSWVDwBA8ReAxty0yh0WrB
HMZO+E/1RUfqLo/4fY/6rf972oqgT+S4xD9hSpNGZno342sEj8q3HPoLwk6Y3kUuZKscUlCSBFo2
CkRhNyQnnw0YKxsQTqaDDmpifXDM5FcaA3z0zHm+WtNmzZXnZFDz4/WxOf9UhxQ2+v+ZbLTlgOxM
vP8w/0rszWbiRRuNByv5skcN43/y4MsusUM6x2mv/WONwMN8VSGQkDq8+9p/yZ0xIOT6M4eHvIZ4
HauRHwXGZpLANDjudBaUwLzKn4Bzmlo1iZ7q3658bubVhqNZ/3TYumKohGIDOC9YX2TyEmVkUfJy
C9uJbKbv6QGX2H3wO/2dk9mYwhrh6ahRCFVbHgCY4flg+1tUSjHPRZTUnN3dj5BrWzUkSHxO1M/T
UCO9PiSZPclpU2T1TbcScm4WnVd7z+/Mq64yxcf+fVvE2qzD//fhicia8moXgblabRs2eFFZNUCz
C/rr0c4sTH2Fn7kkQDK5/GOgGW1lduD0bxPe94yB9L63PWV78RwAxNWTv5iwr4HPQlGNtKB9df0+
B7Gz7vJcIKzAClKzkDxcZKZQzkIWs0fSdtwagmL1tMO7prxw2OzRADG2mfYn3c6SlwkRYqYRYzuw
iTtxUvM2Ll36YXAMbZVtkwgcVQQHkpphDlfiehN2u6UEUiw9nWBIOmdYjnp8RLNWcMoy3cn38DRH
rXvfaR/V0skk89IJPeOrXi722Tj+/ffTZvFqKERahieQQArMfFA1BUL7fa7RTD+AWHBg22tkH/9P
l4fmHcM+vjdHxit5UyDDZ+ne86aLR5TQOJ8n7H4RXjAKI7Q2FT3hqh6lwqeHOR5I7jqPKUl+ifxk
PVWxSiLqa7njtDv2TBLptzXMYR1mYq/Oi0B8uNRMO1vl+lrlCAknRpCvQoifxwoNWavF4YY+mZVK
fjJOmsVOEfvcmApAmmd92xBLPf5AHOWe33XSzcsNdj6rifrtP+olFzHuby4tCzd4ichRvhrZSSPT
O6NDS1mKYKllSkDXTqN3eVeQOsAme7xLHBFyUNMfZzNlnhial+i53tkVdF8Vqx5f0vTj1o/mlysY
n3cepQ3AU8VxbRfmN1bgzINN1X4eVRNMgqy8PdGYi7A4nPb8YN/sh15WlJI6mfxrddONs9sOAykm
GcgHZk2Qyh8vHmTxdYF5I9OFsy3z0qHzW8+ybJjDC6DpyxfUJ2ibOO5XmKIe5jcrThKGSPtXLrSM
KBEDk2ahBdxWZBk882VT/mtHf9gG1tCT+qtYOXSZrlMWIrpUf23NmIYmGMGqzWggr0UdTopm1CSM
6AY0yBxyhV6/4MF1EHTHmudiwxOZ5JsHXiAUsddAHfDzrwkYgH/az/dQJSYYZ1JTMZjqsaGMkKsn
d6fWiGUyER2UQq4Fa+EQl/prSEyzc+4DntOd48ZpyeLUrkANIKypkodSCAEa4yF7GbGWFC8tIuK1
TkYCd0Y6noOxCZYGm7ksbHHHtD3eT7HMoS/+B4plvSi2/+0oSL3KLUUqsqJJ97LBV49MLrrQ0mpk
cSYI8JRFhwEjK1o6pfQqOehWlftvkVNnc2EUPpnGWQ5w2LJnUiQ3pScRF3IhTcsM+g9pKy5MqSit
SLn5WcYxpnoqc40cAfoCdYexFtmB8jEH54cry7GU+QRfRn/l1BhRwJjiTcOthjV4L0hLcLIPgbE4
a8le96nlzGHbmfT+lnqY8axfMC/rFX4Rs07xFQ/NLVrJSyeWEthemFhRv0tTcE54uj46ByEsSj4E
gAWMxu3pOJLc7FlxX1WfO7X4SaHT3LriaaXd7y27166WpLo1Wo8X/kNZnsoG+lkBr8bucwWjhgsQ
hfI2EzbMsqPk56gRnSlrUlHLaN6/jJ4uPAKUy8+itLlNw8tB9tvJQjbYWMymR2n9WWZYUHD+2gF6
LTM8sGgBuyiap0xN1BVdpdQWaUYWSh5daUHuZVYrpzuedN+f/xzVKAFzU3t9bYcPuCWE4NpQwJ9X
8RFbUNNLRd/wZyXsQYfl5gW4xSGdzvYZb1E8EbU7xUD3HhaZVAvZpMZJTr2Ng1+8HPy5uAqZ5h/G
iTALZphhMDiZ5A6x4Ie1Jm+RlRCGT+UdpUSpn57M4shlFCq25pZG0p8ZPWxyl2WjhdFPbn+4BtLx
tCRCzHUcaBU54VpAColIJgeYRb822+IZMTjYT6KgiWBoHbHdrPEed9sBefQtDZ5rS9xBJo+kHCcr
MCKCBY65qVuDtG/toAclQZzu0hrp7m0NTgyLpe7UaIGS+0MNMqyrm0SAsr47edhuwG5Gq4LVpHGS
ymLGS8BhR7IE5GeDwuBt5DdN1oEP291NUSJG+KNJwDdeNREenBsSDCVHwPRV6Y+M+hgD2b5+X/SD
cVVHY1FixZE9macDlROKRvsqiEqvfJ5nEr6CfDlnLSTr9ZXI/INzigtyHNUFkVZGVb7xUlLSN1ly
HoFUIT6Xdy8gm5kS/xXVnsE6M/QfujJf85EfSu5/PVg7HG+ARS6mb/Q44FyHrzQtS9Ud8ou09ees
cAZLk8fD6ExOAnJYwjUvAdWMHiCBw3hUgN0wTRrWQFQWypuNWF2heT2SpFIMqpASPnrni5mlNr6c
MMqQRPoQl1o9dehh9uPv5L9WukQYlBMjVpRY5/+aKrP6SWH3qOHxSoTYyEE0VfbxnsBNkkNdV4Oy
zklKev7LxdfJyUhvBawF0AjDRW19t38TfsMrPwZvzUGST2MqFgchGOVrP/+YW5z6+MmPUfeS63g7
CjB77Q3xmyCjqkRfw4q4P5VfrkXebprv/zg9KvBU2nve4KK2GXfTpjyx1elAsKufOsFYWPQ6v559
4cLW1fJ8QWatr2P/olPdl0X01ppdDbaT19LUH+woVjYGBfj+lOXXJ2LL7F8NEAwgz+R19XKbt9ss
QsqPUVjUn2uaWA4UqVnQKlU7tlqqzgSV/qTkfnDIgmDniIaali2jx8oqykXRc1QV15VgdbLDVRTg
7MKFAM2CL6eF7F+E4Bj6NKd/GwBpGFOsgA7fLl59FCLT+s957jYbvx9OGaf+sq6rIjpmFD2VIWJe
3m/7VQWlgfkRRtAjVHuJB13bRUzGd1JNrzkBrrCrzo8jAnufP1u2O2LJVZY11Wm29XKYhlB8ss80
H4jviq75EiG6ohBILXOyWfOm6qO4YhSRIaNN4WrT5B+uuwgnqp2j5NARZwYES3y9ii/bVaQYBr+8
qMrh7LHBClXXJhUDpORT9mTPggfIJJa388NnlG4I19F0ou/ykhrPLcC0KSuu90B3+ddp/hV7tY2n
dHZ877rYSKGbfiz572jY3BWAqg21NNASxG/k/3iiTC96/3iueebwKTRglmjaJleZSvZVH26JPU9x
Xxow8Vzr92RYDIjM1Cxxf0FUE8kD4/fPBUQhUZi7CUe7ylCPEipuueXcYUFvp6vOdlX19RGJxcnK
AJ3xPpnWW7BVWOmFiR9sNU46J70oSNksslVKKzLz8bmRakCWIPVJZAEHJULXxgqyElbD1PjKzEpF
INFPs/nWPckn1Rx6HKrct+jso2a5U7oin0bb2H2yPBj3xJ+eoIvoArOfiHHfCuW6+SS0QC2r7fuF
a7vClTZvnMuHs1sQeWrKfufiLdMcwz8wkHH8C+hr4/Eze9KdY9h3osdCIJRt2JN6AXRpo9NuAZ5+
hML4K5Dra3PkTHuLvYtqGY/88Ex60UPdn/dhFe11Wt9fd03vU0M3n+e93qQyUnbxJ7yKHP52bT1m
bneKA15WG7H9NcShxpkwI1xmFsvo31KAOSJri6u2PkTyP9B9pdius3ekeMp7YcuwrNtqjzoboNX4
NNihHvcW0eLrj16YwPZCn/f3CqaSYPAK2TB5iqfSqesKtHWc9iED5vaByIVPhbk+Yjjc/+ufq/BH
ZDBqZ0y6OeG9gKrYjGQX/RL4NBLvroN6F8vYkeVEqrxRftotvpQ67DmP8SSd+Lj6SduFoXbX7y0V
rm6unBvFqKSwSlVoZHnjJJvZkJspg7VONaaSHTlztOImhdUB4O7mAv60gltL611mZ3KXqPZOS3+O
8/eNjoXmIyWyaYxoI0kC/CKad1WFC1p/HT4awSIwOY+P9BM/H0uFaA62xT1lrBNBz+ZjPazvKqGC
KB3AOvAaGypzgf7/tKH6cPUiSkEO+4ZiF+HHu0N+/5S/UC/ViaVvqEk8wL49a+b33a4kih+5x+nl
kYUcLw+HCM7nP4RJiv74UwazJvtTUdyKzMyflLZkcteGO/OmKMNvXPjJk9nW/Z8t5FES493DkRgO
9AFu7gXPaAkoJrcqvBxLQ28fCcPhE3EsneHNDKJXgbqho/s1Fz7RuRNDi4OJRvY9ZjmXOW9KRLwo
q5Uck1ASjgvx/gb5U02Xn9h6usyJSArYG57udkoQuaWrhIFGqSKSN+zcx7OrX6F+WvdO6ooKGagE
thv8DIMuTMKdMLnnEQL+JI3YqlLfEujb1ikUXBNh7mL9MGFM56KZshS8KFDEuIGP+nTYZrra5wP0
5XRgQyD2IgOMeavOvjsDRHV0pNf/YD5Qvu1FAp/MFCvXW5N5khCvQBzWAT+OKc0QqStpTK6m6GqF
7Qz9ANk6PlLg0FNRERTPZyooRDLZ5q59LaJqnJmcpL3N1qHjdRrq9PK5ra8U0c2juR7Fjf7KgSV5
fYzr/md20r/U8GytI7C6DBn88Z5GDLWtQ1ucNsHP3ToSXc9vI0BV+GaRX9CII7TAGkIBpt5KL8Bg
hzGliOvzRs0itUmw0McbjMGP3AV1gP3+TAI4dKRfualkmFauSWuz7ijs8upYG82tHpFkz4Uf9E2w
enVL01bcuwkQuy/uWtltotn8tI29IAxw/xebkUbH6ZkQjYRTbgqoIDvCWHHjIQ8HtLIDeoB5yTSD
mjYJQq6Ieg7CRcnHZaaDjXrG+Vgw4rHazDCfaE/nx/GW8YaV+I+u/enwxT6zV8tdSyDzZ5dDsy9c
bKc5SFRGeoqHPCoX11BDnsNg5aBBdDuLp8Wi6PXvm92phEXvwaXnaZY/yIUfxAFOBXd47i9bu4os
mU4Hy6Jg382IYbDalmPvZ4v6ZuxfCB4lSsX83dtJ51QkoaJfPu/B/p0qoguqdRovb1eG7b7Kb6Pl
Ocac/qXlfPWG+IYE65nfVn6tQ1/DtTY+idBALu7u4yaAH1Ln5B3HyRsW5TIp8T3IJrIL6HAYEb80
32c6ef3Tyr3+/67dDC9qENr2Kz/uGDZS6kPSs7QPkwRZzE25jVvuxm1AA7AUTEPJ2yYL1RRGUgCB
OZFEVAmM49ENUL5mokXDRZeVHct1ASXkhFrlxbL9wnpX3cJm+ZOMHZwAZGYFu+5ZeR7K6fOqFVs8
/B//iMaDDFHXRZJowjgjyrbEEdN4kxCbnWNNpLAvD2rGf5ICF6VMgDBY+2lTfScQExIFRR3Uyrdp
WpwwqlPnWPfTPFtanWcac7evZYbcVbw1XZ6sfkwxAvClWlDaR4mN7L8nCKqL6eIuhOI1lfGRaXEp
0fwSlr5GNDBaMt7OKZ31Xcd0AS9G1mp2YnILFLV5JDi/eU6lFdfpn8RYaYb46qrPnyZ0kAX9+4TH
/MVdyDy0Egpzd5fzQEYRLKEElsgRmyMxwBwOar06qRDnTMbTnwXv/ZshSOcREw47dSuEDNHz3e3h
leqOR3SQBwEfsiFcnKG9LUAgm0Dyl41FnYsYUUanZ+nLd952YmeV/ovAO3oFYATQxswSob64Zl+5
qcHZO/gDbd9+K7p0cA2ppsQPSQwKsuYp+uOki1wtHsDtTy8Feq+Yg4R0HKekNjmULSqImC5idzJN
W1xN+KGfD2qgyCI3iVefd0A1U4LJrn3SdbttiUqLsJ+XBPvPujBXFGuWMlkelEjOVFmmcEgyOr23
IDEEEJjQM0cnZ6WDCVDjN0ouB05GBq4iMMYFe3e2GzkL/hH53p1eSDBCOyp7JE/qndsGrKRnSYcX
leDODwiXFC8cpdZZWbx1koeZ39vgt54rVS2D72oBwSOWjwUAcML4IyI3wTYkxXC7sKQi3G1pZxjw
OptY8kNCFXp3ObK81d7MEDxCx7EgHyBEXHkou6/himXiGU/rIwPEhyRMQlmjswqTrlQIUGWByj/S
c3IgUgwfQRnJPjQJbT2FBqnLb4Sj15cM982/XNihnKbO4Uh2jc4ZdThElr73qNqB3K12jO9ASLZD
E5N/kfOWPVf5XtZ+27d58WdDNYoD2BJRvjnKUjYENIZl293mVOC5AS46qQ71gztm1TT8BBuoxJr/
icHIHKmyG5yozyo4PW8gy66kBgnxp5LGVgc41mnvbzsss25YYUD5HiaX5difXuLdBzaSnTeJxSdk
4KHRVJfKTM45hg90QiK3aheWdN+u+SeQbrzD3IdzKh2APdMrbdNA6KBL4NB6qxvTtkHa+cxUhqK8
v/dxp2bJJMVhV08Zu3X2kYNodw7BWlkwykMTXJJbBBMIlED5LJOe12+lM70YvJoAmIOrZg9MgQ2L
rn1as6IC44brdJDrsblB6wwmEdlapd/7rEGr8laefFU/1nsufuNM4C7XT/kJ2pmNssqHIo43MN4q
0O5znmhoPpWwIEHVEsIy4MI5my/qulDA1Cp5/wFbo53y/aO/ah77dAeuF+Upo8TJs548zEG7FIx7
m2kb/inbSiOovE2Jsk1fiPB9NhZz20a7+Z57eYYCjxS5QREiJuaGWPjFQuL29J1RvfNFs3M+nGrd
A+M40blI+vtjMkw6RKvuvOMoHcG4fhONFDa/Eg5h87UbJG1WXpK0Q3BE88wCqhqwG4jtNMp+IOeN
MuV4V30N9qVt7MxE+CsX0kNac1FyZZksGy7JqhJh+5YebAFkGuyudfESGq+vDn/z0VABklVXRXsD
vhU68A5X5heNw3mpeoSQDL9sG8QxQneQ67d6riFM4r+CQUnLuaa7dkv5Fz7SWq4QpWf/ZOZmn+U7
sQ0Cdi6PZmDK8PZNakSkOmua73IeZ6KFI6R1aQkCjs/ge3UY9PB5X5d8demuWZ94ZxRJo10azKWW
PAL8Mx3nt+iNDofk8Nx8ibDJxBZTYBLOnFjGDzQNoyqeWmKhnwA8mYODeQUjg7LqQHVm2SGgm7XN
KjkvSHb2n/eei6o4zWfqeG5FcHjAe4SsBnkiraMJazVfjLgX60HOMBLSNbGs7/vPQnK+jvt8u60Z
zXSqaL84OtV7UKVdVtL9BtZk5LSbHGeEzZccI4nw4S2SUc3B6V8e4tdQNqXr2u2A8/wYgpq9ZfKh
JaQModrreiG/R1UeNIf5unOgXI3Nr9GoyEq0qUuMDKnBN6HUrIJCwkMQQIhA0x70497JxpRTfiMA
ZAPGuPiZyD8cu5rlPN+iqApHjmE4a5+ohbpIZ3dObT/01srCN2lox1DYKZQG6KA6KTiu1jhM0WXs
kDfh5vPPHElcPNhvLjN36U1RT9IibMl1dV3Cj0odynZLDGKE3nZ/Q5RXC7FXHhgvpqTAdezlpas7
xlniGoWrDhD4C5lIClAQcQoX2qk8UNxGFaCdIFdIZ4r2iQf3Nwf/xuFxq4yNEZPtcjnyBmy+hsX3
fpnL8UYBj9nTG57PFEiRYAk4gnBx9qEA15AgtfEM19IEJlyEkhAz9BonjEGhlZQO8w8sI7VIGKoh
kRQ8q7/dCVCOIo/h9y+Kw79v3Ajbrm8hYiK1dm+P04+b9LIg6q2rEpO+ql9xdSxUxtemPXzvJdoa
DhGtsoaul1ZswufKK05ZImIxFLV9/nkBbaUjCul/r+T7Wti58uWTvL+ttOaBnTq06Zy1s1/xHyWm
/ZsKCNmvj2TrPZ47wKcNmUEyjb/JMB9vqxdXhGfrhO7kjhJxSaIMJCS2GMr928mX5LS9eUEAU0Zl
EXTontz1UwVrnVvOcaFLMXvE1tg40t9DXDBd61Cb7XDgWoOLo2wpNyZ/9MbDSC1MQrzczP+Oeeis
Bliji1xrVC32jKJfKWg049+ApeJApOxhEfICraEje17I0qHf5znuxRbn7Dm9M7nKciNH1WgSUlOs
SkT5Cobv6O6dF8wzDfjY2zA5C5MylSnFjKTHkiBBC5tPr6b2IWVpsC2oKs+mD0HeBr+Wk3ffBEbX
6TkGOJwXvg1IoDmYFX3/tkW7ARPP47a6U4N4uBob56LJ5NKUsL/+T4FAh8cD34EreqlvU6TG78AR
KdC5uvoNjxeMh0Iv9nsdExBtXTcGhzJpcN3plr4iQZwBqBuKjBeHhjy67yvVtHxJpyAOIR3I9KAb
xC9aCqSJ7HxIS7U+VRHy/Agp7xI3hmz4q3/vd+XIr3eDwAWPgmZKfP4JFn8ZwtzNeDQaC6k+ABaL
phTrgD41EwhyAqA8ieQwMCCKd4ABmXRFpg6aav1chrKcpwMIzWWB4Dom/vSFD+8WOGWJqMk8lQxP
yf6Dyd164HbtPFshU8VfYHMVbsEEEKtN6xIwHWje8e9MsVru5sP76MFG0i9poOa71zfVhMfHgLmH
NsOsrCv7yRw6q/ZeKmlTfsI4yofllj4wKKEk+ZAvBxkYbQ4YZKe3ZNaFfyZrAmXWhEsXc1Crn7JF
x7FyxSpiXtILGOzH/sAYrsvO8p0lyG/oWTLpHG7aHz+GarHOWT/cqvSK0o0C4MiA5CXe37tzJyuD
F+NhF28pIYq7uz8oEpJL4KshDIu+65AJSMc5gfJYieP8PBQjBzMFPfEbKwg7Mkv8SteS1wS9wnOM
VOy09I5zhWEmTkDiZZGMLAxaWUUSkk6AOudNuJaQ6ADBLj0Nv2nMUAghF32ZrYjJx7X8DvpyLExM
NyUdZdFN/sIS+nYsWL4BrmYT+Ykh8Pg+/dVqIO+ebyQpYqkJXDx1W/KvByksfDgLOOG7cbY+z8HT
ZZZxBzAdLt8XjIzV2bHeQUxTyEY9EFUNE61Bd6M2W8IedPVS+/b4ByazgjGiCP5gSWoB/e5YGqgX
QcWVgDne+pTfbWl8YBFrQPUfSwxfQ4gNRLNh9RsxxpbTwgw2pmGzbLLMGVqO3Xu5lZHrypVf1tgc
/PoJBjNEy3AL8mAF8n/cEZIukHjtICvKgGhWNZxLoQ107XqgUCxRL6b4cMC1Rn8Du0LvQmKdF9cm
UteKwOGZkumYo/OuhNX0O5yY266ivC74Jjgl2C/FSN6Z5JjdDK2ly7YwGHQaSou2d69jwR+CuVcG
HFpT+b48DOZdYDqA9pGARss+xskjRWr0U/wF8TZA8N9ekpudGz0qDIPm3BIHCDVi37lhniXORU+P
VPSup8J8DNLbqHG7US+ym+E3DmMVwsI+x/y/d/8yY43mAPeV1hAMddQAE0UMDf5d8Dqn55vTAHQ5
ykKgaOjeLeqq/eeY4uTa03hnsSHcNN+OJxxAVz7qlJhHkO6fUlTHk2riPr2UUlBtsjK+roj5NHOh
HUXSh4hgzBENRtwInfF1hwn2d9SULjQApqX9y61BNHvWT3OuGPkMZOd/BYAQ4dKEU7SogknfgvBB
O3tjMX1v7s/hS/gRbsyvbnXG3VjN+vkF8GadUHC5gUiOM+JLbiHy889ij1aEHgTyYmwaMPHIf/5N
+2tKEY+Wanmq5GJmeMPR9YPsv/DOGAmOI3ALr3NBct4ME7hwfw6W2MIrqWP39sIVQJ6py9EyZ2NM
yGsugBmXoy/Ilq43DMk/jJUKH8I9v2IxloKhS13a5VjNPjLyPuqrSDT5MJDwtz2PunfuV8Npuo6C
EA06CLh8VxSynFqpQQ/qNCIwUfsk39cqIIqNuuLrqoG0zfSE/J6JwJjHMdpH/MyEkkMDtnEYTXvn
Ah+lYFtz3tND/xWG008II+Kj5/9XJZaUdbzGV0UpM2ESlUbR4B35b0G+0ToZIq1lgVY4asCkgXwW
SbdBfF2FO6yGzKMzHhvOp4pBGZZ8zfKP75NUUxzwPkyit+g+2LJSzR1iqVqbk/2Ndc07buc63BoF
sMc+PIAJDV5kFQCDBaocwo2AQslZu6xA6z6u655b8wJiiLCD/d7Iji2zsuiXma8iYjYjJOw+59hB
peyY0Ikn8pmPhEFVLPoN/pr7FIgxyAnqkBGwAE/yZpa0E1yuvrV8ejMpRpfYNaYIDvIKLvrYMdUQ
LNK4x+ZMjYfExF1aZJ8fxwPd3HiUt96gcAbyjoxqcts22qtjbpTKrMy7UJwXR2Z2oj3qX0wD/Wnx
MCZ+Ix67Q+IJC5h+qnJ+e+Rp3YP327PPmGe3EJA5Fzr0nmUJlAUiBTOPCRf9stvpwrZqxZE3Qgaq
jzPNe3sNMAmd5d/tv8q5yvlJhI5LHOLLYPdIfxmQOeD8jPOn6ms7UOKG1cxGe4j35Y7b8ekaGbuA
I0Y6CJzitfy6n+yGBeyIsfv9ovlk8JgQoYl3SuZw/3uMIWTFWPyXP5gCTECL9AzECbOrhEzODjPx
Wu+0xnwNCQrfiIKkKTyCu/KzhsZrwsNPoM8MU8ltW2sPwLp4WYOiYS0/KGebVQ64q4P116Wh8J7p
njIWEY8MtoN8N3UqEt1zAIh8Z9VYD/3m6ilIdklRj0RCpldeCgsWLqpAXbNHeFt+EXRTDHhqoOZP
To8avHLOgULm4haYYgZOK0lNXErwV4E1EOAqD5t4h7bvOhXwCXF5UPtmABP5QW8KadI6yOmIp0SY
cVrYG3iDpVkfa2u/abYVbcW55R7u2TKLyu45WgL8p56hmoEGsGAz8qGnn/LstkOKRiiqh1PuOnxZ
WUN3kEy7BHHXDzNJM3PKrmNNVD5LiDag0eh3QfOIGvKSN0LBRZmnshoqalBH+OQoCk5hz9VtK5an
LoUBGeWL8dus4ndEEIgt0oMQFosXr7Yzz/rlo+xoV911uTPgvPFnjQ+HNJMYC6hdv/SAqrxAuOFD
9N7rJP4/tmBysOJ0la8Lvcdq5GTrZcLtXhd2E6B1+GtrLLbjA2yuU4fz/0QIXIuGe5Fqzd+sPnHw
dvMUXsnBAjfCrYpg/WCNM/SW6aU5NFjpcA0HX5YJDiaq5u9IVuOaUdlv1I4FkQHyJOkwXVz4+zGm
H9QRdVLfZUzgpetSPYp1qQgex9hsK67v6EZsO8KHOOu8RuYD2hJ8uvbKT36pG7/4KIv1T7ecgm92
J9AALTVgfc4JAzbw9tMpH465CKadCtD3QSdEsn2WH2+45YtF3obleslD2K6BL4Nub61XnrjWbUYh
OzGi//50aPoHEe7+oeCGVNxiRzd7mb50u1Nq7QcxJxMmHCBBUu3IVW8KqDjwphsuH6kLXLojIKaQ
Ih5LHbzP2Bl0Ec302zM3/0BBeK/0YR81THM5UXbi6OqPAp5CdOG3BbijJUsk1EvlXAtkxMzOFkz/
T/6R1tANOsKjruycxvLP/kxaBkOVCo0ClHWa4Na/gJrxLwByI3C8cPPK7qL0Owpq0ppgfirtvK/t
Rf9RVL4cCuHzSaReayIct8OppxHu9WyTvZH7xID8+QGkODRYU8AvXRDSddtJOznmmPt5vWnS9VZf
KsL5SJZQ+G8Nxn554lHadWd3A5Gh+9tKB5ZkrSypH0egize3ui/7eT9SXA+vKgAh/90Seggb+PBb
QrSNc4rwQF4Gg2pNSL01qwBJPPgfaQVFfDW740lG9Oxbc6Q03HACh5JmL0MX+J72zKJjI8u/4ZPn
py/7tZzbhhVTybMagcVUw81dl/oOrxG6GS3cHyiGAa9/4hD+GTCp3DhBofqeb0RVgXCpGoe+IXbK
evCHOr6b3HPtKm86jJeFutEH3oNf1sTAh+ppaOrusToL1z2+wrDGYK4/6VL+68CqSqycsAkXGGgP
jqJreWVRL5oqNFfQi8cOy+ZqY4P1Ft/mqwhY+qyPGVEfIwJmOYzB02Lh4tnyP1BnyBExBRz/Owzh
OPEGbQ8MsMut2RvbPT6IYBkmoclvcm67WNvwzSIxh7v8rfFbxNOI+BfEpy69056dG4klTHnb8JZ3
SskIJcCwA4Qk2otQq9skBDR0Mi3oN3V6O/kg39r2MDKd9nketqblI3onuKfy9boChYTIJFmNBLBL
BgPROuVqqyW6Wj5jZupsKpYMgibZ4jNMtQ1V9nIPuwGduuk7Rj4rrTKjv5pNWQedqpZZ6nttMdZP
kngF37xgsvzk/bWkBwcLkoTVtWy/V8Vm+G16HYiW3zS8Q02Vj/oZV1dQWLTSdc0wqNGPh8K2EHs/
A9ccyPXjnnAU57EmtG3Htfdq0PSy5bWCSfVlPhKsCYV6x1EaHYqk/zodoOJTBvLetRUjuC5iC8Gz
hahxMpUFXLkOpeUjnBw0p3j3+TYTM7NIAWFtT0Wdx1M48b/ER8FvIHKU/oP2jl+javpUjoQOY4MT
3qqN4q1QZ1ewZ9X4C9FNPj3/uZMTvQHQ/kmElNnX3+gkc6DbDT3CqSX/4Xk5WhxpI+xPRJAqUD4P
rIh2WqqlX9sd6giSYkLJxdXppbo3HRLgLB7IRDNFl2H6Gn4UYhqfqyvYPyK1SFHVhegoWIhA9Esy
wNC9w2es0LTKBx67dVgHJpfqJWTNQjiIa662Fwa/sXWQVOzblOQVxmplHH+MM2JIqCRaEaou2gH2
xK8XvmteI/SvnN5zg4E2xb34FCsNWuJDFVHd0SOck8vdxUBwZ/KGSOwMfXPXKDOfIXX0mek6yxWk
JjKn8/KCr0R3+EU2O8QM3A/oievv6TzKZfuukecqJ3F1QOIodBqMYsojN2DZBFNd+HoTwhEj02Ni
Cop/lu40EtlZG7abfUkRnYzxBGpC8dNsQfP1CuFnsniYJRSfyEbGED9IF7QjPnCveJn/x2BRQO51
CWEtg8kshKtfSWfLyoKN+ZxzXWazvxHmvdEUECzbuV7Wn1ZsKj2qPkeSIeipKX0MkiQMVuCJmiFS
OINwZZUX1N3FVsCIX0YfMzlk5paiHzuNX+stVXIRLTd14Ss9YcOaTZcuhdHleKz7WNlbba9E5UtP
CAlnHjqZ+PcvgG7uJkG8hbEIXOQefmpufF7+z7c8A9mD+axA6mwEv8BVEyI37uAygvRkYKF8aKAF
BR9jZqAB0bRuP6WD5Fi0/6MtR6/2Rv8flkiQwYf0bEBxMWuatXZJRBvVLdJw4Pid93VEVMPHfgyf
Iv5bi6fuKyzP2cMruVPlJXITtczg2VcJqiUQ3DIWM1GgQLr5pwDqLlfQY6wPEPtytg7Q8eXEWfpc
EvqSJGlwu+9Oiw1qSBpz2xKxUoORdwTiGbsB0HeF1rDzwE74toRs+WdDc1RwC8RNewipVcSHdbhL
UMYRM54QC4AARPDQKYg65vRpyPbbccvnZBdv87ZYdv/tvKH+DO3ckDr0XPe9Q4X2+g9NUZA65vZH
qVHdlD9ZzCxrqFbiLO3bhIY+Mzuj9MpU/uYwvLQmsfVNz9BiIT/J3EBbR6FpZ/eJerUEUIMQGg2s
/zvi4/gTIgVkcPLIGYsKcf28zw3IQCBaVP468ByTDhK1EZhqu2MVH5C+JXKQNhuwgAZt+nfQ7lVI
qoQv4VYkhPoZOFf6iJJiq5s9e0SIo8IvfFvJdM9pdRAL/imO3042VPa2f2dGKg3uQDwHjr0ZztHa
hxLoSdPBBQmB94BGdBdjBVxQ0Nq/UGsP7TU62YBuPFaQ+IzdvHb6MzGrwBiXNPjVAjgN2RGoxJKS
tYfjM3LCeDSyNRZyauLFVLF9qgiCvExjRUo/3gPE9La3KyvlEUkEBzvA2KHePtIlOypdtLPtCmBb
qHmfnSA7pXJJOJxKypWFSxB8ui5oQv774wgo1moHYtbZt3o57dUZtXXkg8gXKdWZY5d75OWs60BC
5+K6vHD59qsdkgeiShYmvFe4MXT0L221hC/y7bjahQffgjuMmMA1z+ielmMFJZSneyGONlSqUQnD
oDWF3B8QyebfLNCq6Eq9GwQDgBtCeeyLBHhXmJ/0y0LaRyFnn4jnNtwa1lA1m9HwfupK22JqlWem
YRzSN1M3R/gneDNwxt1dkItD7skV/CVoE+LjnBCX+Z/V0Odhbyx9mMWlgk6RUgCSuZFkbT1qzJrw
r1jVX3i5U04itrV1sgiHNt6Of+Ge7XGqGtLifQbYKOX4UGcPYORczdziMDY0JVynnhBbZieq3FYq
OMBOsGkIwiP3Orj7EyU3u6KcLe0Dna05DHreHMxqOaJGdC3XXB42sVxCRncsDXAZaz+GAc1yS7n6
M8aOU/vMqiVIG0OpJATE0FsYrrx1CWSEk1IRx6GVQczeRJjDSGvkBDDepJdNz74JtWLhfZOz+Rld
8ROWcGTnnbBgYNO+DGuilAKi51CS6OptrvQ3MLVgXUP6/RzLMkGrdwKqLDuyx75wzMaTOs0iTSrv
JbdnJOy7YoZuxmjsCYHkiwE3kzUi37cM7L0BleeSI2muMWQvnyleDLufmDftnd2epYxmLMFYmPvE
C9YMw14FsQg5BRuMPEZnriDlGA1FnAZYh63pkqGYemJmng2SUSaAbI7cVRwvAZpYUROnPW4dWMGi
M9hVAphiEDt1/BluSdr1UAu9+O5ZXfaBytFVvQN1WKknA3zEh6V6iDElBvOEK5N8sXuqxFqPYG+8
Vu1I9uigTBkjZ168z7YPzNFciPksmrjtAiPDCr3G+Y0QyOxNaarESwz+6188h6PCWgLFn5B3Nn5p
3na0C+IQs5MQpfCU/nmflz5+FdrVrKW6TTTr5PZ4h6+3nlbrdVW7vQlWMn4XW0AhTx+rK384/dVs
VycZspzr3CPQutYLCsK3Ie00sn98AaIqK0WU2PN7To4cJtqkiyVQTZWLx4ATwWYvQT3iCsEj9gqY
oyZxnE2lAJL9uH00tIdOYLhkpJL7rHAh8I1ARqrlgP+DbA6a7CxBxjLKsibtfQeaHFuhcivPRMj4
ndWZq23oUCKS+2SzIQUUErIU/qAz64dg/afuZ5e2Nx0HvkkKaPPJ+iE/MKkWR9dgMZHjPTXAdOCF
JDW6AdawlKORI5TZPWrQPm4dPexR3qzW3axbSP5jCLaNl+fhzfR0tJW09u9JH4HZsNqilGxy+BvD
rbImg5RT2jzowFAiYUVaJOdHCEiWIRqNhvpayJuBFcldhUr4OM+CvefMPUHihF+r1dKxh6Ptxu7N
H7D61ThFSeyIqAWtGtkm4G0aeKeyOw0piUv3F75t9wAg1eLI4hqutQ3nnbsOkpGt5tGwCn10ANDE
n8O7WITgQow+90MkHyJYV+EA0YZvptxQXho7g3YXgTXeyF512ML/nRUZQyBA2+Ww+wKbCbgILLQ5
z7HJQ3T/Tf6Ber/WfMJHsSq5fs+wR07w4r1/gSfbiYcAUTVqH38mTFxec7a26Ghm+T07zVRpH24m
IS+JWRPuXvcMOSQHCxh74Q1ElAn6INvlOJ9fku/x4oL/Yk6IqtKlt2Rpz6duDJWg+wsIbpv+tqmX
/QmWMKmQobXpJHpNjhiz4Ufwejoi0Pgwxd+hJtUEUVErJAnMPk36aon9Qdb1bmFYsGUEYeVfcENn
Tk5Ts6oiryMgN0rWnoIAGvswXVJkXxwz/fSCPtacndC7PV8W8rhAFrONm9M9kG1aVNTHyytEfFWk
y2AHcD8ySwQnHUtu7EVfZfSOGuGCQ5yT1of/uyg96P3qkzS2qSTpCNDrI8tXtTw+OmyiWm/ey822
BQoODBqsRFYo7PAdxp79ZmkVCY6sW0sF0EhLU2DrCRGAyxlX2fNPmcvYgri9V4/XG/nNN9GBtE/w
SgOo+FMi6ywrgWedUH27BYn21uExmzPajlvd+MBTade7f2hhxLURMMDqqiuCNgHwHMlMIN2D5yDA
rrK3reKrE4CCuChJ+f4m7GwtTWYCvyyWhZ4QeTtLW5ROjkxnoLe0nbwz8z/DIq6gtVfVAFCJjhfd
1Kw+2+y1hinq527GPMb+Ft/EzyU7nDXRRJD6imdnK1rU8mnBWt99Uaa7dh7Y7NENLTEqPyeuQZUn
HtcisoycnhbvfHm65PluRB325rtZMZL48bh6o1ZsBzkHm2BM2YcFihqgvzQamuIILtsiZbDrttlD
filNzZ/5jd+aoBjMSLe1ZgE3f8cPIIpgNSnx1EoqDlKsHj0QqCn7JKJfnQ1+58OIP1lumbXkLzji
gzYbkc0rGxyscUlgUidQGajnxZrMGHUVZNeUi53Iwp1OonsAwh92dkoaCaqhlqc9aOFEoR4jBhU5
A4pSpBDy+RRIuI9qN2K5qGo+A6rbBxAlfND+mgN0KsLvPOIKrF4gDgBailU+up2adG5ibGCQOzU1
SYkKbhAMQBj4dP4ZteoFXh1Sr9uemrXL2HrlpB67lkrU6PgO2nJEMQuy9OJrmQGG6fIuffaTpq2V
MKC/tvYymP70H6xqKd8692iXlaRn/e/tfydUEuF3/HUPAu4CG0p+Yhp0yJXKF1qqnMWBwWuSW3Fo
MaBDBcYFHDlI/D0rQGCq/5IiSD08r7dolmMqO4O1/WHrrmyKsBeUo2kdxZCCR5Eq0wgjotK5ZHF0
NI722gyLUAg36mj4qeNI7nDznd+jkn7LJEnLC/xqgN6M97ro9z6x8akkVNeNsMK652d/rwJ0o0EU
Bq2wS/bnLWPAvpqM5af664U9Tc31CwdY9/ziM/GlOZnrgN4D1mQGRG+2y7i8b9bn2LYgz3r88ijE
8P1fq2nqd/eFxzibS1wiD8HEXqC/SB8oYMrIhE9N+stbO4FqcpeDUabbLCAaz69bh2G2ocssxHbA
airHUKRKpR3uofuh0KMd3GlIiPIuzfSCxkLMNumAPa6AdiXwVB7OkjwDeGvLz5ytoM1bEdsoKBdC
WgHXX0PGhMpMPMuoI4mN8iLniiprNrBEwWFrJGth0NB6GC6rAx5nQCbNjAusdqGpfFC0f+gs+REX
zLOT4otIvgEirqxd9P+BCU4zclb7yGXn7WzSgMOOfqexuAWj2wrCkyKWFq39a4CrsKPriS4jHJz1
/jgeYz/7d3YBvwRWpbzsDAxXh6ESp5C8W24QvaE+Z67jZgxBVzzXgKFDtZ69o2B6K++PBNAWp4Zw
vDjPyUiwukPlDI737KWXJFcILTssyE8faP5F8T+72ujJrfS7o/N84IgNucfoRQ22Dw78XBnsIur/
fzfERzyul+RmECcvSiPy5gwR0IjpGaYPW8K+740zGX4yBhOckstIQjdJle/JYvdu6h5h7x4ki1ZU
DxiDzTKjKBOAd9ztVWqLAeWis3S2GMeC7mGcjWTc6qyI9HpMHK3Aak445tN/P/dU9Q1g+dJ7chfA
pGeazX2qn/APye2+g2CTEBjT1hvloaBtCT46TResTKglpPFkE4VMAfO1CGNDyEBN7CHUQlSHIqcn
hoFnUPicIbJfzXYNdH794LRQpzgLIwEFEC79XaiKlp3HSDRYTciEkxxcXUkTpyMKPMpB8RD5CA8t
sRGlkIhuyJwrlSL4m9GVazCmhHRWgwz079OwungtpxCZz8YQgZlizkMFmFQ678ntAsbQKBp22qqg
Q0CE8wpeaXjjV2uvmUZJhP/AcivgOXhsf8WFJwLZv36I4s5v0cy3GP7azxLSkL/XM4kddOfsj2Ss
357tT4ansopjh8cs4Yz0rvMWekMlAx/4dp3hsKo50feIPtRjuEtru+jUKOboxLKz6TJOrcRVmGHx
kSeO0K3TXJ9IUWlJ0uTNTU2JsIy5EfITy2qJE8w5f/IZEhC0mkdhXDYRzJAEnc2E5mjScEmw6DjL
0eaGEzJk44H1OU3wLbrLcENqbE98z5bn1x+QPnRndwqAgw44Jdk/bm28XltD9rYWh+0THQYYXOzm
m3sQxL3ntclRq5H9L7MP7tQDr3pCGKIJobJw7NquKlDqhOoh94hSFvJxJJGFuLoZp0R9mcy1jq5N
3SfarFZjITz+9uWYMGf2nKBzjK6pBkc7odocBZZf/TyWB+7Nr6vsHjqxC4lIEU0Y+PC2sM04OK82
fjj9rWI1hHdGlXBTu/wFMyhzcDQ+DPLrc5bnLlRBzradVTLJx+IKcmlAq1NSorNhlSTzpxpousbf
+QLoRQ1IdWDJYt2MGMSXjZIBnrLtL48C3YzKUTKapGSMBV2M+JsBQJ4S7LJJ261MAYjkKLDtUNdk
psjG6Y2PmW3yfjK8xXm+5D9cz0qdEaVelARuZWzSB8WVzTdTBuL0bZNnQVP0GRBluV73uUOkySLE
zy5u05pq/eGqY/VbJD4uTuL5jiideYlF6vzuMq3pYmY2tAzo1zoPaGyCxulMYc0ROuPd0dDGlS7B
rTOs4jgzAa/2uzJABb1PkPTb+ttaLCOe3hWGpEoyCu+dA37zyh+f6dp5xZz8mDHTCeHYLwgDiaVB
ZrK6Lp575cxaCbGA1x2X4YW6tvYqWj+9wqMssD41MNnW7iOKOGtmunK+SROAFFzhYHVl0dB/GsKQ
h9HJPShlKS+KhswLGNDUPdVNuiPXQYHvcIhcuKbbDe9Nmp4n2hdFfG1g4F2OUzC3mIHUHHqHqkKz
Q2C23OetVih4Nep6jrVJalqUh6Sm6LbrMOKXhFm9Sc+3WVxHPxcmvVyfsgkslqCnk5r+3wjdDaGQ
RApYD6ynQA5SjRvbGIEgWGG6PCd/CQkgV0y8S/euwxVSmWqZj/vxmCSV4yQwSNXZ6qJyAHghHsHc
dW9DwGFOLzOBI/VD197UTGesqdiTKBG3Fwg1IZpt5CpPEshHImNMqNR9sowlEbrtHqd4ZLU/eWrF
nuzzwMov3dA/zhnDEjTvG42TSc0k/EBoHU+GW0OABzqFr+bBEaM0JvhmWEVH6opBwqE/6AVPA230
hMxUwTPf2+8GxsYc7kOYNNYeYHElR0Pb62fWidff1jsG+ZJYXhTdoG9yu8I6YkEC3cD0zXv00F3U
kJsyOywApFzfHD0T5rRRLgTjNt+PW9/UZkJ/ORnCcgJB1ukUGYPBoUFMw9fFwChMnGB93hWiv292
midbSt2phxUL9GEP481i9la22kMnHrflVaUn4OUA7fSp9Gs43QzFQqFKF5vyGU8glESiKLQhfNw6
Lvbx8hbrvUONzQ8Kv5MrplxRwnYynNfEHPd7InB1JhEeRTTe0jPfLshoyVuTjC/ViqwisqLwu6PG
5UVIrpg/dB5sRXOgRqSgt/9uEmdvwS53zTdCzHCmKVkETxh4Wwoob/nRSmjiXDzVF35jb6yZNIcc
EpCqiikDaJNaAe4R1b145nB1JvMV0Y1g4hnqoopHuI6HSFni0AzQMEkUg+aUhpykVJRMW9y2/EG6
W34vMhjyr2LFUeE5lwh+/h0cIbkFomnfBDMVUAgaXuYpLGOMD/eZDWnpPKDhggFWCYUTYpY2eEFr
ATyMgqICIlggz6d5/X/Geab3WQUX6vBLqmBoPOGBrdoOLs8zGnumTEmpG+hE7ISBvAd9lN7m/CDb
jhpMds8ir+yi7u9YUufjGlRXG6UtujjV0gM6KaxQJI2lEbx6NAXI1uGzTp2spX7TqiDiJNh/+PQC
LW+sro2aE+ZlvuQevBcLdWmDD4RldCcldr4qj30ex8uZwhc9hlhvXyVVnQWLrTA563egoNaRDf3z
U2Xruwl+nWniTs00yFhvGYFTOs7/CyiiA0ajRHGES0HUrL2/OBFTjDvuFNq+eknGwdU8K87T5a3Z
jIyy5OfaTjuXzEkN5q9bHW31dazp8sULRRnhxApb2ndL3AQ+B+5iSHFIQvzEffuXd1up9fo9psf+
s6boOLqcV8uqVtoDBBFB1PPK9U4VGu7sqUNzh7MqphNV6xs2ooM+csjIxXscYa5U7Hy0rBE/QDXs
lVLQrvhTsJti1dnx9rdpZF8YDcNSd1iLt+rP2ArC4QxYuDEjBBBQH0BLHtM4AmqYmeEg2rMdGuqR
UiW1tsYWiKQH8LBpcaM4qCuBL7MojWoPF007GTOo+WBI0kGob1gZbrnaE+iXuab5sz82qM+FJYsT
ANFJjsEHHsXMmH/BfXv/+PdsurocpnApdspv8WAeW5tJ8mal+E9KKSwCWdnMz02KN2i3s93DP2yh
G2QyT8Jlx6C5XjRR+FVV354EIb2IA/V+lq8lD9iFqf17ldEoPTUMRg28fnWYkKG2qu1RVlPg9PWi
xGSPV/mPHFHYekcedrzIDv2beR5eglkT4b5D/NOMuSVc5XP3h2Nu7HvllTcyjbt6fYHPOXh8r6mq
OIiYu9l29endMWntcOgRIkIeroLHkSE2Se1/THGWfJZlc9BbE49QnD1xHbNJJSLSmBnll08ne5Lo
mMY29kaw/U9fnw3tmhgepEhrjwiVhCPgI6OlKTEstkbrZAd2Z1OJCmR+TpJpQyVktDE4v4Ttb5Qm
Hcs/5d6Kqx7wYeO3hNdLQ8E4wBguGWKHMgmZKM07DnZ5fiHiSExBGYRLJjehlqeV9kU6mSrg2NNq
5PypITIDI06yM73LVFwyPQXzc2uPUVWSGKyKpMhY8iPGxPlBSrZaAizco0gLwKSSHRnOa7chjKoy
vZi388iEZktRMYrX/89lJdCdlgNuKU28SiaJuZJ1ax+zZ3aYn9zro8HK9zOmcB/ty4u6sH2Ops9q
ZiAA9+IthGlADUEgs8waYnP1CDTYDhNc5uw7rMe3JiqDiR5QSOni5RFLvGP3VvlGnTzaiUmBa10u
jOa39fGG1GY5f2BWGDOqPwmlzn4CvmY6nFaiow8BrJBVp3JxUFoCNEg6BCxavMzlAWBwxxnO2+Os
EfPdwRewriQ79+jYDjxt7yZHClh+qEVeuY3hg+aiHScEDt/QTdj/7IevZHuZ8Uphdfb4N19vl4wo
GM/FERNtwisdvSV3HjWzoLtd5MkbTdJTIEl4yCdb/8h3PX7nzIC3rOE/cJR1VIXmYOUGYD2Q07qW
1Vt3FyYblSQAaEEJwC0PaR5ysQiRRBQMeQKskkXLRN2GKt8Y7wh0Dkn1CfPBavPXHJuB25DTCwUO
2zsxemLai45XQv7GMTooyuk+JukUWJzpEAkfsRYEoJie3LLHkdwAT2oow1K3rXV2zeTIrHN9zOEc
PLh3JmWuDAIU5gyFWRWm0mlfIKu0a9/RYhrqkLnb/utGvnI5YX1MhTlQwrZdkkCrQ9Tm6sxrMGYu
OjTnDUwUY0btx9oz2/nIyqEx7Fqw1s2XZCTJphd9/+YR26ZRtM6q+ajIvyGZsekA3QbUlCadPzDr
l6tKZplibUJPSKLKWmQKsReiHTuVIhWAwniSfqACfoLUNkOoaP7Wv6GCAwG4GAPhBZtExnYMkgJZ
qEqszlM5+JXbqJ59LHebloaZj5T9XPfjzQYN0vnUV8RqsYYFWYS8C7LyTklfTAVh38EK1PsEo9EP
TBhhneP6sSRt718ZtjqhAR1K5CY8W3x6ITW1TY+AuU5SE3wK7mvaGKzj+W8kfAYs4Op6Oapp8O2m
Zv3ny09ahfl6mmheeKuLxILNB2v4/xHo/s8+uqu5JUowG+10izbzdwZj8PMuz4uEEHYLubsYL7Z2
qRssErB/YSRZGI1NUS1/43UJH8qtrgDMZurhwW4aCJ/1VLO9v+i+TENPCqUsbCVB6091TgxtsqvU
qYVytChheKmCWsHiSWbdzc1kidJsXWQVl4t9aFxdhmRlMJmCwGR4lSsme2AyOtWohrGFgGAjZckR
Qx60FKpbGQ8OPSUwq2gGXpITAPxQ9NWgulvlBKY4rhbltj5yHjAgo1O0m7Bwx/hC+QYaQguW9oFg
8lOjGcHp/KRmxbalSmdsrDT9H1asgXeJ7IbD3kwaXj8rbND1SkJ7ZjH4YWxmXliI/M/RH76Xwrcn
NbNr9Ot1+QSIGEL4jzyoq98PQDPg5bxKWEeXEt0EyyOjgWv8WBvmffTa5DjIV2bxl4voj1HhS5Md
mbwStOHtKixCGA9bAfqZlUbFBKYgnUprc42aFOUseSyMukJRcFo206Sm8B4bHoq1uz6+jgt10M6m
y1csop0GTCPavzPR325Ittu4qD+BKDRMhdmoKq9ADhN7IYFRioEfe5G+dwCe874yUKPbz9m9owlR
Zy/KMt0F46I5uSTWYjGFAi5WZ8PpliTJ7/nUuz72vz0N/JoFkkq3fe9Ku8Mv8OvObWflY9zayJFj
NSzeX5ixZhCts/C/RundzjqT91tCPntAyVHKXQGDV5OG4cflGhmwrCT9feAegIYz36+tNnODuvW4
LejHKxnIytPYmRuHAXbImD86Lbh/H9UKJ92fxFd5yaMoSA1gOCJON5NEHBzIqGHd1j1gltaWKKMf
MaNL5t3U/H+8niKDtAeinIHD9XQ2Sc/Lre7A+2nAk8aJf4zLNyOUykR8nxjidcpZq0VIDdD8jwUB
LYyGEc+TWCA5J630JrzG1mD6LDxVUzuhspdd2mxGDYhA61jhhAVk+tvVTqUG+MPuiYN4i34l29ye
1xngiuHW1QUA9b2tKIB3tBvwQED2A4rgfybjf6Dy8rKA74UcMSUzDlFBJ9gD18+E4PaN5S5ph4V2
mwdpnBI3iWKfpCZqF901bXbOjT5N4RLM+pUcZ+cTgccynwmmztl136MDBtijYqscQAP1CF8DmEZQ
xd3zFJT+e8quut199NLTQsL07ks8bN9MpBwcy6Vc07zNxnzr6ypIvFkfOYFptjIE13AlYH/BhNlD
UHiSBCsa7/L0RgnLmtu1Hd8wkSpfaYLyX/2QhbnHYYLcQQrBHttUu8yI5PE+p8E/6D/4/uSOwqJ3
ylRLfsXfj3dn/O9rzG0YNmJ2ScOkWfzkoc1CJ2WDhju/xj8gocmJ8SaRHcpdcrkPmqkKmjkzWn0e
GCv7gJzfy4ecrDPIu6gY5Ku83ErVuG+5lmS6JWLKeGtWUHn5KxRi0LWJqlb0eIyxSCmoeL61Qn5N
/LlUzTVQhjPgwoIN7I0yJbDAac6q/dkddxGDzlLqtTzHWcf5egM4S8Hqwj/KA4V5htdtKHGfLj2w
6wITO3c0J6KYWK1WHBnB4GvVSSaSZsBnKu0YeMMKKgQp1gzLiCzQcLSTy3YUH1p4IGepL1wvY0Ug
8WoH9WVDxbK2JaGgERQgTqC071nw5Bv9plP6qIFzclUXOCH1QDL6dNN7bDUZjMG4SX6EC5A7wovw
5osrKKa7ZkxfB2yVClBr+FpyEwLM+SwQC6Dk9VfyBpcvU0AqwriZv3tSdOKwBqgI4gc3HJin0eQT
vTMqINYdNcybHs4wUnQQF0raVBchNuC3kCU+/vkMhfAsDX7YyQ8BoKGb0ZYlqUQrR1Dk2zM+T9M5
sqS9iCMkJ1PEB3SGEKjbTPKFSg3mcY53mOSMXwAqTipAUOl20474gFgmfUc4mnB3A1DZ74sE5xPl
WMn5gH2WwMtEU0+wcPkl/zoTiouF2gIHFuTrdmQu+eZXNGAE9732gTrWChywX19EyxdcCrEEhjfU
19kznNpfBPpa6ElNIFeX7c/ZGb58T6JKKMdubD8nLwEt4JOTubf4sJXSs+QwkgvDum98YVHC5EOu
ckC3HrFb12zbs0HL/C2SXZ1B+qgnffZjYqH5RFTQmhUvPNdFGuK239Bd3nXgGycJHEBrCXGU/QWC
mKIzBlOY6ov9BFuOuYJS/fCUbp2B303SuMYFdn3L7LdUv5fGgRD6qC/7AH+GtModegTu3OC8+26p
1yKzwNXyYqT6Z3OwqPzClClqMgOyftSrwx6dCpsnv9MKKKd50/ljGS42gjI6pj/+XVMXe55RM7ZY
zZy0biX0Ej5OSYjUMEYeJg8PoiYs4dnDc1EqqTYCLxYjeDVkAg0fcYKu9Fp2P3a857yqs0zotwUa
KWLh/KMg4aqNdNP2SIdNVDOT3tAYzQJO4FQvqkG1hQ+rsYPbUip9GHYijkeeShhr4mgZggZz+Om1
XesZA81nAl0TrokoVHpGmDDv4KlHDV48genMhP49CTkrthPSpTyeuiASrPEVBT4aT9UdRmzNGxS4
lmQ1SBPxlmoTcH9QQISNw+cN5EvaG5clKbfpmebChggrjhWifIHMXnPLDu7poDvW3sivZ8S6ONIn
3usUeR74u0yo67o2F3iJyA5b4FvW4CsYY88anAu4KGD1lL8K6qEZbLQ0/v6RJK63ezoJLkAd6Web
fIHx54VWWIKgt6JUYOHGbvYqnQvQONyRd1Y7L7O25YF37PuuatutaKX/wsdlo1yvJnX7rcvVWlKu
4wOAeiT4bKErHJnjsSgG0Z5+2QWipdPQxABykOcb8A5JOCk4GhiUNQpsm+fQIZoWllytaNp2yxJ/
eiOW5GP2DO8NFbreEpDfin9+xptKD6bCjhP6hh0RvsoJNtgtE53YCvaLcL4E4NkEX2DegL2KUtJc
7TfRpRQZyk1Mvz97JJbIbGZEuq4nVFaDlEU7iappiKBDa5BG7k7CbBwDP8rFXL6wCBDwUHbt2MOo
JIMIpvy2fQNrX4Sgl2AUl9aVr93NGIGyEdXmXuRCJSASZJH6XXGeu4lI5vcpxVZhuhYrGXTVE2Ty
LujjC3y/vJFzwcrEGq62UKmQs9jaoKdQJ4z6QVp19XZMNpuXRbpGByVhz8esJz6oKy0LvriOqb/v
xP90nv1DCsYAwHXtcOCD4+gqcJiLVzaS1Soh4951NPYH0536NKmLB8J7N1qvLJvLndhr9Xn3JwCV
VNYHMGDE5B0kfAiS88UCiMxzt2MdSDLwXGX4/AP4s3zfc774Hcs8pjzT2aqNVcGZMT9fueQVj86Z
2JstaPmL89xOigRgugEanZs2UADMYNweGf1kzoaD3bv+bOjb9d5Bk031sii+XJZ1NrZaM7ey3gJg
H+7DvbsgLfFrcIU4JzhOElVeDEkmIXBziETebe5Q3hH7UpyeaI+il13ibFDoB1HYhWjNvyrK60/5
RECAs1SZI8F8eDuX/kWbzVIHbgY49b0lPDbG7V2ooSNHa2JOorlPLdaShbSSkZ1JjPXT+D/4PcH1
KuNmkKLecTLtOKsMnEmPtJ7s/gkfXyc/kV4IpeHzf17vPSplWUFueld3802DJkGyKYOwHLhK9PsV
T7/8XSlyi9IBCEOU2iUEOC5FgOHFr3QmEY8KCCm0IYoyNDwe0TMldHiFhHibqD2EhcgrMRgNvwPq
Oa9sC8bqZy7r6qQCxzifBCIYCZj7QBaAYuevnKg8ehl+G+3TQmswgPi37kH0sfWvYuL0c6tQhLpF
nWalZ0TlMl7yN1WhvCoGbwn0aElXVpUcea7JwKrhvRwtjhasD3wBdqa9YRVxU8d4uqHkP0LY6HoG
B6ET1L8nbHswm5FRArBx0NkHYKXi6ilAelAWpn1J6bPNKGZlepDjWXsAb8QB8tPf4w8k4RDS/UwW
F1Kr6fw1jgvAGDW64gN/nwNAjD87PQNFvJU957dyTYkLYOWB2uEYYvQHWoskjVslwSWrsu+rul8U
p0LvCVSmVri98rm0SMXHutk6WJsdijYNQZh6KfxFm6oUJbXNAvM++6XDdYC0M3A+o+X1Bl3jQmzV
RzT6xYxhiiD1BuM29DccncFBF77zhBzyCRZhTr3ArZMxGb8Rn6voJ/WAtBrEUdm1UTgO1BwzbKFh
fU8V5gJI6QuEDYcM4JNUSj9hN0mF7q3OcKxn88Er6SYAAU4zO39MKe8ay50re6i9M/d0gEFDCC6D
vZBjmqiJAUFKb7c8k18oXwxHt4RFU0hWx5LDSj7qWgvGYU1dQ5nKhrdsH0cTk39sFXznEMVDWtl6
qJO63mJoaiKLCzH4LdGhD7t0s7hG5zDaCyTrWnl5GUITHohIBSJ1ZVK2z+O+UBj6/GvLBM/wWpsc
cGdaIvtGZ0hV20zFcnqI9N9W04Ms6rFxkdUOM3YHiVG37p8hU2O3mJfumFeHtuUD8xw5jgZ6VBLJ
5tWlqu3McrTLQeTdrdxFn54RJHybr+DHq1rigqXDNSmSitREYP/JD9as8ZW7lzZaL+44b24EufcL
X+z6v8kfFvyfvC2xFDlAhQq63saeU9nWxwKkp02zSSP50bclZqYgN6BSQ1YgF+5zCoG88ZHOeUy5
Q+qGFxpIfKE+BtIIF8rKHj46/IyiQRSQg4zs8koZ3oVCyQGx6yAgrBMMBDD2maiAcrCPolbUnSB5
qUHezwVobjx1CaQrYoc+bh/BWZfXtj3ps0fyjUYU+qZqMlbE5OSD6ssZwx2LkZr8/IClPMzoYql6
8+BvmQsmu6Nkk2vMQjvCL8T6HhKtZIDJGIE5NVn2ecOlNry8xzypBlAAEYGKvN2PnTVCD2BbEkN0
VjM3vAk+3aUHSPjoMJmBJuEPHjQC+JwoLCgJCJ+hXbk+6mmM2lWXBxIt3aywnX7C2/h7gxM1NkbB
BZOZ7jFrMIptOAQDd2qFazQ3NjDoCNBpWLgQ2g2xTdqkdXyQLI4U1w7346tm4MutF8C3VHLFKFdh
haYnBFAAFJhyYJ60U1vvdOVY2VF+aQ7eQKRzyb85EbrbSzCZ1xyDojbJhxXOFHtEC7vyY+Qi0jTm
Z7Zhkq6sFxzZm8mu0Em6SwUpT0YZdOTNtr47ATGIyA9LG7NYZ/6m0YW9Mpp/cWyyjllupBwwl/gU
aFp7drNiQNuXQeGoH7kb0J1m6UiOP/MfROwETseLO0CLpnJxyJ1zQ5hP/BvgnCaq92xlXNm3+Zwn
qj3NGoGgy+7pPPrSz5WANTFO1ykbP1w+6nFOm0mjufHJOgie1B9f4HVJvMmVt/da8XS9WDJlPVE7
ztWiMYWFSu0ypDbhNm2O7q9xxXUJyYOgB9LH2DchYfqXMBdee+f5cL7mw7BCLF10PGCzLBi1tyTq
/U2AlwCnXe3GE+rU+Sr0HJA8adZ+IQsMvJKaQP1ggZyowhbuwE05M28Q1mYab9GSz/zuzBhxYc41
CDrpCn2qvat0giWXSJ6ggSEO1xoSQPOJnumEhY5Hiz80fjNHQV4n3n3GA4ZGhPxdGsI8Wylzmx2B
s1Nfvwte2ho03nOn7mBGMZIJDo04EVLaFUCw2AaDtbLTqRt2lteUWEnnMHbCmtZPzfHjgp7mU72c
jD0yd/EBdLS9Ryj+odNX/DxgmUvo9rOuDA7zi4Bwi0sna5s4hYKI7MVnu59sgUJWizF1sQVsGR7q
1Xxm34EEdW7zDuuvInqQS10WG9gpIyebMIALoyEINXV9CZ0QALE/JQH7Wd32T4gzy4ynmEvn91wR
r6M0cSkH1vn9vH6RHShr0jRGbeEmJqSkfOx+mof8McSirQX9Lc2TCxiEuPoKtBhkYrDeV38MJ6uF
UItPl7m5+azHiG6dvIzRHUoS/NRVmZ6E47a+r/2Tpn8hhmyRIc/r4XGE4EJmWz4cIE363atk0n6z
3pSnIJH7KKW6ZZ6+owfg7vmYaOvFtavP3VosyBm36u6BRCcmUZL2PzOQzNbAulmfWhvyusQk1cJQ
hv6TiVH0CuLMhOTM/6bbfI+jVPM9YEZ/xILbHnS4etidj8vwNX3aM8J/RGWo0S5kzmbIbUJ2ZW3L
6TAm3gwMviqHR2YOdE5jQtoCu3cuj1khXxbUZKuu7RqG3WJNXUhEFy7BrXXhKrCYo+qzJh4CH/0H
TryTIMVYNMwaDDx6PcIsnBciNAlU/ZQTH6Wv8MREcKVndLL4f90/q/vK62h+Ocm7ahp1DDGCKHN4
eK0MZvQv6Dmnq8M4tGX1H7aOOYskOTbV6GMt4kMUgSKU9Vt/AUQbVj06mJsJUqxJB6Wx0UqTHVUV
VL/y62z+/1EL15dz58ZpGhzcwPiCe7W+odGbw+c8HtlNS2Tm6tjctDrl394Xmi30TTV0WtoDAJFH
hC/r135p8SwlbGHjzKrA+HBvIbeu7laZPNVVN9cGE0xKsDIfhMogbf3kxgxITsV48VRBkfYnGjGR
W1mb7HR51CsVMRj1jC5qtSgSZNwgu5UOc6xCCuyTnEAzFEnAAlJ8rXKB2md1B6zA/PfuovmvOnaj
Dqu+pPK3qNZIU+l2y03VXgWbofBHT87PcczhwXfsDrJhTKGnXAI5GF1A+u8WeX6OPJVFXKc6ywtk
M/A/PpjSyH5bek2OFHx7Pk0XejS+eIdgMyXah0BFJ7zdlvRWachtQOhOPEE5LxE3vvEVIM3sIP5j
UhKTsWLb89trFsrogwq9r3M1wOmwb1SQwxTFJIJ/KQSuM8RuouSLMsPDoR7nRDdj2rpfLLWEbW79
O758ZSHtqoJfGLbKZfWbS1lhgIyw6kQjJEtV0OXuOeUSj/uPcnv4X9lcn4ZHG+JD5Ml79ByNHpq1
N4IVNhYLv/0PMJ412VN56Ii4B7pA4Ihh5uFkj1o7jiJa/UWMHIOE/nf0EVD5VL9EYgunOeaYv7kP
CUU/D6eG96GhphFBrLFmcDeG8J8BSHpE+EhtKmQI+uhzlsvtermeet2NDsX+eSke4gZszhEp6GSi
4YjdUKcN27TXwyCMawP2mO9iJUk7J9AEQPTKmbHox7Cl5ais7bWVOMXbuR3P/HxSFGgOL3rJUuz9
Lhq8b9VWeko/7zXiNmnShBfGejVlB/hT0YIGIwlf7rmctqIguiG8ByMS2d7kd1ZPYbfb3nXBpIMt
g75BBLOakoxofHNIUZp3fT0HuMWeb1v1Y8PqJLtjrPs2NDfRqBWWbGcyYbbsxhfFEP8IK9NTOhGw
996Zj7HAZss9vwDM1V/pcr/iMYwrkEycgib7E+Ui6M6JV5y/UW1W3DZcWQOuTBdBo024VAF0Ojpt
t1lsPR9P2dYk9SJwCrC21GpKjpvD7sKP/cIzCe8BNB01XUTiyIZYeo0OSuOhGV4w0IPK++3mD0qi
MMNxTsncH1nceX99Z0IZJaYxxX83GNpcZX5aHURmwwr8/fuXxFW19vTEN9u5AStYFOEW4EqyKtVG
P3N4jr/+ANUgUsz0U5i47zQVszbGkpTcFotKyV5GanT52cTK6CJPAFQARLi4Z5h4xxW0pIzlZehX
l8QRhLBhN7GTMzvM2nwQqAm238RT4JokJYvqBallfRD+bXVHIiJBHHfsukWWO4vTZAzXCEgMuUk0
xCvu6R6FnfwkeGEqINyomupXc71oTowYhDJhI7gi9F1HnQJ9edELexjuhg0Ju/uxfmaxXoo3PWKj
XSqmj+Wx8Uj+gcvF8q38PxFn84poPEP2bc+mmSmVhqKQZXKiqjhFReFKB+ydDy0HccOV73+lyznB
UROdAmB82ZVOH13e9Wm0ab7vMusT6OriY36NzjBsrDFXSV2BCkCvJShjDth2kbX139a6wNbZsp73
H/XKglRh7EtrN3g9MmQlk82CJGWPrCwkTpWc5rfJSox6GMcluVnz4W8Q2TNEVl8XfcvD7qihczG1
M0lbr5dt+DfOQ2BjvSi5KyMB4IBEgMiIArilNztUgNQ0i1oR+WVFeqof183qchFZHcta4FRRNOUy
PvebDBEVioPnsoWXkuQM4pKCcx7hH3ouNEhlzsmMH/UyR9gEE9zSKKwzxsxirEVJJUxL49hxBBgT
ZHjiyk2YRkEIsTkn9MWCu/OLi0SnENzmDXx5cQNlydDf37Hmv3gf5TrY0yNIQUoevSZgG4V3bG5u
GptlCEa6TQmcWcF9MFYyogtQLbelpB2F7MgEBfSHMKGvI59waPjHOl4D9Y5Pe3qA3/v+YPPb1Rb4
CvuijjqftLqQTHyLbZIeFLh6XEnWYzsy36VelQ4MeIrI9xuGf4IRiBxsai+QUpgbF2Am2MjwRQeQ
and7u3Q3ZlWhcpqGfGuc0wFvJh5HNusUJIVHnLqAtrE1Sm+FRH67M3pQ6N7G1r7WGON2ZafDGjqa
Ic2fs7foNN7R49UDc1XhM60Igabwi/Rf6XDHR8LN1ERrZj7W7EvjOcEuLItFjMkYC83Z+erKLz6x
qCkpS3CWomFXAxSa2+M1tIU28MOUpXE+DbRfyv6sJsNqpzJ21c0yz+xvQ9pJC92kwmPaTSiuYsFK
DflS+FrLPELJJJRlDRVBBXczsw/KwhJoj+3kmrtp8KXoRlu72v2PAZr3w2VN4i0ZEAILT59THE6V
MWOjPcHVHG/K0diEOZF2N05+D2KEYUevs1tkIXcc+2QSFxnAU3hNXYtLv7vDDKe0vFZeW9hSjmg9
LySR2c4fiIl3px7cqSnDTYdFfaXYOrYJ26k2mhuGopeBKSDvfBjyNsnXWOnm3fsL7oklP70d0zH7
vUBmSRDlXcWYeO/d9QJ5yHbttoCLZfldiyToeYXmbVNdyA1ugg4AtosXSxY0fqpozyWejlzO1sey
OagQxVFoQzyvzTxya1ce8B6lG/B9VPrNbv1zw5OmRylPrRx48cafmkvA9s1QcnhZ0H9lj1i+mral
1d4lDn8yqt0sRIVDyXfkcTrC+XYL1dJnziltpJ4s+Hm4tn/EewLWkdftZGzHmbetu+sQhJPP23yL
2aCuXEc3fQBOTXtEcVsDDLCDkRy8HGRALiv5+QjYP3CqP55A7K6ExFpdUtw33wHHtTpZOw/o99uT
9cBk4tV2Po1kUzQ0NNEb9ACkB5hBoR0CLXSSTvD6bqUSFSDScH3dZaF6Ftq7WkC/4GZBfAxoXA4S
jAxEx/yRNYxS2qcCbK63UJdi/4K030bWXUor3lqBbdpjRDYNmR7zXsknuxJbA57mPIwivlTpa4xU
GWxH7BKEjbWZfHLX3ArQkciT1SkpyCxryDif3a2s65M+GSuarYFFNDqkgpEfBwPvBulyMgavUjk0
lYQ5cP9ZaTghagBbA03ks8yCEJOeXaD4UhsvrY5if5ZQOxB1IBBVndAVJfmhU+H726rnxd1vI+5N
D4PhEbZQ4/Dm2IM8+z19tMYeWUEJoGEXof2QreUvBiYJxBExLI8smZv9xA5NkxtQ/TAvFh0CMWGL
bLp5KoWlQT2T3lHSnKEaWmz3Z6CkgKqyy3CGEIy8pQXU+8kHcQ5f/tRR8wP3vi8d9Pgfh1ZpTCRh
Jk8mClVDh3us0u0K4BJ4dEZXjh7RHN0e/gsNfNUjgdCRqNhC98z5wX7UIo9PLbnvdSTbU/lgcpmb
jZ7BvN7c0C8mlhkpDFDOZ3UHgesxKa3SD4WG4xtW+HTPT2A9sLJpoGLXRXfLXqF0/uiDbUqD2q96
pXc6h96B8L63XJa1/dGiGIPB6011ER/TP6gXUjuMWdKjoeBseEHeGu7m58PstffAxpiAWsih2xc2
AEBizB8bfxKFQOJ6k6GyG8YijzXP0w3h9CZkzcM9uV4M4nUGAkZIPDvDirpQCm2QhrQjNZqZJdU9
EYElKR+4NSs/x2Z9bCG03lW5ofs7tM19TFGCQeJsd4PRqG/ST9j5u+mlsxhY55i+c2GAxShqAgFO
C8tv9sMV8Lpr5orsqZTNlsmKKJaNsHvu4cn3kYBNGudVuIg1XTYnSyEqIbvaP/UMdPS/9Ya2u6WM
qpeyID67V+0cD1+tzNrRAfLkmnL8ardkrcgZN9ulepOkKKw68oTSnhf/TYqULe80UhWoG7GjOk9G
cwGtEqjAuXr976pJURF2h1axFFU/jPPDTpHT79GLP/HOZi0OXWspoPFGZZ/aFyAtvcKk/igC2gCB
uSFR8mPNhBgAPPK4W0GaoV4aPSft1fTAd5Fr7zNxhYo54pyCBOd3cOJy3L9tOALtLWp4eXlGQ4kU
ZAW1mUxbvB4DtMUqLt/NSJ5pU1Zp2j7KhANcju1TMXtxf/ycBMqfMa5gkVGyyy8nT4Sqic1E6rIS
YSN8vcGdMEbQxML0wiAq7K3PJgoZJ220NomT57AQWvYnEep3LgZBld5s5Zy+FWR6uFrn7O2QWFe2
lYEqqNOvqHPCN7YemRT/rJrSso8OJE9SHUfoCC1fxuZVxZuKUYJTPzxD25ghNq4VuIjxF+DqYn3T
HBs9AyQWFkkC3czo9xbf+yqfee41uiEulW30Db1Yf9NYSArJLJH/o9vx59x4G5thYgVFATpv3KHk
C6Yu0e6bdwetyZ3S3iK/6/v9CnkGMJlgQv/lmhbyxkebKaGQZwxKgWaT3XAPHUEQ+tEb3eFS84U8
NpWPbCnwYnF/e4aoO0t3eQl/BaFF+jKsk/5cyxvbXwaXZgT8UraAJjkPYT/Eclvs+/rNbnSk94d8
Lqste8HqHZbVh3OLW7YgIiQhIzaEGZyK+GftSiWtI+FDUIIwUzHznA9rmTK9hr0KN7ykIQbApfvD
+c4EtY8Z7Mk0iuMn66em9rzz2Zlab3iru9Ma6EN9CWTeBtTW3RHKq4KXuKrDKISJa+P85YKV/8Rv
YbsiJ9VHosARwTKWhkvyEH7U+DkyZhHBL5gj682a7p6nA0OjjS38r/n4zA79/zTDHQM3ViUS7kCz
eLMW8yTRpEiykqZbhWN0d6mxXs2wq4eVzkdYahH19n/Nik5RleNI3wT/SJ6y7a/EAz4IusrkBCaF
RHqsfL3gT/okDvtTKu9inV5QMCx/DChy/b1CboThDaE8Cc7ZLo6hzpszvSpmRQCWCO2Nqi5THbHQ
VbABUbB9+N9zMdpX4stqH/NL0TiNsWnMJAOuFKQfZ+CGkx3vtcPAgGgSTm2ovMn7fzPqq+2zM+5z
C14mHYsdCyy+OtGpDSW/Sx9fAPYd+Dd1XsbZPcoi5YKiivwpl/lAKCuczPgbcer0dUsfcwttAaYY
v1Ih2Owr4cUYY2VZfu7aCyNSjbpxT07EY+9/2xkQYL/yB4Cha4qBqf/I+H0taq1tZhK85gUS7VL+
mAgZ50l/IdkNMRjX3VzS67FRaRWgnjFKfbhFNm/l6fU36zmanmvH4dlcxn8aTgMUWuhMHinpv1vJ
DMYli96HMI8gDsjN2ZfKlLxh3lV5SE9d3HujBYddSuiNvtBFxbVvkOeQ+YfmxQ7wJOap2REVQQj+
VARD3bAKPVigiqVxfq5WJSgT9gKPpxVQrNeWB1fbHU9u0RaTrQGbq9COMi9LPFWdKSMz9p25F8rd
YB7zNS87EZbxp4uYGiUn4BiHQ30KY9Y4mDyAPb8cDVrcMsHJursCmf0fe1+KJxTOQhZLggCzTAk0
jTQQ7E7fxUZZLo1ajt8im6JRQEy4rXK3w1m5u9syijAllXU2MPrDFqWIXDOhRM/URLr826hRfpBM
WmkAs0XbK7MY0yJISH43ISeP1i/D0tmKD/gGoipCcbasOzRClyt4AEAtuDYF0O4OGqdRr+rnYPfg
6AyuB8bJWDFOxXPXXcxV4qYaPB4ajEzmalK2iIAGE3Qh8EGUOE4C+/AYVSvgxgbegQtpSes6ioi3
Hon0H83BiYnFPituOm3P8KB9fWmSUUIXW2q47wzgmGEBGr5jzd85hPhLufjWXugC2wedaDIKOt5l
AQtyY3t6H4EkCXiElg0OwsO/VD2ln/NFKGzXzw03Bb2vnJfoK18svvKOmm4mponZ+F+Sp4tI/F1r
i9c2QjuC0xges5MCgb0qQhw2YXhf9/MYXEkPcZiZ21KOd8wQgky7tXTBtyk8didmSIuYkSGL0raT
pIbCfb0BRkKd/6KJhHFw3oPnQ+D8poPvbMPZLr9RPMB1d7DOsBOXlscptW6JifVbdtOYc8UDuP/W
txfIP4q+OiV2qzzY8YY7Dhrx0fW8OAs+MXJd243IWblY5hcMqk8Wi98o7/ZR7zntIEA2m+LdWT9W
Qi2RNdTN2cvOzok6DxE92p73G8KU9RLxPs4JaOhNA5s2BelRmk5PuIz6NroB4W7jd6ULpHLLoNqB
a2PazPcV8FEYU7W/j8/OoWVS6rk2rLxAKPlOq1Pa7C+XJzI4nnuQuv5iQtm0QU/WwbJtVguNoPlf
iBTGZv0TPwfM0De2UJ+Jc7qDASExJsSaoZjpsnKpZZqI2k2/4gIC15btGP4sWyMYhfjiapn+ApSk
l9gtfZAuctlquLxEjJpdxDSE8PM6X5RJ+VBi9zjMCSJntrsg7cO9nNT9TvLg8Y0MOE4keOM+EhIJ
apta1OsNjabNRkLY2L/S+t9TgHthdSjFF7IRtRsxTDEcevNcLfPSXkWmgt6OCvO8vAI1w68nMHnM
tLqAzuU8cBoVU0Gz3hL5Lt4AsORrtLF6nI1VTO4qupyYqDftM4m+GRDKiC0xQIZA5yE4b99ru8En
ZTFY4HNdSJpQpXJX3YyDGbhtlDBIXnScrbXm3sUBfvMpAnta+yxhSV34nnAwBE6cLqEenzG1RfHl
0t97Xd8D8qHZKEwlQ2eqXitYoZ94Zgc8FrOgyQOrOu3OJ241mGbBlrorBV68JlmjAySX23nT/bON
wM/aySjVzH2EfZne58wcSvL81cvzvuXlf8nfJkK0THFHAfBXBpQDrf6MXZ2/gYJu0WpCgxmXCAxM
zp1Ja3zvNVz1xJneTYgosiDPQIhH8yniqjuDJ+CJWlEbQbDA6iXQqY9arbHs+w8+FoBHmuUXSIPT
yjstGdglh623L2Eo799IgAqB//G4QyN+HRohDVuW+eS7F70jGGjjMpoxE8WhO5YGVqK8SGEJjSQK
P8LgM5BKmwqu7mdMz9hmrWODmgkdb3MWWhcq+0/x4S2W+mnyQ2rbTQcYLkIdBjCU8NYl7DZe189/
moiV3j+u2nM5dBf5NOO6kHSWIShYdYZbIhp99u+zHjorWkCxr7nOvkGgyEBSz4MDvNqcI3i2ArSe
3fFcprEM9LfPp6pjaW6yJa6evm/1RTE7TcxBcz6MHPmL3so9zC7VYTOfCFphlpfKY8cACQKCIrDz
9xqimexDqVcc4mwrLZuN3IQOHUfJdBQ53efobqlCh6YuY9A38K49hahcGW7KETQyu8LSlXbmsII1
tAWxyiKC1fB05Rtk1rWFmXQ0g2XBwpI54KoxsdW8gLvmeQ/b2/BnW9TwOsacrJIZGuKNVE+XdpIX
YOLvB48fh0ZFdzkMm7d80Ce4CMkLLfQ+bC5uq/+MV45k8mAyS+8fA0dtUeShJvuMGVnKWAIGi6Gk
oAMa31eY+ojR47Z/PocR4tuZ9v9m5/aTJhCsw0nLuifXSzWOdUs+VTsglcLtXINOuVcul94txsNu
kqCBOlnQJ4lcxrAoxcLzAwMERQxuHzFiDjxiBAOySBl2TOtcI4oMfIrxf6SJR6rgNx6svD3XLNtH
eykayPnXhd5ixxqHm6eCbcPxxN5MBxzHvPHJSqaose9vIcAPgwnzaprxnUlpq2CLmdyqxU3StO2J
6Bnb5mmHxJo0hyECaAiRNpQzfCj35mE5Gh38XX0RNXvB+NT+CTXm+PhRWx/vlQOxCXdq92AnU+/u
hV9HD38A5wLUGkMZLQBvweXWnNJYVWzuMaQnUsStN0YCj30013zauoSXokBF8N3vttIQD8FZ2p18
PVEkEwW3qGsOx66ZCGGxHyUkZ19fqulMIOPaCyu87DLHuKjBnUPuMpA6r+yFJBhSH2WoFBz42Dju
UtHz67CFtLCQwd9O9rooS56C+jJoGESP3+ll9CsZqE+JOb1hicc1qa48XV1KPLbn9RajveMqQDUA
ya5h1ezM0TNxXThpTxDFVKnx16wNMYgPfC94BJy/1clqc5IkCFMRbl23Ofr6FaIX27R+DIsXBepq
yVD43XS6rWa32pU8REr92z1nqHyvgR014/qUjAmH217o0jiIl5Nj41I6ozmMpj9WYMFtWSrVmxG3
GL34szRovdqU5Fsboxeg94MtO0IMnhtwy6hg7GuUJWaTHLM8F3PYe/w2vVISOa9Sut8MIYFVJpP3
hAoNct97CmloKKw3sTh49nqePUJl6t8TdWd2Smnh4nmnSPGB/jItiWgHhPyE/9KGF944U+Qnbxe8
VWbGLkxk4ZOp6GCAlKsdKM/d2Ir99Gkaidp3ilH79S7SmVVppCR7Ku+fy/LVySQX4l3qfaPfz7UW
OR3bCcA1s8Jf85ZogVz3SBvrZ3EvCn07aDOLtBErreui9XW/O8hXYFK+J+BIvOQoeoPNuk7P0kQr
RazIuhcnSf78LkHzSHjYwWhZkSVTi+abGe9faOc6yJForSafJqNgHInaZ0XMbzL+XL0CdlIni2Zl
OiwAKYFyi6xaGPxoXiwbSrsEC+/bwnUGK0ro7OBXAlkVXVfJkfn1tcxLmZbF23Bu6p+AFB3TtEGt
2WIOLJ+Vfwjvl6nriSvCY0hWjVe2mQuPoP8yvQRsBbmK/0wENK/cE3GIs4EoxGNDeClHr968wLJ9
Vd6xlXwUhC761mKej0bOZB/rWfU1lJgAychEJ5N4GSai9S6TLwFPxhJy+365GUFbttI7nqmkIcKW
FB2lFcneptCF7XhGCy6BonnypBMdk3Yd4+cvoY+RJQ15pacD67IA2QmhMzcmczuM9sQvRBVHpnCL
1xq71N85JqqndrEltvk6/ylwUc/DpbledAFVBaEmPqf8XEah1obhXyfYc8sqtPrVEEY4LpI4zh1b
VoPRN1kp1GQnWfhmKaDCcSPr/hcmTedLlWpvqj+hzs2k2n6B4u48hjan16LD5HLqnLeT++SMsd9t
9gkXW8gdLlh/D084/MxVUKBVV+q0CIIrU+ClHKhceHV8+bw6hryeAcNI2Yg1d1jA5d+ph4v1fL5I
t4Tzop3SuNkntnoHPI5WIgM/7Siy/vQD5Plb9xM0fpHqTyCOhX7Qh2enXkuD4/0FWKy/TfFLKjEe
MApP/Wjvv/2xQyctOACqFdr/jRfloIfOjaT6pzcOfqJi36HLXYkjY63B+xFrpRpue+rgepkRQ1xJ
U6VlEvrLQjahjc/XDOuvk+r9/YNx2Csp7RqdhnDzi9fn7LcH+tlLWVQT7nAjNaQtnxiaYti+r5IY
FQLX4XMRw3STp3t7wJ+MYA1S1rnwwVVuY2XShbnii+StxdIOiq0wAJrWI7Duo39m55SBmIBTjrN3
t8sdeZUhiH7imOPvh6sWSBGmaBBl0+CtRj1weDDcWp7Hul2gmKFiR/OOoMHy4u1VZTkqJaTjaKet
MVhiS8tTvWJGkv9LYiV6+QBKqNeKrs3X91QKiSQPNrYbFyP9tJOsiBjJO7W8ObTU4ER03Cl7UbnC
n/E4T8V3mOYeE5RV4Rn0n7vXqtGxdRxJYzVv/nFtfSmIARte0F0Tcjfs4f/TITSjPyKLgv2FFsD8
HSqonWI3iDppCfOrkS7/Q9CGFjBxUprTPDNt+4mz9gi3FSi1hvcprSaJ8SbENDIgP2AiowEtGg88
awM/QMF7t9DDUa18GnsqhnyV4js3VycHt0SBhYdoPX9hwNkFRxOZlNkuSDZ+AK2mAG6R4PatSkcr
w1/Tjhi7AaLMg4NCHp1wE7Wm1dXcZuH8P0cTciSoi3GjvY8B5jvP57EdcvCSgaIrkmkM1ETLzQab
fifoUZaOVUeiTQAA6GyuzlQiuNM2vUrc+Totzwp9+VPLCVcd8mSVkBF7GY/Fv2HcOZ3qJCBRHIvm
H3Ba/OguODuXzdwwxosGRbJyV9q1sio08c36QZEQmc3u7cwhQjC1D33NE9VrqsOT+K+ei7+8AZfo
BEZmLIVW/G+neEtmSEipT1zAil1CzMtHYXrFajH+VIdSh3o2rb82DUoVM8AcSSEyXcUz8neDDSCU
e0jMfLGaDpMhCoiCVb6WsnWVFDl3qEvdBXrcSpqOmvPztDsf6ANreQ6tbrxEJIxTWUocLeMkQqxH
FZpkUm6vzIVg+Hxgr97yVzjWJNTtGuY7nf4iapQB0gtIs8yNx4VQ/O7RdVSkunMpo3ajWOUJSvME
5rXO06b0vcNCepP6pEsW/Aq8jNLcN/die1WOc7PquOugojH0aDEDB4/kEvwXH/6ow+TFH4A53/F2
rB8rS/vEXEd2OOeP6YOkGJJaaGxiKxpRXOhnja8jey3YDqegUbGyDKo9KZ02I9DRVGMbNsIoetK9
XTJoyb1oXlpAQumxmRgnAhBBH2vRgLVtN4KTUKjL0InY3Y17paYGj0UL3U8hy96qulvY+nrtbEAQ
dzdsoTCmiOiT3EFeg6DYA51D8ly39/kwrGQCm22SKQd6VpuKyUlwMAIV/BQrs7lFZYVXxLmKx2C4
0Yq8AmusrTV6ib+Y9MuZsjBgEMUbXwFDkK/c4ujYGHI+u2FnLtRGfQg0378fvxIbT0fKXqUxkVWa
7jBu/z+LcJQXRh7zULWFcdiDR8NXr8+8bRQoJasUmQo4ZNrNS/aPcmcLecFYCralI9qUbixoy/x7
e7DlNVjLzKuVgIgQMcd4p35JtKNw1uAMo22+TakhMnvWCep2JsPLe8ePyUsJAlYkws7hVVXsZFrw
N35Que8NGshwSktrW1SQ3D6Wj1k6ugIFmcj6CoOmBNvkJcQcPU9y0BVBE1+ObHItEFE31Z3fT822
cet4z5Sqxn58gvAmgwUTQzJw+G0j+8cF0Kj5OK+sdLzShaqkpTUjqVUFNDSokcUx4iDVWOSPlrQB
N+YAXsdA5dU6m3n66OhdfbNY6Ckx7C9ceRLIVqbP0YH0sQj2lP7AR3qLL48S/P2Evp6JYeCX5ecd
dUFFQu0g348CVXkRU8ng/buWJ1T02QDEFfsHFOaKrzxWDxJZFYkxIaP1IWrZ8P1Stay3773iSPde
c1B6aPVELJXtzGXOS8XUf/aZq95g3tHcgrll588SsWkvXSFEC42EXf3VBwwgXqFE6WdPQVSVqDo0
ZsbUWhfMmyTMqFQCpRYv8qdXvY9tMrb7dN5yS6LZwHaJcsIJ6HPkxviVJwG5Aua+bI7wbtQiK6d8
zwW6rw/j+LhHdki19ToBg5vBoX25jhTuM+mUWbCXg53pFzXvfMEmTQlWLJGLLkNpqItO/aofhhXM
AhgJ7PpKRcptMizByBKY0yGtjBPo5PBd3aA4nVszc4D3AF4B7mMUaT3OwS3Uy8b0R7uI9pv9v1XB
PNpijIR2HGxF4cP9fC8oAlOkRW1p1jhzlA5+mZRiwyngTN6b/u4fKGPX58db1g4USrIEJ4d53bOZ
SfQVfPMvqTB05c1NQL7oK29ENSo7W+v/vj2uwFk90p9a5+pgfncNeoZ52AyV7QKZ76SWhKD860Jt
WauoCyzyJPmMhPTuO6WLB5+c9uFkxX2YZqizIVzkXnVxZfs+g2HmVDdBd6d5DbL4V13IB7psJZLi
XQWypNZ3LdSl+UAeV0nchD7kepW5+CyacV1E+ZrlGx294K0E8zbT5LLEOGF+Gs86zDJHTkyBinrZ
1GyeNe6XIY2QL/69iGUKrPb1MVHzVgiBoU2ocMfJFrCeg6CbEvXQSQY1hE5MoFgUpux4IMdHSFUJ
j1sYfwCI5w90z9371dVuzHz/jmS2UP0YwkujxspcmPQLVRosbKZTJcE9V4m/XRpE+nYW5A3pNWTr
b8YGb6fg6juvX+jOWnEqgmNleiuCxikD6QZdNerUUAfk/57so1YteuTGoHjGFfXhMeQIOz+KWFdS
4QzuVNzI2pf065OoS28NStQSED1nxA+MQQnFx13FhXGZsZVf2gdPMKR79Ecjq/9kUOzYoCWrLCgd
Yc2EJJl4jIC37GlUrP9vcPCUbx5C+TrrqA6Hb4Eqs4d9z6akFXGXHj++lAAs2MY2WsfhvkXtFEF1
06Lw/En2kCZPc3hwhSqF/nO4QhdKPWJTbBB7xfU2o3uCQEYV7KYFwpWSkqry4SfWHMBWHbalmssX
NYsJagX3gnCCa51GkTdzACH3s+k+AOJNWuRp0MH1jE+Opk2gt0W5QRAng4Bfov3Mh7LaATLtNQ39
S7H9m9i/cgBKFmLMxGYu00oIq4zMfdb9pgikH+1y1m/2JlUHEpCqQ1ibiqV3Nbf9mZ41Rg0pTArO
6SSRPQlUN0ZPbQQnYRFi4utWyLibiDI9vDSfv8A3XKjHOX1j1YuPJHkrtjKXDHdbpTpiza7MR9iP
5Q93mhaev6sdGkY4h/C1vk2a31QtUQHNHRahJjKHiaTigw5anLQKJcuKf5+IfbqiMAFLhKKq6mvh
Q5SvRJEeYOUZh9iVUQkhCIGGfmtyPVZMgaXKL20WQoqun3rCFnw20l4fUyH2Qq9ocJineAZHGG54
paSeBTJZn7SkN0emKqciscDxn5KMysF6O/jlO59SoAky2v+7E5mhJFxNlBJ5dAqy0qiAEamaHilr
Qc9nQLnTl7hBa6/Pk+wV1V1CrwGXDyIGRskkEkdKHrWNmVNLChQtBosTcjkoWOqZ7nfyqEiS3cHl
srfV6SA5xyJF1ugfsdgDMT5qwb96RDnPukD2WLrOZZ2Qou1g9mW0RgO9yqMt9ZzJUEHO4c/bTtts
PU1JL9VryHTsS18dNEIrlfka6b5qmwG9DqeXteb3UV8Q2fLdx2c20R6luD0BSLo4Q83K0Bgvb32Q
J+3aRrNiDd+ANXgU7FL1qkMCvKm/RRi4xLuIQGrmaGoUimpRitNJro5KOnWSx7k4FgLp4s5/d+V1
/paQYRxN0QPUAC4JqlGNFOMydqdJWjnE0LDqK+VybkaZti5nQIXo5xPFyFqohxiNBLJGk18nrsoP
ZDE74P9AFX9eKdmNWQ3TmAkWAVKj2clb20xxqOAuC1+RTJ/KQ3srN6yuKodI2+PaaHPw87VXwi5R
5SUnVl3Ov+LndxHq+Qp5ISb7xJphDrDUC3ppU644mFCv9ZN7nWqbuUGMPP31X5RCHE/9hAaNDPSx
qi5Lv6GzMOHRRbyBfckI/HmfeQC+tNjH08IZonygnergpxmIJ95jGYwXsQjX9jMr2aCRjmEi6ob6
WXL+JBvooQ2vPaMIymSfGxYgoywwoDS8WUqF73mXWGFh8Y8pnFyMjyjepmDkuSYgj2B155mWcuU6
dpy8I7oDAFdMk7rM9tgbfiJ0eQ6sllylwa38HWA7Vq2a+4bWXnXCVpO+PS3EQwTV2ZciDataCXCB
IAoInjPzCdoXxWuGadXy7fMZVYtES9V/f3brCtMMUI3plRsNIuWAkI+UlcU3Wt0GM2s5F9HZpeXM
UIQjOIXXDnkjU6L7+U2FhvFYnJ7MwvIlGvsQj/SSRcllH2eRJdRcgJLVz07HSJN5ByAISE4Y05ao
kRTpouvuh8LCpLVdkZRRHKlOkpfZdQJOABNfdx9u/Eg6bVgltdbsV+QxZ5ZbBb3182CP4FLn1AAN
EmQU0aAVujjr89jNq83i8SuGE+CYxjM1rF1+SPPhDPjYo3jIllhMw5mdOlAyi3w427fvWQ7CzUeA
mddpjsr6KVe9DxyvA8YZYYMjblx0gweQKcTXi+ZgodI0ajUskOgPWV1/Y5RBHgrAgA+dqoyGJ+tF
w1sUMO9yLPjcra0d2Ta95wbS5TRRDmEnZN/Q5JAe8+7J9K/94zlpBeSv/80oRTEL2JDFuJkj0E2p
8hVfUwEzbdtV1lPUdff0Of4r1MaTGizrgBOzPJUBJMQ46nQDkpw3/YhoXpe++Obd0QQT7LPEkZv+
e54Fo8vOUM+rFLQG3Q7xfQnGU3bdg9DA5ZlwBpQOOMkvsXTMQh1VWG3/n/p1GFwf+exvFPIZdmzT
CEzrblPNnyvMdwQGtoDut1Dv5Q54VrfQYp83cheeixMfKD2xmiv27DNT/n3o1We2G/acqcMh2Rg5
VaYGAg/1rCHrenCrlzGtlnB6run+AhmfwigpqwZGS0QL4SHIhb5dLzQaBC1vfJITKYlRdOiU7BIy
H8mFQp52P2jDj94qIz9kvzkXAjqirzBbKa0haeW4Nea9TBDQIPton0rqPsELb1/Q8aN5KCswVxP1
XfdXp1B28/diCYzGUsFyAlXLb/rYAQHqHlKlOxVuU1AsEKExoYYeccX2Ru2bvW+U2eYYbWRedUre
g9xzQXcoOsB4wP7Lss8gYHzSi5CVcnhJ1YX8Lgj+BKFl8S12PV+V9yW5sMqXC7A+eUpZdIJVmIs8
jBqwPbsR4lWogRf+Y9pLsuGOo3cEhV/lPtAiwF4jcoSgJm5jZ+0Djfh2toTDTTtSnMJmm/4489P6
9AYAihKzEnpyoJTd4icOJ9CRovUhxyP1tiETiV1FxPXKtI8160FU/7P45uiFcIH3quO5L/Gm4RFF
i7i+gl4GMP7iV1JNeHB8F7GGN5yDYACAEkOsrM6ev2oz4/ldtVP49iPLYixyEFF4l3jPr8juri4o
sYqOyG0/06lY4gfZYqzk78kNo9uKMyrKtsQhj7E5q3+YPqasLVK0W01wnewIhEmJSa4bexpYNxbB
U+LbPAetEbBxhOJvTSJojHNg60LRuxwhfT6s634au2dA3NvT8fQsUB4VWsaEIK7GwoAmpeRb/4Sw
U/CGN2vQVHBakM+B+aff7377gD85kIAee0mCiphqT6n/vmrs3HVCGK5v0+hYwg/VOBr0k48kBS80
2u1jf900wQziATyuzM7D9FVC7M3gnS6WjUv8eJua2TvbqtiWBeImw9TGXWopaxwbvWHCBaKknhb9
SY2JmRxSI/vV7IFILqByC6o2TTcg5LHUaqpPOg6AhA8qGu/dR4I2mLcTilyf31Yc4BULpzbHwdvN
iooiWSTo6MkEOjH6ag4VG4xNnSJFICs9zdT7CXAaFfF4aVRSwHm6s6c+DRyz9Cblwmas2ewnyGVC
cWpHq767wtXheGFc7DiTvel172EKu+zU5/eQVih9zqvdMhOX7W//aYEhhPtG0OApajr+kzQ/VHtq
dFeVke5LAR2MpKzU3kvyrjb+QnxjTTGsAnN5x9nva2IuYECrQozQ2BaOX/owbYYWMGW50x9P0keL
OXeKr5jE8ZxTVThBKL5TH/CFlTxcCqaZdHhea4QhZgbFsZ9D7lMu9WPoKJu9f4xg3ShHd+1gfsv0
ReqURAtwDnJX1Mzhq26WovZ9q8rF5tq5pzMMjWYS0+z3+L6pbBDE9tKOEgb+5vIqQ2sTzm8G8oq/
MkvTLmZ+9tmISU77NEAr3s65VYAYflY7PohsxUG/YCOEllg+V0Kyu3vtrJD3/w8sD3+JakvnSo5Q
/UFjoKRgk1yogIlG3IOCO0UTwx5xocOXI28MktrUzpZwSljsMUt263mUdG5Mc2irNHG70CgP8d2D
JU2zfWlXkiX0PJ4p9dtg6ttGmbYyK9ANTmZET5fImunKzK8C9+JVeYF5MQrJOobN1oQnEvYYNkAX
DArpmgZCb4PTeD4sU6zJre19fzlAOwvbHaPs3ABYSTOs3nilkiQfRN2f+oFS5xr4dWcB6dsZ2alQ
rqavgoeHULKaYI3V7Zy85yp3SV/J60KhiH+zAS9OYSLfALpMERmj7bZ3vJ9TdBNblHHb0H5mWHw5
4U8FFkUYh5a3BMMxKzBf33+MGxMpK5/IwQjN8+138uy++cUZ/ovLgXO5QgjVlb+dG9mrJ3n8NOJP
oC8ZCVfeRlOQdDBd/2MkxUU6w95tcsrFbaBGkUt9CUR9+Bx6MSBAErD++OPRrx7jH5j7zrCmtMCE
0T+636TjlrrQAt5ayFee7GQBx9f8QcPPLd3fWq+gfQMWKLj/jp8viFpIdLXG/UJ+oLnB6KAcK9OZ
WRcyeyu08E3QvHMGTdhNpjVqtM288a9Xw1ofMwuq3KcYHJKTDzg4RZsTWs+lsQSZQ3tXct6pQIcC
ClA7A1ZFVmB9ICjNs36MdNu0hgYy29qWkGebdnc8edBJCUfA4DlKS4p83UuX7E92nb4hmBH/S6QY
oWtsekUyFD6/O1PoYv5FxILZ+o6EPWxX0lt+DUVKTwVXCo+KO6JV/wS7t71r/jvZVn0jZLUrelOs
v81ZgBxVQyyhgBxSSIKg0YNGy2VbF68X1p8y/AW+Ezcx8hZiU9/GuENERB6tg4LSDRIwCl1PaQS1
k1PAqWg+EdSP4AfQ3TlWXZpggFMJBlqv8tkjnvH3EA64v5b2SLFgmkq1UNw37/+uVy4XetC0DO7b
goFS4Qp86yqUsmWo9jrGQt4c6qgcu9UX/zWlV/rLuMld/ZEjfiuETHKjCwVefOuWDhgirAmDHLKU
pP71PkeA2MSqwIilmxfSX209ZJydpefGuYUDmx6p7SV6MlJrqrA2ZUAEByuqkq/tp+G5YZU4dbX0
ehwiaejzu74+2jhRCtkLgLdYI07chfrHQPJrGt5o12TgoGC5IZMURXrI8iQWNPPgBNJNTSHKTrMP
Yq8HcLobqXcCGk/3tqP9wAEggDuijN3/coIblCUl8XJvKTb9B1snzuUVuk021uVAOUskDU++NWSK
kd4TP/Wpq1i22pVPhp5m2YOa9dNnqElAPWQvApYTAMJiM69mw9S36jO71PCQfvTodpeL1eoaWEP0
BMApUQqikPcElHI3zEMAn5k4OxjL5kFxad8zELUT26/Kr3pJreeVtGhhXeFwWtKw4DQKj04++gPX
BsXD7VL+zVhLyGY62HtxEhqteosZ3wTa9xR109xvfIeSEAarifnsRh2sUn4Jg1QW2n5CdREkyAdG
DwFpJXcE42K5yVXBDIVUxI33BEBqoyJ4oND/OYrVcnx/KPg+S7xnOCG6t6GNpT+VBkwxTpGwyUtL
kId7CeJcPISRROsa4ej+4MdH2KqYKCckfd1Bmg/GlP53+VjX/GAl6tKV7CMwTgpUDNPvaPxcfQB6
kkZl3ABbaVu3eKYWqkadtJ7S4qstbxhKR9CU8krPT88HCZeW5ykw6mTzm2ym7H2r26Agpd+oHWjM
xUcUxAAepRd3gjwqPzxavwDgGj4I5hGLs90aAM0dZ7ZqZef4nGlnG4Zc4jUyfdHwQGnvMuttOXas
0SzRjdixMGkwKPsW0crQq7p6x6nCBmICaShdEXqQBUkxf87KvBKKEtq69sN3Tb+dKfaLJfs20iLN
GUNrtOo26EFk/FiSU2RvOeONGt72ZwzUT4zX4roI68C9eKFcK++sNmhzYTMWI2vdPhLedSgXPSoK
73u9f955UGTg/stKp4ksJgqdd9IoO6CnwPwwgMvY7ptlyMSbywotb6yZJ+mYP+sW2sFDBtNpSb1m
2JUPagtOBqFkg+6G/g9uScGVUGglI7qEeSWErO8aj6tr1wjavH4mdBM/RkHWfdWUoYrLqv3/dXtX
PHrQ2338Oc9+mCtUiAWAf9M0jtx2IjwTLw48gqikwmAOuolMBt6/POxfbFjt5IdQ86g6LzbEFi3G
cdJRwg1LYASjSJPX+LObIhaJNvO6y59oMbuY6HOcrp9RSn4g4BAUaWs4s0JdaBICkYRHwWxtBo4z
ACAAH6wN7KvyiEzj/1OMhOg+eyc+1yLkni3NcKewv5PrZgCQhGT2P+nKh+6F0DeHDDCiGRVuLzUE
eKEFguBwbY327tz9LD59jHlfR/f92mMrkODMr4Ag9xmCDfF/M0xqljZtU2Hmy3VBoSgDbXt72hUi
qdsS3aHHyyz0mxcVQuoylO219YIivq0mXJMDyt8uQRD43bQDfbngvET4ukdQtzo30tlUur0HsS+/
rgB/BLh3e6mZRqxRrbL8ywngOhETXtD8+wAhOdYCln/jUzOr5P4JFjFu7evrXxGtps5yclKa4HKk
2ZXNsShU/2OqhFhivQvaudlHKo3zaTYKosNq+GUQD1ekOvjwCD+G62vdZgTSRnrWydVrWZtOtWUo
0WIbntwOc+bEJma+GTtDm+Cnnws3xixrZR1mAMTvJ0gOcPeZ61Fri0Pf1tvZHycxfPZb11Yv0gy4
jgGOM7e52SyCgtg02uyUJe3eao0Jifm0GMpm5zSzIk6hVdiSFYRVnRz2gSzzE83OxxIl7onI0Hzn
63LM4jm0QC9DRsFyMmsGNrA2AqF9jmCgiF5zL3J0Tnh1vMG0RK6lW51aNI9Ozij2DNLuHoY1j99C
lOsub783ZEatOjcGfvn0PH99JKoMWuUHt4za7RhGhNZciki87LWHxlviDfbpA3BpyQP8fM4vaVvO
ifDADD8X+Eh1M72SKrvOpGw5HJOC8q18V5Lmv9Fc3Gi6Gkg4Svwu+tp0ldd8Oqym0qApIq6Clsfs
IC4cASr4lXQMSbwPXBlBoYsvXyrFdAdEclz5scUyKYGaBWVKuYISVf1um5XJDEuMonmLCZ8DWcMe
p9Xfln9I0+FbdNvP7+QQrl98XGq2x69uDBXcVayun2haWWq5g3Z1Uvk0uuu+78LFMnnyvP2HI07U
A2b3cRqXx1cbBZIBZ0a/J9DuEOivVZzpWt02STZha1d1VAZMqsJZCQz6B9ABOlBINdRyqWqQGbPB
CYBM2T4H5WiSy9Os2uQbrVnqis/qpM4Ny0wd0abO1JCS+lfgRD6Drif+XJJRcm2NaX4ZUq0aHGhR
1fAxsdXJN6wZ9iQ258Jwp4n/vQkxQglQ98RryzHHCdlB0MQGLmghXg074GPmzjue7/OOyodOcjyh
47t1Ork7TKkVUaBYiIjbZj0efGMJdqbWOkKjk2ZUQbpuIG4yMY2a9xdtyWHuOAOzYAL6zXF6PEye
XX5vZ6FEeWzQM8lIpRpGQ2A6Q3b/qdaC5ymAHIfQOKV8/Aph1NHp1RFDrRH42revE9fWl0IW2yGH
1aZFFkX60dYpSaRootZosCtZgfy99hps44TS1w2E2d9w9jpWkeDa8urRFPFBLpN/b9zGqvxYBdou
YDHC2qAzSuQhKsBpj+GA6VhDwmKfesJd+lXWoRfueedY0D7/YV4ZsvOprdbeLYxAuIBy54LbByCi
sbUUfv7SzSE8Vn6VvnVFEJeUSTbkgwr9J6BnA6eFUnw5FfYJ1RWFcQtfX0N5qTT8k4obgWXcxZEe
dXAMFznNzLeXlmRuqcHyQ6QR1A1MADImFeqiXynzg3poOAQslrJoX1EWwUwEe244jNyyFBlx8Krb
7Y4aaIH2uKZ9PRnOchGOgwSjC4xaGpAfjoSoU28ifrVhDoq4loExYTPTMDW3sMIjhaopUWPCwNnR
CiCbuQZEl1z8Y6mQCbPL3+hmXZQ+zwupbe7XFQ9VtxFyztMQIeTsSYf/T3ovBW9XM51qpDM75Gtr
ifQFGOmxBuDV3O/Zolap+ck4EhfaxC+KmOhVL7pz95etmO1/Ttjf9EwmCAiCnjCxlZ3Ssa7jCO8y
np5217Jk2Ko26AwYRORg/SYOa9X44YeDZ4iCHf14Uh++CS6NVy1DYliFrem+D898icfn+fu4HkJc
n9fATu99CTSMvyiwZVlPi0kwdeSWs76F7Ra0vzoZn4T/o0YwVUpIdxVoeWppOBmccd8y/m29zMNN
haHfO2YEaHxfPplBUCIMLOTYz0fiQN42s/PC0ydA7ZLyhZUEPmei4rK7rnkqDe7YOJ49vHLGBJOs
dTIUuGwrXZxkQSRf88aQ8yYzNTn9sAAF7AP0uUa8XqQy/j+dBN+jerPJ52XzzAUSGNDIYdUUooHf
veM+qKPV9CXRHDHkAerPH4F/W6igPTR12S7dQUQoq4w3g20iqJcGR++xp1Lz8Cdeot4W6ODShlZb
a8StIEwS1+JQv+3tK7ypI+iAP6Gr/GMQ2qciuCs6MYtBE1CmkEHe4eJqVzr+FCyO+bAPBqEpQ+vE
r36gd6f2PI4jmv7rGj8hzwltJFAbdxejYXadldD0wN1fraGpJPEaJ15UKfXlw53vRX86OMoPnAyH
dFFu19GzD2qHHBiF3nMe2KE+PktQ3zHPku9drewP6rBSMrI4Qmi+hhMcxRfIwhy9u+3dXhSJEgZI
l+0btHIT5lHOr/vOac8NWqIQ+voao/usDjFdnyV2EE5F+eg26VF7hUIv+PKZ3UopkSQPFn5wjHRO
s4uL5kxSfU/oPcyUdiuugbS2RFd+VS0hwi7Ln0NRIOj92dPDaDWhtKgHSsQ4o8eiKvTGcfrX51wy
aCRcNBqfIXy0bdnQMb2jTE41lDvhGjzstbq1LcXSYTSh36YCsYYS96zqbXkr00p0DGpQbzO3zd9A
l+52B5f2vbJqO8tjbnQD4iEDq86TgjW7gGv7kso2TDfoba0jYG1vYBodEDWxVUw1yQOhLNg7p/Rc
4gey1vPKnyhuBhF8HkMVeubf6svczEcU9r8/Z9LKvCPi1J8R9i8taqqn10c5KxwXJGUfGRonnhsk
rsbKw2xIXKW/CWD6R1/B/JFEGJ0i9CrhWWArCFBTSSnyb2+mtT/EXHDc77htCFqbE1p6Vt/Sg42G
IUYsHOVPK36oaD2xVWa55b6xt79aSq6ZGc4ZhFsWb92CMHL72nPCYgBOy/VPJSTLDzzq3iqnBXK7
kJxqzA+j1J+lnMxP6q0sueUoyCnN5hKu0Fkz2cUgy/8gPG63bClv3KabS3IFibwd94Lnvi7iNYG2
MQhdpW0CYbmwXtWOwy07pqAPRnMVFu1h24VIOZj5W0G9/1w29In8yZx2yuBOhEE8fmR8pNYtQfRw
SYYKbIqnKEH60eb+S1KdaBrZF5DtiuTao35+mRMIVwYCimaMh/wfq70Ynxkr+Lf+N0VvuV0SUpwq
qKs55kCy5yWQ45Jv0C68rh74W67bH8DDjaTcNgByLJj4svCToId5P5hm17eMkZL34chMPiyb5lwJ
c5e6qneY/UH7J+hn51qjUSL8TTpIals8VvSSw+ozujCrekHvtAhw+gKWYKGkQIsowv6hQJAy1Kua
qN60QNEB3P/5fHxbfZMDl+wSD950wYkZHxHBJQdyRuHFgzxqOm204z5gScQD9VHXJdNJehdQr1Q7
lXhtzemMiYQf8BCm2ksAUwI4Z6XvU6N78cVbPFvoQVUeztR8ZSuvWtqOplyKreTH94OZYfYvxj7y
5yR1XpbPRsnz5PK+yfbQV5V27g5x5gfh5OMHUTC97KICTr4VnsV6c8c4N18EDT6eBsxVOxm5XVQE
UHKT7dfEvWIBpyBxa+TuJfSSgCeTX1DVvfdl13Jf+d/9f6joyZXZgbNJsD9d6XCRmF+rbIQSjmZV
7WiXHwLoFmsXQ10hxPdHX3iPHfF8I3ANZiuEIxUhDXCXw7kjYaRxz/XoeUJ23JO0Tc688Lh7sFha
bVsL0A9ALQ5fZ4h7oSKI60M97pvP3tRDBRuZskIiLBHejFerrfBi0zf9yhxsnapvQ4v4iTevtBkw
VF7svAHncgmNiOBuLBzRpU7scaEz0M596hn4k303XedW8Ztuci9ryf70nbBsI+vMyRiwxo/Ti2va
NDWRhOnfOE9ueLRNxFJ2DIzc9apEKZXJLzWle3AWE6FlCZ9qYB0RqVmxDcW7qilhcXjlKRbkzPAQ
Et17KYpxKzHYjq/vyPrwkXKeiMQ5fddTSjS/7yV+LWfYdO7NBHq0h5HtLWNcBVJ1yACvLDeKs5NR
4t3qTKkGzU5s1nC4h1iBuuvVVB5YuwnRiKJ5UZ/f4suO1THXa1lr8Si2IbRe9l72hPjbHIyNa5bH
ySgLsvKnwQQsPlkPDFQRhUmlsv7OLPRqyvnAQ4TrarVyJlunyKUea990G29aUT5cE2baYz9Taw/Y
C8Wi23eOvm3HXfidrDAjk269YCXUiaObonrg8bJ4SGKe9jM4SOVlr7p2eN5ONmjMaQ1EfGEgIuv3
1CHZ+FpcU/fRQFRvj0c+0IH2UE8m6HzfvAQAkLNhNkWif7gPPLNUfpaC8CzzfjaJt+EHpL5L6VR5
qkWC1Lh8DsJMqT0XWhw3AvAKg4iKq1Sl+oTVDRwqKxaidEudkM4rxJwcOdZTmSQ6wJw8OX9dLcmK
ug//RgIkiEn9X4TgzzVw/HDOu3VAcCqbSVEPWgLFSlG5LdcN7jCKQSYeeier6NZ7vhlNQKkbZ+Dp
5ybD9QhqdHgitwdqR7ThrapUnU6xM75oU42TE59QdBzM01Nt1SEBEs/sehEQpoV/pVHWJuxwc3ZS
ofAWCNdj9yirnH00Sdf/GZliC6UXr0X8+ev0zEqg0onSefJqOF1nEKOwsM9wUUaG8v87hopRUcAj
ZqPH43j2MR0fRHgOb/t9hIabJ6qmq+oxV0rmSvnJvnYwykgoQe7omTFA7zk7flcq43hwoAtDKhzK
sh0vIureCzxnswRoTEfxYUQtqPaFqLZzX9hdGA7BLIpV11JLABePi/bd736AG4/jnINdxHpll7Cq
6qBB1SZS5t2wxBFk97ImsCjMUhJVHEf1JSSKyAWcHhxMLyegcEDlRjCx0mC11/2lHBg+o4sTl155
dPIp41QCFawbXPZo9ejx6u98SYE/rZ8pMTX853+lWMI7LAFnqhj1EGh+LPfHuLrEkUvBBPw2M26f
8VkbMTOpaS7VHCNV8wo4BM+b9MJV/D+mOc2EKoJgHjbe5+7R2DbzRpazTsr2ARnB6Ge1smWfQHrL
a9Dc+5kuxO5XqZsDxAsr2uFOWQ8poP7XhXoMRjNHrFl8hJ7QvHaYZxFCp7DPQ1A03r6tYJgsik4/
sUR0dCn2hqOk0ZGS+SWL6g34Su9xgMFFts8+SOQkmPTaLJH3htJdT52Ho6ESQnl8SyMyaVnZc7C1
yKGm78sXkQCJ4Bz28xujizSMFZ+vZtcS4D3xyBg7U+oAo/dYqO0co31XHFxUtXnqjCF5gN/BlCJ0
7yEIC41al2FLlRaV8+qPkmxMWuYPj/zY2SXRSjf+q/fHhOOebaizKEFBdXrf1JX1noIQ7VNL5nz0
LDso0Iwc1kStQJ1/UjCmHSx1kL/Ab69X9MlF4YZSnMTfbpdoaMgaHGUU7IQSoz/+DavgZOnrOE7H
UzkmqX8SKibTKP2pwB3ga/ruZuMPbN8eYGIOlP0oYtdqg9jCnRtatndo+5swg0wCrJK43pzGX9Ew
Oft8tEFOdowvf9zLKh9/LaKFjRX5WZXiKJC7LIjvy/6GeBvDdnDzSnptog6jZnVqJpb+4YnfVo8f
PA6ycHZzBd3BwIBIgcjkWyZuWSx81JgxT0ZujpKlKQGcrcxLibVf9NaPJi6fRpln0NNxMEth59CF
XJIDB6NApVWQipIGPzC2jWlTsK542jz/X23r1PbqZrvvhwgW+15YaMUmyGr/dlDdCtgklRG/ZLkM
egj4pSTs1sw8iJUFPTIesOmCFgEn6c+z7YGkAFKgMPcfgb1m5HO9o3ApDhKgLg56iRSp3zk8J9ct
ObK9/l6ozHpQC/jn17+DEud3E1hqzOT3+55I5ng40s+/020kpXFyQCCs4EJE0Rw42b/bzFia73kJ
0wqMzbrmHj6ImlvZXuXngt8usEI6NTyWQQGzcaq2Irv2X1mIAPSblgD7tFf6r6DeIuJv94omCpdD
BJ3odI+CnZtm4gqgyUhdLrD1m1oNhTJ+y5jbpa/YpXGn0II+GVtrsE2hzHiwSmbbICg/Qc5Sf7iW
5dWC8+3lY1LHuwKukmDdjFyJDJ7TlmUee/fQto72xx2+3p2TPjsVEIFmnrjSbCAR9gFsefgwM4v4
7cKm3a+TtlDzbS7olYZTwHebWf9Pby3J0SmDGlEg5uJHZ5UPgqMcY7gj7l05wKivNakdv0XJF01y
hp9vjNiIOrk64noZNYJUOSK0vXvrN4oTL0Lq4+yq/xbhzDTCUtmU9C97xuX+F51pFWKSmzpwvBdF
DbNyKZP11VS+glTHem63OssHhpQ74bvJIFf7CFqCBFqjF99JsDUQBAS889aM6IUbPpZzJE207pfO
uwaCNr7kAC5VgkmbQvdYjexGynXk7OlCPx44TjgUas/E0MYXAYB+V0iD4C8qt/sAGQOJ83yVHCXg
7xIsr828tyIxCdqW81hW18pYIuy0um1ZtkhDDhpj4DZPwA3MsYo4rY0eBnZHw66qkiNUvv9sUHKw
gGPz8tQKEJz57vP4kBrcKt42Finj2PxXIjyhkNMfQneVbf368hC4/Po4aZ4mKvoZWBGKZlJl9RxO
sdv2HET2u04RPE1zcQTJzoLc8uRNiBXJaGZIHJHIVL+T30p5ToDavJ07fuUujKMaIU5wllgm9b37
0lDTEsnmkjblmd2AJzoLbGRG/CSAZ+Y8S83J4ieo39w0kZ44TLPk++9C4Xu8XJGgSRmFaL4P+nK6
9qp95rmEYFAoq62+BS7fntyhIOoI5jZfFcwm9Issu0AMS9CIDii/itlJFxo2SWWiRLT3O6IVbnnP
05SgS3mUT9oUF7Lr6EipZ9Cx7CePjnEoOUEsrCrtG5Vq11yA117GH/EtTH54cYXhCgmxLhGmd2EL
Ih68R/o9yDz93BijaZTSbXZ+4F01FYBN6Im64uX78ScXzx4CMzYx02P6W9PrVtGJASBzcR6UJJZa
CIcK39fN9DSafkC5ETujCWKm50oxmpErQmBx5e9uJrOqucyPloih2LaaW036T+a0EE/4ZgodjlI5
wK66sX3pbRc2sXt63HlUaGEnwlBjlVfyiq2lHkoEuNp64NIJ1XyNLDqLgxOyZp19j+z1+KRuHjJ5
lapDU/iYIpQoqnFdpajWcZxBjTr1FxYXkuMavymj8IaKCCILUxCP0I3RntcbW+phpyweEqbTIMef
sddj73ujUwF5PVTRX2+cNC2erda5PrxRelSAh1k8bk7EOD7V0smLQxRgzncj+nr2zU6rkd5jtZBC
4zbFtx3DSpYfCucfpa20hCU65+ha0zK17N931/J6rY+z8dex2CDLf6UxnXqrZthhxNrB5G35UTt4
C7zri6I1/T8o8WHNTz/HZFE2LOYwt/sVriswOSotdRRqe/1yLvgQei6gdDxm9oR9kHZqCKvckTKF
HlgRzoZm5KTJg2gzSn4w50H5S4V00VQRMZ701tQK6JhU55GWWqe4JKy2sj0veody+CQkUIw4UEz+
tTO0NbjwoiWPztVrFTQcQdWxSyAgwNHbXV7h9fq9k7k3
`protect end_protected
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 16 | 94635 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eQ6nhT7GLP5MtXb+fBlbtE9CmT+npnamn5AXBYnTqfyjeOq6DAIwn6lQgTicnJ/7b8vS/pIqFxJ5
z65AlaBqqQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ePvgcUCXHdPAno8UEDNV9Pww4PHTFcoymZ491nBzb8ykBBL6o6NnFLuEgwxxviKgq0H7FWPEEF5y
7ZLIJXzda1ao2w72+vmvWH2EZiuCaN2z3rPNz+DrfsXwAzGb1OH4/Iehy3XvXtGI+zucH7hSsj6a
Sc9vBvA8dBIKfwHll8M=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
dQdlOZYXt9reqa5XybzLiaJAnC7PUoDuampMZ06ce/L/c63q0Q1KHkbmXMSMS6lB0N1ReSUcbWpj
LRlGAf54lf/vI0hCDUKC9qOMkfB3es/YMzriqQ5y3aqWB2iF40eOUGfvVNgW3SNszF46OzwxnUyy
6s7ae4HTuu6Oqwopmts=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ulzmoAatkfiB21vOKwcHgYwoa7BgjojqhgHDogYEawtrOHEVucioVeg/09JBXSV1+1CMAQE+o+xo
TYQoBFTxNbgb/B+5EnCgrZE1BiPORtAC5hOAj+HPBOOVm2mKA+QWDGunM6eHx7nJAgBSZg9T1kSP
eDygE/deOV+bjrO3rpg4lYTj1uDBc/gqNdTHFpKqxuyoxNx8OcaKnKuxzrW35ZhUKqACkp5kC+kG
KelDgsp53UW2XScy3KdDdEl006PI5yNCmgbk4S5iqeSNRQ7MMmIg6hix2Vt3lFOSl5HmwiP8A5BE
3f1x2AvKprXs7WCGiBI+NJqQkbQovB3T0ml7CA==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OGtogh+d5rJyPeZ2theFRbW3DATHEGeseww+Pf16AFQWeesc5Ps2gR6yhoEW66CSwrYkGfxk/+bn
0YrsH/HdQo70gaMKCUlaK5kI+6BRzwRPhe6gK2gUTfsBGgUKmCYt5HOyc6kfC3EA07RqlEl+KnDn
Z+Vweg+pNPisU/C5h2GCwOrJBgyua2qstCNZXCViH/oG68/+0B6OVtP6FsYMQ6Ffyj9IhOPe+Qzi
ntX+aTvvTuNEKh9H7VaMej/Av88br6g8iPHrBXcroKOfuGf4CpdRfQGJ4hrUodXcFZY69Z0DvEuI
tAtNz/BCE9leHmEs8edC31wz/asz8IjBnNwWrw==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
YN7C0KuBvDQtiCpi8qP6cS4kuAQsZBZ/QATwixLjifIRlVF4p+2Wq+vgTTFt5C76A6zV5MlkSu1P
De/LheUyN0bIlepSnrBXYk5bHJ/wtCKf2eL52S5bBQV4hSrTHSUf/DuCmWsO6nYRhOobBBh+wc+B
hQWuxi63uOR3qpe2uUP0VjroyoJ8au72wQAUSpLYpOGiUdHScchVkm4TZ481JZSNyPMnPorDUQZL
jGs3VLfQblegSlnSPlyLBb+vrttOFNzLspmj1i1Jv+DKfUhvr3MLnUyGGg4iqNgBY0huFW8bIOHG
f/mM6bayCz0lG2m/RFEyhjemIQSpglaRAHB99w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
hatu1u1ZcAW+FJ1F1qIzVd8M+jrmpd23JO0sQ8zKAqrAfC0aTwA8JxGlgNuDtl4dBtHwl4mPL3Ei
ukxGIC35Vheg5Tv8KRq3KVpRUJ0D+I07Zfu5iZSP73RgPlR5umqeXbcapJ10PYPrVHlAE4Gnshyz
+CebUS4gcBdkkpfJYIfEckmylDrwGt+FQeJdkNsFAWBLQszh9Inb6+tpsiHQrlG17OrmPQZnzvVy
UuSiuxJTj5TEorqFfTxjR63TpGOqBkqOX8Yo2cp0WVFWnDbTd/tuhUbgGinebdLp2RbY3cQfWtfo
pbfom9sGNKFME7KjcYn8afh99AGrEcQm9Wox/VDBiSl6W+C96ur0fJB6AedAyIclLQzOshQP9/PW
va7N3n7eY6P+TIyUTpZWWvofhx5hURk3b7PAlBtYfmApp5v2pu/qSrDenvFNOOmaEvmIkNgqHw2U
g+va71Eqc0spz5PAS9cTC5ipVbf0fCLhRyIwhr9QpmRJkqDzwD6W9+Nr6Rm+FNlhMZm/hmpUoFhV
w19PVNGraBy28H0eqHcuf8NGhAje/CrfD5XQAyCkD1mlbmwddwhHCDkXwmsj65p7yT2gNLy7bAGV
CMga9uCAoP7M+YP/kSaAFYEZN0REjug7BCN09kn71DzL+idq+l7oNkBa1Tp0ZeCVDOpdqGj2kNNw
XzM0Q+tu4U63XuK5fPLGEFyJy/BHYSsl4j/ox6UzimytSMkvF10/nacuK83L2DGZTj6ZOessuNQY
GNw3F+kBSZCJcIUcKm462c+XifZXUm9LTHO3iDBTodK2pz4a0pT5KNBHTw72mbc7+MfPkZPtz+Aw
km3UzPP6cX/I+s8RIGQiJhZy2wXyU+FOsYt+4cu4G8sMOAMlNyX1OUJrjRN1V3Ip7olYSZ2ZWZNJ
582gpngwHypkR1Q3q/RAmpH4mvSSp9gT7dE5Pe2fSZw2Bjo5UhhpzTFVNqFHyCsOH4EIwau9d1fa
3yj3F5Dyk36moL2VpEqBC81ZYAOICrjqlVmAjVkD9Rg4IRDK+BgfZpJgUFP+i+TdADgoTt4ngU5W
89Rsi6onDiRhWUQSMCbdc8dzvYd/U1Beqk6YcA5oUvd2KgjTj8ruQq+uOwA5rohHYRqpfEojxEpF
eiIkrgao20ZwsmxBGuKb11K1Ps76GlsFmljHMx5Lfgljd21/lAKFa4/4XXqAeIwXRlLlGoSTtXgQ
fU+c56ltPrOgQURlVR4eVVtYaYdocq69zy2rpK5NTvs1Wh/Du5y6BO6FcUTFJyGqqxr1ljyGhlAM
pzZi691jEY8Ck0ogk5GRRvrUOipqBWwzqbzm9p1t+e5Qua+LVouFUc+SSV372zw4Jk7XVPCxUA+H
B3ZWK2LfalyvlHDtOBheXAL9mysRu5jB0H9MM2CPPzlX4OXZyjhMdxRzcphHUZV0QIhxdZ1pN+hX
oB36w9/9ib0cmslRx6Ot60t3ivfqTKzmrsY32d2/EXTthgbVhBX2/rXNTuLLAQGJMuGrQLgVul1v
EwrIwJBE8HE9/S8TBmddP0lHLrzWk7Lj8nZFb0VURWoqwz+oHFwH9i4J2yJap/2MpH+Wpq0duTDS
/UYqt1BfSI7yxciu0S9tsi6BmvYpQ92Nm1OOZ086cEbV9vPOJzg7Pd+oB1UppyVY7zdxGXNpc6+b
M++F6Qc/iFM4brEKeJUVMM75Im9XzmiH8UMoB1k8p8Q3pu1YO6YV5JtOFHREVHnXEsuWxkwUfz6D
kd7R0w2z57kUmhBCl8UQ2Gl8jyPKwJN13p682wf6o3Ah900UBPThNMySiu091hNByVz0lrFoIoxd
wNYu6veB5qX7IFAF+HQJiFkvC7RfI3rjYh/TwurNBfXQDGEy/GQvdVCi5BC/KyAG4fVuEnmpp80i
SBBKz8w8Vu1zyiYRN3rf7LCvalLZDR33HUgjoHiztEKEeNGy1tdgXSJEGFKT+U9fgu6vf7vDOp2K
D5dbqaDzWmXsmPW/5Isyl7G73gtu5zyxqhWVUUmzxCilvpIEm6WnHRR04KldrvRVWf+2xUH5NAyO
KROR7YGAVRIwU8FNfTM9WQWIo9QQiAWcfdC2WAcJ287ycgYj07RyYfzhohZ/Bvl5pFTKpB5bwFTF
6HcSPuVDL7ade4G0jD4dUSQCc20kVBPq7eoiJl6zKXHrYsPosz7L7MHSWhvHfmGr0WNPxiBvfNTP
VZXikghW6lrAx7+Z3iCtEq6RTk/Rh2l7zuR4TQsjoV9yl7DTB10Qtl5nx9/vJXF2CIcoV0RdTZtO
9eoCvxV8d0soMR6I1oe2kYr6UyLbtyQYgrZsAqtjTGOkbFfLqWxQnI9ooHyidT5G6vM2KTN6FwJn
vXesayVB6hGMdB9lladRLqcIIXoJFNHbxLzlO+ZB3hbc7wtoEw45wrN5tXMktBD5Jtn6OrWWbqT2
WZvwtxzWikruLG0a6m0XSQVya6DHNT0oRzcD6MxzkmVgKg8YQEfwVjH4v23AWWBd4mcl3GsMADlq
iDK7tdS3TIpacVsWhjZOXw4xmBqWbGV/ystel528hquS8Ny9ZG/vBDi3AQuqbF1RaqwTE7Aplewd
9vNIGsrvsgX/NQ4UIsEgoWFd+sF1gIQag8dke7h/fQt9wWLhZD9m3UnTdsqWWD2hurg8C9wCxYb+
9HnyLdRNEbbC8OnJp/dIrGTd0Z99kEspEFfBTDf77praWc1UIsMCvUjn1rlOWNfV8Kv5krAYK6sA
oEuFlIznWUcn98u71kvUAdQ3Gwx7pdmHy2IsbjhuxhJi9thqbeIbTZMlB47onhPYWN0PONc8aAcf
NEUTaUL1JVYFQsUQw+aS2NeitXBVAoUiue61nMeeda2nAa88OFNDzYnCCKsgnwyG5eNGxgYS0UtF
XVgsNqAT7tnNYiCUq2c0fauJPDT/5by2r4Sa0LcJhivXcBekEe0BMGME3uzG5Iqd6LT6Hf+A6ijf
Gt9abIA8UzA8y66AV84zbmeRWupsSUhqVvhcD4uiIHvO9f3Z2RRJag7d5GQRzvC/1n2rn12XGvyG
90NGI+FjAS2s5BH7qR3n0g6S+9mowMsWWQ9HaG7ULBgzuBo73m8B8IsT/3Dg+sM3WQS7NI88cbTk
gGFEB6E4/OWSbz2azeTdJ1NVcNXdrArqSoezPAjco9W9+psc5AR3nEI/MESAbejCIkpeApRc7oQP
do2pbUM46436OYAvJH8tA5K0ZdTyyE75tgusL8kkgju9wd9IhhNCfPxYnWd3JjsBmXfa8W1AzeNt
T5yUJbsLcLJn9W7oM6NKlgZW9poqodkdzdbjeB5Qwh8RFowX6oke4Cjs6S4hzG3Z2A2JyBqhoXYV
0wOa6DdGl12P8UGNrYAy6gnKkSMgbQ9WFbm4Ju0v+mjLDO0DCCWBZKgf3ENHk5oGwcunf01DrsZK
dsKyqITLuGxwNum64KSk45ptl4XErbNRcMMLKNk6F1iSd44FqgHcaq3+V7nHawyGGl/UicwXGqf9
TYUHaSyBARN6oZuUkeZsOr6BBqCpWUwMWBLJZkNON35iykZdR1Xb4sf2IZ4PgXvlndCiMeGcVsfN
3YBlHxac9930Gk/Lw+svfMzta8JO138q8ROBmnmYRsOyIPhQ6o9gt5cO3bOs2PCp5FEd2hG1Iwg2
C2wWAGknXbIv4LNbybLRzRNpDMx8sxjFO6DN3xagbCnmMkQt4NLyiRlZWdt0/0joNx/inEIIATQv
hNMUytRM2SQ/B1/Z+5buu87rjaCOxk7VgZRgrsui6UpMr6Qc68T8FwzDhXwR6V/wVfrNyAeQ9g6M
ogB6JZrAo7WWwc3LkAGOxVKOsi5LrmYpQ/VFzQ93tEcCAyxLXinkSpaBzTc1vTnA4fBljLUnvrbg
kf8JdUSFzHOxWMeGci94C6e+R9GHb8zk9CIFw81TEiVTA+aY+9DvbLATYNHbTCZSfubSnBABxNBO
dArHPCDw1w4UycA6N9rHsr/fxw2HC2s3rsfm0dV4eYHyEChW3JdJ5RTDvPWykPxpcIz0yZHdQQuj
48ThWjT7mitpX7NHjsgJ7+sQCmMJ7suWJpzr37SIKWQO+KLKQiRHcCfcSzepZpfqfH+ZFUf5yK4Z
zBJATxksdWMakwkJMoDasC0WlrtM3/P6p44FQGbpngbBOtaFYEKBcMw2EVIFWSnzN1L2nzySL6HD
fBjNFLuVEKkh3IgoCVVa5aWSAHPx7dexgRnra6pzQh9Mw9XVoFJB7lUUdER1w/a5KDLsQEw6gWxS
MQG6c6/T3xB7d58sfbeR7Nxqg17SpbLnJiuaRAwSnWHcJavpr8CEtBD3ONQbJd2I4gzfTcVr63QM
w+Nkxmi5dJGqulzS+v2Jbnf7KFO3XbEzX3PX6B6EurnXiz/L2PBPG4s0tXMFfez3KJDydBJ3nVGx
Rwjt2sYHIDnoye1bNYhdfrT2tgS1COiraWN6l8Bw1YKG4isNq7KQG52vx+KfmreL/DEidrkO41Li
d8osaFTPjT2o9OyXLQf5n2V3/+yPDfFMpxjEEcenUCMeMC1kZaAXPddaJInbfUdKJ3cgFPsMNL/I
uqy6RLAEZCit63iZbIGn14kKnzwpeUrS0fL5F3OvpCmqvveCdzJscx0x/eqyEk3gWPEbHBUHqelp
7ZUGoQU4dkUIbfsXvN1OVtiLWJPDSf3w3oXwmo6dYOeDemVo4v4b/kNwbI3/MrbKzDE5jMLHQ5Mc
6lBdixtTwUuyppwb9U7w2Rp5qxPRGTtqXs9FQzwDRmBxCbIsmueHYysjuCtwMERioWpH7QxHdc0B
5p6TaSRlRCDF9jbeSftZPTTmWOaB82orBXz9JnIdXwnP4Sg511vXeT0vRz+cn1p2qoP9U1eyxec3
o9LQgWtVGN7oabOZltNNVeSlmdyo00I+ICc65VQeUYJZkMoKwBJEksl1ZfEan9IBaeLjC9zVz2vP
Z08V+/vG8jusojakwnCWJFznrmYQGjSiqlRAwPxhA22rf419sbn8BJATXjZNG8LpD8KzAVm8wEjg
XWW3k6HVPDVc9p7aVaBFDtjag91uPxB7rHcWBrb8aw99sGmAM/bA3sHK943cWTejGEY5Sd50toUc
dyjGus90zUeiyzDTeTHYcIzuTiOKByvoVC4KnWadWdcD5m88UI7H6dfCHWmds9WVLe0Usr1lDCJ1
ySiZviePoN6i4ftctju+FnuBXUd3fgUt3ve0C6iPaj0FodbiCeFmjvF3d3R8W2UYElONuy+7bpS+
cRfnWaF5Efw9q6+Py8PRN5NDwpdHYuJY7/9oHY8/We4tVTiitQ9r8N0gkDmDq+qK3v2fAMFVhL0o
UpN+Fkyw0qg65ph8cohQvsUeHInzFq1UFv5LLVd8OHZ5UR5JGxFd1nQS3S1K6UWtSDdJjBnKzfeB
oO+2cjjvY+FLZ2rLC8q9gCwKnJ6Qh6qRubhZDFJujqOcBrAxWhQuBtVle1+7I15n0pX5V1dDBSCS
7OPZxOBINNeqC5yHNw502K327L6ZyIL1YbE9u9Qn+nbutBfMenzC5/dzz+hF1esBzsvHwnCPKCbx
+pboxmfjuuG3tuBcFWtCVofAH4OrNpfURN2pi2V3VCVZYmN5oq8jiIE7KK1fKObHnVzbZpiCUSGf
T2HCDExtUNOqAmA2584Nr7d8o3P3XwfhECLP0p0BSpDdGlXxMOpOXqWkceEgpyntJtebJWX4icEi
ne0KMGgMQj1Ouc4AfJ4uAXRWj75iulpGZW0++cYozzI7VOxs4w8oPYHVfvk7zdB6+DAnkRGYKxi1
o72sgnUsnmm3wekKep7xZZQ5EYukIJ4v9OraSVBjBt8N/4DcDaVCN0QKSRc2wvnkOzFXATXY5P0A
y2b7yhDU2Oa9Fy2rNEdMlW0e4tNGLdY0jOZj5ot9ZgxzWxQ0Fty/SMAsb9reBHY6pjPGUdRVUbE7
c8/jqNcAwaxQTzIPcFfdRaRVFVUJqvUMJOJ00HNW58A7xH//OS7JqAv6vc7hAJkzEwnU7k/sreUf
UP9R5UzXwGxWtjDQEYsW7M6fOom2Y0RjbOim8+z7j79sSeH5G4j1k4H300FjPQnZ+n4ReRCyzGpG
9IXFt5CST1BPSElRhQxTIpmHFyPNbWjxTdGZNeq5u7MeRNNF6b4pMnLTqwZ2KINiDry7VLZi7QWU
eaOCKF/WheX//W/QKNsp1u71e13tR6FbOmY5jLrgqT2QgUu6k7dRJdv5hgwWGkpE/8pjk/m5T7Zs
MFf4I/Yvt1btPk6K+XbSIZHXE4zZmT7qNgm7EWzAqB3C7WFgIZbXWR+yoF1Nd0s+x1DckcMcCD/0
PQIdw9dpyoxrtddn73YneQkcxlDoUQKi7Z0EiLmtV3NLyECGTf0AubBr0H2Uicb7UAGvNML/Rn2t
AQpS0aHs3rpQkxVOUXKwARnJQpI8t7Rszj7IjdOaNUuHSgxEhDXl7eRGTpMKNrD1zmTMJDcaOZ7T
jDsgfpts5wmm96hCOY/8Gr/JMg3jE0ELzov8O9RHnvR/bds8NVI6k8/XUPN3uTyemAybD2+Tx4M6
XsUMWBJpTQM2dD2u8hbSbCnoS0GR1mlari3W/D1ue9gRoFrl+dZgK3Lzau5DERRaFZI3VeqZVjkA
KCWppDWSmEiw9FSf55es2CrL5uJ0olKRBIc2m3WIKK8U+8hcgIU1RMJEDWH6vLCcIED7NtcUsM4s
Sc4axZXBEOpiQC5+5L5aCyy6Di0ZN8xmfbVM2PjvmSDGocmkdrhyjZYaytwyH0Cutn/JovJA8OrJ
jJqVFdILOqq1bctrFfI3YLH1PRZVvuNOx/HPBrn8/SRIk2MJdQnENquF2APwvIgJ8H5dYTKvSYOM
A+CFkMcFUkhSPYjjhsEs2VMQKk3Osb+i4f3wbso5LnnyWyDPiVMpahVg2mSQWuCW0W/mgdT7GiIz
3z3jX7qboZiJxIaV+OqfjNbGk5S5G0X4qKqqyauX8dhzLVFw/oWwqxtJXVI//KFqQzeZa25UyAfL
mdn7wbWXgSeniJ8wY/WPczLquy25bVkQzy8DCiuFSoG8YSJGnvQ1MOGwSNkF5kfXCOdLNGjA/LQj
sReoMelZzzbIL2FYaZyywb4xRIL4eww6+N1+QbKukx7I5iD1W1HxPfvJhTAVzSNIDHlBOi8GEVWy
Ke8vjfj8DrgvOouYfj3oNPuPjF3Sw6w598xPeD+Gjx4U+muFHIYVoZdB+bFK8KKXaVRhdqtMq+7O
TrYYp2KQIaZBCkehLRIWe0VrZk4E/hvG1joc6/4WikUqPLcG65YDNoDqU79IBIBlA6hm5oSU1nQI
o/0bnC1/AXsgJLuTdvEhgtvYPQq20M3DZz5Fsp7n+9TV1G75z8EkFtF6ekPjIfR18M5x9SkpKj7q
hxrISgdlaxj517ncJT51BhMNlZBeKtGgFIV4T+56EcaRlDCk/5XKDgKegHRGDD2gY1E4uTCtzW+Y
rarTQ0oSW8R03Qg+5QMttDB5WGFdDZSAwAgNJ+MbnwLx6Id0h4WJczmn/kEain3bWjjvHLOBEtDi
3tSEFMJrGtFngYwO7hhsfs3UecwAtsSEk3H170mUd3oQ2vLl0a0CI26rXbPmgrzBhVCnfuNiudyR
glbn82eemq5U3BqcdUGHKGyML79w8rFOm6U6L0hoBxL1nq4Smx4biZ4owpP/EL2ybVxMetIYDO9j
nd1PHmjY29lrCEtDweQC7wxRd8qMU8KE3ePt5T5nNkEnlW/RBIIl6ae+Qq952Fvm2s1p5dmigVro
5Ma1WHisnZjwP2OuK4zzsWwvTNnbUUyAF0IY/6zJUIrl70vHh1upjLH0098pgh+6h0vJo1It7Usd
aziE3cLYkQ5Rg+22PkqnJ+qyZzywmvzN+LvdaxenQIQsfgkfaqQzym0qYhR98q+rNzSG0k7iU/bT
MCppUB/X6OlND/65I+RSxgLHjF8gt7gcNXNi8od4dVwYhxte0Jdtjvd49rvOP8w7iXfclIMFsmKZ
mf/cCqwK9+P8bZidvOeuJC8fiDqc+wgAy7gOhC+63r8+tb8HLVXBnNn4NL+8ub7XTuhkFOBdbfUD
z4tFxBWkqaFBjC6agRtbkgnSRAhx2l2OukgWMO67aG3oMPH2MGEKuZsXk4FF0v1Gxu1FvlGneYrS
sY1qiRWX5BuLglkjZtyxJv49vLa8TvishzZV9ygWqmoJ+jw78lIrTXORIDI1xwy6hUlar6aKJIiU
FlHvjlBh8myPV+pkG/b6CSlNSNErZr29KabXQUiOaYkAJTXqT8ot5XRoyAAjlgJaXl1MM44zXsiE
ii7TfXweDBcBdDUtboMqJClN8eO7zfsYN/OcN7Awc8lqhLZjL1sDYeviqpflwfHAK47WVVySGz1u
ahRgVqkXzYja3uU9N+FDhtyJB6CCylX0FYw1eBEW90gfHEnxZYTNYq0osQVtGNMt1DSrauhEibE3
XLMwucKHDOLLAr2kNDTU1L9h+U/BNe+588xD5re+azXDEFLrtahp69n50gxTfIcxy5Dq1i5eTVAk
K6+PZfbC1qjwpVLnazPdAhkKzNtvnMnsUGTPg4S/ehVnoqDNfvrYjFLy44uMkbbeEMKHxyfPpsfc
TuUlu4C3160m5CPUuSE4QSwhsia4Yw4Dzdvruaz45YW0i42RPYF8PHS7RU+y7WU9klyhQKl6CkVU
NDqgu+EzsgxKDtFUaRmapjePNVtyd7HdJDdUfbx0N6BBJ9NgmM7XSOUlX9WVNRzKnksnnhogYHzn
P3wkyWuqlbnSVovKHrx4/ECC2EhuBwAh4GzojwzvOsVtm4x6Ua2J6/DiQsVO/GZ36pl8vGIzB1eh
AmnMOrQo3RMLzJVMDn6uZCWONZEweasDi1CCvSN5F1sAFsvimnSHDrcVE54u5o931B6CvB7wcgXU
r1+hVkMfm2wC86eV6AopplPL988uS1TUZtXmbHpZnzF+s422VszwYag5FkjkeUzCz9KraVPRlk2c
9WqmVRcELTEpEzIACtlH8cNPvlNyq6Idbq3Z2E4FZCNHI+Sxf8h5i/yP6cHHs+fcC6NIAg+0enGu
W02N9u1zOqXIy4bWQOTeSOtaIFN5AenMKEQz34FD+8cTTVvNvtvLyXGVKXZl614mxPh6OcExBmST
51b6x4QQwnc+rpwPc/+CCEn07AH1urp+Bdn5kFzKw4uOqUkc1ZmjwKw1HK/ln8abL0coddLovcDc
F/reGzGYazDVS0QNBx8PE6uDRhSvndmTcsJKMk4L7akeQppNpVPpayPeEb3nVTz0GyaPPIW0gXYg
w4AKNfhcD5uy7oPJu/VSYENrfyud58dFD1UhK14DHReNZDohrFS89hU6DWm722gFNewy8iwYjuY0
fQZJYV18Qta2baXL6WBOlAIck1elIOl/lQQ2ek9pMCQ9iTJ4MmMW4Ff9EOLa2APo1OvkrkI1oGAW
od947drlNdHGG/3MF4xcNcvoHNWpg/1I+FWvi98SoKNXTP8IkyygCrEKFdwNKcxkMqMOPHl6zkxv
ayPUNQnA+szsc7G1oNsd2htFJZNHrvO4R7FKcc2j8YsfxUuUV2K6k8mVQaoPxBR81UnCaghRsEe8
smnKUM1oBlIdy/ZYVznvO+g7kyDqkNEFLw2b1+KkI8dxNrkk4Y3XjZhHFTZr+6w595/irVKvvq0N
N3OIvuALhYKT+ALqXbOYchT0Xmq7znRGN/IMAJNgaHRfYmoFJ5RoV4x6ZjwzQ6gXmzRT+2IFoK0G
nlPmR90HaU11ToDdceLTkyPS1arbRE3VwfYnecQ4HldwySQLJJKWGdvG/Bpv4G2oycG+M4gVpDo8
RYP2YJxJNFzOtpr7W4A1524QZ2aLOBsVGg12An8A1SPhEZX/OqkxC5FwfBnxhKkAhCLzths4r8ri
k9ivlO6Iq8dfM/xGDaRxXlQeYRskzaNRmXl0rsbGuXtoOneJKr19oq12XIv469/q5nn/nP4TeLvM
paM2uBvNlnPLn1Ft78xq6izjbHj6yrOveSDGNX7zvbxYE/DiW/4mwAYmnodeFwirTHWdLTT++LYs
0F+bcASYi7J8aR1Quzsc75TP5YKC1x6VmU2S/l22/hjeSFrzbN3X8NBg+Da4de5auA4tkZYANbDo
2J3YUpif6KFftjRzv2jFBtJA3T9zub9jkQThIUoVcm7z+OVyQp20molcV80VXhv8NnmMt2NGR8K0
i5uRFTqmAdgYGFdhzv2dnuXRGD6zx3+sluQ8jXIMNyURdb+hBWrqBDsLyy/5mXQuTbW1Dl6UH6Sm
YZHrZvNiQ45fk43spbZToTBBJ0Y8iZtVaAgFozkxcQ0vNv1h0fD2+xi8c7KZUikbrzZlceRN6ITY
ry4u9c5zxo6pVx+0NXxNGVb7vKC4+MpIxCPynhcUKx2Zc8cfWC/T8/HyMpPa7L75Jipph7l2fSLp
3OuqDGe8mypF+DLDGnfeOi+ijvg0vp8eUWIS3gVeWQgwUIkCT3SpD9A75eGRhbmXiLRmCSeHJE67
SJ1cN2q3ve17nBPOmxHrGS2A/DaXH2rsQdtq4uaQtsrMsOLETpCfyhQ1l5JX9QmZS7vYNEbCWL2P
PmkrR7+J9Cj9Uk7T3Az3rH1HvTn/HToFABDaUsQ5F3uAeQHVHoRc6HxI2Aat8yoA2ruSlQwt245M
G62ru9jAdGBmcYUDNSnimsOgRE36TEiyI/OP8T5UHIU2C9h6hizpa8LuZ+yg+RCZ5VBhSwdWM2cV
d+C3YTeLBP3oUIm0InxYBxF2t2hKtjIvWawNducYQ53JWK+CkEFaS9b15uci7jUij8pgmeUy12Ft
g7WyDq8YeMxhVF6fWSK+53kkY8h3GXGKBFb8zHx3rVgbdZZCONKN44gDUGqrPVLKfT0aaR+HGNU9
ESUMHAGgtgU0E4Siow3N4lOa69B7npu/7ogFens3o+uSzfMNFDYWq8vd69+LTzwOZPGURfT/KIIY
Gt7UPek+ovfsKmNR2IbVzZO5WiFDcnmA5wWzRRya/OBe97jk6uwdmuwUCjjtbhVsayrzkl4PYC7A
L2zGesmKTRX7KqHQZMC98ivw13rqJJGydQqw/785T2Es/d5qTHUwr/Vbdml2wb3dLWNkLPJDAGTi
vtb4Ys7MQinTRSmcdhEOpOw4GYRa+fO20DmmPj2pv5psxMCtmXO61K80EuR+kVIPr9KD3OFB/hi8
dPlniXaDKWBPy8Cs4khmreMOZY50LndcQxzQnvUMe2PMcOJQ6LhKa6H1OsSKDzqIFSVJV4Sds0ir
emogBKgC8lDnrSuoCsrS/qdtSswlHvMlNgt42jn0T/7Jz84opVqk9jp6bNRh+UTZ30GLKYEpCXMh
YZjqKC+cOFETH0HvIP5vjS7DEdfE2F0dYVir9ZeJ2SeffB8Vcw7SQ0NWc/gQ40y5mfSW0sLFirfN
fbhAlBDVTtP7fxKwt8DfVU9B8DZA1RKZePZQLbEXcjG2bwJtwsVtGF7//9YG6lqN5pM6lGrym8ge
qxxQsdlRCH6TK/ct/g7cKWCB7noMOQewBIjKmfxOCEncZWapCyEXvRPEHE4en/zuM3L/MieIPW6C
005ADVbCteWe+CqEIj8zmoZsTxZpmmR/E/TdH16UnhlaJusa2BZORlKfCw48DchLNQV+RsMDeU/u
gzP6UhQfe7moPdczvGbOZsJzx+Z36p2DbmCZE3cmBJuu8iEq4sQEV8YOhOOFJDTDeFvJJw0mQhkx
zSQRooBErKa+HqAfo4+wnw0aleUKtbrc/BCqD+A0aqAxsVdoTsNvzhY9cnlskZ7KE+GI3dNREVp5
M3Fak68iZ88OffL2u/D2IouSUToqudIzv7H1HBzIik42HQcgI6szE5DO/EuCBxlGlwCJBv/CesNw
EgtPtglYx3S2VqqBT2td292ysqxi+wQ1e8yJZhNLi9aPjOtGESlkhJX9Xv4CqHnQFGREcOzM1Az/
28F+xGAmRKvXb3ajcnfNKbvAyGkYL9yxnGhJ69f712zXyvQB4Uk3Fc3r6G4LNhAvg7XIEEzcSc2T
JyDCu14Dosj1/dTj1raTDRqexi3aurIl2cvFw4sDkNAbLHe4tJXDwb/Ie2Mboj7Y4Vdiv1nWhwO3
TAzFxcInSF5PvulfmI7Wu23JaeEV5B3sl0nNokbe1bPZLoGm3WkgR8weNyL+J9JBtr23sXbQLsvl
K0xlIQmbVhy9onx1f0uNVSFKmUxTpTFYa9KKmy8kwHxOWb6za9eGm73ghmZfoJRtIdQXf5QUqcJ0
9q4/4ATa+PPQOHetzO9zHVw5xE+7QcXIEOCrNLgCfQ9Icsymta7vyEnlfVHuANiT+s8XG2Bs4CDI
aj/S+72rMRQTZNiQauGJAEfCrCvupE2mPdG198F7Gfp/jw+JRjjjboTpIxQzWTcsLJXkmrp1DidN
hZObCXTcg86cePZu/rvZ7icGCn9R7ToxizTyRkxCxI9naUU4RPixfnNKWQEqwGenJlIk5d8/AeZy
L2OO6ry2aGKmpIEtetkYjI5gI/VFTSODrbyQ5zuJO1Hooi07GwsxciYp2HG31vjfbvxWlVy7vw7q
FknblNM2BYREPXDI7ZQPrNeyS6FF7rXz4W1S7QR2RkFURVhK0dSKpH7Eo8I1ePEjXyfE4msaL1wn
oy7Vw8d303+JvtOQL6pXnrThZ9GHGBRwC7Eu3FLQKvU0a3JerJ6BxlUKeKOSLnZJC+yuCE0ygd1S
MG7x0BNiiln313URLUzREmC5VTFfkV2DzejCg9xHoZfE92E95SnvAb9t8ujn1KgRWOwZDKexZRAv
rXqR0/9fiXTcvRhCk9Rz2BleIWU23DEpKQrAc3HGt+eoPbihDgc+PwGqvzDdSOAE9BpDNEs/UQC+
0qNQXBMmjSgP+4YTn+7sBkPOTKfgWX3CUFJDGyES7vT+pBl6q+NmtVOPGk2nBcGNMEpKZqfvGfT9
N4LZt+10vZj/TV3d6RSibTQKEXfpKwACMcen1Dmm84pHNJ7Deq0st3TgRRMBGaWb9WWaW+8tLmLZ
W/fRANUYRHjGnJgMkWYYOBHrt9qbYe7Hx/h4Mq/9r4Kp7n9kBcnDgaVXByLgUxzOt8EhqcYi1TCr
7B82S1b1qECELuSwv2SLds9/I8f2gwrBlben8Nx2DSffzgs40bABAwtF6q6LZg/nnpXMTSoXSHSZ
SK4ftMzTyGtnQeewvUdyxV3PZrhbBU2grMsY1JtIZ1q9TYB9P3gm3NGTcMEm6WWxHNMdMtPDPnUT
+OF9+3s2EHi6Hiy1gGcpB9Hk2O235751acG272iLtDNmBYRYmZ5aAfWo4B3YZtW4Mopd8iBYStgm
T3VOLaYy+LJ59gRSCW9JfApZPwVF6xK7BNRphS6DY2/PrSgav2PntCFi7Mvx0ClGE4uwkfJNMAD+
Pe5RjqYQQpr1ThgggVByn3YhiEup1GRWySxNULA/+yiUHDYr9STqQQoSavnqBZ1iZhaJjfCYli9y
ow4o07v86rPOO4vXOv/ohkaI4+SE9rq0vgkSTRiQ+EWIA6BcXzA/QfvtzFgLSIv5kc2Ic7emRLBF
OumCpuGZFYV61VPdAPSMoZ44cwh/qNB1zmObPAWBlwVxa966Jh0BNTPOQN2UGQEUBGU7j7f0o/2t
+ASM9yhK3QeahVWSpKqEW88A1baPvKgTWqHvwedkM6p7TgOTY9A2ql2Hg+uGKFdlkzsQSG4wUiRJ
TtVDXVGa9xTfR7lsVWGlaRbQVZyGHuYxngU77RHp1ummSH5/oigOiDJS2sDS1hDNF0Aa9z10jLX0
j85YNnRmNNe3TKfJC1rTCnwaLs6jj7VQwRhNdykIQrcCCcnAAYxrrdevs/eKKoEFJ+WLZ6uUZpak
BZQ5r7iGlk0QpsyeM3YJLjrxpmFrHjXtZpeo9+cP28se7zpyF6LbzXxhvuO9NtAOz7hohi8M9N3Q
jYlw70JEiULzFuFOj6/wHwhGBBthLWdcyLY/0i/vCRmquMDvOYfJhHO7gWeZE1e1xoIR2JwQ8da2
LhnVk+hp1rqgvF/RfeY2KpdNl+dwj/AV+Dq9O/2b2fFSzKYmJkCJ5fBLXRFUyX9qPt4oIcQSt+qb
iKoDPsqkpAXesGBQZYLTVXF9QgkxNwNNhzkslzydzjYCmzslQ8HUuphgpYwhb7r49RzkAY1Q+eva
dueB50ABCJTg8ALnJy0IlUibVNmyzI9eb+jx8bUBjtYDoP2OnyBbfaNfz9MMNgTsqXvtHquMzxCT
KKwDQN4QJnUnyk290gH+kjD3pDMvxsDCzdzfmGL7zkf4SkOd8Jkf+tjwX160JBvCGLZC4X+y2KTS
KBH0HUs3vTpWo7KcTZALv49kc02tSzEKYu+hrp69pn6iEa9A2sybCCR9SNsihuz1rAf1gx3PPLUb
VMvXcqicg4hPJ0jxKpT9utfa7rAobKrGufx97qJauBEXEaNITLB/qwG2ehDDLgnaSV3l41+rNS4j
rudPSH5z6IVLC2P3w/nftv4Zvz3dVma93fjnKjyRvoCTCgokdUvC4EBMXJURG2TAuWnrOUIDiBS0
mvdNr1Hi7hf7/h/pG6hdUJZaSMT8GVaMEKi9utogM0Kyssv0jTfMal+5j2AfGwvUAHG33xkLEheA
bnI/qgw7t99/ukbzs/Z5UEdIHFf5tDuDv4zbYFwLD8SZ+yLF1/S5ALbeSO1BgnO+7SBhTdNh0ZaN
CAuGvry29lE9jWAM3XgnKEEJbIbwJj7EIDYiJudrA66nmGpSx3lNdwBpLTPCASB8eYzvhLeJoT87
fOgNbIJ4p8KmrHHiBv6XKIB6PhFGVB12NsYrtcv0OECi4j/etW4DGkEfbbv3SCUi6nNuk9lf3Ono
IHCoEjOU83aNGFXYbu5ouNOPX3nqP71IJnG/weWfXusLm6NJuBYCeKPd6yE3bWhcv+dkajvJ1KCb
44Cl31f9Ivn1mGOK91dM+awAW3ncodUulwqSulV/B+Xo4jykSaIdIjsreZz0e2GPxxPKXENvcdx2
HWKStJaYjLDNMvW0ywdw3jCCwLBMSBg92rNHwRwn+SvpyH9osY3Q+aG3tvybO4T4mgGvGI0zwDCA
l/lMq5TX/pqA0gPlakPnRHc+UJYLj23/ulJHSq4bAYlYNuVzY23vaKlL5q7ANd/bQgJQOOZPxymO
1AJzkwbdATO46eOxK0wVi4UioVB8OpqhpC1M5ItSoudLU3BVmtfK24S4Pe/QLCaAASzy9bjuu0xw
ENE3W0B1Da8qTiHh5xYYoGQ4Tgqaf1H8VE7Adxbf0zEa7YghrR1LFvuFbZBgxbd0dhqL7OAbY2EA
nWyA+bsyh2S51x3b5SSiWVCqX9IEw0YK9A24VRkgjkpw+hBcURyEZot6Y65ST+oMHbOImf7+UIIp
H1D8Brx1nW+36x5cc699nxrxpV6xjFsMe6kCfu5h2NCEtGpquNyFLcvc7RxmbaNf6kexMQZhcqDw
Bes2HJqt/Q32kdZnjIFj7dCNcFKk34g9n3BRS9TFXeYG7mLRxntEoih+dOSfNnRi22Rpdqey25Gm
ZgHrSGp3nlsvwMUx2k5N79QLfHy6oQmZKzXyI1KFKlHIkqMkqQxHxUIFHv3NE42ZfIEgMBL18OGu
cLI9OjM4CQ2DS1RHqaWbvZ3dEawNsjpNS1zezwlWYlZN6u1MH3EigSh7bM03X+ZsvcPxElSJkJ5z
CZoWf2/cokV01cfvrIX6uxdoP7nVLZ3goLU4IJKldf/fMiFAn+TINTzGUj35KhSCbb9FTTWuoXGe
YIRUuznHLMnJiN7gK3KbxfqJBPJ9Zy2yzKdiO95IxIllg1DpvkE0ZiHYXOqANoDfY72aYQGPigY6
rxU4P4m+BUTqqqLijoPOOD5ozMEo0gmkqKMnitJrES+7FsxykcssDhHqU6yuUk1XT/IJgmike53E
+jrquTRHrjnApoqa2jD1ZgGNWQqdaOho3mR8od3HurptPAbF72XEQQL0f3YNRh77uusNH9HfGUKH
D+nuPINJMS5cUZEk5rHxwXBfk1O0gl4YmrBLvFAiFZO//f3dSTaAsp0fV49JbMN73UoXS33fg0YC
CHwFf3fvErhbGTfKIdN4aF999sRJnw/De4p4ziE1YQjfM1Ox3IDWbrpemgseJhXnbV9eUhzBTanF
4SCkLNE5aqwli3qX4fzkhvi6QtYUsdr1V+38e3PmAgoaOymBt5gxWOylEnkhROFIMmj0uQZ8gL0b
F3/SqOBYc8hDDyM/5PAUlBGwzsGVJq4FCI5ksMfnp/Y3deipPT4+41Vg3G7JSnhqMM6hdcWsjNHQ
/IdUeQ42P57AADMrfZYpseRfn4Vd6JyAZIUllQUjVD8kAVxbkU9vwIqPDfr2mdW73BcYgw+loK2r
g4TJTS1MG8+pRVtqYICpSnmlsoMe5YSTJHx/MPQeDLXpI1K3/ACMX0nb0D2wZLhP1ZvGNRu0cZBL
jSHVBOIh1WOlhkOPbewUH2N196mognXplz23hMrJyeq6sZTpTBX5fR64WTouEoqHma5GwW7KktQ4
6GUmopNJOFKM/qQUnDUKgwmIXQ9pJCt6zSsNhgRLwPNWFXtb0jhNgF774kusKxBacMQ6SIDMA1Vj
UP00qUG6vMd9H3wKEspyKstmoIhPSIatrwtBqxrj9e6UxMc5Tp+Y7db5++bpnPZrEzr56jr3QiWm
KC6X5Krszj7mWmuyZjz2nGYiQVavoPeNt3FSK1b3/4LXsq6plnjjSIlQ2wkWfHuMy8JcmzPoxQI1
/M8Xgy84ch5voWOZRXe9e6KJf7Yq3+H1ymd6tb0CZs8FYmL3WaFAoTCbFMZRIMllUdgPANhrO7kO
/hsz6O5Sf5pezNH2XsL789mu6BSteD92k1CpgY4sLWreXFrkzLle18YLbUJH9NjnawOPv8Stu36F
OE+2IFoQMl41IGrg7H7iveYMOLhAmrpnnTVnNlTok9l6H9MD4EzFAf9Q5iyjxBCPXhShwOd2DvjT
bZcr96Cl6+DChRotWuxkysx7q/keWYfg76EgF3cCengtGXCmHz0fFX44i0EZPQJcBPYghVybycd3
VE0VHYmcqh7aZ6ITRwbp3FWt+PlysAa19VCiEtvyioc7r0LEg3N5nTkaDMbIYk21E9/2bQkfzYSS
U80W/1cRsdxaVmmOeT78/1AAtI6B4rwsbb6ALOM4Z0haT0ulzDDXSzhT5tZWUqDkLHHbqBzyHPWP
D9ww+qeRjhhFYcAv3bZyStPEnvKx52Af+9+Jth5OcOcZkyezYDRopHMzQwidBqL+Mq3MGnYLTkgv
hk5CnSqL78ifcXcmTS+qVgx4WtMZ3bMe3+FGsz8bu47c5A079UW1VC33ToiYOJ4bR3mjNVKyNw+E
jJCduRBPMVHDdAWgMGD2sOOeFXXW4q+YD7qoCoSmYP2XjgEbW5Maf3X0DVv1NEyCpoBm7vwUhaX5
DIdF0hrprjipTFeVwqAXDU8LgdXTDFsMX5BxNB/BXfl2Pw10QAfrZhYdnopwu5IVa50bc7fFdxzp
TnO2PWky4QMDdpjg4sSWwdrA1sEO2ziAKM6Zn7LHs28NdSkgAqZwSQ37B+mFJ661rp71aTyyJmOl
zi0+MmfDUy7puezINaapgPbcpmFKOWTq4QFQJipQR5Lmu72nmYujMgOVUnoZmO+Npd/+MFpshsgm
eFpSG7z45PqRbZicrGOiT+VUqlHtwF8bueIOzErb6hMZcOitdpVQep2XgFGYWwX8dS9e79v6jCCS
bbc07cacBPZ+x7VUd1l7P8qbCQMZ/t3nEUQ2hXtzLQkEbgj80ETD7Mevotvug6gqVCQ0SYkofN6G
MwD0UthpUpD++olI6jJWBg2V/ovQH/JN3ZIjlXJgSuDCtFDyIbH7IRd3q2Cp7QiZbhnku97EmxA/
qR+U7b7+V+Ep6ERtRPFhxPbeJ4GfddK0zhpquwgou+O5FymJ8eIlm13YX0EeezP5unlL9SNSBcyn
K3VzBTwN8ibMDa6y6y8UNj8UXIVXJXlmqu7T8uJAfJtvWBRF4LilSXKFqOEoJc4DpQOxmQkoy42b
872texpp359AWNhH09AZT0AnlmcpXBIk/cIhFQFsFiOMq2P6EHmlgqVINAyoYdXc/rYVoSEH3PU5
Z1b/XxHBCEFvopnGh7W5qiexaZzZ3Rjc6MrzJIH5H5gFP2BBHSdMBku01c+wLh8+jd7DqaxLcRmR
Qd7/fKd9g4mY7DcEWo0hXNQDTzDpVatIfeYgHhYXYO9oLvV5GkiO1zLreXIQezyUHsLB9r1syvgv
jY/jJzFv8RTl3+ncOvlRl4ONd2OePxBEecaCTXwK3BdQoTnVnC0K7vahx/lsm1xvlPvNrtVh9qmZ
gElwiz6a6J55c1LoLQrUlqVBGgBs3KxoqiSdTR4nkISP8KHHZzAZ22i0mpK/ajDoPWk2OLsIpXeq
6jGi8j5OWhGLlUQOuoO6e5S7GK6W7mC7H8JPWXyiW/V0EdEExmXlHS1stNaexTJYUDHrrBa6LI08
bamb2cgj8/b3kUz5+iQloG09Dhv33edA6nXCV0EgbvOw3jHj7/GukSRwLjPq2aM2W5Asa0w/al22
+eGIDK2n6+o8xKFnby/HxWUxWon1ob9l7ubOJtz8k3N/2fcW4yAzNm9iYB/7LwOBav8R28Q9t+bk
Fg17bm5VcE5Ss8iyzalheK3dujdAQnOydNHuWZ8RXB0mFDVXO4ug5sJQxeHZbCBGhxLCZ7jIygbT
010c9rY5Eh5idS58C1XNJpEMm0Qu0niZMzgW1O1iw+Z0b2WSu57SvGQNET0jAPmC0+nJj+s1sWVR
fQySCbXtRdfxderxCqixBs5N/VRI40EoLG/JsdvppEyQuaV2DZy/FTBF6Dq13R8ZTPpFRedE/YMA
wbM3w2umNhwkxu14xlmgp0ZmgddG2nAAqWZqrDsXWHNSK4SnAcJ+GuDkz/729v5/bI/JJmGu49kT
wWF5C0SxNyUa/Il90Jyja4/a74Fp7c+n3L8QQLHTTSIBz0InKUnK1z2kSLLWb/w5EEhg5VdP8LkF
5v602ns/gqkTaF7um/4VBh9OvOP5CF+qPyVUXVS5zJj9NtarmKPEHJVwA7xBQPUBCwNoJFXSEyvs
eOiPjD7UvZ2hTkyTp36J3kH1SlPS0tKYFprv9YZu5uhOBS+GGZVj3QDrP30YJzDxm9M8Tm0xblMJ
TnGATeTScqKtrFCiOD8QgSAkSN4B1PqYIzNZtifCrRXQhRn4cRHxy6gPTGoPCzjaJXXan6q79Q+b
c2A0XkdKfccTs53h9Dm2/MYs8z1cMuzCpZWvdm+ujdcEiohHHMmYPay6qgqlGdwlen3Qs3/CoZ/4
SrUmCUlUavuh503j562msuRjkpaXOQ/nkmq4L1iYW6PPjva8kshJ+jVOShxlLAZThe3fcl+Pf5Vp
kXFlSr/P16l/HuhDIZIdK8LMrDxWBm9l3svNeQ8gCPwPnEV4UnY2q9lS3t/zSiZmUUxLqj78Vkcy
ddjl0mQI5hlD4o6ZQBXD3RJIH3HAquYSsnq4ZYKuX+y5Cv6DWuWkMfZBCAttp9VeB0D+rMaFrGyF
MHHE+2mcEDyjI35ZXjsNo42X80FLCdmIQbrjbWSUU82fNTmABofVBuJ6JlVY2noWNbfDK/VETgxp
gx9cZ+JNPUHj8LJK61b/8xz/Qx69wckrJXBsx6rYZpzQg11zJs3fiaFhhPLMXN+sgaMz+e0QcZLm
K2XM/leCJ5xzD3vnK3EAsEH3AWoS3t/DeYX7iGZY4+gh7nklOZR7C2qUb90Tj41MC35cKFyJGb7k
Zt0flxrPR177xxBMo64tjcenXBE0NmSoJ59DrXXI0LTGBd+2p9+8e27wXk5c3dhwBfwfmfEAKeGc
1Q4x9bjPbSazS3haGHgDLLuHaJPlMsZKCXzHRR8SuM+yNGEBsgML5gBR0tHSTCm2cbLm+ivuFVuR
ncSBY9q0I+iCgS6K6lAqZ+IUpeYlPh1V5/6ElsSsFul+EvKqNt5Itgd+0OokhJp7MNM8QZOOME43
6qdgAjJ78h665ST6YsVW7px17R2x/IMFjqYLB9V0svTuipRmmRknHdaZN+X0qm3Qtd3D16iZNyuE
FR/3GclgFXLEIqLGf6rj0iGH53Y4pUK9aRH0Wx4oYCcavl5EiQUR0oUrCorlY8QulUUCzRiX3LsI
b5lLSC2UT1OInp0YTBSFY06+EdiT/zguuN+6sk9W62hOXPwieFUSgBr8VWD6vYfAo1r0B+rJ5GGJ
ivcOl/OFNLZp9srKEdVlWpADHj2nld9eFxztj216pWZ/zl+Fgx3Aw/ii6JnACMPjdqRyDkeoOjA2
Y3Slu2AB/tukScn/Fz8ByNI8NSFuBOxd1NqBPVj4JhMGUJzluZoQU9d18yud18H/Uz9tYAw4yqV5
pwTOll+YEOJ408SBHK9tQzjZSpZyiALLYXrJiPJhg6ibnog+CZbXNjaFsEc6v0kt7EC0N5p5ZDOL
XPyYxl57DBxH9c4UfvVWYg7uxrEkQdJFKBeLFCtsTs44U9H1azu/k3bZZvGMSI2BoJ5FswkUnQSy
VlTWiEaSrCEMQSWZIRLQmZF/Lfh6Bgy3SpTWSbAXdRk7UvQM0EQgvje+LaaeBRo6JPeW2Pti9/rA
atnsq6URNNA0UG1fX7grPxCB/nAifF6v26aZvmkxnxWArHRTaKMuQrxQM3a5NI5WOeN5pMxxXVAe
IvEp4DsKI8hBCv91eN8juWMRuAWJIz3AqA96msBlfiBH9IY944okTEIcTqWerAqm+FWe9hj4jCqr
NE30lGMzj6nxmWJkqTaDbsCn0l0h/o5H9TCE2Ba86I/nFeL3tsSZERmy8Vs+cD4lW866YgpRAEda
o8mL6o1p4UhV8HqL+WhLoOeJFIpzYc8kmS7qSQQQmews6LLvpEmYVfKpAGsfUgqsYvrAUhMdRsgd
8CkJZgguaaQdYNqqycPT/znOBZgofDI45VCwi/X89rWbpt/duPU4BGfpzQMNYWC48rmpICHXlBG7
t2LVznhQW/XhP3BefAM83R3bfBW2JspuWvmhuy9OECK5dmt32aSmq3G3DrPiqy4+m67ux7lmArVm
3XQczzwenCHDGasIkQVnKFP0j+wKyQREq3LdEmHrD4stFext42q1xpN9U7m1lYJNL3RpSFchEMJk
a6+/3aZ6v2LY3zPikwBZNfi6/R/plBc9FJVcL7GWTu4Y4fzDqwj65WMTa/HUQiw9MYXboaQTHGyy
zOgBnBu8oCtKTrKSR3/BDGFbIADgkczL/EhQyQyxZJyRPrJScMBTA9ofs7dQFzrLZbbwUjEC0DfW
+6LiZK2HoG50UV3F8IvSmjZy6T8+Q0t3jECNoVkT+U80vhfKYuu+jwG7pe5e/DQ01moajr0+4Vmn
W7j5KXAnAv0yNgVUgQUvL+g8n+Ct9Patmms1XUrqXGgCGSEm0Z+8auU7Qq9pyhMl3s3HZPuWq33X
k92J+TxEWfG3JUIByItFRn8hMPajXEWP2pa0SZNObYRMUAglKK0sHqwl22m1qzJRHoTOMrl5qVzj
pRXFIdDPnZeZq92mABASCvI2tNS1A3Zs9HsAFoy00NR0c/58BEF6+Md+yMmNG7VXDxsNuVUaOfJ2
bhd8z3cISzSotmKxfEu1241TqlydhYZpAqFR0cWOSleqYjArZ3Z7pQGF5cIbeL79a/O8ytpKf0bc
QED1PudzyTc37zNDE+ciq0/KEMT7MepInllPAQ/7PvPFbq9hnb+77vk2dt1xiuTOrWIR+9wfj3Hr
RlukoaZItzboDR8NAMnh6IJLrs4OcDJ7kzjqlX1/AiiSra7yJlYoxlBN3EghqTFmB9EzeH6uzrkK
WXWumV2FZMzDQKBoSziEwQpQ8YytS3U/bEMt8/5HkaHSk8KYKSOTuqBEJ1sFsLNGkZTCbc5VQ64B
A6az8BjrZuoHIoUcCNKl3AwOfiXGbHXTdPYHQn1hpLQvIpxV9nBVo/W1aMsPq74ORH/hiQFPmVct
kDrCuKC+JowyOJJKs90YHVNFJ3eKbYzWre8CUpuRLeX8z0BfedDw5PHcjzWu6h5gMcQ0/sJnsz4N
tnVwqIoSWEN3cpobgK2lC3n+FiDGED5rXs//wyGaU5eEoSKYk+Ha7BDVCl0MNGy1/JOK6eFhEOeu
rw7MJuMbQ86Bgd3eHZqhfj8tIVI/O+oDYnWa/w1Mn6rO7R/SVLu4AMKa+h3StM67UWXSOf+cNodj
zlzwEsEQ0AjorL2yDe0slgm8fEBk/VfszNW3eYosz08n6L5njMXexbL47vN1FI5xMR8DfsdLMZf1
bfGni4R99jarBv6t84k4gxRIPba9jBi6I69V3BIPjdeNWAb/hoc7c0ldyRxo5HFIuFn3auvGD4z5
seBjxPo180nWk+imu7QshoAYwQb9p0QxiR/sLxVHZERqJI0Xf9SngWvmRngE+65W7AK+ezDjgwWp
f40IvTx2kROk6dUfLjrd7hFTmjFU4vYbW3HHnoxCZ1udG9A4LTDxCMnBHbFq2Wufqh3etygYXP24
cFS2ccra9wD0O9BWku+V3YzDaNslF7KRj5vwnDCXDnszO15SQHGJk8uS8XW8TghPnFkG4RADIW8s
gGCj+HyZ9U4o9Q9ncHMIAhPY0LxnMytVPDG7QdDPpMsHLuKH9LJpYO4742OQocnl8EHFw/1tm/El
+kwLZM9LtKr/8WqLqyvPK6igBDgMMEPNfZD7r/A+etwGUZsaxtyzWnvyxpyiGdkekAwCYqHPULF7
8D9Gy/4SzGaoKF/OHslRPraytT+VQheJJd+sZVXXoGZ4/JdqhdTEYaE13/RmplEw1Oz01m0h6HR7
RTnWy6ezVhVhvhpYT/TBCBxQ1SH2ms30OcuTGyAaP5ipBO43akkIoJQR/iwbz382+ho3YrZe/QiN
SL6i8a2oBGoFxGhnLgGTYev1JI2nnz2LF/F8q9uglaM+wzMJaG905fHP1cScIFpOJcmnXFDlVw/e
J3sbUtMjhucIpByfHR2wlvC+0MOR/9HPpjw5vnmiTXaKDSilF0k991XFpPuwNQxZYhw4LCVklCeX
mn/fdE2NbFcX0Kqej+jCIbvimFJmHL4JzcrFiRo3nwtwfssRo0GBC0E0GRfVbx2NxkCe/Outkjc4
3QXcLLtMaxafX6fMLHSLLbSiVjVNqdu7PL+ALx9/Ak8MgY+YtZiS11D5B9U55vaVzCpb1rIqUtDU
U2aC6vctQyd1aAy3IgttcSJRJGJrmcniaewDcrVnwfOEVBonbmLK+RXuQGShvNlljOIibGM+QF1q
R5d+8/1Um568Xei4Xrlb1rI6obOfrVwgARDtHl7jhQtCnIkEL90/M4swCtIWqAik9GAHBBpozVR3
SWKRcpLXMd6+KWaiEjm5QnwyRbMgwtn/HKFr139wqRNKnMe7gxVSJTkdQeaKwcwVT+C3zZRDr25o
uzOVhQHFFzHk0TkoF7lsJlb9XaXC/LflrjnJF1tMcaldR+Pir5ehSC6KmKrHodDc+2QfwjOccvPH
Mc7Xt695k+fO3LOyJ0ncOHoDHgzEVVL8swesHi0In53mSHhQZSUlOo4CFtdzI2p7Nz35VCEkVogp
IU0T0BDadwJySy075XSWtUmBnlPe8TErOI4dR5Jmk3GYjU6CbjOK1LOLUwESn84AP3vifHzYkeUL
TFUc7OqQIVWVuVf+YLmeQI1VyswyfuyQhmSRYI27Ke9kKNDTopU1oSex2jWYG4yc/BWsLXYYP/te
tc47RXMSeMKAYdhfYbocCs0Szgq8hZmwp7dkZgOhdZMOyyhkKOLVc6wpE2xrdjFvLog6VJVWCHub
CEOboYiaQG8kJA+OTFlCj1CeDtbyjzPbCS16m9uOYvHTIQ6VH1VWr8V2gruU+aaIXIafSTOMmjJb
gTDHE4klKG7eHB8nBU7YHDeHrbZ/5TGONjefesuv7CFLysyPfv00ttpLzCQw07I8ndAzeiiLGwO2
gmJBSeAUQ0Ui2CX04OepRlZKdlxcE8qZAprtOmbXbKL9++FhzIN1aTqiCXWIVFEBgvUxwea+lY+I
O+nvRvGT5iN3oNQkBohES236S4amttAj+PB4ptIBtZbKFw1PA4pzxPSRbAeSFjpUlIhev37JRNq1
TQ64yv4fw2Gy3EYW2nw9LDqRfl+lQSV36lSrPOJlpsDR4Cac1SuwXYeVvt2885N+bnWC0Q04MKin
PxVG7WEhfquK16Dmreryae9l2R9RsQmrWq33tf6UNpeYEKzRuNJU3lqpOwXnDyBPQYrPcI7K4sef
WSfxjtTq3oDDz70QhkNCiS97oTvwPIUEsHOHR+ptNi/xX4rOmSLvNH6hMXi83dioDZ/DyRz4Id7K
+A7oQPdxh7MZT82bFmn+mTrCnSE68tkX1K+6rKp42dLMTCmDfZjOwkfYRS9+Y10cE7lFYbHpGOfT
+0JnJ0CKDGD2vSB0TJcnJtDXmNcLZMayzQxG/yHpwGeS8GouKdXqhentVw9Q3L8TBnmIkLSiq82L
40a7PaLjdzO98rLq+2Y6bqCr88TO/75eDrAVJJyLlEhHhdumx/dqNEe1NuHpAya2/XKoLWhDB5m3
95HIojplh91gFcYC1qnrqJa1JI3NtfsOzj4KCTTIy6poW7bi9BJQL7rfolBn97VzpRZO/kiei9qa
dyAjI+MD4mwjEw2TKOKRUu1qN/9Wd1A1Zy9V9sqDnY38cz3EVV0UE/sb7sP79RWmW7d2W8hx+n2B
1d1SjRb1IQObbdl60R2RBF8xmogSMQ2eCiBBLWvtSSgrCrJue55oPmJ8uk0Er6oQ1wJKt9ABh2Pn
9AnorRwTo2Wrp7Z72pI/xHowKprpRvAR3c1GaxevhfernUYt4159aQRTUfqjQoem6rHL0pf03rPO
p/U/g+VUus5IXLIcSyL4xyeFoe+ujodtE+GjnhkxjB+T4ptvfIQWNkbf442b/1hEyTcGAY+GDfe+
nCuW+gJBmu2yrm22VRzQaeC9wEdo+E7kqlt12cers0drJ7apiakn59YvpYrQaZmyGzXaCibrQol6
m82CVpHzZ88yY+bbHLy1N81PxGjmqMLvVHnLPkMFACQZcLplUHReuiPyFwDG+4V4nS7HX4VyHYHE
Nzkn3SJX/1WAYWvwXw00ue6ZubU2Nuy6Ax5vKMsDGxjGHHMv+KJ8YpYnwH1D5ZwF1zvdo+NIiaHZ
8zArw5Nw2Yel1RqmAG4zqS3+wTm/ejHgd0JwZap7GCIX/S0hBU6hFpsaIFFC5/ejedhTEUeS2Y/Y
r43VaTmA8f5AxZpNgBBbICVmlDhV6tIPmN5pfimDOcQI4w0LnTQkpIMNnWY/iwridgov7vH9IhmV
BRftQ3EfP3tcJ7wQWM80sGs2jTEM1o8aa7OFkn5opofDbWB32gg2f6Bz53RemWd+axtGOMIYCFSz
Mf1TrwKY1mbQV/GrwnS3+TsVY9jAGwC/+2OtEM4PMJdnTlG3ygvGYDnVUENQ9MmhVhJ4micnpBFl
5aw8mWkCjTZXYhGJU+N6jxlqA9O2jq/8uUarYd/KfEi4DxU8ceAhbgDpknStkNaCejvlDuOmg3BJ
GYkQ3cGXouQ2+/pk/9HenrumR2jEU8ydNSqlmeVOm2Dnab1+83dLdWjU1EVWqD7WHWEl74Dg2yo4
EwHo3buhduZXc8SlKEydyfgx1aTEvnDJCB77JTqWuoaSz5x67Kr+Soywyk1w9bzLskZgAJhPfXzS
HdnJ/Ip5mDEO+L65iRHYTzZ/lcMUuQ9Gga90oL5N2xSRY1j5BqdiuQjaEAu+xVYyalwkJXDT9Pyv
/qBGlzyZO3ma41BhkRIHyp1T6uGGvCIDIB9NFBsD4tu5JYD82LNDXGQvnsxkY9QX/WiWDVi57xVR
ApfDPgmlGlvKL+H6nHJTaZjUyk96Ihp5NNU59f/i1dlyxmU9oL+WE2sRs6xBNdqK9G7YtGh1FlOp
wECfQR5iGVnlQkjZ9qrwtyGku6yhQ72uuOOtBELPJDrh3TrQO+P9eh0wNlaZSsEKXmerEPheFDN6
4bXkHUunR08D//3fFrbTm6jE4fjZYgUT/4MaeSLbh9c9GzWecjjWSVPhCf7jZpPHoIOfq7vtFPU9
rTga4DxecRb9FLPTbIb6o8/Jeq5t1ESVklOz178KDV2LGfRigy9BxU/JlJPOT9T8PkjA6oJZmlCp
jf21OiCRtoHtpmBcvWh1jCXThUxIcAoWpg1d26Q7nDu7LNDGNmjMdtCu7x4fJysVR1qKxSdSBasS
FvMr9cW2qom1FCUEhV6SMPpswmaI6/KLOCUh9FnC0srZSA3ifa16tx/PS/bUUOqmaaA+x5jHcg7f
2L5zifmJZXz4uksUL6ufk1vK1gpSQHSEV/XNklFUYEw+Gh5tQ3xSboBC6b2g35OtJNEclVriW4g6
gkQlfFNZm8VfaWXiN8oZ6yPrbVU+ADUaSKyMD2cI95g6hu6HUhC+PAtONrEmqOUnwSLGPVCN+v50
kFJQV3k9kJ6AfKx5uolbD4Ni1m8KBXocij79Ix0516T5Ly+sZooZhUuZZzJnMyojSeowQJKY2TvE
+JsNwMxGvI0zskZ3d3BaxUmnyyp+KLVauYJF6bOggycZP3+m5NosQzkOKOhZt5QMkMlq1v5mLow8
Ci5MKpoZ5XAukQM9T6iR+onv6NY1eotb39i9UDD20yYs4PoMom7bFESzvYGsiStcFma1XN83j7GD
hO4rKMvsyIOc+UBvqUQpoyscTF4Binvjl2rWIK9xPI3NB/2xs7RXxJ1gZA+X5ZNc9dlQR39E7qI0
FPJU7b43XGqMZX55bSnAvwW3hCQbC7hsE+Hta9QfrtzF+7LkYHpeNstzZLx1VjvUTQxtDV5YDKGJ
vlEtpptL3rTiDQOXvZBVZrpNE0i+dERhtsxshUY3ckLaVPP4uCjBds3Cxh2QnGhF335+pfAoLy3p
Q2SL+rnED8nY/YOmSnG4zoEpJctOjjx5ZVhPfMV0b4YogaYZHz3Xf9Csv/RBXq55Uf2ImdTdmCJ8
M0nqYxCJm9OPJLgHZgAhRZNyHwJ0+DfXEaPQHcLdxKNOY67kiOlV3ofZM3ICP7cQs2M6jRoqYzsW
swEZlwZbqXzsFzNfVhkLi8n63JLqOfJhKndzFyCiHPxQ/3XAiP2JPxJyFfB6NpTw+IJfgsI0NbEi
fjWFdhMuHf1Lj2QUAccfFgLy+SJWtfs2A7K6L3paciE506rCLD9NNX8XUwjeMXoheBUk0nSK1bqX
eqp5k/kd+e5n1nFX+WUg0cN0XQlTyYSnX3Qzl0NA2SEcckaUrSjF64BkuABJm4+bJ4+9QQaR5DgT
GO5kGPOcymmIrp3EBnJEl6RbQJMPot7miqXN83IVZ3j1sGUjMEZDeTf7ke0q185qjoIGcwTr6pAS
R66kSbHt+QhdOKkt5JC8wSVQ1Uz3y8JN5+xguJHJ0iNuQzRwo8qpFgOtuvB4ny/ac8nygBbEKwlS
5frjlDnVEHnRy7CzXXuy6DQ8BWYeV9qFfw3t+FYIpP13P0vgpZ7fuVS5J2PprHOVoarbcc7nkI3T
QEjiJ9k9Ss6EHQSs9n1QxiiFM9PZgwl4QKEb1r95Qits1LJzvyKQL67Gv0N7QTbh+GoJcOjdfZl8
vSyKJ1IGZTRiO9/MM/ElR5mztwNRKaQvrTuP9/dEn9rrLFCUheaeJz5C3QU57lMKirxy0orPooyo
SPL5sjAGNEaludFkN7/BW/tYZZgj0VYFiWZVBKr+G/fEpky7sjJ5qN2meiTHVLFNeOMo+xqj1o21
dahhCBf4Oko78d1u19/fgxwucEvrmAm88Wc4qzCSvwi8hj3cM/NkaXBlBzwNWxh8NgKokNeNJC4d
ARi3NXtT1mrTZOakbv5sAGx5ioBh3+9h3qbTaE/nzNR3vFo6pmzrpygs+5YiBcIQdcgt316O6fUe
+oaUCKyXM0sXDHMCtIAk1YdValPs2dY4HJo3R1fCgaO+dC5Vm3vYhuyReP0DbEdJD1ZXDT10ina6
fwq/yHkuBojQtwYTqW6OMu7lTXtwSk+GrrJEIDa4mgPq6ilFP3qDH2Ru+MaR1jOrQyCOZV1wa3g1
zqWG04ZXeIf8/eLBSTWyl97ul07cEN3vOtYFBzZd+jpM3xH3Y4ogsTfk4/wZz9YXH+obdUXiuuEa
Iw3q1Z3XZzZ5PkA0mFNfHK+YjA1Mh6PGjNpZ6KU2/9MftUCLHXjRZGGdx4uniUQGMX+6kRj23yj2
SrSgZWM+DQGLuDaEz3lMShPn2qediDzUNFRY+fcw4H3NIuFxLPQhhQwwcacZgyhZadj/8EAya8lY
rwF2QnA2d4+8vZ2CCLBglFqGG7J3Z22CIukBerXu06DrcEWnBSumS/bRuMur3J3hl2kN1E1Q7SWw
vBrCTLIrqEaoNTKDaLytO9VGUwWa7RCmbM+zrcb5kccjRv6MNXILvCQ3qLPoIsR9Q2nt+bmdecvb
7Muni+CpRT1AXt6pbm8fKGfJ4e4xiPQk6jZWdORz7Nr63zwMKOf4bAKpUtUaYQhL5gyyEleYY/0c
mYWf2Vv8O/xu8qDWwr5qB3RznPOKC31pQpRd278pKIzbUzjTu8RxIICpt5d3w30EKwiNcEC7WcVn
m5xLUnZAJPhSwpXMihJoPocFt8oOBvVWPwqiwUIyfTJmWn7EnmbPlf7MkMGVJknnp1ooEvgu/aXb
JaWon+JANK9iOccKe4G2ovlf2bjlYy+W65r4Lq26ywkarfykNKUyMqR5XFJChsw65T5xSaFoTuYA
PtweKLawYKbLoQ4kWOWSAFXLjmy22wJ0/lHoHno/1Tl/zCn4Z4ghDdEJSdujGjFv77vULAfguMHI
BpGWIUKT5LwN5uWkmksJ1/s8be8KM9y2hEixNWLeX47OQjVm7ZfKkZ1ClBGKWYOudishxy0++0Bn
N2D0AWCXLkRKLmEEL4uZlNMg4ikpH4UBFik8/v3ZLJjdURKMvUZ4s1zGXQ4vIHh32ERYED7b8vCi
JIgKr/63Wj3cN1M4ZOeIEHDpsJXeUwurI1MPrymzEN6gCXDwj7IOJcshma+klq3uUiHjyz2PSp/k
wI1YrKVjzOUQHdq706syT1/tjJk8FjhphTs1t7QzjCMNLKMrsrhxi+FOaHUohun7B1yK1l3dEeZu
o+N2SgFkEc0PWlzG2vaEfa87CFDFXvI+iJMnQt0cUEXDbokSLnss2TV366ukNZt7pKKjLcergU/t
aGtkc/NdzvSDo6dVJEjgYZ+qAcVnHw45Sdrxd04y82DjHNc063gMmZkgDIaCH8o0T4mheH4k+dXe
G3bgp5g4L1NORUmVXk3ZMJsrEl+uJmIMgom43FCHMFesMK+tJU5ZQtAJbm35FuaRag/7rE32jMG3
Be/uOoQfg7bMqPUBNyoLg0isKTjHYArylCQOAVtDZS5QJCsnXS1w+4NI5C15+ZyYKYou+orBGVRc
ZHhsVUKz9+P8cCJ4QrbYOhr8VAM9CMZIhntgbUR4P7vRm3rHho/ky9tSY6reRDPwgOgXcu8bSxAC
tVxp0n30uDFu3/w5a6K3qKuwAJ+vARuGa8lMSjhpgQ2Tmp6Q0BefM5UHSGFocSnZR0g+nHoBCvRW
s9A1iwKOt13L9QOy7E9yuXPEdfR1fHdyW2PqxRXe7Ow2awY+e2qt/2tsfd5S2LUJiytZqpjZpe7E
RI+qS7Qcg/PnXlbee6c0n+KdiSHH3heusstYVM1HWQ5/dWKI2dI9GPlRXMal6dDYrA7bnCb0Ospu
O9ysGfgdfdqOYVnfujNA4/R5mr7wlaN9t05rUmNfZLwTXH1NvOh0X4rOcYTve3hPSL8VizaeorV4
YBRfHb4g+thip3K2eBL0jBfEoBTgrY7EVnY/vOWOOgFtqi6eDBSIZv5deRVmsqX9zyX7qi44gZre
mgDqc5PWpFv4t5RQ9o/g5R//GqQZDSPI1oYTDKqaK3wQ/aMKmVp9kwAvPgJ3dnlbUPKGK8is8Tb9
H/yqkUBr11aJ2HV0lU94Abvf2h2XniJgS3JMVsXcJ+K6g1m/JMXYjwpTHgnIEJ1kQjhIzD9o+CEa
Fclsub/4MNI63MDUvdsPj6Q5I0tYt6B1M9PNqlvHDI6IwisU+SevOW2k//UstusVoE4l9p8sJHKQ
EVPnveuyxFtFuf8BL6LZWr3tY0cASPGvtCRDSr3vhQ56L6TzELbwzts6tf76uKL735euzPqYdB8T
63+gbVmUtLTdtNlTKIlM1HMpv8C1NpajKX3kiAsQum5nqkyZd6P9LU3241Ev2VyUQ4VfcEx0WDiD
XMO5QzFnW1aJXFE1WQZPLA+6s6n078SahmnTiLOmxUuEEvWxDzyRPBmh0s/izlwH51xhl/2EI+PF
XPs+aJIAAtxL55HefUdc7z+sNpuzBhVLrd0gH/3wyZeLfIeLQjbwJzTYC2yRFQwvVgF3rF6PUNEH
gVk81+3MaU1vyXbPW7DdCvOTIvtSdG+31D2wE1oyYvVDxuAb+PmZEO2exl3YtpSPrL+eSeAHscU5
gGyC7EgMKPt6+m1vz5qmwIYma/8+vGs1opbQHRiG3CCnyLZ+dUsPkjnQKQIRMCwjD3kJogDVUd0I
dWLtDBuDfM0KAKlaRN4W7NH/p3DJNuzFoGjHNJmyjiwczZSzXj+POvvzX/I8Kxs06oDfEYKXQQl3
e4CIk14q2oXD4zywhViK4HWp9mI1diOWDKCwGCkL8a96bG5sWLmpn6VrgwtpcY3DLQd4ZH0bImLe
HtIPq+pHceuLd41VeIkSF/mehHqLPahjVf0eFzMbD8zOCV8JCIywtAucjoDJc0xbFhOzA0PhyBAY
W4VRefmUXMUBrK0ChaImfoq55/za7a8nebXCJ7Pfjvw6U7LYoE7GQBs2fLxrbMG9ySREoBtRDzkd
yUfAohAh7wBExtaM8m1V9EYv098umDtrjnXCyFbiFaP8Fq13y/3X07kWnWpbFM+VwJs9uolTck5g
fLjIeGZ9JQbH5KkNz/ltaxv5Ktbh3o98CktrCCqFJsdtMobXPwz766FFUIGOQljNV67JJYGiRf4c
5EVei6H+z7Kb71Z2xq0ALqIdti5UKbHZdVdQ/AUAKfDyL7yMleln2YVo4Iek5LCm8AcJUEmyca+0
ePAhbVAlPVgb5yVBQ4zeeF1l7AZW7lXWfytHJwVvX7e8lXZH/Ty16bugBv+H1hriUqDiMBf6glST
dEhSh9ziTbA0TDBFAVZQxB54vOp5ELJuXJKPB8Ba/EW6iO1UuSrhxN2gWW/JDRlKoradEAPopjyC
uBjkzrCsAiWHaHw27yj4/7OaEla7Fb0sd7aSD4NQ12PHedonGFGz3lCL/espRe5HN7fRAbjtuhgm
aGNA7l3oNHqoBpt2jgUVuUE4xf5J3OXHP5h82EabuVweRi7KmBZeVzNvkGx4HYpCgyf/Nx8CUbyA
V93jZIKYjczmbXucF21oXrLnpNLh9qI21KDenmClpFvPSCgr1e2w4plW6cxLO2sv4BzDzYKqdOAr
AygyiVAzrZL7eaTGBuf++zrcrfznqpXp+pcXm0Jp+8d37HJ5JT9AIXBzailrp17u3fInPh3TtbmL
ICltdsJzCIlVAGeazbMM5lRlaLD+D7Cttv/S//mFsXtERPs7A2Jf8b5FjEKX9ccw4xWChxEsytld
EnkWktIRN9S0N5rIX2X/Z0MaDxhZ2d4Ym06exJ1HOX2JauRsuEpdKUPd62/qUBKk5SasJZh4Ce2N
4dQVSnVaWtxUtKYMMmUDabTu3p9za0XzJiPgJu0h3dHcbjhrAgBjz1AEtbHYEJHIPdJNejZqmQpq
h07RychOpo6ObFycYTl17z3cVxXDRKRoG2svaw02Z7qDHiGS5Y80Mkv3M66VfAVMTMUVBHzaUkNH
0X3u4EhB2Odx/wgNji5coHhvnw57YhJMhUspIfqqcX1UjHUYiLeWEwsq9elC5AWqK38iuOicHsaV
EIzsVriDErdx/LQKsbAPydsrQI1SLRR87NwcDYnPuCZT6Qx+FcJS8rm13Pw6XvgH30804ILRU8uv
96LUUYOw43hEXdhmiMCr+kpZcWaH6J5Hpb2UVBbbzmqb8StqffPnZc9LMP30K9dAmQexd9oaw1q6
GPrHaWUCjA21FwbVnQyMpjUTcDWGSY1xXWc3xynRqSjdegljt0Hslq1P9CsnBhfCZ30ONyFuQ7i/
eupXRwbUx7P34vuw7uJQvvMNeKcfi+b3+U/LQwEE1woog0i2XxGdG1N/tI3YHpFCXy+BybErRWI1
uFowlzgaM/GrwKjiGqGBspwEIjOlzFXPESpdgykC3ZOs0smsfDKTd4ifVeEquEOGKi1LrlboAeKn
o7fsgMiAgO2HXclpunaetFOvSygT2Sx48vFlruF0GLDiJixft35+eTzPkaB2In79xxcV6YfPhyrC
NCFZiukvSUaRaKotSySYbnfxEs+jFdQmPdBCncXgQGeObW7L1vN7uVxwFtazASmbqLHayFd/rjvx
P+nKmVVpqVuHRq59dffYfZpYwyC+xk6VRj+9L+NdFheDSA/5fh3VrZ8PNrqF0VtuNV9P+asydNVt
6mEPcODB3IA54s8LsuoxjVYhC0mre8P1efYstY3w9T7F+OGb7KTsL4UuAIKMYPHAWDHOf5qhNR7r
MgTP7k5JH9TuK3drskEscUYqAMlD/J7yvfG9lM9HrrM5ES/43i9u4YMLew5kCpurC+FvJKBqE+bW
KumszayP0ImQC35Fxsm6xQ2FsJi43A+JJvz79sUovZ8Bav2tM2awEPF/qtiKZ8djxDVrWIIE9vmL
K68ArqHrU5HpLoFsepacl34ixeKEuyFRYWYBgg0hGYmxmuxi7i3hSd931V9uKC3KH/cXFj9tpx8m
htbR/A2NjluJrWWYqW4N+IXNOovNDHGTp2Kn8yN2JZUITqboaUO3QZzXvqMcwTcFXBNlUGlUELX7
2PJfKNdyjfMxNX6Y9ROHXAZk0k0jIeethqb1f0ivrF4pZmbb0Ua7U3u6kxLH/MYFYmhadKQmzI9A
ieHtvaYroNihV7wXDp3LGDzITyy7dX6MeVP2f10vHDiEB1ByZ3xVkWXMxk08E/306BD3DR/dhnN3
t3ktz/HUN1cVVvt01lPh3WSBFp+coImss9yuUx5vFma6DvIRUfhdALPL5jZ6L++xlrhlgjkYTY2y
MWKzE8wy/HolHlLS09UZD29cYIMo2YQ9jLP1+17U56RC6wYZcuGd8l8oK4TNXqRWhOPBWDeMMt6X
QuiTl/ZgZOKxvDEUzsrxjg7yj/WnLH1r0hU/ecFk/6cB8pvoe3maTgySB9XVoUiwYgHRigrwEMt8
dDBVJe3e36yuQMp7lbx8sgIlrQtk+SgPaCdcudjq9ta+nAbv/vZdXTwODLU2Z1/zrT0qeky/24Ld
oafRNYWAtI8O1NZn6N6mO6wi29wJy8kMcNm1QebN5/5yEIrs8QeL8iuMzm0dUFqjxsRrSTOwCQwn
YCEAhMKkMf1R4RjYjOt9q/GCBspxCMtCZG5Y/5F+eNXp29OBtfVWESOl1HUIdDQ/pITZo/R3+il/
/tDryr5Uw1c7iKFHlQt2juaZXyMNQmH8zxGj5oPIowgR5d1dzSuAjiR436taU7dMA7Gy7nlSnXzz
umhq+XGtSJYld2t5h5VwlXnjGJmnla1i2cUKlqeAObqBht2nThq4fUYzpwVrPOUDjKowBr+hnWtg
xiIhbU9DpaWmzAFfeOJON5N9Sc+PgdS1gnyZSJSJqE5FlVLpntqAsEHp2DWzNgQM+auooM0/f0ky
HXSnXl3t6gkIzp0BA/wFLDoMOnOG8oqpvSCc3ts5Z4i/13eLb+7qhFtdZF/dTxc6aeqZ8dwb5fdq
7MwU7D2CLGEzynXpHJHn2corwoQ/7Dcj8SNRZ3P3V+GInmOVQGIfPzZh81KIrHB39j06kTnLiIDy
0AYC3QCHNKfm8L0lrc/+5rmpvOzCSQLiW2H/JTVZJpX1LbDS9VW6tZH1eByQPGA2DqLYuIgRtqPY
lFR4ueX2/klVG5H9F7WwkURYOQEtRETA+qm1xgXDhiYL1r8/kHEansQfXcNchXCdMNfJGSJCnI1P
i1nUdM2XVQBIPEEjbfMy8cTZoV8mDYES3vZ4gYZLiQTIms0Oc4P502uR9m1hO3F/ldetSnkUlhlE
Mi0KKwM2Wi1ScQZcDiZJfnWJs4DkQZzTib87wF8Zfamkm6YOpXWnCo9WkyqbOFXrwSYOZ9KsnFpU
vQfiloOMQ8B/DsiZ2ejy5bUXZMYcY3ct6AlQZ3FBb6+25dWAPSI5H1jbYvVfZyVLOAi2R8JkWo+I
QXXtS7zvfgaSBbaJSgPBe5VaudhAkcvo8Yrine992kyo5bgT2pUg050dhhs5N8ywD2VULwfRv8EB
K2m/38wcs4lJhjwcMo3sJ8elNILd19HHY/C/ngi51HMGKD9STD+f+e1Kncptbk2SAzuNulyOXJM0
qmjUtzEb4yjb6aK+49N56SWTUQ0NtO29dPbKJ4gIEy9UTYIlASvBVqzlyOf+cAPGFNWo2UT8YCkR
o3TnlZ3513yzgANHOP493HyHaWv/gskIcycYOMfXJGVI8GPy0/GKOftLjxgzA6jJD9qVGQUAsBca
eHn0iVUZ3mqdMxdP08k6gRNYwshkGveaqF+CgUarTmXLMsqaUdImJehqrgfi0fYI7yIjNexjVVO2
MCJzOdiA1Cco5KvTuJtLRC8FYotzoTQU3d4//65Kxqmwi2KQJNteDPzl2AzB6K0/u2XLwkOwRkU9
b9Y32oTzbS3x/8H9yNb4rDWmuPJQs2/dqXh6kHiaMo5MQXZBX1xt2Yj0xCIPsvuBOoEysL//TPyF
BfU+e4rEkhecKvqPjAm0qxVNgT1DOjY9C5BbUNw35VfFsqLQFlPrEgA0sT8866NQaW1msWpi5Sak
7pUye0+pB8bNg/oW3jGhTyBj/dipYrOY2i5wDLq5eBcPZUhtm/yIEFnOlh+SN6tLYEukX5YRu208
gKj8pQq5ex81VLh109u7YuKBcT/ttz0jDaYdbGofT6nR2iAPNt5Ryn/REB+0dYAULDd2qHmIdc/c
thNBsqfPj1EnxDfyiGSaSpQWpQoRlJr3DMDYUkcPgNa0Me1HtvIdcanFUmsH0R25A7aLWSi31oX1
h92cuifmzgB1nA/ItyBYiwXo+2yUTLzmz4q2RYv0M0Q0OLwsYfS0brWJVQ/mjdoF5KW/6uJiQ4td
Ty6Iro6bqTk9Thexs5Spqtw/ck5KDVjJQrS2/dLLToklNSddnMLP3kuUVqRK2xC1cJMLj4UoRLz1
ABYzWR2Lmk9MVV8KK6mmbMJzCeMPQ1DpucGOy0NtWyjZRghxgKacQCVECMu0ce8jahdYlPrv+Vzx
Y8B+AvmZIlsveu/giSRmVBVDKhDvvHr1ZOB5ioGxbp0gLHguyTJuCGs+gfeItigq/A48jhQ5v9bZ
f1qXN6xXxEtTCi7VaVpdO3an9Rda0Pxs0Gg03WhzQpCxukdoxfaI4egtOn8dL8YveFX7hLwrqWF3
8NGIjS3tSjCK1uHvv6KMv3I2GNv4Br0tdcfMPKMgEtJarm90uanCNCVZbnQigP3w9Bh+nh4zcO3o
ugSR2vit+WezMoOLnehllj/6woMEL7LRSGZz4O4EEx3qrZOkuqdEdc3YBK1TSnbpSCbezVh4h0k+
artske4esVk/7mrO7dABABQfeFFNSgrugnR6EYn3to+e7ugv2PFnURbGLl46VKIq+fMgvUdan0Ph
f8h9V6vzjyAMmdH7AASB/Xa/wDEmwSxG7rn0RwnScaGG/LYXOrz19buv9pHA1/5xPWA5elYVmViK
OO/PaW5Mn9rg6FDrMNlA39vMpnn1OvZidjbs+dgPqrPDErlrcxt98Hg1tUAPQOpQI2SlofYL92GY
MVGfYQDl+KI66M8WzDKL3yl/R3VkRmmwXJudbyjtCu3RCyItQhkdbMUGazp+QD3VBBPjJtAVI1b0
M7zj/g5EEooZyS8OlvzqJl3JL1Hb4BEg9uuJkByC/ArVYL0k9SkovXum//Adqh0jTw4CZwxA3CWT
vawfTFBnxhKTEkFkfxlk2lMoUgvtHwKbt7O9T1Pek6hQpOEBjB8zPAQg5ola74A3lUEJhxaTOIfz
ZK+giutc7MTjwxVeBoxbHIX6k0YTdy38EJ4HZIjd5DX4NjzIeyk8RgJ2D34voriopbDybbtn7RUD
clxKL1GLGKkFev2gtZ38fE8y666xlgePlNqYoBeIZzKP7EmCoSl7acoKls8ylu+y9xWXAx5ZF7xH
rtuVyWXnSD2yWDPabtlepW1ZvgyovD38wK950xe3hjDsB5TdFfZEdhiWL6paNIisgqhrjXY9M/RL
s09lqjI+Pi8vCWDVB7e2+gVS9p0E5b/DuVb3qvaInOlyx9o1wpx5EDd4MPWsy4mJOEhlAI+pr3/D
5zBdRVjXyycNmgTk1IWKSfTGlR0TGU5xnaD6SMTnOGsF3yJpLAPfBN33aCPUxRw1mQJ71XdO17e8
Mdsipzb06oMzTjlA0HTvjXgXX2a5tCUyT6nRDPDsmNaJYDQUsNjtI2z5lkMnqsPuBEZzHjh+1Ael
vn0MYaa3FTmaGT14FmUAh+iyqmudbgDl2RpRWvFVx1KxVsSleOQK67/YU9F0GLOUzXXdc4ilXm3i
D/4JSnm+jYG/ZetkjAEQkLvbd1rrshvbUSZbeOHL5cwpd3Uf/jOnlOvVR7RrhHpls2+2kNx8pcBe
4QW0AD+/jjB5j0QwtAbmcAUXMr8OeqJ2quiyE5y7e4AiR2wJmvi/NlBjf0fhUT+urduayCYtsB56
jH5UncYnGp2on8d2ERYaIiaYXRzhlYGFmx3iVWqmjlpX70pXZFcm/gYQg074+nKvdNeYaD7Q6oIh
Skq+TXeeYVGOWzvoGxOP7Kckkjuq74WckuclFYfUSBJPAsmwu7fbmzrSXS+lvCKW7KUeEONKOOTC
485PfhohrYo0QUasluJWaUptfMjSN4Y8Vy5rp9yKgAf4r+lWcnfalePbKn36A3GaB/E8h53+SMZ0
AJ0x+soaDZOFmHeXIT8hKTUW0mDYs5krcgd/AFMIwNF3N93td86JzA1vpPdRz4YhnP1iEX+pQEvI
CwKexZfxcLRqbE0OjJ0axloHJQ4KsLxi7MLp2xBKCWn5X3cbphJypdztvH/vOwIzswkMLTuF87iB
BHoNMVzOe9lya7OxfWXN0TqDe+wgi65Jg/7iHuA+WhHRT903werlm60Jd3LR4YYxOegEvj8EKhpW
hiv4mHhUnNLASXZXbm/CphOhWzNkVlGPn9qK5S/lS4fEOz6rFJ/a/foO6eKRD1lynIwjw5VpCqD2
0YAkMMfvxoPGJrHJAm3MgyfwCLEKeqim8QdQUI7IXlqrIYU5GdmEqz3Y0HBEuvhbfZZ3Bfvhq6M1
IRPp8+FpxGnLFVJ7BROTHX/rDhaQxi0mkKfFj/oP1vKHOS/S4+QWPtRjHm3jeqYZu8rWBkSRYvJO
k1jo7a8fM9VMSEs5KM/Mt4DnA0utBTrGBEaUelS+UR3stzfGMqaKzbfRAoN5TUBsFQR1CE/+Uqxg
ZBrQc4XIgp5n4lFG8z+jK1aLBhAxWGd7bZs7C2i8wfg2ur998tZ9Ee0aBPOkSqYEU0YO5byr3rfh
wk65euCfFE6oQ5/lG88Fy6ozWah3U4xwBgm7+LOuEOGoUoqwRCQMeCadHvFkgtxFO684flgEEo4Q
MA+sEyx6zEsyOpJa9GhY0QcpEXxGVTqCTeV8P4TuLGkAq2BGGU/59hg0WraCteK7sVf5kVigGThQ
bGanTtNoLzfcp+fWUsJjR+Eayesi7KSr7dTSK0H0QsMFKPHQKecjYQpLNCrKRZWwAlG8K0IMjEYk
dMVxdzt0Sd95WGRZvxumFtgpSEtjprmxLSLCTEi2tzTgOnmmfN7Cs+QvNqp3iAypU26NUGuCxH2S
FqUOCh3sSESWJzh6o/vW8M/EpXzqAYCik1zCTyPkQIZrnT4cz4tuC6fh6mj0rW6DRq5FsO0xFzAK
knwwFqmMAMveVbsfLb/+pFlyiEw+NxNK27tktnKnQOAO9OeBgqpoKvQmo9VIUTtm9jOvJVrcaotQ
xnGrUnd+b5pS7cRfYhtqcPexKX/OIWhg2GF8ao7UbDNjg3O4SwzgrUbDgPkb1T/ABw4qN0i6YsP4
n26K6gMlAaca6fp64+A9jPb6+HI+zmY+h0HN/jB1do3QssKUbW/H5jPw4NcH49s1yqzulhoIAlNw
xo0dvuK76yrJuSAH6hgMLJuwIr6UB3R8Z1jlURkrgN4Z/asu3aTiFA5yTAF4nQEkxXzbcLrZPZWX
nLRPUXML8lW+0QGLWOYwtWKyfxSxhdKp+DZmASxpPqBDPwnonxbgwbZSWVDwBA8ReAxty0yh0WrB
HMZO+E/1RUfqLo/4fY/6rf972oqgT+S4xD9hSpNGZno342sEj8q3HPoLwk6Y3kUuZKscUlCSBFo2
CkRhNyQnnw0YKxsQTqaDDmpifXDM5FcaA3z0zHm+WtNmzZXnZFDz4/WxOf9UhxQ2+v+ZbLTlgOxM
vP8w/0rszWbiRRuNByv5skcN43/y4MsusUM6x2mv/WONwMN8VSGQkDq8+9p/yZ0xIOT6M4eHvIZ4
HauRHwXGZpLANDjudBaUwLzKn4Bzmlo1iZ7q3658bubVhqNZ/3TYumKohGIDOC9YX2TyEmVkUfJy
C9uJbKbv6QGX2H3wO/2dk9mYwhrh6ahRCFVbHgCY4flg+1tUSjHPRZTUnN3dj5BrWzUkSHxO1M/T
UCO9PiSZPclpU2T1TbcScm4WnVd7z+/Mq64yxcf+fVvE2qzD//fhicia8moXgblabRs2eFFZNUCz
C/rr0c4sTH2Fn7kkQDK5/GOgGW1lduD0bxPe94yB9L63PWV78RwAxNWTv5iwr4HPQlGNtKB9df0+
B7Gz7vJcIKzAClKzkDxcZKZQzkIWs0fSdtwagmL1tMO7prxw2OzRADG2mfYn3c6SlwkRYqYRYzuw
iTtxUvM2Ll36YXAMbZVtkwgcVQQHkpphDlfiehN2u6UEUiw9nWBIOmdYjnp8RLNWcMoy3cn38DRH
rXvfaR/V0skk89IJPeOrXi722Tj+/ffTZvFqKERahieQQArMfFA1BUL7fa7RTD+AWHBg22tkH/9P
l4fmHcM+vjdHxit5UyDDZ+ne86aLR5TQOJ8n7H4RXjAKI7Q2FT3hqh6lwqeHOR5I7jqPKUl+ifxk
PVWxSiLqa7njtDv2TBLptzXMYR1mYq/Oi0B8uNRMO1vl+lrlCAknRpCvQoifxwoNWavF4YY+mZVK
fjJOmsVOEfvcmApAmmd92xBLPf5AHOWe33XSzcsNdj6rifrtP+olFzHuby4tCzd4ichRvhrZSSPT
O6NDS1mKYKllSkDXTqN3eVeQOsAme7xLHBFyUNMfZzNlnhial+i53tkVdF8Vqx5f0vTj1o/mlysY
n3cepQ3AU8VxbRfmN1bgzINN1X4eVRNMgqy8PdGYi7A4nPb8YN/sh15WlJI6mfxrddONs9sOAykm
GcgHZk2Qyh8vHmTxdYF5I9OFsy3z0qHzW8+ybJjDC6DpyxfUJ2ibOO5XmKIe5jcrThKGSPtXLrSM
KBEDk2ahBdxWZBk882VT/mtHf9gG1tCT+qtYOXSZrlMWIrpUf23NmIYmGMGqzWggr0UdTopm1CSM
6AY0yBxyhV6/4MF1EHTHmudiwxOZ5JsHXiAUsddAHfDzrwkYgH/az/dQJSYYZ1JTMZjqsaGMkKsn
d6fWiGUyER2UQq4Fa+EQl/prSEyzc+4DntOd48ZpyeLUrkANIKypkodSCAEa4yF7GbGWFC8tIuK1
TkYCd0Y6noOxCZYGm7ksbHHHtD3eT7HMoS/+B4plvSi2/+0oSL3KLUUqsqJJ97LBV49MLrrQ0mpk
cSYI8JRFhwEjK1o6pfQqOehWlftvkVNnc2EUPpnGWQ5w2LJnUiQ3pScRF3IhTcsM+g9pKy5MqSit
SLn5WcYxpnoqc40cAfoCdYexFtmB8jEH54cry7GU+QRfRn/l1BhRwJjiTcOthjV4L0hLcLIPgbE4
a8le96nlzGHbmfT+lnqY8axfMC/rFX4Rs07xFQ/NLVrJSyeWEthemFhRv0tTcE54uj46ByEsSj4E
gAWMxu3pOJLc7FlxX1WfO7X4SaHT3LriaaXd7y27166WpLo1Wo8X/kNZnsoG+lkBr8bucwWjhgsQ
hfI2EzbMsqPk56gRnSlrUlHLaN6/jJ4uPAKUy8+itLlNw8tB9tvJQjbYWMymR2n9WWZYUHD+2gF6
LTM8sGgBuyiap0xN1BVdpdQWaUYWSh5daUHuZVYrpzuedN+f/xzVKAFzU3t9bYcPuCWE4NpQwJ9X
8RFbUNNLRd/wZyXsQYfl5gW4xSGdzvYZb1E8EbU7xUD3HhaZVAvZpMZJTr2Ng1+8HPy5uAqZ5h/G
iTALZphhMDiZ5A6x4Ie1Jm+RlRCGT+UdpUSpn57M4shlFCq25pZG0p8ZPWxyl2WjhdFPbn+4BtLx
tCRCzHUcaBU54VpAColIJgeYRb822+IZMTjYT6KgiWBoHbHdrPEed9sBefQtDZ5rS9xBJo+kHCcr
MCKCBY65qVuDtG/toAclQZzu0hrp7m0NTgyLpe7UaIGS+0MNMqyrm0SAsr47edhuwG5Gq4LVpHGS
ymLGS8BhR7IE5GeDwuBt5DdN1oEP291NUSJG+KNJwDdeNREenBsSDCVHwPRV6Y+M+hgD2b5+X/SD
cVVHY1FixZE9macDlROKRvsqiEqvfJ5nEr6CfDlnLSTr9ZXI/INzigtyHNUFkVZGVb7xUlLSN1ly
HoFUIT6Xdy8gm5kS/xXVnsE6M/QfujJf85EfSu5/PVg7HG+ARS6mb/Q44FyHrzQtS9Ud8ou09ees
cAZLk8fD6ExOAnJYwjUvAdWMHiCBw3hUgN0wTRrWQFQWypuNWF2heT2SpFIMqpASPnrni5mlNr6c
MMqQRPoQl1o9dehh9uPv5L9WukQYlBMjVpRY5/+aKrP6SWH3qOHxSoTYyEE0VfbxnsBNkkNdV4Oy
zklKev7LxdfJyUhvBawF0AjDRW19t38TfsMrPwZvzUGST2MqFgchGOVrP/+YW5z6+MmPUfeS63g7
CjB77Q3xmyCjqkRfw4q4P5VfrkXebprv/zg9KvBU2nve4KK2GXfTpjyx1elAsKufOsFYWPQ6v559
4cLW1fJ8QWatr2P/olPdl0X01ppdDbaT19LUH+woVjYGBfj+lOXXJ2LL7F8NEAwgz+R19XKbt9ss
QsqPUVjUn2uaWA4UqVnQKlU7tlqqzgSV/qTkfnDIgmDniIaali2jx8oqykXRc1QV15VgdbLDVRTg
7MKFAM2CL6eF7F+E4Bj6NKd/GwBpGFOsgA7fLl59FCLT+s957jYbvx9OGaf+sq6rIjpmFD2VIWJe
3m/7VQWlgfkRRtAjVHuJB13bRUzGd1JNrzkBrrCrzo8jAnufP1u2O2LJVZY11Wm29XKYhlB8ss80
H4jviq75EiG6ohBILXOyWfOm6qO4YhSRIaNN4WrT5B+uuwgnqp2j5NARZwYES3y9ii/bVaQYBr+8
qMrh7LHBClXXJhUDpORT9mTPggfIJJa388NnlG4I19F0ou/ykhrPLcC0KSuu90B3+ddp/hV7tY2n
dHZ877rYSKGbfiz572jY3BWAqg21NNASxG/k/3iiTC96/3iueebwKTRglmjaJleZSvZVH26JPU9x
Xxow8Vzr92RYDIjM1Cxxf0FUE8kD4/fPBUQhUZi7CUe7ylCPEipuueXcYUFvp6vOdlX19RGJxcnK
AJ3xPpnWW7BVWOmFiR9sNU46J70oSNksslVKKzLz8bmRakCWIPVJZAEHJULXxgqyElbD1PjKzEpF
INFPs/nWPckn1Rx6HKrct+jso2a5U7oin0bb2H2yPBj3xJ+eoIvoArOfiHHfCuW6+SS0QC2r7fuF
a7vClTZvnMuHs1sQeWrKfufiLdMcwz8wkHH8C+hr4/Eze9KdY9h3osdCIJRt2JN6AXRpo9NuAZ5+
hML4K5Dra3PkTHuLvYtqGY/88Ex60UPdn/dhFe11Wt9fd03vU0M3n+e93qQyUnbxJ7yKHP52bT1m
bneKA15WG7H9NcShxpkwI1xmFsvo31KAOSJri6u2PkTyP9B9pdius3ekeMp7YcuwrNtqjzoboNX4
NNihHvcW0eLrj16YwPZCn/f3CqaSYPAK2TB5iqfSqesKtHWc9iED5vaByIVPhbk+Yjjc/+ufq/BH
ZDBqZ0y6OeG9gKrYjGQX/RL4NBLvroN6F8vYkeVEqrxRftotvpQ67DmP8SSd+Lj6SduFoXbX7y0V
rm6unBvFqKSwSlVoZHnjJJvZkJspg7VONaaSHTlztOImhdUB4O7mAv60gltL611mZ3KXqPZOS3+O
8/eNjoXmIyWyaYxoI0kC/CKad1WFC1p/HT4awSIwOY+P9BM/H0uFaA62xT1lrBNBz+ZjPazvKqGC
KB3AOvAaGypzgf7/tKH6cPUiSkEO+4ZiF+HHu0N+/5S/UC/ViaVvqEk8wL49a+b33a4kih+5x+nl
kYUcLw+HCM7nP4RJiv74UwazJvtTUdyKzMyflLZkcteGO/OmKMNvXPjJk9nW/Z8t5FES493DkRgO
9AFu7gXPaAkoJrcqvBxLQ28fCcPhE3EsneHNDKJXgbqho/s1Fz7RuRNDi4OJRvY9ZjmXOW9KRLwo
q5Uck1ASjgvx/gb5U02Xn9h6usyJSArYG57udkoQuaWrhIFGqSKSN+zcx7OrX6F+WvdO6ooKGagE
thv8DIMuTMKdMLnnEQL+JI3YqlLfEujb1ikUXBNh7mL9MGFM56KZshS8KFDEuIGP+nTYZrra5wP0
5XRgQyD2IgOMeavOvjsDRHV0pNf/YD5Qvu1FAp/MFCvXW5N5khCvQBzWAT+OKc0QqStpTK6m6GqF
7Qz9ANk6PlLg0FNRERTPZyooRDLZ5q59LaJqnJmcpL3N1qHjdRrq9PK5ra8U0c2juR7Fjf7KgSV5
fYzr/md20r/U8GytI7C6DBn88Z5GDLWtQ1ucNsHP3ToSXc9vI0BV+GaRX9CII7TAGkIBpt5KL8Bg
hzGliOvzRs0itUmw0McbjMGP3AV1gP3+TAI4dKRfualkmFauSWuz7ijs8upYG82tHpFkz4Uf9E2w
enVL01bcuwkQuy/uWtltotn8tI29IAxw/xebkUbH6ZkQjYRTbgqoIDvCWHHjIQ8HtLIDeoB5yTSD
mjYJQq6Ieg7CRcnHZaaDjXrG+Vgw4rHazDCfaE/nx/GW8YaV+I+u/enwxT6zV8tdSyDzZ5dDsy9c
bKc5SFRGeoqHPCoX11BDnsNg5aBBdDuLp8Wi6PXvm92phEXvwaXnaZY/yIUfxAFOBXd47i9bu4os
mU4Hy6Jg382IYbDalmPvZ4v6ZuxfCB4lSsX83dtJ51QkoaJfPu/B/p0qoguqdRovb1eG7b7Kb6Pl
Ocac/qXlfPWG+IYE65nfVn6tQ1/DtTY+idBALu7u4yaAH1Ln5B3HyRsW5TIp8T3IJrIL6HAYEb80
32c6ef3Tyr3+/67dDC9qENr2Kz/uGDZS6kPSs7QPkwRZzE25jVvuxm1AA7AUTEPJ2yYL1RRGUgCB
OZFEVAmM49ENUL5mokXDRZeVHct1ASXkhFrlxbL9wnpX3cJm+ZOMHZwAZGYFu+5ZeR7K6fOqFVs8
/B//iMaDDFHXRZJowjgjyrbEEdN4kxCbnWNNpLAvD2rGf5ICF6VMgDBY+2lTfScQExIFRR3Uyrdp
WpwwqlPnWPfTPFtanWcac7evZYbcVbw1XZ6sfkwxAvClWlDaR4mN7L8nCKqL6eIuhOI1lfGRaXEp
0fwSlr5GNDBaMt7OKZ31Xcd0AS9G1mp2YnILFLV5JDi/eU6lFdfpn8RYaYb46qrPnyZ0kAX9+4TH
/MVdyDy0Egpzd5fzQEYRLKEElsgRmyMxwBwOar06qRDnTMbTnwXv/ZshSOcREw47dSuEDNHz3e3h
leqOR3SQBwEfsiFcnKG9LUAgm0Dyl41FnYsYUUanZ+nLd952YmeV/ovAO3oFYATQxswSob64Zl+5
qcHZO/gDbd9+K7p0cA2ppsQPSQwKsuYp+uOki1wtHsDtTy8Feq+Yg4R0HKekNjmULSqImC5idzJN
W1xN+KGfD2qgyCI3iVefd0A1U4LJrn3SdbttiUqLsJ+XBPvPujBXFGuWMlkelEjOVFmmcEgyOr23
IDEEEJjQM0cnZ6WDCVDjN0ouB05GBq4iMMYFe3e2GzkL/hH53p1eSDBCOyp7JE/qndsGrKRnSYcX
leDODwiXFC8cpdZZWbx1koeZ39vgt54rVS2D72oBwSOWjwUAcML4IyI3wTYkxXC7sKQi3G1pZxjw
OptY8kNCFXp3ObK81d7MEDxCx7EgHyBEXHkou6/himXiGU/rIwPEhyRMQlmjswqTrlQIUGWByj/S
c3IgUgwfQRnJPjQJbT2FBqnLb4Sj15cM982/XNihnKbO4Uh2jc4ZdThElr73qNqB3K12jO9ASLZD
E5N/kfOWPVf5XtZ+27d58WdDNYoD2BJRvjnKUjYENIZl293mVOC5AS46qQ71gztm1TT8BBuoxJr/
icHIHKmyG5yozyo4PW8gy66kBgnxp5LGVgc41mnvbzsss25YYUD5HiaX5difXuLdBzaSnTeJxSdk
4KHRVJfKTM45hg90QiK3aheWdN+u+SeQbrzD3IdzKh2APdMrbdNA6KBL4NB6qxvTtkHa+cxUhqK8
v/dxp2bJJMVhV08Zu3X2kYNodw7BWlkwykMTXJJbBBMIlED5LJOe12+lM70YvJoAmIOrZg9MgQ2L
rn1as6IC44brdJDrsblB6wwmEdlapd/7rEGr8laefFU/1nsufuNM4C7XT/kJ2pmNssqHIo43MN4q
0O5znmhoPpWwIEHVEsIy4MI5my/qulDA1Cp5/wFbo53y/aO/ah77dAeuF+Upo8TJs548zEG7FIx7
m2kb/inbSiOovE2Jsk1fiPB9NhZz20a7+Z57eYYCjxS5QREiJuaGWPjFQuL29J1RvfNFs3M+nGrd
A+M40blI+vtjMkw6RKvuvOMoHcG4fhONFDa/Eg5h87UbJG1WXpK0Q3BE88wCqhqwG4jtNMp+IOeN
MuV4V30N9qVt7MxE+CsX0kNac1FyZZksGy7JqhJh+5YebAFkGuyudfESGq+vDn/z0VABklVXRXsD
vhU68A5X5heNw3mpeoSQDL9sG8QxQneQ67d6riFM4r+CQUnLuaa7dkv5Fz7SWq4QpWf/ZOZmn+U7
sQ0Cdi6PZmDK8PZNakSkOmua73IeZ6KFI6R1aQkCjs/ge3UY9PB5X5d8demuWZ94ZxRJo10azKWW
PAL8Mx3nt+iNDofk8Nx8ibDJxBZTYBLOnFjGDzQNoyqeWmKhnwA8mYODeQUjg7LqQHVm2SGgm7XN
KjkvSHb2n/eei6o4zWfqeG5FcHjAe4SsBnkiraMJazVfjLgX60HOMBLSNbGs7/vPQnK+jvt8u60Z
zXSqaL84OtV7UKVdVtL9BtZk5LSbHGeEzZccI4nw4S2SUc3B6V8e4tdQNqXr2u2A8/wYgpq9ZfKh
JaQModrreiG/R1UeNIf5unOgXI3Nr9GoyEq0qUuMDKnBN6HUrIJCwkMQQIhA0x70497JxpRTfiMA
ZAPGuPiZyD8cu5rlPN+iqApHjmE4a5+ohbpIZ3dObT/01srCN2lox1DYKZQG6KA6KTiu1jhM0WXs
kDfh5vPPHElcPNhvLjN36U1RT9IibMl1dV3Cj0odynZLDGKE3nZ/Q5RXC7FXHhgvpqTAdezlpas7
xlniGoWrDhD4C5lIClAQcQoX2qk8UNxGFaCdIFdIZ4r2iQf3Nwf/xuFxq4yNEZPtcjnyBmy+hsX3
fpnL8UYBj9nTG57PFEiRYAk4gnBx9qEA15AgtfEM19IEJlyEkhAz9BonjEGhlZQO8w8sI7VIGKoh
kRQ8q7/dCVCOIo/h9y+Kw79v3Ajbrm8hYiK1dm+P04+b9LIg6q2rEpO+ql9xdSxUxtemPXzvJdoa
DhGtsoaul1ZswufKK05ZImIxFLV9/nkBbaUjCul/r+T7Wti58uWTvL+ttOaBnTq06Zy1s1/xHyWm
/ZsKCNmvj2TrPZ47wKcNmUEyjb/JMB9vqxdXhGfrhO7kjhJxSaIMJCS2GMr928mX5LS9eUEAU0Zl
EXTontz1UwVrnVvOcaFLMXvE1tg40t9DXDBd61Cb7XDgWoOLo2wpNyZ/9MbDSC1MQrzczP+Oeeis
Bliji1xrVC32jKJfKWg049+ApeJApOxhEfICraEje17I0qHf5znuxRbn7Dm9M7nKciNH1WgSUlOs
SkT5Cobv6O6dF8wzDfjY2zA5C5MylSnFjKTHkiBBC5tPr6b2IWVpsC2oKs+mD0HeBr+Wk3ffBEbX
6TkGOJwXvg1IoDmYFX3/tkW7ARPP47a6U4N4uBob56LJ5NKUsL/+T4FAh8cD34EreqlvU6TG78AR
KdC5uvoNjxeMh0Iv9nsdExBtXTcGhzJpcN3plr4iQZwBqBuKjBeHhjy67yvVtHxJpyAOIR3I9KAb
xC9aCqSJ7HxIS7U+VRHy/Agp7xI3hmz4q3/vd+XIr3eDwAWPgmZKfP4JFn8ZwtzNeDQaC6k+ABaL
phTrgD41EwhyAqA8ieQwMCCKd4ABmXRFpg6aav1chrKcpwMIzWWB4Dom/vSFD+8WOGWJqMk8lQxP
yf6Dyd164HbtPFshU8VfYHMVbsEEEKtN6xIwHWje8e9MsVru5sP76MFG0i9poOa71zfVhMfHgLmH
NsOsrCv7yRw6q/ZeKmlTfsI4yofllj4wKKEk+ZAvBxkYbQ4YZKe3ZNaFfyZrAmXWhEsXc1Crn7JF
x7FyxSpiXtILGOzH/sAYrsvO8p0lyG/oWTLpHG7aHz+GarHOWT/cqvSK0o0C4MiA5CXe37tzJyuD
F+NhF28pIYq7uz8oEpJL4KshDIu+65AJSMc5gfJYieP8PBQjBzMFPfEbKwg7Mkv8SteS1wS9wnOM
VOy09I5zhWEmTkDiZZGMLAxaWUUSkk6AOudNuJaQ6ADBLj0Nv2nMUAghF32ZrYjJx7X8DvpyLExM
NyUdZdFN/sIS+nYsWL4BrmYT+Ykh8Pg+/dVqIO+ebyQpYqkJXDx1W/KvByksfDgLOOG7cbY+z8HT
ZZZxBzAdLt8XjIzV2bHeQUxTyEY9EFUNE61Bd6M2W8IedPVS+/b4ByazgjGiCP5gSWoB/e5YGqgX
QcWVgDne+pTfbWl8YBFrQPUfSwxfQ4gNRLNh9RsxxpbTwgw2pmGzbLLMGVqO3Xu5lZHrypVf1tgc
/PoJBjNEy3AL8mAF8n/cEZIukHjtICvKgGhWNZxLoQ107XqgUCxRL6b4cMC1Rn8Du0LvQmKdF9cm
UteKwOGZkumYo/OuhNX0O5yY266ivC74Jjgl2C/FSN6Z5JjdDK2ly7YwGHQaSou2d69jwR+CuVcG
HFpT+b48DOZdYDqA9pGARss+xskjRWr0U/wF8TZA8N9ekpudGz0qDIPm3BIHCDVi37lhniXORU+P
VPSup8J8DNLbqHG7US+ym+E3DmMVwsI+x/y/d/8yY43mAPeV1hAMddQAE0UMDf5d8Dqn55vTAHQ5
ykKgaOjeLeqq/eeY4uTa03hnsSHcNN+OJxxAVz7qlJhHkO6fUlTHk2riPr2UUlBtsjK+roj5NHOh
HUXSh4hgzBENRtwInfF1hwn2d9SULjQApqX9y61BNHvWT3OuGPkMZOd/BYAQ4dKEU7SogknfgvBB
O3tjMX1v7s/hS/gRbsyvbnXG3VjN+vkF8GadUHC5gUiOM+JLbiHy889ij1aEHgTyYmwaMPHIf/5N
+2tKEY+Wanmq5GJmeMPR9YPsv/DOGAmOI3ALr3NBct4ME7hwfw6W2MIrqWP39sIVQJ6py9EyZ2NM
yGsugBmXoy/Ilq43DMk/jJUKH8I9v2IxloKhS13a5VjNPjLyPuqrSDT5MJDwtz2PunfuV8Npuo6C
EA06CLh8VxSynFqpQQ/qNCIwUfsk39cqIIqNuuLrqoG0zfSE/J6JwJjHMdpH/MyEkkMDtnEYTXvn
Ah+lYFtz3tND/xWG008II+Kj5/9XJZaUdbzGV0UpM2ESlUbR4B35b0G+0ToZIq1lgVY4asCkgXwW
SbdBfF2FO6yGzKMzHhvOp4pBGZZ8zfKP75NUUxzwPkyit+g+2LJSzR1iqVqbk/2Ndc07buc63BoF
sMc+PIAJDV5kFQCDBaocwo2AQslZu6xA6z6u655b8wJiiLCD/d7Iji2zsuiXma8iYjYjJOw+59hB
peyY0Ikn8pmPhEFVLPoN/pr7FIgxyAnqkBGwAE/yZpa0E1yuvrV8ejMpRpfYNaYIDvIKLvrYMdUQ
LNK4x+ZMjYfExF1aZJ8fxwPd3HiUt96gcAbyjoxqcts22qtjbpTKrMy7UJwXR2Z2oj3qX0wD/Wnx
MCZ+Ix67Q+IJC5h+qnJ+e+Rp3YP327PPmGe3EJA5Fzr0nmUJlAUiBTOPCRf9stvpwrZqxZE3Qgaq
jzPNe3sNMAmd5d/tv8q5yvlJhI5LHOLLYPdIfxmQOeD8jPOn6ms7UOKG1cxGe4j35Y7b8ekaGbuA
I0Y6CJzitfy6n+yGBeyIsfv9ovlk8JgQoYl3SuZw/3uMIWTFWPyXP5gCTECL9AzECbOrhEzODjPx
Wu+0xnwNCQrfiIKkKTyCu/KzhsZrwsNPoM8MU8ltW2sPwLp4WYOiYS0/KGebVQ64q4P116Wh8J7p
njIWEY8MtoN8N3UqEt1zAIh8Z9VYD/3m6ilIdklRj0RCpldeCgsWLqpAXbNHeFt+EXRTDHhqoOZP
To8avHLOgULm4haYYgZOK0lNXErwV4E1EOAqD5t4h7bvOhXwCXF5UPtmABP5QW8KadI6yOmIp0SY
cVrYG3iDpVkfa2u/abYVbcW55R7u2TKLyu45WgL8p56hmoEGsGAz8qGnn/LstkOKRiiqh1PuOnxZ
WUN3kEy7BHHXDzNJM3PKrmNNVD5LiDag0eh3QfOIGvKSN0LBRZmnshoqalBH+OQoCk5hz9VtK5an
LoUBGeWL8dus4ndEEIgt0oMQFosXr7Yzz/rlo+xoV911uTPgvPFnjQ+HNJMYC6hdv/SAqrxAuOFD
9N7rJP4/tmBysOJ0la8Lvcdq5GTrZcLtXhd2E6B1+GtrLLbjA2yuU4fz/0QIXIuGe5Fqzd+sPnHw
dvMUXsnBAjfCrYpg/WCNM/SW6aU5NFjpcA0HX5YJDiaq5u9IVuOaUdlv1I4FkQHyJOkwXVz4+zGm
H9QRdVLfZUzgpetSPYp1qQgex9hsK67v6EZsO8KHOOu8RuYD2hJ8uvbKT36pG7/4KIv1T7ecgm92
J9AALTVgfc4JAzbw9tMpH465CKadCtD3QSdEsn2WH2+45YtF3obleslD2K6BL4Nub61XnrjWbUYh
OzGi//50aPoHEe7+oeCGVNxiRzd7mb50u1Nq7QcxJxMmHCBBUu3IVW8KqDjwphsuH6kLXLojIKaQ
Ih5LHbzP2Bl0Ec302zM3/0BBeK/0YR81THM5UXbi6OqPAp5CdOG3BbijJUsk1EvlXAtkxMzOFkz/
T/6R1tANOsKjruycxvLP/kxaBkOVCo0ClHWa4Na/gJrxLwByI3C8cPPK7qL0Owpq0ppgfirtvK/t
Rf9RVL4cCuHzSaReayIct8OppxHu9WyTvZH7xID8+QGkODRYU8AvXRDSddtJOznmmPt5vWnS9VZf
KsL5SJZQ+G8Nxn554lHadWd3A5Gh+9tKB5ZkrSypH0egize3ui/7eT9SXA+vKgAh/90Seggb+PBb
QrSNc4rwQF4Gg2pNSL01qwBJPPgfaQVFfDW740lG9Oxbc6Q03HACh5JmL0MX+J72zKJjI8u/4ZPn
py/7tZzbhhVTybMagcVUw81dl/oOrxG6GS3cHyiGAa9/4hD+GTCp3DhBofqeb0RVgXCpGoe+IXbK
evCHOr6b3HPtKm86jJeFutEH3oNf1sTAh+ppaOrusToL1z2+wrDGYK4/6VL+68CqSqycsAkXGGgP
jqJreWVRL5oqNFfQi8cOy+ZqY4P1Ft/mqwhY+qyPGVEfIwJmOYzB02Lh4tnyP1BnyBExBRz/Owzh
OPEGbQ8MsMut2RvbPT6IYBkmoclvcm67WNvwzSIxh7v8rfFbxNOI+BfEpy69056dG4klTHnb8JZ3
SskIJcCwA4Qk2otQq9skBDR0Mi3oN3V6O/kg39r2MDKd9nketqblI3onuKfy9boChYTIJFmNBLBL
BgPROuVqqyW6Wj5jZupsKpYMgibZ4jNMtQ1V9nIPuwGduuk7Rj4rrTKjv5pNWQedqpZZ6nttMdZP
kngF37xgsvzk/bWkBwcLkoTVtWy/V8Vm+G16HYiW3zS8Q02Vj/oZV1dQWLTSdc0wqNGPh8K2EHs/
A9ccyPXjnnAU57EmtG3Htfdq0PSy5bWCSfVlPhKsCYV6x1EaHYqk/zodoOJTBvLetRUjuC5iC8Gz
hahxMpUFXLkOpeUjnBw0p3j3+TYTM7NIAWFtT0Wdx1M48b/ER8FvIHKU/oP2jl+javpUjoQOY4MT
3qqN4q1QZ1ewZ9X4C9FNPj3/uZMTvQHQ/kmElNnX3+gkc6DbDT3CqSX/4Xk5WhxpI+xPRJAqUD4P
rIh2WqqlX9sd6giSYkLJxdXppbo3HRLgLB7IRDNFl2H6Gn4UYhqfqyvYPyK1SFHVhegoWIhA9Esy
wNC9w2es0LTKBx67dVgHJpfqJWTNQjiIa662Fwa/sXWQVOzblOQVxmplHH+MM2JIqCRaEaou2gH2
xK8XvmteI/SvnN5zg4E2xb34FCsNWuJDFVHd0SOck8vdxUBwZ/KGSOwMfXPXKDOfIXX0mek6yxWk
JjKn8/KCr0R3+EU2O8QM3A/oievv6TzKZfuukecqJ3F1QOIodBqMYsojN2DZBFNd+HoTwhEj02Ni
Cop/lu40EtlZG7abfUkRnYzxBGpC8dNsQfP1CuFnsniYJRSfyEbGED9IF7QjPnCveJn/x2BRQO51
CWEtg8kshKtfSWfLyoKN+ZxzXWazvxHmvdEUECzbuV7Wn1ZsKj2qPkeSIeipKX0MkiQMVuCJmiFS
OINwZZUX1N3FVsCIX0YfMzlk5paiHzuNX+stVXIRLTd14Ss9YcOaTZcuhdHleKz7WNlbba9E5UtP
CAlnHjqZ+PcvgG7uJkG8hbEIXOQefmpufF7+z7c8A9mD+axA6mwEv8BVEyI37uAygvRkYKF8aKAF
BR9jZqAB0bRuP6WD5Fi0/6MtR6/2Rv8flkiQwYf0bEBxMWuatXZJRBvVLdJw4Pid93VEVMPHfgyf
Iv5bi6fuKyzP2cMruVPlJXITtczg2VcJqiUQ3DIWM1GgQLr5pwDqLlfQY6wPEPtytg7Q8eXEWfpc
EvqSJGlwu+9Oiw1qSBpz2xKxUoORdwTiGbsB0HeF1rDzwE74toRs+WdDc1RwC8RNewipVcSHdbhL
UMYRM54QC4AARPDQKYg65vRpyPbbccvnZBdv87ZYdv/tvKH+DO3ckDr0XPe9Q4X2+g9NUZA65vZH
qVHdlD9ZzCxrqFbiLO3bhIY+Mzuj9MpU/uYwvLQmsfVNz9BiIT/J3EBbR6FpZ/eJerUEUIMQGg2s
/zvi4/gTIgVkcPLIGYsKcf28zw3IQCBaVP468ByTDhK1EZhqu2MVH5C+JXKQNhuwgAZt+nfQ7lVI
qoQv4VYkhPoZOFf6iJJiq5s9e0SIo8IvfFvJdM9pdRAL/imO3042VPa2f2dGKg3uQDwHjr0ZztHa
hxLoSdPBBQmB94BGdBdjBVxQ0Nq/UGsP7TU62YBuPFaQ+IzdvHb6MzGrwBiXNPjVAjgN2RGoxJKS
tYfjM3LCeDSyNRZyauLFVLF9qgiCvExjRUo/3gPE9La3KyvlEUkEBzvA2KHePtIlOypdtLPtCmBb
qHmfnSA7pXJJOJxKypWFSxB8ui5oQv774wgo1moHYtbZt3o57dUZtXXkg8gXKdWZY5d75OWs60BC
5+K6vHD59qsdkgeiShYmvFe4MXT0L221hC/y7bjahQffgjuMmMA1z+ielmMFJZSneyGONlSqUQnD
oDWF3B8QyebfLNCq6Eq9GwQDgBtCeeyLBHhXmJ/0y0LaRyFnn4jnNtwa1lA1m9HwfupK22JqlWem
YRzSN1M3R/gneDNwxt1dkItD7skV/CVoE+LjnBCX+Z/V0Odhbyx9mMWlgk6RUgCSuZFkbT1qzJrw
r1jVX3i5U04itrV1sgiHNt6Of+Ge7XGqGtLifQbYKOX4UGcPYORczdziMDY0JVynnhBbZieq3FYq
OMBOsGkIwiP3Orj7EyU3u6KcLe0Dna05DHreHMxqOaJGdC3XXB42sVxCRncsDXAZaz+GAc1yS7n6
M8aOU/vMqiVIG0OpJATE0FsYrrx1CWSEk1IRx6GVQczeRJjDSGvkBDDepJdNz74JtWLhfZOz+Rld
8ROWcGTnnbBgYNO+DGuilAKi51CS6OptrvQ3MLVgXUP6/RzLMkGrdwKqLDuyx75wzMaTOs0iTSrv
JbdnJOy7YoZuxmjsCYHkiwE3kzUi37cM7L0BleeSI2muMWQvnyleDLufmDftnd2epYxmLMFYmPvE
C9YMw14FsQg5BRuMPEZnriDlGA1FnAZYh63pkqGYemJmng2SUSaAbI7cVRwvAZpYUROnPW4dWMGi
M9hVAphiEDt1/BluSdr1UAu9+O5ZXfaBytFVvQN1WKknA3zEh6V6iDElBvOEK5N8sXuqxFqPYG+8
Vu1I9uigTBkjZ168z7YPzNFciPksmrjtAiPDCr3G+Y0QyOxNaarESwz+6188h6PCWgLFn5B3Nn5p
3na0C+IQs5MQpfCU/nmflz5+FdrVrKW6TTTr5PZ4h6+3nlbrdVW7vQlWMn4XW0AhTx+rK384/dVs
VycZspzr3CPQutYLCsK3Ie00sn98AaIqK0WU2PN7To4cJtqkiyVQTZWLx4ATwWYvQT3iCsEj9gqY
oyZxnE2lAJL9uH00tIdOYLhkpJL7rHAh8I1ARqrlgP+DbA6a7CxBxjLKsibtfQeaHFuhcivPRMj4
ndWZq23oUCKS+2SzIQUUErIU/qAz64dg/afuZ5e2Nx0HvkkKaPPJ+iE/MKkWR9dgMZHjPTXAdOCF
JDW6AdawlKORI5TZPWrQPm4dPexR3qzW3axbSP5jCLaNl+fhzfR0tJW09u9JH4HZsNqilGxy+BvD
rbImg5RT2jzowFAiYUVaJOdHCEiWIRqNhvpayJuBFcldhUr4OM+CvefMPUHihF+r1dKxh6Ptxu7N
H7D61ThFSeyIqAWtGtkm4G0aeKeyOw0piUv3F75t9wAg1eLI4hqutQ3nnbsOkpGt5tGwCn10ANDE
n8O7WITgQow+90MkHyJYV+EA0YZvptxQXho7g3YXgTXeyF512ML/nRUZQyBA2+Ww+wKbCbgILLQ5
z7HJQ3T/Tf6Ber/WfMJHsSq5fs+wR07w4r1/gSfbiYcAUTVqH38mTFxec7a26Ghm+T07zVRpH24m
IS+JWRPuXvcMOSQHCxh74Q1ElAn6INvlOJ9fku/x4oL/Yk6IqtKlt2Rpz6duDJWg+wsIbpv+tqmX
/QmWMKmQobXpJHpNjhiz4Ufwejoi0Pgwxd+hJtUEUVErJAnMPk36aon9Qdb1bmFYsGUEYeVfcENn
Tk5Ts6oiryMgN0rWnoIAGvswXVJkXxwz/fSCPtacndC7PV8W8rhAFrONm9M9kG1aVNTHyytEfFWk
y2AHcD8ySwQnHUtu7EVfZfSOGuGCQ5yT1of/uyg96P3qkzS2qSTpCNDrI8tXtTw+OmyiWm/ey822
BQoODBqsRFYo7PAdxp79ZmkVCY6sW0sF0EhLU2DrCRGAyxlX2fNPmcvYgri9V4/XG/nNN9GBtE/w
SgOo+FMi6ywrgWedUH27BYn21uExmzPajlvd+MBTade7f2hhxLURMMDqqiuCNgHwHMlMIN2D5yDA
rrK3reKrE4CCuChJ+f4m7GwtTWYCvyyWhZ4QeTtLW5ROjkxnoLe0nbwz8z/DIq6gtVfVAFCJjhfd
1Kw+2+y1hinq527GPMb+Ft/EzyU7nDXRRJD6imdnK1rU8mnBWt99Uaa7dh7Y7NENLTEqPyeuQZUn
HtcisoycnhbvfHm65PluRB325rtZMZL48bh6o1ZsBzkHm2BM2YcFihqgvzQamuIILtsiZbDrttlD
filNzZ/5jd+aoBjMSLe1ZgE3f8cPIIpgNSnx1EoqDlKsHj0QqCn7JKJfnQ1+58OIP1lumbXkLzji
gzYbkc0rGxyscUlgUidQGajnxZrMGHUVZNeUi53Iwp1OonsAwh92dkoaCaqhlqc9aOFEoR4jBhU5
A4pSpBDy+RRIuI9qN2K5qGo+A6rbBxAlfND+mgN0KsLvPOIKrF4gDgBailU+up2adG5ibGCQOzU1
SYkKbhAMQBj4dP4ZteoFXh1Sr9uemrXL2HrlpB67lkrU6PgO2nJEMQuy9OJrmQGG6fIuffaTpq2V
MKC/tvYymP70H6xqKd8692iXlaRn/e/tfydUEuF3/HUPAu4CG0p+Yhp0yJXKF1qqnMWBwWuSW3Fo
MaBDBcYFHDlI/D0rQGCq/5IiSD08r7dolmMqO4O1/WHrrmyKsBeUo2kdxZCCR5Eq0wgjotK5ZHF0
NI722gyLUAg36mj4qeNI7nDznd+jkn7LJEnLC/xqgN6M97ro9z6x8akkVNeNsMK652d/rwJ0o0EU
Bq2wS/bnLWPAvpqM5af664U9Tc31CwdY9/ziM/GlOZnrgN4D1mQGRG+2y7i8b9bn2LYgz3r88ijE
8P1fq2nqd/eFxzibS1wiD8HEXqC/SB8oYMrIhE9N+stbO4FqcpeDUabbLCAaz69bh2G2ocssxHbA
airHUKRKpR3uofuh0KMd3GlIiPIuzfSCxkLMNumAPa6AdiXwVB7OkjwDeGvLz5ytoM1bEdsoKBdC
WgHXX0PGhMpMPMuoI4mN8iLniiprNrBEwWFrJGth0NB6GC6rAx5nQCbNjAusdqGpfFC0f+gs+REX
zLOT4otIvgEirqxd9P+BCU4zclb7yGXn7WzSgMOOfqexuAWj2wrCkyKWFq39a4CrsKPriS4jHJz1
/jgeYz/7d3YBvwRWpbzsDAxXh6ESp5C8W24QvaE+Z67jZgxBVzzXgKFDtZ69o2B6K++PBNAWp4Zw
vDjPyUiwukPlDI737KWXJFcILTssyE8faP5F8T+72ujJrfS7o/N84IgNucfoRQ22Dw78XBnsIur/
fzfERzyul+RmECcvSiPy5gwR0IjpGaYPW8K+740zGX4yBhOckstIQjdJle/JYvdu6h5h7x4ki1ZU
DxiDzTKjKBOAd9ztVWqLAeWis3S2GMeC7mGcjWTc6qyI9HpMHK3Aak445tN/P/dU9Q1g+dJ7chfA
pGeazX2qn/APye2+g2CTEBjT1hvloaBtCT46TResTKglpPFkE4VMAfO1CGNDyEBN7CHUQlSHIqcn
hoFnUPicIbJfzXYNdH794LRQpzgLIwEFEC79XaiKlp3HSDRYTciEkxxcXUkTpyMKPMpB8RD5CA8t
sRGlkIhuyJwrlSL4m9GVazCmhHRWgwz079OwungtpxCZz8YQgZlizkMFmFQ678ntAsbQKBp22qqg
Q0CE8wpeaXjjV2uvmUZJhP/AcivgOXhsf8WFJwLZv36I4s5v0cy3GP7azxLSkL/XM4kddOfsj2Ss
357tT4ansopjh8cs4Yz0rvMWekMlAx/4dp3hsKo50feIPtRjuEtru+jUKOboxLKz6TJOrcRVmGHx
kSeO0K3TXJ9IUWlJ0uTNTU2JsIy5EfITy2qJE8w5f/IZEhC0mkdhXDYRzJAEnc2E5mjScEmw6DjL
0eaGEzJk44H1OU3wLbrLcENqbE98z5bn1x+QPnRndwqAgw44Jdk/bm28XltD9rYWh+0THQYYXOzm
m3sQxL3ntclRq5H9L7MP7tQDr3pCGKIJobJw7NquKlDqhOoh94hSFvJxJJGFuLoZp0R9mcy1jq5N
3SfarFZjITz+9uWYMGf2nKBzjK6pBkc7odocBZZf/TyWB+7Nr6vsHjqxC4lIEU0Y+PC2sM04OK82
fjj9rWI1hHdGlXBTu/wFMyhzcDQ+DPLrc5bnLlRBzradVTLJx+IKcmlAq1NSorNhlSTzpxpousbf
+QLoRQ1IdWDJYt2MGMSXjZIBnrLtL48C3YzKUTKapGSMBV2M+JsBQJ4S7LJJ261MAYjkKLDtUNdk
psjG6Y2PmW3yfjK8xXm+5D9cz0qdEaVelARuZWzSB8WVzTdTBuL0bZNnQVP0GRBluV73uUOkySLE
zy5u05pq/eGqY/VbJD4uTuL5jiideYlF6vzuMq3pYmY2tAzo1zoPaGyCxulMYc0ROuPd0dDGlS7B
rTOs4jgzAa/2uzJABb1PkPTb+ttaLCOe3hWGpEoyCu+dA37zyh+f6dp5xZz8mDHTCeHYLwgDiaVB
ZrK6Lp575cxaCbGA1x2X4YW6tvYqWj+9wqMssD41MNnW7iOKOGtmunK+SROAFFzhYHVl0dB/GsKQ
h9HJPShlKS+KhswLGNDUPdVNuiPXQYHvcIhcuKbbDe9Nmp4n2hdFfG1g4F2OUzC3mIHUHHqHqkKz
Q2C23OetVih4Nep6jrVJalqUh6Sm6LbrMOKXhFm9Sc+3WVxHPxcmvVyfsgkslqCnk5r+3wjdDaGQ
RApYD6ynQA5SjRvbGIEgWGG6PCd/CQkgV0y8S/euwxVSmWqZj/vxmCSV4yQwSNXZ6qJyAHghHsHc
dW9DwGFOLzOBI/VD197UTGesqdiTKBG3Fwg1IZpt5CpPEshHImNMqNR9sowlEbrtHqd4ZLU/eWrF
nuzzwMov3dA/zhnDEjTvG42TSc0k/EBoHU+GW0OABzqFr+bBEaM0JvhmWEVH6opBwqE/6AVPA230
hMxUwTPf2+8GxsYc7kOYNNYeYHElR0Pb62fWidff1jsG+ZJYXhTdoG9yu8I6YkEC3cD0zXv00F3U
kJsyOywApFzfHD0T5rRRLgTjNt+PW9/UZkJ/ORnCcgJB1ukUGYPBoUFMw9fFwChMnGB93hWiv292
midbSt2phxUL9GEP481i9la22kMnHrflVaUn4OUA7fSp9Gs43QzFQqFKF5vyGU8glESiKLQhfNw6
Lvbx8hbrvUONzQ8Kv5MrplxRwnYynNfEHPd7InB1JhEeRTTe0jPfLshoyVuTjC/ViqwisqLwu6PG
5UVIrpg/dB5sRXOgRqSgt/9uEmdvwS53zTdCzHCmKVkETxh4Wwoob/nRSmjiXDzVF35jb6yZNIcc
EpCqiikDaJNaAe4R1b145nB1JvMV0Y1g4hnqoopHuI6HSFni0AzQMEkUg+aUhpykVJRMW9y2/EG6
W34vMhjyr2LFUeE5lwh+/h0cIbkFomnfBDMVUAgaXuYpLGOMD/eZDWnpPKDhggFWCYUTYpY2eEFr
ATyMgqICIlggz6d5/X/Geab3WQUX6vBLqmBoPOGBrdoOLs8zGnumTEmpG+hE7ISBvAd9lN7m/CDb
jhpMds8ir+yi7u9YUufjGlRXG6UtujjV0gM6KaxQJI2lEbx6NAXI1uGzTp2spX7TqiDiJNh/+PQC
LW+sro2aE+ZlvuQevBcLdWmDD4RldCcldr4qj30ex8uZwhc9hlhvXyVVnQWLrTA563egoNaRDf3z
U2Xruwl+nWniTs00yFhvGYFTOs7/CyiiA0ajRHGES0HUrL2/OBFTjDvuFNq+eknGwdU8K87T5a3Z
jIyy5OfaTjuXzEkN5q9bHW31dazp8sULRRnhxApb2ndL3AQ+B+5iSHFIQvzEffuXd1up9fo9psf+
s6boOLqcV8uqVtoDBBFB1PPK9U4VGu7sqUNzh7MqphNV6xs2ooM+csjIxXscYa5U7Hy0rBE/QDXs
lVLQrvhTsJti1dnx9rdpZF8YDcNSd1iLt+rP2ArC4QxYuDEjBBBQH0BLHtM4AmqYmeEg2rMdGuqR
UiW1tsYWiKQH8LBpcaM4qCuBL7MojWoPF007GTOo+WBI0kGob1gZbrnaE+iXuab5sz82qM+FJYsT
ANFJjsEHHsXMmH/BfXv/+PdsurocpnApdspv8WAeW5tJ8mal+E9KKSwCWdnMz02KN2i3s93DP2yh
G2QyT8Jlx6C5XjRR+FVV354EIb2IA/V+lq8lD9iFqf17ldEoPTUMRg28fnWYkKG2qu1RVlPg9PWi
xGSPV/mPHFHYekcedrzIDv2beR5eglkT4b5D/NOMuSVc5XP3h2Nu7HvllTcyjbt6fYHPOXh8r6mq
OIiYu9l29endMWntcOgRIkIeroLHkSE2Se1/THGWfJZlc9BbE49QnD1xHbNJJSLSmBnll08ne5Lo
mMY29kaw/U9fnw3tmhgepEhrjwiVhCPgI6OlKTEstkbrZAd2Z1OJCmR+TpJpQyVktDE4v4Ttb5Qm
Hcs/5d6Kqx7wYeO3hNdLQ8E4wBguGWKHMgmZKM07DnZ5fiHiSExBGYRLJjehlqeV9kU6mSrg2NNq
5PypITIDI06yM73LVFwyPQXzc2uPUVWSGKyKpMhY8iPGxPlBSrZaAizco0gLwKSSHRnOa7chjKoy
vZi388iEZktRMYrX/89lJdCdlgNuKU28SiaJuZJ1ax+zZ3aYn9zro8HK9zOmcB/ty4u6sH2Ops9q
ZiAA9+IthGlADUEgs8waYnP1CDTYDhNc5uw7rMe3JiqDiR5QSOni5RFLvGP3VvlGnTzaiUmBa10u
jOa39fGG1GY5f2BWGDOqPwmlzn4CvmY6nFaiow8BrJBVp3JxUFoCNEg6BCxavMzlAWBwxxnO2+Os
EfPdwRewriQ79+jYDjxt7yZHClh+qEVeuY3hg+aiHScEDt/QTdj/7IevZHuZ8Uphdfb4N19vl4wo
GM/FERNtwisdvSV3HjWzoLtd5MkbTdJTIEl4yCdb/8h3PX7nzIC3rOE/cJR1VIXmYOUGYD2Q07qW
1Vt3FyYblSQAaEEJwC0PaR5ysQiRRBQMeQKskkXLRN2GKt8Y7wh0Dkn1CfPBavPXHJuB25DTCwUO
2zsxemLai45XQv7GMTooyuk+JukUWJzpEAkfsRYEoJie3LLHkdwAT2oow1K3rXV2zeTIrHN9zOEc
PLh3JmWuDAIU5gyFWRWm0mlfIKu0a9/RYhrqkLnb/utGvnI5YX1MhTlQwrZdkkCrQ9Tm6sxrMGYu
OjTnDUwUY0btx9oz2/nIyqEx7Fqw1s2XZCTJphd9/+YR26ZRtM6q+ajIvyGZsekA3QbUlCadPzDr
l6tKZplibUJPSKLKWmQKsReiHTuVIhWAwniSfqACfoLUNkOoaP7Wv6GCAwG4GAPhBZtExnYMkgJZ
qEqszlM5+JXbqJ59LHebloaZj5T9XPfjzQYN0vnUV8RqsYYFWYS8C7LyTklfTAVh38EK1PsEo9EP
TBhhneP6sSRt718ZtjqhAR1K5CY8W3x6ITW1TY+AuU5SE3wK7mvaGKzj+W8kfAYs4Op6Oapp8O2m
Zv3ny09ahfl6mmheeKuLxILNB2v4/xHo/s8+uqu5JUowG+10izbzdwZj8PMuz4uEEHYLubsYL7Z2
qRssErB/YSRZGI1NUS1/43UJH8qtrgDMZurhwW4aCJ/1VLO9v+i+TENPCqUsbCVB6091TgxtsqvU
qYVytChheKmCWsHiSWbdzc1kidJsXWQVl4t9aFxdhmRlMJmCwGR4lSsme2AyOtWohrGFgGAjZckR
Qx60FKpbGQ8OPSUwq2gGXpITAPxQ9NWgulvlBKY4rhbltj5yHjAgo1O0m7Bwx/hC+QYaQguW9oFg
8lOjGcHp/KRmxbalSmdsrDT9H1asgXeJ7IbD3kwaXj8rbND1SkJ7ZjH4YWxmXliI/M/RH76Xwrcn
NbNr9Ot1+QSIGEL4jzyoq98PQDPg5bxKWEeXEt0EyyOjgWv8WBvmffTa5DjIV2bxl4voj1HhS5Md
mbwStOHtKixCGA9bAfqZlUbFBKYgnUprc42aFOUseSyMukJRcFo206Sm8B4bHoq1uz6+jgt10M6m
y1csop0GTCPavzPR325Ittu4qD+BKDRMhdmoKq9ADhN7IYFRioEfe5G+dwCe874yUKPbz9m9owlR
Zy/KMt0F46I5uSTWYjGFAi5WZ8PpliTJ7/nUuz72vz0N/JoFkkq3fe9Ku8Mv8OvObWflY9zayJFj
NSzeX5ixZhCts/C/RundzjqT91tCPntAyVHKXQGDV5OG4cflGhmwrCT9feAegIYz36+tNnODuvW4
LejHKxnIytPYmRuHAXbImD86Lbh/H9UKJ92fxFd5yaMoSA1gOCJON5NEHBzIqGHd1j1gltaWKKMf
MaNL5t3U/H+8niKDtAeinIHD9XQ2Sc/Lre7A+2nAk8aJf4zLNyOUykR8nxjidcpZq0VIDdD8jwUB
LYyGEc+TWCA5J630JrzG1mD6LDxVUzuhspdd2mxGDYhA61jhhAVk+tvVTqUG+MPuiYN4i34l29ye
1xngiuHW1QUA9b2tKIB3tBvwQED2A4rgfybjf6Dy8rKA74UcMSUzDlFBJ9gD18+E4PaN5S5ph4V2
mwdpnBI3iWKfpCZqF901bXbOjT5N4RLM+pUcZ+cTgccynwmmztl136MDBtijYqscQAP1CF8DmEZQ
xd3zFJT+e8quut199NLTQsL07ks8bN9MpBwcy6Vc07zNxnzr6ypIvFkfOYFptjIE13AlYH/BhNlD
UHiSBCsa7/L0RgnLmtu1Hd8wkSpfaYLyX/2QhbnHYYLcQQrBHttUu8yI5PE+p8E/6D/4/uSOwqJ3
ylRLfsXfj3dn/O9rzG0YNmJ2ScOkWfzkoc1CJ2WDhju/xj8gocmJ8SaRHcpdcrkPmqkKmjkzWn0e
GCv7gJzfy4ecrDPIu6gY5Ku83ErVuG+5lmS6JWLKeGtWUHn5KxRi0LWJqlb0eIyxSCmoeL61Qn5N
/LlUzTVQhjPgwoIN7I0yJbDAac6q/dkddxGDzlLqtTzHWcf5egM4S8Hqwj/KA4V5htdtKHGfLj2w
6wITO3c0J6KYWK1WHBnB4GvVSSaSZsBnKu0YeMMKKgQp1gzLiCzQcLSTy3YUH1p4IGepL1wvY0Ug
8WoH9WVDxbK2JaGgERQgTqC071nw5Bv9plP6qIFzclUXOCH1QDL6dNN7bDUZjMG4SX6EC5A7wovw
5osrKKa7ZkxfB2yVClBr+FpyEwLM+SwQC6Dk9VfyBpcvU0AqwriZv3tSdOKwBqgI4gc3HJin0eQT
vTMqINYdNcybHs4wUnQQF0raVBchNuC3kCU+/vkMhfAsDX7YyQ8BoKGb0ZYlqUQrR1Dk2zM+T9M5
sqS9iCMkJ1PEB3SGEKjbTPKFSg3mcY53mOSMXwAqTipAUOl20474gFgmfUc4mnB3A1DZ74sE5xPl
WMn5gH2WwMtEU0+wcPkl/zoTiouF2gIHFuTrdmQu+eZXNGAE9732gTrWChywX19EyxdcCrEEhjfU
19kznNpfBPpa6ElNIFeX7c/ZGb58T6JKKMdubD8nLwEt4JOTubf4sJXSs+QwkgvDum98YVHC5EOu
ckC3HrFb12zbs0HL/C2SXZ1B+qgnffZjYqH5RFTQmhUvPNdFGuK239Bd3nXgGycJHEBrCXGU/QWC
mKIzBlOY6ov9BFuOuYJS/fCUbp2B303SuMYFdn3L7LdUv5fGgRD6qC/7AH+GtModegTu3OC8+26p
1yKzwNXyYqT6Z3OwqPzClClqMgOyftSrwx6dCpsnv9MKKKd50/ljGS42gjI6pj/+XVMXe55RM7ZY
zZy0biX0Ej5OSYjUMEYeJg8PoiYs4dnDc1EqqTYCLxYjeDVkAg0fcYKu9Fp2P3a857yqs0zotwUa
KWLh/KMg4aqNdNP2SIdNVDOT3tAYzQJO4FQvqkG1hQ+rsYPbUip9GHYijkeeShhr4mgZggZz+Om1
XesZA81nAl0TrokoVHpGmDDv4KlHDV48genMhP49CTkrthPSpTyeuiASrPEVBT4aT9UdRmzNGxS4
lmQ1SBPxlmoTcH9QQISNw+cN5EvaG5clKbfpmebChggrjhWifIHMXnPLDu7poDvW3sivZ8S6ONIn
3usUeR74u0yo67o2F3iJyA5b4FvW4CsYY88anAu4KGD1lL8K6qEZbLQ0/v6RJK63ezoJLkAd6Web
fIHx54VWWIKgt6JUYOHGbvYqnQvQONyRd1Y7L7O25YF37PuuatutaKX/wsdlo1yvJnX7rcvVWlKu
4wOAeiT4bKErHJnjsSgG0Z5+2QWipdPQxABykOcb8A5JOCk4GhiUNQpsm+fQIZoWllytaNp2yxJ/
eiOW5GP2DO8NFbreEpDfin9+xptKD6bCjhP6hh0RvsoJNtgtE53YCvaLcL4E4NkEX2DegL2KUtJc
7TfRpRQZyk1Mvz97JJbIbGZEuq4nVFaDlEU7iappiKBDa5BG7k7CbBwDP8rFXL6wCBDwUHbt2MOo
JIMIpvy2fQNrX4Sgl2AUl9aVr93NGIGyEdXmXuRCJSASZJH6XXGeu4lI5vcpxVZhuhYrGXTVE2Ty
LujjC3y/vJFzwcrEGq62UKmQs9jaoKdQJ4z6QVp19XZMNpuXRbpGByVhz8esJz6oKy0LvriOqb/v
xP90nv1DCsYAwHXtcOCD4+gqcJiLVzaS1Soh4951NPYH0536NKmLB8J7N1qvLJvLndhr9Xn3JwCV
VNYHMGDE5B0kfAiS88UCiMxzt2MdSDLwXGX4/AP4s3zfc774Hcs8pjzT2aqNVcGZMT9fueQVj86Z
2JstaPmL89xOigRgugEanZs2UADMYNweGf1kzoaD3bv+bOjb9d5Bk031sii+XJZ1NrZaM7ey3gJg
H+7DvbsgLfFrcIU4JzhOElVeDEkmIXBziETebe5Q3hH7UpyeaI+il13ibFDoB1HYhWjNvyrK60/5
RECAs1SZI8F8eDuX/kWbzVIHbgY49b0lPDbG7V2ooSNHa2JOorlPLdaShbSSkZ1JjPXT+D/4PcH1
KuNmkKLecTLtOKsMnEmPtJ7s/gkfXyc/kV4IpeHzf17vPSplWUFueld3802DJkGyKYOwHLhK9PsV
T7/8XSlyi9IBCEOU2iUEOC5FgOHFr3QmEY8KCCm0IYoyNDwe0TMldHiFhHibqD2EhcgrMRgNvwPq
Oa9sC8bqZy7r6qQCxzifBCIYCZj7QBaAYuevnKg8ehl+G+3TQmswgPi37kH0sfWvYuL0c6tQhLpF
nWalZ0TlMl7yN1WhvCoGbwn0aElXVpUcea7JwKrhvRwtjhasD3wBdqa9YRVxU8d4uqHkP0LY6HoG
B6ET1L8nbHswm5FRArBx0NkHYKXi6ilAelAWpn1J6bPNKGZlepDjWXsAb8QB8tPf4w8k4RDS/UwW
F1Kr6fw1jgvAGDW64gN/nwNAjD87PQNFvJU957dyTYkLYOWB2uEYYvQHWoskjVslwSWrsu+rul8U
p0LvCVSmVri98rm0SMXHutk6WJsdijYNQZh6KfxFm6oUJbXNAvM++6XDdYC0M3A+o+X1Bl3jQmzV
RzT6xYxhiiD1BuM29DccncFBF77zhBzyCRZhTr3ArZMxGb8Rn6voJ/WAtBrEUdm1UTgO1BwzbKFh
fU8V5gJI6QuEDYcM4JNUSj9hN0mF7q3OcKxn88Er6SYAAU4zO39MKe8ay50re6i9M/d0gEFDCC6D
vZBjmqiJAUFKb7c8k18oXwxHt4RFU0hWx5LDSj7qWgvGYU1dQ5nKhrdsH0cTk39sFXznEMVDWtl6
qJO63mJoaiKLCzH4LdGhD7t0s7hG5zDaCyTrWnl5GUITHohIBSJ1ZVK2z+O+UBj6/GvLBM/wWpsc
cGdaIvtGZ0hV20zFcnqI9N9W04Ms6rFxkdUOM3YHiVG37p8hU2O3mJfumFeHtuUD8xw5jgZ6VBLJ
5tWlqu3McrTLQeTdrdxFn54RJHybr+DHq1rigqXDNSmSitREYP/JD9as8ZW7lzZaL+44b24EufcL
X+z6v8kfFvyfvC2xFDlAhQq63saeU9nWxwKkp02zSSP50bclZqYgN6BSQ1YgF+5zCoG88ZHOeUy5
Q+qGFxpIfKE+BtIIF8rKHj46/IyiQRSQg4zs8koZ3oVCyQGx6yAgrBMMBDD2maiAcrCPolbUnSB5
qUHezwVobjx1CaQrYoc+bh/BWZfXtj3ps0fyjUYU+qZqMlbE5OSD6ssZwx2LkZr8/IClPMzoYql6
8+BvmQsmu6Nkk2vMQjvCL8T6HhKtZIDJGIE5NVn2ecOlNry8xzypBlAAEYGKvN2PnTVCD2BbEkN0
VjM3vAk+3aUHSPjoMJmBJuEPHjQC+JwoLCgJCJ+hXbk+6mmM2lWXBxIt3aywnX7C2/h7gxM1NkbB
BZOZ7jFrMIptOAQDd2qFazQ3NjDoCNBpWLgQ2g2xTdqkdXyQLI4U1w7346tm4MutF8C3VHLFKFdh
haYnBFAAFJhyYJ60U1vvdOVY2VF+aQ7eQKRzyb85EbrbSzCZ1xyDojbJhxXOFHtEC7vyY+Qi0jTm
Z7Zhkq6sFxzZm8mu0Em6SwUpT0YZdOTNtr47ATGIyA9LG7NYZ/6m0YW9Mpp/cWyyjllupBwwl/gU
aFp7drNiQNuXQeGoH7kb0J1m6UiOP/MfROwETseLO0CLpnJxyJ1zQ5hP/BvgnCaq92xlXNm3+Zwn
qj3NGoGgy+7pPPrSz5WANTFO1ykbP1w+6nFOm0mjufHJOgie1B9f4HVJvMmVt/da8XS9WDJlPVE7
ztWiMYWFSu0ypDbhNm2O7q9xxXUJyYOgB9LH2DchYfqXMBdee+f5cL7mw7BCLF10PGCzLBi1tyTq
/U2AlwCnXe3GE+rU+Sr0HJA8adZ+IQsMvJKaQP1ggZyowhbuwE05M28Q1mYab9GSz/zuzBhxYc41
CDrpCn2qvat0giWXSJ6ggSEO1xoSQPOJnumEhY5Hiz80fjNHQV4n3n3GA4ZGhPxdGsI8Wylzmx2B
s1Nfvwte2ho03nOn7mBGMZIJDo04EVLaFUCw2AaDtbLTqRt2lteUWEnnMHbCmtZPzfHjgp7mU72c
jD0yd/EBdLS9Ryj+odNX/DxgmUvo9rOuDA7zi4Bwi0sna5s4hYKI7MVnu59sgUJWizF1sQVsGR7q
1Xxm34EEdW7zDuuvInqQS10WG9gpIyebMIALoyEINXV9CZ0QALE/JQH7Wd32T4gzy4ynmEvn91wR
r6M0cSkH1vn9vH6RHShr0jRGbeEmJqSkfOx+mof8McSirQX9Lc2TCxiEuPoKtBhkYrDeV38MJ6uF
UItPl7m5+azHiG6dvIzRHUoS/NRVmZ6E47a+r/2Tpn8hhmyRIc/r4XGE4EJmWz4cIE363atk0n6z
3pSnIJH7KKW6ZZ6+owfg7vmYaOvFtavP3VosyBm36u6BRCcmUZL2PzOQzNbAulmfWhvyusQk1cJQ
hv6TiVH0CuLMhOTM/6bbfI+jVPM9YEZ/xILbHnS4etidj8vwNX3aM8J/RGWo0S5kzmbIbUJ2ZW3L
6TAm3gwMviqHR2YOdE5jQtoCu3cuj1khXxbUZKuu7RqG3WJNXUhEFy7BrXXhKrCYo+qzJh4CH/0H
TryTIMVYNMwaDDx6PcIsnBciNAlU/ZQTH6Wv8MREcKVndLL4f90/q/vK62h+Ocm7ahp1DDGCKHN4
eK0MZvQv6Dmnq8M4tGX1H7aOOYskOTbV6GMt4kMUgSKU9Vt/AUQbVj06mJsJUqxJB6Wx0UqTHVUV
VL/y62z+/1EL15dz58ZpGhzcwPiCe7W+odGbw+c8HtlNS2Tm6tjctDrl394Xmi30TTV0WtoDAJFH
hC/r135p8SwlbGHjzKrA+HBvIbeu7laZPNVVN9cGE0xKsDIfhMogbf3kxgxITsV48VRBkfYnGjGR
W1mb7HR51CsVMRj1jC5qtSgSZNwgu5UOc6xCCuyTnEAzFEnAAlJ8rXKB2md1B6zA/PfuovmvOnaj
Dqu+pPK3qNZIU+l2y03VXgWbofBHT87PcczhwXfsDrJhTKGnXAI5GF1A+u8WeX6OPJVFXKc6ywtk
M/A/PpjSyH5bek2OFHx7Pk0XejS+eIdgMyXah0BFJ7zdlvRWachtQOhOPEE5LxE3vvEVIM3sIP5j
UhKTsWLb89trFsrogwq9r3M1wOmwb1SQwxTFJIJ/KQSuM8RuouSLMsPDoR7nRDdj2rpfLLWEbW79
O758ZSHtqoJfGLbKZfWbS1lhgIyw6kQjJEtV0OXuOeUSj/uPcnv4X9lcn4ZHG+JD5Ml79ByNHpq1
N4IVNhYLv/0PMJ412VN56Ii4B7pA4Ihh5uFkj1o7jiJa/UWMHIOE/nf0EVD5VL9EYgunOeaYv7kP
CUU/D6eG96GhphFBrLFmcDeG8J8BSHpE+EhtKmQI+uhzlsvtermeet2NDsX+eSke4gZszhEp6GSi
4YjdUKcN27TXwyCMawP2mO9iJUk7J9AEQPTKmbHox7Cl5ais7bWVOMXbuR3P/HxSFGgOL3rJUuz9
Lhq8b9VWeko/7zXiNmnShBfGejVlB/hT0YIGIwlf7rmctqIguiG8ByMS2d7kd1ZPYbfb3nXBpIMt
g75BBLOakoxofHNIUZp3fT0HuMWeb1v1Y8PqJLtjrPs2NDfRqBWWbGcyYbbsxhfFEP8IK9NTOhGw
996Zj7HAZss9vwDM1V/pcr/iMYwrkEycgib7E+Ui6M6JV5y/UW1W3DZcWQOuTBdBo024VAF0Ojpt
t1lsPR9P2dYk9SJwCrC21GpKjpvD7sKP/cIzCe8BNB01XUTiyIZYeo0OSuOhGV4w0IPK++3mD0qi
MMNxTsncH1nceX99Z0IZJaYxxX83GNpcZX5aHURmwwr8/fuXxFW19vTEN9u5AStYFOEW4EqyKtVG
P3N4jr/+ANUgUsz0U5i47zQVszbGkpTcFotKyV5GanT52cTK6CJPAFQARLi4Z5h4xxW0pIzlZehX
l8QRhLBhN7GTMzvM2nwQqAm238RT4JokJYvqBallfRD+bXVHIiJBHHfsukWWO4vTZAzXCEgMuUk0
xCvu6R6FnfwkeGEqINyomupXc71oTowYhDJhI7gi9F1HnQJ9edELexjuhg0Ju/uxfmaxXoo3PWKj
XSqmj+Wx8Uj+gcvF8q38PxFn84poPEP2bc+mmSmVhqKQZXKiqjhFReFKB+ydDy0HccOV73+lyznB
UROdAmB82ZVOH13e9Wm0ab7vMusT6OriY36NzjBsrDFXSV2BCkCvJShjDth2kbX139a6wNbZsp73
H/XKglRh7EtrN3g9MmQlk82CJGWPrCwkTpWc5rfJSox6GMcluVnz4W8Q2TNEVl8XfcvD7qihczG1
M0lbr5dt+DfOQ2BjvSi5KyMB4IBEgMiIArilNztUgNQ0i1oR+WVFeqof183qchFZHcta4FRRNOUy
PvebDBEVioPnsoWXkuQM4pKCcx7hH3ouNEhlzsmMH/UyR9gEE9zSKKwzxsxirEVJJUxL49hxBBgT
ZHjiyk2YRkEIsTkn9MWCu/OLi0SnENzmDXx5cQNlydDf37Hmv3gf5TrY0yNIQUoevSZgG4V3bG5u
GptlCEa6TQmcWcF9MFYyogtQLbelpB2F7MgEBfSHMKGvI59waPjHOl4D9Y5Pe3qA3/v+YPPb1Rb4
CvuijjqftLqQTHyLbZIeFLh6XEnWYzsy36VelQ4MeIrI9xuGf4IRiBxsai+QUpgbF2Am2MjwRQeQ
and7u3Q3ZlWhcpqGfGuc0wFvJh5HNusUJIVHnLqAtrE1Sm+FRH67M3pQ6N7G1r7WGON2ZafDGjqa
Ic2fs7foNN7R49UDc1XhM60Igabwi/Rf6XDHR8LN1ERrZj7W7EvjOcEuLItFjMkYC83Z+erKLz6x
qCkpS3CWomFXAxSa2+M1tIU28MOUpXE+DbRfyv6sJsNqpzJ21c0yz+xvQ9pJC92kwmPaTSiuYsFK
DflS+FrLPELJJJRlDRVBBXczsw/KwhJoj+3kmrtp8KXoRlu72v2PAZr3w2VN4i0ZEAILT59THE6V
MWOjPcHVHG/K0diEOZF2N05+D2KEYUevs1tkIXcc+2QSFxnAU3hNXYtLv7vDDKe0vFZeW9hSjmg9
LySR2c4fiIl3px7cqSnDTYdFfaXYOrYJ26k2mhuGopeBKSDvfBjyNsnXWOnm3fsL7oklP70d0zH7
vUBmSRDlXcWYeO/d9QJ5yHbttoCLZfldiyToeYXmbVNdyA1ugg4AtosXSxY0fqpozyWejlzO1sey
OagQxVFoQzyvzTxya1ce8B6lG/B9VPrNbv1zw5OmRylPrRx48cafmkvA9s1QcnhZ0H9lj1i+mral
1d4lDn8yqt0sRIVDyXfkcTrC+XYL1dJnziltpJ4s+Hm4tn/EewLWkdftZGzHmbetu+sQhJPP23yL
2aCuXEc3fQBOTXtEcVsDDLCDkRy8HGRALiv5+QjYP3CqP55A7K6ExFpdUtw33wHHtTpZOw/o99uT
9cBk4tV2Po1kUzQ0NNEb9ACkB5hBoR0CLXSSTvD6bqUSFSDScH3dZaF6Ftq7WkC/4GZBfAxoXA4S
jAxEx/yRNYxS2qcCbK63UJdi/4K030bWXUor3lqBbdpjRDYNmR7zXsknuxJbA57mPIwivlTpa4xU
GWxH7BKEjbWZfHLX3ArQkciT1SkpyCxryDif3a2s65M+GSuarYFFNDqkgpEfBwPvBulyMgavUjk0
lYQ5cP9ZaTghagBbA03ks8yCEJOeXaD4UhsvrY5if5ZQOxB1IBBVndAVJfmhU+H726rnxd1vI+5N
D4PhEbZQ4/Dm2IM8+z19tMYeWUEJoGEXof2QreUvBiYJxBExLI8smZv9xA5NkxtQ/TAvFh0CMWGL
bLp5KoWlQT2T3lHSnKEaWmz3Z6CkgKqyy3CGEIy8pQXU+8kHcQ5f/tRR8wP3vi8d9Pgfh1ZpTCRh
Jk8mClVDh3us0u0K4BJ4dEZXjh7RHN0e/gsNfNUjgdCRqNhC98z5wX7UIo9PLbnvdSTbU/lgcpmb
jZ7BvN7c0C8mlhkpDFDOZ3UHgesxKa3SD4WG4xtW+HTPT2A9sLJpoGLXRXfLXqF0/uiDbUqD2q96
pXc6h96B8L63XJa1/dGiGIPB6011ER/TP6gXUjuMWdKjoeBseEHeGu7m58PstffAxpiAWsih2xc2
AEBizB8bfxKFQOJ6k6GyG8YijzXP0w3h9CZkzcM9uV4M4nUGAkZIPDvDirpQCm2QhrQjNZqZJdU9
EYElKR+4NSs/x2Z9bCG03lW5ofs7tM19TFGCQeJsd4PRqG/ST9j5u+mlsxhY55i+c2GAxShqAgFO
C8tv9sMV8Lpr5orsqZTNlsmKKJaNsHvu4cn3kYBNGudVuIg1XTYnSyEqIbvaP/UMdPS/9Ya2u6WM
qpeyID67V+0cD1+tzNrRAfLkmnL8ardkrcgZN9ulepOkKKw68oTSnhf/TYqULe80UhWoG7GjOk9G
cwGtEqjAuXr976pJURF2h1axFFU/jPPDTpHT79GLP/HOZi0OXWspoPFGZZ/aFyAtvcKk/igC2gCB
uSFR8mPNhBgAPPK4W0GaoV4aPSft1fTAd5Fr7zNxhYo54pyCBOd3cOJy3L9tOALtLWp4eXlGQ4kU
ZAW1mUxbvB4DtMUqLt/NSJ5pU1Zp2j7KhANcju1TMXtxf/ycBMqfMa5gkVGyyy8nT4Sqic1E6rIS
YSN8vcGdMEbQxML0wiAq7K3PJgoZJ220NomT57AQWvYnEep3LgZBld5s5Zy+FWR6uFrn7O2QWFe2
lYEqqNOvqHPCN7YemRT/rJrSso8OJE9SHUfoCC1fxuZVxZuKUYJTPzxD25ghNq4VuIjxF+DqYn3T
HBs9AyQWFkkC3czo9xbf+yqfee41uiEulW30Db1Yf9NYSArJLJH/o9vx59x4G5thYgVFATpv3KHk
C6Yu0e6bdwetyZ3S3iK/6/v9CnkGMJlgQv/lmhbyxkebKaGQZwxKgWaT3XAPHUEQ+tEb3eFS84U8
NpWPbCnwYnF/e4aoO0t3eQl/BaFF+jKsk/5cyxvbXwaXZgT8UraAJjkPYT/Eclvs+/rNbnSk94d8
Lqste8HqHZbVh3OLW7YgIiQhIzaEGZyK+GftSiWtI+FDUIIwUzHznA9rmTK9hr0KN7ykIQbApfvD
+c4EtY8Z7Mk0iuMn66em9rzz2Zlab3iru9Ma6EN9CWTeBtTW3RHKq4KXuKrDKISJa+P85YKV/8Rv
YbsiJ9VHosARwTKWhkvyEH7U+DkyZhHBL5gj682a7p6nA0OjjS38r/n4zA79/zTDHQM3ViUS7kCz
eLMW8yTRpEiykqZbhWN0d6mxXs2wq4eVzkdYahH19n/Nik5RleNI3wT/SJ6y7a/EAz4IusrkBCaF
RHqsfL3gT/okDvtTKu9inV5QMCx/DChy/b1CboThDaE8Cc7ZLo6hzpszvSpmRQCWCO2Nqi5THbHQ
VbABUbB9+N9zMdpX4stqH/NL0TiNsWnMJAOuFKQfZ+CGkx3vtcPAgGgSTm2ovMn7fzPqq+2zM+5z
C14mHYsdCyy+OtGpDSW/Sx9fAPYd+Dd1XsbZPcoi5YKiivwpl/lAKCuczPgbcer0dUsfcwttAaYY
v1Ih2Owr4cUYY2VZfu7aCyNSjbpxT07EY+9/2xkQYL/yB4Cha4qBqf/I+H0taq1tZhK85gUS7VL+
mAgZ50l/IdkNMRjX3VzS67FRaRWgnjFKfbhFNm/l6fU36zmanmvH4dlcxn8aTgMUWuhMHinpv1vJ
DMYli96HMI8gDsjN2ZfKlLxh3lV5SE9d3HujBYddSuiNvtBFxbVvkOeQ+YfmxQ7wJOap2REVQQj+
VARD3bAKPVigiqVxfq5WJSgT9gKPpxVQrNeWB1fbHU9u0RaTrQGbq9COMi9LPFWdKSMz9p25F8rd
YB7zNS87EZbxp4uYGiUn4BiHQ30KY9Y4mDyAPb8cDVrcMsHJursCmf0fe1+KJxTOQhZLggCzTAk0
jTQQ7E7fxUZZLo1ajt8im6JRQEy4rXK3w1m5u9syijAllXU2MPrDFqWIXDOhRM/URLr826hRfpBM
WmkAs0XbK7MY0yJISH43ISeP1i/D0tmKD/gGoipCcbasOzRClyt4AEAtuDYF0O4OGqdRr+rnYPfg
6AyuB8bJWDFOxXPXXcxV4qYaPB4ajEzmalK2iIAGE3Qh8EGUOE4C+/AYVSvgxgbegQtpSes6ioi3
Hon0H83BiYnFPituOm3P8KB9fWmSUUIXW2q47wzgmGEBGr5jzd85hPhLufjWXugC2wedaDIKOt5l
AQtyY3t6H4EkCXiElg0OwsO/VD2ln/NFKGzXzw03Bb2vnJfoK18svvKOmm4mponZ+F+Sp4tI/F1r
i9c2QjuC0xges5MCgb0qQhw2YXhf9/MYXEkPcZiZ21KOd8wQgky7tXTBtyk8didmSIuYkSGL0raT
pIbCfb0BRkKd/6KJhHFw3oPnQ+D8poPvbMPZLr9RPMB1d7DOsBOXlscptW6JifVbdtOYc8UDuP/W
txfIP4q+OiV2qzzY8YY7Dhrx0fW8OAs+MXJd243IWblY5hcMqk8Wi98o7/ZR7zntIEA2m+LdWT9W
Qi2RNdTN2cvOzok6DxE92p73G8KU9RLxPs4JaOhNA5s2BelRmk5PuIz6NroB4W7jd6ULpHLLoNqB
a2PazPcV8FEYU7W/j8/OoWVS6rk2rLxAKPlOq1Pa7C+XJzI4nnuQuv5iQtm0QU/WwbJtVguNoPlf
iBTGZv0TPwfM0De2UJ+Jc7qDASExJsSaoZjpsnKpZZqI2k2/4gIC15btGP4sWyMYhfjiapn+ApSk
l9gtfZAuctlquLxEjJpdxDSE8PM6X5RJ+VBi9zjMCSJntrsg7cO9nNT9TvLg8Y0MOE4keOM+EhIJ
apta1OsNjabNRkLY2L/S+t9TgHthdSjFF7IRtRsxTDEcevNcLfPSXkWmgt6OCvO8vAI1w68nMHnM
tLqAzuU8cBoVU0Gz3hL5Lt4AsORrtLF6nI1VTO4qupyYqDftM4m+GRDKiC0xQIZA5yE4b99ru8En
ZTFY4HNdSJpQpXJX3YyDGbhtlDBIXnScrbXm3sUBfvMpAnta+yxhSV34nnAwBE6cLqEenzG1RfHl
0t97Xd8D8qHZKEwlQ2eqXitYoZ94Zgc8FrOgyQOrOu3OJ241mGbBlrorBV68JlmjAySX23nT/bON
wM/aySjVzH2EfZne58wcSvL81cvzvuXlf8nfJkK0THFHAfBXBpQDrf6MXZ2/gYJu0WpCgxmXCAxM
zp1Ja3zvNVz1xJneTYgosiDPQIhH8yniqjuDJ+CJWlEbQbDA6iXQqY9arbHs+w8+FoBHmuUXSIPT
yjstGdglh623L2Eo799IgAqB//G4QyN+HRohDVuW+eS7F70jGGjjMpoxE8WhO5YGVqK8SGEJjSQK
P8LgM5BKmwqu7mdMz9hmrWODmgkdb3MWWhcq+0/x4S2W+mnyQ2rbTQcYLkIdBjCU8NYl7DZe189/
moiV3j+u2nM5dBf5NOO6kHSWIShYdYZbIhp99u+zHjorWkCxr7nOvkGgyEBSz4MDvNqcI3i2ArSe
3fFcprEM9LfPp6pjaW6yJa6evm/1RTE7TcxBcz6MHPmL3so9zC7VYTOfCFphlpfKY8cACQKCIrDz
9xqimexDqVcc4mwrLZuN3IQOHUfJdBQ53efobqlCh6YuY9A38K49hahcGW7KETQyu8LSlXbmsII1
tAWxyiKC1fB05Rtk1rWFmXQ0g2XBwpI54KoxsdW8gLvmeQ/b2/BnW9TwOsacrJIZGuKNVE+XdpIX
YOLvB48fh0ZFdzkMm7d80Ce4CMkLLfQ+bC5uq/+MV45k8mAyS+8fA0dtUeShJvuMGVnKWAIGi6Gk
oAMa31eY+ojR47Z/PocR4tuZ9v9m5/aTJhCsw0nLuifXSzWOdUs+VTsglcLtXINOuVcul94txsNu
kqCBOlnQJ4lcxrAoxcLzAwMERQxuHzFiDjxiBAOySBl2TOtcI4oMfIrxf6SJR6rgNx6svD3XLNtH
eykayPnXhd5ixxqHm6eCbcPxxN5MBxzHvPHJSqaose9vIcAPgwnzaprxnUlpq2CLmdyqxU3StO2J
6Bnb5mmHxJo0hyECaAiRNpQzfCj35mE5Gh38XX0RNXvB+NT+CTXm+PhRWx/vlQOxCXdq92AnU+/u
hV9HD38A5wLUGkMZLQBvweXWnNJYVWzuMaQnUsStN0YCj30013zauoSXokBF8N3vttIQD8FZ2p18
PVEkEwW3qGsOx66ZCGGxHyUkZ19fqulMIOPaCyu87DLHuKjBnUPuMpA6r+yFJBhSH2WoFBz42Dju
UtHz67CFtLCQwd9O9rooS56C+jJoGESP3+ll9CsZqE+JOb1hicc1qa48XV1KPLbn9RajveMqQDUA
ya5h1ezM0TNxXThpTxDFVKnx16wNMYgPfC94BJy/1clqc5IkCFMRbl23Ofr6FaIX27R+DIsXBepq
yVD43XS6rWa32pU8REr92z1nqHyvgR014/qUjAmH217o0jiIl5Nj41I6ozmMpj9WYMFtWSrVmxG3
GL34szRovdqU5Fsboxeg94MtO0IMnhtwy6hg7GuUJWaTHLM8F3PYe/w2vVISOa9Sut8MIYFVJpP3
hAoNct97CmloKKw3sTh49nqePUJl6t8TdWd2Smnh4nmnSPGB/jItiWgHhPyE/9KGF944U+Qnbxe8
VWbGLkxk4ZOp6GCAlKsdKM/d2Ir99Gkaidp3ilH79S7SmVVppCR7Ku+fy/LVySQX4l3qfaPfz7UW
OR3bCcA1s8Jf85ZogVz3SBvrZ3EvCn07aDOLtBErreui9XW/O8hXYFK+J+BIvOQoeoPNuk7P0kQr
RazIuhcnSf78LkHzSHjYwWhZkSVTi+abGe9faOc6yJForSafJqNgHInaZ0XMbzL+XL0CdlIni2Zl
OiwAKYFyi6xaGPxoXiwbSrsEC+/bwnUGK0ro7OBXAlkVXVfJkfn1tcxLmZbF23Bu6p+AFB3TtEGt
2WIOLJ+Vfwjvl6nriSvCY0hWjVe2mQuPoP8yvQRsBbmK/0wENK/cE3GIs4EoxGNDeClHr968wLJ9
Vd6xlXwUhC761mKej0bOZB/rWfU1lJgAychEJ5N4GSai9S6TLwFPxhJy+365GUFbttI7nqmkIcKW
FB2lFcneptCF7XhGCy6BonnypBMdk3Yd4+cvoY+RJQ15pacD67IA2QmhMzcmczuM9sQvRBVHpnCL
1xq71N85JqqndrEltvk6/ylwUc/DpbledAFVBaEmPqf8XEah1obhXyfYc8sqtPrVEEY4LpI4zh1b
VoPRN1kp1GQnWfhmKaDCcSPr/hcmTedLlWpvqj+hzs2k2n6B4u48hjan16LD5HLqnLeT++SMsd9t
9gkXW8gdLlh/D084/MxVUKBVV+q0CIIrU+ClHKhceHV8+bw6hryeAcNI2Yg1d1jA5d+ph4v1fL5I
t4Tzop3SuNkntnoHPI5WIgM/7Siy/vQD5Plb9xM0fpHqTyCOhX7Qh2enXkuD4/0FWKy/TfFLKjEe
MApP/Wjvv/2xQyctOACqFdr/jRfloIfOjaT6pzcOfqJi36HLXYkjY63B+xFrpRpue+rgepkRQ1xJ
U6VlEvrLQjahjc/XDOuvk+r9/YNx2Csp7RqdhnDzi9fn7LcH+tlLWVQT7nAjNaQtnxiaYti+r5IY
FQLX4XMRw3STp3t7wJ+MYA1S1rnwwVVuY2XShbnii+StxdIOiq0wAJrWI7Duo39m55SBmIBTjrN3
t8sdeZUhiH7imOPvh6sWSBGmaBBl0+CtRj1weDDcWp7Hul2gmKFiR/OOoMHy4u1VZTkqJaTjaKet
MVhiS8tTvWJGkv9LYiV6+QBKqNeKrs3X91QKiSQPNrYbFyP9tJOsiBjJO7W8ObTU4ER03Cl7UbnC
n/E4T8V3mOYeE5RV4Rn0n7vXqtGxdRxJYzVv/nFtfSmIARte0F0Tcjfs4f/TITSjPyKLgv2FFsD8
HSqonWI3iDppCfOrkS7/Q9CGFjBxUprTPDNt+4mz9gi3FSi1hvcprSaJ8SbENDIgP2AiowEtGg88
awM/QMF7t9DDUa18GnsqhnyV4js3VycHt0SBhYdoPX9hwNkFRxOZlNkuSDZ+AK2mAG6R4PatSkcr
w1/Tjhi7AaLMg4NCHp1wE7Wm1dXcZuH8P0cTciSoi3GjvY8B5jvP57EdcvCSgaIrkmkM1ETLzQab
fifoUZaOVUeiTQAA6GyuzlQiuNM2vUrc+Totzwp9+VPLCVcd8mSVkBF7GY/Fv2HcOZ3qJCBRHIvm
H3Ba/OguODuXzdwwxosGRbJyV9q1sio08c36QZEQmc3u7cwhQjC1D33NE9VrqsOT+K+ei7+8AZfo
BEZmLIVW/G+neEtmSEipT1zAil1CzMtHYXrFajH+VIdSh3o2rb82DUoVM8AcSSEyXcUz8neDDSCU
e0jMfLGaDpMhCoiCVb6WsnWVFDl3qEvdBXrcSpqOmvPztDsf6ANreQ6tbrxEJIxTWUocLeMkQqxH
FZpkUm6vzIVg+Hxgr97yVzjWJNTtGuY7nf4iapQB0gtIs8yNx4VQ/O7RdVSkunMpo3ajWOUJSvME
5rXO06b0vcNCepP6pEsW/Aq8jNLcN/die1WOc7PquOugojH0aDEDB4/kEvwXH/6ow+TFH4A53/F2
rB8rS/vEXEd2OOeP6YOkGJJaaGxiKxpRXOhnja8jey3YDqegUbGyDKo9KZ02I9DRVGMbNsIoetK9
XTJoyb1oXlpAQumxmRgnAhBBH2vRgLVtN4KTUKjL0InY3Y17paYGj0UL3U8hy96qulvY+nrtbEAQ
dzdsoTCmiOiT3EFeg6DYA51D8ly39/kwrGQCm22SKQd6VpuKyUlwMAIV/BQrs7lFZYVXxLmKx2C4
0Yq8AmusrTV6ib+Y9MuZsjBgEMUbXwFDkK/c4ujYGHI+u2FnLtRGfQg0378fvxIbT0fKXqUxkVWa
7jBu/z+LcJQXRh7zULWFcdiDR8NXr8+8bRQoJasUmQo4ZNrNS/aPcmcLecFYCralI9qUbixoy/x7
e7DlNVjLzKuVgIgQMcd4p35JtKNw1uAMo22+TakhMnvWCep2JsPLe8ePyUsJAlYkws7hVVXsZFrw
N35Que8NGshwSktrW1SQ3D6Wj1k6ugIFmcj6CoOmBNvkJcQcPU9y0BVBE1+ObHItEFE31Z3fT822
cet4z5Sqxn58gvAmgwUTQzJw+G0j+8cF0Kj5OK+sdLzShaqkpTUjqVUFNDSokcUx4iDVWOSPlrQB
N+YAXsdA5dU6m3n66OhdfbNY6Ckx7C9ceRLIVqbP0YH0sQj2lP7AR3qLL48S/P2Evp6JYeCX5ecd
dUFFQu0g348CVXkRU8ng/buWJ1T02QDEFfsHFOaKrzxWDxJZFYkxIaP1IWrZ8P1Stay3773iSPde
c1B6aPVELJXtzGXOS8XUf/aZq95g3tHcgrll588SsWkvXSFEC42EXf3VBwwgXqFE6WdPQVSVqDo0
ZsbUWhfMmyTMqFQCpRYv8qdXvY9tMrb7dN5yS6LZwHaJcsIJ6HPkxviVJwG5Aua+bI7wbtQiK6d8
zwW6rw/j+LhHdki19ToBg5vBoX25jhTuM+mUWbCXg53pFzXvfMEmTQlWLJGLLkNpqItO/aofhhXM
AhgJ7PpKRcptMizByBKY0yGtjBPo5PBd3aA4nVszc4D3AF4B7mMUaT3OwS3Uy8b0R7uI9pv9v1XB
PNpijIR2HGxF4cP9fC8oAlOkRW1p1jhzlA5+mZRiwyngTN6b/u4fKGPX58db1g4USrIEJ4d53bOZ
SfQVfPMvqTB05c1NQL7oK29ENSo7W+v/vj2uwFk90p9a5+pgfncNeoZ52AyV7QKZ76SWhKD860Jt
WauoCyzyJPmMhPTuO6WLB5+c9uFkxX2YZqizIVzkXnVxZfs+g2HmVDdBd6d5DbL4V13IB7psJZLi
XQWypNZ3LdSl+UAeV0nchD7kepW5+CyacV1E+ZrlGx294K0E8zbT5LLEOGF+Gs86zDJHTkyBinrZ
1GyeNe6XIY2QL/69iGUKrPb1MVHzVgiBoU2ocMfJFrCeg6CbEvXQSQY1hE5MoFgUpux4IMdHSFUJ
j1sYfwCI5w90z9371dVuzHz/jmS2UP0YwkujxspcmPQLVRosbKZTJcE9V4m/XRpE+nYW5A3pNWTr
b8YGb6fg6juvX+jOWnEqgmNleiuCxikD6QZdNerUUAfk/57so1YteuTGoHjGFfXhMeQIOz+KWFdS
4QzuVNzI2pf065OoS28NStQSED1nxA+MQQnFx13FhXGZsZVf2gdPMKR79Ecjq/9kUOzYoCWrLCgd
Yc2EJJl4jIC37GlUrP9vcPCUbx5C+TrrqA6Hb4Eqs4d9z6akFXGXHj++lAAs2MY2WsfhvkXtFEF1
06Lw/En2kCZPc3hwhSqF/nO4QhdKPWJTbBB7xfU2o3uCQEYV7KYFwpWSkqry4SfWHMBWHbalmssX
NYsJagX3gnCCa51GkTdzACH3s+k+AOJNWuRp0MH1jE+Opk2gt0W5QRAng4Bfov3Mh7LaATLtNQ39
S7H9m9i/cgBKFmLMxGYu00oIq4zMfdb9pgikH+1y1m/2JlUHEpCqQ1ibiqV3Nbf9mZ41Rg0pTArO
6SSRPQlUN0ZPbQQnYRFi4utWyLibiDI9vDSfv8A3XKjHOX1j1YuPJHkrtjKXDHdbpTpiza7MR9iP
5Q93mhaev6sdGkY4h/C1vk2a31QtUQHNHRahJjKHiaTigw5anLQKJcuKf5+IfbqiMAFLhKKq6mvh
Q5SvRJEeYOUZh9iVUQkhCIGGfmtyPVZMgaXKL20WQoqun3rCFnw20l4fUyH2Qq9ocJineAZHGG54
paSeBTJZn7SkN0emKqciscDxn5KMysF6O/jlO59SoAky2v+7E5mhJFxNlBJ5dAqy0qiAEamaHilr
Qc9nQLnTl7hBa6/Pk+wV1V1CrwGXDyIGRskkEkdKHrWNmVNLChQtBosTcjkoWOqZ7nfyqEiS3cHl
srfV6SA5xyJF1ugfsdgDMT5qwb96RDnPukD2WLrOZZ2Qou1g9mW0RgO9yqMt9ZzJUEHO4c/bTtts
PU1JL9VryHTsS18dNEIrlfka6b5qmwG9DqeXteb3UV8Q2fLdx2c20R6luD0BSLo4Q83K0Bgvb32Q
J+3aRrNiDd+ANXgU7FL1qkMCvKm/RRi4xLuIQGrmaGoUimpRitNJro5KOnWSx7k4FgLp4s5/d+V1
/paQYRxN0QPUAC4JqlGNFOMydqdJWjnE0LDqK+VybkaZti5nQIXo5xPFyFqohxiNBLJGk18nrsoP
ZDE74P9AFX9eKdmNWQ3TmAkWAVKj2clb20xxqOAuC1+RTJ/KQ3srN6yuKodI2+PaaHPw87VXwi5R
5SUnVl3Ov+LndxHq+Qp5ISb7xJphDrDUC3ppU644mFCv9ZN7nWqbuUGMPP31X5RCHE/9hAaNDPSx
qi5Lv6GzMOHRRbyBfckI/HmfeQC+tNjH08IZonygnergpxmIJ95jGYwXsQjX9jMr2aCRjmEi6ob6
WXL+JBvooQ2vPaMIymSfGxYgoywwoDS8WUqF73mXWGFh8Y8pnFyMjyjepmDkuSYgj2B155mWcuU6
dpy8I7oDAFdMk7rM9tgbfiJ0eQ6sllylwa38HWA7Vq2a+4bWXnXCVpO+PS3EQwTV2ZciDataCXCB
IAoInjPzCdoXxWuGadXy7fMZVYtES9V/f3brCtMMUI3plRsNIuWAkI+UlcU3Wt0GM2s5F9HZpeXM
UIQjOIXXDnkjU6L7+U2FhvFYnJ7MwvIlGvsQj/SSRcllH2eRJdRcgJLVz07HSJN5ByAISE4Y05ao
kRTpouvuh8LCpLVdkZRRHKlOkpfZdQJOABNfdx9u/Eg6bVgltdbsV+QxZ5ZbBb3182CP4FLn1AAN
EmQU0aAVujjr89jNq83i8SuGE+CYxjM1rF1+SPPhDPjYo3jIllhMw5mdOlAyi3w427fvWQ7CzUeA
mddpjsr6KVe9DxyvA8YZYYMjblx0gweQKcTXi+ZgodI0ajUskOgPWV1/Y5RBHgrAgA+dqoyGJ+tF
w1sUMO9yLPjcra0d2Ta95wbS5TRRDmEnZN/Q5JAe8+7J9K/94zlpBeSv/80oRTEL2JDFuJkj0E2p
8hVfUwEzbdtV1lPUdff0Of4r1MaTGizrgBOzPJUBJMQ46nQDkpw3/YhoXpe++Obd0QQT7LPEkZv+
e54Fo8vOUM+rFLQG3Q7xfQnGU3bdg9DA5ZlwBpQOOMkvsXTMQh1VWG3/n/p1GFwf+exvFPIZdmzT
CEzrblPNnyvMdwQGtoDut1Dv5Q54VrfQYp83cheeixMfKD2xmiv27DNT/n3o1We2G/acqcMh2Rg5
VaYGAg/1rCHrenCrlzGtlnB6run+AhmfwigpqwZGS0QL4SHIhb5dLzQaBC1vfJITKYlRdOiU7BIy
H8mFQp52P2jDj94qIz9kvzkXAjqirzBbKa0haeW4Nea9TBDQIPton0rqPsELb1/Q8aN5KCswVxP1
XfdXp1B28/diCYzGUsFyAlXLb/rYAQHqHlKlOxVuU1AsEKExoYYeccX2Ru2bvW+U2eYYbWRedUre
g9xzQXcoOsB4wP7Lss8gYHzSi5CVcnhJ1YX8Lgj+BKFl8S12PV+V9yW5sMqXC7A+eUpZdIJVmIs8
jBqwPbsR4lWogRf+Y9pLsuGOo3cEhV/lPtAiwF4jcoSgJm5jZ+0Djfh2toTDTTtSnMJmm/4489P6
9AYAihKzEnpyoJTd4icOJ9CRovUhxyP1tiETiV1FxPXKtI8160FU/7P45uiFcIH3quO5L/Gm4RFF
i7i+gl4GMP7iV1JNeHB8F7GGN5yDYACAEkOsrM6ev2oz4/ldtVP49iPLYixyEFF4l3jPr8juri4o
sYqOyG0/06lY4gfZYqzk78kNo9uKMyrKtsQhj7E5q3+YPqasLVK0W01wnewIhEmJSa4bexpYNxbB
U+LbPAetEbBxhOJvTSJojHNg60LRuxwhfT6s634au2dA3NvT8fQsUB4VWsaEIK7GwoAmpeRb/4Sw
U/CGN2vQVHBakM+B+aff7377gD85kIAee0mCiphqT6n/vmrs3HVCGK5v0+hYwg/VOBr0k48kBS80
2u1jf900wQziATyuzM7D9FVC7M3gnS6WjUv8eJua2TvbqtiWBeImw9TGXWopaxwbvWHCBaKknhb9
SY2JmRxSI/vV7IFILqByC6o2TTcg5LHUaqpPOg6AhA8qGu/dR4I2mLcTilyf31Yc4BULpzbHwdvN
iooiWSTo6MkEOjH6ag4VG4xNnSJFICs9zdT7CXAaFfF4aVRSwHm6s6c+DRyz9Cblwmas2ewnyGVC
cWpHq767wtXheGFc7DiTvel172EKu+zU5/eQVih9zqvdMhOX7W//aYEhhPtG0OApajr+kzQ/VHtq
dFeVke5LAR2MpKzU3kvyrjb+QnxjTTGsAnN5x9nva2IuYECrQozQ2BaOX/owbYYWMGW50x9P0keL
OXeKr5jE8ZxTVThBKL5TH/CFlTxcCqaZdHhea4QhZgbFsZ9D7lMu9WPoKJu9f4xg3ShHd+1gfsv0
ReqURAtwDnJX1Mzhq26WovZ9q8rF5tq5pzMMjWYS0+z3+L6pbBDE9tKOEgb+5vIqQ2sTzm8G8oq/
MkvTLmZ+9tmISU77NEAr3s65VYAYflY7PohsxUG/YCOEllg+V0Kyu3vtrJD3/w8sD3+JakvnSo5Q
/UFjoKRgk1yogIlG3IOCO0UTwx5xocOXI28MktrUzpZwSljsMUt263mUdG5Mc2irNHG70CgP8d2D
JU2zfWlXkiX0PJ4p9dtg6ttGmbYyK9ANTmZET5fImunKzK8C9+JVeYF5MQrJOobN1oQnEvYYNkAX
DArpmgZCb4PTeD4sU6zJre19fzlAOwvbHaPs3ABYSTOs3nilkiQfRN2f+oFS5xr4dWcB6dsZ2alQ
rqavgoeHULKaYI3V7Zy85yp3SV/J60KhiH+zAS9OYSLfALpMERmj7bZ3vJ9TdBNblHHb0H5mWHw5
4U8FFkUYh5a3BMMxKzBf33+MGxMpK5/IwQjN8+138uy++cUZ/ovLgXO5QgjVlb+dG9mrJ3n8NOJP
oC8ZCVfeRlOQdDBd/2MkxUU6w95tcsrFbaBGkUt9CUR9+Bx6MSBAErD++OPRrx7jH5j7zrCmtMCE
0T+636TjlrrQAt5ayFee7GQBx9f8QcPPLd3fWq+gfQMWKLj/jp8viFpIdLXG/UJ+oLnB6KAcK9OZ
WRcyeyu08E3QvHMGTdhNpjVqtM288a9Xw1ofMwuq3KcYHJKTDzg4RZsTWs+lsQSZQ3tXct6pQIcC
ClA7A1ZFVmB9ICjNs36MdNu0hgYy29qWkGebdnc8edBJCUfA4DlKS4p83UuX7E92nb4hmBH/S6QY
oWtsekUyFD6/O1PoYv5FxILZ+o6EPWxX0lt+DUVKTwVXCo+KO6JV/wS7t71r/jvZVn0jZLUrelOs
v81ZgBxVQyyhgBxSSIKg0YNGy2VbF68X1p8y/AW+Ezcx8hZiU9/GuENERB6tg4LSDRIwCl1PaQS1
k1PAqWg+EdSP4AfQ3TlWXZpggFMJBlqv8tkjnvH3EA64v5b2SLFgmkq1UNw37/+uVy4XetC0DO7b
goFS4Qp86yqUsmWo9jrGQt4c6qgcu9UX/zWlV/rLuMld/ZEjfiuETHKjCwVefOuWDhgirAmDHLKU
pP71PkeA2MSqwIilmxfSX209ZJydpefGuYUDmx6p7SV6MlJrqrA2ZUAEByuqkq/tp+G5YZU4dbX0
ehwiaejzu74+2jhRCtkLgLdYI07chfrHQPJrGt5o12TgoGC5IZMURXrI8iQWNPPgBNJNTSHKTrMP
Yq8HcLobqXcCGk/3tqP9wAEggDuijN3/coIblCUl8XJvKTb9B1snzuUVuk021uVAOUskDU++NWSK
kd4TP/Wpq1i22pVPhp5m2YOa9dNnqElAPWQvApYTAMJiM69mw9S36jO71PCQfvTodpeL1eoaWEP0
BMApUQqikPcElHI3zEMAn5k4OxjL5kFxad8zELUT26/Kr3pJreeVtGhhXeFwWtKw4DQKj04++gPX
BsXD7VL+zVhLyGY62HtxEhqteosZ3wTa9xR109xvfIeSEAarifnsRh2sUn4Jg1QW2n5CdREkyAdG
DwFpJXcE42K5yVXBDIVUxI33BEBqoyJ4oND/OYrVcnx/KPg+S7xnOCG6t6GNpT+VBkwxTpGwyUtL
kId7CeJcPISRROsa4ej+4MdH2KqYKCckfd1Bmg/GlP53+VjX/GAl6tKV7CMwTgpUDNPvaPxcfQB6
kkZl3ABbaVu3eKYWqkadtJ7S4qstbxhKR9CU8krPT88HCZeW5ykw6mTzm2ym7H2r26Agpd+oHWjM
xUcUxAAepRd3gjwqPzxavwDgGj4I5hGLs90aAM0dZ7ZqZef4nGlnG4Zc4jUyfdHwQGnvMuttOXas
0SzRjdixMGkwKPsW0crQq7p6x6nCBmICaShdEXqQBUkxf87KvBKKEtq69sN3Tb+dKfaLJfs20iLN
GUNrtOo26EFk/FiSU2RvOeONGt72ZwzUT4zX4roI68C9eKFcK++sNmhzYTMWI2vdPhLedSgXPSoK
73u9f955UGTg/stKp4ksJgqdd9IoO6CnwPwwgMvY7ptlyMSbywotb6yZJ+mYP+sW2sFDBtNpSb1m
2JUPagtOBqFkg+6G/g9uScGVUGglI7qEeSWErO8aj6tr1wjavH4mdBM/RkHWfdWUoYrLqv3/dXtX
PHrQ2338Oc9+mCtUiAWAf9M0jtx2IjwTLw48gqikwmAOuolMBt6/POxfbFjt5IdQ86g6LzbEFi3G
cdJRwg1LYASjSJPX+LObIhaJNvO6y59oMbuY6HOcrp9RSn4g4BAUaWs4s0JdaBICkYRHwWxtBo4z
ACAAH6wN7KvyiEzj/1OMhOg+eyc+1yLkni3NcKewv5PrZgCQhGT2P+nKh+6F0DeHDDCiGRVuLzUE
eKEFguBwbY327tz9LD59jHlfR/f92mMrkODMr4Ag9xmCDfF/M0xqljZtU2Hmy3VBoSgDbXt72hUi
qdsS3aHHyyz0mxcVQuoylO219YIivq0mXJMDyt8uQRD43bQDfbngvET4ukdQtzo30tlUur0HsS+/
rgB/BLh3e6mZRqxRrbL8ywngOhETXtD8+wAhOdYCln/jUzOr5P4JFjFu7evrXxGtps5yclKa4HKk
2ZXNsShU/2OqhFhivQvaudlHKo3zaTYKosNq+GUQD1ekOvjwCD+G62vdZgTSRnrWydVrWZtOtWUo
0WIbntwOc+bEJma+GTtDm+Cnnws3xixrZR1mAMTvJ0gOcPeZ61Fri0Pf1tvZHycxfPZb11Yv0gy4
jgGOM7e52SyCgtg02uyUJe3eao0Jifm0GMpm5zSzIk6hVdiSFYRVnRz2gSzzE83OxxIl7onI0Hzn
63LM4jm0QC9DRsFyMmsGNrA2AqF9jmCgiF5zL3J0Tnh1vMG0RK6lW51aNI9Ozij2DNLuHoY1j99C
lOsub783ZEatOjcGfvn0PH99JKoMWuUHt4za7RhGhNZciki87LWHxlviDfbpA3BpyQP8fM4vaVvO
ifDADD8X+Eh1M72SKrvOpGw5HJOC8q18V5Lmv9Fc3Gi6Gkg4Svwu+tp0ldd8Oqym0qApIq6Clsfs
IC4cASr4lXQMSbwPXBlBoYsvXyrFdAdEclz5scUyKYGaBWVKuYISVf1um5XJDEuMonmLCZ8DWcMe
p9Xfln9I0+FbdNvP7+QQrl98XGq2x69uDBXcVayun2haWWq5g3Z1Uvk0uuu+78LFMnnyvP2HI07U
A2b3cRqXx1cbBZIBZ0a/J9DuEOivVZzpWt02STZha1d1VAZMqsJZCQz6B9ABOlBINdRyqWqQGbPB
CYBM2T4H5WiSy9Os2uQbrVnqis/qpM4Ny0wd0abO1JCS+lfgRD6Drif+XJJRcm2NaX4ZUq0aHGhR
1fAxsdXJN6wZ9iQ258Jwp4n/vQkxQglQ98RryzHHCdlB0MQGLmghXg074GPmzjue7/OOyodOcjyh
47t1Ork7TKkVUaBYiIjbZj0efGMJdqbWOkKjk2ZUQbpuIG4yMY2a9xdtyWHuOAOzYAL6zXF6PEye
XX5vZ6FEeWzQM8lIpRpGQ2A6Q3b/qdaC5ymAHIfQOKV8/Aph1NHp1RFDrRH42revE9fWl0IW2yGH
1aZFFkX60dYpSaRootZosCtZgfy99hps44TS1w2E2d9w9jpWkeDa8urRFPFBLpN/b9zGqvxYBdou
YDHC2qAzSuQhKsBpj+GA6VhDwmKfesJd+lXWoRfueedY0D7/YV4ZsvOprdbeLYxAuIBy54LbByCi
sbUUfv7SzSE8Vn6VvnVFEJeUSTbkgwr9J6BnA6eFUnw5FfYJ1RWFcQtfX0N5qTT8k4obgWXcxZEe
dXAMFznNzLeXlmRuqcHyQ6QR1A1MADImFeqiXynzg3poOAQslrJoX1EWwUwEe244jNyyFBlx8Krb
7Y4aaIH2uKZ9PRnOchGOgwSjC4xaGpAfjoSoU28ifrVhDoq4loExYTPTMDW3sMIjhaopUWPCwNnR
CiCbuQZEl1z8Y6mQCbPL3+hmXZQ+zwupbe7XFQ9VtxFyztMQIeTsSYf/T3ovBW9XM51qpDM75Gtr
ifQFGOmxBuDV3O/Zolap+ck4EhfaxC+KmOhVL7pz95etmO1/Ttjf9EwmCAiCnjCxlZ3Ssa7jCO8y
np5217Jk2Ko26AwYRORg/SYOa9X44YeDZ4iCHf14Uh++CS6NVy1DYliFrem+D898icfn+fu4HkJc
n9fATu99CTSMvyiwZVlPi0kwdeSWs76F7Ra0vzoZn4T/o0YwVUpIdxVoeWppOBmccd8y/m29zMNN
haHfO2YEaHxfPplBUCIMLOTYz0fiQN42s/PC0ydA7ZLyhZUEPmei4rK7rnkqDe7YOJ49vHLGBJOs
dTIUuGwrXZxkQSRf88aQ8yYzNTn9sAAF7AP0uUa8XqQy/j+dBN+jerPJ52XzzAUSGNDIYdUUooHf
veM+qKPV9CXRHDHkAerPH4F/W6igPTR12S7dQUQoq4w3g20iqJcGR++xp1Lz8Cdeot4W6ODShlZb
a8StIEwS1+JQv+3tK7ypI+iAP6Gr/GMQ2qciuCs6MYtBE1CmkEHe4eJqVzr+FCyO+bAPBqEpQ+vE
r36gd6f2PI4jmv7rGj8hzwltJFAbdxejYXadldD0wN1fraGpJPEaJ15UKfXlw53vRX86OMoPnAyH
dFFu19GzD2qHHBiF3nMe2KE+PktQ3zHPku9drewP6rBSMrI4Qmi+hhMcxRfIwhy9u+3dXhSJEgZI
l+0btHIT5lHOr/vOac8NWqIQ+voao/usDjFdnyV2EE5F+eg26VF7hUIv+PKZ3UopkSQPFn5wjHRO
s4uL5kxSfU/oPcyUdiuugbS2RFd+VS0hwi7Ln0NRIOj92dPDaDWhtKgHSsQ4o8eiKvTGcfrX51wy
aCRcNBqfIXy0bdnQMb2jTE41lDvhGjzstbq1LcXSYTSh36YCsYYS96zqbXkr00p0DGpQbzO3zd9A
l+52B5f2vbJqO8tjbnQD4iEDq86TgjW7gGv7kso2TDfoba0jYG1vYBodEDWxVUw1yQOhLNg7p/Rc
4gey1vPKnyhuBhF8HkMVeubf6svczEcU9r8/Z9LKvCPi1J8R9i8taqqn10c5KxwXJGUfGRonnhsk
rsbKw2xIXKW/CWD6R1/B/JFEGJ0i9CrhWWArCFBTSSnyb2+mtT/EXHDc77htCFqbE1p6Vt/Sg42G
IUYsHOVPK36oaD2xVWa55b6xt79aSq6ZGc4ZhFsWb92CMHL72nPCYgBOy/VPJSTLDzzq3iqnBXK7
kJxqzA+j1J+lnMxP6q0sueUoyCnN5hKu0Fkz2cUgy/8gPG63bClv3KabS3IFibwd94Lnvi7iNYG2
MQhdpW0CYbmwXtWOwy07pqAPRnMVFu1h24VIOZj5W0G9/1w29In8yZx2yuBOhEE8fmR8pNYtQfRw
SYYKbIqnKEH60eb+S1KdaBrZF5DtiuTao35+mRMIVwYCimaMh/wfq70Ynxkr+Lf+N0VvuV0SUpwq
qKs55kCy5yWQ45Jv0C68rh74W67bH8DDjaTcNgByLJj4svCToId5P5hm17eMkZL34chMPiyb5lwJ
c5e6qneY/UH7J+hn51qjUSL8TTpIals8VvSSw+ozujCrekHvtAhw+gKWYKGkQIsowv6hQJAy1Kua
qN60QNEB3P/5fHxbfZMDl+wSD950wYkZHxHBJQdyRuHFgzxqOm204z5gScQD9VHXJdNJehdQr1Q7
lXhtzemMiYQf8BCm2ksAUwI4Z6XvU6N78cVbPFvoQVUeztR8ZSuvWtqOplyKreTH94OZYfYvxj7y
5yR1XpbPRsnz5PK+yfbQV5V27g5x5gfh5OMHUTC97KICTr4VnsV6c8c4N18EDT6eBsxVOxm5XVQE
UHKT7dfEvWIBpyBxa+TuJfSSgCeTX1DVvfdl13Jf+d/9f6joyZXZgbNJsD9d6XCRmF+rbIQSjmZV
7WiXHwLoFmsXQ10hxPdHX3iPHfF8I3ANZiuEIxUhDXCXw7kjYaRxz/XoeUJ23JO0Tc688Lh7sFha
bVsL0A9ALQ5fZ4h7oSKI60M97pvP3tRDBRuZskIiLBHejFerrfBi0zf9yhxsnapvQ4v4iTevtBkw
VF7svAHncgmNiOBuLBzRpU7scaEz0M596hn4k303XedW8Ztuci9ryf70nbBsI+vMyRiwxo/Ti2va
NDWRhOnfOE9ueLRNxFJ2DIzc9apEKZXJLzWle3AWE6FlCZ9qYB0RqVmxDcW7qilhcXjlKRbkzPAQ
Et17KYpxKzHYjq/vyPrwkXKeiMQ5fddTSjS/7yV+LWfYdO7NBHq0h5HtLWNcBVJ1yACvLDeKs5NR
4t3qTKkGzU5s1nC4h1iBuuvVVB5YuwnRiKJ5UZ/f4suO1THXa1lr8Si2IbRe9l72hPjbHIyNa5bH
ySgLsvKnwQQsPlkPDFQRhUmlsv7OLPRqyvnAQ4TrarVyJlunyKUea990G29aUT5cE2baYz9Taw/Y
C8Wi23eOvm3HXfidrDAjk269YCXUiaObonrg8bJ4SGKe9jM4SOVlr7p2eN5ONmjMaQ1EfGEgIuv3
1CHZ+FpcU/fRQFRvj0c+0IH2UE8m6HzfvAQAkLNhNkWif7gPPLNUfpaC8CzzfjaJt+EHpL5L6VR5
qkWC1Lh8DsJMqT0XWhw3AvAKg4iKq1Sl+oTVDRwqKxaidEudkM4rxJwcOdZTmSQ6wJw8OX9dLcmK
ug//RgIkiEn9X4TgzzVw/HDOu3VAcCqbSVEPWgLFSlG5LdcN7jCKQSYeeier6NZ7vhlNQKkbZ+Dp
5ybD9QhqdHgitwdqR7ThrapUnU6xM75oU42TE59QdBzM01Nt1SEBEs/sehEQpoV/pVHWJuxwc3ZS
ofAWCNdj9yirnH00Sdf/GZliC6UXr0X8+ev0zEqg0onSefJqOF1nEKOwsM9wUUaG8v87hopRUcAj
ZqPH43j2MR0fRHgOb/t9hIabJ6qmq+oxV0rmSvnJvnYwykgoQe7omTFA7zk7flcq43hwoAtDKhzK
sh0vIureCzxnswRoTEfxYUQtqPaFqLZzX9hdGA7BLIpV11JLABePi/bd736AG4/jnINdxHpll7Cq
6qBB1SZS5t2wxBFk97ImsCjMUhJVHEf1JSSKyAWcHhxMLyegcEDlRjCx0mC11/2lHBg+o4sTl155
dPIp41QCFawbXPZo9ejx6u98SYE/rZ8pMTX853+lWMI7LAFnqhj1EGh+LPfHuLrEkUvBBPw2M26f
8VkbMTOpaS7VHCNV8wo4BM+b9MJV/D+mOc2EKoJgHjbe5+7R2DbzRpazTsr2ARnB6Ge1smWfQHrL
a9Dc+5kuxO5XqZsDxAsr2uFOWQ8poP7XhXoMRjNHrFl8hJ7QvHaYZxFCp7DPQ1A03r6tYJgsik4/
sUR0dCn2hqOk0ZGS+SWL6g34Su9xgMFFts8+SOQkmPTaLJH3htJdT52Ho6ESQnl8SyMyaVnZc7C1
yKGm78sXkQCJ4Bz28xujizSMFZ+vZtcS4D3xyBg7U+oAo/dYqO0co31XHFxUtXnqjCF5gN/BlCJ0
7yEIC41al2FLlRaV8+qPkmxMWuYPj/zY2SXRSjf+q/fHhOOebaizKEFBdXrf1JX1noIQ7VNL5nz0
LDso0Iwc1kStQJ1/UjCmHSx1kL/Ab69X9MlF4YZSnMTfbpdoaMgaHGUU7IQSoz/+DavgZOnrOE7H
UzkmqX8SKibTKP2pwB3ga/ruZuMPbN8eYGIOlP0oYtdqg9jCnRtatndo+5swg0wCrJK43pzGX9Ew
Oft8tEFOdowvf9zLKh9/LaKFjRX5WZXiKJC7LIjvy/6GeBvDdnDzSnptog6jZnVqJpb+4YnfVo8f
PA6ycHZzBd3BwIBIgcjkWyZuWSx81JgxT0ZujpKlKQGcrcxLibVf9NaPJi6fRpln0NNxMEth59CF
XJIDB6NApVWQipIGPzC2jWlTsK542jz/X23r1PbqZrvvhwgW+15YaMUmyGr/dlDdCtgklRG/ZLkM
egj4pSTs1sw8iJUFPTIesOmCFgEn6c+z7YGkAFKgMPcfgb1m5HO9o3ApDhKgLg56iRSp3zk8J9ct
ObK9/l6ozHpQC/jn17+DEud3E1hqzOT3+55I5ng40s+/020kpXFyQCCs4EJE0Rw42b/bzFia73kJ
0wqMzbrmHj6ImlvZXuXngt8usEI6NTyWQQGzcaq2Irv2X1mIAPSblgD7tFf6r6DeIuJv94omCpdD
BJ3odI+CnZtm4gqgyUhdLrD1m1oNhTJ+y5jbpa/YpXGn0II+GVtrsE2hzHiwSmbbICg/Qc5Sf7iW
5dWC8+3lY1LHuwKukmDdjFyJDJ7TlmUee/fQto72xx2+3p2TPjsVEIFmnrjSbCAR9gFsefgwM4v4
7cKm3a+TtlDzbS7olYZTwHebWf9Pby3J0SmDGlEg5uJHZ5UPgqMcY7gj7l05wKivNakdv0XJF01y
hp9vjNiIOrk64noZNYJUOSK0vXvrN4oTL0Lq4+yq/xbhzDTCUtmU9C97xuX+F51pFWKSmzpwvBdF
DbNyKZP11VS+glTHem63OssHhpQ74bvJIFf7CFqCBFqjF99JsDUQBAS889aM6IUbPpZzJE207pfO
uwaCNr7kAC5VgkmbQvdYjexGynXk7OlCPx44TjgUas/E0MYXAYB+V0iD4C8qt/sAGQOJ83yVHCXg
7xIsr828tyIxCdqW81hW18pYIuy0um1ZtkhDDhpj4DZPwA3MsYo4rY0eBnZHw66qkiNUvv9sUHKw
gGPz8tQKEJz57vP4kBrcKt42Finj2PxXIjyhkNMfQneVbf368hC4/Po4aZ4mKvoZWBGKZlJl9RxO
sdv2HET2u04RPE1zcQTJzoLc8uRNiBXJaGZIHJHIVL+T30p5ToDavJ07fuUujKMaIU5wllgm9b37
0lDTEsnmkjblmd2AJzoLbGRG/CSAZ+Y8S83J4ieo39w0kZ44TLPk++9C4Xu8XJGgSRmFaL4P+nK6
9qp95rmEYFAoq62+BS7fntyhIOoI5jZfFcwm9Issu0AMS9CIDii/itlJFxo2SWWiRLT3O6IVbnnP
05SgS3mUT9oUF7Lr6EipZ9Cx7CePjnEoOUEsrCrtG5Vq11yA117GH/EtTH54cYXhCgmxLhGmd2EL
Ih68R/o9yDz93BijaZTSbXZ+4F01FYBN6Im64uX78ScXzx4CMzYx02P6W9PrVtGJASBzcR6UJJZa
CIcK39fN9DSafkC5ETujCWKm50oxmpErQmBx5e9uJrOqucyPloih2LaaW036T+a0EE/4ZgodjlI5
wK66sX3pbRc2sXt63HlUaGEnwlBjlVfyiq2lHkoEuNp64NIJ1XyNLDqLgxOyZp19j+z1+KRuHjJ5
lapDU/iYIpQoqnFdpajWcZxBjTr1FxYXkuMavymj8IaKCCILUxCP0I3RntcbW+phpyweEqbTIMef
sddj73ujUwF5PVTRX2+cNC2erda5PrxRelSAh1k8bk7EOD7V0smLQxRgzncj+nr2zU6rkd5jtZBC
4zbFtx3DSpYfCucfpa20hCU65+ha0zK17N931/J6rY+z8dex2CDLf6UxnXqrZthhxNrB5G35UTt4
C7zri6I1/T8o8WHNTz/HZFE2LOYwt/sVriswOSotdRRqe/1yLvgQei6gdDxm9oR9kHZqCKvckTKF
HlgRzoZm5KTJg2gzSn4w50H5S4V00VQRMZ701tQK6JhU55GWWqe4JKy2sj0veody+CQkUIw4UEz+
tTO0NbjwoiWPztVrFTQcQdWxSyAgwNHbXV7h9fq9k7k3
`protect end_protected
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-4/src/DEL.vhd | 1 | 311 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DEL is port(
D : in std_logic;
E : in std_logic;
Q : out std_logic
);
end DEL;
architecture behavior of DEL is
signal S : std_logic;
begin
Main : process (D, E)
begin
if(E='1') then
S <= D;
end if;
end process;
Q <= S;
end behavior;
| mit |
nathdwek/vhdltree | test/dummy_project/long_component_name5678.vhd | 1 | 94 | long_ent17y_n4m3_with_numbers4567: entity lib.deep.E4
2numbers_should_not_start: entity comp
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_0/zynq_design_1_rst_ps7_0_100M_0_stub.vhdl | 1 | 1970 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_0/zynq_design_1_rst_ps7_0_100M_0_stub.vhdl
-- Design : zynq_design_1_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zynq_design_1_rst_ps7_0_100M_0 is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end zynq_design_1_rst_ps7_0_100M_0;
architecture stub of zynq_design_1_rst_ps7_0_100M_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2017.2";
begin
end;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-7/src/Zeroes/ZeroCounter.vhd | 1 | 2760 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity ZeroCounter is
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end ZeroCounter;
architecture Beh of ZeroCounter is
component MROM is
port (
RE: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DOUT: out std_logic_vector(8 downto 0)
);
end component;
component MRAM is
port (
RW: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DIN: in std_logic_vector (7 downto 0);
DOUT: out std_logic_vector (7 downto 0)
);
end component;
component DPATH is
port(
EN: in std_logic;
--operation type
OT: in std_logic_vector(2 downto 0);
--operand
OP1: in std_logic_vector(7 downto 0);
RES: out std_logic_vector(7 downto 0);
--zero flag
ZF: out std_logic;
-- significant bit set flag
SBF: out std_logic
);
end component;
component CTRL1 is
port(
CLK, RST, Start: in std_logic;
Stop: out std_logic;
-- ÏÇÓ
ROM_re: out std_logic;
ROM_adr: out std_logic_vector(5 downto 0);
ROM_dout: in std_logic_vector(8 downto 0);
-- ÎÇÓ
RAM_rw: out std_logic;
RAM_adr: out std_logic_vector(5 downto 0);
RAM_din: out std_logic_vector(7 downto 0);
RAM_dout: in std_logic_vector(7 downto 0);
--datapath
DP_op1: out std_logic_vector(7 downto 0);
DP_ot: out std_logic_vector(2 downto 0);
DP_en: out std_logic;
DP_res: in std_logic_vector(7 downto 0);
DP_zf: in std_logic;
DP_sbf: in std_logic
);
end component;
signal rom_re: std_logic;
signal rom_adr: std_logic_vector(5 downto 0);
signal rom_dout: std_logic_vector(8 downto 0);
signal ram_rw: std_logic;
signal ram_adr: std_logic_vector(5 downto 0);
signal ram_din: std_logic_vector(7 downto 0);
signal ram_dout: std_logic_vector(7 downto 0);
signal dp_op1: std_logic_vector(7 downto 0);
signal dp_ot: std_logic_vector(2 downto 0);
signal dp_en: std_logic;
signal dp_res: std_logic_vector(7 downto 0);
signal dp_zf: std_logic;
signal dp_sbf: std_logic;
begin
UMRAM: entity MRAM (Beh_Zer) port map(
RW => ram_rw,
ADR => ram_adr,
DIN => ram_din,
DOUT => ram_dout
);
UMROM: entity MROM (Beh_Zer) port map (
RE => rom_re,
ADR => rom_adr,
DOUT => rom_dout
);
UDPATH: DPATH port map(
EN => dp_en,
OT => dp_ot,
OP1 => dp_op1,
RES => dp_res,
ZF => dp_zf,
SBF => dp_sbf
);
UCTRL1: CTRL1 port map(
CLK => CLK,
RST => RST,
START => Start,
STOP => STOP,
ROM_RE => rom_re,
ROM_ADR => rom_adr,
ROM_DOUT => rom_dout,
RAM_RW => ram_rw,
RAM_ADR => ram_adr,
RAM_DIN => ram_din,
RAM_DOUT => ram_dout,
DP_EN => dp_en,
DP_OT => dp_ot,
DP_OP1 => dp_op1,
DP_RES => dp_res,
DP_ZF => dp_zf,
DP_SBF => dp_sbf
);
end Beh;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_1/synth/design_1_axi_bram_ctrl_0_1.vhd | 1 | 17300 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_12;
USE axi_bram_ctrl_v4_0_12.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_1;
ARCHITECTURE design_1_axi_bram_ctrl_0_1_arch OF design_1_axi_bram_ctrl_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_bram_ctrl_0_1_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_bram_ctrl_0_1_arch : ARCHITECTURE IS "design_1_axi_bram_ctrl_0_1,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_bram_ctrl_0_1_arch: ARCHITECTURE IS "design_1_axi_bram_ctrl_0_1,axi_bram_ctrl,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=2048,C_BRAM_ADDR_WIDTH=11,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_SELECT_XPM=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC" &
"=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_1_arch;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/zynq_design_1_system_ila_0_0_sim_netlist.vhdl | 1 | 3912778 | null | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_auto_pc_0/led_controller_design_auto_pc_0_sim_netlist.vhdl | 1 | 510749 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:20:13 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top led_controller_design_auto_pc_0 -prefix
-- led_controller_design_auto_pc_0_ led_controller_design_auto_pc_0_sim_netlist.vhdl
-- Design : led_controller_design_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\m_axi_awaddr[11]\ : out STD_LOGIC;
\m_axi_awaddr[3]\ : out STD_LOGIC;
\m_axi_awaddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd is
signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal next_pending_r_i_5_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_1\ : label is "soft_lutpair118";
begin
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axaddr_incr_reg[11]_0\(9 downto 0) <= \^axaddr_incr_reg[11]_0\(9 downto 0);
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_7\,
O => p_1_in(0)
);
\axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(10),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_5\,
O => p_1_in(10)
);
\axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \state_reg[1]_rep\,
O => \axaddr_incr[11]_i_1_n_0\
);
\axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(11),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_4\,
O => p_1_in(11)
);
\axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_6\,
O => p_1_in(1)
);
\axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_5\,
O => p_1_in(2)
);
\axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_4\,
O => p_1_in(3)
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"0009"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[3]\,
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[2]\,
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(1),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(0),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A9A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(5),
I3 => \m_payload_i_reg[46]\(4),
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"009A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(1)
);
\axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(4),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_7\,
O => p_1_in(4)
);
\axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(5),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_6\,
O => p_1_in(5)
);
\axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(6),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_5\,
O => p_1_in(6)
);
\axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(7),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_4\,
O => p_1_in(7)
);
\axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(8),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_7\,
O => p_1_in(8)
);
\axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(9),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_6\,
O => p_1_in(9)
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(0),
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(10),
Q => \^axaddr_incr_reg[11]_0\(8),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(11),
Q => \^axaddr_incr_reg[11]_0\(9),
R => '0'
);
\axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(9 downto 6)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(1),
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(2),
Q => \axaddr_incr_reg_n_0_[2]\,
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(3),
Q => \axaddr_incr_reg_n_0_[3]\,
R => '0'
);
\axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr_reg_n_0_[3]\,
DI(2) => \axaddr_incr_reg_n_0_[2]\,
DI(1 downto 0) => \^axaddr_incr_reg[11]_0\(1 downto 0),
O(3) => \axaddr_incr_reg[3]_i_3_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(4),
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(5),
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(6),
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(7),
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(5 downto 2)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(8),
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(9),
Q => \^axaddr_incr_reg[11]_0\(7),
R => '0'
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444F4444444444"
)
port map (
I0 => \axlen_cnt_reg_n_0_[0]\,
I1 => \^axlen_cnt_reg[0]_0\,
I2 => Q(1),
I3 => si_rs_awvalid,
I4 => Q(0),
I5 => \m_payload_i_reg[46]\(7),
O => \axlen_cnt[0]_i_1__1_n_0\
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(8),
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1_n_0\
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(9),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[2]_i_1_n_0\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_2__0_n_0\
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1_n_0\
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_1_n_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[6]_i_1_n_0\
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[7]_i_2_n_0\
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
O => \axlen_cnt[7]_i_3_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[4]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[5]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[6]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[7]_i_2_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[0]_rep\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \m_payload_i_reg[46]\(6),
O => \m_axi_awaddr[11]\
);
\m_axi_awaddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[2]\,
I2 => \m_payload_i_reg[46]\(6),
I3 => \m_payload_i_reg[46]\(2),
O => \m_axi_awaddr[2]\
);
\m_axi_awaddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[3]\,
I2 => \m_payload_i_reg[46]\(6),
I3 => \m_payload_i_reg[46]\(3),
O => \m_axi_awaddr[3]\
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => next_pending_r_i_5_n_0,
O => \^axlen_cnt_reg[0]_0\
);
next_pending_r_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_i_5_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 is
port (
incr_next_pending : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_axi_araddr[11]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_14_b2s_incr_cmd";
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC;
signal next_pending_r_i_4_n_0 : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \next_pending_r_i_2__1\ : label is "soft_lutpair6";
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
incr_next_pending <= \^incr_next_pending\;
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_7\,
O => \axaddr_incr[0]_i_1__0_n_0\
);
\axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_5\,
O => \axaddr_incr[10]_i_1__0_n_0\
);
\axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_4\,
O => \axaddr_incr[11]_i_2__0_n_0\
);
\axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_6\,
O => \axaddr_incr[1]_i_1__0_n_0\
);
\axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_5\,
O => \axaddr_incr[2]_i_1__0_n_0\
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0202010202020202"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(3),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^q\(2),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^q\(1),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^q\(0),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_4\,
O => \axaddr_incr[3]_i_1__0_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A2A262A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A060A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(1)
);
\axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_7\,
O => \axaddr_incr[4]_i_1__0_n_0\
);
\axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_6\,
O => \axaddr_incr[5]_i_1__0_n_0\
);
\axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_5\,
O => \axaddr_incr[6]_i_1__0_n_0\
);
\axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_4\,
O => \axaddr_incr[7]_i_1__0_n_0\
);
\axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_7\,
O => \axaddr_incr[8]_i_1__0_n_0\
);
\axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_6\,
O => \axaddr_incr[9]_i_1__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[11]_i_2__0_n_0\,
Q => \^q\(11),
R => '0'
);
\axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\,
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(3 downto 0),
O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\,
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20FF2020"
)
port map (
I0 => si_rs_arvalid,
I1 => \state_reg[0]_rep\,
I2 => \m_payload_i_reg[46]\(7),
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[0]_i_1_n_0\
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(8),
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1__1_n_0\
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(9),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_2__1_n_0\
);
\axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => next_pending_r_i_4_n_0,
O => \^axlen_cnt_reg[0]_0\
);
\axlen_cnt[4]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[4]_i_1__2_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"A6"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \axlen_cnt_reg_n_0_[5]\,
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_2__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[1]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \m_payload_i_reg[46]\(6),
O => \m_axi_araddr[11]\
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF505C"
)
port map (
I0 => \next_pending_r_i_2__1_n_0\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => E(0),
I4 => \m_payload_i_reg[44]\,
O => \^incr_next_pending\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => next_pending_r_i_4_n_0,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[6]\,
O => \next_pending_r_i_2__1_n_0\
);
next_pending_r_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
O => next_pending_r_i_4_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^incr_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[7]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[6]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC;
incr_next_pending : in STD_LOGIC;
\m_payload_i_reg[44]_0\ : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[0]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \state[1]_i_1__0\ : label is "soft_lutpair1";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[0]\(0) <= \^axaddr_offset_r_reg[0]\(0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
\wrap_cnt_r_reg[0]\ <= \^wrap_cnt_r_reg[0]\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[3]\(1 downto 0) <= \^wrap_second_len_r_reg[3]\(1 downto 0);
\axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => sel_first,
I1 => \^m_payload_i_reg[0]_0\,
I2 => \^m_payload_i_reg[0]\,
I3 => m_axi_arready,
O => \axaddr_incr_reg[0]\(0)
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(0),
I1 => \m_payload_i_reg[44]\(1),
I2 => \^q\(0),
I3 => si_rs_arvalid,
I4 => \^q\(1),
I5 => \m_payload_i_reg[3]\,
O => \^axaddr_offset_r_reg[0]\(0)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0E02"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(0),
I2 => \^q\(1),
I3 => m_axi_arready,
O => \axlen_cnt_reg[4]\(0)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002320"
)
port map (
I0 => m_axi_arready,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => si_rs_arvalid,
I4 => \axlen_cnt_reg[6]\,
O => \axlen_cnt_reg[7]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
O => \m_payload_i_reg[0]_1\(0)
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
I3 => s_axi_arvalid,
I4 => s_ready_i_reg,
O => m_valid_i0
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFABEEAA"
)
port map (
I0 => \m_payload_i_reg[44]_0\,
I1 => \^r_push_r_reg\,
I2 => \^e\(0),
I3 => \axlen_cnt_reg[3]\,
I4 => next_pending_r_reg,
O => \^wrap_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => m_axi_arready,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[44]\(0),
I2 => \^sel_first_i\,
I3 => incr_next_pending,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[44]\(0),
I2 => \^sel_first_i\,
I3 => incr_next_pending,
O => s_axburst_eq1_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_1,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^m_payload_i_reg[0]\,
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => \^sel_first_i\
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000770000FFFFF0"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => m_axi_arready,
I2 => si_rs_arvalid,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \cnt_read_reg[1]_rep__0\,
O => next_state(0)
);
\state[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FC00040"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
I4 => \cnt_read_reg[1]_rep__0\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[0]\(0),
O => D(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[2]\(1),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \^e\(0),
I3 => \^wrap_cnt_r_reg[0]\,
I4 => \^axaddr_offset_r_reg[0]\(0),
I5 => \wrap_second_len_r_reg[2]\(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \wrap_second_len_r_reg[2]\(0),
I2 => \wrap_cnt_r[3]_i_2__0_n_0\,
I3 => \wrap_second_len_r_reg[2]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1D1D1D1D1D1DFD1"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^e\(0),
I2 => \^axaddr_offset_r_reg[0]\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[47]\(1),
I5 => \m_payload_i_reg[47]\(0),
O => \wrap_cnt_r[3]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[0]\(0),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000404"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[35]_0\,
I3 => \^e\(0),
I4 => \axaddr_offset_r_reg[3]\(1),
I5 => \m_payload_i_reg[47]\(0),
O => \^wrap_cnt_r_reg[0]\
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB00FFFFFB00FB00"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[47]\(0),
I3 => \m_payload_i_reg[35]_0\,
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
bvalid_i_reg : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
bresp_push : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
aclk : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo is
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC;
signal \^bresp_push\ : STD_LOGIC;
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_5\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair128";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_3\ : label is "soft_lutpair127";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
bresp_push <= \^bresp_push\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAABAAAA"
)
port map (
I0 => areset_d1,
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt[7]_i_4_n_0\,
I3 => \bresp_cnt[7]_i_5_n_0\,
I4 => \bresp_cnt[7]_i_6_n_0\,
O => SR(0)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFF22F222F2"
)
port map (
I0 => \memory_reg[3][1]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(1),
I2 => \bresp_cnt_reg[7]\(3),
I3 => \memory_reg[3][3]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAEFFAE"
)
port map (
I0 => \bresp_cnt_reg[7]\(4),
I1 => \bresp_cnt_reg[7]\(1),
I2 => \memory_reg[3][1]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(0),
I4 => \memory_reg[3][0]_srl4_n_0\,
O => \bresp_cnt[7]_i_4_n_0\
);
\bresp_cnt[7]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \bresp_cnt_reg[7]\(6),
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => \^cnt_read_reg[1]_rep__0_0\,
I3 => \bresp_cnt_reg[7]\(3),
I4 => \memory_reg[3][3]_srl4_n_0\,
O => \bresp_cnt[7]_i_5_n_0\
);
\bresp_cnt[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004004"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => mhandshake_r,
I2 => \bresp_cnt_reg[7]\(2),
I3 => \memory_reg[3][2]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(7),
O => \bresp_cnt[7]_i_6_n_0\
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0444"
)
port map (
I0 => areset_d1,
I1 => bvalid_i_i_2_n_0,
I2 => si_rs_bvalid,
I3 => si_rs_bready,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(0),
I4 => Q(1),
I5 => si_rs_bvalid,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^bresp_push\,
I1 => Q(0),
I2 => shandshake_r,
O => D(0)
);
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__0_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__0_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004100"
)
port map (
I0 => \bresp_cnt_reg[7]\(7),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \bresp_cnt_reg[7]\(2),
I3 => mhandshake_r,
I4 => \bresp_cnt_reg[7]\(5),
I5 => \memory_reg[3][0]_srl4_i_2__0_n_0\,
O => \^bresp_push\
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFEFFFE"
)
port map (
I0 => \bresp_cnt[7]_i_3_n_0\,
I1 => \bresp_cnt[7]_i_4_n_0\,
I2 => \bresp_cnt_reg[7]\(6),
I3 => \memory_reg[3][0]_srl4_i_3_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_2__0_n_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \out\(1)
);
\state[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^cnt_read_reg[1]_rep__0_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
O => \state_reg[0]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo";
end \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair129";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair129";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => sel,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(1),
I3 => \^q\(0),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[3]_rep__0_0\ : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo";
end \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair18";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair15";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair15";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \^wr_en0\,
I2 => s_ready_i_reg,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[0]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AA6A6AAA6AAA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[3]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \^cnt_read_reg[3]_rep__2_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[1]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
I3 => \^cnt_read_reg[3]_rep__2_0\,
I4 => \^cnt_read_reg[4]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
si_rs_rready : in STD_LOGIC;
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[2]_rep__2\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo";
end \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal m_valid_i_i_3_n_0 : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair19";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => r_push_r,
I2 => s_ready_i_reg,
I3 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE7F0180"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFB20000004"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[2]_rep__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAA9AAA9AAA9AA6"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read_reg[2]_rep__0_n_0\,
I3 => \cnt_read_reg[3]_rep__0_n_0\,
I4 => \cnt_read[4]_i_3__0_n_0\,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5DFFFFFF"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
I4 => \cnt_read_reg[0]_rep__1_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
I3 => r_push_r,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF08080808080808"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[4]_rep__0_n_0\,
I2 => m_valid_i_i_3_n_0,
I3 => \cnt_read_reg[3]_rep__2\,
I4 => \cnt_read_reg[4]_rep__2_0\,
I5 => \cnt_read_reg[2]_rep__2\,
O => \^m_valid_i_reg\
);
m_valid_i_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
O => m_valid_i_i_3_n_0
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEAAAAAAFEAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[2]_rep__0_n_0\,
I3 => \cnt_read_reg[4]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axlen_cnt_reg[1]\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_0 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axlen_cnt_reg[0]\ : STD_LOGIC;
signal \^b_push\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state_reg[0]_rep_n_0\ : STD_LOGIC;
signal \state_reg[1]_rep_n_0\ : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^wrap_next_pending\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair115";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair114";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axlen_cnt_reg[0]\ <= \^axlen_cnt_reg[0]\;
b_push <= \^b_push\;
incr_next_pending <= \^incr_next_pending\;
sel_first_i <= \^sel_first_i\;
\wrap_boundary_axaddr_r_reg[0]\(0) <= \^wrap_boundary_axaddr_r_reg[0]\(0);
wrap_next_pending <= \^wrap_next_pending\;
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"04FF"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \^axlen_cnt_reg[0]\,
O => E(0)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"000004FF"
)
port map (
I0 => \state_reg[0]_rep_n_0\,
I1 => si_rs_awvalid,
I2 => \state_reg[1]_rep_n_0\,
I3 => \^axlen_cnt_reg[0]\,
I4 => \axlen_cnt_reg[6]\,
O => \axlen_cnt_reg[7]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg[0]_rep_n_0\,
I1 => \state_reg[1]_rep_n_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^b_push\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCF000045000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[0]_rep__0\,
I2 => \cnt_read_reg[1]_rep__0_0\,
I3 => m_axi_awready,
I4 => \state_reg[0]_rep_n_0\,
I5 => \state_reg[1]_rep_n_0\,
O => \^b_push\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^wrap_boundary_axaddr_r_reg[0]\(0),
I2 => next_pending_r_reg,
I3 => \^axlen_cnt_reg[0]\,
I4 => \axlen_cnt_reg[6]\,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^wrap_boundary_axaddr_r_reg[0]\(0),
I2 => next_pending_r_reg_0,
I3 => \^axlen_cnt_reg[0]\,
I4 => \axlen_cnt_reg[1]\,
O => \^wrap_next_pending\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"5555DD551515DD15"
)
port map (
I0 => \state_reg[1]_rep_n_0\,
I1 => \state_reg[0]_rep_n_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[1]_rep__0_0\,
I4 => \cnt_read_reg[0]_rep__0\,
I5 => s_axburst_eq1_reg_0,
O => \^axlen_cnt_reg[0]\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[39]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[39]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^axlen_cnt_reg[0]\,
I1 => sel_first,
I2 => \state_reg[1]_rep_n_0\,
I3 => si_rs_awvalid,
I4 => \state_reg[0]_rep_n_0\,
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^axlen_cnt_reg[0]\,
I1 => sel_first_0,
I2 => \state_reg[1]_rep_n_0\,
I3 => si_rs_awvalid,
I4 => \state_reg[0]_rep_n_0\,
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^axlen_cnt_reg[0]\,
I1 => sel_first_reg_1,
I2 => \state_reg[1]_rep_n_0\,
I3 => si_rs_awvalid,
I4 => \state_reg[0]_rep_n_0\,
I5 => areset_d1,
O => \^sel_first_i\
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEFE0E0EFEFE5E5E"
)
port map (
I0 => \state_reg[1]_rep_n_0\,
I1 => si_rs_awvalid,
I2 => \state_reg[0]_rep_n_0\,
I3 => s_axburst_eq1_reg_0,
I4 => \cnt_read_reg[1]_rep__0\,
I5 => m_axi_awready,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E220E0000000000"
)
port map (
I0 => m_axi_awready,
I1 => \state_reg[1]_rep_n_0\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => \cnt_read_reg[1]_rep__0_0\,
I4 => s_axburst_eq1_reg_0,
I5 => \state_reg[0]_rep_n_0\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \state_reg[0]_rep_n_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \state_reg[1]_rep_n_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \state_reg[1]_rep_n_0\,
I1 => si_rs_awvalid,
I2 => \state_reg[0]_rep_n_0\,
O => \^wrap_boundary_axaddr_r_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair126";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(0),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(10),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(10),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(11),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(11),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF6"
)
port map (
I0 => wrap_cnt_r(3),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axaddr_wrap[11]_i_4_n_0\,
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \axaddr_wrap[11]_i_3_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => wrap_cnt_r(1),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => wrap_cnt_r(2),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(1),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(2),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(3),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[46]\(13),
I2 => \m_payload_i_reg[46]\(12),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[46]\(12),
I2 => \m_payload_i_reg[46]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[46]\(13),
I2 => \m_payload_i_reg[46]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[46]\(13),
I2 => \m_payload_i_reg[46]\(12),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(4),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(4),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(5),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(5),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(6),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(6),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(7),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(7),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(8),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(8),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(9),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(9),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3 downto 0) => axaddr_wrap(11 downto 8)
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3 downto 0) => axaddr_wrap(7 downto 4)
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444F4444444444"
)
port map (
I0 => \axlen_cnt_reg_n_0_[0]\,
I1 => \axlen_cnt[3]_i_2_n_0\,
I2 => Q(1),
I3 => si_rs_awvalid,
I4 => Q(0),
I5 => \m_payload_i_reg[46]\(15),
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(16),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt[3]_i_2_n_0\,
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(17),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt[3]_i_2_n_0\,
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt[3]_i_2_n_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[3]_i_2_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(8),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(9),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(1),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(1),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(2),
I3 => \m_payload_i_reg[46]\(14),
I4 => sel_first_reg_4,
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(3),
I3 => \m_payload_i_reg[46]\(14),
I4 => sel_first_reg_3,
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(5),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_awaddr(9)
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 17 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_14_b2s_wrap_cmd";
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__1_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I3 => \state_reg[1]_rep\,
I4 => Q(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I3 => \state_reg[1]_rep\,
I4 => Q(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I3 => \state_reg[1]_rep\,
I4 => Q(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axaddr_wrap[11]_i_4__0_n_0\,
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \axaddr_wrap[11]_i_3__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \wrap_cnt_r_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \wrap_cnt_r_reg_n_0_[1]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I3 => \state_reg[1]_rep\,
I4 => Q(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I3 => \state_reg[1]_rep\,
I4 => Q(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I3 => \state_reg[1]_rep\,
I4 => Q(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I3 => \state_reg[1]_rep\,
I4 => Q(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I3 => \state_reg[1]_rep\,
I4 => Q(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I3 => \state_reg[1]_rep\,
I4 => Q(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I3 => \state_reg[1]_rep\,
I4 => Q(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I3 => \state_reg[1]_rep\,
I4 => Q(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I3 => \state_reg[1]_rep\,
I4 => Q(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_2__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[11]\,
S(2) => \axaddr_wrap_reg_n_0_[10]\,
S(1) => \axaddr_wrap_reg_n_0_[9]\,
S(0) => \axaddr_wrap_reg_n_0_[8]\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[7]\,
S(2) => \axaddr_wrap_reg_n_0_[6]\,
S(1) => \axaddr_wrap_reg_n_0_[5]\,
S(0) => \axaddr_wrap_reg_n_0_[4]\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"20FF2020"
)
port map (
I0 => si_rs_arvalid,
I1 => \state_reg[0]_rep\,
I2 => Q(15),
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => Q(16),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => Q(17),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt[3]_i_2__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
O => \^axlen_cnt_reg[0]_0\
);
\axlen_cnt[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1__1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => Q(14),
I3 => Q(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => Q(14),
I3 => Q(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => Q(14),
I3 => Q(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => Q(14),
I3 => Q(1),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[2]\,
I2 => Q(14),
I3 => Q(2),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => Q(14),
I3 => Q(3),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => Q(14),
I3 => Q(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[5]\,
I2 => Q(14),
I3 => Q(5),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => Q(14),
I3 => Q(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => Q(14),
I3 => Q(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => Q(14),
I3 => Q(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => Q(14),
I3 => Q(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(9),
O => m_axi_araddr(9)
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"313D020E"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_1\,
I3 => \m_payload_i_reg[35]\,
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => \wrap_cnt_r[1]_i_1_n_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_cnt_r[1]_i_1_n_0\,
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 53 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 53 downto 0 );
signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 to 3 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_3\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21";
begin
Q(53 downto 0) <= \^q\(53 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_4__0_n_0\
);
\axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5__0_n_0\
);
\axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_6__0_n_0\
);
\axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => O(3 downto 0),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4__0_n_0\,
DI(1) => \axaddr_incr[3]_i_5__0_n_0\,
DI(0) => \axaddr_incr[3]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1FDF00001FDFFFFF"
)
port map (
I0 => \axaddr_offset_r[1]_i_3_n_0\,
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \axaddr_offset_r[2]_i_3__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_3_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_r_reg[3]\(1)
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => si_rs_arlen(3),
I1 => \axaddr_offset_r[3]_i_2__0_n_0\,
I2 => \state_reg[1]_rep_0\,
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[0]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(2),
O => \^axaddr_offset_r_reg[3]\(2)
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2__0_n_0\
);
\axlen_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => si_rs_arlen(3),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => \m_payload_i[52]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => si_rs_arlen(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[52]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(39),
I2 => si_rs_arlen(3),
I3 => \^q\(40),
I4 => \^q\(41),
O => next_pending_r_reg
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[1]_rep_0\,
I3 => \state_reg[0]_rep\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888082AAAAA082A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => si_rs_arlen(3),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002AA02A0A2AAA2A"
)
port map (
I0 => \^q\(4),
I1 => si_rs_arlen(3),
I2 => \^q\(35),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => si_rs_arlen(3),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(35),
I3 => si_rs_arlen(3),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0EF0FFFF0EF00000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\(1),
I1 => \^axaddr_offset_r_reg[3]\(2),
I2 => axaddr_offset_0(0),
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[2]_0\(0),
O => \wrap_second_len_r_reg[2]\(0)
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA4AFFFFAA4A0000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\(1),
I1 => \^axaddr_offset_r_reg[3]\(2),
I2 => \^axaddr_offset_r_reg[1]\,
I3 => axaddr_offset_0(0),
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[2]_0\(1),
O => \wrap_second_len_r_reg[2]\(1)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC;
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0 : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0 is
signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_5_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[0]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_2\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_5\ : label is "soft_lutpair53";
begin
Q(54 downto 0) <= \^q\(54 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
wrap_second_len(2 downto 0) <= \^wrap_second_len\(2 downto 0);
\wrap_second_len_r_reg[1]\ <= \^wrap_second_len_r_reg[1]\;
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_4_n_0\
);
\axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5_n_0\
);
\axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_6_n_0\
);
\axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(11 downto 8),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4_n_0\,
DI(1) => \axaddr_incr[3]_i_5_n_0\,
DI(0) => \axaddr_incr[3]_i_6_n_0\,
O(3 downto 0) => axaddr_incr(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(7 downto 4),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
O => axaddr_offset(0)
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000700FFFFF7FF"
)
port map (
I0 => \^q\(39),
I1 => \axaddr_offset_r[0]_i_3_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_3_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \^q\(40),
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(35),
I3 => \^q\(3),
I4 => \^q\(36),
I5 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
O => axaddr_offset(1)
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"03FFF3FF55555555"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(2),
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \axaddr_offset_r[2]_i_4_n_0\,
I5 => \state_reg[1]_rep\,
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_4_n_0\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \^q\(42),
I1 => \axaddr_offset_r[3]_i_2_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(3),
O => \^axaddr_offset_r_reg[3]\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2_n_0\
);
\axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(52),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(40),
I2 => \^q\(42),
I3 => \^q\(39),
O => next_pending_r_reg
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => b_push,
I3 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A002A2AAAA02A2"
)
port map (
I0 => \^q\(2),
I1 => \^q\(41),
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A0A2AA02AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(42),
I2 => \^q\(35),
I3 => \^q\(36),
I4 => \^q\(41),
I5 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(35),
I3 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDD8DDAAAAA8AA"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r[0]_i_3_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \wrap_second_len_r_reg[3]\(0),
O => D(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\,
I1 => \wrap_cnt_r[3]_i_2_n_0\,
O => D(1)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len\(1),
I1 => \wrap_cnt_r[3]_i_2_n_0\,
I2 => \^wrap_second_len_r_reg[1]\,
O => D(2)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len\(2),
I1 => \^wrap_second_len_r_reg[1]\,
I2 => \wrap_cnt_r[3]_i_2_n_0\,
I3 => \^wrap_second_len\(1),
O => D(3)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \axaddr_offset_r[0]_i_2_n_0\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[3]\,
O => \wrap_cnt_r[3]_i_2_n_0\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800FFFFF8FF"
)
port map (
I0 => \^q\(39),
I1 => \axaddr_offset_r[0]_i_3_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \wrap_second_len_r_reg[3]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000CCCCCACC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF2FFFFFF"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(3),
I1 => \state_reg[1]_rep\,
I2 => \wrap_second_len_r[3]_i_2_n_0\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \axaddr_offset_r[0]_i_2_n_0\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFE200E2"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(2),
I3 => \^q\(35),
I4 => \wrap_second_len_r[0]_i_4_n_0\,
I5 => \wrap_second_len_r[0]_i_5_n_0\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_5_n_0\
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2EE22E222EE22EE2"
)
port map (
I0 => \wrap_second_len_r_reg[3]\(1),
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r[0]_i_2_n_0\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[3]\,
I5 => \axaddr_offset_r[2]_i_2_n_0\,
O => \^wrap_second_len_r_reg[1]\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08F3FFFF08F30000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\,
I1 => \axaddr_offset_r[0]_i_2_n_0\,
I2 => \^axaddr_offset_r_reg[1]\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]\(2),
O => \^wrap_second_len\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00FFFFBF00BF00"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \axaddr_offset_r[0]_i_2_n_0\,
I2 => \axaddr_offset_r[2]_i_2_n_0\,
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]\(3),
O => \^wrap_second_len\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_4_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
shandshake : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair82";
attribute SOFT_HLUTNM of shandshake_r_i_1 : label is "soft_lutpair82";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => si_rs_bvalid,
O => shandshake
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[0]_rep__1\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\;
architecture STRUCTURE of \led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_valid_i_i_1__2\ : label is "soft_lutpair90";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[3]_rep__0\,
O => \cnt_read_reg[0]_rep__1\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \^skid_buffer_reg[0]_0\,
I3 => \cnt_read_reg[3]_rep__0\,
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[3]_rep__0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
shandshake : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel is
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_5 : STD_LOGIC;
signal \bresp_cnt[7]_i_7_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair131";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_5,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bresp_push => bresp_push,
bvalid_i_reg => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\,
\in\(15 downto 0) => \in\(15 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready,
si_rs_bvalid => \^si_rs_bvalid\,
\state_reg[0]_rep\ => \state_reg[0]_rep\
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
I1 => \bresp_cnt_reg__0\(1),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_7_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_7_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_7_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_5,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_3,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACECCCC"
)
port map (
I0 => m_axi_bresp(0),
I1 => \s_bresp_acc_reg_n_0_[0]\,
I2 => \s_bresp_acc_reg_n_0_[1]\,
I3 => m_axi_bresp(1),
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[1]\,
I1 => m_axi_bresp(1),
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_3 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
incr_cmd_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd
port map (
E(0) => E(0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[0]_0\ => sel_first_0,
\axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_12,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[11]\ => incr_cmd_0_n_13,
\m_axi_awaddr[2]\ => incr_cmd_0_n_15,
\m_axi_awaddr[3]\ => incr_cmd_0_n_14,
\m_payload_i_reg[46]\(9 downto 7) => \m_payload_i_reg[46]\(18 downto 16),
\m_payload_i_reg[46]\(6 downto 4) => \m_payload_i_reg[46]\(14 downto 12),
\m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[46]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[46]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(1 downto 0) => Q(1 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\(9) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]\(8) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_12,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[46]\(17 downto 14) => \m_payload_i_reg[46]\(18 downto 15),
\m_payload_i_reg[46]\(13 downto 0) => \m_payload_i_reg[46]\(13 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first,
sel_first_reg_1 => sel_first_reg_2,
sel_first_reg_2 => incr_cmd_0_n_13,
sel_first_reg_3 => incr_cmd_0_n_14,
sel_first_reg_4 => incr_cmd_0_n_15,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 is
port (
incr_next_pending : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_14_b2s_cmd_translator";
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_3 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair14";
begin
incr_cmd_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2
port map (
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(11) => incr_cmd_0_n_3,
Q(10) => incr_cmd_0_n_4,
Q(9) => incr_cmd_0_n_5,
Q(8) => incr_cmd_0_n_6,
Q(7) => incr_cmd_0_n_7,
Q(6) => incr_cmd_0_n_8,
Q(5) => incr_cmd_0_n_9,
Q(4) => incr_cmd_0_n_10,
Q(3) => incr_cmd_0_n_11,
Q(2) => incr_cmd_0_n_12,
Q(1) => incr_cmd_0_n_13,
Q(0) => incr_cmd_0_n_14,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[0]_0\ => sel_first,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\,
incr_next_pending => incr_next_pending,
\m_axi_araddr[11]\ => incr_cmd_0_n_15,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\(9 downto 7) => Q(18 downto 16),
\m_payload_i_reg[46]\(6 downto 4) => Q(14 downto 12),
\m_payload_i_reg[46]\(3 downto 0) => Q(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1(0) => sel_first_reg_4(0),
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\ => \state_reg[1]\,
\state_reg[1]_0\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => Q(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => Q(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(17 downto 14) => Q(18 downto 15),
Q(13 downto 0) => Q(13 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\(11) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_15,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_2 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_push,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_2,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[2]_rep__2\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 53 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_offset : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
shandshake : out STD_LOGIC;
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\cnt_read_reg[0]_rep__1\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
aresetn : in STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice is
signal \gen_simple_ar.ar_pipe_n_2\ : STD_LOGIC;
signal \gen_simple_aw.aw_pipe_n_1\ : STD_LOGIC;
signal \gen_simple_aw.aw_pipe_n_91\ : STD_LOGIC;
begin
\gen_simple_ar.ar_pipe\: entity work.led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice
port map (
O(3 downto 0) => O(3 downto 0),
Q(53 downto 0) => \s_arid_r_reg[11]\(53 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\,
\aresetn_d_reg[0]_0\ => \gen_simple_aw.aw_pipe_n_91\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
axaddr_offset_0(0) => axaddr_offset_0(0),
\axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]\,
\axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]\,
\axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i0 => m_valid_i0,
m_valid_i_reg_0 => \gen_simple_ar.ar_pipe_n_2\,
next_pending_r_reg => next_pending_r_reg_0,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]_rep\ => \state_reg[1]_rep_0\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_1\(0) => \state_reg[1]_rep_2\(0),
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_second_len_r_reg[2]\(1 downto 0) => \wrap_second_len_r_reg[2]\(1 downto 0),
\wrap_second_len_r_reg[2]_0\(1 downto 0) => \wrap_second_len_r_reg[2]_0\(1 downto 0),
\wrap_second_len_r_reg[3]\ => \wrap_second_len_r_reg[3]\
);
\gen_simple_aw.aw_pipe\: entity work.led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(54 downto 0) => Q(54 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => \gen_simple_aw.aw_pipe_n_91\,
\aresetn_d_reg[1]_inv_0\ => \gen_simple_ar.ar_pipe_n_2\,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
axaddr_offset(1) => axaddr_offset(2),
axaddr_offset(0) => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[3]\ => axaddr_offset(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => \gen_simple_aw.aw_pipe_n_1\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
wrap_second_len(2 downto 1) => wrap_second_len(3 downto 2),
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[1]\ => wrap_second_len(1),
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0)
);
\gen_simple_b.b_pipe\: entity work.\led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \gen_simple_ar.ar_pipe_n_2\,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
shandshake => shandshake,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
\gen_simple_r.r_pipe\: entity work.\led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \gen_simple_ar.ar_pipe_n_2\,
\cnt_read_reg[0]_rep__1\ => \cnt_read_reg[0]_rep__1\,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel is
port (
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
axaddr_offset : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
r_push : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 30 downto 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel is
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_11 : STD_LOGIC;
signal ar_cmd_fsm_0_n_14 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_18 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_4 : STD_LOGIC;
signal ar_cmd_fsm_0_n_5 : STD_LOGIC;
signal ar_cmd_fsm_0_n_6 : STD_LOGIC;
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_4 : STD_LOGIC;
signal cmd_translator_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wrap_next_pending : STD_LOGIC;
begin
axaddr_offset(0) <= \^axaddr_offset\(0);
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push <= \^r_push\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
ar_cmd_fsm_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm
port map (
D(2) => ar_cmd_fsm_0_n_3,
D(1) => ar_cmd_fsm_0_n_4,
D(0) => ar_cmd_fsm_0_n_5,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => state(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[0]\(0) => \^axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(1) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axlen_cnt_reg[3]\ => cmd_translator_0_n_6,
\axlen_cnt_reg[4]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[6]\ => cmd_translator_0_n_5,
\axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[35]_0\ => \m_payload_i_reg[35]_0\,
\m_payload_i_reg[3]\ => \m_payload_i_reg[3]\,
\m_payload_i_reg[44]\(1 downto 0) => Q(16 downto 15),
\m_payload_i_reg[44]_0\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(1 downto 0) => \m_payload_i_reg[47]_0\(2 downto 1),
m_valid_i0 => m_valid_i0,
next_pending_r_reg => cmd_translator_0_n_1,
r_push_r_reg => \^r_push\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_11,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_14,
s_axburst_eq1_reg_0 => cmd_translator_0_n_8,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => s_ready_i_reg,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_17,
sel_first_reg_0 => ar_cmd_fsm_0_n_18,
sel_first_reg_1 => cmd_translator_0_n_4,
sel_first_reg_2 => cmd_translator_0_n_2,
si_rs_arvalid => si_rs_arvalid,
\wrap_cnt_r_reg[0]\ => ar_cmd_fsm_0_n_6,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[2]\(1 downto 0) => D(1 downto 0),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len\(3),
\wrap_second_len_r_reg[3]\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(1) => \wrap_cmd_0/wrap_second_len_r\(3),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(0)
);
cmd_translator_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1
port map (
D(3 downto 1) => \m_payload_i_reg[47]_0\(2 downto 0),
D(0) => \^axaddr_offset\(0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(18 downto 0) => Q(18 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_offset_r_reg[3]\(3 downto 1) => \^axaddr_offset_r_reg[3]\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_offset_r_reg[3]_0\ => ar_cmd_fsm_0_n_6,
\axlen_cnt_reg[0]\ => cmd_translator_0_n_5,
\axlen_cnt_reg[0]_0\ => cmd_translator_0_n_6,
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_11,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_14,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_1,
r_rlast => r_rlast,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_4,
sel_first_reg_2 => ar_cmd_fsm_0_n_18,
sel_first_reg_3 => ar_cmd_fsm_0_n_17,
sel_first_reg_4(0) => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => cmd_translator_0_n_8,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]\ => ar_cmd_fsm_0_n_0,
\state_reg[1]_0\(1 downto 0) => state(1 downto 0),
\state_reg[1]_rep\ => \^r_push\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3) => \wrap_cmd_0/wrap_second_len_r\(3),
\wrap_second_len_r_reg[3]\(2 downto 1) => \wrap_second_len_r_reg[2]\(1 downto 0),
\wrap_second_len_r_reg[3]\(0) => \wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(3) => \wrap_cmd_0/wrap_second_len\(3),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_4,
\wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_5
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(19),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(29),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(30),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(20),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(21),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(22),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(23),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(25),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(26),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(27),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(28),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\m_payload_i_reg[61]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_10 : STD_LOGIC;
signal aw_cmd_fsm_0_n_11 : STD_LOGIC;
signal aw_cmd_fsm_0_n_12 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal aw_cmd_fsm_0_n_5 : STD_LOGIC;
signal aw_cmd_fsm_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_7 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal sel_first : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC;
signal wrap_next_pending : STD_LOGIC;
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\wrap_boundary_axaddr_r_reg[0]\ <= \^wrap_boundary_axaddr_r_reg[0]\;
aw_cmd_fsm_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm
port map (
E(0) => aw_cmd_fsm_0_n_0,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axlen_cnt_reg[0]\ => aw_cmd_fsm_0_n_3,
\axlen_cnt_reg[1]\ => cmd_translator_0_n_7,
\axlen_cnt_reg[6]\ => cmd_translator_0_n_5,
\axlen_cnt_reg[7]\ => aw_cmd_fsm_0_n_5,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0_0\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[39]\(0) => \m_payload_i_reg[61]\(15),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_6,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_10,
s_axburst_eq1_reg_0 => cmd_translator_0_n_6,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_11,
sel_first_reg_0 => aw_cmd_fsm_0_n_12,
sel_first_reg_1 => cmd_translator_0_n_2,
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[0]\(0) => \^wrap_boundary_axaddr_r_reg[0]\,
wrap_next_pending => wrap_next_pending
);
cmd_translator_0: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[0]\,
Q(1 downto 0) => \^q\(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axlen_cnt_reg[0]\ => cmd_translator_0_n_5,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_6,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_10,
\m_payload_i_reg[46]\(18 downto 0) => \m_payload_i_reg[61]\(18 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_7,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_12,
sel_first_reg_2 => aw_cmd_fsm_0_n_11,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_6,
\state_reg[0]_rep_0\ => aw_cmd_fsm_0_n_5,
\state_reg[1]_rep\ => aw_cmd_fsm_0_n_3,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(20),
Q => \in\(4),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(21),
Q => \in\(5),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(22),
Q => \in\(6),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(23),
Q => \in\(7),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(29),
Q => \in\(13),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(19),
Q => \in\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s is
signal \RD.ar_channel_0_n_0\ : STD_LOGIC;
signal \RD.ar_channel_0_n_38\ : STD_LOGIC;
signal \RD.ar_channel_0_n_39\ : STD_LOGIC;
signal \RD.ar_channel_0_n_40\ : STD_LOGIC;
signal \RD.ar_channel_0_n_41\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_1\ : STD_LOGIC;
signal SI_REG_n_10 : STD_LOGIC;
signal SI_REG_n_103 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_153 : STD_LOGIC;
signal SI_REG_n_154 : STD_LOGIC;
signal SI_REG_n_161 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_168 : STD_LOGIC;
signal SI_REG_n_169 : STD_LOGIC;
signal SI_REG_n_170 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_172 : STD_LOGIC;
signal SI_REG_n_173 : STD_LOGIC;
signal SI_REG_n_174 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_45 : STD_LOGIC;
signal SI_REG_n_83 : STD_LOGIC;
signal SI_REG_n_84 : STD_LOGIC;
signal SI_REG_n_85 : STD_LOGIC;
signal SI_REG_n_86 : STD_LOGIC;
signal \WR.aw_channel_0_n_2\ : STD_LOGIC;
signal \WR.aw_channel_0_n_42\ : STD_LOGIC;
signal \WR.aw_channel_0_n_43\ : STD_LOGIC;
signal \WR.aw_channel_0_n_44\ : STD_LOGIC;
signal \WR.aw_channel_0_n_45\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \WR.b_channel_0_n_3\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_simple_ar.ar_pipe/m_valid_i0\ : STD_LOGIC;
signal \gen_simple_ar.ar_pipe/p_1_in\ : STD_LOGIC;
signal \gen_simple_aw.aw_pipe/p_1_in\ : STD_LOGIC;
signal r_push : STD_LOGIC;
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 2 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
s_axi_arready <= \^s_axi_arready\;
\RD.ar_channel_0\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel
port map (
D(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1),
E(0) => \gen_simple_ar.ar_pipe/p_1_in\,
O(3) => SI_REG_n_145,
O(2) => SI_REG_n_146,
O(1) => SI_REG_n_147,
O(0) => SI_REG_n_148,
Q(30 downto 19) => s_arid(11 downto 0),
Q(18 downto 16) => si_rs_arlen(2 downto 0),
Q(15) => si_rs_arburst(1),
Q(14) => SI_REG_n_103,
Q(13 downto 12) => si_rs_arsize(1 downto 0),
Q(11 downto 0) => si_rs_araddr(11 downto 0),
S(3) => \RD.ar_channel_0_n_38\,
S(2) => \RD.ar_channel_0_n_39\,
S(1) => \RD.ar_channel_0_n_40\,
S(0) => \RD.ar_channel_0_n_41\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_offset(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1),
\cnt_read_reg[1]_rep__0\ => \RD.r_channel_0_n_1\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_8\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[35]\ => SI_REG_n_161,
\m_payload_i_reg[35]_0\ => SI_REG_n_163,
\m_payload_i_reg[3]\ => SI_REG_n_173,
\m_payload_i_reg[3]_0\(3) => SI_REG_n_83,
\m_payload_i_reg[3]_0\(2) => SI_REG_n_84,
\m_payload_i_reg[3]_0\(1) => SI_REG_n_85,
\m_payload_i_reg[3]_0\(0) => SI_REG_n_86,
\m_payload_i_reg[44]\ => SI_REG_n_162,
\m_payload_i_reg[47]\ => SI_REG_n_164,
\m_payload_i_reg[47]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1),
\m_payload_i_reg[6]\(6) => SI_REG_n_166,
\m_payload_i_reg[6]\(5) => SI_REG_n_167,
\m_payload_i_reg[6]\(4) => SI_REG_n_168,
\m_payload_i_reg[6]\(3) => SI_REG_n_169,
\m_payload_i_reg[6]\(2) => SI_REG_n_170,
\m_payload_i_reg[6]\(1) => SI_REG_n_171,
\m_payload_i_reg[6]\(0) => SI_REG_n_172,
\m_payload_i_reg[7]\(3) => SI_REG_n_141,
\m_payload_i_reg[7]\(2) => SI_REG_n_142,
\m_payload_i_reg[7]\(1) => SI_REG_n_143,
\m_payload_i_reg[7]\(0) => SI_REG_n_144,
m_valid_i0 => \gen_simple_ar.ar_pipe/m_valid_i0\,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push => r_push,
r_rlast => r_rlast,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => \^s_axi_arready\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\,
\wrap_second_len_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 1)
);
\RD.r_channel_0\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_0\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_push => r_push,
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_165,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_1\
);
SI_REG: entity work.led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice
port map (
D(3 downto 2) => wrap_cnt(3 downto 2),
D(1) => SI_REG_n_10,
D(0) => wrap_cnt(0),
E(0) => \gen_simple_aw.aw_pipe/p_1_in\,
O(3) => SI_REG_n_145,
O(2) => SI_REG_n_146,
O(1) => SI_REG_n_147,
O(0) => SI_REG_n_148,
Q(54 downto 43) => s_awid(11 downto 0),
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_45,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_42\,
S(2) => \WR.aw_channel_0_n_43\,
S(1) => \WR.aw_channel_0_n_44\,
S(0) => \WR.aw_channel_0_n_45\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[3]\(3) => SI_REG_n_83,
\axaddr_incr_reg[3]\(2) => SI_REG_n_84,
\axaddr_incr_reg[3]\(1) => SI_REG_n_85,
\axaddr_incr_reg[3]\(0) => SI_REG_n_86,
\axaddr_incr_reg[7]\(3) => SI_REG_n_141,
\axaddr_incr_reg[7]\(2) => SI_REG_n_142,
\axaddr_incr_reg[7]\(1) => SI_REG_n_143,
\axaddr_incr_reg[7]\(0) => SI_REG_n_144,
axaddr_offset(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0),
axaddr_offset_0(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[0]\ => SI_REG_n_173,
\axaddr_offset_r_reg[1]\ => SI_REG_n_161,
\axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1),
\axlen_cnt_reg[3]\ => SI_REG_n_153,
\axlen_cnt_reg[3]_0\ => SI_REG_n_164,
b_push => b_push,
\cnt_read_reg[0]_rep__1\ => SI_REG_n_165,
\cnt_read_reg[3]_rep__0\ => \RD.r_channel_0_n_0\,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_38\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_39\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_40\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_41\,
m_valid_i0 => \gen_simple_ar.ar_pipe/m_valid_i0\,
next_pending_r_reg => SI_REG_n_154,
next_pending_r_reg_0 => SI_REG_n_162,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(53 downto 42) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(41 downto 39) => si_rs_arlen(2 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_103,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => \^s_axi_arready\,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
shandshake => shandshake,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_2\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_0\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\(0) => \gen_simple_ar.ar_pipe/p_1_in\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_166,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_167,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_168,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_169,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_170,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_171,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_172,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_174,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_175,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_176,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_177,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_178,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_179,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_180,
wrap_second_len(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0),
\wrap_second_len_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1),
\wrap_second_len_r_reg[2]_0\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 1),
\wrap_second_len_r_reg[3]\ => SI_REG_n_163,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0)
);
\WR.aw_channel_0\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel
port map (
D(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0),
E(0) => \gen_simple_aw.aw_pipe/p_1_in\,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_42\,
S(2) => \WR.aw_channel_0_n_43\,
S(1) => \WR.aw_channel_0_n_44\,
S(0) => \WR.aw_channel_0_n_45\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_3\,
\cnt_read_reg[1]_rep__0_0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[46]\ => SI_REG_n_154,
\m_payload_i_reg[47]\ => SI_REG_n_153,
\m_payload_i_reg[61]\(31 downto 20) => s_awid(11 downto 0),
\m_payload_i_reg[61]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[61]\(15) => si_rs_awburst(1),
\m_payload_i_reg[61]\(14) => SI_REG_n_45,
\m_payload_i_reg[61]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[61]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\(6) => SI_REG_n_174,
\m_payload_i_reg[6]\(5) => SI_REG_n_175,
\m_payload_i_reg[6]\(4) => SI_REG_n_176,
\m_payload_i_reg[6]\(3) => SI_REG_n_177,
\m_payload_i_reg[6]\(2) => SI_REG_n_178,
\m_payload_i_reg[6]\(1) => SI_REG_n_179,
\m_payload_i_reg[6]\(0) => SI_REG_n_180,
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[0]\ => \WR.aw_channel_0_n_2\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(1) => SI_REG_n_10,
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
shandshake => shandshake,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
\state_reg[0]_rep\ => \WR.b_channel_0_n_3\
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b10";
end led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter;
architecture STRUCTURE of led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of led_controller_design_auto_pc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of led_controller_design_auto_pc_0 : entity is "led_controller_design_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of led_controller_design_auto_pc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of led_controller_design_auto_pc_0 : entity is "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3";
end led_controller_design_auto_pc_0;
architecture STRUCTURE of led_controller_design_auto_pc_0 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID";
attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS";
attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID";
attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS";
attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID";
attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID";
attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID";
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
inst: entity work.led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-3/src/prim/NOR2.vhd | 1 | 185 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOR2 is port(
a,b: in std_logic;
z: out std_logic
);
end NOR2;
--
architecture NOR2 of NOR2 is
begin
z <= not (a or b);
end NOR2; | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/vhdl/convolve_kernel_fcud.vhd | 2 | 3077 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 2;
NUM_STAGE : integer := 4;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_2_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_2_max_dsp_32_u : component convolve_kernel_ap_fmul_2_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_1/zqynq_lab_1_design_axi_gpio_1_1_sim_netlist.vhdl | 1 | 111722 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:00:33 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_1/zqynq_lab_1_design_axi_gpio_1_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_gpio_1_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_1_address_decoder is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[4]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_1_address_decoder : entity is "address_decoder";
end zqynq_lab_1_design_axi_gpio_1_1_address_decoder;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_1_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC;
signal \^not_dual.gpio_data_out_reg[4]\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[0]\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in_0 : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of intr2bus_rdack_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of intr2bus_wrack_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[4]\ <= \^not_dual.gpio_data_out_reg[4]\;
\ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\;
\ip_irpt_enable_reg_reg[0]\ <= \^ip_irpt_enable_reg_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => start2,
I2 => \^ip_irpt_enable_reg_reg[0]\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ip_irpt_enable_reg_reg[0]\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_9_out,
Q => p_10_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_8_out,
Q => p_9_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_7_out,
Q => \^ip2bus_data_i_d1_reg[0]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_6_out,
Q => p_7_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_5_out,
Q => p_6_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_4_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_4_out,
Q => p_5_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_4_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_3_in_0,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\,
Q => p_2_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_arready\,
I2 => \^s_axi_wready\,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_15_out,
Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_16_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_14_out,
Q => p_15_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_13_out,
Q => p_14_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_12_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_12_out,
Q => p_13_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_11_out,
Q => p_12_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_10_out,
Q => p_11_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_rd_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FE0000"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => ip2Bus_RdAck_intr_reg_hole_d1,
I4 => \^ip_irpt_enable_reg_reg[0]\,
O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_wr_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_2_in,
I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
I3 => p_14_in,
I4 => p_15_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_12_in,
I1 => p_13_in,
I2 => p_10_in,
I3 => p_11_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_5_in,
I1 => p_7_in,
I2 => p_3_in_0,
I3 => p_4_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => ip2Bus_WrAck_intr_reg_hole_d1,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(4),
I3 => \bus2ip_addr_i_reg[8]\(5),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => pselect_hit_i_1
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => pselect_hit_i_1,
Q => \^not_dual.gpio_data_out_reg[4]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(4),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => GPIO_DBus_i(0)
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^not_dual.gpio_data_out_reg[4]\,
I1 => GPIO_xferAck_i,
I2 => bus2ip_rnw_i_reg,
I3 => gpio_xferAck_Reg,
O => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[4]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[4]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => \Not_Dual.gpio_Data_Out_reg[0]\(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(9),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(4),
O => D(4)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(8),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(3),
O => D(3)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(7),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(2),
O => D(2)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(6),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(1),
O => D(1)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(5),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[4]\,
I3 => s_axi_wdata(0),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF01000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[4]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => E(0)
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"44444440"
)
port map (
I0 => irpt_rdack_d1,
I1 => \^ip_irpt_enable_reg_reg[0]\,
I2 => p_9_in,
I3 => \^ip2bus_data_i_d1_reg[0]\,
I4 => p_6_in,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => p_0_in(0),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_6_in,
I4 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEAAAAFAAAAAAA"
)
port map (
I0 => ip2bus_data(0),
I1 => p_3_in(0),
I2 => p_1_in(0),
I3 => p_6_in,
I4 => \^ip_irpt_enable_reg_reg[0]\,
I5 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(0)
);
\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_6_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_1_in(0),
O => \ip_irpt_enable_reg_reg[0]_0\
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(9),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_0_in(0),
O => ipif_glbl_irpt_enable_reg_reg
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_wrack
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_1_cdc_sync is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
scndry_vect_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_1_cdc_sync : entity is "cdc_sync";
end zqynq_lab_1_design_axi_gpio_1_1_cdc_sync;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_1_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
scndry_vect_out(4 downto 0) <= \^scndry_vect_out\(4 downto 0);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => \^scndry_vect_out\(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => \^scndry_vect_out\(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => \^scndry_vect_out\(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => \^scndry_vect_out\(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => \^scndry_vect_out\(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => \^scndry_vect_out\(4),
O => D(4)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => \^scndry_vect_out\(3),
O => D(3)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => \^scndry_vect_out\(2),
O => D(2)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => \^scndry_vect_out\(1),
O => D(1)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => \^scndry_vect_out\(0),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_1_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
p_3_in : out STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
IP2INTC_Irpt_i : out STD_LOGIC;
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
GPIO_intr : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC;
p_8_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_1_interrupt_control : entity is "interrupt_control";
end zqynq_lab_1_design_axi_gpio_1_1_interrupt_control;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_1_interrupt_control is
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ : STD_LOGIC;
signal intr2bus_rdack : STD_LOGIC;
signal intr2bus_wrack : STD_LOGIC;
signal irpt_dly1 : STD_LOGIC;
signal irpt_dly2 : STD_LOGIC;
signal \^irpt_wrack_d1\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_3_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
irpt_wrack_d1 <= \^irpt_wrack_d1\;
p_0_in(0) <= \^p_0_in\(0);
p_1_in(0) <= \^p_1_in\(0);
p_3_in(0) <= \^p_3_in\(0);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_intr,
Q => irpt_dly1,
S => bus2ip_reset
);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_dly1,
Q => irpt_dly2,
S => bus2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F4F44FF4F4F4"
)
port map (
I0 => irpt_dly2,
I1 => irpt_dly1,
I2 => \^p_3_in\(0),
I3 => p_8_in,
I4 => s_axi_wdata(0),
I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^irpt_wrack_d1\,
I1 => Bus_RNW_reg,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
Q => \^p_3_in\(0),
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^p_3_in\(0),
I1 => \^p_1_in\(0),
I2 => \^p_0_in\(0),
O => IP2INTC_Irpt_i
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => intr2bus_rdack,
R => bus2ip_reset
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr2bus_wrack,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => ip2Bus_RdAck_intr_reg_hole,
I1 => intr2bus_rdack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole,
I1 => intr2bus_wrack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_wrack_i
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\,
Q => \^p_1_in\(0),
R => bus2ip_reset
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\,
Q => \^p_0_in\(0),
R => bus2ip_reset
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => bus2ip_reset
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => \^irpt_wrack_d1\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_1_GPIO_Core is
port (
ip2bus_data : out STD_LOGIC_VECTOR ( 4 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
GPIO_intr : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[4]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[3]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[2]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[1]_0\ : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_reset : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_1_GPIO_Core : entity is "GPIO_Core";
end zqynq_lab_1_design_axi_gpio_1_1_GPIO_Core;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_1_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 4 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 4 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal or_ints : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
Q(4 downto 0) <= \^q\(4 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus_i(0),
Q => ip2bus_data(4),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[1]_0\,
Q => ip2bus_data(3),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[2]_0\,
Q => ip2bus_data(2),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[3]_0\,
Q => ip2bus_data(1),
R => Read_Reg_Rst
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[4]_0\,
Q => ip2bus_data(0),
R => Read_Reg_Rst
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => or_ints,
Q => GPIO_intr,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(0),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(1),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(2),
Q => p_1_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(3),
Q => p_2_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(4),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4]\,
R => bus2ip_reset
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.zqynq_lab_1_design_axi_gpio_1_1_cdc_sync
port map (
D(4) => gpio_data_in_xor(0),
D(3) => gpio_data_in_xor(1),
D(2) => gpio_data_in_xor(2),
D(1) => gpio_data_in_xor(3),
D(0) => gpio_data_in_xor(4),
Q(4 downto 0) => \^q\(4 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(4) => gpio_io_i_d2(0),
scndry_vect_out(3) => gpio_io_i_d2(1),
scndry_vect_out(2) => gpio_io_i_d2(2),
scndry_vect_out(1) => gpio_io_i_d2(3),
scndry_vect_out(0) => gpio_io_i_d2(4)
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \^q\(4),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \^q\(3),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \^q\(2),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \^q\(1),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => \^q\(0),
R => '0'
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => gpio_io_o(4),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => gpio_io_o(3),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => gpio_io_o(2),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => gpio_io_o(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => gpio_io_o(0),
R => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(4),
Q => gpio_io_t(4),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(3),
Q => gpio_io_t(3),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(2),
Q => gpio_io_t(2),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(1),
Q => gpio_io_t(1),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(0),
Q => gpio_io_t(0),
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => \^gpio_xferack_reg\,
I1 => \^gpio_xferack_i\,
I2 => bus2ip_cs(0),
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
or_reduce: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_1_in,
I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4]\,
I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
I3 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
I4 => p_2_in,
O => or_ints
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_1_slave_attachment is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[4]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 5 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_1_slave_attachment : entity is "slave_attachment";
end zqynq_lab_1_design_axi_gpio_1_1_slave_attachment;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_1_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_oe_reg[0]\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair4";
begin
\Not_Dual.gpio_OE_reg[0]\ <= \^not_dual.gpio_oe_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.zqynq_lab_1_design_axi_gpio_1_1_address_decoder
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_In_reg[0]\(4 downto 0) => Q(4 downto 0),
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[4]\ => \Not_Dual.gpio_Data_Out_reg[4]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1),
\bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2),
\bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3),
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg => \^not_dual.gpio_oe_reg[0]\,
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(1 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]_0\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \p_1_in__0\(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \p_1_in__0\(3)
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \p_1_in__0\(4)
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(3),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(3),
O => \p_1_in__0\(5)
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(4),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(4),
O => \p_1_in__0\(6)
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(5),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(5),
O => \p_1_in__0\(7)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(6),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(6),
O => \p_1_in__0\(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(2),
Q => bus2ip_addr(6),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(3),
Q => bus2ip_addr(5),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(4),
Q => bus2ip_addr(4),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(5),
Q => bus2ip_addr(3),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(6),
Q => bus2ip_addr(2),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(7),
Q => bus2ip_addr(1),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(8),
Q => bus2ip_addr(0),
R => bus2ip_reset
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_oe_reg[0]\,
R => bus2ip_reset
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => bus2ip_reset
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => bus2ip_reset
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => bus2ip_reset
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(0),
Q => s_axi_rdata(0),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(1),
Q => s_axi_rdata(1),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(2),
Q => s_axi_rdata(2),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(5),
Q => s_axi_rdata(5),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(3),
Q => s_axi_rdata(3),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(4),
Q => s_axi_rdata(4),
R => bus2ip_reset
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => bus2ip_reset
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => bus2ip_reset
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \p_0_out__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \p_0_out__0\(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(0),
Q => state(0),
R => bus2ip_reset
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(1),
Q => state(1),
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_1_axi_lite_ipif is
port (
p_8_in : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 5 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_1_axi_lite_ipif : entity is "axi_lite_ipif";
end zqynq_lab_1_design_axi_gpio_1_1_axi_lite_ipif;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_1_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.zqynq_lab_1_design_axi_gpio_1_1_slave_attachment
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[4]\ => bus2ip_cs(0),
\Not_Dual.gpio_OE_reg[0]\ => bus2ip_rnw,
Q(4 downto 0) => Q(4 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_reset => bus2ip_reset,
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => p_8_in,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]\(1 downto 0),
\ip2bus_data_i_D1_reg[0]_1\(5 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(5 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => Bus_RNW_reg,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(5 downto 0) => s_axi_rdata(5 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_1_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio : entity is "LOGICORE";
end zqynq_lab_1_design_axi_gpio_1_1_axi_gpio;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_1_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_19 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 4 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 27 to 27 );
signal GPIO_intr : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal IP2INTC_Irpt_i : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC;
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_reset_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 4 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal interrupt_wrce_strb : STD_LOGIC;
signal intr2bus_rdack0 : STD_LOGIC;
signal intr_rd_ce_or_reduce : STD_LOGIC;
signal intr_wr_ce_or_reduce : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 27 to 31 );
signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal irpt_rdack : STD_LOGIC;
signal irpt_rdack_d1 : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 31 to 31 );
signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_3_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
gpio_io_t(4 downto 0) <= \^gpio_io_t\(4 downto 0);
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4 downto 0) <= \^s_axi_rdata\(4 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.zqynq_lab_1_design_axi_gpio_1_1_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(4) => DBus_Reg(0),
D(3) => DBus_Reg(1),
D(2) => DBus_Reg(2),
D(1) => DBus_Reg(3),
D(0) => DBus_Reg(4),
E(0) => AXI_LITE_IPIF_I_n_18,
GPIO_DBus_i(0) => GPIO_DBus_i(27),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_27,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_16,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_15,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_14,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_13,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_19,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(31),
\ip2bus_data_i_D1_reg[0]\(1) => p_0_out(0),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i(31),
\ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => AXI_LITE_IPIF_I_n_31,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_32,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(5) => \^s_axi_rdata\(31),
s_axi_rdata(4 downto 0) => \^s_axi_rdata\(4 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(9 downto 5) => s_axi_wdata(31 downto 27),
s_axi_wdata(4 downto 0) => s_axi_wdata(4 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.zqynq_lab_1_design_axi_gpio_1_1_interrupt_control
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_32,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ => AXI_LITE_IPIF_I_n_31,
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
IP2INTC_Irpt_i => IP2INTC_Irpt_i,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(0) => s_axi_wdata(0)
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_27,
Q => ip2Bus_RdAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_wr_ce_or_reduce,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_29,
Q => ip2Bus_WrAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2INTC_Irpt_i,
Q => ip2intc_irpt,
R => bus2ip_reset
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
bus2ip_reset_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => bus2ip_reset_i_1_n_0
);
bus2ip_reset_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset_i_1_n_0,
Q => bus2ip_reset,
R => '0'
);
gpio_core_1: entity work.zqynq_lab_1_design_axi_gpio_1_1_GPIO_Core
port map (
D(4) => DBus_Reg(0),
D(3) => DBus_Reg(1),
D(2) => DBus_Reg(2),
D(1) => DBus_Reg(3),
D(0) => DBus_Reg(4),
E(0) => AXI_LITE_IPIF_I_n_19,
GPIO_DBus_i(0) => GPIO_DBus_i(27),
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.gpio_OE_reg[1]_0\ => AXI_LITE_IPIF_I_n_16,
\Not_Dual.gpio_OE_reg[2]_0\ => AXI_LITE_IPIF_I_n_15,
\Not_Dual.gpio_OE_reg[3]_0\ => AXI_LITE_IPIF_I_n_14,
\Not_Dual.gpio_OE_reg[4]_0\ => AXI_LITE_IPIF_I_n_13,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_18,
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => gpio_io_o(4 downto 0),
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_data(4) => ip2bus_data(27),
ip2bus_data(3) => ip2bus_data(28),
ip2bus_data(2) => ip2bus_data(29),
ip2bus_data(1) => ip2bus_data(30),
ip2bus_data(0) => ip2bus_data(31),
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_i(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_gpio_1_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_axi_gpio_1_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_gpio_1_1 : entity is "zqynq_lab_1_design_axi_gpio_1_1,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_gpio_1_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zqynq_lab_1_design_axi_gpio_1_1 : entity is "axi_gpio,Vivado 2017.2";
end zqynq_lab_1_design_axi_gpio_1_1;
architecture STRUCTURE of zqynq_lab_1_design_axi_gpio_1_1 is
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.zqynq_lab_1_design_axi_gpio_1_1_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => NLW_U0_gpio_io_o_UNCONNECTED(4 downto 0),
gpio_io_t(4 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(4 downto 0),
ip2intc_irpt => ip2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/ip/tmp.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 7 | 143167 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
kdw3Vk4SOMoCuhX9g3/ccpT4TG0Kx0+Lbjz4qUWScnsJe0pdtdmxrME5Nsb8sE1MVjZWu5rwZGxv
uRGERi4QRg==
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Lxs6dW5fuHCnLmisK0WT59aUB8tGqhtuJ1xtmFDLVXwkjD6cKNIbwoX8pftRFPWeW5BswTuRjVPP
tKsQRaHNTUSAxitJ1kJLc2uxvRepOce/EXFKJ+Wmu0MziyRh/TnrAFDSEMQdTqa9wBlUcITaYJ6h
O4cFL9fSmjAZsSdonV8=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
sIyR1qa4vHgif+HpOh9onOtHJCFz724zs5gOybIbz4XUHEG6XcrqF1haRr7D0reXGkDMwfB398ee
pyZkN6MtJZePhIt/xlUbD13EB6Jl6f0AAYJBHbCB3TkU13U6YfCa0mAilrrIOQn1wVCli2CGy5qV
SEEqEKdXfQoeZMNe5MTv/ahWj2T2kSxWXHKGJExcU2DUWb1Lu7XeNsOGMOz+cOb6BTaNOG1TkLqt
S2594DseSvSk5+5fh2bxWtfM7yLtW896tLcZnwnnNdBrf8AdiFhoItT02vObxx+9S8SLxsa+DRUX
T6lpnvQIDw54Ayr89tkNKdqlDO1yQ7A1SXDDbw==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aNEFgIRhwky7UIabl937yVIGme1rC140V0a/LEVtbNv7pbFAcDuP8FCtJrlBW7vqgzeY1xs8Yw7h
xfsEOz4yTJkIQHY6I/JL8PDVBFYkNJ8BHkPTigSPl+ldRIHKiuIMVRBoExu+sK9WVZiMOMsoWxCn
DNyfsAvKHM+HAa9GS2MuZVLQz3QRWxHK7FmN/Ib8Ann4NTP+IR4iyjEHMys9UgaYeCHNTwHl38ZO
viKTWzt4R1rKS9eju37o8hOeuoUYVXAH2Py9R5NvY8Qil9+aVDaBnaHu5+2Cu3TWUYl75usavbdK
oUDYWDBECZkuiXD8oCLNMCNPaihrqQ6cxp5lig==
`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
B+D066MY7A+yxI9Yi3HU1Mqtl7FkVBTfMsPitQ31YQJdBPTdOKpeiWINEcxi37H+PGEl/wTH7elk
wVIulrV1uzewAtZZNUG/L6YUquAOvaQ8Nija+B1oM4aXgJP4rYZd9p1NzF1vsnrKszqsO7rNZIeX
vmM1FF7L4UBDGOxv+fiva2WDaq3kEUyk7z9HZANP/Wi2Pvp5NHqw0sa/zDYl9zpr2KdWB982QGd6
7DtGrVg38KIeYIVKAoW7pZAIpPdgIsYDGkbfVsphNTPFfM1fPQowHkXLGz++mePZxzjiZ7WDf6FX
gAQWpakdHMoTLYq5Oya9JKA4KojQ2/HuRfgBXA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
C34fYGfIi1VgHnO8PuOqb7whkpaV7PPzwFfszF0kHOkXYL8ZeMU0c2RvGZ0BbKoGDM6QG7oeYcKE
JvSzehgj6xh8y3VyDmuK+7a+ZVaxJZvwsRVa11irLDWnRsYMXCTIk+T6TO0pWKmfQ5nud5ugDBoM
kyY1ZwOqMdtCqpbSNg0=
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
r73f8Tx7qh7YAQvlkX0j7A9PltBNQjGNK/icGEEPSFMC9iu7CIR9t4L0t6u7zPfhfPQns+KIM8+F
1o1qJ4qcgLlOIVOl2/oRhVgcxqHQOyR2lq9EPKGpNEDLgzY1l0psSzo4dMXmaPNkguDaN89IBwIR
69Mg0J7pIzqwhz5tUue2qxD9JTDbSCAkrWmUCuQGUdgFEIWhpamWbwgTSMGiwseWVHtyYG+vkR1a
tqDvi3mMyrSebPCsxM9+78ozZV6qSMWBFaGxRXbID74JNjk7d7rU/RVU0mxRvK/Ac0FZB6R5uDud
YLJedvJrLpHbrH/Y/tMyqxK9z06eF1wZWE0fig==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103440)
`protect data_block
FF9Qnq8Gaci+3FtTM9E5GbyvEaIThd1oSpqhiBT4jf2zueQhdrNGJBmvOqSh4Dlx/44DWBd60MoU
KS1hiVSeroFQO+tzmSOHd5Hrl8uAOaEoXLrsB50uXwqb4Qkw/HFd24dWqqXUR7Lzz9a3sX1TBwhY
mluXo5bEM3Qx6SV7Bzp54nWFbEiitX9W+948L++htMImFaBT+/3Q22tIegUTqmDeVRUmM1FZR8sJ
y7wUIwBCAuu77LpEsN/3cZ7Z6rCGVEk1Q1uhkitXOW1khmXg+4vLlJuaeTpfffXQ4A9Z4I0rg1Pk
036zyqqsVcnp4CpzhdNzAPajVlBcax0kan9How6rjPMqy4AD68k9oHHM2x4zoHdA0BesGucyqmUY
Nt0sxWcDtbNlFKTpxtuRA4ZdyvNpkY665N0KoQi+gLOanjwjgWUh6SboHMGj6lDojvhd6jYVlyCl
joeanOdFant/0wu2NT3VGtyREXJhxIs4Gpfr53Zs5kXJw19nHlEwHFDLGxHy+nlvepirNjmj0GYJ
pf9UkkVoUrwLnmyLsyZPJ0G2ggF8kDc5p3x8d6oQZtNc32vqKPF3y4IzyvRcBWTcEgteZ8Dd63Q8
9hmjriSx51WOFt0qi/GEWGgfzRxO5sp6Z4deQTgOtt846VM5i1+/U4N9hasj06nPYYsgvDPjHoLq
m6AJBuKGaLHjyym9YY226qp9lPfZwnmMsEtqiqj50bYmIaMaRzeP1ihOJVn0vPo0/XZf+LRRxHcv
GWaMFtiYDzqfM6qrjYeg8TiakGM2XJvSpb+SFDaDAvyntp7/qxS0N1paLea9ARVEYE0rgCsg015h
LF5fSnYN2OQREzR/7jPWohDc15rJo72ZyDG+6GSnJRZVYal8Bc4T9ZjMFKhnTy4hypPYfWTSXJS8
/qyxZd6dgi4UO48BHuZqMyvvLtFVKy6imL/M2+nwTEKA1ESi+Xi6tdjqygQIYVm2LZVMcaoX2SYo
OzU/c1tML1U7VqyLFtAq8YOg31mtSp0wUIFkoh1VgMR0kQqcBcX23vg/uRaVKosem5THgtgJK7NC
AoO8QvlaKmzqVY+/9QumggS+2VWG8gWIeeGNhNV8LMBrObxkf66nLmGtrW8nsVBmbajqKt8KkAGW
xECk772v+gKG8KRuBKc73fC1c8gvhgU/opR+QsaxjasTFWY9gai50Mnpg6pDcCDOU16UQWdoMzaI
meIUO4C3soyGUtfgEebcDR//3G5db+bSP61j9W0T8QFuXzGv2zaIIjaiix3Adf0Ibw3fWCtCWKL4
GNJywTLXJPH05zXV0RyT97ivHWO2msqxFcpoe9pD1O7AHwJTAVIQx59lClLUGN4e9GCy3XtOSggU
r9wgWXAWzmZxsXlH2yo/Nv/YFauKO8hKMPiuZ2suXWFGlXwADLYMcY5wGvSOKx2vUOob+VAGwCGR
NE6Kw8A0zDx66kTULDKD4iYHwkCIcgvJI3knGNm4cIH+ZZdLT5pJ1K66FGl9dvLA+GFutMnQ5cd7
Kh2q/I18ARkTO8ka3oV/H4o5D6z/ye0yqmsVLpfeDmQPSmWA1DUr0YeZlTzJJFEkoUpNKl8tAs+C
nzTCCeA2vZZaHQNmW3CKEKD1Nx6bHMv1QBQoJZ1TZaxwpT/6ESdaiIC74rgOAMPecuSXQ0MaiD06
WtMKbPnco0520KpwUyZTNlTyrULQI4+zLwymR5+KiGZzs68HPftq9K5/0RpJ5tOvnnYGpogPQyXR
8r5aMcE9wZwC1ZT2guMvven3ANgjzzG7ZvMIYQySQAayMrRPDtqqo0K5doktRtIDWmijkatCAyK5
KKJ31HHSLg1bNp7oC2u1MIB3mZ+SaKAHbMbdxcUTnGYvLOH/ahm0lYAKSAg61TjJHvfjQ3Ov6E8k
pgS9xrhiIimjfFtWBCc/TFYATPg/oMmnFLZUyJoxvCzRumcxVaWPePbSDd6Rdh1GA89NQxWKTleL
nzeh+YSPVpxlQYqDyylUmdFzU5JFFn4yJSTGkmFzGVn74AlR8hNEQe5LzP3dd731WnvIyHMPof3x
yKFIiCGOEzT52JumyYxThVQmO4ozbsGvtjZ9muVzSwUtZaa9CqgSIGt0gOpxYrjb+rVWJlhdNPy7
yEgeJaDzQjT7dlPIh9DmYtjzIlS+fnMhWSDqXWpkoGpHBljiLcChDVcuFPB78ClAThRuDFTus7kK
x00tQkcTT61+pztnhZfL242npG4cnt1IHYdVBv+8BgbQObi3/Pu7aOiUnujm6L5F1wY+HbUA1Udg
Bt3P/fj9OFrf8Pp7DSOdEcMdDXX3/whg5F+tO+GwhpXZJzXbum1nMoymJE7x5ScQUls85oqJm4Tv
AcBAF3slAct39IB/ioG7dM82u0Gf+wX4ptz917gj462eHxXl7cKTUjWl9NW94bkqnaztQGTfWvv3
eoVMZgFZo1wO8srnEAbBz+DTOqKlb9PRHEK8QWljZMsrs5toceNXUsDlaf7aiLnuzC6iMHYFM4iA
g/6La5PithSq5+v/tVoWrVCZNzwO8dIivJYat6ToeCh4LhNCZTG3KjSofpU4A5ftHfoMpFnLt7XX
0fyKrKX9NIft0w7G0SrrvfTM9qLSF8GzXS8Eh4RSj/uCVkqZIymZoZ/lK09CxCbcqzdylPABrlQy
HfsdfEvuhT2JPu/Qgf8M7n6LEivEHd213i0GM6ZHgUgjsflho+rYhIv/3qcrWaFB/swQ6CSAmz5e
ZcwQWAc5cPzFxSHQRVaN/VAcIgOj70GEw6aTTErReRtsk9N+m5SUWnIcA5sKTpbRx9V3n9TEGSBP
aVeEh2VO/sGJipiUe+6gjVZc4fqbGW3eeLTSEhY+G3geSUBg1AQPgvxySjAwtvQU/mEv1nAfoiqi
ONfxHSstPwEn8Sgi2Bsb9Ok8JrkCkc8IKEKiSU/LuWBOVvqxoBzWg6QFAzs3Kly7nBjW7RiT8C8H
d85o+PQ9EWVBdSfYZSr+kqrVF1lpizAa4Wnse8plIXQD6gmXusiV2tzmQkOtOBOEaW1tYRJYD6Y+
ay3Zitk+rBlDuCGge1IwUqFnBW28FfbUvWJDj/aS7OQ/CwYJufAgR8rwc/ioBFK9QIvdl8E4hYb6
c5MQoQQbakt/DfwJoIe6W1rk8GaX/VojSnDnIuuyCe06IKKQWWqd7wBO+8RzrbeImyiHKkaBDNHr
dQ5OUrcN75a9GLqrZZ+4I2Xe+GT6TZ5rDXtpPE0fJ8f6U2Fs41EjecGrXQjj5lFUV35LeQP7LHRL
hVYum3vxbVYtVWtZoPio7h4iYJNGIr94EGR/UpFLKEu2HajvPqxVnqSBLG3y/x5XCNBlVkT7C9YV
zNYn9Ec1Q3DXNguFizlmem2BbnIjeD2y0DGZS0/tEbd4UaaaMzhqweUyhZyBZ8hdR+lKdDa2RUiG
58oW9DNw456Hrj6NzmGOMU+lU8fVA9hBvKWNcWY1pG/wGF2QR2NeRAHxyfcxDZWDcVTSsNwzdWtK
kaLy8Aj9KDV/vd6A3K9r2Q8YQKMWEXLOLCbQ3x/I+ihLpkoKbz/wC9buW0EDEa6jyDl+u8DOasFx
jRZEJBkXuIuJ1B/Yp5cKQXJinwpkcPt4sd9DfF7MpHw6uupvaj0RrWS0JDwmoByhJLFXagCNfeNf
uCc2wVRLm5eOFgYC4lhNaYClRho3QaG5J97xYFSSfzb8hUepXuwZj9p6wX2FC3qZwwTzHl9x7OQy
51GPuHbCrTHKH63OxFqAb5WAYLfm67QhCgENKfmoLv6EubE/KU5OFCaznxIPq+Z88wTBMrmCqKxx
M64q2dK25LbGfMO67NCDasGAZpALlRzHlA5CKSVH6+fHDa82NY4h9yf7Ub3ah5Jx5zTaRUDmPXGw
zbJO3ZhR8nMg8bsHaVLNOENVP1bkpMmYLR3h3y3vTFa0WR9xGn+eEci6JaB8iRiaxqqhxzRCbOPq
U4LesebmD/WAenSc5/nCJSjTksWKiQWrKtK7l82xC98fwwTxW4Lpryf/mt+jbIpXYd3sXHp+Q1AA
Isq/5/Y15EvQdP2oaD2TwzpdMQba9dIkaW9xzMHBmypc0jKc4RuDxPKRjtKDkDKc9t44KilLMNee
R/Aut4rPCMZogpuLCcN1mJUvAMDoVqf8jwhLDFdz0w3z2u0D4OE6Eh5QcCHH5gmtGcsvAjNPmIfl
FCEZxr12hezNVtVUG/vRvZOk+ZzNVZF+/yzuITEXbFBYkyJyXTSWGiirSQntZl+eYhdz3T7JZrH2
zyfJwIWJ6Zmj9EFUxf/E2efKh1VYXHBL0qWbaZg8pUsFxZyKVLZD3hm9R7+mFg/ordiFTxlh+Aii
/sMAwKn2R1BNC3lTTdCsU2l8i2iIUd9uCkMyL4uyTgg29O9+Be3Z5oh1fJcYeAwlq7R4Fu0p++JL
EvdqfxrtwBUMQh/YUnVH983S4dFzFTAIC9Hw6AkJpKaQABj+SaegRRB9yo5LD95MPGkjSckNI71Z
AjFODf6qEuwU08F4cFtFVwn98IC+MXlpYa2NaMNtzo9P8OwsW8ihxM0mkkXw/0DFkamkuv/BlQcM
Vckkim4EGJzBx0YfR3QSLCxe85cmCsasBQyswut1jtrpFv1w/l8k2/yJtEsI1zCdS8RdfQ5W+Uf5
Xlwz2blSPADADd7QAzgC21+h30sN7BAAgyku8+Gt2b6ZSD3HnMuLYtUQ9+gfU5pYEdANmT8W05r7
l2ggKpk3V5kEirYFehWrbg+5muJ/zkPFlYM+zFBMW5/Kc/XDdYPtdc2ok4MD+xc80j2l9d+WqsRu
OmSymrUmUwbErFWS606lOJSHpVfnUiHZULEAl1+JGgxmaIsleL0UjpxDL719dJquwsvCSvtj/cK8
lQsxeKxUGdJ0Wt03epkVFGFEwl1ZSuCtoJKQVNPtqTaItAsej2Opf5sOD7Nx4arFXKeKkfObkjhe
hj+nzNyRBL4A3s32XO/zHwRnSev11qn5hhrweC+c4L3wng9ub0SErbO1YRM9w7IAzcf/albB0nUC
d+f+bJyaCxgd5q2cw0BpOtOeLm0JTVYLHWmeJj1q9H3+pWEOuEj84MP+iu4aj9MxmNYLFvwJtS6b
A2kW7JM7keKiKN86C04X3N+FUnCiODtKRTYEGhTkePEYhdhMbGtVr362ssDkRNd8FalLQtnzD9o5
EwnDHh9hXz5JLUJjVqXtS1rLCwMQoxObySiZmWEe6mo0OUMeVVsIQhwko/if55zJkWsBDCR99cK+
NVGHB6HjF+C+NIkinXmh2eTdvRZ+9cZE+aKLYuFcnPk+CglO422ov1Yk6YcrKtXW846ZI1050nTT
qeOXd/qtWghru/eMRlwDHkZK7ZZQJ1PcXOlV/JvzCAvMui1XVed3kqMFixZxVBnkYNVYZt3wzEOI
yRKi5cIFnUTOFEyKS0G9110RlOl35O2qmzX2By3Lkgy6hbnzfTC8aSqph3yoZ9SGB6ol54A1N029
j5Ca9G0/unhv6fsd/9adx0peFfbw5JRnFbBxJzLk5n/9YU88IxeLrQJ1t49REnZG57uSF/Jli4oy
tBxahY3laUBNw4h98X16hk2Sc67F+Q9vu57QeN7H+b0z2bBP5f+q32hyTABkOuDwo9pAihGXh3C8
nQpHOuPJfAIAg95jwhC+9L0mf0cw+mMdxf2q9r0DPpHgbGnS83sGgwZSrfdbuzNqwCMKWPwg5l4H
1kwliKmVvXkAXr5D1keHqYleUY5RpVuGeSWZ0vGlWEfNvB7sqlZidNTfKnPnHMM9uhxYCdLQL0Io
Mr6O7qH254taja/6nXo7yBMYXbdVsDLFKJdMWVtco1HeMx1Mmb9hsjcjzOrjs5oZmNhevSLzx7la
LCcE1xwEZ2qTCM7mpfoB20YZUYJLqROoxGv68m1Efo8euotTl1hgROgzHO4Fv7D0DTXe2BujO5LY
Vflntol4FVcPpgShcRGvjbwidzQQiX6gIL/ywqb3ZTSNysFiMtZV8ZPhdpcfyMNYbMzb5ix2iWWV
aNpO1JFn4+vh4PQ6ZxHArMex3/xVMQhYkRQy2vSI/Kqf+WDV7DXoiPbqrJ3AXm/sfZobloeFlDHw
23lU0MeXZqPtpbbauxGjGStHMh4czSqG0G3K2PMqKTyq6EH0FQ/JlvvJafjt3QAizukDOcthvLlD
esjyxBRe4Dmu9XQWm9YFEd5952hpV2dGvZm3d2d9aFUcUYW+NOB2UwI1oE51bY0m/ChypMnFnN1B
1QKjVg/fsXc4j3lCLAlf335Ai7nVDkwhXWaiA4zh8LkEa3P2Fz8ZUJHJlOruqq9lxd1W2OFCr3Dx
vJllD4Gs/Sr5+GYQ/gIVk7iLJlLiEUvvkU+h93ZreFbYboPHa86PVnuWSkqSZkxWMZnV+iwTe1ne
iPjB+hntGca1+kRnUAC49BcB8T9Vw/vBIuhuq7v9TILLhZbeoTW3hngtbOycxdcoI7hqGK+OKlsa
aaud2GMGFcDX7UZhQfY19ollUskRXY8Pomc9UDPPIQzaEiKMoFE4d0d4ut8UdD3zthiuOpkkXG+W
tcwNMYi3wBDZCSajyDXu6fvE9ebpVgHatFnAvIV8fL7/0vbx2keeAHPzu6Q6pbowCQPncLndEsSU
MZlIX9kK95pkCIQ6v+NfQPQvi2ATKbf5TscZvYBnSVq4tLWqi0oxVudes9/whXV6L8x/4ULF1Dtk
15ayFCjAsTShgWvsPdQHQ4gynpI0F3GPfoytdKeXc7MHiyITMW7xIXEij4KMeQQx9XQRR17q71CL
UkFzoVN4LoRemipiNoAuW5pZurQ4XChF2eUOpsTaSHaD9TaXZ2bkXacrt+ladQhbtlWMWWhAgWTi
fMBwPrNOpPS2cDwHOdIhI6KIZnUNGpiIlscJLikSAIofWQGy20mV2qkjxgVEfWrUGmUtgEonhmae
RywlnoeA7MZ3DX6FTo11Aes4DQAk2Y+sREo3HJKGfi+vMkN/10okt8U1Oo6GXlsdKSwj5KVFo3j2
i/PoYpaOzmB/A1neT3pFF8q39dcINBSBYCbgIleafNH2v7GgVv3qqRHjKICEaOV3Xn1I6kUvnUF9
X5BF5l84fv1lJgY3qTBD8RFVaplYGu73ih4cHVh6lw51wlQjZV/ETnwcybNsz26ZdbIseopHiQ1u
gtfg8d+zfDgzTqR1BBtrBJAHAAFqDFUJhrKDgDfFMmIkw2GdNWjzc5NNINl1G4U3U1XTvr1WvMeS
UOGs3aDxXLnej4vuCVsX73h9kJ92TMA7O2wkPQ2JHHfQ/y+7N+H9hWbQ+QwjxOqFLKILO3YiT/DO
OnGEbhfpkPW0wzbAuyAsK9KHS4HEa1r3cIxDsTDolBlfr5BZd40axF6MI4+Kt3s6oOE8U3bKjYEB
iKnIr0CdC4OU8naMji0CChnoo3mPVSy9NmBkIl7kBVJVJFmPNPSUxGyrodtOZkIFi+ryGANKoSMl
VvEBKV72ek5NQnCZOxC3T1g2eoftYZsVrzr43cN1HIJ4A5h02YLMWpeTMaKaALWIxWseD/EeMT5I
1a05P0vMnlpYvoCgTsVhRB/NPq6806BTOJZ3GAoMd5BFwxS6LtN4MQv0zc6167diiSY6iH1bui2p
jSBg8yTGjJMpVc0cX5CtlQRPYtgsrRjIJ7iQV0vkeYkICz8/Y4wnrJ2D3ALpBfjgvgmsME52XnDP
VmFAHuaD7vETj+7EujAO2U23DkvoWsBb0e7jvu/CVpzZzfxLCnmc7VeEY63G6KwPIbKUBhoifmvK
ppR6wufu1tgxeUmvmfAoQP/9Iqz6e2A80DLI7/Grgv0y0mfgaS2QLtK5vHGHfnDGjZ8yjqjq4/OJ
3lY+tI/mmBArmXPhMO2lw4Gupi4nJqI/Rj/+ythmecvbopX4p4f0U3hquwWMvR1hiM1hfnxCiXaK
sSvbYw3EqAfQkZ1Qu2zJE/Gt2QBa+779i8QpLLGc2gMecCQgIzEtuQaBtro/R0iN4Lcy4Ey5rkAr
eRYUwy0hnDuLbBr1xWozHZMfQVnn0B4mF2WvpXrJEDkHHVBaGzNi6o3ID9/aFzSBMlpu6mS688ft
I+uk5L+KW01DG3J6P0up+xS4KFy6EdJi6eJsKoMiJzUps65R/1fds5DoASm4Isy5nGH5ozoGsYhq
/UsX/3gBjaSnAylhSzjGyo4Ys4uNNmaq+wp/IljwCNG0K5YzdG3b0FffPf+rZ4dHqxwcgtQlhqPW
S2Xws2Rql5eUXr44+3gTESyxnr2yDwGfn7a6oMo853fhrtfMVrbYIZI5dWMfvtLP1tOuIgsRG8lL
uyGdMuD+Z5RdTD68HzNNlXgPRN9+AZBTiPaQ6hC2Xqd22kxzPucr9kH1yHa46BWjoQQbWMeGgs6R
aGyBdI3mP9a80tuDOFxIiA8Hj6TOdWCj/LwhViA9ZTGttDnV9bhLobdfy+MaxMAoqOdaTij3m0NR
pEMhWAGWv9f+UgqBnPeAGcW06Gcl0rQLZ8k6PbqqQ4h74KZ9k+PA/96KnbIDVswNHQrLs8QUA+m+
jHWv99HQLb+da7BWrgafqnDJqPumscz6GLIDfAjNbCD97cgf2SYl+m2V48xX//lL1eGCbveuxqDo
ChoDzYolLyUgC8GPOgSEtd09tI7ZkRTmiAX9f8XnkbGIhalTI9zmlXchgLcOXETHiyPIDWA0PE7f
r9jok8RibycHVsrpq4RIo7NJFgLxH0FxYh8piT8mRw83E9VIWb67YVKRxyeZBWUou6ml7EYuEvTH
wdX3Y6oBhJp9UeAc9+aAXxg2uBhIbiNWBGat9Jb4gPhnxfDJzKOq0TrPEk9w5fuJWgqKr51SKXOd
kAQh22SYUDuvO40I1N/acoTaaHxTiMX25UDNwQ8ah6Vo6/44uES4KTZ81bwPoohAxakb1HJ//3sz
EH/4lgwdv2WGBuuGYjRV63eji2PXYOrwKUw17yQulciy+aaKSylAetJbpw+BOO4C29MX+ZGfMLq6
GcIHPvOVoM0+j8duBawXgIJhFs+ltjSdtzQpXZCAXVoPzDc2HiQvlCoFcuBYtB36hmZYB3ArfUYy
dJrzFiawB4eHjG8d+2W55+ZSKzz9WwLAKu6QQgCFXh3fj5AJIgdOM5AAgBB4JiSHizTcvDY8l9Um
qJvkC1r8E17JPfH3qCntfwtq2XlUUdyafMvwXZBeQYLrGZVGMz3kEbPaVsUZoe6V1mZdmib3W47V
LlSTVx3kTnNn3COODndGT7qgBk1Yoafr8p4mkwSDDXClG6aHGpdwreoZKafrclYtgR4ipVjKeh3+
j3k4KlGmtbZMQepSyhcb0/ABofx2GK1tj44QULE8Rm93iZc4gLXHatJDHZ9SpUoo13EaRSfFECWD
7AfIVWRGMalJy1SuAmQfkBQ2jWTmM7JdkgLB91VtWL7cUSpl6ecienEOWFyhgFQYZjrIHtdX7xI8
COZqilj1A1RbZJ7eo1cKiHT2hscnKSjiEY0XFAYz/+BCJd//CIQRnYEpDG9bhxRCgEwQ/GiHs7+y
+fs2Jc1KLOhrVQYzk76S+P1ShWQBXe8Rgcd3dKQQI7vjKnDlcolssbcB7qJV3Xhgo4WFeAcgLTN1
geepECeb8T0nMi6kDOQ9uX0YSVD5wI/Zh6IMklUuf+8drdbiSGRd6WuzZvzT4npkHgb0zrFYi0rs
uPa3wJmzjFSZJK7j5URL447MtM/Pxb1HpF3OyHPPD/mwerpFRrYRCcFVXE3JEykEqEKb4XysFj6M
t9QqjKG25XcCG/9+MwuvsxXaAnsV/NNjpfpcWR6a+DHrutTm420KZV+dy2CZYsq2vltRoyp7UrUr
6TdLZKixZumU2ETN85gv6lHBoWnQC5v3rujg4Qm86PekWlac77H+LdKGZ+b7Nq6sRVmHcOxxIka3
wGthhGKDkG9KD0RWb11lDQqEeGs/gt5e7YMXER6xebxxpqhXV8ZO27UeYA1HbQX13xwRsa3jvKVd
QjzJt68cp7cuVBH9E6ChsYxmqAXd2PfGpyOTJzbUrSpsqJKvMJ3OlacfYLfi7+7IvsaXsWTDXH0l
mLr16xiHRz1/ZB6+fVIw9PLQZ/HQbR1sXuv9Z1EyUmUHpGNnmUsAgfanBNpGImIOSakH+nHnSecd
mD3YiPi5RsLAsvDrRan11zJ1xkL9LnOmbwooF0qvB07KGJKAw4vZUmv93sQcgqS7Ti9WnZLHJ+Zv
N5CGoBP8JPku//U7cGiEWYFrv8mwk3XO+Bd7uISf86gzeuJcI2D8qoDMTntNnzmahl0kFphRyjxL
FMAr/aKeQRXKwLqzJKlDbiLLQGRu0rWkfRkRz+E7bwKNfNryb//EPQPsWo4r/T8u/nDgXPOTIU+P
LuvrSbRBfl/lYPslEL1djacrhHVLPTS6NBibk5FoUNarFRWL1qkWmPvquB0AViEFBx2m/lCSiLLx
czft2eiODKQPKXf6KHJj46d8Jtn8776meYdsvb1bHncJdxM9b05CfEJW5eT8bcn4vDnEeERuGAB+
mPYZsLDsrEjdDTX9VTykJibKkPUczkukpBJ7YCxw08GftGeAC3jQkYt6L29Qbo9gmiCo9Wn+agy3
xbXubv0GxIMzXKMBY3NoSa++KJKXAYIedR7/ApDott0Z8Ye52ApcJCmp8gvADtrCpby81Pl3qf/b
nCdVx3mBybfsf4j2vgwVjz7y1Z0V2MY2NtiSXWs+CalB8I1VkeKz+hxYExgxCxyjhvksU33rD5vn
/U3iS2e4fpSXcEDL7zzhvDureTeF9rVE5YGbOq3oAd+Tq2haOlCW0IHY95cw0IjwqmhikOYKZ8NW
J5Ejvcw3P18xoaPsZtT/6k9ouREkcxibLbp+GaK32KgYP2qc5qwy25jh0y06mVB/C1XrNnt1244L
aVsFjtMD0VdFjFcd95wlZ9GlvowJwHa97SCYbhLaTSzZXlVjVwYPXfkFpvppxpEz0MoxvMHFqVIU
QX+kAKjtbrlQdqNUyE8SlmZ4xbl/iQaeFthJTPp0N+NY44ymJdVb/RZ/gI1W+DN0yGdfHuosmZrL
CHv19Jicw4I+KxE4uwh35LfXTadUeE0QNnJvGLr+swMOTZBn3Wmm/ZBsFF9HhlegmHd839leOuOd
tH3JcPvjDdeGZ/mXESBWxow1sa+OEuqozyeeHoEHJXzfpyyB22N1fzYH01c7ikscHNChE4+1tuhH
BhN2mL1exdF5oHFbFPrlumWwn8LeIdpHuJSCKn/xGBK2s1J8l8as/hokuIxJVZKVcjhXyFSMmbxu
2t10lgS8yh4mPPUtx5kyOO5cSJxdRN9M4cdWfK7W39SWMfIIpO3tX6IzgPdpw8YGBgtsIbfQSRWO
vSyBBm9nyeLkXjRks+Edb/PQZ630/Y27W+bRX2uPhgnLmmQZnNF+JIlguJVllmsRxqeF3ltQ40Gi
GNbO7bcMIdjCwjwq7kgD87bLUXcCwBUOKgah1dMVTMjXBBIWPkSLD9y+fSVp3FLS89UG4jXjdQoW
716pp7LO25Bat2ZmYBG82SzRnC3Zs41vU4o1msvKtIFhe2sY+6KjLTMsMYLGX5AgTY8usRBeSQuS
pXTzqTsTYU/EJvk0Rz+sAJ/ajzCKVqG1pqjRwRnsF6TDwHwkoyqYR0cq/w0JlxGdELBjnwQ4HNxi
iavcAuJgz+zMmk8hosg4ksK/FaQdVjtqJBFZDqXa5cCLSTsa3D1GWlgoIPUuENcgB5FA8gNPj9nJ
Icg4e8PwHjRqMt91BEDuBZL+ubs1h/GeqrM+7tn1OmK7/RRok7hRqeUX41k0IMSJSyXTHIrpzkKo
Sr17uXNsYuMN+cY8LSmPJPqB65XEk0nutN7xsjNgP/wp0La1gYMXbktYNY3PZ1v86CMCRB1rAMmC
69CdJpEAysbzT4D1fJKJMV/yW+ANrpDJoR37ZPEHa5ww2CmHIE847pyuuBYj61bmvwX3/BR1Ik52
n0ISxa7ZSm4Ys4+f2ksHhTv4Vbasw+GlVC64Ctw7dGqLDkXWzG/OBLvtaL8gjksgB8Ivv1OAFZc3
m+LyAM8GQ8xeetptcMhTUzRCqaYlNtrzQU0iBt8zQkEOgNc4OC4xPkiIbmv+Al07egxsVU6tO9B6
RvRPaF/BRi47J7oKDmanhlVU3Gng7SK5h7IZ9NeKPDME+1PQwQ7C1ChehXhorDXBBAmy/5VkDnKK
LEPzawHY5MvG22orKZ3TrKoYm0LwPV1D3dDtzrfxie8TyK5kq2xZ6bR9iC4Dm9+OD+wqs6y0MwRj
CDRncMSCf9hgIrCjU1XfcS1RuDz0jSrtJ0KAQzS+7B3koglu2sOfanRi2A4xkUjkqz5JgfpzLXbh
i3ZL0eVdMuztd8wBq51aMNqdZQmwIeHzYYqsBBXn76SWJ0hBL7Bs42759Kh6hjAmEXlolWCTfsul
udQz27scdh0HtZFidKff93XgEfi5MH4adunNTZWBmv3+6sTcV3m/f/Z2h136cDNuUlA7NfAqvoV2
Y3wvCxD3XGJy04+fL6S7MvdNE5+i+AElpmX0PeZ1uj6QQuDN7NxarX9eU2UVHFUkgJTAvEG8p6fn
Cb/B+K3NYla3eUhKiBXgEtIvHjfGmm81waFtBXNoHXByp5vNs7BOaIRnuqLlYxSw72cnFyhYETfd
e+g9YU61tyj4E7Y9ppF8u+Blc0xZpBEQqo0fmZNVlcSE/6u/0enaQ0It5ErLI9GCUO+98cxUU78h
iu2xwPOnjlXa6twsNHOH5BLF0bRUhEzFEdCtU3Yv9034XYgAjxSDtlycipwrwVTvRN5WAH24j93N
E/SsYrJnoLul/rhhjriANYwG3aR+TXOl4x/+sRYCU/u7SMxqXxoRh1TzChqfdK5aUjGVVFrsphca
v7IGMZmTbJrWxC3LEbGzhmcpD3uGdup825liCU/OSYu/J4JCgxAl/cXC33EpAfyP6ycJvx/CJW9z
ilhCrF2npW1LIFOVlFCyuGrgjIB6Kci0Gg/Xq/nXm0UMOS8or/BcRHXCcOt7WBaYtBxmjLUXouc8
up1//aTxcQFOnOR3JDlCw9/Vo4HdKpZ5KyyqNRcBVbvVVMaKkwsm7aOv6ONKxvGH+4HNls4Ioyz9
/b1ugObbyHRrw2LvCyRf+CT6i9oY9II3PRgosYjSd90B41XxGTIcWkKQt7bb6phptk5URdgEAeJY
rBof+qfaXCk3zRlKV7SEfcCQLW4OKy9AIJjQv3q3HU5+PcLXZeCv2BWuC6++AkZ9V7WLtjvM2fC1
aveEov5LgHAKEhcDFtyZTkfPguNle8ArSxeOwGJ4hSxsk+C3Vy6pd+49fcqIOJs2U8cCpiG68Q4W
fICdAnoju+sS6ouCREG6e6QDj779gA9UsF16tqQNZUdNoAiwG1t1TwPSe6xei67fFYZicvJjyyyg
a/WtBwz4YS8Bd1IRKHbWrrHPP2WDbeJUdlox9m6AriBEtHHtQAx7IfjVQamxfm6iNQO31xnYPJML
3Ioo7nugu1q95yJG5BboOOPZ+7HX9VXquTA8D60zoAMzdgLNr4lV1k6GrIrGqqJ7wxB1RIsic4yY
MYNbyEz53jWzCRFHo3ytzDVCIVdmaqbGQzpFzzxB5G5XI8tQz5ixE6s+4a1L+TzzrJhTXPxLQ+hh
Tkwb6qYe81r+R3RjmwsotcNFEcuWoNNQnmW46XBB87jcATE02lDTrfdSwqKg9kPdDp10dVGztVtY
tMbb3yAPMj35pQOmH5adFfWJ3Cb4St0gSnOytmLGRUxAeugEeb30/GtbNPaRzn/Wb+RgWgMHn9UC
CeUkLfnn6c/qeqpmxpIBxfahs3H0OzAuQsbMIqKhro/aBBGyVgGe+cjxyFYL8txLTO8jsg0Mm3cz
bfyBKB2q4a8T/TcbK9UilNfKNfkDN4bM9e6Q20LSIchkJCvfyHfqEKeAictckxK1ang1xjJXPZ9s
W8ZDOrYX4gs4bDIlGDoCECG3ZRSPAy6Pco/lpfE6bzE8k49rSMH2LSXXF0YRPIj8RcwjCy8685+g
c3OotDGqpViMme9Gw74DkqcDdk39j0uKRSNZoPwOT4y8YBQHJs+7anG4HkXD8qK6G7qOZkChRDR9
Ij/CYd4bWihNHaNpN486itLt2apPgYVlURQGs8m4oWyGwxA90JKQQEWtv7SQdyTBhpwBpu6x9/qC
xlGTRfICFPh9yyl9tBbJQd2D8Jb4zkmib9aUVQNBa2FmgnAjijTdFNntyRt2UGdMGSGwP+LU7ceI
3ysZhANinS5G8c8xUvQDbgTgWFedX98hqHJUzOIfcqmzCooZ0Op1aBmTfqYPyGMbPtMnST/oeH1d
PEW0MLMViSz5LzcCJew0YGe7ll8KZ6jsz3WKFPz8k5UCN0qGJ60qJhO95oXp2PtMpwxHgQ3buVdv
WsogZlCoD9NP7Al/bXXttkkvf0rbBgl3SwO+EXbuRtipvY5QzxwAsHRRAN9PekOqTMnj+04ZjLR+
NEElNqMz6AOL+sfoBt18CAKfg57BCGi+/V0FIOZSCg8qPg0BFe2dqqU+U9kV1qBrf4jxAxP4mQP7
rvXgxVedD2onaEQJPLMjOYL2PZJzuTFMzWWieJ6M1CezngOZeEaQ9fLLb6hvweD+H9nCFrIYWGnB
XQnjkLEoDGPlScp6+2gRkfG7d1jtJvtKprlFmm7XV2jQvP2zY3UhGrhxuKQI2Q8tsiNoyxiB5fxb
pfb/wNDvX1s0HgwtoGlv+xZwM47rUSspZs2SbcZDFo1g9ufmrni2pm3eJtGCQKxH17y8tTv10Jyx
l8lf8Hv7t9oZI/B7/y5wJ4DQx9p1BzBQ9L9pU6HJErbdWIaTd7VBbfsBaXRDKFin0+U31E2CCPcM
Y2eKotLnlRJYO81gZDRO57obGr/jWvypuBJeN5ePNGGKHPBfuvGhcM1QHA9wk/NoOkg66yZE3iBX
fEQCnHBEo/kZbQyEbygHZJd/TH79lTmPyXHx8oowfdex7tPtbEcX34d01Vc6K/blLzbCOP2065Vq
iuB1wpXoRZIAYdVFOf7+Txsqam9G10M9UHny/52NUzH4xYZGrUzPm3PEal6eFkPIXdRACR6tgYvZ
KSYaf+1i8UfeJMa6+8mgdM5qcpcRxTWBIWoWEPtm2ediQBLYO+sgNHP/pPrkd4Jq3CPd4qmoVjkc
1AX46QVKmomTg8Sx0mODyV49NqrHVC0kSRBwmAeELMEUkE2Wu4gTtGiuO5vGbK02ODJN+XpwnEE1
5UAbl01IaDD7RWqLIpyKetQjtCntHJ7ErVfwkT3FsvDg3jaZMjAMaYwPcyULqyVpcRtv9ipNOkgL
VcMb0y+uSacM4toXE7WptXKH5X6+c+BqgrHTgIcRkcdT4ZjeIcswpqetcfYTi57MKZy9DUn7TFve
ZFAAkYCPgFls3DRvIJFMIFDe8sTyb8P6MZ+gKhv+QmJaxfsiNM69Qyk1ns3/+V3x5p02B9cnh5vb
FRXd+/Ps/7ZBpLCALToUUk4vNw2/CFXkNPnnprecLL2k9YvcLh7vRGnQCYkOM/5JAacVczM7kDwh
dWZ3pZdbpElTl7wRf9bsUzlwPWEoC0crRUA9u8FnA+zObaXq3BTWmd+pgqdWdYUIt4WTQd6jV7wz
id2AhtpiIhFJJ1ys4qU/HnKRYXCvVSCVbIj3FaBdrUKtiFW6V59nJWLXtyCE0ihmZ4/y56O+z9c7
9baUocyVfcFB6xmX5IxnOkup583mDqYJhl5pbbCR5+/LFe9X7oeMWWniPEdl34KMMJHwhMNmkd4/
STYjV9iBmcIa5i+Id9XB6QeIep40t5mjpcjacow0ET3dEQ5Oh2eXgv1FpeFhKliBMt+ToCjtvcJ4
AOp2N3TJy6j9U8rwBnHJflTXYjni7swu+n1lD0QrXsKPfr28V66vFgjcWUSS+vDMHBV4Y3vjnCkO
1trc8eqW4ykSsLfrRB/0R0PNlo9Jv3t34kc7EZgVCVjfrL2seVwdZ9oHIflkV+ZAxAGWka/UBfJW
KuTrPZx+Tjo+ErzG+3pfqDBxsg4VzsyJMS6ys0DAWnB1W5kCn3+gQ9mzA5cw/JK81SL3vRjV/XK0
oEKNd01ds+x9F2vJVghpEDh+rHcOm8R1OZCkbywjdFQ+pzKarsYmG8FycMmAIHxJdjIcZ7PX71+T
/yrHf4X4AKMVawC4kC3FZafbsTquSu+AirXZLpFpdhKdQ9N8/FIWYgWNxqJH92uJep//pkNQPIK3
3ja/zFhpw3Gcy1cVdQeMKJZaWEHM2G4HK7kpqshfEAyBfWpmR4UpOVgH97g/h8PZ0OtsKcHqtMza
JuIjDeYal1lbzz95bae5kwJQhfQyfYHL/fPL9bpMHBviBGxTYSy3wATALRUd5bAwvR7m9s1erT2t
1T0GXkwqXiO2Fbb04G6Lbo0TLTqQidyMAF5je1SuspT8UKuD7CzKMbVnPo/agBTUwBfeGEhMDV/R
yrBZmM0QuWnxB9Ao9OnGPthptaVJGe8Ar7D5PnPyuUUkv9z+/n2Guhrr5qXHfrlITQl3rFu961F9
Hp++b/SGJ8aiHs+qQWezrhFBbCyttYBgOFiZnkZS6E7aQj7AMIbOex/5tzkPaJWknKWdIquw2GKE
ykOs/JYlrAxhqH3fgJ9Sr66qlVmlbFcQZ921+yIfSkwHrcizVqNFkqu2J6SAL+ZpGQHvGlqeJpAv
pZ7jVMrXR9C6JJkv/LP/00JB8qdPAmJYi+v8ZRM4Eyy4Mr+A1esiUS13+HbDyN3BIV8TZuDFmNRS
GrHNQ8jZ0ojcJUPjttHawQG1giDJvb/qc04exNfH3Jlc5vM6vnR1oJvIR5Uh/aGBZH2b4ohEQh5e
mfViZEBaaUilhIwFkkDEEp7wbsJLxBdeIdGAZD4ynnrD7yWK5bnNk9g+Er+rnchdERqcmId6zv6o
Q9AU9xr/PZdKQOYKuVqjRz6/iIcbEHt2o13UwzP0pwVD0jIFaMe5kaIIeIK9nVaqyXRRJHLjSXuo
hak2wjczYdiBhGKcKZquIJI4pTj6gz6LxirL3AXSJa1S9JBBgGMVOIHURU5C1JmkGUpvhOXc/plf
TVD2RcB/t4FlaUCmwactmj4WjlVdLcYLHWD79JJkqJW1+z9IvZXHOyceGs2PnFIPDm0198uwSPCM
cs1DY6wXrJSjqwtifInPbUqxoMH7Rg1GokIeLNCRnRmk+0qRdyllVVMACBGHcshVy2OZ12tul3x/
Ib9rd+9bCm9JpA09zWK4bUg16nHjtTV/zXqpY9LlVoZkw+uV2tReAun2FjAwN7xb/U2rK3SBes8V
8Se4xH0pqBI28k4W+glRfy+F6T6VO2hy7JzHBbTUbrzJsxpwcJGN0CrMuUGmGGmtS5cCdJRokCn5
+uP3tZpRAN5kMmz6coOOQ9uPT0Zap1ANhvNPuTED91y5FLCorS/Jn3ULQJCDYTm3Mjn707mf5UKZ
ljvF+9/ZEhRmAGT0uF69Gnp0I9jce0D9AlwbbUduMTNM2tvHBxpOahI2TSD/wuqCiNGeWW7ymhgN
uH2NRREGqYRzKhRbEEZy+movrBh13wzIYCznNZ5wTazPyunA6/tw2osyIyUpHdRP6bQvTJ3FYRIc
6IWkoYJmLfPuUuEVRyrZ0vodIfuU+unKLFZXySTwjTwN28NMBcW6pmZx7QE5BxB7IOt5pI5CNtiP
LL/ufKD1acdm/lgUGu5M0Xh8ZqYv3n+sIZx4Lm2kqsFEJwY3ziSL/6J1N2omC4diOGfqyIWZrRlE
ooNQWg4PxCAi1gOv8wChSl/KDVzDU7JbQUcFSBbaabLa/82ICzcjG7yX3oBqu5FYuP9467JURLV1
Urvm3CkaG84wDzVoFQ2RT4HbI9VwBhgeq0LdNu5OgzqAub7mJ4Qqc8XR/QpxG+tgdc02rFwoObhQ
u6XypDLGjga2XVnW5x4/+Ec9pzJJfiVHvmitWAOy/Id9sSISfZxojKjVBomx40OrP0QHirf4EEKY
eEkQ0q6dAuuOyX4rz2CAHsjhpSl1emwU1aGbYPvjgEhg/0K+hwxCX7hSHmdiCSXoJ+HlfNzpONQ2
R+GR00Kp/0poDDfuXErGfDa944sYkpjV4TY3NEnPiNYbZcR7RIV2xm7a9kCPSQUn0IIrARzB8z3J
rVtkOMyISmRvEjIANINrPa7NEu48STmOTmIhskJRQP8Fdg8QJTzut3QeV9lYI7Ui2RMH3RQEi5Z+
CemVgb3NcPcFznYWPoNi18mINfngHZYzIksAo/lQ9MH26+ufl0Gc1KkbrRL8xu9igEuc1TgvOI94
/Jj3381OtAe7a2v/L3an2BcoiYmJDv/uM17ebfygnJTYEZ0vUb/uqjmOjOBGI2SzVMUlRZa81+de
nSZxaDuQq4xX3LQcBqgYYuafwoQydaX/IxAMrcOrj9TxzFJwWzFq+sl9ewN04ADnBQH+IhzUgiym
TvacyR2PaMOIKAj/78sBGjxjCMJu8wNCPcNMEJO3H1mopM/81xY5WGKEjPwICDK4YVjRrl8OYIer
JPv0QakJi9gHAm1vtXDz6v2nUtbk6xFt+gRHXT6a6L6YwQq9wbHMQ9W2gebesRZ8CqUEqrcqm0Xv
AYtBm3fNwnZI7C0mA3jgg5NzXPVh7RDMFK/DM2AomJE7u14wdzhQWx+CD2fuhqE9S3A+XUNBqw47
bRTRJoPx15jV2j5BiR+9tT3CtvK29CgOunbVHZyglmYYVt6UOZpoSAcakq55KI2jqYy3Uq1q5ZgG
T14mO5pMEQJf1km89RHXIhHYZEJQnKJ80zXszrAwJD5Vso8Wvc59R963ZSDqX1meHybDp6CnoKej
VT3msF5CnPtm6jxYiohtejwHfOQWsWr4CmjuZZuB1T3yFNALFnZrBbO0dOkvN0bXEz/TcjBoniUD
bkvM3Vem5jB9Cq8TaT9EdGPMH4ipiPLzwiEOIxNcw4lX65yToAw9rJ4ju7kNYq+ywtPoo4ZJelJC
6AhgHVmIG1LXxzk8SwQEND9IzEdT0tBvBP5jG6b+SYMf6uGQvE7UWs1d2XFKsIBTrxw5AOJlhURp
WqgiZ0hkTirwA1j+dojuRHs1wwLqCR90RwTZ6f1mcIX6niDi+U5vJqnIyDrn1jn8Ql3FyrmLaci5
kUVC1Q/VUUW00fW3BaMoaJu4KVya7JGAiM4v67gjjQ3v1InUlb6d6sDc8eanE0Z/5Pjhp52GI3rF
v7vc0wyRyDssEcpCeBw1Sh72Lq3ToB7XKK0Gnc4c4apxeqTH7zCcpqortmSXDXQ82ykvSczcR1+D
ptShgGmJ7VJjcLThnFe/MyTztbssq+Z0460oEwBlx7vyjjiPb9+0OnhaRbodH2GlGWOOzwCyv8Ex
WOPJaH75m6C7It/tf1d8I7j8idKPvssYO+3TKXOHoLubtUgHfPB6avW0zdfxg1IDHWE6keg/Czbf
ras2i/1Lxs0eSi6Ezdhc3Z+V8+41ML07FeCXNeq3/AdgdmzSacEfin/psusdV8c0zyN5jHqv4+TD
P04Tj7Xdo9tylqEY45atn7Xzw2ofekez4tq9UPWA2qQTggOZ13+gvBoQxS+PLRkEN4SWeK4eNSId
eSKyUHRf157ZFBJh4KeNXQlEuqamUrrsKZWw9VAqKQTt0Ec0xBzeMXH9fSzfVNsPljLvHtNolc5v
LV10cygOa5S3F3gXWgUqEJfCnWDdvA9hLdMZDed6z1awfi16eJtFFufGr9vIWtft4Pl4YIYN3HNt
gjUs+3hROHTBkd+AD5vJ69D2XLlHyWbZzW/l9nN140w+5Y9KmzIDFal0XIlSXdd5ANBT1R8XpmxV
WS1d3SoTBJ8dTfKqwvM5KvyHF59TGPkg5FRWv5j2B2mZk/M+iGPV0DS2iRGctiMeJswbkCN8MRBT
y2pZfcepXGABM8CbEbn5Nfvbu3XKHUpDxKK3kUQJYdpkL5e6KAnWg2LXfxao2PKfd9lyDBWu8v2H
9lxApQeElXnpN6wP/fJWT+YfPIuxu3z7XMXy8VslcwypKkC3jo5qIepw6JW5oPmPRPY+N5f4tADX
hi6k9HmwpfxZ3hq/UuFvkeGJaRMAH99AZ+RaXJaR89Z0iR7GHQaS3Rsi0+R4Bz2ibnjGbxCC5B/3
3PnKb1SLtE7apffHcL3xnzySvuXS3VEx5IURc+/sIsymfiGgOH7mHvxT+POo7aGNDdkmkF6LX1BV
ynMYT68KJwDdPpzat4hiRUu+fW0DfCC/xOt3AC3eiGFoLQN+zxRcH2Ew+DH+DIkeV4z2+rN8mzR/
ZgAbG6Zn3I5mwfwqEdhPcV81OmC1aQMkIc6vQOjRq5utF8m/s9vHBxooET+GQr/EFTiRhG66++b1
CXMc40XH+UnyqpMp70UT0OtCCaE0OI2GuLfAW5TCPpG6f1t0oZeCvl/DJepAoC/ZF4CC/FsJCrys
xSPgnHaTOC2zy89cvDvrxDkdwX9YyuMD542cvPZGXGVWwwryhucM8RSCmB100O26KpxYsOf2CIG8
6NzdTqXSGSaF025t/vspm+Niks+bJ39eegJBYCYBm/ohtzJ5Ptt45jQGL/nj1LOsrwMQylCiSMoJ
E819euAii+fQ7SzHoSaZG4c2RmaX8LKrxaTUNTrzSl7HY6y08G8R56PTyc2060pnWo3aMtGzv9j6
Gk+qf67FvEX/ejgIBhSBggAr35n4d6Wu6C7sQ/wJ+q93u0LXeFlu1oX0tSpRuYYuFD2QToeyH9h3
BCVCAr+EvuJ5ZkBu5TGQs2/JXq4wnjfVGks4/lLVqshk4LfTqrKUGSimvdPLOi0Ptwlf4wvoW6XH
yBXtKz8/N47w6eSTz6sQCHijMkdvsgcM8GQhJvBUeilkhmjwlz9VzIxuV9lnAgG8leHcRy1ME444
/8UTcIn2dqXHGEC4wb9JqdR3FUqp+Z9m7hhsHNeYJ24JzhalYNOvHONzGq6srVdzKw9Xi5ar6R+S
PaGRK8b+4qa3SPzfTz0FENUF0L83U2DGz7rbdin1oUW5KB+2WgE1CWUrE11jSlo0unKfubJLTYi3
hnFgAjk0sk7f6hB3BdwJz5zPXNTAjqV4I274lQUzLdXx0Eejs9cuSDX7AzNCXBjnZkm8YXNVzKUj
y/VyVc764ib65QFQdnYOZsUdbYlpT/oIO3j31CQVkeWVnWrL32g80/PHhLXueoKTIn37Oc8xjwS/
oTiIcHu3mViDy6IYEBz6+1Y0PetGiuqsByccg7uX43lJUYwifn48HzhIkFlqxlm/RyYksm8H3mwE
GNV8An8di7uc9Utf/0H8iYiPypZNHi+8TDiOOH8tJ3oGSm69nK9iXzw+q8BcQhuhCLTfyzP69ARo
FbnTO71GvUfF+q5VQ/wAeAlirDSOCp5zVzsxHzB3WJOmaLRzbHFZ1567ka5QTBI91ASYzeqZ1f4d
06wniUvRXsXAqRALHQIchgvZ4HEcfNiXE2q8vORfIdDvsF9s5PvHpRh3gkle2C61zfH1BXR421GY
vYVIkhHkcQJczmlmo8+BQI23E2zhUYSEC4XIZXb7/YRhK4+hpZA6rxe8m0nh3YSGuH83kYqqz5nr
RHZXTb0h2DKw5Rj+7P2rUw/JYZhNgLpsMW+zaOWMtsCFXOnoBdKo7xn25R+Vm1PBjh+4gVTp4NgE
ib+VTOXQce+PgmNwHbOcMQ5t9SftiQJ3BEx7CAAq65F6S0I0THIIxezZmJr0y2wtPJJSeeWw9nRG
+GdaUB9graip/ACweFJfNe6M8mUDm56xTwMBiAmZbwNNVDbbqk77HrbHDyiUrL+nKzQ6U/yKPoq6
mavJmId9EYLL0MGHD0ftukcDyewKQhcgLlLy2i6vrFXp1RcaPMihbM/MyVmAkk8RC9oDZt7ybkPU
Nasf+K8E4+QQOJ18wYOp1UgoCQAUQVDnplz2NabzwPbsPOBl2HBGfpkuJslS3tHj3d/N29nxQz5T
siavXM3k07+AWWHhN2wHlManvajQN3IAsLBLgBjqAi1a/cjqilxlIgZDye6WDtEQSlkSwmWH+TPs
N1VoNjhj3RoSlH2puIjHJcMNRyRAPRNn+KcjWJx2ECQRoSknCB4OuP4giSXA1gYEkMPrY5LkFurv
O8IhAQ3m3zQ239KIAXjSLf2kbArYTA4bs06G6/LFX1YyDgd2FB7v0Bqwp0QEF88xcjApTHUjcmt3
PC0UEmSk4yeuvu5XmpMwLFpkmEnNrFaPuN+y4VHa7u761q2AmLkHo+p3YdYqIbzeMSe6RldlUQ3Y
g9opN1qymt5T1AAry5qQXwddKG/hIfB4PD23o1kb1uX0vFz1ZOAycZt/Dqkw459UWSmMT168GlCw
Ngvre4SuS/G+6N2You7A6/3QsaV72+rDbag9ylIFf0PYBsdtshL7+X+e8AqFHX21cSdYFGhfmOn3
cX81e8v7ki65CbdUpMaK5x0NgGHXA6hGHfFn0fNpd73Fdp2XSJgj1jwp8adSgbHCtMnjOdc44JdQ
sCPSTOdavCgXmHlp3SmOtIh8du7Kxi7fDYAUuFah3toMv+r6tCJ55fkAIau7ZVaL/cMicsFEQhtX
5fQInB2KYo9nIkc3nV6nJoAQ2+z6LLqn/131U2IHTyXtcYqzbCEuhjdxlMkeCVTnG4eWrg4MMElB
/z74ogJtIgnF1HwzHIqqvXZlxLbd7OyyrNw8gfUE5Lpx8hAJuJHWhEe5nq+tlMdNyXWrpXFQnbYj
TBBauo8tPcdeigL+DIyTMlKWLBPGVW0fUhs76NRezTY06HXjzVsIvvx0cCzr/b05W2PqOfv9wYza
ZariDXHnY5Z5Z/k9zRbf1lmpFyn6gaqVDYN6OGuTbvzYAdqW+6e/fsJlW8655wsoN3QHhxKmPaxw
X0N1TTfvQoRz6LO0bDzZRG0Jq1L5I8Teuuo49cCpQ6XkVY9cwPBOrPwMALhkhuTl5uWo4Y6xgGui
sEXrHktALV5Bx3MH9LbzaRbgqH4+tgtocRHL9eafeEcifPKyUoSU30sAACNOTSMNevUeh/X82qwP
+U9PHWqS+Q/dolhmI2qQSuI+zDgkgCwKQRZ5EVYUq7xe6+49GKJ0CrStjeQFgH2XUy46tYCXEcKC
dRRIRA4AsoPd96UZQbTxZWyefQoZkozFsel2qh8y6pR1HQPXz54HuW5www2keD/3UlTRHsKTF3pb
kyc/q8oy8rMwXdi9Ezii6npYamPh81wBlCuKrL0uqdZEVtcVgH6skUOpfT8ZtNI980rKVj6Ybit2
x/NpGdb52QrCjyx5A82xup6dYn9KWKpdU5xA4cVL+0g9DlTRaZw5v/4kltJAD9v3Ndnn3Rkr+05M
/6qd6w4WfyDMGTCGi+8IapuqGFiQ7pBcpqJHSnpdmvU28toM4TGlcx8ZnIJ+1DPJCXeAbevM/Efv
uRIojU7+1UjG1G7CPcAvBTcxRDRiTEgFpNDRBbCiIpP/+mXLnCMddLLpMEpjxrml5JkBwLyRoPck
QBq57Xbxn3mfKOwMukGCXCcfH7MXXobQds3LRtcQcIfkUXFWPgmfLgg+jstIs90lZV//axmJgwoO
KvTtgN1TCmghYfAHGhgYeJoehfM7GDyU6hUMMVardfn1qvkdaAXGJWn/iTPXGaLUVc2CMJhBighO
3HcSc1kv6liSXdAeb1srw4IgduDTdH/cVQnFZyjQ2XWfWXOCgOH53dLZn4bWPbCtzTFsqo4A3OvT
0Cm60yOXbRT/tzhtVm5klCYIi4xDSoAtKLn/2tc9gVrwox+8rwaH6mAzp8ON0soqAFElnK4/vSKe
uqJIew9hETkM6YjfeWRxD/fPvBAt05ezIn7uAdf5bSDAFn3L2KIIW+B7DPDJ2o+7m3525KCUmQjK
wIB//HH/jP3Mczl4z0pZBxA21Up4i3HY3RApCfBJvGq/SGBC4KpU0tSKFqPkXAXi1vp3xWeEGXGt
ybmRDCbYBUm23Bv9ppm59m/sbMhDONMp07Y0bY5EualdAQ1dyzz3IiZKqLg2TirxpBFTMnPxWDAU
6t6qiIhT3eH1E/MjNNdbLBVk6IClfINAGrFI7nTQLexE6Huukm9nb5assvd065XyivvKER2Uo7ju
XpUNZMWnwg+7z7q3hUyLZJaFtuar1dRH4F105Y2Lla7Pi8LhC7Wqqt4DjA1Qoau+S0sjlMeD2xGv
MhNbic/XBa8QxXvgrCSW5WlJePGOz/wYDs0TIrFmjm2mj3VsZ9Y66ZDXsFGy1nf5xzgxzZCZeFzS
5Z20eYeoVzatGz+Q9YQnieub62WTYVlZXf5+7tiPkUmOw4hZjW1aquJJ/0PPHQcrNWPj4VnOoPcm
BD25CGY6LqsGXhterT1Ly4ApwzQ1xWT6TGD6AWqIRsj8J2Ey+xwphjZhvdK8XYTR2Xgf0Y7J4U5W
FbsjgWDJKnqkrye4pn+3o0mUo/zleUdeb1Uc28xvtEpBPQFpiBvI4L0YysopvzsOdorjOWHN4y7L
9n64p51GMP3LghEYiMGvsCTUwrI8sQJW9AdTkot7Q/0767o06TQXrOyJ5LF9AtUamF4orRg2gsmJ
dPLcdeCT3LupcoqyCy/49YG7p989gwStEbxt2VfDaHwAjeS9aJapSkUWys+URl0gTCBuf53PFV2C
7rSNcDJBWbB+rZLe+kCxEPz7qtNuDypESA5v4VAQokFwTsLhXoz/n0z6pbD/d9DqKSVSo1TKhAjr
uKO1VgLZGX3kRBHHyonzGAorEszQnZpfIE+lm9ywJtoRrzcBdsdvnU58g0FevIr8CVodnwyj3+f8
JojKSehLEv38Dvju0Q0cdTx8HO7a4oMI4g4LFGE+/XKX5gignnzRcu924CxSSQJt4PJNAUi2TJAz
K+emuiCQ7jNq5bqvQ5WYObBX3W8vzUDD3soG2N4dA7Td2MrFnu97CkfWd/v9cJzKH2DZOsJPmuGW
rhjDdPO9suj2FuHzk3WEmkzU1Ok/63nGiAsfPGjLE+Rm5EOhgijHNDD7UuGhurhnvczQQMf1I4vr
0N8QZ7F//jasaLeKprd/RGwyQavyCENcV0YZx8243hHkJVJbm0lTwk8JXqhC1hw9tiaW4OKBOGmJ
nDQCUG2CqH/LafG2vlpMCG9qM8ukhHN4fo+tmRmMcWyLKmeYsk4P+k1c+1uMmKRwKUuNCb+hpQuS
QETdntvnKGdDfQz++LTG/B7024bAe4AsMWmZvpQ7+qbnXnxn3Z1gMcff4YgWWBaDfLlKCb90hg5l
JOBn0XaZFlOkUQlbN6YVivJ79U3ALMQjNv3rDD4JTqfIwql3vlhZw/rPtAny+rR5CgyqkdU1VP6+
EK5duTiCsKIF0V7bXynytjxIKYMQ8qi1TunvzqByFw+dEMSLgXrKyqD8xjrDuyyS93he2zLwTIPA
UJdFTJXJhdQFYSK+b0sSa+XMfHK9F7KBbt5WjKYdmvTuCF9YK9IEKiKfLkzX/fDokuxCwmbllC/8
bws57IWR9uYjIeT9lzRSRAX3WSNPFYtyga9wv93xsbT0BZweXXFwAv2u+Rv+oP2IRWtqbyvQWO+L
bKwmwqCBlUGdqyVjCPOY7GVDTZa/IieYr07NHqBlgNkjTbR7OJALI8HFfQBM4Ng6kjbUMrky9yuz
kE0ejJKo+cRNYdJ1z/S4YguS7/GxbpyWyL8dl58xpzrxb5hquQrh9MwSL+6jF/3c7dzqsc2iKI3U
xBceXBK365rc8p254lXjvbbGA0HzsVXROq6oRmemomahnAsCj18IcS+MmF/DUEG4mH/XAxvr2Oky
tn5p+4n3KvB03cbb6FT6hY6Xmv/OL8NLRdTcnil5npRxxYP1GhuBbMvbylKxrP56i9CrvJcZ94Q5
4c7Tm/drQ0UO1bvvp0RGpAO39JvJEwm2lKuAq9qA1KnBVr/0WFWVPNxh4O02rbAPIwm4FVRaWhsF
m1dAq1lul2Mgfo9+ECSJx4sBQ2gzs81oazoBMBAXWqzTGKRvLZCJ8ZaVGCu/FDdQwQh64eEmeofd
bM1Pd6n0Zjfp1JTc/7vsiRFhM1xmEF/YbiYpZdAzIKYcnRhVnDJQ8nApxxknEBg9qcrB5yZGlgGy
QR/5QGR9VE9SbumbT/VjiKvSBRYQVgEfj4xKjEeFBVLg8saovRyeKfDGIU4G5cIVvC49OF8Vyh+N
vRLT+FEdJ5HLGBei0/3kXl8Bw+yykqLL0XjU1rBNDhnRbwi2Y37G2nYOBD56akF6QHe/Vs0Lvdcj
oYu0lPuyy2B1prFxMWumrDHFySTD/GnUfxS8PMVjivdj/7f4Y0Rfhza2JRZr67FIC0WeckRjlIn1
9T2yjoJnaU06k+gV6N8+FTNbO/QuiX1z4AT0DcFHfS86V1f5fvu9g+2hiDNFhAlzhVJxlfmBgKL/
2oesLnrwYfwEw8j6zs7/iksVZoOBUOtvv/OXEoRG7EagpQF+OXWVMhTVAlfyrX0u3j+Van4GbrMu
sLrlX+AG+xuqD7x+Q67/Ay8cU/OTPa7MzWQtVDP12weu3tHDMy1qLoDJXsgU6qwQ1AySNHdXfHUl
1YonDoF8lWvPi75H+A7OCVM/+Aa7lBdki+bx0A1mXBWelxEjQPiS3j2/09ndgOevTFmNjwxxTGUf
ghkusQaPxct/C3jA69SdCPMWsYH+SwCW9C0DSpJaFoR+FsWFdfKysQ5gcNPPXEbKHBs+uhPTRGjf
RAXivupUANaOzWX9RniljsOvIqZv0M1H75LTtyoXG7dsgjG439p19X2yXUByV32AsKwXNjBaDlB8
pMBrDW6NpLxjRTm/ZZum3Fb+zJywqfxz+LL9M26YZzL+YoHRpmiXwwyJR8tQDXbUQqwHf2q2/kJj
Ba0PLu39svg0Q5txUOL61zQfxZGZat/jy7aMkQzUWeYKPtgtLxU9EOoelrh7SEpxjCQQKzTZeJAa
FcswaCC/9y6vwXrSzRcZudAGZR4AyfAhJKWTIYQzQvpzDMd7uaJcV4ynor6l+5vpADZ3zU3M96VA
LbvMcF6ExFCugd9ZCaBqs1KrhTf3SAQcuOzX9QXmjx5caZItF7+ne/lG2RsZctWya/6xlIC6eOxJ
xYQ+U7iD5i/095GigM5ElMXjxMAL6ySrVyUQLDqiyoNm8gl2kWyOQGNZutxjffb1JfyjxC+OVd8+
tioVmR0fpIS10LgdNGui0YWZhZzxb2+TXwwXAOzUgbVPai0T3sYMNCcnIlx3GAmHiIRz7ybmkZdx
O4f/9tgvRNWuVOtyWO4e6F8HDGLMDV3zZS7o8o4YMij/fVYcKujfoYYpzsOd4gzHgPLOJif5HQPt
Q2vKTW7x9wsFkBhilXWgkkmq98SJNAojniW+tD4b3jhP+1UMtTpKoYUu7CjHLXS2xh9OAO0udpWH
6VoqWLdP28i/dw8T5zdaSCWZIOtACm8Swp6GEOn06VWbIXkHcem1auHk6NCSqSfiM1Venkfs3DiJ
5efZz3bh1tETAZEQvGaCZH6VeWpOuK9+u570LDwyWtyNCvbEEBZclxPZ641dsRcX+GL/hZpMX3YR
kXIcp1PmRgWINavSZpQ5Cn04AmHHh21oMi397iNuoYifu47GDwmk0Ct9NICsOMhax8ICO33dlwRy
UvrQ/VApsTmUDy5TvzdD4n1TcnO2oOE2oktflIBR03oqOSqLUWwXiv/RpDcxbmP5tzKEUdKbzzzo
wmgJOOKLqOWjb6uYGSeJTVXSAuoVnHjFU/03CLRhnhoxphbyA2PO59os5D9vgHF1IkeKs8/ndcFD
M7aK4o16W5KhyYuaTQKuWByTf4fooT2UTQ6qIqHNhrKHQ/I/fyU9y3uzBlxgsi5qffTadkixgTD4
6VhBEchbx0JiZarrk1TWmjl1uTIdT+n0/MXKWw44vOg6DfIo5jYub5uK4ahEp4UynbmThJ7fX80o
xeGdl3T/G5yCgTXIsUldr8WF+z9ZJneDPUzLDoJ9ibTxAwIq4aMIk4FJxzIugc8Wj9F00PsQEjus
sUxInsoUhhktoAJBC9qvfL7WGtoSxjVRI//X92Q5ewgU7VEO/a9oz4JaAUNgqPPe8X3Q8bql1Tz+
W21lRqTKew8s2A6nQGzIiWUVAzyIQHs0905HiAIsr0Ma9MYYXHkSYFAxSWv2RV/GQmysS5tD7Ada
ohMiTIo6lV55TaO3TT6zYubYcH0oYcAr/iN6qki03D+kNMC4pC/1VCZkHjnNiqm3m3+aBDZEzxZz
QbH5njNZND9BnGAonFIWOmLnh4PkUKhOpKVOC/bMH6zUjOO9o0alF+Jygznm0wxYUQAa3Mic3Cdw
GJ3dRsbalNcPIapDSYUhtVWG4FSguuwNrjMmFOlMObd3aktdV/4+PP/Y/vk+8busJUbeZNC9KUFt
t/oeSK2cSiAk2A/EX4TdRrAO82hzUlsvcFulCP9ffztjj/5uCBicl1UE/qIsyaP7EGQ5J3xlEgIa
faNMg27sUNhf1/mKp/RxbekhcX7JgxlNocrT2bPhdPq3BVbvUF0YKxDamVsslnnebXDsd3a4rCkK
qP8q0AsXtNZSbFiCqmkChYkaWmRBrO3wDLr3YzKxDCPWuDENpm3a1s2b0l0zp1vJf75QWIuXRydU
DfVB/zNp8XFBpj3OKBFdhnMyX5rm8i0cM4zBjhNm4mZt2MgHlRpZqhgiXUJ56yyUEbzlNbalic/X
3/yZ1WVt+WJrmV6oiChpCx3IJTbBhBPPfol55+Zoiggys29iAhOK9dTbv7GUcEagC6cF4HKSyqVG
5seZp8GlWiB9dcmMng/vjrr1Md8MZS3/tkDVnRpPfix5J7oBh5LPpgiTk0Dh4bEaZhAH9gVAkgly
Ln0uy6xlIOKU+w59F1hvAk+AgKlEqYxRWJ3UdI7+CaUBKS4EkBJe1UU7oGl27kDHzPuDAEQqk2CB
jttdZyw7FSYNKuUdaVClkc2jhwaw+qFZ+ioqfBGUNAgO0vgtJiuU7TvSfgUv1ZuAChg85BhYqfBv
kysnew0tYC1oBrQzp1zxLgkX4ea+HEJ299tjP53USsqJpSBTHH5jBqV6rYGRVYLp1oZZTOiCUlpC
MzB0BafhpGFJbrJ61Fj7fMrY5Xby9bpqie5ufpC3/IBuqb9j+2dxvVeic+ZDi2yO7u1gLbuRtpgn
tBVj3LigX/GekKhbbjt+WPfvo7ypg6hCDC0jfB7N1vpSQiq//O7i9LztZFvJMEToSA2M5PiH+F0l
XtTs1yt1Ddn5qWLKmy8rilPT76fQplHTUH/zXlLZLihGyuwp5zL9XTyF9AQSs+eF+DirGrd0+G49
7AC3NBS3XGhHXsKxJTl9vaQ7wDiT0rQEjdf0WCyqVm7zu5G1anfA1gm7oQqKJWb5jtU1O9nZt29s
detP9DiTdgLFoFn8mVZNq0vP06Jb9gMJlIuAU+qHgOu+Rbq56jHs52qvR/4/cD5Wu88vOEUn0i4R
yBt4FfnmsEwP2Iy75Ju3JH1uJ9//jXD+rw1telxM0sWyIWEknpuXHnfJnZ2hlKwNxIOJMVAdtiO4
YDdWyPov26iSd4Cq5hp4WnUW4Trh6U+7lG2oHk6VVW5bhjHtxFFp/ydhZK9OtbtIHHLok28Xcrfq
8rKHFYB40Q+/6Hw3Qv758ijyVCchwdaagsVqCLOp6gY6CVA/SuasWJJTvhpCc5GOCChTYTByKvo6
SSmbH/pB78bRYYLrh83rGX5gZM/B9SdJTjVr1qm9LcsusKHzx9Bm1qr6u/taFYZCEYnlKJydhWSK
L5ka7QwGKtRjPZdfxErxGV74FduQQzODrhizQ51sIpBkVo6DbwgzUSG/HZKDEWu8vfuWRZ8Qg/uz
I3mX0XE0T/GeXdZDK9ULMJ85J9Ca1/Ve/URH8P59NvQHN47ENoaB5/2WCupZderRAQPqCO0lOUBK
0PIte8CiTkSO708i2ry1RvuM+qwY9TUZwQtvc1LKPsDdBX/d/hvDUVYY2WE+FOzzOXciikf4hq4u
D0BG/xO5VZiSXr63tDyW2ffns3t09WTUss3vOLUMS1jeCEUpcfkcoI4XsvOBa0DdpnSm7gZVPlwK
5+4JS5wkxkdmZYDYTJdKHGOLcySua9itXYfk25LKI5R8o6vfPqp3vZGa5WHbC515U1s5wxMj6uV1
HD/sTJPBa4Kb49Q6DN0mY6fc45ARrOF3T7yJrYG/KjvT0L4uYpmkRZlBOJ1Az7g+Im6zHoFJDxvD
8aJqn79yOIEH0H1O/s1cmY0w8Rb2Y2823aZ+CAXxi0iVfqBFA5Bj46dcFor0tiCDrMIoVg7ufXGc
CeOJ5tqsbZgZK5CYjQt9IEA4tkAEpskyc5EJOyKBH2ff4E19h27FQpdli6h9g7Qq/mO1O4ICWd68
5VcHKttIbf9jtqdZ3B3XB85/xaOCUEg/oAxCmogJS3Mnvq/qxOIpBAEdzBX2xOr4M4EGSb+wS94p
lWqcwmGLpUMtPMDLrR9jek5n8k9VTNkXiepFi3CGelXOpvvRGMFpmtyrU9S95d/QDvpmYZEv1nrI
EUxea9Gzjm4vbMzEnDezabxZ0pzfRXC8JQdSPIcAkGaX9BymXusyuiiQxMOrNokdLbnTLSigCSaT
iF0sOZoCzkzVRCRXLBhO7n0uLJ+E8GR3tITSfxm6kRYL7RdT+m19ksMQhSjl8s6LpCqqSp++jthG
ms2D7xfGUjqj7bMnuTn38KxghNKmIijZ6LhLO2XW3WxbxOdlaX5yVn4prga+lF5cX/vs9BzUHmoO
MrDu+a3XgKlCUa4cpTzV87Izm8LIKuLV+31T2nI7da6/OWT0sGnER/4RSNEiXKqLW8uM0eNcrBZa
U/yDJJDZqzwz4ShKT5dzAcKbzEgHdYFxjhOSz+IhmuW2RZ7CcGD1w4WV3GePN4ksBMIXEYH5CnU3
bARpmgbPqmP23Nhu4xhx7gstwCb2RvBYOFnCwJnlQtSOkOe87KrtAX0jiktxPbGRhazd+EUqZJFt
MKRAIcRPnpJeqbbzWMxSv7xY2CShXsqCXNrHulSC4KTJFyCbJc49/u48518XJR8LhVJ6iD4327Qj
ciuOg9I0TCIvqGmaq2n1fCZSchrijsQkZVQIuxRPyuXK0H6Iy3PvZT29p7lLP7Csqyavx+qbWWHb
acLLNDD/0t+Czm8vnVko0+m2lU6pa4qJXsjryEG6sEOcunaWVesIdS5aeUYpE5WK/NgvJu6tMX6E
9Aqy4XxqRyp6PhJeZoPRRvYI+GBJJYpOqgazBwLSXCFkV6BjxpGLCF8BsWhkAU0d4B223nv9ng4r
6ApN2XsqE4pydHfqG7dYCdDrCXC+AeDc8Z7XHScZzFHObvR490EneV/U7N39tqcwHrSxyLZ2jHp7
mEObhY9hdW4kXGNzhsRvp8jO+D0v3qN0m0BoYCytm/wY4GTLiuSj0vxAFpAWTvvFBj69rdbxe1Wc
tgNdDrhIkO0JWXYvkmXzhpHhl4zWHLD0jQHk1f2cEJliYWRic2LW+e3v5456KQmZMQegb7crb1UD
eGB9VQMTkMXjGvrhq7AzFC1bdz9stKJCkt5y27UJ9GUHicmb1c66UeMmS84THC1MmDAgAnZ+idbH
VRKCkKLzntcnA5rRKrHRSkqKUyOyMRef+7tJralI4UvE77AsB8Yj8G2yJXwnkpZ2rw+Yw1F1ln1o
wAouEcAVdU7YaPqnp3dw5etw9DNuDm6iSaouU85FIVA5CtK8cggERICOMJVuz2QkI8bl+Q6zO1Rg
OxFLvqyvSZA0LFIcrW4/IEz3A2N2SXr++SPVtclW2WK3KwtCJgdQm1JTwQDfyQk8IGifuIuat9t7
UMk8ixT/73Q/PbcUO9MN5GZM8aHHbNh7YLGeTD/wnpwKw3paGAVF/uZJntjn8KMDu9SJr/PxL2Zi
4S/ZArWO//iCycpvh1oKttnhTWJtW6qbmIG7FQY9jFlQNANMp0Gj4bmFWmkxiHbo58e7xueAf0nb
+AypHx9FGmQOlZtqjPazsfOwTcxsxjHxrJEM05IWaADnfR1aKeAy5TzL3gghFRMG4nGYccwB2buR
dmmpf5yAtKDqTVyt9y7RNEupgnr/6uu5mBvgGIDdWeofO87Ng3orak+Zl8JMEhKROegVEEL3rAku
p0jMxxRQ/06O2SlB/7PoNV7hjfe1jl5YiSpZg2vF70d/V6nryl6MloBrbFfTjRV7ys5XCJaFRxUI
5JPAdBE9MqIiv2TASddd6KiDeLmnW36b37UzraVgrymEniSSwuz/wrJrntuipOb4OmSwpfYABaHp
TeCOvzdLxEirMUvQ6q+oNdSAAn+54bTnk/CBvKS/2KQ006OyadeRyB37mjYJ30Yp+5VbiKKJtuTZ
LrNxXFqTBIHxjN6hrgbGhEkTwlTxeAQr6Bkey6N2ywzlY1iTcMvVN2zckQ9JhkgKaltmuwRA83IY
0AgepxcBTn6yk+dlkiy+hGFxgW4bQZrT2taM9EBWwl8bDyXa1/m1sN5AJFly3GNG/4i815KJYKaM
VOB6q5vImhPIKEHuxNgZlpd+pIHO6JqGFkW8TLOcsjEbIz68LO5bXF4C+Mn3UdcpYZ9vkqaID9t9
0H6TblYrr06xcUPFkddj2zNTeksvvbzg5VmRW5N1I5ofeC6xB5sXoM+SmF3fob5VCxDIjMHY7Oxv
Kt12v4xVdsCYTBlYZXcF9zxSjFNZvJxt8g8Zi864igaCoh+fSqneJBXMB+blmdb+rcftHuR9wpqx
lPodHz58XJuOIH0/iw1MHFmF0V/YiTo2wiqnd8e09VIX7q6XgOIt/1sHl5En+qs8TVDs2XlxFoEL
k+7juAO70NbWAg3KD9yl6UV4/puAnCtLbsv8DSWaFwtmnOoyGvByilCXSuBwsCYFG2cZUg/CZmJt
R/0GUhUub8/02MN8Hr8b5z5aQyeQa2LHQ4farHF8AAdT2Pl7KSMYTZONdnHZRNF9tP1lBNBfsysP
AMey4/L4ht37wwyWuq6ua9ea84gyVz876xCoGhtNw5XNnULJuyXsJF5huH5RlHV2d4RHZrg8jush
pKN2FRCYQZx3Qub6zIICc8Zl1hKaD/NQzkHkGHyD1qhyIyh9zsWVued/gc4Lsuc1rf18ueeptJbo
VSozk5fLIT5Yg0zhdZtrGUMyhJA6V1WqoJsvGv+BtB6qx5bb8Q7IAvQTLCu5JWJWNB2vFo6nxC0e
wWBkc1eLv/aOB6UYOJ2qfG/+zed2NyhWpHje9Ji0D7E9xLJo9b5SyupiLtE5oE+vn3g33z2cB6R0
NuS2IoidqHNL4y2Lbg27URuZZLpEFEYRL5Qagj8PdwJtXgIDwpI5gSFbSzaqb8MyazxOkjbw9xHA
IsPOhDzDfB+EAD8IS/b27C6MKcilOtKtdMqXdI30P6Lb+aAeTq/iDfO1VAF1CAWIFRlRtx3w4uRV
SI3O4sSFK0pGqi1yLQQVTmJxJ28WGv9HLLCyjIwgiH79Vp0huOT8mY5fMZME731aheXP2Qqf147P
gw8Zd/0BvVpfVSo+TtE9c2OTB3aaSJIdYBD8e75OcC714jDjr2DjXKXjvaFWQjf6b+iqLoaGh6Rq
vxCS8LNjyG5kxHzCbZAEHMUo5LRkZjd3/CbS56VXoSvVb5CGyGI03oJb2K7AaUT1PvohNV1THntP
3SGX5wW3fHj+cArQ7Fd/UNuYjynFFcBbix1dx5z1hbpZIjLVsjPqJqMXEgfbRArK0Mklu9ojiTz8
MEo8PbF8X8d9KGMkqPBLVMR946UoXoK7cJJHMQB7JVZrbe8PDd3gkihYafnXpUFy/Ta2lAzChXJy
w06Yc0034yYOey7WChxpRE5ID3vQJHD2RWRKlQ0VBk+patP/u2PM48MppeOHswtGeNoMOp+mMg1R
rA5rGM+J6KiLaCMsc6gGnvntiaod6+eOQT9n/MXr8Ed9i0Q2rCej/dnYl63AN2L8t9bWjUWZdhFD
4VQA+Ok2QPzXl69YfU1POLb5+X9gEtKbW17ad4uZrwaALb4YU9wUtj99W4tjo/FXEGnuTaGY/1Nf
H1y4wiWNz/GN1ark4pd8+AAs4jCtJubyYHjmzbA/MAm/p7IvYn0KPbI3rdK/goyBT3t4vb3P7Ve6
gsVMRwbkfPnZ2E2S1PObT2cOlXjZxnCtHDAaUDYNzqySCJ0583ILJMq7eUg1jOiTK7J477p2jW7S
qz/d4joT+sd8DkRcJi1ZU+MGnchz6ji0F+8+uYQex3eQmrMPDuhoYnMR9nm0Hyi+MGBe45Zy3sjF
MziG7OzeKxkUjMvp1zGENXVR8VsYjmp9Ra3QCy6ONhYwYeQOfEmPJ8Dq6N0Y1XlkTKSiMgZ+XP4D
Vj3byg1tuhoPq3FmySlv6HwugIkI6Gfj9B0XEkJWyYVEuDLqm66bOnE6QKeIsvumYt+SemPa18un
f5Rccm/2WmeWcsZnI/j56tTnaBGz901xIBWZFwb9EBCJX/M2Qkg1BUgLrDEabxDNi3Fc6t27ke99
JnP31fxB63h9lsKqEARXm3dtHqgR+ptShoGqBzazLcgbHmNtweCtXMbJ6Rw+B0t9FW6EphgvgCPq
dUGPoNoMMQbdN2eVh7pVEHLmzpEarFfDvWiItI+gfxGJK9dEjzKKKHLcmyYBFh8FiyvwJklZ/CKr
164grO/NtJGXTjmefu3RPHf/OoDRb/for8rQDRMzJl3lspMJ9JM1JTIeRldCDt8CMJYh+bRFf6ZH
CN7YHh8hWqZUYpltkD+FlECAtm8Vd4p8fElMzcbFYLd+W/lwuzL6kMqH1J+hLRiFymboOl4cgP8k
ROIglT2u4H3+yomlU318JyAP7jPlnTtEBHbNAsodSuCzF+dHl90L3qdPURx9xF31Y2LZrANb9NJJ
IEtLW8CgBWWKJM7kf67lGqp9LLR131rm7CxL6u4kU0X5d66hzhQewQE7Bnaj2Hed0G4KF2sVmxvD
mqj+E2sHM0e6Na/E59eS12zwmPz8YOlg/mrVQJHf0jrORlQreIv3B/8kTcepIETT+BxNt0JT3LLE
U8VgEAk7KFEhJ4Yn6OuhachBSia31zosiqfwqmMcyB/O21ggkVxowATstsiiRqOyR6ChsVYoqsk8
hMavr9tnnWHaGi66yZvnd+/1FD4IeEbj25e/iCrs5IYsegWdQfErQH26nw5o68o3bJK2lp1mWdL0
75aJ3CDRlZC5es5LGPrbAqlAKJl15hOrYhMawOsz8miLdAesy9ZmYeW8vWMsfZwJgj0OhztgyYIo
eVzgN3C4xhuAn4v7nRuVPwAMnmyz7ZSL2lDtRMVHe5VkecnBsSGwipC5b9EIEMcJ4OlLzG/MyBqg
MMPD/jOSdp4R1hIwMPYHpnri37QWkzpaU0haA2sffXKpA71S7DzQBq1fJ8VIP4++NhggfjeelJH4
VfoszE+TQZtNsErDoHZ9/xnw7z1GIEk1hKF6g4vQ2hFEWl0EgXUPtwxKxy1LGH68XWxcWhdBQ2tM
6TVA1QUrR4JMZTF7ckrzJxA/DgSaFE83t2OQINM6XyIoI3aE4efYerOhevG03dJyg5WJrpFEFq0G
7Eu/sz0HLBk1obfMqOrEOSRl7rKa37tCT8NoiLO1u2YtPVlA23adCO4zEIKwWLwxUh6fkM+psoYU
yvs/ebFHrceJEZXfROyLkuRIRpKyAUim9kHB8IbPWx75S/EGumR/V2+FgkPErNpbAf185/RE7U1/
xYcM95FOFUiGJdk2SSrbHMj8+8BB5DmGxmnERrvgmlhmkH1acuyKUzHfnH+aafToLzBWicC5Wv+f
FRLMMN10pYdT46+3opLIR7OEJxYQiTx3nS+fKzmoUBxxFiGKgChowBDBBbXFWR705+hOeQB12f1n
hWSiDS36U5XROnS/PLtMlg7Bi5nmG3zAvOFKmhQmqRS32y0OC1+hbJMejB3wE2MEaJp202QxO5dw
2YFUjSmMgg3pEcws1unVysKEaE6/Gml/96Jkn8oSsbfvSyDjIi6x/zKbXq2Q+1cCRZEpHRnQOz09
mN3oKaQLfYR+/0N25O+BMaCpSuHKNyCbkwIcS6Vc6x2sQx+Vfle4j6f6E9aJYcAajCGOURlwCOm7
l/is5+0DPxcDxEn4YxeUk7B2jqbroNcfQXQZ8wlHBurqa8I/dQQ3rIcRpDri2dwlOE3jI/PU0nbY
t3fi+t7ZMOM2FvDhYKKp1vLKLhMpj5AOBx+ISophzAoK7wBovN1gzueO0rLyUWDYtT6+YbGMj9Hn
rrfXGYprnOxyJ/LZytvsPiMfNXi15v+Sly6DNHvMG/DLR5m5yhlTNvcMoNIxJwnNwskMsxY1E6sP
PNmuOKkDKEU1/D47q6QVkRdeB/wAVdT04vB/8/fm4aeDt9KyIqvUBbvHYh0qv3MRifAK5P6Lp3D8
fcboiYwJgcwXFzJ6IHFSIgPOO2Z9egPZxbaX9zyj6dXXEsNvT73yYUT/9Be+6KLeFU8Rag1P1HB4
NP/zi5XvYx5YT4c6IOla2WXis0Igabl/iYjJ0ikfnb52yURBMZFj5Y+g3ihIo4fsXxURcij8SBXl
VMej0vV0fo721y/5+rbpev5VDH7O6myHM2SwMSSFYj8IWUMips9e5ndzJgPCqRYXFlbzPNYTrqUD
j6JCnyHW5oy7eUrP6r45q+dTyKSdytMiRM9UZqY8MkxTesQXeaAP9UKSXUEHx6aWSfAIKTw1Qzym
l5XI7pOuP2tcpp4Td4W1UWGFeEzRrAyr/l0QZnpgLSIQ3Q8KnBPIUdpQGokYQDtqnj9Bft7VRsjl
KQAymTuiFqyFUCH75hFkL8o2Q4NVvGkdbOEd32TUfBXGoI3urGZfYitnf4rPzjNH1FXwXIrBdb3E
uF9SicVdH5YFHo346yvEwxGCchDE0R6kp6HNUDTbgF9iUth6WpBgGXrdiI5/8CDnhG6ZODmFy4oF
MT9BjQOXpQLtm4XBMCwilljArR+4rrd4clndL9M8EjcgvJqn1DLGZfjV+xp0YiRrAuQdWPLoMOY4
3WR1nlQ3OXfzrcT9ouXa5g9u1w9HF87r8tkqXEvzBRpYiDaLaL3wQZbd8P6OP7fJRFKOOVfb6vDZ
2dCBKdMLGsi1yCq8hRc0upOcGS1Ug1KKauQ/3X87tzmlTeYq9Dm4zo3JV20Ih3kplhfV2OxFn5RV
5IXCPoBMeTKTpDvv/WxP8FVixRj/EUnRYjo0huWAu5tKRT4+Esk/ROCVQ19a7llixBYAkuxTn2D5
Xu/nwuVbSfMHfIkqTxrUi2lCl+e0g48nS9vILTayk5mRgz2cmtYqxlxSYRLW8UNCrUEgO+y/E+bn
JKDGOPwcYO3EGhXtW7MP3QL4cmOxvFUT0H3BFrz4UwYLqycEyZOXj6fiMwHIB0TSiui0OiNGguiM
W94sOQnNK4G+ZhttwC9HMefWbYD4F1La69CiFTR++ZObTmsDhfxM/dwbTYrCk7aotAk6U7VrIGt5
oZ0b9IsIxjNtZt9wGQsKoJaU0lXNbyPu3n4XndOoqOHVZwn4Dfb72F8HDfE8oBhQ5DiY+bpDU/Ep
LthQnnHm91yQwogU/6H/WLVAOL489HVN14Wnl75lBheKtpqNZ52T7x9k7AZoVKcVQle7yQYycAkG
R6AJA7h8tMZbWScPsrsz76IxArLj1LsndmaajZzivBXOLVh9Eea0rTDl8nY2BM/4XVTDTtJyrbkO
Lz0vJI4qtuMLIYtl6HHh9/851D9w/AoXtN3yL4n7QN1vwCnPMmCo+Wsw5AOaidRO2NcvKOtiT1aQ
TF29KiMldvqsblDUt4/Byd6sTstCRbNVXEujc7YW2RLlURem5tXiVDC7MVWNUILTjqnHIuAkVbgp
lKY4CWs3O6gRH6BHV7P/lED+/YcxHPCzdRdkISDoFP653fHuqX5sqXwBF4/aK93xqj/XjbKy/hyf
etD7pZSptBDWDWCth8zRo+XA29vshRtfZv/rFHDmtv0dYByRNDXUAuRD0YeYuPwNApUX/9otZVII
oSR3q97nlHsBmjhG5JhaX8Ey1k0+j4a73ttk+Iy1jV6VW4O8tWfizgfhLgFB0P6Prm0groVHhnSN
Eei+bpCF1wj8CLO8XDWES3fYSqoeXFhqlIGo8iTMg+YZnbc6Upnjq4yo4l7KkbSMWeZMQEBcjZ0l
9rrsoyR2u+1RSzyQtBLsB+TparsMXjYWWySGc3Ige9eMwXoVLKZ2tQMwcOYDkhsoP88abFWyDCul
ngTE8mem+RATMrCCk740wht3orCrlUv1RHqL3f6lLTJ2hAubQmr0ab7F9EJjwnSx//EaG/trK+rW
8FsoE+BTlxBAT/5l05bxBGuF1sC/wyJWJjpCeNtLObpnpuTdsWLRkvtcXFTOFUNw2Y37JvhJAS73
mczzy7nHncLLk9sciRRzlA82UuHykEHVkjYuj+xSS55Ao6SOHhsuzXgstoBprdWUSorFPZ13DdRb
Pez7QYg3zi1d747dYkSQN/mpPN8fLdpghXCxdDHKSY3nZDu6fgtCzXrzepno6o8KlKJfPbGKa2/t
bDIf6zz0kGZkITTZ2ThvMAafWJLiePHepnOfuEZDJU7WR0A+wZ7x4VevbPGSNUmcG4rz7YWXWH97
pXMKM0lT6txO7n/gxbmOpx0dhE+aIKN+Bm9B5RiCRV8WVBfWXWpWaMh9+EOyuw+5IxzcivEC9JER
C+iGxBouc5eRM4YIClnPLfF3H7D6KZC0PQr7yYOltqv6unOWUAjYih3baxFIgB1BcGoYYtVNMqWl
K/a+w5p0ZRwSWOtXdXTYT1sSoKLogZxkNKPyXyYApH+MJZ0rnRwtbJvB/bgsZYb0dr+ofiNrhY1I
PB+QlTTCvY+HjpyjC7k7HamKicnL9T69gBS9fIUT9xCnZ+nocqSeq0KrMikMlau5tKMJFfDbZW7i
gMYtmKHckieOCyfkQdMJtZG69oE3z4UtJXc7wGecs1ds52Jlz1LkN45mmMKnvnI401ywEZo5pEcg
06MgbBlbe1abdPpfIFJqmrBFUmK0EiA7ogdeCKvK9MWW9pJMCsBW7nNdmDp2QyKAMHix+INHEAmo
Dk6vM6Ad6wGb1GDpdgn0vXXYG8a7CcUqaY8KAeCBUZVupkYZ84XFWagQGC2oZ2y1qSueXwsIZwg1
TVlESJHglsJ5a2PnCFBrGN5H3cmre6YSamQlE9ZgKqCr5W0vd2LkWEFcr3+yMfIulZFHA6HpArip
2r379PjUQSMck9d881KZxLx6ZgowTFT8OK9VMPRN9CDO5zbd3VFhAh7uzuH/bxZQ2Apl+Lr9yYdq
GHrDsiqHs9/CLV437C/et6QG7t0u71+jbSkfCb1xKDBLToDK+jUWIkHPOcnAxhhwhfqEk/exAVfA
ZAFHXwJfKe62hjc5Lnj4+kpu2WHIBh9rP+tYfB4ofOHYp9uywt/I5mDicgwJsciWtAw6twv1DyW8
xZF1+wpj4Ll1Xj8+5FO2EIreofRLTwLhON+aRxL/6Csa+6anrhqA0lult5HJzPzGzWwrGPlnGUBE
jAnKSm+Ph2LLablzoHBxeRjEQzmkFm6ieNuyIGQCo+/MYWQBa640hXA6y4A5b1oYcoE2MVmqs1aY
8A4gZ98sSOMDSnMef7fLYSmVQHrKGvR1UIR3x6Z+LP5H+bIznbQxm+DDuLgeUbftr7KTtAPpwktF
b0/t5wbX7f16qCibKXA2GKoGPXc9AJaoaE56OR5Jl55vgTFUnLgoERaqMM2nZ4vCVmKG++r37aLH
c8Usvyd/Ovqfv7+UzkE548p07G/l22/B6cx+f1d2gZ7O8Bb/sUhcM71f1jYOlO6wyksGQC4XLqOp
+bwGDygKAOVyY3AOuy6op7NBK9gtkSe+t1MCWiHp/WGYedykfJpvBwgqHvKkwEbz58s524Da1QAw
MbXms1ghldrOJO8R7r4QuTmissB0i8fAtwR0jEeovYYvmzR8+e7jOxg888SUCu5Nrh6p+MgmtHCR
/9T830hTGtYpl4Vczh8ylo5rV6iPVyxehAf5vDW7FYrZf3EYeTqoCJJOi9CyohRqVfgQn6Zk5ZPJ
vxW4UfRuDMAzyHO/fdtb8SNJUAePXeN09TwIpKjhfLvKfXmrAcRZrLZliSmM5OlVc1QvS5W3lCkA
ezmq8FagVCByrHRcEztvYaTfsjE7vufzrkX19feMxLuK6S87x3Ou0Ny9AR14M/AoFJowtcW8zVne
LwHx0fqfc/dCLvfB0vOAOYWJ8+GTqirda0el9Dxzv/j2iHhG1jjb9Zx4LxVNH7saXjoTnKqaqalV
ELw88KYXH8PYeZwni1/AmzBEDRNuLa/l9IfebADMCOlSAUQRGfaZTPtrWALwGVHLkk0GaspZ3BRf
TyS5LLONf647JwLzgXu8rmQufvmnmwSGaHL0l5sLo5yotTttdQOMm4L2/GdUNv2jBIB5PukB7G1R
EpXFP2blqzVcyOI0uPfhhfY//6PciyuiEO1nEaXmRg72uQ1yEVTHJAp80szg6fmDUn2I2nGQ4Ave
D1wjgRB4KiAHX9Kmcpj0O/AK81GFHdl1oQrvLPeRplTs0IqYOkxU7VnNCNOZME0Uf+5SZvVotg6G
3vRZ2hN4nYIQPnjiSa4+qDAqQPa6hwhlhqZHgNutlF4DKE6DKJwM4ZglQEzvLXs+EMmvkMd999ct
wm3Z7C+b37g+e2eSVXyr0/SWT64V4kjkzEtIvG1aRnYljsmfwlcEtaTymIExjShAbl+Pt3/hfhCz
1FTZpZ25y6TVFY7Zceof5xz2brnirE7rYAo+n5BHEs/f5c+spapAg/0sqhI0iHTUrf5oIRww3mVP
KA60r8Su1b4HQ7lH3f2dGFVUi2DSKGKTMjNYIesHznep7c+4KJYo14ODbTjqvLOp3qXPa1cQTn5F
/D6WXe+zhH2peedUZvjN3t6BPI63NlLwPpSJsFroZPKZVxEl4lcrZYbd5YikQLsfKJiT852s/+0S
T5YObJJxp8B7IjpfMgVy3qMi9ZETKT9wGPjJ4KNOLdeN9XKgAYE71IO36fDH+G3O9s+UBGmWG89T
rhf9zdAo26mDVzBgoEZOfUhnNgy2NosbPaHX7YuIIwQexB0vH6V/M2/Nw2ygcvidayIkpe0nG94+
cF1wkbTTNXKSQQYicRIiR15wqz1wA4Muk4gO5+P4xZrJsKFiuah2G58pJUPoQd5oOJrpHSl+Dth4
PZIspqL/zGBRmWT/oa3vNAZa/DP25UlTJWpgZCWCvXXJi5QucwYgf4DILlamoJEUrN94PAcwgvZ7
2StWb6aR5Q6DN5YUcFqo049IKLBdnCKhZVcvEZcdrSizcl0PiRnHlX9a2WD7+7Df1KAw7b/ikb1l
GWP5q5YCOfxWTxshKU0e/3h/M2o3sK3Tfec1YBYfC/6N5prn3W1z2T8wbnuyQkWvX2RgJn+PbRKu
juyz7V7gsMI9aNFWdSuTjzeDy4LskGIAUXA8LohJ8+9g9PDorTMGEQjrVaKcdX08JWP/PhY5iGhL
y0nVggVe0GkzbCcStCpKRvntltcqm+NeSBUhDo6ukP1NreGtObBR+wX7Rog79SH0yPFUhfcMO0KW
CLIDxeZ7ei0riQgtC3uoiVq4y0jlPT2Q7qUAqkyhVelRlXBSZ53eX4zv2FPIG6gs2k9NuwoWQi55
wym93r85M0P39qAsy/MHP+l0vh2l+dOphLhzubWyIrtwcIHXI2wQ3aC5MYiWXryB5ATqrIX/uq/2
jBEkHX7kM2UN4MBhwObSyIEi+Y31zM+sTEnDjTp0neo6F0dINtRxXFcHriQglto5nE84s5ZVNM63
c/K+iWvVIXMVQWAOzJF7Y5dMyKKRrSgGPGJojP6cvUKIkC9YUE6++ADTTqtfbz8IAVnTc5AVzbqp
7hbxFddht3AnIKmhkjRQaJDcYnzGQwNR1rHTvwFJHCNcczArQoAmsHBv3TbnxnnKBPX/YUVrD0t9
M2K84w+aUmynSKHs6mzr3qELTMhDKfronRs2Yv9HM97Z5zrOxnvcwvytT9LFWNHFmOTXNOiwcDdr
2YFlloOMurVErcpgt0G91rVbcCKlppreP5pBI091Ln0+snt7TOdOs1JAs3UvmeF8SBt37O0Awaer
yhofbnW+xxN1vzHu7yHlWpWlilJ4yout6aB5N30jgHdiPAgzL4ZFYYoyPbw8lOkQSIaaMhSqJ/Ul
j43kwHOhKye2L6EcUarctmwrVQ7/oqQ5vCIHLz3P1V8CCea1NTgJ5gD1nw3/7YL9qt05XuN/heaq
+4ounObPqPLG1t6GcwaHcVDJ9f9kKuhNF8wxajAkT7TKJb/PmZ96OcMWD3mXIoKihYyBRak8qEXb
ijQsRCDyAx3vhjQGoQsxpnsEYsAXFNJNC0tgMyQFwzSTWQG5ejhjeadlvEFqBaPU0yFo9KNMndSg
Lg+ORw9EMNKGOHLQTTbISD2kltjopqEvfhmvz/fY6XOxHO3/KJJmcSftg2y9QnN+G0Xz+x0TnbmK
ZMFYFUaw0GOaA4ZF2VmRtKq7gMWXLl4LGoq5zaGusHmHviu0w32m7IRTRqDAxUisyBljuIByC/ck
XiBq0IteHpJ/3qccf/Ge8HLnn3SK2Xo7hrXEDDsfp7EuIP35FAjF6BxVKh1rfEfjs6pJjEFYrWPj
9mXd9mFZSJDWn5eRo+lGhmX9XDxwKvzSumjpKv8cOSALb5PUD8xbx8du3IUUC9rvS6iAD29vWtpe
8GYTEKXG3px3JMqmxotu47qgCAeQWfZaj+aAQgC5eyS/XTsmGoZJ0HxzAlhWFkynm57S8+j+boJR
W6hUHMaPWIEKxtcczxi70GStvptuImXKT7yeeD+U85jnTj6Xv9Hy2UK8wTYBn8LDCqYVi3sSe5kY
Dgys16wD4i+uEJi6bpfXklU0kf7At9ByMw3H9mnalTE30Ocgk7bXjjYZ832arT9et93dGT3bc3Sy
D5PSuXtynZpmzsWZgRAVY4jzvbLPiX/b+fn0J0y0e0uS8ce34C4pTPWhm67+oj0x4bbV4RmteD0R
3Mrkpmtx5l9jvIpF2GIj7uJ5TThyV+a8fkwPYA/tsoG5KJDyti3bWTW1JQPPEQDqz4ZlDBV8moe3
Eg+JJlFqAmMTGsQEflYw+s6OeyHmKlnqS6pZn5UoCKNXe1edwPyhbpDA+HQck/G+2/N70MdO1ccG
hRmY+1AXw2Foo9giEvz7Gw4lf3ik0KJ6PTAGX2VzVsBbH9S8DQMIeqmYTej5+oamfud/gSoOA8/W
Yqed0Ml+7Q2TUxVoZNIfsguLssXMV3mzF8v4+RY22LCbzrhlSb0PVG0xMsHaM+4G0jnQ1BUey8Gv
17+/4GTDv3jjTqLy50g3DbFXdXlvPb8whMXfi+t+FH36SzhP4Re13YWkvyIfnjbdRFVzErFsPkZm
O21wwx8GOMQWV7ptO23XxKk2+if2pVk4XDWH19foZnSzcodcUusBE/qpAlGIzjsgdYFr7vw1LyO0
cAghYsbYtRyJzXv26WkzyFZQ8RboYMLOYymUjYwQzVE9PBdwoqPvIIZj+QmZrXWaCJyjmq6ZEpcq
RE0gwilhPxzf0uFnjZf0lOXeenbujOs5SppM6rENHXbLpg5cfN8+UCwuNbtqWJTEDZvGgj8pmcl8
z+xUtBLxpS1WFqBsjbCJfo16q7hYD36Qsk8fdFD7PHXWLBgL/MFIAJ//pA9jmQYxsVQqIbYKOUYL
WdMxuFRJs2sV/IrZQf6OfMWIPLAFvD0j1Nvk2o4xMUA2ChtZvtZREjvtSOAjnf/GzSOfk8z7pEtJ
Ad5YqxXi50kS+7wTylREIOG+ZQntTDYAfnozbAyqw+7TWgs2+Saj8p6DqUxltvls8eP3RykLjtul
Q2/ar5K18JvlwCLq7CqNjvMZ1oIIEhkTLhqKRYePRItAxn9ep6aQmSFDGC9SLR0wzyUAAIEzWk6Z
FTHxXkhH160d7dALjK27dIMbUGC2kjxEDs5TCoUc6sdKYRC9PxfVUSmwbrX3C8EzJ2dlQeum/6kz
0+epPI0n4MhAb5zw1QmS9A6yYtZZ81mxrZeOGJbPhDlJ42sUGDsQAyo5aMbStbZFVtGSkB3xYXKK
F29kjDwH/xYrgURNbzToHILQRW/7VMNVlape7SsVDKuRhdVqPGl0Ao5tCPDsuOBHC8kqkLWHYm/S
IiDJ4zNA4ycYPjLeAaL/DRXV0mSMkGdyovey4jp2/4ieN17pPYS8HqKVsF0hI3KyV5MPOHMmE0Ij
ujsGQR2sdemruHtY4wcpNHmMgSjPDPHZc/GVRHGlbNDm7nZArio7xDvb+XuaJ25dN+GmwoucV8Oj
WpfxVbH5vthKLMvRN3+BWfBvURU1eOBAKWQD4oAir2MPJXebPCpFHp3OKt6AY1uZ4G4j9BSV6wtu
gOhtPxVTL+xPEBAR1RpzQ2LdJNMiILug/psdoQZdO0EuJAp2or+6l8eKWRUCTd04Kpz5piLtVY5b
5MYNt7/fMd/6pF4iA9eoBN8yjZ6IaWEJPT6o4ZjFvXZn4+2F82yesRV3DL/mMkwGL2f0lOeNZV+1
+4wNT9Ty+DxdAV4MB4McZiCJ/XFG0To44+NIQM/O1RPWOB6iP52tvCpgEyOC9oe9ul9HEdvGiHnV
Wz/UDWfQJUstIO8M42Q7Hs46U3M46Vsfs2QFhX8jUnoyBe0fU1cn3zAPNIeDxRLZVmHgk+cvOIOl
+4EJO49ZgbU8xAeCt0f9XcfB/dPNYjT3/OUxZMvb2yrT9oB7l+8aD5qZxDSiNU4xnBKUa3Zmmp+7
+uiTFo1oeTAtV64vgmlTuCamrbI326vjtbaADi8PJRYhiLMWMLCUFTPYh5sCgd2bSG9hymUaoQyo
SmxP0ld3gVyYhzdQYsy17mVc0D8QltFu7AhKMGfZom7XlzlXaX4dWohgKzGsZSBdyop9cjDUihxj
/a1BKTNwpPeGyzG9KR1sO7HsrcgBWsHpDcEpWwGcG7gDtxuj+UrRvhvrYJuN4YhSbsro+dIZpgru
3silInvQTEyefeLkDkG6SPw8i5LBBPFP/why1HgLR6e75b8ib7RVspYwpW+24KSG13AxH3toFEbK
gNk4yLI2j90VyMZk5aI80Lq4pmyz4D3nZeCML3kZ7qjSAz8N8xoDfGgrihwJFXtUoIDTfrJblMvJ
xIBKuhdjzAz4t0NI3phMdiapfjYHMMDADEBI6e+STAf8nqfhOQdAtEc0erxmzimM/QLQtf2MZRSS
9q8pY/94WeKWUq7dn2db+zcIdb0WgTLuzdDN9JiY8zohYa67CPtuKf7G8Ll2sU+FEsE51w1duZTK
lJTr4r5eOz/FUcUQAXY2QnQnFepDRpuQ9aULEkZR9pIADkqAMmTWYMqrk6uLL9fkNbKgsD6oNZVC
IGaUYSH96dJMna6dYaLtnBS2AmPUwL4DaxuT+xeWYHBfY8JX+3EtVTPN/4o5DUDKJx7qngpMYJ7a
NSUkZDDlGK8joJMLfrobWGu2Clu1aoxFBk03ngT8h/Iepepbfbw7++jQdZ0cQKbU9sNyksaqsj84
Ss/ysJBwSaEqH4RVgwgPV4vF4V2n3A+Ix9WgAarct2ivwbr1a086iI9N2teJXMzeHsMw1c/IYMa1
GQDZDt7IeCGObyG3MNzZseOAw13ILo9TF8V4x+USgm4XMzzpCrYks+enNB5D33P1XnLDSIYX/xZf
NGTu+pj/tmrV0h2bWPkJEHtp5c9EfdMRPCk/PoHc0qKqcMz05KG/OpE8wCL7K66+paMlkKoo09fm
BQE8u0nbNbs+6M+fLIWb0rRlvy2L3yqw9GBHorEF28QJv9aKOaeopcHkeH21jNGCYKlcH1SPJWgs
pM2pj3+I8UDqxQPt4CGzhOEczURnJlmD/6YKF7T2B4D5jkrDSuPsJsiTEf5AtfaXuXx+v+xUvgC0
3g3ZsbnbnsvmJxRcsvpd33dnA8vLpPFmzV7nR0uRzoDHNpw3Luq4tBC5MlnVQeUAD2nuiYbUzSCj
k/C6qMvBWGiidblApGod4TIjCWFKR8kcpoG6sMU35gBd5qg0eR0Qv8wES8DAQNnm6pMX9MmDK9op
PVRC4Oem9/wTkXDultENNc0rc163nl2v1sGgdPKStDBM9e5Md/BIoebaIT04YUUa/FcqpQJXGHU8
gKx67z/S8kroZtO+WfZjK9jvnNnkJwsXwoAImEstmExwQ/SQwZ3rixXylUsuhPS5SupOMpQ24Cv5
7Wn61PvK00I07of1ZwmfyzZIJccmuAWr3/T25yJ3LhBialtR8g5oZey8Cxqc2ShwpSOw9sSSaoBj
8MHsfB/PYf9BPjimXq3Z9/a6Tsa4eIRmFWazhTz+MNrMB/xK2jQKXDPMH/KXWl2+prZS6MS/iAs2
K0rqNhXwLomPn7M18ela/+99GFcZ4KH7EOg7v93yjCw6R24jbB0fbRqP5iQ6CjQ+Px9qHNG1suiL
rzkpB/+Bg5X01k/S8uWHuaRTvwDoYRXYR6dZag8JYT1Pv4JZD7h+ZSNId5pH5ierfDXhfxQf3oHa
DeT1yUCQfpeBwIR+zTTFmxJ2pPel4IQWVSUWs7oDSib/kIhKqHWfZipGcFMf7zeGvXXqTsgsgc1z
1o6ZzsHM/8ssqyt/P5qy50KfLSqD4e/noqzEoElldOzb94VmYwwpKYqCWW4dB5opJmmIHmDyP//z
m/kad+M3DztcAx0r0h+8P4KmQ60vGH9JHT62exRGx/D5kY2ypsfUnFBy9NZpopjoGzGsaVyS7A9O
yBKSr6gDCrlBM3vc3u6gS68daOIpvnphnls46JuGL74uLxhvfraeZqfi96vXaYo6tVM68VFwdYhN
7BC/89ptwM6iZp4Mxm1qCj94u3Q2MiTw0VmFeFAD+DY4+HRRpdrEsPTu13BpZJcY40MkFbyotdpK
ccLxRf8KO5Mxj9GPXs7Xjk1YXDRGAs686kkK1BwW2kGzcndt9c0PKP2eOW3pGRhqFVFtIK+rE26X
QjNKT9T1WkkGuaNWITyVPoG5z4Tu8BA5DMPTETDq2jQF3ojpWIvHmRJZbZISPYi/K/JiSLhP6RvX
Pw8mjWZSYpCDfWB3uMCVV1sTzYh6FqnlJlWqZb1nvaOv7r5m8yHMoafrqGU399EkNJ4TnF7ohw+0
ujYBKtHdYBpviXg6F5IGx+phcSiZbMJQyt+6RTiM+D1G4Ig71yfqN5CNeqAWRtYe5Gnxa2eyjR1q
0RXbumj5dfYPuUa/HBvTqkIwRAb9bHFjJVqbFFWaoVQ9Y342brVunXsRnm8s+pVKxmy4mc3CrHjE
lVRuLTdJnEgEKmvGhGFpyoav5/7uI0I8w4m+P/co/fC5ULFw12RKDErHq8Qnwg0/xV32+Cj4e75u
evIhh/SOUCAo1o5M5inL7Ec4pzkwCOKgaIDWIlyxson7zC3r2BxRNgvgyVXvpIAQ49tStRFNeUZA
6mMuQ2kD3DBjNt3tbI81qLHu5IrSXynGD77PJOt05ZlNJymTN79WQq5jUczIGxis5uXu8FrvWu9O
rf21Km7gGBnuvz590tILFcwV2gedepwT6Ir/ZXC04VxCcBvK5zI0z4jDo7NM71qS/aoQH+Xazvew
aISYD+BszqUt65npAc0sSuy8qu3W5mTmQIDmvrUm9YjtFFqgYNcLfV82nkFtzeC11f+ad+g1VLkV
pPJLFrqzN9zsVgZJxDt5epvsFHJ+Q0paQCXW+N8TCX5ETv+eEeD8pvCF4FLgutyQWWrpFCib4Clj
sqU6Oovv8pOvc/CYZ6srTYUsXDFrKItofBNW7xovZBvuoqX48QzEJN2ptihyZ3qA3vNFZQ09VH8g
07eCj1dmpgU2Si2s7yzF6TD8hB8J8QksmymhieQyIQIzJC+5kbiJAQyZaHDd8yZDzdZ1ccUtScBw
6aiYqF4rg2p/+CvvKFvM9pU2HduCYglyd//Wj20btIu40swN/+bSK43sh2Zv/PW35FUm8CF6Ds4L
j2JCvdY83cacgUvfk5LoM/WDoFkkaorQ8Jy56UIGWU3HTEt/BxvdaO1WpeGDeRjnwM5xngdeKfcH
d8OiWcbBps/pCSjqE5YZlcAkH6EGlqG8vw/ZyIooKAiIyxYMZ+3fQa2CX1mbXZjFqeTGl+oC7EJS
zMRBLfFCZk772JoPDOpUf8nPufa8jd7r+kNuZXYchv3LdfjGdca0+E4ojR+u8qqWB9nx2gO98Tuv
HbawPscIF+F1YGC7Sko+CRKXI/qb0YDjFksTzDbwrKmyxGhKnC3og5gtVjZMdTN+s1JX+SeUQQWJ
tTFdN6iE4A0N1QEuCMYHfCUsrlbqEfRg6CJlInxxDcV+qqQ8G7sqP9gXv3xbtB8E+5OjwqiEy6VZ
v+c+Dx3OZmSKPFx86WVioVGdTRWemvQNzSmDiVvAb0Eu0RewLJ7O026t407OUHEyVgG2Jr37cH6k
3swhHEB5ZFCTbHv9v+A9COSgING9EboMrMCvJasUcU6WxFEcb9FUFOndAiwJ1kAxy8LP2908S26b
w9smkxzdZta4L6fwSPE7JiB3txe2TN5yq7IZdVgh2L2c3MDsXBqRl+sxfRyRy3uRkkaYkE/0rTBR
suUZtvmAThhiBin+xUrLEFHOPdwASB7l/ns0jxrIumxUt/J5S4Fy5Nyx2OYqEpYzMgHrMrCcPSOF
oY5lUWH61t8jg8XTuIxemZGegMIHFrrcPikYQ1F9udN6sYO47PUqb9JXItGbyLAhS59TVD9IQWHt
u+daHbsHM62Ws0vEoqhuGIWY5N9GlbhRH8iynxdLuDqrJYnn+cdtImxWWQcNdw9kfRqasC8pG6G5
AiHl9Iu3dANM4qc4mnSFYxtzAOsd8RjWFcB6h5n/USOhCIN+bVcBb++WwlHKUJmNDojUo61dHO51
sYuFSuIIzr8JRKDINRBWaZ3VFEoQlecZZhrE/4Ci5Bc9TPpvkU/6/m7kgJKYKwBMjFXTvndofLHu
TfJN7YpIWyieKbjE7osvqzeikJMHP05q7DH7FDhDBQDcODmowmAomeu1+Bnlp/+zQZVRq7mHItcV
PJrEwGPhw9jVVpSMGLKX6RJWGPOuNnpJoHrv3IYnPY79fKLKnOhCzvfAB0qmcsmnV+b2NhLB/X7h
Tjl7jhG3amBF8CymXdHTXRJiyNjQ6R+PFgr+m9tUpOcNK4W+00JGSmBcN06ZotlPympk6lGnNZHA
sAu66TlKsShEkyrapc4Lu7dPvQB3rkwI249gb1NXGeriEt19s29Vg6iJUB8ImywDW6XRQ8LokAlH
IwYu9nZ1ymYxUcKvsMW78DGs9uugT1W5aIELuKCioL48N55AtPFJAAT2n86NBVRPOGjpmRBFB44s
dLLsrpkxnJDWWyGz/bzy/qw4oHMP0LYU+gmSuReEQRush5EhYu/5EnbqYAteKb2vahdPBBK1zE/+
2RD0SobFfA2gHLLhF5s63tFnwiR/qnwnsZMevnvRc4Rvy4CimQs0tz0EnhioViQsjntTRXKWMzrX
aOBTpNE1ij/xZajkSM5WGD7imeldKc8x7WuP0NXCim2iBOUhT0QhvVomp0ZW0mHQ1hvEfhzkYN+5
YX5xbuVAtA7a2mS8uaFgAJ6Ij0nNhqTxJnMpNUyHgGutv0Kx4uVxCZsatqv/rWKqMqzKm6pySap2
nCj6CiqGAJbTB0Q/+VcGQJy8HYwLviJfaI8xHN9BxKpOasJMiCYVW6dHacqRk+Eqpm31pbO3XiZQ
L3hKmVvHXDeSHLwkVbuJMTm8uhYb+1i4e6FocHZ4fxSZNW2LWBpaCHPyVERELA0e8Tp0vOh1BOFt
YxGe8fxdxTXo3xnvlqnOFh/HW05elwHKbnbxt0V0jPS+2PeHprdEq4oY7BaWHJujfqoC3RWlnoTQ
V5fJ2DtplOQcgt83zTfRUb6Vs1ipirCoOX0Qvys73hU7EIHn2xR/AzkOxXl34JnAF8lidC1/62/C
P18Ci4nlm7UJqohgZ0qJOb6eA6pzj+WmIFAXIby6L47lDBuHebPEi337TKnwyekkW9+vqkB0aqWg
685TFHeZT165UsyBwMA/KvYWaSkrUgnUulOFhUqhcPdEY9a4tm9BybmZ5CC3YEiIG2cNlIWMziWH
vLcnTzd0U4If7bbOraD7rTE5T7BDc8hVSXdFSPyKSmGx0d3PGhCaidp0eIxBsuzevGY9MEkW+WY8
+ahLVvjPIwgxLhY6G32ZLcLNCQLqQvSkVRVarhDbMLpJkp84TVb9+e4CLmDLcB8O14DpSQpk/Wtz
TqQNRi+fMc5v0OQC2VRiFXjwnrpWFdPLpVWHegkRXhCpmMhf+0DZQAIiSimzN2H705DUOG+PduDV
7+DDa8ttbVtyjBETyK8QW3aBcWxM0sYtweUolzMpUXUOBc0ceCUbeW9g+QJnFCinSLL0Ih0gEbxX
Z1FHaFYqLUy8Hweav4U+D/DvyNTLjbm+bxfgxOe+eRLCnotGStclXtyoSO/dGwK0MTjn1wcnNFB0
NNVEVC1CXXVnueKrCiruUWquDyjwRU6TE104uDERDz9Rxy41Tm/mioSYhHpeZjAfdzS7QZtq58Go
TVTMmwJC6QiNZbshfi0crOeKx5p+nV5r2IntbVh4o2oLhItGchW3YPPvcUiOHYfA2v0Ku/tE8EPS
O2mJ4npn44FSUK2UVkVcMT5LGx0ukRaqXFqRK0R5JDH01owGvK/s8UmXdGSoEPne0ZuzxM/ZMkxV
MEf1wkUXbqpBRtRw8+crSnAgcIDCLCqTsZLPqH+US3clJq7K6mmRFcJZIOHXS7lHtxqSsIgdkqfP
TlvxC602lccUnDU8IWnh4NKm7k5ekRpUxZ4Hu3pz48n2j7I8UquVDcNyaZbh1SNrOWc/16dOEhMN
ItXKM8CielhDJKPcEDEOjFzacmONv9umtPVNCfyfo8e+i4K9mPntXWG/i64OKRopK30VGUIZjNHZ
Co5nfCdlB9saiuv19XwX5sHTrAOvl3ux2kE/F2ePs+QW0ysGdRuGS3Sftu3QN/V2S2hm98DJaFwm
PhMalMmihqlvVefplWebllrwWrXMCZ9biZ8naV/b/HFms6NliFIm+hvlf3zY7qti/7SzY7zjfmq7
YCFnTFz0QwEpVFoePhtTqYYOJA9Uu+XjplmX9T8h2bFxMJllr0RgbrBNP/iLoJwW3dpwa6Tuy3x0
SFwHoHxhh5f6QSC1X+9mp8I1mrcwtvLgG0wYYh/Q0lo7EQNvGeVOFV2KBZG2VoLyZE6CYpEhofLP
4WERpmKK1UqO4JElTFSaiTZuZVNBaLAvcaHNGsLcfogn5ZtjQshMHUazN/HZloGAifIb1Yv2Vvq2
VJWo3mgRuBlP/iZT4QEeNAXJkUmnPWiuR8kb0o1iC72/gyBVQQSkTwDzU1E1yV1d0jtIqSAqvuO9
mfxLvBNwpSSmjxxZ1T/Id+pLcX/1julDP/autLJzbj04u2ota3uPoLaNE6vCtuXwwoBgTfS7pP/V
Id5/zu1Fwq9g5AfMiQDKZgeIvH6uCOk/ecCsxzwF+kj1p3UYpPTUcfuTPSYX/TzfoV4Duo0JQhYV
BNKIzc6GasKD4JCkBn4/I2NNnLJNME5qGFHG/ikwBSVqqlFIgihItyhKKuRqrw+8FYxwyc2tOhbC
RT34Wdyixtb5GY1klZgPRz0lFIhYC6t7uk5YHQsCPErcYLmiaEgt7tqZLPB/MTw3LH//3e+hC0Vy
pCXuLGxaOnpurtrmZxmZ0pmFbm7Yha1Vb7pl5B4z9vF6VHPaaORw0x4wDoEcoHVSEe/kt3IMdo6q
wRB7fwKVYGaYPmtsuI702tKiRhGUhyk9GM2fv/ZvJF/9nEg8VyQoXp4dYt5pl4pWEpp0/pCMLku3
Ex+ubFgbSmHVO3xU6PYKen9/ck1Hiwmni9VMRT6H2xKyMqK2askVJTIKzIB2iMK1VY8ZsxZExvRU
oH84q4DsIM8YFEU7wjVvjLYjUsGxs9JtSVWRoM9rLbCKRWOdbOXm6le/CXhfFp/LqikQaR+nOln7
L0mM1YmVOEfpwE2DRIU+XRlq3oVraRuR+qCYNEyOL/Cx0EtAAl+rwUwp4US0R5uynk/Us7U9+7q/
Y28VymKH/Bw12t35vQ3/kOxynnuIc0Cpt06TshUOxNzdL+a1Is7Os/1v/hIpIFeEyAsF5+qvejHH
7wHtCHH6t1tamAgbCAKCC5c0Mzc1sfNh+ziLSu4pZKoKPsphLzhuklZYwjn3esfVYvDzttiyRqWg
JpEVYAVJIsr0DJVxJoQHkvdy2LFD0EW4Fa7Bm3O8UI/FNJuHm2IJYOSlI/4T8ZOWHFYR2YQBTDHp
tkdAqc9PSDeflHwJjKm8k8xV9gye++Xxq4LQu/DSyxBmKQNf3WV5OZu55omIOqdSVL8Nk6P0lvUo
tadGid4s0Vx4lsOPR1Iczkciol9S4Wtzw9BosAfd7rcofjl1wCIY7g2Ez/2odXcaDnOWOwRF9iq7
Crx2TGqfmxYRTORaGuXNJU8WEGf5diGvMFp55nPpFYDFZ+O9Sltiafc5AZyAWM49379Ds5F1ZCME
IBDNxPg9iVLaLeJl0mJnsTNRoQFbyVDyP52Hffqlmi9Jdf4R0/IWlv7ya2TpaCn2Hnq8zTB3u8MX
l6x3+HpYVFI4buUIjQwBYAgYMM9/A+gFKuWkZ3QMP15L3pv4Zi0Rw6kl55L9lfSDyr1+bl0nPPLG
2P9IxNDUjUZ6veKngckqWy2f9dFqzXGJfSifPQYuqAF6W2JBSXVzC0pjVYcN/jwVPChy6XxxDk1L
NEpTkwCJQqPPVxILNJ/IqwWgZQTEZBnA40OobFByAcSD/GUZIzGDFt2Gc2GxDqHslqlNRmCEa66v
pK8aTd/R2Vm5XIzfMuzHeOsLSjPBhkzybM3Q7/t+4oBU1YDA/wpe5IH5nPV11pOnPChR14Wlz69Q
2b0sqEZWimRJlvu0xw/wQg1yqJLUTp+al3KaUTXRyWBwc3C2Y8xKKbx5L4s2uvJQ0MNTKBy1riAf
HQXmE8mfuMhqAJpR7m0VrwfB5ZbD2QEI1NKy5Uc5JjtxTho253I3if3a1yYGdAYCIydLeBpqeu4c
EcCLzY3Pa1QEGFOVstswtEBu5fKNIhCZSnabBwKZxSJHZu11ywK/Ab6auwOyssmTcuH94zS36VrX
qpMs9UWw6gUV2BUjf4YJJlBW3nF/UB6bXycb68Ud71reA3UoR0+UUbo4hGEPn6lJgj7outjelLiV
1wDebfoOiO1TWM8lpSjWGao7tM6TqEMgZS+t3dy7HBeQQsgH7KkQKELQr+xCsR42iutmVMbYKLG2
jI+uubWlSDnjzo7c18anFw+TEI3oB3W4UquGf93lkDrEjBHG1SDTqFHHnMhS/+GAPiL0kZ6Lj5gs
eee7eE++paUzB+KHEa+DxhXENm3LnSwtk8Vnr2LzigjRZmX+YIoT6E2xt8wESU6cLwLEvNz7w5Wq
Vd1LxeyHJCKmE21G3RagirQENXfMLV3GqWUFtW6Z/eBbhrqhgl9acIdaxr/DG1B6pwD5RkIxkE3U
ls4UEu8Vx/zNYTgj692yfXkmBVHptLch+PUW2IaaBMadoiD7BzJleOgj4HD/Wxe9zyPeGkid1OEB
Lm1Ay/xcDUbca7Gc1kYq2f6R5cs6UDVTu5F8bWbQK81HsU2a8PkU5EZ89XUmuxT5VBfBXtcNxk/m
kBQObf/6mZekjbItma0BnN+XFJAJlHNQc0f9oBk/16xWytELKxRMnLtkpVmhIb3hrBKaQdmhH1OQ
BEgpqfvGoddro2qEPf/Uip/7ORJeOhtqSo+gsJ3aU4nhBA9/3YCvb8VV2kgeSnZ4JE6cqgW79JMb
TLm06LLmqFFYIT83OqttJOKHUX0XNINmVawYcJBKM7gNgcIryC5hHeGb89lmKAYdzKOUwiQFetxO
eL73QReUZaY7GVuZ+Cy7oEdBgpYN6fkWC+JMAn/7EpFs2QWFwrX3U5prA1I63x5Cfyxe7SAyrtXD
9+ihPWUElaTnsBtosn8YBrufEyDZiJ94zHqxUYtUHo2XN/6u5L4Mm1l8s5hY1TF6s4EBf6Bw64wz
SSogjpREGAA99iqCsE639Mr+ToOuVlrpPI1HBFWhIKZomFyDHAoq7Gf4fwNwSAfPiGiunf7FdP7x
mYrwi7bMzoQU1fe9CD9ZogoxYevFQJdKqRqx/oPtq9S7+VihUNdR71JiBgYSuiVz9/d/T6COrz2Q
i3/1fJG14uN2CjFi4XmPZvfk7qxIqWBZD74qebDjaGT13pXOgzeEmDINRkNWyP3EJMDw66fo6Wx3
GOT7onbTJvbGg8m8BSzVOTWS3EpV5fVGtYcX3gSi9lVWUl5w3igsAVxVOoNNi9tGugZAgumQMNY9
NLgEjXNlXeXpui3UXcpO8nVS2IPufyO4wyWm1TBD7zIRSTpfGRQOekil1FUK9lJTdgueKTL0Du48
DGstt+pYiZNnA+LFgB3GLIQyOZhuDXN918SmYv6rXXNICebaU2IA5Mb435wg9PUloAYzQuXSMhUQ
vn/yMZx7ejPaxo7OxiegrrPYrmnmQtVeakAUVat2p2eIuXnlGwHPLREQJHvblwdYOSx4J7rADgPr
w7F9lg/I49/Xf+WJ4DOi5JUHqd6do1rV7GCykvMsFdNJA7sNLYa9eaGWlxaAWAy504GZD5EeO9o7
+9XW0CbQRL9lCJImTrFwOFpBFbGRzgkmF1++qv0/lOYXceXuYH0l++KsqI9ExtBM7QMYohY6uiaV
N7AEVaif+TePMqWrgpzgdC/uKKCACDuGxYUUIzj6oIg5f5ZGF3m+mznrJwmcC91BcuJEKM6cXM8W
FyUDC3rqVRDxxWvxxYUrr7Wg51jhuPZmhy3GPwx10kxtjXdkxZmNDuLVroCixXuDVpkXL22svHJK
7O+coXjYrAQRC6/cKfpm1OzuHZPleeeGoFke53aiUD3rB8tZaiSVQo7vvqOERv+8uFlz/41wJKXj
Zd6GGEXkvKNcoAxMPJ3taGdgOayo3XMvxJvI2WtzQbcqhpYfIL7TeIPX4uBgrF6NozbrGw+epSpQ
pB6abiu9uiDbkI1dWfuMQ+0gxi3CK8McnbzLfx/LjSZ9c9rRyxru1QKYE6xrqNHozHBsJ/5O544e
kudp0IduO9poROVt9XWwDGsGQbxG7k6wAvxHy7f8ojkfHHTYb6HRh/Fob6VaL6Rx6qU4HQTJ5DhK
9fjfK3B8/ZkZHcV5Ie5emGJJeJ8zWFq7IUcVK5cZqVt9z4ki0TFVZ6EI8lB6i9krJ9WDzwF6ftyz
5/k5TUKTLNMO/TzTG22TE3HA0S/bMN4ta50rdoGGtKMFuxw/X+AG9FquBR5CcgGJ6780owPGdT2w
6i0HzHOtjzkx7W9y3mZdCGV5G/5+kslDszMNt91xpEpziBB3YouNwpjYpFgjrmwW+QOokA20US7L
cyHAbnFXT0ntjGAc1w07KzKG900BvFNjErzKv6bEcvCIPR7l1C8uipppJHxWVya1oSm1SaTJ7I32
QkuzxxD70HWUubwtk9J0uW0q2zKJtqUhx6X51wpbBdc9E+vUlXZv9NdKk6qHZkz9C0RT57T0vZjA
Z7BY0V/NsLsl7dcPQPEQXNXEWVXSV5VQyohYc8HEGJrlTTShZXd0HHy198jBM4zf/qQxjFybgli0
BPCCwSzXm+UIXsfaZPCgWac6HRNIrbQEwfpXH4LAvXtnd7aAS5Ig1XqdTpfkXURDvZhxAjc5YT+5
hS6xTgD2ebRN4ZSfAlMiGCi9L0JtqtktS5JmltRv3YrIN+oUTI6tdCzHhszK3SoLHKZ5nzCTCRhT
52EB2+Ltcmh1YliOFFoxny6WU6Z47QJRG7SGlfKOe4b1pkPGuP2sRY9xaKkBBAoQK2G8yD2Poy17
xxUQNfnapPOJKYo6qSoqQTfLYPHnrxRDkUmEMV46r8xJAC4RqTg6zYJe7u2miBfHp+aDecjJPzAI
mSNOe2bh00NX6cxTw2onnTU+tyo1MpIBivGXKtQq4TJxCkvG5Ypl5H6w08dH+o6GlOIe91oS848X
ns+mQDC2C3+dh9hr9WCbbymWbtJgvlUXEuV/og2HzkQ0jwMBoppWJ+nA1wdfVdRjXpAXB6OcV/Xp
BAOo+EBZJX7NDvTbY6UEzciCVSVkQWcuMFrlNJjHu+EKbDB2zgqH7M4wla0DhpuioFVR+rr2WxGi
VbFACF5MNb5TKzeVsLwTdfoBpfU0wVFeHQ748yihPpc1OnKA04uSGV+YWACTq4cwgIaROkdnO1Ck
HnO7Vz1xaeE9wvG0qSv0+e+VK1RE3B/6jMxfb8rLQHuTBOm6XJ41uIZNhrlyVGRagO/2SqR5SFO4
Xqlp96zrwRBihdv8+LbKi1JUtlLquSj/+9+JTGNi3kUzfVm9JvPD6Tev0pxVblhD8hDe3JOxElyS
uinydUORFgxPS3pN0MboLbPH1/MX9aONgl3uVsvwyen+0kWA4myLBswyaFw1nQOM+tLK4jRRfT4v
8VTLbEf/0RXjbDoIO/93JEvp87Z1C6EBWwXzrYaVdLHeiTOkNV28AUZEGUrP2qgukHzIPW7NVqdM
zhgZzcV++IoaVaL+EE9P4kDjPkQ47NPYHlR4e4ccqgBP+F0h1asWY5eDwqOZyCUEdnsFcieWxW0n
8voJG3eQBLUwM+nqu/6vVvZTBjI8RKdGTT7cJuCmwB2Yb2s75efEqeKQVshCqn1ARlT0VumRSnnN
kdtjVoQQtl3DkIf7NpS+Q4YyCGp7bPDKb8fA7lkgnOyU9zP6sjPPjya2g8hO6x1H5OSr4OnY+yOz
ccRqNzpPugC93pPRicGERVqCVlziOATpTTxepetVUGIZ86P75Tz9EZjbDu1JdPTa8APJgJccWdMm
U6wauJiB2WHEEIHdcO/z8E0E07UdHj8MFnePqziYON/HA1Ht3nhx6FpvfKlSiHaeThrQru/Xjt14
13dDnufA3c8Ja6fXC+hIb0AKQVuP4rwdzeMVMEoABY7CJ/xVYCl7AK1EgbdKa+dbKz6bU/W8o1IX
ZixrcNKKfBLOOJwlIGO0LrNTxnGL5UNweByYC0EiLr8XuzVSTOJFoDtzJ83Xgw8KWCSgbQNsKlb6
NNhZLbZS1ez1PjIObcKwaDD5DN+CtZskq5DbE3qZBcHT3l7hWGdG2U4Vk6TmyQyIxRc0CO4iAwte
m+qJ0t+1bIT2LaMbmO49htguZ7394BEYhU3B/mykvCZ1ZC3YgvB54zqMGIKexXXgrkN6JaIvgjDO
Ixnalr/0dHzDLsGxI8qWDJxryLHIF7gqm+S75/20Fg1tV20KREMbJqRKtByqTGs0rXz+mSaNWHie
OOxaCbK6XIxqAejnbrf7XGWx4M8KGAZv4Q1R8iRO5nfL6BzsbN5shwWVOXtAxLscO06RM8JpIa9x
xurk+Bd/abCKCx6lygICuYjPlt4ma+lBBo21C/qppNhmuKrpJA/i9vHGRwa2Tb6FVMrV1o/C8+D+
n+VDwMG9ljb07QWzwKyqEkZMcBsh48FPuh5Lu0ZN8XhmzfbItoEDSgG7ncHnuBuhGwIy0U7Pf0ix
TJLEyQFSPgEKg73wyfUP6EwRf1tyKRPSzGYSoqBLeywIkrFMoVc6UsLI0R/+4HzoFKzqxQ+OQmSN
BDPKrPsdjzHn+2s9Qea+eGDqXHwXOSmzPwaJPwZEWKo4+fobNEJ2NcUCPQm5ZBkyq+rg783SC/C3
5jtOhbdwqF45OGDAmJFgUskJ8KvG1uM/wetD3ng0Ec7at6HibHCU5T6cUOAS/xLn72MU3/QAAiuV
IS5mezUSHSqbJcmvHnRYvrOmPSrLFHmCcQ4scsTNTfDOxQ/9+eaBGHKxCEog5WjU1WYJeHqOs2KE
EkBB4g6ZRqaEcm6dZmWgEePfQZjztTzKVr7qeHxg6z5INLXIGhE17FcYEJTk+kxThKfpB0BBgQKI
7VAUG+aMjP3mO/FTsMY/5PGswxHONkxPMplDeqh6euRCY0YubvaGvNDp9Y4Iu9Z1X4rf0TJptRIh
k+NC2QAmvfpDjhWpestTbejTTTPcQYe4B0pOYzgtNF369YV7yj0/BCqxT1MpCgufynekg5+JyJ9F
6Y2deiog5p7q5XigMpSNjsweoY8s1twciAUPiRfTpP5MyPo8iIEUj2NM3tAjw3WndVYpYhScEFd0
szw3zuw9AC03BEXqfQg2zVpx7NU9g6JBE9d1GTLeHQ74kBkHyr9FOFXOhE9vqLRsJZn2Y7QztG15
IJKEepOr/IZQfjdLGydrkdK14uKK21umnbV5lw1vqmMNQgZ8aLnWnt4hmX3xYMk8I/FIWBUBf2Qx
pLUnHJtdsy/J/YdB7LyB2pqpbYQ/HwzlcLk4T7+7bWxf0JdaIJfopov+f+OxJgckoc5dxvW1rGox
rtfEm+oQCtzxFH5LsrWTje9F+CNZHWUrBFjQVvLEIkHCofFWREtRZjjGXnEjb6jMopYCoxICfUIH
j02Y6X9Zb+fUQRpOwu2UJqlbx6va2DznDuI8uyFM3op+J+ELRat64qsjvXbuNEMwo4n0F/7xDp1/
k0Yywzm+rCPN2n2pxK4YrlW0ItHDFdrOceoqp6w0C3DmUziCRcq+EPsr1QZF3vGZNHohUYc0q6I0
nj6BOPeOcD0+qgM8ehmaWKhlHoM7nUYYT9YNsuLuAPrh5/a2U0d+NoDi3xMIjqcPBC7DjxO5KCto
JtvhHweANeki7xqRbmgV3XfPLyfWxCXB7oVt6oZWC9Wult3nu9jbTypljP8ExQ7ySiTONLpof+hA
aZfIK+u8pOKSncwhLdX7qknab+Uk3eZmnaDso6hunsqtU6LdNO5kAzymbP3Xn9gUP5WOJS27/4Rb
QqU3zmNyVRPG0FEBoPT2PfEs1WONTDySyRPlCV9v1comf6flQRHzWfN8qqQaWiOkx8v7ggudKHwi
N6wRgw7PV7NpNtvQLcGhyTLkK9NtKVDC7/xRln4UDLJ7taV43SOKMrV2na/wKdvCTYeJWi1FicSv
v6Wd4CVMFRsiYHnDnrPP+icayA33AL0J3rM6ZtPrpjz+8+sgSd4JTwJGgqGhMYUTqjOgo5rTL8rp
VQMhvQYxavqDFEOAoD8cvLPmljBH8CG84Y4ZAOxCrkC0+xdKInxpDIH6b+PGpBON31dV3l4/heGW
vOsRlcztZOzzF8QFB9Wd8FtpgYfUkY2AX+a2cnxXLRc5IgxAjYquTPKAKRORCA65yrY5gemMGOCL
tKVHn2O1+zBrqktAinKB7vAJfKUDprauZs20yzLsR2L1yKjLav/n56ZkQv6c0/5nh4hOhfC5BXzJ
Er6Nuy4WkCJMEDfIeLpEU+txadlOiSK4beemkOGhWgJSNvibz6kIGgSDl1ZHE+Sr7PnPhCKY9+xb
+OIYUcsMxV2QWO81yNw7wvwtP1a8vvEbGpkIRMoUaRuIPnjgV2ngy6t6f6P+rjWyHllXYAEHABeD
Edd8cmDgjvb9zdOYJGKau5fJT3RGI0em8sFFazPjem6+XYmG/naPZhOEmmsM2jxbYS14rVM3qlvK
43S9zVlA1q6stG8lVRsEJhlEd+8W4FWJqbpCOX090+N1mq1MJVPe/q4qMKpo74yWO+QO9fp8dcyM
Ai/muWj7sZ0wiUEiPfL/euXo8TXv3i2FTnzZ6b8o9uXAKjnFpfS0iHZzD2wicrlmVvgCX3rW8xHE
1BLEF+GsRDrMDqc9VwWJXX6cuoUXugpNqNk5jKtl0jUGlyAutIC+D3CbowuKz8eVI/GK2Hojvdwl
DNZsLGgjcw+ZpZ8ijzbidYSFi0JLeOm/YfAQ6sB7bEUV42gau5OGP6UejYQH+VNZ28hYLvLFyFuU
MM+qC5FrnQ7PPIEC1rvdhUOZGc2cRZEuwb0n4N5UU1n5C3DFj7tpJn1CRwIJ2VHrU3/WZo9zJ01J
pvsmFaLYCicMoeoBqoy9+0E5e/wFUaEopK9RdTgXvrCczl/Ah08RsqrDWkr9vz1PpQguQc51Q4RX
sM6ym7/8wBeiv8/bJnxH+anu18bcmVjo49JSt5bTF9ZvAw4ojZOFTY0dWyQYMtddlLqQAP4ZqB1x
8Kot60Ee9DY/GTv7NIn214ZnirszdinLx3qtfZTOzmuYGWaFlwDsHGqGBj71toFzOlOsvW6UZakt
4ee3X2a34E/f/HX+PVW96gL2g7J63QLHCs7VPzXo1HpD6Hnkk63r/WW/53eI6Qx434+BqEMy2gub
wYadCjXwyEpjC2sO/eJXIrZKnnC3jqlMJbQHK+oEYpkylSa70+fWboJKoeYOmPIh1ETfwkAahCXK
pHQs0naDqmAaATxQPVd1JlK3IjJbxgryN6cwHzLiCySCdlFiAj4cg1A1TvBxBkl3vJP0vdhEsZlu
tzI6t+th3OSHNJDvr2NIHkdba0kfQiDTOX/psc+zENeJxuVoKqDFY/+2N3L4VLtxluN5E89oSNO/
rnj2Zi6abr/cNzGoWIyHykutqSfFpOtyBnhUJvo1x8gzHtO9xQczWktTMV7y1VJY/LKe9MrKKPh6
TQKDp7dKs9BuVfCGBVAkX0EGUDIlHSE7XCFydcThaCeTptzNM6wqesMWvlDSkP4sFDA6iJjfzzcZ
/XWR3mQ5YSShSpLThFosDt3eBcboED4wd44o0fQdNkF/iDdJCUkBl670GYxhAlvrK8eXz9e6q5Fg
W4Hv6HnaZ9oXEDmSVmjWMYBCfk8U2jwftOkYC36RbJSClDTF9JYlto37tHCQKlV8U2kqXkOvw3Pj
tDTjPHjSRnwnZEhMqzCZCTRw0skCmsuqASvUI+XIJQdzidciGpadHUOA5pMVVKfpkBqECYVqeXUz
JP6m/oh6gZEcKs6JSNomVp15lkp4qp/vgcfFRoJhM7lJHxELExOkId6OQJ2eQVmuz4+wftlkch7e
yw1qJz3aOU3KbH3hPc8eIdwMCqkDpz2hlCy4McZzMDDGJmC9dmCFrP5BhEsLyJcoSfYOlnU7hSFi
C5C7e3WZqPDKCXx7F0kGxiTyffHZwIWFBa2NgBhuX4BHhJEVt8D/uon+Vq4qgofmhg5OHXiiJzvq
NHq03nOUZix7phkMqJQUcFFLhr5W9O8akQkGeIMh7RUcuy/LKHPgDp6Svdmogod/BAsg9kKSQIEZ
wYgbp8zUKLoO1ZvGpoTwMV+BYTWXzRWebq2s5hZb0FDctxLhsVgzIvUol2Tad+q8G0u+WhOlDQje
QDrf4TKGJ8SWG/uwXysiUfnHenAnr00gVFha0awpndSL8wfWc1Z1MXi9ZH0SZiHx6Joc1aZSGZhQ
8OaMN9qR86HGlA9kYT7XOo766sbSqDFS3Fka6jXASyFsy6ouVL76YbytaVlK45avMExbbT8q23a1
sumf1B9+unevVeo96ooErW7lGojOPxtMbnHO6d/wzpV/jxmoVRpVL2yR7k3OrBgoVGMk5yriPYtx
hRmu5DTpGa6qUO+0ab7AooEoyNJ0mxQ/tmGgLxI88W9ArkkpglMPQxunZx2um8VJSEpjmeroPQRf
l9iMfIxIjuKfJ3N4dZETVg0DdpU/RjNGpAI/9+50Vb/+AxAadfuoiLMFRwGCqfmcwUqI9XJwAqRv
Tzd/3e/qfV4dRh6vEF+AWJmAHexG2/ywQmJDFTKD+AQVs6UPy1EpN0DhLrI1BhuZGwOjyT/OMcZG
Hy00Hw6SOr4OmYgx4yf0xqrZc4l4rY7UhijXzOV6rEyoALNPyqECweTvQqEc7BTWKYQ5+H6zFB42
x+Avl8oCGpuWjX2LpeHdoAEYtV6ClaIf3gaw1CzXotuH/UsLmk98A62qlNioA/Bc0mW0oUkCVnQo
WSnSdK5GelWCjvM17Wo1r6dLBqg4kJmWnWTH45aZMkStrJ/h/fZqYmMelOOzn2UJuWpgbQvSnwKV
o6Gi2k12FlKXuWr0Ph8By3EzuxPzbWddCXsblHY+HmlXHb31IIk97s1+H3B5vU7Ye3d8NYOQb5cR
RbLdiWKlVNKIKvskZHMyGHdINHFQX7IBkPc/Yb+paCpON4y7SgIKqNIfVIWRaFC0mtwOG1muoxpN
MwtCoWtoBqhfdPhg+wifuN1HRDZKoPmZJPLitRLREwnbRp2XeMwrJaOwMG+NSwORtydIYTxyfvTH
ayo7a+N20SqjBYKlx0kHXKHOCDVtv1/RpChSJJ7Ov6C36dvDgiMYJ5lEHFwx/XmPdhvzsdAQKlwR
JoqwHRCFRrOxQSq4HcWnBl22L1zoJDGlQxCtrVXyNYfSpsq5dsRymHL9R8s0ppzWQcuRBTpPsbDZ
L51UolXFuxN94vdJPFWA7iNQWUs/ExXZnsdWPceDMrETy+7NXuNIxb7Bd6Au5ttJv3XnKFuxu6Xc
zxG6aSBKk9V7wyek7aGRFYF32F/58hPNc9wdjiaRD/LdUTd2rHu5Y/6aiDvSs2JuRfl7b0N73/iF
bJ7UB6i2yjjlhLU9HWjg6C4InRSCrssIY7inyLoYI+j7uyXNd7RXqpMdQ0P+ikZ3QiJy61TfixCx
Zl9PusxuNwvpGg9HAi6fItK9BmhVlufXdxOYSrNOgl1rFNOU0vW8bxFhIBbTbm1qO0vPKKFBH8Lz
Sq8xz1iLkhTAxgbp46UInKHaDBrOyO6MnRNkKK2h0tli2Y4AZIp23KVptKB7zdyx8qSJm7NAiH3B
uErXCG92vSbdYwoHMiWg538OUf6HcWEm5yFqSxpjP29QduKEvT+19lm5IBSlIkDkgMTrO93ZvTWS
yTEE/N4Vob4q3LGbYgB4q5H2Wox+GRQX5McWPKF2ImIE9tJcrMMRqKC/2gVby/hD4/ab1RVoyqog
xH846UzfUJbz3hbYxdjBWCmvx0icIxlq/qfsArfmt2lKHtbIaSbkTusSUWb/+/rykJ5BoJjpRl8L
fhZ/sGD6CDc2riHJTiEIISvx/pdSMviquZLWHY05jjkXt5Z89xPE9jNAfAC1DGEIHor857LICQX0
yuRpTk6NcEQQU9VErAy4s9WgAzO9MLGVgMrJZA0y4hxktNwAmfF7CTGgGp+2vGEBwYVMUmOYEXjv
zd55dfNo4mZ4CIvjkUCzk8LJ7FhvYkSuPokASDIEMJfruY7ZTClCuTwCCbUAersOc+t/0FBx8Owa
ZGRN/61YhOoqOTggFUut+gZWXESUS+tBeFj5J3yLc25fiRxmlLsvi3BzqjQXFlm1o7kKEox051Wa
DN37UbVJBD1Yy3FyVCvUX2aMrECLVSgU9Yw+5HQcwkbYIhJUjrDpV5Ejh6HS+sBDLS2PI1Ekls1t
qEgbMqLDmTVHtMZ+y+WPap3+F6AP1Bp7Z5lCl06Cixiq0AFZWjLKahAUcjKhEhh9Q/aZAh+fhc9h
9t+Z12OcwT4Eg8VB3jnimmjOXkPX6oXHp4943GQebBLPPGr9U4+EaUg23yGw6miafv2WZmr0iZE3
6k5QT0BneBFrK1lLv5agkw1ElSAvqFKQyrvo0cAYkvYm2PXTGflBgASAHL1ww2DlU5qih8Bw0sv0
4A/4oTgQ+m7ubLfx3Q5veM+v5V6PrqbJj/QWpa0IgRVHNsU8kmlK5YirYdYO+rkaV+R05uOpndLj
zN1LBfJJDCHyjx6egbQ3qIZmmU+tgZgqt6xGr6hwfVqK5R6toVuzQAE4VwOIHG55G62OEfNSIkk1
BY5BxTeGjiPWn2CJ+cXPhnc+8HY3j6SgAAoK/y7F1/U22YTyvZrlm8EBEKcGvMAKlPPRaJbE3B78
TdIG1Vrm/pLUSInfR+mV1Rh/Ssgr0+uqHWF0JDk7ToMbZ70Kw1WwCeaKpeTDynky76kAmRIKebBE
PfZIlqtta+GaKKmRKGc8VoGOLMsdFsVYwbX9qS37cUuLVLXMq1LF7TN5Fum8iwow3HA78rzHaGzv
Y6l/MMuG9pVLepGjJyPdnt9QJJSDm69Bj9i5LO07PlQGipqSujs44C7SfxvGRPJawiT/Bupjb4xu
1vgPTwjF+LQ5+LHxQ2eMLhp5EoEgGzhQrX5jFM8lHGCNCRq5y7+SkfGpqdxZivzkZH7+YXCrEgTz
8uo4ncACksl3sysm82jfR7J/ThD7qw88l1JDo6FfrPni7kvdShL4fT5ss+TmE6jqzznkUwijPERU
x3rLNKxDgB2DAzSNCmEIxawUSNkIK5+V6rAYJ1UcKE0n6+tRdax/9/UAUr4hd/zSnozsRYvRMBPm
0ql3U2oSe0kp1G25tEN9ZHzGo+ME4JYLEOP2pF37u3LBfzIBgnd9gvZ7R3NpQnC+EcjL+vXbTQ1M
8pSSeQ0m28Rd3/DczSbdmxhfCQ7D5AARhOmvcfIsHB4fBRjFaIBQlsOakn3Hk9/P0VNX1FZu84oE
Zo5LM27PyYajMmIMXroVcyqLEiKoIvdfXkmGJmGNX7vogoNoC8+kGO0ElXoJoOD/kze2LUcAdvNd
KglXu8Jx04z4QOo/qakFBmfAFNgt0uNbur60m6Qa9nu7H5l+DoQFNmy1A180UrTM+ZKQd8HVef69
40vUIBvvzkcOiVshDj9BzJTVamHUxBYA/mi69dghTZwcS+qT2MNGqv9EkPJmlQHgqvCSEx4l11mk
oio5wo9VMGXrk24WqrsLes4xkVlduonkzg6T88MHleuPkFzsF12wBEZb/7nfS+KgP7juoci7A7LV
AZR6JvGh6bxGX9ncmpRpAzmjJOUfdVjSK9Y/oKZErXZqd5d6csTSEl8P/7ekyGtbv8ikpb5Crut9
bKe6EoHPRuwCp1xammpCPqmTvJxSD8yN93daU43pdGY32eMj3ApElv9m7UEiVNputja+MQerMNve
9fFbbUi2m1rQQC+d9MQz/eLmvKr9wuT3VYOHwrVh+nDoReAPxDb0GQiaO3R4/jQITrjuwynomGt3
m9AWGB8DtDabuLysNQ665rlhofVmK7hMVhGnTL2Kq1LLaIN9pQdx9DhExU8Ue/Dk28tGP+pqRSBX
qGAmcCEwaeTISaJ+kN7xlCklaQqHYpUH3vND6S3sWx5W7I/1il9cDYAkaNBpviS2YlJ3AhXAYCIy
Xq1pTsivZg8h+cR+DXcX4WuqpuT7L3VRpW3GzKtINh4pUHZlJQNFlo2wNJQDBSGQDwXJPuBEoZbW
auQH1hmCw11IgEptZpi/1qn0ewKvA4N7xFP+D+ZZzjdtP3KEwt6KjgXHGqS4M+bQH+Vhs4cesUpc
ZYyn9YPTL715oT1P/c0kK+2XMtQIibx5H0j0wAttHcs3LdpywHBv/edHuhPvMLkkSBOikOU2rIHk
gK2XICehgqJHeGKw8FKRXwIUNeMv+4wEpSwn71wI6+kasgWdSUjeNxGWXXOwUcXJZD48jy3ufuvY
CsC05XPcBhReQGMrxX7kXQMA0FnuHhMux/dtER7P2+218UPCmZcflsXhcHWFYHixlB2frFyKMDE8
tUDDaosnEHgHYbh8FPdYLYrDD7/c6P0pxV3lQNRHo1pQCjMzLCrYHUnzQpi+X/3BhFlWlnWFuILc
/lo5GhwN4Cf+iF4XoCbXUogUJhIhTcMfDV1o5Hn28KMB+PJhJJUS5l7O76uRJrgJpJzWasqOqCoi
qaDkoAB2hgCVWO8aCSd0xsPi17wvusYgudJs78Caowx3fLnErPBX6KBhdNOafs95RRlae4rCiIKY
b35IwDCiQ1h97jpJIgoodbIgg3y9pp11/TGgO4+DQrmhIAfzPGYxc+FtQy7r00BEhbcom2ITlN5q
nD80IfULzx9XTI6KUBnDPsv1pySqv1nMvBOielxWgDcmgN6l8NJ93FAN5MuH2+nATRFuCoVTT7U2
rBAkqfdjxNgv+e7YCHS1wGkhlntruT/fK9bBmEmc3vaAhD29aP4LiqOuwC2A//RANmNS7s19dZcw
63yxFwk1UfWjFl4Tb7ozMs/kxy2D8f2pDmnf9gROPmYQjeMemg28VvKV9L9ghaF9rPlWKFFnxEeS
fsCy58PW/KWOcs0rrRGfWfzbKvlAaJlzQrUm9ctv0lEJLfPVLyLyT2kJGn6f4iQoMoUxoJ8ySiT4
DgWM7D7rgpRDGKI0wHGbyqBwxhStQtclxdS561C9bVjRLuQHLkJUguljkkR2Ef4go7xzX5iuYLgx
K2mwtdK7U+LaQFIsSrn6auWiAWadIICtcP/tGwJK4o99Rohq3Di+DZnw42D8oTqL2bTV7S/uYP/t
LjbGLm9MJDdZah8tCG5leYJYT4u+Ncwd4PolmPSnSmnemMYbBzlo1xV5N1EaEdNIgZ0hZtVNbCcn
a8O1UvJ8FVLQqbW/pocRbxEAWPPDHgz3zGb70EGHkkGawMsfu4nV5E2+uqxUptK3bzRxealiiunR
wNus18G7IZygnVwyJWyRoEOdrOxLTRO3NlfwqfqdH6EN5rcMKQkjPTVJJUbZsFbnTO9qXW2oCBJC
uhCdHtMz1qQ+vld884OjH8r5NBT80Oww8Ig5OOgRIqtTt7FBFjRB2y+UzO/grn7RAJxs0VXWLKKv
euYj2t1UNSgKxYVPXI5G+teFuAyK29I35c+RBLRPuMiMEtOFqhGE1GnzLp5VIxytTWr1gYLfKHeo
7SqEI2k/xXbw2MAus2TUR4gt64yqyywFVGO601W8X+KLGtO+w/59XSsiIUQGaEybgonfjknxZC+1
6xcqunVEt6Xfc3vvZ9Yzdlp6O6YFFubzj2cnhe2yZV6L/gdUtp7ipCjDfG/wRNsPArB6c7GH/iSq
5DtXDaeZgcjx5MmVMCJ2ualpLfnzGW8JzREqFD94OWhRg1SJe3pRic0aKfjpbxOiN5c/Lr4akJJa
DMutONQ9/JPXkZs3HL45pvH6qedfzxS2kKLnjvjuVV89jHTJ6amDFw2xGI33uJKBowtkCH0X6pU9
bb8HOOAuuRRtuNBtA1OWJgcZlRdLtYafDSyoT2JNiVWOotpDM6NR+r6O9bwEMvI2yHcYxitd7Zrw
d/MgZbK8w9RrOBVz8dW4vxRQ6FOrrQjHlSySEzyqUhkaUrYT+bUm6yZzsXhLbfXPV4fGURmQrRIB
XajvjaZG1FNZXvOZFNamUUa8mAxHkjYj4FwuOJbt2iDMNZXj8B9NjbvwQ72lOJH+dGi9yFExmPW2
90XIEioyC90MqZ7EY0v+fwu2Nxvxt7uiFPZj8cIzKtwDscAQNAd9Deble1xQP8DOE1H4Hfih9rE4
sCMSCxM+FbLdgc5h9+07PMXtOdAY7wtvNmzyhmWobOOxMqA+JiKZX3eePdvdHPT8MXoGVY44mMBK
/rG7ZYFmgFA3q4zzRXef/iQFOl6ZKBZBh/DQVIrAFc/fiRFFYWgyPvUek61HewGManknAwxIVnQ8
Za4BhzdGu0vleoLacJQT3iAJJqnSUbboSop5GEF1Z+Sw8J9jnfPLV4p/8crhgpl5W8Em/ymBTy/l
zgPahnCD31eOQjXD0jWG/qCigtMGUCxEIIdV91tGcqCrHofcKGiZCzzSB4dV6RXGyiF2PDBM/N+h
8qnSSgtwJt/zZ84J91HCqhDnDXMP2uxU2UTG6nQLauel3VbRlcuNe9LU8CYkxRmTxlNKpmPJIHwN
BmG04MHx3CnEaAAZrPSy+YHdAXSDyxwhwpS12fg+gETkmwLbFxsZEQPWkODtoFGFfiwdoCox+TTN
7A6qZWilBlUAxJlAJKfsDCC8uxFfIIlNBd0SqRUYj0dERJzyZxlC3HZ8yfYohTvKk3u9UDaoiKAy
RPG3TudGWj0exNllEy+f8D+Vtow0IFUDfOeLIw87qiD/CtrgORVvQp6ks4hNufeef/aZ+OLum4Xj
BEEkKm5x7yZwmXlmf9hmrY/ukNdqxksj/bZKnZnW7zGbBUIrDKhl0CPeITgdzs9Iu4KwcaFKBaLS
I05tiSsAJJmRw8CTPHkuaSRQZ6iDOiREP5eH4iOvXc1HEK8n7Nct2fttEght6lbDxoj8PtXlPNs0
DOcBswHuNIdWOYVuypzkf9Fr/vt6CcjQqBIrO9zNO6NGdBeluvv0mtW1on+wNXQK0ytVeRViF/BC
CbxKm62hgMMZ4Of0BlfDj9VUB3zBliSXwOwXEDaasLl6wwVsox2iOme1qdDAT9udr1VSa84HJXNK
Ru3WqFY0Swl+47Yr7EOcKO1R6HHGhP2ybIksvSHSpcq3awk43G10mVRzMTEhXbpf380HbI6o9wET
y9bcgdvcyu5z/q3U7uNJl5iAkO4sYoCqdCqotkqYiiKndqrKoqU9gntZfYX3Sa3GRk2G4CefZBP7
dr+yBsIfyf+jAO1ESjp1ssmh+zqHx05YvERFwvt1Od+DQH4rrIdejLjDUij5CYa9yc7KsFzL3LNi
h7awfgQnl2dmCabKmwtYWE2pQnp/6XIkwHxC9OTNbE+Zj6SY5vsKcFetWZhUkV1Soh0sbtB9XA9L
0BHHlio09STHm7BzKs849knTlTuqJHgoen4HdBJFOyV18eE2S0ckfiMZKaZXudhZu1D4XNVRnDT5
YSrZVxKm961qAOEIVgenIi6egZ38+Ww/WANEEvCEcTK87xsOpqcyJ8lGFeG4W/EsGTrKCngTfRi+
NdwnEHKF4aiY6+3BHIjnc1XxeQ/aLjAZEknO/nDFwRQUvsPALFlXuYW79Zd365DgUuQG5XmrrduL
zq9vZerSvJHmRBC+/Yi1XUc+/JvujsANjgrYXnryKEqEQZfRGoOiKGA0uw22i58HAKchyDIVnNBP
Ypo2BIddDJe4iLVl698HjUeEGdUFEUz0ByNMSKGJ8BKUOyKXojasTClWoC92oP2vpgV70NTyJTuV
geooEXBmo0vjYfg439ZyhywrH85r+/QEAW1/cSipAobiWSylhndY9oACtLJvjNn5QNZb12gFDVuG
4Hg1eUHQRCOGHZtFqJANrMywWdG31ybtqSO0njCVA4vKey2InKPX6xIClvRzPIPDmFbgl+ZAPOVV
0mmvuZD+FRl7B6ImE/wK6ctDUKTdXnKfAmu6Ew67guMqrbYlGCqtj9ymX+XfH/pxcFRTavPmQKHJ
RV82imxtmCVJyMYWAEzZHnLLJ2g/FNAGV+36gwwS3mfxEWLbwCD/0ArcZVv+aDp8rkNjuDgFpliZ
R5dq6WicpsSSPECtW0zrtQkrTjqt5MnwKFdHCdoY9ojrv4vqWqF7GUJ1oERfk4vXfWpBzJzBPETG
kB7i4GeDSm9ukNAfH+CoaqiqdbfOK5Ia+M5UwsjgN/yyjXCgdktx5wiQeFS3Wz6Ymopp1WyQo+Kp
NQt9DF3j8aIJh3X/HUcczscD+RyZ5cWkooTdjPlq1Z4I4ivi5UA8B8Q+0z/iqpXtQuMz83TP/LRV
bM6RCOSZdh3yTPvDrsUbct5ndCFGYfxrqdwZRuSSfP8ZZgBcxYkPXCjFNVp/Oqao8QYsvJEwVkg9
WPB9v7B8TfgAiekzQ3ZZpkM9wC0F+xMvvbiezbs2FHLKf1VWNNv4jsHcIABbp36HTG3h+yhdczsg
Be0jokqNMf3MhybeVMrylfSbb+vQk0EI4JfVnhsqrBYiJt9x06/6l/PZOEp8WsxjFUymwTwSp6lx
j611JZGpoLRiM6dPZ/AlrUhk5buMAKZeD5ASz/Jg7EWfgb7etRoT3+WwOZWk/hurQKqVLYzXEsiu
cmb4Y0nO+TBVbMu2vrHrNhyJByfn47T0bGxSY5nGLNmHksvwuaI/VRQXDjhl6/AkccZYsMyiCRTk
ezyu0L8VLMl1k8R260IInmPmBxkBRvnl1yFrVR/KGBf52sMkZoRctc+PmJsrNlNgdoLcRFyJO6RR
zoC7MkwmVfQcEEdp3TKthnfM5zScBT+4IF6kcefk6d6hDjs2ku0oLJKQvCUs41VM/qTj6lusNTus
t6BmmRqEcVNFBrkDKujoXsRRLL0u3Rgx3Qpu6ZJ0af6jjy5eM8xMCIg71yBwr0BIohSF4jx5M9eA
7if9NPNyuvgni5U0JeVA7xN3FnMoG6PBB8zClT47eJKYBnC/0xXxnI6TdtllGugQmpOP7R4Os4e2
A/ZHxPyz/0z779d/NBCANb33/WqbBWiiZu1Bg4CDcoyWb1eEKOB65WTRM1o/gJtWnHdAk5uwylcg
nt+tnuJsEorrIa+zBFpbt+B8/ad25UkOFb6JAmEktYAGqvJO0Cl+ha10JMFaR/Y45d7/IsnIc8Mh
JrstE+2DdyD3gmh/xfrm/Tluo+yYlMn1kd9exXJOVpSO9yNvxsH/rDUfXOQ43FvSzA3Sy7MZd2cU
BzGvy5KoJyWTAAQ9ZH2qcgs5kUN177zQG+QT3ar6FxgdgKMMkVmSpBmyMHg1BPbVHCoD0ZE8UAZC
wphRjMV+67nHItxfvOO8FtCq3oEeg55HR8T1TEvruyouNP+zT+pnOd+i97j9xJQ2pYgl5M1z8sB2
lsUREH6KqWduwYHruohym1w6gUDsyaafBC5QDVfkV5g9lCp8OcsA5Mj2sAT9OXj5+tfWG8KcFjMp
5uuOi1KkA+q0W1jXCr8BPrmaccS4UY3dSGRr9WxCIU3u9gLPV2zYFucdWCcyXdRQWVk8YaLGMxYM
LNezYqtFhYvQNN61UpMpwlig2Pa9hdiDAF6pfmKVDe4fd9pPr5K1A6MUwxzJODKiWFCaAS8OQfIt
qzKoG3RLBx3c1a9hhctj9IIgipOAzT6Cdz5s1PSL9AuhUjLQATGVsJqmGy+EJfFuI9ECYy8MSC2J
f7i7S7Jjtr67g1lRJcnZ8C/qu/6Q9Kv1FxCeQgF//LLU1HoXOOVQLmqseVTFrbxfZ78gFmGmt0ZE
enuMpcKQ7jhFTmEgOTAPvReGNAY8SNh6aR+y0gzgaA8d6+kTbWGC+WWDyhT03YcIvUUQM+eXpQbs
9qQMHg7esL5ZYXvwLudgIdW1NNQ+wuBrW+Kz8KpIPtHn9UVRDT997B+FfMJXcDAv1c7MFUupdO6O
mliBpCwx1fO+NJQor3yuOYQ9qriuBor78iL76omF03zsFjKj7J7bB11oPpm/XRH3QLCIm2MDf9eg
ac3Bw4xU2tWayjOOHOCEQC3X+VICFnDl/7uiZCraiH1/sUV4LAmRn6c8jq7iFGcfFO0tEGEKi8Aw
oeN4bec6Urn/ZGJX6QLBTQYiOvWNvkXOSWzfV68PNRFrgtx70qjD+plZDv61jPWM07g50t/ImteI
+mDgVwLFKbHMDrQhC7qrFJUacXWHcqa8E0p7ikLhvKPfsgd8+bWHPV28lD8Xh8vhDcR0CnLXMoH1
p795PDwBDqVi8dfswqn/4+pCvIF6+qCLZFtI2KTaCNPnM3x8DCFomwGRetz7q3+Sv7gro4xytMQ+
8VoCdQnkH7+rqTyJWYQkjzvOp9fsnfOmyT3v3r6teJgbzSP0VRnZkonwvJASYRNKMIk6nnmS00Ws
jxAMhKAGYcaRnt+H70z6lYnWwQMDrcDrAV04gKzp6iX6zvmDo4++PYJXSlWLjeZdCdIn41vJs9N7
RpfkMdkZLAwVL5Y6AHRzKFesSNrqKLp5fHALZkP2+2/e7prsFa1tkFBvNTIDH9dMDvyYcsF6iXu4
mkjZ9oDbJ7CUOiV6gdylwkcWjIRQMCzuCmMAIGwZG3P7SJDkahqGFgpDrUzhplWTLlEg+fKMQQft
P0Oq8UUbbtlHgHbf6wr58tiJQ2NVNDyIsASMNxSopaenzUl+5jrHMfUWyr7ZzR+O1iE0eTefuEkS
u6bH5N299kcwtMpG33I8o4Gx80pEkSHoHM1golzgqXzy9hN6pp1ey1Ei70YAjnIjRzOfEADPgo3e
X1v6rL6+0S1m6NSiKr91/UBv+VxLnuVwOf6HeNWGoSnwAIk7jrxf2PP4E1JLCAjDCgpN0LiS3Xbo
FiVB514+4kTydyyCbMU/BdZoDqfv1UCVN+tTURtWnBCMEHT48CuHXTQGjyZwN3sMKOBUegmqM3eE
oIl3FCFIuPg3Nb9p3H8eoP34JnXtvVMddcKgQ6CLWNhphY0PmisGbu6kymk4OWQ5ZabjAjbKuRa8
q54k4NK0Cgb2eee1H6YogvJ+ogJcrYsY2JIt8j6rPH9Aj9b3GdSq2GJo6xmEJbrvhC+S9PeMAKys
U5Qte+q02G+U5ZblcgH2uFXj/4FYqMj1EN2eMCZV/xs1TzAxq1+qxF+pG+M2rGEGxtgjVa+R/mpD
0wJBoxq/QVOk0LWeKTb07bQwJgZ7PvlkQhz6WJ7iYdWM91zquHDaoCmiKOnsJJycLA3fDD8xYUf7
XPfOAGMSIAoh8A8146dGAf3lftmUrIREqtRsyuveo4zoFPwWJC2kZ5b9wmXTJ4kYauIxHsPmSYn8
+7rDy4rPATt5AQ1xPfIN93l6ZhBx9w41qpDAXRdsi64pjhU+kv9oT6VdvG6fSEdw+MPN5lRJYxX2
CKnNY8yQBph639keYaTNbnIMhwHM3d6hU6mDRBNL4bG0NicRStttBlrYXdeEpY0N9QH0s99hEnes
7bNyzq7bMsAWlAKsurv2lWK3QiqeE0WWqxQt7EFIwMTaA9eoMvHNQG7OWw3vEYvtKfd7ajm2Wweg
SRqprIT736Z/MVIDkNXNGPxXXAxPeM/pxJTggNmGqztuWKqO2Q9jl5NWywpTiJBVxYe0ky6w8lCh
np782e3GRCpPBa6HEchmxlMi9qk3O8muksQMSadcCPRNB0iNqGroGQKfgBe8EHZLuN4hMeZjHcjI
b3ytio2/rAcmufInyI69pWJStuvYOjL23xeXbnHXbxIOzfn9WIQezdmlXLMbxz7V9CGpSY+suFum
+ClM9KTEjfCjEYmW4ZLGgtHn08iNPwyYweGcWD+u61DSSxuhVY7X5Ubla04gYWqanz0yOVEgavSG
2zMGRzNeZViImWsGg9EyO8aHbeeYcSwyaX1Neh2OD3MlOhaeGoszn5IeHU7LWwhsxUCLTo1V89g+
Zn4X7vZnRgIqU3jjQaHOKmRcMAswXF2mDozS5IKz5ZT7F+F+5w6/eNWm1N4rIyp3XKnw379rI7Uh
8sNgsWmoe7UmskMFP1ZLBGLrAr/S0jR8Hf4pQUa4TLmdvaB/0jigdCGDvcMsGF9gg4x2HkxbiyY6
TApNpSQ21RyMnEthD0Nzmp45iKaU8ZZWJE8YnMz2ktJVwDBl+1Vt3iDm8bWqHnWQEWMbGWRKtFw5
iIw6ShmmN+JeC/q+1fejUUyhnNvWUFXHHn94YYmMsWktkj2qIZkX9EoO9enYOFfAR2UredF9S+nf
17QtdhI/zjWX+dUkj9Ob94nQos4FHtYf/puaOtAWClNH5ec0XUPV5O27EDQNxZzWtJ9uk4V416Lk
X40gGml0E9q/aHZloSJivWrsSRmdSxR9x+glJH3cjc8PiddaJa7XlFiNd2M7OBzBCUhB0tYTt7TW
JcYjDJU5xUe9ZWOq92RsnET7ssJBGOmp4WkxDbRw45f4/j72cMXJHrM/0/Qw1Z9nXHhqmQz2TBDl
zxregB/b8e31plpvvkkOrT76eU+1kTatI+Sq4K9VYRupOx7cg0s4T0p8js7C2zhI8Sx4hy0PngX2
R0uB2bGDX4LrTOUzng5ZLysapROS7KaO6kyo6jlFBeFyavTqDFpQM1U1zRq4Eu35uUuTxDuIOmtV
O10fAjpwdnbm3DC6yXR+dldaVFZ3/iQU/o+8VwCXRZSICOt9zn3wIcb8GvGwADPzdVBvytP0dB9j
lUwefZCXhZbWdb7pwGLOs5M3ijb/YOwjPRP6GRflcTQU65CtwQE13fn+3vtDYi4oYvPdiJsSGyce
deT8aeeT5ueM2FrbynYBAQgvjZG7/nGtOFv6SMa5LGXwIulC2ptYru5d+pncYDLvXD8v3fRYFu8t
xCh3qrV2LW1DhptE1gHiqA7gNwGxX47KK05qL4do0nrXwqezXoeKE78NIOxoeM7wkq3P8X3H84HT
ZYwLxczkFQKzLdRSMHDQKIcRpmW/o405CedqYe9JBdSbwQE86A3d7Uy3j+C7RBp72z/ckhDBwCWP
oQdxdouNry9D+x3uzkH11JiqBt712yfqPcdTpQ89dkl2KT34Lez2MRY0mWiEuijleC7KCaFmwBW2
hrul5QU8LDh5S2oqv57ngV8UQOa84gTA1qpFJJ6wh+vhSqxUZMpFQ4GGXB51G54VzPgG4WYu/fSr
QUs8Qm9LodDsv3ylg9gM3gEzIBlt27kCj46jUnR9/5TxPpmytcwaicQe/cPvUAQuYPzRBpDUzXhy
nyMpDehN86eZcumLCf6TJv9JAdcABkXcuXcykvmaNCpng3zNzodNIpz2vpFu0889GcmBkssUu2cd
6JylclLWNCVW65PhaO+qM7sY9baVi0+y4I5UPFao4/bA8dWB3LdL5BC+yErUzQUOxbu4ILPmFd1t
SCyvzkMFNVKR1wtVMaPvvhrUhU+DfZtvrPlvJRWr58jG96bfgy8GodTgHdeO6DfpdSMnd+oY9vrH
190S3nbYU66aTUA2EuTA3aUhk5iq3RsL71YYnSDJOoGifgosNTlQJzwDVsX//iVcAdtCef1FWRhl
ZbMgliYQq5u071hPd7ddkna5il03faQublSaL9Yr3l+5EJUg08RHGiQ5xjtDsspDkLyXVoXBOHsU
k2l8BIIigfDtGbYT7aHzB2qDMfT11biCg+X1BeqwjSG9X1Wk+a/n8XUIzJ1xwlkpLt/YWlnO/yJB
ux8R+O2qXTNkZJ7JO9gsNLmQbG4ebuQ9a5w4uIG5OJyHMHkjbaS2IYsnVsYPzrWm0MT5TN7TiUrc
Xmw9TA1ch9Jc0L7+ndrjdx/XPkPS/H/nk0tbhAgGLyjr+uYrqod/Bf4JzbofFTEYNi5F2CfY5xWL
YVHf2c9ib6Oi1EPMoVPOVxTPgIkx7sxW+sXNe/daBUpEw/8Rzlwh121Bn0Tq604Xf5HhZz941Y0w
5RhRxT5/p8axmULtvvP+zUoi+fgwCjK3O6Zbt2hwpDDKOzgqGOEHeRI8oAJw6hn8gjb+eynZ0Rh/
5CfmNonhzGFWg84Bl/n2Cgay/5/xgjXp6hvofKjmeOYNaARdBUhRsZRDIZuBHy1sCtJ9o+99wxnl
sfRgKL/+qmkQq/BLFOFvwDbFzveyHPLwSH8CCEtcp94S/uruZ3A6mlNpeyW1JWmi9nZPQ/EMG147
Md4psu4srLThk5uHjpdIRjxyAM1OJUjx9tYVPGlkR3uLIo5fovkI6Hy+doHuTzd/JGMcxqaWrgf7
VQLdhkFtIR7asdq+UQQzILilnVPHJEldKzuX557y0yF9t2jaP7N7oE52DFOoyQSMft/Lk96tnNwd
tI0gf+jmf70GciYU4Zhlw95/KfkgwDczCckGlQ/lZFbVUUG/F1CmWw7Nk+Q1mpn9BJCuGltqNKha
8cQIOfsfv0jLXOzNcgMU7vpQpSrMInHzPBXJ3/QVKCx8VRlVIi7sQvjvrPQpDHkDlC94dPFq+6D5
bM+H7ecKn/KAYvkaUnOyYFSLb+9onseAAZkG28k9+nM3YqhNhz60wivDs4h1CyWqAP1fJ1s83Zzt
2m48TrNydtzVTtqCVNjLKLFOX/wPbY9Tt6k2JbnOu1u3mo7yZeU22SAnmX0Z5t1ibvBERgug06wQ
zsMCOqBiyO/FtPesNriDM2QrUMLRF8Xc4Yhx50xaNlBqyQ52GFEqhEWUuDEB0sqBfl9+qyS/WII/
HU0lQxM05ibv5tz0YFS5l7hK6LU+RnZmSCCusA6JHBJihKOgAc+pspRxMQmlDknspAA/X6182ijF
nqKsvi0C1TRV8T/fjXxtb9kd/mSw0pXdOEYFSIUs8pdL+Upa5AoGNZYOAllnpCx4ZwLBhHQtyEmx
KyN/BecTZ3U1Z3+X14xKglBK+6iIJCPNEDwBTjENczJ/w3DgmKNT3bpBUxfEjQU22Q86DzCYXH0x
qb1qqhQ97qk/QxEJw67FpgRKzl2xG7iLp0KAXwEtNMXp4Kfb1fTRmwQAYmf+l5h9HJs9A9n1fWEv
xLSusV+Y4aBpNxpXZheratol34MlrGRhySP8OwgF068IpH0D2/f1lIbLjYKg1H2bC8ux++gNtLNk
y2k3zU7Q/qMNqOXvFaXpCIlPKWui3z7VFMuQEq2i2YuLvtV4S8+lrIj03sD7FqNWMBjCQKvnDh3I
LAc/djE0SclsfnHBusTAFyqg67GyPidXtvhUUffh9pf+SYO6ggmRo1KFOiZonxK2WImjVA2HvjGq
SPJ+f0vSXZPTK/8/edIdy+WgPbw/mTyiogflnymPjdt8tP6piSN4JDPYgl3ZlxwuNubDtEfUDcMC
1S0LTk+dlQ/uafdJmojOQBVJeCybrukVwBe5ILIM65lyW2x+lIQfF67pV7hxx9o3zeE4Y13wn/Jd
P8M00HnlXHeNh54y32pgOkUrhH59EcjOpz3fTBPAHVXtfpN4ejs9Qq3sskbumsy1lRBYCEGNA82T
UQvG8Hi5HIjWz8byU1Iu73Ln0MpEPloo88iHb1DCBKX+ltQbbzBV2o4LaxJJAjX8bEYcXWHPQG03
tIHKJRH52p15wbwd1e4xJPy2GZph4apx4BLOoxrj6U53Dcb1aMAuYjuj/iaEmHaEZQVpAOg2qqhD
BjONiGYoKS6Q/+p3bveTGWLbRGDsOkfPOjFZgleGpLFUZ4WCIrar4+W4QmWz6jBf5T8h3FyIKNPe
csaKGo+OWFdNuc815suBanc0CsAxvlbSL/VilhfWYIaQkvoH70UvHrjksAPMM0lk2nF7Tp8Q74gq
dav3c/tUEfb65xNHT/AbiwDj8Xoq1JRSNZHIgxU1Jz6yhOKzbfAfCy/56+LrjKYvGOlCT4YopgZP
v4eVgy7y+/jVALN9wPJFYNKSd09jlD6jFfP0IRSULR6U6hN5Ji3q3TWLXoOKni/PTYLjtyKORdda
rm0UqCBdlepQvcRtx4YK5Txu19prjaAEY3TLMMklcN9zn285rGv1CJwdBezy/FiolhUUoOiSkprm
42/lrQWUQQ9RZqLMbkyF1gYPDMN3A8ZsCsubv34YnfqmlQLApygZILccDEjIOPJIhrDDqkL2TBts
+kztGH684S6MRzEBC7xi+rkDvJBtNCApZJxJujw/bJI6LboTGZwBeNVkGrL36Kfe6bkK4AknHj32
Q/IcErbSa3pH/J8LiiK231apzJTqJV3BQCY6uuwn/sNXsaNlyJIUogd3TJ6xab3/ox7Go1tYs//h
nOxrtQ0PsXTmE6Dj6afA63qMrm37mrQGiuHDPhQYTB69521K5G2YwpvI2NzzZexweVO7Jq2e2EAU
kGSvVVgyFWLrCgvBWvarzIX75+N1TJTRXGtW7nbaL0TEjwNtNnvSZB8uwHVg1lRtd+AORf4Ip2X/
OO6mSC156jbEZvLT1QTzfJKd7rgiQkTtvaUyI2u8BU3LNuN7IfQOCjBOVk1OZYboGcOqCMD8eFgz
WFEkKGJa9yAsuaWe+1oDxwO1pxz2uvah0I5h/H18SsCh5ezTaJEkGLe8lIkIJBxWgvSBeIki4GOK
GamFl9G2MPUPwK9x0+6gErGQNLqq2po7aA82sV++q/rd6guxzdy/5AOAG/1TcZpasI663hcU46mO
yOzxt6PHtcl2SH6xoQWa14Hv7nTW3QUgKGk7wnFI94JIWhZ2td2bBbZZe3Sy+F+Hu3M940Xhcf+5
1QjzcCMXqTSymrDHWgwifP3etWzMMF5HesvEtRxRPRD8A1CbSpVIBVGjx7Cx38zWPov0k9OqVKv3
6j9CU1XIu5dqu/w0FfSn/O1Q57lpevOBgYS472bhYN547kJzZuw5JlCTVbrK0MFyJNRkXVev73ZF
m9bA2Ju+Q1rYPwT6i3NkGTm8O31ryYWi0SOGXbvezbb0v+hQ6LhS0h9JL+LC1doTopf7UiGdIaFd
KU/Tx4U+Cj42UCREzLAwoFqq3LEmc43iGEUS1FBSqb8WbHTNV2Qz5Q76mVa9jH+u06OkB1rhJyeX
uU0o2x1BDWVwQ2E8DZcqqCprUEwMtzb8fy4hpNCkzMTRwzL2S3rAAk5Y0SESYcxOXqaX5XgOo1r4
2DJOuzCM+ISzFySS/1xrhHCDmG0Yh8x+li3xw/61CwIl/68fdmKfaZKLVVTJouVweGQ+oRyYFUuP
Xd1VE9Lzwo86LHhrGqGvyT9hIVk/BxpCA5HvRxWH+0WlTiQFuZMPr9a2MJHfK922Tf9Yz0vxc3Im
cJ9vFuhkJp+bUx+nwz6knnSfWFsgVCac2WErwDoI3WxSH7wu4uFqFpjzLfUg3xgpXf+R+V8rzWxo
/srMRQg64EtMN0qUv+I34djFSnla3n7/NS5o4OME4rXMrqWYJ2Kfrp+e9nQLOI94YQ253e8zJQZV
giEVYChEDoRaT05Eh+kkR4ej7bE4uIQVUH7bvJXkmw8H5eSiT9yG5NrtRwqkpXTzCsrsbLJthR4z
c7q3OifNVMxn8iytUqy+vIypjdeLtK1xJ21feHlUgmel7HY9Q15dHQGOjAhPa4FQpzMQ7qb7qpCJ
FHbeOt8OYsIgI50bUpkxFvhXeqMHT8GnvfWXxt0Uobq4dMHd5DNh05Vz6dEnnxQAhEGJoi3XcNXS
qOLpELBTubYm7Dhb7NkbYPbWteAIjfs5qMioaLyXROr8YhObsWZsp44MEU1A+mYREygjgLqGOju+
MAl1hKHE2f6oid1k3fG8eUyXiJoGTJsKA84AdZzIZ+w++fToNNCWAAFq2wn4Ix2jOrEZpD0OsmUc
W0eCmODP+orltZ8+iOpL7lCt0izU1cH85Fp0WptkxgBcM/t0ZxiwqITYqbLKC4kg+/BPWXmFs3c8
SfZs7gdjxMmmx0tiWYhu4fggKyWOG/ylJY2GepTV1gd/Y6DaYE1yKWh893a8PNZXQvG8Pdrh+2ex
wAa3jEG+zYSmn3bnZrz2YWazzVPeLUMGzMrWznddynZVQHukcbFRNRQHLgoaGBem+E54TIWM1VyS
FB5A6vIjogipCJ0GQpXq+/SjhTbgAl6JJC4X3OMDEj/Eus7qSAdH9ZWPJMd1OgEbPR9LErvp2y0Q
+rb1N6esh+JRS6oFIVxiRJuC8lbt0do3w+3JfUlQtdWQX3NZSGGzhmBAeUd9KTbc0NP3eTMPl0Rv
tlh6NKUqbLtQK641r/AkMmQGig++lCLmYaGpqVKCpEtL484UZmBbF7psuYoPndxKh3NvgrHd9Hr9
ZtnFl+r4RPCJHRORgLmVHAjXU3YZ2/hD7JrehPhZ/NNlAVOh2yyItp1U2KmGP0oWKuXywE3YRul9
3m3lAs3kgKUu8Qb3ABvmT8e8Jb8dufAawpPwUxHw69jI79jnO9i+fCYuDMFab8187MmiJym7Bl54
15tQpq8WjCAvT0KOANM8CW0AGdFt5MMOhK7tfLA2bNc7ccQ61HBcbBaxADejQ0/vcy4Oxuzr2F7K
4fiBx/kkfwalJJfeWKsGx9iHuj7qmc3qWrT5SDZNdVCSKFJmlZXrIlgRK//IwDIkh59Kh2ieLsU1
1bsn393ZiDtxIqWow4qYJKwBElP2BuQIsivURA199b4rfXnqqzTV4jrHvhTjCRt7OcEMhgxQliW9
jg9hXy4WqZ6Ub1Pz4ef+Btgf+iOaD5qHUIORIcCLQlFhfMZrcxzJ02yzMwAY80s2Dk9peNh3MoGR
lGvWz5dmDXbQxckfaXjfwPeq/ghVM8w+DqkmibwCpUKOLe2fhr3Jr+fj6kW+34kAp1UMH5NMAW6I
EEgKq0rlS3gEOm6HAyzALBWpuuLskfc2a4FC0cDNJ6C3ycX+n4PIOQe1Te7ZMgiAZZEoPKogRtGA
LeH/If4eURjmqG+hp83FkPEW7+3JaS80FQ1tYveMxgmuNjqxFqCNzhbHwd7LKkWfFgPy7kLzBELI
0OcMt+bWSwVAZfelTSgxVBctbvu2FometQHnqtUW0FV2UfGTLktqAPJeQQOnfJPFcZTr60c4NWPT
vdtmYB7JIMNtIbFpfWTsIxidg+K80kr8Gw2KtdvuRa32ECD2xvPXFY55JInt2p7r/4O6JLQwBntH
icocJalJp+MPAKv+dxBfDUwYFOhAptrUMbNu8/4DftYA3k7Kpip78vM7hK/LHXJv1fklbmW+nDpa
DQMW8+OTHGY3tRVNaUOfmL+jVVNMzpxnTsBL4rHP2dkameQa4HxngXk68qilgfk4l31+YmEg6aG5
Jbk0OugIZTZNopW/MOj8VZeYMZN72wJhV5tun5cyS0Cs5PVRCHjtp8b808bVvaKP5kQhFlt66O5d
AwOoiK2ppeZb15zop6ABU8H/EJjia5wMnYFnj0PWuV9zLFYPh5hZa9ci2QhKQVxic9TXR2zUfW3l
Lqgut518PiGlzzw4CGAmgJUV9Yr7XLegoOreYhfLtvfXjfA7C7tMbo3DKkkJvcpiAjieeLyV6kVm
0ErcOq57B3Lbg2cMHlY1glDQxe1Go8B1fswqi3fSExkudTadTI8QBpJt2whbkoj/ewgXPQQGLliG
/DqiWxv8SYguG6TQxw/uGP+JIONxP8k2lxqWb7g/M0Nq0ykLzSkR0/4AlESpmx/SFH4voJNo8Ato
IZya90yTYmOWkYmDREoUMZLKA17mCmZ65eceveYVEAe3SqTo3f9A3U4t5NtMcqyS53rixNZIOhyQ
34w5WyOjqr06qQy+v6Lno8Y04Xub/l+AWKKTuYWYukFo+9qkWGSgKlrZMCzpmrV9sLwpBDRA+Yc4
ONEH3UDscth8hbIBXNpK3Ujtoju9XR9P9fTJOOpq+AKvAzSPvFfiMzcsCU4uqwR043sXe+Ig8Wgs
T6AXKzUzH6ggp+r4McwJvOIRzmZsk0BDXAVttRXzNUOazriTWpboZgAlZLhySd5JrMxSH8/LtP9T
MYE5RdTHg4ExZgvRqdQNOUb5mIClZ5SxJlh3VsMPHlF4vOR9wZbGPKJK9exH7RROEKyAAz61Z2/w
KOv3FxkkMAdqZmD27vArodx0d6HyAVWjpayzoWctOMe7mnQjLVf/LhWxyNItdIteVV9qRa0YAL4F
C5OI8cH1ofdYaZsrVBtzW8YnsJGfvo7x0PXk7tEMmEgMERiK9ZNeRU8jvOOgWkbZ8wa0JMH1REpP
OpL9mKG3uddGSaBwRw3+dJE1novKKLnpCa9IszCvt14cvER+LPRjkV97tF3gz8YVPorLzmmdEncK
nrsyMjbcmMOmr37o7vzy8WVIzuNWUEtew+RiGCNw35VYvp3tSNCEfRFVhevoeztweSTYMFvWXIzr
8z5l6ayA7Rg/DKWW0qGjRsV/etffqxZkqkaGBKhW760sbxaN4BCHB6/I1GPnXoMClbBY4wppfKiC
oXJQtaYzXkuVROCpgVDHUMtwoNrZyVWnMit09hn7/5e7jmZrNeAwgCvVnDaM/P6Tsf11IFU3MiT1
UhFJ13pxRAj6chM2pXus5vlssmhrUaZB4B32+a3k1ac5WQ0yYUiRjzreimvFqXCgViNlAj5UF80t
DkxUhlXehKqj6OJ62kPdgexYdv/EPhT8A5KOwvwbkXVGUcmSRX6oUdjaIy52B+OJj7MZIHOeOBWF
mtDzPkO37BMSVbeu+d3RJfxuam92dVPfrzL+zd9tSvaxqPt8Kzrz17D7rJFac/B5KjIP264gNdPv
PxT12SXxvlPaOGqlJtZOZNApml19fa/z2qLyJdXkx5YkpxSQ+JjPQZPhDLWPi46+cd/D+ufMYODw
Z4/hEyFJPZUPLlOxPu9GmJsERrlM+fFZzQAThrEwnwGrKqSf3qCJMDIlx2dlXb6mtcGMx2BKF3W8
SZR3PyU6vvMxPcdfUk2yukKGtNHJNqBrs3XtqZEtlUrRsJ1lIvnxzm/mFNRoa4eep3ugYOIaJ37e
R974kplEg7I0b+qlzTUm1h/lg6j5OmVWBPc3GSMA7tItP4gK2P74LTA4ikE3DcCJ7xhtwhlKcfkO
2VPDAnls1ndvnVvZs6An7WSe306/2axdvKVZdlDhnc38A+WGhTknFYr5xPU8Yc5jhv+nk9Xszjea
auqKQaFPqRkrEACq1mhWSruPA/yuC/WqfV4OzAJ5rW9Ak25ZG1cMUw3XFvYCwaQZ9A6qY+NVj41N
TGNlTarIhiXuq4CToy4Cgm4X6tlTupZg0fZhDkhOFD8Z+fPdD+LBVIKz0U4tKDXItFtV8t2kGuNv
E2x7pPa2H07IRFRvrolPmVinvoH0aIQEuVbXHZSH2DeEVQ4BwQFZWwFEZ+cRCxQUAppdxOuWEnIF
bbsGVqzCvrbIeUYWY9GDoBKc6K0wg34krUk/T7OzGnuRmmKw1O0rVEIQtTt6sx76Tm++u/yEXrtU
fTv+Da0oneLM1YcsQBuHbAjfbBxXuHtRvjcjooekAN1uWplLnXB0N7Y4lOtRpW0Iez2wsnYdBdHv
/dRcBmT+wCoFIwEBHxOC+H+9rjEjjeXl7uZQ3FUUvxRP43ZKIMXySDJMkLSfkZFRklvnOyVstl/I
NEp54WC8UCmIhzlSI4h4WczmKPCOV4mSpfPpUaYlWzPi91221tfcaQrrfweIE7zBJ64E2Iwie6c3
xVSTdeo3vF4jCw2eskEuVIPbmm1XM97U0LH1r7I9HAJFuIKTyejuDtF0wNJCqBe1Xs46d0lp5PMs
/JXOiaYQGNDzP0S3YBXPUHnEztO3twKb1DP7m9+7YuGh5Zm8KWnP/Q1YvNEiakXR4YNo16E84kxm
mJmPIIWw66a49AN94Dbx+2JrppTe/kjLt/TOVvyhkL0pspv54cBgHqxFiivE/KjANUN+D6iAJTHw
7z9SmdpxgMwn/K1O19bx8rWJyL2CwSs63Ih5IoCKtnJAh/7XXVYVHs5XzVrZGm2YY/efEoL8G/oV
PzzNTnxoRsIlkwVbtj/nOGo3XiHu7J3vfst5h3R56EkVWKlnNnZRNy+ObKxpo/sVytQa04D+I1E2
QOuSVLI1NWJEHwosTF87ersPZHQoLL8R+B86ujw3jJFV7kLm+nKFBoQ2Bk4oIow0KsR2CtMBn3zx
6LgZxLXVCEZCUIMbbj252Mg38s66yFd2bRVpXUjhe6MOga2Trk6TovQ4nRSc9BMGGGt/GyAsK5T8
HvQIfru6/3vPl7UGjs/AbzWWa7oVfVm49Gd5RnbAE/tryNOEi3CikeHgB/UvUSPX9kdTX3fXMiH8
9RUWhHowfuwVW+qn36fbc8y1RmU8tLwBW+5zNPb5P+5CmRQZq921tJVW/ootJYwZvQ4tRwgkvJ1f
wlBqm7uQSBYvihgJ+nkM2qePkQgGBCjCuEAkIiRm5F0I2wmoY/jmygvKLw6vR65mLp/eM+xacEHC
HaQWszkSNmIp4CS4OrmSyJbfky6+ktpOz0pY9f+gtAlYD8BggRVkw/liRqlJ1eiDQq4/j5tplguH
fD0xGWaO0vAzSXk+5D97Ql90Us3MiJSB/6f5O0D4FBGG4u7lJR28vds3hgeVa/hKR5Q40O7Kdrdg
F5xKG+39FSBpQfJ1Q1d7VxCzz+lzTYeS0GjEJrAfcLfRDQsoHp1pZwQ646OHYimmZxggLhbNpsGx
ylRiQUJQhnrLWqxm58a9YFONcWc0tfRBAFNRfld7JrsA7JTVOdGkziuSPXMmZNeDvyJX3g4KxrPU
dP3SUZq1rC8inles6hcTcfZuzidvZoGUAlTAf3lE0vnqty+JvdGCP5btCA27bolOCCWNDn8UvBiZ
IJcXdpDNliI1T4CQmv5xQckssOxaXSIrLC7TW9S6NugDNQ6873GK9D9JxnwGhNv8gBpLtPrcycE+
pznBjr9af5eXlYSEsrGAM9rwc1qasSJwrzV1BuMU8zCATkhP4ULTUoansTZ4xY5Xjo57jqpaFP0e
1KbFFJ4DXbuWATuPll526zbtIsG0e7JFb/seL4aE8XDKIl16nQ81gWQWYt4ShvJErNi1g+OfvM9u
uB9wIGsg7evWnG5917QXcMV7JQIce4g9+FdnyqlID1kaYmPG2KcrXP9lK+MVVtZZUnTakST/f1gq
Upn5kjiXF/0rv6EW6LfhKcuaOTJGRYORpChItE9BmJDPC/Erp0+MBl6iDZYbr57hn6+ilIgYv8dS
4p4Dc3VKmpvsWqrJHk2NrybXIP8/khuKmDTjwicdIT+1xLLEO2QAng5xziifa0VxSxyZQxnz4j1v
9jd4uVCDsWaxdM+s098nmpns9z5xnGUCnCwx51RiGgvh9+O8jifXgi+eesChdZIfG/1OTknAVGwV
wqoBN5R6NZA4+a0k+khs7uCIBn9+9xNjOKvQQ0guCNxw+d7bonZKwC7WYr50eP5/Jmc0Fje82gW9
s08M4a1LB5tj97RiWudZULJylnxLE1aQGelVOJ+3Lm5W4VfhmuA/mWy40Z/7+mnqYBEzFCWewHsS
qtxgfj56BNsA5iWoMZv6nFyGnUPQ6WeaqQUFmSFCFix9gC8eR+s75dTfZGdcNDkl88qkj3+c/smt
sVfNT5d2kNr2s94uclLyKn4g0OlPmh4F1RPneuMkaTUTYjBDerdHwQmyhT5vCAP+KEirdhRUKmcq
uFr0IBcvAuj/RlKWSvInRYSgBrzNwqA3uHzvBbtbpEnQHmah/NZ5XvEWU1enuH0Llz0CKMnrkBO5
z09EuYzfwF9Ju6AFizwD31l9FP898sHiNzYluB5TWgWuINGoCDVxZeBCMNgowhe1DQMk4OGO0hs0
yE8mNoLGfF/nU2ftc3JVBkFfmbrnH78thU1Xh1FM9WU5vRPrrIR696CKb0IEgh/PP40M7lWjejzF
7KrEkhabOMMrGK26TFyVLcTZZ4nuaBRSzS4SFpU4KTCVNnvMIdGnGN7lrEQK/PRPfw0xHi8aPMZP
IpdAgpymJvuBRv9iiBKPy9NeknlATslEzNhNlngxkDWrTa5O72CXBkk+D4K7vm0bNQs+BASjS75+
5i39SX4f8ToKLYrRAWEqxlcAe3D7Xm6LULQp284ygndpYR3LdyJI9uP/Nr4Czd+bf71EmJMzcSuT
W28r0UvVx1LfRkghvINlsujm2WpRDRWZ+ZgF64TAyPqf3q/brGpP8v7i0dno6aCdw6WjOXpBqhXj
kIoGLHDdutifp/UuZZpi92JamTUgbT6yru5LNn5O6tL6GqR5f+1Eo/7OiW//8rYBS3mh81elRgQC
JPiCneOz2J/rx8k+LsaNNDciM/Eg1zSwO5HObI/3NIt8uL40qoSz8gtVhw8NQpz7FYtJ/PVX/mDr
zV75XXfcacmuj6IC9elDqM8q8EnuuAeGxx5algomFb/iHC3LAGUD0hrl/Nz4qf3MWjZ4MleQXKXW
43dCPXMynokaj9a9KKMpQz+Ex4QpserEcOWHQ6dUkOlTxrWuiA4UvSAzr8KTPbD5vQQYEyqT5Dhl
ivp52nK5UUT+r6xmM3RtzrUdqelUlQO31Tki0+pqI+SQ+TNj/Ju9gdHQIbTlCk0CO+taoclvBZY0
PmbBRajB/SNgXAetNCQmLPw3hKF43sqIpuN0RcLdFRVzWkErrhHAHs8jrnjr2mLEihkle0rxvxiG
rX6yk1E6LGY7+T9zGvwL3KgIC/r6bOQE8EI6eIoecvVnRvATAVPhhQzXkAfoHNh+549Kw6qaqXS8
SucrWBU8i1Cg9tpNjIJvLh0Tx7nh2QbWM2d/XWqSX4j1G0euhLeW+BBEG+mZrmkV52AJihDyGxdc
rzjuPSN7K5vHpSZqU0v0kONQB/iybxA+DFqkC3rHGvsnQedMadI/2KJ2Hs0hC5D+Iy8ra9/g2Hpx
dnJYlo/S81yHLvFAokIP/vyoSuopu7BW3MXxgarh9zSWbUeDYATJpkhGdl7WQt3CtYzZSV7N+xol
KWr98kapnQ15m2S3VnQrMtE5OhRc93c02eQULaaDl3+7bnobj+IjmoCJThJ4tpAd/45m3FgSf2IL
gZjV8muOOh3hBB8MHjOCsQE8L/79Qe6sUtODLg2LZHESf4J2hgbSfvaq/nloaEQ7eGMwakOx5cu5
/bxgOnAi+wPIPH7NhCu/7H3muPb6SWO6VMAcy/q1AX5TMWAO+C1uR99ncg5SUmrYDbnpZd7BwujH
bFbhis+xUyt84BU8AzjBFPvT0at9G2/WETdHQuGmaJ2RZgjDcqrzvVm1uigS/ynPsXAmeJnDosKT
qysObp9gqz70EI4Uk1mE1+nciQi8kumRCJYmB4MjVgl1IkmbLap1LRrnK6olVaTn7BKaUT74vIFf
jGjb0iedJvOR8439Tus4nsP0xcEVny6MeenNb90bcx4u8lAyVOB6JdWboUEsW7PE/xA8gCs8dU74
ZxsFfYpfQ5wZbxHXHMAWvOX0OVK8S7FHayG8ifv2FzyDhIJP4klf0/hCVynM+NC3XlJrbThpwAOv
PZvl79/ISaOWSy9AzzrEApJCZXDF5auvob76Roh8YYbhjbYNujhHQxvW70pTpk/Gd8b0zDBFtEvW
eWNWB+i0IStA715xKmmx+XC/zVuyLKODrqKX+3D7iATIFalk/75FZKnoVfvqqZKCawZZk99f8XPT
SBC5m6vkn4nPpstPQQyON07vqzdxKkR5NnppoWy7qNCK2Pfndgt0xMyjgGcXv29EjjvFd0DHi8c0
Lcggo0AXc5eKdxIHpoytMM1htp8rwMxs0zorfwTKD9efbrN7+asO0rZoU2G1m9r5vsFMQeaImAiU
v+GFgpcy3pHRQz2xMR8wObtmT9+vzQ3k0Whk7PE+8Zkh3L799A05cjcr2ZIJtwPvxleReivTws7l
mGU8BwflAvIuwQ5mKSGy57/yCCibwu64zoGuY12MVqFY9rB3aFVx1iDlUi8V/ZGFtmGpjiHa3l1g
x00B2Dty4jhcH0ZvqTjrxro6EztN/Z9R9AGE2zAAZ2UTis84JmeitKARqYdyYfwbYx8ISmHDVmEg
YZv4spj7QtoiW4z32F5JM48GUx1pLW4wgFgG2zisrndVyksBt/b5X0VRBOEM6CyE5kOTB3qviwMs
ly2nFNzEp3CdVIVx6d0WGEa+7ZXjMYz+9IMGq4wer9hDzCXZJcOhgUtQLB2fNqitNATm2ekJHm2o
OxWbvjm0Qe/MGBQa57b59m4cN7ggDM59d1ZPChTZ1vL1LaZv8MBQy6UY3D8Y5TlUj6kBioshPjwJ
HXEYGviTYXYJTFfqUR8Bh43LlyrammexikaHbVWbYwmTDddfQijqbUu7zPrsOpPCJJ38FiH/y2vb
5JBTw4JbRF/VxmugZtHnMfHiXce3UBSpmsiKcYRsM+O0SiK6u/zxg7msVJGroeAwdP1ABl0itqRA
rDcgtkOiOrdysCw6TiLJwWhC42jCQiit2heChHXjDtRKFZJ6ZQhb2ohBH4COxAEWh8MgsBHP3oDK
5S7Kmf87x1rUkabO4O3hKsNokyg3afFWJ+jwjXyFeG8IQlS6Nml/GI4AWeL23uuZUIv7IxbKH0Cb
eOlEV7EraRJIiyPxPErZyS4YZ2yGVHuS6bZ5uj+2ozmllcMzR4jIeQIj6/ScKH4+bFwkuKIqjr2x
aKt2i8LCezR9WYGAavn7MKc7SsomufhZq5K2h1504UYtVMTxUB2smBsl3VlTnYT6wZlvKXiUpVXQ
KzxGpKg5wtjuocK6tcvGISd7HwJyWebZqUKBx69J2fPvNMuBAjcewi7awv2NzCG3YGXRDHN8cERp
/cBFP/JJi4RbLXMofLdCFGob2potI//v/SXzLmy9/h1D1+fxkJpR/liS7Ha5S4owjUe7JZgra7vC
T/vlEJwMtPfx7LFQ6jJHHY2P/1uEgsvFpFxgt8vZe2FRgXTly/3mm5Y1CpOqv/bIKCMlA8P2m/RZ
3tBVAJ9o8Ke+5IFRxXGssnsL2K6P66xBPGwE3F9q7Do7RD1l5BXzEaizNtUVRkKncdmQ7fN5wUjg
4ukg0XxRAZ/0SyXR+BD/zq0VOkR+AihuerwC51jWamF9MwblkAwmBFpOLp+geiGfDT1JuvdxR7A4
Ks9qTJ4QEjSgGK3yWqhJgMxzLUcnwBbjKq5iRIXytI8OuFrVqdp/EuohLw8+jZlokp7LpxLuPcKn
oF8kguubOXuFzZp2x3al/ko4/vKqCIhzfjwyKxud3hU7TOb3JOKstafrIf6yCgxogFra9HrYuHV1
ppiwViq9kues7fgczTQjRGe91hlpcZUj6ir0XCFAnAS4Oi1U1Eut1ATpIuoqR0dthfzeSaecvsqZ
p8ZU6y23+TbpnhJg2ga2OemXPitko6r2rpRz+USRYdWdsNsT0L0og4KxcaSgztZtZDf3iMCF9FBc
bsnV/k2sXsG8277OGOH+m2d2zA9kvGU6LTYBqiOGnbRKE3RasUi7d/3BtOyEO71n7oQWeTZpKXSN
k2KRAm/bErmUnWrB+T1kT8bJLqvNITJJbfG7oVcCk7o/i/Q6MZIAnaTYW5fDExDM+pG6DrxbqKEh
Afc/xRM2qH3Rg8JLyP9b4NqV8iBU+p4c5Z83hsvcKplC0SC5b7bu+DjA3TP9nPz+VSa3Kx1ULeuW
TlM/32wDz/XwWE/YA3aUp9n4BvUZynkNVp77I7f9nbM7eErqt5FEeWEPnrVbClCGsB1a9bHdL+pl
jju93gML+0FbHnPCOkt/JIsotC7nGsFoluVsUZ8V3UY1bYX9tRYlWkbgprGy6LziyoXZO7rLx2vo
CXkvS9A8RYo9YqhqOvWmekQ1026I1xgHZgqLGRIVRSaQmslg6T6G8QC4lnG2WBm0VL9Adfb268sH
ydXnduRqRUy1577oAO9RXVzcgRJoX1eNPm4IJVUK1Pz3UMDYzeGRLv9Zb85mXLaHoI4oIcXyIknl
DXEZPZ+gNnoT43+XouqALRxq1jRe9nqNEVeAq9HHYIqKSnQ0Oti5ZCqWCFAs0XR0FjlUFmbPyhHi
bl3In+bUYxomSCHT0Cm3WoT4+fEkextgQ33L4sMNju/1mL0wj+Opttyi0ONtuIrz3l0SDPAYT0bh
MiMJdXGIck/f5HOpYrxuuTs+Lm3TMJMzgvpy3sFfRfUF9jvZEO2zDeRgq8vabtkMNKUlfosQXj6Q
1cu970TG9HrjpAo13Qtrp9EFZQOoMQdZKR7N7lh/2jv2yqV4J2LZenFPnzhIJyPrtlg29HaJFEaf
OyzBO9po/7Lhbbd33eVYJib9RZJqHEEl4C8p8CQH+vizsGwAVO8OEEp9dOiS54n8/urMS9gMvH55
hN/260EdHVtQrv7yQf7zAjwsrc9FXhFn+xmHA/cm29d5pJ5H5nLAzgoCw2DfeUW1gywvluXIWPdD
yQ78wrlLIoCdd4iWrMQY0lt5kIDe33pjcoyGzZKtbdAWAtErGkaEuThcaBSXbWP5AjRCQ/CWZYE0
3EKrCxEdhZIvRZqsBQ7mB/5MdyJ4woFQWtb8IBn0N20X/AL+auYNZrbCFnbv4H8il0zi2HzG2kvB
Ho0ByRC6XrK6zeoAvsh1wEUY11VuMG2W3RyUE48yMNIPeIwmhiXEY4eXHj3TkP6xzYDD+9r5br3A
lg6muVbz1QGF+GtmGTX5SIDzVuCOmcljLl/5wZDDqtVsC4FOQaePMvZRWz12VMySZslsGGvJVz2H
psRTk+5Ntkc8FRSGKsWHoacAJk/0w22+Ll0Zb5A22YOM8sVhIdLXjtyTbsHxlQa5I77ITypZX8Gl
I0E/+Im8S7OKLrYDelp+UL2q4zAlaCYUawljiYucunqgU/rZbopdWA+ifUVuI+Z6zMprKGnebwk6
WcboC7BKdMIfKRWYC5Xh2MVliVZ/pFgqfpjLCtDtMx2NTZC0+pdtgNKifFRQofy/iEG9QaPdOyNd
2oBm4hXA/o4R9WSp63F5jMkqfwLd+GFvjxzMp/Rzrm89ZYMsE2LdfK4E9MyS/5iotbmtdbHJJ3eS
FaajX+IkDJg6yF9BP3TXB3zPnFk8QOHxbCEIuQ23Lv+o8BfwMzhP9V4Gk69YGxVTP7OO/zpaO9Zi
GW404skpzpOtzkef2C1R9bM1DFabZMVT46rai5+kMnuj2S/wcyI8qc787PxLsFMG85WW1p0Bwebk
GPuamvdPMRQlHmhUn5R3I2c3S9x7uchwQ4RWQq02eQ4K46nMOGSmDnLb1c3Orvua+QRCswy6oKTS
C1+8zIcxlzUU5g3WMifjD35qG5tz2pPzuQ2h/AMZ544Pk0s8VTJaXjOmvGkTbXlUbrEnIVSuJtdv
jvpE+xTyE+Suv7mU6WQojBWIk2rdMRwvRkkKEOM6juh/iLuF+lwi/NtcLGqsoeBYmsxkIPjL5z3D
uSBlBZ5463w3e/XkyKjnObTvPd47iQLPTeSvJBlOgzEFNlLcHGRrMYdwib8Ivw55kw8ymTBWkP8f
Ks+0SVZNu2TCmvLmhjkQYjiPYnPz7cFVMTqsMp2CsdmtJ90T301Ind+7NJkrg7+QU6wMKL9wqC0c
c+BTwvJdyDQQ7npf53IJo+y4GdmNL5t3Bl8xcjFbVRkC/Ml8Yd+iWCXwzRko5Xsz/zp5prhnnCWP
RCpLL2QhVhh0UhHKW8pzoUpgJ9SbF4BGTsfDyLYL4WbWdMMwMHspYFPL6Wbjlh+NdDfafIQTCmLf
mnGY58qv8W39HpZJY0rqjw5SO6WoThEAvpwhpJbHPA6cUjAO1Y6dp9Ap8kxUtrkcs8hubvORcf6F
ahkACJ+bXsYExtTHeCIj2bMz0oPDe3ciMbykyNpFpiyg6m2aKIo/9FxjCAqfB0d5trQxCg2PfStF
3R5th3/a8dr69Eih9HMpcLMbPBOHE40jkVUSXVfnDqAQLZneJLZaxDTNR0HgzEKYQV1ntF5OscRh
fBjWXgVyEoTTZXngU5Dh6GF19YGzUlMjlphY85RuVEqAq7B+N5DSY7PAea+Hqc/xe1TJdAPlstBM
7yjL7JUxdNn2EOW3y2UL8521YKEt3wEG6+wb1vaUyX7LbRduj0TjNB6qw1du3JtK1gQ9vupEuAFt
GLGWGqgGLgzrYsHDpUGhjFJw9Z2IrT/UoWbaM7pdKbI4EUeRqyBQjnrmBH176U+ishVPL/Mx5FBP
j/+6uAWL8wxDiy+yyEAzdQ/k2aHusQs4kx1Qin8Xf+ZbyzyuEI0vffgRXx5n+ZM3Wgc298DPAUhm
EI+4xR/RMGKcpvllthBtrgbRZhcry+arEl5cYO5zbJ5G1R7UKZ/Z1m1VvnAreDlOjdg09CS11d+o
ewVjhQbu/Zu/Np/lVWznIxrtyK5M41/wO/wyKSeS8SOn3b4t853KWLbPn9TchWfXyUix03Wp4aei
+0L3oFLD1sZBsVhUoQVTViKJkejioraCMM6NXt+OReTUF5KyQccCLTg1BfDM1fw1HoN4o8lKNB5L
zy9emT3pqq3U3hJr8kOKgdbJoDyLeVHtI3MPoXFt7zl0E2APA+VsWtaOA6bDCZ+2gL/zyW/EmX5+
vlrt0EleO3k99weDYIWdfvn+wQFzrv6h6ewjwmLN6qNk39sLUkOtA+u4mkjgfIdW1Sh0QfjTl09q
Zsn8PhEWCz6jNQrBTo9f4+cT6XzU5Q23necJPVVO3jZSYapIWjo6hxhDQsF6gIVXq490qkCyX9gZ
AbA92U/WF9f3LtWcjMrgtTD6hDsGIuLl4mJe6hNqq1Y7NZRQJPVK4wh29JK00yHci//+dzTGMvLG
Y1eC4Ae2+0LGnl8b+efO+q4r0y8HZF26rX2QZaEbHqOqDYikayTfZa1/GmJQ1r2CKMCMF6qbkX6r
qGLB9tyzWYwUT+mkeRCygKD1lwWlZcwMMxvx8kZ0UcYdGwSITQAh6bxAzw4mDJegr3+RjPVSvWLH
KCNUko4uzcCGzBVVPSebkOvX52ETdQfnFarlj05laydU3vqklNX+7ZpuzKoIuo+fSVsQklsjBoyS
CTBd98nreo6OaMBXKFcet6PKWQRQs48QttqO5s4RUpl/QpnsYs3fmtD8mCIeeHfPD7rKd7Vztotj
A7pR5rU/HRhFb09cb3iWXVZwCAydXq6o6rGqVEyDGxzUK2fm59FzP0DuXBVbgE/B4HodBbVGtLBg
yqY9ahqIX6mygeTyF8zifHdwYWvrAEKm8BMlfxOx1k4OaQPpFfXW3G8W0DfRB11wfOKVEFDn+yT8
KuH2x8yBzTP4cThm4nVSNIPhUdu5qLLgtNXNYfoTxQ9SoQXLH3sF7H8csBwG7+Q9GTXeo2ZpC+A2
KRwSBCNQxUGj+pk9GGIH8pPMXaVppJ/az9shmHFXvHUEhQJ6TMbNgqkImBfCeZM8Ra6OpAhwJ6c0
C03Uc0OAHuC8jKqaW37TzTXLoNuQwgoaL8KYbrxi9c9M9luJjPQX06kW1yuFLxBYnGqfaTz3BFNO
d0yzQAZzM+7Y3NWjP8G9OOyJgIUMgPbKmjy9WtX9E6/v5tAppiOf3Av/Jg8lQFyw+cU7g+0bIFRe
PMx6jz1aDQsy5vXQd59wWWHZJp1A/IhQCLmoZUR1YC2KK0ui+pLyiS3RzqGFuEb9PMcC/0RGKTXz
PY2Uut2REsmvP0nA1KtZi0sj1rW49XzL8d+nFF5DjgfYgaTnXQ7ABoVNhaR5+wap0dUbVOtXpBu5
pYqmKxkL8L4h884fbzJ88zjeQ5OeYFIRqN+fIURUVfr0Ggge6lPYxXhlfmG178DS3XCzOiFcapUi
38TKXEz0YidUf5ueLw8/8Qokxyt6/pdIoRm7cmYylexatd40X23U54jAlYDeKWPk/GoXyVeRxM7X
lNB+fU3lBgs36wR4JfGqcr068AzDJ/8AQs6HroAD3SRKLaLtSM2j9yWfZp42NBCgeth6KMdU0TmE
b+BvwpXRISBBUUYu8HGb3xtUQjw7TEV0RghDf3AVxE8R6TLore2AswXrJqW2fgWA9RqrqEg0wDPa
4nDu5z0hA+MLs57SaGJRGm6QRxaTDTo9s++aUabEIcF4CPiaE+WECY+zU8mhNYePk85Nl7iassP+
qJqJ4/jDyRPM5xnIWDTkZpwaqFtDTInyh48UFUREOCZIBY9IGHxKcepi+5qx5oRhNlcyGoFrq7Jl
W+m2rpwKOktTsoYI05zrfp6WfVqhMIyhx6libnWu18GamDfZUflNIcDABsy0nd6M5ohysHQRY2UT
7N1EVLD872MSJe/GwnOYc6BWRoofIveRojdgQ7v+LtdaiE0d/VJuR9CokFtGlSk0WYVf4VLHE32A
/r1xRdBKrifUJ3SaS8lF7Abq7gCNmSucN6+0InUInZkP3gp+0MS2iJCcAs756G8TPEpFmBHzP3Ff
kqLL6Q7Jd6KHuZr1D7Erw7xHZR3yqYokxL9idTya/qMJYVEOV7b6A1MxrQsMIkjMQ2DkCEJ4QTtg
HT7grl9G+zW8oB5WakZL2iKnuzeeYfLOAy8SiNDVfGl2g2MTE8Ddz3xYw5V6HyjJkkzJLO9qMW/5
yHHPX5vybaYFYFpvoUNshOU+nX6E2e1n3XB3U2E0QIZk05Dlqes5PhttL3UngViWKl10qKkRUwAb
rWm714tk1TPZWRH755hwLoPoWA5pK95kjL2XP8Q3WNH6vGPd5EhVG9lsDKyQ7r2qxyrpTmrLPaLO
b3Chqyn0a1iAuE0uH8QHCqLdWdUwu//qvSj5483WwsWDBrbayr3e2zRZK7PwhgvShPgdTI6p0rQ4
GxRSwniUjyoD9FT4LxPa9SjwpttDSVrvhCLXRRMXac1C3RZyVvDN93zHN+N/wdNBCHHgwrIi1AjW
IWwTg2MmQgCbCn2FV38pKmFJL6qwzG3B+THEDTXd89OEF06BVTXt0OUfjSgtLhVYOmfqkNjVIdOu
OwjmQzvL+gUNWoVsB1xarNnOFwsT0177CwgWgrlonvBLXVcRI63dZh+F7Zd+yWyJtiYzU/mTs4r7
+zIrtSq9uc05ExsFMt9+rAggyvaJjsmteVGRObN4C6QeEdApYgRfGWV8cAbC8VLeg4gfMkcbplA9
/oUoXU99vU4w4lvlppxde4Ee85hLNEXvhbwmLn33ZwyUR2zfSoZ57NjI05Iq+x/UxLUM+Y2jBSC8
fgCbX5LUZs+t9hNojglWbihw2InxKipEWV7+ptJcLuXX2Zec2gex1IuGROGsryU7IcSZEmUStu2J
M9b/CjjWeR60QC/Oak9QeYS6Ledr/d0QV0jaHoXIrPvpY/W7/zfwEY6pHs4BrBAbf5lTZkHN5dDn
zXX9+rWR2oLpAbwAmwz25M8/zsPuBaoshA3wWfYlmHlrwywR4TBZkPCcqW/W0++rzQVlXnoIMp2+
ghJ77QlhO4VfXa8j3zN2vBDaXswt1H5trcqenYGPQLBoFkXCoSHGDqXoUMhKgXhIsVGBByl7YAGT
Sorwz8SKAbDcdm2yG5kdYXcDyMgWp2+/Y7kd5yg+N0xYRMV44Cakt9q/g9JGw96+9md56jpXm8Fy
KZMS5VpdJ/I3QJvPqqF9q22ZiX23PRf3h3DjpdpGDfjgnGHv4qAJDCxtEWcvahPQrQCR1YOEH2o2
JnommDdKCMyGbHeXWZNKamzrFvXSXecf313QMsZskyijLN0LNHsbSG4ZSxan05dFSzOYClhm/6/V
zTJJJCUUwKRq5nWFilWJRXjUorTlHZqw/0SFLp8cDqvF6tvq55ueR5UQRApzLhMHV2Vm+Dak6fOJ
uwvToli194OGxTbvSiu+trgeLnD1DTlzHPhyHhktk8avEVYlaCmEmXJyffaQv8paKD4MxxNnU8pm
37G08Zh5DHUSExbue5HR3HWbbhHae5ItLv1+msAmDRlubIXUz0bcgYOoQCbpHFigUwwa/gJZXyRk
FYtSq/6V3G4ico4awcMcepTwxQ0Utd99Up+QLx5dXa+UJ63AUqukTOc3pkZEBMv23aqqd3ifT+Eb
mFJkNhpXhRjwD3eVhGh5zdC719vMZCzxTso/TLGEiajRJnv/2+9B/NXoFknWHthLBQMdz25DKdYR
+OeI8+stwUi2Jm59+rG6yIYarKV0Gw8LY4A3YP0LuRlH4kDCLg94GCaj0NWC2AORDfV2RNwMSS8U
Ed3uH6WVdp/kfaGmjcdL3j8yBqpAYqEXv3Ji2IPnVuqMotCYrUgMkv+x5zioX+kPtoKcSR6yakfs
gVDOoloY7x3Eg1xrZbFlaMSsyT1CbDYsO9DscFv6YY7qPs4Z7MUZELVn4dNIoyCByobEkecytEe4
NAnlDAHbMDpP1LddyQ+PPKNFEPOgrmfnjsDSllBG/YhRbblSwEew3gg7omqTUQ8kUpq4z7sXzWvv
22bbWI0+XVBLPSg+AWbONFvTXIonBp2HINzTszwC1bnqYjkwAW2o95N/sgYtyMuxNy2sZcmRe+jV
xp0hJ8rMJFBCSoAV1kErY/nqedjmtFZsmgORaCT0VOTB8Frua7T7qr4os51xVVAQEJIKz4sJI2dr
N51pcnjpzvdcQED4uCZGmUqwvD9oqXv6r8tesa05Hsw7v58M2aEEi5QZ/8JrxknP6lDMwx8BV3jG
MjMhLjH20d1pS6oKIwcj1XeVxSXFhkP9v4IQE0VZSRvzuysuqglMouCAx25VUAgcR9Toa0d9aLPG
Yhu1RsQjhU/czW804DxaKsP2O2OJ2m0gt61XNaD6KvkSXBoKdwQkjNea1rn1RaD/g/5HpvZod3Ei
u+vyyBvRZ7k3G9dBOnjdPQkhgHlXFjrfalKoBXdIBb+sq7ALM1zQZ5/5oBTGV2EtS3vmudeaCCme
CyoFZKphc4OFskVOnf+ilXx0gDSDrRTTrhBl49lDTpMHFKwjZK5CZMEL16iQvpkDDdrpL9S1gw8a
ZcL09XZ4gPZ66P9r7/uaogei+soQMXKVlCszkbWOHjz0WcPjjAkfXZY+h/t/XCGH5v1xSCRjKzt8
y9rxZ8wRlsnWO6KqWQFnK/QP56g7yvJfrg4Zx+eyZBE+0CdedPKwOVLOWVTYaMtWd2ZhlQfd2R/8
L1IQZMjysHgH/k2+XpBc6K/NXOL8LXy1qvSQDLZlkEK37xCk1BZJQ6vJ56x1p7WAxfsokx3G0IXg
zoThFwPiMc8aRmFRX+RJbtcrmbc6AGxXy1UbCgPlFjFttY0h3WX4dfemidcA8STz/B26R1OLCYAS
WYp8ptKlnol17Mnl/0Aetzf+GsTeoKLcOeIHCd+H0Yu/HOmgfYJS2H0xFN7xGiGtzXCB4KVMBzKM
OObtViX9zF9SC3JXMF5YbSs0eRqsaE4AgxeBkWGE1kuoHeKpi33Nl3PxImvT40oatXXE3kyIkxGj
awoHIO53kfjh3MYqaYMNS1+vF6ucc/Hn3K7Ra+28nAkZBaVmEbx9wdgP9EPqV+X6OjJvqE3hM3/N
sWner8whEYYWmXNVd3qw/s8vjIxiUAwME9fkAkBP+JOWmqXna8RCCjl8gtLHPR9F03ciAWU34rrs
Dj0xJqHWJ3q16zdCQejTjlxA8zTdagynCBQ5KXMXF3IXJphQqsIp4Upc9nCfyDIltKIGc8Nf4XRb
Goq6KbR4tXygJLzuYXIa3d0U4Y4dCO0ePiVgneLBmVe9g5O9OZCFItMPu77FDcQv+GjyCuswiVZI
kIOLZqHa08CiJeKoxO8T0BDwcLkBzaIfT/bSTG9ZrRnH5jeqDUElHneItUPoqDnxy8e/fS0ie067
vIBZSESHfdeAKmrT+YqIbvL3KhfyfadsMwaaKmj0cM7olLASagk/BXa57CTjqz3HtCZTpTFYS48S
Y/0DBgMoNQDl3yBiC1RCa6WDCp88DS9w8WBkUO4cC79mBn4f4P1c45QY37zLs3WlfI66hXXk8Esl
UhvGoTVfbohD5zeRr5Qfq0XebFC/OA+eWOS0/kvPTBFI6XhLDCCrk0hZGJueeKWz1rmctl5yBBY7
OA73sOjqTMd9tgRwM/rjMrQ7S0z2tCwQS7fVgKIu82MimVprgHWn20Tisd1WxJsoqxgv4k8pXEy5
0CeIJ2s/8Y4C2LYaUx0zsyA7AhkyvVL1rV5YKS8OGV5UjXRnY71JIXhZGDzFToa1H0SsnM8cjJ+0
MoTRXQ9NEl+7lvN/X6Dotgz9TGyoPonfJabPPoMkJJlaKsWQDlP8LFkdxf6feYv90IIpfAC3A6m2
iWIzGD01i4JQ/HbIJsUMDOD5HHcFRgEvJY43gtMArJ/gsI+F5PSjFGJSwAkIfVS9ZKbGsppBkkHj
88nCWmkbMq+bXJV/GcXdlI3eP32qUO+qusfg5nfWXqa6wEUKoOJqeFA8HZnQ8tpX5W8WTcGHg4Uo
jM7W76QNvXNiD73AzyN2wj1TXKterUNJGUYDsUtr6E/jIaggfTKE07H/ITTprRNhWi/40/aHoocM
PuNxlhW8WpgFv0G4Dl7uBiHT2b+fTybwJFkLmd2CO2Il/c2JI2DfSGOdQiJf61cEPODOmyjQfT8r
0yJ5JpoihwoU4Ir2p2IDsOFXUIKc7IFMBDsmOoGiuGdSWBqzLTDQqEYL57p/Zlj9xnRmPbUCcxdN
xEq3700rDaoVKkcpFTPzPQNbzgRxNJ8O2ejenp4bk8C0vqQpyYbNhlthjStXKLWfELHFD0bKLx7Y
y+PiDslctth/yXTFNci4mTjS3ksnLz2BnenxhxvFASHe5+QwgOhiW2emrZXTPMEwO7gmlTrr+r04
4IXTTADtuayytWlpJtGNqmgcJ1bkH36HF8SAHMWvDxbro8gPyAVC8WfTOemOonotVcZA8QUX2yQI
5VIbcYEL818Bc/od6QSA05R10d2/6wBtIFRXqLKnTH4m2LX3Sb55REwppEkysw6UsYvORPD4ahu3
ycXVsypiCfSEn9jjq9BK3RNmgAcEYu/y727FpXk26TerCsOTeEg0R20CO/zu/o3eRgCroiZEXcag
VuL1IjBFAPT34DJBEmW50dR9FHJQN6AKJjV9OlClU6bVUUOGyZjYYTSCll9NHuxi+9DzUOL8fd8R
e01sx9f3E/A3epOCEdd4wjxo224sBffTv1eHXiKnyiHZkHc+X+kla2+n95/clovFk57qnxxVttuB
k+/LpYA8WBPGZViJA30BVA6l1lveQ3+OQCt7Ga5Jbl+8NW46S/fHCc6jBXe4XIHGhNbBp9CEP3UM
okUllSudhsz0SIDi0D/ZVnEOC8m3xFaxyetRzuypYMAGEf/Dy9qHFUcAWhry+IjSLJjPapB2mlZe
eHQVlvNUKFQvo1oYxqIGhiIrhyKM+xH1WFwcsFILJu0InZ+BImoAUY55moJeoXHp/E204WwrptYs
9JvrnhIrvpvTDnEUqLNpY1wDblcOpUT6zN7wTc7F5MURBY3zzTZ9uthpV379+l8MsvJLVF1YOJ+3
E57JwWqZZhgf79urDns/+tGdyx3OmjkUljTPDXYj6Iug7vKODC+1+Vjlex9qwV2jj57c8psnn+UO
Yoh6BfMX+5GJqtg5IloX0tf+9JPHwD+kvWFYKSNogKXPwBEJqJiOfhepCE13HV1yzKTGx2m2Kr9p
msZmoeKNxAyjFspUYYhB0FDybgcxqAaHj25wQy8oCEwK2uVjciXifmQ9ujaTnl0Xl4EhLfsG4Jss
V8+YsTpigSP2qbgiU88HJKG6ZkcJakvUnTPVcH1eIQ/KD5oAIKNY15z8VsdXmP/jqfwa12XlGJym
SZ0FuUphM4oqIGdWjdeIWTfFJqAAjXWQxCWOsgsY31+hpa56HWbHRW2WvXJEtw5Chi8IyerBE7LH
8KdYd/SiXa4nx87mS1mvR+gdwpORyrhvdfzL31UJuo1WI4VwT+s4fBXja7JOOl2SPVxUmSyWsB6h
RLApMTlw9lDARBzGrjWX5QjaAytrd0WJmZDzwbOBay1xvCP8K42TOFhbSmvarmBUdAt0puiXn2AG
kZaCBBUO1KF5EYCsuMNYkBx3Wdmt20/JYqlISg0q1uMaXR/0WHCtjbJh7byJzRh9mwyecEX90bQi
UfKJTAC5SpIk9Rm5BwPoinFPYCf4KjvPPocBA+Bfez/i+jeGeUtSEgkwf3qwBXRhk87cd1KVGKtn
YfDR9pPlkdamimE61Jp0E9tgyTQyOyRYNfmWYIhogdlz4TNh/whnScmgH92r4o2xeBuD+D9U/rBJ
t6Mi7kO5jYRuHNTbZB3fpgt9btpx3wfs3VwngwAGiEMEzgii3D5ZPRlCFHlwEb73pKZ2esLRdyWj
OuPuSdvB9bl4jZRJ6qtMfUx3607LOmgedEnB8i8NUur9xscy0le4oBE4rtNbhla6M9Y9jTg73JVO
lnaVcka/NPsffGxMvvvvJTREVAY+RQ0JCtm9LhzF9X1hGZFVN2vN5r4izHL32okNfXFazj9KegcW
Dnl+ntwPQrRG8lNzpYfoU0RlYFPMI5KC1ZhDI0KWZMyVb3RgKZ0w9XtkMs+T6x1CWysRYPG9S+bW
kzqwZl8fH99h42Nclzy0ofL4KbNMkwxqILC1dLTVzD/IFEbhIwIe+VjJIy54WkMngbOt5Vic4pLl
U7NVMFosNBjNddpVkrxYdRxl6SlQaBoZrSHpACGdKMJrcMTp+DWB0JhGs6kT9JahtnVq59hGlWhr
8HwBy1y3hLY5amtEgrBZ6K3+6akAb0sfEFlwDjoGXSMpISgynbGux75CamJSP11qC5bx1mq6LmkD
c9wV14OdghmLVQjzsYW/S57uyUDyu11nTnbt2Di3Xf10tW++5xOdswS3U8+8jbEv8mwL6oKRiCwX
rBwE4kFGQjxmsgnIU93Tvrnlj6fqe1+4swp+u/jOwc1+tzGtAORqvtjJQJP2kFYyBvIcDjPqqPni
qBTw/xNXKx75heOC3nUcM8KPJZF55r7GTu1gYw++uaN1oXMu68nVldcEzhogbb4WmCxLKkWl3Qqs
Pa3MQrcxcZ/WKsNY09+nKpN8TTT64rXzFDssikX7qDcCeeLt6AXxSGrqzb/W23+hpXeqiObVDllv
PjirhzynXHSz4IhfAyAw4Y6okn2Ns8MBax35ACCArfnLTYJ7pO4CLgyFpveiJvE0sz+yWeoUzaG8
83JIlOc0NwSH48wjDi9kDnYXHuNj2og4qYHAfO2LHxdhDgrT03CwcDvmsQ3i1qpsFI+NqLy/zird
EVfK/euEXchoxPR77MC8LjRl2Yy3ztFgTP8we4h2w6Xy4hmlkYiHRPYpwlspFdhPvQT9fmI7gBoV
0vpEVAMtxVS6VlHygA9yPIpfn4NzT0SdmcKmv0X/iq9dv9+U13BBIsR89t4KxLESD56cD1ctb4RG
fjS9EPaevMgRMsqAOGIfetKShFkvN2oWhRKRkVkfP+jekI3wXMGUSJ0oi6j+MqfvKGi6L1ie2tBc
7VxA1vAnOTteyRyj4gJm2vhrNhBv36egxXnTXS2M5Q6FHA/oELiHPoVm2xsMb++/kIpxjIlAIbv5
GNO5mNqRx+8+05vDSvPG5UVpcEpJp7IWeJOe5kc+f4C3F0n0732Rrd2Nq784CdPdZn3RDbtlJer8
xBrDnOPBHVk6Twb0P4jzscKv85J9kZ7uoR5MwnRknH6Ewjz41qJReM6Oy1A8r1+Ey8sHMlFqbWsv
5TR+A16fDDZEtYB5SuIplYVhcYTUtbH8k6z3X4hrfd2IKOJlFqg8zg6138cWAZDvd2HGpT6RvriM
tEzMr3PUYMvpFddlzUXXv2og10os2N+Bi5fMIFWHAyseYcqRWJe2tHep8RoLP6dUuqaWK9elGqcD
2yF+Q8aeh5AVqToVXXFqZzCzTTwNW12u9HJiAnM/05Cyb6IV7C531X+aEjAurennLSCIzlPUWrsh
1w0TwU2eoCHFyMZjJqd2eauUU93goi1tYf5Hev2AT9G5Hd8X50zajEUQu3RNhu+/jTWmtIHWuWMk
8oT4snXRfCiC+LsWEMoL9LXSfBq3aQVI1oekdCGf5GZi1iPjl/LVdZyumHNcNriVkKc4tqhdbTlt
+bYw7elhaA9/5bY435cipBLyTK7X6td1FNaQ8p3QQLFkGI7EqaVuxrBXoM/oet1rORZEmX3GmCeD
0eFhzHs+xel84BuVjE1++UR1x1ZHttR+1hObQrn8uUz9x4muOmnb3mOghJ+ng1zBctPf+1z2XmZp
XvyJx+sdcS9lY6KDUhyaDFmiOGqaaLO/AgagDPVhpzYjfPeLYg4Dbp8e3vwhZ0WvSsWTSqhoHTIH
B0iJALlqdkDbuk+40momdezuHNvVtKXeyhoemqJ8wfAte++L5GLRipp6jU06Ii7d6WZW81203fuc
KST5rKGulp3P3Yr9XKjarmKg4dLFbymrXrPI4jgmpPwrSaQXlfFBqENhX6yZ7OCF6Vz9C+g0qD1o
l2nzn4FN+ksfrBuyEnnlfBU93jJwx2R8YH1bfNeE6R4Tqo4kL+CmxUn8iK5BLq4oz8j3xNdD8Ory
lb6CMxgoFnC0MJ6zH71fFawce4c9vB2fc+hFDjvkJd7wYWiTYh4Ab38EhngcruYvx5GaRVtp6NcI
OSuvFvGz3Cxi9dcT178LDvVypwlgKAVvTCxnbvoixo58/D+D/SH0Fs/uqtmG8Hgm5bYVdUd2r+TS
HpLPQ9Fdvs8HkYmyPFobnTOSmKfzKkDIis0VnVUJWphuJs5rd4jCOvvQbrN9I+SJq+YHSh1/Obiq
XOdly7aKVyPj+ck+OshshSGvR2rRDlJEvt1vjYsI67B5W3KqwI0j12409ixqGgGd5zoQak5VufrC
ZLzwRyfKOmR4G5ZXDr5jrRG42R6k3yWuSBOVlKhcR0Zga/avdx8j7v31qa8Oy847ajsVIX1PIBpz
gLtro258JTD97YCleR+BNSJ/IdzNZ5I0ufLHaJqYjmbfQ77xnw1i/+dVcvRWyTQ0/A5DjRpjgMFD
bA7nQw0zkxlYoMtO4XiKUswtmFre0BtNO6PF/UgKwvOGlBN1dgx+aKI5923q4Qb9BvVgzCq+7BPl
mCjlwELz+ogRxg+aCW/zc2r1nIeogjb1B4Ft0nT8IbCYe6Jp0OPQgbSOQiyf1uzX7F0GeAN+kp9G
emziTcvsnVQhOw/zzPn+8Z52T6cCcgO2huV5v44AploXPUeu/Gn8LsgvyhQAk9jnplbE5CAT9X1P
XABysD/8jvulVCrMnDM6mRzvdGOP+BZZ8fkmPgqX2EXMgOCsndRaqczUchAs/Plz4I9l8BgpEaBZ
E8FYurGH4xmBjoMhePA7lHuxAzexUP12eixS1TFPn1q5djFJ68LK3jXDxo9lGJM4saU9805U3kNM
U2/UN7JixkK+Kz+Jq3xeKm2BwoTFuauQkm9ttMv7AWW9FAJfVnYnRfKGh6NeWcQJ9UfaRx5i3Giq
9uBs7bL5pV9FHl/JFqa/bfZ9kvL4FcjD1k11yfBxYeFZPK0+SvDFEFYQwuFYQid1f5aKfNjbITG6
laj/VQE3uplSOgrNETLb+zAXR12Gb74iGwhD4ZmV9Pu96l2m8VDCRDlnch5V6zoGc2wquYAJ4/t4
+UOmjZFRwXLNmpoau3yx67RMmgsTs29LdTQt9cWsi2vod+KHg/FOlWR2ENcbftsW3kMwryAuJXQU
gEWDSk6+Vja7J2w3tia4pdTmg613fuSrO893GEx945ktdaQ00dFE806KGF0xZlBV5XVNwCkK/4mo
efw5dflNBo/PfX60MpqWuTYQXd9iQ4ZdsVxU32k4RwFZ070US5/42jB0C33t/0qJSVAm7GjmoZVV
3OCVEF+bou0YlX/VLka2lBtJUaNEiI+GN+UYFCIdZJI1Y2lwy4CrysKAREmKTX+m/PZpXD4KFj0l
jndBa81M4GMbpKII1W71QqRIYJB+ju4piZ4lRqD6OFUpUoCYwkoP368LciQnpe0iBUiVOLc+7dbY
vC2wyHMfd/MPm04Fjco+sTNTv1/D9l+zn+y7ev8nWbXtb5ZwDcTZZVyVP+0eZ7NvnOKQPNqN3TL8
1Tz8GZ3DUjCprcR/OL53BuXcaq9yae7bRH8SptOAu8VZjMkVO/bORZDHpAoHB+LnE5OUVVTiWAxR
WdiadiSk9dj6+iP4BVDfh0ZZUqJyuEnSumn3Hnd6SctsdlunfIAUj7MFsnerW2ts7tKiAh70btXL
SOAU6YuhvucRhyvclKclK7F2DwiMwwxdiAQLvzGHwk+whF1Mda6HOgabtCYudS2EJLdmfEz+GPAn
eMKOsUqWuKQ/b2ETNyZCvrQZ1z1JyKbprjifl3IxME/MkCo7RlNsFmEGJ4Pu5yxiXLB2pJv8eCfH
1NYwq1S7T6KmXC1HYCCcPHOhCbBYsvoV9ikaJfebeq34dFq+5wQ5YIQ8au69GH9KZSePx2cuoikb
EgEjbZCNRmd/EIsvYsKfa9dG3zBNF32Sq1x5KV+bUS2sf7he1x9+JK3t63fi8aoHWGKgUbX/yFtX
n2ixEtLG4YHezOz3X8Ki1rPvQOJwVQwIAt7bTj3LVegbNN4oLSdZvaZca71I4umazhdEeEvj/N44
2JflJYGYanZG9/XEQoFTarWXWsoDf3bPUYQuYyRPf9urmKCgO8cAXGX+QbOi19rRR1r2RbgQfgCX
1XIE4jUGn3AZz9Mbc2P1zA2NNkHEOMPzB6HlysIa3Fo8pQQnPm3dJWZ8jQt7eo5Ml3r92U6ycKGB
A27rM7JQNlsv5lcWIsjMC/U70y/I3UaNdtbAfYZFXStbFqAarMPHErtZPzNrfcq7Swnt15sk9wkV
6U382Sx8yj5+e+JCyIGMIxoBebxfjKgICsn1q6niC17BxOFUaPWiQeGrt6RKr3yoskh0FGQber9F
OLIocKlge3JuAmHhWW+Uv1YwpR5Tk5POtMtPwX2aK7AkahiPAIURqhHuusozJO0a+bSND9w8S/b5
Ji1bZwE/NdIixDTqQYaKj7Tk5uRT/rWVXQTkn360NF6ydOxbsjaV7s3RvFNOS53oiYB9Oq0a0Zle
3fm/3ym0emz2UoHTPMPSGj5XPMXBKGi/jgnUq5y1YLGa2+r+Ir42ghy630aI50791glbjW8U0jIC
HfqwDH6Gk9pdvtLuC7IDI3xFBD3oK8gRoxg9tyVeEu7oMp0QhOXQIB+ARHZkd59B+HG5tdbQYf+Q
jRzY56QuhKNCEj+mfkGXBS917NLqP8Bgh04H6kvVWGCc/e/nUFYjxfJGAyUClaLSuExDNNr/eL74
40NSa+hYkc3rhF7X0AeTp7psLyqgzayagw5AJxS5zp0jemXcoVLVPNWpK3NzW639K4zAuYMI1+Fv
GXgTidP36IlsU4KlyHbOjiQh4b0l5MrG6DTSiYcPCm1h+/ktR+VhsiIXYhPOxHMwbchqs5ZzYX2s
D+FhCzGdk1jxeYUDnERXgn+BIsMxKrpQTCJdnpmzi4EKtMtwvn2aRlhbw+DYJ+kgcnE/8onA4wvG
1bHxYuTU9szrFE3NzeJV0+e0wdDGMR2W7BYAYj38LWaPhq/H5Mr0FIB+Fd7Xrgkl06RVvSKTSHww
L1HcyvMcSI3EBYU7eMTQ2/t5+6rq4aDjOLNjSSLCaKe1DqegimtfIEnJUpTrOulDIkEBvscaDqUp
uExZgxei1pg+pH2T2GBphLWdxJQB8Plp5xelrrIgEXZSJoRClQcx6pk8W+K268Rs+jIaCdiKYVFR
YwCxbDpIdi+vN87T22U7m9ui4UWbX5K5A1BH/Uz9H0vYJr2pvyAuqyi9qiE0UT+XfNgq1aRtOKaA
1f4Jl/nhyy2o7NLlEJ4tiaZ5/VOhz2D7/J4F+pqA/7iQ8w60G96m7xFt4qNudFYQjjk2kR61byqU
rdh9itYOrEnKmssRYjEEWK/70QOuhV6KfAMTYAkPI24jmW/fTHK1bTH3YhQm3N/XCFMTMBv4OIt9
2lxTxAHAphl49mECDcjn+GggDUWyv+UB/v5+eFGri/x9P5Wye27duR7Tr5K8arcjjsd36EiEVZph
i/PmLOt9r4wzmF2yfeoGRPho5O8wXUIz8fvnLCYUc3AYjIEn07W4oqR6PnzyUbEbiUCQCMwOY/Gk
wtebNBAeXuCBtNLFOL28VlQErZb3tQPuyGIq6jJSQpphhIlNPPjoSI2QrUgtRQaErUxj5OIHWuqA
Ydv72zICklpQpEE3YvnX40QlqmbjvM/+19CuYGZQrR1Pkr1ktFQb6n8yn9j6zMsHMrgOZE1XrGnV
dN+cM/h40eQ7vpxk1PE1s6/fSmQFjSDCq5YrjXQh/jHBrjR9/mnQ1fjcBa3CU+10z3yVSC8ih6UV
MotHf0+XNNwp5uGE12lu3K4JxpJ13qCodFATSNhGv8bYK6trijtk6i5g9Cs8gD+PJsb6bk6+wm2I
0FhrBdkOR90YTffiZnTQI0W3HnnkXkamoSxQMVFZf1HKh7d3WOo8rT8/pyralqi4OQ/Cl/mLP64d
PJszcNyJsP9okJI1Yc3qmXMjKVj3aD4yEWIHiWXA2zPwvKNliAwUdPUQwKdDBAiMtr5mpaNuCusf
5OJ4By6IQRVnrU3BXEWywvPSs+Xj46wdb22ZIeVq4sSF4GDh+t6oo6GiJ1kcaTpVYt7DDkKgidXi
29b2+PV4Eq+ECrwBeZ0SFNnqv/yk3G+Yn1nQtuCIPOP3uaYT61ANYRPDWIVmbihxgMZyVq0UmfDX
c95FmWkCzjOJ4Z/Z2+iKoLaxlfdorkpQwnmE/xllM8XBXa3leWTpR6c6Cv68rk8IimO2mJWKCMDE
uSFOOvmBJtAyfcvSnDpLCEPVIbuOqQmCBPTIJM/goCoza/HSYG7lhkbmk0ZEUgyu4g931XvbM8uG
OJHMtjEkuwDXlghEMuQWtPrxo9QzV+PCSpKCwpWrl+e2wpdrctF0Jtc6wL+vN3hLbPYORr9yXIjX
tGh2U7xhFGIgwrHGoE+qzm9VsO4CnTHlNSrKo+ZpYcnJm/Rzspgt19LHLW+VRN6fbf2wKKAjz6wS
aJb0unWDrVN1Jx9P+66xkje2tknmeMR9yPcG2nse3+9dge3GJe+16dytrjxmNkJ3bqT4UuLQq8fa
J9gRtGp4ylKNczPfjNe1Adm4Yw8A1xn4eAExehHDTaevwtzucfw7vyKvF0+Acgb9e2hrRfshZAh/
16mEjJHVUJm1zulDV+XRv9RgDooqH/jqzhVhmyncyQqg4VKLAnQ8KA39dr0vAAk8KmGuQPbPbAvO
BUgkQL5ufRNNF7hVxPNegIRQjI2MNORkoHziiHRr2i0WUz8MIlT1pYw4dgfWTbHVEesCB4Qq0jff
hhYjwHbKR0TJXJ8YDiUCPEPd/azWxRzC+9VA1TCW1NmWN5QULNK3OVpnb6yn8KGL8lxhjBY31Gcb
vhpWEkyzVL5cUTh+wKQvUIDWoIpy3YPvOqnhv0/0lxr+jOubYl8Vs+SEHLQb03FGstyyfpKayV2M
h0X6DMluKypqEC8hoJIuDC7LAqnZlj9EqCMdkzpfCdl0fWyoUBi7K4lzA8EQUbusulY/f60a91im
9DuxvuNl4jGmjiqbwvlBsWkND7HDV8sNjcWfuEG1c8Fo/RC5zgrjYBR7Fh0b6/PgfiitpN26ArRQ
I/wq4Tbq5PpTWCg5/jVHbXmp9U7fInVhFsG0GTh3iX8FJQGfKAdXpqfl3GC2gqnqDacEawOvFsd0
Gb4r8GNgMGBQQLgGh5fRXEorP0gRsMPiMvbrQt6BbAbOBGclv77a6LXreI1xMlD3o7LeS+p3Zqsf
c9yUFoc7kQXr2wZM4DX8Ukp9YoDjFOEgUxGGNf5BYqepiGTuC/lNFj8i90NxrUyu2EEx/a59hnVr
XDVR30vM5WPz1daLHuJf4csxi2ktVqfLFRwK+7HQV4EKJ1AgmQqpQ9kRJBZYEWNF3c72pag8hBlj
u3w0TpZkoOTozRWJaQDhG+UWyCRs7DqT2eRgIMNvDSwWWSnm2RpXzUbJRmawTUu+XRQM329Ey8cl
skLdzWBnNpU0PF04biO6fX5FM3UCqn+eEEwrAOWWXG8Q4wOUwcgxyiqrH6rmbcPpwbNkYsHlUbWd
bKxeN4swExxgqOI8LJQw6fCEOv9rARbDrtXoAao6EoMO/f7tnrD/aHBXBj85Xp/zwGcymcyiFuFc
H9ESEHrC/UAjXBlU0fihTYMVka9L53rzMCAceKFLJ6Lkvt3bGbYZJYd9TST7zDk1aqSiyZ7yn8sN
L5UcSJdu7QxZ+wZmaCarUGIXRNw7QKDb5J086mzB3LeZgAqV1AusGRgmhaeJ4R+zDzna3QQWV69U
ZTwaytakmStJfPPlUWslMLrce+9akZ4k5kWooyxhyYPB10Ap8sP3FFo8SGg34rgcMrz2g/WezH0B
tJuSJMhKpmry6P3kNcU1DXVmltLVF0zuwVIcBfrTNnyTfRFf5rlGbJTqs0HgiQhwazuZMej+hj0b
4kgJ2nN3Mzrlnoi19k4KumhzYRwAtlvzzB+j+gU1WH1Sar+iyeC7+q8dY/tZDU9yjQHfxQFL7Bq4
n+0TQBgd3doe/9gsnoWhvBy7LRvwFRHkNLj38b7kni53cEOKf4wzYEhIbyegktokrygTMYeLop8+
Ehl8TbXcgwdZVEWQSHV8Fmu0l9AAB4w2Ixw5zlRSp4k/1+oRUS3sgSSZZQLCoQFkgLuUPImhAbrs
8rh0DjUvIIv+RCPG8O2k/0LXCBmzNXaCLBidiQ5hn4YCjIxGVCnEMO2j62Qi2wuEqkWgnE9DZ4Jy
d1VkHn91/J1MM4EuVovaXFnnJfV0cq/06g3JkfF6ZOmsC5E3LvvhsdgITKlV+Q2GPVB0MNQr6ji/
qqkDFSbLs87TtyzKVlHjRZZKsvfxdpKtG7Lrbj1MC7hw6fn0kOQZ9//ClI6O4xqdbqfREXG+5znY
YDa/7UyhfXvFvog8SEbqGKItQVWDpDTu94WpqatbJ1hWuFmAg+Yf8bn4c0Vmpkg1ADUENS0mZkID
lWPkVMb8ue1fHOG5iWLB5Ymzb/CWMpFLA1npwHAsMlr11/qa0AMbAXLOP/DDgOiZgDwuXEzCM2Rl
yL/uwINEBM9KffnhOvY9JahA2kqjZPd44SSallnbsb4iZrvy2dGad6rw/2b1G4ywTdMyAbR2oDN8
PDeO3sj4iBjisyngVPc1oZQqQLXxMVO9BPNc3iRSL0takJLA+GAyF4l0EqwFbyKFnckautREI8ni
6LLpM+6FbPaK8Wx7BixWkAYFJ52Gu+EzjNOT+bvCBCyCyhJjMQEySrGaV4XV2biMAzulqP4/SB+L
ssYgEFSjternr2PcYuGWe5bqOgZjBfGe5vz6blM+WRIQ902kt1kHE94ouDlKWDww4bsxTEpgnen9
l/pgTa5M3bjLZvNUJm3JuwKJKJyQhNbva30LysnrkYxMnIIlqU4Ark/8oU4a542jzQl/qQBxh6Vb
v4xJXH82d6Y5g/DWNXWbEPGftBXws+8U/IYT1b1PJZL9KHNpeajQIZGUSZZQdTKQk8o7wWIaM2KU
mGdpEWrntVbO9qk9fZhuqWfTm85GDDHzQwDeuQfcQ/ojKZr9WOCCgZNP6ZNb5+wsuMxLFBtzUefY
OngCFS5T6s6Mq3tpNQFY1Fk8zY03Dhq9mYzmBUHhW/BiivCoKeKSpCHCWzp5hKzCZDTyQO32FN1k
hab0bKxLyEoRASZ3NWok6n2QuTYsf7n9ZEGBC+8lxl/W4DDV7r/4yn0F6Bg8YyHQydr3hz2u3C/R
/wCnHzxQSERZFRwgsMUdc0qakoTIP1mcclp78AATq6vtO33k6R5VTc0A3mT30FaQuCJKbXqKzmDs
z+7pyrOVnqlbb0g+MsHbyVQOYLXYE8xaesoRwPGkLLbhCG+typCiMXI8ZZJ9JvyrpjnXC3CUUQNG
sV1drqi2vn+0HqHZZaVGX3oD1zxlVBlWrKGaX146D+wiR350FkVOk4SlMRl8TQ9IUBWXOgnrKQAc
1+on0yNqFfrtfAHPLrruV9X2/lOheZOKaEZwrdJ9PvZ8iUEzjqr18T7Arhb1yo38itYzJhM0/BeS
qp092jI2ASTqDwuGtyD7SFaDNrSGEizvbTmg6qE7u7x/eqm/mfDAM36+pdRzfovtr++gX8tkf2yU
7XqqhhiNmDWqrKJFbjW+ToPMPBMjUHPTNDEg6Q7PmJd0ADCQyRw6CZVFURkokY45XJDCpEPaIVmN
P+Er4gUYVeDR8u4fmTeS/fbs2FVBORSJE1moEn/HYyEliNC+lUpo+EALIghWouwkdhJ0yjtdEaeT
5F12pRPHlteXCK3Km8XPk5V4drx/dwTCl7T1BK4i+XtJjShm1UaslF8aI6c6xeMScXCk3688370W
E6PF9JS47CAkB5e1Gu9wC/E/yeo1U8jZUQUnZOVcJPo5TzcifAi0yZwmtHYczChE8UOjlnW1wtDW
BbgNZjsXZ29HtmGVwDvERaHqXy6kbHcKBLMwGgCNZQqgi3FBtkkydcls0BB2rAg/AMlE1ngFN/TZ
Z9A8qlGL4a/1MqKRF9HH0WZm9TdsP4Cqh5QJ3yKYpiU0zgvE9BoTztR/9NH8aC3Z/pD2vzUwoEOf
FxR0kKu2MJn4MH4H3UmPGHVYJ89wCvGYwduE5jVHLZItgGzt/TCeQNnSCq7ktfE7fQD4p2kvdFYW
U3b4NLW9cw2gfp+ijnv1MCrlpU7s4nu9O0k22Ypc07OCVpqYAprLB0eP7coQ5LDKcYAlniSNFbol
WWF43MuXd+xhBOFtGXPpXHezjiuydIPjOJnJT4DADyJHwa3mHYygdWMWWa4RF9mWqK+zQGKScbw8
VYJ0fPv83p8ANISEwhLMw11SNgLGL2GnPJ3BeOOPclyNs8et8EmVJa6+/qqrSpMuJVTiN8suyNM7
EHaKuBRCuGsLV7oNvERC+N3Mp5qyGpK9KNgE6D8Gj+10sjzhYQP9u7Hzztcf4P0P7ZKBM0ocIiDA
rNXsRuKB40KiiIllqJxxSsFjIK0DZIDaW4LW9FY6IU7uZItD7/r5Pb2AJpFnpIaHygyQ0eJ9paMK
7Cv5tXCV0X721JJyi4a4K9uXHr+a8DBl/HMu4Y16XnnjcJCQSaybHKAQYAyTR2HrhXchkVyH2BZb
Ux3lJOCxBDSeJ/ihNHR7SKmnokfKBd0kxJnyrN70JqXtr8kobIksWyDEDX2zfd8mcj1aK/prOjUb
itOXI2OGWOBmVVS7oGtHmGOr2qfnL6ukV1wadEUOtk29CwKsW16zzZoVJYeA+VB3RdPJ+wfwPOj7
81Cd24zBnUxP6s7OyVzfFqecY1w4DfvsOxaDAgrbg7F5h38YSY1VjZDZtuvG4rn+YR2pRpHQpffr
JifznQWWeManvSu0pAZGPBPtB2VmBCUGbgA/QI8jLpi5CAILfQeMPwPktZMm2DnDwWbI+q4OFoVg
P490zGCmjwn9TTTPKztZ9hrezzA5Gh1WKrNGh4C/4LSSERiIyUFK0gpfALe4VIxz1bDyCIPiRqYI
YM4zmFDajstHPgtedXz5A+UUFFcBungDVmc7RMhxAhxFhQ95warvht7jQG5wcaP5RbALyLEvYPZM
fWnSyy7BShwZaO5zjc9cMyOqZvXHvmUh5kU8dJ+9FdGTX4b2uZ8hLovwjXHyyOWGfuqPDsdXuBxe
lxrKoBh2sfNQ0C4/u1g8K6OnB6cej4uCPo18NxcufBHCd6OLZmOEPXkIBRkRoTgWjonKsr277UN6
E7Y54XIhmMfrw/bD21ZqowxG/o7UbJR8DrSn8bdfaX9nweTlG2cV9uq0cOjOsA+qi7qdlQnchy/l
0gpxybZPfmtVtK7FRyxgF3Qkx6bhJaGnkRczL3eMlBHL7wgG+1+x4D17M+rjeakguIA87zNkLLuk
beHcu1vCHXf9Svw9EEhP4EW1xzq6d70lLdaBDP7M3NUdtS14OrqxDyRnsPjrNIzki+oVh5GgJ2Vp
Hv3tneslfdgHMXY7aHqfLuuHtlvRvtW8t7Cp4vSNhdfqJvqeHE2l1pJtRrvvLKicmekU8D+k1l8i
CZ3MMf3zA6vUsZFBvt2ukzN66emG7zxx6iO7JfAuraUa73vl/ZhyEVDdQQhPeSu1yBRm0thq97hp
/CijQ+F1fXfcmzFYflQmmT3J/vMSMim4KL1+NLpq2BbUdholo5m1w+htFaT5ikeSCt0VF6M89IAS
x8QprkFdjqqRtPkF/4njec7KxZTZvN4qONTS/Msco+Crv48NOffwNVg07Yj08tPO84mR5uWEuysE
Ys1qDRyODDOBDnppzDL4U7sO7Q6d2GAMGU/qlTBe4zg0up8s8pGUvCHoiV3c/hOy1chbBsvl8rRp
kf7wI5172BbIMHbm+X4g4k8LvxICH7Yq8wQwag4UOe6h++fajTHXrJKpWLs0NrkqJU1Om9kSofDv
ONTLSm5MKzDFrPzq5ppfrY91H9yVxf7O5q8lkF0d4d6MZ7zQbZ8xm1SXglQRP132aenJaDjhgLJ+
r9yPj6sU11/1b4sihbCYI/jqMsmF6fuOmYqL6fmCsMn/ky36IrIvhMrGq0H8dYQGksNVQSlZkf72
Pyj+rfbd1pHjvMmhgLNJ/MVmHB8j7XfSM0zKMee0dIZjTDEInkKXTlbp4JQ9thUb0/F792Fef8jj
yeWK6WlOdIcwsy+eSyArqDX/1RmpMs6s8e6wf3hvaz39jF0zcdEVxxFXML2fokT5t+n10TQsiv25
qBIpAnY6/rpfN3ReG9wewsGNwhiewn7x9vvltza92hX7RvSm/VnoXe5ShP2b8soHGSJM2Dxij5RR
rswNirU5AN05jgXZA1cCM50rz8dBoyyX6flFC50c6LWq/BWAUnuoimSdAythk6rjPTmhlq0loYMU
qnbRNvRZsaolx7pYDEBKdw+N4Te8qpnrMzeJuFXlWlQX4kOBwg0RcNGXzJFyeLJ61AiKB6OdCfdG
ts9MRvRsEDTtiGvSctAFEYQN8hZHup9JXvsHao3QUjjVSNhQT26L79ka79TkNosd61MI+GMUuhHd
B1MiTvfisykUGjHmPazOcb9/syfqLvWlESjU1cF+Kwo/HneHdGcs+9prVHfp4PdDHTcNGcc1AxDz
r9VQZGlZO6gIwS/KwehKiav12HMFV07j2sD6C0I89l7W4x9LZf7NOfDOTeyDbsiho/R6vgTOqCaU
Nxs2RMSEXfRz5or+LEraN5wfMwsdXlKVmIeeCNwExtOKKliBJWSFrlbibASaug/aWXpYwQgTEXCH
tnKSIe5K5ULdsK1o5njtiiBoYgirdvBaIoXCA4Bs7Dt1V/VJX0Qaa42tyfBVvs6VNkiqpIVeR/+l
me/la31zK/It9voX+D153f5HhR9cV1lVaBFqBn7DJE7B101Yxj5OVrvkyrKakT2mnxgeBzi8nvmU
Vl4TYUEos8pc3WFpyuSKjtnCZFfoEsWQKZv4AH+DXixa0oV06kZy8upJqhPhmBp1Q2wFimHVTDxF
MqptvNrJMvV0fI9j2/TkwyEENcrzuSUKeZ5E9NArFW78DpEoAu9F+IHzjiL2BChFv7Nbqimqcgm5
bhsm5lIhGYLAKaGxWFOSzlG45C/6DTyJXF8OALITo8WX0VSTch1bu9TSFxtZdneyyA5TjxNp9IwF
JOB39+2OtoUnxwON0qTdNadtIW7wUotqJ0SI9meDJFN4ViWNm1T/ydJXanbaawpWNStjq0P5XQ+1
cHfjVHIru1KT8qHlafFeAYSyX0QfIikBrUt1z5oDcvFHHE3IpW8ixlfpX57RKKZMZA4ho6f/CW3e
YmqAeqUilSSg+5QY7U44JPaO5JqZGiQ6l4TkAcsB7I/xeYBlgTdeYHWM7+6KjMd5/MdYcY5YQ/yO
vZSIKK6hiVvZzPTot5xHdUtkyYmyTnpBWDWVzTqu/f6E9eqqR+aeF8vcxUDDqWqbj7eHmkLEL/S1
WAo345O6H8FLJmG0Cu29EwR61bzGfVkuun5RCtlVGAdhxaQTYecGq43rgZh+EsnRdjMJ2C42ToRV
QIOuQTWD4JocyMAa7QMM81BGDF7QPTItPp+wsKVZ4VZbhC6XGCrqbNmJRwKb/CdvA82elwVEJ9vJ
RY/I+WoYxt9A9j1XcU/PVQ8Gtu+K2K4V0HM5BMNZeA2PsaYjulrAXdrezxqzrzZUhuKnLe6yNnpR
uYwyHW7sEMFDjUsWIZDKl7aeZkHJRMevWkhOinEJuonIxQtEkAkefgh7PE0n57qAlSEE+GQNUkUc
uu3KDsIKlJZbdKMFPoNAAcD0lbvb8D/yrwm5IhtanymrStmD42jarHpYgg3DsnpdYGCZ6eUu4Edi
ecJ9ZGt4T3MAGY4+cavWWIJ0cETuAsORXwxgVuTEJqlPVhDf30USVzyoe80jnGaP1269TavU1GV0
grV222em+GH/kyisubTym0qUcVyPr2IHEJx+OmH2d9+tDmdGPimVq7kUL3FWJZJ+bt8W+aizLLEN
mQSb8jjJ6sFtc/cGAMSXWHi7keFSg8Vj1EoBHOKazFrh7r3lQokAz3FF7MBWuKsNw+tuNWOvTOU4
wWLDYa+fA01gQa0c/hAeNJU6lkqJeFIPwDhh2Rk2xzxlubfYXAn0+Qo1d/iVB/WJDWjazpqjbVBo
kOu6SEa7oNYBFGfauW0vnFvkwAuz9NNHm8Pkdx0pop6Q4iSMJXcHuePPp6zIa9RiAvs+M5LcYG41
So9wjfSidc6DGz28YWr/MdsHsLTRx94rqkDlAEtPTE2DJYFrHp5OCf+IXNlFhIZZVfynfDuOvbPk
fN0RxDKm32Ytr3+eLzWweWUG8bzx1dWYITufwLSVL3cqJ/5D413mjR+pB0EQiEMi72kcvTvY+/iR
Ju8RSPuRSnChF/xW3hHIInlob0yKI9IYPK7qCi6+Rc6IXcXUUKQiBjNHo8RhVpzR1B4e7zQ+wNKU
XXsS0oAskuwH89M0d3eV3dz4OeVAHPxdPS+SUggeT4lwmF9+o8/utjxxbdwpUYpYG+nFU5v8a0vU
C8+wOWURcrvnCmGHnH/RbFFvUXwjOAG26Gi2bFkC61cOfjDSt3uXL/U2Vmluof0g1MxSBxPYi52A
ltwNBHhoUDoxNl2Nlk5YU75u9vh4Bi5l2D09yrI7kJDK/w3zdMTCqFPknvaf+0ZRXni748SK5zDw
U4laQxR2KO/ayTngt0VD64f8Pbjb0aVrbyOcgs4FbOZgwkCa1PtE+/9xSPQlH5cvAPZz9nDkEYwO
Yms/o5NrEYlT6ZWx1jENp0gmp+WMjGxrXJyif5b6tj5KLq4klsKMj4CzQR/cmhz0EmpDRNJXk10r
0F0o0lk5imOzlqGFZlGfZmab9lS/56VmNCpONqLgT5ICssRMj2zS9cOSwTgSmzs9U8AaHsD3iHJY
0L2jrmhmp5heM0Ikm0r9SWCn6ui5177tMEQVElyKoxG7OfZfdKkuZCw3QTA2BBKuGdM/6Y+mhGsR
f0FbfHwrcbUdVxixsqVOIo801dxVEoJUG0G3x9/hT5siyWWC7QFSQ2IeE6qqC+0JDOgYtjd10WVy
wolv55SgNPKTZuBk2uVktZJgebpLG7NgFO24jp3mEHx8IC2ThvPUZZSnDPEw6yLyXPnMeWbEpUpx
pR7Tn5nLPt93BNtAFe8+6FObKt+MG6jnUOSyq0usgdCXME88saUxoG2qYrD8JNPC7y2vcGg4rhX9
LNCD1f5gYDlDHIeS78qnfaGoDaAYN/CexBhn24afQRuGd4yK9KI8pjXINVxePTZdpYVlY84NU4PB
oE60HHcjPVz+fTNYu5UmEbvwk++zXfp19s3v98NC2RmATnO+vf6qND38KOD+4w7/PcLuhd+7wwo5
15NNDSEczQ4OApmBLlXnH0MD0b//PrLXwNLUbGowfGyl2Kl6rrMSC+pWmCF3fXtOE/iZYk2D48uO
9HVfmZrVKp53CZJKgpomZV5JiOzFpgVeKcTdEhRFl9JKVnmuFzTqOkPXRVNJgT0a2atmPEi3vG3Z
h2meOEaq/62r7fEZ0XkI2+c0JhTduN2N9PG7yedbiBdL4YUblchq1VGKFmHbrzh892n/S5OgCM6M
xvMEg6/O+lOIR//XlNavRXJl/lIhCUO8ZdhuqqCsAWE/C+1cEWKoDymngYDnmsYFHTQbw9kjyaGN
3EW5pP+4qtyFqFi3b5ITRiCMTG4Ii3l7BPQH/YcXc/hRO5A4mvqK8RtR0DnSF2BhoUdYnMPfn2jO
M7IsBgp6HOHE9hGsf1QDKz5NQi10hzdUdlKCXMwl5qamCgN65ku0IK3yn6oVrDmiQnKvxpQy9BxD
F4G8A6IIu4SOydgg8O2wdgQqG4+jv1TBY8qcaHpWO8oAJx/jv6PRE6JxuF3iV+yb5WDSdGwfIoSP
d2VGoKKlaKf34SnzUFH56jy/VeqhuLThNDU7+LmF6j4P4nttBCint1c1g4q8cw2SljlWo+Abzk2C
gTyiF++PdmkuXpv4Y2A7/diQkyYdXTqMg7MR4bSsU8wCFzqp62sqFQOiyVCn4ql72DWDMAqhhQuJ
sChH5RD6mNrBokB4NOp4Tj1ZAgJOvfLeSgnP/Dq5OyaTKNDH1ZymjVBC8LD2xBpc5voKfWsV+srp
PD321N9w4DCzhO/bFuIpR6I9sA1634VYaUMPLY7rTS9DbXv19NOJV62CWtPlKNZYlmaUi/A9qDy3
LT/uEHxXO8aTq7GkwHoMeaQF92CJfD2rom2rNiZqQc88UUCOAul6giHsPdIpqRn6KbZOXyxhu1xu
lDAi2XcJRn8snJLLmvzrPDjxjHN5xJvMMKaXcoZwlhANXcG/pT3XipJ3ekiHo/BOwtVbxzJwIVl7
TqF0M4oy3YtFkH6KZ5erojKalJMTB7zhjR4AN4cM8dZ22HUMqYs9sv55W9fQ8mQneI4lhR5REE3V
yRYF0ggd8z+K8Yz0oQkNxqNrDjylHMPgKerwHyiork9chy4Mg2Fd7mAddHpWcH0DqiKWhE/mDb+W
QMz8jnPV9+sf7w0MYpGIES1qEdZH7LSmK7kKKrq5DshyQxUE+hLkNIbevHPGLCZMOQgkiAULTr1n
lt0NJtTbgHq6yPJgBqpGuN/IkB417Vzi7Xt88LhpWMW6CeuGU8yqZ1YOPNUSRWD9jK1NqRSKRdqP
3w8Y/U0JHfAqtK/YHBPTRX4SrztL9iJ7dUyY2bb5Ftk1rI8mLAMrwjIhJUvkMdhazO7+21Pv4Ouf
lCFESdbKxzKvbttHXoYydFQTJZPW5i/DBdJz3EegkuNJtqEcM+X1PM2GwQFn2RiKMrTOw27iafjH
5bW0PwpTUyn6MV17R2L/mW+bFBGDtQq1KvRCEAjUZ2vWDRXzxhWCm44M6YGCGBpDdJsA3byxxaGW
SbergRkhS67O53LJfuXwf2YOnbU8Tt1SPfu31imai0lJHjN6hq0Bs28+ab5THFybfS/Y8b7zXqxF
qe5+o+PNACtivWSqgzmNEtXTut/r9ToC54PZ3dBa6Mm41pT5OEXPkNJBwzsi0LsJVAGM24QWN6Yy
SwRzeBKvwiMTXJS8pTCDpcUMYAumUcQIcGpwig4bv/lKaV9F6jodmFz+fNYqGVd87cdb6wgqJzOW
+aYgEwktOkcpv6tNYyTyBzraJhES98utt+Dty9fCP198qRhIyO2ijLSLw/RfF4EkuMMI+bYQtcc4
bXqaLA8d6X/SfYXggXd6yEERCCUKRa3YwQPGjllw0QAF9qEWEF1MRiT6dea1PFqs52wyd4kIB9D1
3ovmknO9ApVXdQd7Gzfqj2INu2/qILQLkcCr4x5UhYxclpaBSgOt631qoAn5D2bl1/ZhtoVnY3Rz
QNwbJddK1FPamNYSCHhEvD68EsyKZFWL1To28Kih4k7C7YQPuqcOBBwLHIRq8bzYeAaQ+hU2mSTC
ZGWMqqUdUgyf1Vcf6CWwko9KXaXzo8uEP3KRS01jpk6CZ4kY7P6unJvgfi0YO5gcyd25KMHRvy4I
nXzth0YoC1bQzcEtDchNOrW6Av1pT4OjSjp4hx8HTC3KfhB8UxYHYQEfCDoaRSnoKeNvR2RT2vd+
XFX01pVttX4D+pIfBOAKlBd3/oMieK2ls+sselR15F/ZErQ4haS0S3q1OdBRlPmNCdzz9sx8FsoL
OELic/n4ZV9bt0gfHFs9mBzAFqEpstUKCq6Lsi3U4JPlYOafFyPjgc3mDMJVUcPAjGVZDjbh+LjE
MIlZ+JkjobWPfxtcgaos/yhm6qY8vlvpR48B2HFaCyrXXM60oX6u9qCzy5I089BFBmmzM/KMIy2Z
/t+dBWhx4hT8Wl6LOtZmtMUGDbe05IwfUFY/ogZLU1UseC3EAOs4wtdJ/aHMecbvsoYuDjP5cJ23
wRRCHbstmuRHHA7ADqxP5rRavnTvTc4j4NEAJ6/Lisc0QLB25y8P1nDH5+UBvFoSVf+5vq/PFWPs
jdI/8wZuBKrGb78uuBExg57IYKzS7NNLwdRSBZgiQdFqQANgEWitbeDlgww5ZTfQhMzD+f/Didl5
n/cQQv8t5NRSXMG1MTby/VLK/jO5StlRMbSEjHM7dEMXU4xhwF/v3Qlx1gQip6RY71kKOTxmeLoL
W/kfXs04I3qLMpJfBsLomPbhqVvyAuZXFMKx0P9XSi7vIAJ9gkmZl3jUEU2vriouwn5ZkxjZE2f0
N8T3BMeMsD2LZ1lIFBn+3Nuhmh8IqibRv04YXpwQKQDFzANRAMpYW+7ZgcthaG/WFJJar587AmVi
cqcZ68VMqIIAX8mJloLyiwOvzx/Yg8+mw1TF3RVVx4xWxVSQZZK+fXremvSyaiveT1c6PmjaeUW0
JdriqA9QgqyJYHciDdQTU6RWM53dFcIYiEHdtzBcAG85hJvJb5yYQs/jtv+znO1v2aEAIk3+cMkj
fvPNeRVEbQUo6dh5W+ALdtRuXakwnM8R/xRmzJGwLsFlcixB3Fs8G9utwILULK12wxyR9hRP3NGm
ec0xHZFliXxOql3+FTKL4cJEv02DkCbEI2uxE/b+7Fmg81Hf/VpDjPTnKPd+exFbf72DkZNrs/68
oR+fU3c2QelVtGrJuhm/1TsMZFjDNM012ZVee1egRS41AC5ePYIxLlOuvMyWyYgfC11wZfbmziH7
OaEGFkITINqJsK6FDMH/qlZ9hQNnGmLO9qxIpCkBZb8BKWI3dTXPzNmJmDvF17t/VGEyBcT2pDDd
OYQ0+6xGXEXTiVoBtEkEjD3pIXeRTMZ+Fti7HQa+WDVWMzp/oNokrNvX94qKnGSCMWsfWJJNBDXd
svXOYWcv9PJWb9Q6Pp1DjsynpJ4amTK/mQ00nSgN5qhQi4wALpA9zvT/L/49eAiDsqKRuhjnOK6z
9FR1dysWyTtQJfqD40u0xfGs2aN+oqWM01mAScLR+HtQU5MssVuLTdQTbRL1ZE+4VfGkaLUVlo6T
9il2gfaJpoAZDWiAFSeUiz8Bb2ld0trwMN0pG/gHFx4PGSwW5S1YLoVutmQ5gAbQWHVlQIaV8Beu
ysuUvGeF1RixSjVEFHIyzvGIe5zSTmJhw1qiur3Y+ps7PTVg40hVvrvNNoThopW7SwzTe9QBm0XF
3Ur+mq0pXFqBWMX9m31IWWiEiO24n3rHutYzUuMP9e52rxRVD7Zq7dp+ce7i9tQxtzN2OQ+Yf4M5
tVkO8FlVpXdFVW8fPXxmTxxQUORIa17u6dG9wU9WlAWkxbFL4BqmCJoCCxK2Y37a/XS9prFpDZif
BtPHii2nMs2BXoJ7qmRRMJowDf7miMc26xW7RulUiuKX7BNQVyipRwICyll+9aVVl2crx5eGYse+
sk+/ks8zIgk8Y8Bb+BdNNK2/jg6QouG739/RSZjr05I/tsmu9CYcDAI3Ef0tFlEsiF2kFmPUu4z7
57/PsR2LBD45odXcqPywCdDudXfWdLtT8MAdaR3Q/Hj6Xs0LzRVUnBPU72BcynZQH6sUSg847ugy
Hq35/vH+v3W/2O5W1nYJYLVXZlawoDdz9uN7+cznDOvWbz2IQzOiaMCmj59XX+F5nrok732gVWx3
0gqE5h6QrMlEdfqqZD8/jpylAjCAEteXTCLAcAB7i8jMwzm6hzENxZVAV7LW7MspGcNsucLGC4tA
aTEV3tR3qqHsVgZ7m+aNP0BNYvg10X1XNkN4dE32cJWWwIqHalGK+0or4NjxOKfFWnnOzqQHyOF7
YvlFBvXREJD/qtFdIJKUZLuK5FdGnehvu+aZjHB482bSR7xkfSp+yN6hjL5fz3MklRH0+Bon4bL6
dyzwlISBOS0ircThhT4PBrxsa3VE5VsVy9VukPM+LIxrXTQCp5yn/bhSI/lteiAzz6Np4DTBDzDZ
fubtU539e55jGtzvH9+1jZPJxII8JCf+0QHztU666qtLNP5j/bZ2Lr92exO8OkXhw65yIZc2g+Nx
vGn5c69JMnwPpwpOTMqg/g5k8SpKCC3XIzNozmZStrWosgQpnEEvvAbtsDcfHrStHkpudjxgBLur
L4DmcmKjC2svKslcaF8qKUvCSiMX9QGjAR/rTplD0Ec57xshxffI2IBu78wWDUCpCzyMmn5HsQD8
0cT2NgL19Fa4GmA5lLq28OCfnnIuFNYNej0XUmpaejmGyPIbyAFl0fgc1JhQDTnZKVGKbwwPOmqj
wpdD3rJXk8SpphuGgvp31VGuw2xBm+zV8vZ8PvduzvHyO5HN1QEYLGlaKvPfA6kqXWgHOQHCBUWW
9tMJQG4ivbDCDt94cVzMOmdGz+A8DN9u9lY4TUNNpspj6WlXBkoZRI+nGhJEbLmp91Hs9EmmSf+7
CpQYzDYAcgupqJ8JS+B0LPPQwB/LA6KgqIcIXBcQ71AofzWXfZIHJmX/ObKyZmfUbrtHfmCWlbMP
2ynAxOc/Rrh9IDo+ouhd4ZUzWl63Hsph+Oqy7ZDP1q4/CVV+DPPHLlzJNR3tJ8QFkdDq6nHGT7O/
8szVG6CxWjp8fiSfKdikOnczvsuo1U/HogMYGPcVegu+ad+JHAF4Gyt6Jen5Edx+t0kP/T/ebehb
YNHj2uNTzYcq59kfHFiczFosHNXm+hjswpe5oxJhTpTjxMacYYsUSu/VQxyQXR50+M6H2hlVScvz
7hPhV6qWF8LAW8y+cERr+TNZZ51bZIGNTqMs1YdPS+y90CSoKIuB9UAcVbNZzuCKhbJ4K0ylODLd
qBpveEl4Ti2FuuBbfCpujNyZyhhvPe/lLw0opugZUfQFpSOhKomTnhL/ciOzjfAUGwq3Yg1bDi9E
lqMVac5Ev4TiI5G9oNxH6hwdDI/maaRLAD7TfVTCtm2T5V8OtIlDj6tDEcTtl+Ez+A81Jwz2HMKq
Ovfau6Z/Oo1g8ue0XM0PbKlFfVVEgZl5jZQpgFqwS/2HszPxzKVkQGpeGmHDpWpfK4LCuurVv9Ov
k9+HX+LEdw7LFNBTtMXF0hOZDXzDZPqY+e5Ceqh0wEBbzYm98ap/fqyBN4SqBSHxnCK5AsV9DUI/
gwDS8C+2xakKnx8rr2rla3UHpjlpK9TVxFmQ5rlYlqQAt6fYY4im44vGa6OkvczrWJL5a8OOhOOz
e3NkH6Flj07zqiLuaQ6sdPff0CoOLjTd1O2p7ywWY4KQC5aNnYpMYZ1OX1PXfAwr8eFjjiUDicXO
3nS6gCfJU731alYeZrZJkxowz1zScVwZgMt0XAUtKzHTXEB2KFI069cg93Ih1MVuKEVi38aVtn6C
TkBiknQf2VqkHWegs51p7k2OTFD5u2aUhmtqexHe279eMSAoCzKXgg7KALg0PrkxKx2mdSc4ZzXJ
M57eQl9R/Yxn1+alIWLvLfr0B+imavlBPVZn/D8NYClidISDEk7gD6gYcwvgjLsOFa+DOl2XZXfF
pGSFz5q07fvmt38cnQV8v+QnmbOfqImdC2Yeijh/VLl1DnNZPN2jCzL2ORRi+ZHUK5H3/9OJxUPe
W4PXMMS7Uu7aUtAYEKgj7H8Xgb1SLt4nMq3B7JCbUK20FmnSCpnj0qhi+hssZzV8l26z4LX8Q9Ei
hs4XPBx84oW7pUhIlVo+b2ekf+7a08BCXq653E9B9LOb94llJ9+FTcpvGH+92sEEFtP8jL/HwUZa
j4BhXqrHwiNfKPbUXZeeCubnu1LXHg3oaB9C2yqKoJy7+j/vlCwyyEWPwwBsH/+3rKhTUA7hNI29
Kg6Z9KVG5ARRcj26tIjMtZ1vNQO6ZHfVHYAuKgLXqHZQxkPYxPIBU2Sg7BmadKaOy9ygGEW9TpgD
sK6aQfBz4KMwgiNRYy7csoRcU708vsnLl1yW23DiHJ1Epw5sZqgB3CNyUfimNnBazkBmGlWD2e0M
FEWziBXHl2NRZeHDuhRiwHpYQ/RpS/nEFW64+BZsCu8ZxZhffsjynu3H1em9MaLj5oI6aE7v4IUY
7LNqNky4fi2ARNaqIR8nKxVyliMqYNS1za0SzDtCXFevvRpPqmVbP0gBD485/wFg7BBSrVf8QJ2f
zNOlZwLIV02qSM2gDm9PRnBjKlneY6fQaNCmZpFMFuoi7hDs+1wz1yKhNYZ+UgsGP0zueVyACj2F
4Ce57MgUdahFFeuDO5ysJi//ufebxNigPntNN4PYIoEXUUkLi9YlfYY1AD1BokbE4IDvdzlwwFPa
QU3ymDMP80FTu+S36xV7TpFL3F8YbAt+2oa7pcVXc2oSorThKJdAxuNrBq7FsdvTI9V0joR2UgNZ
xmievqMmwiAWgsqAMgfwVLdb9C1PqRpCDlbzwsKajj7c9Q1MynVbH5cebym9KsgImkilqmyPyZv8
5wW8IXgOV5xpBBr1jQy9uE8dydmBJ5l26wFg2FUNpqEo9dR0Edw33Oc93uhFk7ZCMz1NbAf8ND4g
Mgfkgnc2PVQqop1HOnvPV8PZI0uSI67uJTiTUxaobqAwNUh/rSFU57cmf3s2xrDqpbo22dR7ZWoj
odIabz2BLHpv6tezRNuQlwL1oka83mj8WVlNhcUDp0J7LQ65AwVzVf2HVQ3cArFIxQ/wbkpcNAK4
lSSKZFfAPX1n62bZF+9M/rl4UlMYVnixllQfKx2MBWanHCf8RLQS8hWdmFQSdd6+hj6C4/hrcAzd
YtsZ4QxXmp3beTH4lnUnfAduC3MxKNNB/Dh4HYLuft4mvpum87xwNz0mF+aT+k9nzGldcUNdApEN
chhlkfwwdz3RjCWsx1PMJ67xrs3hj/tNvVDFG8tozeP9WeXJok+uP95pF4SsW6HYMRld5KPeJ1kf
ysQzDtJxs5e6rUqWoXNvTp1LUOvWEgLl6INdF/xJAOEyIYmT9YFR4kOzAioH47b9X6N24n7WvXSQ
f2BTTHs4o+XUtbOZvTXpwZq6/6LE6UP/LowAqg7Sm+fQ6VH5g42DA9mBfOn8mCdKp6UQvb81tl0u
NVM6Mb4t0vOShqy5qetJS1ZVFYCRBgLPsskEFuWxPxfiA7/LkrhWEnmzUsNQ5yo4L5EkIxzbHJNK
PxDAO5XJzQJ45WQ4ANDuH3p4PtT7F6XmSlSxOyzrjH68fopjk5ngFQAQdhI/Gre2nkeGymaJn+/Y
UzYKE5b8ZwLsqDA1h0FOy7lDCAVWaklTN2FpLLbKkwh/BhUlGYOZAoWjjP4HKzx0etSyM8Zy/8WA
2Ycq62CZiJzIghfc8dioNsLy2ZOxMCvzYV5mKQLaywUUfZeRo7XmRhzj3SjRNy98SbhMW1lU6gCA
naxzmDsWBQHq2XZO0iN12xtvwxhwgBfhUsKTzIboIkQt3x/7/kNrnrUlRBIR3fo+MRpQj9rqYQRM
Dip7wHicXnW3yVFwtsZSwGOY3d4ETfzk+/OrNUzyG/ZKRDqZlewpOv2MTfVZzinEdgeWqArOPNHA
MFypVGjCN2QUqIPG0Rok4BebNJLU9eWTFt4xuo5e6CoV9VvnTTj42zXua7eh9eysqD2r7XP7i7of
t1nMasyrvAX6uegAfUK8ErxN2IdQkPIV8+W5yH44IQGgtBSlg9H++Ut0rj7TdgpM1U/GfvQ8PzOR
HULVN4LOcG/KE4iLOr15SRaMYCw5Il0B5OdcVHaWZQPRMfVpMYqQeZZ4/SQyCOZ9iIAzw5zX4hAG
+MGfQ2aGjW0t9JFWsaK8A14MBK9vWRGx7PuMa2c/uj6Ri1AlRp6K3r2g1rUTaCGPMEUhHTII3Ppr
qpVEEKgqZzl4y1AzrH2DCuD+62iaFT1GsHq95dq4kOTc7Om7o+pYyuXoEvXeDNRCnQLEK3Np21wh
5jWoEsHwGfsp3SkGIwdWH1Wco+PQnywZ7owoYv4tLszeaMp9LPxJX22OitrxRW5Dajnxvh7lLDlB
vRIsdkkW6XdjNvnx8MtJZ8kNrNkSCIPMkYXIwUUJ2ISMl/ikmfZGQKf/7vSkhOUNYF5xz2fG6L+U
V3xS8C2Ak+qE9O6rkER4wWCc5W2DVbbZ/KviZzwF1Cn4W9YlyOyywwq8MC76CpTshbKo0HWFcDRd
hbE3F6pM1T1f+KUJs409k103pdWWLj0eaSATSriixDRxedn1pPvDkc2twvbAonEf0Xi9baYEmUjt
jlG9OolT5wr0/TR1FPKKuphOUMvS4tvosmFVzxH+kDwLRg9XY1YjvyW6ky3bp6/nceEjTbOQ+6LN
7/NJuxSIhvB1IImXsQfNQkTUQTQNe9jBpeXP1Ly0Bp7RstoowZDwZw84CPc3pok+LaAtMqDlPAvy
m4pqHjIviJHmBGJHqUkgipbpA+Hakp1KyEFQg5Nq7FNnBaOCn40oPO1uCHWt0rJ3sjN7c7nUJ/WF
XvPzYMOdIRjJDuFrxQEXu4YRO0hlvXpAusBWJVuYAst1eGLpIMdFuvamv8st/qP9BA4o2nZUQHaK
mOise3pH3c5nnvGBntD3OxmDWgivXsl1G+j92fXWjsXUjkjwAoDNSqEPEnRTG1d+HWKYaKlh06E3
q/j9IAsGYkaHG/xRVPNZfJAo/tQ1mE7SzQ8ocQYGZ7xC5mZlSeE7Qxo9s40DhOPqidTLpfAHfDv6
HPyNhtX74dKJ69RPD/rU2IjASphHgXr5hQX+l/6MqUHpJwkuDMAqauNyyRd3MSH9qGjxJMSij5lp
vNIavW9EaCeBMp0yVUDQbBJ8uaIOQi14xPmVYeOYcnQSqUAuf+I+KE57gJ0LBkVu+VpDuKnTYccc
bh5M2tgxR4YXL2Ah3u6QivHM5FZIGyWNfWMhalj7lvj20kFcOeqUMJXXSBRDMtGZR22UEWf7RiKu
/GoEmodVifl+2UgmcX9AwzBKAQszU1tTu9zj3BKrB/VxkDPVTX98Z9UT6cCQb9KZNFat2kJrfymc
tkyAtRO+ZzJbILsL9OH2fSV9N3VVrkGbj5HPoi8czd7K7a6FGkOmj97/QWreWG9D1Kcx7Z20sRPQ
Sfuw1mB+SORBhWjYG1p04SyaLHAy5LMX/zGuHBicuRsjf159txomEjBxaw87qmXf8dAza5iAIuVF
bPTUz9+MGjB/t3sXeSAauKQz3xEbyRNIIfU3DprSvHW8qbfvrA8w2tI7I1HGv1e6PDpzN3SZCloM
tV+fO0zT6ogCnq6O/eIAY6Vt+dKX6sIusDTbxGNhY4dbFtmMyTMv2YbDFGPO9NgXE1dRUyGshzNs
JGmUf0MEu66ws7hMI04UCzE9W9BGMDKIzWVIvKlddxusi8h7AK+i58zW3Hn+Ay5ZNx+DDU3JQ6zR
WNB6uFPnJ1DsX01+Y3T/vUpWPJHLrulyWdj0Kcaztv8NQ4bTCozszAySkoMWoPKbBzWv2BQ6hRyX
dQq0C6aIO0gESDq/j+b2dHMwH0bpcuohF2oWBUNO6lV7oit0zAXAt45mjpsQWiOcvy+Sf7Z2vIFj
4Crd8HSeS3rOg5XGQgMeb3FFdvMGRdu1xY4DtWLNu6H1vu9vF+yydOInmk/6cPmPTVzmqJ4i/BgX
fu1HJCjfCZVQ8bESLsiM4AIlLFYHKNL4XBeKa32Zb+J7gO1fH4Yukfn0vIeyM4JSQ/96j1xR9p3z
gyvTQ6iXP2d5Cy4TTSuMGuMJSUUvTVXwxE+y9RW86RYuTevHs9Tdnii2D9VKfqIFfdLS7siz5aZD
zr2uB0LiDWMSAHUjNbP9fAifBtXk4EL2oNn7KFXsFisBPI7BXtdpG3CmgJqqUkbuKy8e/mb7kfCP
NUiGodlDIXDo7dILe6hWDj3ccKNdk10QKN+7R5vgZtAoK+/L8LClqSKsh4c/kGOsANPYNR1S3Air
fHfoxuOOnVb4T6N1FtjD0xMB0On1Kei4mkW4ooiw5YtITb0Y1jyplld9rvm2GLS8y+xNzc4MzXCH
k8K8k6ZxLtHF2aguCH1w0xM3xMeLLSjejFlj6fs/q0gjxRsmD24QDiaOkyhCQvmw9I7KeOlRfUsQ
K4awa5KVUUoUkvO9hOSvznOUodV4m1/yM1q4tlVWce1AIbVlfxwn8uCWoNZkiJ5YowEffhXcV0Eo
xnsWHeyBA1Qs3PuTUeq2YdlPFBnk+mX6S492ZzOaren/DfsL6YFOvXbiLMcYCKXgXDpRtygzmSGl
DC4XeTIZ8YLQBZFvhMBd1T4JsN+0X2FNAmIfA6VzaL63oTPrvZ9acPqrBWt49YDgmQ/HgPGfYAny
9XE0nyM87CVmiUnp4f2o3fZQJqrzUuPxmY9HhxAzQEiPoIy5HFCYikveR/XW4hZjTp3JixHhUz0i
WEWpOm8TR94CFktbJyZVT0bs4vsBCmqAwr8wsGGqVDX+jd0eCSlqWgJTkdflxPtBBUMundiNm2e8
YzfpZuGThqLhZNbOtWo1m237u/e1IwDMrIFGPyifaH0wRV5sfQ7L2zp6MVOXACKVY3W2sBPOruRx
mI6zVe0rVy+dJtcNUTEnIGFJEx9wKp44k8TYn1xnUa84h78SrGk2mKbm3VawPEDcbLqxJbwiY9Cu
Vh9XXWRYDvdtAx4LndkB9P2l8MxA/kFCs7pf3QYQ8EUL5VNyMtrv6dI7NzWZsKz7SKJCY9W8oeao
DXzhEugWnCcS/7ONc49ZTTFhRHHKwxSiwOpsCuNmuR8BhzAMR2I31OeKT3m3855Z9AuLiyL2JIjD
y5ZBgwYtgVPSEfLafjQzg2OiZ5H5Sp51DuUyNaClw3QHvMH8BvyHhA1WdM2V5xVtK8jy3LFfdiQ9
QqeGVzgTBDi+EI0/iA+vDKBK+SPm31r4dWPZdJZlA/wfHDpkd9cWF3KZz0lhr0kdnDSBfSjLPnE0
m5SaFP/+QY3k1Df6ptcxoDtxL6I6e5N4W2H9b4Gny5g7ymycRoruRhjLQqIC8jVX/9fj0kUbbS7/
RQ3SuIY/abHZWobJHQUyLzSctsfVS0KJ+jO8R0t71Vnj4PZpCyq2BMZ7/+qjyhwTji3zDzi9AVzS
mRBJLU/Jz4nXFIEVDU7th+wlV+sUazCJoYWHFzHqG4LmquEEunnbGM4MDqotl9vcBIXNePjxsKgO
5ZeNVGLcwNm3/072FmdCQF47i6ZhtL6BaFmfs3skcvnO3t9CHWKIBHvTp5CZyyDKe4XIUtjffrdo
JU4COPrukCJs4C2y8OmYcNKwpuSR7llDAI/phBor6q+yWC51dWlDFHN9CS251eu71GsbpBNdf95A
uCWIeFfMoanFPKyt8ArpwwF6HMLSZo5gc6JIU/nndhj1PcvZQOlQS/pQspuNGb/nJQWGnMrrjbPL
1HCyN4w+wEyYYKzF/S8oZhFg8IcQ73bvBkrSaXKi9y13U7n4W3zib4Asj3Tx5upoOeCEvGsiqQdz
KaynMNeLJK9eGYRk/YFqQvMz26LHkL4LwKH/jQ1UIKE75+0ToPMo2UAtvrzFr+HjfWXHKEoxiZ2/
eduCNCqS1/F8Q4b+Th7Kqcgdn3Z0fnh8MYYQ24gvHwP3ZbBLWPLuzRmKisD3Y4Bo6d5IdwlNXbGV
gjT8N3Rs+9y+FgFAPc+tMLIkrBdC45fHcWp+GgJO3Vu5va+HpXpwWA7eZbczoyA3m8dkE04G5SP6
HB4UThN76XjZxXMONrJmuxW2bsu2f+SoVhbQc2XXORfPCj26JvLqjTaqi5EjKUStA9dh3aAN8Na0
hadadFrZaV3VYAwquwT8u1st944Ub4a14S2cyKzK6OCnVVSB567YnI084x3ALaQPTJs2643wDYWV
5x3XgVGL2gxaxdfoIn8i5FpSm53Teoqs9Wj8cfcy0m6a56adSEc55zU6be7OBTwLqC5idfOXe64x
Vu0+QoH4dhJdyBw86FBAuNSPh5uYEjtwOuCcO+I/Ulq013cO7eglt8JZOn3hzZ+B3jLy6wwrdlCT
Qkoqy+lEoHsRYCLimBtraa5qPwCiubixwNNjxAFXLih4puY+mhq1yBjurRnIksAu7TSV4JjNm+Uq
o3pbyLMCRmAuguXK6ofravhWiszMkRd3j7dl6JU/FOxjeMTHXBwpSkuM/Ld6RSVzUmO/OtW7Ho1p
+p+Pohct+YlFQLiC1NlC+IAwNk7DD5Z2miF2Q9Cu+YnpTIYBT3qk1LwCqQ3InW6euMtTEAqCyIjN
v0/YhlKV660P2xaR2+9yLNof7UJb+tqZLDCt/dKEskWNSF4z3U7ovCQaem/SEozFAHzobmDdHIOf
APwof7Mnc5GAPChryTQz87l+0zLeOjVWY18PtOPZhVHFuvIW/IJ47YgjRk/aera2LnItpIp/IpC8
tGpMbLYTGFo/OP19rH8r33JcVS75rBBElAsn0iZVPrhhy1pSxi2qeIE66Cb/se3prdmzjchNUsgE
INtTijK6g3RE+50EBhp/IERxzO/FAnpRZ+2x95s3/ZEDHun9Yr2tWyKtu2nIP3orGEn1DE1/eOca
o85wTCr/lGsH/xxeAxByfxaDZEAWvw2qXQ97vgY+9gab7n/mn+iurN7FfYBOcArVgWxZN6hPP+q6
UGJJBy75ObQarPVe7m+YAFpAnRyujOaPQRfPYJnzwKRYfZ86COL6ATLBWi1nPxa1FrmNZCZ8m/da
bM7EgVSLziiREsYSpQLeENw+nf135uVcfmZ9TyaQVvsDI7nCYlLy0Rz8QWd/xnE9Lk+NeatVRfwu
+S5NFtZF7KChq8WRSUtonMz+/bdL5G/up8ztNvqeXNWRCBg1x0oyueTff+DbE3d3aL1tuIni5JCp
JQLuiyctsXD55fGJCKqsG975XT4vP4utN8cCYYTfKOY5qDM1WJqINVnt7a7qq8gy+e1bHtQPcEys
AGmEE56o6lNLGLID5gwzI8Liy4+KIOaxdI7qtJHfwWu5vuf4DfTeZ04vtxo77XG+I5uy7Qyeo6AF
m9P1iHfFpJPOOHR6fozZMsEDoD0QWpLuZ/AyHqEQ6CtYzNfePLD54o1ZxYghIX4SbU85jcN+JXEw
Key/C0biU1bXFJ1Xt9s7eOPxKNkUTNoSXDgZDCLcK5ZBpGrrRZEBpYNnkWeNAdvNusZ5zgXjlhSq
rzx4M1t9rn5iVS/jZoqu6CsFy2Wn5tPW0368ZpCrKzGZUTBsaYvPKS0qP+yHif/ScKVYsIJXc8o1
WpOKxpm20sKdDOv+UMO3//cJ5fiAwixR9n5KU1D+B/5U4gBs1EWzYe/4wTnLnvouytaVDEy8B4FD
LmXPeOFTWxuqeMUbduk/8zxg0352cyopD9TxihQGgqRcJvQF0smSWavQiqNfA6Sx016R9ywSlBjz
ENBrKAzI0ahXrfnr9Uo5KOJqBZNmwZd0NrWNwbJwfrfYXIO95QitQW0sBFvOkakyFPY1vPFmyaXS
2/Gz7xzvcNkHP/74y6rLmCfmcHRgfzBtCFHj4+IYdYsxwJmxPkC2OToUcFf3p50lhdzNxHuSnaFM
ONH7LI2PBbfrgrtdaMT+K1ptZt/ydtRSjpmlN2kUMu2LeI1+LDBINek3XTBwg9PEPS/AdtpAcbEp
UG/gBpW6UJIPlJEXe7MmqcjbrrCExxXVBd/SyUgJUfEuplbjDzbjjbP+vDBOiNgNrnMhT5CuR/sR
lzrVah9iA1Mr9HR9CEla842IQ6OCxPDQmKEWia65x6oLzam06tzTz0+8CFC8MNVe18+j7J/XjtfD
0OOYh6G8ffORS83AwRHURzR9ujCD4cnWBFIGcWHGKvGG0HrsFCmpmUW8eyfsdZBDUFwpgjs1Rlgc
N4ohv0t6WCboQL802kNC1ilmucpqMRie+ye3uwRVFWPC2lK5kxBumg7+QuE/lXpNsHxXsbbuvNok
tU6F3OExu+bGOD2JbjcmsIgggoimPF1mG7qXygZUFaY2bBggtKhmFyqFR37WJLEhg+G97Tk/DK2b
xxx2iYPjJTgKjkkkfw1DMJT17LC8IfyV2DfHzCdGZG7FVWnYOMVuxn6iC3k8A+Aqxk4e4HwTDlvZ
sKc7MrUj0dqKyioJM3P7X1QBNaHCNxDlu7m5sp2HB5uhmKO6IfrINN+ISc2gFjkRxxvIh2klPST+
BkSnFf/oLrbgzXc/8xDeCT7ZdnQr90vLebDSQ7mNgmeYtmfzzE/lGxlqYBzy+s5QxVVLDXiHeXe6
lb9fHhY+t6WjyjT+NTeyxxe5Gs3dSro8KJUCdMkjqQJP/ukA8sO0DSrN3ZdEKgYBioVTB6yAjDgn
4vIG/BH1BtwWkrj2MJ2nOnrx3J5D5Q9bDj3v+Kf2/ZKsi/IGnUZxnrwBpa69SVVvG6ppFZxpcqpP
dnHlCxGKMh7rcJyCNRJUq9Ygphfdy+VQCP5/Pu3u7PtgNMlTIaq2HIhdMps2EYXi4uIovfeOLTXF
eiLMO3VgeAXAnLOGnCkdA4V5N96ffxAwMaQdq8Sbytmn8WmChe5bfaoBofjDL+kT0ZOZx66hMYrl
f9ABDG/BB6M75yuX1Awfzz8FcCL4ZHW8kiFqxDq3sPBxbzoCbEyH71rADbs6jI5iKXlYosc0N6Le
rBR3pAdRFNsjbIOXPAw440ymuOiJ/+X+RMMr/xDt6brs9Ae1S9Zw72nIy90SdeHJAWOozLyoasQ1
G4uZaet6M+llEKfRkV07FMz5ew0//rsFIJEihhsSDl0fIbQfnYc+PX+NvkC8c8I21OgT8s5K4SMn
Dryz3SR2GJRY6s3Q+CKbzW49LkYBaatVECWpB08buZoAtrIhrZxA6SZCaH7Okbb6mQEidHgafwv9
TOer/su+tZRRxFrNtP+8bHn4Lbx7yDbyk083EuUnFzc6bhqUlu6/u8bwncJtF6QaeJZQ5oz9qfRs
5964Nc3qYeN3UCu+WuLARbntspznQdPEO05Gqjy9sHftUpDJudExNe5PjtwMc9IVs3clsfN8aUAx
knpxm78epXcxc7wMbBUxQO9eeH1UvpedD9V8avpJK2Nb6hVYZLLEKFsZUVAydOrSQqq0LhaMzRWA
xyc9PNfC1jKUGASeIPVYnsPD0a7BrMPr9pwvbZZFwMKZLnaksY31MF+Ev1aodZFGfF7ns2GD/SUe
qD5LbkS6ejOAPE1FmCJZHtl1M5+SpkHVPxOfk1lnsteBUj/UkBC7YirBIly3e/KbkMxnA5Ro0dVv
9/WVr5buzYW2aukuDrqX2W9E0UijRJmMAXcidxpaG+dGN0G63eFQzvpWIHW+nYh7PK6pbjNC4IxY
WJgm8NWOPjrwbappdhTyJHCfgC2G74FRJ/CqbuNAeVeSsKMg1HL9KAXKvQGtkg2gH8LL43cl8enD
2ydVyhcdsYaCW+CvCbdkfyaMR9Hk9FW/8WXkQCaOAey0/ozRt1vDVoiPueDTA3VFWIr62q5mmn0r
Sq5pqEXbJw591/2BkZy2OZeF7LDplz1Qn17/iy1wq8f7lLUNcmD15r7zxb00JKFrB0gTJijBc0ae
j/JZG8Hi4DDaNx32UO8sFMpKz8DW14FS7cKUHcC2Fozl2qzrAlAiTRAQUcB3bEpgOxkdt6zeT8mm
/tYYc3Hz5tW2gFGShW++k/VD9bqaxV+W6BnoqbEYNRgQkEB04zJJu/pX2G3H7HHb7WbQ1JGNXa5s
PHhVIPnlo4lpWWyH+NRdxOPsyFIW28MOpEuiMbpIuJql0CR7LONk3nS0taxKg9kUYWnFDgaQdXIE
HjJ78W1N+dcyBIj6vB9CHyOpvXKwMKTPbgOXlOT8gb8CB2cYtGYME/YGvUe+QPtW40bFNWQutMPi
PJF+aqjgDp30dGKH0ckEf72cMusoRtp5hToyxo03zRxrUpU5dCxGSwcqR6cdTrdYbF1VjKTn8p6r
+WHfWRUDLjGo74pxhHDxAnY3jcFDQVOLsm4taMcEVmdYmTHUAMxkvwt4y9vIMYpjsbb1J1ozo+aQ
TlCk9Hj3iOeYpwdj8229fSvmzkBiYlPUzdR61rasozW2ZSKe14AwA4vgszxuJJps5ZXFVg7Jq/Li
98MQNabCdBVr4jAoUauiW3Nttd0Iwj0xHSgtw8QSSlwm/BKOf9cdY9E42IEo658XNRwIChhl6PTw
idyY0iq5RKdPwtXhW1YBqWdavCbpG0griMOIxGrPLoWUFNimbR+z8cJaMWDBKwW9L6MJc89TUJwV
sMBK2Pr1mGd9Vk6ZJrvCDzR90Agp2UYMnswDXeRzRUiDk153Dh8rMcCIgvPrRT99Ixwf4W8aCPoR
ykKTZdo6ff9a5zmJ1PJ3A0yzfOafajuITHzeeHZKldmWbzNp03NmMpzLZbdZbs9mjAkaZOvWNA81
hvH8NefwsUb8gKyZ4xrhqb6RTpM2nkKXv2ldPyg9Gv5M2ZlKd06k/hwmODTEq6yD6GDQKspfS2pS
nlEzrlL+I5YW00YXtgx8xycNTj0x55d0wVnzRGIfM0rXLX7d+n8USTAwfh8qlglv/PGnuyR9Gwpj
bDmwRpADCvpEOf0O5vIXJ78dXIG2cYCpuCn0zazC4V3B7npm1N00vcAABhARFQnDy3A4xKXZx0ri
l+h780IbTnhMFgclB3tfyNbNpu59nu4g6YSNOTLN3DXN0rLqmFP1XeQXbHAvm1XfZPeNKAONnHrA
IGv3KZ8FFlBAX2gD2bY5lNEjskvYLiGIXYEXBsdhMBdvzLnSmx/21+fyAbtqYd3jBBP3QM+O1J3G
fupEJ3C+JWo5rnsfjLLqEr3BFnTMWO5fPGt8e+jF/Ps2rKXjrQh1djy+tHpb4hB4Gn7moZy+s6lr
bXnQaf7tocaBzD7ogOZIw46Vky3X3VbehFeaxvMubP9bnHEGGIXD99Aw8RGDbFcC9UkW2VQ0xUpp
aqec5g41qDpWjytbavsyAl3kwpxKLB0VVF1MYcoUxcRoes6+91VAMzZ5vx/KwRteJWSPBvZzyWQL
f1gBrEyvo+hx639TQ0dTlsjVzNCcjHXb+X/o1ms2BlljNKwaYFQVkdeI70Z+uCS1loKtwgsWpxLw
UShgWeI0Os4MJUbkiwQyHiGldo0se7SI95PlPLgU8Gl12G0By7vbv1kLY7pBndV5RZudYqqD6o+I
PJNdaQGvoKeuiDuy57Mqv+mQ+XaTTZHSiym125WY+MgaXfWJYQA0GX8GVp98AYXkhS5AvzvYV9Te
WRSXb8xaX0mF1izEYcMBxYKiXaIr+XAQcck0Dlrv6tv3JSeTTWD8tn5WEZlGv6rOEm7SRV76MEGu
T7l1oCewdYJQbOHASZ34bYBv40QZP7aGVKXijIEem4z2CX4Tf3ko1YHj+kXVk8Q3a9r5PxUDrZ3Z
cf0m02FGeQrlMGbADRKYNZC3mBmJN45JdAyYF5g9QZ8bF1kb7spbSz8r+RgT7f207x1fHgFSGygG
36jmqL9J2te0DzYjnf+PXg/gfOF7eRRJCdpadR6W2GwQvfRcLh+LPgufj9kDNDPCR3bxTrP662F/
KyoGiAUCzTC02l/kzMbmNeoHdokzdmg35biyZ+uzdpvxKdIkU3qxvML3m2yuQrHjuu7H2+riofcD
2fWFAy8qJYRv9tjreUn9BUIRVBXBQl5RzXT6QvUt3J0maeHakLRHU0ITg5BGSKK5dQkCkMrfIbw5
x97AlPGB41U/9byHEzEfkUBVFyb2aV+p0FiAyO/7i3/murNQgBhERGfsR0cJSf0GgtbcN9u9/Mk9
PGkAxb/Q8BJmxaaGcWaaDt3xJNqspeByLdD3vN7vwuZOMnJgnXfcPY9V+TLqUFBtn0MEzMSwWTYW
xb6OmIvcTL/p/A91tg+QpoksYRsYxoJJly2lqrK9GISHlABDwunOPOCF7JovQDCS8ECHh0T5Su46
h1eQoT+mcg++HjLAcsOXDQKqLvyZMbcB1fDYmQ0oYEo7o21C+w0NCCyH6A0vKVZE6uftBGZkOHRw
Os6YQNX2W5S0Cb4Kl9Ud6kLfIoO4/jwTf+x41SbVTO0hHB6xN/4GLgsVyICMhKDxd/x2NvDG48+t
ht09puSpIhhWK6lYZB4dZyaradYO1fFmz+5yyubg+W+uji1IULp6kY8RmABewdcA8bj8aMgdbu5x
wAYwDXexIThsVX9BB/DhYrZlylc53Mn3J7h4Iqd3d5KRwIcM0Elb2GmL+4Xxgkl9QQMccMinEg0T
VVLvrYjsThh15irD/1UJdZHkbu5P/iFqUJupK73YaJ+4GUtQkk56fpb9y7caaibeQ0DZ5tMK38VP
0Kb+zF+oBoSs5mUtmkDuURPU8Va44a8wWykrtpkAsp21+FcGXDeTHltJtM9aPlSmNkTcu+WBFBEx
leC09Uo4cp1tyXrRVSbrxCy2rgkQRQNS0tXENe3FYOW8nsYkELaiWDfqZx/Ytu2k2oC3icma3bll
x0w8aroMJs9DdJPS5HxXoSxrOjjNW7D93qTJ7qoypqWF8qeh3yPLyXlB5VHUSbsq3APfHFLeGNJG
0NwhUW5F7oPWD1wZjJp3hHudtLFKmV8PHO2mZ6sT7kCyz33efKUQwaNVfFfX37Glgy0iINmhiQMd
GQCJBvl0NYA3xTCu0OxpynDb91khdEK9WahrP58Jptla2UiVp3ll377ZNFrbU28+ZkQTO6IfO35s
s/omfWf3NqIh2l/My5VioD41t2BWBJshH3ciVxHxp1q/oNUvKQjPHq2SJaCi+dsjQw+Vxm5s0MFT
aFgyKkY5JUDsZAAdVj4wpLaqSzl8MixPOl5JKvj0asBTpSh9soM2eHJhd8Qg3O5iXi/FQW0z82qR
MzYn32Tl4t4VSJEQyyXFSa/bfppJdjXtoiMGcX5Tm2Esa1BJmHDb95bQ+CmteklyQ5AFfrxO7meq
PMVGA4S39wlzUPhOMLNqLkHBQx7cGpiggXpJEypdFwit7WUtMME5lVWjwRgcTa86vs554nQ6mgqY
HS0Ts5rqysfpkBrg4cwu8yl3kqrPs8I8eoOCJGvppzPZqxGx6IGu7r+vGHm/NV8t/kbZbB0LWcgd
xEWp6Zbs2vULjpjW4v9h8+qHob3ddPxTOZnOIoO4YOpSFj52CgHhg0mF0IogOsqCvWPZ7IpRQ3Ow
N3zMbv/Oh39yx8A1Q5veUITx4TO2NKhCY3aDMz0/BsHBv43IxOznSRFTJ+QXoxx5BfUiwksErEnj
unIddSDSc/eLd8LuE34+B3UZgm3HTEY3jqDIlBP/jkxvEP6WavGFEGTiMFgOlO2uc6Etw4M671Hq
eOg1GxUClQ7sFG3mjs1nr3uYbJZzgKNfLPbTeDvhje99T/VbDCHfQF9x+H4suRdXOaLiN0xO3PJh
AG259Urx8WPINN0rUQYnx7H1Upl6YU2ztwBb+MSUDUyop4WNYCQnZnLzcnQj15TtNZk31U9L7S5N
0XQArxZ/qeBEGsLy4oRSQjuDIKkMUX6EvjlfyPcGHqOtWGZU+D6whLypKY19N/bclp4ek1wWbEBi
ryOn6YfXaNfs2pJagR5Fb2HMHIYY1Vk91E9kNNX51yhJIYjTC0ykZHHvjdl/yZi4jpwEmKrXHelw
uqhUWVZPI4lRl2hy48EEnsFjFqjGZ/fIbYuQ8DONRLXh4RaIC1FNw/kHNxmBMlN79KjRuqmrqU8f
WkAvXj2CWWHxO32Rb4MkY64P6tTtvFHlvQk0rcHrNoldGDRmZmfsokQumuSlmLgGaJbMVZkD/oTJ
HvdBMUJisgvQzpfvnz2NvY7hbCPPJu/z92n6AinxekFyJl9LmPEHyK37W4bEGHp6A93xHj4aJlNp
My48b4wKK63caLMZ/SSME+CZC0D6Q0U9QRutjvzNqevDzLPT7h16An6r4JR96Ah0w5Mx0pK6rBhn
buQp5/MaW3gmHUL+zy47+jufYElkU1mKz7+3XDlUGYQSpPGYiOZrVK/23QmW6gNRnUEJ+ApzJzmO
6i6pdJ5AkCAXXee96DbRU2QllB0Agmcy746vwcCWJf4T7fYxCf7UmzEeYHTBXidgU9yPJKS5Swd2
cAEFMmJSFLlPtDgwwiwbI5ucFRyYNaR92idF3k9p4oNqBBIO4UKMf0Rh8T0GO08o2tjZUh8Z8K+p
ZSZzVLkCnMVdPI548q/TMbT4nc7S3dvCoeuleS6E+TZfW6KlZfRrtdFl+p5fD2xcDdRRIv7MQdvu
s91NsfSSh7cEkcSo84WawrPZtihNLW+CupkknrAp/kwMcz19G9znNAczj3eirmScRHPNyyRJxKY8
RWn6ekaFUz4ae1w6R2kA5SAOs7q1qqFdchJUr+oNnEVPHZNvjUAl5X9svG7IzlDi6sPgS2gxoYKv
itkEpcTliIOibLuzxbiH1jydpVh3H2tuYEkWeXRkDQWIB8I0q3Fn4fE/+cZmZPKocmK/CqMgRxp9
4064iL1rC8NSg+DsZFT4/R+qKUa05N98T9pHyZgiiMWJwb//1x1CgMVqlKVR6DxVBapkEuMe+HER
fsvwi642aAz7lkTacUYaLsUzDRCdhLAynFKsjrrNj+cg+qsVwFzcSm/D3o2jHAfNqc491+r0aVQt
40T6N01zf7GPFVOk6PFNRAFmj8tavAWHq9OsNS36nui/+SEa6Ryh+JVYT90q/dViLb6EHzrQL/rY
L5XQQ63MQvGtJ60oByO7+dyh53QFdhggVv0xiqKC75fVILKxOEUM7ZsJs+O+r5nvTEzJYHxoRJmO
vjrI8SuJ1f7eK1/wV4y0lDSJ1UgfCYsQRfatuYcMShZC1J47gWoSB2qY2ZH9eZVSDzi1iiVRi3+e
2QHhko17GqlJyKww3b0RV4I/iXgt5GUW/dOwuYODFbDeie4WWOfWeqdlsCEYtr7Zu9Sxj2Yu7Ds1
23KA7jizTf1PWRQbpkqtaphVjxFy4opXVWntBtdSKGpxsihkhdHNSlAd/brLVMq5quY0s3sXTHw0
PeHVVLZI/zXl6Bx4XmAnCMwef3/vcaMgiakSXsEOHwyQwcncN4iJTev9wQt3yeEALfkzaq9Qavp5
uktNk9BZcV6pJJX6vp9jqhSDkYlWqtRU0x2Lg+RPOK0iU5sbEatzgYor+cNWB7ToyfhA/n8WHSw8
/+nc/oaQuaAewRNqxUsP9S1UPwq0ZzuiPCWC7dqi/pLfbm4nw8W7UshBhHma8POKbsknO7ntL/Jj
glAzgG3FFwlIE/LWKCIF1iVGNaMEK+DaRqcvl92wPTrf8FlvI/X+XqKfjqfZkq8gx2TevzNY6IUY
OuDzftdD4quJRjKpRIh36iMtmXcAUe+lDF3GDKVNj7JZBa3gWisypKHbAGAlmap2vGQ4C3WcfzvR
zvoLykxXSjJZsYAtH7SNjMPUoAGc8xBJyiZgetnYUVlizSsJjbFdU6C+JvRIuQ5Z4OXHXHep6JvE
KZ/L1NgLWUTBJVe9mB4dCM3VausFXjgO5A3kntjMmRG6gt39j15wvHN8dOPrGP77DpuRZZ3Sfl0I
xx1sqgVJ5vKO8b4wZ/d+y4hTq1MZdZQPn2+xofr0KIDQpeBWfw2XR4GSTicHDf4Z2zo7b6ZiooAR
FkukIs1R3cvXcUQtyOgsFtfhcXmuJIWjhTosh1cOCpMCEORogV8LR47+7eyp7zkRj1PHtJvTyBsR
RqoKUyw4YpQtGgg2nBovSq7BnFbDWfLEERSC9pF1HzRQfxntLkQ3ojbhQ4WG7cGMRK/6BgKdCt+n
hPvslgz1PDJbrIu9hLv4JciH/pbwpY6bN3ufieBWuCFANlu1+dOixB+abJVqKP0HKSv7fc3bkVj6
wDeOwzVVenstxZMOKo+uaXdOQKcJxz+/PnIS0V7WCYAfcqSZfiRcPwbW1c9TNodb8ZLM6lvynIP2
OdzT+TDryQzuQkRBn2KWCZwqKjDDNe7NynYW/a1W2P+YQ9WvuUlsxETAKsJ/N0udhFNyCWz7Oi+I
PAJNdQVXh8bE8DWAkNvXkmjF+fTrQ1gpxJPlMjlM0nGn6XxTGN4YN0Madg8ggp+4ZxGzaHB7rFGl
yPCv4BwwpfadeGpN6tagtY8NFvy/3AOdTUTfvDtbTIw/Kp57VweuLNWy+l4tnHuYCuP3GAYAsRl9
TZirlCaTSvG6uw5OqJfE7J6HFr51sIG8mDFR0w7I5M8i7eKFHeJz0n+PpEij7eiSuC+47rTuJOU8
lweK/kcNtBu4V8LdDSPs9BKP/NpZXqemwczTPcsdij0ThHgI67yIZ1h+Lkv9qTNWB0u0aHulszYW
Ypg55syf2iBTudTA7MPVhx0epVR5NWulyvQ1G88ksKDgQVwMVmyfOpX6fPESK9slWpYoN52v4QgW
4Pw4MnoMS3JtPpmBRUnMZ5nnfszKMt+cplwKESuSsH5OzLYEtIf8D68M5lc0UtMFQE4q7XLaMo0C
V94jKqwJSD65EvCKqrJHqvY2u8/+EFOhLQJiJizfk+vPw/Lok4r28XXGRL7G0Shvmq7hG6UL/YTZ
iorWtzst3SbrcctkePeJv1nZzf1F44QN+3cRM2SV0nNMOjg8b41/Ew9iWbl5LcWyVqecFzfD59Nw
pLid/PCMjb6dUFlVYD3CJ86UOnEwniEi3lyVMJXyNEnMzmUVStsam96D4Q5f3r8u+Q1xQBbz90XM
O0YYCJ2KXmZuBM9eXEz4J3Lq5BaKouZP98mnfWYCGO53popq5AsUjVEO3nzuQsRdY/6tS2wqXKfW
WSOvua6kBfyfTtF6GYNPBW2wrldl+A6Qu46OFDBDdPOlRkTfU8Ylr0nasos8+TvXiC83AYyge+8c
qWUzLW/ZtKhIPQVbdqNLlO0iA+Qo/fLfrCauexXYABJ5IuBzvabe1e5ohdssNUGo49JqiuXIBPso
SL1RxWXnrx5mKKwTM51x2noVUbX2Msv/S7mJvvNcB8wG32eucNAK/NgPXp2+h1cbVaSrwN1TRTUe
w3T5zluCIPay3VnNOpHYnMrG2XXZ8UzT8NAt6KKbMeQOlbR9ss7ddeAK2ErcnW5h3mIo8EGMU8Vu
JhGs31+0ctE0Pb6Zh83kl1MSKWwHr/PErwm7oEF+Vvbrfuy0TS9AwZ+jMpslh8IPMHJr/bNdMV5U
FCblRw9VavWPLAt7mzYn3F+wMN0Y+8uiI6cJEcM4yVYL+d9lrIxqfPlY+nvf0iyDhbkM6KP9Xei5
HN8m9oRoAWjlB/dRZnYUCNjmNSGmd/WRte4Kyte933lfUrYA2NC3lsbkZP6tmosNSHFpv9hFZuKq
4IOHs6QMoSMvSf68x1WPQ1pAQtg257hLE0aOO1XwKcnaAFDpKHVuTQdMiGXu5JUpOyaeYS1P8k6s
D9pyteDFLaQ/i7jtdSy+22+bOrRJJYi2bvN827Kpki8/EzCDJrmWjCiQ
`protect end_protected
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/iis_ser.vhd | 3 | 4421 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:20:51 08/06/2012
-- Design Name:
-- Module Name: iis_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity iis_ser is
Port ( CLK_100MHZ : in STD_LOGIC; --gbuf clock
SCLK : in STD_LOGIC; --logic (not used as clk)
LRCLK : in STD_LOGIC; --logic (not used as clk)
SDATA : out STD_LOGIC;
EN : in STD_LOGIC;
LDATA : in STD_LOGIC_VECTOR (23 downto 0);
RDATA : in STD_LOGIC_VECTOR (23 downto 0));
end iis_ser;
architecture Behavioral of iis_ser is
--bit cntr counts to 25 (not 24) so that it can set sdata to zero after
--the 24th bit has been sent to the receiver
constant bit_cntr_max : std_logic_vector(4 downto 0) := "11001";--25
type IIS_STATE_TYPE is (RESET, WAIT_LEFT, WRITE_LEFT, WAIT_RIGHT, WRITE_RIGHT);
signal start_left : std_logic;
signal start_right : std_logic;
signal write_bit : std_logic;
signal sclk_d1 : std_logic := '0';
signal lrclk_d1 : std_logic := '0';
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal ldata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal rdata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal sdata_reg : std_logic := '0';
signal iis_state : IIS_STATE_TYPE := RESET;
begin
process(CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
sclk_d1 <= SCLK;
lrclk_d1 <= LRCLK;
end if;
end process;
--Detect falling edge on LRCLK
start_left <= (lrclk_d1 and not(LRCLK));
--Detect rising edge on LRCLK
start_right <= (not(lrclk_d1) and LRCLK);
--Detect falling edge on SCLK
write_bit <= (sclk_d1 and not(SCLK));
--Next state logic
next_iis_state_process : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
case iis_state is
when RESET =>
if (EN = '1') then
iis_state <= WAIT_LEFT;
end if;
when WAIT_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_left = '1') then
iis_state <= WRITE_LEFT;
end if;
when WRITE_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_RIGHT;
end if;
when WAIT_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_right = '1') then
iis_state <= WRITE_RIGHT;
end if;
when WRITE_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_LEFT;
end if;
when others=> --should never be reached
iis_state <= RESET;
end case;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = WRITE_RIGHT or iis_state = WRITE_LEFT) then
if (write_bit = '1') then
bit_cntr <= bit_cntr + 1;
end if;
else
bit_cntr <= (others => '0');
end if;
end if;
end process;
data_shift_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
ldata_reg <= (others => '0');
rdata_reg <= (others => '0');
elsif ((iis_state = WAIT_LEFT) and (start_left = '1')) then
ldata_reg <= LDATA;
rdata_reg <= RDATA;
else
if (iis_state = WRITE_LEFT and write_bit = '1') then
ldata_reg(23 downto 1) <= ldata_reg(22 downto 0);
ldata_reg(0) <= '0';
end if;
if (iis_state = WRITE_RIGHT and write_bit = '1') then
rdata_reg(23 downto 1) <= rdata_reg(22 downto 0);
rdata_reg(0) <= '0';
end if;
end if;
end if;
end process data_shift_proc;
sdata_update_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
sdata_reg <= '0';
elsif (iis_state = WRITE_LEFT and write_bit = '1') then
sdata_reg <= ldata_reg(23);
elsif (iis_state = WRITE_RIGHT and write_bit = '1') then
sdata_reg <= rdata_reg(23);
end if;
end if;
end process sdata_update_proc;
SDATA <= sdata_reg;
end Behavioral;
| mit |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/lfsr.vhd | 3 | 643 | library ieee;
use ieee.std_logic_1164.all;
entity lfsr is
generic(
init : in std_logic_vector(63 downto 0) := X"0000000000000001"
);
port(
clk : in std_logic;
rand : out std_logic_vector(31 downto 0)
);
end entity lfsr;
architecture rtl of lfsr is
signal shifter : std_logic_vector(63 downto 0) := init;
begin
process
begin
wait until rising_edge(clk);
if shifter(0) = '1' then
shifter <= ('0' & shifter(63 downto 1)) xor (X"d800000000000000");
else
shifter <= ('0' & shifter(63 downto 1));
end if;
rand <= shifter(63 downto 32) xor shifter(31 downto 0);
end process;
end rtl;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/sim/zqynq_lab_1_design_axi_bram_ctrl_0_0.vhd | 1 | 16949 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_11;
USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl;
ENTITY zqynq_lab_1_design_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zqynq_lab_1_design_axi_bram_ctrl_0_0;
ARCHITECTURE zqynq_lab_1_design_axi_bram_ctrl_0_0_arch OF zqynq_lab_1_design_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END zqynq_lab_1_design_axi_bram_ctrl_0_0_arch;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 7 | 103702 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
NYrdTNMqn5FUtu/sZs2oOOJayzIg3o9wiGWfLMpBkovCyYc18dvTyFvEfa2AsAyKBegsCwxTPfpr
ySmePDtCMg==
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IhX5yxY4OBlZwZvaazEwJV4OnsiHfjrpZB3IpZMSD/s+Cwa/5dsBg741Lc4SgogSf1Ex4XDNnl9H
CvHBKCh5u0meeT0RidfrxmPwlbQ7uSt4F/miAXI1iXAimcPUY6j/PWpMrnIYh+TFSrYCVluJslFk
EELXU0EkR4urlE0lhyY=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OhxUD2uVj63nMz1omDJXp6aXDFPgelWZAEeMErvRDsMVXlgr5bXJSbdsRVdva17fwqclCJZw5eSw
CUxRRnKZKM2Dbj0fTLwxrRryGdL4fM/JlLUVRfwdpKM+BoZh/2cnuxw3Nl/SGIcrK3fv7jfLYnI3
N4HRQoq1DEDeee6wLXWXBpzL1HhqiquhFegvXu5vSAq4FFT6VUYzSl6LruGwlyhJDssyzLo048wm
HIp48yoHP13wS1lv7C/LJU6svP5gyKwnOZgpCfXb3dD6TaSmzBZqHEVaYJYax/0NCsLdkLz/3xgK
dVI58t4ZY9aUmjPCeRTVRxSb2gnyJlebNGvVzQ==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Iw8nvj5r9yIp7681RDd6Kvbz+QmrcR1ZtzvAvrxSizk50GiN431QFuDe53tBJMs352oqxHPMP7mv
kcaG4Zjx+V6koCuWMqn8hJ92Fby+j4wrW5z5b751T2XdpiMdFDEBc4vYsU9Cd+twcx9+FFFYgySY
Fb9bzOkFxSR2lewwiNp3PORA/PNA83U+m7/GtSPb63eJ8U2XaNQO0OVWVAcBN1t7YNpKiBdgDYNN
7QIX8wncDf19/DmKVlxV6xahK3qR2v46uh+5BVoE3fhWUce41lHr581F2KzuNHDzGoKdCHFtyvWr
p1QXV5kSB3gR4sXdUx7v72jJI9xGevaxHHBOjA==
`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
TxI6eYScORM8Ldt8/qO07bswJ+DInBtDUnS9WNCkNA7lw0D28K7SnFMxU77STpHKS/u/0KwRPU+Q
IEYdpa2XQ2G6DLmUqflg/EIkoQ12wc40GG84u2N2mDyPH+tmLG+V7A9qsQ7PzOZ6zvyxkVABkulo
VDg5WByMI+4f8mG0KEU6EtqlMQMK7IvJP2T13qTHTDx8T3SKpDGEpLme4HosRbPMwyAN/0X/sYDy
x/+KJsJ1p9D7wLDiGsidsce3QkS+yMrc/v/55jzY+U/z20sm/FEdbI29NYpzH2njqmVTlh+epO3W
fYeX1tuUNemxe0z06LZJqbWWkrcw2QfN6fiVsA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A+AHQdSz9QxKV8sVHnqNgxsRx0C8MiDPavCE9qEyX7qFyY2w3wWvISCp0X/jBb064sUOzWHaasZf
YyyvUTtUpbzv4pQ4uk98ILiofvL/O0QPRLRv3g6+0lhf78oLBk+/pq6tmfp575mbN+zNEiETWH2B
gS6WB2pI0OLYI8FKt4A=
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fIsSotJhFgxqi/ldUzVJv2ql4Ntar0Cb+w8uJ3HrrKuN1axuptl6+Kh4yFFqAvtyyqAffkweHHxQ
HiEH4bBpDUVx4OM+9Xl/Co8J+3V/UdWsXA8TNXjFXwtCj9i/9NZUDfwdu2RsTUqe4P/RuTCD8Lpg
/BcJsHrHUCRz/Pr+AXokXJe9hUGNIuEYt4Mjr33Rth0l992Cap1KsJKW1r3O23gHt8TpurMSgbV0
bjUoAfIH9B1FfGfqrDR6+ot1rvbJL35Dmbaiyrfzx7HU43XLgrj6CgqD9ELpgRsH2xuMttAUeVyT
AiocoCWyRm5XU764RVvxu4r4OEF137RmYqXoBg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224)
`protect data_block
RH4rw+RAj/ZuucjnVhQEVW1/ZrArE7LyYB1eRRPA5c0m0FXy6tSnWfN+Dh3298rnJCibfuWzLDz6
TImh371qWHEbTp2sgxHuDcM6JM6vukMrJLd0o+mXUXnX/pzWR5f6zMTZajqdwAt3l8Zfyvo7shS7
0TWYg57rpfGqdyeFaOlTWlTjzGt5+Td2VtPSQ9s85rYOVFcKEG7wpXh50WycEAH3LQNJxQMfP9F9
8EvGxjmsNaIPwry/voYXicbruux2VepS936yxviGxiQast0DTFrJWSJ21hbvA1Oa7PVj9nytFNGs
h+g914VvQ2Vob8LFvrC4d4iQiEBuL95QgsEp8kYm7pHq8NOdkq9m4vMd4nn9kDQ3Kk1X4EPSKbdy
aPC92MsZOTJo/6QkPdCmFmT0nS2GBa49vKFG16nOpwAgIphQff31QSJGMJGyvOQgbUUQZld0MXd3
VV5gGx4j+pw1TGgJNVfPbVBeisYVobdx712i45mChBHqv5tDz1+EUvYHMAgrpOPBG9rmcZlkXnfK
gI5DAT+JSsbHyHvSYvQCJtdf5yIbirm9cmgv1aqoLN3yZcribeXwXrxHply/qzoSV2I+bRdLAwjf
79ksnfybXnh59Oj3ILUww/LRdLeU6IeXA4qiTuUySEYBhT3aBas476hGeQa9LtlQyDnuSvIzCmzm
m4nzouzEcOssRgKPXXEcL3LCIB3dHmnay6RnkS2uBYXfgU+L0u5q0EX7sMlYXZU7XaIdMVtao6NI
vqNVknUnnxqx6gOHNTxoxl9EAyY51Jj89Gscbo3J6t9Pl1Bw2dWewgw3o6B/8SbHtRpPi1Y1LqVl
GtRxEGuckOH9nNseZc1TXuiPrBi8lTY7rPq5iVLrVtCPEkd4/mwCuTn2le0lp4tfy3NT8RMT3Jlu
mY8CAinl8azuB1x/E6jEvaknQwhKZAsgWsDkppRcxzaK31eDc5H81SsG7jDsFE9tzWp28u9w8PHx
jOBaDDxIB5DWj3gSYRCA6I4Omw0NPMcZBt9oOjz1TqXzgZaFWjqPWeLdfDX9OHXdPNdlazpt7jHe
cxVJCf3GYtNA6SRmwISClTUVeT9hDMe+3SHbsrcJJXFMf+OQfCpUEM3crBLFQS1S2+ChtdfeCat2
TBfWuxxLXMnuUJvl9g4c4BJFY6jUir8vd/OnVeWAyCGByEiBVnPEDgWy7XG7RBCStf3f+sZ2tOa1
B6y2KdL2kvKKHWioC41uZL84dIhDC7iaxda29bKor6MNmfHr2pG6LVTZU7fVuJr3vxWqgK3kJttJ
nVqjgu6g6lfELggs5rpdfJTMpugL5eagULnOS7brC+ko/nQR2XejiaFTAUvVkWg/Q0qERBJ0wpEu
FmXuuXIuEElWXp8tURJB96180d2+1ltbfrGjfvlQauEBzA2tDQ1IppB72xiyW1a9RSvFHmP4wUAT
XSoku13OUeVFnmCr1iezjzZrLMZmAKHTf94NyHDTdeTMG9TwcHHMvID/y+n17FFVlWR3Yu8IQ9xr
o4s+VdxzHzHAx+kqDy/VRam6o6IhRE21q/sZtExuEVivw2a6B++9t/8LoEreScQSEBxUQPLhh57O
5awpknNlYqeY++Rca9VkJzPz2JM/ASohcBVLMOP9lRbGIJireoKexQoWdm7FbK0RfQari2G2//O5
PpgJAyQ30VoyISIuAlPpOalPfbUUeqZTtSq/vS6zPb8tZHrNHMYKXwHPhCXPvYOvECQjdciSbAxT
YftrfnUg38EUEveOCjfAsaQDNiqpnYb7cHfFcwI+vrTOTQILu3JX4wEtqScVjhSoUq7zM13Nr7eh
x0O45bdcS23jeraXEHRjlkgP/wTLiTYawKxoaB2i4Qd8wt0lX1ouDiVCPhwMBxtTcmk4N4IFF3mD
EidZ/mYMZ7MTiA9BV/e5GqAzZPbLy0pPWFCZ9BTqbKnmqiNpyj/7kUOqNkk77TDfSDPIKNcgflmU
eNmndMbTI4wKckQsMwIbFk3DvTO6QJb7OlkP7VQxZdPw0MbUK0xD4O7aoMv1fueF7+fRYCxn2ybA
h/Crw+TbTDQkixMhK0dQohgkwPOEtYjCYzxpOE9aR080u0y1y+Il/Cwd9H8ctbaMThWderIYJcaW
TgUDcC/dwgm972pzVX5f92euQO6jv7UPSvXmia+OhvGZiLJgd0WenrVd3dmd0uTr2GtYtqUlhgFS
9YxqnKe6wEu+Ts7pBx8ThMumnDtmaJwUDE9U7KsIbc1yOdjJFGI+djsoCXF8uBnUcqbfZNKCw2ev
/9c/ZV3nK1WEgIyVIDn3RqVF53QZ5Iutu1XUtOzBmAvnE4XiAoPpy5m+3tyClaGfwpZRnIJdJhqg
oqSt44umjp+yr3UgyFqRb3s0Opv/Mt4JIADoSPO+hOci0wlZUJdy/0t1vXsD5CLbivqden1yk4la
W8bLGTJoUn+C/2tm8ow62//lVktH9oPHbzC0JN92QoV0KrLdYciiTfskC+8WuS3tNVY9bMHt5wC6
6UPb0B36em7XyShxU7RM8vp68VKfM4dvgpHqNLEBWBONMcrYs/DgA5JrCqIYW12hICWi4qZHaf2X
vMsnSyTyjO8/4f56xzo1/cLHTkGrIopdTimiFhAojhtHn+iobl/ID2Q089InJDUnHvcT27EPW53l
JdXMRejtfrQ0O0ONRLxtrm0esKGIm8KPVdGDBfG6aWrlIuWWHstSjJgf0yBe5nvf2tknyZCWz2WI
84YeCd7TZJdDSuZzvRTh4gi3fdZwnsKxlHI+8Qn3RTInI6TrXCHOoufi+IOn6lPQ4r2W8UKQjAbD
MFaeZTGsNxLGhaQm1AKKNDm6ebtMx8D3j7BWVtn4fk1SMn4+C7+dXdYHbbeJOd7q6TDxKpXXcH3r
NxetviP6+k1Lj2+H87eE5oNM0bByxtLWaS9oapJcBPToConYhVBa63GYqJEsB6eQOMlOrftLbCcW
dWQg8ta06G0HswKBKxpp6Rq+Umq28G0qQsxuaoiCE9Kee9m6JBoKCxfa2NhKbZkQStCzeeJ6EaJ1
DWmVXUpkYZACmfY7ulf9JkPhVTOlTt6DIZPbpitjgcVlrAzl5FmsOzxgTXuOBvdpJZeckWlHLjb9
5hFfTfriUIf/Pt8HhL7eTL8DzoOuOMaKZcfu0DQ/If8oNUzuoi1N2RSjuSo0AWJQFLeyq2w9aRQZ
U6QJAtXlSBj2kojTjY9NUjTgLbTh/nZ+yABF5niX5/EUt+s6aiSYVyRwNkiXXu2wJLENEIK72zbk
J3OXghJQ8sBJhPZoWlM/hWMuV6Q9P7gDT2PXY0cU+crqu8jRzLTKQ/OCPVyFOcQR23LvymWvO81c
1U3QcSeR2Fr4u7nbYzH5f0InapfrDI9zbHagB5Rv9lOdC9gpa/z65oytm4lOzR0uu90p6p6Z29Ry
sCuF1TJDmcW7HpgUJEXgP7X48ThjV7nzd2ICvAof6Q2SJXnEtkeFpGKDwHVEeEn5JZ1dEWCVwS2/
tE/Ve7c/9Xa47YHLqjIrBjp83SnCX80E2/n+kBvpZbYVnr5fOO9kL41Tm9egsdMm7WvTqh+ogYln
4dwwrC0kwFp/wUcI1bOQqryoV90UDS7SkzYsIjtET8wWrJP4E+S4lA6bgcWiSbQuHbvI6sXZ2+D6
mugmEQaA7f4uh0VFYDrLqeVWyt/mI11cPEhU9eA4EtOtJI0Zb1tgDSyknbamKwZSfoj7INS6NVlz
zDuT86de98Eo2xe6DiJbt+q00nJWu4rpBvmbxwMzrtKbGMPaE4uvnrjGiuJIcN2rfQ7G1q9I9KqV
JuCaYSLthyHoyG3/gFdmharZDvE57Cklfa73MPSgrjabedso5Dyn8+bIVYWZ7mwlWQ4Gg8XbZCPA
QMEZgQNSds297er6tdXJSiyK4kiCYKW49zYWyjMfTND9kdJBiozl2IKgPjF0MrVVdGQdBaSrNahD
he1E9ji80qL4uONL0nHAD9ou94v3fNVBXP+xSMY8kWFrRa94mWlIFxkICJbQ3e/SwKqxwbOnN9Fz
fOV/pu2QBHc3pX3p72drOkVyYK0fmdWvxgy4fJy0a2oqz4zFZ3flH6BXVklmoddHclAWBnjuvUhg
bPkepuksCvpIELoLAK/dwOEeUyWaAIatCI22TO5ZgihOJP579228fvuyhIttr/3bN9wwpUsnNO99
nb3kn9qaXxjtMIx3CDEEUHaqcDWxA5eiRQ0yIqrUZyIBzlFUz/1eThfNI7CSlzpwKYf4web9strk
E5niBl1ungu5Gr5KWshpCoXVh9E67GRFXD70zRP1JJYoQxWRYN9nAY6QwXShnd4L/jpd/4T9M+/M
V/aU/v8H5PV/ZD19U4p8yg8cJJOeUOTVNNnw6JKqH6qEPfeHHuJ4T0PSOdsTbwxwJgdUYB35lK2i
HCSqWH4/L3LY1CDsfaH3lGnzPHZpQdG6HjXTH4uYfnKncwR+RzRGBar7woxoy3q6dShNULnMsIGN
dGmPx2LSEtBv3ssVZZuzaOZUnQrj5f/reIE8NYPacA+55z1YB3YSrjHn5alC4t3j1tf0/AJFHQmQ
x/Ekq41/G9JD01jd10vCOunPMBnd7Xmgcaw3vIhiP+RBsiTOnt5v/55ExP7zY+MO5Qp+AA3ETsFw
7B1bkgi+UNH0q/VdTt+zpkEHMiWbM25zphYUtuOCZktuR9vUahGBKnxWIERoOg7SVRYc4KqnKG+B
WNwMHrMbplxpra/ePh3efsWAvUCZUe5+u+n99nMCdrMuoDx+PW4AaAMYM2jhU6I0Q2bipyBxAo9j
d14L9ElG8dzbMc35NLabW3UkYv0Zr2s4DwKebDb4k2FMyBa0GRQ16KVyzEFglflKHLUYjar/zcmu
oNorGsPK92ngeZWTT240DcAKbMC102LflMQ9rM+u5JXW/azRDy2fBjSvHIUSS6YQVzQHp8Pa4oFt
eyEhakJgVqC5GzotVgVL7XQamKZiJ6wr8vJHWHMtJ1SKxxotAGLC9PXk772/xmyKF97uxlhN7TSe
5TjCtCM70JUDIloPKHBpA6wbIwcnfZs5p6Ty9GPKid3ODEmxGDgzk8BZf0ABaRnBbusZMF8AUMuS
UfvwjHIE8/uroJCqzKUbHzo8watfXIW7FYKfPC2fBz/HEwmwynG6hEJsfuU6BzEoOfE2MTVjyKuh
BVMWssUlxGKckWbcOoQrRpjntB6Vg+4kTMgs7j8KVuUP+4xSX2dv+sgnM2Dj9mXZihTIkeZlbzz1
KmhrGwW1dtuuCoZf577luQZctuw6tT7B3iZaYznDcJUuSMNHSCwOveN2ET/NYbnlJVUmARgY/xPg
BoBM/2imaYvsu2RpdPeoIVCPY1Fi/6ElkcrD1QEvh0pCepUSE5XH3VramdNe75LgvjHVYnIUQMwz
TbdNgzbAe3qUFS76Ic/WDKFWXVDqe1eSqWVgMQoWrOk0nwE8JKqxokkRYRm5BmuPsdPASf3A79CO
uOe6BYafrc3G1WvHSlhpiPfOXHEXvJKhU0n2OGZd/aUs2hhqBNtthX/ewNddQ5FbsRNCdNn6DxPt
1oSJJB7LCNvbPccHthcELVAjqAorl9RrOvDgkPRYvEBvzK78qg/aAAi/WntLTxvRybgNoITUf/vW
apWO0j1wbhFdSA5BF5Se+DeMhPZLYmGB8P1O8teoti5M00V8B6tb6hqJvh/PJRvMNu0Xa3fknPD7
LkhGZqqZLc7W3iZYHeIsJHtt2JJ9UhZN4bIcGH/xevFefPnodGvSFwg0NPlyrQDvLwMNOZhPb4ly
lm1m+9rl8udqNT88nRabO8htHScUlIEparYuH6vZCFDQ8nJkcwq9IUl5StNOrIvR95I2XFGycEsq
6AIp1HAmDKfOxDWDf2wJvNhEBNirZkSnmahzxX4q2o53Cy9imOEFgElHPNGc9Cj6chDifUfisp3+
EfezmvO2+UfOPIxeVuj+LrrR7J3yoiN0+HYAMNDpopACk+YWuee2kCmekrT4NsJSB9ABSVvqV4Nt
xZYSK5AxI9JoDqGUJ9niVhq/ZOW+pr6rN5cq9IcdA9Ah2P2a9hQhlKiOB7Qe5Vo9yt6WaKD55lMQ
W+PL9arif3XTX9WbYLQ7td6zFcXOxS3jS2S3DnJvM7lvBj4wg63agMNYYveSm3oCfGHeGVJjA+Se
U/dfMtjql3KaNITLXJOTuFJ3aeNDw26Mm2mwJeUg275VktHGy6dSQpmyB0MMoRPEXbCrA55b4pdW
iSqOFN4H/Jb/ynqMm1C02QD6s0wTuBJut47dG+zmcbveNHSG6oDLi/ayt4V0v1X2I7mGwSkgHVHx
oFKfsWPj5itrvqWomGbkyppgcLeuRrWoEeNSZtrqR533Bm23TtZ2ft2LgBQVr+3ev1U3LwfBQ9wj
2R/TMRcVZmunFqLf9nWefb+LJKue1wH/VEVcA8MUcWTltzoCoOyidSu7qg9WhYLUXU6VOw1+NUSZ
A9l92NHQuwAEseabrw6sQN5PUCNlqYvswWEZXHrXY89AXa8Yhn5cwWGX8jAtQw7bFXii6Qs7RqYO
h7t21758pAF1FGtokpPYhAkRgbmNoLKKi/1TZTB+VffCU6ViGKe70yBdzJk3dmFgCeoIkb0JmBwq
R3u3Zi05N/E4yyAG1zLVus5JL4qh7CM5tR+m0mX5aB6Qam2zc4yKH3Bn7HyN9YcJhpImQPC4UkTj
eiitwlP0nk1tKENyTM3XyAEGRUdfrazypW849+HaSsaSLVCtdYO6lsQoxbdUi60Na1H/wuLThNiH
QR9P2WLi48rxisdNgnNVn2ysZ8no08Bx3ALmsStTm5c1vzbLCSLRIniutF+PcpDqeziQvqVFzDyK
ngmyVA81X8idnsMRM35ET6hR2b8cGCFZL5zbM385zc+8Z4p4jeje0lCCbm2ccvYHRqyLUJ3NVg6a
lmMC1gDBFFGkKO12y/LPhWbk1YTjGPxO8UiwMxIXp23FzpZ0sN1JUlF/RIYu8lvTNWvKycHCyEo3
XdudPQow8gsnCY0Hx58LeI1gZreY9kUWH+rkWfIbVmZtrYt6F7arwLNjL3LpAvEee50NnK8JF7rz
66jvg8MGn4Yf++m9CsMbmn+SQ4Xp3IjOYZVomeEwZ/HWBsnHVb5cSpwa9QFI9TGTkOO6djElbHpQ
YinKkQoEeZM23VvPRMwiuwrCc/RIPKO+izmeM3tNUWMlp4sgAtW8opnqopHKPKN7GGZOPm8kPHPW
D/YSBciBDOahldgpNbPyjqMNtj2QieXTeuKrdkm0AbCbDDz3UT9r8RXVRZlMu2sXy0Ukn4Xii9iU
+Y4JuCJ82aJZuWG61ih2IAVnBqrdm6yRSuj2FgY/S7dJPZZEacwqnzhvgcaBHo2N2B/w9eCvRBOI
yc6un2cTP5lv2tsXbK9NKFkxj1Nh7YIp4c8hmg/93coStNQu76DyhVUpamtnV9L9fjHwlW8Qhcw9
8ChCjiUaxGzDuVxLB70eM/QD3nNkT9ho+QrHUugYQbKpYj1mNHtSxizZV6lA2tN2rESMXOoET6lZ
xHX8JwpzZ4DCwuYWO4iHTA9W7ipICyuojR165o/l7jwzJluzf3hbewolPfnV4wgiy19iJNR7bwFr
qj4t4T2JYMdBs42WsUQR6ejLF0li3hFjXkLF5yNpL6aGy8xTTDkkqBeQeT9/B3WdYMyWag7Y8pBB
FshlzkAn/Wy5N3v7W7SNunk9OuPtraYqFboWKDCqV5RZlO2MDjsSpg5t8eVHlNXJoAVzHJm9r205
rXRt//7vg5UwkRMNVOnn0RPJBFNmU372+dFBdHgs6bubCWZ1btFk81jdvXAa71VPiXJh0hVEMsd8
mKvzBjpoRljoIFDB14GuLSlmZpH/3vMyWGsiNTLxe9mqy/QzBmBa2trUCrdXz+zLzRgYJa5/e6SP
1+BgpkdyKzTaxemLevoGD8APPUXqwAqN0bvbDpkx53dZLlNzk3bHACFbThPmk8916gLwAUgn098K
A5aTsgSig8RIT8RO3IiC9UmH2lJIcvgyvCXefWz/mifJER+3/6p9gkHkzZFzSlnQBtkpl3UzPRDt
sgu2ONCsKIi92gN7SkblTxWKXDS7agOn/WGwgMfJyGCgqFb+I/y/svv8MsXUNPwRwcbz85dE4fua
aM0YihN5kkSOaF0Tc2z+sGQXEWX2jdPaXtGntk4twV946YEnC/2FgeMtugx9C1HZNTcFHCXujfie
kYE8qeKJhhrTFlaF6+2PIOg5QHBdLpItzFiTuoCwmpOt22QUq9fYKAZ9p7B3ZZBiyi/oP4A3+un6
tiWd+/u42xo1mnWEkguf7NIRAsIZvfLyj42PXn5VWkEgwE1+hkzjeUdfezuCKkBtU0v5AyWZO6pZ
CPOV8iHd9PqgT+GfrX7bsxDVfS98xM7TI+NvzS+zhpN8kpomtWxdZh1WlUTwMOHJBOb1v8wyRVN2
fCDiOsT31MaUpcd/6GSUsVeXnmhrIlN9wzar4dGSG+tVqrisuuOt92Gkrnyca3iXhmM4+eg0b7tR
Om5/VIgt913lrPy8uo6w5iOVnGKgasZvMj9bsIjwELGklt42yNZlKCHHvkj+tlE7pCG/D6eSwreT
e3az1iowJ3tkLMhAe6f/8dZB3iTij1IBaeM9Vk5gT1+EtdE7o4uwVbMXr2C4HML/0ZaD2aU1nPn7
zQzxjbiyCm6UcEkUuWI4IX2/vTxPlRpkUCnw4p0Zdxhdk40WgMntBE3s6N73dpOQP97gm6tnqw/v
3Zf9rQiiMyWN0rAqeehpujTDXb2iIZkixBOCv+r6zDWL9QYW7cCkgJBuYVomio5U1mZFtVdpslQb
a2Qvjr3snp0V22vJ4SXDMygwEcto4foH/qsBwzoX4Uv+odvpRUQHRW7i1X4ml81Al1Cb6/IG7jiH
2BrSBZ18zOHdw4iydqDvQyb2hHuNUrbsUs7u3n932AkaGeU4+MQZWkw0ZayRuqp0W5Df5aijOhMi
v01xgutyE2XBNaSlhrlixZsg1I6bBbCU1MXp842xmMoZViwWnoy4IwEqJYffQj5zeNDMbCHDqxZb
xowtc8yN26jyPkUtrUjHl6b4roYGu7QvU1KTA3qwjw0TpNuQIsgNvr5AE2aTyb3UFBGIRF/8Sxrb
E1Cq1jtnz6OhuvUTiwV5O0KoPCYjpKsljjIBK+//zPwLeOIPV8tl5KNUZ0zFKFLy+J0GLwUcdgyD
myMd5AvdnK4L5IY5dBWnvX7NDBfXuNy3Q5bm9d9BTtHSofI6KwdWEX+fuICv1kxqGvChcx2qEz/c
ZgXtKxnIsbgTctbQHpveVUaXArfDoY/92SREu0RVTdmLHGflwcCUtix64r9P4QPiv03DOLnmfw68
ekGpy0PZhdQj4TmjpaBnoRBn1SKxWdc2G3u3kzbowd86Q7+EuWMn6Uq/guuhYc8PP150fY7nLpAF
3S6kZOOT13YPhXcvtLT4oRsCXQuipCOAshzh3/kLPNjx/8jVe84HEPp2YhZlVSndrR/P4kGhEs5+
eaLEapfSrBySkE9+fADj9RL0Zfjo4vQfOAK1ghT30OybvjGypuhBeSeUEFrjphq31OSumXvDO5j2
S46bHUblyW4YUq9xKJlJXhieujOkb6l3YtzCAf4QA7IM+H2f79IcC74/F1NZn3Iz48e+WTteI/xa
Z13lDHl8a/mI5RvlOechniQ6vSFrdAHuRWi0aOx2CqGAgcnSZf8LkRzPh8YqOw9b3PJokzeugGOh
eiUUJxD7IKnWbo0bWwlfFHwpynM3FIbZRxoi/cOA/j3dCUWsnvd/5IyzlycLnEW+ZT/OO2XIklTq
goID75ZRFRFIq2Lfy8xfPwUhxhyuubnYVjVLSAwSRojZIWNhsOVh8hFwnwWG2RS+x0S0DI7+RgGu
kLEOZyvHp6UKIScaeHcXaCExPBNGnZW0mC1mD6nIku7Il08FelXV7FvaMWQMJjEo7HKm1ZaKDgDn
+QXChHj/0QubhLwmU/JjgVHKGDqonhW1UYmR2WP3MY72iaFcKCatt+EFHWvBQESota32hEGWa64L
0J5zs0lb2kHQEEj+H4JDAJEFUYQUo/noevKcIhCSlYV0AdKukBAo7yVBFNXhdaHlTFX6Ah14CC4O
YbdzLNHUB1GrHqiqQw8GSMlld2sEFYjqSmKB6czZ19acFARyuaKN+I75g+RUfhhetsmsauXKNQ+I
6T7QncMMfh+i6Kr8zyWQJXGfazp2j/ZjIwuWzOwQbrDVVzGcZJsScihfovxJUmeZFTWGqF30nZJ7
rIAVqlAa3OasYmMxVPatxqdJmwjhSsjslW/lYPbZsSew93mCRsVaPKyY3FPxAmcH2upDyJfW7LhG
wpM7nC5gQ9HwxZrz1kjQiQLeEuf4Ay7f3Pok/0cPkzog989cVO/MgMs5l8x/6ESfd6rocjj6COhE
L2hv7jpnsxMBWinOl68tYPKyFa51pvgTo835w07Ak0F04IwGddQ6WQstrHwq/hC+GIZ86zikE2ap
aHETJVLFb+5w84QsnAOrZPAwpZsabfMMM2yL0/OVA5QN4aIIUs2Spz9a+7ZUyPoXu+cAau767CZE
rulaeaP8DIap6jA3CtseCGsPzVulj6IkevdvGwa086uVKXyvUIsW+k3hQid2hIoOfUxmSMG3MDFE
uPVOQ4uF8FEXTFfsf+PY1yD8/g13L0mDDictEQmJH/VDFqZUkEi5sUaLt0sYxwOFxd8XEgPc89ze
Q/bHjlIjpRlh8rkK+TxFOJgVRgigdnzB0+v+FgP2AeNv1Qj99zjzvv61m+AOCMAj7iwSUPqZtFWg
RphX54a6FFu+j8KtTSIjCOczS2rf8TzfDqd3bD11Q0sDoTVGBhRrRY+87UT7xBuxdDWVUUwbpTQD
Y7+u+2BVmsyUWuf9ySHaWp62ejrAt+RY9ekLlWikbs+NIPfwSp2x2ZhypFnhVwyEeX8Hvu0neQrG
hCcS3HcPm2XHm/OqQ5M0BSzOAVJ9LaQRx5MhMrL36/djAVqaVsgruN4vGu1KV0ltCoTv8KPkEM+w
1ZwjW7/jPy6q29GK1msHXAa1kl92UkH/81e1ytDZDi7Hf7k8v9SJokYyEI0C7KdTrpG2ikO4yaYF
Syou4NDu2nFI3XPpMCpU7CHlf8ch7SKYpjMTnzieKQbvCu5Lu2LZhy3qgl3utQajsO9wxJ5YYPPY
a7imD78OuNj/PK0Ug4C3aY9U5JrogoKdOuRILC5rrSbzfXXnkXzpTpMBb3wIudB+V5I0ZVXVpuAb
HPaI0FqJoffl98x4u2yxVGxvaPIiffsk8xDJTXas26LVfOgRQ5FD5w7ep0Z8+nv+FGsrn6jZCqsK
DtPbUhA9dBoVKhuJGJ7AozZKwl9wdx+/kfBgQG9JXstQFAc2zRfK+RXV1YHwMj5WR/f0N35H71V2
ZX4pcfnJp0YZMnbIKIkHvcdvfvSmCy/txNsTL8pVXH+nJD9izy2fvFaSsFrsvJye3gCwadYua4n+
mLmgEvjuHmQ3gAdyuRLXpyvBUdhJeqeCSuwHNvRqEJ9JAmByH0JvsnBqnthogWeB0hqLUMR1K42B
mWiVX2t44jH4dFjvr7pHKu5KZetzcpTPgIfgFEdfQHs/KQUjcDay9mtuk1/RkkUQj0vJJp7XoH9a
avSpZgYTuOe/X/okN1S2I54osprm6bXy74yzXpUEcI52N3P7WIblNPF4iSZYQQ5EVhh2THtZSQwD
GK6YWPXTz7Wf0WS2NnZb3SS1JqVDgqR93mabvnsNSwFJ9mfl89YJaauAS0kgEx7m5cLBQDo+fVM1
fT092tfYij36T33KXdc4iAmV/osMril3C2XFL561Fi2rLLFPYI/C4XVEDumcUTK8sRw28cCJflwL
R65Zje6Ny10kVpNngOOxEwoiFmdHucTJRuxTPXzHXpu/lWNMiwKAu6sM5RLx7pY+rJ6iqzaoMVod
613N0E0OyaLjMz3QWyvEH1YwTEa8oaiJEovTugAraNBxnV2NBY2wIUDS4/KYN+VRDjrGe6pAfXn1
y+SuZw0wcYPocBUq9wHmAhZKzeDbjaPCNeyHChB17oSxV7QXO8w564iDSh+JKqZ/9axe4hZ6+ZYZ
SG3TluZpQp0scwsmXq4XGmwxjURJmDXZxBdvRoiTZDIVopm7PsUWDsE53Ls66nfn6b/IYxMnSzyB
QBrZV76ePgV3+poLksaYmqg5cDNduhnHPjmpbI+znhvWgWFvrzD4wWFNm//Q4LDFqIra1QqTMuAm
edPtU+OkkuW8PIxaz1Oj76SkN9HbckUmkqUJ4OVVxlM/MNIrDuckFI8110AUH0igQhcFdGISa4Up
2Pj5DqzHcPnXj8VT/PzvYH+qheRS9WpD28AHBmhxJF+6gKyUijCHFdQo+2sTgYuG3kNw8BaY3N0s
bL6LlIHpaBZWc0j4MeEHdv7B3+KGtY0n4xZBJHEBfFvqtyLIfQyMfgYGYQ6Ny2hB85M3tww7z5WE
E+5A42im9oibOegEQ9pVsek+qVns+wuEBNxEAjjqfUfuzWTYa6RQqAbY/ogL3lubGDhEMm3LNVrQ
3dVNRo/1v6/pfYna0uW7RpUOht2OplmRzT9s7vlXOcfD9TdS/ywfhg5zklbM2BUkokUlwH0C1pZF
c8Ta2MCuPpi48pc0c8hym41sQb++zoxmQcMKdPUhbAdrEJg5Z+ONIejY244POUpzmgq8J0728Nxi
h41QLuLjOs8Y3ctnLhq7ULGeOKxogUuBwQG3dzTY/0Xrae1NLU8mqRUxCtODhWbMdbUS45IB2+Vx
09mR8UZSU8NV19KkLSx6lI5AhXaTXyj6B55nzCdngWjK95XJ6iVijjOItmpTuhAFp2VZSV8vC6SH
/4ME4IboT5JqVP5QRXwQsz31qnaDjL+5E8n+HsF+L/wl9pF9AB4cslPaCiNDhJuFOu4dGrBzoneu
WQoj3mry/ow3/UALIaEdk9KpvDNmWF0uN0u/8AYDfc8/V+yj2Qy19cnIq9KrJV+bdMFpNgwwfPN/
feilXMHbZ9rfb55Zemii+n+MMq9rdSWRnyAQBv/XOrHUQq+jtSqeRclR5a4eZhJBS0I0GzZvCBD3
Vroa6IXmFpWszYhSQSlI/a5EFA62/OSVXlOWrk7Vm0np0EHe1ollwQIa7ZBv8ujgLxKQfl9lphkF
6cVdP8XSx+A9xb9/OjC58eHAdV1F/b2Da9RGxm6IzvmSBsYTmuvH+x2o74svI7pIguVvjSYPBZb/
LgUzh1JIEzm4AeUNVHhru0YnLByiDurKL5VyZ/5vYFx+7ugs6YMJQjs1mI5NLCfKG0u8MT1KdRIw
rJm0HELOVruL+Ps4+qcubuVpT0bsRpaK1q4+HZ5ex+tRzG1u/fLcGwJwoPEh8L/xloCM/HW0D6Re
OgIH6g20UEPqxXAmC5dRHjjyYAjaDIC8YvYEOWkvanz3pcHC+4B3nipuvCij83ODb0TogwHZbMXC
ITKOpRc+rFauUOLekWEXiwPikSZODzKMqj8Xfzot+wBFQsIe57G8DEJg/V81oLYuehlZ6i19h+8+
ONVnFwvxfcdCti+k6kB6ZfVcWIwA0hwrhKJGGf90A5aqec9fkDJHAO91/MuC+SFhLjfDBz1sQeA9
SQkXC5j1d/R+k6sW/nZnWf364J7yrOlCfiCBW4IrQ5mc1aU/uSbb9kT/Dt9OOfhArRsR2VrysMEY
kI+IS+yLOl7QcJdUqRPgE0AKeglj0Hha92Xaix4y12K8OJ8A4kOV4yp/qcJ+SB+XV7QuEIngiB82
TGcwH7cYmt5LjwrN/ZAQndUIwkrBwfeQXZTMtGDH92PlQhl1ae5ukOqCiDWJLQo2FXt4CpFwy6hA
HlCRpNKyrPr7zGFJ3WsRsc6/5qmkW1eKyPW7xt0Fa2WRTj6p+MdrWNg0q9yKVmejSbMmqhxl38RV
hi4h+QbP80kah9PnyC79ABzzyCngv4jGjHfMcnFeYAyizEGMKbfCthJhXNzoIWV4SUOfA4+veVh9
/Gk2++YFuyEppTG2n/IZEEdIMePwkIA0x3oShnGBCT0LwibabnwbBqwKSxgLaR8D7DiW2ndKtKyA
SK8+/zmooAqr7/zr2vLrk48+rVpmKiFCvFerhe+WVkbrI/BfWgMr7LEei9dgDnGJLw6uKm08rqd1
danO8i5Qkd5MwFYRzCm6UlkOLhgoMe5O2esEu+ciXMeuaYBr1AKORvgUt41Q3heW/KCRdDj+7h3G
vuRsNOlklsCE+muU9oZ+oszBpi2XPhmeMdO4Bp55B2qVRhanrErUoYIC+dpgysVAcFFvL6tk6F/n
l9RWgucqvaEl4yXFUeEtuZReKxZRaqU7+w+A+Ao93ftTbqe0uotIX0yHvlxRXIerU3FbVrPitmIv
J3mJ5kyhGnANcMwxibDfRWSuOeTfS8E2yBT8cFwo0bRuremkGA6NR5QMEIlCx9ktnM+hbjV1B2te
SLFCRjFTfDihFXB5L9+WKZKDBLBm2smBo3IE2hh967bQBhoq3kyUn9T5V4SjTsSK56BdDpGScjJN
+XcN6xkXEErx5AeOEWoaKNT1hmh8R5sDd/M+XRBQO5LNRLWXKPP20gtzNliGZo3jEO9YkYv4AR/Y
Pj+QgXKxqWcV88IThY+DWiSPa+Mc9/Ewjd1VjvA4EcZnfScbjJSwUh3HYF0GxlwjEikgSs1a9opw
RsNsMEPQnyXnO/JbfXijXao4eMdleoXDb5qxZgvgwxPD2zKQpiljbIOl6tUi85faz33pc+9GqziZ
GmSvHITab3ioSCUJTvHFhsiawc6Lk6az49l4NCVD/K4zbaimU+yiqrsBGRC0PwCSAYb54djFwDWZ
OthhZ/OX7K64DvvQTeMKdDxC+NPzcsja4W80mFsOeUBUD75f+jj7MGnKRVWJoYgZoBoxNAnpox0T
RRBhHqVqs/P6N+1VfAt/dPHl4DvHHERNrQIuoPIEGOzjbB0E9r+czZYLUZci32Fp9sFTCYc0v+OL
KGYRpUchlki9WXFeRyw7T576nmze2/zAnYXUcqX7evB2JSXzYomWuaOeb6sy/eY6SFjtamyRciXu
J/6x9klR5IfiwpklouVroL2hxYx+jn4UyotqGBHrvFHJ10ubFczsL6J7VtDV5oLLiPcsivfKpmCH
6OdE3naQbbfZFjptBGoH+7YHXv8BNa7gNR0vBUrYKDUvopT5BFO6Vid5YqZNbqmgPSMoyTaOucm8
KrLPgeRHWIHCyU6+cD0QsJBDWQBhyEdpQgvzEReJsszzA9LGqjAnrS9cwq0eTA2z7DcuhofPWWlX
O2pF7OxJnNYVB7eUEZGZoa/fWuqP1ySzFV03Hlj+gPfoPHTfeUbyO9Bg63casiOhn+sEQ7AnZadx
2sG8XGySj7B0aPgEvIfOn37I1krKgMS922hSSAjz0rOCBEnmNLfraxUacll38W3WP2FIRVHhWUxk
JPPwDlNyBxXihQUVILeQ3QoU03HzKUQgXkzbfbqwRdN7/N72LhutMNR/z5xttYk/bqEsg0mPO9er
KZs6EQouyn2WKNzWJOyBTnuf66iECxyNsmoDlkyXp/k47FAqzYbKvpRbYLBMAzGwSkzz1uNnNgsd
gt3Ue4Vb+X23/8q9mlRqKUou7E0fT2NajnU7ic4Db2FtTSx73fJLqDFWZZU2RO8FDZoDzJDyNfVF
kCr3nVOwqPveMxBVqkk01GRET1OYOQ8Ck63pgSyuKvvqCEbFeEhK7H+Hwd8sXln8fpL5Boxd4d0k
ZpKd9P1TMnXZs7Ee9zqcCuCellzi8UKTAkvGy8RQGxQcpp0taPoWf47QSIca1Vwx2uu6YMN5G2p2
s529T8OZwy5Gtbu4IYyXcxFh5H/GWNelYsPpJYwKlAwvOolucqK8tu3DnkNMoz7XbzLJYJGrKwf7
Kz0bIRL1J64MowNTb5srbMQ8mqXzZROvGLF2x1xsjOlYjcwQemJWU5+PyHXng5tuNwzpZBJqQtdx
HlcSImeZbPqe11jT0TtBVSksZ8rY7NFQcr/ysarNNolbt7tPNbqb0q0H9obS3E8wkEJpqx+I0sWR
1/fvT0h6YjlbgkC9gcdV+jKWF58hOI1g2q3Pz2YtI0CqpI0L/fLuYRSoIAs9zJQE3zDGMk25QHTD
7Lvo8M1HfzTYFKNdLodqvdLxcrEu5TsX4ziXk/+zeV+rgQFtyVy5ftvOPJXhfApaE9A5r5kZIMhI
MyG/UKTwD5Dv0aQvk+relOc/tJdCyd/KgrU7j0rRfXa2bftyEeOxlRPUrrXpaLTxkxeye1yxQoj5
OAc49armOqXcY0O3P0U45LvOJejevkovtOP2EMIkMAyVyUKio1OXyAOGMv+80HZ5nZJ3JMGH8zPM
dzsjxdc+rzPLw2JUzPdc+XoBacB6KsqpYYNVb1CX5vj68IDntkbM8IkL2x2YBKc8bnOSJYsHQ4MK
HSKzZ3wloSelC424kik11blKeiY/6HflFo/5LPLfjNhg03PMNGUr73FUZV2kIcTzzDtKaLghZxBF
Ee0hbnh+XP84lyhtMyHcnKPcnrAbFHVy6ddTbef5V8o7KSNir5za8Kmye+ZVRmHBZoynzpzsljvE
0wsbyJEEAgywC8khaUqM6LoMEmv96vkiq1mDTasdFn5/gAyJFLo40VBlv8majaVJjceCbQ+khsZs
/3Q3/xW8eHqGE2fOs4GDWUQ/TTAhHJYUvEk8MUfgcStctxK2GFI7/4KeBisjbTzisSY31VyWsIqt
bPQ717uJvokVjNB1vxkh7n5M1Wm4whIKhoxAiUwSakUIfexDzwlfDLicMWiSm9hkWZ7zT5oB2ENA
/vsPMzB8HDSFVL2mKxnjh5IxOqpT+qFN277itE2LZGQ/4Tzsy0B1ZHiXN9oHRM9ZJxp1yaoWeI27
+a/swu3xr/gB+yMTE0PkUqE4dr0AHVcKQhQdSh64G2GOyqlMeUTBveEreJNy4s4yDod7VBOBarCz
2uv8Y8dEoW2/Z/Tf1i59FSg6JHlJRGL/EpOfMz1zj4Sj6XfXHvxOcH2tRQ1Z8TaolH2t01imvGyq
vPi/+e6fmohTro6rfD8LjHd/AAfyDkBgpfrIlot7wGz6lFSf8u16tCL8CY/Fq7bzc/NTJv/LjPDL
adETgxLx5Gunvb0kJsDHyY6e8teyIBbxb2PvCTTMZ1TPh5sjb1h3SBfmw0VBLdD8c27cz4QyquQu
dZky1sUXNvNJIJXIeOKJaOh6mz6AoE+2RQksf7Zl+UOKO9PHopz7UsR7/Ub7Ws+tFxWSmyPGUbnP
GYfHV5+C+9IyBsB/8/hrz6fjo3QDLAOAH18McEyFXWTbTlRopB1P9H+ob352vcCm0H7tchzsjRfc
VQj2WA8NtnM6icSgw2G1H5iitRbroOy6kmTQUkuQKIBWJalir7OV5DfaT/acFSawl3tBMxo3C8Rm
2dOs3p+hgIXplXVQK8FFV9qSThfRNc+83djrGwxfZTAyMr+QlnyUZhd4v4E+jvSSV8jU4UVxXU6D
tUBc3HpSVCNAEnkoSKFrThuIVRI+SlDH9LULVxlPCVse/4MEOG4oop+Q1CIt+DoU8MZmpCdJwgOh
m7ftd0nCtWFx8KoiWhQtVwk/LuCxs6jTQUKC8bVPXzAEoRcO0S0MJK0asLEAR6XMFu5G3sn9G0LD
XNdx+TA3Xa73MU9iGYQvDNCCyCvGZ5hbso3rlWQHMTkiZOk4e7WePQXBAKD+ba5hwSEzlidSydFo
1WmphDVK3VtI2GeBNdM03Qm5CTUyQvm4G7s+c1zkqUl4NyaF/0NefVJom3zzEvuoGsvnqUEGuGki
5a4e5LTgsf2GH58fkYStgqQ4wO0hWmLEuxBAX93ZloU1LbQDX9kPm2B5dKTvhf9VAq9AIXSzts7w
RFeLSL9VWKZqZdqadszJnhZSbeW8H8mnbnOwfspNvPyDEkCWimnxaMFGqXcm8/73GYYV18uONyA/
9IALHgOHVO5x1FwbYb9MF9SxCkP2rnwU0IovlkqUNpYSJ4no7U9tYZ2xlwrDx4iIWY31A8qqaB8F
m6jCL8ct4/eW6RSV3O3jOnKdYPA3nHaj9ewQm0hHg/4sy5vqYzNG8rJ3mAIWqYmQpU2NyEgbmQpA
xl5fTUd0FqzJLTN+FGo7zmmz3Zrq27ecOdijI+QNpdwYSANjMs0TrBJ6A+kgl8Py+jt92+PHh3r7
mKC2JiiKIRIBvorTu46Spr6WKIyh3H+4opsBSoRT8rmlqtXZKwgTk7Dng4FqHTL2rw5G8zV9zFQD
VcjOnUKq92oVlktIEYNmp2MveDRsbq50nqKgSVm+pB+dLOKnfWFyuRHoskAoE8lY8J65lqOP2+lP
kmPdCTkOlbTsjoVKg9HKLovilVSNQZjzeptzRF8YXu0z9BW1+uIbZSRcJJb7W0lX79y02ow6X993
ZLLojq6uNvEOZfJh746mW1Ym1WB1rIcPhuY1PppnLjfCAv2jID4xQhWCJiMMJFUiERc73b+RhQSm
3LO7fdFHmqRsHjU9qNwyIAaKIkoEYhN6q6L+TsNg3NX8/jUaIigvAYqxlaZnq0Nb7Yv+exmyQToz
I6waDnkZSVnrcIGpXXqHmRTh+NuxAxx76JYXFXrYaNq6aYjXNiR/Sj7+Ju6hzJYsw2u0lyleM3gJ
U69lYG3OXLMghPQ9MRPFvLLBn/BrIhgx9ZHTHFQxogk4rTX5cYxgpNEcP/VcV45Z1+MXbosvhou4
1oTS1okxFc5brKgBxD+deAhgOYLCd/Rqi7rHe64B2lDFdbTurYdCx3KL1X1NcdJYDA8V7sM8BuST
D2S9eT0GCvWVR5Pfz7+d3GLD2xeJwEXjZWuS4wMo+wN2p5VycnPaBrj102PR3r6oqczRVMkNKaoa
mW1XjZFuhzvkUtK1cQXpPuEYH2kvZq+n+Kz+tLsY7cV4mYrafkWv1WvaHjMA4PV6m+64vVCdflWn
iyGpYBGcVUtfAyK9V3/uD4CnBrVllE1CYskCYNQU6ZyP6GFJnVjY51GFddhm9xurZ3lu03J99R01
/Ilz0l5K+h7wxjbcRscRJDqHyBorTBHOWP4fOPdD66gGLuwaNGbPQg8k0xgOGcY7fPqIUW4ZfXKk
rh5jcncHrA2KR8R0QuCJQOo+gM4n1lPJ0HxcAhFy+yxLiTIp01D2wSNK2FoOzHTl7fulOz0PLKj7
ZBjgElUyaxvzV3o7IM7uTQoEc0PuLQd7/l2mx30s3r7y/sQa1QuJvfEKaCL4sojObFsbCr2nQynZ
KPfaYacuEZuoCHUm/5a0yWEEW3WXhRFsVKYPI7nl9uNH80fqKLa4SDOfeVsipVr+QuBiLpA3hs+n
nDvptOaH9k0A++r+RLOpnXe8uEa3VGgAnBZGuWtSJdYIICBnSPds6GPaxtR9We27QdfV9tKCcJe7
1Blrp24zMJZniMX+Ep0QEZ62ofQKDpX1lkFVPTqVvSVoJg7EU0gzsPY7CSRiks7nrXV2xVLwEYfo
urkEQ+V9JeJmBOZ+Gi66MZFwqXC2n3rF04xqLCqr1mQF90mNnU/EajkXTK8xw24ltbbhfNH1rAu4
DGvmmLsTcDHOFdjlB2Va1Y8wv1YK6XhIFrF4DRFrxWi55tZHMyCXt6EMHIkXACz8tbGw5F8U+JtS
3YWtz5D9ZZY0DJ2ikr7q2VWdCEj2j2lFUIyd+jYvDqpuEgJVcUTIhdFTPFPpsC9bSQavZdy/IkCj
CzB4VwnpNZnVQA/ypkcMuIKkfcMsHnMlYEj3MHOSKUrgRAmwtclFRnc3hRv87GVytt7F36V9nvFi
qKmUhDNXLykggpZOBbKfMyF+VrDt1DGCcefny0vn9uqK15/cAeSZqi8wTYnz4SEy8QkGNAULDcH2
+4ivtftAx92Wsy2K+9DnH9AB8+QlBF0iqh0sUPMsuARweQGzApfjbNwkFjxB76Yk2nnBZWs0uXyh
YTcwQ26Ci4IfFEumcUadmmml4Z8zFy+dnv6s7k/whqTN6HKAMOmv6/gt2McbwUHoNGGysx4WTRx9
0bWlqmjfSoPWQtH1KbvYVHsgEDZycRRD4qNknzVF5Pva0kq+xqqQt9q8TpJm/Ua+qy+8VKq0JwtX
m1uKqndUKJnjK9iJMU3dVQ+qK/MZFVUw4JCXP6tAHlLFUL6hG9DYShI3zn11LkvWymR5On4Eyz+M
9JNGiA3/NAGZvYpOy+FsOkTfD2ZRKaDk2NTupZzCNBS8M/+TBGe1lO+/fCalwRWzn3PyF7bpsjBZ
jqep7L8lCMZ2Zhxjh9J0qHGsnRRtfdkq3ESAcJitfqCijPEaWmMhkNAU3YfcKSI0Ca/DTjcQ00AN
zmI9exErMwzZrpI4qdtgcQwz4kNtR7qOluFclBMYzJ7xeRoOfT6L2aLohj9fdTM3xGahIKvoCg4n
Xy11YLfW1UQYe8E2TQ+y3N2XM4ZdJ83dStw6ERvBUetL/mZqmPaaPdaj8appM6P/uSK+wikl4xl8
JxwdGlvIcHbgbKU5/tM0HHBnjRqXXeNAiWHIetOEZ4n+bsAQ35+T2WighQiI3pPgD5WbGnxIVSL1
8f/M0/BqbjfWvHdLUzXdT+akHRJUpb2bPXTxwovKshsN1tY0MsDk2bu2TefSKzfqctqorjhvUVLX
yPxEKNj1CEcVlkODiKdrh5YczCzFTOEzhsZ/4RZD1lBf7Kp0IlsLSHzLj23fk8/3sHow03Y+TuvS
mVjPT9mXcc+1OKUFcR9vcmEa5tjhkNEOWsGcgG+xrkyOWduVXrKAIasW9Frsa5GPJ3X0JfK1PkbN
gfSpEejBsvVZxD43alb5LEQhktU0190F4j3EF0Ggr/xshenD2+qutGaKMqzJnAHV/wvQ1j0VmXp9
bbQrOqEgQ2RlM3oQpsYlgEYVLND6TeiipikLQT/Qo21tsZl2H4RxLOhb8gcXaPFRu5zXhtIgLRem
MUFyDyTuN8pDTlmBX2tLVTmIudetMhPLxFMwNocwfGeEapkkd7KcdpTSrlk4CUFji6D2KKSCIcYG
XGqRaoSqcqdXPb7Pws317qr4HN1IK8H/hj80MRimj8mF/WApnTlgWLtEWOgGHkOmetvwAjNWEc6H
pgt+sJiHUMg427siblGIdIE55jndFnftMsuEEvT6xOBKC3Md53r3gvHeXbM6NdqLgPn+klTYctad
9/RVZNV/f4vWYi1z5SrhnrWtw7mKIN04yB4ZZlOxdTbIS2QUFpwCvrU7KOh05QP1sIon2CM0e0Ci
iVJke1DP/d0UTjyg9jag7Fu2I2GsDzr3e3CwM9K6SOwVS8fLaSjBLVu0YJUHdCVm94SME2DKyBMm
ayA3LzaTMP9HvLnVUk09H3Li3lPM3pHfECzqnxEtXpfJzc9Lb7pW9ve2gE0zoRKvlAanRy3QJRSn
RM2S8k7L9Ij+iZyDZ/D73MgDm8X2zjGMahU0b+OAhLkueEd2RWq9OdyRSu51gLDVbxKAq85W8/nw
23DtvWF2HcTQ3kxoEWPT0rIWUv3tLsYhwcthO26bA6NYf5qRdTFxdcBp/zCjJpSIM7HT6qGDax+U
i60vQbHvp75EbnslEA3Avdauj759A5OfYnbwgTzn92e0gTx1vv/tWivKwPwFG6c5Dhh2Kt0A9roZ
u38xE03Fgyw7+p+YKK0Go+93ravxQ4WLU9iblYcjl1v7e3V0lNpKkHR/4lTG8YEdh+0MfKWjK+wY
kA2FzVXwQ8oPinRMZnkLMXPbg7PnLiWhN2bfLgGNLghaEMvhPnwN5R+O8V3qn9C5M9HZyuYp4qnB
45hwpZrezGwcMBFTjbasG1/txbVZI5vlvXK1H7ORBCOO409rPgQXmJuISWrVY0cswv7AEGB4NwWk
0z8UBlXxaPn7HJm5vnGq5KCqRa6LkvEu0pv/pHgBgSgGVgC2MKO+p3g0vdNKMKB3JwYzEC8surpx
kYeznlihfeoXa0U/9ij57zEuraC9iy+bJYC4zDcpyYP+hlGZKqbjc0ouUXS1Ki6cN7YPoJwiwFLv
2vbMNhh7CRrKuvK3BnftqStZtE1VJEQuMAZiMeUHbp8SIOnh5C4gBGVh3KB1TiD/XEx8/yIBbQlw
U4hXQmqi8ICJWWJRczC/bk5QUVMsRDQXcmCTNBucMVcZKm0bJaK7sP4ksBrbJUoCpiHsRD15JDt2
HZLBI5BWwS9h7S/uZtHbnsLA4HIkLge6a+stqiaNP7d6jVF+3eY4Df0fgtCj6BEA9WSQ5GuFT9Eo
vjQrkcK5C16CUvsSQJofL8aGPDh7ZkCHPhohmjInvi1vkCecz3YUPPXEC7lw30HIXkFYEVyJPbNj
dynRsbmGpymVSG/0XUwgF9kxxBeR1K5omUmm6YqAhic0XVcfdKlhmrRM65vLGFmkqIYl9EHxAdU2
opUvOLkZLCqTVNRQiaPs/SjJjZLF18oKbrTAvQAo1XxHkFq6+cm4/l9UxGDinStpCdXoAWCAsKW3
eqOJU3mXdk6MStuSAvIwRDG3dl2lncEe0T9/VxyeYPuHwNASgSofHRBr9d/MNDabFWAa3gg4MbDx
J7sc8RUOmKiGad0gQAp+SiN7d2nQiNzGc+lIqCY7HFyzMTUu3RXNm3qSETxPKnFxbUo69xuuc9pJ
rx2sPpU8JC49y1HkfTP/s0cYOy3bqzoaKAWBrqLNxd/SyyxRKTc19glZqpZUccHlTMiuLrNRC6Bv
rn+QqbAhbuLdLyYI/C28wjRS1yQ0STPr3w+Iucm7GHJjhl997pgejQx5hbriCdvVYU1Zfr4nBtYT
i13MYbVn0hbNxI7qPkwL/YFcj2vOjQ2ib+ZNzlkbol8DF9YNV8XGA6sPg0ke8NVqHYBGiRj2Jei/
x4NEOAiNrQGh4ynodt5LGhmjH84NcbV1/PydQw/KSVLQN5yA9syRpd/MMcxEjkV+DwXZlou3Bti4
av1XRw4ZCifxW25QEyCPwehnuheMfFFHTlSuA+0SvRxY72fv9Es9HQraqU0Ca285QMGGfeX1dc3X
1rdZ/febOsyn1rtz3TsU5axBH928ahX96VuHc9O5MKxz4ll7wpFjJsWFSZ9L0FzC4EvpEuNgmwHl
7tYHTu1Xr+AEzUwCu0j13eqqx56AyLxrCEf+8srMnD8Slo192TRv/HUKx/MBTJpLO9JPqWO2NNRL
wxH8/4SZiIzl0FCaKLFZzAT6rTwwR9yujTtVOhKrHrL5AyBLnf6Xk0tDS6dRuwfXSl2azisKLfyx
gCGeEj4HCQHKQtdEmmGTwEy9dOAv5JftJrsUzeXC9oCwKHwx3JVCsGcQPsMWhr/fvX0Ht9AIi2eF
P4KkRRE1fRd9EOA5CnxkWceiSRzd2qZg1c17mp2RMzLRb5y5ysGT+AUeuu2l1XtiY3nZpdy4CggN
It7sTz1aQ74oM06lznCoXdMRR92LgR24vlvA9M4GUVmQbgGi0a3d6JzpP6kRuNgEJkefVuuNa45N
8sUuygOr2I0IXQ98UCVhxIFq++rXjPYIRmSHHMrsHhWha/lpdqyIUDUpG+LRUPLQ+oJl05pIt+vD
7JbrlxCRyNE8s+OZnA+2rrA6U4xQroozIrihf/SPMB6Tts1i45UP94wR0Gr1G/HOeNeneYDnSQQL
UWzAhwUJQvYD1mjflyaVtZuiHPGDvy9inS9pgTkeywJ+6BauYMSjZnWS9J8VeA422LR4nKOzSD46
vR9AtbySESXmbKd7sQQAiJk+TgWWa3ARtSL3hJa7o04ujftfBxOXeRBeDqGepH1yMB3ghYG8gU6h
PV0uaVD3L7447toTquSzbj96PPrZJt2Jq0ETEJUMFMcnI6gtdlo78B/2m771zZKpJpfglm+J99c8
E84hLhU1NTxoH+ZHc2/adAVcwWIxGFeRVkhjFAk++oaBJ7SuWETlTNdlqxFl8CJu/2rvivtqajae
Mfn4tqxXFC5q8qKoOakbxXZduffBT6B2fUKMuIFFBgnz/DzUTitYOzzUcctKkmmFPo+4SC3q0L5d
W1apQM4ZTZOKPlIKcu3Z2Au3AxFufrhpCJB2ZL4zFGAK4dpcemTrge/LV7+KYeBKHdgiAEFlKTJv
qYnA6GtWXYf78MUfJ/H6v1Q5anUK/ksUwV1aa9+5pLgzFe4DfCA+l3HVQQ749gMxtI4E9cP6VZje
u/TNQypLnG9MBOxdAR04UuT6V3mFAmH2mL9gfdbDiatxxg7pEqtHN8eJNaSd4/OA3qFsSZUfBcoa
VnEzX0eZyNT57J896S5ESe6yA9NzoUyYnSxyMWHZgJxwpTcBee1xDbNoKkvpe9mtGaXgSsw1pLxZ
feDo5iFwCt1N8Vlk/Ma0N75psZ/KCpGBaEpOfbfHDKRrrjuxjddn6ZgWv63of3uhJtMlRTS1c9lQ
bH1crABeHiK/izQqFDmNWB4FhYIR5/hhvHpWgWfU6PQyJeclxjikM+4QMeV/syweZc2BusManEJ3
rGBgd5JBy+Dh/pZhfEcp4iErnZ1AOXXL/gCE/fNPbdzNd2Zq3CDMTvI6RtLpJi1plpGr3Xd/Kq81
1ERiISc7x9L/85FLv3VHxGWsMYepaVaGEtLNA0qjDSmZGsifgiWP4MYPBlj993etGiK7C6V5MfkJ
0j0NquLM8fQVDgXY/N+eoB/KUzo29X1mwJbM4WlgzTSaUgZuWeojAxX99lmEohitqSTgcd+DeZH6
Agxd4cyJ6Vzjb8sTadaAusezSjtprkvxpYcUi5U1szFrAQvtE9NL4Z/EyR9xQj3Eb+inEMuNvfcK
2R80nOuGD4q8MqJj0oXdPWTDvwDuCuQSqZDml3e8/q7pb0UuzXDxhRer41I4EDYmchzFJuR9pQty
QTzwcUVdZz4JMvrhncvYBL5FeZA8VyqMVmYAqypxWvX5xiq4roBTQCjPs2A/cePn1jA/mKdMtxpt
+e3bogbgrVHOQdB9oW2qj4zp11EQ8rdBw/7N14OuUgHghg3gK8nPwSpJaqO5/S8vYOwRg6oEQL5B
OyVgbR0EaRF8lGwo8i/LfcdZgL9Q+/TbUVdRSxnYxPqS5a5Hm7cN9Da+bnZNGrjVZBbwXcE3wKFd
dCqmxA52hCUeo0Hw9y8qTEw32QEROQchtElXshEvBEijKCEpKH7HjyshyXk2YfMpdvl01GzAg9Dz
so8HED84rgBEltpQWdF7S+7JoFtqiTwlT9+et3Z4u3pUzI2sistW1nmprXu9GZuUxyH8II4Kiaem
nZ6b/CBlVTVTbYg5nyeQaq47vDUM0eYt+vf56D5jlx6LtxK6KzH6HKELmkOEsS8e44LL0W649YOc
6DxL86/n6pkN3VhAWFHPqXuN28eEFn608b1KC/Co8FFjnv9rHePzxhq75jPIC4z9gv1BYYz5oEjZ
wMJFKO6qxTiL8H5t9op4BCI56f8LO9czC7dk31kGdfna6K6D5sDrNmZtAzA8oTbzAms91sBKevMv
5lHosYdph7IpwAiZ0ScPCEC4p/77TcPkG+A+M9n7Up8SJMsLd68C6EcmBVxu+cf9oaQGxts8NKKA
uj5WyONwo3/lcmbgatz7Anx4WgVgy3nyK9YzfLess7iYg7CJWwj8GizFcd5YEhqplUM3jxyabnMF
axSz+oXKYfy1lgwVnH4hSH4Q4pmX+5b1FjKNo14UJVDfZNkQ8ULqxNJXejehro6UEYRCMFQbe5aS
plv9FOlOkQ9a6WDKoiFbXs08Rv+CuEx9WU59OnLzf3snr1WUVv6neaSEiXFrRJeR4I1Fo9zhCqcU
tQeCISZVK7lWPdiYYdDPxzmj4TN48/XtewROwST91lV3wzmnDUmaHeJme+r2kWKAoib/KA96JlJh
GMMaHp1guXZXsl24+BBMt4hs9z+lg6gFvaX7D3rVED72yxI9VkWi11Grjlj/UvEIe3YNlMJqje+Z
NEcZwu8HL1g6WYK3bWFuk+yFQfLzya7wPHekzQCCkfAuUnFVFWDVYeif5VOdUWk5pdZ6aIXqQ9YU
XSXnDZVd/wxg6ci6LaYIVRs4/4NLO8Ro4kSLUwg9LRudfJ1jkYv+35VJyhIGVryRbVGY6m9ugOMm
zpEj4jCyYP7mAfBYT/BU4vjL94w+oB9NkAlDfVEu97o+f+uDK1WcJR5dpNBLOi3JiifptRXTFCaZ
HhzQS1NjVlPrN4n8D2jVvhfBmxsT2JRQhw/azB6OvTDuXOls3vujrmoKC0AhP2X6a8MXaoApxg7h
fdBHqbhaqEa682uoooiVFToV8k1GKwBXTpy9+z+maAYquPf8XKzs4KhAl1bkaNVsUsGhVIvRZbEI
NywXwuiJo7vwtUybB4VjeotJhMpv0C1jWbKn1TpPkpCED78MTHJhtYuyePv4xOZp6eqXe03Uw0gW
lfBg3/QtyKtLjpi7jDvbAl8qeEn/yUBwLHMp/Vg+srHfpRE/Wmo0a/sdvWbzAij0yMu+QlxX4opv
aK1SMmE4T1jVpZDgHdw6PkS0liDF+r3tO8VsKYhZ78xp5/5Hv/wwVA4+59HX+6wuzy/5k/ZCYdkk
iK+UB/fdgRtr2PGMFIHtFWNS7jUmU5U08SQIExTV4CKHFpZxv7gjBEL3rprCv2DFwishuD//e52I
ud4hm3XTpI2r4goFQSsK5Q8O8yjTdIzHQ1cm0T4OOQRsrinbx4MgRM8y6NzbCGcgIfPQVe4SxCfn
kqYVd5UrQfK8DnlIdId3fPKZ0TgoqJgm+Wp27+oVirX5X70MePXzA6M1VfTSaKfSsMOlJJ9cP/9f
6No20eFEWZLhBKTopSDp9nXlx0X1+wfqS8/fcsegDpPo91LATzcDXzrHbb2XpPo+VoPNomhhj/Dm
ecPXwviq5nRW+ykMedv6xOvl8SusYV5HRQTpry+XC1zqEePh9xOEa7S50D/m9Cn9iGTOyR6ktZ6X
TzMZTWdaZb80qPkFCOYLisKJigwOpxiL1rawWqwhuWvxhj7dKlRSDy4PgzNfUzSQoOUsoyf7rRHF
Wuw5kF/Qz8Tfl9LAAlWfss49h3fhT8hs4RfH28HMrwBNwAftZVCMtaIgJBQWo2/N2aOOJ19xNR7A
AM4mjyPIty4nldB3nEZZ7o1uZjylNFf2+jqS+OMCRTF8GUxNKWoGdh0Zn76tclgN0I/TtRfdW+sT
c7lDqyeZVy8l1tXU0yZQK3Ws+Ko91/eUyv/D1OkbKUpi+3OSAx/gcEav1mvnU0EE/4+OFqMLzUHn
zjTjFDLQnNS612oF1FAA9iWhugOhq/t2bCMzc9+V3NGpcGngvxcaKRO3rpEEBVfVQ4X0u6uleABg
/b+hVTpxMGITn1fRaKqgQx/MfVIYgyrcVM8Vxkc9EFuSAyxUDDjB3rpWlWw0wIOsmFn0FJ9wNBUo
TwKbIc54C2bwczs0WfPCi3HOIITUUx1JmF9Cne4BQQ+tUgyoqu9lJPFwUFiZNzyC4we1Br8v5sPC
I3/m8g/lPQkx5/rS4XaQtCTMVQ84cHZefev+cdnELGUNbdVYQwOuSH5N3mLgTJRSKEdqp262Cmbk
yewRlfKjY3fXrx7D7U+HbjRpgearlFSgdE6iOICl4JcTVG2nKkxi2UfPFA0rF/4sfvYjCq1AsKwO
fewjaBFcPcpPhV4U0hoRPGbw2bmr02YjwT2OABcViX3QBytSZlvUpJFA/cQ+eB17DNYf//EcCg9c
2KlLkmqN38y97nU9beQ61WX8jFA+zu4oPasNTXif/8a2eGHZIqWoGPSo/NK9/cSn4IYI5jOQMxU8
4nR7pbegLDaYSBjxMRNGhOGLeTcQimf+Nq6ZD3/qc9RCRtbuQvDrPh9XVNeP+ExcBcC/hWPrlkpE
7f4XgrPgDhPHspxmkFztzm4NqnW024ayZnLHsHBAcE6tMXmGJx92l56AQJb0jU+Fi9yAVKTN+8RQ
jqw9XA0g0cf/5kq6HnFDHXTaSSV7D4Ul58fc3YvzGL+bKA25kzNv+SLCphkzyL4plVk7SDs3Vx0K
QjXpJ487LvqmLHt98GtjRjVlI3+3Tw8UY9Og3r/+2gQ9vOKMKnuEmK6eSjhB5nqcx2gnBbBunOMY
BrQ0pzVDvBa5KsXhPBCDcUmFsbeUX4y9FcHd67KkFej/V6o9O2KvFZ/S1qbVR+A7iu2/kcU9psIy
iWbBl67Xi4puq04ef01vw9g+7u1ArfDiF6Ps1HMMSON9SomgLWbWJxiCnI5mSGaQ3TqAooI5EjqG
s/PJ+ilPsvShpY3CSueJYwlx7QZTqXWGRg6yue7YcdS7gyyMFAoB/sQxp0cN7qA5C0qqCJErI4cz
lwszVcEJsZ6zpgDwzXGX77tXW389BSXjOdK0/JydNAawGMLotEay4dxYpf+2Aak24nO3QZ8ApowZ
FSd1DY2Y2Odzj4DoQD+papifrhuxvF7e3yYp4r3tY2dGOMOTYEGAK7ynh7Wt98GHV3sRIEAh0qRX
IzulEyAbv70bNdfRFADUI1kg7X6pyt2qFLP8z5TOS5q4AEWMJn6QPOU57H1F62qLemyI4mnz1Bun
jcq4Hk9rF9QSOt5QvBdxAHFhUFf5fgQW8lYyV5ra6eeOAGNZQkA5JuN/2bHtqrfFfvLJ1L+ADmvQ
csFRYJ9y7aoFWQ3yj+XDQqsEoHRwfvxB3iEvFRJPTiB9pvPLoIp5Vytd4/i910Xumb4oy3zvX2W/
eMbi3BqqW2m/iG3FxFC8IcE5dp+Qz1kfBhu7LMWIJM1zebff9JuBozK1xMBoSlLAtl37OF1EKFnt
tOtdNYgdKWwSfxLyxEvv3Mr33mJpGO0t1euZg/9s4EKdBqWHn+mlRD7NP7qwxKEGHKRKOGYKZYmA
QvN4YImRFdtIu3CitDqwRqllNquusIaAUIPuGXmd5DqwNa8dFv6Cbo9EfRdZH3X2j5lGOVMJsnez
LP8DLgk7gujum5An8gxzdjNvPB/+WwaPrfXFfUdBOV2Js6lbmSJf3QGIHBJduu+JFB7C/O4uYQAV
TcAu6gngLuyk1WR+R4DaGsQ8cfNv+oJ9afMDCJL3tP5y1Jx8sj/R1TK2K3lpoitOurhOV2JEXXrE
3tR3884XwfgJRIl/yPCeu9C5EEAAS4QBKyFg6jdXFaqkhjCJeDoxrYDThko66cKUyUlEWvW+BN4N
s32l0xWHFBY5kvuEqkTjxlwW4N3x0LT6kfcJpdCEuxxaR8lkxR3x1hL9/RHndQ57a8zgPa5w5K8u
jFuNppAE54sDYkIT7twKbnvhwtBkPTV6tpEStKFek4gagRHCa9vUoOuDoTr6psBCjRE2S8Q+zkbY
PgA71y1Po5z00FEQUexHxtS2thrBksXKPD5c5cu8xqP7GhfHD5hoI+RCrUpWAuRTCLQ1gymscXWH
BdL6jOsya3+aEp4kl8BKlvGvzAt6UBdpsafnQ2rLi63532P30dq69VcP09hrw21Zy775vgVCmlzh
JkLvMZKxaYhaCm3aX/9wQnmdYgTlsVJBeGBGfAsJYoo0Hwm4lhlonMei+oj5/sAQw9NfHoHQITud
iqGl7F9+d5JeS13AJ3eh5XtZ96sKWXK3RcFHn6AwJGZQYsoCHCWoaTvt7AG5y7syy3jSShoxGiqc
LwBZp5REk3O8MSAbsgACRe+dYlx0SJ1toRYL3UB/QxLdrT4OFrSo1D9vwfsVxFziahqQIuxRxC8+
Bwee5JJ8grZBCMpxM13l7tuZYSkYMDyb7tMf52P1H8Z/zY9FNiT/M2qB/vR0jnZwBtLKUjhPR3wU
fzSeevlgMVUWzwI3KmmS/NR24irZsHnNyAvbbOQBjV3pbx09vNrbOSdC6eQ/vfqcFQZWBkmx/ese
OVsAe2jjLEalyd/8qww2zKRZzyv5R9ZwZGvVO7y4ixnpcJlrcz790ztAmWKrxpnnAV41++103VaM
raRlQlsgrfLLmVjXpyM9/1qauQ5VVEmq8vGWIKU4jSZro8uGRDZj0MzOrXEJLzEUMQaUDwB+P2I9
r0oOrIp4U3HhReAJk3IVXB5JQe3i6rOcjyaQnU6CLLz62vLYw7D+qJvOdh5UxCh49z2h3i8hMAMn
83ZjtVKDmh+zOJZKHtV0BJKIVCV8WbDj7Df8J8Kp0+mvjPg/mVC0OtXFEFuNYLgxJl+M+02xf2tG
wTpSrtOPcRes2zvjzkn7hqFXSrjBpOWtbw9WxByxSYHzDbwjhfXMdXhj2jnjntye+BRmDnNGh1XN
vKChSpw0YgH9h3JQIjPBrRqz+QyeKwVLc3q++DHgcuNrhQxlgAY4uP+2mnoFRvnGItf/Vy1osO/v
LvfHlF2BZJSD8zozFDzSl2mBBRAL5jQc1YsKQRNYq1otAx1NWNorbP3Z9MugH2R2p+zCaMa0SdzR
+wKlEx1sR/DEdznrvBBWyIA5YXobW5/m3o9vEz78q6QUXskJO6X8xxA6kpQZWq2uXxbBDRKmFiua
RblV2HpL4A5JAF/LtpwbC0rUJBZ6W+TsRIAvfDnf4xIjk27xFD/xFbDBkGCJ1bqPirzk5p3Me3gV
6gpkKORgL3/QcA1Hrx4zZJjm1FPwj5PVLtJGFbwqWfV/o1Nb6hm4JEB5wVJo/fygfx5LfFIXvttM
QMwdX6GvMhepyA82Mv48sT5QDH/3UDZHNahKUPk8Jy1x3rm/xv8L6/mNr1HNw0UrbAfyWrAc7rIk
5G5hF9iB5nNbqZfFTOGkbkurGmm/nxW4aqCBOsH9rq7wEKFCN5TkaG2ZjMHCvJifsXjED2wzRcsh
YiXu5f6C42MFQVfUsgTByHCXm203tfUSbQayIsPAS1a6bWjJUtcNy6i4obBy40Du8qLU0rH5lL9P
+GuYck1bxUEbpy0lR5keaO/LZbdSTu/x455+ToVwz/X9U8QPprvpon3aM4oJyIA3MtXCeoqC5Y0s
OhfOmc5sDmULPTIrb/4d9u+fv0IWZmfb5lzDolnfTFBNJP1rX9GmTWRiPRawqsbxgZRo2uJXsITd
xSOcdz3kbek5+5JuHc5C5pJCBC+Bbj6Z4tD3w0csnd9lM++MbRYx7wDiN9W++n1U+jOkKxNn49xA
Yk+xpaNf1pF5AEwTxNQc2nul3clFvv549w8hmrW89EWEqDfnglNaDsZCdBAXgyVaJlO/40C1eSWE
jZQC4Bd0yYdMzEcWLv2c4EBisIbDF6oibBJeNIyEE5VuS0VvKNFndikgdSjjy4HVcH+5q+4Ld3EV
25qMQdejYHht3j8I8Cd1RkAV1xPBTypH4xWW7DfwRYK0ioCtrdyKw8UDuanCpoReezvxmVBfjbRe
JFvx/o64veroYtRUMPpZGHoPExYhXCwl7YUevirKMblfPQBpjCfDmYNF0H/20HxhHRIaORJD714F
MYzrH7GQoPoK9sekF1PCRznN3mQK3D/3hjt0locKJohAfhxL5o5ZR2SG0GXKHxX0m5w8V9FWoIpv
vvmKZZP9VVlpxrusoV4mUwAMlMu/fvnOx1IdgZC5bAnmMaeGqu6SrmpQpJ+Kb95CfT2CfSitluSU
Dnedyk/9heH9YvXWZDXb32ZwEAkQEb4JohPUgds22Fzh+5cbJ/AEv7IfsjILYHZYDOThR3nJ3ong
0N4Kek8UaNV0+6sLsU0yF3oZWnqVd++WNTUNZDLB0/vbbXaGesgOE1nAhXOl32r2zkl69tH4zGvq
FZyeHSkb0gUiO+62Az/zlx7hjD/U63heTUpW2z3CvUVnSo/PWWgOtT57rK4Rb1B2yzPSwmXY99zV
HPcdKlixArNh1sStfd9hsovlkTMUsgqAfoktRxu6pqyH7zDQods+hBDPfWk7Gmrixo4BhYFDHlsC
/pepmqyubQdsrbAEsb72gt8vUchBzEOvUbnkfJebAXORzsIxkdisqTzPu57IsNJPTpPZDRU8TD3H
h0ziN3UbMEyr/H/gZ/8tEVxK0RveVMJSlnGnIDglt5uRC9UkjXug1k5epp+DO7nfr9ZLjDpTBI4X
eRSWYzPXn0dD0cP2Q4F8mnA4M+HsXj1zNri3rvgFC8VCIuagh1b+MLg/NHyOSUGDc0Y+DF+XJf4n
jVFoQmQfJSJ4IaKnId9bHZmzR2JVRu47V5FHGkV5Dla9UMTqVy+rzX+k93iwZZRN9r7eQalrzBh8
8QGv97nd4x/oDEhw6UiTWeGI1FMlXEuD/SH2aTLeMaqEzpCUK369ooYKcPLTRgZnqegeERUm0edJ
YnySoqB53Qc7ukXv5Ce7QkhOC641z0S3PM1gn7jxSzL38yO5b9QdxSA+ObhJPoSu410gi4z43JUI
w4OaHlHpzOW9intNGJbUsmFwJEkChEQDbkFw+Z2Q/brUv48uLOGZWadQl1Re1933MCSSxavmxzV1
vypJ8rosln1AXjT2eIryY1MA7dQhY05woNpynicnb1uPDX+wUV/5lchL3YIkTIccGifTWANTFio2
skmHWNQ9rkhpH2VM0e151P6bA4zCKIjYiPqWZ7mzv4wCYAk17YRbW13gXNc1+dHqU2ymU4Tc8VZC
tHui23KlLfaQO7eIKWqM5XrU25DRFIf+i/4VwWl1tRHRXRPkB3b1j7FU/hb5NvUPtwo5vjnfFkCJ
LwRa1ueg5IlWLdzqeoyVOjMBpwzkq7U93+RDGhqZ07iCpENAuG3oyM9GU6fF0wwdvm3BXBaja/cO
HVsTiqL9lEb3FG1vHW/c0MP14+qqYdBMGDb2bnB1LIJbFR6pWFmkUXdb+JqRzxI6hR8F/3+EHUo0
4/EdpqpObNW2wDxFKZ6WlTMh80Cdy+EBo+cB63tcOjl7W/ChTa75J0sl+tEcjgCsCy4rLXtx7o62
Nf3mIZ/Wle1wmjZaBWcl4NPYcr0BLl95XrI5a8Uj6yx2lzgI9eiESRbpSoClzoMjeg3a/Yx4ZUOA
qkostmV/7h9638MCkVhFUV8qjrdhqexYHwcOyJXh/kfVoY+7zLYne9z4rCVBGmY7e8IqDHwvygwH
s0Z/jrm0E4ina+ht57lnPva44af9zoSpvHhvYTHVBnFkFVuoVc1OgZLYaZQqYKBqnsn8UhkE0dKD
UIys7QlIqEZ+Zv+gfZVmR3V8m7VR1NSd5erZOoY7e7J9xv6DsEzLxLtI/qqrpzwAjpOTCjZBVlH3
o0f5HqSjS3zG79TPtTxLy77GoN2z0uOd0iVK8Z9bS2CFq4Drgz1unBiwIeNxf29HG6unmUdJF2kz
hkiTqU9hxq99k7ftkgToCPWx2WeTSFENGYP24uM1pCiLoAhMJQg7tTHcEsCILVEJI96OM+fHXDC9
8YX2NpeW+PdzxFLokYxnzO654xMp0BS7MJhGytE8AEKx7tGgi530wj3DFC+JeTTm7rDi83rJy1lG
ar4ds44XdzK2tEH5CSe86reHAfR3x3XBIrBJ5NqgGEIm7l1naJNaQSQhoDLuwlnQERR8l6WpmkSk
fFhh2vpRC14CwrzE41F46ysH2U6mVgGpWs5PYjF2/UaSi1myzy2/L8N2Ge9ZjaoN57Ou2ZS+J74E
Vih+dTrfK4iGgjWwAV0FHVcL8G9bZ5yMGnd4BZp502gv2HWMXQNcKi7qhvfY2uEeCDS1C6BpY0wu
Y2tm/u8b0QCVRDDRQaY2UXQk4xQDa0/iRJna4tYp28yUZtecBJKxgQr/3D1mRGiVjVqY5Vrzpmb4
0SPz+hBKZLlb8HnyteeKxUotOsKKz6c3FNXwkh17S+HS2HnbaHzjr+QYpnxEBJKPLHSRBdi0lu8h
IoY4xgbP/eUiIi9lnzEcBTW/Vl7C/sioYAYklwP3csLLGs9rfgfvFjBL4eyi95RaWnF3QNbI6FAA
nMz7RO39eQ9tCGYsvj0ZFs3ibOpNT95dzjRA3cZkq1ZmP3nDpQkYnQxSA242YzxrV6HYyjW7y8QY
g7g5vmW8GaKC4o5aiyoTmK0swxQy0No+fSLmmz9bCREJBAMi60Wwaw6SQAIL1f84YJqbzhDh9m3G
nlkvuJerzBNDFsREk0aZARllr744VbUzN/JdRIb/FFLosgV0X6QPdeai1Os8oQAu5QLYVoXYqJ/Y
h3ebJqMZC7gjMJ7GmhgZfQSvecKNkxok+0UA5Yym13l/hGMI+Kyaons2aGHQRQEpo17K+hyRMafs
y9RTPdK8UUYfUhZayBeX7VH9VmLJoNl+WifVrtyBNjB+pO78qOWjSdHrn1J9mSWnr3B0jO4XZwaw
qn8WKjMgGeJPyWTKS/Q3OlQNtVH4sgmsFgy2+6Sa3yS/nf7BotgZKIaWrGPDBeRLnFz/wF9K/Me7
Ghj4XoGATAMZF9IldOlyOCpV5I61mLImU5x4I5eX8ih1pjjtro9mAuTtAqUwc97ByaB/tWF/QPVg
BicVhKZ3CcHbHhXHNBS24wBSKUg5e5AvF1WXzQmkJCtJbUhLAvi3hCs3PXrDaOdTUseYeNGoEsE5
pBy+PffA2JCGV9x7LwRlRkr3lQ4Br85EMD6SwNweG1TwqfF1Yu//XD36w7Oq4ipa/iy7voWWw4AV
RM/8UX1hL08eCCVn/b933fPjdv27mfrJlutBroKNYm9llKS39QpVRNZdlnCqHbm1Mk+v/zB23ZNl
0alPMS2AMTXDFO+869TUJrv0rjVkf3PwYue5LUJZf+hrTmEqVBYBanNPp8zOMojysVy9DOsYR7EH
K5kFHluC3NS9jycGI31TZ/jQ2jV0ZGAJN0tfcic5vbpa+h7x5AgMjWfiNcYS7HCOqwwEv/rliOvJ
OzuoaFnG2biIOH3Cd5y7u+oUHw1ubq1xM0aEpqXrql9/febMGjFgQ56CpQB+SOiXPv//hpXrc3Ia
zeprhchytR+s4+sOMIci0AdF4+BhPI8C0jr4StqoZxF2MqMcyhwrxXdMC/GRtpnTExzX2JUMATxF
nLjZJ8HNnEODTLk1wqr15lZcKwAyKvbiqAdgnGaNmndWdO11UcpMx/7UzxgNPlkhvB+wHmuuH9BI
jMu58XozuL4FhRGdg7uwjGfEP1qU4OwE80O67UA8sGNyeKaTUTXpyqLu/FGLiUj8k15NXhGx0aFh
E6DD5XY7/IK+LTxNoBb8Wvzpgly1pmwQLilzAWhklloO2ENvWHxqsHHz4m8pstWs6WAiuV7+Jl4o
x+pLK3GFLPCBYoeIrs3c6aL5fvMIgXVKReWF8UzVTqLf2kUVozVTdTDIBFSdefuckgQrLJGNVkfL
SEDCBrYQymGJ7IBn1X0xNmFOEzvof5WZzH6neDeHCPDgImSXuLy8YgWJVCaYRQKtFzg9smxwUKKr
DsYdE576B6qQyd6509gjHp7WaNghBppwNZ5+LZ7dAWJr+OjeAtivtXHLgaC178BSQeH2ylHzcXWO
Lt75HMMclwXx16Z1nEY/ztgzkkmB+U22dAylVlkkrypSbBVLQ863SVpNma3XnvCEOa+YjykoowYO
/nvTBJiPQR86fgTgxVP1hHHzCLyZfEmvW0SiMHix5J/0wTNTQTF048vBySvGQZhwJAfNojTtJ72R
hcxTmBjj4Corf/uVBE26kkkCKGam6oftUBOn7u0j90QEYDk9hOF/QRB8pcpqmRmfSStnP75cIYrM
ZYEJWMh4bO3G/jNYobC7iUf2kHiRbh5cGsVD33+OpbIRVm2TtJGOlFFSaLSbGDWlRBcbMcg1aw2W
Y5WLTPvhv1KKvF2NpVZJpBpMqZ/CT8kmu1oVUDf5wJlPgfZDuV2v2a9TggQ3ffFb61JtdHeZbHOk
2DU0WzZ/w7qT1girhl2FHPc3yrbGKfv4faJJhpB3IKTLjj7jlptTluntLtvvVF2CH8F21IzdlWYZ
tB5bwb7m78lQPTgOMT+SKlG4J+3zMxYZm4zZso5outUco7fwqyO8siUb2g3Q8nSRNrM6j8M8nh8h
gegc4FYkwiekzK1m9ly0gmOsKS4CJPOdbHpsWjUPFLu08ehnow/Fx0jUxqAb4Gkt/efFQ1zhjCBY
1Tr2h/e0OdggXV0hEVIqngj77S7unmFugnf8P4vv+9c5pDaa2h7wH6Gzq2P6zEcQ99kgmRzLO4g0
6WStBxxyDY9lb5bLmnWjtVAf1umbFIXqbd9/PGQnVRggjJkfE+rzZdvITqXhzl/3HPZqfTYF2GPB
YWsmFke3jz3/na+jsNLe2Kcmv6GX393jMr4bZuSrjv8WGRjp2CWqed+HAliP8aDehWtQO5JgG/h7
tS9W8djyYecJepKkPn8ATOzND7ZD9dTrRHzh9hLMAVSGExc3v7cL1+vuV9f01kr04dIGwlwEp3+0
ikrVXszD3OcAmY8j3uo/Y+sIHdv1TNnlp3zHhIiHyMUNpxCTsDbs5fbXi8QYuSCi5CPpgCYzw6kT
4EQrTj/iPlLefxvitkZo0gkfIXwkzzkyC4nNS75ACLcwazG591MiLO2wbU/XNtmClPDCDR/NnPbD
BQKaFKwJ7xUQQuT48rgD9dc3CG0JnnQAXNkECMFh2cUZqedrn5rMhxiz/OJq8i33SfxM926ou7Qn
6U1AOshp4jGTHW6fIvME/UVTFXEeNS5+2NKM+1imukSR8YzHNLcWG/6FnrTXPDubbEK2cV5bY67p
LoqjkoptKlli2k5t1JuKAWFpcrp8/QWskmW5zJSUtF10r5BgxS0OL94bq4myfQAhoj5D64/f93fy
3rNf8azLPhYHTCn0W7Vef2cDOgc1HrmoBOoNUgtOHgyFD0HM8o4pmTgohpUc1b0lQf9ptpII+lBv
hTFi8sd4/BGQmLSG6dY7nfRgZ/ilMb3kfMzI3/GzMLW/eGUXiz05KcvQXFywI5pjpKy3DMBC4btV
lu+gQkEyop8HLpDg8O4e+oxcbBkdYBD3HHHxULB956EmkCvR6xyfl3sIjU4nBySLd1OVmLtm4MuX
shRNCC7aNYurBRbqm+Zr2ezzxT2UR8XO89Z/9eN21l4qTW1p/uMNom2d2hCVTwO7NbGOVFDZneH2
ElkFPgRIGqiuomSRF9cWdpxClJUjWEvoYjGuAJG2GvyYCCv2p8bd5Oj2Tm5wsHd1oeaT1KT33EzR
afzb2GLXuPQO4Ba6/CrPKGXu0VZLGbp2669YvRYfJGWPD44IK3YDuxZc9WTlcf4S2CSIfCBDhWt/
7/QnhkxtStgVIxJX+xZhrEZmxQ466bkbZmS65fj4ugr20bShGTsTNKCQrb2XBM2BRedfYaNM/fJU
MF3L1qhEIcZBAXu6ODwdvXeOQvWKztz6dNoTwps5Cu1pduFCqL+BtN1wE40UJ1z/ggod+3ZzGd4a
TeIu72cr/knkYxoys8sBTCLFzFQ0W9l+0kv1PjdS8PBWMJEyrHjvrGnaUJXzauN1Dvu5tfwqPKNh
wqTHgHUxvGTjhYYgN3kK8fkyy80Y3cRFDXG9iURfcm7dP+BOBZc3z1d/QR4S+/w+COvk8Vt4eRWl
YJ5hW97U9vvrKzCXPqC8AKdeLBZRS71iraf5IWHzWkTPaoQaW1htfhzeCDrtMmb92pesfgup31Nd
S37y733dk56lD3hr+RQnK4O3T0DhpG15tZQZUcT3A9BckVNY68prwlAK7BomxJrBOHqhwObUPuZz
5moQFB6WhwGoSSA3yfmHKUeewIqOfIumLkCGUU7GWzeEZAApBFU/zYvGKBviMxPR6Q7ixFVN4Wo3
lLSjISi7TRFHhPMnR+Zgu7SkeSt8fSrScXaX/qR1bmfysaABpJckmhS7afSmxT7Ppdg1pKkWgfgD
xe7tX1Q//WEsJVK6ypXyBUrj2T5/ZTvZbsC6HgRwfw9xSsnxSao0Kz+Mb3xZZ4kX8GoK9TuaB8zQ
hmDLpMkRJlnc2/SvyzDkfdISmcHH+bPyW+0Y9Lf2DZn2FC0f1vmIfiSIWY4SKP9MlTZFKOgTzXbu
OqROU7kArSfIeP70kBxf7+j1WAP3LmzpckCoxx3YOSBquMCftkZOmYJKglrsYp6OZzsPkyhvtYGn
9ejqU/+PMhO/J5aIgZI3X3IQRD8YuQDF/yy3HGJXYVmwvRiiI4GVXMTuQ/egy9IXOAU317zB0+PD
LDFc5jvzaawbRszhvH9kkfpfLpPuYCJcp/na8FrX+shcmliE1Dvls0LK+MdhPabntU4LFVCYldir
AaLKAU8xmn2gDcFt2xRW7r+vBiYpw/dN5fGe+1OstwafvzXyvNKPZH7V8ZGQKr9bAqtAlQSVyyyf
Z59/vZG8lHJkwNJdk5pkGyIuZspuYEP6XEAdjW/h25KNRC+wRnplPA/iaYplJAR5rGWiYYAC1vf/
ew+D8zokAvqTRMwi8GSLWY/2uaTAj5ke1OWp/TGtrbuOQ5cMuwq9ptkpaRthkapO7/BFlnc+IMnV
Dg22O+EqqKzL6M5tl80/hc63PUY5T7jOYaoB+Ipjy5R7twmUdbEfAnN2iJA/0Br6bNo1/Jhkntm9
6pQuopUYITykxiymSIAYStvYNjS1/ID/dSki6AITAeS/OvRzFr46TFNBqxFpr7NDDgARUwV4UBUs
Lodjqr2vzmdGXtexaIBu355+t2Q+Jm3HvBr5OzYr9Q/LmN6cuvjWrwCXmvIT6Fjc/bmlgWtq1ECO
UuHkUKEgYjUSzJbO/MT90xc9hFRFLTb8JOlQSpQ1TOlPfVWEXMq4TMtePE7295hw4VwIq2QvoRdh
j3xf351VpPCfatOivxKORTOVLdwevpnNBkU+Ade3je9E+H/kUMl6R5guwtctXTRZlVFrNy7mZ5hV
ijzOlVa8beR2QTXRx66oAgGIvr3TArXAcax8LQQn/2dxCnYqTc2J2AcmVUEvLf2xfr1oV0PnYx8E
dlgaCxJFR1A0rK9Rq2v+xv8u1psMktuor5OJnKHMTvuyblaeIrCnf6dESKOlhYIY/lAH1+NeHGzW
QWG7I/XyjFa6DkslfJ6oICqkBqFnN7H6e5HS28dC3dZEIxefWmh2DWBhOIfX2UlYeCKGboaqHoqb
6iMRu28G6wnzc1OeWd2ogQhveOFjsr0BaHZnT9qV5Q47+4hCmdC58Z1zCtH6kDynPIP9O9aSRMhA
MqwkxelAWu9sICcAHV7mtXDAeSNTHg1Z20jCoUOTAO+L2GISEaoNdZ40g8Z+pIft8i2+oLn1v5HV
1fi4pBehb+47MbA2QUJNaL6sSyB9I1PR6pehV0/OX5sdA7obnjqD8rBk6GCEtw7erjF2yGYDaIpS
leEhVXJPdnM/J+MpP38T5wDh8itiyU4iEYLT8HSPY9VBWjLhIpv5XstOp3+f5C9vQumtm61P2EbT
o5PbTRmYw7kWzhlbj/J29yjffqgQ/MqoEmSSBbNf8GMEvC/B6EVnW0kjlPriaq2Nz6R8+91IdjpB
1ZQAvkhplRE3USPhDlF2CTfE1YP5rMeAZBzfg2q19svzgjq3DkceT4FwJ9nIs+AEnJB2E4Iy5bEA
tcdRvtyq/EeRx6H2+Wu6n8elntsg/AowV07TS63dnaBu6COtIVm9jmFJREhp0xigCPa17sF0S9cB
XwyOpyh1LnbDM9iCRqK6J2UJfTUD7kD1fVJIym3yKMUSqDGx9MfsO+cuyWS0RVCf2D0pTQEFHQxC
JqFB0Z4cSDYvY0GRT9CcHPfwbO8WbkBx1zRYdH4Rvm59uxBOyj4KQnr0BwsSQqViLCOmDO0bY20g
e9+bajH+/yIQtxjy3t2CYg/D4C5kbE7kHd9eifTRUpZ/DjcLh7NQtjvqjWbAkGHis+uBP6pd9ibt
MKJhjpzbBido4Q7zy88SopHECL6Ef3pkyGgj/6LPahDW41Jmh4orCesOEJUbgWqi49U8TPSI38iG
xt3hAIjlIugmqxdJRuJCeoY+WStp5dToxXdbOtE8PRu2hsEwf7VXOlgDA+nHhZJLr9Haa3x3DSBb
fMBxvdd3RrGXP0GRC5/psW12gIlggSpj1kK7hEnGc0hakbR/M+3sCY1OSJ5tcRvz3QTfv+ijfGoi
vRnc6zmeV6aXhIMCKjJuA8FUVsCKvWs7YnWUBP6mGRXLeX5k8eLA2Mf8C0+3l838qVise30eRfPK
ttUACo+vGOiBUXI6HPEYyOVA7lXZGLVLgbCSL+MdII0XpI2ikxfiWGvzF+DbYtkAUhvGMgQV+EsW
EbkgiLhNzbOtmB9dHr3DngoZBAWyFkKi321NikkNKLuYASsHmmUlhvPP62mrtXny4dGLpYJR15lv
kdXgts26p8cqqqatKCQWOR/NgOLYRtwI9qL2IrY+xuWwxY3d7kxDRQXWCl8EB6nH6QaETC+HnRfe
780d6R5pv4vBK5KN5JSCcn+mOrRgz1uzgL1RMZkQAiBPKyNf/kPE/FGGeI2WScKTNjg4BH9YTHYH
D7hSuM8/r1lXOwIYJxdTJKSl35/HcwAvjId6FKLlqJl5nNmbMSBdYi/maefOlaChVeudiAyAYfbH
89fdfXlxeBUUr11nJlibBrla9G8kNdXeUCpxcKxHkSxtEV83Bd36ObRE/CVhtvg5we29zmOXLDG7
oR49i6UU8yLimiHfnyR+4aMPGvUDHIShaBCmgpRR6txFt2pBuORCLUV+fzEGZjOK0YKHcOkSlYun
nov6YrwOQC2GjQ+uFrLCsXEjrDnmk1gfqthFttOEVlFiq/zfNSLqtEsf7tlDSUu7BRgjoENsRk7X
zmcqZ/SiHRX0T98jfaH8UWTut8M+y4F6LAjfaEAuxGR9xAm8WaMDzH4GgGK3WEBuLYf80MGJ7v3k
dlBZgi3GSFnGLUKaoLf9zX6nNg6JJ4uGklxnEfzssXsUiF/Gtisw9/V5w9ZjLo4vlq/qtSJh1y+9
tOCFlK8VWbmagXUWL6wb+qa1crQZXEwVDykhg6JL9kCDJxAd1PYZNnZxgSjFYAKBDY+19TQFx3cy
cMJcRrcZp03Sk2X9lhI3cOYCMn1RFdQlH0NgrfDZ3TK1fxLbVOggKFhSi3xPJx2nHAwPMSzNC2Em
7Q8C/hNadbPOQhIj8krvMCzCUPtIrQZI7whJHUYQV0FitrMoQvSOUu3Q68JICb9lo/m4W91hTVCT
VHxIgCOTKDmtAE/oCOGambK/FRDzbQPxCIbexgPjx+TZxaglDcZmtYR9OkIkYwhcOS/9UpmHnS6b
svbNBadyXCns0B/sSi12mL/34fWhLnEIL7zb50lSTVrypfQ7AsKtOagWdNXKg0foZp/wNUNR+uIS
xhbFnhmYg+U8eSk5WtDrTIHGuSvmX2AR3U8oJSD5ng9HqF6KdG0euEloM4sRQmT5L7UscAkiUYr2
vA4CqTCvYt3nioBjK+D4eIaTNDuT9LWSSSi4/6U7nVns1h3HgxAY4j1pbfcdHUYiJ1tQUM+vnS0M
Ux0hWrQu/kGMzCZgSI1TGMCivcRgy2Sn5PQxV5P50S9LuMw0+ncZWZpg++XpmkfhXya7Bttja/uy
rKj6EN46SR3dK+8+gY7Im5p3UrNpc+soqZh72YJhCRS+b4EE9aCR4Dr8roAqgmwj0eRgM1PESkFu
y6tWzn3STYoJWdxAgRe1dLCEpxfvNG4UqUw++TvwKUmT5UZaz/s/r6IfUl+65ymHmWoRrXivihrS
iIoRuKlQg1rKRnb2WzVL70jz04mIXgnswaTl5wdkp0ZdQeLdkzQyrB6R40UfMXHw/htRNEedjXYp
G6ecxFNYNKwHqNWr2UWHY05vtCYzSkdVQLirjlWm05oAOv5kUaeAwxEgAkiplzbbmtHaX+MR5pfR
/NSpToCisaaRt+xelUHCs57qda9MGJIR1P+Qp3/IHCkS2FoX5jjlnbb+k5C4IEZtEqA0Wn4gDvzg
X/ttqYKqYuswn4jxyWK3VVPpBnr1dRTdptwlcErlhVQKgmM5z244bKg+NpVqp6uqEiRsTX8iE/yH
a0JMnLIZUNoZNBR9urvPFfmvymSmaZ/dY4UDiBhygBQ7HXb/JLCsEf0cB9DxBA7kOWTWRbVBM00H
5NrXj3x7LDiMeBVdXpPgbIuDyOy54Qf1GweKSJxdEDLplCreRnTuBmRS0oGgf7PDrdXaBSM2A53s
s3vf9TUglsT6PXpA8gcaenttcmmqrDplODectjkD0rwSa7edESb0mnoh0cEyMSYjAXGPpFIrtybL
RspeIKLSZtopCrEge8MMyr3PgWiL3Zn/g+JHVwBc5r3Py95opHhBakI4nusK4EIiLtAxXUcoxmt6
AMP/XCpsGoOgo+YPno5KF9IhLX7/PTpqZdmJzXeUTMIokl1j/ToYiQ+ak29rUwiLuSu92YIusud8
Xt1hj18/qibu6zwrbLy0LCvWS3nuO8qKbeKx+7bUpOw/iBvjg8huQut/hLXjagKir9+FxX7yEslS
8gHNhTOqCHXTf9VzULjKgyYa9XZ3w1Wj7UZTVoLejscA6FlTuPfG2mCoa/w/PwZSMMoikZ2Fclk6
MmlJLXEXUmJjI7e0bg6tWefbPh45nhnRu7mOz2bS5U3aHm/CcoxV7euu0ci/jEbo+pT9Zn/UApoC
84sx8IWBF4nMRd0oApqDPrD+pnW8SSeLx01MnPBS5ILfNWP3BuYzBEvtv+cKJsueMC3PhM8hVa1U
skAhqPFi0J81wvLawkST/o/88zPde+RPnfIYUppdZDJ3SCz9ciOEX9N7Q7drSEbi3vDqyN/PYEMT
nmfLuijIvJfBrO8grcE6voTTot39ih3+cs059xskZLP7IFSeP8qJ8Wgxh9wx4TxkwYhdAKIwm5jW
mJiiKxp8FRPG3k0xir6dMFpxOEnRMXrT2w1h3n7WW9FMHgL4aGk8+m0+7VRei5sz5BKMZDZgltGF
/oBWRd1+Iz0CS4izkyIUOLyiW8RSVdQ3aa9fk2eGT0qAlbPQTcGNYnJPFNa2jqieSMIg2M/7qQiB
9u7zjpyXL29h7stOXMogkIENte9ZJH/P0kSz+JKuSCxJE5ayNxVNsMztXgKZPRgOmcv1uq1ymYXC
e7ICg7RqaW0d9Kh6xSQPLinyBIZXlw4KJMtMuQGvyWJL7U8HvntK9R0I0hj6TcAaFhlRbFPgqJnY
iuRd1kei1UU6VLieRglnkGPstqZoCDLCSPq/KKLzpBcBwr/38Uy9isB8advBvZw0Be1IgpyNncJ9
JkSz8UpM149/ntuX6n8sExWaFAjLYt6xz70Dq91wbhQO7uJKnQyO+83OsMLFujKK93VxY2iFzw9K
29S6hjgAKUfCNFkTzUrrA8iEMPH6Z2zk3bVBHifBX12g+U61SKpjRi4djDqXuovLgGgDq/hcPK4/
McPxJfkR52vFcqYIhSlTQ6EtD3HLhsFY0way5hEi0cs26esVNkE2Qfh9ncNDqehyInYRKHh52t3G
D5jjKAQdDwStxYDY8ENjgCjkh/bJ41Q9pmssFhWMECBK95FOumpAsTkm99BjNTikWuyvVvveesH2
Lh8qZrKBGKE5ncd5Mbc1Cl0vv3B1HTHXuUEqI/ujDIkXAeDhfYSu99XYUbEWylwWZu3NG6RjKydp
jo+YIqR62xoSPu2ONpkpEw65WswemLQRTI+8sMXccqWwH0DZG+gSj5UkzaaL1PrElHJtJ8Iei/yG
XhbAHdDm5Nt+oUBkhuBI9eDl+O3XD/d3Bs0i4SIbg3aaAlLdrvuaxbUOp/cmGjiRZWcbAt3T03rq
FknkmN+vnrvFWXpHlTDg/pl+a20C6tzlpGP3XwMDF3XYaPeSPfGAZ4pbrEQrjj/NRIebisUW2Dsu
QIjAIhD7/zpABNGEBIjECuYGiWvQDF2CdHjuM2cE+wBJAEd4XHIqAeHM/+N6IKoN7NStXMh12lcZ
i8Ta7ScJoM2ZnH3zh6YOlZrcZx68T/AJKmjU5GIZHw43XaL2Yo5wUxFogG5UeLNngJcfjWoJ0AX/
JO6wYdsYiQBR1o2gz+Ik8nXSn6kDLaKzqJcLTpjkUVo/DO1CPnLsZhGAikkwL4QwlD3GWjacEBDs
j/8cgUi2LQVkfAHxL+qaN+cVoz+rGKEa+D5d1FxDVuHfpT91POBNTdK+IsJ2awJT0TGAN4Ht4WVM
BDYmqLaENd0yI1Y6MIEb0L5aff/1a4kfbL7QXZXe3xOIJ8/OroNlGpu8uewvkcy9oj5x8IxlPi28
bGTYxPYalCi4HzUmNgfTS+Z7obRzPg8lGdrxUbL1+Xr2GhdROesxm7KfCFJuWwO9k79Pb1AkFSJK
x0HfjQ8ycAh7QvRAXkhNm6NlsYy+y661Zi1/8J6Wuru0wlVHpTshk9W5Ti0lOmQrzUW4oaldoQlR
TPHOurIHx91N3yUhlrVEnmHZMsgqLQ2QNQeIwlrskvRnNQ32xk89gKTyVS5basn5c6KueeyJcuAl
ow1YRl15YnuIy4zzLJgfegowPkJYiBvH2IcUnDtx+yWeJZH/Cqv7tMwstRKUoP2JoBWSkhjp+Wrj
57Ej2zm3k5bmJ9bVn26VtVdjyYTpWlMjbLC5B317l1SfERRIFAvlwW/gSTzKg7cxbOlp6lFuMSI4
acYOKxL++LSHZRVM86bmz5dId7Q4D7/4lJq0o7WWtTHUlwK+c0unUPVWS/SXd9Jw0lBmby9ooN8d
2ChOjX8Flb6STxGlT5V7/NGgAG0KqZrZwebto7ZF40ypmftyXAmxJMsFv6HP4l6Eyzhbu/lJbYZt
0Igez9JC3z2wZXR3z2cT5XmDTZj1voEvDrHmb3daNWbAYLPzTFkT4CvDKK1+Vdq1UxiJiW7KYjYO
f0bz6xCb5AjiFdzNdCrtFUNF9Rk4H+fEfxI6SUUYfyO/jxG9Z0nJqjssEsv3JauqWce5PFK4k3fO
9t3FWk3SHOKaotGNirRdtGAPql9UXnyGpAEDxG7GSKw2DuhmzvFpQVEYbL7VLH5cW+6oRkfNJDID
y96mJwqfp9VShgi09pE0Pk7T+OalzJeMtQiyzqGs87WHxzFSmVaCVTc6LkATpA80DN9/36KD9qdm
4QDMTZX1VGiYUj8tvKnNnhwTWGAwwBcIdX8wpwbTqIocSXdjDgRhKh3uNwxXvhWI8k1w/GpdLKh0
260bXMHbonFUh674B7R00RM2HTlRiobjKYAyeOdaa40uAqnbbnRHRA7w4rDBmoj3jjT2gvfWAzQi
CXm5NMwBfcC4LboebqCBxOpp5Khp6q43Y+u/5RJUm6+pEAeXPSW30Fj/9L8E8KertV75VdM23IfZ
m66gHc0w9uPKDfxkK2WXTFBhynJEso9Y3rEjKjuyyfdoLqBLVNHOPMPzqDB7n75xPWBqXai459aJ
/pdjyJ3Hs5kaqW0cT6ejWtP/BdwNjuZU+7IXnDzIfijziCUE405bAcwybXxC8lOnYd/u2w16VNof
D0j09CBzNXlMNXgXTC/ntJgGzNoPR1s3jQZVvZ3kdk04qPUb1QQoeyD0L4cA1uwJ4SvTH9zPdabV
nqtTZ1jZLUP8PCYuxc/y+6Ajdy28x5d6g0b1EDBWWXgvcc41SMkg2/gN5/crGU9sHlmWPyOTSd75
SJzJhR8xpolJwp8mdhtZhZs70sHFHC50HOhPrZ9vHWxNQmRe8BJc6lLUao162qfqmrdzgyZU76PC
A75/3pgyPlJGn/oC7WjKfvypuinArnPcixCsaoqvvJI/53cyVXm8X7CJb8ELB5BQ4u8Tto3TFHm3
MiZ+4W/K1YQFTE/3AjAexLeZJVLdbxCNVumAeaBHSHB65dZ7w65OL8/4DfooDi4MTuPyVgE8PxCb
MsqYWHsT5Tr0SVRHutb7JGhdenjzr4kzGENZHVHJ1c3OeP5OEwzmTCRMppN0n4H9ALKpINStDHzx
RWMzeeRLckigi7ht0KtCicUzKFZMx1Thc6+ZfvjqNI6obilPpxS0lYykoi9KYytjk/xK0Bj/gNE2
35HitjmcOJ9IOSQz1FTq1ETkrNYOdFl635zG7jBDv1vobprTdA4jGv5bVl/bHhxpv7sDeT6EXgCD
C3/p/pNYNzgU19atNxHFWjlFsY/EOdrXu8H0aTqwwrE7Od+FmxTzHCyVkWwMn6vNob5brnkiuKxg
dyCMYO81fFmUGvl3zH5DAKPqcQ7yBwx18ohCeKPENcTMz4nRR+ePnU4NxVNp0JGJst5p8/zb0rdK
xHZ7No5q46CQ5RaPh8tRahS0zk/T+dAv3s76KnXB6rElt4n01jUFRL/ydR6Za74ZH2TLte1RNEFa
N26UJrYBwNetUSrM4w46rtORA0jxQpRNXujTGlKkltKSn8IxCWuh41taDti9w1WyJvKcVm/DllbY
rB0H7U2my6OoOUy3Eby2rdbONJ3AWf5F6AjdZZaMVLeuQLKvWIEWr1uxIdqaV2IRehBV4qFZmjze
4HjP9HhsSCfvfRIXk7YNoF2j1sWeo0+F41UWvL2ioEN6CytdQm0oLtdPNKO9KfixIhFlJvADrtCN
pt1KjMfflrj6gnSebOTEAmQtWNP+tPnvnY5L6mWrm7JF3Uv6qWk7SgzkMQiOf0DKnLMyHRMBoZO1
gkIMq5sYBdDjXAjxS7oh4ZFEKkqhPvOWDvR2bjz2i732n+n4h+LBGUL48It0pP0Kzjp031jBZ+6V
pvE3Qd0HLu8pqGMYYvxKaZ7/Y8nSbXAYv4U2F0YIvvO8yZ7KcC6f4VEPfO7VM2cS58Vekj6s4UCg
TfJzXyMdgvy9cYz43BKLg26AjP/qAmGtkFFT73JI2HoFrqaG3TsiNzNaitkX2dmK/NhiesY006sw
JV4M7L/jMH1/VjBy2tPHomqcXgqRNPKDHlaEx4IJVl1pB5HOrM4H6rmPKpX9QEFidh3p72dMaYmV
as273SnSYilg3I9roHx2M/tafv20BC4doZIuDlmL2G4CK/kuX5YbRgwLXlFTiAfWnwI9pdgQ0gFp
7/Y5rHOfaFse1pigoP8JVDNBP3i7avWviJrqnQAHFbtHcfqt0eNR6r0zCoCF0te35J1MEWI3jpdt
k5IozRKGPuHi8m43Dpure1XvMwB6KQkrwD6M3DQWb6ZsgqeqeYhAirgeg+1zElHExFZwuyZ69/t4
vWfSCdIMBo5Ipd4O+eDq8ShBuZkppl1hb3V5wMpLMMAYeDkEz/vWumU371DntD/iXRfwRT6QLKn+
HNvD2ycAxXBu4ODm+AUmYu78QSjmkDqREhuzKdluXXvfXByiNjqoovAuh9WAk8iV/QKEZt8i9W4z
usexJ42Up4YyhnmUzAbIZkFW/S0646YqwYstgo3HznpDQg79hH6Gzju4AmlPfnLwHILANSwyz1fr
LhZV4jYI9/10IN0WMYEe49KZQOCuE+sW0N+Cn7oqfaCp72YZEq7dj0EDTn95KgOt1sNGxeQCjEoD
7q6WVJn3rOmqQtNWdZyVKDTh0LMos5z/lPVxO2p4oFCvSrRlSDs9ZML/4P0PWkjH17ZtglVHzwCJ
HZUXFfeFDcr4G4wEVrR2o3+nGlU1vF/OsYRsyYZPlFiym9+pZr55rtQDz3lhaR03o7V+CZjWC+KT
rxzrVdoQ/RIexnb49d8oQifDvZ2WppYasAL3dBC5dTwOVONBWThKBs6T/f8zF4Lzi40EcZZDspsy
ePClB4m7nTIk8xiYmTOopY/DC6Rzfn3Dw8WTUDv2+X6oeTHajjyPR7QAjoDzGk6PY+xm7fWxqQqg
SU737pHcckM7ZC1nKjdZmjiAtMg78WhZIzDYUi/qXGG6n9Clyc4q74BQ0YEueb9lh57XmvdoTIZw
DrpqBXv5rALHS48gwZZznfVq26/xxWZQql9Z4vtAreWwAuBhzn3Lk7f90jvwkZpsCE2jeljN+iqy
JMsoXkCBpAxfs06qZr+O0O4rADgc0Yp5UnGfXaR3WCA7kMkeXNw3egfhKVymY6aLzXMjvh0jvn1p
hHPaQfMS606TORQSyIZQNi1UZ9+cjAjdUDUjG2tI5wCyclb/X85XhPSP2kwg3uorxBEVJfcMgPfs
VhZ768l2muaKbZQDc7tkD8EpilrFlOqcLSu/yZjshYWIt1iqYrZy5bhgCidpxSNsPB3CnMKmyi5A
nTyg2ZC/h3Rbbm7DX1x3zNMWDMTen8eXXQfjL++F2YmAOlB+jYTWPWbzpBppDd1OeWMd/2ZoAJpr
KvQW0TbYHalIICO+4C/lFpH8m+9pKFKTaPeWg5W4rudrRlRajX88GlB/IhVAFUicnbrP2ZK46b7X
46zESU25gMmf4GjPuZBX2bHSTuVeVR5w5t58De+V1hLUwUPy2G3yI2j1Nnd2w0DGt2LhVgu4Ib1I
XNtvKHIP95Q7K8GZB1MGVH/30T+ZJdKK1soIC/i/8Qu+CX37IGW4sc1MZpDuxGqjwxHsx7MmZ32T
Nz+LGf9CF2oOIhGl8YigsSwSUKiWpAoQUl62ulY617BcqzeysVm+jCUmGb2Ik6JFqVqzzG8n+AnG
wXxhVG53W3uQPy4HVfRKWKh0Vi8y8RHCvDK8oKaGpntXifhSwXxApbvO3Iw9XwcFO9vqcKPZiu7w
e+HVfrx54wo8LufMJSuaGVBcVyUVYGLvrDsxa3wzA4vcU0y8sObtWJKKyAEKudv6j0wt+QNqTmvk
jOVMUBeICgvqpDbUcqDFHDvID918fnVeUTOmHmXxcnA3vXzhMBmDqwbwqJEao/HtOKTjcmJ9xcje
6awytEMR7Ke5bdCSCq43+1NVk93rZdXeWL47aFRfhwT2SX1xdsxL2NeYqyKJucNcLrImI3NOW35H
dxvXT74jprAx/Rzj0CZ5v3eK2B8l9J1eJviJlFtMuzwhh8iqLi/y2cGO30BWT3vhFOKrFZAKImxG
laXkB9C6c54iYZlEBOZCZAOG/QPH9sBgr0veSAyBulVBF8Cz2+KkE/7ulsXyhowF33a5G93sM1C8
uUZZbzxMXjjMuUHXk7RVa195eIrz07oc52TiHDT9wHL+SQphVaYKvg47mBZDF1/95QBfq+uVKTr9
amFg9g7sxK3lKWxMXrGNZ846U3lABLzaZPIHdwii7d0xzow9zpx7mUzI0M0IUfn6duJqx7tqGbDd
X8vfAkjkzL8GSyfIhOY/SUsLWszB0kfukrXaJzC3Q8fK8vRrh7O+Wj3D4ENDpoeICfQ8fZdP7/dD
Dzr4R7iiJcQqPvqa06u4xga2o8gvEyRcS7T8aFEU6CQJ3FH2GNJAKl8As/uTpP+KQLsUj2MVgDgz
fUw1YXt8mxwyTqjNdeE2pH2MDiW+pJQ0bBPH0T9nHLy2xjlV9j4ReYHkiDzzHo63JnTbmxOYI5gB
KIVzFE8XIjnGJCmz8HwFdq6+BBfdTQijMKY51ple6OPvxEgloCZW+JiYroJq/w8QRQcjePQM4SVq
UtsLo4rgYgE7N8fJI+YIXUdTif6nuFlwZEfdcH1i1XYjuw22dKLPzX/XDlKrEYjajD7tKos+HdfK
rn8YMpWu8gyW9Nx7w6ilZ1jTp0w7IB8jHMkHaJNr+zGn13qWXv/i3mZrdUY68hi3vrAfCy4VvKmp
GDgDikd+tWONOlQROmQ7L8Ke4gbhtpHFj+/WCz3cGc1S57FDsWeeh1I5WMqE4SNIukplc5D1Qo83
6A86SvpNOn+gav16q7W3KFLoNQspLESrYRh9PT55CY64MU9tk9DibDmvk8AStu4FASwHGJlf8acK
IP2hlBt/lFT3W8sz0n5tuhbNKqmfewiBS8U0OfxQM8QWzczXbbVoERzV7tgGHJ3CLEWEqQCmQeUP
I0ZoyyG6G8Cvwni8dcWUChakvLh+csu045omLZa+lJTb+dt52QrOQX+WQUVb3pV8ZYzQpfcu0ohi
acpQwlCHf6dRjSwY91/QNQDQTZiAq55PuZZCC2ls2y2vU3hRnTeugY5R3dYX21g+qXJvU/eVb9pL
cYXVw+LlqYgC6kVmuOCTD2uUg9z5+H5R+1EQ0JO09WHBWgXHN+6xGrwGasR5hCvPhlVG3Pb6tarp
IM6TMQtrjuDcu5p+iFPd3jUIyfMO0JBp3tsoI4yQKv6bxQk1h8oyyoUr0YX9A4+vf0yYvJcpLy0d
lA6cNYLRElKIWAe4Hdl5pmHLfeww7pk5bZs8nLGzIBErOrUSjTdMrI6fh1WdtTT9JZ2uG6m3E97U
13tVnzcU87PEADXtLKZp/SOiZvCCkagzO0plyl4H98TqceS9sta/9jNAZuasAwwyeacFVD7qDIMr
FZfYqrk2pIvpwbm8+A9XxNXZYS4O8puGXpQWNwJYPKffnMbF6yVatWlMSiWpoqhGED7nOi0zG/Iq
YTbP1IhjzaGeDUSx4cBUu/diJUnR6tTC2gqwOpDe5aqyMS/701zlR3/oBpudaXtQ70C4nFl7BS50
Y63ly2oL5khW9TifuBtcbhOZbuOKcfqJYLFxJvACFeA0PHLs9GKPt3E5dHocgMG2gOyN8/AJmbwX
lWopdegCH8WQu7mbRvgveeKD8kNyqtyY5AfLClwVH8duFJE5NkkPEIpDdZhlzgqvk60nwr9wuJx4
Yi4+cGC8w2bDyqL/U2zBQadEsymVqBDq0RtPfBNHHQ2H9mQBeHzUVWv3yg2fpeiNK1ZTlfiJrt+x
HcFTnXpz6le+vIhxs96ckuxp2SBMqJZFF/9SKfxza9NpV6wxGvsgrJvZ74EOd3rFbnFilRvbtcjn
wXbILHt8a1HbasjY37EFFR3i/ckkHqyKkDu3J8MP7Wu0nus0WLCcQdtY4Ov4L6owPIw5ZlekUbCx
VQLRQ8vs1fvbwet8j34l5V/s0QY1VevJsowb1WS5KGM+b16RZcgXIxWZOPrGcOVJJmY6GLSsYVHs
rZ336xneBXy5kXlFzl6ELO3oqKCqFRLMVLAk4jZIk5sdq+t/qf0xSoZCiQ5h9GUj57XKeC3v/NoC
WfmX843Dft4JyP+78z8J8QaIIeN08M1GK0qbR3P8qxnIycnvUnMmmWXruYZGof2shZq+CM/bC0zs
dY5gEy3JPCWK2v8AV8Amvona3U9T02buwTT2dUfqRNPiyjw/fbaCVfBEBD6K8u9nMAQlCpdb1gof
WOnTCZVFj+hmrnPxVqCjHrms8R8vqYj9OeyoQvvK+W9He1zCQdNFMEOxO8CYat6gh1YL+paqD2L7
UeANRx1t9g9BsGPk2UpPNkM+DUKkulbQPoBJDuXtEzwDdNC3yI9rcLdVUJiexquk4Tc50g2prfh9
meoE9TUR9m5ec0r5gU+fabyxdejDJ0Jko4EsGjJ26czQhhyiy+sHt28RwcT9Jq9HXxCQklE0nIaX
lSUhbTnDaM4omeB5z5axLZkYWUOvc5Z8G2OeBM79sQwxKqFi/7XgrOn6GdtKtQlLBpNiSnaHzcSA
odZ5DCMW9neUGJAnicBI4d7Huo0UkSAWckXCLLmrGHndMGK9UqUKYrxRiB6rH7mKc9Gl0QDw5Rf8
L7TToSt0rdle8aiYK59DMxUVGC6HQTPXHiWn5KjRua+4F8P303QZg/sURXX8jOSiFryVISS56q0k
Vii7NEBPmpf9xUY+FAh4ie77Pi4dcbDPm/ArWnfUxXc7EQdTusXOMB32+EXvBml87pmBnl4C7U0T
4rU6VsOkeJ0Hlkm7/sy5ZUE3i9j/DM1lWGUF2Z5Kay6tRbcw448szkew3XTt+cPO8mLrDlMR/QcC
or7ovNv0QqB38FzaHdxe1sKWNwu5lmAPfZP7soPIgNNjkICBkaMhFs9n+dpKVz99VzUcLvPKjr/e
u+yOYKH9khbtHi3lAUaZUlI6JEZOO1fKci9gbmzoPdEhJmVakuQtDHXbk46iI/RHUTw0kYhGNzQi
sXx5b6taJHkcF6iOeWWaKrpwa8EomqP+JvVCzzcxFHzhEV7/M4AniXjG6ul7o5LtOeZMAXokgaqx
a5P9rbMcuRaRT/5PHMBH/n0woS9+mnyV9n7HK/dL+ezSnTzZfdiqxBWGR1wrP9efAauZJoFW6fb0
0l9N8mN07Ue4c4JeGRcbWI9hA5/Mpq0vUWHmihxs9MzjHjRtNstehJ547OSMHsTNjqn6HPljPKct
7lz5El90eLpQFGiN2uBwATJE2iZGoj6IORwnDsHeEjX4PkjQzZM8jrkkpxsfahROiK6odaAiu/o+
P6dJYKe13d3KDjT1mAQyjIyy6049ITQMU4bvqvHlh7Pzbyh/zJIACl3aXkFO1ZXfcV5dsyKCY4Oj
nMRCUEnhL/LSbdzm1bkhjOR8qDnpJo90Kb3RjMrSnLJi8YwdIOzegdSmxiOQvj/l8OgRW0fIB1sq
R46S5J8RHCOCLVEQ5d4RvDQMv6177g65YM8awc58Rkq+gejqTZ1ovKZh85DXJGqO/kqqpYWZ9Vfe
kBSum4SqMMUVqvdzuH8e54J2B1m97NDmyiZoDt3V8/QLYOFn1KgnLuzGhW32DZd6Rny1//QYNCIc
noroSHYF0hCDndA7AvjPbJTMDQjXbx/9GCtjBff17ElIj/uKG3094hQmeqQo3Pfyroz76QljjdtC
DqSFTS0i6F8k/t7e71cOhoFl+Hb9XtQ9bb+hs4LuKB1op/2ohqFr1oXPsNO6jfvCHsDMJGCgCp+x
GUIDSEDKZlcnqaaHPhuoEYAnJqPtkNKHbz16tts0WJxNBU85jkiCN7JEBzN7BfC4okgqj0lwevvj
myV/+dVexkF3YQj1MDJ14QqVXJ+WlOrxepQl9oH5fMPlK1caaD/pMi6bDT1NLJ0z9sWzyf2bZXyA
AMPQZRgBQMg3faTD+XEXRtVAXHNhg/o/MI18ew9foAwJW1y/szrcp7YDvO9GsBk0dYb1D9LumIcP
soGlPyYU0B19RYqIUjC6ew1qihaw6Pfr1/IWbP07uti+atjzQUcHww6RZy0rbaI3IBRlpT6UTKLc
VR/4utAeB8A702xr9f8WBdN0HS1WKY3yWOS4hi0rfHGRjS4Vzbl/dfd3y3jl+vTSMLkToa27N3dc
4IO5IfVz6YZfeifubsY/7X74rFw+sHHSyAVLRHnlwDuqe86LHD5Zw+IfiWC+91eNs0vKLYYIr9cM
S/7Jc5WNFiYQAit48NhuIhgmI55W2vcFqALL8C2VRqJ6sWrhuqwH6hUzECzUQvstlZumkmJ+4NAp
VrlVs28q+mW4X/6SUkoih6FOYFgctIgeE+cg/HONTpB+xhDccGppeMnmibb6kzmUDJShD3OyvCeO
GaExH4f8/sMLI87jkMSJ7CJAMfB43gNQ3hUV6FtQKMTVTF/otS505IpScf9jb5hTTH+duAdh6bAU
jutmugjuPzMrF7h6DE+NW2G6tjOVxXYxKYObqA91XiiBzmH6oR3bjS3h3ikjftwNPcVD9JAVkhdB
JU5QkbGc+JIPDE0KazlCr9SDO2Yf6znhTTQd034UFYRFDQl89HKQ3soxYPhvJPRroWwNQltrak88
dDxVhGBvzgHpNPb4e/0y+pcByJ3lv/jviuu9VuCRXrp6uKwLIZ6DuCf08XiGse50Rz0fIFR7EQd9
1Q38CexdE6e6hOFJHzw3nsmVoFJbnR2vSYFV15DYjv+/2lj+uM77xYq4+8q3MsBcxd2c95Y9Mw6N
idl4TdRHdLz3hLRP5pwin1xNbvPFLVc/vCObg1/DxnIXATziYFeFSEHqa9dn/4oYZj62mIeFuU29
oJHB3yZ+8aFVixvpsqOVKhy2BBE201DLUfNVhufD01LeVInr4apn/2Fia4HTdfWiTLmjcEH0hnGJ
OqLFw/Ra6u1l8Zvxqu+fKcwoCDouOQxCwcCjR7V3QVq4kePo99eL4ktSTjLlAFWm6/vV9djCoaqV
aaBwq8eX2jvdbersns/PvsFxqBAt+G01AQQhDe2JhHNP9w69N5KST/xrq26Qsgd0hO/lRL2dpLt6
trPSJgnIAF238RrK8r8EhjEtozxjq76bOHgy1yijH0qfapDeuB7SHXVgmOyxOuCZ4DEo/JqG23UM
JOSCfVex+YLLaRE+pfOmo5FpuNerquHYgH0tUF5jruKfLV0RfiF0tO9x0kshR1palDekktx2urze
g9Iap1ZiSjfS3rhV6XlbJEI1pcRpPjqzOf+8uMreXARKgm9t8Z4skvHnYJiDQmL/d63drZuMV/0g
BYuPdBBEW4qAtK/WhCmexXhaz0p2h4oA/RpOo5N2S49utxPw71dXbqm4R9BLBMAN17Ah+FwZ46+c
gK6+u8kNJBT1kVpJmaPsXZS/Taup4y3zTBG88T3lvDc/8rlZI/EWuGOQ2+X3c+xfZglsFhFPnUIi
/dJYDebsUDVQxRVhV7ZGjyCE5IasadpEJkaGnyuSROFUJPjGytKDa5arCfz+KmJA4mHKoJRDVtk5
dYEgT+BG31vvsYclTfOVC3RnrHil/dnA/ZTl6jHHIxO3I5sWnwnxIpDYXoYynW2sz6AWIaJVgP2E
gsxBs1hoBXYhxYwxIZRYJK06ICscBIRrGPXGxN45q8/vc7vJpNfV0XAayj4ci+CyAz2GWonGUD+3
gij6d7YAxzCKbgT3ThPdcvZllEHFla57gTfUCSqblaPISxSUcXcQVqq2oNLMgcLFx705D4DAiELL
W54JK/wBY3rMjedY88A1FudtMCjtxT+JKjuS16Lvc0g46b76GisGpCTBH50Z6RBZsNSTJDEKQfVc
BYnhTmTsr8D920q1b0IDa6p8OZT1km+bWXy6AwwDSP8ssQ55hz6+baGu0mPfbgtkoTuQi1Z3tWYF
2ZsZy3ykgMKnKTW2dtOHVDfy9tofCWbKwKtqhhq2jUyWlhbSM444ZFSjOHF0sPbb70sHOti3QnMG
DG0zEdRqCUj10CV5L/3h54O/iUi7rgGtsMIZwbNhBUakDzdEFzeAW0Bj/Z87DaQ5EZWMRcWPAVZf
AMSX9EWY5mxxkZrsA6Jg1rovfo1b02SzI+BZUH/ShnuKIoOVb8NUwphuPXU1kNiV9XmOKbmjwdkL
9GUKOxJFtPUVLdy+aFb5wPEUQKMJnNxSIxyuxbrwrXvWO2tQQersDcz6fYmW0ErqRHdHk4oIYEV2
LTPY7/ovfE77aBadFrTieRLKtYB953gOFcLbcpTADBJQMWSIrmxZjC7ThiJgC4mjkgPYnUvYIREi
axP6yMQzjZ+GZJYAdBBoQMvgOk0U6abx3QNpeJjG5ZlyFIb6sXKmhSkLi7KGrXoOI4h/zwV0FZln
ev8kA38T86FCaOfuFtahsWA0ynhNFYWhYrAdlEcS3EeQ6GnAXLtaP1R/tF35xVxDhe8VHRuDm/p3
7MyyRTsrNV0Q28qMjGG7UKoGZ8tEZTGoKi8ICNl6LBH1IwcmdhjmucbYVUNRgMhW9ic3qFLB+rou
AQThFYGZ8kVz5c1+m7zNyxmQFPThiD3SNbKRNWCylBoUL5mnoAiF75Mo53atnMJwlLwnCgJZEbQr
fQ1TWcQB7pbycKp96bE23y9xoNzRSxrrf/RjxRVuoLNiqHglJJZ9IuSNMybb26YAmPp90jT0Omgw
Ucs4Pf4BrhY9DFRieK4U3P6pAhNh3L7YfjqZi+3JHr8MuqW9g4y3u1yQYu8Ojh/lGV7g5WSUARG0
5x7hh6BKJpXbsrPcPUfX/IKnTF3AC0Dhgy3GjmMmOxoafE88WMbY9Cx1qLI5r2kaR3VXquLuN6Wz
smnCxJ7iijo/KTOgPE93cR6bkbWLmqDb4AfZrnhxRggq/4OVhAU3ZT1KuKR3f9sJSQQVgyKvzgPw
imF5zsU4GTlcQC3DHytIkTQHKlmd4cL4SDsHFWWXPzy14iqODdES4ajcItoKvkMv3PHAoDuDQ/EH
of/LUXphb44pwg2G4th2f4npYtyubhZILMTs2ulAT5yEd2o6JMnRqUF+prgapstvIvB4gxua2KGB
Owk4aSzARIPa5b5TUifMY3CijfJ1PIpFLHNDiwp3XumoBBF75XBqWNleaGQYMK433vWMtiZOTHuW
du2nvGCJB+/QyfMyJz19tPDt3acyulf49RGgKRzdJRe9f8+/RgXlmWOFfIpMQh7VcQtOfMOPIpSm
uYj/j/TyZgBdkfP/KuotrbcFQVAQ3JqduXW3nq4K3rS96LFI4uzOx1UpypBTY+AaL0wSBnkjeVss
asVih7JzrwmSs9GotS6LRzvIytuAmwEdgxJEFTisweUyQCyNNgkNjQkXjKOjVBSUTyJFbxr3YY2y
Of0FX1FPG0pBIIduWLBJ6uFyNuIJpZK1B454uFXovCat2QdcKcmvRKaxxQUOSSBOeu+wJcRauvRe
76yb7FvMYEClN3OIldy+lKX8ROROBWG7TJSSA6P1aM9LZTf9SQGwKIdQ3/Ts8EfUPvhj3Yjf4iwY
hArApI7Im4tBAROU/tSUbIvxWmWwS3TBFCQ9fW/VQqNX8M8nzeT5NrOgAx5CUcsyVmAd4+TtwAac
v2EjI0WhIVY7E9TWX4QEcAafR71WyNMfFvJpkUf0JGSUww7Acqzspmi7egYiImmocwJ21CE7+pxU
RIl+gSEhdH/ifEh74v+CC024DpeB1NJLudJjwmw43rLnECGRMJe/cRBv17Dr6lTMH5nfv46F/N+o
9y71NkIDLdMmIOY7HjWMB4u2wA3YPwpECTDl/5OVxJVWLB0Amg22ecQK+vid9cpKv9WduLWAzPEJ
j+GN9XGIeN44WVTHxA/9xPE5vKfBlWkYsJzmLxd8QnYAlLH6QZ5XKi+6CG5mHxJcFLI92eo1dMej
B6wgiW7MjUEgOk4bRI7zYgfhUCYjDIfczMfibF8KSF6t7ecIq94vRPy2J9FFvo4dMjHy0Aayyc/6
ZpvXmK9yDK90iTKQzEnQuOWzTFIloB14d5UAg7l/zxts0NAZ9VwYz6Aza5VgVuDCuE5xraxf3yEu
OYJt4hXAOKaJpk6nx9zFx39dZrWqghYqsLMUrfA2ZTpXT2jsPq64dibbRwbbA+foljESElANMIDj
i1n4wrvxU1GBKAaeKeWZ6c42Opr8MfXN5AgKMDyrlnCXKLbTV4k2ukPO5kZCO6Zw9BHg50MEAbNF
iaFDOMQap8HEKTIRQqNes1rAyYwHYacnrAONnGO4hZioFjWics5sqD+mrFMw2XgGU+kkOntfwRoX
KgDlmIUFewqpr9Bd0YCMo3Zd6JTrd+EPh1rBhf/SPqBgIqPr20ISfNWwXdcPHBHNLtA3iT/uGq0v
DW03Xi0BKK//UXMaqU6pBghAe2RkmYX72LrVSwk1yqQljtqoulBnKR7tty8ap3p8/qQIVhLx+iVs
RHmVMxjzGW1x/9+X4xTqMZX1pid9Id8Ne28CB05OE76DMjEhJL8pGvRal5aBS8UKj6b9OKHxENpd
eObWJlDEbZuviV0s1QKvDZ8Swi0cAja8Jr9RE0WEaufaIYSUtLQ3n7f7LG29h9TTyOhZpLwF0FtB
Mti4MC8oeQ5mKweRyIgQ6zri2e3tePZu24H0/c3ekAwVJEduIlRgqKl152JuLvOLjBVoU5YqaoaJ
u+QIjoS3kGb0PojlQvtKBUPiCerZCdVGzZITs+xTpRw48aRfDcOdwkprO6NOOdm06l6aN54WdPVm
RwAAsJN/879QNYyFQ0pLoEoFmpNmjPknOGyEQ9lPT0Tjgn8rZVBUkPF031gaCA6GH6kjQTNGbuPZ
ZX9AHeMwyqYLLxTZF1C95ldLT7Dq1RGSUhjalwskqzj4EdpvI0HH14ryDXVhNdadnntPAMm3tK8P
tLtUwaZ1jGoN4I5ieTPNFwBzL66db8ql/r3qy6aPXwc5v8Pycvm39paVadSBQ0CK7DGvL544ZehM
g6QkUyIEy1rE7wGvPtlg/50cBWOZmtzPDb3EpOu4pvwSioXJVPf7Fyn6GnDxTPj7Y8aSHFSiEOhr
Ya30i22w0PCc4FZuacJtJ8B4EYMCytNnW9X72swc9wNDJn/0fv6KUr95VM7KpTBCDHZVTSEFI5p3
m0/q7t//AhH636d7filmqNu5KNCaEy8N5DCvfwoyCrD98xiyubbwkmqcwDZRkBV4gVal4Gbv1SZl
lAieL/v2PNXiq9Ym+36EmXwF6619M+/V0RUJt2h7NGdhxsLeSrlmMhz9RA4xm39oB9MEAo/9xLW1
7mSsRkXw35UkGuZv58OioeUrGt+zdItmDKZLNWzWV+qZ9byv8FJLlpudv0i0wVrltA81sZhLbmZj
6o7PCleNEdBU7UWv+43V3rOCoMmqEQ/YsCRNi2NaHzZYS1B039N2+rwTTpZXMdvqG1EppKd0AR8l
XaGue33EXsGwrHkkehj5pf7fyr6SlTD6ual9qlxuXg48zYOMF6yB6mwyB0pJi9eZ+pWEjC+YpE/L
89ZdUanRlgCBBKFXlNgFub1ePwfpwnUl6/PKJkpi4TgEYsHd+LiQQ/y5WRpgehofly0u5wiP8CI8
wZ8K7yWJd0Yx3OuL3PgP3NUXtReZVEWojlUc8umFFRAAddSoNQ5XxWTV2EhKTNlGv9lD+wW3sAEL
s3ECvC7266CorbkkmykbJB7CZnG2z3RAubcrOJtkfEGcPN2hBhld6utflq6ZC0vmI0/yuBwX0O+k
oYR1h7MJlTwhjjVJMhQioCRwNEnNN0GGb4HXhgUGPRdaUEjpmP1V0uIqvrGsJTtXPNRLxv5XDQ3+
n+x45JPoQBNcTeRL2QfwnBk5XdnU6gjz5+q3LaUQ5N11KK53JsULsHdQpHf8NYO52cq7tV8RbUYl
kDVwW/NT+JpTEuNSYwD0oG+zowGVpGd6OzaqICViA0BG9+had4vW45ici22vS8cz9b5vNE1oH++Y
e2Mdrr/AkwRIsz+/z/jVHsfzsKAtT4Rw2DeWEn/kICPEYibJqb0POjB2zdkNuSSCBYzH/TNTYIDZ
EzUltKF737wPfH6U0DidtcuOrGNGlsefd7l078U0wQYCqZplIth5LPyHT4EEXSdW7AQn29XO8HqP
hDEp2J0mUErfl0XPf/H5HO8DVj6In5syRyffB5bVRVLMfPdkWwvOpbwwWrWS3NfxD8GIgNZIWCDI
NPFgMb+ylf+okhCNvyqyb3sYhisMbU5hptDGoTBBzouc7UYG4VcrdkXyO7ZK3wX6LsHFRtdPjjff
AQq5a/CZWfHxeMyefCyDjtydITX2PliGtYdu3oo3etdokHOVBm8xyhdXZuof3QmW1ldoos9NafzI
vQlEs3XstQybA0oBC+RDTwXslEmypTTr2zHHAR5nFmI/mtYBLfgbub1hEJQWszAIhxaHMNeCH4fk
KXaNBK0trVXF4hIr7yUmwOurv3CYUEFZA9scY7AOILh5KJmBrkDIrVU6vt9yatUAF7DszBmzB/Qv
1dU8Gd79ruvmtrv47liXRBuHt7qk1Tlz+lOonZWRUdEVR8mvYaQnONBPzs06w0z62hclwDTnv0/+
0CtPeUv6WZLcnHL7tONLttDfyDxIaeVkFBKYj0x3jb1T2ueSm7IJJOz7eHBk/2L2Ktqv20OAwfze
39+Lh2mAB/7s5rPnL1aJTHmbw/BNFVssM8LG9TjfmktXDqU/SiIOsxHfy7DNpromjx8nvrwmenkJ
w4nwGoT9/cgj3hkBBi1YiLmixie5rzwuVG22rePQyV2YT2yayKuhYuCnhxM+5Z6l0ajw/Ac2zUgn
9pTvE7Br6vcZ/TxWWCDKe/BB0pO7N8Il2++30s4Nd5fqroVhyQoijjg1c923tHRNmvJKfzp53h5X
LRfs3Ph2Qa1ngSSi78AcxcK14Msynjn5VzEx8EbLSiZ+RZhAV20kOL0zmnUzp+vv1fN7vonZQ207
ZTXQuafSWuLgDXF+qzrI7iPSBKLIZund1rxz/9Qqj+iDyby0x+6QhsQqUCYC9sHxMiwe56k42OQ2
x5KrjN4Wk4cJVuACnb1PRSG0TcJUfh4IoKFGNhU528saPW7GB+EVpy8ydTmPoTHomnOsKOMNNK3/
jXtOA3arfP2IO1cdVBmbDwwlN7lYJ0ykEHGFj0CEheFHKQ5PIxOe0ZPwY+quR6wUqu6T82XYi7UI
Lhssv6wnE935fIOXehzBAmzW87HJWtSvNFMVZ5XqzyiDc51ejw9Y0Yo/hDHZE2jyjrv2bZJz5Z4a
FWhNcXPelEXR5zlJZWllVuIOKlV725g+1LtNUZgSVEt1FMIT//S5579TPv2zPOYn4YJ3pS60fCj9
KS0qFvDz7O8Te8FxvS6e0uM1ZMfUxn0oPXVB0tFI3XZqlf9IrtP2FdWMY8PY+RVmmvnkDYIHASkz
3vaYinb+NKcOyWWO+gE9NivQQKVqNXUKdhi1gCuJ36vmu9DbpqL9wGIpIDPRj9++IPPCZzvfXVZ1
lW2eAS+HK2W9N1W18RCF+tQ/KUCo7N37HuYCAHBrOePlQhH3wLkcb6QRtjzE9yAfMoP3j0gUBJdv
8M7gT/dEdtU1goQjE3a5MQzsYkKmtH8BJEBoG83H7CWr3ATOilVRHLOzdiqB8d0Owur/lPI8iFxF
VQaHkmivws5b2njDTkPg9Qtbg4p4bAxJ7uzZMqSpLHypDWb6lA7WaEiVGvPRBqmASWh3yF2A+/Hw
w63/BaRifbMwjH4adsryyUneVrw/790UW/B8oaCOanM3nqsfGdsQnxl1rrl8s2k9B9mPcQ9QUeOi
SZQCBpvRmEDaSH4YVFI+C7e1PR62TFh/lDwhwrEsNex+9RRlpN9/xc2n0Q2ClKcuIUeiQtvvdfYx
wldUJASkvVz2yaPZ/yWtEGOcVrGRMhyrtfqgRo5d/ypA1hJl+0XVZYKdoTP+YzF6J4dW0SX/0FGn
c6clKyBAMG8w8tXyJcDobu/We5ltTIELZf0wbrcZyVi1ONo7fY43jMCZb1L8qejTkwBUUhhcAMJ9
U+Fjd38FabMudBpWGrIMavAojpiolARh99U2Q9BB8+bS/1pPtlhOgqYDZ/6n4xdoCE9dR1eohcKi
+u8NlUAl3UE3nJxMh8ieJruP4PHx4Zu75Us4V7KSAVL5ChhV1UUnqr/eR3j0KqRtfgXbGwpaVT7q
fpT1dWodcAWAXb/4S4k0aGNrVVeTpzZahilohIHDoPWGuQ7YGwjEBHd6670ODKV1gg/ucMGr6nJe
BJGVop9ASpHKq1nWl+M2bfk0lUiUOvKPyCoy5NTnRw6/x7GmSGjvRnvJIwvVZPhiGRyFT1GK72uy
fvknlstdDzzjIWaYFzhYdi+qNQKY5mYUCbzs5XfG8H1VN0u1rc4nJOBkmYYd6uUrIcnyadbG/NNo
ZRO0Qa5uMmb7ER6OU0suhyPXPXBTMDB9nlHez4Uu8Dz/7Z1tJgpda1MApSXYo7/2aT+VSCzEplyq
Mgficcfxv3sM/j7Rr1ltWoe1hqiCiVC2TvG80EblIOjXaJkFui+tEcQ1pLShrmvmfWgeGXocND3a
9kBgkOme6UBhkLB70NspDt4pZJL4blD4+rirEEGjyOzh4wHwYg6BbPCw07Ua2PUyCUBc/cy3pmag
WP2TmW6lHOtVusR28b/DKtDz0m6dOnVWVIV17EMJwwoIVt2Brl92YwV2b28KUgOTEAmc9mnDmkiT
U1EYSw0q3LVL8o1Pvx4JuvewXatbJJ3jQu/YXpArQXbtEv+ZGw/Xsd4mPdp6m5n4BBLgRssvLVFo
kykIoMseQ7rdYQJL4UcG1JVFlN6GzIE5cxE32LNI+tJDD6E/AOJHN9GpVFv4bm3OXed+Qz5+Bku/
O+kT/SGTKq3f9+AqfBDc2nSF7ocaFXddlHfiKan7BBTo/Pqe4on966nS6HGcozpKKb3+eUz3B9np
YmR1SSB8ps/Y85DyH2keBM89xluJ2RrH8Gs1URdXgyFRwBU1E7Kj4OcuoiPw2rZJo/nWw0RtWWub
BOU+J9TqSp2zOdDM9zHU9oG+0Wd6yKKGfUq5CN5u131ik1l8zn3JOQFycaokmvDMoXLaf28jhOom
dcaknFwB/7ILWebb7LIEbFUndq743ii+lf2dpVqgvLWzRodbqcdDDN4QKrZk9XE63K1Leq/vgP96
DLEj3GvLmyJupvfkhvuci+azFXsbAFNZOJqFOpreNpgzytc8ya735sPwseur0obGztMGahnaRTXN
nJRVOQhAF6FKy8wFLYi0uMieVYNXLlxnqflmiKMtZq7/ZBSaqoMeq53SpQClJz7yntHzKwFTgyOy
PGHT6xBk7J+Qh8o6O3kS0fBGjK/YiDGbKhuStH2lWIEKsDxmqF0lL8F6mxJDNilO8X0sgggh2e99
STYETpc3HMnAX6WP64Bf6oAUT/wLWZ/I020V/6+oHnV37M7iAWxbblMuvD9tfYjUTt16HDUdXZhu
U/hlqgbdQkTIotfOc+KQ1IoP4S3VHO8pa3k5wG/AVzxgBMkahSsIgBZSleLMPe2Qczpxnai3RdC0
tH71RBMeJuN/077qxMotZws5Z69FcLrt7wmqrGVOwfyQznOukWPHiKJcai8OXhYVoHq2BuPg5kzp
cFXedkLtZCNwI+KnrisIUBPzX2ABa3vTNYujSwLj90MVYjzvbR6ftLmpsGSRUI2qyh8YKwQVE/xu
bYt1tLj2wje7BHOL+30m5tcC/ubZdGdHj085M5djlq9VyTgfaBrKOATzSv4fzguyZE0D/o6Ef63O
ypTvurPNk5s/dVXKhY8Z9wspveFcZYp2JQeNF498Z7H0VDigpahZ/Kwcj+enFck5RrOyQCc9wikg
lrVbIjAyV4nE+Pv4CYvllVvLoiRX3epqf2PnAHxkg8GgKJ5XpeHfP6uhioz5fhL0MCI7vxRpk4eO
DhGHnf4UFSYU3KvkTZasnS3ZzCqZUZK7ZAVF7QzWzSwxB+6vZIG2Sw5/pPVBA/sNEkgIiJoVACJp
Hg/fR1/dgdD2Gw5/B0uPqOTAmuuysISwRNM4qFjpeOu/TiY22KmEcskUlz2HS/SYL3cP6GnE+6dh
cM95Agi4i4OjV2DQ0Vj3FIt86+EDkQe7pGNcgg4oRbR1lGdVko52ycBsJBi3jvvcaTwTqssTUEWF
5eGpVK2dL53B12EVDPNgONaWxbXRtyo2SvUV/qiiz1yKxGUV75cA6X0e43jRyjqU0TdRLDv98Obo
iUv4GDyBpphvziHztyJUldqdi2eJIzPDmbor3vT7XR1L+ZRXxKF2DcVpMlEsMdk2hUcgJZ90S3jF
C9xHf0f9YQmPOHix2ZWN7LoJxVgtb/mwzMKRV0Fa68DIY1WNgJs1L2YaC2fWYNQ3EjiSj4Zcj7W+
Dg5XLF76l+tJLHOEkeB8TcVm6NDnVfbEDCpIH2RPt0c4Gy6RScBcFkycmoIHJk5ZHrpUD3zJaJrG
cHDrtNhgMASvnw+qtRkAHuA8lAO4SOcFsnXDg7RkAhai10T/lmbwv5N9d5hTjjkO+O/yn9NV3ONg
Cj+27RJ97vF9UCCvH9imDS984jurG2SRWy6IXFUWgYir/OMrBdo3AJyweR8H9urbX76xCalSMdIS
qQ3LlRQAq4ViQ2nMtUl2yuAJ5PWS47inwVbCa4Pxb/TTJWm77j1HS6Q/xHN4q/qDRORQ6VmVJ/Ad
BUiCCZ1ryOGcwAwC5gY76/vEc8FlnL0iKNIDlbfQ/3tC0FzMrkW60dC947LOXx+FwQcQnnfIiQhV
0zNTqe/K1/xByiHosYuQIL8lngfKB51Xgz6KLnkPyW4F9awE+zYkyMBtYa0XpOl/k8BYjXX33l8t
YYUMkusJv9ENwGOflMLlUb6lRtprjoZzMj7N+QQT/SiYIVX2z3A2f3XgReGxTNlWRC+VznZXq2MD
tRHIlb1eB2IukRHuiuIU9pJuy/Phd1XS5i/BD/19FxvTDTc5OsU2K6RZyJtYy/1cYawfuhl2gHMc
EQu/CapxExA3t1+htMyikl6yRKKRa5WhlWeFZ9IofmEUbkfSBp69Yrx0QRPt+D2MxXc0Wq/HzjMp
RTnxeXt4/rxPahnEET4n5JCqURQ28j1ff/QR4gtg+7zq/2h1JQo1itPwzXStNtNTYRJsu7mN5X4F
0TzDOzfsrTAxx5spHoYBWGYCby1dxDqMBpUoZ0pn5KHf2ZFqJp5ssCpx2hziVR/CnHKHu9T0VW4T
c8pR5yJo4pv5n8ARKjP5kRK1pqCnYH8YouU4Ksrv5HML+EYf+NXx+we2knof6wRlGdUkMJ+gCN4c
d01+skNo3aU7Hd4vejP7A8AUumXXY6S5kcmL95XpbKZg6L5QCSGoiGq+xXZCEVSIgI98Owpjb+f3
eXzNji0+dWTicLX68MLq7u0Ig3H8RSFBcJZuGQJgWZM18befmmn7grmiC6JWBontoeBezCPRn+ub
8slCrPldtHzqMGUWwFFff0MUK48yIUZn7jB3k+9yuUboCm1ndlTOy0UekswXpWNiKh9aJ6cKDev2
GbVTNx37nUvCp0jcfgTufe28wruCYYdPHL2AMsl9TSNiZxJ0HIXFiW+kBy2/oV+pZeG93i7RgsIW
p3UlTeoBv29gm1opp1aupW677n0mdeeyqx5Sh4mgGN7ZpjgoLkqZq8JhZKSnSMLWd321W9FOE3T5
aCCL7hmtvwLHuN8bx55yBaLR3PYVwEmOYeUKRKDRvrMTD9Ty92oqSR6J2Wjm9DqjYFzZj3BUrE8M
n2sJ3hYWZfJ+35PpT/4gQ+f+q0uZds3kRi4F6KxaOUT4yaM2teZPTnBwLkDz5qMQgAhxSIidnBGt
9FhmWk6dpSrEdQ9GqvCCssDagdaRnGf82a8Az/9jqGMDi/I94D9Q6jo30Bb5SLehiUkCCPp63ptk
D+4j6H/iolGgPx+Jn4atyt4O1kcsa/qoblfkF/IeNqEOnkuo2Q3Zs5q0jXMvxjJqyrnT24pqY5IS
SHRoUnavDhXudWl9IPpOm+T/AjBccq4fVCwc25UV6L1ley3c1wEgmPgUS3dNCuF5LyxoI1oYjm2F
retGfJuo480hp2+2RzJzVAwzDW/0A+LRNqrmxJzdboD7URznE5vqUQtl+8NvojNUNfQJ4vAKCSOw
qYe3c5OdDAuM1hZocNDwCJZlazv4GHYvzOU5Yr6yRsycks5G34UFbWFIdjD7kIOhu9fjxjWngR7+
0igldSdqgtV0Znopdxvj+cMPjwrMyiQDuu8hYn53vC9j5Y4HgX7dbN2cdLBh+oDIBmgJkEg5pQLZ
NjDIc63mVsAyHPq0sSZnxI3c/G7r6MnHaqh/YCSppFUXHekydXnSFRX1tI8aDYNtO66lIiKxm9mn
epy4SZpTW+2hObgz0Xcdge5ykJkRnHVDtJontwTJliWy4wKzzzinOayAc5fPzQ3lSf+D9IwXcgtr
27SYxaDV74xotJmLm4wkuDjORCZ4szd3DYVuaC+ErcA0JZdQhnWAkfxfZhV2UDNK/wP5D+wxsvGX
d2ynmUy8t/bA31mdu2PyluYFxb0HF5Gsp7yYO9cZ4757eqr+fjr/g+VcG+kWBKzQQTHfasvRTOfL
eaGDVnmg2SwpM5ORd+SODB7w8YX92reLEF89aBvIceZn1OCZXuNF6S5K8Bj0W01wXIXp6+Ip0DgG
p53nODSO7a/e7hBVt8wZRQ6V5L+lc81KbT8UYv6BrfEzTYaSZgvXF3Xoffe6VS65iIwCCno7vTAj
gUhlCPTpZaQ/LZ+mnfem0KD8Kyn3LjmGWw+WMDv1P7UHR2xlsJ3TcNLSSGCnRM+kap+VQlyJFgbj
0zV51ZkSFPOh3SaYI/zuOmMHovZ+KQ2u0Vuk2Bl1I1nNzyo2QqYjPpsA2Z+3TZGvW9Okx9H8qg0k
41XcPYMCt9kArDSWaeY8xdCdHaq02Pa+ES5kD2z1MRoaBOIEtlvCfuhxPSaefMGvbIgbo7xg3g6s
OOMu3PtxeyGqiKteAK3LsD5PvC0z+kjqgnziukRxwZOn/8LuUJLTr+DDffe08XLcpijDgw2qK+qO
2dYwYXrrcz/M8arL2D1zkztiIbpCwnDUc0cMfd/YKXqLzNCwW14+xc25ckD2/kNb9etflolv2X8u
NTD4ncqehWtXTOzSJm4dImRuH3HKcwWVsscvgq5QmNGcAdUM0kKoEwtfg2lrn5PqzxhOAFAoEW8s
oZKbnG6zMWwUKKP95B6uylL0PAdYq1PKBoPNxCOG0v4howDRGEBMvQrlaP9S+J9HwZCe+inKL4JI
mJxtIT5XuQgVZVuSU+kY4wLePj+Vz32roelR5ID9CF4D0s9/KA8NSdc4wxlpkPueGu6+oLVjywqK
OTl2p2Ms+mv//GpsjLYoJuWEKdLOfLeK2X4aupVSW110rV6onC+m+nmAU77b3pErcLQnU76xN6rn
3AE0Yu/ZCfSbqOMXTE53zg4nuhS8u5hcXzGE6qdqDcZvAL84WPjm50M/6gR+rmuxg7Q7w6xyLlsu
tHxnxrz5/J71oadEHS+CzifU/Kb6flJcVQFFy28X3gxVAT3KQIxtXJUPMEavxL/N7kobJ0kEICsN
x9ZGPt5cGdpYtwZLpoN3hHB6cR1dQsKXEjSodpA4/XRycRe3KLhzviiVhSZjZ+nAcie4MU5A3nZf
iVeMVoQxc6s88Woqjv76KqeCDpuSsCdH1BHfYODfCcGMMn30TLfm0Lcq/vCVNjcWd0tPrXSBNJ+G
H81II8NhemsI61gB8lbli4TFTynmE07j70PNA8YJKh8atbt1uoE18jjdZ+24ran7zYGfUJm5/8Ps
PQ+d4ViEex8RS3u1RGYSKcGQQDi2vV9dI8yBy4tY79SVz7wYv4xdJ2Rnb/p+03SbtQ+1BXZGGeUJ
QABplrKLMTsEera8nUB0VAieYgx+e3Yl0Ub/ldWIJckgwhWOjIcTo52SsEznF+jtKL/OnUd74gJ4
vEowiFBTHei/kh5K6fp9R7JravdmcIowpA+PEID/Vn9W1suQ1B/nhX8naXunRFLF7vS5WS8a+A55
nzO02IxpxmuJgPA503hUBexiEdOaQb5vM9L4KA90164rXBqW/4psTEY2CU91L+XXWb8gM86D0ByW
Wi4Au78Siilz7VfpHPhh/8xU97V0tE7vtekZFD/WpC2CAuSlgnxK/pdCMdbzTE24oWZ/niGCYR4r
lHCGzQKUyje+VCX3DRE/62Fv2IBbZS+lyCUxD8dUsvJd7AvFbt+unhK4jN0sPnfszr7KXccxQpwF
guqWcj19dIf+Cfxk6TkvFt2P2y5xk/nAVYfY6s7DUzrVFTA96LpYHkSxv6+WynvEkjKuKdB/ZWOo
pPqfnPH2HsiaKbCBuq68A/ctVz2Zjg07FdibxRXwxl8sWtd0DK9kZT8wojm4l3W0Aff6V7En5A0e
Y2Ge913h5q6RCSipebU6LW3+oG3qx+JZ0F+Q7qItnwcNITmT9K67kKDLtpqKsZx1ajMYTuCLcHuG
C0f1dzdB3zq5JwjFZDmU1ghxbzZm+afIVi/aVBISi7iiOK1N+KuHCG/e58TPpMOwDsNtTgZ8P/Gk
Fwx1RIhmunj8dXGpnqpgqzORNGxak7Rhhlw4do+whKvQJb7VCdubUDghI+L7VoDCdhj+15OAwu+U
QffsedtTs65Wb2xJ3PsGJAQ7kn5DwUI1uPqHAYNS2N0t3oAPo/Lf52sf+wOsEDyA97RPqk4Wjb18
N+6HvBYwme/wWounn29w5Pv2y6/vuFCNdLjfIaZTUSDr4q8P+2EX4yRmbpMmgAVCzYPADeeOpQo/
2ctE0mcaDRPfvkm4Zou2ISRZN31IS4CuXL2lTbKvnkQ8mhKzDQmkly4GJkFF7DrGE1cEQVbf6jg4
hELDdzACPJUhpxZOLi8nBOHs4MjNMTbGrFjS/8+/2A+rEM0nZJtaFa5Rxlpf3oKCr1ve4mpfsWQy
aiGxwp1ZodsLjJRQZMbFbWIkCALp7QCpy2mYi9djOt8Pzy13dWv50+DMysjDcRkhEqOXwVoMMo3m
q3VzGPD7hoDXXGxTagXZW4mKtbzYHa2f3GDYAkyc3D9yrJ0CmPnV7xHTYFfvJ3ePGs4NBFe7SIgN
RPyYrm0usOMaPp6S+1zOlGKnSbheea5hmQfGsn3X0FcnWb8DkLKHSin/g+FF/7CHtZvXsqgRuxef
dhOgExamH7PYdmUFevbSLsAVYiJ4vhCjJGgYYp6pI10ql8agerdOxasIv22RoShSAF0kDIXyG2va
3zddZnfeZlS9vn2hgI3jZTrQX5lEXIDX+Ne6+ab53T31by90jLk7kY9dnaXuSQrcIN+1XiUj0TnB
/Mst2iUpJjcnXx/gnl1RyfWb2LFzAaZ7PXX/Xk+5nN6k9+YXt0mbNIvv4KL+vFlO0IxnjWV6WSWI
Z7ASC765m/N5D75kHGyRSY1sk+GisfkqJL0nnUsMChW9kNgeFnQce9RCzkLdhdV05YDhAUok+Cnk
7dqxBoJ8w3D4kkELWqR7cwEeaJGZ96ABgOMuhX+3g6I8LgZYBAE7z9SgvAfyG6YTO7AW63kU0sj2
aUDAmcGbogx8dUrLfNHBVh5D7nWDCrQFgUwBBzxzD+byCKl05OWucKkVKMyosllUEsib0ob+fdUi
hrMvOZTLCBuRpUDQSsAyrGyDMj+zEAfhtvsPGGguTiMoV1iawBXkshz34zZwG39iqxoRBQQ+J9zW
b5rkQiAkE+uV+qyIgb6h3EzWwEI4oG9yyycf4TOTwVEs/JHZ0dnQV60njKmqUPcRVhVzOGlv4KYN
ZnWsm/RLM2FpqEAgFIEezVCgmITLWvMm7NHc4qhaq94rivMuMPfpPB9D9XTLw/Y7LrfeaGUkd2XY
Q4Re+Egx7owtdHqrmChH+iSGvyRHZ6UmAL0oefaHTlnojIDRVU3q1Paq2wO0cWYC5BUZoLK83i/x
DCmaYEyknkCJ9SEM9iMMDTZCvbkBrmmEVzraNUQ1rLHL2P0eKtzYw9GcXIgCZCvF8vAe3rLAXhiU
OtqahGENoeDvzbWR8AcrRptbAqovS81rMiGPf5uhVeEXJV7HZikllIcH/IwETVBrU8jHyWioc9GB
qON1iJkDz8JKLOu0J3AnvPUi/FCwuLGY7PTenjVLMkGrGKlpC0Pu3asjfk3vhHA2F85jcMm4lP6v
ef5FrPywxw9RrnUKm6l7qg/wFura5fWiOl4VPze40WopUqyVFkJ3ZzC4zZJOrio3dWoSUOoy1UqJ
nodnfJfY3l9b4QsHf2szB3JBSNgLzBkn3eB07yT+SmBlzUfmwrTMBfAHUjVVp+rD22NNu6vvGcFX
aUipY1ZeCFGReb79zj3O56hzICgk/WWcU+AiRUYGYAnjOXMMMSgXUEcormqKTNA5U2Sa6NAkHawK
CR+t4Ti5odhjemkPBLHFlqZhkrTBDPZohIefslrCFyV0Z1mwqXZUJlktD3KKPnxmPpQd5AEHuAu0
bBBH/KuYJm3olRj93ZSDGF3v17r5fE2JpKhlMf4mXN3dxqmRSOdOmkolMhWmwuLZUTUoEsCMCoNs
IQeL1WK6Y+pLjpcqFGa/dKXl8SUUh7O5k0KUDFXRMqBa5IMbdt0qmzqdiYgRWXoFyKhdT3loPKwA
25IKef8tGkBPJlHGTptbP2IdkzeyadRp5FlDDbMBHGfCgIZ9yziQAHSDtrSgYHVQ1/V4fZU9xvVZ
UTUTHZ34wk7YtSMu33d2DzPUYYJEJQYY/Fpz/J5k61P5AsnenMgrYM1L47GRkawTECEJiZHwJ5/G
2hWD2YJsm1hMMIBwFuTydQYIu+b3kz+6h8babzKMjlKCQyt1ar3XD3cQFiPRg1E+L9kKi33/xxzA
OP8zemjus0E1zhMxAnrWrOosfpeIvxFAM86IEefNNaehuoK8XrwlXvYHPI8lRcnSw5FQo/PopZtG
qH2pYnIg5js6zfip/MXxRNGQ5mXrU7EhLOV/cDg+HDpfMe+TqfEy1my6fBaNfGlAKxEw4Ejs5//K
2KQY1gc2rxQiNWM/et2XUhde2a914TdCGZrSkwEtLATb6mUX7QJKh6tanf7xQyMNY2b3i84eS2kI
90EcN6AO/t+/QvmPkjiyD4nhNxN/nEggfCQhNAqqbTZH5omfvsdd0bkwGXHq144VcMJmuzCzmJ8v
foyHPA1kgABlaxheNX1KZiuPy5vkOWoSoTgR/d4WwQnqTPoZcjceh+02RE2jty5WLgw/LwPaJVnl
wxhm+L6XvabLZagFDB8St/HDVrDyXcfBRU/E3ask5ipH/dDP4h2N0ov9f+Bt+p0BFdBtYcxNFNr4
8BU/P6nw3jfDvxYuOGiGbfBoHmT4D49phmMfrVOlh0iW+z1mXoUbw2UT4eQ5O6itKe/OQblmFbz2
MDEMQCXFNEDg8G/8Yfd58swi3KJGI8JbADm8vN0Nmal4osw6eCxrkKx1cLANPgbcB+Bw1B8rzlKU
3c0HKliJC379Z1L/D/eps+60iuP6NNdfwzIxBgaraYXcEGrMlSc9MCyaARGpTqGmHokUqeszh8Fp
sftXJQ2Eg0Wuo+DcrfB79+Pdkt7Z6um0rGpB3bUO0qWUEX73ecPPgAL6APslr0W9g0JqfQIunroP
n8CZSwbg/wqnsdnce5/+c+p8XJes1pd5P+/uOEvwitBTCVccg+AxBbqPAN30r3+z/PNellPxKb+2
M4TG1mHtaua6QDWSDVJjXo28e0WahCJ7dI+WGFTHRV9TqVwz0KzMaeGGdv9bL8JWboD40Bz5GdGE
cvQ2N/RqU2HmmAHN9/Gy+/V8eDXeXjNpka4mTVNLLu6ue4m94EBTfOsqLqIztzvbK4qTR3rq9SNR
r0RJq+pVXNP+J49arM3bWQtx67QywmA+LpcGK10PQOepV7zvKA/StqyQN1TntbUgWo84iI3JMZJH
KYrE74yHQ/Qy4cPAtrPJFo5k3yuKCAqlINv81DDNIs6XSoZ+Vx5lt8waTqtz9LTd46TyUS7OitSJ
V8KevqtfBU+N64nQQPD6cQ6g1pT8WmL7b73XSiGgmOSEhSr0dqAeseDyIBLrcB622kvPkqzcvvak
sEzU7ZmbXgswzBa/7pz7IluAuatci14627sjrkxsH2THAWR2A8n3P3kQ/QGeDeq4dypFKhRGneJ5
lX/otz762yTLjjJbSkcba2VHOHbtw2sqOdm1CQ/AiHxuD4Zg7C0B5CaGUU1r9MwA7fpIEjInC1PN
6jMtBoQ/9dkrvTgJ+Y6z0F4bVyX7ahxPgdmarJ6m5JVghZE2bceVMgVZgIMil4y57YDEuFI85DhM
PUceN5vMOGlTwR1dof/oDqxbOBdvHDbNzSa/qLPTMjy/0q7Rg2QErsdXZBV2gUQZmt2xU/bz7wxZ
qEah4e812Ximuqb4wbchT+Z2MOffcJRaWD7QoonzgNLkaN1Q3kd70T90F5WsoZMnkOD5XgHUVcXP
GCuluhl9KKi9/msx/+YMPxKKSQ/AfI+LOb1LQsSw4WqMjQQKdezYBX3Ju83cMkyKSny0CIeQh+cz
Bw2ap845yfdNmXpOXBQ1OR2efoDQZBGME3Yql+wX29Fcgi0OANx9hJaGuBCdY8zM4ZQ81kntGfkt
a6boQyiNADzCtEzc/ojXRGvuSIw4gpjZkhaCjeBS3w61sYHcFtOQ5VdKNMk3JHGo46rn4qiVnEQm
7XJ6+36zYFJXgDyBI8aqSTAcTqKDfrO2Pl+t6ZGGdjPS4E7CU5PZnZrCe6txJuXnFQZHDR2e3kEE
65Nl0TpTrqBbRETpa6eV0JumqxjXbHEQTaM7n6wyhDdpAGAEldfLNj7MczzPgWQUeesVJuj7mEtn
SEoptqQeE1mhaxpSk4hLaNRJDUkPdyS55U0BR00JI6NxUZTnHHzHJh9lmB/PfLOOvypluFywI1Dw
Olbkt2DOwcK0G6/tPFgcpjWNVEzFEZyNyi6HjRqwrXaakKCv6tdS5JUsoKJipt1wC/xi/FYU3bJ6
KGwSqJDh1NoVN4kinBVGMROhKyE2QQa/2XAOlCa4+wGAYJkIiMUtcA7FrLW1/3cMSwthvZpi6d8V
wUhyDcY2WH5ugtmm2EKxWGNYSqyRe1lS6jalQbnNDV/xpb5qd9tVs2V+Zh46fK47otz/lvOnouUb
B+2YR9XsSb+Q1qvHO0mFjPCoiMVABSkm6CJSKDDBzedmK04WQt9Hs4dw/iA+0D5ZYMcEj8tY2PsA
h0QxYAMUyIpq7KXwoVj715m6y9yjrw28DO/yD8tYk+YpscAaDswjzKjdfT4Mk/BufZLvvFlhtoX+
PFLqr1rqTbkqa/2gBsFALTkjlxjJ0FlGHSWtwq3+0rS7EUpdJcp7rqhiAPBH3bDaCOz308WMy4Ot
uSsuzUFuJUaig0OAztt6Nx72REUQ2mun/Spc6uepGjZrOi5wrIVeVHLDjic5npfsSAZTaJCunzy4
Q2RVPOcaeObxYu9hNZtGHpn/gpZ9S+OV6K9LD0Mr2jtlNG0abnX3SWgJn8aOREgcIzBPT9cXRX7H
XUetCESB6zvx7eupWu+Z4wFhejszF0Nqc8obomylMA5YJo11XJAAnKTDRNmj7sevAg3UIz7plqZI
04GAzqvABO2zE4OdFZgooDf34RMESmPPDBmgsg+52mAPxvlyYlC5v6GUu4jg5JBriA9gnJsbwpBb
0SSUAtBPKw01v483zHVEn1ZL5XPFPWCKCY2p1ugm2+UdoVfgqgnTiNAZpXB15k0g3WAOc5NJsrVX
uOknDQotfOXh6l+gpOsk15tLfKrW6YDiq71L4fiuo9bONttbpq8wNibWLO/rqUK8L5Xu+mSA8OQp
sdYCWs9xfDeGZiqpr78hrKVp95oaN4jaqWVB6nNlsvykpkgKlxhjpluMx3WNgKVIvsCfG9gJnXdj
SKrEfom5sKcvH3KgMuERv5m2bxDDuBGaMl+zOOlTLTbH63KQmFpwx7ps1aT/oyrOa1sqXuNB6QcQ
+06kWfJG+6WkGjlPX361z7H00vXwNt9CnbGbb2lvhWCYK53NcJO9sWzkzlGtA3kTpxgQ8VtEydmm
AnIKmQRUZH1PO0XCEjVxbLKBDfD1bn23fn7yBQf+lKo362WVzFtqwmknZDWIPp279Gg+CpmpTiSJ
IDU8PkfkYtxbWLIvo6pKLluAVQMgpD+Ms4XAvBsGZo8731Vj+QdbyyAu0XQCJKAmYg9jD2d8NiV+
IawBfQ7F7WLqrdFocLk0tsXTZpNVxusp22rf3UszoDS32TDfZkEuhaKwqtM+g9Hbjsrz7wt+npFH
ZuZikXT9nB/zwm6LqQf3IjpwuctEfG+FRZbtOiyc27UpFlP2Z2mQMZ8FqUSooz7wPKmzglNxLXC9
5mjab9Bzg2B5O1DwQFzExpQe+meBjxbVZVl93t5P4hTTC1PTqP8l4ROz/hKCWw7LVUY4I+f76Zcv
jKmgZBdlpRMZG92aPNOZT2lqiVtw/BxusDcm8UlefR9TPJXoFKSZXa1ENZuDt6G+K2oWFaWGSgST
2fDcxPvqwQlmTHrOY7jWUUXLJrR4cwoQqRj/h3Zm/2psnP0hAuXz6/bDp/LoJvT6Wi50HTbwpjVv
LWrd3iOHBpBbnUZPqzFCE/eKjRNuGqRV78F589Eseats7UHcbNhy2eKuMRHQ6UaiTkwZPHMlTqti
AGDBnsRKhK+JuhLuR+ssRF5p/6AQsmslThxtqHWURhzz6EcO1O+bN3a+ItyR6TfQ30H4e2F89Ec6
LYzNRpBXslWL6LBAS912fDNQKSWqyM6oiwCVSmZXsuGHQxWSbUqDztmrMcFwEQFki+9HtzVLqeiF
2pvBTH1nfR1PtxI392FpPhzbqb9+5BFT6xzn4eju6ybs20dXQTH7OED/RpCPnbCJYlp2u19UHD+6
/eMyq2KokGMFVpbB5XH02e8h2pByevCOuswmTgZU0kzayyZARlR7lxvOvIyjnpaerajVrTNzks/V
Ps0VspdnMhP/NDwPNl7+rC7yfR+BgrJBnVM0rwFhiHsVnYgJ3ldYvVpJTNAXs+zNb0Dw47lfTkWA
GvSMwP29vKstKXroKcDCOOeClSmex+cXlNIWKHL7NW+v39s5Vi7BG7odAQQZz25CU4wDOh3aPKBx
XlBGQOm98XTtukVx7gUGGVQk/TabF2YdqUwecYOjKB0K0dLEg5x4/n1e7X+SjjWl4egqtvyzjk4U
iOnpROcGtkUNyzQQ5ww6cvasrRh97ai/OXpfBrQkGbfJKWKj8C7uc8NJF/L9GkKeJKgKxI/svPqd
TvTidtZbkkMyYsItXWu2M3Udi4gVGYAcocHx0h5oe4uTbDNsbLFhQLHRoLxXAnWaTD2vrhV3jVSD
08ho7+k0LCkr1TdJzO4fQJWilANS2NgucwtUZRHniEGA0C5ovMzLhunU2XcCLrqVD5G/ef1JcBfZ
vWKJVhwghywVAVX+AuuVXEghkTIdq/SUyomQ9GTvuUqwFvxCHtIrtHbR/MrDhdwvFdLqjBfBxy9U
Wi0iAJsCGhDWoaiPgRr16ZhqT/iJ7NsNqflgSfYQYWe+ODw1v5sFRfVMRy9yA7qAf0ssxSAEf3w0
C9IFNGAMmRb8kn+u/FopqWRYzP7g3ixuBUnUOFZ86oad4Q0HQiZKj3ZoFhZxs8rexCTvou/OvhkE
x2n4tb7fkg9g9HKdTN8BJzxYk+xoegkgf5e/Z2VXcmrkJB5BJ96dm6nYKnw4J0TVe6rGbCJJukdc
P3uffIISBoxhQj9QPo1hleLQvJPgCbNqmkF6S2yfw8XhTEbzrh0VXjcBd6vrztp6QY6LjLQJr3K4
HdrSg4FLH8K5e4p9HHTJ+Z+A+Sby9RIcvlDFGjlQ5ahMsM2MBrz0suJBV0DDaucT5jLxCNjf3T/j
eECq+gLlYhMmpHFuzSRokDdwFNr3R6LC9JI4MLAgPP36XhFFhea39D6UriFQDOF3RuXreDWT8Zny
zdVQ3sQlgEWxcSz60SMat57fdsBtzmcwlMQ7I+0BFF6NRHx/xR5BvsfCrggk0U82CEm70AV5HlEt
2Dmw1/dO+RQcfmRsohD1iO9rvg4ZoEbDNFM7QbywF03N4Nk4aepOO6K7YnqhmZOsgJ6RJfAov9nO
YWl+7M2NvzO/unYWI94U2hxyLGVKXsVV0P+LA/N6pvbgnnYVHbp04gVtlqTMFXOEwGrK2s4mPjiZ
2m9o488AtbqlZ4KZX8s0wMF0qV7UinXJfY5FXXKlqRmJxlxEOIqKFNWV8l8y7hF7eiC+lwoVWyox
ykocQU2usxH29MVrWKScUYWGtuSvayEd3WUcbQNnKUV8oqQ8wmrt5veta/EGdexwk0W6tAleqQrD
k1jM2RfutlCZK7+59027vB8B29kwUAH3ZbiHVp93JzYDaXKZyA8TAgXBkaYSbze+fNm7aKS0dnei
d/0IkLSCWYT9H5OYN9w9K1NPtE0XSXxAicH4VYX47+uFDKkAc7MPnvyMYUqkaRJziZ4Hu2L12PBg
slFQVYeJcZKH+m9fk0FFo8EAhPJx6TWgu9QEMTHgpFpaz1q72uYI3cYlfpr6m+cLm8FCxO2zURb0
h95Ta5D4Z284P+OQZ5+UBFQwBuAqZ6cqQ8tUfR3AVNuhfGhWWkFtLQZ/r5HBBLGYvO/Oit+YtLnU
C8q/FkctCeGHX/UdXZShqMLDxnTLO2dqqSnrBiVQC8L66jCUsonLwBWyZ9zjpnhRqZfdobuiGHs4
zF7Gc+WYXo9RVZIDCbF1EN3hdByWZTIl5AeKg50aI3l1IjkmfC1D7XvRsYN7bheewWpwVnTtV8tt
p1B56mz/hsUTS22y2vr7S+G810CNt13/y6cJBDsooEPQHGObwkNssswP65S0q+Jshc4CggSw3Ym+
W4ohgLIi4CMrH1Hl9sL0vW9Hlyn49pkZ+meZImlh+/1bJdjPKhH9z7lDRIblaVBg29t/dIqoqzmJ
rNOlesWKxHXyTLXBHJRQeyPTWUqzVbuElGwZ4/nGu4qIzTNkCxe3iPgfwsX/4R6XNYoA3pJK+s7y
zuaOZGDbPpcXrdAqspQ6lx5CeK6qkHHeZtMzwpw+vwlgBYAwcYpBR16vxmUP/jCFQXWUFdqp1IXp
lOyfL9UzIo2GTTjaoNGvIJ6uewe2iE0qomOKz/Pd9o3FeGVyu2vd0aHZEtePL84kK2G7frkZhRL3
MjzKfwsHzswJaRUbVyBlfBktxxWMJdujsp5NK5ADThaVthE0uxa5kmwo+C7zb3b4lQoxaVkMaHOZ
fBv5bOCOCgFwEFULIGaQMPN96aBqgiTmmd7kUWEANScgfLzENfAqcO22+aEOTQw7vpKydfc8neMU
ZRwhZSqoa+QelPmrV0nLtdmvBrHQFfwSvSsAl2oIONGdUfhHW7Qc3w869KZZIQjFQ+bki0J+smI3
DK7F2d1n7vQUBXl+LdSPXaat4RFDOEMmfX2+umIaei4CkxkUJP0RusH8lj5ZAxDUo/nX3Eh64fbL
TqHAiiOn95J1HdTcEaiUm/TvzcPw1J+XQDJqj6JDkG5qNU4vhbjnON7d7mVMHajjor0OOamIssFH
YQr4N9//HfdqsvjWFhZf2RTk7S6xFS20MNxTi5NiixZZceyj4CQLTZP+D6gC020oWr+OA7NOHnlF
UoNVPEMSW6qaXcvCU0Jgz1FszfTpTkRJxEj/X7K00jhs0MunqUZ/6ffNfdcIvmpVDCqDOFxw1aR+
fLhpneaqkw4p2k6UHSyLjm42+1NiMI2Um0PlIPF41dwBKR40mTLiYRqbE+dyIti0fsQxGF4Ww0LW
XHFG105LaTPCXxDyfkz8d1BzUgwYZxbShC1A9T6Kks3n3eo3XrkOan9lDeHPRumvnHuiKCfzBSxy
1LtZnbpKbkIWnp6ajCjL4KzsQqXcjh9NWi51HxsWaPhuLigklAOgdZyZFa32+vUqjbAkGYFqWuU7
/3bHBU92u38N12jf0+QYcgV8+f59e/yKlRq3pX08hheWqo/lfJigpD+i18Fe2sp5xec4Wgwk/6ns
73j3LwPwDzyBKvFVawuRPHV7yWuwvaappg348uLdArumsi6zT+z9ScEAacJ+NH6jUOS+4thlsNwD
NcOhay/g0G2Jfl3kyYjmWKfOb4GcAy+sobMlSkCUJXGRzPKP3zBbmyMEMbTxB4ooFLFs3tubUH//
KF/J4F8s6eq6P0FCca/J59V82bpVz+f+yhYdbJJ9JVjwcKAuvl5u9qVvHwe+kQJ0/qWDXAzBpB9u
zXS+6oYzobsfLI0IaGAjPrB9yPoWfL599gd7wTU/RtzW4Z5xHcpmjTexFHRm4uRolQkAHCBok4+a
vLE4zwp9o1sbBSNrXKIVf96LX/Ty66aIaDvxjIvjnZdA9iLJz95BWXhHBf0uZSqX49og+LKbd2wT
RgIlboEXFHfT96KthBVGbgVPniQwlkJepe2KvUwIUNv3LaqDPtbVP3V4xd0pI/rpvw+T+mjKQ53/
1kGyZuBrLU+J3wsrrSm2vsHMs6DQsBKWBYE22NwJHOcDPPvF4dI7lbkNbt2jNddz6WAQKOlyO4OR
dB9N37jBzViM82zdmEHw3kjzE8i5Hhp3IoPCZAG09rzX5I2IsAkPbPzFMExrNsjn77ailR0CDPDF
dyncWzIYfX2npAGyxIjUOi62I+2NPTB3OfSypWQoE+vtKnpc2gP5vtJykC6lEYCfm/OQGDWHFup6
zMkHx7v8jqgZyXUdrFBQuc9c9ZHi+pQEaIV21JWjveCUeLgOXvRav23en2U7p2KVtbllISmwc44C
o+roRcsP+P+JGAhEJPmcjrgEbl15TZymO9U2+nt6ULOgiYpvXdGmN1YSmLH/n9w73iF1sch3TB4f
MatOJb0IqPtF89siBVmg1cegmM+xVyzw3/qq1pqh2MsiBewc73YZfNsxsP01a980qajA6TAaPqsB
9LexRZclJKAJcotdsLPi3bkiimRlL54T5MWmfNzd0e79+tZzQkUf27mvwmUWXh9gN2n1w9eHPC/0
SDaCCeMWJjQh4HhJq5AeypiWIW+33dZZ/iFijNrbcEqpCw8D2g9tHjoS/0uOTr6aK2GAPR5mkz8v
AFLkQWWeemkJ64t5K9K58NOkl17YrDSsql0YTnQt8YYlXtGkrmpJ+w8fMFYjLwddkJchQwNZNe4l
Rm5UcM8R0/ByBRHofWNwCaY48bimE2xZoxaXXnbR6Nt5niQIHOrJHSJgdIrNA1E6XDUUBufdY5uq
HBEe55PrJ6I2gxTiY6QTcDGYW5QXYjHIwAZJkUEr0CT5kRF8+0TBMkIu/sbOrEVYOyvm9w+1L4dO
9wjrEeIS2hSkYDD5SUi3Gq4Hmia+X6ZEppszjTgLvDBZyRatD8ACV/HjTwNwDL63vFdVCNv02C9A
c6QY0AFdZOR2QbfvQORz29BNb7nNGbgHVsKXcYTXaqzBt+fjwrl9teF97T1fD9aGtteNz5v1d0a4
Hy21axVvT88l83uCAhKkdgPIT4y3youPhVPxDYNnhYEG6c+VO06uYR5S5iEa6elDbdjcxaxOcv5l
R1e1O0E2Jl8W1dLU+XV0NFbf/4Ao3EtM4FAMaBVCZQKjZ55yzPoJqsipbW6VsndA7JUSZAsu7tA1
JtNH/dCW6UIeHAJiX/I+vOyaGDiondQSxQ6Fqbq8A7EKRsRXWDP+FYNr2pV+TdCGgRjvflCXoRBs
A0Dx7yDJde9TKUqGELcsYPtGh739LF+A1IeEMwdWOdqtImfnvAdAMKS+TLu+P3+sdscjlrHz7j46
Fl21a2OtILJwjeOTgiEbhuh6XKAqpeOtGS5sAU6rfb697UCn4gNf8oiplNHzsPabaclFL3wFivRS
yDi5bLfbjS5E/h2o5+ib0bqwxOIQjHU2gGvUksmZK1U/iGMDOlWI7rzu1c9SURw5gnEZeh3zNSlI
ShMMw904QrWxuhcaS8nDWIMpWUWB9jCMOk0RrWojq9tnFHbNy5d0CI8r9PZUtwTE/cqp7I9lEsk+
6ALjsYQjn13w8v7683b3ewBnYisJI66ZFTwXkYQn19LbGqOJK/bB6SWDmUbXE6H44dKisTrxgynp
+RiuNjnCU0CHw+/poqSeKfIumOc74KU2uZ7NOVjQbjua0FT5i+hiQoFXhO9FlVIuajLS4ufE88r1
GwYtxZ/lbIuAC9fCKAGF4i/8eETZEdZ/JvLsPrU59koXMk9XOCgUWNmQtW1D+JQcvq84tZTlTLp2
cRR9lj2UlZzH0YtRKBTWrcC2BIwVF2gXVwzqMEfEZNL9+I/ehYieDB5zKfGX+/0dNLfmxQit+Wm8
yZpeWnKUakKrtGW5d4gAJcm0bgYCBHNOI2plbeEiVih/6A/+YEYnmCCbX2M44KX/XUl2n1INcJBv
SJISF1KlRqnMzSIuY1MZKd2tbh/POasIARsc6w4INpw3Sb2tY6eP1VrXUmqnKOURx8KzSpYac6DB
R3/mvAZrBmXGsLIIecuA5Ft3fiZR1gi54omWZO71aq4AXQDzimJz3edxdiOTnZEM2Fsw1Wsfu1gz
Tjedp4rGSJa6cyHgvwNK5aF/m+siHMzQnrF2RvSx1FgAkV9Q2AgfcEST9DmSwTM71ONTmWUW8VSc
yTXJdypXwxpoCvYSSBkcHhtUsepqGWc3RNsHx/5EvKBeiW2x/CxGYq9KNj/ZTGfRRg7giH2O2Qa8
LkIHQq4KOV788DXwI/RwXTMw2F7/imXwqd4+KEHxQbDSMVu4Cox1MyXktbM8FR1h2xkYNXPKNCpI
TKeDEH27GVvMhz4/mAaIq15lQCCqc6DQM2Pm0WwNhSV3J+YU4P25m1OiNBUfwijLqlGDjYL3mUoH
m7aohQRVR2QZ4kr+CUZdH9E15kYoIJblhlV7AWqtGgdFcybb+EaQTNfVdToDvAHb48eYg4Piqofx
xVMwk/GkvGPLw/mnrihjICyepf670ctknwtZ0M6ZIP73k3gX+r/gxKUYkzR+AJ0oLE25a9Pn0oQy
yqs47VqvIwxva7M2SCFAh4fWZ8Ugq2tSq+4YcF1XWY+b+r4DuGVRmzIGwWYhYEaIz7nNhmNJ9eMs
nYgozGAF72DaR8Jf/U1U9jnu5QizM5TfiPgM//HvsmTdQ7fgu1YNVaH8WYC6U01EvT75D7z6fxPo
umWI3FBMQDqh+fCd6VpBtx13YJnRcAHxoK0mF6XebvpLkGQb4MMbwto+rVHkwCPQD9jy8aH8rPzC
BrOryY4VixwKSjLABzPgaexTUN2jKN5HllIiq6TljMSunIU9moC3A55glNSVtcOllcxYSByeOTVd
7Hayuoh7jcJArMojA+u3ZojG3cMlAPcVR4W+ktdZvaXrZlEh2m8wxESLqsvZ8vHLN0nEuxzCAK1X
N8nnLNZQE+cobMyqOWdoxIBlHuS1Wbs19ZfLaaJ5FdHZGeaDMbRC1i7wA7KwTAh0vMOv6unjxIjz
z5VHhu1z4Tbxzs/k6C8g49XvHmW4g0vbWJpzJfZViAOgakmlvQLX54jkfLFkmRRZb9GIxg+4kxfA
gmXzL0UF21lkLH1RcXklOnMSySf8TBE+J3p7H7ixCE06+x3F4CEaHo+RzWfqWieIw6VJXkxWMl+p
PC2YoEkThEyrz7Tp0d2h9OvDUW4AkjRwXpbnbSb6Yo7xngsRcelzo3RRykLKeB6yh7hi5/rp5vx3
azULjginbnYYRmVSQLnqcli02hZ9B6X6aoVExHB+ifoPR/MYZ8eJ35T0gmFz2IMabIkhZjQICWNQ
3P1nT6ZY7haAMzX5lQ1iSYAl05DH/6XoJ90tRQhLi+yqj4Yr30ox7UHClyZ66UQf1KP/jsjYGgBE
g32NQervCCdKDkoUVgT+1FOsjY2Zp8tCL6SlZFDGJN5zWayeElsTQPQ1NHSVWr1gk/vgR3a4332H
7LxBHM+U6ejLX1yrXB9t43g6RMMK7BGR8Tl2WjKJZz1JiMCjEc178Y75cPZjBneilRA0guq9yhV4
2KfLSCrxQcCR4fRKSdjzWf7wiRoSPwSOqy65G+JEF5P7WLVZjeyqFcP79s0eWbps+BBZfAFh95Au
l3/QbZQgOlmi77xTpzYcBQVfuw2E59suuyx6n/FMMdKrkXJ2LBILCOOa7Q/Sy6BtMv5Yxh1scOPg
FT8eGiUi0ifO4EsQ2/kxmbBcP156sqXx79t0F21o+77Pjvk2re4GMTF3tLc693QidHHqwN6RvgH4
OnhMeXw5sJI1haov50vKYg3JS3/3IYcKerToj9hHN9ou0HisUjHUU0jcJlitWdjPw41L3uJkkfZP
Ay6FfU2FPus4n2+73YNai5m9yT9FQi0lw7XXxpINnn2D43kZxlB6psrKI9W3qWc8jTfhc+SyJ78b
dxlvMwzSEZtchAMPZWc5MvcDxRZhPFLRN+8z8mw4D0jQxOTXHT4q0YqoNG3EWzcX9GcknvPGrc/i
wXn6jMCv9t0TZdeKWJzbWnWMHBrtHmhDwlHAFNQwPxjbYtDcT0GstUqFznk1Z0tdQ8qaR6J1rSGK
x7iqP81+u6H3y031xOCdey6E3TG2zg1aMPiGOr4ZTmRsRiwrrNt2WX+8YMqtmp7RUKEQVS2pbX5t
Q66OOqKkmmOOD5Q0KZVdAfM9lpsjUGL4m5T2bJVpEhQakCW2cmo9sTflQ1FITkePFgtcyBeRuIl1
6zvmtfTq330C9eEYnVHMIm5uXza4HX0Vw7COFPAKhASbhhWSxZiSyEu4xOmQiC2DyVbs1zf4PYc1
zK+LDc8Skad+3aQ+2Pdb36OaD4lEky8jXXvjUrsAdsttPdV96XIzBh6NXkTOCA8SYGEr7me3Fmbb
TBHkOzvhqxj48ez2iZ4ddJg/pFwASLcmPW/WXDvrM+VeZEdRTOGg44PIHxG6qOgAo98vFZf5RYLR
/lsCyW0uicLla10ipvg5k8lmh/0uZcfaFZvuXX2jxTTycX8GEJEQaefNMDPf77ggh4js9EgmMSoL
jT8AXy56L1jXzfxu5dC/NAv3L5n9GiHcmlSmGbE5ekww3uh7VGAWPfInD5G2diSBy5JEJM1y6V+3
zB+RLtRAev+naPhJ7JOFDGQW1qq5UKr1Uz1aC+4+iblY7AusjbAOYr2oMJNXng/CUYH/k24PmcMn
rg8bYW7QK1MKPg9D1KNMh4eT+B0zUKveCBUh5cYJuZWH9PARaeG1IS/w/Drg4bK0+5FByrEShIEs
cJdYdcS0ARVhj96sWTzTJYCj8tBjYNIQ18exEluEM6oa2o5dKpCKBwdd7Kj486zDgi+DzUk5lCae
SgDAW7ytpVBez7ZSfKbEEl+04wrxMwKxAjYe6JcKLpyPHbMyrOaWQODHMQRdIAY1aQqT/BYRcSnS
5Wy9H78NKxl92gBakfgyMAFUqWM1QH0Cc3rjeeNxn4JL7ze7jVTokyYkxjgS0YRpetwmFs1Soher
pWJFue5JhaLAuWvmHRdYByY8ShJTQOb6Jpaemt5BAHySzsrv2uyvbSKa0SAWScTPLt4er9z3II/D
/xjXJ+rUbC2iPoUxO1lYtMU5zDirnXEGzUR1L+rH7mQAvr3I4XCCMSzUfhNq5msOuOOZe+w0j5O+
cyK8psnptZpRpk8VvFz0EGsbO0AsCSiy9kM/nVEy07+MPUjuABjqmg9WLoEBuLlbIyuufnZ4wnI4
+p1nB4o+54LH8P0y30/b9cSEZpD6LiJ0dm4tLkoCFo28X/BmgRrr6mqSeGM1thG8XhJueCQBlsmQ
49dD8CdI0DmOgcAsdCf7Auh/LP8IRyZy0b3VPF87s58nn38h4LaM7Jgxtc2QU1WF7I5krgEWuy4H
tLGpsJutpGFy5BGYbY685zBOCJMoZtO6aYXYK0b+00cCgELLjQBoogtsri/0CvAHgfnSHhI1S4bc
BPB5y9jSWryftf0KnUgOT16BJHW3Tw5P/TcSYwffugWfAQ+dFGyQWHURhD6c/xajIRouZNOD88Z7
Qxc5a2ZEr3PzUf4ZbWhK6/KzJqfeQJr1x7m9K2FSuI6lPxuRqdlRkxNMQYADVN/73wETGDfLLQ3Y
ZvtZm+fdTIrl8PoRvFssa6NLkvn+2kcGJjikiV2AmcPMCAPziW6wtUQvtGg9E+Ie+l8+5fgAhAYU
F8FXh6vatEQXoRb330lpwUMSwPuUM5sHQLjUV9DSXO+16SYvX9rSGIG3H1KeLledNb+hBFxfeaMW
ZJZrmc2PrNnBH7aIwVpKBYpess4AhhEUFuL1NHXMWvjskNOi6nipayZ24LJGpwgOPaRPIGisKC4J
zmsqBGUJ0q53Dd6OxQaIzHw6/z8XClOVyTqPQKzDUBZkuVaa+Huc7n1kTsNjxMjNOiJO5AYaszNv
kKigs+Ej196kfKVhmYUOIAyfzS9KBEuFISkKOWEOkl3e6d7bIlUgjRFmQejULRWpnyinoM8Ft+fi
rDapBce9CvvqCYuc5zA0e5J9AmT0oQJDE2uBQ/KAnH1BkkPydQVVzvvHeZNda5HzN4swv1Jh+g7a
I4j2sPKfzBtmhR1XYzutAmeQ5WQsP1vzSGFPHV7uDX90Hhe/M6cNywDF5egB0SvNLZyESUg/+gcr
HN//fAUyqf5LOT2s7RkwIeI7fMt8mgwx7md6cRVT0fpDXjPS+p59XP7lJKPsyJsjD0np2alp/oo1
olFlzV9BfW4/0jUepTzeIndoAOWG37AMfkeKJau6PIqE8K7XU0dFu20VzT1uM5YdDGWxw7HeLg11
Sb1FOua0j76Rpam42NuSM2zYrkb13p8ec/KwOPw+C3ywsKyBaZVgLhifjJwzOuX8RmW6aIvD1BWI
oNNS65L1HF4JUiAiEl5JbqRzUDd89ZU1fEhOTgk8Yhnya+Y7caU6LczzZdFrxtq2+86fss2qLjei
R+3/rzIty70d/fnXor0NvWaDG2aoM+UjcCxS6rFPZxFO7atnJ4EG1BLxUWH8ufCNVUzcK3qK93oW
XD0JeNsUhRBp9kka0JMlbNw9HcoABlMTBzCYZIx+9BOKAgkPVfe6t2ur9mg58xYUeU/tQC5LV8Pf
LyGxXQUa3cZecqDQFJ1udZclp1yVAR3oykWPwh7BPGWeGD81vALaszB6iJN9PYcoaaucttWwB0lq
WBKjMbOu0lTAbRdqJpSbC9EaYyTie01ut5PL9rTOswV9qtQXBR7GsFqGV7OychSyVDr2rGM0q+0w
/I5gE/a5yvgfVrfmyEirn6CTfpi1LGd3RUNJxamrVvuvJdBsXetgKtxAgrCqasB8hgsCSMZvyuq7
yZhYhAQh0szkN5wKTHqH1dkx5dCsVRhXIhtSDALnqpk14maP5tAzxzoKAywiaDiclOdrrNyzTKeL
i7xqz1I9zFfdY2DXLgWKLqXJDKfIu4litUgUNVLSewn4jvrwvnyfupQwIxiVq8m+/uvx/snT+yId
z36v/XI7viC/xUZn+kumChm5BgyZ4nUvM12R1yPGlVPbm5wohyORnm5BbHX4K6LC0xplKhONZe3U
Il5K95fvVrDzz06gWV4nmg3+ycJvwwmtBt7qj8wZ7TmLXvKsGbkzaalqjBXToRh/jdGIrUI/+y51
oocCkUjdxnQ3cSywX5wp2iWTdNL90I1IUZpp9Ho8yOoCVyUecPL74XhLoqCziRjSP3DdTrdKNeLX
3BqnF0tUrfz9CR0r/XXYwltS7ia31wi1GNX/9dUr/fNW2mw2DI4WsGMGwAAHW0MheGxrqA1P84Yk
cXNHJ9JJKsqqTl5xDWmwdv4Cu6A6KPwx7k/oklS3fGW5tw+uD1wsEQEzL+znB6KoLLWyG2OBnni/
9OaukuvNVYtUforalbpTpe6siLuxvz2e9Frt6OcZQrATrRPp9FoZfUWB8MoPMPxwXuho/IwwcOfQ
v8B4mCh68FBgnLQgP+3O5uZamnFRYY/1aeJX7Bg17hSGCNSPY+776PLjheZF1Zlhf9ISAOEMrz6I
KRl9akIhkCkXtuqaDbwpQWiLSNuY69R0z3491rvyFZ6T8Bk7FWOycIvSK8hnMTongFAzCH2DZIuy
R2M197rB++Ato5D0Dev6ejQx3Hxj0kyjm8M0Kq1P1VLFGRPYXIYuOKIPULqdBspyPJjd2IndQZY+
EQIq9sG336FqEz0Sqwr0sPTYrToabjOkkv0QTfciA2YqXuX6dP7BGpXAQCHaePp1PyyJs5+lYC7P
ttQkDwNTHc9mIAhYIqJUpf5cFPPU0NpUW+hgeAncvhhpGh+vM/Y1Zf/KTrbJaIS/heHZAuIG/BDG
vmhqOmXBNySvZG8wkVWFSHv0tNLOGIRZlt/19ZMQVxXbJjP5iaQHYvWlF8MGhTy78SV+CXgZU8bh
klri9fD/uRUXdSjWnb0LnumaMU0LaII2otcaHdsT0byVO5fI00A4GZVKebFJMrTy8wsItvCkcz7N
Et8bg8cDhSzrBwf8t4/Ytl4ErauxUKXGaPbYX+UUX2Ga8TBsjJp1ru95x+YE5wEUhZy+z0fGCfhy
bNl/ddm36w6hloitTqzVGHrAsW0QhcuIrWCf/x0Y/OiKypV1QXZ5nr0iJMTI6ChlflrNUhRmy4QD
5pnMk5UEwViGXALy9SdI7O4IobYLJFMGANqcFRD0bdOxHw/G53jm+FFOAu66hR2AVaAIuvtUmfFo
fygGk6HA7g5P2CfSl9dPh7THNlaVCXyCyAJ4EWF29vQoqpHbjBdXH4jnPOrXHqNLXr5xx2+6HXey
UjIzP76uTtnapRoWnDPSoJL2Hewv5/LpzMIucFJGzbddxP1Y2cEWqDb4R83Gn0JD7Hu2T7qQAgtJ
vE+KGfzRqLvjTD+jZ9C4wH/Zk9+x+iu6yHrWDvEZZwV+ZWS2zvF8F3bqUgWkZkQ97FihpJp5qesW
sKH67ytXu8AgUlnPWLTTVCyxVe2jx7rWaEHsUd/o8xmRqc73u73JelKI3JUl93tr4T3Zswr//h/S
Q1TSX0KkJS9xYsDRgKQEXzfOQoP8qerAroCFZgeqRKeWt8A+uvR48ujcjEfWa4m1GcVTBZUDaejN
KBTU0pCJCanzmAb6Q4auZuWMz/KihTry87auT/2VI9wj9yr8NQaOstvDbqFLjIcCL9BExqUSlJYV
LMo7A3R8FpCy8mn0zkqpghATvCaCbHvDQ8RsiSiQ3wobGPXYbn6uR/DRMy2Q2PNUvH3cuoDRot6b
RBMN2+DSf8SIYLU4ZoZwXNtGnkGSX6cqrWYUqA7INe6Xbu8HezToMq8LqlbK/TrhB+ty47Jgf8ES
2BagWPgLvFMad9j1bVYV3bnYlTwt8XypQPybix8M05w4tTkUAG01BDNGBZkjv6KuJahmK3xIhb2P
6sH4JZObROJyZiVNlPeyDMtaxOn7hyODgh5tJFUfUWnIzJn0i/IVEBdsr7Jq41bd2hMkIKrosYP/
t7re9/8JVZ4hjjEMn7oOJYt7HVrKiVwrgTBzD8zSUXod8d+nSzeFyhS8fB8kc40LGnleslLCtLLr
syc2micCIOJrgrCNtLeTsUw2bxyBLkosdecKr/U/ZET3H5c06X4hdC03R5NBzx3qGH4VCA1UJiAa
4cpTSUYhgOqgRA7lQtHrRQaf4auFWhtYOsCWhm7/MW5sxSVQuf/Q+hDtnigVYVCgqC1o9aIql4Tj
IhLR3JIHevNrBolZdD9ak6OyWAQf6d9WfJsPvNQauJnMWPS0roxvprPP8rAkMwxpg8+dk/bIdGIw
mJDYFJ5Tvg0U9hDdsdL+32mVedhdsiDo4QzhGBAaVFBkvjdVRTtGSZtrOk3VHmMgBgKl8hb5Nswr
Lsy52ja0rsldc78h6hhSd2QrOZcpiHCe5RxN0IFNc+XPVN+smJtAvVRNApppomyTbCL5Uld16siv
yAVU52XEJuaGYvSy3/sOICMR90M7xfHbXI+cHC9+yAVxJATYBZeCH6Po7+MmE1pnLs34FKk7AN/K
yl+uWMb+N5mfqOLMjpN/8QKA2dFkCiIEqd6O3UiLk/2vKngACpwv+OWs3dSeeCairYaSVuEIgN7X
VbwEU/cHycz9tQEs37Da+y/VEJkz5gJtZjWexDf+HedtCPGDIJjbBXNMox0PHfQ2cF1GtJ9FRiCB
hEqc9IVfxQd2AleFYoxHL1pVoqnj3TcLooDgIKb+BTdk8HGFY7umBUOnqF3EzwLrVTBvVkwcvomb
lu1uHyh8BDHaZcm/bB6e/It1qsiuFsLldD4DfyAK+JFJL1oCviH0xVIfDSFvxW3tyCcBf7L6N0d0
YOMVyuatSog6PwolOtPSue7XvU8t5/jzjVTe+IfNculOtjG9URuLhW8GfLJeu2EgS8SabFBf0NIh
dWjA0zCBEpmg07rhMkS13A7PCa6glUVq8GXw8LWzhupHUFt1gQRI2N5VEDWzPsjNzxLVjcWZxrk+
A4NlOWFN8AlspIlDzJlMstUM0uAueVDm9DFzpMDKO+EkgLOoCz/A6gCuMtw6jkfX7XBQeXbPaRcI
3+beJyKlNNl1Luteu32DbQSxesTnTtk/ce9ai4oGmg1yMO6TxaSGfbwa41wOUR4deTDBKrYk8N/R
P7O+XdKHyxs5geFdTlikxlN1y6rNHzOf4a5Jy+iLKv0OyqQcTIfgXvFD+9CXu2qHoQHtPXp2e5Sr
IMiVh3FLVzFuM+vbeeZBNooyKV5HnIZNC/mW2Lya4UIFkwkbsQM4zoTxhhUD5Iys5Mwr/lsSOjfk
GjSpaRqacR4unUQFr4gKsa9FPlZNHD5G5MiiznQerk2N2D/H4oep42syqNWQw2W/NrgKRoVo6whE
SP+9YQcJ5omZqyE36PGgX6aJj6N7bMjArGDLBkpCyvdZClcEPDiCX7jDDzKjnIorScsAqbTy77n/
DhlnwkJO4qGVAY9twm5z2DDEpn9tfxGI8zYJyUYjMkiQvX9DsR5zgSv1vrrwy9dmTgZD/YbRKnpp
D8oiwlZOLo4bsiaul8VIwPot7MvI5JmTs4PzkvCmFEx0G3jVH6iG1v0yl6Wd/2JnIBMmPjfrPEo0
olMssaVGG+Tyo1xHi4P+s5OQNziKPQ+2r3o2VkRneikEB30+tWItvoUpfjzPepZdQt2UkEKKwb/7
wkhEqfoAwVCi7/5jAYK0HCPzuEf3CTssXrWSjtqZhsfJrk/d0Y4QWDSJcmT4Tc/BwJtHaLc63Exb
/efJO9mkqKp5eT9z/kRm418rMgi63a39Hq/WpUlvdI5GvQNSgtYZS1Q1THBjbti3cOS5vEhCwg+L
TFSmjLFPUL06AX764QJYj9NcgfhEYhvsJ+ECOp9GhaqXzitVu1NifXrJ4ei0sOWZwc8n7y7HxIvQ
XcA6DTF06Esc8dyD8WS8qm12YL9bNyCnxcAVxQ/w1bPexen+PutdfPDG2kxfe4jA1dw8XX6sJsBG
vTyYJnmE5RFeHRoekpC1Cqc0m2nNocCxmD3XUJuE0ZmW7YghW1Sojmmdhs0WzaNAPkkCfP5hSS4f
/NGdIj/whovBGKoCp9pw21si4Rn83vPapWsLMbZ05qVkaYtAU68nKb7TaGK82K8g5ma+7MF85XwH
32S/iODxTsCPVtE077RBWYKkTtajFdzrtXbMQGV6Me1QPpjMeT3jkjNNxpW20WQOKdMCIqugZmnc
TRIQ8BRS0Q3Vte5dDYpFos4zXqkS+rlOsCi0AIqdeotNeZnKqAzfCtabWPICAgEu44qSdCmUXqG0
ij/G4PyOCFkPi41ZysXBPt/9uoaEaQ89qDIFFrvU5DLCNN/6tXTpzewwt+oY1gRvwmiCqspaLfAn
IVUMGoJ8b5JyCZg2BKZDbHBNHRjhjhKT2YCcmdQ55tbIHoDWBJtjPvixUo2UTG0NX0NPcS9aWjOw
5u0O7y3uDIiti9SyiKYQrla9k3tUNiSq0ik/vmzvd4brLGJZVwXiFcPKA+4oBX0BRnyAcm6VBpai
UoFTPv8fZpVps0T1vlgYlch5MwDZSbr+1S579vXNcHw+MNrq7h2UBTq6h6bHL+wsptj0wpI+fzMM
Ixv/uxiIKlIugcx95P80kZB7ssaW7/CX5t5sloYWuhFZlAD2DVxD/L16WKAAPLzDqxD5I9m80qeK
CrvSAb2LJgc1meOjb/wXorhmnMHsM/fofi3A1eHrIflhjiq/FhQT2xezxw3qDU51rOo0TJRQK5EN
LZrIX64ITdqs79LobuLVpbxGPDBeXkpGUtiTyCt02Ir/Um/bpjWT1SAgfm9xYBdgeHDm+DknL0Ya
nOkxFqsJuq3QF/zrOeD1v1RGmCyPasGul8gq5guUihOMx8xd4X9lUCrIZO1jLNW9B/zidj0cuCpR
BCKtqkDihnsoM0vhJwkTmIkY3nTjNqbBh4AzDPuABu5T4Ea/supcIQwfVSePCjzHI7YqHzFV6tcR
Uwuh1fd7mHl349wxTSoK1HOX+GkAm6j7fZ/u6sWiy71XrKluyvQLUS4pihqKVCflrL8vn7XffZTn
GgAIQA64U/f2walOwrADwGm77TMqkXGcv55ufFG/eeLkPeRJ8lUmuCNgjIuR6/xz97p/dz2v28+q
KASEYgvt1YbR3wmxHCSWdyrws3GbJJQrLFC7arB+LNFn2rPhwfAMBgrnVaUHc6okERZWPH+PO7Jw
6/s5AjaC+HGyg2rxmpm6RZnfP0ST/OebftEe10BQxtJGJ1U6Q6rOQCRNB4Zf+/nfbkk+gryLwxu5
B8vWjhjj6kweysvV6bVZwlY6VCQjZ68RuXwidCwjReOgduf7aUUeQTnUQ/WiRRSosSi7QO8iVrbh
q2FMfvV9qkcvm+INuX+L6vRXywpf+el5abkwiiOI8mI9wPZKLpPQygN1HNjrqnDxDDDTArBmL3nN
c5dPT4uJtmO0onGtMqLu9FaW5G6qxteQoPwQ6Qm1qgZCUCMFw5tCP/I4LKh5vnsGhunqGDQtPxFd
M1yYDRQPOxI4WIJMG71XY1eGpBkJOILvlZ5U1ArbAMWRIg4IbUacIQYUhLNva+xLf6423fRnyshY
V2rnaO++27GxB2TT4jB9ugO1sWf/xLeK1O2Sdb4IYmPE2/CcaK9o6w1Lt8Wmziqaf8MaVVpcaahw
8vuL+nLq6p4Z+t8dBZ6f8TDW9ILrWtrkGAxheR7lNGCee2xA4ydgOj8p0fx5VvRsRzJBijjnK54w
KKwfgZgC8+6y+u8sQ+qM0bvyPJ5hl3kumsnxPgZKUUjy4n9eLixRuKFoylkkMemAUrq3TZC8l/Ga
jIWI1BcToViB8BNKV85EwL8WA8V/d9SQ3ScP6HsDl7nXgmnDOt3QMwt9g2XLGDbLwj1MTrXnWTA/
0Qkyw2UAbAH9vMAQDSvhC1m1VWUxQBDeifwwBsvXHmPd2Qn+LoVg6P/9EsS/OQplE/11l6iee+wl
elLFmbIYjQPvGEANgcEKiA4/piT/usBPvM/4gE+Zyf4mQTaznxOyeNALv35w7EVvIZHvGpmrd9ZS
qM/KfMtJsvidg+A6KBxGgc1iuAyrQ84jmSn+l6rMVciQ/AFvMREMfwuDoXAOEkiKg1PHP5roauui
E0gK6ViEmjZqk6wBKv73bO+JpTxn9dkRMTJuKs3Q9sV7VdAaZJ4Qg4qHHkeFnkgcW3Yzh0ScXR9r
HLgAL1Me/0r7T7JNv9MKrg7LhRiKeXXK2B1qK72xJcxmmptcF9fTgy7BdJmCVkjpXPj7+FdUZjzN
2HGfN5W8ksCXD4Rqq+p+GOPg/1BlzaOQzpDDsuv3SIAWLvssMzHmd72uE2gSuWf6A9NI3GfLoOx+
qr0rY9NLJHW38yIDDrWCLA/uMwWsGRA3uNqnS5vvhyfTpuAhWMDW0Fo+pqPH8TmDEp958tEIWAqj
jSfgAhitHnCxKMMNjGphSYMLYKfhMZFtd1a5w5t41ODM6OY3ImDOQCSyHRka+moTlZ9WyNcpRlQ+
jb9EKoWc5CdWa3fycNieTSvTRgiaRlUK8x2Xbb1tZ2AKPlNNFhhhE19sMK/yodKDT99SP6g2LGh7
Z2lU/QJ/XuGyFGcnEK+KImlhiSHn57AMjnFcGwjFapY7NTuaZjh8VBNRJBXtgPcKw3tVjyuj80io
DutxGfvjFqELkKV/JnAxplVZAA2CCDLIqh7XqrVB8IvszpbKGyGQA2bR4OJbaJRAz6C7wcqfDvlH
HwWT1rr5s8sDmrqMI/KxL0MLkUca8Fscqj489seKZpu1XdAnH0jSIaVt04aMfZpz09uMxPs7JDkP
kvuGWJnLvopwzAZKC4EPIV9uVzsF7Oqko+HHQIWcBLu4w16Xhpiln9f1qQOEgnyW9W0h5eIudTtv
5YBHka1wlFD3mK/ettnMQW9gDqcazxRa0DNIRxwhB9VGRN8pkJfuDrwX2TO5fK2PYaINU7UOsCUX
ak4tlkDntsu29LC4wHR4VBJbmqlO4+bVQgc/EXa+t999JD9/awbk01Q2qDJglVup/EqyJi4g4Bf/
lRKdc1Kc6pCo+9Bsmv5HjDEYZ8Ub87IddovrmR4AvTIr5gSNU/L+LgdGiM6nKUfK1/kQLfsxq8kS
fsP+/oBf8ebUiHdKkR5L5SMUQWFSp/kNSWlLaz4WwaJOBk5fq0RQDWZ6qvXq6bBe11fpkOwiCXOw
WGMS7I+pApwrbHgRgNtPKQTn0epcoEUZT5KfGr4NGKmuZV2qlV4nIJOjZH6RiXQrjCJ1FrrAU8Uw
U5AXTaNy6qy9hzR67sAbhhmyEQdWF9RkWtSI6w8nKoXkQgKSZMo/vaueAJ20eaG5/h63ev155DT1
PT+9OqEuqGnaCI8Xiy9DGND6fH0aheRhpag2Q4QTzHcxhzInTJu1fiGqC/ZxSCYrgZTeu2O9dkJA
nojHewRADx9pUwy3nn9Z8HiITSC+nhd4JbtbAY3PhbjySUJYMdmoz/aQTQZhFt45V5/gNcov9TFC
tNAnIpp5cBaftNNmhCEUGcYeh61ZlkD5c1aLxvgFCdCDjrCyMsbHtS83UhYZsBAKNl9hGx43eS+p
CdI4rZERQ85XlWiwfZaS4P3SnhAKqk3eG4KH6BSEwoVCJi4LzLWe+ifgabGXCcrzKc4kDs/o7D/U
GrBybWZQF4htP1KT87y9XYIRIBBzzQC5xQPTkyaAdmmlULORjEp5uxObLODCCdOaRMJzfDj04cV2
GCpBzz4KG6oI27B0Ct/zA6cpJqu/G4Bpf8NzReVUD7jziggPcnZjWbr2qIGJ6Wc8o4uU82uFH4oa
b1dV0IY5pm5NzXqWaOSyJlOYiHwyZPkedNfRyXnfg+9C7vrzXgNiJ0LJo8mhBDPOC7O5mga1PLPm
+SjXPMoqBdknp8RrSF8Q8uRn/GN+WeoukdbIpT1HyH8NqsBtLc6UsZ8WB1V+nFZv8cRIQ34RYfqw
AlgsVNeLBZ+oA/XLSKOO/pC4XiHINgCs78fqiijwG/+BtpISNl7OIuwFLOd58xEsyTLPVXUrpXnE
wzDr+/pFI+MkgggKrF3IHp7AHux+oCvPsc2MYl9kh0e3H9al3wLRXXjNRZDvLVGbWmbzP+tiZok1
132kDRbYHTrder1Vs0vlnQBwG3Lcm2aAdsIcVJnn7yBXqvGrrPTJnqb3DS5eaF4+qxklzHmeQCti
CqvlC5QN8aCJQR0UrsqYvZMFTA2OUqfsTiQeKrD0Ar1kIPytCTK38T0tZ6KN/9Qh2fa3tbr81heD
4fTwAr5wB3ZbxoQrVeqDEbRvwYwQ9kWs5HK0UQNL2OhzRlc3IDJaKSG3HJeOCEeERuw+1dZheChS
5AAR9Wk1t6eTYhiz9CdT7+0XyaOgLlTFGQXYZZtJ2ljYrXUmhXedKAJX0O9Nu0WTsSi7kFD5o+97
IuUltHjVDCxA6TUpKQQRaW84lbgplwwR4QydLkUoSGWzr9vMnSl4Bj8v4aODldmvJCEMhwQk6u5T
lHI7nsZ59/ags/qQbL7PzqIgs6A+gBse+Kj5sLK8GaNa64rs7Z94e1AIGdghyNb7H6Gm0j+DEI69
XS1i3kXBlIsSHJ5NAn30YFWegQ3CJMf42qi79f9iW2jZ16iDEDJPrUXUjneC88pgskyRXkhGUoUR
6AnGHLpiHQe0gek/FSWBBr3tmMG2OoYjqB3fUNMm9OcYn2tjYkkf+Da+3ri96M9ciILwGTg4GdfN
h2QR36u8CB2i/jvEx/c/gZW25ZAt3xAgka8uMcWuhNL3nB35OX1EDTl7pL84t60jmQP+tyXMYbXr
+savux1RUOHo9IoiNZyJnuHwGede2T8v7saNYFcNqoJbRqe1MmTAZAAFztHzh64B8qBSzhJpri5y
mT+P2v6IO8AphetD1975kJP2/HRJWCajc5LE/O9aVnVmPeK6y5catj65WsEBJ7cdLpV9/w93H4qZ
4Fuov5j9dTXxNJ/+RMuLflGL5WYHzzj9/Xx85KOCIrE1Na3BnWzAz9wRVo5uxdyRAWCO3iELw8te
W9HWsyaJ8v2bU9Gn7OoJ4Rv84zpgqt+x95a7Mmms5oN4HbBpkHmznItERbWUdaMLA8sFVcmdxcNM
1uxCeogMhtPUfajivxbse3Ta4z9XCabelkPC5MVFys8nHEPcos5o2g3y8vCADJJoT3FNC/WmdQQe
/vhjrw9RTdA+hgUoNVRRUaAb3Wj18WfcmG2bRo5lDG7wVda3ZqNDgl5i61KXA9pnZVv4OyVwofZT
H2PAtJN3zgVhTIu+BofRkZ6irX5e3j38Z3yOgcZVqi1ZNQGFWH+kVX8tardDIB6BYgxloo6p03HP
s6BOrTx9Safaq73srHcfO0MBIkiSmo5Pkog3IIs9cJNv3Kj9K0mN/Fkrei0XRDwW5NCUhaHdGkxb
oRrWDtF1mMEBYZMdzFkoaPTpQImblsQEVWhXqPW5stn7b84el05Mlz+ZmY4Q9s5/5aNg97wORJwf
BDWudVkUnCkMwSwKW6ie/fNtv+LpeoGsQ7gQCgQbYC4vtvl11Qltuq7R6FNHY5e5cuPTlyDlX26X
BS6IQ2esdp5dcwn4cjoTmXME7tZyFqsOHyZ9e+oW/5Ve/8mfAqzVUdiFDjtlsiJNOwt1zyRBJcM3
TsY3IGJtRqJozXPtbfnNZyVUT3F8n+udwrauN++wgnbvYOVIFzI6BRIihXwfPTqJd4068QjDyZq8
6JzqstJBB6YDXG/l1Aq7CN+miCNHhSMobZbTdP4Su+tfhVdEMZNUR1Hs1r6hs32IwBPO0EPYfvgP
m+etOTkB+atTgfWrTs5EjHkvyBByoffnmVJgp2zhHt/4wtjKgYp/1Egs1pCP73a/CZP1xdLb7GOk
3hnkY9pAFMcpZ/9vNRR6ixwWEdBYv+OpNIZbFDVySBxO4A3qbQuF2kP32lXW7kTic6xhknPKDTnr
fknOAMPOiH3vSJyft54CtIPa8qmC2LHAB514+S+9WU1Rq/kI8gqf0TFFIREOL42ld2DkoaKFDyzX
lXv7W5pizy38NhMzkSLUvUNWzRqsXHDzYmb7wn/LXd8PmW7EXnZcQXWvhn7X3BjdlaFXjiMvzs3N
h3812Xw03tuJC1AFiPdQZXSkJrwGD2J1803sL9EmxrvL78m9Y02Iu56WPBZolhMIZZFGw8mBZQ77
3ANqsEFcVePlTNPlby6tNdj3xWXKntG856rBlKrUpubtBN/bp2S2JQJdhMLEMGGHrNEKavm8wfXj
fpUohgB1KaKeYqhcq3/XulxsHmDWJ9ulrcu0r5u+ZXwQAD/QVyEAFDGCK04QTh5+ZH9MivQpGlvd
OROei74TFrXz1MbBcBPMwx5XTl8rHTZ5cpeWe/4VLugQ9YmTXzl7v8ReBvLhiZ5vcLMf1eS4+1j+
1Mq0wBuDkKQaJYb2XDDOyHgBWHede10/hGsY5AokMdRXZn7cnYxeb4QVTF2A/LXJz8Mi7eSe4t+K
tjYAUTS0TUJnVSkD0UAwLb34+7so762FHD/oKfMevWr8NIUXU0zuE4A0FstqldlzUkuo8re3gtSw
oYf14YpsGG/wJUezXIb8WsOR4+ak26rVB7/5AXcgWmBYDesgbIzniShjk4ECcHM/SHbNDDNkpJkm
wsgHjk8ays6+n7wUbdIBp+Dccj0H8avp9kRP5LXDYRn2kwPbNsQKQxIiYBfeuMcS412B3n2s3+yp
lfMz+crYjJbx/LghlRk3JrXSIPnkTvEhL5FRgK1pCEGODlzV6ASvozPQ60VFU4MiieBKYIU02ZR/
YmwQqsgglyehy2iWNLJLPUdcxOByyYsbxLxRoBAAGzNgc105BTBsyUSGXrN3lVFPeeFw1+i+4wv/
uQtS0WVywtvVgZQQGyXHLoVeVjn1LXrj5dsbbU/EoxXG5dtABEc3Yi+KZheb7GhWUw71Km+WQST2
DSvA0qmd4b8E0/jxpP+yInwJ38WNm1at6U2DAAvP2ecwUMyeKLbGKfV33MoIzTTADcZ96bbosqr+
yAyabbhlVw3MiZlgOKdz6NADTGcZbpoHTgLEz21fOi9gSXHLBypaSeIeiPSSKiHoUG6rfT+xeHaI
lSkflK1/LPE0yVDq3/QRUECOZ07hdizcbR7ulT8JgzboDIZ7FVLKB6KiDTkyPFdXYSWYBpXaMz8S
UDgNb+u0V9GcsaAgt8P/YLAqqsOyjQ4hDZTpfX+8r0J5jZCxRhjs7g4hWFt4zoNg7fKsUKb2WHOw
s6xDIiFXt6ZvnglPLf7mztJM6UCi/INx+o+O588z0aq2wWPCJ/FIBSxa0TqXoqFuIx184iZPCEQO
GDkvRxGc3XVeWk9Q6+x09bbFpfHBf+KkHTMWWT/nVgoDR4YjicBUp65bE4zscooXsEFWsXjVAzez
F1ekZwnKbz6W1yJR3m0ZHddvvqzxry7Zk09nbZ3tUtpff9HSKTelWdq7MCX6Zueh3DOogTS0dce2
76JnSeskSbsIzr6LFMyt6bOLQHBIVDCrN2t8xCc4cA8LoQZwmVimDkGJHLd5aqMlstFpV48QT0MI
xDGjSLXFnUtkdMh1zWxU7LrSEX3T9ABeltXl2KqGCu5M9oxblbLXPZ1apcJ5Bc6KdTC/I6k0Q7eP
jJdReZzwoxeqp8r31kYcubZnfTJY96nk1RQk4gxrLFqfVaEPKlBL41Tp/bz2UApm3441qak+CzLL
1uqNuOEKLClIYuTugriZt5JqrEbDuXwmxIEN0YGiC1RmCh7QouFyi8vmdONtkE6YFo3K39qx1DW0
WU1cAHek8vy92XhjlG4BxH4S0O6ph6tADVvHXWlaB5pLf0LH9qN9oVDwUW1lQe5beNtku7uv8yzf
3HZ54j0tHK5bkaRk4mbBdWhU7feKbDuZw0yQZAhOoF8fonO5WymEejpNYA/PR3CGf/M5mvagZVO2
EdZBii22fbyJ/PE/LBg6PIPSEHVZmNNxFBX5Gt/ZIbH1spzBG7O3V3vwMojWYsbccod2zB+gakLm
1CjYH7FQuegwuG0yNav7hQUwtCBjo/5eX01mXVD01aSw5l+bC43k+AaixdWA1TUMIyT/2Spx9huM
ZM57oT0YeRD9zsmgCHNuA4PvuUTn4n8Lt9KSv3rPrOA/nU3F9B4ciEgPRjJwO/CLKnsgNQjlduaB
mzrS5q2y0st5l2EoxmaVzrS4QxWJhKrDUrIeKHlne04mED+8jZgKlf1Gm13xkOswJteN/O7/atoX
cMl3Df5H1/aEMUNgDM6Woc/d2flyfdeKJ5DZy+RDrFI5kP7L27Htl9YOV4LHUsyjp7DU1cTfuCK6
YMRGo+TXn8pxidwkljwQUFc3aRmTREnrvn9tO7N9MUkvfDmKi1l7DQhXQNPPwBF4fD2WgQ/dpG3n
RNWsy3jhzhtzp7qS1hZ57iSBIC3DoYEDIjab1H8ksjEnhgGO5pwsdhSFO5eNRWwcV16seb/5XrRt
lOwcqRA9bzjqB4wdLP+NBeu48iJzDlWfY1nqkYkulB6klKkkQU5Cea7/FE4rIokBnji61s+t7Lb6
t0FP+AmG+I6jybwOzXPpgrJ17QoK/aRS1/swHUz4fx40bBItzGU7/NJOCFuQOBqM8e3qsvIjgajN
QTxblZmKjAhceJvrbDHe66dcTPKjNqVXA41mknrVZsJdc6nfaKFoeePuB0EgU30dqn62t1kUWK+j
yERwtrhpDNZCaY0sITEKpRR48BCd3UT60S3HG8mAyWvPEHnsYErj+yqb+T9HNdzX02DXwQeqrdsO
Ucv60mHWov5V/WIEl7MnrgAbbPhJ6SrgRJ6L7hFpOJFdRhMoEusB/pNrPJIGPNihOYAKvp6gd16W
ZfP+6Y+3kd7G9ykkrd2rcDQ+SYZnK3gqz83G9hIwOH6axLGpFT1QheLUE2ZJewKQb3+67uWXvU06
ct+mzCHzz70kvOQtH5b6Dq4zg72lBK6Nzi9S6LwQvBcehop3k0tZ9H/Hf84nIX9YflieQ/FofBMu
26nNflsT2p2Kat6WBym7cVmuuRobfKWl3Hwk/d+jUqAoxLc3MUeZIpbdeTbD2QpWeGpolpBCIYHN
5K54whg6rLnsZCcnG/O9frqqYeEb3EN4QBsWdm+xDiUv2F9kiMtOp9SLSK6lqBxQxDB1hHsoPyZ8
uq5q7aKdKUC+XwJKHoOPRXhC3t3MNO3WDmuGsJ+ektnT+OowH943xBV6EIbgsnk/uPn3tQnmZVTZ
wCTE/1x6qeUWfCN799+mifkygAn/8+6FQI+2QLlZ3SW0gYBn/VrPWx6rR0Spz6FGlFJxPY7zYA/N
xTgqagrblMd/rKcPaa8r36M5OjxSwCGNZkgcDfqy/UQslbciHFsluWKhB0EjrQYNEdoQ71t9k3nx
EIjegV4TvdlCziRWo39uyLZ/3lInoxPOjdI8UdcUEYI+QPKdIuK04nKUYLIZTQsjKNDr13u6O+QQ
s1aMFjqI58xmQKKXLflOFxCrG/54tg8A+fO4jbbJo/KzRSYOwrh5hwkKuDBbMosDxC7cPttkUxNA
pFRlpmfiQdMbRk3hmBocHoo2xwaJEtq4C+VJ7FpE8Mkn0e/pfQpa7Rrh22Dl4LizpuU9T16uiGMt
NmSpALNeu50+Ch/pfEP+h9lnewCLISMwkuZsnALtqNkh3caLaQVlk+Z43IwcdbHX/LGkB/X7viD+
Y2Gzoi1/bwFhmOoch+IgvHarJZIqxqrgj8kWt0CjyINs/OWQhVW31Dqex0UZd+n9XYwIkRPzqADo
1g3HzpVMqhoy1fPW2tkRxm99QljBSml52hOukk+B2TrbmL1SmnJvVNDvM+CSYTlA4nIZpxfj15yN
T1IF8yagzqEp0u3Oc66bGTpo98nmwIyjNkYbTtBHZbAMnWa9IRXvzDayflSX/kpgSSM3i0FL9a/H
1E+SVlq8PbN3d+SN+rQQzR02vZOtLuGm7HmpJmapzsNFK/M4DVIKLJkoVb3R5U3pm0QMIgnpD2Jc
aaIJyaS28o5VTbk/wKFrwLcSvOBG0f3qBZdH9iV6YY5HvZdR1hK3cyYTeuYG0wGPISLQnlaRkIPu
6NSqo4zSAZHwUw0Q7IbgK5NkghqLKJFjPJs/gKWzGWz+pAznEyIbSnRFKbFEHdPugNkaCukqWKrs
4ITSzyME3SwMz8tnozJQm1b3SVL9voh2PZQqq5dmw8lKEe1jQ9ZbonDqZrTykD6yo1ViGWFS6QXS
gB7g070RoaM9WGFu0bNU+HyvnverZiPv7GQVL38343JdNjyIN+p4CZqWpw9dfEII4T4UCutj+6Ny
mM31dzn2SMim7dBLvlM7/LBc5iaIinVBuOeZ9uBOd4SYljDH6ZO3eZ9mINT6udBxXl78NQoHJkmC
1KA4jyWEPRqcYYthHvyNDrDDIDl6PJOKNlh7XePJrlCVTGmAieBBkLr17KAHcRlUxXgi9CNCxE8t
lp3016CZRXO9O2H6d+3QPzw0PJUzDtbyTo76nJgQNs6vO/PQyjPquZGuLHtZbyXWedf8diNSh8Co
Y6xWumWGMf6PyT4IKVcp3o/ycnGQ743MPDVPY/8BS2cbwiz0/N7HMW1nQOX3ttLjiwYVddvRHVu5
TWqU9sYbzY42UEhrMSa2MLEWMlJ7UsiBh2B5S+cOZG/xI07QCcHe1GtOnwAtroDUATX3LHDaadWW
xya5mDUuer9xDU29v1dhvYugp0HEjJNSmH7QkXvP5hZMGXwJvWZt9Jn33G/CdK6VH/4FxSibp07u
9nlcQb4PxjTfX49LGWVeSsl0Re8eBNJ4gHyitokk1qslGcegDp9tfbpk4e1rCOwvoLlgHQw21ncW
EPN5fLriqBTeZs/lzASSOvTpY+nx6/XpNG7ENvHxsYKjf+F2Xl5iLa/u2k0ta55R6DxoUcEW0+bQ
+cH2ap9APD3kT1xDhew7F3uFGEh9VqxmDo/yzDS0oBMiofazZTsjeLxbif/Oqg6jBHiCg6TtfNSE
Z6G+h7YMovXkXa7ubg/XES9WbddC1tUC2xrAOfWvnvHH1VIRvikpvg/qUr6D+j28S56Sig61w76k
R26fvnsTVGIqzMwjlsl7AVx3PeSOxvNQ6ixgKfq22INlE2i4y5ZD3kkTJ6dyHvAJLDJlJDwuqyql
4XAGncHLx+dRhEsuaTbia40FO77PqdWzhUfF0I2aJusFZEu2QEmgM6nhO30FVFklvk2mmxVSaYew
yh/YcQ3Zwt3KRVhSlAtzBOHfHPLTtUo8qCUdno3rpZ+oKfMylQXT5GtAKPkIOvjSSsM3hHcKy9T9
L0NnG2vnbny1JQ==
`protect end_protected
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/6d8f288943408fbb/zynq_design_1_rst_ps7_0_100M_1_stub.vhdl | 1 | 1958 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:29:40 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_rst_ps7_0_100M_1_stub.vhdl
-- Design : zynq_design_1_rst_ps7_0_100M_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2017.2";
begin
end;
| mit |
MarkBlanco/FPGA_Sandbox | VHDL_funcs_and_procs/VHDL_func_and_procs.vhd | 1 | 1453 | -- Based on tutorial here:
-- https://www.youtube.com/watch?v=j2lAPIjpF1w&t=309s
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library sevseg_package;
use sevseg_package.my.all;
ENTITY SEVSEG is
PORT(
SW: IN STD_LOGIC_VECTOR(9 downto 0);
HEX0: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX1: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX2: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX3: OUT STD_LOGIC_VECTOR(6 downto 0);
KEY: in STD_LOGIC_VECTOR(3 downto 0);
CLOCK_50: IN STD_LOGIC
);
END SEVSEG;
ARCHITECTURE MAIN of SEVSEG IS
SIGNAL NUMBER: INTEGER RANGE 0 to 9999:=0;
SIGNAL PRESCALER: INTEGER RANGE 0 to 50000000:=0;
SIGNAL SEG0, SEG1, SEG2, SEG3: INTEGER range 0 to 9:=0;
BEGIN
-- Call package procedure to assign values to each 7seg display.
HEX_DEC(NUMBER, SEG0, SEG1, SEG2, SEG3);
-- Call function to update each hex display.
HEX0<=INT_TO7SEG(SEG0);
HEX1<=INT_TO7SEG(SEG1);
HEX2<=INT_TO7SEG(SEG2);
HEX3<=INT_TO7SEG(SEG3);
-- Define clock-driven process:
PROCESS(CLOCK_50)
BEGIN
IF(CLOCK_50'EVENT and CLOCK_50='1') THEN
IF(PRESCALER<100000*to_integer(unsigned(SW))) THEN
PRESCALER<=PRESCALER+1;
ELSE
PRESCALER<=0;
end if;
IF(PRESCALER=0)THEN
IF(KEY(0)='1')THEN
IF(NUMBER<9999)THEN
NUMBER<=NUMBER+1;
ELSE
NUMBER<=9999;
END IF;
ELSE
IF(NUMBER>0) THEN
NUMBER<=NUMBER-1;
ELSE
NUMBER<=0;
END IF;
END IF;
-- Does lack of else here cause a latch situation?
END IF;
END IF;
END PROCESS;
END MAIN; | mit |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/fifo.vhd | 3 | 1952 | library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width-1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output : out std_logic_vector(width-1 downto 0);
output_stb : out std_logic;
output_ack : in std_logic
);
end entity fifo;
architecture rtl of fifo is
signal s_output_stb, s_input_ack, full, empty, read, write : std_logic;
signal a_out, a_in : integer range 0 to depth - 1 := 0;
type memory_type is array (0 to depth - 1) of std_logic_vector(width -1 downto 0);
signal memory : memory_type;
begin
process
begin
wait until rising_edge(clk);
if write = '1' then
memory(a_in) <= input;
end if;
if read = '1' then
output <= memory(a_out);
end if;
end process;
process
begin
wait until rising_edge(clk);
s_output_stb <= '0';
if read = '1' then
--data is available on clock following read
s_output_stb <= '1';
if a_out = (depth - 1) then
a_out <= 0;
else
a_out <= a_out + 1;
end if;
end if;
--if data has not been read, extend strobe
if s_output_stb = '1' and output_ack = '0' then
s_output_stb <= '1';
end if;
if write = '1' then
if a_in = (depth - 1) then
a_in <= 0;
else
a_in <= a_in + 1;
end if;
end if;
if rst = '1' then
a_out <= 0;
a_in <= 0;
s_output_stb <= '0';
end if;
end process;
full <= '1' when (a_out-1) = a_in else
'1' when (a_out = 0) and (a_in = depth - 1) else
'0';
empty <= '1' when a_out = a_in else '0';
s_input_ack <= not full;
output_stb <= s_output_stb;
input_ack <= s_input_ack;
write <= s_input_ack and input_stb;
read <= ((not s_output_stb) or output_ack) and (not empty);
end rtl;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab2/fir_prj/solution1/impl/ip/hdl/vhdl/fir_shift_reg.vhd | 10 | 3079 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fir_shift_reg_ram is
generic(
mem_type : string := "distributed";
dwidth : integer := 32;
awidth : integer := 4;
mem_size : integer := 11
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of fir_shift_reg_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "select_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity fir_shift_reg is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 11;
AddressWidth : INTEGER := 4);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of fir_shift_reg is
component fir_shift_reg_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
fir_shift_reg_ram_U : component fir_shift_reg_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab1/fir_prj/solution1/syn/vhdl/fir_shift_reg.vhd | 10 | 3079 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fir_shift_reg_ram is
generic(
mem_type : string := "distributed";
dwidth : integer := 32;
awidth : integer := 4;
mem_size : integer := 11
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of fir_shift_reg_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "select_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity fir_shift_reg is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 11;
AddressWidth : INTEGER := 4);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of fir_shift_reg is
component fir_shift_reg_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
fir_shift_reg_ram_U : component fir_shift_reg_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/b32f033de8d0536c/ip_design_zed_audio_ctrl_0_0_stub.vhdl | 1 | 2512 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:13 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_zed_audio_ctrl_0_0_stub.vhdl
-- Design : ip_design_zed_audio_ctrl_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "BCLK,LRCLK,SDATA_I,SDATA_O,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[31:0],S_AXI_AWVALID,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_BREADY,S_AXI_ARADDR[31:0],S_AXI_ARVALID,S_AXI_RREADY,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_AWREADY";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "i2s_ctrl,Vivado 2017.3";
begin
end;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-5/src/Task4_TB/Task4_tb3.vhd | 2 | 6048 | -------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4_TB\Task4_tb3.vhd
-- Generated : 10/18/14 16:15:19
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task4_ent_tb3 is
end entity Task4_ent_tb3;
architecture Task4_arch_tb3 of Task4_ent_tb3 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task4 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task4;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task4
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test reset - state(i)
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 11;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 12;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 13;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 14;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
-- Test length 15
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task4_arch_tb3;
configuration Task4_cfg_tb3 of Task4_ent_tb3 is
for Task4_arch_tb3
for UUT : Task4 use entity work.Task4(Beh);
end for;
end for;
end Task4_cfg_tb3;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution1/impl/vhdl/fir.vhd | 9 | 14661 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (31 downto 0);
y_ap_vld : OUT STD_LOGIC;
c_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
c_ce0 : OUT STD_LOGIC;
c_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x : IN STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of fir is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.714000,HLS_SYN_LAT=45,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=329,HLS_SYN_LUT=214}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal shift_reg_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal shift_reg_ce0 : STD_LOGIC;
signal shift_reg_we0 : STD_LOGIC;
signal shift_reg_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal shift_reg_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_130_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_reg_178 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_1_fu_142_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_187 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_134_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_fu_123_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_1_reg_206 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_211 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal acc_1_fu_167_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal acc_reg_89 : STD_LOGIC_VECTOR (31 downto 0);
signal i_phi_fu_106_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_102 : STD_LOGIC_VECTOR (4 downto 0);
signal data1_reg_114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_148_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_153_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_157_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_123_p0 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component fir_shift_reg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
shift_reg_U : component fir_shift_reg
generic map (
DataWidth => 32,
AddressRange => 11,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => shift_reg_address0,
ce0 => shift_reg_ce0,
we0 => shift_reg_we0,
d0 => shift_reg_d0,
q0 => shift_reg_q0);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
acc_reg_89_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
acc_reg_89 <= acc_1_fu_167_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
acc_reg_89 <= ap_const_lv32_0;
end if;
end if;
end process;
data1_reg_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0))) then
data1_reg_114 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
data1_reg_114 <= x;
end if;
end if;
end process;
i_reg_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
i_reg_102 <= i_1_reg_206;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_102 <= ap_const_lv5_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_1_reg_206 <= grp_fu_123_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_cast_reg_178 <= i_cast_fu_130_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0))) then
tmp_1_reg_187 <= tmp_1_fu_142_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
tmp_6_reg_211 <= tmp_6_fu_161_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_fu_134_p3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
acc_1_fu_167_p2 <= std_logic_vector(unsigned(tmp_6_reg_211) + unsigned(acc_reg_89));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
c_address0 <= tmp_5_fu_157_p1(4 - 1 downto 0);
c_ce0_assign_proc : process(ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
grp_fu_123_p0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state3, i_phi_fu_106_p4, i_reg_102)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
grp_fu_123_p0 <= i_reg_102;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
grp_fu_123_p0 <= i_phi_fu_106_p4;
else
grp_fu_123_p0 <= "XXXXX";
end if;
end process;
grp_fu_123_p2 <= std_logic_vector(unsigned(grp_fu_123_p0) + unsigned(ap_const_lv5_1F));
i_cast_fu_130_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(i_reg_102),32));
i_phi_fu_106_p4 <= i_reg_102;
shift_reg_address0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3, tmp_3_fu_148_p1, tmp_4_fu_153_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_address0 <= tmp_4_fu_153_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_address0 <= ap_const_lv4_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0))) then
shift_reg_address0 <= tmp_3_fu_148_p1(4 - 1 downto 0);
else
shift_reg_address0 <= "XXXX";
end if;
end process;
shift_reg_ce0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_ce0 <= ap_const_logic_1;
else
shift_reg_ce0 <= ap_const_logic_0;
end if;
end process;
shift_reg_d0_assign_proc : process(x, shift_reg_q0, ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_d0 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_d0 <= x;
else
shift_reg_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
shift_reg_we0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_1_reg_187, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_we0 <= ap_const_logic_1;
else
shift_reg_we0 <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_142_p2 <= "1" when (i_reg_102 = ap_const_lv5_0) else "0";
tmp_3_fu_148_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(grp_fu_123_p2),64));
tmp_4_fu_153_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_5_fu_157_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_6_fu_161_p0 <= c_q0;
tmp_6_fu_161_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(tmp_6_fu_161_p0) * signed(data1_reg_114))), 32));
tmp_fu_134_p3 <= i_reg_102(4 downto 4);
y <= acc_reg_89;
y_ap_vld_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
y_ap_vld <= ap_const_logic_1;
else
y_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab1/fir_prj/solution1/syn/vhdl/fir.vhd | 9 | 14661 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (31 downto 0);
y_ap_vld : OUT STD_LOGIC;
c_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
c_ce0 : OUT STD_LOGIC;
c_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x : IN STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of fir is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.714000,HLS_SYN_LAT=45,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=329,HLS_SYN_LUT=214}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal shift_reg_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal shift_reg_ce0 : STD_LOGIC;
signal shift_reg_we0 : STD_LOGIC;
signal shift_reg_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal shift_reg_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_130_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_reg_178 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_1_fu_142_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_187 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_134_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_fu_123_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_1_reg_206 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_211 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal acc_1_fu_167_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal acc_reg_89 : STD_LOGIC_VECTOR (31 downto 0);
signal i_phi_fu_106_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_102 : STD_LOGIC_VECTOR (4 downto 0);
signal data1_reg_114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_148_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_153_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_157_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_123_p0 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component fir_shift_reg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
shift_reg_U : component fir_shift_reg
generic map (
DataWidth => 32,
AddressRange => 11,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => shift_reg_address0,
ce0 => shift_reg_ce0,
we0 => shift_reg_we0,
d0 => shift_reg_d0,
q0 => shift_reg_q0);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
acc_reg_89_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
acc_reg_89 <= acc_1_fu_167_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
acc_reg_89 <= ap_const_lv32_0;
end if;
end if;
end process;
data1_reg_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0))) then
data1_reg_114 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
data1_reg_114 <= x;
end if;
end if;
end process;
i_reg_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
i_reg_102 <= i_1_reg_206;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_102 <= ap_const_lv5_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_1_reg_206 <= grp_fu_123_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_cast_reg_178 <= i_cast_fu_130_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0))) then
tmp_1_reg_187 <= tmp_1_fu_142_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
tmp_6_reg_211 <= tmp_6_fu_161_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_fu_134_p3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
acc_1_fu_167_p2 <= std_logic_vector(unsigned(tmp_6_reg_211) + unsigned(acc_reg_89));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
c_address0 <= tmp_5_fu_157_p1(4 - 1 downto 0);
c_ce0_assign_proc : process(ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
grp_fu_123_p0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state3, i_phi_fu_106_p4, i_reg_102)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
grp_fu_123_p0 <= i_reg_102;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
grp_fu_123_p0 <= i_phi_fu_106_p4;
else
grp_fu_123_p0 <= "XXXXX";
end if;
end process;
grp_fu_123_p2 <= std_logic_vector(unsigned(grp_fu_123_p0) + unsigned(ap_const_lv5_1F));
i_cast_fu_130_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(i_reg_102),32));
i_phi_fu_106_p4 <= i_reg_102;
shift_reg_address0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3, tmp_3_fu_148_p1, tmp_4_fu_153_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_address0 <= tmp_4_fu_153_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_address0 <= ap_const_lv4_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0))) then
shift_reg_address0 <= tmp_3_fu_148_p1(4 - 1 downto 0);
else
shift_reg_address0 <= "XXXX";
end if;
end process;
shift_reg_ce0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_ce0 <= ap_const_logic_1;
else
shift_reg_ce0 <= ap_const_logic_0;
end if;
end process;
shift_reg_d0_assign_proc : process(x, shift_reg_q0, ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_d0 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_d0 <= x;
else
shift_reg_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
shift_reg_we0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_1_reg_187, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_we0 <= ap_const_logic_1;
else
shift_reg_we0 <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_142_p2 <= "1" when (i_reg_102 = ap_const_lv5_0) else "0";
tmp_3_fu_148_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(grp_fu_123_p2),64));
tmp_4_fu_153_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_5_fu_157_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_6_fu_161_p0 <= c_q0;
tmp_6_fu_161_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(tmp_6_fu_161_p0) * signed(data1_reg_114))), 32));
tmp_fu_134_p3 <= i_reg_102(4 downto 4);
y <= acc_reg_89;
y_ap_vld_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
y_ap_vld <= ap_const_logic_1;
else
y_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/TestBench/mrom_TB.vhd | 1 | 1381 | library stack;
use stack.OneHotStack.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mrom_tb is
end mrom_tb;
architecture TB_ARCHITECTURE of mrom_tb is
-- Component declaration of the tested unit
component mrom
port(
RE : in STD_LOGIC;
ADDR : in mem_addr;
DOUT : out command );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal RE : STD_LOGIC;
signal ADDR : mem_addr;
-- Observed signals - signals mapped to the output ports of tested entity
signal DOUT : command;
constant WAIT_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : mrom
port map (
RE => RE,
ADDR => ADDR,
DOUT => DOUT
);
-- Add your stimulus here ...
main: process
begin
re <= '0';
addr <= "00010";
wait for 1 * WAIT_period;
re <= '1';
wait for 1 * WAIT_period;
addr <= "00000";
re <= '1';
wait for 1 * WAIT_period;
re <= '0';
wait for 100 * WAIT_period;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mrom of mrom_tb is
for TB_ARCHITECTURE
for UUT : mrom
use entity work.mrom(beh_stack);
end for;
end for;
end TESTBENCH_FOR_mrom;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/d5e322d2745b1271/zynq_design_1_axi_bram_ctrl_0_0_sim_netlist.vhdl | 1 | 330319 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:41 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bid_gets_fifo_load : out STD_LOGIC;
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
axi_wdata_full_cmb114_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[11]_i_3_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC_VECTOR ( 11 downto 0 );
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair44";
attribute BOX_TYPE of \FIFO_RAM[10].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[10].SRL16E_I_i_1\ : label is "soft_lutpair54";
attribute BOX_TYPE of \FIFO_RAM[11].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[11].SRL16E_I_i_1\ : label is "soft_lutpair55";
attribute BOX_TYPE of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair45";
attribute BOX_TYPE of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[2].SRL16E_I_i_1\ : label is "soft_lutpair46";
attribute BOX_TYPE of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[3].SRL16E_I_i_1\ : label is "soft_lutpair47";
attribute BOX_TYPE of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[4].SRL16E_I_i_1\ : label is "soft_lutpair48";
attribute BOX_TYPE of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[5].SRL16E_I_i_1\ : label is "soft_lutpair49";
attribute BOX_TYPE of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[6].SRL16E_I_i_1\ : label is "soft_lutpair50";
attribute BOX_TYPE of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[7].SRL16E_I_i_1\ : label is "soft_lutpair51";
attribute BOX_TYPE of \FIFO_RAM[8].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[8].SRL16E_I_i_1\ : label is "soft_lutpair52";
attribute BOX_TYPE of \FIFO_RAM[9].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[9].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \axi_bid_int[10]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axi_bid_int[11]_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \axi_bid_int[1]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axi_bid_int[2]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[3]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \axi_bid_int[4]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[5]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axi_bid_int[6]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \axi_bid_int[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axi_bid_int[8]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \axi_bid_int[9]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair56";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair56";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[11]_i_3_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D_0
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(11),
Q => bid_fifo_rd(11)
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
O => bid_fifo_ld(11)
);
\FIFO_RAM[10].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(1),
Q => bid_fifo_rd(1)
);
\FIFO_RAM[10].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
O => bid_fifo_ld(1)
);
\FIFO_RAM[11].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(0),
Q => bid_fifo_rd(0)
);
\FIFO_RAM[11].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(10),
Q => bid_fifo_rd(10)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
O => bid_fifo_ld(10)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(9),
Q => bid_fifo_rd(9)
);
\FIFO_RAM[2].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
O => bid_fifo_ld(9)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(8),
Q => bid_fifo_rd(8)
);
\FIFO_RAM[3].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
O => bid_fifo_ld(8)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(7),
Q => bid_fifo_rd(7)
);
\FIFO_RAM[4].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
O => bid_fifo_ld(7)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(6),
Q => bid_fifo_rd(6)
);
\FIFO_RAM[5].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
O => bid_fifo_ld(6)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(5),
Q => bid_fifo_rd(5)
);
\FIFO_RAM[6].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
O => bid_fifo_ld(5)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(4),
Q => bid_fifo_rd(4)
);
\FIFO_RAM[7].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
O => bid_fifo_ld(4)
);
\FIFO_RAM[8].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(3),
Q => bid_fifo_rd(3)
);
\FIFO_RAM[8].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
O => bid_fifo_ld(3)
);
\FIFO_RAM[9].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(2),
Q => bid_fifo_rd(2)
);
\FIFO_RAM[9].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
O => bid_fifo_ld(2)
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(0),
O => D(0)
);
\axi_bid_int[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(10),
O => D(10)
);
\axi_bid_int[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bid_gets_fifo_load\,
I1 => \axi_bid_int[11]_i_3_n_0\,
O => E(0)
);
\axi_bid_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(11),
O => D(11)
);
\axi_bid_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[11]_i_3_n_0\
);
\axi_bid_int[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(1),
O => D(1)
);
\axi_bid_int[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(2),
O => D(2)
);
\axi_bid_int[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(3),
O => D(3)
);
\axi_bid_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(4),
O => D(4)
);
\axi_bid_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(5),
O => D(5)
);
\axi_bid_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(6),
O => D(6)
);
\axi_bid_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(7),
O => D(7)
);
\axi_bid_int[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(8),
O => D(8)
);
\axi_bid_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(9),
O => D(9)
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 );
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \curr_wrap_burst_reg_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair57";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(13),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(14),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^sr\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(15),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => \^d\(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^sr\(0),
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^sr\(0),
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[15]_0\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[15]_1\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[15]_2\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[15]_2\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => save_init_bram_addr_ld(12),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => save_init_bram_addr_ld(13),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => save_init_bram_addr_ld(14),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => save_init_bram_addr_ld(15),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A22200000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \wrap_burst_total[0]_i_3_n_0\,
I2 => Q(1),
I3 => Q(2),
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
I5 => \wrap_burst_total[1]_i_2_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCA533A5FFA5FFA5"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
I5 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800F3000000"
)
port map (
I0 => \wrap_burst_total[2]_i_3__0_n_0\,
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \wrap_burst_total[1]_i_2_n_0\,
I4 => \wrap_burst_total[1]_i_3_n_0\,
I5 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(0),
O => \wrap_burst_total[1]_i_2_n_0\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \wrap_burst_total[1]_i_3_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000000088008800"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(0),
I2 => Q(0),
I3 => \wrap_burst_total[2]_i_3__0_n_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
O => \wrap_burst_total[2]_i_3__0_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => s_axi_aresetn_0(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
axi_b2b_brst_reg : out STD_LOGIC;
\rd_data_sm_cs_reg[3]\ : out STD_LOGIC;
rd_adv_buf67_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_araddr_full : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
\rd_data_sm_cs_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
ar_active : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
brst_zero : in STD_LOGIC;
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 : entity is "wrap_brst";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axi_b2b_brst_reg\ : STD_LOGIC;
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_adv_buf67_out\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair3";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
axi_b2b_brst_reg <= \^axi_b2b_brst_reg\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
rd_adv_buf67_out <= \^rd_adv_buf67_out\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\rd_data_sm_cs_reg[3]\ <= \^rd_data_sm_cs_reg[3]\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0F0F0E0E0FFF0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080800080"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(0),
I1 => axi_rvalid_int_reg,
I2 => s_axi_rready,
I3 => end_brst_rd,
I4 => axi_b2b_brst,
I5 => brst_zero,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[13]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[14]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
O => E(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[15]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => \^d\(7)
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rvalid_int_reg,
I1 => s_axi_rready,
O => \^rd_adv_buf67_out\
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^axi_b2b_brst_reg\
);
bram_en_int_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(3),
I1 => \rd_data_sm_cs_reg[3]_0\(2),
O => \^rd_data_sm_cs_reg[3]\
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => \rd_data_sm_cs_reg[3]_0\(2),
I3 => \rd_data_sm_cs_reg[3]_0\(0),
I4 => axi_rvalid_int_reg,
I5 => s_axi_rready,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000E000F0000"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => axi_rd_burst,
I2 => \rd_data_sm_cs_reg[3]_0\(3),
I3 => \rd_data_sm_cs_reg[3]_0\(2),
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(0),
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"02AA0202"
)
port map (
I0 => axi_aresetn_d2,
I1 => rd_addr_sm_cs,
I2 => \save_init_bram_addr_ld[15]_i_2__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[15]_0\,
I4 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEFF"
)
port map (
I0 => ar_active,
I1 => pend_rd_op,
I2 => no_ar_ack,
I3 => s_axi_arvalid,
I4 => axi_araddr_full,
O => \save_init_bram_addr_ld[15]_i_2__0_n_0\
);
\save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \^axi_b2b_brst_reg\,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
I2 => \rd_data_sm_cs_reg[3]_0\(1),
I3 => \^rd_data_sm_cs_reg[3]\,
I4 => brst_zero,
I5 => \^rd_adv_buf67_out\,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => \save_init_bram_addr_ld_reg_n_0_[13]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => \save_init_bram_addr_ld_reg_n_0_[14]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => \save_init_bram_addr_ld_reg_n_0_[15]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3202010100000000"
)
port map (
I0 => \^wrap_burst_total_reg[0]_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => \wrap_burst_total[0]_i_3__0_n_0\,
I3 => Q(2),
I4 => \^wrap_burst_total_reg[0]_2\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A880A000A880A"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => axi_arsize_pipe(0),
I2 => s_axi_arlen(3),
I3 => axi_araddr_full,
I4 => Q(3),
I5 => Q(2),
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8088008880000000"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => axi_arsize_pipe(0),
I3 => axi_araddr_full,
I4 => Q(2),
I5 => s_axi_arlen(2),
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_arlen(1),
I1 => Q(1),
I2 => s_axi_arlen(0),
I3 => axi_araddr_full,
I4 => Q(0),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aclk : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_1 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_26 : STD_LOGIC;
signal I_WRAP_BRST_n_27 : STD_LOGIC;
signal I_WRAP_BRST_n_28 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_3_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one0 : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal brst_zero_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal pend_rd_op_i_8_n_0 : STD_LOGIC;
signal pend_rd_op_i_9_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[0]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[10]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[11]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[4]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[8]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_3 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of last_bram_addr_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of last_bram_addr_i_5 : label is "soft_lutpair23";
attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of pend_rd_op_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_8 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of pend_rd_op_i_9 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_4\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_5\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair13";
begin
Q(13 downto 0) <= \^q\(13 downto 0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => I_WRAP_BRST_n_26,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CC304400000044"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDCDCDDDCCCCCCCC"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I3 => end_brst_rd,
I4 => brst_zero,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808880808088A280"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_data_sm_cs(1),
I2 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I3 => rd_data_sm_cs(0),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A88000000000000"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => brst_zero,
I2 => axi_b2b_brst,
I3 => end_brst_rd,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => \GEN_AR_DUAL.ar_active_i_4_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => I_WRAP_BRST_n_26,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(11),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(12),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(13),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(10),
Q => axi_arid_pipe(10),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(11),
Q => axi_arid_pipe(11),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(1),
Q => axi_arid_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(2),
Q => axi_arid_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(3),
Q => axi_arid_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(4),
Q => axi_arid_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(5),
Q => axi_arid_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(6),
Q => axi_arid_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(7),
Q => axi_arid_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(8),
Q => axi_arid_pipe(8),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(9),
Q => axi_arid_pipe(9),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(3),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(6),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_23,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_13,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_12,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_11,
Q => \^q\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_10,
Q => \^q\(11),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_9,
Q => \^q\(12),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_8,
Q => \^q\(13),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_21,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_20,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_19,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_18,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_17,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_16,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_15,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_14,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAEAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(3),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(0),
Q => s_axi_rid(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(10),
Q => s_axi_rid(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(11),
Q => s_axi_rid(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(1),
Q => s_axi_rid(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(2),
Q => s_axi_rid(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(3),
Q => s_axi_rid(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(4),
Q => s_axi_rid(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(5),
Q => s_axi_rid(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(6),
Q => s_axi_rid(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(7),
Q => s_axi_rid(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(8),
Q => s_axi_rid(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(9),
Q => s_axi_rid(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp20_in(0)
);
\GEN_RID.axi_rid_temp2[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
O => axi_rid_temp20_in(10)
);
\GEN_RID.axi_rid_temp2[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rid_temp_full,
I1 => bram_addr_ld_en,
O => p_26_out
);
\GEN_RID.axi_rid_temp2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
O => axi_rid_temp20_in(11)
);
\GEN_RID.axi_rid_temp2[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
O => axi_rid_temp20_in(1)
);
\GEN_RID.axi_rid_temp2[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
O => axi_rid_temp20_in(2)
);
\GEN_RID.axi_rid_temp2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
O => axi_rid_temp20_in(3)
);
\GEN_RID.axi_rid_temp2[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
O => axi_rid_temp20_in(4)
);
\GEN_RID.axi_rid_temp2[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
O => axi_rid_temp20_in(5)
);
\GEN_RID.axi_rid_temp2[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
O => axi_rid_temp20_in(6)
);
\GEN_RID.axi_rid_temp2[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
O => axi_rid_temp20_in(7)
);
\GEN_RID.axi_rid_temp2[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
O => axi_rid_temp20_in(8)
);
\GEN_RID.axi_rid_temp2[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
O => axi_rid_temp20_in(9)
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(0),
Q => axi_rid_temp2(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(10),
Q => axi_rid_temp2(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(11),
Q => axi_rid_temp2(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(1),
Q => axi_rid_temp2(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(2),
Q => axi_rid_temp2(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(3),
Q => axi_rid_temp2(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(4),
Q => axi_rid_temp2(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(5),
Q => axi_rid_temp2(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(6),
Q => axi_rid_temp2(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(7),
Q => axi_rid_temp2(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(8),
Q => axi_rid_temp2(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(9),
Q => axi_rid_temp2(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(0),
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(10),
O => \GEN_RID.axi_rid_temp[10]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FFA0E0"
)
port map (
I0 => p_4_out,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
O => \GEN_RID.axi_rid_temp[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(11),
O => \GEN_RID.axi_rid_temp[11]_i_2_n_0\
);
\GEN_RID.axi_rid_temp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(1),
O => \GEN_RID.axi_rid_temp[1]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(2),
O => \GEN_RID.axi_rid_temp[2]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(3),
O => \GEN_RID.axi_rid_temp[3]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(4),
O => \GEN_RID.axi_rid_temp[4]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(5),
O => \GEN_RID.axi_rid_temp[5]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(6),
O => \GEN_RID.axi_rid_temp[6]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(7),
O => \GEN_RID.axi_rid_temp[7]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(8),
O => \GEN_RID.axi_rid_temp[8]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(9),
O => \GEN_RID.axi_rid_temp[9]_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[10]_i_1_n_0\,
Q => axi_rid_temp(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[11]_i_2_n_0\,
Q => axi_rid_temp(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[1]_i_1_n_0\,
Q => axi_rid_temp(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[2]_i_1_n_0\,
Q => axi_rid_temp(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[3]_i_1_n_0\,
Q => axi_rid_temp(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[4]_i_1_n_0\,
Q => axi_rid_temp(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[5]_i_1_n_0\,
Q => axi_rid_temp(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[6]_i_1_n_0\,
Q => axi_rid_temp(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[7]_i_1_n_0\,
Q => axi_rid_temp(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[8]_i_1_n_0\,
Q => axi_rid_temp(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[9]_i_1_n_0\,
Q => axi_rid_temp(9),
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
port map (
D(13) => I_WRAP_BRST_n_8,
D(12) => I_WRAP_BRST_n_9,
D(11) => I_WRAP_BRST_n_10,
D(10) => I_WRAP_BRST_n_11,
D(9) => I_WRAP_BRST_n_12,
D(8) => I_WRAP_BRST_n_13,
D(7) => I_WRAP_BRST_n_14,
D(6) => I_WRAP_BRST_n_15,
D(5) => I_WRAP_BRST_n_16,
D(4) => I_WRAP_BRST_n_17,
D(3) => I_WRAP_BRST_n_18,
D(2) => I_WRAP_BRST_n_19,
D(1) => I_WRAP_BRST_n_20,
D(0) => I_WRAP_BRST_n_21,
E(1) => bram_addr_ld_en_mod,
E(0) => I_WRAP_BRST_n_6,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_7,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_25,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_23,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\,
Q(3 downto 0) => axi_arlen_pipe(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_b2b_brst_reg => I_WRAP_BRST_n_27,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
rd_adv_buf67_out => rd_adv_buf67_out,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_24,
\rd_data_sm_cs_reg[3]\ => I_WRAP_BRST_n_28,
\rd_data_sm_cs_reg[3]_0\(3 downto 0) => rd_data_sm_cs(3 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_1,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_4
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8A8A8"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => act_rd_burst_i_4_n_0,
I2 => axi_b2b_brst_i_3_n_0,
I3 => \rd_data_sm_cs[2]_i_4_n_0\,
I4 => last_bram_addr_i_7_n_0,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"04000010FFFFFFFF"
)
port map (
I0 => \rd_data_sm_cs[3]_i_6_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
O => act_rd_burst_i_4_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCC55CC0CCCCC"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => axi_b2b_brst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => axi_b2b_brst_i_3_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088880080"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => rd_adv_buf67_out,
I2 => end_brst_rd,
I3 => axi_b2b_brst,
I4 => brst_zero,
I5 => I_WRAP_BRST_n_27,
O => axi_b2b_brst_i_3_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => axi_rd_burst_i_3_n_0,
I2 => I_WRAP_BRST_n_3,
I3 => \brst_cnt[7]_i_3_n_0\,
I4 => I_WRAP_BRST_n_2,
I5 => I_WRAP_BRST_n_1,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(5),
I1 => axi_arlen_pipe(5),
I2 => s_axi_arlen(4),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(4),
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFFFEEEEE000E"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => I_WRAP_BRST_n_28,
I4 => bram_en_int_i_6_n_0,
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF777FFFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D000F0D0D0F0F0"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => I_WRAP_BRST_n_27,
I2 => rd_data_sm_cs(1),
I3 => brst_one,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FDF50000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_7_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEEAFAAAAAAEE"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => bram_addr_ld_en,
I2 => p_0_in13_in,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"000F007F0000007F"
)
port map (
I0 => pend_rd_op,
I1 => rd_adv_buf67_out,
I2 => \rd_data_sm_cs[0]_i_3_n_0\,
I3 => bram_en_int_i_9_n_0,
I4 => bram_addr_ld_en,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"1010111111111110"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => bram_en_int_i_11_n_0,
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"5500050544444444"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => axi_rd_burst_two_reg_n_0,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => \rd_data_sm_cs[3]_i_7_n_0\,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111000"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => brst_zero,
I5 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_1,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => brst_cnt(2),
I1 => brst_cnt(0),
I2 => brst_cnt(1),
I3 => brst_cnt(3),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_7,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_6_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_4,
I2 => axi_rd_burst_i_2_n_0,
I3 => brst_cnt(0),
I4 => brst_cnt(1),
I5 => last_bram_addr_i_8_n_0,
O => brst_one0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_6_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero_i_2_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => brst_zero_i_2_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F6EF0000F6EFF6EF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(0),
I4 => disable_b2b_brst,
I5 => disable_b2b_brst_i_4_n_0,
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => brst_zero,
I4 => end_brst_rd,
I5 => brst_one,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFF10100000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(0),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF1F110000"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => rd_data_sm_cs(2),
I2 => last_bram_addr_i_3_n_0,
I3 => last_bram_addr_i_4_n_0,
I4 => last_bram_addr_i_5_n_0,
I5 => last_bram_addr_i_6_n_0,
O => last_bram_addr0
);
last_bram_addr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"EF00EFFFEFFFEFFF"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(3),
I4 => bram_addr_ld_en,
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDFFFCFFFF"
)
port map (
I0 => last_bram_addr_i_7_n_0,
I1 => I_WRAP_BRST_n_28,
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => bram_addr_ld_en,
I3 => pend_rd_op,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_8_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"02A2"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_7,
I1 => last_bram_addr_i_9_n_0,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
I5 => brst_cnt(7),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88C8AAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEF20AA2020"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => pend_rd_op_i_4_n_0,
I3 => pend_rd_op_i_5_n_0,
I4 => pend_rd_op_i_6_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_7_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00030005"
)
port map (
I0 => pend_rd_op_i_8_n_0,
I1 => pend_rd_op_i_7_n_0,
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF00EA"
)
port map (
I0 => bram_addr_ld_en,
I1 => end_brst_rd,
I2 => ar_active,
I3 => rd_data_sm_cs(0),
I4 => pend_rd_op_i_9_n_0,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_7_n_0
);
pend_rd_op_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
O => pend_rd_op_i_8_n_0
);
pend_rd_op_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => pend_rd_op,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => pend_rd_op_i_9_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAAAAAFEAAFEAA"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => act_rd_burst_two,
I2 => act_rd_burst,
I3 => disable_b2b_brst_i_2_n_0,
I4 => bram_addr_ld_en,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000300BF0003008F"
)
port map (
I0 => rd_adv_buf67_out,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => I_WRAP_BRST_n_28,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => I_WRAP_BRST_n_24,
I5 => \rd_data_sm_cs[1]_i_3_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CCCCCC88888888"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => I_WRAP_BRST_n_27,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAABAEAFAAAB"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => \rd_data_sm_cs[2]_i_3_n_0\,
I4 => \rd_data_sm_cs[2]_i_4_n_0\,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000DF00000"
)
port map (
I0 => bram_addr_ld_en,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0FFFF33F3BBBB"
)
port map (
I0 => axi_rd_burst,
I1 => rd_data_sm_cs(0),
I2 => rd_adv_buf67_out,
I3 => I_WRAP_BRST_n_27,
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F80FF8F8F80F080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \rd_data_sm_cs[3]_i_3_n_0\,
I3 => bram_addr_ld_en,
I4 => \rd_data_sm_cs[3]_i_4_n_0\,
I5 => \rd_data_sm_cs[3]_i_5_n_0\,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004050005040"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4052"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF5EFFFF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1110011001100110"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => s_axi_rready,
I5 => \^s_axi_rvalid\,
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F010F00F00F000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => rd_adv_buf67_out,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F700070FF70F070F"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
signal BID_FIFO_n_0 : STD_LOGIC;
signal BID_FIFO_n_10 : STD_LOGIC;
signal BID_FIFO_n_11 : STD_LOGIC;
signal BID_FIFO_n_12 : STD_LOGIC;
signal BID_FIFO_n_13 : STD_LOGIC;
signal BID_FIFO_n_14 : STD_LOGIC;
signal BID_FIFO_n_15 : STD_LOGIC;
signal BID_FIFO_n_3 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal BID_FIFO_n_5 : STD_LOGIC;
signal BID_FIFO_n_6 : STD_LOGIC;
signal BID_FIFO_n_7 : STD_LOGIC;
signal BID_FIFO_n_8 : STD_LOGIC;
signal BID_FIFO_n_9 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_3_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair65";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair63";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair62";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair62";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
port map (
D(11) => BID_FIFO_n_4,
D(10) => BID_FIFO_n_5,
D(9) => BID_FIFO_n_6,
D(8) => BID_FIFO_n_7,
D(7) => BID_FIFO_n_8,
D(6) => BID_FIFO_n_9,
D(5) => BID_FIFO_n_10,
D(4) => BID_FIFO_n_11,
D(3) => BID_FIFO_n_12,
D(2) => BID_FIFO_n_13,
D(1) => BID_FIFO_n_14,
D(0) => BID_FIFO_n_15,
E(0) => BID_FIFO_n_0,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
Q(11 downto 0) => axi_awid_pipe(11 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_3,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => SR(0)
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_21,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => SR(0)
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => SR(0)
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_20,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_20,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(11),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(12),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(13),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(10),
Q => axi_awid_pipe(10),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(11),
Q => axi_awid_pipe(11),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(1),
Q => axi_awid_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(2),
Q => axi_awid_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(3),
Q => axi_awid_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(4),
Q => axi_awid_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(5),
Q => axi_awid_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(6),
Q => axi_awid_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(7),
Q => axi_awid_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(8),
Q => axi_awid_pipe(8),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(9),
Q => axi_awid_pipe(9),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_17,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(10),
Q => \^bram_addr_a\(10),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(11),
Q => \^bram_addr_a\(11),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(12),
Q => \^bram_addr_a\(12),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(13),
Q => \^bram_addr_a\(13),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_16,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_15,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_14,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_13,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
port map (
D(13 downto 10) => bram_addr_ld(13 downto 10),
D(9) => I_WRAP_BRST_n_7,
D(8) => I_WRAP_BRST_n_8,
D(7) => I_WRAP_BRST_n_9,
D(6) => I_WRAP_BRST_n_10,
D(5) => I_WRAP_BRST_n_11,
D(4) => I_WRAP_BRST_n_12,
D(3) => I_WRAP_BRST_n_13,
D(2) => I_WRAP_BRST_n_14,
D(1) => I_WRAP_BRST_n_15,
D(0) => I_WRAP_BRST_n_16,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => I_WRAP_BRST_n_0,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_22,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_23,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0(0) => SR(0),
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20,
\save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21,
wr_addr_sm_cs => wr_addr_sm_cs
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_15,
Q => s_axi_bid(0),
R => SR(0)
);
\axi_bid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_5,
Q => s_axi_bid(10),
R => SR(0)
);
\axi_bid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_4,
Q => s_axi_bid(11),
R => SR(0)
);
\axi_bid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_14,
Q => s_axi_bid(1),
R => SR(0)
);
\axi_bid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_13,
Q => s_axi_bid(2),
R => SR(0)
);
\axi_bid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_12,
Q => s_axi_bid(3),
R => SR(0)
);
\axi_bid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_11,
Q => s_axi_bid(4),
R => SR(0)
);
\axi_bid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_10,
Q => s_axi_bid(5),
R => SR(0)
);
\axi_bid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_9,
Q => s_axi_bid(6),
R => SR(0)
);
\axi_bid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_8,
Q => s_axi_bid(7),
R => SR(0)
);
\axi_bid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_7,
Q => s_axi_bid(8),
R => SR(0)
);
\axi_bid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_6,
Q => s_axi_bid(9),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_3,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => SR(0)
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00A0000000A0E0E0"
)
port map (
I0 => curr_awlen_reg_1_or_2_i_2_n_0,
I1 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I2 => curr_awlen_reg_1_or_2_i_3_n_0,
I3 => axi_awlen_pipe(3),
I4 => axi_awaddr_full,
I5 => s_axi_awlen(3),
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => axi_awlen_pipe(7),
I1 => axi_awaddr_full,
I2 => axi_awlen_pipe(5),
I3 => axi_awlen_pipe(4),
I4 => axi_awlen_pipe(6),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awlen(2),
I1 => axi_awlen_pipe(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(1),
O => curr_awlen_reg_1_or_2_i_3_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => SR(0)
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_22,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_23,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(13 downto 0) => bram_addr_b(13 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
SR(0) => \^bram_rst_a\,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
port map (
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
port map (
bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2),
bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_bram_ctrl,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
port map (
bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0),
bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fadd_3_full_dsp_32/synth/convolve_kernel_ap_fadd_3_full_dsp_32.vhd | 3 | 12845 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY convolve_kernel_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_3_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_3_full_dsp_32_arch OF convolve_kernel_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_3_full_dsp_32,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_3_full_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_" &
"FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=" &
"0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0" &
"}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_3_full_dsp_32_arch;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_4/syn/vhdl/convolve_kernel_fcud.vhd | 1 | 3077 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 2;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_3_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_3_max_dsp_32_u : component convolve_kernel_ap_fmul_3_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/747b0ef18f7ea24b/ip_design_lms_pcore_0_0_stub.vhdl | 1 | 2608 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:37 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_lms_pcore_0_0_stub.vhdl
-- Design : ip_design_lms_pcore_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "IPCORE_CLK,IPCORE_RESETN,AXI4_Lite_ACLK,AXI4_Lite_ARESETN,AXI4_Lite_AWADDR[15:0],AXI4_Lite_AWVALID,AXI4_Lite_WDATA[31:0],AXI4_Lite_WSTRB[3:0],AXI4_Lite_WVALID,AXI4_Lite_BREADY,AXI4_Lite_ARADDR[15:0],AXI4_Lite_ARVALID,AXI4_Lite_RREADY,AXI4_Lite_AWREADY,AXI4_Lite_WREADY,AXI4_Lite_BRESP[1:0],AXI4_Lite_BVALID,AXI4_Lite_ARREADY,AXI4_Lite_RDATA[31:0],AXI4_Lite_RRESP[1:0],AXI4_Lite_RVALID";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "lms_pcore,Vivado 2017.3";
begin
end;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_12_no_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 16 | 103154 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT
BA51J62O2g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5
SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd
dL4PQcpPvGjWJDGFpag=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR
xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4
baRQNPLxEaKezVhSVCk=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7
sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE
wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe
W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q
FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C
0VJyPqkc+IZ10Uy+CwjZ3gik2aCJtFHgbPZEhP0+XKjQBLwHhckgiAsQKEFBg64vuzWzJTKcrd8M
y1dHROrhJIJ2ZETFcQq82/pJKlRJfZtZ/6hf4Pm8j1HXf8PipItmRfk8oT6gINQTxdgPn+GPPHQA
vOqMJgeeNWmb798ytYKPyWjNHH8AO5w9pVD8MtvX00hVtMN1XB0GzxE3WTEp05lkA2cus+O/sK1U
qXLYWyaUDH2MrudJxWFhrfcMZOEzmYNkFxlVsQ==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Dp3qi42ziRXBSD7E3fpHh0ylwL65MH8Anyn1ckdFcJOcolKl5/mO6xYc65Lj8dDpKGL8C+hgatRF
3UCoiWfsnfEn7zVRIzWcy/HoIWT7NAa6mf38jRFNz6x8/lkJVjX7fShumTdbhOLLUB0egoIZ5xoz
V2CyjRk0r+OjiBqnq1+6G/4SPn62GZ20BQbmcf1ZCHSQYF0FenJHIvqOYzEfkkm+R/zQj5ZOgPVL
5lRFhgk7DGi4HUUIOebvz8WvCEyuJfEPx2GnES+CuAgPWhZjz4AuriOd8BhXLQvgSsv8yDsUnpsK
h97SJlEQzELELZWb+djosAWEpy2DHJ8EvJoatA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224)
`protect data_block
W586lrbjJwPkA/cUT6LkPYkoU37uTL5l0rnTISyfmy8YP2CQ+irdPfNKZUnJgeNz4zvUerii2KTV
HfEo1/Xxvb5QjFyH4Bb+dVNCNtSfdQhJnfKHFN+fuRUrNm4VxmPCWY2ZbZ9as0Jsucu/PUk1a8tK
3usZF69e5bErqilTlhYG9aZ/2KAfpE3W1oU99vwageVTAphGgFLSnf/Xdpy/OHY0IxF/EUdRBKZP
9t32eYnwZxy+UrpgccF1rEq1Qa74SHqgA9JcmjE1n+EH4UOjP8NRB+8Vqj7TpZvI0uJ7YM8VZ3Cg
rJVpJtAFFNBXIWGcLPYzmUJuk6boDFjp1kkodJNKSGqbq1m0RQXECL6UtzG8a9Bi9QTMoe9oOqGV
3q0oNCIdl3xKxjrf26s53XW5H6NP7vUE/g5zQn07oao2/25W7l84Lyy9m4r6qTGo2mm1vjSrelaS
pTUSN/3pIEp7lJPnmq3Hp+183xgafhA6QqWIn0i/hQXNxcd02vpA2Z96sm9N4RupukX+JXVSD9Pr
p83SKWwixHFermRj6wtaqJlFzU6NL7cQ8EX4JPup12oTWx4Q15dNOejYToUyOL/4D/ziuphZyNRX
yZva1ucmO1JXkvr0kcJBw8PeT8X5dCvOZDJfOc336GS9ZJ/wOCBrmGSvx0u8G2IKVtOfltbf+PgN
gJ6OCeIZv9jQGb/pMKgTT+IRO0PYdAxR2SK0+J/DapQ6tH//fC9sfOMG4BU1EaKzQ3TTZ0Vin3FE
9gxpzl3LmOb/CIUMZ5nD9DQJoyOh1ykWJ/rBvkiv4nMF8Zq22sKP1IE0UYIT408s5gTv5VyyU03s
K9wCOuTLN0uaVL3hL5EHXJHhWuKeN0l8C1C/4mK5+6Ad+ROklYdtLCqLehl18NNFs/STE1ApK4+t
F/4w4siBHxmn63EO3cQdPXbRQSW7uSWeNErc9bjZAgQeOw4v6k3wiPuegUwaVMnmFxKX1j6aU+/A
oPrOiANZM2xyo4Fy9MtEM4vkUk6/RZVdtHQ04euHnGm/tTZQ0FyFZr35vweaxUwoCNkWWxV4XHKW
fzBZdL1ehcRuvEmhunf56CkfzK2IVTbS4AqYkOpLDqs6JVjE4mUwde9iQL/8OeGfRQvBoTVQYB6y
iJHu9SSsIHp9Q1IXboyKRrYrvU7aIa2QysEpL25yZliDWRllungWlvouxIMthW7M7BgiK89xRcHA
KaMnCT49D9PHhgOtkSO6xro1rxfKZebDa+U7TpCGHEy2E2uNeDiLmZ7m8Vh9SxlPGhFPFa+IAIgU
VHs/Bt1YT8tH1JuFJ1Ocjk5ehfj5imZtAns1Lorooy8GmW6ezrv0GKwPX54uHKsp2RPA8YaWhUNN
4LRDmfsiI/KnGhjsCiKIpmxfePRPsJNZaIvLdgfwkHp6ezkoWXjR33oWncM6vn76UxHN/MfQaGqd
tPNP7umFuFEe9EvKNanXPZfQD3wvfemUZgV30IFx7oz8S1SHPkNisSV11FlL/MFlaSW+slklJEVq
4iZOr8Vfrf9IJtSBkmnMNTEyk4WA7qNKS6x3wsRmhEt1dKctyfLTX5Llj2yAmlYykbBGwmHWfMv+
US7Yv7rG1taU+C1m8VjcxPDi5CB5tvXL7t3uZHYAEamdqbIRKELeTScvw1Lt0iirfikTffgp/d6k
wgIM34n/YQ0J8sPCOCXdwqE6qsKliMwrNdKvzZTDgpaS5ET70DuHAlV1s8O0kcX6aEXetAmqxHmY
h/SDcr3PiPFk4rwcpo1H9fTGfDqiDY8rNrydZSm6IIQVLS/JQ1TfL/+KBh9wx/gcvyiJkmnXgS1C
G50iacn8ZIeBgCkEn+BLl5HDiSsHG0ggRE6eIateA8Vz1OoBljer3/H9IQGD8WM8+NjFUKE4/Umn
sJIpFXMoo78ADcFOitcV/k7ExoVFetnkqpsFXHEfxncoaIwufMWytEucYsWQstVA2p+wYe5P4Vza
3LIhVfJaF2LsiDFmQuTXVr+RWkNQjkQqgpM2a5Ig1Sgx+O2SpkEZURgQxf6IsQMHrkOJgNl7hdSu
T02fNSZV7csO/V04T8a5wSFw30ij1d6hPTOHGAL783PsgWbVc1X+5mU8JqlH2RlBocHd2KPnU0kj
RBH5yNFbT896W3qGFFIp6S290lVWdhXGV0S9kWBC9bfdUsxqBfOh0otAKd7CyIl2k/o6Ju2O7BoL
rul1vhq4WvNMjxB9IKeiC8/CJ233m3buZYAsD3QiLbj6xGdLIlf0xsFuqhpv5Pq2RzK7nyAsEhgR
Yqisy5p5Jx0Z6Z6/ONbzJB1zIVdYITBvAJrx9aGOmdu4Jw4mWlegxQqFaxgotfgEiQOP5ehspBJ6
KBbCXy3i6utS59lj3uuce1GWCKJGijkUUxhX3IbUPN+Vd8arBNnAJsS7i4YaHmawCGD2PWBLgGSG
Ja6+fy9TWENkQuFTwkbNdnY+7Avd6YJ/myg67eK2h+w0ABn8s53rSbW5UWUb0Lv0W/Ui2BephCXA
w44xPL/MxwVOT66KA4OyCz8taUt0qr9HsmSKL/16GngywYDLuYx2Zh06eDkUuC+hO3b7/Y9Mzz1Z
kv7J2D3uf/jPd0qIYqA2heEbsT0nFelBYi+6GxZTKoTK7iEi2sjRolwfXW8O0Wt8XaVGZnUFloR8
km+A69GYK7sgkOH4jmk73unOMKV9x0QJbwZyiwcKgPtXl9tUcqIjemrj6Gg4WRx7fSSxtFGSBvfk
9trnm+n+MQO7GM5gEWqucW5Qv9snp9peYINNcZW9AoayZVST1niagqobbv3178eYZ+HsTFFOBmaU
UMdZhShqX9mVO6tJv1OLuqtnwENZ5ia3ydrOV7fz+DoUFTIXYfrq5VusR4CD+VJ++3y4e7uAEiaA
h9S9ejKSAif2AnwR+sMlOkWLfbbXroxGDHfMe17OAkB7WYOrv9iqxt29/JVh8cdfKLZMKIx8Fr2r
+CKciGu1eZytb2nSTp9pSrKOjEVR9EzG3kdEfZNHwL0zdRWz4YLz2NfjO1rrP0sm164Gpt9kV5dl
Qx0VVFooC8+rYHntISrrT5AHdpnWBCN2GhqruooW5DWdjaX87EaDlbHfXmWpL6lmr47offDFqng3
hgauISq9DOUoIqU86rgj0B6J7nE/fuTTcD6kzkFK67gC8847Dka57FpOkNfHDRMVH1ketf/9mHvR
aBV7Bc8eWDE9jGZ0tInHSqLr/MrFEAyKsaHsk9qSO9FOodxl2kBw4q4r3skuMD56Z1g9r+hBRFac
MXXI/K0oV66EFwQjpq96pB42jlKA7yl6EI72jORJbbpz3Iw16PQnFDvRH4WTdtmOJwWYXrmBgwzs
4DkfD/3oIL37oqMJNtbF18ilCdpDOCwBaCSa5Bp++aVN/i8Uben+zkJf4TJRojvLZgW7PRlWNun0
NGERaq/8D1C47M9MdAmwEPZcsgLvOftLZZ8+ruCSq1ijLj0LeqKEq+cufNd+88lmKWDN/OK2VmZk
aMGyzFoEsIiJSp6T5h2CYEGtd1cWR80qi50YSifVHpiWD4YC/s1mEnLz6MzOUgMHGkjd1K1U37JO
fAqXLK0l0EGZmZ3Xx8h/DJpZbVXyk2CdaKOjP8vye8gZ+Q5jJfx/fFgw63PJEqZuCCf1HqYqCgB8
2lJM5/llQ9yZvaxjgmviRHtG+9IVoe2XVY/6mJUv3dcXdDUCgdwAuq1r1DnOX/Rj0v0lzSbZcX/1
XYSSocn6jt2owvyDJnnM/rfR/j1Gg9m7OCYDkvk9XuYwWa2yWAmkhr1LRxHmrkrZj3aFk8hRhEG3
3X0Otmt1bQ4DVpJoM9mkE+lsVDYLgqLE9Vv9YTjdmqSwsI06UNV5iMCsjKY7k+ltfnJen1rMCZjY
sCqyNuLxKCN+svAWW6ZUDVhX/kY59XJcJJiikdQqQk6w9gNmOXbCwpHEL/8nvjvjD34gc7EpfBmo
S6O46THooWJ9MP6hzzLW0YVwVc16N/iTz/xlnc0KLWD0nuLK2zB+fkHU4q1eNw0NuK5D/tyn1MjR
szyerwh5q0z4dE7BP3sR8sQzzJPFdO+XQ/V3lbNZIfzV1lzH0p+nFyssqex/0qwa8t9E7dAf2G7b
LKN+O/LAIyON0ZufYtr1LrXgGC/tBx7ReU+nURoRKoTALuQsIMTHMcUq0aGy0IWhvX4MRb5+jog9
yttSYwQciqt/d85CA/J99gWdlFMxiSjGnideeI2unK/36BX6c+rd5QljmyKdKm7mW6Mn5uoibf9G
zhn2LRgkdFsFHuxgVBOjJnrdg0b5vHzfwsp4y2LhGIDdBpXrNTXGWssmKtObapjAhWCrZ3hldqtx
ghmCv4M5LlklNPUU0PaFgyPTGKiH9m8bEfHuMiDX5zPmugeqgraQh3Go5SxRZ7iIYL41kCU7vTwx
p5PwoRQu1AcAN7EjooA4b9mb+IZt4IamkFC6scWDthshLOIXfe2mNJFH0zZvog8ybg5QBV3TRwd2
F6+4AEiNte7D/rIM09ia7QgWpg6iJHMVI/VG2I0HSKZ1RKZkzw4ERxyMNuiKrPFBGQTzWNUciO7T
KmV36OP/ih6LstPix7vi+qxm69DP71Skrse4OpS0oRpRQtf+DyjZI2LQySHpzZBwAEMRsEgmcF0Z
Eetvn6wPFP5roOXrXi8OxUkWc+IZTcMfK4jbw24ck2jCd0Ua4NSTMsv6r/LPMIJw8d1c5wN4tHnF
uojDD6hLjbkasfnSCjOJ62moN5B+EBXLjsbqvl9Y27htcb39+JVtnP2JLmzBMwc63IXPNeojE48l
P2xD75Jqg1eUb0jMy6icIcew/1kujWMf2gaMeBB2tLJuw8H6lazScvVJDJTinJbKG68ruxrRoNdH
U5f1bINSbG7bt+QOCb/CYGC6YW30cDVzBjym1E10GfD7PEKMo40H4zMTC0DfTgahOsNrZXEqlAQh
3nq3XB+BAt5X19W9Jq4YcUcQQvuztIueZugOcOPEKbrVwkNUk/INJg0IkOOCXfYkRW+xcUdvqoA/
+ot5aYc/Gk3nBTmwGC81BdblUoetZU8PsqyPaJUlnyykCezUx4vRg1f4TJ16EG2cXzEW56idYpWh
4mk8RcwV2ld7qwxVj7BgDGuXcen0n3VjsAGu9jaml5c6zcJQO7mOM8vXZkrUsvIpRvcFbUCWGqPw
rv/qnRS6siBdP8wEuuqIBjFTZwQ8s9lZEyLlwd1qnWjgcWpGuJ7DA53jOX0m5RpaxQWwgPPsPgWy
aQsI+hmvusCPfcIj3pdp4aD1YmT+4YYM+gQPf+jdtbAYYoYFWvh3GToxsbvvfI8qG7u5j3TiXKmH
Yj3PBhIo9o4+0YxQhIgUYSAixcNqNyy/vUgZMIbK3AHIkmdxwWtk+ISWtpXQKayOXFE1TzbMQN6H
/v8AQ6Q1YFX2T9LQQPT6s3GTgJQucUpD7xLoRDhxD/17Lpu68/HnrxIbKIXRvz9vVjQBj+efBBOc
C8h2taOYSLpiVuNUIsMAf7y3h1cTIaKhT9/cZ+wWA2mVLz4p+2aObWo4Nn0QfaY1My1iLcXo7+EG
NEA+AO06zY6D0BkOXVLiIsekpHzd3oQomprIOwcPr3h72fxfgtMtVWA7KtVO19cbxN7CkXuK3xs3
4HonMntX8fmOn6QsymS7YipgUoKuMRMtHzghUWDdO+FWzi3QmwazaLBL8RUgibxsq/YaP0RgCyB/
e4PyQFz8uJVhWsjKoBGUwWjNfnf7EMhNvW3jogcWaIz7qOKUUBDdpCQ1n0UwQrtyBa+KamXm3tfr
o7nJ6+D5swnPtyW2oY75LhUHyYlP4rtcsM8ZDurty3AnhBCju3QbCQpKvKE9IHF0ha1YWXsmmaOk
b4elff+trfUKTCWKlTgGJVBbfHPH8VNXH/XhFWri+CEcjjDRyqdhh9z5e+LAimuXj8Md49JL0eRM
mTkr9igwtPijAzMOtbrC7g/ZRckpOiU04WGgIsIo8eEsJRtBCuYAN5DKBLqI3+dl5Ay6a+HOAhda
pRypSNpsirP9kQAtvtUoLjOXhMi/dZ8H9VQGWfxEha2QH3o2SKXh8dmH57w7AAvpdS4v9WYa850u
soH9wyxLHfK+sx7l/phFfzhrk3HfXXpBQq6fxG8ZuTj5PtfEbiLpXwe+hZxvPfqmhwepuRqSS6q7
Y65JpXqleujYlCJwPf87OILVDD7gqD4DNVYLCsc66QT68SXl/OXxFFJgbZp+ifQrgUH6seTfGp7F
aW+4B39l6xnEr7JdKX7COvjiKzm39Vkj0rtdxLd0j6EerWepV5Aq2vmTpReUjfLpyeLW3dbbi/Qa
ggLpB5R4ZRyAn6g1geJ0tEaEcZnsI2b+uQmOANEqk1UPPxrO5/ghflquW/wlUgwv5GZtL93E5PIj
UnTbmA+341wC4YgAcruLNJS2jJVTQKZP8U7Pi9zJEjw7x0wM9A1Qbz9EZY3x3YEDsPWXRQ+91lp0
vS/Fx5zlNykUmttCHwReNiZDBOX685/FAc8XZ0NTUz9WRBILhsXw0q/b3VACFRuXljP0eYOfUZO4
7MrRD2E4JFuESwxn1bPIozTVDBugFKsnev6k5k3NOtuKxwfR5Zphh1KO1UCmE1xpFwqgB7ZQbQw+
wqF1GXINLdHJ7bx0kN0sR2q7obIVNorY5IufhTDkzvyEbFNJlBMSfSCgqqxbTyvUY80lzNjQnsBP
JQ9wHFXr6lsCrEqCNU1BEczVmzzMxk5WIYmg3I1Ms7xmMNxPRRyEKN8uf0hlTEdTneX+jbjr4Ut2
+nuXwhMnJgoPX0KWuIyIXC0xWxfP1FVmXIBmtx+JQ78+SCHdlqIPCb9ttLJyGGxsQoYEom+JMHVw
+61pRiAONNC7VKqDIoJTurRctTt8rrfvwX2QZnlJ+bzeCsM6MKC+3xqFISUBZxXtbbUVH9lf8sfb
agys7SYVt0JchSV9sJOfXoxmFmpoh9Yx0iN8qvJqmF7ZFpmSlh7ptjF79pIYjvrfrE/OJJyZdhRn
CjpSC5HTp7gESuMZG2V4cDl8ae3JagtCyk7b2/vVa2i8sHn0rbJ++CquXeNukZOyKjvQ+Ez0FYCX
sTeog9fIbywtr518FmxlA8lZrAQN/obdYevuNv8BWXg5FlIURRGrfKtv20QlBKmsjQeycHx3U+kq
tB0mu/uBnrnnasewiruVAJZSyl4QAJUn6iQDEmv/MQKqnN8Nb+j5OPmNeQI57ztVJ1Sxlvn/GTSi
45msKAK/1SlfvYHqQVM+QDB+R0glUGt8XRb8znlpXpzKf0p2LXBjpYqxBFKbix7Qkv1pvLiNZ7yt
3WOhkxwMnNMeGBwyiODRjqcWgzL1U4IRuuiMrdTfxm2sjJ5GlhKe44C8Glcv9T2oF+Kz72G8JeHm
K0PHwg/2GMBHTLZMM3SDFwgz3+7V0VBSeUuz1ORkOx9iKiF9/yL+uBy7++qZdzbfhzJD/eW4uzdp
TwtxFS63AINLv3r6Z5cCgcz5SLl5UDPWR25Gzot1b64nVjJ8suGJfEZvOubV5LORvo9QB/JOT3fX
Apc05QjypNheQBTg1POqUkv9q3NNXYZ6CPIXiN2gjbL40dT7Ik/yvJvKm3PULiP6dH5vBS2JYAyF
ukcBGVKLscKaiiHmMITSjlV5pvCh9IeKmgo84Jd2SC6hbcjVQsk4LA2cSi8h6HvaocGW9faZvstH
GWsR1yPlj7clPUUZHUNSx92CXFk5ef0JXAqucPUCZiCT6UzSDFyF9WUrC7zRIQ2T3IHmtE13ReUY
aq/sYS32px8IVh4iRddNoTM29iZBywC/6vaqF8vTke0G9uKwzga7AyRWnbl7ule5wLS+WXQrgztl
gt83u+xlUS9LWuYMDcTp0rZChuIc57EwuvfoFohpZZubt84FtgpeebhNt4fuMUP4TCDpWc9NjCGM
3yNN1kwMTiKypWMbHAxtLgS6ILViwP6rsUJj/Kj0zqhf6bIdmELG6hpYEIiFKbPE/bOlWmjExQOf
FsBYlXKk1N0uILFAuV+GUB7X81YSW1F+UVEkTOtp+QdIEBjodRh62wgtL0kDJBVkuZv3a5UFmebt
S0Sa0h0mDJ0kGt9zzJwD5QW5yWTi+BkxM64RjpmZRC7G2HlAUT3huf3quAcx1Up74dNnNM+pg6Z+
4SUbYQU6jbQK1uwnxCBkN4MbV4irplS4hn3TVtDQkeBP5dyuvEJVd60v5dBLS6T2iHFdRA6acWOM
Tub6LL8zmvbxltH3Zph9lGtdiIRfclEcctt2iP4fQJERqJlnk4o3ZdwxSkzlwKOhxUpYNn0eBaN5
SuzB/TkfD0e7NSwRlfDTFni808QDgRBkM87PmS+FImUHf3q+fi3WXyBnTYp+lYw3ZXCeB2UtEIzs
nuSL1BjlxpqGuSZ9dN8zOlMSNPCJH7W/Xd8sjqCfFhVCZs9fPPYmTKp/bWSQDPtCRVFyXKIvZMsx
odzZFkQcaOF4Gt+yU8w7VdnKXh2E2baN18U2PQrMocold+oUZa6imlr502f2XGeuWQmCWASnhTyj
qahUv+CTUhoDQDgk6b+ZFGPNw7HoIP3ioJsrxaU0DkeHOrcDCZ6C4m2klni1lvCWFF3qQGKOF6nu
CJTzfKcUg256JQWl9NdK/NXAfY1Qtajw9pAEL/4UPmfqZXelzn7Mgp2HYBXoht6B9oJmdCPy59XM
QFDeRxeiGgm59Pd6bEmrFn8o4wEsb6uZDz8r4SmZoqaC+W2vMJwqSdUruJV9asQ1qpTU9YGeAX3a
rz7GW2W6iZul87tKnNYwee+wM8sh55uF7zmXMnF5Z4IDZbpTY0efm+TtkXwCLw55LMy8pElP1udV
q1tDvND2kaH9JUNLIlk8XZoSvZLFktzgceFkkRxlQTV4LhzoifMpF67hQ5QEr98mhHDVpN/rOwwk
49WfU6rVrnlFOSgaZPRcie+e+P6DsFjGl2rPJBqpWVzMOilhmgqlOwVVu5DHs/1dAws6JOok9bvw
layrMGButLqy4H6sTm08dJ7wYdY2vxTGyVEjUskCNPysbI3+vhLONytodsI4e7stNaSf3hvAaGSn
etLFvcifoot1W97n3g5yFOSaqu2Q1OdCRTm9AYixcXjhsI6+0P0KXa1VNR6/aI0Ig7aRaflnLEkS
sSa1VUYgz2n3sPlxk706XFGSbW8sNjIM8IK4fx0NR43L0hURjm1jpVkOg2QorjiOGD9DMNycnIc2
oB4/+qVQmjGPzhrhXq0Nrl/soAadErlKJSr+P6JYNF1232NkVYLEZv/C89DCqvV99/425h6Pwe4M
qmcxzLxPp99xLNOM62cJPSR4tcJUqDGgEoia2nUJDj7sSq3+tHK9kQkZKzqa/AiANbyTFJrB8g+X
xqfWCQ6eG/BDZf5dvaWUWDURPnEIrZcNJmHZjQzptfUvfmQ+/SWH62JPrTMmYEIc4643M0lmcu82
CbLeS1LL9vxQ/earcZKPJhQzUWbZ3FQwl8avWNpkD1PcSJBMQuXrGiMaZt44S5wXaM3lLRDrxGEi
OBkE5xHkPjvPAK4c5aI6tWT1tnGqtKkfBeruus6Yeot8J5WOglsnViFsKZvLHfwP7DstCCp6I+1p
CoMG96doEXod1e3AJu3mFCIghVlOMRCc/qNZq5dWU4/6BbkxvVM3LA5dUb/VhKOKAflkCd0jBoXT
zxneVzY3IJlF8dEGOBsXluPLeTePgb+NPbo9xhIBCGQH42HHmFcyvU7IDBsVmKIw4up5l2iGeToO
8cuFnxxckDWbqMYYS4gWHGpc+uC7EkeBKhJQ26EfWxxOw9WOunFEbHmdTAOoGs+WM4S9aOX7B4wP
Ls+iH/MLZBmmRwJ5rOJPaGdiEKpneUsqUTL7lBp09YJaEsEf3c4wi1BTALk4/WzJuEMRwEx+zApr
O98KZixLVWxvgIFdtUsZL29gKx1SR0QivH4Ud7CCKX77h12o9UdV0LJWYcryUxGpvYYme98omKqf
hdfns1OaEq+QJSfXSgdDU4lYDcemcDSAwHPM7pzwEf5RRqGbGRV5DQYB8/7scfeUlOCVogbms3ae
9KRL0gLgOmNaBdK2QIO/Kzwe5/PyMCQNW0h50RCiaD6umhDcyyvecxhYKDtwi2Xhr5Q1nJAtWYLn
YQ4fjA6NeDcneqoN2a3MOPMvJMq1R0LCK1l6u6yum5zqUm/6JD0RNXrHe9aIe+KUt74vf3grxV5i
DKDB0G7wsuThUTnjYyS1dQ0rRsLkQx+22QNebjrWD5vkieJTHUYoXJ6oq83I7aE1mfC1yrlmM19I
dW9B0HL2Kh1j5r5O6GSiPsmhMhkhnjHb18kdelbVuGnBwVWJBt47hMjiiyTSAATpvoXn8X15yQkH
0fkJKhfuJHaPdiFBnkE9uzpi8JQ4oeukAEYSbhF2zn9rA+q7XJXiEdZS83T7h7ahz1QS3eOYmACQ
21v+IS7ZwYBU3EfdkfnTmc0/8N9/NHhTc3m5+l8u5L3YcVGpEf3e6W5KLzHz5s3HHA61+Ge1c1Fs
saKW8J6DvINg/oQbNDEO9xuKjRwl3qHaDXRlUO79yAUkRRhGWnMRRDYlXweB53yE+VgZjxDpfNVK
RZsUA2E49d+Ggb6apPiuypXcJyAsLcEDIkmvKCTTj7pWGvmRE9+zFvbwD/B+ZYhC7xBnHTaaisKd
DRygI9oD8NFR2rtcy/xay3hs03mj4d+Fo9lnWUBRcN8LhjGXEI7Xr8TTC1sKetyL+rTJAXjBwIqn
Dd3Ks6IB0LOaZm5EFxUip1gSo/XZIKvYEnPtVUZ3ukx/dYhakYpSKXCNqiEoSxj5mghcqoitghSd
AqHII/MboZTdC9i3EoakcFdASxoIJzwJ94bYJyGj5nDl5M6/ggrbfLp1XcGZ6azUtqJoRkuHAMfQ
Tt5I90/QYBswgFbdmX7o1nDHfiUqrjQ0PilK+4mj6xIl91HHpUMYrDVfbAozBr+8i9Z9Tww7dNOD
+3W1SvU/nbnIztBp4wr2Rf/BJkuOmZTlC2ISAgM8fGAu0z2L/5506ivkpLQt3cTX3WOui1S9+lAy
oRV0A9yp/0JMwD1Z7Fndgm7rfU2xsVdHKh2VntI2RzS15iDGld0zb2hGK0zsCYbRSbWThqFSTUAp
zFTnOU6gKO0DTqKfINYalKv+d2JqTP+tIsDjgZUgk2zEDHEMJrLmYXaINuUCEL12NkaE4Oh7rDze
Ik3dvvqspciEgilmHWntmVmJ8o53NtEYFzXA+l8HqwpPX9ecyuJRZuc4nHmGdvnnvzH7tOiBLOM/
/sNj88QGz/scWYGvRW0E3ZzcsTQz3qOWCudmd020+W04SxLkKvJxBdOGg5tj+vooT147JklEfMsF
+Il39Lbx286+QNftSd0HA96O9yp5CsjTfyodUres8cQW3w4yX+NG4Ze3TWSCHlYveFxzdysjyOR0
KUZdUeMFR/pE6oFQ3C5COztb84/mX/jHK6a/igk487Mx6zyBFHaiFtifdfkYMtGtG3tQEtgGbCMx
WsEP5k6JJPgS/ARSBRTsbpxaZ5zkW10dEe/CkNO165TyIvoVzhGuS0HT2aVU1Cbl6wDD9/gGPgHs
QGoljmEzjh2vyJwtLrzhREVugRvCTA32MPDjXaYoKRB77GjE2mFeZhd6J7tKjWgl14lZjQ9LNMPA
JDyQsnRamnK6LPHsJ5DqjYX51VTpUeo7T1gEGhOT6Hjl7VDj8zO4CwCojRITxXa4FxKpcDuglQqX
WwCO1s6AG6bVqyyQdgl1Hc2CmhXbxJGmTfYZLwBwNaOqeojiyQ/yQ87irlLJVeRn/mVDkTFtyYAp
xtRZ3l+ttXW9G2M7ZD0RDvcB/yce3MsxalFouq9Ox51V1+mKKdMACYOZPZ+8FW2UVTkyZrRnADbw
FyZF9nP5XKV/GLavbBTmRBhKvzGFqHX5CYr38VH2Kk3wCLOdEg9LEmRA9gFRBNYYw5MeFliDfHlj
uV5yGC5xisjPmqW8sSDiSwKnRS4abh2p2463vMJe13eoF/r6dBxL8UBAXy4voiVdls0BxjGrtqAw
i25bqFhhLcZyxNBnGw4V6/1SQcHuhvlkzYrGYb36WjzZdIeoavDHllSRYI4Q6pg0rz0irmRzN0Z0
ZvCY1e+sehfSWOMmmG65FVoh49E//8T9XpuqRdxda04vuPSEXqMznSFaAjFQit+gRNFPM+OP0Ui3
5QxE0OJp9BXKMw7ql+X/1wpkfK6cPkDssBelzltVSkn7xVBazRm3bCnPE6bz21fVE5BBzkrfLsHq
14JBKrowkjeeifp0mqByL0KG+b3AL2TsE0ox40fXFnLUM/PN9R78MguMSJ3m0mUl9pBq3aroKy+Z
06tvDgmDNQRH4heDGhm4N3Z8OZlzplvCFYTMgycg1AbrpN2l4rFjm7LEdCWDERa+PLobhKZJ3xSl
gvxrb2cBEvwPAg3MPizbpRJwHKnQZL7h1nusvHpyn2QASnhpVcBr3gwIKd02pATnKeBALEkjiSUy
haxcb0qRcHel8V88bWaNtqZox/QmzzzLxO8lMLa9n3zpE6T4PV198Zx9SWqypsHWfxhD6ZxVVsNx
OAV18zX3PKi4uPoTD+gd+cbWsDG/NR5uk2bR9BFjfuUmjmwDCEzfwajlUr21jiZE5CQPwsJ+PGQN
KFe/1qxZ9yH/RuFRUBLc8HXTHMD2qhFBQqx+lJhJpq1pcmeD4Awc89Vo2rSO3MyjkjoY1hGqUYoe
Q1L1XzXywIz9nki3E1YmCI/TSfM8b81W6+oDRn1Z/k7mBYjDhdMoBT6CpWWooeIPqXCVtu4MVUYb
HINE5ZABs/Zk3q3eSDEOybblcZikTHYbb4I+FmJkkgjJccm1rLcnujqJVg8VEBbHzOZBPEDM0SBN
/GApng8a1NFAr30UfxSHZwZqzmJEcEZnw0t5poEcjgyPYu14rL3H7JXxqoLPBzEvvYgrhsqdKdZV
mIESTosaJ6Ssc/GcGupGFJhcNmxyV075i48ovcHVXPT4EKqLUS8Twzl8oqXT+RLXdfSKnB1SONWb
duxCVcjJNKN0rKbTpmP5VwuFsIiQYSEhllturb0ZXNK6KoYbd8eqaWZTafuGvmdmSggD+QQufKyh
tkCcAOGazIVrVmVCLDKFXHRxdvy9cJsMiWgZ7g3iVc4iJsM3C24iTuYJ/bNhBjlB9DpLnFZj8AKA
VSCpaWjiW37vPDJuFHiYXDXyRBsR2G+HLovdeHqnRaYcn9eHtkFl+ALjzY6JmmiO3GvnYBDzsFN3
ehxYzQMi44zHH4MbUkWOx5z4hBeyfC4KpnfxwYdU7OulOWlsRWp/UmSzdhe6cNtCPXJFsTuCtvBc
9XPUsrw12GxxjsYpnlmzf28MUagr3MWvjhXDy+kunV10s45FqxtaUh8bPsm2nJ3iygfkU4sCuTUh
ZRRJNOeGULaMbsKODOjq4nw1KTfvwWY802gzYnPrhdznUPXNEunXy9J1fVtfC+2YF+AC/zFs1Tik
53qe6sIukviJnk6Oza6zbYWRAfaovkadKiFPmhaGSpyaPD3eMQ1MJ7qG+O25918O6M/yOADMcHSX
rO3EI/fWoH7hVH02xrCcfn41L2yiEA+tsKk385/1gJd3IY8V4e3FjI+3/I3vW0uSrwsGMqrMWOsf
gkN6mpnQImw1qb92tqQmrxw7j030A4/IwLmwUWI2fC3N1oHNdPpauVODf7YPImUi2sGeOhikWUwH
zTmFAy7562+tUhl3mdqvRUcQLBqD78Ruzh5/jzBk0rZN6egfmBc5F4R2JRCqjdWhwEWTpZwB8ntD
vgJf7jNqKVv0KjrT8+6zBcLH+M/tE2PN3XaqDCsKjB/kULH22o86mFW78OCLlAXSHFqeB9Rtl6O1
zp/KNFfS5MXlYgHjdC3OZB3a6ZOPT5FfB4gdnbGfe6Oy+Eggl9M0bqQBooRhciLGbU2P+nrMJGJ3
ZclKzdLLxOeP5x2PhvEOu4v6SOQJfIJ0xPW98SRJQMmRNMxpF07qJOXza1Ztl00MAjlx+TYl6wtO
WU1/Qey0nl7TK4Yvo5VLXi7GDEAwl3zLQNbGwkJkgSm3EbyqHYq6I16lyjDMIe51USpeaKot2+YF
HoNt9lVUXBfmUnt5WE9VfAsAkF3In/Gt8VJV3CM3e+PoXDR40KWKuQGtT3kEctix0Yl2AFWqnRvC
EaHEBxlZVpFHf/cWgo7VF03P8LhWRRyKCEpCc3RYZBNHCfCuNS1nOpZhzktdsSZk0auYyCj7NGyT
hnygyDSXn8jRfUQTiAYI0Dh5X5kioYLKOh+IeoXibvLnkvMHwHzYZWI569zQmedZMwjbigNe69px
jcHWp7h8tMSH2I7M3TSgj7N9qkbjolswRIi+AScwUUcOEDg9uo0pw++TUJGMXVPQxV7NhhXL4PQ9
yt7BpvfuuwtxlFLTXgrWMyHcWgBh4xKt6AUuJNuFYrgW8xWQLcuCCmIoRsDDPTCnD7utc5pFFUz0
jJ21IKblxdIK9r5GuCDp8eHDXvRcD8b82rJT10OU5sNzvOXKmadCZOMJzB/9Mv437oqBsgPqLg1T
rM6KXZzGO/daorXPkQlUPaRE/AJaZPg3SrNRWOQSCOuVRAwJUR0ElOFgViDXPyvIKeOXjA1N+TjB
4xoFBPtrbOAyOzIy9xtYb8xLkY4081AoozUXygGC+0B99WqruXRkx2eIzOoOcrCPk6AujhvSPrkl
vyqKefi+byA3+6Kxe8WKV6GL9QsuQrQQ5Mm8qIB0nBHrQWxLmH5reMs9kJYfBsaf200oYbAmMx10
l82ukErgRaUMu3zsuD6Pb7S7Pd2luiuHAe3puuIO7hG9rW7zu9gfXu2iUrWqF8pWEcxYJXj1wxF0
ZoBWcFpcWwsjx3oy6rpNF27Vxg9t+3HneGyklxF8/DO47RVf5j+P5xwStmdfxXlKAbpd6hzlHuWX
oyAwsy7jCN9wFOjBbMAtR8JMXHs/KIr2PY/NepLVKH3S3NLmDbHrFZkZkDfoYus1JsQjXEdvJU/9
JxDUOOHmmfktYfCATvnvPz84aq2I2F8L4AU5aKFF932IokbBoHf8l2CEpvV469dmLf57WWGb1YhV
2GXPWEHwxqiNxBWadvGrou9hw6mk7anQlQ+d0ZBs6zMgDWbnQ4lWKM7w1if2nlF1Ng/Rew2U9Gpm
IU4+X4Eo7vYJ/KEBFMr07MtkX2gpEPFNSQHn4mjYzBD9lUt+/WNkvoWB2EZy20lrtFKqyLSomhWZ
GSOGr4/+OHAmVUeL4gKrDET7CJSUJZ9zxq+HE6EGPpDatxc5oy5vSVKF0oYmZGXeiY3xoc0cU8NN
I5drKPipQLTnXriL6gvGGpvhHFh7f5afnbXKy7UFKhHR6GwN1Ee92rx9u0RDVO/xLtmHEozijnuE
kz2lWg+Y5Kn6OsqKvO5GA1tK7SOQwdD3cidjQULV1LVtR5mCJwoQhooZKAZg7A1aPPSagD9GBJkU
Jtnw71VstVEJIrLV0E7WM4aSTJzubSx7QYHmHVL15L8HBICWvSzssTe5hKLn/IC4obU51uAculYB
3T8tYJ3KqEzxQntUYljqMkzUmEk87FWQSLHD9qu2nxz3ZTdWd9TVVkxVTHRW+gsAkxTS3R+oP0aW
dx2XZK6mkIcproGZ4Tj5eRwkdPsPpecS8R8wjHlGJPHjV3iguCtyXSQJNyXM75fb4o5Bv1hAx5XO
27X3w42kMuKKGkyGIWw7e+RqOXDCcyuorrCuVZ6TgU6VBD/HLWZfjRjWao+s1FhgtDfMBNpcTg6+
sC+kRaHEUKx6vNSZ08ubbGCVv8Hke4ckYmnknD3g9gsJ+z7WZ0nroL98A9mw682Nqs1mNCddTAPR
DKNp8XCz/rmi5bkwU/FPpVnKSghjadremoPzx9qIk8FkODOj1kpAn7VBI7HcgtydC0E6QJJpQZUZ
8aJyq/HGnkGcLbs7LIcmOY1vs9ks9onr0NLd367muHyAS2KhKih7ynK/dmQRjYkgXy4vIJGmkqZc
i/6z1gEO0jIFnfhWNSEDlr+EhqAVR5w+/IH8RsnJgMgDhC+Q/3W/9MtmyuP0g70R8Y/IwfvhUHmt
uiRTO3GN3tcm8TERR6s5at1oDJqX6Z6IhfDZNgpCdCCKCr26it+LjQfX8IJGMuR7no5VWLYZ+cE1
GH6H3qqlvuE6TUqZOcCvWbMBaOQrYEqOh4IIMBWk/2nkpjGgecIaxxqrvteYxal3tRZh334IFXTr
O0czqLMdq9YXHy7WT3OMKLrND2k/NNGV2Md6u5yKIYRxUvm2giIX440fS7R939tlVSsOJs0MKVya
rCuKD7nKno1TAJaRdB3dkqW0tkzjlnmPaAlWxk4rHWh64JwZhtDypzRYByq+eP77EbS7NiGIe4CX
WV20gwE/7BVzx5EmuJjELdpNFEtAmBzHj6QR/EwsqvqRofAllVa6VlPBptmXWuImVcIwBbDtFkxE
UWkkWcXaLVsqI9AVcnVBE+NY7dm1tbbjggTepPO5veo6EnIX6btjK9/3fatcH//nyWMJqqS2pn75
W6KcKIW7umfzOTD3FPPnbAKA4QATYzY3OK6nZ1xLeevILntkB/sSEj2X9aJL/tx4J0H8KKeQCvrO
fMqY8szNbmo6icUhQQMknG52x5v0qipYkmuRSLaGxvsiumlGmrueMKxQyqGkq0pFPzHMPpiJn5LB
LRIBLul4NH6RBXjm8zqLgFZGvafFyPEs7ZoObzrBpOgdhmEbD166+AMQ9bhNrbboPSIwuMX7O+TJ
Ej3gkbsambyD5LxP7A00MoV4Gtnob3Zx7gfbupOnFWFcbz+GpOmJ991dIPiQtS8IJo7+KE7AJVAf
usMq6qxlxZuceleJdxhTkUhbzUw5awh9Hq1T/Oqk+8VSKDCdNe7Ja8DFTHr48P2utvZtSlmecTJC
oZKRIpRjVYcV2kP93UQI3aSGPr6ceOt+SjNeg4L5m2KMDDKQLpi65wv5qwQ1E9TBx3k2b+gq5fC5
71hrNSL2n+VZ9dTQOF9iiwDA0dSVuXx4M8dvZPjz99Ls2oEwHTxVhbUPGO+GrKgZM1QHHEnWcKA3
55J/6K7cQR/5sNabEU7WMWZzBr2mqLRqax3k2OSjTAcHtNLFtAp6Jfcjdl0bAf2gdd67nDH4G+oY
eiUZremwgn7ou1HmOpsRED11p73lasGBuoW5l3PzjWvuPaHT+dDhLS1nbNocHuFFlFxpcdNUfG3y
St5MsEApBzdd3lmmq5bQ/fO1bhzTz+1j1HcOecO5ljVfytRHTBdJlXhnEEw8KZSnoIh3dNd23MGH
rSBKsykE8FsEglY+lUONWqBpKJg/e7pfVyK7ZqL4F4dzhbBJUFoXMb2KX/DvttKYmzw0td7PYe/N
9NrVZKlMkx70qzr3/ZLtVRkuwLdev54huwDsbWIm+LR68Bvmm/1BtbB9mvcj0Da/G1nejrOe8X2J
0AOZWady8yxh3vL56Z3geNp6WIMKaonL2IQC+TJYWDBJs37VoAwMBiiOhWf9yxmSgzknYB95Csje
GyLm+wj0ic3PjiEYw2TGjWBQP9gnC93vIodh724tHabKBjyjhJj2jtEWNrjQ0COzpkdo7jw/Yi6f
yPbkdBmApNXd5c5pDIOZNNPl+qkgKOoq92M/kVwn1Rs7C5QaHMBiCXEB8M8V+beeUO18DMA6BgrW
luhXFM0UxhRp4+umH333nBtLR9udwQ5M2G/PHZhwWKKwaSHEY3djjuCRbt7DO3E0UaNf6Kt3cxUw
KWojY6UvPLkVc5gxhteam7FHQ4OAo2jNEx65VRtIYcM7s6NF9FMR31k3MMEd0TOwdITaCO/QMu9N
p23kDwO4i5ShAxDamEiIRax7UzYkkB4i0ADd2b2tm4ubxXGU1pMDrg7mGK1d0Btyn/49JRE3LsWb
IqnNUYwBvGyl7BAMjWoKKPtiQiHdI5ELc2X3Z8ERZwl+HU/r6wRHDFLEULYJrmcDMRrUfeCD0Jt4
BtgV/8d+mTq7aAPYADGQNOfKZnpsxs7e/5aUK/FemBd3QMBzp78Cs9ZLn+CfC2nBc4GZgCRGatmu
cIdUw5sq2ntofOVK5uEht++yI+evuCgD1Cxj2AtYYS+SXBxrWzfs+Yrj4g4dPK25ZAamnN+uEI31
AJ8o8zqY4sxRd+UxCTQxY/jtGZFfz02irvVd1KgVsvLZNMkfQmFQBzO1kJFIfVu5pa7BG3MI/EiK
ptqbAyYZTKfKE7Bhun24iNrh2UmzwVevfvZfpyjrmCK5gGARN+B47BKBBl0yidiU8by5MOa7qzdv
veG14xdN+kOiA34XHtpjKMpmLGgXqCFXBq6lh965KOuwrfP32MpoE+2e+aAUpz15G53eORrTf3rL
dP504sJTAV3zgnogZMbRLNqJNPKqrGUnCU2fIiaqt74HVZpDjFVsfMjADXj7JPzBAWNn5SRI99sZ
5nDnlw57jONC6s8HBDBQzsMgrOWhsVwFZg6S2YMGpgp0OaBGxmWaLWF81GRdyp/RbONyKaAEFNHn
WI1uCGxHe9kLqQBKpYR2ZkzOQkfMqCdHcRysc63egBLKNRGIzYVW1fRj6pWdfPJ5pndVDNBSxi0p
iz2ujOWnn5FsKYwdDe+bSE49jEioI4JZAH2VWZQGR9PU6lr6vMYmrqvZ0nOzfJKRFXdUnq4300ey
xoh44WfKd6WaOOwvsFT8i6XycJvZ0bkZDCot0NATR1J5JwAdHXPG4BTwEF1O6z9o5Gt5ShERHVlG
Vkfv4f95xRF8kTlTgGZ9YD29dn6J7XIVWoZ8TxRPcVvc9jBC0dfao7pkz1DIsitDQpF+ZT104Hae
pMbwiqyccmDJgYa9z11gNBV8nB/fIDLUfEFnq6CsVF/EDprOLB+cgaQlASnBn9XaXJkBrvtJvnQm
01+g2HpHFaKSjfqEK+yGnQsiAp/5he8WX8CXVr+c/IYqA218cGtArOj9RErNNpjF6bmncUIU3J2w
Xuy/9JvtTrT5yHepcd6+rhXnpeYeeJk/lnNpj/UVsm+ZlFUjOFZcuQ1mEiQlGWebtRs6HuwXRbhW
g0mZ7hrvTnc9oRfn8HNckv3Evs78xijdHC7JdIGm+R+BjoyqDogTQviA4CXsb4Cyp/PSG1PjJQQQ
6pKTmpAc2CNUHHb2Ln27BZDUib09qed2dPz6TMUe9K4+GdQgH7kg9r9/yNhrMYaGxTWJBhOLaAFY
UiJEQ1oucJlIdQJ+2DqWUSwe62Zy1s5C+ZLpVMJPRIgQzqKuwrpztuefHuhFt6UfkTpXXddLDvtP
BAOyJkwjbEAvDiwHhshopa1f1sjKUpOJva6U0C+u52BW91Gr4c0QnQVCisGDsO94NcOsXwP/THlB
m/L/vX2dP2rS1KtTPNa3CRMlGQxu+3ggYvLsDVpqIGiF0vhgQWIgHnGmnEciO88T69uXmzU5qFJd
sBC6Hws6Ua6SUA8YPQ8xFYFcQVFxp/+aRLqyTejfVA3+I3lA7tLXAYTBpIhrzF4t6BZRGYvFzgz4
IXXNsFMy4HlY67iaYTDQ/qS3bDOv2KAmebBSbhgUDWqw7VZJeP+fZZPDU9nKVx9wyRA9Hk3k8lPD
9Tb30mQ61fwE1E/KmMAa8W0jv9a20itH4jvUa7FhqDx1Jq3H1Mgu5XGK/CUCGRL34AQAqhy8taaY
fN0au70dBusd8aAT/NbY03gLGGuMRSMWWHyAHeM4ML4gEjc8TmXoXHv5aPi2YDRvv/YUnxnKFK2f
tSO+snMbti7TW/G/+mDvhVGfIumsMJpVlWjvrimC8Ans+G/LsxguHPAnFg580yQi8NVxHLGBCqtQ
h+5PYTfrLmcpCI7uJ7CYIpTeh6OyhtRlHPQgurkMVGkjClQj2FQ+ZymQgFu8YBeujCT5H+gKSJE7
fd5uMBdDFCotC3yteSSpUu9nD5TzKLrR/TTMyTKO+X35H0D0KvEmodsBG3WEq0p/BfoU1P+nl521
9NmjU1RP/JbmgNyjuyxcK2gUsBl9jOjil1NEeSQhyrvnKxhwP9OqLi3FgS9MNUkSJkJKosp3Yucl
gxOdxA/zQKQBMYv5LMHPLYlKGxGYzlZS55Ga2xQPHFwWNdNmATFaBUZFuLgfzW9lJzfdXIjZpyhv
Y6s7HfzQS/CJQ44AVr2hymoH2Y1pKTSINF6LMvwA2nLAS/rjoqdGEqqAIDBVgJJFcYgEZTVd46EC
/o8VbCe9iu/2uzJ9QL/wTrqM48CiSZl1kF0xrFS/K/PklJurXP2VuRCyZ85FiW829pfRAq0tewK8
EaqYQ6fmsyMC/dvZ9klrZz2GwaYtCQt3Vvp32/HKyU7eTsm8kqbGFz19K+7q6kJCP7ovx7m1/gxj
4l8KPbjPw92UEoBP3tr4vvWP72+yirZ/yieLFjehZL1q1qRNESpKW2HihQBFZXsQqxFgkE20rtfQ
LgMeIC0VrXjoZMZKVAkjsKTRWS+aGq7JL33rStjkVqf6n9OwI9BNQ42yO3yWR8zmqvSjXqwQp9xk
0V5HopBV1mNs0a7E6XEijwcpIC9k0rxb61wdvOlIRFG27qlTU5Z8lFITRv6JEhSINY6fdHNPJhi1
/t9isnRcxuBa/hmZEn245oCH+pfYyVUdEbdvk41jXJKea3nlVjTbK7VyAauB/zkjoK3rtRqhzF5d
BbgkhKOwkpPwfcfI2h/loQcrgobWzO3/Wv1knwDT13bJ6gy9r/uCwHo7/L+NN6Pd9lOFhvsOhzgt
iLBXXBmu8TGcH8yo84bCH5VuM7TxuzdRqvW83zY5e98TVOU1/xyiVB8PVnORVFEPIa3+4Mrjgz+b
Xziq02/FOxNiZnwW0W1SqYN/8+ktz2Z/W00V1vz3S4TaJQYZ+dE/TXh/T2jKZVV4GjM31B/NTDAF
//8ymPZ4Q+RwHnku3m66rAFHOXRmIQ2gBCoph0Izbk8kSgPFuGDeiosGswYt4AO3Qa9+a9vwGcp9
QOEWLNu13MSh/txUW1z0BFY5yIuD91ZSMnyLo3x54wB8Sf8HWaI/WiFXZtNMiEUKG36NXL8vGPKW
aJvKEXK2D9B3enlrmW+xGmLC7sWwgV+oGgcspmLgbuKnFPwld5Pjzs9fRDzJUQFx+q4bkGXeUTkh
fXzJeiknqz6lBM3X8fZB7bEoLWiEcvWbVfTfnjPXfqFoDbfb8Lzks1WX04k0xrOOeRU3E571asnz
cyoyXfbNvG54YNePxiPlnTWOpBOvvvfcFkPrkoSx32AggQ7T6Dd6oF+d9zZtokD6yKZemV9foQ6B
O6Zqd2qFcVnCPerB28QasqJ1mMA/nhy4/VwC8EpgLXeGrSu+Gkbb+aLma492cAEh5n8eMOzxj4WW
EN259j3VErY4fgYXdBU4o7uc+AYMOOE9uPWYZtgxXx67phnEwc2+UYpjUw9tkT+dZumm3GcgqlB1
XVk1skideTllKbGhgiSi5IzvnKPCUHHGWlG/rY3XDmTp7iEbB8MrQ9cFTVhojl/3r1JM04CHPkTk
0+K+kimnuR/v7UZ9SBDge/x8kyKZ9rMVzpte+mBioXdmrs2VRpmt3PqKDFaXJ/KMGyQQwFf71yvu
ARdjCezq0X9XTrv5KRkbI171MgZWT7elrZx/UkVyCvYsZNnsUSAPtes16yYNBvmZItXzER+nbm1W
p9wbyS/8aw44mqvZlJ86I/lFdcRl7OtkTosCVP4+unF8uNp7HyMxFJbo2sdBXz5oWCFusuU3t7zS
coX6zVXBU3RVnThcHKXpwTOCU3A2nRFyVDiTBcjKqAQxMMjxSmKwLMB++Yw4BOxYvTi5bXU1iLJm
U3d7Ms61E4yxRlQQrHxbHOOoXoEl4EeLr/HNndeo/vqXQTYaHGtQDxNFgO/PQdIKTvYj7LbS7e7K
gi4JwGY4rJ8BZfOzx9RpUrYWGnM7BaWH8269g11ceFHWQMc64txv0XpYm7/i/o0kT4XUNZ/lrui8
wpuvmhZcXrWoxyptw8dNrc9HurAaxs8PlU/wi7bUijltagbweSSKPy1E9XvOy/RgM1J/H29MZXPj
TjBQNMCecWluUbntYLlQFfJZe98FK1pTOXXIaniMv5GUSQq29NHhiq+0+Qyj4YM5qjhruL+9VcLI
ZOtp9AHc3dbybk1iWIL+r3aKoQ/mFe/ZNYn2Z8t0bFJe4DMzfDnxLCXZN1PLwuThZ/k37egzxGHQ
9Wh+SxnHL5IxUcPcjXGjv64mmNuMZC/84jKTkZ1obSgpOg4b1Cksm5G6wns7TlpuCH+7j9I2lQf2
lYG8/cPh4/UCkCFYLIZiJzxpFREDN3iZSmrBIx0+b5S3ZVpravlA1WaAImGlgvEJ515gzmZ6vL4c
Ex/AYnY4hiRGeI3gPAP1UbUcufXJXXkuVDrf/1r1OR97IMSpCmuiI3ZaRG2Te5wJsIeD5HjKc6rV
ZRf+5Sfd7vkm6upiZo6i5Q07W/94k1w0Zj0+DLPxR6oguVJn12SKx7xrKOUI/MGZ64gwWeQ9fTYq
Mczm1IwH4mwd9jlPA4JSZWLs3CcdRa+cX/a40K+vKMEGFq+5FL5/TkHt8r19PykexPDncLCyLmkK
cu1WXczcxf6tghB9amn4MPVvCBXthWzrGX5+lyU94KjeCfktQdoh3x45PQ8ucxxurbFVTQ9X9Dm+
hIIvDs3+O75hR/Dqf5UZOGKd6ToCDv7dsjXdWP3M/ZAwqIKX/B6Pr4FpEyG/KkdEYVlwshXHixsA
W+A02ojI0+yha3guW9qzppnIUKfczMnKPppnPG88p0ILzHU1z15UTP+EvxudKWctaWObCV2nDnRq
UOO8UmWLMPQxkLZWsNsWfrCQujIRmAGUDM4ERcRoFGhvPIYg9bLK874DuoF1tXwuDqdUdK0SVaXP
+Ant3qqSGExF+6QnFoSfFq9lBZ4+Vka8du0Kr7C0szObA9zGwQs2mSAR5jpsbN9mrJBCxX4J9p/E
WzGMsAWE+stwSXJVZj8GXFWQAdltGLQ8vIqteg+klsVUW3d0W9H50B6BSoRMRNt6pezBWTR5aDN8
oI6ypI8O3Op2FXDfrTEq7pCjfA+/T8sGyctqcLe6mL4N2+mb6qBAc0OCaMcr9jmLlOAVgScfov+V
eJbmzhzP4y9/ecOT9+gXw3Gk11138w69KK6YwG1K43NK7L3BJU9z2udha609uQJwdIjpTZj+GamB
4w+G9AgjDjqd1bo85GGZXooWdJsT1j66FaRMWNW5s/y7467/5J1eZXX1JByhwSLo/gGUx4cbmgKu
C/sxmFS2JJ5L2ufawdCosg93OPecBwgQFIIr5O7Lz6Uj89RD1lUWMfuJD1fUP/dCLJs/Tml3nbZB
jyeBtJdnmiO79TcQBKiBkxt4LCvcDcu3ditHMb6QsBtsBKVr0MeEEQ96u8/40BZH0myiHWi4Dz5N
K680tnva9FH5unJXTh5Th+8orgIjPtQjEcMX5IvjBti+Y8lmLCwNBZtOmla76Q8TF9Q3omyacnCG
J2r+SuC52ruw42EwQ4GSnEZYEoWVhXoCid+FAbRmN/fzmtn3SxEpv2Gk7hylwWwYAsaZH0a8tR8h
ir54BGaJ4Lti3Jqu4e/ClZCvlluEyujC2PJUqKpqI/pFtmlBPf0xsvHSxaVil/MnvDFaOq/mpDjg
vmBkooP3aAUaQ3XWSQdzJxV4AhczfyLxzs7i2UgXqo64z1s2GiWSVrjwmqYc/uLC/wZuGpiXrXk0
7do7Anb9EbwTr2wxt2/Xxv5CyHDYlSIM7JVo7geRYwwK/uzsLSF1tqYrAPKD8KMYd/m62StcyZt2
lo6sb0lFEQ2grwScVT2jmwSxgFIpwEjHZEUoqFIsaEcbaUT9PJAD6xJx3qGNNFZERkfjRwx/JpOE
JogWPTdehxWML9zrBeOCe23h89tceE6Q2Bm3pjd6HehkinPrymsNtzpYLgsqXFVvE9z6mt7okDV6
fGWrxPkEDdd1stuBsTvmIru4vCo2UPqEwuCTPF0SmKTtWI6zZPFuYtwALWUopVhhtE78a+YR4e9r
vYmUsQqHdiQWVfrCB4Kj66HInmlq4wm/0350zjETKMpWmlS4isoXzzUvRUzEUuywjg5YEQkEqzqG
AqFUPJKHFVNeQJTNn/1VzRk3vKl8DXByfSwdO3RIdaPTAlxHi1QeGEgsxKvGFZrMH3URYpWG9aP/
NKXarjGBfJ0bGoUmRtdUGxRtNNantu9gkCmGv1JvQ58vKazI2HQ69ob+PzwAg1jcyPa3Gv8cLHbK
0zTVhqbz6/HfpwNRt6IUMArkz8WE+nRN8wSj8YbEv16b1CgkJgtl0XYvdQr/PFOb4bcLSbBPPtoq
mKYE/iBLDJlAahHD3GvC9GgfsSM2v4XplbhZRWNQuMyl4B4Dms7jI0YnWCPGzqxDrYGkI5QQQ0tx
mkSceBeyhkNZ49+yE7GReOEzv72X/FrKlME1RKvSoWVSBMtH+KdKAn5n27rIH3U74UwNCrxqKdty
zU7KEj40Wcwo+WFaeQ56DXgXkv7cXw6d7DETKivm7Xfyc5IUlY19jfL03S7N2pcX4pVSWr2s7a49
C4jbeMtzcEi70uZfT/d0gRerXbjlsb1YYHvCMx16cU735pMkoIkjuhwVdYTB3jQjBvy9z6K2AzPB
28EFOiiqW9V2oXwQKnIIYEqnziIGgIaxcip7DwjVTC0dDav9gA0l20kGaXqtK3w0BWq9pZSaLb6j
hqGr+TW+flW7PKGI7jULX9lXKfLEKkDRoXEmvdaO3qJSchyF3uA0/QAadDIqQXXD8f4rjdu8009v
4Qh33lomHswmclJXpQVT11+697hS3fd37MvQ/oK6HUXKYGlF19H82IQ6i8Pt3BbcpMoRkfRTOoU7
YoM+4cZwFh/qgpko0N6YfPuj8ruOW2Bp+MypgeuDgwc/Lq+fR4N9eMtYumWMnKD/eCge/VVWHupj
cucT6h8cUHkIig1+l4c8YKeXh4IYg0Dqzbt27iVzajdK8wpRxLhraidFw9vFhUZQ6/466HBfXpvq
VaF2wtrkK+7faiJGvtkjTsk0/5UbkmGlMhOqmKbfSwbRZQQI0gfET+0DneVh/m0+pppVwPYR3i3O
rVpzvx41azY4PSc6c5Qfw0bKB9BCB+TFPUfTbqluZiY2aR0r/sAQa3DGT5F6Dd1+7nkvv9zZXd7E
Eq6vs3UK+zlIshYBFbVX3ZUtG32njB7Vwuenn3oXAl4F9FUshUabM7azlwA3CbZ1CUIEvtNNdDvT
OhzXgTaL4uop9hYApmrqKz9KbcigEBbVNiU3Kj6/dCD+hp3is8wNL/gJd5JaMi8PeBmlAs5af1dy
6sdv3EWd7Fz1u9WzQjkuUd5cXK13n9EBFXPTAH3FEiVPlDxrc6fuZf/7xHgg9YqhytHadZWhMare
CRO0CVGPhu1nEM6VSLbh3WTewwdhjM6KD/RuzD8/Fkq5PjGH1YrTvpA+iLB/P5mXShRioumYrgao
QfNu37oinDmvRQLjAStav5mRR8egxyuPOBG74wRZ9R4OETfEvTiAqLhEDUZlFPL2TAJhV46amFjq
vNdAfGhwLWxJvKJuZ08wlrNMq2TX04XKzR63SgPWL/QjBKZrO7NUbyv8NcLbmJlWjyd6OwgBw8sb
0lelWO7eEmG0NGg+EAXlGpXQdhUGy7xdFtkkSFMWlGyCwAUkvRnsS+ppI5sOE8keDLCPVdKHzFZE
61X2IQRZtfvfAGCbrpKgkSUgErL1FibNKHeEAUIOtFlc1srepErBil2xNNh7xPu1CoDldolTke3O
zENT1UhDYk01l47fnLqbTZZjEnDHdH6PzKansIockmE/DcLkNGPs6MLdhAGvyB7FiuLn3LampTMo
RcsPH0smJQQ33dhOUnXcHk4Ft5ZxWTnpVOY9TK8XFVqTrjlzd/ayRMP3VvLsNc5KaH5eyijGorXv
RC77l9kzoTpfItb1r+amAKOtZIAhhnx4Xun9N+xo8gIEC8TuptN7xzBN3wDvW9sJ1tXCyY6E/v6q
3Gr8drwcTwxa1hXeDsqaUPKHbp7nv0LGfwxQUw2+CWePKBpwOJPQQLGAtAwyLszEoESeIsZtuLHs
RFQqQ61lZyKTSoZksJTE2rIEdIowEdXQOFKlcvIFJ/dRXulAeVpjxHDe4yKbz6oHi68XNidxgAKf
ZGouzLTxp5NqDoEVMK2IMtHURWeopk8oUdPRAU1IXbZNCv+M8EMEscBD28VlLZd0bUIgVBtpyRRq
8VJj83rz1l2hZglY3Zkel0AOyc232913FcgMxGDgEDzjCYf0gKNH7S7LyjJZTulUmW8R+tajtftL
kDsQf5kc0gXT+3uZ8rv/WOVxlQTk+NprjcfuRFdKLWQiYerpiJaCQUUw6XSndKkQd7qn8SYnpYXt
IvEFjsNb2Taq2JA+evaL14zH3bHQvn2QsArjtltMF6Bm3zYVVe1u/Ra05mOttiXcI1RnekxOqJdb
Lztwz5F5JGRqEolLM4sSz0FWyHyqk3miXKDc5VvazhxFeiv6ip6SLTACznUv216wYbtANdvc93OS
Y2CyasBEqOzDVskCcuxwGQmeYKKIK4G6pG6VKTOACtVfIuRU5NebZrWYr9VKgopL+p8X0nUJPa7w
VV4btdlDxKQcOhpW1oprRdZPoS1D3qKHOHFdJSHHGLuk2GIY6d/4iF9U4W64Fvr3+5uCIe/8nw7I
mtdwG4BvnviZKtHlirJbiD+pWiU/3lj2JU/xZLlGYAmL+iMRN66Ueg44b0D7KWrhSBEzTeh3EpXS
cLjYZxkyaGxN5zx+aZi5hPBXDBOvoAqNJ5rt54ak/WVJZ6rfNNc++Lzvg4jZaej7Ae1KQ+PkZ9F6
O5nO/QH6wKvbS7wBvOl/KNMj3h9+SpoMZWQGv+sugvtZ2fP2LTRMuFhd+pXaJP+IqVF19auBBtA+
EKDd/L3dZBsiRWGyWmnQeHZHbxG2V18cjy3Xrtt3RSq3HJdzLjhhuVOEvvGVyvWPZbnR+gpY5I9M
3Lf8qpN6ppVkKQmThtR87odsLUWAz4X+vRypSBIjmjzkggXSx5OS2E34Oe3P2nMV2brUWG59QiJH
4Dmk81koZlds8+IkfsDyEjUU5Wdv2myHiIuQX9A4wi4Ev3dWsMQb8Gc0aJwQBXxS3pDL0m/euF4t
NFezpFkFp82DNJ3tvOboHm9W6lcN9Ah+tmIX4xewV+iYtu7hF7d2tSdblsODt2Eth1utscmxfc2s
pQsHBfunkclCG5x4ixcMViq3Vf4gujxxsZg4BB7QVc1quRbHXQLByAd3Kuvt1rjTyGHeXoIAP8bV
E1S0PGKxBwPFU3VRQ00JimgyBeOzn0BWoFSbeD9doH0Nl2WLFdi/FR2SyqrhDQy9mj5UCo+NES5h
D/7riKfBvEGz8bPbQ09sLYIfG8CGM84+TaR80d1gPf1OLL9lNf74LZRkYPL0xTgmn8l9Sg7BV1tn
JRMPO9Gdpd6jeGpRtWrPf9NhZ8aUcqBBy4J1e1e5l+1EL6n91qmXC56WFCQAi8vFuCYaGJgkVLCh
xCPQRuHq6zFXlmwRFH4nirqJg4LKkbXfN/uqq1vAn/OWVZvM16tWu5l3OCYqzfRoJSQz99HmFG39
di5GPfgMQtpTTmQQ9bAfuqBnKxjmFU+pcbzV3P1bKUdeVbG3p+Ziw69tRtT8h2ovCuYMO/WZ66tO
yuFat9b/3MKKUpKxsHVeBiQEvWuhhp4j/P/ICngfOB+OaauTTyvRz0L/XdN56w7ma2A1vGdQwHtn
u7mnWZqY2cZnWqp6qtXhMq0MU7hga+1BOf9K9wnkonMlEcFI/xnlonLQZey/THDXPtIY5ghHF+it
SMQB9G558Zaa1qANUGy44hOshMGB75pZjEJrKQ05PESJeKq27x/xcKt1KCtZQZ16LSSbFTHHyeUI
N4ilIJNFyMuDfgCewMeZXMdz9J6t4EqhYGpVd4Va/AILPBKWGjm6ZtkGsJD0SzLgLVXu1GfIQgDX
n0Io9OqfdC4NmcHAv0afBTiFzr/p3QwZLSNDKePfGFb+0wm4fTRVndgDiQ+zy7AnTuDgI6Wm5zi4
hr/nrMTpcw28DMFPn17V9JU7ljQ4u97zyJfCVNGtNi8le3oglRghv0Y8is+ooI8DzXJNnwfkSbVD
R6x9luPIwlfCEDBd51181b3aprmfNcl8p7sH78TPlJpBXo9xBI0yYeP7K8chW6+Y3pc89x9nzE9a
580A3tlmUEvZtyDF19JT+nAanUATpt91XM0srhNtEXwZQbMBVtS4N6/SRfRdJw9wv1KcNQc1xzZn
tZJWEbtfSKA84Ztg0DZqCa097CycCt14AZbC6l5POE4ZgjYWYbdsru8peq4r4lAnJqWBEGDMFWNU
jFwoXbeEuWFE/9lqZkc67jFQENC36B3nTg3UW8MG8xmznf49mwyeEsddespMHTtAJm/nNN0gLLZ/
Ouw/FFsLa7qEnQqKB2V4rfaJDo91ANFnrFHHNELb6h79SVm54sctjrw+6d2O3IUeUZFjttCr7qEy
uuYosYnPhTfk12YTQUmrXHI17MPp5RY8+kKBlPkMtFJI3PQtIQJ7KDvFLmioPv2tPBKamfwmSPM2
bAd0d/kfUwJBEMyOjBqkunSTC/Xxh03gJsV5g/9ZV4cM8/Ir5RAMSZSoRcuzECm9LhBMlETLrI4n
cpO3nma8CogadOQipd2O4d4gWd6LmIjG4QdYnZu8pc9gwkhOyJDnZ5gy8Rv54OllytAhcYqZe3q/
QT8CbZ/4ZEXQji+za8iVfoU2pMYxH5e48TfjhEAP7SfutS0l596vs518X71Avn54LSO+XcGL44te
Ya4Nwp+9YIBWlyRL1ZXdiHaNkVyUGYDouIXD6poFKNHelPRtiSrAnxxyipWVSI9bgkBdueri16vt
5a4ArIhiuUIYHSGRC2+y8cb+3NTQznZYe098HpKiTbC2qy2WSt0uT+rj+LoN01L7iqQV4eNmFJjJ
fb7Am8Q2W9PH4YnhH/CmwrBYboBjji2izihCbUEPekH4iFBdf12V8CEgY/axdRugJCUZWmOUD4n2
RTeMMIcWNGXNfzkZ7N4wWHw3Y255bTncvU9YnWtiCd5JpurVpHbnI0ENsEs8CKTsc+HSSwIfXXmV
oz6Otb+vCTVhxZp4/J/wMjWqW8EPH0oAAVuWiZ34HAMewLZU9Txq9cQ5mExMPt6OC94MTJPQWVbq
8ktuReAGqA7c1+ooX9+ctb0QtAhbKuDFrtV1owytL+ahESMWlkCbZxmXnFspzESwloi1gUspG9Vx
UCY/TOx9puvGuctMiqeaLdf405saqGJj18QauXJPZcqpOTjpSD179sJbkQDq+5NGvqOnYnQ2K4XL
/uFxS9kwYUnHsdinONAzRZH28XDWlNQsRgUxTjHPxASZsu9+iBIINMryi5FRoPTiWYwFIHiiXgA1
vlYpVLo0AcslZjPWb6Fi7aT9MlmlsJXCgMiAqTqWdhWFJRsYTzemHeAwjAWholby5kdSzrCSQwDu
3qIw+SC08hLIrFSHTOjKSRFDj3U8KKDDjg+wR8esY3NfD14eD0Mbc/ZlfrEkW3S42HdkYBN0gUWi
AgmUe8VZREJ7P5QkN6CNXlXRsDtuwS1mGZX+Z6+34PDKASRZhyD1Iz8+i+s87z27nfoM/hPB10Ya
BgnehCx8EUuvIXLpYci90CHuLO8C7SYngwhEGNnTMon5epk6Cqz4RBHSmW0UBB4PVVU+l7DgQfFC
NyCGdMADWeU0wDpyRTv7kEZSk1stLwcCDyOi6zN8ZiQHoPwB5pCNesrr62zt4rll9U+NFnXmJE01
zYcBkZQHTeNDorAsaWw09mjT2aIWk4eaxdMpoQsWBSSquwr1PEBpnCIAmOMuou/x3ggK67Gs9TuA
IstSerr3SGTuaUTJlfkig/B94ort+Q8PgRKUWArscHTL+ypLXhC9IdauDUC7tA7T1uk7Xop68Xp+
TATeXYUoAnBfImxy/vf95pkGO96AOMzw+Mf3ClIbkG112KrtU1Rw+gtmAjhfAVIyjv+IU/oXtZAL
srOmlGTuUTv07x2xX73+3faC81k0+9hf+VEMEVtldrkX4ZPd6Yozr/PYcHI4FW+87DrqPICkUjHE
dBMGfu6HqFMI8FnF6wof3VnW43T1kC1XPGcR8OETKBgp0VgbTNbWUhvbqsQGKifc2LfpOx36s1vh
NP4GnCjL4c3k1c1MLb5LStcytTDQH9pYYRAwrvlN2rshyE51PiRBqR0naD6AcKk0K8gPGhSRCi0I
YlBZXdu9HkhUunWtTilteVQu1O+qRtUGj9Z//xIAuaL43N5g3ngQvlydajgWKEY3dFIpOGzzh+Kz
nOx4r2JzBZ2Fw90SvDPaVYmO2xdUvtcvD4Iv7oASaA0ReUKDdULcHQysKEFhM8WeXa6a8J118qvz
zTO9qqhHrHWNCyanCtN7Au1lUiFaHymfV+NTjPbMaYAO9hxmUO9r9G/KOXDBE2p9qSaNpzGVTmDs
tpRXbTJYp3tY/K5fHQXTEQnsNEi1b6KTjuoKWMHy1VTlyPIKQHT1GyjssEIaqASifih2xC8tuRO/
8fMmHA80GxmMR4teXlzp0O+wUR4ZcUn4jOIXARR67cB13D3x6VFnYnvCxt8wNZ2xT5VBrkwtoLye
OZQ4wekYmkBcAiXEpV4/H/ETJpb9wn5xw6JdKWePtrHUQYqAiFYtWnLK0r3bs/mTAxXMJ63y+0aM
3edVWDq2Pk775GMRWbM9XhXMJKIoIgx+UtSANYso/5ATzB8csNmyerAL5ZQKM3rUx4hqdZy5xRjI
La0OYoPj6ldxqbBeNf1Uuv39ssF89pSsCYztygS+VacqMp2072w4k18JnrYj49C4LULYbRSzhot+
yH4ltME7wDIWFYWTtZb0ew56Yli6Ej9T/M/iewaAn6lehXdSt1MrstipWaxrZjIRt0K1MuoRl5Ka
TlLox5SSt/TZIoEQ4VP+vOptF6jL32WPf9YFlcbm4ZBPfi5FVvd35z0paCWkhIVK685QG9EJOPqF
kD+GVx59Ercxs2hahOy8NeClb0CjjFAMB0DNuPLXcQlTUGsVYFPHZhfQOWazTmL/ZBChI1QsL54N
bc4k1c6AjgKE13Q/A17SZxcwglktNE49BinBpOKGOAx3w+wqoYBz9f9H4AP7pjdJvodGGnhkYrbR
xTYTrQj7aY4a+Lo3uhI+l0/ZrAgTd6naTYwDipjaclDPAnvRiP91HGFOvmPfaq/mominVRtb5fFC
F3p8kWcVj1pDikEStAUQUikUf5FAmYmBpqhA7mfgB5HLFpLf8ThIUwmIVUPt9opVxK9zGJumXTLZ
kCgaJd+h9R50bvnzBu7bkr0NwqHEKd4WgLDrL1srtvBj3PVDeK++I623+vlyX/oXCtV41ktm3kUp
v80Zklhlg1qB4Ku8cR5MlxMq15r2tvkJoXbj/0lUpd09WLFo3yq7xxH+9QUzP4r3sNtRD99rGRfR
Z5mWKxDdDe6V+wZoKyw2FHtb6NPqabnAKRhdKffdvm3yhsglLcWtIAP4PxXutcoYVRWH+nXdWcvN
zBAXMWAtMvG1VGMt8W3q4ScvAsRl2rD9uaIUTMvuU1Cw6sdn49/RmNyZKSkB22fH8bNnXQWesGe0
Sqz8sj+K6EPHbN3Javpk3yWPZgaZ3gzjfW74YWB5kw8i7nhyNQw/G3RMr4tElRaXcZCJ4T4MfP35
o513pCwzgxE0fM2vtMzpfqGvWs1NGzQrL+OddYEJXocn/3Dms/Sm/jt0mOHIIL5pNiyHBNxDn8LA
lWBGjBsbWaeKUolibXP3+/oZBg9mi7xlL9aD9k4iQnPNXzLKmNGHXCekF+eFsy+D9rIMUKYOZiFR
v87U/wAS+J9D3eg9Td9x6lzMP5iQZzDorji4DEGK3YRRhJojuTclGNGRk6M8muITAA40IdU64wns
gywbTkJE4yO17ipmPR59C/jI9caxkVKh297rNW/FIaDwzX4to9QDLSbShz2HlY2WkMbtgluvrfLF
auzGq10PjWozQd3uCes6M0b1Fdu4V+OXUVf0EtTDRv9YxPuwY0K6W+dA0eMuRJfqJdsVmVyM4Oae
enMI4U9nvxHQvZQSIL4vnb7cxArAS3p39POQM/kjFeo1rxGnQDR/cl+WHJJWPpCEel1arfGYkzWI
NgTkbRsKWRTt6ahOYbMJUyE+T9D8/4eFIQdOhubY66a5YMZRKZq6b+fImxJHUdQrQ9BDIVqjIPwc
/bd7oOHbmmi9f+WrZUjgs3FjQ2DBeXwAuUAYC/yjp4QLhopZV2YnKMyZrsN7YSFW/scsZxXrSVG+
mYfklONS6oNK+OHkbel1u81IA7mYtbEJXmKDq0AG84Sy+YJjG8DVTlXzk2/YZrEuDSW8WU5XJaYt
UeiGPR4GPPUNuznq0wr/Dv4BgRlwGjKgfW3c4jCF1VtkTYVkzf7W/c4X6itcvLWf43tFaqpV1MKu
tlI7/gSkNFgPlO9lJGiNirOq6Ja+9AWSDYjzOpA1h+UTaG0db2egYTtz5AaLvt+5XvzbFrf9Bb1o
aMV7gAa/c6wXcKd185XbWLDo4PsLD70lDDPLi0IoHkehw3LzBtCTiU+3owgdTHX35DthPERg1DP0
yyxRfCZrXcMXY/72pdABptf00V2vq6paQX4RSSi1/UeUQGmDtZu8r8XvYozVY28CK72ViFGJzVa/
jsv2k1Zae668nE128r/cFBgrMwFnFt7qq7BS2GNNoQOjovX+VGLSQAgIKBCnBb9l1AeX+R21T+sJ
TX9kHqeBxegaBPXRlnJFCbbIG0Sz9yQohQeZ8Xqb7/3jrTXDgygDw6DHLZ7Wh8QGqRXskEX2a/zw
UQ9YwDHf3mw/3e4nQapC+ySVFQQfuLFcxhFrD5YnoTeWLZiuxY8C3RDlgVlJAOhBS31mK0RV+Lmz
EBmAbVeFVXN0YVKVbL90VWpndYsSyKtrmju5iYyzL5lWCZ28vQ7XvG7vUam2e8pS078DwQsv6OZm
P19jDYOidWepELczRBa6NXRpv9sURcYhldUHaQXYZpcUzfuUcjhQxLjfPzV0PdHHnxd+RD6xas4l
qfpAQ07e+yiLbZze9/CPJmH3L2Yk0EUMrl9g7+oIVok/YEt4eERHa+vqgpuS29jymAYFLq8Lzvsb
SgKgGxCSMrgBLB0gV6Lhvd6RGwkYuaX3ZnsFa/ESWAO+ZN3KtomPL0a5jz5CufhT4ZdC5LLX5u6p
F2SW/os+yQGDzEIbex1UC5az57s1bXnTKE63RAOfrYw+NRYxQhbpUQw5BkrcPDcE1M1HNcdtGeHm
tq18GEtdIq6IffXkWYTYsfvbjKuwHQSjx7apA6G6CmqdKuPpnqDILSGFCNWmmId504BY7Fwcjb6d
jw69f7y7Z3HPMkJ/ARWN2b8pgHdQM6/e18iclh+di+aI2rdpEPfjIlq/BQ3nLy1x3QiO3yc/cohp
WSFsq9lQ5dXga/sVwDjPJ5EPKg1tfX3msHd/NaiFZmsDWXij8bREPe2WZopHJQjGEnjyZai9OtQi
WpGTxfOd6rbVceUGWf3LOzJykVBZkppX8n51BQ3km/0wzZhW3l4tVE1HGLJsZ0oWmNxYN6791CkN
XjZRbVzr47IpoNb0ihp6XvoiJAqxPyrk51M8Uv5Y6jJ3x+FA9Iz8QGTvqW2bjf18fORSay8/HdQX
dhybbb8yx6EJFcS17pGv68x8modxZucrAqN/YJYw6sXmkANPg2S8k72EPoHr6LGKIRcssRci4U3Z
oZj/hU0H4wI3nRo9pwmRiYbDkfGbvwP3EUHIsuNDIvkqqc9JDzunQ51vGFnqQd50Z9GT4h3LISFe
Ermjp8QaN3XkeALRwX+GyRUXuCRzgpbO/3NyKuD2c7n5dEWcT8y79Z+rVO3PhnR/NXp8Hq9BhWyN
3zOWth2YrjzfBcqME3sLz52Ho3L4Sw9932cAvBYymg3RPnYNu/0wvqjn+/9R1h8U3+5mN3Us5xK5
GN52JM1KppRuqcVpJdrdoS4st8Z6htEUvsaPOSW9WDyi1rYOujPfzmqzLyLbHLFnBb6h+GokLT29
FeCS0PK3ltDU+OYbcQozHEqpkIomjiA9mYecqK8HATMRRS2b8NOBiTmbaPM9lfEvUNouGH3yW6pa
qiXRBSI776XmEjuXUE1J9irKJGi4uEM8Rhc2lATU20hSunZQLk/+VuRn8ugTUQRO+Yls+fYTjG4+
UYXUxbXQwPxhnI1ma5iZcMG3ECZCp2IzGRJbbPK9dmSMzc+ee6wpA5+lxzRU+0iXJMY7tuws/vqT
EVIbjYMNbHjZyhmHVlqhwkZV/g56Y52JiHE2SrTPYaDTq7PbQN+34jQNzdVpgtff71tlvmcHF+Zo
diUWRQfA+hdEeGeolg6Z+8Le1WBkV0/IEaEcgvsuPruR2A/ER/M3TOawhX9cdmNS9ZSB4GXgJxe5
oydwbcWd0XSPjUG26ea6M606fdhfgM9hHpecC1aZXBsifmFByFVTrMXrF8VgsEsx9Q1HsXF5qKfp
FADv//835yBbmzEgcBrYI5FcWDza++SWnBt4pk0UM+ZKUJSCHe/2RgcqTvGm3+UrT6mUaCTpAva6
aLmV6Ktr3F5C2iRaLY6CajDZ1GScSIoMRF0ixxGQPg/hXwTJaAwH7HX7g/x8lzuHEcNilFFAyzwy
9viSNP3TIEJFYHf9psSLH8nQkn4GmUb4rdiy0aCQzQEB8uylOy31voiHIxSpkuaxc0ONVh4/EKs5
X82Kx3mW3aMekq/4uXkx8a1E5npfqzrBFI1miNyFCKIqxQZUjHfheY2b3SnN4hoOVaqkHhLsdFhk
8rl1NsjMWPwRQ9EQ6omCbS1jXGvNGOyau30rttnjBtvD/5HS9QNFxol1LZ82TRycLFEyu2GUNJw3
2xO5oAPYMtiUNHY27V3xqi6fRK9Cg4GbtFRqsBsb7ZN1zGUkTotn/dmyugLfTOE5qpXWF6+ark0P
k0G9Bz7f5BLHk3yfdyDJtp8dgr9jCRfD8BS+xO+Y+chauv3cOjatZVOiKvHzMuo5sxR2a277tqNl
qnPTeA1kRUbZP99xVxDFOB07jLTIpVNazY27gcoduZQspAn2WF0w8jMeC546QzF5nqEzyqwN5RUh
4iRdzefa/q7lqEA5MJUcM7T+nQsV4ESizcnXT7IU4fCgMlCAsTTKOiDU1L8dqy4wiCyh6QclQj1O
v/oEJlJRD7hxorz6TLwxv6sc4iLXLqHOatGz7+iSaRnB0xAANaZqh1uW8d0K3PurNCIO0qfW6JTx
BPqd9VWibhPA//E38ofUvCV+sswZBW5J+ep3/uHzWrcZ4CfklzriyswQqT5UQaOQXfp/DzqCo0tS
lfMvRzwnVFiDceLHc2COfHaKLNZ86zWepReyLv39F6ODmkHeWbKDk1Gnq9CESvpXEtNGrPuLdI4J
pxasanH7GkcPHXDby0IIvr7riK2dqp1Kiu2FFEPK3t/S4L4/3/c4wk67rFDVkbC/keJxZ5k6jba0
HTh2byq09OYaKf2T9N5vIuRKiDqXowwMLLpqrNVT+wYKzHPg2s3jZwegvpxJ1rZVA9bPCaigaWh/
PBUoIBOTQcN5fZZzWC8O/1NbGGX+0F4OIw+8WBu6D9amXMGrTf0gtkDTGRxjWiiRX2BKis1R4qYT
VjBRW/B255CFTdLc8zdQWmEG/IIqACUVTQJzx0BQjvpa9PNTsgNr7JKDBDgMrK9Ad+9gdftzzqF8
Sbq8qz/cJFNOiAGw7Wsg6dYK1n1ZdIpI9RGSG1g1+H5W6HMh8wOxNndLQPEDhFzQq+HypJMociZi
WqSVT9RWbgKiqj2KJGNk9bvZkrKTcaY2nxuP1drX6+khQdYZS1FMLBUK5eew7wJkGdMxE6LUKwfu
tyWEW7Gi8ADEwJhEIxoxFlssLTS+9RdEIsfuSataW3G1RKgomv70SX69r186lOaLvVEkVH9Obquy
CmqDf6kFowtEwCzMZ7GAcc5dnrhLbQNEEGDHZFE5Dy9i8Csi8MiE27l+S0Mx3TRzaiUrRR9I4NN/
5n5y2Hx56jZJ19ooX8Gj8UP1mVnhlRXwtN/uMs17izT1mbQfBjjvnl7D6lUzqnaZBReqlTyzx21P
orvAKxgBU+iTXBXzrSfhVfOFCNHMM5SpanZ4+cYghqVgxW4SoF+2vymMSvahOibNk7Co8z43TEI1
1A9BovoPKrIq14m/+EAPL114khsR/uKnnweyLSzx5Aj2IJ5tUjCrZlQUsOvpIbbmn7TgU+8KZAy8
V2mdvYzvrHJr79Zo7+wsvPPG7nnuWcnGl52N6Ud+Znah7yfO68FYGfJjMW4ozBBHzBErTguCylqT
jTtFoE6HfHfqtiX6aLPvHzwayzZOuVxu/ONYkhkm7S7dDsP8zERQTKEIQQfFdzy/XqH+ty/6pJKX
y30aFDKY1qg5WwfBYYiMct7HPeK6QSlD2H4iOutROqiDVDWrjNaMYit1iDE8pfWdGFxDk0XAqp3n
N3lQk3eVbJta6nXavRodv3M0VvU0pjREurnfgAsEOd9Wg7kAlNmSyrFoAPPZPXdolTZg+TvouvyQ
+NAQ8P1gIfKpttxCsFUrrpzhvC95nO0JvmwTyMexOCskLyEsA4KQiuUolZE5FbJmibcCt2oe18T5
RqnJ7Ca9zvYHzLc/UhL0FZkR2tYlZVAuZ4SHihNmEmPvrXVOHNFfcpGZSXqVwtzKsoZWWmhL6lLz
iLXS7exUH2LEMUuTsqzj2JAf3HXwi3P0oqGJPp2csAM3GFfvAtsPTCmvU/cspyARZWEYiWi2gwM2
7JkUpuVE84hPOCNe3Z4on9TxYW5pWOsX9HUq8HPvZgAwc0jThqO2//Lhr9R0XzVkyeXx4/i7r40Y
u8bu3MAULHh5WRnqRPeK+ah3LsQiRX4y3753ra4gYv3oLDI371wBdbj5pjzUMLW7Z/AJsNCFXxgo
hysU1BBnzNbICG4iTVzk0GwIvMfO+quiRSpMwn1KP6vPFJDdIYNP2W+Vyla8/hNP6mHe+iBdVkHK
debNHEYA77AVJrBzTAYdVrTL+83CCBAyAd5P5C1drOOo3qBEwlVngdI8c6LxfLjUxlcMMU3xT5/m
5dNCStYJiDqJSTtI5JBEHTPb68EJgJPGZ4DOOt5BWigF1a76wsTsYNX2BjXlAzBedowx5N5nIO5K
pN14KrQi3xH0aAE9ZYRW1QJ5VKOfksBVlBooNNasvua7hKWNQ87bu1XL1QqLN8PphdJeVYo4aSbz
lP4Rui5KJc3tAhWEHvAjlfWsdU4RhufQv2nWC+flEmC3yvueQ2X1gumfQj4o31Pf2XIMFfpOt4fG
6PyH94ulZUaR0xcCL9niYhKCBT4FiElbhBE52fuK0G7ZtBRvYEarXpYI64TjLre2HJMPk1auacJ9
6VdUXccZ51FGeRplDAkAt/feU1YBY2cg/dQw3Fcw33UwhjT18tnF150Fg9Rpr+Q2XhKDKj241SX3
Pnr/siolw6ergCRqKHhB5aj9Q24wx7cxcRUJhkZES2aG1Iit9Ucty65Ha17BwmicVf17tN1b2N/B
Jw0/0ZgfMt5H9TzMlLkYgYG/pJ/fTXMG8Y1zyGRNFUdxn5C0Qwu8VeOOabKF78VCQs1bVyiLDmVk
3Pr3wH4Aln6DigPJW+YhgsjCRScBCpprMflc4KmMYTM/PdLIgN21c90wq1nIKbnyR1LDiXDFJova
LPwrlNZ93E7+DupLuL21sWg3sTHEP/sHqCGaqMZ6LnL9q7zZpwWofgaXNi71F38WltOfhz5BF4HL
kJcXdhuRmGllxHMrAuOzauDnvuDEA58EDynDtLyKaunmtW9Yqr8VQ7tvzlROhMEYVqZX6/Botxai
jD5cTgSGglwgpbnt/CKGSUQXa03Mb6hHhUpK/LBnbZ/Pd+zsbye/IM+OmvKZal2nJGQFBSBIeofo
f2UozZeAzeOgo116tqvjUc+iAwXSXUrBmIemL6X1zT9KCnn7QeKmGUzQeEkgZ6mqOU7AI3Z2pBF9
jCyEiVBl7s9w3b6O67ue3KdLKI5O3msPw3Vz0MdsgZ4glPVGiCMcSE58pq/6eworTLzX6lrWJrsW
T0Ridp4R9GqAEOih5AsOY/NXGabyd5VKsiJgxYqey6fujpsWPWpXZTznqShB7LdMoMKx/zXZkQ7d
J6xG98Yn/osCebafmqP76Kbmmcd+WbVKeZ8tuNWR2eahXyq+1DHGuWE940ayJAwOimu5ru893iVE
pzg/BdZwLO7r4KFMRK0GljUi9CTmRxSLcn7szxXGmm/fGd1rIWcMWu7mSTHDCjvaGuXzJ50eQlPJ
x87xq/D79TprwbKxtlJfOYWyPAbn6uUnsFacJblscXhGRAS9CDwM7U1DALHSEGYqwYs8x3DwdrmE
YeN7m5XSTNJFuSZynn5Azw9odfbEwN2CLS9u+f256jAD1CVE6qIHmF7ox0U4lNZNQp+QwB8xN+PA
i6rMwQpBD11xGt+5i8aBW9VC+51Q1pUcesIalLMn73zVHG4I4mep0e3KaIoKZrLnOrwffp5ToNKQ
9jcDHToiXF78g+t0usGOw731u2z7Vnt4ii+KnCMeIsJ07XYLURQWL624pwxEM0ISgb2p9YJYu2UL
2Gee7jIntlp8k3mz0DPYHSQbR8S/n1o+HG2qN0b/1fXDN4jpfhIiXiqCTckddarIQiJkyrZZp4n/
0sDgzS/e/ujW+9kMbTdW6VBhsAo5ALFlXKxK+4I/+6J/nL2PrA5HobePrOa6V+w4K8NnOz6mL5qe
29jnx9kWPM2cYHURd3OgbmyNPyZH/4zAWfnbTR/RULXIYndn+fzduV5UgwSKHvnVAunhH04yKgHo
oYe3x9IkHJ/DjCyC3pegomw5wR+WYYc3Hs7TZ9dZxvQVbsHDIYZy+GA1mDb74ztBZBfB6nYGwVcy
VtLB89XkX6LOwqJtclz6+bS69fppBfEnZrXPlri8Rc61cxS5PCuwCobG9kfq+hVXMhXiVtySR2nA
0f8HrpzAyQ0Umb+/5RBGAamT0JsPv03DnuXE2/04jUoM4ncipUrRTRKOlLA8+XMpPQs+DUB40LJo
3u86broNoEOIg0bX09fqHP77aojBxQsNXduNpBYycRu0Rq16lQBUVB4s4o4TwDP+kDPSNTic1YR2
iWIIj0fJDVbPfDVFJw2OLEmj/IsSNyRzHB8Kl4UzfR6i6WB7I0BzUqbF3V1Hsec8KP5jOHRIifKY
V8AHhF6AGsIIqLdrhFxE8a4FEid6LhXLcYd3FsgeypeZSypKrQ26EawqHTaU7QmwEAH5+LmQBFvo
8CNjUcrwYOqBoKrVQhRy5r0tOeq/zxO1gPry9N2KKoB3PrrLEOggB0jHcBWja12ileQQcagC3o58
++nkDw1dKU5QFHv1GU9hx0tcFlDMMnC5+03eNTgrXHtgGLk418r02o+Ed/OWndN3iDyxc6xBexAa
q/ENl5CfTUMSgz2I4AJDyIKKQthIwU/3QsAGWGZFl8LgBpSVO4FIrl14QiXzewHHMcdrXYW7SvgN
1afW++h70cHfKEi4rZVhqldj+USsQYm/b77tJ7kSDiN0srEfZm4omkS7xldnJPpV74ODTrsnUK7F
+6xIIyVovLnNn3Fsp95+mV0EntHJYlKnNHOHvwGpBlAuw3IqzrdBHwCyMzLPX10AZP3Dl487b+0U
437gHFIpQy/yb0kt5Fad8S73YTu2Tz0zAzDuVeumntLIxZ6GtysKcCNsePBp5DHqBQ7MH+Cfwffg
IL7v3LzOGN3kknWHkdCsUodQzzHAjnLEEZOxHxM5BRisUJX5LWAMQZyoAHlG2qdipzGF4ovKume7
3e2MWEo/AnKeU+0j8hjxyYiJXj2fERSI0QMdPMCdCnjoie/G4V3mKpcMSmwmJBnFu6D0fbGyVKX7
BTuUGkgtBf1C29Y6wEz+Zj1ErwamwnODomjOGdAHyRekPTmSYNKZdPPLAoFF/Bkwvcp47mXXnGyQ
95F4XTNS+kX0M1nw0jTNAAZT3zhcOf+KwBOMHkKs9BdijhpF+DGw01mIfy3fP7Da+y+EI9TT0ypR
c3XfW5ug0NQKQgDZbCsxzV52jIAf2keiqkwjQwS7PNJtbo+VgTrkB7YpGHV/aBO0ZcBa5OuYAi98
suoraEqQsAYUBE181Q7qLGvxHruhHIt0Hp2aCeXiQtdJ7oLxnuC05lgLOuPkpoWLowua1K6wmq4O
EmKpl8RUFvYil47+7ah4Qq0Zku2r9pJRWEVU08H5Z2A6ejuOxbYebOvpyW1FXlJvAItOH76qrp5R
o8KrClSpN9M+9RJU0tC1HjY8htVvrJQrm21Kw3TGsC/9v/ng0TvTZDbdcprI89p4/QNevuz2pyIw
AeBAUynxD+AGAgrTS+/JlnVt/70r56Pb/FJV0tIfXk31XvKj8jTlwqkYWF4sgRFUL6IhOt4HC0TK
ICEPRV3I7r6ZehqLa38ZwqenbMUbTcU0hXRROPQy7D479LrCvB8pcMcQhHhS2/u9U7/vZCrhNUAJ
rJspflGs1aFWHyxaw7kHvWl+lPKs6+jQfP0GIY4E55WA5DFRgjA06S+x1N0IQJanoPu+UkdKEyXH
d+xu8QEWB2VeMYx99iFR92/rcpBpTAIz5THF0ffCK0DYotuPX75tje+LdpEtrlWCqJfhgvhS2RtT
RVea/UEJZN43+FuJ9bo0H82JBixmEdtFn77Qba+umvTaOpMhv0YO9EWLU5AfHs0UEgrqqQgNP24N
+9UU/3Of7tBUAB1R9s4RyqZPPFJbaC2yzmrjeWewHPKsKNqHOZKbEMrLAnk6fVRjRUtGIhoNMZgR
VpHmEAbbaqu/lQdB5IYGPVcUipxzYeFL7I7GyWlYBT8vu0eHy+rLvvHzQO56801VNua+/NSp16C2
CwLEBCV2ItwgKuXTgAQhlReZ0bzhBveoUtKNUAvCyAKVYS6W1UYpi6KTtvAQtse9alnnIxKWFVAt
XLADSEkSN1BmDZpfuQ9zG378ZQccyd87k+ZqlNLeN4o5mF+fdXJCdCDFHb/u/c6Ss6R3ELiVvdkO
+NqJzNmkfCbe9eQ4obvNQ/mXBTtjalvKPwM+pRt/+G33iduCMZnn6tLvRuiG7jTGlfIxY+euaz99
d2NjWzeRGEAQgkwJs5zna2dQBHEVC27qat0l/ubiMFnoyalfVUi37tZMXSFdTjU4LELicM9DtRK9
PRQ9IDCwsQq9LF/ZWdMWzgWOTxkxiOf/EN2e1xk+BEyq/NomqKnKcT3ktXhslUiMrhbXfXaIwcxf
XFLNCiSCTKzX0XGb0LGoL4gWMScSeaA7BKkaCXcLGsG5hBelhWrirUfbT7S95Ay096ldq9oDgYZJ
jO2pbNYcIVe9A8spa2DYB9uXDHjuzhIP2XD8xRoB5iUgsmWHdJ3uqII8VhEIO3yA1kf2FpFnG/3b
WDjG1YXIYspge/X7dSDRXdFyVJcaPd4mBh3Qa82/zZ/jBAS89hycBg/ki3ia47fcq2y652nkiqNM
7qJ7mMUqXamR5LjiwGDq2WgFA/hnE/y6tjuFtbMuHm6oYqLw9CB/MkR73A5g/vPGF+Hn2Nfyy64D
MZmFoRUcStSEoVgtoMyMh/TLYTkT818r9fv0J328Dvk4QpsMKzppHUjcJiULq3es0W3Sm+TyyQRI
LptAJeEo3nW/CadnjjngEtyU6ZTIN3HEPh09pPh3TEyG2LxO5gVqH74SRybwrAf522ZO1T+qbC2D
Aoo7o9NL12R6x0VrVzhBJ0kG8XkFDp8IHk1DjKI1fv8zmMi5A+H5RVsI96Aq2FuHEDzYgMffLhFC
3ZACEXir0Mn0gO/lorUQS9vOjL5iDbNefv0skih+AzKqXqTLwkK5ny31LwigUwcbMQSKf+nqK2eu
j6eihSCGtJ0g9XhUnWMVl18fdKFOvrcdyArKfc1sXSUZJ6sTbkvVzixR8K14eieM+EYIkd3loNxJ
alK0k8s14mMYhNZ+mw2YlvzZOI8fwkxnGhxS8UhQzeEWf6sh1OnSrpCXQrcrM1x/R5O08hbPsKbp
1gi9rjjXDcNSsFwGGNXgWtcJB2f5WE2GktHc5+6kErXYhc6BxXZe6s9vfbwMPBVwDAyABkVki6aB
Vp+92f7Rms/5IabU5A8CnM0srSS3m0iYFm0NpenZrMqvuER7mTaZQ3LZ0dIVWBbd960OC6EQ4HOt
LRreaK19c/nDYTmL0w2XHY9lvSr0qgHEcqd8M5gdvM7k33oOFa/H8cR+RkqgMep36iBTb/j9gtOP
ZSvnW28EFU635NLVAY983NbWB53e0D8/O/drGIM8aI8aHuYXJDb7Yuxj+QEURaFMmT6QrekNvOjY
mGOP0ShHmMlNHpovtPBGww3VAkQBRwzBhiw4QdA4Speukdn1W558YFkVsh2gl/cX8bdNpK48Qp/B
VX5UJAMEKiPhiRsCB03gC1y9uvWTcJoZcFu/5WCmkE5JZ0mt/OAK2328rhlGAXup89zak8NpGH2V
sl560UyY/vM1zdLoym6kICawcG3tpHbFBIWdzNt8koL/6/yTYNqy6rjub9262X3LgxbUM8uoptkZ
+bkUAIR9y6smb3ZZfd+3HHO7qVUv4f3VTAelrHBfeBOPpODLMTRvUHJMMjTz8S8luMD82sYu9zVh
u/xDVdZuJ/AZDkrI8jetbwEil0f4ZIsqSYsUOp4IDSuncmWTOQFvvXahbSofDfg+iFexJyYvdAMV
sBNRpgiO6xRDCSXL/qKdEi0l0fmCIN6y/FtcU8XBFi5tECPcjCWaDu8ntEpjRa8IzFTJrUzxktsJ
j9k0ydwBaae9PBoY7S6OhgwN17LdGm4UwUYWrfMggGceyEKC23GB3E54oDfcCO3HZy6XPYGNg6Bk
CK8HLJ7G5H8uY8GlkC0s4CDLNNBC82dHHywgJPLANHTct+sR/uQJeWfIcf89D+HUQceoCCQwTbUd
ODAJAbaE0UpDXSm0kbcIZeBFlcTq3q6Q8DrUFauMSZUjCun2tEpS7scQ8YCZvNoW56xQ30Znkx5A
wgPcctXCC3f98ZPvqUGw3zyUIGL8vbTP9kS98sCF1Xmkx5m66P3rEJq2J/AKobqDQQFym2ypp4to
+Yi71UXnkp5HVgBeIIJbhywlHojVYBaNrMWl9De3cMEshb/YWBNr80K8kgeZ/W0ybCMyajcNyMIZ
lWsPm+i9eRuoKHECSVYNDhJ28SJSbZPvtctdXHKXO/WdHXphEjl0D5kcyJPcmNNN8JjLfAeqQUMk
nxyX965CjTCS5mVYjhyRWKiY7p7fv4w125uE9JUl+A1vr3mALAPX0bh8hjuDnjWJSzaAFiDUAOTD
wmVVsVKxPzObabyGM51Qao4Oi7iSTihlQa8UvxqO9X8mSErDx9n9/lkGdFLIBOnqvyzSp+6ZQPsQ
SVvJI0ei8Qp/kCEjLEMb4RPicP9PLD+a7e0Qw7fukVf7bk6FR5EKRMncOxCyKAWUlth1hKZfysrZ
VWO67NHpDalXzixPPwQ+ou3RW+hOc3p+ai4UCkUazW7fF2AgqkZOONJDYnZikczuMN/T5kHk2SeX
E5yDfuOEXHuhdNK6kxd1Uf65f+qOiK/He85hAIH5M/idNQMF7hMdMJPfaHDTn0OIepYCZF9UyrL8
odnNlneX83kDU/nZ4C0bAXhcfMFgu6uS94W/eCP7V/MG/Bq54qT+/nG6OWHzlvB0gYFrlNYFu4RW
i6mViCpAP0APKuMV4WO2k3nea5ZraI3Oa69/DVEDSPf9H/WW54Mcu1gCoKXEPKQFlxU7gU03KitI
hfzrHj0rjki67VdQ7pcfDWJqWmPosfUr5MRYvP4YffKCseYKMj1FCMTHSEwgTVPvdeWDGoMenIni
coy71xk5N+EBE1ozn4JprHvkfDHZQ3yP0RS85dQOX6pN5PogJR2vJc+9/y+HIlcbuWcAPZlFsGpu
ZDMgkXUH+Qu9pGDJnNLDTiEdWkXaio261JVNpxL5pgCD6Org2Srd6iCE4VajfXnUVXlEmwajWjbN
Kgxb4ZsQ3YdqoVlmbQgzekWclLu+OUeeDXI8G/Tia5Soyw3hceO4qG97ypfmanP7bzr9zFDeOmRT
cdjT9LJ1S0sOIdIBRSj8jQmbF3mApIgXcNt7KQE3PXtkKbkb2YXVfj00r5INUdt6ae8ilSua2SOM
B6nLoeDdIU2yonqE9llJGIWsYC0fAkf9WncKQMyHFQuzwMubZFL8ZielnOL9TM/PSJE3HMAeCdT1
WCQ3vVaFcRDT2ps5K9tCHzQhkiL7LxjIIYXOjUCuMJlhlELqS09OsOQllTk/ZregKu3MVWoDmUgW
oKc1fOsRyZcupJQavVQTmVBGWCxRsfWwZ8mcWIZreX/fY2bivCZy1kxghssiZ2x7jMh1ylmcSl6k
h5EwEFDdY4e9XiAGKgYVVuOwGOMw6FN/E7SCyCriNjkf09tMTJe2EFGNutP2EhfyCeSr96YmcKpG
HuB+EEq+a2XrD2cgbQ5B9VblC2PIuPVALngTj8pGd5iDanJj2siDxAnl9DGszHnW/pp994U6Gplk
DcyFY6SsgEVM7OGS3TG0B0wGtlWj5tlCIrh07/hVhvKXG+uBZxIf8xQBp4CvgwmlUz4CZxLQYEKF
94eg/FDutZCMTCi5Wp0crjBoN0XuVAYRNhiymv7kxOAHki6BGC4ywrB+KZ76R0pVNHWnz7mP34AY
AwfCNx1OevYWMrVdzDAi/Jqe+vZKljk7LtZbMYB0d+3rClw/J9xUAvRDxYSVwCXqOGmSKq+f+Ecl
yXppqwBXjveortl/D2y+FVIkm1FiCNaOYs+VlpUBj+GaK3/GvusqWQkV1eu35cUJJhFcnzaBdEOB
9Otle09Oicy8g4QD+ZotoZc2IGGs+8OoeBtxHp4w0VAUIy+haFD5wpLjHPPyMwTv9vQ4VKhlmvjY
6AWALMCqLLcyCFLtg/ZlTQGMAJGM7zpVgQ+1UV8jfS04XEm9alDbbQycIMaVIWvfzXOPvOxhOIlx
qaBZILzRJhe7mLsgeyKut7L+xwzZZ/WocBtziUPqYtXfZREu9tyfBuwtINPVuHMSEmvbMmg5MquV
vnOjSqBe2xxoCxtmLWKVtvbPRrDWqBbB/yMOLRxOPdovuTT3G5j5pDxM7IIAufRtOdP17qOJwR9A
pUQj58snBxA3POK22JQUmiEqnDp+ZPgyGg8/UdFMFlgM8k2sO6ylmKocdxbmlTZ4XJ6SRJ66v/L0
n9/Yn8h4q61Xjx2l15SQX+nvGaqYBxi6TfjKoE4YeQuPItmtcqeRl7UkEVl0ZivB+qlOvV9L4/sp
QKRf57RDWxe08lEsD2DTzGniuCkz1TAnF3UKJAY3v0zqPdYzSSmBQENvYpRdnhpxWyvtcPlXdYCa
uFP1RpfP1oH/ik9tMMrdi7utUwnUA2VGFNoDnw73zJy+0vnTB8t/LWX+tG2/sJOcWsbuH+SKMpe0
Fo14GCTjCWmM6OWhaurpoYw7Gwe9xKb7hxks9Ci5VhrAihSJFrX9hGWKMZ+pIbHTYSdqPYfsI6e9
HwwjBDpMfDnclJM60lpLCl62yGpBvWI/bDIGfsfxYeDiKdnLsck/osM4SkPD3YISJrbv42VIYyoz
WcgB4BA1bdEuu82KhPAk87hYSH+7MAkya5c+XmM6TQnADF9k7zaTQlBPUsvvfi9T9u8Sum42pLrX
kVWn+Fnm6vOvvn8W1k/5O4wj9vbv2AjgfzbWubGa18c8eLjOCFDQMhd2DI9Hm8LF8hGvgiLioDxX
l8gGNLHwV0ZgvDvCJfWx7MezP/6vc6Owdh9qktGnlWilwj/9nlN362V0ChcoOJuuTFSb6egf6TU8
zMuHfDwPY5lFL2IK+G52mMStDzPs0LDNmWxEulyzHyMLeoMs4r0kZ/kNE9BkLCkHd3Vb+Edg1aiw
DZ02sXxY/TrjfosL0NPlJK9TcFGuj1xpIRFYq5mgvz1AeztvpjtkmsyTR3Uag1ErfClmkt+Xci+U
usAlgvDgLqbtH9uT7qK3zWZpkPFOLH1nSfS0nSgXwCl1l8H7ZbleR6Sfk11LcR2/6FkUcYVDn2Nl
+6ZPsrMB8CFQrFJWZCBOK7qnTB+JjlA8UlIpH2K4LRAkbtpsUNNcphfv+fCDlNj3A7BQAIHpmFPW
owtxU/8UKyjxcwy1EVyyP2PuyVhr49teq5gc6aU8fXRS0Goc/+fHQsarCQPMedSSNBywd+rwMdS9
OFQ1iWgR+hdtplJ+Pxm4XXTqLGf4wGrQVIi62p75RaZZUBy2k3UmwfLwG86JviPnv8E/P2/YZkDX
69aJVe6l7XKPWdGlNRttXhAjSAFFGOUzRuNQjw4piSubWBfhAGGh/7aKu9Yq9O24wenDBYWrCSmD
lpWv2L+DiynyUJXgjuQ/rvqrlG9CV8Cn1Q81Yx+S1TOFU2UF7L5ieCbJXx7ha5y2SWMiKMvxxyyf
jg/XHAgygSrIP0knbpE2q6g6whbIMYIPuuGb/W49jlmi5+RbWeVCH5qWyJL62AB3j6MmJnrv6jd+
lTGgNKSVmAsjwhLk+a9mXWIJgTEVx8DDW2ffETd3aKkueK1B3RtXKIqdYcrssEsm/+0c1mK16PIc
w5Zkg9KORYSfpwwJRWfBEeqQ2vgMCFm7UVYTnwX/2BXgeR+9h/ptzjaSbpZtrZWSONrAfER9i6BA
stdwdWlNN2nQC+q3Aa1ZEKeoe67KFgJQq59XHdcpCzkzTH+WSG5I8JyUcMEzD+IJBOyVLaHITIkU
piBDFs0aa8sYgH6e9iZmqD/vb6d9MQ0VO1mGfXw7QMQ3O0ZesNagy4MFqOUinxa5Zsppj4IeXoTp
dTuQ9G9JTB960CnNR+aqWm2/qJkWnSYO20o4X/QMfG+FQW7ALYnvNY+Oe3Amn25uKaS0YAvVig5i
9A+gM+aEYxdrj4YtQ2wmTi4++er0MmOMhP4QK1P/PlAWwnw7wLqHDF3JvBpS6O9xDxGqLu+hs3c4
Jf4p7geJELAe1xGsOZ5vuyNRrwUh57FqiItvzgrmtzl9vSMWpnpmNJirX3lKWN2GzffYjevAe67j
VbYmkfQTPIFgQlolMMXVejTPk3ELeWO36Vy30cw5jhZ+WBC7x0UMlRFSo+3/ZM0W2ND+ISDsjOd2
/QkQeEwxQy9tu9k59tTw+bxK7JH/C5mPqg1rTOTJgU3mlHP5XTXdYoGRNZjtttBCRZeACLZ0Z5X2
+Y8xHF1ptwfhG87LjV39m1AkInU8AxmGkIRXYn8VhR9cYFatzvIEnt322V0yxmqhoqfC8ZgYe+JE
pgOIg5BAjlUcfxy0DNb35XAXWzyKCfOnRRVqbtPZwzRfT4ilX+nrUBZKITJWDZxeQUckhDY3og1o
f6y6hTdvT6x845hcWNHh7KxUze5USPUR72LbKZMoSi7QG4httMlos6PtSo18WvrHXyzZUbfjzCOz
hKBU9ocrkIu4VE642PPgMC0Sln+Dt/9gYe1BUl4HWc4rbrpHE0/AAeZT9khKOphoTghSs4XoQiCI
BcAGONpR0dJV3uXRbddm4gNE3yhBaCzLTS0iSvYSm4XeqBjfPgRsbKuUe4otWgAN4ok5jNKIbXHz
MqfVDO2DLnZq7s37AXpX2+Q5CD6/DGTYOmKWw/mTHlQh/O8sSc1yxD954zn+bvADjJYCw6L1pPEk
/EfJ7AhQLzMxJohttqSLWNifKifAvaG+UGSGfE3nyFE3UYM7ZdgC9PbjujHb1458FRB7PxlxY8iK
perWg3UJZTd3PFmQxbXiXzgIAtPW0bgxXUokGAmyxjXfac0sWiWwLsWwXCpHrSR9+DsOUZa5ua7O
l6aqrklCDQE74oDkWYoX4bpXCSowlecukug63Vpk22E1+KnhlJxPct5u069YCkls92YNjJxhZ5u3
MvPfrNcocstTau07Naao7+YbxsuXRHXiQJ5PzL+BxkeGixpfOWZZgJrszyY4W0IarammcAEkEzzj
1IRzLQAvSeUYXbcrJMiXI91uyqE2oBWwOaEDt2j3Uq72Dv8jYpbvFay9IDbVa21qaCr2ONJVzWuZ
7rOw3eDoSTsOP7Cmf+ZprHPmb29697R2EvQ7Hkgb7TMCLpkES+2ovHc0T0/0Ro/absfM/MExuyX4
Sp1QxwwwxbaN0gGVyZOo46HQIRldmBsZKuiJRrRXM6wwhgdtpgYt4H0r4COzCavPOzOddd4WeTFq
liKKSgPMq7+8LZPEHhCcmv1WK2+Nf2Z20XvPKIfaskdtuSap5fVQ3B4mQT8695rkasCN1TBVSU4G
3trCUNeUTEOBaHryF7kVf9oGFI7/QypiKR+vj4P18CTdEk4R2ucNPFv/btqYeI64S47NXmQzzqPL
XTJfOlhscyQQQ26S3ytpITnjH+W9iJnxCVPPM7SwNujonXhIsNjJmAkfaTkRHzKOcHZw5/iPJbiv
3vYZhA1XahtHFsV/TXsL73LD01K10G76RK99L20B0fDf4+TodyxIJb6zcsip17cya0mEx+RJg51l
epah5X2vWFzsUyAwm9ICO+Q4Im8vePcGHJdlN3qvCb18+IQUqNmQFMQKmuz+p8yo3skkR3YxSqfl
p/5dcYCrgv55sk6sSnOMG+esOzboADBgaBP9GmvW2MD/ieCKtps312o1BHKXogNtVcnPT57TfE8Q
edOhQcBCugy3VDmJ/VxcSfBxjUF+FrlVd3zv+EQ/eQUmoAvTbC1N5/PZ46H0SQ6rPDKHEKE0X8Aq
AjksA0GWmgZMsUPxDt824msTDOjR0dgflMubFss+YkCX5UKfNXjIfgGejEt+yW5yifbmNnBp4Y8A
N7QF3uHIKsENb8QKMbsRW24mBrbfpjTlSOfkKSTCM3syYkdZFMvZ61+4p3bhDN6Cpbh0TMJOZCIM
5qf7l2jv+vMLXdLi3xpE87ug+pW4dqj6VUVb57ZfeS4uMcU4OUObzZVnDUMtzInCtfmuG2aJCQtZ
IeRhzFuYJ5023HOV8qRZK335ft7zV6gbGEAnnv0dW4nZdlTpAe/quHLd9ENolebz5v93/8aMq9y+
xe52tfaozNvvXniNhEKzUsJ11MjFnmZ3A2C/YdoiLOh1QG5Y3y7xB7/o6HX07naqWu5smy3N55Bd
6HuLaM+MBumyMhJ4gDQRAAaqZJ2hJr3O3jNMmE3QvX9sBKwGFwGOEyLcFbUntdATzL/99pwy+Dcx
bWvys69Q7ZwLPh1re/LEBEYmr+EB35RCjVf/gzPhfJlLT697Mx4uGvy1yFdps48v0zSL/Mh5mkli
ucBXEuo/yT5v6+VY8PvmYL2IXyz7+QAD97SFngSMPgf3V2S4MFP2u0yIDNCt+ax30eJceGUbFsTq
ZFT/aNpMzz6ysUb4Rb4a01AIB/Ahi40YjzoUbfCoP3GjLYPmeYAIi+ifV7r7r/Tji2rELxk8LgNz
PkVzEIxq4nhDvjvhuFW2d3if7/jZRLeNEFcNK9hKbaV+l+XJ++OI3XFhoTjKizL8glekAu2vrcRI
Xgv7+tQpmxCk5AqSGk/B1IJFK7Qv4deyVIp0sr4rK3tJT5XQnwNpHMUIGJguNqTUPqwljNmZxV+6
G73b6uZSP5lqz1aT1LWPUxIyhmf/VewlCmKvWOuZGR8ZmifrSK6MJ8WlnM3ut8nk/eIOBjMEf9Ff
ZBXXp9iKdZ4190zEtydoauRkuLLeU7hQwtBAYn4G4g6qzPPmuLsEbMQ7rOH2b1L9wKOa/el2BPBj
xC6X9XSbWjfcNuhAVfan6HhraLSZX6vpVXXhalxwhQMSW3ki2yRsA11scxgTfWX2QcbaKIhypo2f
IQutI2FNvl80tU7Fg9g6/XfAVMbS2LmJbvF7jfSo5e6Ya+rgMWsNcQaXzD6ATRvVedsd7kJt++Aw
63+AD3RBcsDLByaJShL1khc7Rg7cyNmNvoC6ABQqYgXPwiEpX/2SujlzLl+bHwLNsUUiQK7xsybY
3/i1PwQZUzFJZCM4Hwzul+kYqXybuD99hLVmSQglYG9Rxuo71BJV/KPhaE96nMzxVnjJG+fEGgLM
buPgV1R3pIY+ECmOnWI7aLChtV5bi0UGlXbrX+N9z9kwYKz3MNG0RL81jIylz6tvW1XPO8tSOhi0
nun+9bhqsBHsbVzr2mB4J/pl5ZM/lZRrWqrcSYOJdp00yg713SJYIIjPv4wuKx05D/zSkR+0iQCc
pmPmIypYQrTjLGRZFyt2oEYhO/tQl0I/t38T81Bga97Nf40RmXiHwM4SnTiVIfovy9HJB7XigeCI
TZjfj4e0v2avdRuZqnzQiayRpXHVnFO0bnZ75DiX9QHJl1mBYUMrlX9ToxNb7gs7X3MgEHB/o3o4
rVYm4kix8WJ2w/1zxrr9mgUXFYkcfLaSG24WexjYXm0+JmEfXj2yyb2WXxYNaGzjbLYHejXvawK3
0CscPN7VCc9BTfWMM0HyMHz7oGMVAdF/RD1yJ7CUN47FZBOcPCTA0fNM1Z/76YYG06X4nDV20bzl
Rz1ZAnFX8gteTH+z3LOnfgI44okiti+A5XB0ongg0TKESpm2bGYuxn+mMz0huxb6Yxk+9KodtxfB
GGyhT0tK+gVVSZB21E/UQRkK3Tsm8V0Q8Irc34fQth3RyLnz+KtOSY0FN6+FtmJZuPQCQCQL18D0
xvJ9FZZSMFUSeLOpY8rBCzUko8TVTGdNyLIoZqkP3XHEx7PhlOvY6WsuhIM0gzdlR0kbn3tdFKaY
ZmjejKw7/p1QqUmspghW5oUY7tykS1rL6Ugkso0wkgbLDs4WTRD8ZGjC6YaHUixrG7VL/PS5aF3H
EMeHiLLceqFTPF4Ty9g0I+peVNvtC6cMoyRkV0af5BFc26p+NyZPtcKjNLKv3bzTxepLayk1ODBN
AkjRjhc6SzkiksRZOqh54J8hNOyUF/kYL/0C7xVGT+GioDCEfsPLkTG4fYz4HK/ZxShVki60lK/3
IpQFfsnuqUFiPNhuQKS+Rx7OGqBnRjUq1LWWH5aQsPyqsEifNcqSlEq96P0MtX0vV/zI1P0VN7lb
996V2ql2n87atZcITJAB63bZx6vmPwVeXjseBmjXhFzDtH902f8MZeqDHqFIcdX5drBBvVnhveQs
5XD7ZiOhJj3UwhA9dD7ZgExCUxxC+WAaKUDhMlz8+iOJl/FTUKXD3Jz+qYj1fh/urnZy5zUcDORQ
ddUlZ0zd+9W80t4+2oDhnbgFDzlqqvsFVLbwU70w6SqDSUb3mTvOUTmlBGOFnBZElkeoguTnkQHW
IaJspqHQzKI/0qAZPws9+y9TseazQOBooAVOLcFT9LTX94ZqSKT7oKxgdWaAPS1n+a5n+H+aayek
BvfG/bhOZjAVp6K+fLRZR+lD0+XmyeMGkoI+QfXqVGpMxQAozNU1UeaxqTO9LViMZMhqbhlELo/N
S7QN5dfsnbKVO1tMI55T6kjwEps5znMQjo+8j2ufM9dF38mAJt3mtXtTTdBwvw/d7rt6oSOGvJQr
0GgKmTkAg31C3Wp0u+fYh8FG591XP0MlwVddAVb5PMByDC/avkQKEhrXi2aiX6yo4x3guTt5VYjA
ww4n0eUSkeGCpOriCsAaMGdj9aCvp0eMFRJ2o2jJBwf4mmnkn36q1wZcwYzvYajCmIefHo6NllOp
S2QoPasCdoqX9QAvrsGo/8d9sixs8s0Xy5BVexli2jHkvvJZpZS9JnpfX8po0JavG23dBM4Xl+Pz
9R2x8GpR7TDsVdBXwgSSjqAGVFdssQdM83IYrRY1qTiLuoACdZkt0cpKJ0T1M3vp+HDF1+XA3lRE
LI2OwE81y2XQIGZlU4Rno3FcA8TdnZxCWuK38lwFH400v3+upQ/1N3zi7PwJWc7Z7Ggb1f62jTra
aMCTy8bhoJ3IHAoed3rMIILA2xrwxOc4Ku0k+qfw7vfcuXYlWfd8d+6K3KiN3g6vhSz4Je81x0a9
V3HAr3WMVcWMklkaROY8a2FOlihCEugQD8QxZnx3YaH1gyXwGAGuA1bnbq09IMiRcpQ3DRAWV4Ab
g1Y6Gqcc8MlveCWeMD4wQk1vnC8ByUVg3nW0Q6faH4ONvEOCyow3VWNW/SQY//KDBwnXWXSBvw0p
etgOalOcn1aJbqBhbASKk5TBniSAgVKs4TGOKadTu8rwMYJVnFW+6xfkrZ7r/Vtn3Uc7p+Qs4VdQ
jWF26GTJJ8zaAXEs71Wji0kFnKumscbxLEdFgFHgmLR1RaqdyK2gYjpJ31jD0Q6U2aSYLw1zsMQw
L0h8yCTF8EUO3m2E93XMPwm9MO4jL0WOLbZHvAwOBL6fT8Zge3vaiTco3l8QGaZPl4woHf0v+vOi
HQGMyh66fCSjDqb/Jsz/JXfT3CNhNOVxlEqfTpzc+7dYEhYFXDGBxJyvMYShNP1XZW6Ym1tbNOQL
Hfaqss7cbXWGXyhE3eAz1Qt0Z1hzV0VV0/MYIZ673FIgMDvTD/SeddmHQzhhmA5ZQgYa2hJvKQOg
WCDKmljPboUxPxoXZzuLYEt4gkmzp64wUHfUZaYAOIW0G0gCnZYBfUBQZGZJQcuy6AWfo1DPbVMo
MIt0QWxg2XucNZbJ5sXnVhDNj0iDwimZk+z0CdppS9e2juU/nG0BqIWrgKl62RgPLrBk7ZveMvtl
4UQ58MlqgWHojd3bsi38Ef2CPprdGo3FwtdfA/BQBygizI9oMBFFhCYcQL3ZBfqwC7226NWtyjez
Yhks8BF4Q+Ng35BlRoqmQmPreOCerk3IHP5FO9GPMytstqdpCaEnCQB7Pi4uD03gDYiK/ORAV5Hs
HS6lju0mzMPMIJrMQ/hgYztajmAZFggM/BSreU+i7xg9E13J91Mj5sNJQfarZ6dpyIs/5YyqOYqX
kQu66tdtsY0DE8XtPaypyaUfYJt+MBe2+jzDFNETEz6WqH6IxoPIZVCEtvwG7gcxwLERDX03bfhI
NONpxlersUFzFG8HOJdnAGmLMj6XYoi4uKFfV3cal5AVDzJKQ1HbErHe20/VJzgYLi0WzUtxQpw2
lKHhKDGuCWe5utfbGEbboPN/gKnV04DHZJ3e8PIJTvw6RnSngyZes1cWuoV55leoFZngD/4NfoXu
cmJW2qu/dmGJRTEVDkkOErUyoXpC3JY9UABFpuCS8+LCa+KqgP+hdeuuz4Uek9dBREnisA38ir31
oiwALiPDaV2GxpEbj++oWpykPmwC1fqyEG8jyW042eZQRUfqghSEVg6cXFkqCX6kHiWGyjEklcVN
t23blQ4fPBXdUssEfwsrBJCV31xANFPlURyCzshLG9JY3/UKH1oN5eXouDvur3/FHa8W+aKqUZqD
mKQRuv+fJ2FleFwvCcbUsbnXNC0pK5vJjwmK0MxZQWI3mtHECNoO/sZksm6vGLremAU9Tq4mIGPD
4Ee8TV+0/yF0WV5hqUxm2LuBXwfMJjkqQOVsKn3mzwJs440LODTLwnlZVtfUsvBX+wCOYMw10Kf6
e+1CmwmPanaoHFjLyf5rKO7ByaQspY2K+6ouQ7yyWvMpwHrBs+e5hfDSQ6oViUMtixV9X/Rz91AM
8sv0GFe/LkX5qWLMO22ZsiBZ9c868aT+4henV5y4GDl7bP+sfUoqGK/K/CPawv66+4ez/mLA19cD
kGcC1MJ+zCfkVBG1icmbuBMrIuqY0mxe9uUbUip4k+Q9vP56ZgrVFyjhapVxSU5DNyV9PuUL3YnD
ObFxln8kH6moYKmpRU0zb8C4tJ5tyhfbN+OCUoM5FlhgMYoYRNWPSRCp2FB1KQ9JKT8HMlARebyD
Wzhdw4wNBJvqd8YvsC39MsWSltQ/UV0hwQo4L9mn1NzzfOotsc/mWkZHlC6nhqH2MnAbTTVdJOgc
AwhqOfrRucSOxPmHIExuty+DvjZb2sxESZkGxVvt0H77d7SxJpY9uT/72V9UO3Bp0UNDZfdw+NA3
JFn11snBPYyOxYx3+Hu0Yo5HF8QbZe8MZHgD7RcWDgayLoDphuzTa7ob/pG5z88PG8fkcR575Rro
rexDbFhQzUqukfdVB9GbVSBj3mkziiX8LTQ5vJmANqARRHKLWifVZFyn4mMi4bXOiWnSnCejx1Rz
AYT/WnFfDTDeqg/a+sjBfijNOQXIFjU9wCMKz5vQN9FmZcBNxEEihJGEoP9KFIItZMUgQmBcViaa
LhdgxGJQJ6h7r07jmlTb7pWY9KNAbWywdWAZOr869551BkztC5wNFjJcB3IVJdEExmXgwrBvtdkR
OGwbooVxgnVBmuGemsQQj8HVJ6PIdU7ZPfbjkjLoPEYsVkSUw6B/r+X10VhJ06ueeYThb264szL0
L6+Rp/wHE/yqloI8tLA+wlzaqDbVbh59XDMdTXMgBTly/+rSC+Ghhmjshaq5QiQpWlpBoocST3lJ
MTRq5KuiFs4D2350iKCQ4EL78tYuUxzhyy/GiW7NXMwhcdoFO3hKGuWkKAfd3SQ8OrV+paeq6Cvy
qhoxQO0cvCnfQ9agmtr/Np5FL8ZJGgmOI6MoyDBS8se8ewdSIoPZNyHn1rAfQvOUsKGHLFyYY81G
q+xVycnqYYOvk5ZDwAj6hUuyylILDOzRIRhE6MZSIu4KPjYMhbvemJ0cMVwqYadMgfGPiHtfjHCM
wcd0nwkSC9bII22LZP+tYoA1Hi9c8A6Im3UBAIr7MYWTtEHVgVJxK3FVc1eEVlqL3twrSpkjQDCQ
wF0lPvFNa2/jQZAXlTKGq8QMDzHV4B57OUolxkcy8XyO6EeTzv4Gy1mc8ChcBaCjUEi/9Yf3yhIf
2jc3dQ9XU3gSfoFN3wBicQjv8W+1XByJUp2J3QxFqiveYDmhV49aDGXZbXgS4ZmiA559fW0K3xjY
gyRdbY7xAYsO7RKzs5HfPb5qxuU5UMcdf+Or89MYhECCuf3CJCdeR613Cgh3bIWxibGVTPLlU/ZZ
kwdtUCsS8Gth2QYTnQtnV1fFo8M3zjOf0n3l1Eo6A2SBaXLsZi1YQlGZj4cF4jqYQ+ZYC8ENv9+N
gyteY7IL7NlBgEHZvtkNUK3ZUOjcjGXrqPh4s7vO/9eLV5NaXdd2nGVMV9nqpfohr2cnBqjHUbzF
v6pbhaGvDQ46O3BWEdptvtBav/XQW9tjJTjPzvSntaqcRSlOAX/O8eZka9hjsRl58PSlzRWV0jHl
aAp+ZNdEaEdaDGqBHYN8m2e6X0oQbse6wGPsGVWAiItOMSm4YM9qaUAGgZmIxfBC/LxVEC1fxUj2
t5pkewjLWFoI9+ue1qBxZelYHAHUVskBkqwCiuCU8KN3Ycwr0xKOY+UT9ogpeU0QFfZxy15XRr0A
M+i+WloKRwZ//J6VSKV2ZY/kap89YjOiPhVxhkJEw8icMlhur7rQ+K0yIqy8JIbWBMwCLP0KTXp/
yRlsUvn2ytaGcMAhQRJ8Cekeo8yOGIrIm19Pi0lK9jljkUtaqcE3qO0VopZmDx9oV6jKrK2v0/aG
nU25EjbISoSOseYG9DIRRgco2HxFqHBg7PCM0o0EnlYNgIke455NqSNHmubqrd8cotjo7RF7teqA
OWHncMCpQgS/HXDI/VqSPkrt99GQibo6aROFAuOj8W+kKsqIkZX1COapwiwOERz8caY7DqEApuDz
bt8XPvs8j8If48oPCRLVvsFC+4l3Fez/WPlktYtHH78V/tkxDaYB/HRpTvIATNi0ApbGTj5lvygK
hmwluOdRoEHt1C2cQcl/8XBHMvi3TcWZtuQQkk7DpUijMQtnOQZXrX4s82El0KEbpTxzAw5eNHRb
j6O/0+7FftYffqkK1nR7v2aSHISZZ65jJo6fRpI+ALQoUnrjc08Vc1DIHAjuhEAx8IxD5L8NJ1Ye
WdYVAx+BFkwBaJRGX9d2l6AAJv7zqnyXawG0ukuzrNogUHNjArgqG8D7yMz1VEU63BA0Vsj44HKR
0aHC/uBfy8jH0n9FpccOuWPtI5sYNLm+K+EgZeDmqangQTkvM0hHB0Ep+2mLyIgcfttZeaKttnqf
cDCj7UL6ZQtttx65znMk8gYKTrYKIR+4ywVzBey4O09BVzsIaysbZscfXKf9JxJCctdjfNTqoVik
8EgWgL2ID+CL4+Xh/KCJVvjjuWVWeZAMDkYBf5RKy0rcApEn58gMyreh94RgPQofvbxZfRntJzT/
THynwkXdjpGhJYrp8oJwBlgzq3O5GFKF895AQY9Qr0eIO+d32VhK/KidSb9stdp/ju0GJs9GguIj
oyTb/aM2Lm1zmIEmzbyt+JIt6/0r4O8rzFbCMtWxnC5KyT67SgWuNj2aTGexH2ynPHc7PXa0PUYv
Pb3L1yPPD7X99awyUajw4yQzXT83ui4uktfZs8l0zgBrjgRq7+iHKbGAcUdNzOH5SYHH+/stmfUU
HAZLl6mkl7v5VJdpAaKNCemUr1yxtGbeOcZRDbEne+fI5xoZECyMHRw84+wvrcUS2oYTO1uzBDmb
FQyo3qdoe1XXEPgz0iCJO5mVIs4PMEhFolqI6ZMxzhDAP1Iga77dNf+6VcEcFR1iAUprDQUo7wtg
mXrK26sf0ksh5eAN2Rx7SH2vKIc/ELaHbq1MSi14LjWjAXveVBmccr38vMHzqn1iyEF+KTNSTgUc
AXdHnGo71G4gU7LpIAbMWWAguuRj/fsR/0iiMq4x6oj4O9jKky1RdsafF3OQhhTN2xFfec/y+fop
qcD8OMChw8TU1QtZTn9lCH+NMyp5+Cm1C/3DIYdpjaTUtjzuwdPP3a/t+gWBmtNGvpv99rz0i7+S
gaPMsevJ5vCrfRbBXIWgH7EgQd5jMwW/fIP2eAwzSaplYb323DWQwpEXmrs+OQl+gHrJpj7cIyDY
kS2xbv0EOF+IReTuCUIYVmqXdutLw/xAcRtd7+2vU96V2+CBhFAC4JHGMycETKE2hd7qoEck0yOT
JaAniuGnbwzitnnfRdmd331dfUhvmoIvb7Lt1JRb2hAZKN7EZsvzXEhr3kNf1AtG7fK/kKRVVNNI
rgW8MgSzOlOVv7ytSJRh8hW2Jg9DsItZGghHzqE5+s18ElgNbebv8cQSxXSRHuGUmw3l3akIJq2H
HDekpbLV8SFw8+fBdLneEyDbDtJZjRRtkQC4BU3YVbxgk+AZmJEoCNYnzKwf+5qeMMpmyOiWnfzJ
lnjZzgDehIuwMKHR0ZVW0U9ekpNJFvkll4OJr0UEWF570lVowsxepDSh6RzkFrRVAWaH9WjtNFQQ
e3AaMqrwzLptLi/BNxde7MXPyAuwut7olU3U58T6ms960NReEcXbp5Zcg6tNPFynVdlkCFOnHlEi
7PxQ5lG+49T68PKV+NGBqZzD3p3XKsUabBjbD6aD6qNqmTuRYaKww6brwdcBsbUEs3JlAfUq/YF3
yin7GB7YfcbfZ4KVII4aP7BxduQnWB1nOPNbeOv4HBFnBiMdZkNb3Ffk8fB8fzSQkuDqX2ae6VO7
vHovmJJFQoNDCxc0y9lalTSYpBPghQk+9D8hOj4l4Hmab0thTEuwpv2DM9kGCU+U0pb92K8nhrzO
+jZCiAABE1P8Ta+/5Fxzrb0irn4t104cU4aHfRNFTQvj9rsaztjtlMWTCNIwjn7oOWJnjzoMbuC6
noixnO8RPiL9wL78sA3cIzQbm9lAt5B27GLp6FL+UqucRSCWFNsxJm8eyb9Z/SAF2mDavbQHbqq1
CfpTn4XD8YQw7FbA4KFQ9TndEbFuEZUwJd6P9IxxP0wYKSQ3EV+PnGvw2A9P6wcDemx/LtNSMcvH
+4Jue/luAYco4a3RpiUCgP/I4mg9mDvLik9n6XU6dJbbR9mnYQJEVR+uX0Fec5ivniBkTnBCJ058
xpJPEPmgBJNFx539yfrwsKsnBMX4tCkGBlM4bDZWvJjZ7gso+u2S0I4Eku6n1KWC13yLsmtWVqTc
M8kvEZRLzhVSbloL1vYPr1NNEL3bqTlpg0ATe2LKggjHuYcuiqq7pVby9/Foib7A1MXiHvHSsQlT
Kme2la4RAW7PCV5GP/ExSeFPFid8VdkPw0LXt4oHvbDj5BtSpTxS7vMKE0OKcNMVHxcXN5QQmggI
/2sIICfKrlKjGLZRju4C5fZEmgoyd5JysZ7KK4qUG5Y3OW+6KPTOhUsHjQcPRb9PttdJW6HFhvVD
cEr90Ef6O9N/Es/TVMUN/qZBuXdSOA0TYTnAti0LVFREftMGL+B43uqJ103A+zXXlFfFdgMr7yYB
StUS0EXhecD2UZQIv78mkfoRC3AVsr75cPmYQ3D4fN/jrGTppgZCSNZjEVv6ygF9Xf8ZOMTl7ctW
gqnTzpbHX1Z6aNWVV2gbO0qWNutlD7Szv/XqqHnpJ1WtUHyZj8D/xa/zVPj8YswmogogkmYp6NMb
Pic2vBZQ8ym/WQFEONZASOmYpXy/V98VjXVkoC37np7ji+bZssvsyAwm5pVqM86rTCUqb+87RODN
U+BIjRWv0CY/ZjtAmTlQh4NpkdhLfMgtfWfUB44VHcZzwRLnERKelTm9GacC7xSY6SzGrYGwgDYB
pxWhY44QC761xiApbOJC6YfQKT3OwL7w3/y5qJygE4DL/9xIWM0tbK5BtQ376cSMW8JJQboLLxEO
jSkE9cAkKFBgI/L1fiajtAhlF+C3JN1KRPRa4nqQlgq/GAqqSzThK2iN5INvFl0LuOr64f6jBkuD
rc2cD/hoJl9ZUA7NC+k2NE5HbnxSLE6VZ2gRIRaSX2Ub7ffLoOJEWWA/0VIRsJ0f++vUPTLdI6F7
m+loh5XOrK0rRCGBBDxG1ZiKdEG4aG/FSy8Y8xkFzRZ1+iLifij4dEOkVcGUpTjLkko94VSrNvp2
NDqTrcGdxj3U9+82onNUfwHmDo9ewC/paOmx2Nh1tr42lGHBs6fzYeLMyt/mWGChD7cKl3fHg74a
ct3CVZtcFbxHGSYiPPaOMwowZO9dpWhw0KOTbhxrY8+ibPOLAo0Z4h+uhJBVbYFh+N0q2x5mtIWE
zafhdUbu12RfFlViRxVCT1PFc2j0CS9yPMgvtM1GysCm31eOAd5TZ9rr7vzEm1vo11fgmEB18/dD
WV+ao7MjDIxFyr40jUzQ/gjSgv3r8Z+Bjs5IEyFOZceSC+pjenI1qrYIK0Re9abuzbABzB6FFYk+
gGdkNetPWE4CDwgjwnF2zJGpMVrBKVyZQsJNwfuvhQ/XV15hBvDO3sjX0yOnDnawqbWRFbh0A9+f
Xzkwa600AQ1llhUJaN53zmNDCY+Z0NYryLQnpR9lvz5NbEjeeeW4S+J+vjf3oz036wmkVHTV5pS1
/Ssw4Fx1sNsaBmL5wPNh3wGx/U16Kdc2V4W/1p45ja5l8KfVOTzKfL+SMJSxGYqpHmUzCm9UNTNo
prz9V2b2KTKl/ArlN1KgXqhpR/zVrQPkUZUQHFF7OqzNyqJZqAOAU2xUcCpt61ZWl0eAehUQpvK+
Dxl2ZCOaxhYId2YH3EaB/nWNLw0ouwUU76RZrpiW0c60YUfwB2jjNTQYK5TT0RE2Hcn1B5tzrmUy
Z3ucoNrGioYDqLHCSF94pyfvmNo2ztKdHdfIVbX7BQQWuDa4va4ATz7b06M91Y1VdxZrI0jp1cnc
tfm37DqrIBFJQqzvLHSYsOoFl+60ShLMpJ+48L2+ZVNiEoR5pbw3ELBjXmA1VuNsglKAafgTvUSF
i/YRPxV9GQurdWHyp6HnxhAQ4SxPdckrbpZd87Uei+zcw+ILczCl41VyNYAlttQABv/HIDb10pgy
UWwan4qwNyvMB/CkCAO8g6bd+TS4hTs7xyT71yzEx+52MBrzqhBtXJ4imp8O4Jh93CvUVtjqPrxE
A5ke/ily8mRxYs+k7q4G0oQ7syE5LxJ526QrxyGsMSlvltf/zp+v5gpx13/sdWnTgKVGqMqLHu5q
xsY6A7X/5P3DDpdUjO7ZSUuS6sVIViLZfeCdDVBthcW+V+cRuT/MPM2jVDbYXZ8A4KOpXSUzkJgD
8FSg+bgAaeTb4F2EjPRrZjqY1cBqn+GHdmovX2zDI0smgWQSseT7IgRMTEafDdb7sXLWNKojK0ja
eroAVWxsM4MeCfX3ZlRbksxGgsyiLjVjKLzurRgP6lYWo38B1kRvdj8aD+D6cvLzevVxfF4Ozn+j
YF6MMMgFRMZVnQI2XR3ntDOPQ0CFhH2w+J6rj1qR3RoB3mKTdsPCLGBL0hR1RDD22JPjCYSgaZ93
9XJUl4+lDerfiWyp5nj+drYXNxWBgqbqidLRA17nh/IIpojMghMZHp152xoJBZ28X9RA/o8GOfHp
F5nlrlD8xmMuk+SFT0mkfdw87NnBMVvWt8ztdjRhytuiCQdbheVh4Dnbo7XPP9+YqfwMKfawN6L5
3neHiVMTC5q/ephxwf+8MZRfAYHl8vQkAHtlUjsaFD3DWHi/TjXxodejRObDumAF/RcIku/NdXeD
Wv1z+BvX/lzgO2xQkieXL+0qthai5yV4UfKcEGBoBNfmkKQOOrqf5SvzqtDMW2mfCCoaf5m9mGnm
/4u9Rjo3yVgDazpJ7CMXdb1+SQuTpxAaseEu1+sLMWqI46xqNi6H2nmEJ7Am5KbC/IlrFotDdQHz
fzKCopivXcxWRQsp+yFPBmxTBwABb8U4goJmTAEMOe40Jsk1Lcz1w4ono5Gahp+lxtxIACeqdSCg
sJOHUaXcdfN9wVAaCHd5WKgpw5fQuZ9oJsMiGAX2YY/0c3ws6O8Yk8KCwLsFO0rX5Ip8PgAtQNDO
KI7xzPY4CpQSwH/idhJVPlEBnGz1EtFbUYvhC2rvXV96Ocuc7O78Yp3w3QdEnsOPcqyPo/OLft7G
VxygYmqIk97KxWPSddNu56FJvXEyV1M6H7n3dXjYhl0acvfVid0649VBbIuqi5NgSpHmEdeJCNzF
169c50XMQe1A6FAz5jJgeoSjeiBDD6HsWDRrBl/oG6b8H2CgKxiz2nXuew9fMnCAC2aPlpYN9SGk
hWNwFOF3AQbJdPqgkKbqVkw8O75XYey20vBfjKviu+jHoqeZFeNFC9ks3GbczJ9J68ju58wy6Ygt
OyVGJyac6QpdjzNtWTYMq5K7wT7HicrzPnTDmWrwHDOLdPHYCr+8vCERkAryMgIdUSlYpifGgxoM
cZ5sV6W6PlQWUsK34jktcFgNa3HPNUq3S86bjFX0d0VViGzb959peTkxOhICe2K1/CrLjdgmD2NJ
Oj1dJyd69+Kh01Exu2E5Q0IqMFYAKsKbBhHKc2+R9rRl+/6nkgLS5GZL67XeLj0QBZxiYHcIoN/p
NDP7LRfnt/DToNLd0wF0J7TdxJrYl90Vnch0zPi1vopPND0oL76Nl5Gp8KdUNyukznfoKyBh8u5p
x0Uv/xXj64Q3TEXFVmbtsvkHc+KRIEbJzZbo4adeD49i+S37Ykywc3U5vEtOh449cQqTihLanSmW
TtKWjtzaQ/b3mFu7fcgtVz33++gH805zZi+RyLc7VWa1nYDnwikav6+QtcQwGTfN6kO+n7p5TmwY
jIm9awwOcuaDEbWYmcrtEfgIyiZwoyiFKXlNNopypnaLS6h+6j5e96i2y8H+7e+hNBPbq42uthwE
/YlI0GDUKo0t1UpnZ47jZUKS/AatOTD/oBcJBshnQYhAUGW1OQPctZCxlNKD6gOpHLGU3a0BQnA1
j7Y12et/nd46AqJn3fn+UkE0KWxeZM6dTzZqOV4T35d+MV5b7elfHWhiHxsAT+d5iRq1Vx4Gcxu/
Pp4hszwAclIGPxg/JDF47WR0U7bXf4VIEHoXKcqz5SqENzIO0HRCzyNjD5slh5fcU6XvqdQL5S3D
Z0rRJB5xBeg1rAsBqhgSfTBs42kCtx4ZyIF3Bp7NA08pa17ikD53S/0ZVphydB8WeY4qITdkYTMl
cyh6IeR4rlsUnfcU3HgLje7BNALUNCiueias7gWh9iYlqGVxeOhyhf5ntmy9SDZ2GoRFCLnUO7WL
1RWogwbLzEcfahRWRaHnBRs4cB4yM3XAOFocfx0n/xAtWb6q+Q8ATXs1uy4XoW0aLB1E7VbCqwJ3
D3q8HtepjMkSye/3TDxrYslcdVGg0xC67hRJ6G5npmgyXKmMzp4Hf4Qvw+KcbtvomcuxXm06XeyZ
Ae0LxZTKVHaCBKIkTlKL4ZsNuc3/ZZL28k0SIbGzHZyywvejmLGzAhorHwHk/fExlTqe0ndC98/S
aDLYQ2HqmZCm9dGt3fIz57hsPkH6G7bRfP95fQAazaOr9hJ0T6x8Y8ae0ShffL9W46/zLER6+pjv
GJpkAx+ZqdFK3VrEsnIxCk0jvH94ioCHcRD0BtU5mx31pXgFyliCfrN0FYcZgGgU04lD0lFVEiHL
qUUM8WOKYOLe33JoeDghXW+iuxOzJPb3Mlm4+ElY4X88mzxcJHHdxPoQJwWVAyzFB1KF1Ofa/R4D
a1Wvsc7GY5eDEe2jfFvl7KDaRvAh30yRrSscQHe8bHAwgKYgld9yioSLujanon1REXMdWeEBI4O4
sNLWv1deiEJW+b+qhHpNqmHdC+grfUK/QQF7cSqG7bGmTvEDH0/6TkZz0UsRPloSTA/7fMj7NwPt
4IcNbPeZC0dTZnuSQ8m/jd8EOz5ViPrZp1fA85ATuWsW4t+riKqRbqiWwI9GZSTYiWt+IFMARJ12
Zm7uUvOLaFrwvv35VgmaEuf+ZiRHDkhH4/GLcDT+NuOwZaY6XQExTDcLowELl5tE6WnG5rJ6d2Fp
UhX3/iEW5WYaBwQzN7zYlem2+MumbOND9eCnc61n0v/q+vz/1HHhreFGVS2vONhdy9Ib0ErfAOj3
PSaO+ywe336oMyP+Qusanqji+YX1RFb61PVm5fWA14KoIVVsVVHM3oPKWHsfz4YPK/ECtulNpRYl
2S/WlcLTsN/E5uC1CWzxoEtWcnsvtTEF1npW5R9yZySh5p9pLCWuyPi7gHc+9Twm3e+ZXqEBjbPl
NL26gixMVKqGwNx0B4ilsMCojLrR0BuwFYu+flERO0idtfoNDBlx8lWk8XNnKtjh+3IKRfs6QoKK
J8x5eqG95mHMl8z5pVB7j4kzzlpgng6vs00jB1W92Mh3PCmlVsUSgotjnR4OSuqOcPlJjdbUe6IG
uQaS8GXbwLQvfA6n+99cBanOkokbSUTTuya5PV415cNALFXbrIaRT14aHk510ulcGibOvhinLUae
1RbEe4n7tFWfdGzAgk1c/2mcND40ihOks6Jg8R8alkTNIJyHp+zh10/jgwqExVY+3x27qKNpktLq
N2S0ivBkGApNfIWAny3WKNC5CsZ/qliPrdnCwmIvZbK+AvCW6Y37tDQfMrdHbf3atYX2h79InUSL
mU+8QztG81Qkg5akP4aDslRr6oh2xqym3yGvycdCmJ3X6AU1yUyzt8dBq2H4W9MzeWeIdVWToMUO
cnIbw5vX7Ap1cO6LCkQmnEnG1sIFmFIBBAk+p9jQ93a5C6iOJqdXyrTdpwkkp2uXGH8fOFGrlRqp
9G53rQEbsBKx9UF7SXjzspKkzNa3luJFwMpYMAtm/3GgnkbeYXkqrHiVjkoVaMxUye2pujFZC21x
vbWN/Qk17zczfPaig7cFgjNhgHRVN+iPd/9ftjSEhUC2WnUsoLjMuYKysKtxGkRdvi0Qfduom+R1
V0nTCtUoTHDgKAv8nMo9JMV+lIZjVyAPGx6xmBU5PCkT2CDlB0//G3woG58BAobSjTCPNt+HJFHD
iXOelav2PNKJShQ7s7omKgggnOvxE0KtdQEDWO3oTvuY47qfDykc2gBlZz7T9kGNIzWO2S+iOAvZ
hFOq3LIuWKPSmHdip3ieicD34wIxJraM0SwfBA0Mvp1ep6zM16RhSxNhOVDTQpN3OQjupKc52YCO
FEwQPuYXJGRAqenY8Um0r3AMPo/Hxg0BmX8O0055rIkyA3PKXw7GQcu6qZ3GLawEd4FiQBB6A7lW
/y5nUvqRVxaeixhqtaRWulPbWNZAhG8MZ7JE1Qx6CR5gVdMnO+oBZL++bexg6Jh5ELSV1XagR6SD
K4/GA93hIZyjkExsbO0fUIWpHHq9gleYBZiKxEwzpT3eMNz9m6X+zhRXg45dXqGyt/MbURoByuP3
gyRMGCEjykwOk7tKKPnXZSNPBjU3C80jqHB2RReQifYmjg8kX3QQcrlcSFngyLRXtwmj+rqROlgU
359wN18l16D6+78RKeKMo9S9exXaVX8ogYT+e59R7g6Fu/ltvle0UTm5M1lT4TvNIWHmCWI2ORe3
ucJbAMa8nsdtHr20Jb/wMIJzIfAieS6a9Jo/nAepOe7j01wN1NBzqcsMDw5hVsGuYHrbIxLFeBiQ
F6lqAi72CeksDuA7x9zwpDK+koROosFl148nL63YxfoHh9kmCSSQc/qLNqb9LsMSZuiz9IM0I2Dz
KsIUVcCMTI48Kn2unhKteg98ExJGYxn5BYa9rMCJMqnWvLWkZrZOE2TBkTy3XdUbAnPESEGRzbfY
XrmlMCN2teWaz5nzlTuI4cbI7uGxKdmfNJlblzgAolviAv21fFpamdt3epaGR1UBo4+ZFCFdqOyh
glyvxFK73fWrMYO3RPA44/do3hibidpvdunnFJ9NzJr9v6JBiv723eXo7F0Q0BCFzdfQ06CCilHu
WZvPSRAuxfQLO8CpL5EGbFxibLEmYDge7JUGAyL47gSLKI1VtEdpTAgrDguPUGlNu6qc+okcE19Q
qoL+6/jobyjQVQ60ihAr+M8pCnYJepu7rwEoshwfUtN3FtBdCuQ8ln70YdRvNRruGrAUtLavtW8q
UcsXAtzjRXFzWIqtQSBwrcTgxi5/AcmYB+tMSukDjV3Qj8ptTEduSb96jZ0+tsh0kse6PbTzUlVu
SbatQO49oYkGYAX4QwSCmsIg+4dNAEO30VXuNhMuavREENoHf9UxAwUvSAyRgiEi5nqDK4LPUwmv
5JyLrMRJ8dY21eQDUCn8g+ASM5tzsK4fp260qX0EEy96wGZgn7lbFg+zb6OWzaVtTnRrXwIREqc8
uVEwu7NBBlEselnir+U30pJAU6N3WF3EfPBoM7z97AIo8AS4sn9WGswOUaQAUjSz29zkiBzlKEP6
WQs+G/mROQdmmfDL+ylcI5SOBALFgsXkyw7MfBwvI6vPHlLp7SfofeXzK1FfuWIhAQdjsoDANZJC
GoL39qNHhdSDEHg01UKLf6sh+Ju08p1r3rhP0Vaf7xY6ZymXSlD8Ge8dv55iNvj4D5Y/Sa3lQb3k
LH0NFEN5bzpy5Ct+SviL0Un8d0ktLPVmFT/sc0YueelOJQ+I7V43NHFFVNjg7Rk6cVrzeiIaAqQ4
dFxpfRsaRMJ9inm9UufxAjhJwRnz5rWvpXNur4ZGob9EYjaf+CXXGcqnW6OtlIkCmuziBm3kBqtS
epdHvRd77bwnGGvbeNFN3S8NzWIYIKDp2XBiqpuNora1gQNiuOjWkxMYKDeQB4CiSVVnEVhzceM6
1zV/gzVVoCfXzscR2PH1FuazBSo1+edfnbvVdKwsrXXmgEA1Tqj7XHswE/LEl4Cta1T+DPZ4tHEy
EyhdNnngiXZjsNcI3jJO3hjWnaJL7/qQx0fW+yfTvAa5wclleH2HVtyykeDnSrqJ5ciJPew8B8Ka
VSdKfyJgC0K+PxUWoFT82vB6w0/V4fK7WqI51bOBSWzrfJcPQpwW4wsXnRuTJxXb/e5lSBXqIDR4
f8j5Bxio3TASi5LKIkdKCC3v24b/zp8spBtBy122or6SWAxxD889rlAOaqEWC43M4nuyWSz+NRXA
X6iT2UZEBhSYG2R3MgVaFJKiUhoK5M8pd+3F3J+kIYQ9ZyLGuhw6G/TXW001z9fZ50YFXk1KnHS3
3TwzE6nN/iZ0xubrBVHOUBOdxwbLLBwC09nnmHefmj4mvusJnQoUkOnpn+DkzkROw/6WV2XuMqC+
oJ1zWvB3ZHpWzvla6qFI4/QDXBkQx+Rpbuoarlb3D98cIuSKMW2OB5dMRTG8RSMnzy22rbh7bNoG
MQGlskDwlQtvu0Od0ojl9p4bulqZeYYR2Rmd63Q3TYqAcdbtEGjfjOwQ1qVgYteLCo0cII2NEoX0
4arC57JbEnnOmgfiFVU2H7lS2ichO427sR/Vm5VBKNeZMT+ctQxlsomwSZ/lDFoDuZZtrTZ7SRya
CGa/m+x1R//Zgx/GFTTq9SiV3ywvMdmMej4N7UHMkcUavYdoCjGsYSajJ3uH3pcKQ0tJBiihhXBJ
+k5byaoXN8Xoo+krNgWTyQ/eaQu4J9tK26mXzn/1A3gWWMvN0qtk7/hu7lWzKAWA9iLGZvoJpwXR
x/qXn3jaX83vox2HOeE2tZYxNElykZB14hVDT46JRqAD/c9B/Nj5+xj/YqYno3rDx2ReqBrm9+E2
tpD2NthZcIAdna/XPkAGZ3i4NdX+z46E0JamJ2ls9UtN3sPNw0VwpSPIXnkkWIlmUDAkWqJoElad
F90J45cwKIyTq2ZHjOaCT/FXO9Nv4RB2yHDL4iSiuKE63sRZIaSRWRUwCIqjZrEcrGgNu/4PK9wb
3fkWmoGQqwTnVMihhglo+B5f0CshN4u3WL63CRfOCWtp1y1kdAcvX5+pX56Aqw23Ud/1+fCNCnTu
ItN/qdHbuS+7BkqDSwUpC9u24V5wS0fppr3jXi6kzDuN/OzEHtzsQ0nlTBoDMyEaZe9WVH5qnPgi
p2CQ+Dm9RxuI3UQ/AVpqm3/VhMscFERlMj5wYY/QaN6L7AApiKJuxNmHGpsUH6MkgK3QKyOrgiTZ
lK30K2Zr4U0894S8FLaT2cl1v7KrkvaVTCms6n0G8jw+bHxOe+yTf6rKj1qpyhyYQcVSCsPaha0x
djQjPf2aWdsUBe8+r7tvykvhKhVj0fY1XKLzy/rKi2N4WGXs9p57TZ1KyrzRCXvb5a3cxbaSQ+it
2gjWr6v9E/Wzz4PtLCH6kecZF8qHgF5tpyA05laDQ0pJ0GB6+ssstMFSK9QNsMf68vNUXweMnh0H
LsUOXomNTx+YH/OxF/zfg0590pzE1dyE0CZ7LlAVLSeuprEzNiD7/EOMBJ+WOOW6adWTjufIw+Iq
LuOoYqHgCkEFzbg5Ptae/+/wd49n4o4dducCHXoGbuZGRrChoP4IRldKFxwgcM+/aCfmv/+SYUBK
NEDxqms2BufyW1z1rOHIzzZz1uJl3pUxk0zQyPmmlLxFmUmFAIyJbPR2p+AKEkVtPji0dLqBo8Gt
Fzcsc/vCqCzhH0i0tTeHD0yUf5tpyGZRDE2E7MOGJp5wmVTbMeR2p2XaotFPplo9JJm5FvLbb0+y
69d24kFgx2ILEdzjGkpqMiBYtUZlR9xpiwu4/ij2QrHV7HUkoxhvdyi73cRKIDlQGy7x+L9f7Rlb
tk7IrhTXdm/WImpWvXs+wwVR1sfbp9pJT8gebakLcCsqu5OCYUK180IeLPSlTUcsIxvUAd/74T1L
9oh4NW3qRr2NUA59QDkcT+x6erp6FUJsV/Gt1uugBmHBCTDWoem8/t53eXMVUR1gyVs9Ps7Ce/Wm
9FKltvRnbzNgSisddweiKVK2v8Zez5ZV+Y7T8GmeGifkkWD8PN7CxtIqGIx35pogpDJL8QL+R/Aw
iP97ZqSZfqBTHy25f3pFfrLncR+ZUb0POeZyaQR0Dxc9/B15xKopluH4iteh/JyIxIN+NEXEo/zo
NXQx5+dlqOxmglksowKDubmVGcTjFRzUmUKcCLhXKWmonuojOSPF5Cd7CnjJGCq1X+Ln21fZPawa
MOpC5eNDtw1j72RJ/y8CY7eJpKj0O6QFFawBGRn6Qm+pXLSgOqWZJkXTx9d3K8kPK2RJg1dhYpDg
mKok1vv0um2xBK0j7ve+dVKr2OQ29JYzgl7BwvC3PYKTJMmfyVmJmNtaIYuxBV/uea6hjj4mFYNl
3B/tYS/GDM8pHCtENodeoMdM1F1parqaNyOhhannDqJV4MBTxWXfqHAKYA8nQECji5erx5swNk0C
iAXAs6UWQz08C2DaTOpQ3vYnUMVe1/V8qljBS+dejLlohH20uRX3LtsJPjYe5ud8PczqZ8i6AHan
rvZlGN/m1hQflNqhvqXowO4Tar6AYtG0gDsv61mNIlIrFVDf1Z4LtiSOC2QyuDjlbzciiSeYQIrt
Ksw9VmY+MooQI7qAWH0cZge2rre5u/D5aX2PBnJvn8DX7OqUg8iJlHtUZQTJDpyPzwZVHaGiAWrN
h1C3KPUs2fO1pQHmJqUKWmVtNzIZy95ld/SDEvbRajmR0oNVeCwbypJcqgOlVJZUuEJVs6J10lAd
j96Q6r/HC8gc6cw91+njkTc33dtNL5Xa/zn75yRT+W6102ySVjxFnCVUM9Wo2idWTGq1kwVXInWa
LRYaFZScPpPdI7A2Sc2bEC1SPWVfzS/qGcANMyPDnCoPMKXy7jvP1yM29g+0hJF26l7YIPZ5FTeq
SWKktFG5svRJjRvKk+Jsss+8l9NbHhlYza42dyYETnZOzPggvWcaiuECsb1ovn6kXXafK4Fa9aN1
Uy/sQjjnW9ZzuS5hURiDaX0rKcLj5AeQD5ZGTBd0Al+k7rziIkUS2UAiC2bABzfjbjfeD+gO31bV
ITGB2/o09VQZQbekacSmRyv21P+VgG7JlDeXAWSU1qh+eyqVQSwK5eZixued6SRXhIC/jUcDswUU
sp0YsWKCQSmy5qSpLNb77lDXx9MvoBL/F34eO+s5IRtCr75YQEClzel5POIePpSBTagDMJSiwFoT
CR+wBb3ESEzZeLnxrrFXhdKFw2NudrIpHMqcPQXl1vH0SwIwKMn7wBnIlZKQlytzBJu83+5nERus
0nE5PVtrjREQmynIX7gV/Qst8WhXjn/1dfHdhQAcP9mKwtBDpQUFvnoi/yPwXtEZztdtSLCZEFNY
gM+W194aQP9a2ahAq9fGywQs0nqKGI3Z9CJ8GodOZhDrsP5PVjYjDXx8kqaq9usU2N1kJOjsxi45
hVO5x3luXOJev35bbH9MKf3e9tAAav/GE72X1iSnd/kenZCeYEt03rf626YsZTzPL8n52l8Y2NME
yLfr3mv61cJxig6e9IafBS79BLNsn6mFyXnU3WaajqZE27FFGf9sxGUgHIHyTjKyf2/DAjMShDbr
JEfnu/9S1Inq6nZqhybWZOAQVjyVoLOCohCJIto2woIIP6hOeCQmc6lUXTeWBw9SRfOZLrpcqA4o
VEBtBfenmySUNpQeznHLW71KEWtz87vtFh0Yo8W5WwgFMI+4uj3SRsTg72MgiRmHhyfN0IGIeXga
yO2TBneyRKlzCEEbPW7l4he1AI+oQVkBncj/Dem9WIWTxGvgX46m9BD1m+xuT9H24fnuc4WJgIEF
CmOj84kbm+tYu1Q2L/fGqR7cAE7EC0oXthpclZoqza15mBx170vaLRU8eZTm2ahVGa8PXIwUGXXX
FfMLml+0UYew89Ht9UDz7fxqm9z+r7cDuUOAwnrJrka7Px/nUWRy/w4VYKU9puCC0E6TS+Mjsopj
GI0vo3LXeyMO6X0bGs43xyiYEmbQjSjB3EQYYUKg0q2G/O8OBQJJlHt3xDOkgP0KD8t5VLrmZzFO
ohRJuA9rslPJ0O/ExF5W+WCVlK03VUGjEFyAf7gkxr5e0ci8EpT5MCUpCzUjS08UUw4/NFz0C+5F
/HrwXn7iHLT7OtZ7XyKNg68jONYIXDHTgssfLj2Lyeh6GaEb770byTkYLXg0PmiBdo9dEQo3wHBB
rs7PMuypF5O+RIvKDn/RC2Aoykp4LJwKrO5e/1Z+QikCmkpCsv7qETD7yV0nzqK6csnW1Aew78Sw
hM+dj/GXlctDJB332b6iqDX0jOSzteL2DUD9pVd/LBwigqi5DK4Wk4aJAysbZL/uMDK2RDn+8h9M
zF6E2jiNmCkNdNic60FXku+rg/VWGm/A8yBsAuLJcRMknwAcx+VKXfBlXQJdkacQCbkl1unXAC3O
gA2hsnPXg0b3iMS9uZV+1pDiVX0HeHga9WBO9JgoXkcM8IOLseBviulq5fJ99Ka6w2uGvE5nbCIS
rpRNq26vvl6RA/DorpG5cM6PnqbqYU2HUf397v5hWGCXT241sMDWCsx0adVy2ZhAsPMsFOXj/81B
w09JkwUs4yUFN9i+3ZzS1hHzESwojwXuLrRtg59lek7yR2Z9epAq+OyHr43roN0YyxGWqbefh8s1
USe8cu/0EIxwnVfAXs1HcoA62WG4lWaVE/fmW6mcbNLvORX1o3lNRERNka6VI5Ik2xzVgbGuTMT7
NcDkQQOTYpL5Ihf/qEMQzXTHLtTc+kL0S9/2GgDlsBOzWKH5VG2oPKP15R8PGs/Zi3DrjIIZ0/4D
5fvyRbzS/VOkeg7wvnklL20lkcVGYU6uut4YIMHT7XGNXxN852qFxf/jsSgKtvKcDhiQho/uo9GP
630+qhvYOgedfKN+cJ6dH1jM6E+OJmWsJmiJPRaTLZ8cu4bHMRrKXk0FSx0M8G7jz5yF/Z8UlTtm
viq8/BRuZtpmjHo837mA61/CIZ7S9730QEcHvkOvHzAEtKzZHyNjSv2L6k+kw6dtjZGjZZYaviS7
XvToGoAP0+LOdJxoslVKZ4TPttm7+PTGxi4Cc/DSl7ydliS0cVhv90wmndKYs4h8zpGGMi2sUMvG
BhMNtg1LIvug6HqesHr8BBq8eNDn6aLwaX/+E3xQA56o5zGFQf/8Ee85ZgrGAvt/4VDO3E0dX0Ym
9Gi3XI1/Clyo0BOVxYLX1fwZ21cvVrteECbsriBdngGdpDDxcT7+KyOLDZCjYbTn8tdLLjBeNgSO
HqbC4S+amn++a7vMgpQkLeuCMqimJl6dMO+6akXb7rgV7OQwBo+rhhK5T7NVNriPsPmBBQBj4X8p
TcFaGClmh5BZDt+gIitNskO4qwWog6a+kk/i4i80mCh8rkDMVlNmBv7sX8Yo2OH51hmjHjnb5w8N
81EBYINW6iNcLZ2jnqJLSFUvnr2FBG+JaIzRYekRMKgt1GPoUcC50CnXqpFrqITzLJ4UgPliZ0bN
fbLV++aUleJUryXqmu7Uhp4xSSjDyVNhJuQajxwvPi3lsN0tKDoSm+hWYZpAW6qf37iUYji9cGHB
Td+i4OsTJU1ZVlpHx7T9LCtyLTyUF89IlkVJrVfULJ1PwrF/N7L50ZYpvsoGYXG6Cbs/HerXzTv4
Ht5A2MBSbF6qKB2Ky+rsVHw9lJBl5AKH3sXjxqdFviYHIHQPI3E1uIDipjZf4fjFmZA5388sc3T0
E1IgaWb0B2+bBTomXjePKXcn5GnUWDklm8a8F9ZTEh5itbwbAnJSdho6pyo4tTRFtf/+jSPyG2iY
WIi29tM9fluPi9xXnc7LVsvAKjtPOD8Js4CzdrortE171RURuSvftS11V/3wNetsBLJGcGqBTfqG
euvv1FFmC6CQ3/LG5qm0iBAGIlUS2V5WiSZyBF8Skgtnk+s6BE9bqbIJdCK3bK6ZEp1DgzfXboo8
v5V4q4a2eHPTyZhmtVrhbFeX4Y6FIIHYcisGHf/h0RkmA4is6na7Ua+CXbZjhHE/GQjzzkwSweWz
Q7mHPPcki7AvIv3dzDlUYWghk0qgbFoXj12tBDOCSkdFheNeYzTQmLfWCBUEu/AEkUF4HIP9aavI
Y3dsBRsboPJG01KvfXACIImAXcfeXgPjeoJJWbQCHKpqi29jddsIbzuPxdaEb1oSquwo/6AqifwM
LBreI5KL8F7dJgHAK8jrBvYC66XuY2u5rK8/kc9XoBaRtvKUxJz4y96boF0CKi187B3jlizLutts
I8MQaOxEtspEmr1PSwdcqr0u7wu8qU/70qP4s/ANL9q8+MPRF0IqxZElITh0uG6U0ue5rjkvKRAc
PMJ5Kqmr5ipicWvSZhliybtkYF9lby++Cs7ebRpyJGlzRI9nIzelD2Ov6mURwetx67mKR1AyiocK
4Z/X1uVyWMQY+jNGHchYWxjxsPxHQXl+PW1JKGX9K3MpfgVH697YjhiB8+/W7VfHmORNf983JI/y
cOESVcVf3wpKHH1su0MR5vUEa4OP9tUcpXb8WGJESj0rnsZ3t57Q5kJOvzOKTvQ1LW9QwK9cE01j
ZgatBPWxRfXMV2ctWFWNw6UH4el+nb6nJOep+q6OaAthskmxBWwEWRmcsNtYlaoJURvi6X1bCWiQ
36gY9y1QobM50MU73v7D88AhJ2A1ptsoPj4JbCaOZ+hvKjM8SXpTebs+8a3hdExhrh/rZfMbJ7Jo
DzZEPtOQrhe71+QelQ622suIuP0N0U1t8I576WWe6j7wGsnav23ETHxCR/9/9Ssea/6bIGqxWlhB
ZIcOpEWnEsBwY01CdZspuJKU5NeR89304gO+Zbc/Bb9kQP9fieXeIh7x2eXQrKj0g6Bsatg3YBaQ
PUT7v/Ris/Iy+soaFmaMgcPENc88KsHp+OGXwdviJCwFzMy5QzPZKM1ygFKG2ndwOIATvCmaNoro
wVb8GVIG6hM68O7mUa46V7k0k/Lj4EzFOqeTx6IRcuhdeq+YxrxhC5r6CwHsnJWA36Z03rSE2TyC
gUkdN/TB+pQ1lGdgY6NC4JB9FHaTrxWJBrpLrMFlVE7h8DggYLykH9VWbmxDGu1+pSi3mTMDqknh
5PuiLpv7aQQWyvoV87Vz3XPACkTTyX1sS6cRz2jWhEPfOgAVRUKqQa0d56uZy88zhbbcF2wd6zRT
EDtspO9zC5ksb42htZnhMouCfUqSRNcI62RzeLEv74zshkfUYlYHjhHblhhRO/9gDrky2Jz9Bio9
Uti8pqIYR5YYJueKPEzE2awhramIgk+cxhpjCIwusEFLj0LBsH+ayGCG/UDFN3VS5N7QmI12t6Fl
Umj89PEK4kfmbdMqHgt6iR+0HSlQMgf0/iWR6HXwbwmdVRGDgqIPaYf65O8EcqNkvUA2sNad5Nn0
SgNt+88VNqfLb8Iuf+9c9mdd4ibYJMaONtjOPLWgaV8GlFJzyC8xMWh6m3ZGf9E5i7NN/nIaPhm9
EE7CojL3naQuVP8cBc9dv0UsJVClU77HYJmm6MdGh/Hng8B2dkS53y7gTEKSAmOWyoJiaQujE1W2
vC9b+kY851JuSN0DE9eH5nCfZQh+zolRQlCC623NkvoeUT8OlONy1PqK4mjmax0BUDNIq9aR1WG5
Eq+RUWz03Mtx2PQNGt53UKNv+VHiH8na2bDajnxklQ5jmus65qnzRDBoyLxJUPMc/QiMXOZmSMrd
oF1Uek7+KK7j2RB67Z7/A7FYt4mLRt3TUQFoJGr/hCF9+iRv0O20fkBcRL/h2+5XW/F9w0sSpuyH
mc5mscpGp+Dok6zjQPjXGJh1KslN1LoLuFttR11iZk6e6FtQadIe58FE8CdvbV/BkPGULTkGwZYk
5SKQ+/P0YQ6979i45syfC/W/WqU3YbEMKOb7erJm0TsKAIXqNK0hbjeppq5lxotcLcbRPenKvvDn
eve1tZXMEL+tIWCRYtjeU6MTl0ankEN+/kYhszxTXUIEiW1ecHDjDD/q/aTQ7eeQPi2l3z/p9fFT
VdNUxnQHgai7EQQKJ9rISkv0LZctjKzM1GhD6N6dUCKoBYqQWBJ9Tt9+RKIgZsmPBaV46Pfopdl0
obXdtiYNrDu9bn2xQtozGfVLk0QnsZ4DRFnV3wjQemzg2EFPZ16QMU9Orz1Tr7TfUHEk6HzM43A6
VfWGMaH+6sP/v1Ngk5KXww1XBzYG5UBd+t5+oqUGbrq4RaOjfk6iWUqD/L0Rro13k6612Z0yTb7n
ESgBvEbBZz6ilbFcFeyZgZVsqqjWgZpd/CTNzVzPNzQSqnn1HNPCwfCA9JtaQ7kGaFI0yebFC+yx
eHLA0cAfnIh69u5asZt5OAeHJMnlngzsLXvZq1jCVayN1srREc6b7uFdtaQ2tI4fOELd35K9MNrA
KwnOA+ZIJArdSPTFuLXaaaP2Q8smN55dXKnHhVs0Hn9tg3CCXHc7tHxVAu2PWHxGvLbOMOzQTwW9
VhGTP72vPSpuegEsqGQlpPqQnh4IbkB36jNQRhGZ4HnrzVNEkDnjoRvb2n75n+8oWxsQ6qqZVsie
KceLjxFznzugpwnrUe9QvWEkMx6iy9TeuSzaVdkq/xzBCYxq916xT9N8QG4dChalE+8ZgiTA0e62
XJ+X2wxgNpMbPPxrnsUoB/Fep9ZPehuuJO9L2/acYJPha1Qh35t461D1VqjpTwWkQWSPGhdsT7Bm
3eiMFNZtrLuqZIJ8gNlE/ZVD6Pbb2fsuFf6rVsRyDx4jk3LLrIxlkzX0s00wc8s7sTGjRmLnjvtZ
WvSL7jY7PB6mjbhxTTG6PzYaKQhMxO2a96NtuMOXUSMJSkXsDQGy8dIMFk45wNHReis49/25+HCb
f/NelqLehfCiu4SHZ3tk91KRyZtuNOCYfb2gKc/2JRzUzf2nDCIEisg0AgG5zmgrd4z5KCWKLkm8
iEE6tHuVxpL0nt0bhYgqv5j+qK2aglYw7G/TdEMOXXGDZo+HIKJZ0zcahASWQ59KA5TjMmUKV/qB
ewTkkqEU22zeLftA8MlKZVQhur+jM8lk3ELJX9gleCe5Bc2c5R5fl24WOPrKEnMTv/w0uaqprlR/
NZd4zNCzY+R3qovw7HuwKH3xkWIHkDBaV1F6ji29yF+s1wKdGIhvq/EQtBsr3nCjS8Tmf9H70ZfG
TA8mlePz83GdA+vlMuvMFcjjVEZWJsdd/ILpl6eXZkBqZ5L8Dy81bwYcd80OsYevFb/mgB/+2zf6
zIL3P0PoK+TWtmL4micl8fEM4UJdbUzawWAiWAE/gVzZpcwmLP8PJS0/X7oDYAKxZiw7adPtsSkR
Prfw8y6TU2aQahf5x9ajwHDRhmdM6BMFd+vj2Uz0wjXa+EJwCvi4LLihLCprQZOdnqTTLTJ6+lR+
CV6cs+9OF7KfEcX4pYX/VtDGaB7YyXZNUMJj/cZLjJMaTYNMCdSqzxMMD407LLUWL99jdxBKEuMR
HHCphiVJ6vTwYQqQNyOnWDOi3194r04IBg+wpzN8UhyPUw6JhBn+n4kkJkAt4owUFIDsYDFmIU2u
3+vFHvFlVaoGbC5/3lubEqI8ll2fI3O7tbNoxEYa1g3m5F7244ABNxg90hwSaZ350Q4N46UZPX2z
m2P16Y464mIMIDrzEcxBPMfTWvAGvFNC+Szkk0R5cY7ToZxN6XwuLnuacMIS2qUBZx/3nG9h9mB4
h6Axzx+VhTduP+Gzs3zydJQx6h/jxglE7/cqszrn/DVYP4X0ZnYOUQoHc/klivYOsRFUy9s/gUfw
oLMokjmh4t0rJwp561gvbAs5CPwJZy36k25c8BXFaN3GFuSp1qNz+uhXXuAUqDPMxgsqyX4zHRmo
hwEpDw+s9nNvUnG6JpeXVGraVEXMSfLeE1h6k/UWa40c7vvjbjd1Lynjo0MVX4WfNr8ss84kAE1i
O1Sz5R/Q6HNraRUO2J3oP7oCU1o5lcT1ZC0f7iYU7oYDvNcMWDZeCnjKk7sajy9V/3W8/pwv4IUf
JcXPZ3hvVSRctR+r7iOX275LmhB8D31bctmFkTTwuHJGN85XoGulO4fchyX18DOIKorzm4LMC+c1
rt33OrCC+iaefvRZ4a9mEUpLsEEX2H2gctxRj8ALLOZhJtH2gKNxYnKVZ2iSXAZR57Qfv+L1xaS7
hnD+1DWJQmUfbREJHOiaK2Bh9r6R3/r1nLolBTGVfSpptCpLrU3unXXBfSCsyN5kyd0zJhGftdr1
RV1kASJRVWDPZlkU8+UmAeP3RjG6BDk6HApn0T9kAry59B5r/70U9jfNSdAaPxowJkOk5D6IxMM/
ZnGB92BaSgeavIFdpdRaGx8SikFqXSE7jiWe/huXSrnLycJW6r4RCN/+HjvKkp/zlsJm5447iZBh
V3jpNZCvn2ZOjFO+sxqJ1hKY9xKcToT9SifPgvAeWW+mgxesmtetiTLG75H97rkn27cRK6Kvd1vf
2idvRYkj2UHe3r1nIOxkZ6/Gjcpb6T+1AQIJ6N37bqx73yeUxkdjiO52/aGtBPwYF8LoCA3tcPj+
bAlL39nYlegWNTwFduC/VY+ZsSaN1y/9L1b/67FSop8bTDhwGppnjIvZKntRJSCzRpJ3QT8G8E80
MwJAt+ki6yQzy4CKQcHRlNs6AIvCfDf0a+iqCxkEJA+qVNiASLsVpw9sX6FhmaVDy0Qaqvyez7S8
cmKin2RE5uJNuqGJaVoOXYNUTWpZqWDfMP69aeqwsj3C0ZKEMyFyvXJsJjcL++F+yC/ACuYoWHnD
uD/+F5eU6ZYp/5Njwi5EffG17j5YkYPod7pG4kvl/MRvq2E/Lj3nvMz1xwl4GQ31iSaQatxxNXjZ
q5Xh478fsB6k0gJm3pzDR+B1+wN3vCITLMrIjSJZeZbACNd1bcHJNWjrzzMLYg3Dq+hi7xPNLcA7
5b60Xwlt2OLFADcYSdHpl//FWFbDSq/gHPPEl2jeMWM1moJ+1g7qCh1vK37XCBTlHGXhZtArujTz
1JCUk+qJiJgiF001apv5hvMwFjhBTgkpCdQJpeKF7hzQ5eC1xJH1v8PEQd0jKidCJL9VoQpc42OR
k09bOrQ8sir528Hetzts0N63OgZa8PDoBOTiQQSbRpvDxTBCKIndPFnG8XVLWUNuF+Z05NO+BYRR
9dU2IHVTVC5m2bpveQdYjUIZAkyU739jRDZBqcyXDdARM0dtv1X/S5YD2jLlfnV2S6W+xx+h20q0
bD6aYRusgP6SIZlazZbFTk/PpUH3BLrSc1KyuxqEJe5gb5YqwewCBra78zVIQd8mmwdDiWp4MuBP
+9WMiQ3RafijGC/WSCvIPtZXhi/tCMyxbYadZ9pOIU02ZjVj3naO9MlVBw1K+7g3muxuyDWjBvEq
4NXTYXcveQcKa+nPXOcB56F7wDf8yh1dIPTXEMWV6UN3oWQW5Ky34/1N1NWNND1YXANwGye+DhVE
bmFiJtKWq5+svpPXWRj1ISK3hGNR/oXoPTJOHiDMkqCcEbzKN2RrlZ6ADvzxyuL63kDFdNOQQGwD
eOg50/pNKajyVvW+Jib9coGlIXjtILPe9VsM/mjvNkL0OqkigTHEZIAyzZZMIXCEqd7LAMtT0Ai0
rfMlhIubCxEINxDxmwBPW7MJ+2QT5ovsqsGMz4ouCAfQG2HhfmuqJC5/6oh3vrDk72+VCNu/0FlF
n1udHrTCOEwBng7kJAz76XrNP5ycycDQMesThj/EPvCttq8kI9XPRP60M55p7bz2PsaT5gb6bSWL
z7xEP9QgTbgzAy8Nh6YV0ffqvrVrKMOYzHhIA4zyAj+qMHHyf4Ssh4EBWu2RsBUbXXEesOXCMr+q
SQcknjOBI68uV7hkvxLej/7Om1CHeayChW2rp8U+zaDOlxPg3AKAu7mj6FQ4hPaYB/4pBictpd7Y
AEEQqKiQ8tfIg7OT/Oc75N8+fa/4cH+4Zc70gxXSgwBBBRZTdhBhOHyL55P3fka1S0BsNcRIEfej
kYvyOKOzSI78tcNDBImlg2JpCJfzLDchyuHXvzh/9SiNPBkMXbWdrSzDZtHH3mSi+n3vtbtCLHo4
8hs2Ze+1wcd/hzmpG1dVvB4cfz4cbNg1FgryHpkc10xHqanIa2sIDaD7+qBDbqFwQvas4KGL/TKA
/i7kQb/omCD0hSUXvhz2I1bVyOPdC8ceW/8FiYKug9Bgqej2TXn3wcQAAm95wbSqMGiFvDiMGicG
4HG3upW/RY+ftuKTX9hchYOOU4b9UvAhs2HNv/h2jATDI4a5DTD84+P41ionqcIZPBWODxfDKR3n
JxHvYMo3kwfWobcF1iKkkxJbUfzyNJLYNE7g4LdNrk/CQ/g0t21QpTWPT2UaZGlz+J/ij9ciCbZJ
jKN6Y1KOSAta53N83ot/+P9eBwz5sqA5b5SGvS+78Q3pb6Ga30EoCWzy4367UXRyZe5IldkVWVOZ
PhYO4iW1oOQdndzyqBSh7AV2O90erW/aEqWA194FEprzffTUN5oKow+zjjaPXNAGSDuX+jJ44JQ7
oH9lah7lY79o+NUoP3QOI9HiEo9fEeowgeD3lS2mlMKRGrUJ/W5VIL7xfSBEK36Fe6aL3AelWOnd
4hwO/Tti2nqRGHJqrn9zJo5eSwNkLk8vLvnzYh0Ui75fscLqr4hNpG/7xh7KxHz+86/1A6NJZYUk
pr2etNxBofgvzuH0KxdLU0R7etzFmj9rVq1QcUI/sElLRecj1e/Rjs1zBNFLKaHXF6em+xTpBqlx
g9VisPjW+Sq6OSRQq8aJjk+fkCT1mwMbwWRN3BV0xN8+n7ZKtx9Pjg4xwpqNCSObFk65vOFe9DEu
npQVnK3ddiFK+eUOn5zhc+Tkh9jp2EIF5C7263yUM8iytT662x4dpXYfA8kMimWkB07trj9L/AvD
XV0eEnas09Z/R0mGd5G+CdZEaM/f87UvVzlF+ZXqrp1X04fyGDrMaAFDQ6FePKRsuRrlRLUNPWaO
aAgLdwkz4Z5L87fUFGvoK4YpE7nK5FDn9ZAvsxEMqP7SfdpBgyO569hxE04eBB2g9peDdERdD5mr
p/S9lvt/H4TDq+HQxCfug5WdXlOc8OIB/APwfYOv9d1THF5kcc6pg/4iRAwvep5+XF3V7XgHTm65
+bBPEuhRnatGJ7aw7HefguhOUWUn+q1iO8oL4Sidy3NgETHvXLM0HEe+H/cBTyl3m4dczF3dc5qp
tauiNgIhIVZTIALMp82a5Yu7leK/yyhUvssz11veT+PWaro8vKW4NUHLHHGpYie1GKsP/Sap5b6k
iSRg+FXs4fuYKfFNLdARUPv1pwo1FPhD0jcwVdCBqSXKDV8hDgIxfkxmnkIO/Wtv4fufk97C1f7l
doqPX9rgqxjpNORZtqCsxkUVF7+qbi1Tfz/BOWLumlOfi7jljAEnLf8j/Lps/PweaEZyXVSAs8On
PvUhFsJiTwAq4JCytYQJpn+KLjLd6ZZMWUzWdn71px4SJsuq+TEGhOshiqJzio0D2k0OA6D4BRik
p38YIuE5WWpmc1PqCFxDYiU6JxKQy6v0VFPUAXRpFGeMijJKF8LT7TyIj1qHo+O2WKCYLyjX6QxZ
SjCRNHQIl4UB1jJ+LxXGp6KjZMWER16Q/agq1Y+kEjPlEi/zeDJMh0YQbmH/EXB8rchnPMeFHH/A
0lVBzLelLqncMeC17snzXPnzaILzB/z26l5ibty17cJnsjLQZKKvggVs4YLXZITsYs2cT2ezLeHG
LAOHEBD/cziY2vsFA5CzQSw9sDF/qaKEDC8XM1mUpL3SjbseJ3UqI87MT2vZPJpXwUrv4Pa2+AYR
sOGUDdjS6fGlS1Y5Pik8ilM1k6NkQJ63Q4DiM17Jxbth/I9JLgJEfOQU2XmCDKT3V7qdmR3nqJVi
Y8lF91c2EwUsBE3rL++2OzYGxlmHng5t1Mu21uQFaSq/n+ShkWuQ81CpNY5QfI0R81sM3ezbsmBs
8LhHCt5pRBu00lSEFDYYu4VykHV0z73sDfGyespMNc1RhC6B1mxoYtsWNaWHcQju099MBGBiL0LB
F0K80FDQUlSERKkpj21fduqJHEO4SivThQyjc3ehgk0Yyv+T6xl+Wr5rKgOADkHiAmBz5v5Hl70j
T3Rru/QsBzYMybrAA5R7czfgELk9V7BEpoXs0qpAE8TgVVHQibG3tto3hQryadgFRvUKw1e9bkh8
E4mTGGvC8BGC6nXV5u7rqQzFAZlcSknXg+958hgFwL1dYxzJ44/MbVNKscy5UqwN4Yz4F8N8K6mb
phYelvt3sSFOyd8A8Np3fLHfUeuJGNrBKjrHTKxDWTOOO20jsHHz0qsTDBd3zwdctob738NXbweo
kreVAApPyS6LlxuSPTbo9kCTlOgdext96fFi01+Ug53uQnJi7BAAThKwFbfO7OsBm4MD4EhkrPdt
dwpGYZmjDkrW66p38/wHBykSzoKEOktuoG9xnIMEAXLnVwp8TsumxZaUwRJnp9XxDssTfj1USdxd
fPj0bCfFMI3B1OeBc5ADFiogli4xVbkuOPU8aXDi7zYvJJBtDA0qPRx5uiUBt+jMjjoex4ilPFCF
hLhCC9qGm/SaA89uvQdBBd5sdCknC0FMdogQYPg/MI2HfGjaPNA/GqQFVRZ8kvlHVBEdf69VYOCj
8b3FzPYc/f1aFxZ7KkGB6frFJ3WOAThZqjfME5Tt2A/xyTWuR1qX3wCLKxEToBkVqpBjFmgcchzc
J0Zuch6xVdT8mubt/Hx34Z1TDG7l8KarW09NAh8wxuwIkO48zZG4fHM35phC1vhrWCYUWGf4+0Gs
FqCJED6L4p2WF9d8MEudvqrqJsr2925NB/kcyczkgf7R0Oj3O80ha5q0MaTU5g/sg5XuX5kaSH2L
oEZqbrUpep+utd+1SVpog1xigXWV6xhzVpufEVFOtIXrA7h8m+fwQ2siLEceYOXGt92tYeNZZqGZ
F1CEUvTqPAEXV0zO9cPaHlFoTMdCvMd8fCrThQF+mySiYV6io7NI6LyxZSQa5Y0LeqRR2zfz/D4j
GNgzNOTluBLqtzlfxizmsF3GOYZxeeRcP3ToNzQK+cRmYoBO8eSrSvMF+gQmlS7o49woKgIsAyMi
9SfwcVi/SmAfk3+T+TGoakgmTROyhmKb3XsMO109c1F8G5vqGzzLDsZ8UctTt1rGh4oWxIlsksnb
pF/9FryYadmGJs1d6bq81CuoZAl/vwP6k4M/UXPfM3s18Y+sw9m1vS7JtUTC2FHWuASkRdmmfjPq
mvI48x5mBtDKE306cjfzFO99Y5f8xMdvmBF1scvE62No7lD2rGQTKwWgp8mhUfViNQ19BXVJGeYn
+id4Y4RTuzPqXUvYlZMADkJie9pCqtNoGKEwi/FoCc8HEu6Ew2TJ7+XFQ6/KG09ANDradmqrkXwr
FYmxP7E3hmz6ALfOuYErEM2xy/JUzodLbZwKURm/WoPH0b3tScvef+KXVHKrE8Nk1Db0CyrMyZqT
Zeb1calFivaERGyqfzCZHqcXWbaADLvr4ZrVbZ4MyhOvTitabYjR7x4Om6ytZXpxWL+9DjNguKPy
k59i/Yc1pLSfDNFLX9254ZnPkIvSdPCpkuH2YXAjZb1/7XN76n12QQtlytcn65LCtNQrl95V593f
6KQcR5EEDJFDqrXKYOwlg7XrxaQbfIXYGrKRsy9QhtcKs4S1w47HDkb/obbRkuFHSPgi317dZVs/
jv39IcT89CxR/LmFaCrhoyKbRwzXCjmwz1QnvgicXdSO6vE8fK1Va/Tdtf3vNpmiREUyinQajjAC
W5QfgGLU00d5eG1K/NoAuBugPVV3ktYm27nIBNENE/+/HahYO9qLNc4PD8B9+ze20NAWUmxdiiQ+
8unXt+MNMw52JsZ3Mm1Izq22hFrBUlbBJxxUxHdHHiKCwZBlH+82CLRUptZFj5pknJvkgV4Smc5U
uVMO0di4fnsA7iJNw9lNd5sgq5ajmrSeLBHJkUmUabq2zB2FSf8psuLRrdO7YURmzQjzbS7z7Rzr
3vnJj4xvjRI4bCpNlU5yScGsa3CDZpqGB0CTb/JelNv8959taMYPQ3MuswRuxwvJBImzT08PEiu9
nLmMazyz+N3t9AfXCGgj02vMXqIHCngYZ46USMPXRek7lRXzH09azzxk6jffWps+/jb0HmX5DtRQ
00B2YzjL2wk+lzRaNNKJH8SXTsIc6iunjsINSjG3/afP4FSDKBkzko3SFfuzW7Is1wXDELnAryEB
EFuMCyBpjEp1hopbzZFF2mizPiyhLiRXccjbAgKJ/sC5m9SxQMobaHsg6NU5lsRPCytCTsIXdtnz
VcVQ4xYCX9CwOxkK94zHsBtwnww/m03A+P7CMOXc1L2WPNpboRazxu5bp6UpxF20IqFLixiqRsE2
hYBG8ssNXzQhruLE3aCQpn5oaML6h7NxB13+xQiAvazeVgGyVm/HMvebEAnA56tmZw/s7MSnEj/G
asA1NNWTW4nWsWKPrlcvsHNIDcREu0iser2N6rMpCSvW7Sxp44a+h4nIcre6sr25hjKEoGWUt3NO
NJrjpxRfd5jDVlhIgEWyhtd78M8j+ZTKgiqLPFOsVcil1iggQ0aB4sQ2htEDOmHdcNr/F6FM8J5i
5k8Mt9BGs10nh/CQEse8Mv6n86bFo4K2JsPRo6u9/nCTSFD21Gv6ppSMmHskZwprKusn4T7zEbWk
AJ8mxDwcTvy8S7CNEfwsBNoIEPQAn0Fg+UbbIedPs0HxWM/y6iOObdBAry72Omlpa16vWUhcYkTn
njcYCSXej/vY0KdeGNcFPjaiuoYeBBNQPgWQn1x3/oPyvTe/3XQTeCxafn+aVQ8eAa1F4NroaO5s
NCbnlpsO8cmOYe+qsSh3QxudvtzW5fS+z7znSrbCvNhEqZOr9Pa2GlqKLn3jMJtMCqoucZD8vaq1
tu1wgPwspwNLjlD3aToDQt5HmyNH0yPv1wkmpzg8TayDESzAbVwgMhb3FvFXC2bSrybZ4inwU6PJ
q4tOYKmfSK7oa4ofxT1CHH/GC1gKbIy6mFaqnLnn9Ms3Sv2qC/ZUSlETg1HFgB9MWs3oh6lRjap7
BKTs5nivAl9Mrs+/soiEggBeaHi2zUb3Bidke22WUnlFwtXFEy+78nt2qQcCE1GyYjCgLxU9MQhf
8eHriaXt5xx48aOLOMRiUm7b6BPRA3/P+gm9crU2pLogX3m0OSKgPdaUK0BeITLKBiKEWV6eXil1
dR44VyKWdhCvgV82Sr6aJFa/4X/oLU6U6gfdDURmNt9zOSSQfP3+F4T2tq8Ag/1WBiDMJ01IfTIi
1Jw0fl9rFiNLYeu5KN6tQFFPrbpbjUXe2eba1UZHujDMtVwzTP5zci+n7rdAtoLEn/nh6/OJStTB
gvQ7u0EMPVoN4SzlEUr9B2AH0FvFEv/VPwWK3Q5P/YKcYsaleDsjs0E72osDbTZPn/eZGi7QlTYP
1GNYAww3gcVlVR0e+Ec6GSYpATBouaqNUHvELvmJddZQu56ZbDKV55FKJsG7YMUytrkctS3n5jR2
OL+Uxv/j6MusZREB2AVCuHoJkzC/k4zK8xJ1JTQFZulknOTBYiuU4CR++k15er0EZPivvQ/nJNBr
OouStBsMJCzv81aShKCUZnoO9puCLFEcrlkIXyPJ7l4m3OQdQ6TCoq9/PTWFRkwtFK7potSqgr/G
jICy2vx7G9G8yMRhdl4cAy/8/H/RrlXkF9dtF/p/mHn4i+nrEoR6RKutWsLo2fqxK9KacxdIUDjC
PA00V4+gRzCDrCL939vvK0h/6tRQq5t9H1x0ntsTWeJODpmgIl8lN6ekFHGHBJPKY5Vq6/dRrGPx
91IjuAU4gq372VT7WhaEpqQkrDxfmXiPAp+WZQMxULxcL1dg45fxRwTqmfd0u0OWL0cwYrcMg6Z0
bRFYnUDJVLVncVWwLl1RZCXQUvfXtvYhhNqdTKYGP1oBd5rUA9VcjbYhKbnS+Zlom3ChwweiOxMH
n7Avzet01rPfCnsqRo7SpYR5zkTyerBOPY1PXYXGPNFM9i+P5yQBbHnDVPXUG8Dq/9iQblpQMIMP
LRBudoULAYyOEziOi7FODiUgKxwqz8LWR9JsWxQI62XThDBD34HERbeTbeeLhd67XFpAJzXPJ1ox
GutadVQlV9B8pqEErWWsiszuageH1sW6g70eHWW9xok4l4/oiEtcyHazIUqYotau4Y1V/QcAchGX
aYD35W0/zs54ub/2DCO11DyoChRsuqCNO37wq/2+kdhaaP+HqAEvUFEkJ1RHLagG3mdFkOrxEu+C
LP0SBoxoau7l7SChdBriPv9A8amOBhynyACuSAWNFrFd04+toJHFZ39fEM/nIlTvdfXJ0sEWAoY2
5lEH9ChCzOcH7PWI8049SWpO0mKqk/Xnt2Rd4W9SBM71OMoVbu1OHVkrlrPakUFYe5HzNb8IkvUX
79ClYHO42nuWEou4Mx2bJlvesMOATublvPDVqWaJB+Ye6rfq1yrW32+33+VKSi1b3rm8u8kFTkOx
GF776LlBniWV4KpJzDhqODno/AJ6VD2SP0omDmNzTqYUEOEM7tHCiZvtIJWsWmhL7922MdZRodXP
AhsYidEP1PEIz7emgsb8Ef2C1gD6z86irg4olrSwCEv+/+PdoPdEQtCQWvLGdtdtjOZWEiJ2YbG5
I7kBe8DEn57o1iPe9uRMXVsnzqF7Vh5X84Y0zQqMWEjiu1d1qsupHCqwQ6Gz6SJsZ5SxWidw8Vip
hqUHzk6AiyXJk36KiWPxu8M5b5RqnYnGZWNK6Ydpcsc1OcDp5AkovPEnKczYxM3SwYhIuksY991F
iKoXm5F1kUA5lN2sR2bD5Vdhy7nwT8d0jzZ2cQCYVjhqK8VpbHntVFCjslq8f7A0jCDr8WewtfzJ
ErrNj+Qjvu0PoBwT3eTM5MmbKQEJkeW8s2QN6XVggS0fclMs6XI/pXSlXTZ/bHzLmuadNnAzcjr7
LtM+bolPcXbRZBXtwVy5VNPvuW/4QJvu9ypwD73SeOnC5A8CbZkK09BiU5/htR0ea+VJFjLM/4B5
2YEBKvXyk80R5/IBWczCFD7aH9zIixnx7ybvOJZHFeStwCYWOZMNPVpMGe2Z2AWrcW58TkOttjrY
oO/anM6XHHm8DO893ensn+EZGYCybpeKTYKhJQc/IHLpHSAgDTUU0kEABAlocoUhZrz/WueL9B46
uGVEqOe1rly1jVPSaqIAuO67Aen03CtwPP0B4/W6gbdntMCIo6hjngmy0Cu7m3eRZUKD8rpMET29
KSz+6uxdt2NSbTe2IMVxt0W0sHbJ//o1m1rsuny39AxjcqBg9b+ILfd8s3QGMryqIs0oq9ZZKC2O
mRzFgAcXwgQs/IaCEJaoogvPwxNYp327af/PNj3ukRocKOhDxe89bKF2SPK4ZiQuB5tLBstcBd6a
fMMkiSiRmFu81kdjJX3OI+cY9ymsBxMjHE7tCbvpxfOmfeITMSiu2q76QK8p/mEwGCkHWRtYoT9/
Eh1rI+kgwr/HF2N52sRjf9yM+VfQNGKS+9zEiCMUtix0gma4tjKx6iYtzt9TVRTT6iCB08gvwYfw
9CMqdS32hy5x0vCAea0acQSTYF24XILRfy6q1L0UUKW3qmNLHcp+728E7HEJKJ6G5w/UHO5MbfUG
3Is9HpaxOzCej4J3PswLzMK8Ds+GCT2s0ziht+lVdU745RMyZLb82WRmuYsj47r6eBNXE2jCqsqT
ERC4yDHq3J7VLKHKp9iqakqsfCp3pypUo1hJGcbSnYhBXrwRaDNoxRIbH/O+DXbC+9o5AtSZ2Dr7
yxiLCqgOtYwd3qkm5ae8aRpzJsEpcuH2ICFwSqB4OmY/lq6QFt9/0W/1zwmR46ibD4lmeokXN3df
L+TvGa9CGInokgiFkvH9ziNl8Aeo1TBZBG4Z+CCYHYU0cxOh5MK4+xtOSGH/cIrBjtHv8XCHUTog
SMWifnwen7N7ykCNUSjIhGENMhD2rkCktwFALJVElptevnmXtiZqeXV1jXGU370T9EI9mhpeSVFb
yN+MiT35sYaKgnMknk8WVFfMsMrKZ+vchT6QlG2XXPTpADfVJpbqhQc8YsuKo+u8LQ+NaR4CZyjl
2hqwe/nzgl5UfGul07GCNBwu7ZMT03mf1WUTlUOVZgV3mGIgEJA1NNPeWt/1Pv0VleQKg4U0efag
JQgu6CfCTojccQm9KirgM0bU3F4eY3VNPT80i4QjcOc32w4EKAbkCNjXV9f2DSePWta1yHzGYIYc
yeoHewbi5C1oLiW+eM6PRvt9yel0iTnQoCj0cCGe8ARzgS5w5g9ZkBPEBeY5BWQjzbgkBUxe87Yw
+Y1URXiJ1IKcMO5tFI0T+b7Izl899WGVw2iatq0hIUd9ZYR928Bnv6OfY9lbHuzN6msmZiKP4eTY
3eWTFGEB19qQKRXLJ2Gl1oxmIgHnFj6/ySlf/DH1ZxHx32OWHZo/Zg5VosjRAmqe2vfDp5ugS0x3
5FesyKH3S81Biy5CQ2WQXJtssVkpaa0tuYiIW7Dfce9Ihng0taDSQWwWvuHL9Vdb2QmZT8yduyAe
UUuaxmxxxcAzxw0/7OPcu7qL6g/Lu6HI00lO56ssG85zIyfOpAdzvzVLoLLlZZYdffaCAu3DDN2U
2a/9EtZWRunXgLelo2O87MCBTjDPJykNRZguySYEeDidU1F/E2JfJ8lrZjSpR/w80glNuePfAe0m
4ydMCBna6R3/+OTIdog8VlZXMfCwkghzOfFVV3DVRjqvAa9lzQlYKdamNzldlfe6+9A4qN62RRBM
IdEV/uuvL79dFQb0XSQ5vErbSp5t50xgLDbyCMQqDQ6H/hUGeXVw3uY1c8NIijcoEIA0hNyIYJoH
9K6vk6IZJp+oebdVxsuxgN0javS/e7PlsN1b1n7bWWjANy67PNFmA9G8Bu3h+qpFxOg6kT2VJQgn
4Q7bY0+hSzudDgC50apk+7nXD8XIj0ZhBVf+BOdksSK6byw+mvz5VUeMhvarxipyhNHRtGmxtLUG
WFIo54xHc0vh+hfyxHgwHridpQDlrNvYvNiZuLvRa7+foRFUKHIO4R9M3AfmFY7EeIL7YDMCUh6D
ZJC54bHhI4o0EHll6Ecl22fG4IafWZBdd4Bq3Gl4VlPEqrsDo+gvOKf2YdUTpWle9C82Q3JH8qWB
UbKbrEaDsnDnJm5Uy8JVyum0Qa3dYFPpMoQswm/bRWp3A0Xsg0F3AbrjNnXXZcV8dsPmck5yICN3
SpVia+x0SsMT++11YUpYVdzPIvrWo273I8Q7oPS67Naz9hOrfonZGjw4bvSP0yGqWv65tLBeVLxc
R6aTVIrWAlWyBp2UsbWoLf5N36YvewnH7nWzmsETwV6XSZlLBlrMjNb2LPf0QoHWq9sC2SzUJbe3
Nt6SlvCyVcubBT4B8bhtA3gGQsimzreImkBRpQAwdderknzb6fVfxJL/e6c1XbaLrFUfYS3XauXp
1jBReftzqIdatqOiNd05ivko89IBBJHjWY1U5ppOdT6lYsFNdypQ9BsxU+iGmns1ffpFh09OvmwL
uuVapu4rPA2OpXaaMCLGkLoJTn5fZ7t6Uyr1ijnlh0bBqqcxWKkBwCE8ITIKg6bg48RgHQy6VzFO
QQ6WISH3S3XQqZVWsUnhF9GqjXAIMkXguqTM6iQgQWGHahXOi+cWoyVPig+5d1uUzrB268WhWCPE
mgD3ELn7PojSfsQmlLCEGQB+ta753+ogeL3dwwYLhzP+PQm3QOpf/psJy0k60J9WtWubfztKuc+V
DQwHyDM1SQC/0oHyP6UfllkGo5lZE5H6Kt7+vQznwuSq7iZpvhaT9P8HZNwVLV1tiYkCFACh0BjI
ko++06xRcgjiAzcrLvLPrk1k7yTEsj3IXlbmAle/doKzSs88UZZTG5byU/U7RikzApwBZ24WagA4
0/eXlwWSIFk5I0BABTWZwg722SDFE2IyMb4PXH34PhU6hT6liFdsAvK87FOJD7qYJzXtDa0Re+vV
NwGUCuymrz13opmgfPhB002vU8qUTPNEq4cy36zZBAB3Eb6Df8KzR52W9fQ202LgPvEz5LTC8Ffw
/ya4PZ4E8Vmas4o+oGv2cYORJBEoFpEnf86ztN8oWSPWN5qDXYFqNxiys2fJx3aVu9x1D9Njk5mg
XW1qCOO86rWblrGAjFAwdW7d/fNvIR54tCAN2kGpIx4uPTAET9ghLL0YVWRJ+IIA0YWHdxKa4Ja8
273ROfce2t76+HXD9W5+5+uxr6q4pDpHtIiMhKsaKjUYIeXYLFVlczPsUTatH5DqH0Fxwxsdjwvf
jVu49LYW/FbC15ehPdRsXf/UJCGnRkJ3amjm4TOB+UgIgk+uTPKwqEdzEee4N/f+FHKTsnJxXLCc
uhr8SYqU1HGhtycPyVToXIMPf7w6rwl8MW+jbLr505HwIPXcM/SqOhyNQoXx7YnryFJwdzmSzLcY
aWSDGi0e9oKCesTt1w/NDY4QYvoDBFYLG4zprs+UVMTBaJwGNhIDiIa0B8EJCrNOx+3CvNHG4A8i
syvWm3OkuHw5+ogHBhQI3Gr/e7xk25LDlmWmuCZV71r4BM03hFoJTnwgbEUON8n1X9yVFSBaYQvD
yrg2uJKbhEGAMTqrUdYMXdz6Pxkw2H8kZBcjE8z378TrgOU017PfknthC8oPrF73irgxj6M0QTDA
XJjq0Jat09bXTF8xoX+nSGVzbHz0bR8Ex7rpjCqU2hqJ98+45aTl6kP0fvGsqCR8DZVW81SQmtNF
zYhs5puASMOk2CiOcAqUMKrgDhumVzx4jin4u0U37ySnnEih7pqbS3gpWSyIZgIvMwdhSMeQqSBo
uWNNeEwHXeYuMBgSHMDO4ACtMG+QGmqlykpCtqAJJHnQ+eAvBsp7WB0Id9WHl0TXuzh0/7Hh2RMk
SS2ClsWSKHRsGgyCPzOfxqohBINry/euzIE6Vqfy/a7UnEnz+TUZb8jriB4y5Dls9efACaWoamhx
9pAHAfp8h+ZFT75pdOZ9BylfOrcTPYEK7n+XsC/ousSv7ly3sBp61tL2mMtB4Op0oZ+5CRRXmmjR
7ZlXaNWTzP2QlcsLejPC6OWxyBjT/Ukzd7ALBFDoQ3LWYUSZnu4WwhX6HAedzZ0wMo5Ryw/ii6VV
hM+3n/Gr2uw/kiMKHSqKvVqu+oDpTU/P5PCBp6Ol75+mAueZpke3o9IAhUyRnalgzd6Du0nEfb6T
6hdXVWXHnrTq0yuOIk4HDPAzi2g6iGQuPFteRgjsJFXSUBUISDvdrAcFJxpNFMjrRuF1gqc9Z2NC
vyfbmh8zfvRLpqXNxKdmr8x5JaJjCElG9qrMLcGnAzT2HWyuQZ8BNme5WuuhfZkfRgvCEfKhg4Az
aZbJSbLxfqFcPV+FtzmzrlOw3gAnIAoGmomhF4QukoFNAdO/o5s88Igi16MNOC3FVmc+DsmIb2hQ
7ugswxxa7yfx+TAgZs+y/6gylqXJogaGk0YAuAvUE0m1jBDq8ZB1y7UpSmpeDrG5uDcrg78682/J
Oqa8/x35hVTfVRDALoQJzftEYqJaZ0NeT/Dj/VF0SplFbPZBzVwtvlIvA3l2KBzJAYD108LnDFi8
Z8foF3LgJ0FUNQOQS6+csgTUzDqIUkvzrPE7VpGZZvAMR6nu7DNFIn8vlZxtYnx+rPFDAPh3S13H
Bs1zrqXO3X52g/dc7ycV3EuETHX0lkA/UodnFzk886+vpjVRiKkoIRZm37pu0XLwiIPG0cj3k94e
bRyyH/ljCzSZCCnOIL9kekzfw8d6fjZw0afLu6LHt7jT5WNqH4pUrhqoaOJ9DhPiDeFwFXGwjkTM
r/UGaWjYCEtcVM6KzTl9bSqVtjE3ba+MswM+GMS4CvSjLsdMPaItwl75iEmMWLupcRL4j+VTFpzj
azFwbNQGLaW3jLF3uJUz7piyEk/KZ7PCdEmPjXiB+cQ3PSXQySCCrcy1IlT0CgxFVcoUeoZW3PsP
1a8yVGHZQSWZO/rEvJefhfHV3nEdY2XenwjWTkj061hSOerq/RsNwL2hkblXWukUvUoTTCobWLmT
PqYnaUXfKtCBFSorN1QiDi32QmLUw16HrkI2AjFOBiy2KVB2mfC9RDJTIIoTKy8L5na6fWTMjb8S
cAphroPg/0wxW1egC3kENCHFNN1bYQBaneXNtbvJkEreE3MZQmn6nvySey4nkySXxCa3nnpQleb7
biqosFlyCd6mAyK5G4Ys2iZELV+7tdPU9yVLtR3dRDMWMLtLZLwNNoVrNZZgy4BsYNzftu+1L83u
0xa+fvui2v4DjgDuUnmdtH56cXKwdiFq5/7uXIqMzUvzOcojlvD9d8JjvIm43EyfkWr6iZTw2RXG
R7UzYOIOMWzrSgCuCCCFsJLtv8Xr9s3nDf/fXmkoQtxP/PzJzR/N/hd7WGzJV0j6f1ZpoqDcreCG
MpDMd6WDUCHeznUuI+UrLf21WMFAPmZCNeVBulLTFqjNYsFindC9XQEppBS/7C83e5uK5rMV990N
fboSqNtljpa8YoObaCcp7oqCS54mPv9zK5LKSZDXuk2wy4Gq5aTdtIeQe62qNlHLg0yRllIXg3Ej
y1Hd+lCU6hDzO1GHnSDe4ClSym44zSeuWrt0W2ABq/C4BBW2RZ/SMN0DOxSGKUFhUPsGNUMY4/UQ
Bn9ZXPuz3mLnpAn7FD/cttAMnwoLl0UoVwzsdfABSecpaV9dO4i7Dicu32pAMPU6sdmYBfgqY264
XX05qklndEYXo30/XZiLFe28zyQVpngpE7iqdcL9sk0vPg/7A8dyxAipJQK9xF4VAleEF8ApSgyM
Iuad0Fi/sqQJyxy4uA0tej7FFPnwHTq1NucXmvFiLsFtH10tTPlblBKRreaApCkmKk43wMgJjTB8
g/mnRnUtt3g8wNZTahZy7qFbUlTCy52881FPHXVSAHTJxNGduKdXUptx8HxIwCQmOLcElfTcEm6A
yTJq9W/3DFcWPl0SE6GDwRvVxj+9sNZ2AIIaduBn9gedmOEtgwK5Oowv6Yxa0ofAZeKZ7GpSuxc1
yECY+VUqoC3qdskrVBpcWdj0+azjQmdo/i/Ab6w9yRWp3dqk9ZXTjL8IQFw4258LX5QKEM+MMUBg
rMd45VY4hNxazVF1yB+SA5fob2Yz2htKBCOcneEQIu2OLtKDZbp9GQD9otoHiA6vDzWgZl+31ADB
J46bAjEe6e4eqYbuEvjwEOTG/lJGBt5Udm/OG32tGbtwZOJXVsXpULOB24hy6fPwZ9Te8qtg57Kr
NLdIl0y2t9bha/Ierbyg8nEylEun098tR1lIlyMKTljUPxt2iMfXSfNwVoX55seP9XOd9BZz02EG
qOVkdg9SNWyI1dRQ+2JpKij2f4RyJSJOI2q50djZz54xRfLDp9HjgPs8I1CDvNJTFGRDrSNqamJT
bO8NU6b5fN8kDTKvIIp+GLJlv0ngImutI4dnTuNqRx16rGq1lqcHagz0HhxlI00HLgqHVG3nfOoW
A5WCDLvfBT4nYPhwLtl+4gcE6fxOOkntHD9eOtJ60w05ftVGuPN9xeuRAmFC1sV6AsTitHCfgKPg
8qD7JTeviseMVw/Wz/ebi4CPFxQZvecm+P8/OtiIQySfGHRr/oxroD/9//wzOrKRsftUOlAEEYcs
Mhwtn34zvlGmYj8TOqf/dnK+vokqGDa7OVURRcVtyojAy3g0e27EEDOjwZj1C5Pr7eKrVoJU4mMt
K6U3e8ccdQzy5pDzTFgNkwEmFE9NlsFNjYlrXtF3kdt2/QuZQxBMgEwFsjOnMfyUBxR+PE3vMGcT
xV/OdMa3zWhbQTv9YdN3H3RPHTxEYJJ3TeuaCe05RCD1neoIkmA1q+HTmAtGFtFfYeo+q2t5ZHdR
0S96AIEOBl0v9Q+QRetfINqS6O6iAWmysOat8SbNtT6jEep4FFq9vN93WxJna3crwRB8z73v2ppo
k4BVmamRXggvMRdf2fQVOIE5NS1xaZEqcDzRMMQCpmAwp3dCUxyUKOBAEbwJbSGKF98KLdwYtf90
n2ar+BlNyffkvBJvEKWJnsDgMjvBLjgylZyTgMlpm+MnkLriK683lvlNXMHfYGwFY+qEYk5c8kAX
xQjK84n8IhpH60d3Om+JRG/9GokuyqY4/dz5+IDKZtDDHc/KiINmDJfGtInlj9Cq2FLYd2Z4gLk0
bZL9sqSOKC8ixjHVSmKFMWGZBAhY9n0ZPwx8+ABo8/IPskE/Z+9hqJFFjb5CSby/lb6zJD1NJjAi
JIXtF8vX1PPxvKpEk9QAl4Hi+e4XsRx7nxb7J3CNEBPa9NEHe+C7EpOCZfXLkswhCy1gnb1J8wMu
KBsgfehDT9D50tKa642olcVmKWTYI+K0g5vUa3nc1+qpcGCieB/Vpd12HaynwvwQd5Rm1NUZu6p8
1nUCBYZgSNTrVi5Mw4be1KdZ9QQvyKhAg6X4mZbgBUU38kbEKjlB7TAdr1rb1fb2blc7IjkHEhz5
YGuSbinU8yzeTJ/1aYWbtcvpVEdx/8Cgdsz+KzSJ49gWXdSvrkmJ1bzyWxY6+369KOYiAWooTq8E
cX1/QiRCHpLotBH9PJBJpV5luPBEUOnW8K1fXDlh5IPhMTjfJplShsjT4MauC14rnrakWGiNznIy
OalD0z4bhHoz7TGtK96aMQTozSRuxtLQIu1k3SU0OlWRw2b652awUB0RnsXq9Q2upo0a5eOmUWYn
MIc8Po+xTctRVckSEJN/Z1SlqLIOJ7KzHqQe61ydXRzVQm00IEPOoKetr12QYdr/3+YpK6rbzp3D
2PzrwQTSeAjMMQuZ4aYtXyZpbWsizsCg621PE3yYK9ULiwe0/r2Bttxe5ji6CnJ3pAVXwIaul7L1
TMd1mH4+NcuBRUT2juICKlWOAHihRdHxD7l6aSMqC5xb/VJci62flv3hB0S4PK+xY/hQlvg41hfG
Evry1rt6kulfNMarS/gZlOnzaNhrGe9eEGtoRdQ/S5omlNposct4Ysk4b+9EL9wGmxhWIDjQ8S07
Wa3d4tn9qDhOl5GtBSJgVZUm/bMTujofJmoYPnDfprP4eam4JoVhwycKkNGtwMEyYndOK8I5VInW
3HSf1krSEY3tNfysMMjCDFtYz7TsmpVxQYYtO4gjGpEdCPCGGHTn01vkzRfvQanRLaI465Rp6bQw
4iYuvqRdPtPEIGl6Udrc29qrP4+7KKjNMtDYFEFWSyURy3HLlDUljX0w3JCeQ9yawhrGMA3kE8HM
+eK4v0bTMBBbu38HMBZKOYpqVAvsCciqRDlYeI6EjK2+Xd+TAME3GLFgS5dQLyvSYfT5JcdOln9Y
p3tMkznWklLCd3ovEmqAvMhtYrVGOO9BEw66Led9OH8jkdDdjS1LoHiOnH2xa/Jwbai101p8NpC8
zqsxTrevZuuXXBJRGWyYk/kiHUlI4n4/rh9MXpWTSH5Tn6jwRRF1zicf0cDuET4MMtsbFpDvGEEc
OaXQkN+KHi7WZD+OvDmtGowA84H7R+G4uZpwjbW/EKUHf398owgAC2N1+fADIElS658K/wRi5B/3
D4K8OnfB3C9+zR/SC7ySog4ZzJ5zJ3aLDsF6nMQZX6rkQ+CZsQgOR0oLUalpepZH5FMfaQ3vEzUc
f1OJKmBTctce7qddLCiYe194PZmOItfT7Sujb6PDa49xQsHGcjM2Um1VGNDYj2rxL08UJ9yB6dIP
ub2JXRi7caOkKjUBnKmdb3KOiGJBcq8/dzdLGyz8+eDlaIq1MsRl6D/acNrl3yeGiQ/MtXFFbobL
AKcF14wt7PFSXurNsIUpdK7wOb06zaIbpf65wfWwH9vyqF7/YUoUIsN3fT2KLnW7ySsnWd1mhxyC
cvt/aukOgZB2cyFIqrUvkBKoErLG8DXtFWpKJFpXTnkXp0HHsVcv/OnhSlMta5wsXRfN7Ez7wZw8
vcbpXQ5LcsLSHrenDH2HpdBm3Gb/ag0i+re8NwYx0mtsNNt4rZTCmma1CGuUIpTMPZf2W+LENXyi
lN38MffOvZaovkVEzMJu/nezQkm+y+UGDIn5sjNdXsFUobgDj7mPY7dvWhmk+uYAFAJkJejvK6SO
dSq09UJKun3eDRcQ8YG8tGuOolfBs0orrne8vBn/HK1U+IKpbQUNnLB7VbT7uOQs8bNKgIO/HjLT
BuHD2Iq3mS1Agp0a8k7KHN9pfZtiInO1wkUddYwOvA4qZlhffI3Bjx4H3g3G1dqJO8DFdSCMxsCl
A4+RsX4FRHGLzCGMjLwXrZeBmk6O9heBSIK9i+cIr12+sYp5itPnA5p38FD5WaWuzVFBWof1I/p3
3orF3qWTqzofqiwxEiE9f8TBvbRFXaLdKVnstV0XHvCN9On2ggKpcdLdgELwdyxXp4AD10DWtm24
nrLOkAD0eLWaNR63HNBLBbMPc+p0/DSqcxLbAPj7EK0jz7sb4YYOLuA+XMofYazZ6Y+Sa2ZFsD+0
wJSzNG2N2QmHQ25NDOrVrWFjjGlwKJN+PMGCeDIFc3gzAR4WvjGjL+qs8acliuZDFouh2hbej0O+
fiiv9lkGKoRwPCWf5pHBxuZF47nzo4oWPiQx+W9DFUFQom5A/eqJ9pkBSYartZHgtPYQEOLVFUJQ
kWNSNe6+R1ZN7rfUHHLVsfQDGcvrH57hJHw9UqJHzEgempiAS+MOtEoyNI1dhFnwYJp2L6BN4md9
xos91yem3sdEy+O6tITSQsHto+f/znAIRqzfLLby9t/1jMejad0hwDlkKFfvv8xb7NKr9r0sboZ5
7y3UYFm24sSENkEWkkIQi8n3yCCQQLVI+9JydeQimWkNznIwUr7vrCEZxu00qyBB+4TIt36XY727
ljdRkIE9MxSAHfR+c33giJpLZcd4q+hCdM1QK3cq/H/Nvd+QcQx3kr0GeLUpf64A//HpP95c/BJ4
NtZ3B1m1cIppkaA9dwtTGwwMTQu6mVv+A9bLFySyKi1YKf1+1t8zJZ4BW7GLTI3QuXw/zWKEJ1ZO
ekWIV5A+Z2mWP60BnswcIyFhzZ7WoJp/MM2jMpErkVTRBeneHNtAgBgRIZovc8Fq2OlGALwlBn0t
UC3kdnMdGqok511nrFLWi3lfBtki3erP3VcEMgoQu3673CWYKHOehKDMRS6sudZy6X1KIkdjlq9b
RIr5gJ2vQouMU/InKHYcqGqKO6zssj8NxKdFOJcn9hTHoiFVVYbQZpIWyKQyYoxPIKBC14NOY3v5
0LY1F4SGJ8fJ6ZFryc7Dr/DYyNGpRFeqTgn8OzO/WHoOS0ovw96MIsFK4uiyH03Jo4zCRgNOS4/P
dKy+dJLutZjITzJS5i/SrzKJa5ikRGw+OmuYFsS00VkS5IUwkoofwlBnZFfC66j2zodbITimI/gu
2BkNuhRxyuW2ZTJhAqoyJebmm8AGec48ajL2xS7P7Gb+HS5wFSsV0pj8nBehl7Z8ZkOlA90bcasc
PMKNmMJsw34d9FUUJN/4xsN5bu/e5lJnc1zD6PSuNp6kU7awe81/41hlsTpKxW+o4shNAw2pGXkA
ZeQtP40octVV8EX6K+INBwjbEaNddPkq2OEjXscUf2zxtgyZQwc5L4WiCOn9z89LNwGQOpEiQ7/+
26dFaDLbpBdJ9/scG0DGEKhI4qm351kYNO0+x0toEpsbQWjSvKcO8LkGEgAM+stIf1hB3w5DrU6D
JeZqYgdSN4llWvM2Zq8EOSpnrTA14BdXKDTk8kLo3j1XY509gp7CTfRgXav7DgLFaJQCt8+xe8/j
8jbh18xw3nt3DBmsZM0KOqbIroNGhu51D9e6X8DEn6EDM+V3rOypPwueKCy0ttwsaCEIz6ISkjXJ
n6mA6lmLmpX40X9YmLt75a+iImUj78Q5ZwHLAk4CeS3ugHpxSKvlZhfqggkjpUAC9VQ8Ek99pepF
UeZ2xtrl0wkNlmcK9Fka0AkPZ/CHa7Prliripesn0MEkc63oDunhsre6AURp0+nTIJojo/8Ru8Eg
PZQkn7JCswRw5V4HrQlLNui5jmWYq2zPOORbV6pVMUtxYCz1SwwCyg/fsNx3EUeDFIpCQUDby5CL
HYeVJn2uW1Cm38MTiqjOPoNPyrw5dh9FKlE8eUJtof3Enll9J5CsKklTIMsbcYUQNwEJNDzWiCQ0
o1AgbFNrRfW8O3Np/2XGbNfMIt7kZRJFTHGe1L6mJvtA+Hg0mALuP5DC7MQNWqNPY5N/qNW0/3m2
FZ7m3CWKtwQIqiMMv5bCkvUHpI7OGavAnJoN8lZzJQ4LF8mdoNYoySwz2K2mJr+WfgnYr/T5ADW4
CbU6ZYCwJ9MO5ScP09OuFe2c0qAkq3hzey4kWU1arKUMTPOfc9M7U1WQ21XqEDvpxhe+8jg62ync
/jQc1RRQmo24aaLMnlzNzLw/bc0m8uQJC/9CIw1CvwpED5EFVCvz3hcH1uUVW7SXTqDMpAbIB2XX
gMOt9eQDQ/RY3DgIX6GMZ7RI6eLrbZ6xLKE+8M2EhlRTR79J1EJ0DQz2oOHsaZjiULrfy7DFAKci
4y0aTnNmA3q7ggjawdm987QHBpVMxddh1bL9PvpVyxOBFvlPEu3fQvfkQf11WyBZRbMkqb3u3XVY
GDWU6MYkq8dCSxsqXdr64HQ7kI2BOt5SkSQRhmJa69FQ5xcojNoqTxwAsRdAEFyEXw3zAwUTygAM
GPt5d/F2h/NTsbpcvk9k7UXuGoWFWvxFzVkCTm5Bc2uqtE0nuifVMC8jLXt3gZfz4Y84oIjYYXkm
BFR1c44Udp+TCTW8xnncpDS4mW8xKSYYH4APtQy1/5vUEbBR3t711zdtCfbXmMdyYHykWnTOga9o
lIUCIlPv5XWhA2uixPe1SP69+x9Ymh88VRkQQm+Fjbm2gZxM5Xc8IJgk68eAmr2fVslFyh0ZMjjy
OEcuYtlRyNZvmL5stt8f7TqP9/TLJQzAuAFmKA0USo6f7hHHPaGbz3hQQvln4CT5eDgKNYG3fJDU
OE1oaYPKriO7v/BkggylVoo/ZI9RJNaC0iEKfcapbSo33xRr/qNtkrnxdsjXsCjzSJl8mLEk/oSX
ouJivTJPFCwmzUwvalMEcvHKKkSpBfVPMFeZPy40ctAtsY9WVBEnVgJJUMKEi9AXYPooFasYu29K
TcxQjxFMqOTPu0S03incIgkjM9sspLCeAr7nxo666XjCRqsgX0HjmguDCaklnFSy657yW/UaNxFm
LZpAVS56jGoJBgA5xCNoZ2OHubFjxhpf0Cfmjqi5X7fOtLNKpdt+3crqqWLmwfWBsbrydgKIlC8/
NmZTDj6rJzD+5KZA0hhLriMGQvNv+TNFws0fUqmZSpfyZlNGj084YcM9lI0UU16HSZzqoVWCqv+R
CMaROTaKsu0uDt0HU6PQZoDTCYLAcb94TNkfj4+s/3+wXHNqFlmgjH8Z6yfWVbU8LlpltKR559h7
FpWlu8sCALiLwudwMo2VSfW1ZQlzhQgxoDcN5u+iCotZUOX2OtW7Jh3wH4HvDgo0acigFVkAI6sC
yh3pJaEjHKSmV+pEfjqMnAVvtfHsk7+PcuvnG0Qed0jyha3wcNAbGEw+uSPwjh9Pvz1m6tQ+VWkb
ugkQACjZuf72K+EPZdcrWfBpq3t3qG3iMOc63Ok1e4VkLj++NPFSs6mpODh9sgFoWd1tHUpqOmoS
2IIIjVcLuVKje2p2lpP2RoNFcUDK/K2O5WyqP45FECEs3nW5lIX0CQIMOOp23g84AAdb3roS3TKH
A9pn1BPFPW+Jg4VnIgbEmddr5R/9YN5x7f8hTYtHfPoQmX9TZChAYDbo34GTZEB553RmEgLuBlYj
B/egwF8r3tMvHq3RcMAtm5xv2lT7sHxxnWy0UNYYP6MnkKYxepKS2NeWX0VNlfgYr5VO3tFnpN18
oIyQd+zriqk/8RqgMH6YIIZkA7xkfy6QyElrvBfIDv2BuQtYOkTMsC9E1byDhirP7xA7odeejyft
DPOnYsgR+madUa7mOB1grhVII0NRf+PadnT9tlNw8VMwfirztxue1Wu/z2hrRxYloveeK9O1eTCo
bncQkLZNRAbNkDlKSGlczfv/VKDwYtNUJBaGUySXWT2r18aL+4H50N57O9M1E8YUmTxKd0PQk+HP
9L/lCgmx8AYIUVQaxf2iL75zq4goYlqNhgbxqDgNEtge5nIwHKwFgrRx7wpcwxHEUnbsv0ToE9oW
a0NUbNpIu3jjr+gZ03XQLLRNPbsmnBu7BlDvAKMOkMC74M428NTVyXa5GouVIP1SFAda9CbaEFv7
eAodmbZvGQgbiQHQlVlCP7rOYK4m2g8qkxdiOHFVoBw8JZU+YtDBwMVIk79sBXa3LAdDSkFRilt0
7xs1msOtqnlQ2yLUsK+niZChHxASBtJLtZ1FKEOukeJK43hvonmHGu3iv0LJFtmMTnulL4ikVDpQ
EeVICvDJg2dFikiYyM02pbWEYCzVciflBc/UosQSAUZ95h09Uo/CcCl57VNTVMrdEiJ26Dy/3QFR
Aj7NjdnpXN3RAS6Px66cGCIWeK3WIE8Fc71LRJm4dSRmNSBwHDbFMg/SUl7MPk3osoftl4yF6HPI
e6zJ1gMfDfYEX0wcZ/LMWO+HGtEIBVSRxLqZjxDQdJaD3Ts/ogyFoIWF90kg8XeN9bZW+y7FBe63
W5OGLtCgk+eMVBAUs0S8lPtx/iImIrcKMzSvW6ka8vCGF33uoWoCo7povEWyaj+HF1d2LDUafXMV
X+nA+SXfNmV7aD6g3W+FMnARKRdS/tFdeLR0DN3EMJIlYfu6A8tqfKZj+Vp7rlX9DFQSk6Yi6uKO
qorB8VwOT34rjZysj+z3zY4PoVpOu29x/5Bd3RMWo5Gm3H3i6cNantd4htZPEP3l716PN5vC4kCh
quTeiP2YfTnPf/HJ4saAKrWBXZugqa+WxOqKPvsdSZVC5e9xV4f0acjDU39pnzOdOTbN+rgIgVtg
/coyZBwicSTs/r3x9EpedyKzSOJou8g92BopHsy/3J9+0XFnnEQyFbrhYE934Sqpr2vNlNP4bDfk
+nJtMGP+BiS9YNnP0+77ucRVyGXVThklDBZI775cf+CVSuS+INzWhDuM3JzTuhLBORw7wUWqj9x6
pOnuP5SpGQzY5dXXYpXAL5Zp9q5nyLdma7cCTIp4Ts84R0DqPyCveG4KeMwoznkcGBXuauaO49v+
aR96bFoxgAcOI3Ut2FeH9unsoUwYcNijt9rLrEq/wKrvbEdik6hYV8cZIqpWAis9oFoouSaWFWBt
fNhqhiCzgypQbYOZ20gVZmHgwRtKBd2uyaWdN+8PEJUpGUrzhYlqeM8HgIL8bQDRk+Gk6Ss+QOmi
9DjXHUqR46WUNGIRCswg9TgzfzCZgQoc8TNgtdV4+isfcVrNXe+W5VowEoAou+DS2Ni3dMiEvxb7
/v5fLZrBi9ck9ZeFH0wtA72jaK2oCMlh7mO4Ej6KiMFWI6EWWesZFm63fuDKwzArGq/LXo/2IKIk
ERpfXiEFP0rnB124fQv55a8tRrGhhmQ3CBozwltfznWepYU0zHxoATlz0zgCmGUl8qfLhiBvHdEh
DZgTvl8+hq3B7pEk5zJJ5dI+gingYaLrfio183pIQuYDKt4EkhdnLiSFJcOrji38ZLMMm+bgW4Jl
3EX8D5uFeyDEtA==
`protect end_protected
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/841f5df448bf42bc/zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl | 1 | 533334 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:40:47 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_auto_pc_2,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit |
kloboves/sicxe | vhdl/debouncer.vhd | 1 | 3491 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debouncer is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
output_o : out std_logic;
change_on_o : out std_logic;
change_off_o : out std_logic
);
end debouncer;
architecture behavioral of debouncer is
-- input sync
signal input_sync : std_logic;
-- delay counter
signal delay_counter : std_logic_vector(15 downto 0);
signal delay_counter_reset : std_logic;
signal delay_counter_done : std_logic;
-- FSM
type state_type is (OFF_READY, OFF_WAIT, ON_READY, ON_WAIT);
signal state : state_type;
signal next_state : state_type;
begin
-- input sync
input_sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
input_sync <= input_i;
end if;
end process;
-- delay counter
delay_counter_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1' or delay_counter_reset = '1') then
delay_counter <= (others => '0');
else
if (delay_counter = "1100001101010000") then
delay_counter <= (others => '0');
else
delay_counter <= delay_counter + 1;
end if;
end if;
end if;
end process;
delay_counter_done_proc : process(delay_counter)
begin
if (delay_counter = "1100001101010000") then
delay_counter_done <= '1';
else
delay_counter_done <= '0';
end if;
end process;
-- FSM
sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
if (input_sync = '1') then
state <= ON_READY;
else
state <= OFF_READY;
end if;
else
state <= next_state;
end if;
end if;
end process;
state_proc : process(state, input_sync, delay_counter_done)
begin
next_state <= state;
case (state) is
when OFF_READY =>
if (input_sync = '1') then
next_state <= OFF_WAIT;
end if;
when OFF_WAIT =>
if (delay_counter_done = '1') then
if (input_sync = '1') then
next_state <= ON_READY;
else
next_state <= OFF_READY;
end if;
end if;
when ON_READY =>
if (input_sync = '0') then
next_state <= ON_WAIT;
end if;
when ON_WAIT =>
if (delay_counter_done = '1') then
if (input_sync = '0') then
next_state <= OFF_READY;
else
next_state <= ON_READY;
end if;
end if;
when others =>
end case;
end process;
output_proc : process(state, input_sync, delay_counter_done)
begin
output_o <= '0';
change_on_o <= '0';
change_off_o <= '0';
delay_counter_reset <= '0';
case (state) is
when OFF_READY =>
output_o <= '0';
if (input_sync = '1') then
delay_counter_reset <= '1';
end if;
when OFF_WAIT =>
output_o <= '0';
if (delay_counter_done = '1' and input_sync = '1') then
change_on_o <= '1';
end if;
when ON_READY =>
output_o <= '1';
if (input_sync = '0') then
delay_counter_reset <= '1';
end if;
when ON_WAIT =>
output_o <= '1';
if (delay_counter_done = '1' and input_sync = '0') then
change_off_o <= '1';
end if;
when others =>
end case;
end process;
end behavioral;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xlconcat_0_1/zqynq_lab_1_design_xlconcat_0_1_stub.vhdl | 1 | 1473 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:28:52 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top zqynq_lab_1_design_xlconcat_0_1 -prefix
-- zqynq_lab_1_design_xlconcat_0_1_ zqynq_lab_1_design_xlconcat_0_0_stub.vhdl
-- Design : zqynq_lab_1_design_xlconcat_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zqynq_lab_1_design_xlconcat_0_1 is
Port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end zqynq_lab_1_design_xlconcat_0_1;
architecture stub of zqynq_lab_1_design_xlconcat_0_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "In0[0:0],In1[0:0],dout[1:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "xlconcat_v2_1_1_xlconcat,Vivado 2017.2";
begin
end;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fmul_2_max_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd | 16 | 292080 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YNZOfwFmq+EKwX1iXTqpnCzO6NCkg8iVZ15wmEqF2fK31FdwL7p+998IAHTcmvJXXulOlBvS6vH1
+iYCkUubZg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
fSuLWicvAgz15dAyaBM1McguU+c1OlTxM3rwIjZed+XVwT0aj3kC8vBXZpS89nkrz4cH1M3IFZBK
zd+c70XrF2f50b7PhHzi1/zvy7zfnrDsI3RQtNlcdzxESKaNa2OVRlTl1FiVvvM0flfMEoGOVBEg
CInpOdHF1+GNpH3Jzc4=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
c0YpjGsmE6XFKBplkrecWMiGPy4/BXTRGoswHI3n2HH7rRfRrIKKFBskl5r4MXDh+36ObQ/r4PAk
tfwFXdRBQQdjX794wIxcy6RXY7xcRmOpxCWwo0hF7M+Du5JZuTdvu5waK1k3RHlAIf9fMqtpFqa4
/KglkgOK46YLWOg98V4=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cUsDUT+TuVyMSf/EEh3e3oVg55uMy42ju7dn2qfNxoV/6aNQsmopR/owNzHJ8w2iRIbnD/sWUeVD
YfC5Nh9wQkO+W++ModGSDC7LnmRkQos1o2QXsyGO7CwRp+BAnJvattDBYemVwv4BYerghJyYxugG
VuaHyMph06OOJqTM01KRiHL1l6599aYPL6x1/zhvgxuLp5p+bcz4yWnxtE0ZoamT2LCdP7gM6f6C
edWtC0tvUpoBL6a3+CkNW424HNzG7euC5cgFf3whD5KjxK0sgU3DOgHfGxtZT3pY69/36mu756TX
JZSijhFRV50xlcUra7R9ar0hdrBRjEOSw7W3vg==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
msL2o+GmDoFk+NL6vgip8zUMztiw6jKP1JrnEkE+4rDO8UAEw73Bp+XaWDJ56xzku7n2eZey3ZXo
5t0kzk9ueKFNecgIlJ+KU5U2yQqYWSItsRIQuSu4rKPl8Rqn+dE0pcawYSBPhVOsFFtaXlpfXI5E
/6dCGckETNQ7yeYg58KrKQfp5W9zaaEw+sE6ym7QBzCBb3dmWjdUqH7paIeYhjytGjAkhoofSzNg
g8k2NBO+eeLdDWD+xxiRjuDbJXen+TTEMwG3QFWPP6FJTr097RR19HGV0ON+WT7z7zJCaS6N+Ajv
3OxS7NRyD6qW0oN/CBWf8OZtJ5pG6dKBLcxCJQ==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
kXQIZv8mrCnXdeUXTei22vQEDigOjr4M+bzu4+tut8y+H4BU8tqpgWzAawYjBx0Q9HqqEYYKSACf
UeawwsHxb2466iL/YrIN9+RqC9NKqlbJC0Gk251C/dmXlDQUuvsewDbLU4g9y+zb3nua3y4dKwNC
QE25LX/Sa3SyQazOgoFWwhfEsmEbi2LDvoNJWIuq7sSOK2Awu1VlnbJcXjjblq6y0akDL9wLxa0z
9pb1oK/XSraNLnR9asMy7i1xZ7fwmuxwLowdIK1CU6T/qtrhXctBLMsJlQ3gnD7FJ2klrTuK3ilX
2lNAz+VBfdEokkhLi1QPBxGu0q6x58LkOoJ5Fw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214080)
`protect data_block
BR1Q16Lyg5zz6kUNIT1/rUVWp1M1MAxsi8GRvHObVeRDDhUtG4HwVLWBhwN7oZq1PeZ8fiBCeUnY
GLuxSH6VPc7Ep4Q2rDBs7DAz8dfWQb1LnMEB4lXwtXR4DJwittOqTklXJ0bv8Wt7aEyWWhCNKKio
v3x8RzWi4xSeOJTcl7VvmVRF4ZCSbzSi3gwZ5D7NkqnN78x7qvs9IaZ7+sUk9tqvRGcTKJb8mFeh
383QXS2Odp82BtHJontYNTFemShoOdmQUtt3TCT3z8DS6apGPx2XCsSyUzLnhCPQB3RG5LJgLaKP
OSpTiGNIs2Y3voZU7+8ATsTkko+1szYoG32QramG3zNz5HnHxcasFU56LZvQ8G40S1vZWwZaqbpq
8FBRHEi/CRkCJq+z1w4DxVQv/FvnFyfVVglAS7WHs7TgafDag4ZAgpiyOlP1hBy8c95JR4kv3SAX
8ASRqInPYY8HLN6A4mImkIX3YQge6uPjx3Gu6yzUIpcL3Dr+qgq+kNiKu7UQnXZ86IMYeiZz9Uw3
gEpnq00YIaccHMXqAvjBrljJuBAy+QEKZ0tmpaJhzBUNRwpW8pRZXpzPb8SssWvQHQF6UpTw1Ncn
cGF+TveIZkx6u8CbTof5tY+pGoxAwbKXVHpQGy8JI/YApoM4gFB3kO0yGeMVsEZ6pMWHyLr+uWJY
hJ8LQYicN6CtmGkdKgHYp0WH0W9QuE2bz2A7lCwsTey9NpPVppgw13WRweaZoOO2bmrhmQWM9Ste
Pz14BsSz5StRO6emnbc6g/bg8wdkdEUhAdg3Q9gAtUTtKtAgdOTaq6S1h5z7163v1gYg8jJnuO5t
i+v8FpXHhjWKetJLwjJu3wgfhG2zeWQ1zr6+2nEoZFSBlEpocREGBPBbqTENGBxOmiXeuVQj+j4F
hbS+n41nPbaFEmm4MxwCOWF8igwSUN/QjN9RA6wqjcY1G88cFeF7SLMqFlNsxA/c0WnJlC2jCcIg
ZkkIvUPBeBe0thAxkSB1NNfFBTgW15BCD2inpCFzX4HWWiohnhEyKmMlXI2DhNvCr/da0JkOPpXV
ZK4qG1nHxY9afOsdsr80zjOklpilxqv1yA3GqC1jjsoN2G+7DFX3MqT3WLtZgO0c+TAfh2/YjkHM
z4dIoFMrYz6JqFxWCDU80e37UuuU/V56w4SSzUlFxsxVc8sj7JnVC0D/2lhu5i/csncT/1QkLvsA
gQailKvcsWcH4cZJTvwNlohWvjVVX69oAcJTWtA1Qsn10vQ6FaOXar7rHmSYrLDJwVikZQHM2JsH
o8zcngFSO71GAzB9lRx4jbVjOVYo/t1aAuHH9XQwiuba6il3yIkWmxvPy7VPc7WuDA4fIl2eG1gi
pSPrK/2o+scJ9NR627nnUkBLSc0GcZBgHSbbtf6kLV29YdIe79rruwgANFjTRsaQJxmTbh6aDwTQ
ZgiOSUj7Yh27d1GhU1TEhmP/HLBjnCXWkmjt3lIULjR6ktBzulf5nK4uONilkUrrM84BUGhj8Ctg
JpYEu0pQ9fhtHvZdagKs/4f59HU4FwCDsgBf7yOBSMG08gfNK38kT4uWzO0sSGjO6z0cgtf4UzgD
gJdAncHFQU0XDg4+Uh58ldqUQNs+xj+Gb2OoaRKW5ThG2u1VPGGuFOud/11QuHb3xnhkzxImMims
JGdrAQ8/zlZghI+mQGI7fugi5U6o2hgiR52YSPou491jSs69Hr4o9+31Uk/O2+qLgB0iQmroafVA
HvURSCmLQ5OVjH3GMi1VJ8/dY0i4kNxTnGpYwr36q1VjxeCN1JJuCtw+jH14xC9dd7jY9NsIBATU
dwyw2D8vSx+m55g1+FMlj2WirC2fToU/EXBnCCy3xvbCX2T9mIAwti69ziGNJanstLKrNns3dfwE
IVjvXIkrI1fmrovyFJQUV8zFtnHZjK7OLB/dL984VmPVLS14K+yPbVUR7HF8452myt8FGuqVhOma
D1tGpzWIc2qwTVa4CFgAQWbmMoVAt2bULpy88F9NQ1B+6OAUd0g/4SQZmrhfL58W8ddIOZSMd/nA
zaHh+zUH/+N7+lwGQ4lF7cHnp1Jc+tEbssDNxGqVPsYrCXb6M9Vyxqh0GOZtoJr4l00CLF5fn2Ho
6G86be4szTVe4TZheAT55nK431wWiuDCR8SjHJxkPpPxKtEki14IsUrRhnnQdk+ubjbnS4Vnjo2x
JwlMSHr/W6IFPk88iQDjUYXQKDhZpyfvQqKIVhGDTzOuB43or6wt/Yay2Ux+VfGU6907WqjZu/ft
+LH63N7k2ySUbOlK5OLz8k4mcRRTDDXaCDs1lc2h/Bv5LQ3Rmr9iF1TXBeEGwcV80HtDxjP4vD4w
JIwiZc3ypYouya8NtbvXbbfEdVh/Vzrx4CVGHybD5YXCvQHABHcgRdP2wxRSTlc1favJyU58gsxf
lZDwsfuuV/mc+SZuYxo+kZQNcd7J9AxSRO21OVPVdlNnVk2b3e7NsVF9yMhVALs6co2FWrca9rYr
QawDNpQD3RhrhzSDsuOglPMxsX4IF4GLNfENamVh3pHmXbD+3aR0Rz6ziB8GOP2A/EWbuBfBX9jh
AS5KigAYwf4UIvSm6+U3s6wCeSpP6O4dci0rL3jo4bKllVNcPuO4/tweZKafgFdyn48e8XM9f6zq
abEfoNT7izTjBdJfzh5oiahi2U0Yy5LWL+tvdkEjSMgE9iQ7A30yHXo8MfSb3haME8n4wfZP3WH4
w1BcU7EWYn4hozbJ7omyOudp1GyROpgMVVZtu4HfXuKxGblAIg1irSg7Vk8x2xm16H08bRDJZp9Z
v7UDskSoLjQ+0I+VjEHdumlOpUA07/Yw1x7NBJ43pA6M1w5hJjpawm2AJJYPGemTfWW6DhNy0Yh5
CO5E+SwQymR9rDhe+MjDXrfNxESS7eQXm4rUkLOP6BzHTmgQ3ULwlx7ChIblxiTtu/j5JndaJoho
YS3ugUPcZSA/XygT/BP6faJkR4UkGzweUH3OO2tSWp53KMC8sqKhYfMiArPqMK3eDozMEyoeJ2so
C4DiAjJG4mZzRBAPzl2RtgWDEE9gmZNHKa3NltxA73dHrad9qdKB0OMtOmLX2HfYIpu24JqX7FGa
h0+NWZlBRPuTGV5WdZUg6M724pJHnG/9PDhseTqjG/LfXITjD0pE1Pv4G6PyDJ1D5YrDrsgdrtBE
RACjmYj8jHAbj9QiMFM4U1a77UkcLLacxkIxiv32FLOoYQI5LYfkrZprtuLbekpq5HUVRua0D65r
SBRRnxHR0s4Evm32yhGnoGGhGMqHzl/OmBs90jbLwXQa+yR6Jku47XStOziHBtfOteQ2EWlswhdo
Tft1JOCce9uxEwjAOJTOlaQg7sayhSE8KkF2qllY3lPwez+bCMkWvC9KFX4UXq4ToWvh/gIwVuSP
LkywPwXZoLN3hZjmhrSUQmsrNp/JBoGW44jCtuuvyczAnkqguIFjVdEhfRkty8QFHlTFz7GqkeEE
1HrV6ffDOJOYdRndqdHVNdp9SOqGWmJ+dfT5BURCdTxdgjqw4iRIhBdl9c+O5eA8+H2goPsL9LUK
6tx4uOx+g6Pr4/01+Bp5aCrsiiqqDpTGi4/Y9mR1YZn7n+njtA9gm+BAbDO6EzSmPe/fa9Cn+cZF
ndzAjkZ0GOWi6Nv4QXM3FffCCAWUYKejbzS769+rXZZc91akEUpG92iPuEykeg4KAy3pZZh6Afmo
z/ja7wBXeuLFxNZ7LHfkNAqq/PL9DfVYuotgjxQ/UCXTluPo9u4hVyfN85EmjeiVIchysrlh4V3u
d8FDTTeRaODMPl/Us0F899qnepstx8W4ZdpONVMxlOf9hP1+anC1iN2h5gauKgqQ8YAh/L+xLJ/K
3MUh8jRw9EHg88NeL2wIex80Mx76AwGb2S62cSO3f0yYUkvAJsC3NydRwpf4qgGvMtgfxVKmwYl4
RkLPmCWhAnoLuhqveWvvEirP5txkHZd/tYJ3VRCS+1hl+Lb/IRXNEOEdH55W9jtAdN5JqITmjk6O
cxpT3R0ez6GY+q32Q+kPul9ER1gBzPPMWWdPBxZ7CJsDJMJLRCK3f9bJPCHe/y3cI/gWF0fY4iM3
QGgheDrSUeVKrTSCjHiGE5qJ6vcA/ddJMQnDeuF/24AOK6iNHHIkxrCuVy5hkKvG6Y4sryVOLEUV
alshUJM4J296SJjxNSVpd4q9u2jTvwQY1mXbp3umx2105H7FO7ThU/Lf/rNpdGOy0yWFUvQ13lIM
C9bCmhkkpFvo2h9F1YvJmvHRDK3NZkq5xgYxb8WH+1vryrbA+Aliop5YaAAIXTxQwJt2lfJJXcfZ
dg66dTBJ95Kq+2Tp1z7vhggalibPOttGx5XYAwCpYXZXmdMnNLUSTCOXDWQQWvubRgfD+MuspBqV
2eu2FAgn/cYid4mIoubRztD2SXVIVfeZYAgIJIVcHbb+AZeBRsM/DfmhFUdYm8uro/43s2ez1Sgo
+Tn77TR4umfbvll/IwKyfUoME0HDLt1S+zmis+8rkOGun8nBqMSgybe9vSm4nXad2M1oZWyUoaOx
7KPbT5Tt0RXXtivmmKbchL8FmSr8niyjjMG6CSyEQL46lY3Y5KfUI6TwGLAL47EyiL1CbNxfnKa+
B7XbCdYnLY8PuZjNP3ntyEhDr9mJr91uK7HzfKrEFrI/Do6H4rDHlWUDKC95gLcw3bqAV56/0bZP
UT2NY8IRAZGwi11YmDzanMy56oAh0WIcJAkNGhzwR4ozuIIdxVoJUXMiL38hK15jsEo8nf4jeCnq
WkltNuQmtGJP0xbWtSiBCKRBu0ezci/ky3LKU0EjH+TbfHfEObfYiLjz5ElVb24XOEHLbCk8BrRj
8CqPuFOIcWe9ex3VhVrOWKYPCuqVwxwhiwZKhvUNMUs2pwa5XQB+OK5Yxwly/OMX/G3zJ4qgz024
gTmOrJ+Y9ft6HTFBhrc5DCEstIxR7IbJlVGgzwaaW2LWZ0YLhFOQ1gMQFqKS86tu+gISs1LgdPP4
QAIWY26C9rDbWuZeBNI6KdhbmL8c+yAnQ1ir2qPeiz0JP3KZZlKfTECbgM24FsfdEIr1pt7Rx9Qt
3rTY8qmkAwcNEUxK4BDAEWw23aNimVxXO4yPkXJ8Dc+q0ietgW9mXaFJTmJvHSl24sOVmwIzcjUQ
MwbyjdFIObPlwr4G6oAsbwDjN8rvhq/UOU2rPvyGkuk0otim4do5ul2aXX80gok+vLMiA3XZyob0
izSnDBk5ooYfqlaPDPFRqdFfNU0eGzb/t4HvCl89qT4FKsRynkgxAjbja0JPUlJJP6Eqm2sH8aU2
0BOYSTbCABhunP6NNdJ17SEbCwVVN709q53ZplfzU6yllCARZRm3jBLbUD/llpf4a30wAUmYI3xu
XV3OfrRJZSMSUIGn0mDnILPtm1vCGKhH4RHXskwhrU0EgB11kkjXJ37ecmoUQGrMQcNV0pflIxtp
w4STGBZXkv70WzmKYYExXcTPk3gGl9DQytj9KCAzEF0N5gxYp2ir5xX6d2UZFIxtZSZcITsSYC3X
2lOeEiNDos6nP7/+yJXBgI2zsHZ3jSX6VIgSCxkW7QtUFpZ/VMm6kZJYzerC4Hnbn6T4RKaoQDVz
OfQMsqW+asrudukxZyEC6/gaG4uFNNnXkV7VseuNqdOiwA0iluvBsFFgR/01tkTvYaAnxCHYG8vW
sSMQKzPQNrvqasDXpoM0abfGqR9GvvVFMsXuLw1PhArVu2x9oWXun4bmI1XrE8lbbK4CbWce8HsS
/j4XE1OhmU53iPAx1e/8pXTvjv58aJ72SNEEfoWH88qQFvij56nlmlHiip9aHa2S7bqss2d+2qrg
4DcxLoR9LKCoMD1hO8OOrh5kUnAkEj9p0K+FLGTRJR5dq1Xw6s4eCBrWgEi0KI1ZMm++K6sJ8c09
Hj1byKlobPmK1sAcsfq8503siyNJpuDWKVvuAr9whRVZHmYIH0EQSO8N0bp717j9/g/8I3OnDl5j
vsJwl8u47w04HivS56Veunvx/zcR68IjyKcVGYXcwG3pObmVfe3KphK+YmG0k4Ddjbp7xnu23wH6
b/bLqE1+5+DfzDXTsMIAg87Yt2dDx0+y+5/pi9cZHLlNsxIbcaorzv1PpsLGZyd1qY2gGM/d79rd
LIwsvbVZaiWeaIa9evyy7jALJvJvbe7UU645i/lquN3Ilk7dE/RDGcJerMdIl3J58p2g6X7MxCXW
4W91NZNcn2BcWkOMAGIJkigeaLdWQxy1v9phJiORHqbdIoeLQn1avPCJRCnWTnWDVC6hE9dT/Ury
JGJMLDADdMQBeJIc8eKG2SM2K92fzdf3AuF78MDM3M1J7SDtVU9J/7qN5Rzdg4rS64rhT+EnGByn
uHAUKs/RrJJx+TtTvLiSNid0zMNMKH05qriw0EdMEw83hm6wkeNEooEi5ltcziCMsLTXgVmAj2pc
Bid76IQYvZZg+GfVyuZCfpVrcmislWROpw3fKv4FIlyq49ZY3zdyUvtnCMZkNcNekmvy0R7I2quR
Kh45SfO7PcOGrubW4H9Vnt95GtCLiVvelbNsh0Bumk6op8caUIHyedpcFM8VVE2HxYpx3NIhqBdh
czVivuiMfKTaSzODkrOyY90DAA5EqKF165SThok/x6K7yPVOuZnu0LxEIlx9arnzNN7cSLwx460e
DiRbDg1y65vPJ2WJ+N0OG+o097XNEfFcJUIUQhOqaPFMQhU7ynav9TYRbjlSu/EuGnCIqvBZn4oM
4VwFtb0xlVSXLIrcSqKOgGWlhGum/OID3NsCWVSRIgn92x9Kl60ar+2j7Uqt/kMMK/Pyufmkz+6P
UQ2le0WoYXUrF9ORuuJaPklkt6iA7w0niMGUDw7S3EYjE6uOrcanqez+KlbxFxb75o97uFesk+Pb
b/0V4O7S5WAuJ4qVQd3300ZYN0EULUMc7uzvcDTkk+Gw2EaWoYSJHanMWhHklnDeQ4t5SrIQUwwb
O3Qmx1XoOTwGghv2ytqJdiZI5z113urzEe/srCkZ3fsatvrnFYtpvQFFxkIPp5oP16C3sNn3ADbC
ur3kqqVEzwwuS5KM1qQKNKsOh+wiF5efUSGb6wKxhhkihGdV3pzZniEWucq/o2dAF6rL7UeB4e82
TTjMWOtRM2oGA2+KGV/mpAAcZt290vstpOy2RBHsVJDp59Bf2tnHIuy5Ls6xjAi7urOVolMW11Ee
Uel2oDZzh6DQBC81Lsl43LFFHLdDjPcs695d8qRgWbonBfNpvVBDUdPdGBrGm3lSRw6FsIH4A1DQ
Ejpms6oNu1PFQtmnpzBtEGdsrIfFbNfBYEeysNl5/q/Xu44H7+hxLFwwVKr8EpVFRdtnF23lvn2Q
rHwnY17jlXivPgIN/p+woSEHgre+iTgC3h0ndrn2j20kgSGdD37jJJJ0H6c8OqaJEWvFKhAN8enT
cyvM7c+DqjY8GtaECTPEr1NJ7gqvKVc8u+vXGgHZ1oAsP0UdTFu3aDeD03oqVxC+wFqdvG3yqCZK
bvoUNNYE5c86giQjQUK+JKXR+8EbziMeQPE0VdCxuW1KNtECcSR0rEzGFIFT01lvBjy4VX305CDf
ediwWyRxsCmix8XY/dlBw/+h9Al03W9j0bHCgYZHSVt2SRrTLufj1s7LOJ66pt5u0v+fk1N3vZK2
Qotq4LBIQ0ku5Htl3QMnDz3XUs2jijaAQ1M6L465ssh4gTdeJKbQDw/c5ByMgi+70xDwLoGY/X00
uDGsPygdyUUNz88waf5cPGEepMsJLEDcpj6YHe2DsYdlFWycZG89UWkbo05tXz6qVmZZS10MN66e
FejGWBBmymaZOAtCKnMUKNCTT/z56pDIG3vsRQMQLn0KbyO2EOyvy08GWu9gvRyT8SyCNrVozvjR
xPJe5FhgrJyq0utal5efWvLR3QKxTY08V6ht56rLgANt7lipYph1UG9rmj/DRghRCTXeYpP/V1EN
o3fOEUUQ7UbhDjwJ44RVWYPaAUjhm4EoiginyoIBmejWCTPOIaRQHb/wBx5rwkEKHtCTaojAn0JZ
TiXOmZL80zhhPzroti+QMveCnqoH04b9TpmMsJOYgN9+5b0OQb/G5FROgOjhTxD0LK4lh2I2LUGy
eTQWGCvkN010fYgI6IbPybY7K5NL3fNBXQ45WxJ26tkQBxRQHj+1CeOvk53vKYbhT66mCKsszJO6
RW2RE56pGRNyIjZjXqf+IMw6G77eRalpb2hUdCQR7t4HYbbER4dgSZfzKpY+SFNaqpaG0L2ha5t+
Q5blpq887kdWGy3dRetuvQCvcFnlZ7pkrxWt8+Q/GbBaBxX3t4O62bFc/eqyWu480q2ImQrDiLy1
Opt7t1hJQd91KHTE7ffxwB6DF75xAp37OZKz7ixS0lAGtOCcvV+EkthiaohMUhEClI2XaUt8Hzh9
pxoy5FyNajYfN6n6iMaQs74Y5rqpmBHAU4jovBoci9jlNGSiZUm3gPEQmAGCvAfbGXB651m46TS1
iiGCDrqwouZmI4S1jDva8Ie592zfDxWf+ArGULOeEM2DJN+r/3nkgIqfBNXLwUl9QfQMyN5dsli1
NoQ4cZ6butVnpxZzfRybrUE1mSaMZyEekOK3fGbsMq05mjfRMEZC3A10eaBdqhGQ26WywsWgRSwQ
Xb0yuCveCNh0stJZwyZnFXTL4qGfFdjCcrwE2XDUD0tMORbLKwyX1WycEDw4AUbLKAL32pqX9gSJ
pZvGKhwjcHTjpN95xYpEC+TVW44V3P1XbNc2ofI77ewBhtb8hmEIHbxF0pHp2c3cCvgog79SYUPx
3KqZ+GmpM/x3jRvQvyW3E+0jIyNYOFTA5S3Tf6tVM/fCMMYU5AeyuB3fi4HOl85XVPp4+tZc+BnW
vEyV0GuhLBOgySvGNOa1Cz0gKw47ISsJYysuPzW5ruDYidh0zeToG6+iQXXN/HrBMbqzmIuAAV42
BgaPudbEg5SXPHpAPaGxfSULJMlSu+6mklELSTEh2mbetT6IE6nL3v2ipVMZ7OoflRLY2CX7IRpI
u4ucOEppIDYNbGjbPit9BJlh0mSN0ONclQvNZ8pGFP35m4Q/95B5yMFSKjrZrhy6U92RajzXAFCo
aSTGbehpMVwRxQFs6I8RplcpwPOQGfUccd8vqa+9MS46DfWD9pQIWfoyIcIZPCFsWpUgoe5iumyJ
EsdBFGaKmhyF4+S8umgUae+SWZa1NOrALEyg6eo+pVjo2q0/T6wPNCWNu/yQ93vXvKuUYtXyAlNt
tQbXbPcCQVFUi+/aFFpPKXfaso9lcJrpJcsmb+OwL68Jx/x5am61Gu5f6jneS8ZkKVU2XSpg4svK
MWSMzmFr1Cf80ByP/yRB+68Kh76zInmqgEuroh4PUhbUG2rUqFu4/XcjODWfKe0a8vXaK8RMP/1b
cABZeqpjaQxEv3lZ3vW/lwjW7HBcLMZ+kbTKRyD1DHQ4K4mRfZiyrY9vQg5k7A1LTHELWij8rcl3
ti0ly7F2lVxJ5Gz57Ab8WjXT+jKw4ARichRj3uiIGZhVdY88TTfQHJ3MdLfOOBcyaA5jtXkxUrTO
6eED548WTN06oK2ijnkJeVy9A1vjrETB2DFdVY3svHV1S7e3z1yX1Y1woOvM8Ki/fqQMfhTBFV9M
A6l72IMYBEvn638kzyU7PxG5dqFypWtuO0hLTXMQcBJBZBTZzi+LjUtsOSE0dcqWAM4m3OxMFNek
tpNdczeLp66j8GnPxQ+TTYXGiaLgbSKiXoXzrj+Omg2CylIYeNoMBJrC8vVELBjf56l+SIfATDIu
lfOZYktfRRRHt7vPWrGjoROzh2+BOurZW0eoXyeryqT+0ZvXsI6uEyqVYElm5URg+2zfPh5Fq19T
efd/xfIl6nKLEtCgDlzZe3/dQajmCCrr4moMTIvxsiNf5EYpPEclw5XWwPxxlZEWlWdmkWgQ99Tk
1ho4KFPoYNRvbTTibS5avBmy17dx287+MGFzCzRv3DQZ7rTsvIWDchECwikCQzJoOQyMuJ3R0zAR
9GGspEw9LIEoWj/JgodLPbFosEQTWVi1F/x9P+DgFFVrBKtA3CNxhdv4JQstFtZXvl8q/TrVoSh9
XGl7wO9jlKLlnlfpU+9wi5WhdVH4vm4/2dPgt4pNStp6E2VX2CaYl0H2fN6oemDnd8pJ8reRcGQ2
pOfpY66VANypT9SwD2Noqt8M00XJEdnC6fsFQr2THr90SovPaN3USHB58a5o8tFrrDBc/vukCVQi
Q9BaBEc3qtJ/165NG8DcTMo1dFS+QL4LWgQnR5hgZngI1DB1OUqFvIOD7oTJZN2MalwR3pfD5cZS
WHVX0fn8m/zWt+3ZxrPpeHySd+NUlSoins1W9npHgfOPN47JUGjoguf1t0CYmZsWg0xLbFgF38a2
dEJVWP6HJKaoP+7cQa1bXlrPCvqrORZUl7gNhaakOEnbaQft9dviaKbCXsUTuUFJ94+Hj5sCz/2f
tAoF5O6F2YWUC/MCZEPqJeXfN/GGrpBwjAhiuN8a+uIsJ2bdyd0+BezcPB1VAZu0ydkM4SVxt9K8
hteRBmwGiZuYfba+lZ6jXv2GftfJB3NnC0oRw2/yUjRLozuPeTl8Kq+PguNorq2dttQqK4o6BANB
u6gCzHptqiex5iIINKjG/emYNszSeK6y2PbQ+uS4wDBRy5JIABsIiZXG2l5jy/CZA3jKUHnI+EB2
go2sF46w2B7820BLpmaNUSt4e4SfO0W5lZjICuy1HjZOWeUvg3IWESvV4E0erd7gXsM65jbpIDfb
Di66ZzaXKaULR45IwARDLF41WT8C4FK+zVhClH/jam32idL5dxFDeqMMLrJj5Ue8ol+UYeRerH8C
y3hOzyJsaxXb+Ojtk62SN3fqT6XTpM4O7WUMkhWbg2YJ+wHaF/i5Y6kgFe9VteBSDwhqFY40QKzZ
ojHRssGWIcKCbErhHV2b+mBEesS6b0ZlPq6+Ufw4AzdJuSqaFq0jZ9uZKqW9neBsrNl+dkeuDSLY
QBRzQW/wH2+pzqrR7yaxAzPhZifCJ1RGxYzptPc1MjuMYwvWyYZwPoWBFCyj4ib53eVNpVwMqEV9
hF46W7XVJ9S0yseIR6MWy/nqMh7lKh2DzJjubOksTZwUzqoI5MIdy7xgnFfZnNKFkTlO8I+LeGLq
/jsgorocKI/eaov/kH+p4ntxzZ2eM41lz+N1QYJKm//9E/1yDNS1HYLQA0z/qfuAjQVirAuz9iFY
iDeQivkBtvCIIL/7ldw7oe9lkOLnR5c6/3Ggl+QOxUQhqSqmyoizhlgbR01UJ4/rd8lhAIdNaYX6
2j5HjYgOpipKXpNXNpi6W9G5cfmiFZxDCnfeYCeUXaVOHrIwHmleu3W2s2Jspjdp/Q8235xlaDLS
337LfEB45lHJJUJ7K4j1IgI0gm+WC8rAZpyW3Rahx7nFtdvFKvlvq6/FdMmIGDUvNwTz5R0YId4s
wjuznAOX12wmI8WCXw3garUvcqrw0R+/9JF9qboMeSCq8uLLuHnbkJ8luo9lbrt1q4VebTpjVQLG
uswwTq8H99BlrUOMHMCp9UIoIIutSzKCeleC4xGT/ETiik0cU9CcdiTzzOr+XRsRI3Y7u30ex+VI
13DMpNY5pjqgYejMTGu7I+Fuw5PwnE25c0YCeAG8aoBhZn4e3Va0omVuXU6m4ZApuTTvQor7tov3
gaO+afdxAStccTq/tE4BQr8dc7NS/rQlxnSImjoi1DZP/u3Zs8lj/4MlcqqMVKsrHhMACKCulB46
ZBSm97bVlvrjKNksWETEWJCWFn+8sNZru6JnwGHleZ8hEJyEAv3tD/YJ+7bwozZczuNu3NELNw3s
LAAI/AE3xroPjH4LQN5P3rNmzw5lpiXe8l8wvKkKR0V8KvuRFNF5XkAMhH0Bb7qQG5a3yAZWsgw1
i0wpcaKzB414famGkPjln7BW1kY76iVZw353waeulfHtb4WztHYOOLg7760vtlQovtCMjwjRAkNC
ZOuMG+wywM79FUuj4ReVVKt7+m5pGMoi+WI9y8bzhwxVWbgc/loPe/Yvjt+oronMcI00tXJTyDU2
R7Ov4VakyfpYRV3PY11paB+SAS/NDLZTQYes0/YTq3ZZOEn/dqp0blwhLxFp7fHSFzSNMxdfUPEM
IIDeo9W+JyBH1rdrAwVbKjv+Odx9TdlYSj7sAuWsM4xi+eZ2M8jbfb2nYrSTxdCDz7FEq6GhgJXn
KCnAweiBPct+i8HLZiOUiYrm5zg6AF5Dtt+xRKJu4dywIxT2bLZCryxJ73Onp9ps0jmrdb7ashpM
h0XROh6oj+Xh2tDZjQ7UI4RGqq5+vqEoke2ldswDEQN3cT2neGB+wnBkBXWQz0TFQoIhqTGgfuiZ
CZcpaMkGEhmhrqThGsGuV3rHtVdHrF+lPfe0uPUCCag6vlrFP4doB3cuykeqX5OrcwrwImcF20Wh
zLMIO9WsfIUDCI3DUXnF74fGl8ZH2jOBAl1cuPlpFqjd41dhQ8cP4ocpXK0Q44xu6uIPaMvk20yC
L5C4x0D8YXF8ccFVEeD2Hk40HD8yBljjdj56lX4MV/5Dmpp6E39OhOBiBiDHwR2f/orM2pOp3mTw
ny97EnuNlEDlraUJnSzGZb9l3ny3b+7Ip0aYLrz0wp5aNqVmLxythHDztQVKs4hQY9tncW8Ngp3Y
pdz+I8m1zt4YANLqt9ssiovGfOmzGYR18a/VBTzAfjrD3V+mQyRRYNzs52cIqVzY7twTYr5A97Fq
5TyD/4SiJ7V/TQoztW6D4lNxjp3pbKM/UZyLZXWOu9UAVHi2F7yRTFl7zBmxfJkUeIJ/kVfDxAR5
Mnx8kWqVGv+Fa5md8zEOdAmjYJioNq0wjFqRmbgZxXbuLKwEtqRZThkZqblglD8LjAeRH5HW1ISN
FY/WPenQIfK0ABpH+Pjtp2MsWKyQMrD9uYpjB7s3TBU1s0bOR7eBaP1Wh3R7Ks3NBQayXMoYRcZG
/LN11EMPKhIoKw+4xVHp49S/TsKGe6ENnbOIodklKMW72XqsJe3H8lihpnKFj3WOKkKWklRXAide
I5NHqwNbw5SFg50mhmHf4HdmJ12lLycmEVUneAw0zB39kXODgDUyhrqAsCtUUKUAWIZVlnnHze40
h1tDWQwYIYiEvhDi+Dl/MXqqK+4OVZTojBBW/Nlbp7lWU2ERiH1812YY+XC4wrUlpEbBQEHLb4ir
HiqWsSBOx4OlsQPJ/arBaR6LkNHsp3LjNbkPyAjFEjuGjIvDBzHTJsSQZON4sZf6qwH4Yo97O+3w
5PLLOhbKmyTmwmwofUmnYYQfShUofVkqZ3p/HaLDcB6zlPZ8+dq0jBdTQeOHOfoA+L5+4cltfdYn
lzh8qmLhaK9NChE7JC7oT0o/uCkM0+0baDl5YaN3hrh4e9puX3A7OJsOID0JILtIjBzqVStwjIzB
+rs2qRVPRYrx/74OGfBRAH4hODkDzXrFk1bjd2RizcQEGkjc2+Ahww9R0tI0BxBMaeMnCbSkWJqO
jwG8Rj4kGkeWnBbMlQUPsh+DNaYAK8bHgM/cU03ebESCMbI3pExG69Rum7kw8BgVXO4eCYeZvmoE
CQPoxfWynx/s/v+kZ+Z81UzlKRYFRgouM6Prus+IY52y1eUlDYcVZ76TEGWPVFvPZ65ggiuMv235
kBtv7b2ULT5ipo+jGdj7zeLMN5In3drVfejlLyiz1jE753uWpfrGWf2aGpcfxgOIYhuwrd9aBz7I
AJlpthPKUFh4adlPRPvfrS0UZauQlWE2/9zH4TfbaO4MaAPPM0qDRwbnlK648Fd8COVmjjEsFvqv
2odIbgkqQgJUybr9vXa8SmWQbE+VPAjDdqrpzN+C/ajN85Cynxo4FxJVsOmG2qteFuG8KU0plB74
0sHJFpCBMm6h3XttFDCU+z1Ehm5cfiWEI+lZQduafxcOiYvidh1lcmoZEd08FoRsQ6/z8G7rKkYS
sU5dvHiyo26iS7oPjbtmLJQ9RkLuutvCSl2cW3U0Dja9nRBFnCxB6VjmnLs1vwxOp88I+IgXqcM6
Lg1RmpYf8YQe5WkT2Yz5CZAr7We0eIu7dP8RbJIpNjF1LRlHcxwAA17Rr8309XjWbHI8bjJavEro
TrqVAJNBk/mqJQhp76ZDJsruF0LhenCB/ryuNV7jd2lscNldk8f8cscYfT6muEnFn/dn1/fWru01
sKm2YIshX97C9Sucan1iDlAWbYx/7VFI3MeBZFKs8geSxCh2I0uBxaR6lkQk87GBzOF7CBcHChRm
4p8r4iuZfdpYNLzb49wTcx8g8D8P4ejI0+qPe1byIN8yTLnfNHe+n5fhNUUFo4YbNQPV7epZi0eg
mdo4n3xonZhNLyg4XFHnRRMxUa/CPu+wqw4TLXkkNqu63MoZu4AjyqGlpvvFNSL3BuD241TnedT5
XCxBhkuy2yHQgBno2JGQXliDhUZB4mkJbYf8qyRl9Y65IqgOnWUrvKWiQSEBaBztwrC4D4T5uDB9
1tSdbdiCP3ghr3REsmohLXbf8aTwPxcqAltP4+09zSBv49qmccwxeLNrgnyO0IfYTr3Yc0VVsp93
2agbHLDW+h5HIv58tHEUzRBVWXLYDyCfUzY+8WDpMBnWO0ddOMhWBuw8OcxfgtvR2rfpuqIALcIL
IGc+IOxczLbpVYo/NYlxyZB+uCHSXKdLI1djJh4R7HrLC44z7UtDZsVlabok0bUzIm9lfNPW78mE
22nOkhotTmlugk/4BN0nLNjv2JqSeagKPJUKeJd3G59D40OQw43k0x+HRYOCGD+eSr0Lp2mhcup2
e93to1buNpWkZskuLZNnOX1tOe2L69k4snN77yZAFdd55PNggrkpp+A/ltHDc6oDiCmc46DbaNjj
nnYRmu4WzerhLgvpFpByYP6uXiEVIauntwb3hhMcaJKf2t1VzQLOf2ThGXhzZuspJ89Ytb4gHsGk
zhGhKAd7dnyNz1cWlCD0M9PwXWJAsGs1ryLDJsP4GvGY1BOvBMRGwTADTEXo5Nw924xG7QieYiyl
87qUUiPAizlK/kqLFA8/CyHIllXLlgjybNI5aIaDKw4+OilEA0kfT6rvJNNthDE2ooTTJdFkKXPV
xozbJFBSaS41v0eRIqs8HfaX/hz+2NE0iN1aR2PKmuIOXsRPDmhEorMs0QZNFVYxw2sKqJVVeya2
S8+YWZ5/4m7B9OPlJUZZ9+w9GvpfQMmBlnslL6rhGqadgxl5GOzIH8xfqhmOUc8vbMTTAnrbko9N
NcIvIzmwv8GXHXv8Yk4sNou0qLBM/S0DJN2LtNueZgjtzDGx3PSkPkORIy/fdtHySF1WIaFEbxWM
GeaQl08L6OCggFEFaAB8O9Hz+ESJxq5IG6LKM729dH3ycwG/SsW2m8euBghWHyTDtc94eaubFxc4
B5pT6Q/puOmvKfnmB+CRXoVOgfQonp/zSaw4aoNvbK/Pnd2GdgBzjl3gK5NBzS0dTiPVLB0aXQvH
ppTlTBTKipY0AB2s2Vy/Hkm1gne6yNKVzy0HcB4Hsj7hCQHI7pXeFQtqE4bJ9TK9KldnJ3/6Ezer
MGlfiKLyhvoqbYUJjqipyZUj25WLXo9uS2Hb7DUgK3Tec7z1tyvaiOZJVZ3ckFey+xxxKYLLXVD3
osimiQafaIdpxTcnMG7Q8pAnM7WcRCgS7Ha9O4sOyPAA5XLDrO9mxZAfjLrRMt+WpmzxlVYkSUtb
bKHUZgiGNuNEpBsbVVVQ3GWmK5hVkvzKpcfY79ZHKdAj57VKyEAyocIFoSBOGu3DXRkjKs1k96EA
S6MlfzZq2kstnUKN5J8tMXtsEXmldmk6y/79ir2M+TiZRPV+cCapva6DQhp1lx/F5ZDkq5j0rpYW
LxPwCvDZ2lbX5mwVxWr4J0p6E6waq2DQOury5z8nTR1oR4g33TNuGsaGDXdw3LmBkwpEKHmtULP/
Il4557HRkFG+1vlgfF3NDJkhVNmpKnAoPqziWahQ/NwTQu8GeOTmFE0ZU3MBe77KcK9AUey6cmDX
5iR+5uwi+cIkhXY9gG8gVu5f/c8AqTRuYJem7623NsIrj0Biu+rQuMPxES8kw3+xxf2oK0+5Sg7e
lh2Q2oHbSBySsyKl9vmPTPnp1L4QDRO/PnZwoeB6aj4Y2Fas9SQyP50vIYJXGqdsG1jvIjUzE8PK
Wyupp1KBka20QhUAWtFklTHVYYzZzBrfWQnOIUzqyj9ZwJlO85xuc6X4ecULUcsA+oq2kPSKpVMv
S6vtRE7xAzcG0bWXPSomBVkPyUpQRXHaAtUw5p/s2fd+PTyurGn+lduIe20Fu2Z+ygsoXHmyeEla
NvjNFCnjGSegbQZfcbGXIa3JiVzw4eaElRW4gOweydy2z4bWRVTGGqh2uVZnE0LaSHgWS4dOxVDG
FCsFqmTYdtL1cZnJqxOpprcD5gNEohq/DEcf1tDvKsAwbIGBwXYzje8BgDppDgGe+CwH5Jcal7Mn
N/L1IcLt+BGzEZ7FQHA4f2b4OJFyh/ZO/8Ro9IXi8HQ99unPVV8tMcaZKJZwB0ZQhrS7JUo+UWsf
qRttZaehFc9ydHWPVm60AXjIbTyLENtkw6URiESoQfXu5Y4D0DyHZiaNnGAeJgcpV9DWV38wBqdU
z27cezYkDijbn0Z73Y20LQV+/MsbTJ6ta/iXTSxhFSXV4JCmwxqTykoN9+8rDZZoM4vYu8a4/TAu
OVq+MqQ1r2ZG5Gf7UMaKu9ptjhzq1pp5HznvJMTc5y2F099OwCGVjNx70Obc7RUPe8DcSFGX7oID
zP6h0Rr627dcA8swpckTxaS5hJmQ3DOVGlE+rOoJ8BD1XafRMdpZ+bABSvkKLSJMuXZyYHbVc2gR
IhTfR89qnIe0wuxpiuRFlkSk5mb2efvxQMnkNS/MUmfPbmujR7pBCTGFneyuJM1WJdHEF/KxV1Mz
RCqCQzUAspZqfHEsQvNqSldFnNKoF2UOyf5Ku6NP3YtPa3Xviq+/UNY+Rlw9lkhf/jIGqibsCj8e
m1ebY93RaKKTJsmBcNKnh3nkrhqypRce3d+OX7rVnnsf0ae9CTxJUA8Xcsjc5DF0ohtK9StrEqvj
LXttVmYZjJBSamcyXy7CIcnMnT5ErK1cUp7p3GyBz0rvKRw+LuPmUkswLVsSxNv14784Xs61UMzJ
eqHtD+VaMaCPGAH24JQVGs9UF3X0XdODHdZMAjeWcekRgDZfRy5mzro0t52xgXYwSvTQpBbbBmqt
wZtFwBFD9+a+VqR4HtUFd6iQVU9JnpYaUmOaHA3oMImswNZcuidBpObdTC4ZyGqRZSaxbzHJOrqx
oAh1YYi2XOEztE1VxOolr6oZm8G6CoTuyPulTVBmiEp6HIq0WpYyAwTI/SUxlaYoAehiCAelne0W
mLDHkHA3ABngf3xugiLJcP82O/ptbCj213/czV7YkfyLzSosKz1U8CTXuuIhlbpq61gabbrajSVf
xuElqyS6XmFZgdZihNcsx3mJj3i20UJLHmNh2rYXamubvnYodBAWZVro45+7z/A5krtiPswxs8qR
9T6+TJOzXvxd+4aXO8+EI8BbTbzdkHHzhnMonq4YB367ArwhaLpCT0RmsloHXV9KuBdLUxRK7hn1
TgYGudARTVNLsGtnoxcmIJqGtf1J+2n20ZB6cT5zTVrsBhdAe9+2V7EBTWfyI6AuYeM6ldLzSD4U
3RH19HueRmxth/xYoQYqsUc9iH35QBn5dyyz29lioUnB6NPQ4K27atyStIuu7WDnCRqNxH4cT9dv
pv69TnBNKwUruCciAcdFKQb+nSf1MCjfK9Hp786aBBeftQwJ+Kywf+V57Z1TmmSO1qV/EIulb74D
1qS6vcFmIwL3cs8oKk7nED4Fp9STXHlAXCnayIuZRCyvfMpHtX7bBCpXwYinxXApdl1cZXCod2IL
2U0Pdb8GPMjSfsGhr4LNzV8m/z6Oi8a02BvXRGXkuLp1pcYwBypec9oSCX9P1GWsb07gBw9/qS6y
AMLQm0D1W8k9E4u65rwE1emd6sAA7sQMITlil12acAOHjL5fVz2DaeJWLysEr2+NwrRlKTbHlUJU
c8ugXijABJx5CesNS0SJDvTx6o4qinsGxL6+ivs9EiWTyRIzOZvKRatnmP2NAGYaLMGz/cJIQoCC
8lXT43jRNGfy0TNHzhPbloPIPick10fW/fbfEQ4RROH4qpkXAT+6wfycHevxzMSptLaOYjk1UbeN
WwZZoMNxSIQvpuHjUtiWkcvVtJ5ENKQilIMWwusLtRF8jDp58sdA2GFBDKRqIVLOUXtqvb+QUXOo
53/abJzr/s65zoX9zMMxn9ldGS4AECKSYwgcSbg6PkVQvdWyUiRk/h8KLzQxsps5ZPrg9m5KUhbU
swk/U2Mxhi5Ehzq44cGKuBgsuykW6dYSmpRKL9WUcYdEXwArNXuLz0wVPGikgd5WhJcLxXSmVmZK
GPI5TnVHsC+F5NdgmG+ZAztyMfEmd1JwPCX9ZUrMuI7CCUj2S806Z4Z6Hlfgt2xEtKm0Ugl1XY9g
vpqCOYNEllzYbnbPsaCHMt8A8a15cC/HELXUd8LNygJFw8HnDjahWwhC95o7hq8GrTp1aQsLwE+w
WN0of3wn7EbHuxQDuHO3mojnJDgGINYLDqJZiHJlSHWfzzIaWyhqTT4RqpOxg8RB2Q6Bfp74ZLbN
Y5q4rYB2TxHDMsjDJmaqTHKHFI48IBDvT3aJtncNd4aXYKKb1QF+BLyM8H26gGhfS3dmwXIqxxqs
NFG38QgCVwWr6VIR3dBozX9N4xiZkrX7h+JcCIt/FUrsA6CeJX/2pJbdoMhDujgyWrCDXjUXn0Mv
UFyOadyq0DIfmrRWgewHjeWEMdR3mlWomXBOKEh0PlHk7mOlc6dddaR5e10adx5sQkpKEPmhsZcf
jjm5r47zPERRLJ7VGRIER43MXL+j9AjYO6Jz2YQuMCSsPh0zruRYgVi5CWOBKOTxPyVXyDbwbP24
Myu2VHjWWlQcJ0ohres5FVzMFMikVeWhYQTD1WRmvYDb1ckVG9c/NvvrFzf07Vt+hj+wducefDjC
V1XUvsNL5QM15dE0hjuMqoc5tlhM1752Ov8QH/HsEJvpiuW+fpG1O4e6DTiTg0XN4w9gvM9p+oVu
qScs6f53ngh/p9oLsKBLoBLcxS+0ivgvv2IoXgPJp5SgN10w1IgWVy3EniacTBiyOWsWdkPFNF84
MJ36xXNTIU7AH9DFvnhvirP+vzX8hgsIqEkE0oH3gI07WdNNdtV2jYwnZAIs/uMWJm1n2zfa1qed
HjdgHC5vaiag01/9gZ5oUy8vXDqS1kMVy1NGH8bW2uWmqUTW+rnS3H4KU0Y6Wxk54KPK8dDCo83G
9GS3ed4niBKgnHLYFeIrGEon6KmaAVYP0ZIQs8Krgms3HeFvIclNM34SwSdPjqZVc6Ecz2YQNMer
RsqwTEck+XYWjSvhSeRJnZAJ7dQ/n+EMqPyQjHhFTcnjM+2MYVpCRPSVGXt3U6HUDqAQxN3+Oi0L
y4XvQy9ssyLoLdVdleRC7BOQOzXnkBbfHDjK9z64v/E/5S6sHTCvE4pveSIO4uk6PMsj0u0ZBFjK
dtwUvKPa0SNF9uOj7lN4ogCY3gYC5SB35dywSKSYC9h6cC7kyNYGaeuZVPB55wM7D0NnAHsWDxCd
u7ayrBlLY0KAMNQPsaxqHR3ItfZPXbmOuMHKhCxD/rJ4k9HAFW9eAC5weEM0am3IXHx9WDVhFecx
dSsUGzqN2xRcwUXF97f+hNGInABUpuJ+/Rlx3ka/sYsRPMcHwsumg95pcXwiWgTFXdjTgS+fIP7f
IH22fgWIrJGPbG9ftNum8CNJCT+hAPJqtCjvy3HtrjR2z7WkcfUnislZXL56iiEZY1iB92b8603g
Jdb5kP6IId192oVNogWcxyOv92cvZdTNfOd5zoASt8JlJaypEsGJjzCFTEm7/aZqpYTTxueWL33A
voBy2fthhoxPcdXjxwShRTpuxdg8nlWR3vTi7at2jaP/OG7uW9q3JkZpGEgAhyr+2kMVGS2nntAI
LFe/0/xSGUYhA23go0ZKieIjly5L7ZpfHDnpy0duvBHHl525hhwaGaie4zvRb2k96kI3CoKLtE6q
s+mlI6BehpNQ2aii6x5befLITXinFLyY191Y7BuQg7i8llzQQO9V8nJLWYzDr8Rc4suqTmBwQ4M1
6HnmAFmfeUKTeR+USIwm1ULuGPBst94YMmoaXUY/k7s+nBPo7jogyx1pCxQ5BCiFfR3Ug/I+0y3j
rdrXAThSGQz7moZWNLiTh4QIkDPoC7uBHmeJVe5sFYnBd6hPZAcgtGjN8YPPj84fnX7JNXqq9d+B
9GOSJBP3C8DnyjHH2KUfJOEhHg0O9MGjnBk3gDjQxEyFelasUuF1WqELrA53C0R2XzI11bd+2oUQ
PGHrqWXcb547PlRLnoRfcXEBtuOqpva2I4PzSlikIFaIek8+lL7AR9d9A6PDFVrcwHK/0Y4I9s6n
tGYxd9KqeadcJFELD3oioMmEuE5Y5btnNOwYCNFjrIbb1KHTc6Rg8PSDm/X1Hu0WlRfPeVWu/+kO
Nlh1GMpGQryzu7KupxLqqIaxNa8m3UuNvoexwPLYwjWd1ihN/H1U+77rkO9Kq17qWDYGSAb+AesR
gw9JU+bax+lId4zWbLVKBaF6/V3CWNmjvIpfHWw1L07lmg3OLqD2ZbZvR0xKy3sOlW5vgJGXZLJF
fpUxPaHtpXyFJ5HsghTpU9kPhYhEm99pYs9Srn6YSQw3PTRanM4q8w0yykGITF7LR0zyu5ZK+bzd
IQVpj9Cfz1hHuhIMEGaeCGRRiaD1/5CeEsVRbcx03pjHfXEVfKG5m4DfnjYPIFSDXZ6nTypPSgd4
fq9YDb3RH3OXly+wVlODDcKDyynvC2f22aifmrHPtuh+aGWTXShqMRNTum9b7QFVS1qwv5mRkjtt
dH2hpKfnjaaN85ei9YcJsBpcwc3SjWoK/Dr5GOOQgTLM2QyKc9b6Y/wbvPmkrgiv4b75t+AROZwc
HHMuQqdUUlT67P8bbbKHrTh2m2XwOgsBfDkEXz6yzMr+HBjj0hkKdo5hE2Bbu1/UOoyYcGIsCoLj
6e1Uvx8LsJ4KWa5z442mRMd6i5LKVj3rW78uB1MJy3wcAlvyeQQHCadP3rmNdDg5Kj2gJgbvSCq7
IUu5dSY5K9nf/n8cG8rgsEDE9evLMJnrK9GUNPgq8CmxuOQ0SqRsvRcDrC0H7MKhiu32zs+hh4Z5
m+oKE+yXXoytnz13IrqX6p/uWgeGV9D8PmZ1Fn7dR4lLt1E1ns3/lve3t1CxGVnNxczP9g1ApYpH
b/wNqb/o+/g5OdBLAxzHhF2HImH+dMvmZUEOO8Ad5a2+wsVNaLfoMdWDM80eqcaY9zAp/JwGarJQ
d0fefX/MO9RgZl8eCHrKgv/eOohQekvToh45eNQ6CITkmze4NsxTGpSoLsbMNx1siKxaJlVZW+bm
/wqTUxtkUpV6wD9DL/Ie8rCLeC66RMBrlIgUnFRXI/Om8quJVKEWjXtWEybWV8B0nPcIfmNuFuFt
+GaighWyJu55mud3EDDgXquXI9sgZTibmlDQ4+eSCcAvGFEPu+B4AEJB3xp388ocNOeUQUS+X262
ouTfr6PUvrrYIVg80kehoHvRzgwMErtpdMUDqi2ZdwNzg1pEzYkDid+SFCcuh1Zdvsc8BsnJ0GWs
ikitNbqGd8W33fU5wcGs/9iUSD5YieTI9C9HxtrRJSzGshwNeE4Dv8lXf2HTJgPhhXGNNs12NcDI
Q8P4HC4lGzAiNcKi4ZyQ/smqgULp1Rsh2yG2KpMfnTpz1CkwiQ9kcBBoAt8dErDHXQbkOZgxcnrU
0CqKbQ5rH8R1eIcw0sCjkgXo+jlTMOSh8K65csa9YfXfQebgLb84HN7NvG6jpGvsaVgPI2H9ynHs
AWiqxvbvDYP5HIScXIkEQFE2iTuUx3qv2V0b8TlMLmtHSu8RqyiXAnFgNWA3/UvKKVLAne7rgxID
zFCx//ERLy7aUkdzzCe/Rx5k6noSMYvl/GN8kSztOxlxo0CLxj66khk5ymzPs+uwUGbw1qryCys9
jBKs9qsls9L/F6J4Y9y/Sp4D6Mqpf3l8QdWmcnpyPyhqlLl0Ue+9kGOTWgcJ+Jg69DivdVLv10Ab
Cd4APD73053yTHGZ9TMAm5beQUGfD1/7+4SjOQjEv8TZ2AKkgZ7FSX8sWCi+AcJ5E8c3GnM2oEkT
JCvvPHGB2wE+qko7VPfLPn4NOLV6vkIC+EHsO7fBtwyPpRlSlevLm9h17R/TU7VP5vJkGKxVWnPV
kE2wHeSUqwOD2kDZ6cW0HpkSozkn1XlvLINSQ4DycXce5Xh7g8d3IS3Koe0wkRUMmcaAa3A+Nw5q
iJqgr6Ym5lsBKHnT+2gXDqh14CDf4pE+uBtcieeqo2LgeOdDDXvuBiSTwWMlDJocMwLNXvGdAVgS
l0pEWJDQDCr/HZuIkSvVjbpWe4nrYvI4PH19eZuZktcKaRmyNBPn12Ma+WAxDIKoVBlqk+PNKl/H
kH+7ydNkEn0oPPkcokHoY1PYAZExvDsmV3A4eFVuvgkruiXHLNkypKj/UOEWc105UW8V4sJaMltl
hXQze+jIDUpw9NB1U5gwkFWjyO/5wtV2Xwfo8pEfOhd+12fEJuH4utOQS6hLCOdDLzTZaJw6i7hs
lINZEUFwpnleNdX5emr63MWDxml0Gqr6EcybRBG0/0VY8Lymn4POlYBOWFS/cE0M3fCcOeJboKIO
ZHzl7JCeHcYhqwKZKcMe2CTE29w0+pXp7KkMKBJQqwTb06JHgrC7wi9Frxx1pJ/uWcN6kVqSjfsp
QY1TLuaZL4scUEn37f5zBvCJ5V/9wqPegPVWn4Ku74R+Rn54iVjNkxDPLO+UpuD19wXSUgjAzEJo
Pe8YNWHN4IkuI6ofclCv04xzOlC5dCRnUe440pbZVfJ7V+DWVs90NdnYqSpvkGHsiQjGM4VeZK+k
YijH+wzUaVu7HJfNyVQtDD7WEvYoTnI7Kkma9/puBybP2+Dtsi6/KP9RU45Hvo8MdHlhd1tY4kN9
Le2eX3MVr8HwgbUBNVxqGZR5e+MPo6NnXcEOqjDXSEdrC7fTnCgy2vkyLWHT5qZ3vpCFq5pmVEFo
cU0us7ELWeLfbluwi7tnGfl5tPgEtr6kAB9HiPaDoZRWuG04HjnYYKnGeS3xhkR3hDpum1cWq6Tq
w+TOFxWOEA4vfpbqXKde84VROmxcYpJsGCjK2FiPcUmw2FzFpPY/fksrR7m4xkW8GBRFbqGFW8ns
QvkswlkokT5boSfsiltaBRSEhlpb9k8gEKjNADiIM2ZAWcDZbzDAZ9Td9XrBo/zN9FO5l9bygJ0W
060RHjEZaIbyu6ssFjSraiO7s4XEvTrGC+YxHG4t1fCXtS3nx5B8JBnh8Q14ZeoTmV+bGBKiE9/h
bydceh6l+3ZQR0B87sBGQVm97Yxuof4voqq4RDD5kWDRtJG14d9mGEqQzkOXjEp0J6PZ7W6ul8yl
/SNCD8RVR1GJHsbnxVN6uKpWf/Eg2qi52/LIBfg4f2rTbOX83GPffJ9A6DOPTs9VHOhee6l1qz+B
SZloA/s1d4JxNgbi6iiG/NRc2NOYUhdojat89qbBOb+uB4n9ABlLXO2D98IbfbaienbPBPf3n+uZ
mrlhMlBcUlaJJFKLD0rd4ff+jKVYmbA/Ne7Xc2RIqQDHvTRQeVjY8YpUJWUVJKnDxtwO0/BZ0/Zt
KwaipXjaoAPXZveaSvMrndhLn6RThDjMwTt7zqlrsWuhCv8JRYy2riNGnEl1FmUUIe+ciydnY+/G
cqNBk6PgeOXSiLvTbrFHA2ZJF/nYbo9ZXPz1/8FFC4CrgpsZPPoHN/TlsucQeXlggrvAIJ95bkUd
8GshnN3CFqE9I3IAx1WFpT4OncoeQdYZB2T+DREmAWn8JBYRMwf45fw1L20eXMGDXW8MHaRkHvdw
nqkBci+3V1h1cq2mkuB9usDY3j6r9ZiSBeEYmXzQBDNzsEtjmmtFj4tHL8ig/6ZTHZ8k7EXhDCOj
GtALGaEuO3zAJfDE4lP/LR7EFJlepGgy61f+6wvgNZjWaS93qlPDnpKSeY1+8J+sn2VRcE9PLWew
hiFzkCFnhMAphsyhpTGvy08KhB9G2upq+bYgTlU8zzSSmKpkpnw394nGENvGosvlvTbA5jeks3y8
aMeH5D5xJ95h3zZZ7qRXw0VDpbtWA34rbKN0Hv5Zvw7/qfpH5jX5isfIQtJvYrWtiRiuqVSNEzXa
uhUtTs8g5sYxsUgeEtgilzWw1VmZtfcxhgv2DGDqfNO6rV7tCVs08uA6A3EVvhBnUlsklYd1ZMGz
rlx+2nT6eWxpCrfzfj1rln7dC3j+TlE5/ESeaQa30Db+I32a8FDrIe5/zLEFMwS0Y2DLvDzRHkaF
59s5zpJtO5wHezQNAoQFpSSNgotRWUo8ao6ElKv17Lvk+fUGDH10EJ8jjochPWQVR9fLbmc9gApZ
CdrZGXxzfiq9I2C+ADsIkB5ZxUZQiAUM5n4oGY1FqUtLwYlhFZSKL6AScoDkrG2fJRnxTdbz3sin
g8oJS4eugIdwHb0W/Oamw7pkhau962nAv8w8rkHANoOwXoriLitR3W+pKWV2SjlZ1LxxK8lvemY5
af77JkBu4pDWXODeKwljS/t8JpBGSPD1Qnu6A69FLbSN7Ml59OV9jcTOnBc7R4xRztLBzHenXVeT
x+L4+xILlDg/LGuUmPKUB2X5rTAq7ZCsFuuYqqOc37pBQtkI2/01l1O+0bsUmUWowY0MUB9gM/xo
fjoHsQnCKP8YVXMckz0i0xgquRm5nCThCA4Ke7wul3aF3c1Dq5QYKAEghz8x5zQtezZonz/6zOZ4
frznn17J+T1D6/lutSyFW3hzaMRrpaeiPrVLVyVcHDOVJl1VnKfc6l9Bsc/rKiUtpzYlDz+zvPTt
KRSFsdJ3hV/OEPyQk8Zp28Ay3to40Y/kXxuLrJs8JxUuW3oo2BIRwY9KswDOariPre82yD7SVqFl
xrz/n40W3nijAYiRk+7vbac2dwtb1HDdiw/BT9l8ikrRzf0h8gDjWxQ8XrbOwkd9J+QbmPHHl3Na
zSXxqdImqmJKxNKtGDvs3vkWij+Zj/SbaBI4wP+1ZfpuUPODuPvtWmuzGnEyP3YoO6U+f5em16CO
iCFattt+DhZ6t2bWOssuI/zjvItFVfX1/gTCOtv/2oTRrZ6aCQPCPpuiyIyz75bG1MiiBe2fOi4P
k53TlZZSr5PnU/v1Q1UT/QLaTEU+GsgLUfRIkjDrjbZm5fkXBCch9UUCv3jcXxWunNAv6DGEYxtF
Fs2g8SJ1f3iBoG7M8UTvcd7H8HQbxsnD3v6zN9oa/RaM4GE/XTHmXQvfMArpQF5tjXNPS5S7lbmO
D2zJU6OnZu/XQTpNA2lGZkV2tDXeCiw/W29sRpaDYb4iFnNYg0uVXHLszQbsxeo48MgWUWpFMkKG
BupZ0CI6peYp2xxkMIyi7+sKuR0RUVAgM3fYCCjCh0DMo9hriKbgcrIcdR7PLai2cdfq48FHUE1O
qOjl17mG30PZHVu9eoFm5BB1eXjEQWTpFEDaYC6FGoOAfaOFgjZ09F9pOvWAMKTR1LrbSD0L9ZJr
5N1HI5hLxOd6rvslxtXcJPKNUyufisKLeO2yA/ysj5FtQ+qh8B+p6KJHSxJ0WsrVtAFgPWKd9UzG
JcYCoHDZ9PDDK+bZsqil+ZtOVlhpG/Px82jFj0dxFvEHMYhMNRhFIAVkoCv/dhDbSZuSCihVZaKJ
yHz6AxK3shbXIDgI1hOlKMTBIJ3+iKcW8wRLRe9PZOgp3a5O6w5aM1ZcYjyhwMVVc6fAlFya6suf
bgO68cA+KZuAHd+YoXUSrp2KIljmsGmlJ67rAlVJusVS4P+8+iNS/hnDuwtzf2AwcgrV2NNDxOBw
j7RigMiH2lel5+/+gC9yzlt6sLauPmZtuZ9b3iblpc6JOCfowJLGZEd8Fnly1vD9MF8m+8vcHcX9
IIic98omcmrESSpcaWCIcGzmfC5QQbh9oiGYAiD5SrfE/s4luC7KRoRseC+mi7UO4gXOGt79cbnC
cHFXEOkV73XAquxm/Kh7HB1x9k5BWB9ZwstpNTj/uibo7fhfTt22qjUSPYG8jnnxW2zGv9zdXdIC
aQd2XXPsCi8BR0DSGWYHMA2xFJ9Q2xhcjhzaG08bpCchXULGJTGtclrOmtRWBHRtGrpMXFI6tvs0
5bBpUxI5GPR6FOGBoKW6JMy0HGKH8mtvFM5ZRJfpiEGchtjlJiFF+OWu7W/T3Esn+tLv6NHaAKaO
CA0Z0mevGMi3wwFbksEiqCw1FR0mjrPOQ8SRx6GIKB75Xe6ztzkmA4Dw8yJyku49M9nu+L6mTKMU
LJ2Y+WH5CxdOfNB9n4oCGxrsZtvQLcDgkyWV723DJQjeylC7J8VCEiQllzwnURhHPZLSTwwd3Axj
L74LUKDSNWVflFOkzaNg2F44TKbG/yyKow5atzLk3GRtITK/RVRLgGujzQENKO8vqCjj81oBkd6j
skKQpH0jsxynpVakJkPf9ztfwX1MlMuHtZ/hqOq2TnW7d66Nr1o6tHfIIreEUCXr/VoLaBDVIOuN
JYF8JXJM4yL3jtkHVDCDxGqdNyIrbvgenuMFc5pr2w5DlYqLMVdS+4ZkolbpleDiMlstrw00zWTY
PUZiRZNPU42Zty1ivm56AUkSkNyL9UHR6tMca1Qc+moc4ZVIt0fUvxQm0hndYS8nI6fpPpa+2G+Z
fyC3MECf89vF9PuQtFVNvy9XqnuRBLLdq8GHQg4Y5xNRrRj3jLR235vlPkcAJ0SjzLAxmCfydheP
nnZxUtqaD4X1XKmkEN++8bDwkiLxFoVOICjfKL7P1kcjYHs9U9AiAftb1K8A3kO2BNaV8r5OJ2S1
uCgHPTAVKgPBreD1qE9Y7TRv1lIM5NaA26jGynjqGHwWln4wQi9DB8iEqi6UQ3VJvb+0i2kpj1pa
Kxg6wiyLtv0RP4KbFTVoslj1w8yjJg0wEqoc45+M70IzaysmTCguo+ZX7Gg1+hzyjvw2GN4NpeDr
WfRK1nkbfHpChkc4kl6LaRHxJYfyXwD/iB7JMIikghPv72BJuzmKZjD26o+leLyKlGJZ2XLqnQ2p
6T8sgoqsmYueUEcz3jdOiVtXhlSelRSRlOpW9PxDNzGpjsK2129aB9ggtCHjTRCqhTxYgAxjVhWW
8r0eFwRKEES+34bbRiA17G7kZKNU8eF2x1j3P5Ze8AHfp1ETV/05clkHvCNkYnPYMjwkKiEcx5dC
ibYu+XrFMoAiv2Hp0isPHlhYIRFH1OdQEdMOlAOSn8deidaMOfP08m4XlPqIuN+CgosszSyh5gD5
kr1J4YqLKDf2DYggEwdZZypwdkHniiv6wfc73zSgUAUKpWa3qL6oPFBT4WqNqGCagkd80y4635z4
bH5BV2qyhSQLNGB3HSS4RIfl/ltdlzbj9v7/Hy34sn/HZyJsNhZlpSimSZCMegxYmoshZZdHlkMG
zsZVb285nhW81XRtygX7xyOZhvTSdWyuqUrygXZ+j7ea+IEJS3WHWd8rMwmX8aYNBDmGmlLl3OfR
1QVTheObOAFMEFVJUXmIbCW+Z2hR2YiEDMcyLG2mALnmiKDxcUZewoikpSfDK1NuIpga24EiRqig
nvsM6zz3anLtzQ24SGvngg90cOwuqYUzwODs1JXO/UmKgyQNnHjFP6Q9FAqPLyqRobRDBeSPuJ1f
dQgAjaaLSomgAW5u+HQ7YlDbfXZmEN3jqoyk/ZA9c4umby42eNGvlwWUMcEJHj4V4jF1ZANKcEQt
2Ah36JoriVzBIukipoBNvmQ9iTTWFJiDf5ygo2QPNxwF/ets/kXk97ww7xhZEngGk2V6HWKmpQVT
UViLjh8Ndr62YQfYkXtH5HNl8hQXsjpdUdjqdciSJoFbeZo6tyGRnf6Kgi04PICkjYcFSawgyho6
YAyZ8DePhlookH5CMXMnOHKXaZ9PDvKGfMelz5QmLfYnK0eEn+WC9lG2o0ds1SzsYU7ykquzSfN4
4FKsHIRVOqAOUWp4dSZSS7nonBeKxy0S1Efa1KG4PXcQ3o2M6a+WHKleVmf64nixYZ1bCmEA7Lb/
U22k09GR14L2O0/dgfrXvTMAQ5x5SuN790HviOS828uP5YSiLoFzrl/gRImHEzesnXLqpJkxYikb
HIiaWVqAqaV++3ealRoqw5rk4LheDxL15yJxDCX9+mnVlIlNp10RFArS/Gvvb/mLqHOjQCEjdXwc
+nIY4rJTwimFGWg/UeY0q2RybR8EL6/AAmDNptKs0BwVP5BSBIEEUfZZb9oh2ZVT/3vyzoHhb4cJ
UU2nGvK8Ze14/BO9E6DzU3MJ9V6QimXrTLbahfLpThnmtAONf3WtVxKii+H8c4NeiBmD5t098/06
/3AlStUMharR9vXb2ysVTinmPBG04o214LAQhi5chNznwMBZs2xnqNVahFn7kUI/176+cVJLMjL+
mQ+pMZqCvNJIdCFYa0Up80lmzy1Kvx3S2qVHIC+smtPckHBTtymzJtMqvgoutLblehTkr9VDxWTW
2FzJSFe6i6ud1Ks4MbDMBYp9BAw+e0rA9V+RGYvnVaDm1tbRCZRTS7LWsvA10MfpcsXPI1uPNS1S
otlDdvn6lkkwXU0PjVrpDO/fsGB+oRA3zu60I8rUNaPc8Y3/x4AKeHgGP+55KWXa0Ijps/bQtMgU
xRcD6leAr/ej7TbjIK/lIVfcncD/SJCdYKaG7zb8BnakKPWLDYCpCGGO/2cW9jv5WgcDeSybO0qa
tQLq8TUNiSzPR2QokXhE72s3bwhbijxUMDv9eMLltm8VUeeyZRs3v5W8SlsIXxMANc2R80ILp+4V
VwMl66CWGKk+iRmYMA1qC5jmwQfTnut2YI3ZcGYuqyHprazNRr4muT6Tb+HwFb2Odpu2AFe8WLem
IFfPmEXIVHRqMlmMPZaqDuchIBo9Qip134y1sPqqijHbS8QeM8bsKJDPZLl0/LObaokfAhn3bIjC
KXEOZZyLVzWDyXOTG4/S28UX/IymQkQtrchAa4MAGvkG4hVwpnkJ4Ws6uB7v1QUPuwcRbXw+HPE0
O9oZUEX0GhbdvsKCeW8Gh85U14ql5C9spwH156xgscVM0rLpNjiUCvXo8py86o628QV9hfU7dPRB
tPo2obolMpWJsKuMxYSGHH7ey2b7lhvoERtMRtGBpt0J/nzwtdKcgd1f940UsCUeQkBXk0FH6Qbt
kbtV+5kyKK15FqScqnQU5dPkPv2JPUjj+zSiwHiTZ/mTH6luIC8MwdGVEacLPxUJTjZ3lCJF79tH
w9bNbUxMSxTrKwIhSImdHcQKqsrmRNJWKINeyhgmzcqM7zFjXS8aik9pFDk8bk18lzKfOpwxHwSt
6iABG35XFbVpAcbQ4mI76mEtQaIOp6uRvjrtLDZPj5eYnHF1j58hn6xdKyXWCjymf+8eoGshU3t7
wa51CKUWqr5xMZEwhcfCfdW6PTURUBikmR/VvHR0ArJ8XK/Xucy1nj3jXrA/GqKKVliR68CC1fEA
ViTBVKqwXg009AnLhTkUFD3xzjBdmGfybm9C0vqAkxtHmms2laiLoc9E4+FLkf6OK86TFuUyI+is
+7XSVFevBRiJrGBOsayAqvOeKg3wcBaIzL88HJkA/Ls+j2tt6PthTmzeTuQTeEgHhqVwb88eRBwy
xNBZLfgARUBmMQt5Wt2xCAAkYwFNMyUFLopZtSnEWTWGVVxxT9IVINFX3S+wDJAjpc5e6nsoTgTh
sC2DW0Uvg+WSgvwJ+cStLhYuMOQa54LQQQzlAbE8wIhFzc2Aq2ehqBTaJCPUwaH/NoKC4V8cFORS
DEOpSUJzEmAQOOvp8TKFj6iZ36GWuhLetIenFZiRh/KPjkDofO4stPeIruF1vtEk7dkBPr7N3Ew4
9zsJx7JQqYOSzmSUYemQpMwFOsQwN8mTGEqYS0MVEWuJYqKgO3Ge92Aaqq3BTcHS6uX4S8SgLmlp
arHKzh3zM9l4sXwOdUqjZKMMz/jOYjt2ySTeVRdM3J90nE11KmmQGKgSLT+7tD2mkev3ivvaYlJk
Tffn+JuSzEGY3/py8MobWelNMZNYHZa8jN5yADpR2WuLHi13Rtg1tkqr5XGx7B/HW8wVrGAm5v2O
iACHKGAuSs6L+MA3e7QirsLdi9hbZzXFmQgxmiwVuHVJ1va29Tm7KOrU6u6QdogzR2wRaKkJRlU0
dmXY7YXpY7qiJ+3BBSHaKAQpXIotqZXJm9PF/cdX0BBY6Nru5PjxZ67TinIAnzENgi7IsPRuJ+cr
tMZQFE5UVKT/tGhb3/xcS4nOD42zB9lizjxeGp7YASRA7CZLldvs910MyEbo+siwQnZk5hRW+Gnq
j/iUgRgSylJE6WjpkPsYar/SSBtBAZVydm0uBAKuGijmhYN0ilz4wI/TiEIRJ1eSj8nka4Ycbkjj
ZFj7FS08fjE51DQDsS7U5Uf7J1Tz9Vx40prxxPQ1j3mnQivgXwCW4PAud1Ka24Nzar94wOz1BNq8
eiV1c8ZNoJJc9At4QeiKj3ZWr7/xpojGAaUMxYsJ3j193/SFLclEpJWwBxJQUKNWh0fDkryDvQZc
ByWZr8jG8dw6ykSgR/RbZvc9GBvfj/fqhOnw4DADOxBxImBdHjAS+Fe27kYXI854hIHf0pWKZtQf
tb5tqHn0gS2tkXq95AIBp/cQs+LYqjWgSA9Z8hB6AYh78RxhzL01RkmyFqRkbI6K42LmVoAoLRXH
i/23lnkiUir/vbO/ujR5CXanKCWD0IdSldXreGXBPE5R9p3pFeBe4FrXsQE8QqU3m4356LqGG+FC
eknB+1F2Bmsj1TDPR9UVzt6sw8eA/4RLxXM3xsZLIO0DzddC6UrrKeuU24z2tU/ArEESNhULA8EU
sA1Pq/j0ef3IJk4XzoMF/EQ/5y/JZj5Io+PADT+6zdz8vkAC9g5G8P6VjOuNb51h1wMTVb6cpXZP
3AfqsTcJTHhOL6Z9gPJp0MoudRiWprbpQwaeEutrmMZtWGdg6czpwfkBOBLwUr6717O/6gH8jyDg
/z+ibpDaGVhujYb8xv3x4ht+Pm92vjVxKK9hmGqeCBFiXa7WDBIOpax/iT8K8y5Ae3jrvB/w9zne
VjY4asxAxbpImv8+gEk1rRM+aeyQlcadZc04JCGCv6wN4q+Bkc1gIYDR5gk+ChMVj7bahZ9dEGCq
HWDRJEcg7kdE8f7sOGR1KOojmoDmf/ZKGJdK2EojdJnpQDfRoFMyW0225cXqqYao8XI5NrLMph0z
8CQx2rJyxJUAw4FKdLJzkze8lhjyh1SwSFs5q5nkxbbPsPM5BwaD3bHuvzgv2+6ua8Hld736/eD2
C3Py1ei1d3NQIsM7zad53GmQKHkl6Gdnn5YOqXBrF4G3nK8HK/Zvy/NO4xNunHhdDGi/FU0UlHH2
IUXcdEON7eUgKvPSbiL5jB0/aWFZns0Y0RNEQkRyhCbRtbTBcV/3BdStrC9FbMSm0U8y7g7BV7qi
1vL3nKZuX4QxG5iqEmKieNZ3ZTjaih1eezKMgCNdqVzjTWg0AuvT43hqvQcmvj92cfJ6SNq3JRp7
bLSA3Cq3HyYocQSX57sgaar3CdArQywnWGdxQ2ShDeDzOif3aaE+iYyLRbhKsI2YSzICZuPrQG6t
4ot5jyrkZNWFuM7JEBI1pV1UmKe9Arh8zcIfBs50wAJrDJkLoIlBkYSUSPRcTabAbhbi92rvENYS
mBj/phes1eXAMK0nhq1A+UcxbNX6fdvPhNwtO5y2ApqzO4mzjQoxqBAnY5dMVfB1Zxu9vDL4ZcnO
ApKLQQ+mL+31DP6mqZPvH/ZWPcRXbTVYqippO0jYCQBZJMrKpPxLgQZbt1ExzNVYNwcQb2TI75nQ
slGvl0TDR5gItBZhpLpvtfvR/JGtPjZrkZpSatOi+uGPYsNGC/D/3HBEhSTBIOxrINBTGbjxFt2C
LHoadyyrQxB2zyLVBxGT4NpNCXzQri3Ay+ixLvyIM64pz4wAzvWvuq5WccX9wLdJyTHr7W+f7OvL
iJ7I/n/l34Rv1I9KmyPI8Y4wRHTMxptwpUbXKOq6HndDAKk2wTlhEtwRTA8wJ+kBVfxPJ0tQXly0
WujqQhOY1gsYcfL2ijM48tf6827w190SH0pvtoXh3VsLbWenVmYLRpy9vtWZS0mFHjQzcOFZz/U1
2qSUWbL7GDOOM6D9Mbbc3d46yROBG7pF2JwdvO8U8EUYL/YvgcNdaBWpRvXXP3e2vq0CwJHSK1R8
yPO6zBowXtbRaGSKK6dgn5oRDBdYHMiMiSvOxn2PWz5swk9vcJkUtYv6jJRdxTChB/T4ExdPgu6R
WRa8jyYnVQUdekA2zn6Z9/YcabqdpsZH8A3XadO/LW8PZAReqEeU0TipxF7Zlb7UD112WmzxgTHp
0sDTkCjpmlljLnlbPEKSfpcDNl6RvR38GpixIpyTKAl0h+yINM+OdNcDl9dACLnHX/67AyDPjr3b
6NYLMPnhGmMRvtwneyndKY0ZEzzLYWHhPthCh04Rzj2n+QhuelFkNnPdm4NIg3wIV9eHUHDhGkKJ
HAComoCtci5KpFV3fd7g4JMZh+0XCIMgEyQ8c583aRu23wLwz7YVVBPdABx84Ruu/McqiUdPBVLe
9j6xltC/dMjxU4F4wuHiKBZzLZ9WiryeYU2MPlsc5V+XkhniztaicjmlkGRrLffJi9HTHJAEXSuq
hZBfEWmrQL0lP8iTzFHHUFeXYIvKE2vnsJR1t5BzHf6ZES6XH3pHYbYR7xpXSn0K3uH8sQeG9GUj
FCXktjHYa7CUzD1yZYLYktVTiaoVnIr5YZKDZhRW7MKpCRpuM7ChcB1bPYTvHd/nuwlxxmOw9PHD
7NGQg0Bn8l7CTudOdIt02jyPK6ygwpGU+M2+RH2NgWChCZLEpu9m7tMmdmhKW91Z1ePKyXeIhH6U
Ie4HZhtRhQebVqMubE86rkq1xj43gsXJYzfcDEUtdk9CjUZi4KNtP5SaOk+wX1iSsxazKO2miAKZ
9zC+EarXNyCyavwO2FZ2bqCJcyWgRUT7a4fFvLuj7oQOw9TfQj/MTMUoetJ4QEcMdaxIY7h8dciY
pSaCseVBB77HaeSu0ZpyqYlSepEKz+3horcG2mCey+7dpv2HRHaQxxc/79Stczvkf2z1EMfIOrTv
ITWkTVKP9bvyJ20cOChsxJoP/dtq41y1tzJmxK8ANjQJnR7YNuH680mxhynERwxyxbKSWm+CGyrl
KC5H/MDt6PnGyXc1OMkOoNxBuMcNrLFJRwOs566FxyxPBBwBZKz9pCRmHbYzqguPcgyDtnc1VXno
IaADgUZ5WbweeoWYRSnH4ZdWgDrqkHkp26P+8/B27x7MH7nRSzFwYQI/dBus/ZD7e4AVs2EhD+28
H/05/osi1Pfb2xns1tDfCS3C0iTJg6pmSPVo49mcNrNjxFj871GLh2qBKm+FSUT5/96BC+gUPBx+
p+TEsZ7VQ62M9LNrWEBfmWj2M02FFtWqCVkpZXiclCMKFbRf/whsnYkYZnqvHrV3Jw4V7VOJ5q4w
NTiJRRKcEyhfmZpaIcc6YIaRrp3CZshV+MoewWtCrkQfxZnJinFy9OOqQBNd/96tBiUJufXlb5O5
mHDxmdM83QRsfT806CiSovBtrv3jsiJ37jFFU/TuT8UTHzqJbA5ruUa5YRY/QghEOdw3cQ2bI2G1
Uh8hOxEyg/gusnZEcA8ExPn9D1x9IYOPMexOMZr6s1nK6sk10+gmVHV5G7arCwDc37UCyJAz1HV8
YT3jPSwSgXpm0vFfbSqt2S3Zco/sDh0sTCXtSH7/LSXLA5M/FKucmwXrjuaDEnmDN268MWX/30k0
NB7smsq0hImaqBWej8yyLeBWhLt44Ah0oOqhZF/+RhfWOnRPluXfsCjErfsHZ7P5krdaNGaxyHZg
YS2DEvkcGD5EOyxK6waOqjrlocYuHtCCzEZnseeAq1p4na2kEBr1XKZPxHdnl8GL6smI4CQHE9Ie
8QeEnmRdsMyph6XVwlOiAloWnfisw/FMzzuEdpU4nW7PZ9fdcdZ/PclPxDgf0UxgcPBCmGO8i/F0
zSUULu2claNtSeMDr8Vvv0Wev8caIfT3P4yQQaCNwZ3UFMrmGMIKHdt9SS2ZCYke81nFv10jDmyw
/nEX+/SO7UZVCnbHEKfhXLMJcDX0pkJfxgGZxYhZUXjyAMTVA5i4OFp+QuxEvskVSxHzJjio9crO
QQIAJNIWwzZ+Ayk2/5+LQAShRYDKBa5ZesMBJ6CcxW+AL2fwBVS2AZxDEdgq3YBo107OA+Dp7xMb
JkQYHVBuQOGmh7/gya84mntEfW5p4/eAgeaJ/xR1lb0/x6Z/JW1foU9yBT5iQLZe5XDbYN2ysp+G
xHsFdwgvdpM6Fou3/Xxoq7O2nEoNwrm7jE7WygRVVtR+bOWw7GYIFjnHGsnllqghKZtb8WQjUEN2
wr47saf+8FGDfm73rGtSdW1d95yj36rhHLlcMfEnFMWReCh8JbIHRJCMlmCdRpDuforB9rCfN0f3
LXElhJHZvVNu+PYs1+OLnS4JwHJVkm7sC6ZSD9S+NncPZ1T+ADbzBZ+evNIl+zPuMSfgkICX1iPZ
Jk7k9Yb9YmyqF8gCTr3u+MjEihRSA15tWH2gyDTRDPUBA076EAaE+LrPuJ4eyFTT5eKTFkQ0JQI4
xE95MLfs9P8a/cziEKxbcl0pXnABbtq1L1Ban9Y5rgdL8nTXbR/u9Se5i/aS3LVdEr+JAj5yCsXk
7VT0zOsgnBOr0+hPwx9RqY5AhFbc0SPdeQYRbA/RDgzltz+Uop8Iw/DKLNSzIxHNXe+5gArYZuy+
gAVcKIwkFebK2rBg5+FleiVlaj17ZqI0WaaMX/fbGHMHYFAY5qAywCwKZiK7phfQsbTMGt9DgXhM
CNEIn78hTvmCe90eEgedIC+3j6rABJDOhd4OMHjkIiq1wdURGvNAxJU5ovPTgWPILHGdBA2jC0Xo
2TlLxBmeqi105x8deCpC6ncdhgz2XBggcqwZXgucTp4lzXUBbyBmxfAg3zl78B6ZMeB0mtSRy8cY
9c5GrwJWmUfmzKg7PX8LKh/P6YkJVoA+ytdlmx3Tk5nBXiBTmCZOv08lBMlI9HwlduRUs92THNH3
vlFSQv7zT5iPr5FQcmi2tKNegfHtFYaZ79mwlicsHxCMAaNXE/sIUnrGBMi98kRTkFekhxr7yq1h
sW0vJt3eDHk8EIu5rmTjaXIEReYZZU7VrwDa3gQbWpt7rhdjMxe5tuhZ7qUzjJDxFakyHAN8Wq5f
/FvtEkTWJEtE6zi7mm16NGJ/Rqk62TCTAWT/4DU+MjVoroEimgRfV57KqJnffFe+dnMpih+IBRYv
PKU8AL3ZL1mUtIhnmKWliyzlt6eM7R7+tWJNro+4UH81Btayg6jMy7Lqipp1kTxCp/QzW8hQiFw+
9sX8tu7P5kDnV3mDAvL1LV/LYKAHyPUkksLEjWEtvHXQ8beKMjP4ma6/OtYZrB4GA3hDxLdEfx5j
nPUkpsp2iWcUbJ+dRyIPGIteYqPi6x8N/PRCevYNYsnx6gccV09LEWik/fU0NNr3i9n26bD9X1+s
amD2xuqoOQVw4gFcEyN955gYwEqj3cogdb2EeplwJcQqfVhHJ8pxF4a7kVx8NEaNg9tiSJbclwci
kwbPG1MnVQAfBYMkuCJG+5pm9kx4c2vkbdt6vapBh9Aj4MQ+O4aZ8G/vTNdfBzF41qwaJnpraND5
d7wmoDB7xvCJsdEreCZdKys8FqgM6pMi3iBSyLtLHOqACZjByq8x7MSW/4RvL6njS0NQKWZzWIBo
eC5Q2urhE4FnXWt05Ce46cCYHEbXoK+CdzQRqrq2zxIwhcaZmzUzEOOf2l+cZtNcJXKfUMKSpheg
hdzdH2ya1EME/xOn+LSKGag/23nFwDBATsoe8fUgGfV5/4eCuAD609SYFUEhDFCZJe25lJemAxba
7lOEDHSqzZJteVxYDBvOZbGeyOivCCKn8FLe4p5QwoaazQCTNEKUHeDTMp/32NW/qCC7i1MFsDRA
BOcCZoacQmyo1n8Elvmc7qBbzn2lTJb3mIQh2hFUs9/n+MSpcfOCrmOK70XT+LhEtSRxM+gc5Vdf
eQGBLNywAE0rKJj+uKade4tiG1PAWKyh7z5pPvTWT4BmFUWonE/M9PQQwkDKTthFeduaLgH9iiwa
InLIYHqjXa/O6rhfUqDCTMLRg9r/Duz+Qg3onT8SxM5Hr/e6SEKUzrqytPnR4ynkjcROOKOv6HzA
ZC152JknN2xrWYewIBF5JpwCaUEqhugDg8F1IoMiJ14w9Y4kQxtPJA7Xk53ITBj19+miqTyMokG+
kg+JSEOZzKB5dRKmFcGeKL+sIfsw2/86LB11Zg5grfVhvA+4Wjz49eSY/ZS7QBjSaFTJF+6nd/Wa
HdvBbKP1YUfkO/pf1RAHGlZNJcj394P4C3sjzWM+Bex1zyfiE3NL0MfTFDHSsdDlx1oQwAy5FkKB
f8FXIeiTjgdQEj4u57sjN0Xqn1sOqYMaF+4/OPreF2mG2trdOD4ftzICHCMy2w90ioGGLoAJTJuq
11hATo5Gzi0s4a6GGWXbqH4/T3BHDwJQLctK4GVk7czCDJ+OvcWlRBRuWgtuEpZwCIuYoGgI0+cM
6ABi138+vsO6CdFfANMZSaepO9rnHx6OsH4cV7Zz7o01B0GomexCIBZKpDdOuzL4DfMnAWMw6uC7
oE51RoQicBVQ5/6azypr1229KbWRO9s0duWLn0Md2Bq1CH+aJ3gRoByOUwydP7iHos7jM4G4joJh
lCfJC8pRp987mGbySdaWrzt3DsuY69Zq+1nfRys5S01D2iVBu+diAyGgO6aVTBeye9VsKwFp9BRt
0Ola34WeDggRjXPaLfYNI3t+Y/XWZdYEPwUgEHB0kB6N5okLqIUNFSE9bR24rFSyZ/7/IeEPPGBr
laqUZ/LUXyLQfmiFlfq4rkXSgoFiXtG00idVhJ6WXnhrRi0iJyTsDNB3bEhHgEIR/qnlXjib/ScP
3bgb6E4TDfPi2BWrsS7x927a8ujU9V7HxTJw4lw7bILygrFGWeW7DJr1SNOX8zDPrQFnKSe3tT5c
gJIMVMlORcUz+BdVAfgzuC/iZbQhF4lDH6NQj7RPgGbOtYW2M0mb/upSUNwBJ7+3Qmo7Yb16SNrd
rn0FV+1vPNncz6WhkKh2cTSKwALfB2HovcYRkWGH9z0lMlQPGYeHGsk82FYnrLEBL64dBRuT6U/8
dK1D5w2DYwVTVI70T1lVuCAtUgJPLgVcmKzBsRRRyx08REhYQtQFXFpU76jqzhjAF70WzyTDkegO
6xFdq5YXayP527tyhlUraFlYlv5JdJK2F3YPjFMxuQ9O7lCm7FEyAjQLhv+W6aEoxR0EBsYiTgH1
O8fgdk/8h+w+VAEvWVkgfVBdQ4GngiyPKq+WDIV4uQUF2KLlHURaq7u2vDXaZplJBIKsxlG0lV4I
BQqaCPaPQneSF86N1CRoAUrOSAshg+Mzgf6h9uvRmXwuY+n78Y/tSeE6FIzlI/jPb2OmwIcPMvl5
0MvC+gpeDatmPQQv5bUPiDEIm2fsNSdS3AwIyCcLn5ine5LDyho5L8UEhC/swEDgI+UFj6svE7gG
p4xKPJ9Qv+o83A8DdXtiW7wMWM11G+YYsB/joCsBcMy7roweP/PEXC6lOVa74aJddnEc17SuqKJ2
0NyuZEyWPUsLpArzZKKD+mvkjqt42erLXidrTtk0wR3aO/4kJfhzP9VZS0R8aKRbd+meJjQ4Y0tQ
Er95XiYDrm4mwZIPzHFeHteU6VQ/ds3uiDRnPzeXwbww+BenFRqGr7AK6JhylAdfnmuZNm0T5bkq
G1i3KNLPXPwpCA4yC/tH+ZJ2rNXwGQT4hiopJkf73kgST7vI9iywN2OWGEPYYlGp1Dv/j5RtABYR
62mlGFgcGdz9Mq3qSWjjg3ycr8JL0LJa0Xw9IXOR71d95yq1gHv/OwQBzrxE9n1g+O3BbjWYrCxe
fia5SWoGceZIZRcUWlBADsBEvCO+75hGIDzQ7n6x+Db8gMYDWjTkaCq3ITWC/gZ+YM+68X6rSkMX
AJe/B5zYwjV2LnAwlBGJuUaZoIePEp62lYHrHLHmFJHXrdoPvmEVVpljowTyRqgfILtYBCKC6Llm
qz+XGVxzk/dMH7n5NRz4GI8Xxony8jqM44UCN9YlUPlTZwvzGiikLJ0rFaue7pHE+Mm9kMP5zUa7
8CS22ibhUvNPkyPP1SC7CQm9YAbPlT80ziSF6CjezR4lVkPWUytVQ1pKQp6NblqwJCIC7yyu19lY
pCPBfYzWeh/c5ojZUt/xSVT/CTctwIICyIRlAEGp38lhZeLXA6jFJNlo0ISEovHhHHfwYQtkI2p6
wgOUn5ALNQo75/vmh0esXN57ZUh/kOhcqvOmvIayDmoDHLjhN+XFeECAM2MRBinQimRlwo+8ic0W
nsE6oy4orxDb6zKguiDOsiIGO3p5QiNP6CDdTAx3x3+FVXhlz3rZzVtcM1MWmvaVz273XgOYok2p
edKS8tyKdVOyn9AKnR3sTdUbmJ8KjnsVydvBVw4qfO9feXnEGHyBMbXJr3yYUKTqGleowOogK1bu
mIy5miaIRqTA61KeHIc5D6tb9X8UktP/pd+5jEst7nPUD0f3FLYIcNWcOSBMqnMeKDw2eBx5Oo9j
MXty5J4F14asaUMNQMChgEH7UBd2TMLw4VopxBWZSRlsINAG20F4AD3MNauYAM07e/DfHbkYrdDD
pV1gkPZXnYQ/qU0Dnb+uVOZwYFSxNUljvzwSxtjuiQ2xjrwyQRFO45jSenTC4dHEVvu+w8XSJ/TY
ZWa50wCMyQj7WNLtyp4lNWzMhfKd7Gt3zbvy+uTeFEYIrIYgvez/yfPo24YpnE6K1TRRb1aLkZZt
1VPR4MF2QL4ipC8hxAX7m9u2XHCCHccbiOIis8sm493qnUGsQ67kxL8yA9uN5TO+X43f7ewbZhiP
WTBBxk9tSDIE5uJ4zP3Ugvv67KiP+XXd5kNE8DlghaBYfB5U5f5bYcKzOWH77R4iM3sX3GvcfIEb
YVLbp5n1spvsrzKEvbjHTlOg7+d3T7MOBa//sqe5vldL80b7D++gG/rvyMeDAH3u3rH5+gKu+V6x
brbkzleCYETNEp3q88xZWecoOi2Vg2IRTpZWIQHtMH2P9tFkf9288vuFfTasjz+4ryxViXj1S1BT
bpHaHrcqm/P6ovNlBjSDnTKnQd3hmy4IqapEmJEtZLV1L0n7dFIzVEd0a0cOdbwPwyNY/EelxGi2
GAfHXGVxXRsgUX8rOizQWuulHXJVLDH3UsOCo/2cStnK0fboQL8KavRFQ3c8//v5SYUUz4Ch4LmB
pBmR5uLOxybiBLR9k9mHpMx3TnCMJsqAWqncgWqg+9oh2b/FiXXANC61LRfam8hD5RfdI6HJlvSl
i13HX7kdHdDY/bSRj/rRcgR1lu9NqG8Vy3zbmqgc2stxpCMQLyH8MHD0Sp4w2KCXJADRfh9cfcoj
0yRhkzLhffxFxmZ+MdZdtMz9fae+PTTD+9EN/nAuxBEclLpkEkMNk7o7FzoiRC38yc2qeMJe+izL
PUjJ2MNHjqsA+AiyYJojzh/bi0r7y1jSQEqul6iUXdPslNtIVAP8tuSE4K/9bK7vmKIzsLBmepCj
ZkKDPUhhbeVfOpMA1LV7xwalgXlrOIHyCMJttmhK1/IB6rpwsQyRIXqKve8npVqVYZ8v3BluDoDK
m7LzFTcpzWAWzBXoc7fEm8z4M77eIJjlG4AXGtbFrrOmVhH/q9iCJ3ejjffvOAKgh9ua4I+pxFpT
m45IpPFCdQWHKlgxfjsKzboWJTX5xP1k9vIXdqqoYRxkAtoLk5lZJUuICBBHVYKrcR+cQxkq0Ksy
hS6QaTE1CeGcN8PH6s1uC7CTkK5Qt0AKFy90SMYILB8OtpajOUSLia/PRDvtfewBxXyfz/iUH0df
4+32Ai3x8mQ/JDVVaxNbnezAFmxdUnjY/n267JhNF3tm6bx+Tf5rxzUmJUOD7lnjah6QkLv8svog
QUqMiRswqwsAeOkvWzvFjD0nOTofNdVG+s5Hm4tK7iKzn6aS56g7e6IHxpzGG/FZ7HoBywZkfDRL
H2qI8v+Z42zpNj8VHROXC51qojiZmtcAt6CIT0bJifPlM5nAi1LxdyLuZxavCWP9wP/GsBaKJPbR
BOcYxzCdA9HZLvwfYnYwINQAcDxf9BvxrKt6B7zEFlXoCP1bfgVcj2AfLTFluj0TZlJirISuhn1n
P7TlABqhPe3tJQqJPYEFhiFalwG40TX+eCaVrhK74bC7fQ3uaOWaorLsjzQ9fgFbbwwyd68d694F
vDGGqI2gem+mTvfpmGULYpry51//17O6VBX1CpTqm+diVFskaGwYqwxfSwyeoNs0NHncY0ZjMdMK
bfrAD2JnZ31tScTVYF6YVnSjy/p2gGiHR2b5nxUS2Lav4SjzoK4jvzVFICE6UMrDygIBGZIn6PBr
yBtITb9UzsT6QilR7058w6jL/U5l0UKNG+7ROE9CAiUc/P2aF1TyP39DlmyCR9k2rJRSu4vwpog9
hlpUZCa91yVqPj8qjcmzUE5VyWDl9PMB1MD6yTYvD+UULCRFxY2OT2cYeans6lr3vKMQQ1NPlXx+
x/VMojZp1+ShaSpV9fftSaX5E6hxQsxGcjcAkIF7d19kNHhVNgaFIZipLecipVaAqVitTANEO3J8
kulZlYwd0WGoxRzjXepzEXx/wlVWo1Li8k3xwZSnRZX0PvCDdALOiHyRug3N3rtXXGimynb+QgfS
ttn66jWbuI4gRwZUCNgD8CYMhTgWkNAJsoaKgHdsZa0xicMxhqm3flWqFe+9/VHETzvTSy+DhN3F
NkL7pYKfk2z7SM2D+sdN1nLDRCNui7hSuW7nlPJyUXtGADIsE6Cbo5TkE+U9/vt1poEM1o4Iej0n
rlHvXRh13lcEVwpLS62gXqGgCPJLOsxPhYcwVC+EfCUxsUvHCaEwPOV4L5zWvH4y19mVdDRoOpdQ
0e5CbkXm+933X2KogjEpEABlpEcSkgBJ7R1pj2iiis/wf/Brb/NjBpb2kt4LY/Pbcm3mxRS2CvAQ
DIX+6Jy5k5opU9JokAGMekVNgABrD7o9K1P7FYHyQjvbPNjKMnEDozQDfgmWft36g4kaHUzjH5CV
7f5VjpwiaAolf6Am6tjjf93g7R3BUr8enbPvi4rW2U+VAPjJvDwrBd1ZRtmkKo8NV4KmQLi10bKd
EVrR9WSF9aZdQEv6yL7cUdSRLYSxh93hVoIWEv2w26OGLvC7tPXxtj2Xxfd+7RoTO28Ooa7Sy7pn
kFGYrhfrwaM07r6YdeYE6q3NtL2mGFyjRb4mSKB2sZbRBBZPadKNsV3udkewtOqK112C9iUl1YMJ
wszepCzXy89zO+18t7G/HlYMVA/Awe7psc+yakFvuD/FzYOoL2SZQ9RKf4eEPKS2boivDAwIPb4g
q1miBip+TyKDN2EsHz5bLdYcwbJCS8eQ4fOjeTg4xu2uwgyeoISJ5FCIBlaXSbnNN17tF0NNNC3O
OEESFmcuSrG9LUKPjWgKWqX3hgfW8mqI2ozkf1nsBnDmmQRTVBUOr+rhcg1a4pecoORp5bs0oKn3
EtcIVYTetrM6R5lkpnDSoZz4YpAxih7JmUxsgu6ia2HnHtWpgyRShUwwRFrDws91XIURIFVpODbL
gwpVS0okehJFk36jnoWn2xPbuFUBLwFA+oECS6/wXi3xkELUnVWOjfVs92DyHIFSLKtafotUZDR3
fwna8lHrZFHPVQQ5TBF/hrUn0m2eztZ9P2AoCx6mHRg8IW6s9nBG3SzYcqsRGcTd3VfVCbCgPAhM
mm8ocndQSHO1hQ1BYsj/d6c7XLvJHCJgo9oN8U/nXXuSFpT56zTaG7JV9dmmEcdI04xCMvrqYzmN
0zTt10s8FjcXaVrBZIUznLqHGTEj22LtRRQKXQr3nRN1Fbrc1UpgyfjptsXvWH8v7PeRToxVVY6d
Us/DDJdjV81rIp4cFr4q8s/2LHTVDn//Jfb/EtMSzGDuWVxn6KU46o61nE73I/HBTT5rriHsPsse
Uuv/7RlOBEer2mqVhJ1WJFR6TlYDWIHXTXbZOk80YNBS+tAlZzsrK4z4Y5mL/IRItf0UjZ18zm3k
0yy3+NpyqC/G8I8i5V+oQxvH6KGoXmOzLdlYWQ2ogrMED2LDO9121JCKDnX+xdB35WTh8ugypfoj
QDuQZdFuvoM9oyrCUw5EDubrOMX7f2Ngz2+8ZSRWU5kpwKXUMtAmcLssUCKZXj/7zrtxa20xrWSb
+o8US6h+phl4MSSv+FEYT5DcGeEJhaM5uhlgkJ31FjGYH2WhtlpK8Q3f5AYYI0cjPEflIDgpiUzc
NQOfQ1+LyzBAiRMqkmkc3o6wSjBgm20HRrTOSLWH1Bt2lSWsFiyMfzhOpj2JF2d6DQZMGNpwwVUm
9Xo9Hf8lZR+VR5pC7n4BHDalZVi8qchdZcMhQyh3968UqpTGOZfFsDuPgDh+GgwastzII/6nCYCv
w0fngQkz9SHkSY25WMJthPoFRGEo8hwEsQcDMf55QYVndee37JTS7spISJ3lVnU0ia5qpoes1K95
ggjL9RgxfS79oFVPK27+pv4OdjqGpymDrhObiG3Jpys3CZFi31TRaSRt1+VIK7VO9LVjwEUXUrPB
q8QdyNp6NWNIjMvFOGqyzTfJdve3c44PxIr5Qod0MwJGobIyyoJIDgZrjAHFWf5dFUqIYfhZgcmF
Bidt2bVPRmWX2FFMe75eqYlk0/498dYfA5mYy1fhg3JxMvJFl2Pf6SY1+fxMMOteLQ5ohHJgpB0j
d7iPnW17pA/WfGF7/pPYeReeqa9DlIEKprymubqcz0NsCR2e9CJyACEyeJM34ljiv0nSgyI6Csyw
VOd4FdeucGG0k9sVBs5f2N+hAGRK+Wy0ZmJJ6XtU49jo/x5SUXldF5gReQ6q368dReQUC/2Vkqan
4bgC1ghQ9V0EhBkFONwP15RUqhkv1WEvfd0yJK91/OSkIDY5Kx/wz4sPRy/NJTInbf0w/5B81+xK
iPdJRR2MYRtZ2vXg6m16EahAlnIPFO0zkbYoozG1ygS7d4SqYC76LFd7CaR7YWG4CSG5y5awqPP3
x8mS/SFbWufQ/eZZJsblxBuZ1FUU0M7UN/JH4JdcLWn5EVLNpReDFYyd0RjqESvoLRyU3zxEGWUN
1muxYNFga7a43UK5t4zX5/piqz5Lcx5+ZFJKOGdgVSjDYim5afrp4pWi/iQJs9KGMKVFsYkqX99H
bRPen6L1hd4TAqqtk6eFMfyazS1fd7vuPUR6uiX+hCTd0bQzvP3hD8o8tz+C7djE7dSHhArFibnI
zcSQijGIzDsfi7wFuaRHb0cNa1bp0fTLmsNfnXG71j9AIME1yCDgwFxs6I9Q7IBhCW0fyDF6Mc7U
xcw0Gm66yRXnf9XhnTZXqjvENAgpCIySlGDjF/oHimMObS6unFcD5qk+L6nrqmAVGmX4d3U16bKu
7NcV2HBArN6/5jUdYOCMvuPUET6lhtPFqW2ua+2gmwMXhHaDwnGjj6ZJmOU30CaTE9EGt6/qN9im
jXfoVieKntnMNVqXYzyWBIN9/7DMbRVcHeCjFghfQt+8nJolb0cn6q+ltXIYNBlYScDopqvGs7LT
dZF8tQmn6IZx8V5DlD5MH3o7x1btSnr43j6If6p8rNzgGhIrRD3P2PQ/VWMJCl5Cp+F1lsla+M00
gGdAK/DsKcCLEUlnHBhus+qDUABWOBzd/IFuDE4yn+pKXlo5+NgbhZQBAsR0rhXaZqeFUtCETb7o
aWF2YC7hjYF9WxniooD1TSbPQSRKOMcJ8atOSZfvsvoJ1R6hHs0KwQxP9zdYt26E9MeHelmpU6/E
fjcfVEM3bgEdppvYXxGyoJdsRwcRT69OxYh97BvP6XC9du706hlONIwgSyCQGBV3jxwoPjgSCcsh
IklpKZ+/fvDfyS1TcuA//S5Nfngdx7lsL3uO8yIWMLs2Fvngyl03s8wz5BOQqL47l9o1SQuLJe3j
nUgZHGHuPwZ/sJsBWJNFw51uXivqo+f3hPK80Qy1I0gW+aZe2fS435jUlJbZWc6KJQYm3+3nEmYz
CBnZ+bOQ2BHLiKfd06qm71UhZeSgcahMOy2qFI9Wh0R3W7xhE5zwRizM1o6e+8piRTB51beJN9Sd
b1VLfCLbaC5mknYr3InIZSKiHMAYocNeVIz+NnDh1ErdB3UHOXms3kHFl9bEPxhEfUO+QzEUgMPZ
JdboMif0sm7O1q8erkgef8VgvpzAcUKetrTDqfUgogJfhV2iQL45ROT3vTOPuEB+AHEypKzLrd1F
Am+hhln4n+isu92ID1HK/Tzm6kSqoC47VL2vNsdieMHO8of9AZ0rfaGfg1JWmQ+cFRryt7ekmbgq
Rj3PHylb9F3Hrt5Vsa0lQD5rri3idleINXWDaWT3tzEK3dnmW/NOjBVBGfzBjZhspuOJH2EEKR4o
sH6H4Bde7rvE9eMxVS35RDeLh6GjN4dxKmBD+ZqcoWm8YM5Wc6+wa7WzRYSkcwaOUsmhKJJ9QYYE
+L+gs3JPra/2qy7xlh34nW3YEaCpJYIDOEdJhh9GcWLHCLsVnpbz8+eXlDt2Xtgz53WnadrB9nXE
K7QxwccbIUDv8hIJGSFtfo+/lAdGKScQQAq+vkDSSTd5c678vUBn6UuEZXNCn/HO0Qzpqnmp5fKl
sdL6jtgowVcnF/gLh96lV6ZR4Tj95da9zMBdzr8jEwv/Y4IJj+Z7Fzyd3rKqAfwl+LMKup3+dJmU
Hz8SNLtUNM3jYYHrIlfIRjVp++bp1s6Dlq28u6tsG0FDHR0iY3vZU+5aGEoCr/xHvmYkRLqxgL/t
7KIO5qwullQxoqmaaGy6aF/xk/OaZctDZ77uk1DioYUvNp/r52CiK0VUqp0OYz/aMlisuMWWiW/d
hgTVdSyQi21h7MY//66zamh2BF9KvuyZpst5NpXT4aQANAKMWiA1EdaUCQEAzWU5nRoRa3/s5DsL
mCt1k77uL3pAqCdwKItSNqHdqqsYRf3OtNpfCfq+iF3ZN7+kuaQjf6YMjK+jbiBWFZPK+AuMGzVP
DKdvdi/dLIV7u/38ochaN7SvmMPLr232o1BoRnacD45Z7Sk3o0SHI0XrE366HKa82xVLfZybKTiM
54lFppu592UCczLwcHoGkmb8Noy9KJmCxP7WzmDbQUNiA/HETn3dCXcYl7vjs7+3++3OSUA7Qshq
oR0l69aK8/T+uTPFLTsZMtALBkOgyQZMrhTkn8YVM+MDJAnKqk5foiDt2h61+AldC5dGyadWnsEf
uIGjhWzzj4SVPBJLKINSwwVvLPTGZpONjioE5KdTJnjJC5fmVajvtBXvFzHW11CGXJW1FNbxfsgf
s8p4ExVq8ccdSF5CQmIdiT8yxD/uWJXmAgqhcniBLAa0Skj2fqEz6okf8b4pjWxtRVnu7/nvXOGR
zLFpgIm5WH9UJvDm/dHGeSuIODRhtUckr0WYhyW5k0dPS1fNwkTGOkOsVCsEDcmiHdDm8KHeSSlj
xhj//7KwNxEp0c6C3zPPs//FgTIDnznd88C1kkQOCu1TYM57xggAgb1mx4/pAxKH12yYDB1E0KOo
tfNOj6aWk1CXL36umTUfP/Jrt8Wj244bExV05f3yDofqaPgnvhXvBzFPw+IYZz7eF+TBcn8PsefZ
WtQORcVF9z9znvK41Clk8psH4mX4PJElPyNzYsCmy4hPgydSyspG5tI5uWSSN3uSe9VOqWR6P7hx
IfIUXYDmRpODKZeRAlwtcKVABL7i7NFKlsReS9n7J8xLX2mmDJ58W8vLkMKDhIpDsxE3I9r/Rhqg
Xi/7exuynZjifsF/x2C6IRIarUa//RYPTL6yKyp/NSAX9mWTBh2NFcdux6ZpUfPN5sojBGh7HS54
EXVjVvQ23FPUeeve3IBFtdvDm8cOtre6I7xY+YToS18E1gWj4EAkU2IwhLeuAvMQkThMFxykITXa
NrqJKcHXxCaZwgZZPwDev+ZeUFdVmg46TxqPKOy0ht1KH4Uk8Wyvl9sC+7EfA7MIYM3ef+t68FBJ
l8BQukuo0+G2haitke8kAPI7ID9cmfJGWIpvZCy8IB3OVuEIGu3yuFWMCDjQSy3/PZy2X7fdhRzb
4NLA1HMhyoHSawfhfk/fLlEJh9DGxvnJWghKab68ChB3O4NhwF627qUccxuaMlOPrFnNsEE/vosm
zlSPnogI1//qUKiMgvFx67QH4yUcGRokH1rPXrlQ7eb1iq2J8JFLOfe47f+rALxUxfiB3J9U3RiH
DOvNvdfCSAt5QXQMyj/ESByyMPnXNLmSdBcihfLibL9Nw/drLN3umxGHDAiocuptqRVuhVvnvzfb
49TR5cG+UbhDzBu9F4maKi+NfZFptKqlKDtuIohLoUK5s8x1aqun9lwlH1DhVgJ+wLmR3JjrcRlo
OaIuwwfroDqiK45tYiT1hBeYkH1qLcX8x2FeGYkq5vJLrjP87du/Kr7TS4GuAYGTKosdMPSwMARM
T2btHWtOGvxthHoJc4Lym/EWbkWVR2dOF0xfPSqLj5RSnO2/dvcv8OQnYRvKWjH/AmGphKs1zwFJ
+bOlTEyxY3sDgrdDnNKCWXak8dbKl9gucATWcGuWiJUfELkO1IJzJv37GWvf+kUAz2DDOI1BhH/A
HUx7XD7CnHgRd6mr5tNeNQW3u1cZxH5LVpWajdphrBJYL3vQ6wBikS58uMCBPI18wMKn4YnHrsqi
d7MRaHUSZi0EZx+opVav24ehRFGqveGL4zBw7tv4IYwp/1Su3NgD43fGy8tyGku5/vNzzcFf6rwg
NOxcq9/h69rPfhO1V2lpHjQjjMwSg76GvcTWJ4WbCTr6Dyi0pJJjUS4O7L+D2GRQXJfAmdlswxTW
Kzga60BxkTECWDppECZYdFXBEthhU5ZSmoeIj+nYFPkyqDBJECKx5n0nrVxlJSsfK0mp5tegbs/U
abfMzsByQbHNUEe77FG9d4BjvnXZN8fKGMg4YPAcDdDWS7ifCyOAyVH6Uk7Angh3jhjwYnngAEw0
t/hwUyMAvVOgSIX020OjiwoRetZQOMLDlbSv3SbaGgjpyiy+pMjYW8WOf8ELpNgyOza4+wPbOSv5
gneQ4eIyvH2EKItBcFWa08zcxl4bdg7PURMMoPewlWbUwln6IhxfzIxCA8vOuCxPmoWpSHhcvqq6
fCu2o79LfPUczZYMZrsFlx9AAASZnZPnnwXsYIrrKmoHHzFTuMYJxxOKc4kZRN3OyS6hKbPV11hl
IGsqApg7kl36pw/1B5p1rocd55WA8CVfzXCbhCLpbLascrENdTfi4zZbVLWLIc4NhvwUxXvxNp5O
A04TZ84PcPoVxnsJQ3+0TBp5fZf4c8mNaRA6ooPoP3kHAASBRmN2pk7KACzA8PvBidWS/59vHMhA
+4PafdD5583oMKETnkavNqiN1C5XZ4yY0XoRWHY4GgV8S1FkiAIppHTiH/0M7C0H33VqvV9IBJOq
vHzPlKalPDhLGGZ2eS39G5yWvBEamK2nhKYWuBR6YIzv09mf10djsoUTp5vYju/JdYcvu+ACypvq
pBRA/2pPKlShDtM/vuYfWV8rlwFeuGV0qnzID2mGNKmhrR0G6Av2orzRGBqGGs6KAb5dBgxhF9VJ
+ngZb3mGypkF2oEsryyZOpC7b+XWZ1DeniLVkJpKNFIT7vdLiRqYR2F5caAEo6B1DLKdaSs3ztX2
H8/Dkn4ZiJedn6EmO9zBhC1CYWJcozdZzeT98XvqALjrx3b83MM4Ir6ge9u99gghE3XE3b55gM4i
/Ijw+TJ40E/JcYnREI0JY3AWe0w1aNo0+Ckdd2uG3w5r0R2BEroCa7YKQ7SWjXgmg0d7YkeQEaoe
cxuIbMGJTiQ516Dm3N5nCP2Q3czUe6PfSAX1faNyS9VGwe1Sz45PjyCR9opNTFzWRDOX7q6n6hs0
cYoUAeIOjvWrcMst/wmj4vv8o7VMGIJBCo/YPbA6/hpnVFK00jpJueZ7SMvWlcHR0JvEq4q46rLW
fO40H8C3AccYHTBhkocTIFCD/LHM73PS8psMg1+zFPlFxWO07a85sfRq+GWr7Yi04tas0+324dkT
gR8Wn/gquFDckDywC15yHvNVSnrv/EvMsBzPAu0zGsGkVdo5VHWkPB5z1ErREwSx4uQMAA1gIPAg
t/ACxxhC/wLNe9kZ5iN0emVp66xvvV7PSb92jNwLStA9Mqbs7vc3ZkERcWwO8td+rq26kwj0z4be
eBt8KzKaIH+4HWzWt316Stt0fXyPbW1uTFV2sc4yXoKvG6DlkMxXzs/m0cyDtuFYUl3S5tzCxIRp
KE6Qh7b/dSPXNXK4iex1ttUMqwPY/7h/WNg9C3ZP6DjtpL8+eG4u0EGlMUiYdf6R1/t7EqEE4NK2
1Qzma2HxAzil7GrnUfynfdnDZM5TuDZYafHrBTLxgwmIgieWNv3c3yfo0zJr2N2RIwlJ5yKb0hd5
1wRFybfHqsbL01V2hOl3P/xdsPQ3j3spUwsFYS92xDuJBdwZmAR+wmBbzFss174KcMyc9m1ADacn
HkpnaUTgIN490uUrzYKpddh3E1UzJP94QIiyzI9fKSdgwLod6gLXmLnNHTp1tSEecjOoMIEapO7J
8zClL+7532D3xzPYLwB7nxq8ASzqx7X7Wkdf9sMNlhmhLNoEyuvyjWvDceT6IEG5/DOL6/YVetMm
6jgulfEnUc3ymmRuKJ8+acIFItmKwMaIJW6ZoLb+s1hy3UFtyCgEuDPnXQdIz41+KtgCosyMWiNB
JLjeP64jPqExdZFTCNFCEnnwDh3Ha/aE1XzS6jWMTPaIMK14nMvoMnoOKk4WgqReTlPap63aC0pQ
ttINxgzcPo8DYH+lXiby1VVP3snyvd161rnUV7M8KZqPMHxgNB7D/j3JizAlv1FEszYCgVaYx89r
lkXThPwRx9OwfgMa0lwM89tKEP+wNBNjyFNzwmIuJ49KumxpK3uSAHw4sFT0WWl12iJt+OG+rxzF
ROI8XP3c5ZJjmJnSmSzHIeFv1NefDY6HhsIEaX3PBzQKj2I6mrlpqtRTkZ65sj7WUvBtYc8UEW3e
lETz7k/o40qqiCRk3QZqXL/ZvCYQKYyKu4qnjF0gd2yNjufecVN7kKxkUM6mdHGcOcwU1FdW2csl
5y1mIGqi90m8I5AtUVrY58b78TGmpAuIlsMvZQnD99Qrte4n0ru2/N1SIc56u8Z0692Yg+6lcowa
MdFRX3pcVr/dMUX7ZvcdwW0mjYGaObWmtKFPEMJP8UuKjQyLc8oN29MMNiyIU28iV/YizZTKk4mt
Ai24Zi7r13sqmlzWUUlRRMim/Mq4W/bHDW9VAcF+WJmelhP3arFGR5PgAfgAu9nELyIfr6McfcU6
a7O0MyNGzUiKj7pWjaYFw/e6w8XvsArxtnH0/5SPnRO6z8qp3BUJU1sLYTT7fuFQPUQdRWrAfEud
pCiuXmnZu3OfjM1avNwbGumTRXvFXF9UvBVDIYf/O4CrvebII1eaAwEzqGM6F0pJYmLVVaHJNcDL
zVN+Qb4ac/AfIskEDzdpovQbXj91RGoicDVRX5lqFOWFBVi0CW6kDxS2klSM9FJSlRWfQ/qwC0b0
huRIhkPhHvr17dUmCv/wwTzuzaod019ahsjGFD62Jw7BuSqiaBxOrcvSZKxrvHT2xhJztfZVSdAM
VsERJv+R6FIX/meJ2gzHctY7ToGFCAqJ/9gDqlGJY6EEdvdkmE/akHTbJ6pJ+aqmmPKDwSYIgtBn
cCOYdwIeRUDlVqXNvzRRxbE3Bf9TZXn1NTjku5WE/uNF9d5/rng2AIqrZR2zILTYl9GQI4dOhbPC
ZoKXr2wULSI7lRriV4fKBqNM+lbIT1Jlkk2PaGTCOKu4xbmJPFTTzlVJ7FesA9VmmNVQsI91lqeI
MGJvcRho4kvZjRY6MYDgh/3m1s+7IopUJlEB6nsqU+/cyVT24zQoJcHEWNC+VFXB3WUUrSJb7uGW
06IYmNbZxBCq91GoooA6ZiP8B4rrcUwlM/UcJWs52jLlu8aIsTt4wE4K8BHB8r24AG8hDjDhuSxA
GXpmijhVRMNy1NUo8QcUzSZqirpVUeyD10lkhGQP4qJ1QV7iJ7PP66UH+2rW9MwnkXKHkb/1lsaE
n9W/nsOZMPBT1Y6sMDwHeccyyR1BG7tlB/6sLEWKl8AIsuy22XvmIl6hCyZ3npBATGkpmxyM3JxH
c5E8pu+2tPAKoCLqI9RzQL7BXbH1/5fjAa7qMSRdroQYuFasSmx9zawDiuWEHRIUOnrkbCKlxFou
/Z9jCSEHw7dCfdpgwcdC0jC6RU9MpwvfvotboRI+CzXvyxhcZjI8WzDQ0CX+7RhXjmxB3NTf67QR
1ucntA6P8tBNvFmNOxszp1ncoaa287/S6LRBSmt/vn8EuNvfsqrfmAVBOVLvCLYTviYXfVBqB9P9
6IE+eyeE0D0UlNkrDDjXkCwOuCHjlzSrIrEQiNIfWEPBqhRMRnZOqtp1COYCOrGGR2qvI9gRiUx+
Mi7koSh0z1NcPo24n14xoquHFdPsi2Ws/TtySqmkk9dCOAl2CYfk5vQfRqxpui+bwvSikuy8WmSs
D08xaPVsObStjINXsB5iWp0Ih1WlW9HPL+aGMM6CIh6/NH3D003p8L/V+Muj0uTO1hMuc9kVSDIT
Tk5QxwKh7iF9vcR05kvmcLRaiHGuEKeosWa+z6IsMzye8+bp3X2TVnCfCVxi3wongNcBO04uYi0D
EGKon4mW4Ojwg7xROOQMSsqAq2l12/uQwocSjI6LulV9IJXklaKXDPy1akzDrzRmM9PXBuWeJzUS
+XHGJk9JwAPC4TpBsj9961cdpUvnWVt6Mta7TkjkN9UwgbFJprwI4kXpRA0fWM6Jn/kdfvri0w9g
tSXb5nUIucGwAsF+7x0TJ+mKbR03iQRxSr2kw96+klsfACsZyVZ0STqI3p7R61EkT580KmJeoig8
uWKzoixn0V56JtMa2tTSJEK31V3qQ4acpg/Ga3Y1B7uQ2oToiPyQ1pMH+m3gMLVvclrymCNVmmsd
s/UrfvTZaBMce2GKa7pwCxLCzXd1TMvPxeHVANCM684wi9NTG+blgNg6SkmFn29IXf1dLBi7HeLt
fuS03SncLiYQkAXQp7XLl3BdoUXq514EMSXs+rNktP2cC2i+4MaEwfClMYBu4VzO96plcaTAbU8w
TtiX3P6ae9jdrZQ1M7xTVAXX8Vyrt84loPfJhUcJ6Tt+cfkBYzrXzhMwc0vs/3Czjolgz08/UAhY
sqJ8c7bSvUxZgoMilOQVvwEyP+Qkh6IMJWYbv7amaNLk8f6L8g77oVH6u/KcCkl4VlK+JGg8bznu
jQr4kTpVOZhmZ2PJsvW54CF6leFaEOELFxC2fk4Le8N0JMgyamyEbW5xDisifNGH381lxNBaUH77
ZtwRoW0pQBoQ/sWnst2BIMN5Np6DlvZvxZpb172tJyvckq41eJNpXrP3hAiXNQyslE6pUmTPtCrJ
GxqJW+ETDwp1QuvwKLG59b159aqEEFk6jO4LVChM1175a3tRQB3hzgAa/OVp8uNwQrsdHN1orFet
z7JSRyuTEa9ERnbINEAp7aspE5KJJoI0MnIYMLwe4iFTWbbHaKpalwtcvacKvDR2GtvuZrDzSwCb
TKo1shC5epUwJRfyM5k7gGg+e8Gmos662UFUrJEGHGKKaOGj6TYIRsBKQRIw7T6SCd542Hr5ORXK
EI2kTLSSYsNfBCIblXa62djJT4HjgAdoaSk/rGFdj0LzQl5OKFsiVh0py13q+PdmLtcpvbmhs7J6
HZry+z7rN3BoKL4nhgT91HmPkGZghJzv+oOBx+kovG4JtZC9C1DhdzDt2E52AfDnp1eRbCenaWYN
U4cwCqzCtdDwbKBHiH5CPI/kAvgthIYUBNq/NQSfSwvCxB7wNMvF4cLlw6u3SSPcsdS8xzqTSHxR
sVZuZ5pl1dmkMofyZOXjwZD4IEiTCn3NHbC8SdE5rAmCamcoYQXBzksda9aLg3jICzCWoNAcrckY
jexEs0Dnm/TPTelpVkznm848aM4sKJa4NJfIvwT5dvWdelrH+G64tjLWsuoOxH0keWSKFVCNFTUc
9D+vzaLiYInm/TqW+dOngNaJTHjNlvf8E6BgNDY7+EQB6qgRDaNphbJQiCZyxpNdpTsmCVmM7qFl
3bf5te76lTz5m5D+06ZyjC/xwwhtrumzLmk5NUqopK13RCb/ugYdNi4beMwWcuNj/jhB0eqhkqwN
ABXsIGHiYDQ3wx06QJ6myDyFdLgMeBxspKS1oWZe+SWzSwNCpy8xXm4RUL51gu0m8HgivWXunJhL
pWfzGo70vnzQpBDoFEtVO48YRyQv74DMpGoT2Q93pLW8B44kALL4XxYc7XSZNC77K0wNFwf+vb0h
Fpx4RpYEeB3YhF3Vhj1hvjIq7iEpVDBEM2ujYe9d2ItsOrkqNrSroN0BSBq82wmYhSIsiqWvkP5q
2lU7kBa0gUmVWQxKSsyrlLniZDJXf4HLOz8wbeHTJmukzIsabuxWT9gBjOzBMDRzN8rbcZlJFC0R
UU23vT7d8E0X8JJYMy0I1mYQu3QmO8cwpcieNiY+3gFGBQNReK3ozcZShkoxMHRWuq4Ff7zI7l0y
+fpL6bpUQvP8KwzpOMgKwLvvNn9sEPmBTBixfQjRcW8VZLgMPA4OI0f6pcrbLzIMnsP8iury4aPg
CrsVFTYXODSD8lklbzM5b8y5DOuVtwP/rxI+kkAaABO6xC6+5ZR66gUYZCgeqOuYwunJdsiLLh50
TzwGp1jX1kAgbof+h5H27FZtqKHU8JZZTafH+6ahc6GEmJxMzWsScgY+JqrkTfeW+FhihIhTmwjr
RwEjnYWW/MYIhkORIb35OiR+mtfBYrGJX8RcMIEa8dMe+XIfTSTJcknf9bIk561mjr+Ir4Ayg07O
Au03Hph2369D/PoirNx0N2qUo5xcWxQOqkPyl8tdWN707zXOGSc/a0YAzJXjEX5/j0I/QQmjhMkL
ecnQFICbA+i0O7fPi+bvir3cXHBT7TtqMEXU+0umDbYllIjl1hux4xVlKEIlUKWjcH6PLo/eFafh
dRxZemOQtsgBfNHND+Or/z1t//8hSp/jHw8KH5h3EehziGqnOUSKFc1DSYpt8Iji68xQh3h2OiWf
zqw86I+JutMx5NNb6gJrGurk9ZjC0xwno1imTxeOSxe/o6/X5ZrHD7/AgdJz+UR7b/MGpZwUJLQj
mq73UKYdTqSfVVtnJefrC+0NDx7svKCVoaVpbAeKrhVLghQrbOy4APXIRsyOflU7T0YXlyl9jigI
bi8LOiRe8KNxvCAmRVMdMgQV1sBV3VuWGoDwbc7ld0WIs2//vd9MpSQ5n/somaRZFIJTMRiYl8xn
JJdo+9hHuEyjFexVTyTcyQBeebA2QAy2TAQgP5YA/Z3QUEoQFyW49SFREs4wa6+n8XYIWm7wPmSX
JQGIp2+0XESXOLoYzdMI0a+BsE3vJ+IxDq5t8tdnqgOTmmhH6qAJua5rGUFsDMqqJpSt7XgtdNlb
u7cUGuckGXuH1g88D7Krfj0/B95dnTn66U2/IqEkdpGLXJtqDgH2xVkgLf6+5UqfPf8xQo84m2qA
UGkXmK8n9m1ti8LUtaQi7q579+F8La7/O3NRch6B/NNEZKIwlPnpM8Yz0K2Yq0yNHvDe4BWck4ZT
V/CHbVIsWQGtojYUQbQ3pBEPUdFiKI+w3mf1GsArGPaswWp2W7zQFbQB+In1c8K2qWXgfdSwBezr
BThGQ0E71Vz+50tCDuh7esqJq1thNG+KUKLiN0XZ3DTKc9mc2KLbNb3wDJ4oqkqtmu7k5UgbMflP
uzdVdEyfMlKb0CDXJ/3MoRhjtjKpZbkJM96ZKCyXhGZGkO6jgyi8Sf4nl6IkEAGhX52qE4usVvjx
QU2fgJRcgxUM88kddoxCM+Sxx4/BnrDI8R+qC8T7V+r+qnQMFYabWPbiMNpPy5hfD9j7emYQ2di3
Y8ZxUazSKB7vI+quhD5sTsjLlgjw4Ve8RG4AESbzg57izfnKOz/Ru9DodDWBoidGwFrAs+L84Ufb
/F+mZN9WeuKEa/B6wtQxeXGbztVVU5fR2V03LcZDrnaA6JVLkK1cUh7oP1M0zT7Fa8Bd+Y+GTRnm
S8cl+9jnu3eLp5JE37hiDNSCAFewbFP/DrsrLiU4lJ/9jlr/Fpyp4wTSAM5N1QVlWLMk7lKITjho
CR2JvjRu9X7tm5gZVESfrHuKdYNG+NJb7F04iURLinPV5cfLzYHp1w/FY+ol7my1LhvrN3sWsXRv
RAWhOmxvAKkLmVWbleiVw6BuIRfe1+rI5Y46PvGiFJEEjmgAJL7DvPD2T9o6xVAYlz5PH0XK9HGQ
o/xDDtvCBnQ2fEL7FGronU97O/VYZbtb05jsAkFTnlUrLWzL3tkV6GgyvfwZsx4UYT9wQZvmBHPO
oInZLd7pQMARj8kc2iVJR1qBUr4jm9UcT2u5xVyckFJoRcpWJnFEbP6rw91FTARIMQUu31Gn/nGM
SUUnsOzhps7i3o20xk7y/FY7xdam+4/INiP5Fy97yOMZGrbat5dqnhvhj+if8Qn5Zl2OKjDMqXqf
8R+B2VtkDiKvKNV8AZgiSJLMSko4xmwObuRlDQwV9UG0D4q9lor4GDK486escIx7Gznmpfni8NtO
s1Vbg8XY4uZ1lV1mHNs6L66MyB+nJXe4I/K+yEiaD6fMsDvkDJ0UJshrnWsBu/TBIxVvxBUPQVR5
qcsOVJkRAnXHBot9bH1sv8hTSGVd+bd/+GWdEtiU6YkefnW/IvMdA7o+7qwUcWZtcnamU6+1LJEb
dNdqeAqrer6t8pN6kqpm0XIzd/CAbv3Z5CmVyKyyLxR1tzcsmq3IxF8vzH9i+I/UvVr0a+ZSM/SU
gTm8a3BATXyoOtfmJ0dUIUGAUvOxDJWXeJor0atlCP/JsXXfDCBWJRnxmf+lAjrvdOjp+Z4cSl3D
qM97XqO+wXsdheWurtk+6X4B4SMZAhB5ZbAOEp/HYakl+SlzHuguFloemO7t4oRDnLxpB0sm71KD
whDfzIpWWYYHiu1APBO6far4tX8DvHsqwVs4PoZ1qSl6wAPdAH/n80B3FZ8yWScOJ19J3prgZX61
bIhrGoHzXrtlL8VUjWe5k/dbimIlqs3e2tkuCPlqVh7ClZXxTk19nLT14WLF7vsXIjKxyhX9RfL5
bXX03JO+D9pob4KX3+O3Y+ddwy+fCQCBG5OWJe1nPfM7mC626e6e2824G3MDb8IC3HQDV/OejwzS
bvmJpbCPqwotsSibH0yzkuB0LbXXPF7Pdg7rZqA/+1nQswWiwqgf5lRanqNG/890zxWxqr0wqnyC
7bpeOxQTRmBYFFsVc5A8lL0qjnPg70m2S0g7Mrt1PT5EzLtAnJ0JqfSQlorfpYTHDkeohuuYjNm3
hMGrncMR5zuw3+JX01LWfRvRFDLWlW7v1aHMEEWi5eGQbNnMP1tP8p9s/uJ8/1R9K0SxdfSf4Pti
752+7nQGCjiMajQYNhE2whhWvCHUj0DpV1wZbQ/G2axsQRHJMV6cjBbCQkQ7z1QbFiAR1UcVU9Gx
11nozMi0D51G070r+HIcs/Egahdg0Z4YGnf9yxGbgBTJVMwmLvEZ+dbxgmrQc8S0YZsOh3QovIgN
M7qFOZw8lqtm4s8rZcxiNBMJeqhqD2Ngmeu3NhPxWMuXDXQ6ArJUbn50nnsJDAshVu+6j6cJEpom
AaSqKCGzVp3LWu4u85HUp0k7L0AJpp41ZP6BVsqLeNAgF7dkg9FTx+xSfr7I6in9vJ6hRi53mBqs
TRRvp4iTbd4tsEHph9ETUZK5si6mVG6KxAzn1YT/5WhsNO7kZDvY1ctzopf8cyQWe07sctK7YVKn
LXABIa75L91nTxF9s4zp2pM1NJFXSV0On0EHUmmIt+ggKS9QwR6EmC8NnzjDZiLexJmHDkyOOb6S
7fh1IPrMrh5AdnXZ3nBNP/AEgDC+OHoW0uj7rEZLp82ZslN8gfLLtIcEpap+5FduZYCGRB3SyqwK
ta9OpYBEHVmfOX4g/iWFFRJMJfVR5TeLSXaQHfdVasJiifFramR00Xmlw22rkt9jcl9RWy9AT0xv
0xvvxHz1kl16SjOHscnPekNzlEAiceBbqU7ez5rphHI/JnxveCsoWXQZNOyHWfKw9qnbGFr1/6sl
PzQdgQxzwiKusIFk+kjIy4bNd+/tZokPhfE2yPQHbLYIyttjtPLN2NxlZ7qBOxf88p6TDgSaZTHS
NHqwmdIKPraPmNhJ8t+FTDepO1i4ggwT6OHpOkCML18gq0RpJGTZYGYl9HBmYG4cCn/jcON3+/ql
c7sTdxRnpAqgTpf9SlC0QadOnYwWSqdCnc1NDt9hhZYWiKvfM3S7RRfQBqMihkac0lIfBOBj+IOb
uZvyWLexQQsp1BlQCZbwE4LS+9dDSkiFr7j7O7Gqadk3N12JIT+YGJt9N/u10B5uQnXSDNRKWWBj
fepbcOVOIPvn/0e2KsC0vB7HwB0/Kt/P8TmUaDKj1I5Jc712ZUAs+6UGe2+sbGoZ1PTnwrXuTP1F
o1iymYdvE4fnZr+OeOS/6jcYwSU+yKeccEMRD9D6inH21zLgYW/Lup+oj17tGpM38aNNxKmDlFV5
Kt/RIZMqvIEooJ0U2RBfj1ImD6Zk6OyBIjb39NppT+8UuC0Omr1tbG+WLXebc2YXQZght5cCA9j1
kkAB8EdnUx8lPYmSVIJxIzLfD19vGPZp5V/5Y51VXBUv8wfkCpZjegvIeVhex3M4q9IFem7n31x+
rIFTpWTXqk2mRkt2ARsoKEF5PypwlpGXUsfIfqiFfVgju73CXqtbsUWcm46D/KuqSZdQ7WehQ6DT
UPInqZlJmsdsxS2jk/yJ1wZWLdyKG3H57JJXF7GXTFtvLmkb/ZE8gJ5FP9lvQ26FfYyhSB/71L7x
MOFKbI8Qs0F/3QGm7IBGerit6/oqATXHqgv7R3pR5b/hYLCdTAjtSfAQycmnY+peY/EwJNZhoK0S
rIPN9Bc2egcc8EVjIWDTm9jzkIHLReEfNzfcNvKq/dOtZtRI7lPlQ5OcwfHpbqCusmvKY822iYmi
WzVyVfTLdbUZ7mTbSv7xdGZgMryI6cSWjqIcKBI5wTcqbUMlOa72SMFI3STrfkDQ7I93Xyjbwgeo
Plyq9Ow5q9rMDQfF19+BoXRU+fxVMi9AOB4CVEONVQ8D8a+9ZeN67ZWkTJFO8givk2FLvtSGINXv
exdQT36BSGKpJ2Ow/EREYlXqEfxKr0WodzjQLKTNScDZ+qfLDeJJCZohjpTptqXRuer61wTqOYTx
vDZCQbI3dX+JBCCsHPaXra3rf0fvbhaIm6IDcQpwBkWJNXd9QBVSMtZgz9EVn82+BYfVeYJk88b2
g8nSCg8YeVsbt2oLkj0dOftfYlJLIlWkSK2wgD9BGmiEN7PEjvKeAAZTkIMsTNwLGa0lMZtYJeJJ
BBQ5PcWhArqYoME/9U2dJAznNG5ikVQO1+0307/TFW4xm1jl9Gts0Gu+55RjCHHUQF7BVkQDpkGp
MKD+t76gzqPJL6OPoGz7TEbbOHko0dTbJTUYb6McPDThEHpmwf74UGcKoagcOoiCURxwDzYfUUML
KsZm/R+PPXz8N0gPbayYUSDNGgsFu52clDX+A0SjZyV+B3ontpEd6MKs8R8cSP9Ic9EyUH/vO1aS
lB+T9YKV4RVklFL2kXZzl9ay9B0xBcFI17v5S55ldYbzQnREltdMNFr4Um48WiFbXVIQ9iMEDvm+
YOpy+lU1hX2T0ZTyHOt5CHLwVwot+Op4tOFwLJGoMpuDB+Er1A5uRaHNxjZZk+LsfCQajUydFcS0
/p/RPERNNu8d2gjrFTVNAmxuT0GwQQO1/hapAByMc64gJGqi9mOzhDk8fUsSYDfgaXLrwUFHUbfE
xCUCPQQvgS/bpLpx51dtyUzY2fJ3ZuyhDDBXeuLvjH576u02K+UsheqsPVUj60tOp/cII6BkhUs9
IbFnpwZdlXeSuXj36461jkSBTVHwWo3NlUwhwaBBHt3nn1i80YQ5ZzOjOVYlmRTg/N+2QZQ5Ci7a
b8IoB6Kj0aOW4sopkU0lxyyrGVkHFWEuIYDFUspROQ/PZKMGUylgjD2nZT5/f8A6xdyjoDKnxvwy
YJT0wJBOa/g/qMM9O8ICukzdmA0ef6kYitIastVChB54RY9+2L9E+ORMNJcVDaSzNte8BtRPSbJR
rFwx1irZU5OfYVqZr1oiHSJUm4Kqz9T8iI1mreOu/U5THDaVNRkobEj0QG4e5n7/YIYUi6jbXdD1
0QLn1UeiI3Y6bns2zx2iY0S1s1mPtcLPCjZKH4M1Ylz1KfQ4kQmNaMUDx8LxmK/XNmflZO82f+Gf
rYBuJndLUcimiPzoUrWC+1gfZdC+5VsaqzVNnKI4tDmibF/pSIR3U4NUKj1RRPgCxi56VyiL992H
Y4W886sCYrF10wcMlDd35R9gI6w4vTD3iRFoTgGymcuogqaOoquLrwkHFY1XG8cSixUl9D2AVyXw
EfgYpCEBYgpn7z5kT9kSVU34XLIJNqSjv4zkyZFnxlVXCvE0B054m+PbvL2Lb0xLM+QBSAZqOrmm
/+2ChEfBrFDCfaKqXl3fkfuX0JpN+Yxf4+5ZMEV4Az8N1jQc5AzfBMNEzJvLC5mBoB780MVJPou9
VuRPtljZ2tBXe0QmkuL0vGRw/Jn6VCwtj8I0lMJ4v1OTl+ZfMZEhVq/cgktE1r3IknoUs+tGv4Gl
92aB1K6EiL+VsxxOQlsmOKQDRP6vMTBAw/i/bEZJA80mQ9ibOT+uS669/wy4BbDJuAtujTiS4CB2
4rpimwD8HV5OJ0Fp0iChtkLHvY7csw6mB12bwDXl4drxDi0vlpeIirabh7eoymx1hxP6pkstxukQ
+Omr/WgfTXx5PdqunxTAF04JiO2pQwv/vfte7wiax3zMWu9PryLbnCiE1N9/97fdQXxgBE4zzOuY
jMqpPlhZ4u2baZjJZt9DNBaxtvANOg0lcAN8Mo5T7JRsJRVDuyWzMbrlXeC8sH35emTqRU5nM6eq
CkZvxrGajNsDygahSERv/lKh0E5kJ+E49gAFmfDiBNjHp9BAFm00BNWfthSKSIWVQKS9t5LQ49RD
jKOYKRBuDYX65dZ9PSwca+ZJHuMPBy1OCoguZASfnY8o8tKALzev3QgEugWCvtS/B9YeY+1tZele
F3qagS5JwNM2Br7wtsqyCMaDAe9PlyTMU8OXbGYriIuvvVB3B1T+qfojF/XXHcgDcEK3hJKr0gXz
+bX2jc6BvgKRt6EOvw9o6EUGv4cVxiPCBtSF80WakBCvmJkqL8yf+M5f+sPLYH8nc4UghlPrrKFm
2EWanw0CDtABEBx8gs43KKhIOGpmh5CoA+wd/zykBpjUz/ivh2417bNxoWzBec6cSlanh4hThw1k
/5PPyLReagH65LN3MINCXeVj08s/cOuLg+SM972Ql5jliZLdsA+MuGaVYHjXbL7wcYo16YVGK1Dt
hOF6kTw/iMYzwg1oh4xs+22S+eJmLJ+5jdGKkgV4g5MAvRf1wyRwjbcX1vDTz/F99vG0r2eGU5JR
aMWaB2THoLOBw4w081lWNQwxp2Zyg6FTEAAO34XwQrwjzG/Git5ZRMJUBBGolfu/Ti2d2rvSY/s4
76B7cNP/Qptw88jkDVU77SoCcrbQkFVoJKeNrRGiiQGPHPX/70OzzgerKbRerSa1l2m9wz+sY5ol
2g6zasN8EJyB8XQ+EmNJukh5poo41Ytq2VTyVw5lFDlR7BvZ9xUHw1kR1Mm9g5fOsu0scc5iuG6r
f3XrETqG5s0ixPvLMgbRvnj4CHElxsia6YtPgDM7RmKwsZScXKYUnPKQ33b9SXodoUrsLat0846i
pvCO7dMqaeSJdWB3pPf4XCSDoPGdSlyLswHkPl7KmQlLJG46ONAHas5cbLhtIbQrzX9nu57n6r43
DfrXv/sgeWKVmhEI8jPX6GDQJVo+e1YCweqnl7FGtX7CVa2+mTXqLxSXXjGo/XWg9y0rw/XcHoE+
sJbU1AyuxUDzqSGDyil0kwGiqfAw0Ge83KQdc+ItOebvRvhw5ck6IN6bwjY/K5kUbTp1D0yeFyfZ
a3JzuefjCLWTHL66RMg9BlhoRwgdIRnTMwolgVgWCXK+VbjMFeeSg1eRT8c55lHKtrg+4rMDLNa0
uGz6jBBGLs51ulRDIpXiCbvv/XsGdAvD5zZVcG+HHZ/+R73m7/u8LI4HNhMnvcHy73VeqV39Df5y
bcGxyUKLuOs2jECqzztD4N7EdMRrsYDzakSCkeyWlucohYFSdrGEOi1G+ZSecVjtTBZxxXOVzc5Y
6X8lCxjZHn4VL549hXRSIeKCHIBOIiKmb+bPDe6mYvUoWHihY9QFL0G1MFIIQCAS9S1M2A66flax
pzqxH/eNZ6dX3wbH2vzF5fa/o5RnAXWxCuvXLW3qp0GnUbmZysm3WiwDikDoZ47EalPvn2irH63R
sar4KW6x+NJJt2XnctuejHfmxSs1yMAWwQoCLlsZLkbKQTFCX+HzngdfUapzPgC0BRgXy5Z08aV1
RSWjHySERY+OiGTnpre6dhORBXCVXEt+57ODeivvOt6uW5+O/adFzzC+raZK8+XIeNNztZuZLi1s
r9G9CvnMR2FZxrxI/KwRm7Ft3PmTZifAtJPsO4iYZmUek0ON/TGWrmaE91f4RF4hQ3EydFHSnoW3
VC+4ZgK9dfUaSMQXG0QFMU7y111h0cx2zFuNX5NycrcgpU0Dcfz4D2U3fG9RSjiM128cid/sg/YD
/uC1tunjASz7FmWGeLIUesHEQltfdQk92oUpcAq/KBdtHk3HeyauzEfwECOlRTTwstvLThuJS2n/
ksjcIr3UwzV7SgcEdbsFATMMGkhIAyd4CvXIqd3z65sYGqgxdVkubDb5D1zTq+t8Me2SjhXbZrNV
iRwE2WFO5zA+Hl6K1yH+xpz2xj3tn06oaMabzc3kGQnOWePsrHAHRrUIuBh3byOdM+eo63yVDbdO
QFjcMHWL8VM+XSUEULxVqRcwkS+lNiZdD1vFaFVx84O/c8/+TtwXqHL71R3qjrW4cMtIQ0NnJ2FT
lYeVUkUYMhbGBzGGNmx+kt1l/ADjzIt0RxTvK3/e+EWiGSPl36u2m9d5+nen7IIRHijzJc4Y+7YU
+gGnH4unSNiZJpAHfkFZ7FrJcMRIV+9VYvvNC769w7tKKWl0HVvvwEfAJFIuaq/fmqsBz4j8b9US
wlc+bZEjEvIXtcipo5UxqyUaV7NImZOr8BD6EfbGhxJK2GGtqK6q8/yVwZrBtAzcXUR5hGPA8Ibe
ZEeVQSX39g8bRufWoqRPfjIlvkRM+hudM+fHfbpZii4CNgHU19hjsYwNNY7tvHt18oODhHkMFEKs
MXaEwMT7QVroboUVii0+pKYZxRn3RcQ1iu3ueasHW5piaXT2q50Hi5s8mxjtVdhp3B8q3HbhIqEH
vjzv+NDHb0jI6CYhIhJ37lexysjkQSqrKY+rk42WXZ8CjpjPhzMikHzkCPVZKksBBqWqp83kKuWC
tfiixBBUiV/px7WqsfIhwT3t/7H3oc3WQ6CJYweW0ESq/DRxQyE/uWNrTmR92uqn3YUVzjR2vojP
qnQJUyMhXiZ9uMS1iCC81yr8hxIGZBWz0+/Bbpg3FkNx5Uu84rzxhGVGqlGYeTQa2hJCHfYK+T5M
7G/dCzoKO3t6bo7MQG834nhlyYBcDPsk2MlFGPWnLqfPY5Czj9eBru2CsYPtlj9ZCvuagqheV1Ex
C3Ufh+RjxJdWpHEl8Eb7KtoL/79cPuRdTNqTAQ03aoesKmzF5gOuZsP9OSOb5Kffm5hZRCqk8k7k
scOJeHGRiw4M1BG3AqJheICbeAoMzvQD+JgOZrHruGVxXtXrfasE1EhExYDbtUhSsNCMq9LmJZ/Z
dQmd6HPbjL2nuxNZC/7nxbJ5rjgdWA/X++vMFWC/QubNO7+zH0iB7/whk4+w49OAc0j9pvw0NhR8
lHgECZ0AfcqCxEe0xxqlYajb6pqnJ70Fn06I89obBPHrn8LYxQVzE1ihAZv1l9ErGi3yyS5Ubd9V
6VlGYR7OJ78mYx+qfLuWPg+YdDUT+FtKuVihJ6CjNv+hBnqR71nvsJwWn7lpyGEAQpC1b7gCWK+X
aWUgvETSHR+bwmJ97rVyOZUG3QXlckWskb2jQJ35sVQpJFTC0DSj36YdF35Xun0BDiYJ0MRtvve8
0U+SP6nCmUpytL7+yztjnJ05F9PWn7i3pCdPalK9xl7kA8rxXFyLw/TV3VeJW8rOAF0dg6od61aX
neXCZPxYD6GmBcuVSqinoWkVaTs2pMKu3mtbmqF4/ZklwGvxvJfRRxobbeTRE25P1k1e8Pqxa/1P
8UdJzhaaVUSQwzL784pUd3bqQ1PBWHWCda+IQBzsSv4piwxe8qDS8s6tNaSQRr7buZGeXPRplzyY
kUCzdIsQiLb/4oJhf6O5UbsOORA5/29gYXqZ7v3+OCphoBkBx8lOXPDvdk3zMvYaoAanIO1Jhlp6
TsQAN4xhhM1FeWmxXm8VLyX8+WOyZmsyKSBCnklhZRPp1beReEn+op/oKoGOz5sMARyShAEdAuun
lQFWpfhvH9JdWgZ89bJftG2Rocm6qF0VBZK2sYektEABMaUzIEp0tjmkbCfXm1ZuaydI1YVdaFdi
zCIxOCkF7hYa1FFZN9s/cWZiacmG+Zh3Kt0jhh2GjJ0jMbB/GskJQTzZEdtEiBYM6iLgCb2P8n+q
5VpeiAw89kSLNdVeuKyElTt1x454wJjZxczg8QHjvnDXJpzk2qn/O3ukvNg913riain1JxF0epTn
70mHaNdW82ix21sQb5WeeW5lroSOeH07WHEQPp4SDy7xeNQDMkNoGTEmiKXhsjyS7nO1+sz2i+8z
40QVqWlwxXD7c53X/Z7ZDlGo2WGUp2RRMRKTnt8y9jTeuBehIAsqn+fs0ya4L0Gjwdv1mft7JuVa
9LftL8K/Hhqpvy0IRyLTpfCIKh73I0DOT+2qOvJB+xGNZLvJ7mVYCzIWq0M6Nil0hl4ZYy3y1d3F
1eHiuHVSiJO964aBQQ1JYIBTgX0kY2ZSdBNDyJVn7QSx+r5jpNu8shwRtHaYM5ipFdUzCGf2pg9C
ddyXFwt2wbKff/nj3RWaSLU+X2aEsbBX4B6Er0ByuVoO+Nq2Melq9WnPK0PzT0YeNYqTvV4tp//C
I9ls0r+L/9saowEZBEDthr0gIYPKyvZBVfPfoGmAxfTAZ8WPUf5+1EGRHSX1vokGzLhvLuOMgaH2
YqF9FaDhHy99JqU3OgUolKxdTHN/swjZ4sPu/GUeHRnqHp/P2iPu5//TWGevIAO9SmJ8MWy5WoRU
5Gv/+UU6l60Pldw6LDns4FfPG2UtlkUwewDQkLsQJnGLfNsypSRXRupG+1FixMfkOV6RokVJZKUm
C2XpRy8T8RjdB7S+lzbhVH1147RKFnJ0VCvrCFj17BCwsZMjlQL15mn8b7AnSueE5TisUBGPT0Am
RobjQXwTRgD0cl3E786d7UcvKSrT263feD/VXo8oMjpd1lJq92iunl/2+yKd7+G52D5oYVEF1gXH
9Mdp3PW9sHZ/lBsVC3ZifTTW9fELNreDeVMintepagSeQNQfHB0Dt6W/7+W//xyyNh9GG6DEtuXc
12qA12TDDIZuoBKZnwjgszDsEjaXVGWuLuUagrDZrXozGIiDn2ZsdIB4IeueIPWO6cJhbiyUaVSP
KQzxK6AyjqLHls9QzqkUQQz4Va7h8JPADNXg8ZmxeR7Sqs0HpwNPEi1mJ4dDEb5fpfkd2YErAz1C
oRBZRcIbvsHLUeLvcz4m8ML3wAPWhKcEyx98Jn+DoGeIhFE/SPTvrzinxMAN/9c89O/EGSIipuss
Z3ofHGQXjAtmjuMuZ6/DFynoc1nZ8hPZjkhBQcxOkN8mMoZw4cVbrK1H5owpvnPFDvKhxCRytsai
tdjr4RmZQr1l8v7t9f4XDmOsTsm+AEdN3/cBJdMtJKTUvh+OroxcZcV8uikt9GoKkyjmxSVy8Y/Q
5L1xoux2W49ause+wawS4Z0r/RbqYxrPHJkM1lyOLvXwzxSUeAbQ6LR2gGGEH0CIaLL3bqOIvG6N
3/F2Q5rCdlxL49wwlFpb59zoQciXEFZN1e0RKqXg18VkaCu/tDXNyOrp46iYzOQLJxPmYiPYwRDL
9/oMiiqi/WF0TAmHBoK0g9McTcknmH0+GNBfyya3oPLV3VIJPkEfE+cdSxP866VhjRS8arSgybgg
auDeA/ueYGSbHq/oKU/Yh6ZyEGDgayYnc+23WT3e9RSE2vcV7U3Mqk4Eo9J7yxhDraB94JR+cKXc
gI/Ug19oQOWYfQpj5NDB5LsGWGWGLnj6WMGlp5oMVDSVXaig6LQ4/FK2MpjWPMKjDTAssSn0fvnw
f3pQZAXwJ6fBA9r0NGChMPW+NK5mI2kPn3JAZgNngzutwbwFHY1tb38mMludvGAxKTiOyTBhHOF5
mXktR+VuWHdJ55LM5MRKv5HgzNHWv1+OMvIB7ukxtV44PUsTyULZswQ6h9Tin4J7gIXGgdytrjO2
DuTGfXHTZv1nZK7j6c4nZBlyUiMc94CFy/xUJvw4cOw1+z+4IkrnEO/04zvw0bWvmqNcQjkbdNZA
R3tkJhnb5N7YJGMTRbwF/6iM3kHmjtgh5tL2ldkHKBoIgJDFVRwYlDM1507kbyL2NI0fKa2PtEqI
mVIh7zSIX2LaYHfH7Se4p4HlbwW8HWW7U8WLu3QkBh538UjN/cvd6Q1Yr+53tSiHS1huLd5umAj3
V6Hu7hqE2UnvL02dqytnkDgu7bUH9hBrpMa9iauF99qklBGPVqY/aKl99Rj1edWZGDQwBqUZmU8g
lYfJ1eJ7QJ7rKvhnJ4kC2YlUuadRIytYnLo54M4FgG4xHoIvMFIvABj2AZXY0hqkfLske5oI/A/D
z46W6LYNZ0foHp5ekO/60uil9d4GNfqeDzkY1A4PThN8e77CNzRE9+Txupe5I+1uAc5NOYiExDRv
WltXManIJJiQpsBJktO3fB+mgibDXYdptfXPuamUH/Ilxx6mowYRM/gMMhIQxRfxksITx4fhiZy9
O6CgitnBeLVLWbxl9QVreGuI0WKGSW5pUoLrVMVInEqCl95o+gIO7OK0G/sQeCudV4107Qxn9rrs
YnaEJ51JnsV+PAd9SfVFgc2EA9BaI11tCI2ylfllXFX39BvkR7yx5EeRCmWIo6+yaycf08V9YREk
Mw2cvMsw7YrkoD3GauR3IEwnt78+NvdpIM4pouByJh+Paoqt9xEBU5G3dRgW8vHkOcuSllWssIXJ
D7z/p+1djr3ul+OD1xSEhXd40FvuTnsKxZsOD1FmcMGKNDIxGohu5UvXk5V5Yg1ONI5LZbNp/mza
0NkQoxlqau3gNqLGDZnPDDQvuPR9ObMbVI8gLKg4ntHVZ4iVjAwwC6kkOeJVuR1JCrhGdHtDS8jS
uRMluRFdzpwuq/7tI+cLqy+vCShRSUw2cxAqqmE7ZYQA6CSfey0PBCMLjLck+mXxCDoZHhgIIjpg
ziN4I9S4KXKzE27b7FZ/tqPngO46H9t5Gbgg8eFsRqiDocONPX7xGP/p3AT5yyCNcTbOaqBttB6H
ofBWUHqwJi9hTbsVOUefqhQKPiBq4bSvascjyEFPknE7xpk9Z7qltnaBOjlGGj/Y87EeQCF+uY3I
3h7wZKjVVJ0kiGO+y5gYUB4cJprzTf/3nZbO+0ERE4PocVGXCJ/nM4uecER/m1aydOnLwRegzodz
6JhfXOZSvjTcpsIrYNiy+NPilRVm7jZkXd9+ZMNmbTu4y5T15oUxMwnnkwgTKvCT/HpBaaulgCdl
Fl2T0k22odBSqcjYGDhy43EiVBDgrlc+J6rU8nJxcXLxexObCHjmTQj2WK6yX2sQSbnxvChUMJ0o
t7IAX1A5OV+jRFJFyjiDhvZAvACCVk74WnltWL3ERGRYBBZxVeFpoXUbWVz7oJvi84XcGOR/OP5g
kfa0lEAZ2NHVq9Ul5ewARAOHDcHlGbfHWhKni6O0Q/Yl6qEy5ptrkEApkd5+VlziTlnTRFlTFYrT
hWyjwMP4Up3YYily7ykKpcCulODimT+rqDLR3sY9ARkGaqaP/fvw103pz9kdcT23fnpnTOMRxTHH
t/LSvFxDXHt680UbCz0xZbAbLn0J+O36hlpjEiLyNpdv8AdjpAOa8lDcw/hkMsi5gLnwiyHPtQnF
vQ/EiMDiouWKgLQe2NrkakbmDWmMCfdblMj13QrWn8PEiGnjufZa+in2bgAtP+C1IID0HCGKALVn
8tC+HDM5aow6ysm9CITvUBcDP4/zOMkdW5wD3ICB9KJai9Up0RDHf83oJq0390rxwUz5WECA64Tb
rzm0EIrChD3914kaBuzHX5fWHgd7lK5GiNJH47wE92B12Or7zsvD+U9sFB4oiMOSK2CXrKaM087i
KPVjB62nXQ7j8uRjf+wwsgs+7JQqcCfTMdA7QCwvWkl7Bs1j9fBpstDl8MW9ZdgyqRE8ofSYDywF
MVtiVp/LMpIJIXTuh/wOql3xQA3VAqABlS7baR/c5Vjpx1SUpNfFsWxfqIdCk11RxjbOfvuqgswE
MpauWiZGIdkZLgkuiM5CjAKI9zyJlm7t8/miLUxH3uUzb24aBowSYG68COTNsKXDhlnFcg7W42Yu
WFx/Phaw6RCJlUMCmto5I0zhk2YshFkCPa4rXf0L4KzhV+RqBFrl+udvemXyS0s2jJh3ODcPEbpF
71uqpu/CzQ9XgqCC+2y7bKKS4R2G2lUIjYxPTmbYiSp4poEsNjWWUzFq6y5r7tk36RjeZZEICmKT
n7VZADG8HCmnI3HowwC2XWNC1eTuWuc13tNZZO5IEViUSgkA9gUNPHKStMwXceNRK54CeIbKBqsU
or2/3RYFLIrMyIPnN+31YDH6Jd6CC3Ado3yOxSZc1Z+NNchkAJ8/ZN7RtJn53Ex4mVFjiNsYAGj6
mI6hO2+/JT29skAzJJ8az8VqcSYYRs7vC5yfqInp3Iu8ncxRG0/RJWPaIHry+ZX5Ynav4MXwl6En
fjbCFGzAh4uANKUlpcEt08fw96eGjtEmKzkGIHf3R1X/N/HWiTPHyhgnv/5sL3w10E9PSYccUNlz
CyM59af/GG+9r1dwpz02q2s/GnbSW7pRHpIELfNO0cFRA5Ejx4Jup448qtGwtLYoEGdg2k09HT0Y
AUJ5yAKxDZWFqYlgCpUk6iEXUEJMeagDRAHO7vtCYrZyewvkYWEIWG6H51CQHoH15IviV0SKR+Z5
y6SkvRXwxj9xQq7ylruWNRUUuaDlkaaAyuByAs7In2bmukayU7wopmn2dGG2u4w6me42vO1Rsy/2
MoqrumWRgIo5jx7LzxUr/DOXSci/07l6tNFSUH8L7Ym5XqHaKFV95Nb3Py1LancYZucI9jq3lKOz
U1pFMX8OsIXGjASYSKA2TCaFtrRd2e55Hz6Alu4qW0ZtT/lVe3L4apSpWs3kWfUL+geCpgWao96o
woSeEVne1w4ao3EYrYhcPRmVcvSJTDakW6XtstmvXdptcg/PhHI1b7zWQj1yKJAnWweqM0k99Uwh
kNUB/2xqbbyeCf8OcAgarmarVV96NZlXhxEBvyIJoaU10X09OMELd9IidKBAAjm0/F211wAZHGii
tCpSA9ivif/VwMfOEtMbt5hZwoqEc0oGZ/FtiQUjhDTZ4dMTyrm2awGIzDQd9MkQ7PMxVTc32TIr
RkQYtKSZOgIlWKeHiWHaT3PmGiWxPE1gXiVxlR70URfI0hLbaYFLjhzzACuC73E5yoxZu0BFiEpK
ecq41ZM8lYa0Kb0/iCtl1WgwKqrpgR5Vy7+gTat9pqDnkbzouXZut2dsxU4J+leB8yTFWu7eo95b
YnoJ9pKX162rPuc91veQkFCi2ihyGRUPgybnIXoOypK8b87mA6oM2RVd54ehjKtg7yJAf2KmAbFy
QeWiygNe6h6vEceoeMj2x9c1L+p+JrOMwHmtc3ZG0dhrmNBpd/CmVjOTytAhTqXd7JHqFNGaTV9E
Y03B0oW5PTslA0UpsnlJtl1sSBXH4Xz0U6SCE7f8hCc5RO/MgWNGPURuKtP9hAUlrTnuk8EAOfJ8
d1f+h7PVOYsJPIDHULpxU5Hyo7xVltRl1U8MfHP5+HAXCh92gAcB0Qv/bv9tIZePiRyZWermbyqo
RU8b48+C9auggDkGhGddDJDmez3kQatfJf4W4z+n1dHKdtIJw2hlMEAYHsBR1JK4X5U2ReHLNyT1
YiBsYEa5CZ0ehe2B5hN4KffzMf6OvfuJxe/0fEBcgxK5MWB1k5nd8Iy0lqOLhEoiFdEqbq09UYQa
RHizrgGtvWePRI7ib9EkDQ87Hz3H2ycz1NyhFn7EBAs+Xf6wWhSgsTb19C718eW7z1S1Cw7Yx2jp
AhLvW+1xE4BnWdGdT0fftElZSSLyqWtkufrQbCY/+eu7Hf/cVi2VL6Yp0HK9Hz+zHmj+LFkQlJf6
uOe6wF9IzGZC7sxX2IZ3H52gSrSm08+WZ5YWhh9vpe9i+/uryAykwSMMIykdffj/Yw0SqqpT/TkR
UQcWTbENWu1bZjzMPSZ+hfha7rtgI7LmEjhcOiEr/aGTpPQuVh499lajBFYR2XX5sbyi2xWzh/hx
bO4xWlKJVGD64oeip79AsoxNkHmka+1wjE7oUn77O3Qmrfhd9mylxrN+F3BR5XfLbeboOSW8COMA
ubfApjdqSD0uySJJTY+er+Ir9TNNhWijUMKGybs9hIZhEzH/53X/I3tc+1hBq58V07JWPZMTDdJB
gnQGlSGDlHfCjWNEQD+N+hTvlM1mLGT6Y75vW3wzY0AccKgRMmE02619nkT/mQw8amzUzBu6q5OK
raH4UVlFbjDAANkbKsWKBCokT0h7ooUVg9PCaRtzCjY2+/sN6oZvRdLjodHBYwqMaVpW1AC7n84H
HhFJ7WdkmE4og975zVS6HQ2myTjZvMB7MhHUnajvxgP4IQ3qJE885YEVUmF3C4aDvEytaPpFn5m7
+hDOBruM1OcUhAor1kjgqd4nyRLGSbU7oq5aNQEjgin1aO0P41G8NyZyTIR6UykYBt2KhnDZ8Bra
kg9pCW57mKz2iXyMDRti72LehGSt6T2MYmbi18WBFZHi9BJp/OvjW6OHJWR5BKALLndjrEINLdu/
O2aA+RDeLPB9rt/w1hhDi7yz7L65D5H4vAxsygdoXF+aTSB47NUzK0CZKdGO3/T/K+4TIsxCeKEr
9Aw7SnIYR+NMVsyMTE3MbF/IqGO5wZrf/LLcJkGGXs2lJwPXd8cseOy6BgPeHZH4ES16OxLsNBJI
TgsNXiDLJ4MSDKZtTbTLn2+R0bfjhZY/vyVc+YKVMv+R0ySoqjpyAXlL5gupQVIECJOgPUdJZttH
Clv/njsBR6RTliMQjPqRvnfAUqUSm88Q59Gfpr8AgkdHqwqhhlpQFdrzjt5odLQq9HRIs+1WrfLT
DyqBtpQLGdO5rhO0HLukZxyN8JKT+WvDhbKYC3OMF2WhKQe4nD4z+3Xdf2SKRmK5V+oxUdduWC0/
HFGCgzIu8XunpoPmkInRc9gQ1RBzkE8hQVfZe9Q+Ny7JwFxYFvCNJATvC3vI8uFDiANwWTaK2KDF
TJ+sPePOjqbbDsSndbnfuAqnuiRNEnBVH+rcWBSDDkdxDFh7OL8qWqJRAlhWVnCzU/ORWYMtDpDa
TXAQ4+aDslTUMjjOAev+F48RF0I0+XohObJpDrx2w5LCO9nFMDhu3FX8vjDoZoMg2nIpdYIOP0J6
5AmGWWAy4QDgdHePlEUTaL/7LoBiv+zdziVXzUV7TZaUG4MRWpHB0pl9MW5Q4QKLmzTteGcwMWlZ
oX7BjdLIG00LiuDb+strw/s7opk2Q2qcYH84UzSXfK1gb+kyS3qhmk8jGJTKiWP7AjgHbXTOYBH8
MRvuP1A53GnTdNM+q+awjw0hGfKJ96V3JnmqjeQn+S93LvrNTEpcUpaQ0HQ3CQESFuuQHJ3cvixk
nEYSC8/g1G2UI6c1isNe7YyodmrYWJ58OL8pnw7Q1ZlwOa5UUxOhQm3xVCyOzXnWZN9fGX2bOkob
r2KjuL8xgIYhtqOTEwwHys3yfDVHUuSaE0s//9noEiireHROUrTHufnzwnbQI5MnkoC5gVvnN8yx
lkLMsrIHzGFPhEMQaqxfSPxvl0yB/6WPwlvcHkmY4aH41ykfBItlEFfnWbugSupcdWUEcuezw04j
TazN9MdVzHtL1rjXdv9LSZyw1fVlssLgRgp6MTd+6tDaBxtKuVY7zNtmaTU7zD+Te9nFJ6r91vKA
xKH90QkQNVmc/RDewKcVlV1zd8CnT9e9rMOdTUnbm0Fg4JyE30TiRZ/NZ1WO2P4Nf4n4qOk0vUB+
BhSe7LiN0OS5k/5IPv3KOl16/WZ7S9cICcb2xh2iHC1opWLYSFp+rqbEsj7jdUNIkEZP0HuyP1Mw
DDdMqLJYakq3LHNX/Iw0vw2mux9rHL57UXNBLKH3i3/+MGRq8L4hnZGCyVLntXOYmrxYSdwdyf8w
K1pvYuzKLFtYOkp5t5COb8RDaBbevsXQPnDJ1CLZ6ixlWTg2wiRWRaCkJzRH7yeC8m3Lzp2dKAps
5s/pCAURpyJgl6MbvPWeQKoxI5B8DKuDvZ40khbkDSfOolzgKMsk2LozgE97xvpwT4YnzrBt+YpF
VCza8WUbhLFK1pVsh1xMze4oBIA6iTLHwwX0cBrQxo/vCli46kuyxVSNookkaUOACyft8eoOwB6E
n5MLm56P4ImVTSbQ0BnBxkWD6h9AB+IpUMcsgvAiR4ecPZZEGRayxfbaRPqkwXOFB90H4xs4bL2w
uOC/YGXyiCP9hEk4I0d9lU1ek/7xcTDJjnf6XWiTU9F1J6AHmlOTeyUFGOGwyZRbFL0Z2rN4vgvY
r2XPOd6vLhbju+xwsnOFVHphEy6Ov9kx5NQfehY1DLAEzEmfSZnndkD3VAOeI5pNL4hHLA+7Uepz
Sj9ck2YOzpthQ3Q24GzOxRT+V2yn5bkeYJOU6e8a8QBIR48JUCxejb0Rfg/mKW1/2umUkmFIG0f6
OXBPcX3kjc+fNp7tnxxCbsKMr50R5Fynz73ONriQVtrfqZf8cGISGdtculbCowyVZlY4f6Qzzncl
UhG+9KOlCzl7Zgap4UsCbUX6mCUK+U7gYldcN8KbrQWPgXDIfM+v5Dz+YODPxmYdgWHI5O28T5xF
703u0Xsdcw1F10iu4ljubef135W/VSUxx3AgMKExZpmUsnlNuD+50NBgwZTNd7Yz1/2G4XP3+jXt
dKSx3hLfXgV7yNx/1zQnBkOTsOuviY+QSluXLZad8FrcR899QTabGj63B+l4eWHE8wofMsCMBahj
6E2UV8Prn4+Fs/+KZxIqDb9DvCJJV8lh4XhIUvut6vkYDjqawm64LfirjLlo89fz2fwAxe7xWHrT
3gapBrJ1ZBAKCoNH73obW4zx1iDPDajj6/NowUbXEk+TXGYWMzedNMo0b0InxgNo4EV/IBCCX9qG
21XYRlr1wwp8kjQH+Hkp3ZxA8NNSlggB++gSL3E5WukGNIH/V5saUPSjxd75DEBUAPCQw0clq0nx
XCpdmYmDaKOpuDnbBAah1eHBnVoHW1Fd/GCYWJU6w+ItBdjx5R2iTUCFdLEVyDo0SeX2d8rFV+ck
78Z0an65S5eBSthMYT3tnPMbDcBf/h2Voa0WyDJYIK24hEk8xqwKrLyac8JlErQ/DryVrZCYuLum
XCPMXthxc9lNe9Z9WvGI2CMLqROEjexrTnYp+oZo8DY7XqFe+lELkmXkUxnDgfuvu7aJ/OGOR4pj
qkBsN6qqZSWtEAzhe9+EFe2YrWFacEm/ijC8PneMdiv3ZQhYSrFYVZzXIE8+j3rrTbe3iw2rErGF
paJQC2ke+3iHYFKMdk+Cveq64JzXHdmx+Lhf10dBGNv7WCexEW9YhHt72Buvj5wIRc6osCIeHIbF
AxnBI6NduojYV9eQhiWdHmzCYMAxYYkUvTcSY+c+Y2HSaBfRi0Oq0f4fa4nJcbTrhLv9kj7z4IWg
zEYxO/MK8shE5mQLM3rWAbbhWuokRAWDViwuUhB0tNQDdKSvZ3XEpwQslzVGW363pDcMVyeRKL+O
nA6NXN+5gPV+Gly3wQEKA5Q15Y5K0CpWMfuH4ibICXy+I9bIMdmSLQxM05BTqGseiDW44Cc5xyra
BjycK6gMS7zyU+so1nDI2IIiKR7JNQD2yWk15V5iivd2qEpRITMQMUiXwJnCL5dXy5GTjab7XVQT
qNjQF3IPteYImCRnD1M5o/cqhN7qxWpHXbj0s/H1GZGi1ILELvn3EDkKm5I3v6wFH0OIvidzbieT
rIu53MBI0SqsKsADD2Bj24hpJoI5hnJ1+PkuZ8Q3WzD4TUEirWD6q4sqcPBwteMZlw1zUqaq9Z+w
dIx9J1tRbF5N4jfkDuX5aN3daIFJqd6qPKse0AH6lsczHy+HXjLiEvmP4VdtV/WquIiA91zVJjZl
eu8O0lNTab80Wm02AzwEC7FgtObisc0lFTf8o5z1rdCmzurdtsi8khb4T8IBbmz7V6kIZe33IYwM
zXeFGQwdhsH+rBHt/TZYKzkGoGkaDsrJBAZfnaQnmpcC8A3awpUJv59DToz1ZWmXtfZITApOSOgP
vBiSW7OixymSkyGsw+Io17nzubmufxDjZLJP3Xv3gtGRJZA3w7ttLPCQjhmbCHq2SYUDUJF5PVMl
MjNrOZELMmefG7VEegsjxdrYTX7ajX3LZw4z4Pzm/yLQNLFf8IgbU1AakCKzZ0i4JiVUr9tM3jLv
sLVB7qPOlBTBdD6a2K9a3arU33zTWCaJcAd5v8W5reAEKfZ0M5LxXFlZ10Xm6uc23qFIJ3r1dTUP
Mn/UgHWlkOrg9uBLoHktX1vqSOEf1KNN3om8NCq5xf5ZuAYAK2bCH1n3iAmOMzTBl09wKYf30Mw0
4zoXZSY4Tg5bZlBXqYCDDlsmfSJpenoFG4EuG59fkHTAmsdOj8qe+f2aJzq/cp0k8LwWGQdb85St
r9ERY37hfcEcD77v6LIdOPjKBa4PHpRT2EI3MqcKaRVqlgsLn+oQZ3gBjPTzmGhB9XwzLpMU0BPX
6SHUwLdD5jhLB6KSp38WuGCPF7NQMaOUcyYR63x4GUAiM8oEgoV8CR0IG99/8q14MJR5paY7zKoP
mfmvisPUrLFzrOTA5SEONZ/q+iR1s18yeL0m/4tgFa7kytmcc3B7qjb+JR5PxEzwYnICRV5345ON
Y7S82gI0iQbECG4RHU14st3abWm1uaoF/kipdfopvLoO8BUn9yE7s6ThIxKEvVSSKEsbueO4uYv6
6LyE/8PTSmaUTMBIKoOVfdQ/h7nuhMHHZqK1zlkzdXprCOTzm6K79E7FDSUM4ZdLMQscZm/sasUW
PFlVZ5GfdIdECYvdAcNv6KsZnQ3K4kpLJFKq6fMFh5j4heiaOb2U3O3lfcqu34VkL7Fc3+uaw7zj
NucA6qUEQAz2FXuS9/EkY66eRgXoPn4r4DUDR9N28lR3KFdsrU/NXBT0sDYLn+gpDsPhaEoCCoyX
v7dnk9kRvBmg/Scnipm5uAn8MmOAYcB+gtDwXSfbFAV9P4RPy1bZAj8hbqqmwiB4VkOVLCoKTN20
F3BjqQWkspuebfYglskYU5uAuSnd4B/Z2OyNx4KtIY1oTJDjoHUAcTQZRRwk0uG1Whr8l4LCS+Og
1lUSI157JV4wpF581ZR0Cixis2S0pMpLfCUt1d7sAyvgrhOi/EMOH48WZxlXD7YtMl+JDnWY5kww
ImB4DWEj/CiYikEkQqtuTEsmFm2tawbg/V3etpD5k2p6DELtpAeYrGbmbkl8ObrjuwHPhmps3ONW
bDg1tKTUZGYmvH2nHHps+VnHa68vRd3bHTMo8VwjW3XVQCJiYisBGx2PiS1vDISOrJIkIzm7+dlr
UkZ6DyaRn+Oo2ytippDW4N6tOnS1vu4YlL6iB3YfC4o4C2fhzRD3WVzze5VDEM1tb5Op1MqAniFg
JOA2NjVrC5F5pdwscKRplEZbKAg+mSLgkG6Q6AJI59ZU+vIjGS4OwntFOquRrDu4zJrj4MSNmhSU
XvhrdryRZG2PuJymbAlKtvwLTWV4o9Mact28JlkoqLbHB3zHsPDpJ5e7ziYv4WHLHssOj6+QI5uB
WIla/pU+C7b9uW0g2nCasTIY6DzJxqip0OvIVxcm73sNvf5F5LAjE8u8WJPE9UuajwboCPCeD+S4
g1a9r8FaOSVJfIOa5LkAfY71hUe4TkRpWEQLEY8CxXn67UOgrCdh8lVqAxN1qFICCsprk/BP9xqa
F0O4V8foSjSYBM7M0PjnyE6CKdoYla/w69YUJ/KdABlD7OjfFWgWDXrDoW82uI39SubLZQoMvlQ2
fe2fKJmzbh7cnBwnOhSOnnp2n4QAdBHZdllq0TR4HIT9R5wQhEmjGjsDDyfAoDi3W9xfVplGr7qr
74Ixo0fB2NukfGY9XiQwwrP1cgzcwvXGiaxOXtyTleUxS5UltZoUS0mG3wBo7h56IJSAS+3TTddO
Lrly8WrFZEZkSZmX+f18g85FryqYfRddsvNyfgz/5FX0t2mchZXH1+hE/hakwvzWIgnClLboKkeP
YNBSC4QkziOOMwUBN50UjnoKSVGr24XFwIUhtrjnon4CUFUrF9/gn50N7HZ+oyUMS/X/d10oYTvz
uhj5diXqXDBYuQjJYAKevQuZ/e7/oAAN0hZY2vot2ubNMX9YFIKSuC7FpHFey4z1N/3FzsRszo95
QjxYa91DZLvK4oQtYOaJf01IJ1LQdhvBE2Pf4d7ZoNx0mtBcJMGzuufD1ShgxGoZ47LI60jJBejJ
7dv5BO3FAsgUUOD3pTuPuemsp/dFC3tCRNGiH5eGQ+rMZBCGYeYFtR9vnd8M0i5IYv+4fVyO7ufh
7VeNFWtBD6QzbZpjpqn7U7vnAvL6dR7prDA+T8DmzyS5cOPmpXJ6HJXK/8SxFaZz+yErb+9vmqsl
cNAK0y0KZ3YjxjqVUlGzj/0rYn7xBLLu+5MHr424dGf8VveJhwFs8zIRZClq6UVbP5dVygGjv3nb
jsDT357RPKOQh0pNiYRBs5P6CbXwS1FOQWOioOqHvPcbmeB3LZlW6QROrl12gnT5O4c8sUwRCBVv
imSeigwBeYZsH9/6ymN/Dws5TYoDr3YpXHDGAptTTrzGqkr8vDSXjnM8jvIbveVoxq22ssoiA+VI
1nEv5yNJSIdNkDaCsn+lGFsW1J1IyA9z8FuVCfC1j0ebwj4Dt5pOMhHJef630yBRhcNoKUhJCM5G
TXFHUdT0JSX4PY5xyEta6OpW2MqLabuVLHgiTnt2j2+CLqP94nDQjEku6CQ33jVlWluHKcVS+3vY
x/B0MbuAI/edab7rEyE5XBuds7AiER6RZDIW5rVI10ixiFwJunjdQXW7R+e6Uhr5xYPcvGvtAhmf
4WfV49OqAtYpvyuOw1c3EWxqMUiN08Kmm+0v5BhBwsc+03GMyczqC1DTgI6/uNDE3NNPjKjAEwBd
q+Zawrf+3cSkh5bktHnbloOx4XL2UN2HLjc8D8tBbvPijU2fTRglLngUi894Rl9VLKr4bz8MKKsz
rTmQF9Bxw7cogZhbXicpem9btCBxj7ZoM0sOKpLwBsleFFCRxwnf5EFpS0CvzpCudtfkzx/4e26Z
/hup5dthcX2anUoI8r06dFNDuy06dm7JUjjUpzr965GW9yiPdQj8ROfZLnNz+iLHyvTvPq9ghkyJ
S5qKcwzcqLyye+mHd+NQw9lU5hJn1PbAilDYo0cA5Sr7OuAFDSfbzERq+n6ugBbJ5pwiD3aT4rwB
jnWuzsQ0C8yiNwss1pECMjQ1j9flO5jsoPhZ9HrOikdUTBQZ7DB6U4lT/kSaiM37U3y1plHKX6QU
/dp5rTnAIFwbqdXei8Bv8vXnb3eU8WfMO6K2IAW//YXlYZr8ajfiP9nPeRFqMqlKbszaPZMyk85C
/WKJj4aq29FITRDN8J5AuhXvOg12euxhzIIbfn2ce/lyQvEsPhTbGlr462SMUSsJoOcpMr7i8DSP
4dLoLWMfTCjYYNrfBM6ca14awVfcxgYVr0kOGVJKk4DcitMLK4w+ujIZXtlJgMRDrmpGo+J1s0n7
gHTYRd1FY23pWRjZOvXOEg1xVo4wGVTV+MaxQ/MWqI7PTLhwRvh+lnS+1P/sVy7O+2qyNYly5F82
c4G3Xt9UZbVHT1lbkby0lfXiZsJec2pfku0atkCL7SGO3UCSRjXPYV7RFCRVFD5W/zTLwPw6Eck+
LThlsPbze9DlbvG3weK9U3LVN+vuKlkBsnDrhp5uDdu1xiI2w0ewHA2gh+d5HeOP0sGExihXwRVf
cHGGXx5eCwEOaJ9k0g/0SlsrKD/0Lxx4Hm5BHAMAs+BuMz3etA1ECXTEKQ830E9+GsD3rsCr69g5
gFpbXVWqjPz/U5V8j/rMT472ypbWDpFZ1mRWd/b8XF9KmUq4WLfrfSj0WIbdmZcyjnl/XKIFupU+
rRL4tzwlfqGyb5gDE4j43LQ9pkoRMfq5kww6GMowP/vKlf3tiDtIneKZVcZ7ae3HucQY4RoRaunY
QHkR3TiHgZ1xW/fw3TSN9libmYR3ougAtzji0zJ8YlWO+6yAOb87aPwzP/nqxQFR3sxXfuTxTmBC
mxtCZO2HhF3+3FprykDq29CkZkmD1hMy7gOeWC9wmTj2vHpbeS4jmURguyk79avMTTbEN8A6AmRp
5+SYMmqAwsquY3TykBKhXmcnPliXvwufHjlZaby1Xuw/xgVgL7ctEnoEFNXDL/+8rHyOJ0UBkjGU
jOpYySlbJBlnKx6L1rrCb1QNVhGNLZo9tAcizRhMPNt9lNRPPu5/YQMPiPtNnjvWu6o8OKLowFOy
Yd8V2GVkEPbauUxjYPd7W3E0+j9mXZWRVA1pRqCk9XNcTsUG4uEPV9T1cvC6EVhSaGi2ytz0ugI6
TXIBkbfqcqbrjS2442odWZVZpwUx2nFPu2sQBWosda9AK7HZnvaNb+5dd9GN7Qf9OPNll2NzLDAr
XCIwGRQyaic/IHs7dISf5Thk8JZjQVjwBnn4Ubf3ZaC8b2UQtbbU3K/Rk478GTgDk73nxGBA4PgG
Ck+3nTKyz0pJ9owZ0ioGin3Hy81Pq+Ef5I9C74MMsB3Ex2weiWpKlUVFOqLkFV0vrTjMf3JAPjWw
Qfl6PxFBaXhD2Iv7HL11F3+rFlbjQtmre/uCEdVpC8vsws/WxxjoanY9lEo76paQqHocaqaexmO0
7mjTfCbjlj2hOM++rdJoI/B6FMs5yz/+JAPuDhrwXQ3gA0egx674j7gdquvbrh5PBjIqWjemu2Rn
vq3dmOP3jaKUQGafchQwY4IPqUueV/90SnPvMjbs6GWpOiJUrmz+Mj8m3uYQ/IwSvhrB4LCRxpSV
1nhgTCJGQWEO995mg/LgFHXIYwtXM5IlajyETBuBEhecyyRP1+6LXlR+HVEFBSkqpDb0FxpmUxtG
zxIP1/Zr3oInyQeHz34ZiM/nttuMco8Etn7sl7a2IX5NlDgczJsAlCXOTGJbysV0AkjUP8/52oad
0m8m3sg6Q9s7uR0tO9cMO/O8EIrj18zGalOMw+HMpXn31dblYFcl0dr+3nVB6w7CbCOPMhYZ07OO
WQ1HiefL/oPHSxa77Hjo8ya+/LwAdLQJfzYgp4uCu7NMEYYKN2vVOdNggBrQyRZgnHcW8HZpjJQl
oSd93N/6jBMRIdBc4VOYlLpEv4qbv2nvW200+dT5W/aiITgb7QM84q6n2zCZLyyY7pMmSFQSmWmt
lOBYRuEuBFRYKKgjRKuGz0jn3jwhxvxXdd68J7UsLpJSgRIjg5MSn6tUg3JdcAE6R7dEN8A3xNB3
nERpkWRh8LDwaDlwv6oI/9RjdIJlDh+SYICRgU8I/ol0CRTwnHPtukfnC8wCeyAzcj3tRQReN4Qw
65mWDjB6MRG6b8qLm0Rv5OzpeCHSJeFDSdwshKigb/CAeFUpGgW8MSpKZscFrLb46kyNTeKT0Zs4
zk3KW/NMep60LS6cKe6r9EN/3g80uRHqzOQcoLAmWXOOtKKK3MsTyhMzt7QXwxAwniWSoWybLF/G
NaOko8epFPGf3lapQIOPiFZQYzBDUqcAfgG22GXKjyESKXkIrCidhlwzAVOEQzjlpHamPXBrrqaF
emmWiBOtE9RqkArcl7NQmZNN/rnDHjy2VOiw6s8DDWyvhNpbu3Lgjjo2HN7d+Hpwzzk+YK5D0r5j
zQsig53Ruq7FDMwU2ry+Xf8hUaBR5boZqoq4CdGPD8dqX56ZwjmatPN3fPlAVQPuY2alSfxWIpWL
/FNkm65vgQ5fbhzrhRhLw7nyiAJMr5K9u2kQN1TNzXcDJBiucwcrsvj+0bjkVueiEh+8ILcRXyiv
aQzZC/diFhRcRLenGTsRZn6h/TrhzgL1+2IBs1olEwsRZO/msg0YdlCExc4N81G6dIsiwNMlT50c
cOEcS4QTTkeoE6Fe/1NS2WuVGQ+DhUiRRO3NKHULnS6todeiwISN+CMMxQJVXu37hAvLhWDR+BD9
t3ubny07gvOhYfzV8fld//jRS8N+Scoi7VDoa5Yxk/YHW8de9N6s6I8hRyWckFS5Rbg7lt8jhZhn
OqTT6TTH7xlhf8iSU71IXuYrkJ72tJaNOrQyRh24kSFCrTAHeZCUAId3oaeC1cvaihroFOgkT9I3
XTeMTZw27i9Eh0bUZoqbB999UAhW/u2ip8Xk6lwvv3P+XUkspqcy4rGqe8XdZlxO4czJhyIopgZb
AfmawCDoPmNwQR+2dDAS0lhY7U+kNvQNpl+lrSUaFAdhWODyzpLQVaFLIhbO1xRxK4/iQOY4jvB+
kbdj613NcAwswUgkL1lSfPxiFsjtuvZN3G6+692kbrEv9VC8QlDdIEc3kiksJjgeGlO1bhmaLsFf
YcmJ6OXl7ZoYVdqgUzh7g6wjCutrCAR2AeTOMu2g4XnBwoT+zKrq3a9gQIkfmgnuc8/oDkjj5xuZ
LloR/r8diMP9ykpaA/bkRaBEGrzd7/bJWciwRaq++3M1d4ckqTbExBo6n8wlm3P7LXyVv45c3L8m
wZNbg4kSRijHewiFFqGJJ/ZqVjwfATk6w84ihbD+HiKE2s49+Tpsf4EheuaLOTg3Quq7/5aP58O6
qirmYYcYLpcFky3imnU4z/T207K3rl6r4cmuiNgESJ/DMV7l385H2dWE2Wqrdm7z+78sfTNGIjvr
ytqZrFNoemZDVnFTQGy/H9t2FXTpRBzHC38SYO+cTv8dHkPD4oQ4xW3T3UDV3aOE38cT7Z3Jg/IH
eR9Yi9qf+CD576wAb+oh3jLqurPIA/k1/0+6Xg/ohwPlg6Yq0Ss22POZoHMI0zCQx/3/GvnRDT1j
4WyvESTKVyJreF2/D1ljT2SJ9zTtf9QDN0ZicgDUak0Sgy0E5CnisFHFeCaAuR8HwRRpCqsnPuzI
yGW2NF+DHbvRLZjxs3wk92BgAq/ga8YGIBiWT5uumYMdtcEKL2X2+cSBr8haCQoBnHqMUlkKQLiL
Fdhws/2dnA2/IxeRrJoxr7HahyuK7xk6uTMLcdwAfTPT7xFT9hSKVsPDq7jntf2pQvHqKQoy2YNc
BFNDZDrFiGIdkuoWb1th4jR7+4hN6BIW6VtmF4wwlux2AzvAq7aC3BC/QLioow7klHyBeo7KiiRk
fAIzkRGx3muGwPlDPPSkIbmWgoHAJYjPHjRlcLa5dHFcrQ2IcR9X7DILo9Nedngp0WrZY8AYY65L
Zv6ov0C/M/PruUoftrd9XVDL7WKV6f0keiTWc+sCvCrtEldNDcLsUy+YLCxMomGLo9t6ORqfgS5w
z+Sk5TbFIIdm0vr9h61G+KG1xbgya+qNWU6c+0WuxRH49ior2amFpCHPBvMOjq+NSkOF3grNf9FU
ZsBNj9eDYcA3MErWTOjWis02oNHdVnMnIHwiEC9VEARYmEXDNsmxNtpb1ziJOC1tGpa4zE+IcQA6
mgsfPzyaObUqCsg8KgrtDdMwyeaW/V5EW+B+Gm6bPtRWIqkruKpKQRWx5tFjujVqF6FGCD3b7vXi
sE70IINUyUEiWV15yYFNr6fv4btk3T6RAa6ckM34s3K/MWORCanSOTF7JHChtUocfL+jBkRLoIlq
3VTlLqBbrhzDRVBj+ye66mGQFUHUIbnbHb9aNjpfjdAmiwGKffwt5HNagPOcACPbMga4YFqYfbtK
nbHhUOZWMVPGeTSDTwRA5jxjv47Hld+8gSt5kKnWQHxdSNdM6co6hW2UxK9T/BPGXxrU1lG0Fx1d
AOfz4CZUh/2TLWDh0RLMtjhEXwnQmr0nxYSOOGrrtRE/rOWcG+LAsh7XWtSEJfq9nSrTb0Zz7cIl
tELBomGnjpwCURyOOY1oMLEGknvCEd1u5tPY00moyjYAbHfblg9j7s/vfb09nyvZTAU52ZrcSUyK
atBR0Y2nFxPjKLn54gZcsYJuzyItLDHbqdCWC4rpi4hYDVvAdQTobSLPbc4Zs35o0osT5oGckAxI
iZCT7hCKTExGIudAjqMmEGTQH/CC+z28q8uGNmls2e8lh3QKTIlpScMR09oP55wFjaWLcmbQd/bf
PiqbqfqGIo70vmdSXZs4sYcqmm9e/7d5pg3br9VShrayv1lYJaweP0RdtVPrS+qDrZf/Q+v51wQj
+DebySAoH3phq2DTHPGJf7/Hr+Lx287MidOxjqhgzWZ+29Tyub4v68mvrTv3y7LAbdv0IeKbBLBz
1MiPhmVvOv1wqM2C4BHVtkMiEVVH7TKiY2NOtwkYsgdox8oswlUS5tzECEZ9kkIA9/yGhG1oo3e+
lvWX0+osv5fRC5wbEy8XTkiDq7cF/fG1D2jXxMcRd+pFC9Kx/uPEpiNuKHAdTHh3xhziGFqzSNVk
2K0wZeV89oPLKBCLJBibDEB/3AqoSM6vqkeXnX7U1ERn/Ba2QKGM0ea+48/bzb/Lt5vuzQqAeWb9
m8CsjQav1B6pzEzuBon9U3Q5mC8CMuMgH8Clbu2pSNtui5NVNiPEatBIzfMdY/GXCJg78wndyt74
yeTdrdLW2Nt6g0dFfvEl/LuafobvsxTzLxrNJJ0Q6c7NP/ZNGzSlmbWA1CeG6dHnN5Gh0wLGTKQk
aWHweXFxrftF5rcWRysutuWZ9HRLpTTC51life2Ns3pU8URl2ofIP/F2gRn408itlPRkrad378xL
SNboBooVooWqEuGfEOTuMOTRaOgtEmX6WcYsfUjs1z+NZ1s9DP21ATHOkxVI2SF6qhevxdk9yTAJ
XuTBnU9gjDEu5o9tZrM1QwwyESPXEa1iXW4IVt/Kmao/+Ntd9hg4JR2YEt/XP0eK4A+Vrp5FdvRj
+4WdIoQ6s5TyElBtW+qk4nYZEkKSVOzoZT53qGsvkC+nAR/1R/Zqwg9ZPcTpeBBDS71fmCroRfva
5MOLewWGSzaVD37UPxBtn8vOE0zhcPzpPyDLHk3lUY48CqLMCLkDrtdZC/1GYjOF69VD0vuPQ3LV
8kl0mALRfyqefuXHoGzrdD3EbWZafTC1SnUoIeeV0YWsMylTZ6XVbqPLRn/K2PYdi2UgKkAc+SC1
J+zLd0X5WzkC3X5L4HTMufZtuhGzb2uBovU22ucT1zDeNCHeyNSRWNQXZaTIam1YmnyatkcKn55c
bv7wil+dTUynluKX5Ey7t3XL9s0ahWjZehHrsAoK5GQnws4Y7qviwGMElGxYNIBQG7l7rMuEbtFi
6oVZAJ3vHxq4EVzWX3x2TH6bRa3j3XhRaPDZrnO4o1hbqShWoKFAiWymh8CSX0dWUQj5viXwqbi4
9m08/7eBfgpcYJpud/025X3ZDftqRC7BG5Q6Qn4D3r4fY3ETtHnUFImk0q+JG4xmJlE3UxzkNFNp
syo8mCNnXPBd92n+Oz1B7fxR+CbEIk7Pww9+ltyiVXx4tSsvU1cgfKVpyotAI46BsIbm4OMkJ3L7
sgGnvo2ae/Zsvc9YaRXZN5tQB5Vldc4CunlSx88499SXu8KLWOStnhx4D/RagmTGwkjKBXX7M65W
WWg9urbUy0vhBe6zRSrb2tTcI6kNAlJlMNzdiL9vtvkhzDrkcAfFC5QqwwFUR28q1ebOBt2pz1T2
z2qpMhLLl3DLQLCaEvkTm9xKL+FKJaCvMlvQKYXmrq5YKmxKcQdcGZWyyHjQoIarbQJnJ3nTbVW4
ZOdzsGG30wXbbQed2Br7nuaSiQRJSyrLDkJ0mlrMiruTZF1/fAfeGUbABXaLAQxe2EBsDb/KcOz4
BsEzpBfD5L/qNeosfL/1vcH6IvOhXeLvST25G2We0CHJhlrrBtvHQRNfsVsISo2Yp2sz6Puh9ONU
Im+jaz0CjsG8Tk80mZQAEQDOJuwVzXEgadP+GeEvQ7dtQHx15S1NZEKtI7COYMTb6WkCDg0rU1YR
EybVQQV9yT52bW2WkKGnJyfs2JIRE9TKASzc4ECc5WxnSHjTugwGOwnYQkJHmwRm9tZp5zm35eQW
o3fz1PO6xKH79jX3Wl9dPtcKDpbAArgdiTALLqgPa5GGTNBnttamUFU0iU1w1Q8DGif8KsA6oQwY
MkKMtw87YUDzHNbR5iVi7YosuobKTWzWB2uM0YwZ4ansDvat6ONeUqoe9i+V9MNM0plzoEl0jE4M
wDmqLCfrbWYxMUwSQM42ekaakWd57BFZcCbGIPnusaPdITCzBMyJ+l7M/hBGQ4mLctRf7+2+4WCx
8z91PyX7xYOlkZXN4eNjAOMWjZuzzRN25tz2x7piIN72n/FX4f74ivzKknZCCsE2exsJAOy6Gc6Q
c5OHfqvjGpLx168+ecuPrDQGTofyWKlSH+MMQLK/tCXjscFnFVhwn4BMWHwRh1B0atjKHtXjOrv6
w5bQvqay6Q0OE75m/O47oZwyQ8Np1I5KJtjCnnhEolnELMR9eAFe2MDzTMz7cklv/OUIEn4Knm1S
bXJj9bisSTtfNVSBOoCgTVEl9z9fHdytpkgFTBG8uOz248UWaB1tTc6tHGmFn8J8S5gY8jaEINjM
woO3RJwt4/Vz41sMFtO8gZhJ2Z4L/zGx5yG3oq8qjNNuCuNb6OOjAAHD+IajJ9FE7qEB5v+BqA1P
2ZBXZDok1UsDXx6sAbkB9b0/4oAba6D0KrN4fCLV2kM3BIOLGdHVeC2Px/Xw2ZCfwBy+41xBX1ga
rE6k9PLV2nt+88j8jJh1bvs/aQIh/1y4ZvhGRP8EoeDSdlBb9NUCnkr3IuMiIHJEL9m2JpYQH3p4
UExDM4AFeMZefxvhVdu8obQ+fa8jdFm84h/Dd92YwWUZN7D5n5/LrG30eZ3T4kIzfw/8XqIT5Op3
GBsNqiSEF5eYa970TcmFHacRshJNIWguAIw666wZkSH7IX0uljrDTA92CRfy0zCmBmqapqUleUCr
jDIlMefGq1Cef372wltK3XvS7sZDvRnG7oc6q9YNRetHCzPl1u8i/vkhtXQgvo9g21CSukUzE3PU
xOwvdOPER7l0EWB9YFbXWeRaAaMmo1qL97wIh0Ipf4dP5CxKFVtclMfCy+TUoSk8BT3UD/HMRCG8
jl1Zk2deIQ6WfQX7TgxTa9+uhje6qbEAI2fWp//cxomkUcOqJF0tgiPKujThi6VOce2oR/MgfMBt
EPGStiAIe6KCYMfyLm2QjckW/nTjgCdLi8jATEfrMEtxL8ysxfVUVm9W/FIc+cGSegMSXU0MJ0dw
AxdvNBE14urf5ZZPoLkwvmU2AlaN5MUHuquMUn5viw2Yxr4Kpa2D7oWV4lhoGs69G1JntWnYJiJW
9mOk56oMyg8IJLyCyGxAwJvVac3LjFLJemGPYB5s40WnpHVDYenR0cX3JOrxwSc47bEqnSaRaqP+
87fhZg0yrHTcWkEUU6UmT3dPosiDZG8m3FlMsAyoBrYz+e8QhrbQnfd+O748PR+72YShH34nL2aA
SuVm7orL1TCV7sD1sBaB3w2yHhjL3X7lTeoaraW2hh9+m4BpP15WBQ6Q6jWG080LbvBzUHQ8ND7s
qQSzLwXQqbOdtQ3yOyYfMoQOJfkhAZLA/DtKHjhFE7gg9Ju6FH8/MMSxt16qXrXKywIt4FqKFzNi
jtgMk2W8MFG9Z2w/cjnZ25iik2stIQLa2KsUe43nbOr9pL3fmt8cdu67+evDVrntP9JPfScot7/L
8oMs0A3nrAb/N01dDgjGoJ3c6lWfJ4lM82D7UcmNNmiYBmiuROxS9lvKLoQJ0OXAeIu2SnHCCELE
k3d0q4WqbOBrz9lL5QCLewmgAt7fuVhFMDFu0+bqoulT0xkqwKefU3dBp/AD5aFSt/1fMP645YnS
XQyRbQZImKcJmbpM5okXNv4bpM6xGu1RYW3IZ+Nf20EbHRVZcPuviLh/xRzDWbzjnpSKh63R5VMG
Nx8eJL+Uk9IRukTTqVop7AoDdnMR4t6cpaDXNYZH9ec+10FJzTuupCF9kbUrDGHgZQ8Bu0zYgr6c
B4pRvn4F/PMzb/A+S6TriLSzTR95SzuOSc4Is6qnLygBrlsoBiKfwEdf83muY96AYoZo0jIfckJp
luL8zv3KksuEWySC/vMsTcI2chYi+Z1eypqJWV/6k58JlEEKEuJTCbqBgS3Ykd3Diw/iBTEdfAHE
WvZ2gS61rBzNfoCiBebihxLeObJG6vcUI4UsXFhFqDAF6vW7Zg2M7HMvJvQEc5Pm+xsXaZEULsed
Wfj9q0sOB837rK6Do9V/Pyy039eQLot31yE+nCTDyU+AeUPOpsk7LSvW3gbDqwkLBd5eJhDlvGhc
h8VqrBBeaq5q0CvFQenYMhE5WQpuC7kZxnDBsRMDionW5hV9ltQ1LhyqzGnSR31hhwFYsAFG7d3D
H3aGy1uTTfe6871wF4bbViycKYS6XgTqgk+2pwXHmNQqZiL5zEvdbnurIsOZlVW+GnVEZz8T4kUG
3T/lMuj9yU8mo/WM4oh8O96qv+5GsZrSnwYos8fOoiTQtOdnIv/5MD2Ar4x0xMQgT/H7wE9DUJMu
qoUs4Ucnen+WWpllNGujHNqKQuxcTG7QLK6rCq0TkX4ibM8hjlIAMWPBBVW8/iiAGJ8L3A9uW2HB
yO21b+ZluvboMdW4fCQA0Xf4T6SSc7VGL7+OuDgfTWL8/xj/bxMv9Fs9peuBygK7FUlWPgEwO0Ks
m0j+xfeLkv6GH3M9BeXtJvraX68GwX7tKlymckj1x8e96GwOE/T7Poqs3Yy9Ypvax6TeUmRPWNTy
NSlIgyZiw/cfPwSlLzINyyB2wHs55dQcHA1lu4WjPdnMtCdCq9uHz56xCXzr7Ct15LulKVcj41CQ
M6HKCX8iCiadHBvShLe1Yu6gC9ExMqAI4DuoG8qAHIVJ7C5zRuTJWcnvdN/9RyJ8ClFNmTzoXgrY
16BKcrIwPIyaKBgWb9SZXy2Wa0yeE9XeX9ESiXxDvqOpToL0C6KGBG8zhhPqar85cdc4kdIIHWWS
ZDvi7C0EEs3+6WUv4j9bE+/Ad5m8M/Eas1ztEzqnxdirbj8CcgwvYvJlpGrNR05/licCapsRpWKr
vWxXJwg99RXh/bsaA1tTX03o3gfm4wmjjJE0b5+dwnAAy4+ysvi07uIow5EG/Gws/F8fJ5vCZGfV
AmlK2fBnq6tUl2/XVnjqswl/L6xsARFfLhK59zLLeE+5Ick6X0X4mMefKrnQvYqIANYnC6iaKwDe
C022jePsMynATgsVuHQtYL3GG3A/+sndnDNvdSRH520t0gSrx6KRGa4SbvH5OvjwMND72x3dM9uL
CtM8xiKQD4bC0Pdf7qIuvre0843vT0ZL7J2jl1Hh+xMxaQfYgF9U2P3f7jVOgzetRoRvSmdPRglk
lsF11/tRRTHKKI36YoDhWc8HS6j7rsRDUpp2GLwx3w0U0v8azkyb4jWtgTM7jfmdGTCMluuOenUH
Jc1GVYLiPi3rnZBmZ1AcX6tC2h8Mo+UvuEK3gV3Puh6JwSXYLm28gjx0lNmaYMeUGLXDRVLcTnpc
rO+N3P3eisxWz8WHldWPxpJZiSkbTyX3mHsR5jl4m3QTqrqhuXFSY+PkQI600Nv2KAG9N/+NHEvY
HxqQxKoX7iesOUeVXhqVD+gYB3o3UImk8UcxVx/jRoIYMNMIlHOu5C19pPxzA5TnQlw1wbALuQlV
8eHk9XEsIp/1aIwlnQ6K3CfUXDrZen/Rb10JwE0hCinKdztg2BPKrwDIwO+PPdbStQ3yMW3vdtIO
EUUgpFfEJ9xjo+j0DimBunmY9XHngQkgWa35l9Bmjwsks5ZORWj/QbQCt0y1hYEXYAFY7gfKpg+3
JlqR75bHE5V9iU1V08W0bvlpOgXz4iG7DLBFLVfS3cTQIUV7uVtMxQ96Apd8eNNoBnzARoBPgvpT
MLdeqZY5Ib9My9TqIfe8pyqgK7eja47xicZC+1AFbabBVpq9YgIUluKQzr5ZH5Wll2z9PZp2vntl
PCzYmy0tle99CSGtCN5GQMYNtfR/QD62XvrOFzyMghpwxm2jqfLrgQ2ACsUaEvJjyrHqIGxAxXx6
gJz5boPBqVSSnRZ0lYYgu+g4pL88ToFMOyxCDy60EEvcRU0KHzbX7IsxdTvvAYGWd0ahsyY9LWQF
LGCazjJfjnILPd4eVR1psr3ZUdJBld0PlUmOfgfgpM3E7sF0h6EovoFWZ+QbS9MQyHRBwTuvu3f0
zxnCTs8ff9rU1z4ZmeMTQ0OkltLYa6y3v0LNIGlVwFg1BV7fteJDZy5vok54kN6Z//xQf2OtjmTc
p2WBr9c9Zo7g7RkKuKrKG0Ualihn+WaB/lFelCByk+2J1sM6fLrPsUaJPRfalRknrtv9lsBih/FS
pjC8yGCdLFyObbvP+uOJ2724csGGgFS9iLlsV9A9iBNoUD0Vtg3GvFxjeIWMbs7cWUUby/mH1iS6
jGQfxCpUQLTAYfIkUOBGPzUVBmeiMvoKC5u0RA6/Ki7yVnMZ/ZbcE++e5FKS/bbi9VJCYeWFbW8B
Gu9JjVsjbuQ2neqaf+bOlKVS30uClvlEUbncQMvANPaRP+6bixPRQV54WAUW0hGBsPzGmAt8ZLGP
df4U/a7qvWhFfPOUxUdovjDhhoV2Ev1rlQC74xrJpoQtUGn8p0qJWAaY6vCZ7rg/1T5JvQwWsJpV
xaUlsKEIUGAsjGkWsNoOxBkecYuP++s7t3cjsmu5plDwa36I6RX9RSVDlfYe43sXW2b+LODCq50I
D86YJ8oz1+yX1XYL5ZvCWjV5ObFv7Riwv8xi9sv1G6lIHUXVOQ1Q9w9UlIO8DAKBRbQCkfLRHaXj
yYJqzu3iHdk3R/zX2+9x75izTLurdHf8YMAVR/nDG/xd7yrDenLkmyIutX5UiXr9wYzbzkQGZWtC
Lkb/Nm71DrkqBDtVzCza876PmKfqUILIJ716+T6ZJkMutcP0kMT+eN7kKN9f/B0v+nBjduhEmV3M
AHuaXhZsupsAc8JG1chCJcRkAwSU/IcaATWtO546uwTIG/1lHDrwXxLJFN/rMTWpnTgjTfTJEemI
64clXK2pPZO4Cz4IoYaNYGyf6ijghNNDOxz5r1beXEokGL4D5hHjQ+a1ioEYC9KaZIAT85XmubyW
wXM2v4CZMen6gjXxZcGWfmCoxIUsKPCFEM5qCwkOYCEMxayHV5yCy/RUl6CB3YQQOsGRL3gK66mv
MkrwNPEersF9iugI0Sb/UzzxJ9LWOnIqF9EEvSlvMwh8oblysYot7RVGyLO2GjLVcg/eQh1+id3X
Y12/c/iKoHavT22ZZi8EXzHUJz0p8ex8XwwldTZ/o9bdcW5lyr+t1RBy06iH1r8dY/CLHFBXKDja
OrbQvma3303Z+EPt4X/I1nJ9JpYr/bSHl+UFouFpqOiw6cntqi7+Lct8sbE8ElfMxpG0oD2NWyu9
UtnAt1Ogm0jra3qq1cPzYWmkHfEwcSTn1g7ZzgoUD1fywQ9TgKIDjGHwwYBqwT5DlNRSxRjic8Rx
E7a8k51IpsXInkUOPmtubMAJFYugoRP28LrbSEuZau+zdFraK1xwYeeU6bsv6MBmgCAEMCHhqOeT
cz/zyfx2bwWBQHUMq78gHq5fkVGKXU3f8JRwi4bli2xUGyk84jns3scR1nNCUTbqbedOv4lFd+Q7
8lNsSibr9yZnP4zD+jvacjobaryYzDgahNS6r2vLpRYvJY0G8VfbIHX8C8cF5b4Q7wb0dZvCSB1d
rPVfFiQznJB2eL+UX1plB5YALYPyLIhy4rf2Uyx3AicY1OAh8iquoYh3B2b/kMhIRzTFIlmYYaAL
zI39gHISi2AIGTEmMePqp8LoRfANoMp6de+LSDI//SEhDJaPy1GtGZmycBZbDmYJojTxZZwrvcQu
/N+y8AmlKmrJ8VXoZi97fDd/iQcsjtdeLvFfOIVi/S5b5JxyX3A9D2Kmbci5i+F3jkJxE64YX+Jr
e6aUFA9N/xAj+AbszMYdjrIlYdk9AA4XD7mrMSQHHh4BkY08B8PvbFUDkaO67clBX5wGbelDE3tz
Ok52rbdH5U8ulvwj8HYEqBpMwT0GFGfcS1hT23j654Xj4LN/KLbmvdKwc8T7xiPjU2SoJ3ifZiRP
CK4x3g/OpgSBL16ltZJWaDJRD3XLeq69Hf61X59qPn8ESf/14rIBtJjjp3aokRfilgEGYU06W1Dk
pIAvTnVAHDPgb7gn3Q1HUL+7ZiWOZgKnt9bHlrAmCxs93Bqnhusnus0Ci04kpWABOJYu31F5KdCz
i7leAqe1ZdAa0vgvTk97zy+S2fbqF/oF1Ouf+J9iE3VIbe5AO2fTam7GUDGB7nICX2KRvjpLgzQS
qyxbOIVXdaVRRoFsGLfnwWnqpGsHYbqumigFb4ViMMt9sLDEOy1zyqiDp0MpzvS/KnGpJ2kvW2RL
O0B3G1GizIFs7T6lArOwIHSmIJthudSyC+juLgrl1FbyY3JChf2d143O9uHara+rML50+IdFjtwG
WU3EO1LYYkMzET2l6bBBo0SkNs3gl+3MeBZfI47k1JLu+s7FgGLb3HnY6FrHIXuSxs0YHZtNBM12
0IdyplOJZH41ieranKrSClqlyQ7oB+wUTWjuEeUOFfU8jxt19x0TNwRdHluJCgVHIME9R53SSaOp
tcWsZobB7U7fe8K5J8YJCENKTUf+vOcHWFDCWIe9h8XJEkYx0stuaj5fW1KNxFjfAieG9SKxk/wb
ymGCUe0SHoXLaXruayfIAVPy+PNRSPinaF4/hIl340SX8UIt6Fq4aWZSxBZBEEZmMpWlteNuSMU6
0CHnUwBGaDO+/6KQQQCP2VQPuEVmfCxGhbd12LIpzFmuOXubi5i+DQveLlVrL8raBf9G3O0b0SgM
MV87bSE3nZLh8b8d4BG4/zQEDgZkStq8sctNYmtVi7ZmMuVV37I2gBW0ASd3DYedNewun9gvpOt8
k9HAatUOqlBAhZRC7djhDTvq8lz14tvOXKb86GqbFGXYDFQWuqnYIHW3gy23P7kH9Rdcvoa+UacW
2djJyoIRr2LHTg7Jeo+AF1/5fFcbATQ/dsAnXX913xiH/vgG9k3GFMzcLzWNZu5xfMxL/E2ajgoM
gqcOgamJT3PLGyS8mxwBBl+zgghFoQaizIfcyYz5mZ0bhlxC8bi6cHFTr/MJ3zFN+p6UqLTE+BgT
AKTu/q9cIIP0SExgc8w9qcGBRnljIBsL4lV/eLJy1KeeDlEXRjRgxJDmcwnAG5PA3lxGkfiwFU5W
7tBQLOe71Te1hVUMffFFnlkiODY0JRJadj2NkDbPFDi1DBu2mtLCsxclpf0K0noh1YzR4gttr7kU
2Or0XmmJyDdpw7lwoy1c7sWfU6wr1gA+3SiqZg9SKaw6txRvj8nfFqFvAaEl/KcjQVtAbP6DcSt5
XBO8Fgp1Q9xrkSf03K2KYxKCo4KuNc0uh0grQ9Kfhh1tyYH8/WWM0wxm+r+4odOzH5c+EXbGbtjM
mfE16i/Dil137bJZuws+U96YLJyqQ2g24JHIDkwoUTcLr+dp/vEQ1uilctXKeYQ+MXaUC0JphdhA
MzE8tnXOcjmvEB3+14/aXPeIDYbXPNTd2Mq0RQVEF639RWb2UZi0nDCqJHD2pE25NgoZswMxeicT
LJ29DWozMeVoVBGHhQuPUsfLWItO4hg1cV5ZEjtfgIPjgxTyQQuB95H5nhiy3mRjcK+F5YK7Yr7y
jNBxK1EqHYQIwV8otDxlS+mEeiY33FX3ge4GEVUrhppLP7hnjE+t7E4KiZyoNkJMwvjpdzqe3sPU
OLznimH709/E4jMvjJtZ33LJz/dux73DLAJmlv3GERc3Ldm44XQc2xTJGE/8i92A0u0f1DL+bIHB
iRs0CWNkAVUw0lheVzk9SDujGGcf4H67EYMHxKy3/1iAoZ0G1CYYIE4h/rDOXooD8lD62nd3H8Fl
3NXbcSM/1Fjwl14p+XVSvPIBHwyOjtb6f2bpg0Voonwr9V7nz7cQGQjgcPRgXmBHsqHigBb+a4jG
tfHUuyOjZMlUIxAno6gsP7dAUfvJYusLWEAs+GL5hPsDYW2bKQ3Js4rYu6AehNIkZs0oZ0rP1Bxi
W0bxaKe3lDpIEicvwXtAoIVBnFPZA5ctju0kC0oODEbW09Nhv2E6GDMkHdMHgnFvSsd9+v/rtXDL
XGiC+hvgGbNGx0hvEdM93234O77Vvie60tQxkfcX0KOGqjE+1DbaQadN4a/vZvtS8hicRjQErLLo
BQymdnNLCnUiKutkI2Z7/sJzCnlgsIAiCQMuZ0uwH8hs2PFPgkCnFWxW0fQv0K4Dym1RJXfCtVPx
0PPZMYr6lyp/S+yThka7ifmAe25rAZdAE7d34jMB5C7YuDtM0P9NH9NhWByyCRFT8vPHHmt8Qp8S
U4f/X7w2cgkOs+k45yb1TLlFKYhNm653UcYs44sX6EbUiMCCVtE5HaH2n5nyF1dMa2nLHfDpoA6n
/a+ey+Ght+AunfyBfGmMyDSPEk9Vc2LxJMGoz7uEK1MeLuAPOY8VqsK1k+0iyvDeRl/vfCBJDpwv
eO+J8Q+YKaJCBiJWszmbjrhkX4sU5hUNojVbvw2P2UrItaGi06Le/AGHxoi8L6gvk/7ob2vuw0W+
g8rsbVRO+En4+ab84q23etiO3XLNZO1istrAcTfIqd+Tuos5mVwuWh7/DWWaL0obBBBQ7G4wLT44
9ZT8S9rkbjUa92tovY4aKOGg+ffhOoZ4YSP6y3yFn+AK6+8hNrIGmtu1RUckThEJZqgIh8WZxlB4
6nxOq7n8dHdDSTXg4U4oCFZsxS2u6Z5h16oxtpUNImP57K7m38ejrWDt4ESONb+XbG9T/FfCJ9VD
A9m2tBc41mV81CFRdLS3c0WKzlT37MBkDvTYUlpLTfVK/kfJdNXP8PmvhRERvd4Y9HCyUnKpzdEw
ra/oj2NrmEnB4ZKuwAz2n0ARh4QHnUS9IwfT6E+7yesppqZgy/PBjlAwFLEbE+z3vVGgGOGrppLA
Eu5CYtftEizNKYgSysUAXjwrA2JkfJ0fbco/sK7lZeiPID7KelgDhTXbiwgCLzUYDp/IkOcodc2L
v5684KGXpAqg8nCO5pkE6H/uddEA5N610leAkaCEb5k5NDWCWFQijNiW8DqT2AoZ/PYmYSr8eeZQ
3wBRpKAhTna87HfHDIAg2Pk972+/K569sy+9TeZJI0vr/tAxYgP/TH3K1g2Zcl62pjcZfMioOrTR
xJdaDhvtYuDfov73f4oj41MzGEp5G+I9bUE8phubR8ycxx0drEeCMkUkFMwBvoJs9WO0nbwnWGir
bt4z3CP/8i27wHxMSuRCCPGuFsW7MLhtq6eGfwBG5yuK2eNLIauU89z/6xRo1ADW9DFUiMSgMw0J
Rffv1x+KziAAu2hchhuebOaoMCR+U6JEP7xx8uT9GyYaSC2dLToegrJZjEYzO2rPT4xOsAsRaO7j
DlTwsYy/P0mH5AoRW95H9IGvbVq6cE29YIy5ax5GC9xLLAnrXx8SIpdOZVvj9E808DawXpuYI+Q6
5uXXn0Bnpe8QeyzJu0MwTM35D3pW0LpSA6bjRHwoPo7qgsJ1NF5LWtCyu+ynfSmau7wwhMFijeJI
1P9cygfqBjCOS38Bwm1cHBIz6DUXSjU03VihIekExpbqb0J7PD+00CkJU1s9vYJNcbPzl8DArz4p
BsUs/NfZBn/3ovcYElsmVB9TqSGg+hw6fsAFHanfAEVb2PU0RxUaESS0M5HUp9MUQ/ifE9mPsLqz
Kp5atXu+/wddt751KwoddBLzZaHI+WvvjDZCzr390tCezGZoGlTCk/QdfRy7K+gG3c6NyjHbMpzH
wG5aCiQcL3b7D+QO8zGnjgP5j+8gz7GSKZd+VzNXoWBOuHcvDCvf9YdanNRQCVuoA5PzQv+eZDVL
ptycPMsn6bSnaIErlYvRwYuAWLUiAlT8lKJUIBST/QKRBirP/tH0KfBzUP/9qUvgQM4IEd3f4G5C
GpSL076VQLhGgPqATpHs9HTlZ8UBWjyQSoVJJmDpu9dcxVfKhMQjhr10gCOdtr8u5qJgB2Akz002
qw31KypBGw66kCu4EJBhqlHd6NjMD2fB60tbXck6W24CDRFMgyi9zegR7zZwhKI9556yUUW/RXcy
OymGF5Uava2uZCA+ZBCt3Akp74/0qRlTDx9oD/i6Q7//IX9fXBsRec2dWmXJWDLEEpIWtV4MA6hm
8hDCg0s+7AoUAb19Cr4BCdPJHvYEODXFvN53TWzrP0a05kkpwPjnPugvVPcjD93aau3+I2Ofkz0F
GeLYadsQzQncBiVt5MG4gf8hctDYI7sefEzM8GOwxs/v71s5Ra+PI4rbnVvQmhCDpbwSEmV1ffHi
e/L8hCUuSvVz13Ije1OPujPCiQhVFQplLUx1zoH1/7em2gk5soiAuN1XIQ30VhBLaQZffoBzR9dE
waBiFSc7IitRKGbEAJy12p0Z1zaIjxW0toJc0cC5/ueeJKfZvs68GDybg4Sd5i6US1+CrRj/YHGC
ty6cXPpdF6fxzbT/0H8VH8iAhM/ZLUJRc20Kz+0Y/RborqqKL8x/9j0caJLuUUms6qlwlO1tlsRd
43Fqzcoo1dOiWygVUz4StBb0ndjtywHfDqs+gn1bJSk3iy5VwY7oVhkeRKKx9o95NsCfJyOH2R1h
Rr0hu/a9THwbOwa9biQrMFe4kwNdXXqtE+ul8qa2W8RIHmiyscBPgasBmdzzINs9fn8Ab+ghSY+b
hit19ThFapHz/EmsxNLjljal3oXsEv/IIXd5QvRDdwPB7MF+kgs7U/qcVvKboiM+N0qNy6ihwQDK
wh0iPxUTyw4WQYqe/BYCw4z/eJMkYtjxseec8JkqvM2YfSlG4RH05qOvgDCxJppMRAWxilCwyEea
xbMhXB8R6jXt2EW8bUp+MmGMWdV1yVdDdwEf3rTRzcsYMP+ZnESqC11j0G/DIIP8cDA5qoOvARiV
jNgHCm4EbIAHCJB6q2wZoS8/UXxgWXYVPmRR6fR28P8uicTCJMtgL+B1cMSNKwCHzgIakpL978HP
5cdeE3NeS8gpvHjWA29urUbBr1pfcqsglYcSgDhSWjghyywC4AfY0tUGHt3M+onX2lm78SWWsJ+m
uR4puk2+cU3x+iuhivKPP+xvtAPFOGKpuITI+hulEbLXexTlS4ovLhe0BQFtnYW+o/RMmKF7ThQW
CUSy78xm/sDO+JsqkJn5dHy0tJb5HFBTBrL63FMwh+wub6NfZzB3fbNY+byUIqLU96728d+7bXg7
G84kIqS0yuZczOrUYAyBFxOuJUwKf/55SBMWmhA+5ee/l78Fkl+F2xLZhw2xZ9yd5zeSTsQwqsNi
eKq7SMV5w/2t1Mq1zWNIE/nK8hQXsEUCl1E501/vsThecuX/40XOM94oDTcYBkp1kfkF2TLyKQRk
iDZZa+Pw3rrsNCufKj/RQhSxcndpnqBVmL6hSh7P+Q+nEHTEaYJtmnjAL1Vv6ZzPWIWXkikguP6t
GdfDg41FSPImdg+zzyGI6Y2vnfx/7n3kfQtWFbCRgY7D8h4ttn9josPvjsdijtNaRsZtcoA0XIzo
DbEoISVYnFcj32BK/62sS+O2Rw3svFa6j5XvaR0z022zD0Ia45ZeMnjL6fOcZDAnvSEsoiavxCO6
Wy14FkTepz0Y7w8aWt4qVoDvxG4qsNhm01l78yKpsM8+nI+Q2qekAdaHtsNvk4pX8PRK5Dk+FwAe
ElCsHkkJiZfS15W8IXKJt6Y3FlqAttJ89G+drZeunYvzRncvRCQdNX8Hh3mVVVcEyULr5ocuv1sv
aeI+HEnayUfgKTpQUVS4xDr6j2QeGXaFT79apwomWuRxZAzBJNsDB8VC5p6ighSrjPbTvOMmK68r
fwkQppygamXqNpm6tOIzOOOsoVXmqWgI4mJNmXjlhQKbIiT+HDXPrkpOFKa/Sl6unaSLEUph081Z
c9qVVxOAl1ogONC6+k2G6PdIz3GwhbvSkUzDOl4NpYARvW6/rtaj5CYOniujRLH+e9H3Jd7KX/dX
Q1dyMh00aUj4/deFvTuys7oS48vmFxu4l61CTTfo98ZiK1JIsHj4bxMDLvrEgUR4K5/TQWb3VmpH
Y809Jbj1cmhdooyUFnydrDEZmwVzyg7Me3+wlEZ+Y/9YjXwXeFL2wa7EORT5a8bKNU4NBQFWd8jR
bW/+033pUpLtSl/kq6DjqSw/fFSM0bhNx4p9KfOjAEYWuLDHh5G38dwwEe1eo3JuLXwRwGX4oty7
daYpklWmZpAaGrupQ+vA3ZrdhQvHQxBuN+aLw4HfTNY+cEILlAL3ElYyOe5LQbptWVNjFt+gL6lX
y8lzGG/KWJtWYfP/lZoCvjgTudLal9MVS/WiaI6wk1WGDLRItdeKaj5MQUuCpFv/kvHOjY7u+0X1
MRSwomxUWHh9ACI6nVD/aaG5rkIpyA5mAGDgWiHC8//RlK7h5yQMswuKFu6BkCq7JYHN9qBq3NCp
pacmu4o2TxU8daFGLW2tywgHWK6KWQiOSX116mEa5OCQ5eglpYk92lYZwjBvJ30J7P6aMSWF5aoO
XB2jXVZoyslqbHhKXxBhBrO/ER8gIa2nVPN/t0iEFF/IRSEVtBmiLPm0qj5c2QG59BQ6gt9Hywwm
X3XgtjKUImbwRHcgsjnFGTN2h06YmjVF1stUXZuboWKbZylRMpyEwxiyywBKSWU4LCmmIawcjB8T
uQ32whRXVsUGvstlJAREiwBKLlY3dScxzC0mj3OCneRmrj4LpXJvezGbNOLXudZa1ARQ87vCqKv5
l0t7QhawrMXLPejl3KBrdnFgbuFtFLuLJsqs0szvze9e5DS1znamizx/TfdiCdiw9GPisG2/lKta
t7fvuMe0TJEbD3ZDZx8Ry5w8tZhgBjou1oByh3DuQxhzO/oiaWONr1Kp1ebzWQFPtK2h5Vd1GJ2A
m3YCKjEsoNlefUPoC07mj0C4giQcRKv2DTXD887iP1TvR2bSQP5VNKe96KxKXlDpHJ2QElkwMebb
7esh2JijA5hGtWC/PI5szezAOKTJuQBBg2pVx7v1qSgN+RGkl//Odw59zdKy6LyAwRp2jeq6y/UZ
C0aVWjm/uGldCZG0oHK594Qn1GM6Y6loSclZmQTaVk4WVmCr3CrwDMELnEYfbs5jstJ6EbcxcePo
cQ0DqM1vJOdJQd4pSXwD/xq8vnohFY0nXwg/Nzb68++2d7HQdNgyntYxkEwNm4jtLv6NBQQsnX9W
mB1TJHZHESRq+ufTnKrH3YG2ZIb+GfnPBhPVAtfwRJTy2zeLlfZ4wUzB4k7/ir9Rk2h8m/kw5HAn
PEe95PhWJOU6kKOSfh8dznPQLqEKwyrLFqtZacPA5+HSmsHQoNBd/dJJ2W6m+zySwqo36xesNX5a
TDcggHZcCZ+5Q2PmMIaxjkleCIGT5HUOSPkV7U5hLfQ6W+VY6BvVizzcUZiW2jxUbvGyWydqJ+Yc
v1jHj2HDXsUD/PnuIiRtjXoN8hbQ6b6VgGa06U86lxRFS0xLaTZ+YlwRXwNwKk92ry70yBfR7f5k
yCRXqM5NA3f0R6NXEO917GNKYH8GZV8ZEvWAt5rKLcOAgBSl2MGwnpRORMWAlHRUzzJxsGnAmA+e
PVlpY+CfZorez5PAq8NmfUuJGUo0z9Rejz2MsO0++Ct8UAM4O0HJ4t//iHB/D9b8Tp3Bg5FkTPId
lSRRY/Iev8wl6BrxBJ/K5UzbmnpHfU9l2z5gHLIYP8AH1htqZTPUgWcc/kMemIC0lvz5JMNVzrXL
x/YBm/xLL3LvsaowvMlIRip7araP/IWIt5DPrYpHJf9gAz3A6iB0e3FDF/qOlXXi/UNz3VniaFdJ
lvYEn+CkORaMMOilNuD/OXb+3UxrgccyToxmadJIP99x7LTL+7AiLPt3LOPzMeLNJNN0EYsLMBdy
Ul6bqL4yxAHxCXyHgu4dZJRHY12TspteIF10jF/kx2Ydn1QctUl3d5rN8ctHWTvRl20AmIAvvsHl
uK+vzqa1AyvMJTJQumrbeh0LoS9bVik7b6IhVRrTAyiXZ3i6OivR+7TlUps7IPJUDQ/qG5Y8IJfP
5lOtWpINfglhz7QFz+LW4WuRh0fZrQtfzntCqeDyVjJFLspn3yZWQVjWGVZi5UK1egpAAi9r37ER
2Pu0bZTswHLW/Vq6aMb08BjV103fjATv/foOeLk8JdvLFkg0W9ib0hbXNE26P/y+uZ5Q0GVu61qO
K2GG+yTjMRtHjm1YAVj49gU3qM8rSwmST3j2z9ry3xI9gad548BeSXXV5kqfzunjbXkcX7sWPG0J
DCTYoSNk80IK3KfUgTAUhgP9FwgwzP2oH1hZPMEyYWeRDRDxoaApTxM3mNydJBuNY22dGrCX6Tp8
gkK4NCI3K8csU21e3FAJ5J+WjKMthTzRgcjxL1/q62VodkHM/IV6mzXXmoMA5K+B+Z6z5RY0Ojq9
xH3cRvRf4nemPFjiaHD5kB46oLBs516D0Fc9RFx5xtkSfe6ULZpI7Srg5RfmmkPz0wfXgOB+plES
7wLkQ4yoJQIrCdGp/SOgZDqItvieI8ExXECrV/xa6fxydFQTunvKzOiZ64KFnJMzNLzDSEH1+LRO
ETedBwDA/+FLUKFfEBWBJJ54x6GfIE1KXgdiYI5/cDdGXHhRpU5Tl35k+a4iRlx0ZXFbkTa5D1KK
5PoZMWdtt/KuxJ0vNJbE5WFatsQrQH//brnRZus3qOAAqb0uiK8JL2c1nd19TTpLmlZlVxI+jg6t
RJxO8u0u7Fcw5/NIjxznfQNEc23On9ZjDNPjytwZXUoigQ+guWlEkKa7TvrIQAWGSl5dRmM7jBjc
akPraY2K1AhE6Xm4rxKMJYFk2UJ8qU9jvBIwPAMAXQY5dGHPs6ZhMIYOANb38ofH+6Gig6jriiWP
Oeel2HdbGCQpRfFjONEF7DKz+B0+ld/SELe7nodHT9IOfcA/rOXjKSvPHTPLpwMSNnblDa3faoHS
7Ldj5sqHLD6ZqprkQSxfwZD9LpsGIUrGx+npyXMwnxr3ixqIQ0P+xTKpBTdSIIPayQXFAa+8fEtQ
nqZtkEbjbNCK6tMVGX6n9hElvAbxcL+xSh4upCzfz8LsF5uidIH1/YXa9+B6eDW4Q0YzRS/rmbxU
iVD56ZJIu+nS66vP5bWfSCFgvQSvFPYgX3ESn/prVeCRsTnAi110kw3EC6hoSjmt9FtwXkFxYOeu
UY4XIt3Domg3b6WGv7j+OvEBzhAXf7mj80/YG/tkeG/dnw94Z9nnsyDJL+1XRk/nYFdBP7EHdB0O
/ZxoCWn88ZMFvwtMnoOZYJqxje94v5fpKAGA9jkf8Kv9HvGuiZPTqE2L35o0STVivUPGRdjaZ6+p
bVBg5zB1cQhrS56Glu56ktfw+iXj97LfTWcdSHLI8depvGSfme96OMmhTauuEx5iOkvmt3UWWzV+
E9xINbG3dVsmDNupdaRelfzrwmThWNTnVAooB47tpd/Bx0MsCyrUf/RBs75sc3M9VsrXRk24qo+Y
UA+2N43jE/XRkr8sHyQKXgyI5RAXgdNT3ycND3XFzSzvs9bJpA5jLy7ZgdDxGtLluJseDlwoTzSF
Jgt97p91a4t7CMl7rs1Jtpx+Y6GZ2RFDNfodq8XBNgWyBRJFygEFs3HDP1Y33FUkZMkLX5gP66WC
2FLRTKCoHc6gb6FPenVzHOtfw+dUqXBFMcvHS0hEvg2HFj3iyIO5vlCxWmcvDl6H+jMeNnGA6ccY
5wtPcyenvrokvYXyIe1hJ2hbze7srLikobL+U+hKFhRZY1u4p2cphcsQaY76DNs1qvIwWo2ueHc8
B+dIYvQ+UyA9slpZE2RP2uLUdmC+WO28gRy8WD2Q7BaQ4A8rEmKTBfgqtbbv7JlZbhgPPsZ+gTsP
1I4S5TYcEGCVWTDp/h9ecPt5ETvxIye6i4THpn/bivDE05V9ALjz2ZQKAMn/hdekOffKAWLYWd9M
ZRfUdRXDLrWrRoB8KJm7LAV3j7t+1/xpNIIiZtG533n+qTWHVCTuLlfatvj1PQu8ic+c9LqTgcta
6uW3zy2NcQVXnIom2phw4wcP9JSb8e1jE1ePiNNsQmKviSARst8yAvKNNKik3E2/adl0d6ELo25i
eId9viJlg159XNdkxaQjD+8AcCSbeUJ8sOZ274B5oCjbEu9dUpVUiODbcX3jBW08QtNEFUjg9Ns2
JuUEKB2KlcZxWnF4EkrEeaz8QlQ3r3s0DyUhJ1KUmqIWBNkemJmll3o82R4185nfk5PfB/eUwUuX
T9hkdNqiESsGK9bB87xkAHbiiHU1/GDn2VpAN02tFI8M7LgCowfXpu3qnc1spGFwWewHpoC3HmuM
LSw8RH0uy5+88PU20OsH+0PeJ/PyDnZ3HMnZXpyeemol+Er2ftbKMQ5sLK+FKxZ4iDMdidZLI385
bmaQ9PFqNM7WM4YrVzgEf/KWH/hRzkUNKyMOjbBPXKljIVgAS0T7hi6BeP3ze6ISoM3nY/mc1cpS
U0wv1vrZoeVDyTzaCpwtWBFC8tix5DpJJ6UwryA1ZMVnv/MXfd/4gqp16kM6ua1bvYEImcwM81Td
zVcR+7n4Bb1twtaSBH0ff36c9slU2i/zn41DIh3C8/3CDwM1fsPuaHSOQu96qB1c1IBGbRh8Gchq
2k7BsaDydEl6QyPnazk4mpIv5f+sHpbt5R6x3Gis2JzscFLSinSqat4oi0GOKOSopt8NQ7T+sIxJ
67SoDdQcNuNAA93LyFsRR8LJL3OeXtTAL8RUfrgp2v/pUl3AS4JzyU/wy7ZSSY7drSeSSSPQkJUl
SA14is9IDZ1FAfZKHPeVajxTl2DMoG1S9j+nF8eIGApq2a9qca7sKP5tcYZ9eqdon7jNjQjhz1PY
RXURwuykuwc9qFXpsrQ3y0h6Gmc+Q5ngzEp1IzoxTgf+FQXBNxRHWY/tpS6a/0AAwO0UEGZGr/8T
OiWTQF6R8kiVk7dvtX4rduksQTMYlO95mpyR9g+8qIiJUMEPHABHSV1jDcFDIXo8FGwixf1+yXE0
QJu6ev/EHgiA6g+sKliZA0UxigdgSSRnx0xztscyWs+xMT5J4FMm67Q+OuEEUhozr/7/JipFMYUs
uoQg4oX809M6bF6uM/4AuGRRxCTdfOc0fkXYW3qLqZ24duUbyODSlogwyH1ml4IAZ9SJVzs42R9j
UEiflAxdyTAkXDMTLb7RxV8H6dcTzeaRXOhUpnZpeZkfmm8kQY4QoefjLhvwXS0k10FMelkYxiIY
VkZCf6K3u1MOlJq2c2WKMd1ogaqKKgTFRxklHFmiBclOvMse2XCpt6RQ1xMUdCpsjomLn0L0Y7Ta
83aR1L5X8Y/e6WPVSbUp1VhIFYIis0BwZmotbKpIwRybMwMEekjbv+QqxJFfzd5Bczmac9MfpgsQ
9omePawxZSpcBFwMF1J5NmLXV88560oFjD9KkJQdKNmAzfNM30QfGNCARH/Q2p+kVxArqdjtIfu8
tOHoRYatNHxSotKMtMEwIu9491bUtcparPbiGIcHS+eU1JBLNEt70pfMI+2w48uZwLi8QSsLhTZd
ziNfjnNKqHUqV+RDx/3SBte8iTa2Js+AkIF43O/Ra6OaEtqlre0mUfCIoBuMS4TmL9XQ3NQg/d9b
b7gjEV0khpxISbyxdh8e4CHrT2ViHpUG9DafnQhZvvaffstCIOqPxe/XBJFDpPBUJ+p7Jbj/MaGS
h3/zn+ia6f8ougnnzmmZ+gh2yNNNfJqzb9YXgFRuK0ekYwej/fAs7B8uU4gpscP/vNxixp9WXUeA
eeHDeMwr8wmZDeQJMO+PxJa08eIkStRCAUyRUntVmKvgqWZ4m/isnCfzhVvaJw2eqb4ASkA6iR3L
dbFbKEwn0kJ+8C/6zT7CrNuR4VUnDHqQVO1kDg2Z9iL/LD2kGYK0wg/iUmvqLlS0AAIAo406x0tl
bYRftU4q9n74Ln54RCwpHeUz9xzRT5KHO8c8p4apS6FknniNQeqig2sBDuZ+HuWcxlXqFzgV2nQi
gGb9nA9O1CdAogn4/mdSY1/MFVAjYbeFUXwhxJbH9ocmpQl+cuHs09hTN+TQJQynQAivVw0pzlfG
tT8Uj0K+f6D88BjI3P4Zh6MXob7OxmDiRHutB7+S04LfwWKjx4A5USNDac6mIdjO5NfmoxBsAU8E
2LuB1TC8g8bGaG6iJYQ6YyI9ho2xL+zmncIsrUQqrDZGRzByt4gFhMgeBoAuAuGM/6K3qyS3QUGI
nCA51JFFN71PI0urYmAwbQPH0ZO5PX2McxWIDP5SdWid32HR1tcPN7T4wqM2zb9n57sqnfbAaxMl
c76pVtNgzRytRPAM5/ueGU32mIuZOlqMQskDobhpJxoMOD430zwLpnOpRC7CtZWerPNmYd128/F1
RKe7NjyrSEMTM6VnDgi7ioSwPOkU3pBS8eFims9AzCV2xZbMjgSRzj1HAhC3lsxmjzLgmJJQq7Co
D4knj08vJjbDmyxbggqjdfB5isiNcb4TryjL57BP5MFiW+fL3yvbgcCiE0WTno+cE4TQPD5R+H14
a9t+zMvj0PtbQknDoxr0MeFWRLO50PvRiPiaDLm7AV+PmyvjLaGPuh9Me5BzBVTPIiJzmm1ocHCW
tVp9tu+DqEFx90j6AR5lMCc2oQNhOr17wAO1Pldbctk5vgimPvD7Z2Pjf+HA+DYXSUUnKns+K7UU
Uv4Kmy2XyVX6YPZl9BuMpgwWR00SGvpTSefzKgVnBN7J4JeVjomtfhmPL9a0LstNuZK+zpEdvEu1
Q+LKkIpg542JZ2eO8ZvSdPVSL4XCLapxIYjsH4xOl5PNEBXms1eNedcQKoDuJy4J5IZMHf+s23OP
mG1d83w0q0sJBMU3ue75upcdB5Yrcb3uU/fTcjCXjc3KqloMBUbtyAUgIKNvHhHhm8awUUFRiU/g
GiTPqa/8Sow5pvaTrq8xen+SVwO3Nusjz5Z+1QJTWO4I+HZGI8fcz1Kno523K7AJfvy+VelIHS7C
By5qHTs4GIX5SBV+Rpy9V2r0PgcJeHu0I131jFiAMcTo+N1MB86R/9xHpY+SQAwUazuwYoyz8l2D
G4KhuC8bev1cEiC2Pxcxqf2yGnmZPrkRrl5xb5qGdlV61fv/Ove0WJydbRT50sYpqPvio1z36zuq
/YBDPTW+gpxlPS7huODyEoF5SJ4lXYVrR3iCHyi6bUiLoxboZ0RanOINFGozFNk3ObmcvZeBcazk
7Sc4jJ+yaXhlwcnk/m0ttgWFqinmBt23g/d4zY+oyqCJPakuz5yvo/Y3NQbCKzXncWgmSVGBax7d
zyvJbLZZ+2ruyLjuwrEb+iCiHV18DwQFx3b+hzbZ5jJYoBhBmD5nctXKyWZmrBXLMvtfigcp33qI
rpR20rYK8hTQuiBO6FD0u3IslFkd1FHSEyFLiKiMJ2Uaa9xBMEXwa2Tbdx+cldBYWqqDE6lz9ro/
BcdRUE6d8P2dqon6d2In6JWzLM7xRYLzAnUoFo1/nj7S92qaAks1sz+0p0pRv3tTk0Ay/fvlxmKF
l3Zauc92bPUEvSSp3+INPG95Fr+XILXsYTUbpn7MNI91ceE+5ozaUuwgsvLrdxjCppULyuu3RUNl
b8aXtjGQSb9fSpN6wb+AuCaZ04Wwc+cWQjCNpKWpSazSZRKiZ7Ji4V9Tr8SswhE5I3hRmP5psi22
GO+bzATAbZ9CqMRTxHEWhzpCGYtF9OnFjPXPoQF/cbdaT8eVSkZAiT6dtfOXsJvPZ3RQuttZ8Tml
d/P0h8HzLcHaJbro34xLZx2NYpsqmd1Y6VfUrm0t028LTA93ZVIGqjETF4/tWS9PXrWaHjLL1Qkj
Hs5ONVVev5ByWJioeMwEp22J4PpvEK/vrfE0yv1pZ/rrTI5kWKH+l4VCP2f4e75Vg11LpZxWmnOq
3JzvhLyNvyo7n/d7KhPN0S4PdsBtzEhV40roeBd96D2xe9Nx5qfGzQVoOC97FPkSv6yYIFJPn+Os
IwY58CaZAsiuN1lT+kUbhgSY022LkUs37HxMRX8a1lRwFiF2+h9nHIj3ooyv1uLbdKwddLcDFZus
+nZHS7zL1YygxpVZMaDsf8Vk48kdeWw6dIXHrrJKCpX2f/WdOEqJUlJN7RcyqEd8e4jL+9gINyvR
ULr4JR05u2LLpJ4cAc4mikgYySBrsnnqHpwfXm+AejZMGuFzw782bb+qMCWbct6OtUA3YewU8Ius
JfDEXpznxaatiQZF6Q7CTveBhDFNqKfGVr2wzvb4B17yNpJI6G7mAjrD96BRcrwii+X2ZXOhqXqx
toe74Lgj8JPOCdMimsAahgGuwvrmED3lmsHBYebmOP+ZJ01DVhuKMpzruiQccPW2C3EzDoVAzBkX
j02JxjwKHmu3xKx31AJRGSFte/mXg0mPMRui7xLuiX+XvQmJaVImMOfh1w935LxXZICL3CG+rWe2
yGBydcEwpWM9UTb2P6DSFKKYo9cAyEACKRhZtQ86RNf9l+vBroST0SGfjWHaVwR/53Ie0lzz3s/j
c8r1NLL7oCRVW0MDdwHyNhmVz+3STH5zxMhnD1D2cNs/kgdfYgGy2haxj7qP1ohWr7vf++sMhTWT
hMUoH3UEOqOsj2PuhUTERhcyRJ3YwO+hQjIO81JZS2dx0ktaECsidPbzJIrAb9Ck4nRNnV53p9V7
w0SI4zucdB7i90jSVZoLwZ2wcVFRIxP1MBUcmcJmwee0cN9mGSpyGlfQdAWIdGzcYtvDNLMI/BQ7
LngTHyn/OFayawPuRaC79vSqhvDsXD5hyH3NRPTU5fIFivpPhFh26GpUCRKkhMnBujCv1l26gVD5
wHkg3wxCTmn+r9xMulgAKXY6tpNrvY+xhWcY6NxI6NpvjVeAX2vCrgXFiJzQueCsckyDZ66Fyx6B
t5yTVJ1CjJCNMTq+lbcA+KhQP2OFI+kUn8kEWQK4T6rXSbpuKUI10r88emSxzpT3ybh8qb0EW+jI
Ubuu/kyx47KufdSk8Iyr28Z7xClV/ecmZb4PLk2IjwnrAEyMuGeU+D6oHDLq6AKqaAqxRGiAJRm/
KucylbKBHAfRhmNFyzNSQ8IcMlmnqtOjNU3EfkVP9t9K92W+61SCQqS57PibQIbVrGVN+pV6r/4J
HO/vT8PXcsx3MmF4ppXNcnKK+uu1/Y96ERyBuTrTmDye8x2R27Il8ddE+cYnsE5dzmhJCzgQziLw
aXFTCmO4zt8NoNjSzWrjTD0eFHkaPKe8LwGC+t52J3BX7Tep6wOhx8XQgBQDsP0GCYy0i1oOlE9v
0tvBWuB/UeAtGEerPfTtymEG/TngLr3AxhyoLA7TwgVsLnOZfbxp3JH28IreFgzODcGWteNDKT2N
F7AGuFr8VmC5NbrviPbP1RS42lYzCahTI5K1Z2/qawO40p7SDeOzxbT0GJRdWD5RAYvcxhL2mRjg
oJW2flz/4b9KH80fK0EJ+UYZrAFiCjtlOfYtG5+0JO0pqMRCGtJ8RL3yaxJ48HonFqnKYoSige36
quJRo2LGT04HH7BhzJPU6pLeP0v8QC6vDuLH5gHVCx07paCA+LeXbV8tcxYyJGItP43t8uvU9JTT
XXn9WMGs++5nmJee6ouBE1cFxZlIMrWZf1G3cE9T2Be7/ZFwp1vdQqMLXAk9tYPw4hQTMqUTgAKy
mAxscjt5oodKhwjcvIt2qrM9oNdcUr6fUHWj3i7oN3DAB5toissQEvI9inPPsSwjuBiT9N+gSH6m
5K1qbka5ivwfUSTO05d+fXMY42SXJGFHUhEh2IhePfx8sQ/0GN5tgFxbcxzkCt9TycrbSk4bPEyv
4p0hM3ZfTUjB2wdtxi+WbJSF4szPLKBfw1hcJLuFdzO12SwEX0+m+szbC5HxUuYTRfEUMrRiUTMC
EYZrz+FrABl9rXZs+aZdnqIUkIBKodbr3s2+oBojqAHUAjS/tvAStR5jV2J+YlDt7lZAMsE+cReV
EnrXK2S77AWvpv/iapDcLoj6c0XKxBM3dwtrhCo3yBZ0+DLJPrIChGGdB096IQ3UziDpmEZgVib+
5/jhpybZi3hww1fgwyR1n1vxn01WdgdK7kNueD9kpZkBnRLXI7pZ9XaqWgwPYPgksATsYqeBr8zi
z3BiKKZwh7cT9ShNzPnwSrI3zMJNC+FkldOjEnmqamX2rpruDRvzBKC3VrCbLwYIKftED19HqTnv
Gx6KDt088lqOe1V05/hzGsR/1QspgjdTfXHmCQtGsHygeyomBM9hjz81vkMUbe9Gv6UCf2cQYuxD
O4x80NBkrf/mWuaspEglNBXAjQzwG7+eHWIPMzmvRrPD9GSeqnsjRTv1ij7rCum9/D1nDontiUtg
Ec0yiA70yzcrFmn6uNbJLLqwajhwPMNZZh+Ihm6goNCwOVKkjN4qE9luNu3+jODL88YusXgJ6gIX
MJS87Th3rjeKtwpiFd44jR3SKrtJJw3D5L7/tmobk3RUKbAwpuWkDwpPjnt/lXDZ0U1Ker7znMip
vKDfBxQn1wkERefegVASNQebhraZwvJEIXPkyVGu01/vMtTBFGylhN8S0d4VacXYHXg8aFG84oh4
bjr0msT495AutuZf9hlrJ/OJB8QLgXztVHGLGG9Qvj9199HxjxCng5jntDcuGwX+1ZU6PLjQvXGY
oVipJpM6jH+IWqkyRKp3G8jtoUFZ5zCFSaVDq866XoTCIVi4Zp0/8zSYa0N1o71mvISuiIGAHb/X
C58DEXv7dlPKrm/QuXhlOZKhNg5NNy29k28Kc8CxuKR6Rsp8cthqdAhZMYZ8c9N4GPejVnIrpD6T
SOjiPJmW/Otl6wbTiPTppKdBTWlvWzdwRKg0z0lnIKs9h5XLINavLDctChSQo7EUlARNcYgU88zM
xr0WPagZqKkyJu0IEm8/C41Q/6lPQyXID5Z58Kfhfe2Ryw6+HHOZEJY8BzaL75avkH9xPqBxsn4W
dvnK51nWDqj6jlYep6M07UpTxHeIiRJRo4bsDlctoYlfyO0jEnqFE2YbVRPtFvcK2foRDyI9BoD9
H4J5vblGZDos5pSt8LdND5zCawJJtTOokjv40ZHc0MuLO1h2NAB586Cb8RaLkePvQWJnoWsR9eEn
mVKGeMtIqQZ9f32RDOM+qR37dxob6klgapHt3CnXhu4zQZEhSgfhplQMfuzLcFDCR7d+8ozFnxtW
j05LXgDXg9C7j7ZSnqCYBavByoK4vhepoZZlc4r+lJ+d0miKEenVQKw7dpQA6F0ab/ENgZjNqF1Y
TD0t1P+Pym0PCjvyYOpNTFJvKKF/+LH0w+2ocz8/F9Av3WNRjqutoXxDlwkL0po3tD5cxoQHRS7k
NY5BS6lqqF/E2Bxs9/jjOOPfUyPN+j5ahbW423Tsy2RsRVv5rYWTacgmKuMnAHTSuXfehGgmH5WU
D6NYVh6ncfWt7Rxwx/A95CG6p3U6K9lhv6nvsxJSeR3ay6XosO4T4RPcneNozkctzw96j+yzr96v
lO0bg48lZO1K5Tr741I+dWyFhENr/dieIg5xWPIQjgxqTuXURaB7JFK187yipmIyIki9f/Kk5xJC
ujKcnxrg1SGh5WROzMxcujRXkCeV8blBTuXreiqH63GvpdO6bbF9ovcSyFiLe7CEE2vPVebNNNAK
pxEjv1KGdGQIeYJ7xrU9+1jWgdpksjfwscGo7kinpRBHY38RlpnuS8WaeGvaGJ8oDpPYPltBrBef
hIY4CEkR50B+EAUks6Y9gk6DJw9m8YdpeJEhlLh1HuvMmuJ2z+LI0oV/II1SlVKISZqrPDNTd5fp
fsM7FGKZfxxvPpvOA/umyo3NeKO5HyOCYng2XHJRyQwZM2PPKuhgmAYQH9GppGOEwAS+rfsfESQl
HqnWIbh/EZPl6IGtBG7RQ3lJD1kCOfRMPSdgpX4rrd1Wm67VYBudV9IwVWvmqtdZvB8vVHigpYDg
bvw0RvknrE2WxE79NNXsosDL8Qz1BCmqLRL9Y3nS05VAJuQb4iDZlPpglq4bIgRfbqTRZk3vKz8D
7sHRn//SFGDIi7bEdFkMfO9iABXKgo4TPPU1tPDbC3ARPttPSG9qXT0Ac1GtpfD6x7rYSN8tROYf
qMb2Fq6+tTErujjazwrV0zcz2Us3sYKDwndXKJFRGijYUgLFFRXWd1qLliR8HUAwi7XINuvgg7no
Egh0ytZkHnPQZklTDMWCRRtAP+qoJAXLQqajdSd0Xmcoyk2kV5dWzri7Lohe4FL0+Bzv9YoChHQD
HzkpROKMA1HRnH8LTVzjmFLqnZVdW8crAURsy8+/+iqzs2CZyhPfaNVP16Sz51cyLD1W+gqgfgXl
UWESTufPRpbBXosoETTKnIzvUJQLHP/5dIvYMUHBO92Am+0HXIuyQc8ScAZAg9ccnLgi6zNEkby/
Kgyjz9EjlBAcLumrjxiGjGGSzU56pn3IdA3tAuDykjTPHdDeCQIwJgvFW962G3UFyHG6ob0Hxlel
VhKfCdOGAbLP98RfoFTu4EoqxZqg7Nz8sewedZBydSsJSgbVJrxO8RnnvniCAt+8pboQAwTWAbhi
mo54soZDR1OZ89lzLZW/8D0ntlxi2tVDkovFMxHnbqilsLBjnk679daTJEQuuSUeyqyltC7PUkde
bKHuv41fcfMHMUS762pPjMZ3X4B64CCykQbHpj+S5DzPmhiOO+KxrHAaHCvk3OxQj2QBV9hcuNN5
Hp7s76Zukp4FAE6a4//EEVj18yJWE8jQ1pFeGsETljjRDduAhv7Zkk3vqMvO9GOLdZ0dvmwvd0Et
MQGyYQh8i3yYvHCF00adMuYhp2HDuGuq/ZTva1TMPDMvmweferLPY2aqrIPXp98nO2hX3940Hczl
8xvzeow6b5kXXi9MmczBAr+tuy8Pz7OGM4xBV5AjVgGELzCeUgsEv889S/cncdWJlHJZ/LYPqas4
YvPol/B0m3S0GtbjcFZ7ytuMCUz8lLz8kojqNgqj7CiF0AHiXkR7ZOl6Xm6/IP+0h+gyi+t97bIn
GgIbEEzkBCbmqKxC/uWmM9sM8DrqPqoMqKn/xbNvunBwqV3G+zGHyXGsTbISV9+r7vaWE7PDB13c
A/aRiVRsc3viXd1tbrNp7FEyRW0/YjXMidKejFXCiUhagKQlE0/rxWqTRvhtwz6VJ590G0MydmNc
/jq2x//mxaMdhYLBYu2gSSbyMggfQMNO7zAfeMfwDyGs85CT1E60CFusMHwwsd9CJRiY8xcsEYeH
mW1UWirao3OKjyX1xTKPR9whMw/UlF+wh5aegjAGjHLPnfFyH0q2Kml8xTe7jAWGpOhXJ0EHBdR7
YW95I04jMUI9DoNus4lrYswhvk4DuTVA0okrDzP0odDMi6Ezrgcni8dSXVdG8GJOs+thEk6/U0SE
rwkfywbHxYcUfbs4ypuyybN0/A1/wGgephQdCoN84hdufUVbUxLHhaHIqNWxQrjT2x5iu+mcpBET
dIc8Xr0xJvsCKIUu46ywDrfjrWFHs2Y07o8f4DbWvkXn27OhVGhP7e0zuq+OCpdI34S0NztLHPBp
2l3KWvmSKN7/fUpipnLIvOlK5VJXcm072qwCxTkrtCJ5vAmjNyLiSdvB6PLzdQsWty1+XEOA0iT2
lMh6f+nKzhAe/1g8WSAkgr8H8mRDIbHUauaniXXPEcfrIxzJhyQGoArTp8B8REv7uvlmm7bq3ahs
xykbiWEjV1ZBiQX5HQ7PG4dJzZ6au0sCY7k+TMdXuhw7CL2jrzY/RtMUaZBqICQqE31q3YvHd8Fp
WID7/jBHtT2D9bSuaJQARIziy0EqxijE4LF0YmVAHX/tDenFOe12zm0PzrOvUP1KY/t9dJs1TvXn
j8vE4m0Zl0hJ9pElGkn2P1MkXyynOT9dZRGC0LZPEgrUGv1yY/9tyFpbm628C+XqcAswKlmPThAS
xzSHLXokVH4ob+gDgmdSM4RiHVDhPO2H2gNXfxhECyWfvE3JP6QgNENKft15KbXNp2tZs2PoWaJ9
X4y65c83rNVU8U/vZJK2FjJXilLXcBKqVOl3CleRkgD3Nh4iQHJPosakpXmGm2XNGHTTHZHseKi7
m5AfopOrcWe/ntc5/ZaV9ZOXmiswjAiQohTfjcaUN5MQteVXGYWDZEGUtueZ99uDHVYYfDaBOZkt
MVayzBB9iOaJbIKWoj5lKKAV0AvUaXL4sysPolvH02pxbztQ0rtZbv4aAd+vrUruLASD1hGhbm27
HJgheBS0L73kQircD9aR2WP3VFuoVMN8l8bof2+YUPYIrp09Q398+FfUMnM4N+LtYeeOTty7vxl2
jN4t444hOfKbCxTX8ClteOWDKlZRjG0smZySrvG/irPR5el2QIDTWEZgAoe54DoJupoEpG0xM0WH
16VPA2KwZvsoXTTHvHFdS4KkLsAMzmyXQwoauAIxWgTPKRq6AvJtWlTRLYt7EYOyzQQ5e7WpQ244
9UchZdocrkYDVjuPbqA8S9N7oHWQAxtjoiX85Kcawz4FaZW1RhJu6d6YVL6DA7KZ3S7cpaLRO/KT
abGI3rFPKskokklPfHMiUYxr9OLKMf58rmaM+XqrE45qG/VUHvOnn48KGWl5bSPEFBT5XFtR0K5u
bxaKXJE4kRMdgxfrFKToccxYK53dwXGX+celbwjAbXfmbeSlJRyJenITOFk8c29UvDxRWtJvDs4i
1jGut2rPg05ZAre2afIJ/gZ3x7UA+MgQ0S3jxIhL+qpvAY9y0fIn4tTV/EEUduNaYGl9ZTODLJ3G
jG7UYp7kQLqA/81mLmKyETVU4907brzfeLyRkcFzX8BxE7qraq/7BKxdUJmZyPVzSZIu/zicityg
3xTrcCZ1qVbMo8GimC6CJ07PpIjgbQpCOXaM0crGurEpEVTFUtfZGkcqa3zoi3KSjx9/SdzOtLri
33TmamW0+R+NN/pZMO+DxPN6njc3launsHHrO+g+9HAHqWT6iWH8IredD6Fhi44tbVZjWCdD48uk
8JNYUOlgS1Wkuy+tqWfsoQkkQureY6ivzEY4VJ4rqQajuXFpWcHP0KVMlX4HM2Zi4dOeIaY12tjC
An6JsuZjOJNyx5ijxivdmuGaEHEsiVYiFZf6TzQc3qbdjX7JY9xEek64TO1zv4KUuY+qxSt0rWkd
eG8cGDRftrxR4cyKQQUDWoD35B3SqExK8zELXZ6QUjTx2iP4N0mK0ypzZRqvEDJou4bctxq2Y8Vf
TMTksc9LM7i3ZxS966AhaPqULNR+S+k9WyiJ0YUTE3IjSWq4DYrU8ryIajJIZQDUw2CpfZratmuH
iwF4+dyy72ynvez56n0WYDksE+9bhE/AxrZUeCeCwehd8c+6GEA43Un+/vHitYVrEY9c9etSaeJJ
Og6XULhzL5XR8llB/cbHtuIO7o5HyWdnYPRcWL/nqV/mGiDfg5Kccw8ZwOGX8x4hKjCw2c9Jel/a
XbYukQZpfZXQyCVnKjVRDX93rQV1emRII8iygUPX932PLLNVCATjl5PVCQ8dKD01AM8yDFZQoWj1
DpURpH55IW9XhQTNgQrn1Ai9dTLiFMumczDyGq1iHGUL4ItHnYM4LbMFifvk22UMPuAZVoHtO/Xf
D+lOHM+/4bHyEmKewLpQF2S6Qo/7q7gyvafMr8xZ4EgdTyxoDazVQXkWBHYhDCItVfBtItCfZjMj
2y5cvngwEKcA2HBMx/5GK4WNDUgFG8kJGMqLOnhSCTtqUrfUkXWD47xLeQupxoqGhc38UJxGjelW
Nhqsps0Jp7tyHYF3dHlpd/bUT2YaQ4mOYnxRPAAqjfI8zdQfJiw15JE42L1J7LpYCW8z+N4yjwEV
QcOlaC4SZVB3m11brQqYxh3sJKFPBKP1ZqGRbLaBRYPFD8xFvHwicQva4RebHYJfYuMwTZI0rnGZ
8cdO6Y836IEaYn5J02OrG075M3LL6h1hjGmHOQ5KFXqKF5k+c8M5jd71w5ccBTg2TS/C0xOd2/vb
otgkPAtcaIJT8uRcD5vw4Q5wgl93Xk5g3gubD1DoGXgcifXmpPOY2DISAe7ud4enrTZnTvMv3Tun
lv2iEeAXsOFzPoCERDrt2rL6PaWAnB288iH5PQ2BXviXufYwTg7R3TDUsxFSU/B4e52hIW7pkpBL
VW8ZwySVu4jYO4UcJDMPHdI1qDumF5L5SBSLmWStpwKHK5IkfGru8oHl5Lw1Anz5pQ22hMbQYPkx
WGqLoXkdzyfc/NEP3KTE1k8M7xtjRntB8QoZvapv0B5fBENb3DDsUtK57qIPRfZgwTQip9ZzXnQR
0sherIeVkcvTUD+fPvcc1XCTb6vqqVtlFJvkl1NIH95AQhoARIZ86kfLm9Kdf6skvGkbTzM5Kaee
BUdgGQC//8cUC2wK1xD0K+H74jYy95hyjsQB4QiZUSEdEAaUiWCGkjobCnjyQpxTKndJplxQoiyc
9pgCR7yaFXwB5evKVDxMUa7/B/TnphueXXIauszwIVhC59+QG9ISe2pHN+6c8fSsAPv81l9Q4zxc
U37SMdFDQUdjMcfR7+OlVEtibnOuoAlwSb1FSNNGTjKaU1yda113rvVQglAGUnwQvAmJWjvcAH9b
OeMk7wU6+ljbgl451v0WDUJNpl4kpGvhYA/SJ3zi5tpANgKE7PL1PIvCBu+IJlqkhRs/9t2j/AY2
q8671/MT3qJZfhAOTlUCm+aVMebxXvA4tJVz4V9Pp6n7NAUqr4Q/AmAfd+iqe6oLmjXQn/Ww7I17
34gSN1GoO0MergWI0MA7oD/KUPyQeSNzYGl/vzTCapqS8Uu68RnFZ3WL3G5ItcUWGLsHfAdbBxgd
/yHqTTwP6iyPEbM69oRUQPoEgfjcY6eg5Tcu/H2/QedpDPVIGvW1+rtDM8/wOtFds1icCM3letzW
rM46W8zWR+23+rBuYJm3bUXk1Hz9Qh+cEnk7H5u0mG+NeuynQYOwZrCQfUMGfP5eaf1cV5YSxIaT
hwMSzBw9eBvpwU0K7ie302hIllx3V1ztUPUwFn+A/+ZXDfJ8ocKeV63+Z9LuafrOybMJzy+Kd7Cb
jfly4jvVlh1cDAiuzdd1iZdD7/FN0S3m039nKi+L7J5F1Z6ulrKH6YDAI6SCQgX/m0okluvbBCrB
uSbe5y6O46Nmj7Jop5SnCPfIpquLiLx0MmWLjQc7qFaM9Aq25GvaCgfNkMxcHZa6ZbgZjuvPC2jW
qYadK0yfo94u8IjH3d1vJwLrbrgeW92bJH91/0n/1ZLg8awJdgbo19MbNDOOVRVsF2NOh8sYXIiM
asnwl4MsN1Ss1g9uHQ3DaujEugCyZjYlsbgHisZqe6WoOHdY3E2r2tfrnvGiQbpDdvMWF+xDVJFm
dApZLJEbWqVI3ABZyEOoytdWDdP303pvfLTEC1wWvCq/JUS7h0WMSJBTfi9CmZI+DkAaoJFCvad+
KOXns0VNaY8gTTQ5MkKdNJcIKX5nZsKI+1ar0mPgxGmaOR2qzu5HX9oL5YomUb0+JVW8MKtx913E
TZTFJQtXaPCDQvbEICF0hKGe6RtxpNjy2BlQPD0nzG5AU28vUf7e9T7bLvAkBZFX4ykQHeQbjT6M
VCvqJD/fCWMuiDZi8mO+L7S17MThw1/+lG4Orp3uZKao5uW0lEBdNZnt1U35I8rr6dshEJekYIYD
eiZYhzW0Iv7oTElDiVE9NG3bS72Ipuyf9YVNosg3w2Wybw7EshEGsYbA20r2s/qwrQChOE23G5ru
+0wZxWLrcS5IrXLPcyF97gnGIqLARjNkFEUpXhll6XyQ4plX6OlTosq2gXhjeFZ7ZAdQRlIlvLOP
PfzrU2mgkkMpSNkUyVtR3kMdD9XqZXwC3lezc1QP1Dm6Rte8eTjOnzHM3FGE0nwL2sGmjveDaXpc
zhdqeomTA50zEHOpK1oCgESipT3hCJLFpaJIt67nVR2Q67s9B7ELaGZeNHxnXSCZuBBmglJmRJw/
iOSGeN7MITM05Z7LA04BJGQWFp0uLxsWDXkrSJSzYHqLGGb3U3HUUL++p8BqCvufSD8Z/D/0BJwO
K53fR9vY2Ukvpym4Z9C8SUt0eQDZjFpsgcVmNFjAbK6mtFPwxchA8HImRBExbhrXxr4lpCH+iloG
FE0VsagMFvdaLWAEwAsAhI8/22wzMslke3bv8Bo3frW6knz1C1udGtNSF5Q3o5PPrBW53/UemHcH
o1RXNnfU+nyRdWiV/zXWp2exmhI1xM2VZ6LHlUQ6iCqD0P1Z5rZ8l/TroQmYi52YxQkYGvz8HI0U
JKkxwv6QvI8YEdztj0WIfk+XvuwHw6tGtfNCTb7z38JYUMf8R9LMH+fyp2C9RRv9DNhRVpxv3pzL
V/5zrIFdzheA+3SZUdcKjPY7yk6nmG7vJexmF3t48tpGtaa50RL7WZerfE6fZPBrsdjDL06LPGE1
7ApnIqH/fwhjNXxTKLGOxQp8oLVN/i0Vz0q3dgQs/+ldrQn4DX5X4irbLvPSbMOSeZ3i2CWn0Niw
5kiAQaX75xNISsLPHRMjWGhGGdr8lxyrbD9btpEjXqofNh64HE7AmEVXfhII7TEHT9HrI4QqZQff
qRT46c0UuyAfS4vATINpagWFolaoFDvUWBv79q+R8UZum3rFuxGC238h2ny036oM/51Uy/xjz5Oc
PojGUgpv13fFR+QALioMQmtg2igchBy7m6zAp3WWwHtje1ECZnmckLfE4cNG309nds7Os9XRSDrC
0tYZRMvzKgdJM+CYitxjXoGvpOJ9GjFtyX6CG2YbMCkEL1JVsfmmUTihW00qUyaKh0pHRKlPhdZ8
YFvYCHCma88GRuWwn9eKL51IHHnXSze2YlOMuBLYTHyuDsoZ7vbWbwatTGXAbF6MNIoxo0NA7i9b
FdWO/8+BUm0mT8mq6X/HLK+a/1tTuLW9Axv2LW0Dkd5q1BqtJAPBqB8/kPpTNnDqEGaCl3vK98dQ
IwCmtZje3OeZf8hTy63YanWUJESho3K8wAZrxStThB6cycxy1luRFe9r0veAZpdeRRusIRl+7fks
GDniwh78VAtdNQhbGeTzGABllmahMW+cIjcW3CAtcuwAaxEIuAOnWZjwOsLUcMfxEYIO7qLQ03JU
7zgaN9KOG1q7j4qrh1MsfxY7rKK42m82Z9JvT3Hq9we7KzPHEARCe96FJ4Ytq+CjAZvQGCX1U/9Q
AbfadGw9pUidCZ8sj9taWrScAJOfSNlXvn4zPN9e7ntI2Pe0lOwdibZgoqJcrUi0BNIauvQjetTM
L5+rXm0Xp5gmHUxk27VqJ+bcdQxaw1W/XzhjfntnOGhSEAiXAN5opgJOP4VK2CobSkdss3ZL6sxe
8JjMiDZ1ZHnYVE5zZ+1fSYJoNkxIXI9kOlIOb4IBsns1rIKW+w2poLeBUSa9wyZM2Ps2F8heXY4i
vRiFccBdcqnjICqLn1/PbWzLjZMKAm9b5G4TebfMqErAfH8X5a8Ybb90z+/6lRvAYzelDW9pcqZb
pOHBr+uKvcES70+x4QJiq7qt6neGStyeRn5h6yX2HHb0ihbBfjeOgI0zwZ/0g4Ue0hWVmsjHupZf
EEGu9u7H8PXCrnDgxhyAzjp9+a/BiyM0T3TFIvt2TrOHcYDDX6UP0oRuub7FCiwsESCebTj2M7t7
sn0SuJcfSO1WeeotgJEwpSamAdPLBuEb21A6nHdVUOE/0dWYoJPiGTPp9tx6hdYz4DWkHFPwsxrc
AcvpNp3zaJwvqIEuXXPXVRXWdJT5tOCDBrHHa0jf7WPf2RgnNmaRGkVvNeFxfuQJjG8iQMxBNjbV
EtMRYJDcfoeH/obJUjrLXOGoIjcDjvnK2viaBc6fRfAUVbKlkgNmy9ytb17sBhnEmbiEfKqQoY3q
KJ9+K1j3Uhbb+vWr7g56V3TeO1vET2HKE8JSZw/aU/TBAV4x74vDLy5H1CXWh5Enh3OZIEHVI0ZD
uVwEFYWfKec4HutBoHUzd2fMQBqxHcnKFBWR/jMX/36xlAfdRrNr9A5SoiePai8//4IWZjTgVPUG
hftVBrIpNe9UPrq49wjHXjbJOlVopDph478M8n/YQEXsYbuszrs2kTMgLI5nOZjF/rkM2vnvYxRV
U9DualOx3vDivWTbCi6POGtY1a/TjWYSmDV0fOq2/wseRxv3JXTdUDuk45vbfxwaOKcWW5et03s6
u6cbV8S0tRQyggJ5NdQ0w96l5QKNLIj6+FNnuyIBebL+ejDU2Zgi0WAQAYg/dagjEq7b+d3Zwo4l
h8k72tyvIU9Pkze0DpRqvAHLzHt4CO5vj3ec5UDwSxq0e8hq6q/iMSSSTZIxbFkRvYzUVu0yOaIH
WLgxaZh9ULrAF2HPj/XojG6AYmttxz2wvEylU3pd/4tDiKAqeD6wxg0AEC4O2aPqSKI9Q56o8oFT
DklrXhar/UBzh1z7RdwAqM3NrG/9HcXsA1IfngSYAiN4BSDxRQDwj/MoEBFcIzO7bpQA1oeuKnKr
zDFbAaGslFMuIhnekNaWjM+tkAOK06JzMtSsmUHZAaGc4/NxcuD9nJXg/roGGLS1CrlDhcvhCEpu
Lq29XbT2zIGNKzGBuhPkN3hjUU6KHRSg+brqdIWvKimiZTvR+73oN/ise7+vMafdXozbKZ/k0xjz
iM3Ozk+n7xWjnJAW3E3FEm9dImgcsES7ymNYYJAoh6vHzM79KD/mjMtFp/F/o7Cx9G954U6lzXwx
dFCYUrMcUWGDzVW5AN89uYZxTT1Ly3wwml9ux887wo4X5i5jEgRHaurBMiOUcS/Ej8aDeCdcEA8K
2za0NneZ8RUPK4sFEKr1Q9zEiJXfHVb70mZq86mXOT5NMUfcxRJQ1HcHiGv2gPGq+12KjyU0HNej
Ofo9JcwIrrH2WvHKY9s6K6hhsA85m9LZw+503zDPfNH515SySiDV0GzWqaB/1+QXTJO/wEywi+R4
Lkak6HmwLTz4lUuajLVS9SaLbHvD8F2rRnpu1qSMoascrJKEyKQ66I4zJstehW/v07uiVFTLJSD8
nxLACALU+xXEM7IMRZX3P69GUsdLTNThoHfNnSmxp7N99zYXZQPD+8NW2Pqx6rOIGLBMXtQ5FFEl
7TgOGbS95286FDop6Ot41vPEn6IQfmq7wAM3u7hZtyJzEpgMkjJcFLSItfKCWcLleiBGy7qiTjfb
pSiZ4R5K3JZFCURcsZyxIK1+p/5L4Kr6zTRVhK365kuNT12pT3hmnDYtgXDZKAfnJ7gvxA52dVo4
+x+S3b65ZhRA3kYP3avVLPITFH1hrVugNfDI6QT4ZZk2uOyla/h7avaSouK+fznKo+x0mmAIjYED
c6kV2LGP2qU4i+fZKU0tAfLCFAVDIfzEFoFG8vGAdlIJH7VuIA/h65Ir8r9MTxbik1SXLpC/+6L7
wf44nt2pvy0M+evtI0mliaOCTeurlU9WyBxiRYumPv3PzseuB2gQP/VgVx3SKi8PGFI0rPB244yV
iHHTK1fBEoHWVueO4PQiNkZiu5nHfdTAqrw0xx22nIsoRC9e1Tr/luXvQrsIbQuneCs4XRjcnODh
x9ZjBP6UnfMOA0nexvOz719/CSw3tgXCayDbFW3E7QxkTalGiP6dBGrEn8As5mdP5zGE/TnHJtPo
57sOv7XgIV8ILwveltGUtcwfn5C8q5lNFe1LHtyPmFOJn3olQw5XS7AwoZaYRMLxYvJ5kpndaTEd
JnZJnHdQsHj+kRXiAPAuY69IIYZIqo+CZUHdHyYEzd8smrW+/VsD7NwolV0bYDb52nhkL2KfY8xo
MNw0O21pc1WqUUGNxzfQ3BMe7gsBTIxIaFbr9/lHqOVf4DyUgbqCggEAX/rnwDCiUjaDZMWwgIO7
KkWWHrrS10Hu2T9t2bFA0kxmSvyw45F1CTmE46IJLBcxXb0s/17WpFAQBoX444xSovptdMQ/Zz2B
OIKcaEOhqD2CcQXydvzazZAhcFdcqhmjnh80GV5BdZ0aanpznanAdAepxkzEveUGeaKFEA7MVFLo
wwBp2DKeOLT5pPQrVhILBIskwEOB783QyI4yzUeqWYzS2hwWX93Ytc5BqlrxUS/17+krT3xU496w
LuRSRiimX5FPvXz4PP4AnVr1dg9sYjJUuumx/KP2T04eDYzPRsMEZ/NxprWttr6ZHRpfNdlq2WsN
OV3NbM0Pt4UqU486O1/VIkm5vawNLe550WpMbd79Ou7cJEI17mKquQDf4vr3WsuWgppy9rU7XapE
8oz+cpUyIqVz5sTgjR57JXZMuD0YKCoXmios2Wd6R++PQV5rwipBoS7LO/h/0DnTOutPNIgwtEV6
qqGnYSByWqnsYMEMsjzXm5F+0uBNl/uFBNTRpBhMVAempIuzWLnp3xxR/paE49Pp1InDQXKH64oI
H58zlMMblzlU6vgJzwzZL88VUa5MM2e+CILm/4q4QRbP8l0GrrLLdi1YJvYf5wzbrmCSLoz1JegF
g8u9jVt3tTq1GMzthiXQ8fYC+sSzOsZXFUlMlXgBM+VNSUYl4/FfQSrZO9CfLdZ+BBAb7JCRJLV/
xQJpoC/bWK+3vsmTQvrTcQoZP17KvxGDKVXVNSfys8WxFqJXli3DXD6HOh/zMlpihVAdPE/a2Pba
naQqSjQoyTZv5STDm346HPE3QBxddgJwqKfCqT3N2MVb+6V0ld05p0UQG0zmq6HCCPgYNaXnOZop
xClXsc1P5TbHIYMqEMdt6baWE0G0dWDhw1VktUxfvMwlm/YcLyy6OR5EOpb/MrUF4AO3XaL4KzyE
9a6VEkmDMub86L3kc654KIDRtvYAbCYQsYYWIiUb5yWrvOym7oXbntp5QK6FNIij0plGZLdCrxL5
y/lD8uKWcwS8ys48Ty+2cVnYZR4jajvfyUxbekY0OqSC/5/nIC7BKextu3eJVZU4rwDxhpi8F0yT
Hoe+pZjQeBzaauD43DWzOjOfrRtBzRz6CLSg1gtkCWK9Nyw4+amtQp5a5YZWugaWwuFxuDE9v2Wi
FX+uBwRKXmitWkqt2W6eJFwjQ7ohw9cGlQwcweXaCqNuQ9B5nQHttlyvwGlwwS01YdaaCbcx02nv
Fm9a5izj2yCTqcX/WthRrsgmY65WKUtt2fhGddWzNrAdzWfh26I9UMN0sSntbHwLgLysdmmDJuCl
kO1ksY7F/2RcNuX6KPiEjaGioCd2tXw2T6zB9ZIUFEoAwmHr/oZ+dolEsVGGmKcQhJ+1sBvUtJXw
HNcRC04JksWLkFOvIZsZ1CmZ/I5faGfX+yP4IFRdixbxyrp0wNY/ATdRbU4jS6QRgLmpMWm9ZsgT
85OzGLArqIIJ9mz/0mvg3nkJhuDexWyzxF5Vqow5xZ5UzpA18ePyChTgfSylDxDsHVETBQaDyQ0o
Y5fNU9kEyRm16XiD/1uaKbNvVI34mnNoqFAimaRInch36S2vOETZM0dgUBJtNdiMk75o35WLQkwW
MBZeiHgYHOx5GN8SGCZNbBkHelUaTht1fwmy7r3DOCugYpFiRxocrKJLBL727lU8qDMhfGXd54Wd
TLcSqmcfAF8MG3H4BgSUCaaZlyL2xlaXKRhxOYceYSkTblxKxks4aTsIgcY3A3uGc0u5GKctfJId
boYuIvskQyYXtOUxp1lDp91aS6f4uQT2a+/6smQbVTTVmdshHxlalZKdbNcSr/tWCpQ3ccKCwTrm
+nXIStUAc+FsyzR2QItl9gvUhRfALTazqr4euwtYPMu5IhzxBu7danklPsFuStny01e8N8q5aV9y
Fev+cD6LRzZGf17OKFKrMMhUi9DsfsA87bAcSU2mdTNbguu4ua7YWhzGEDkLz8v2bvgjVgPYi+m6
5bzwX90PlJ0hHHvbYkYPm3GUBWhJgVAw394zUXtS0o+uwZWxBDl5ln+WlReCUOGnr2sz3Vr9V7JT
ncH5sfy4GRZIXG3WF9ade9XDFRjkXgy9sjUJH/yU44zNX4JTpBkvjgjivg5P3RjHZAfAnKlsIN44
Q0IEo4ptYiDAiBWL+7UjZkDESJ9pwKY+6ixsN79WrsTutW4S1/TmMX5nbOhZ5COtxEnbxZRVL32Y
TKB9KO4A9sg93Wws5GzjrAnMCTIlpFlXjj//ECuNIPGIR8VKv3lqpXpU19Lj3tYJNYS5s4jAgc/T
KYS3ub9hTOIIqF8KUkIRz4H4FvO9WjeLx16IdDAAG93YUzSfo6E4m9KYiJ2xLkOO0H05UK7Wj8xq
S9TiC5oie0vGeXYLir48UlswgEPcyLhhjHzYX4lVl+9EHF1pVNn+RUF+jOUK7auiWZQwLHxgn2nn
Uh5WJ8W86tOFZVk2Kjhlrwi/bsqhhCeYuEKeo/1r4MypbKw/LNgVyLclTHiQafjPbTthzdoREGiF
G+Yyh944cG2dqr7aTSLuauRXKAdQlYOSNCyXDeNYM3vkLoQ1ifofa80so21MKPSCazH7aebF/YoB
2+mX+ZGZC6A+ZEwFEmBQra6GB13PLJWGGi3KBLbt8t3me2YzQNdK2kc2AajTANi8lrQ6x8b4FqT2
YZgOMm25roFWoSvcjgWLEBpvxtoMtfwPmcyZWqAK7QlewEgoq5t/VsIz4hsxJEkC1TbA5AjBSLOT
UEUfYPV1EcO4duc4/IFWFgPsv0u6O+WBr+wZ5rmiw4LVn3fSIBNyVObSCJr1QObAosKty0kMBtSt
Wg7L8nwyZeZcG5puVEX4yqYFE2dyrk6fEE7+Oi51WZJmwJai7F87SKQiEeWkhqhXZm2fR2dJFN0U
+cgVHveuc2qa1ZZyB8j+haJMkuy0e27ZgKOz7CiTbDN+PE5amoMRuoaNQxcwrnF0xniXK0iLi/ud
HoOfdI+uQFA6dAQIkMdrcgGt6cJdavk0otHveApS6U8z/mycsqL4JuVHDKGzXk7SnAGcV0akZkdE
/K2HdKsOdarlV0m3K+HaQepMCk34wjoN8KD/tAWmCTsvyosy/H7pinGnoWogDGTQs5VWh7dpfrh9
gV4+6ZQ/+WM9aXHXhP8uWLAsFZqkghhH61aD/Vz5tnPnzXOt/bIv/Sc8nKdgTm0/KKfzfsxZCeFa
Yzt650q+nklTgZbYLjek83Cac0n3oPmQ7O1ggNGg3297HRHDQo7bULzwqkk7rPU1aSdIPijrHXKZ
r3POfzrgYXA5TAa/Nj2dbRvMPDMdK+x8LghTPHfeswSMKEaIEBkcKTMlKuAFBg+A6vi8sojK48Yl
gRbGw7D9d8Cf81QghbJDb33OOaz/P7zBFgzS1cvircdqkqYDH/y9xCsrIsxH0Vm7Nb3gTBnSl9ET
rUBM8MFcbPO33yAfXn2/50FfsoP3BECKMKXxwM5Z+yO6zauPRQMckcDAdCUstQTocaYLZF1g9Pjq
tBoaeyeMd9JEZvwdBiIMnNJdlWJCP0ygo+Xm5lfbv6cmmSRsF6L0p2EoT9LLTZNPPD4SJ/r6Aar6
3AOu2UPBO8OPiVKZTiDDra/pZnqcm4c8JVgBNf4oAGAK/ykX5QrEoHoVHgDoB+Foh5586huyxs0w
1ZMl9R5o/8PDSI5QTKxbCPrtibs/7BRPiVClR+kXd3L6sXDqsynQ3VAttDgAgmYcD0bEdISGSxcn
v+GQshK0khRXgm2Z7WLzd5IoeuH2LPDmDiyxbUlBJkHYEuP+aUGvOrDPaYSgQSy4bwb++fJJi9On
w9jHNcnggbjd+00PW50PidyzArMdgo4wkIwYAn+8wUW+dYF759qyspZdKN7KMCTIrV2yrHoEbGym
b87YjygJVl5yBafgC6ZfCwyqykFSf8qTAXDArEcR4CvG4IcT+TPRAHPyvy78mtMsaYTTXbySmN+D
0x+s/zi9Az5BEJiKdtlI/yUCdtMvAtMWQ3Xv1sDYLm4Yd/GeT/tzm42sETjgNNiADleq/2cfiard
9OMnuJaL3ccmk603gCSMagsF5aTQSRpvkt9gjbTnJ6/Gl/RvAROFLye/JjrYlqsQZV0vHu10Oq5R
44p3E34RD32cCqpotVZYaBE77FmJcChXIq84N60BTcjXlnl6UVeGrD0TDFls2bjbmP0vrwsK41fJ
cl1SdDwNaFV4ewWTOAGUj8yLD9Ret6Yd5yCSktPZ/iIf+ME1OS0iONjzpUW5UOvevBN9vdbWqBo/
gDzl8ISskLS9erYmCzADfU8qkGhh4w4ijYoubruPlrTiKHAtGAmiLikpSQ2hI0rFmSvPiM+cezC7
4s5/1FajcUWAZZiwiTwO9ZtRfwIXbeU83PxQfkoGvlSf8/BRlhnV1mm/lhqdlXSDC6TeQ5+92KQD
FG+1qQuDuuhklFrADsXmYtsVR2QbtnIleZVWqm0fq66/mtWOv0FJcABveQdM46kiYd0CDFIYFW4C
W1WLG5L3aSTHgFJEnh2Xyy16gwaW4OQ8YF2rFPkWGgawBsY7d2y2DepOO/t2FJ9oE4lZny43Qqvr
PFE3Tb/4IYSG/tj5NVC3gsfMjT08AyGqNNJyQh3BXPDsx93opLN2R/cutRXkkOmMd6GJQwtF/S2W
rfg+XsbuuLBGaGFJPyGgew92B0hciIvqn84VEMbwJknFVnrrOL2VPe+CK7Zen1EfPwODWyOnTGJT
2x1bBErZLTeO/myCIVLiGF/9UbLab1/uFN2t3QykDE4UM/GtprMgMRN19wXd3hEhclk0AuuCqXTh
XVbn6qFkIjjoIW3NL3qSgzgZBymgxsF5SQYSOhAYV4uOtd3njJb2d98Ipg6kMw8Zq/h1yAr0k9g+
VrfZF+I4bqhtwAtDD8Y0QBxtjimSYwfIktlVdm6xddGBZgalKehd/YtIIuIdvxMLr1zO/gS9StNw
sJQeyxAh8h71GpQ60Z6oyzNvOeX067QWmMEvYb7DROkCNIZQUyuFAlOvb1lDx1knNH4yd2WaZK8r
r+CkmikoRvzvI4eU/o+jOsvVFSWgrydlGdapIL99qPTQneQcc611Oon/Ab3JGfqeMX1ao+o06umh
8vZGBYpMgKlvfN3niid4OiEjPn24owe4P/wf0BcEtzsUH7lWsUWB94z498es+fxDQnuoDh/nY4gE
ajogxrVEIHqfTctwuMob0UDFrvsIzKwQf41Lv1n0nRBcPxJLM5UJ4FJlZIFS2RYIJdrd7gF+hih8
YTOjIoV2JrfBdD0xK//SdmI0GUXHf8DOIxI5kGMsMA2C3TGy4lOGqx/ul4Vad3YQV9RCGKNSBSmP
swelcc76ZHQsfBv+R3E3Qhj5zVjf/K6AoZcuRmOR8oDZH3kuE+SAguAzah/7ESvKGl/2j2XOqDzR
8iiw4nialt0pWtCS6tkAYDgNFRgBuQ3JSTGYVBXjfuzTxw2isrqagSJPHE99MTW5AL6pXUJymVgE
5paNBZsADMcR1hyMFUpH7GPeGsBLRgE/AKMgA2GARIoaY0qLY7Q2ngQkpZxzDK+JTkB2d9bPAKqB
xP//3NfAVyngOJmT505S7l2pkRJA3zrYI5j1lANxGFxyNlWR9ZV+jIsmSRw08iQNYJKeIVFvFn5l
1qGHvHHovG+z6dzxC01rj9zFwVtlh+QuGUZJ44LULZ8d9NIxqFBTw6hzTFEuL46TS4KITWMTa2iG
iawcNB64KNCr/hxLVwfmEPiO7V96PBbe96vC5j6ZdJ9pZkuDE6tWqujrPd9sPbGbOKfqfCMu1lqr
gnQGK2zc+8TwEh7mbOGCbkbR8rdZ+ejP/5kyj5vlz/VpfsT3EioUydZUsNTWnKPuMXaHjUC3y2/b
GmPmlTvqKIvOTpMd1gLCqFjYWWqhpTrAlg0gDtNHHujuUhV37JUpOgQyqvu2yfL0ys1KBhX+KKzc
fwwwsbhs1XqR56X2EuKNYJNJlfGn0h4d68iUsAfHFhWSxteq/l50Xe9B75wleo0rPLXaLl0cZ4/D
+TtblDQbPjt5GD6CqdaoLwzNDp7sbMuVyDrKgABFbLepWep5iWe3Gx/9AEaAD+qIz0TQtdMLG3Xt
s56GGUY7kKfin1p9z+rCo/yd0eak92VLYq1YxTUoSy/7gKhZBLIovInn1DYeF2RcZSBCqIdzpQJ+
98rQYHmzURIhcv+960/FqHzeLpfZn/4+jZ+K0qq++ARWl56UCMS/tsJWH18ASjhi3yXtTN/dMk8p
hr363JRUnazoPzjnW+sZCU0jaw7fLxTzW6MNxyBoD+X/7zjjs2QTAfKiYAfG04VO3HS8raJF/m49
XxPD/s+Yn+z9K8/o3QiY/hQ2Owp6xlB73PLx/Ldb/KPzdc7AsBfkkQr3xJraAEhegTtvnN8n6oXO
vRF3Rv82uX3wiPSBbdaYW9949zkFf3UcjE8vnGI7jymx5eK+9sj/L/mOK4+TluKQDEqo6yIHAnq0
GhXokouz+YH/biv/1C3pYYmZtYMP46TSbHeTg9Lhu/ryEUFxRs9tGTXErY0InTDpXqBpQf9mHK6P
2jF7bW0saKO+hhkzIRYnsVhMC41X+i1uG0CBOfDFgVwiXx1PXdcUY3Ez4N4DDDaZZ8lgUhbTvAyQ
vaX8ZCRa6AUOrcqYzmY0xNkF2vkalIbqfrKwMkpYQOB+740RvNloTG/JSkfhyn4cBdhsahtu91ea
NNcFiukrOsYLZKcNdJ45Mw2NjqFrOf/v4RBHpRrZh9lgJn/7ua1KojRK9Shb/LC1mdgBwm4ut5qC
IbuNjzS9FRojFqDP03lRHGq2/iEdHIVGJGJ08AW1CU1R+RE/psouENV28DWBBZTGfc97O0HqTwnW
mmdM9wjCsukKN2qX0U6w7ELJHDTzEcQ5PcP6FZVEVoF/J4LzSwcN/07lodkHJjQVOBy09bSBymwP
QIi03OlXCj6VclHKBXXmuRLluQ5iYY+6KbY1FV8ra1GBaJKT0AOSlGoamYWc8oO6xCHOKG7sGpeF
8wCJMwwQ8RJ7jyvvcot+FtgRD22B1nO1yYoWSlyaYksIIDvyyJhSaUOyZcQY4nvJh4mgvZq9WZd9
MPAFAVLirpMKVk06BhngHG87iAJIS4VLaGq4T142hdx6ELiOJ9khhoKcF3yNDGZBnvbwk+gu7J6M
Pb/65XDtDlI12Cnzk5bMFf/GQLhNv6s6MLKvmxj6J5L6KuSr+q/BDVn++YqfxqNImu3kEBDwVBuH
Dd3NiFcUx767NF70AigpY2oH0AC1ZlEq/SGw5vX1bsCM7QfGyshRT9Sc6NBeE/hsEPYj7ILxy4Ms
NDFqF8UK8Xz2RAFmlDgidkRzc+8TGyiT/micX2rDw8NJHyKQcgHDOitN4jL3dPvwmmpcrpckFLGQ
fH1WLGzW9XDZt9DvTmixYAMDT9v2pQiljs3DP8jv6K8yG8SEK/knm6eGOCKXIK3Nbrz31rA0RMjQ
hXPUP6pXE2X0ip4wyYPH+mZVWJbfCum6iggLnX0+IlHo1eSy62FretQ1DKarwuuBIDwT5TFv3o2I
b9wLS7pSHXvZ1Ezg4YlR0fwpS6NGbJUqya1KAEEFau4X5/julyKFyZik8Ymji16aK+ZFB2Q0SkvU
x4TZk7vbIW5+fQaNMU5aZ40/8jjF9mHUwLdb+wbhYbiPCifDEpf8HpUin95IbDmOeUgVLwSMQCg2
if98VusA6LtGOrR6gRvGyr1fgVGJKq5faC7rEWJQfjjoA0dfwUP8VtFCtYNdF9uyCSOUGW3JgHia
QB+aEgcH3S/CsD2251pJYmuUqcJl/UQ3pmj/HoRRHPA8YurEr4364AJZbu9d1W4Ngzhej4Rk1E8j
YFELlaWcBJQBz70sR1QSHA5icHPAc7NNhdfD6kg6v6vdizL1Ke9Fg9E3GciCp08XdjNSQyzJW7ew
1mk/IoOn9NCX4Pg2XFLSni+Ar0wGZjnOvHIYafxt5Qu4JADtchbzzQT22asOMpAP8IGbBtuj4ZCL
cPZq19fb6qMemofTQ5dyIfyjSk7oNXijwYi9+CkefHNgDugJjjyPRepN37jTWB+FmEI8rUp3dmWo
4IoutAZtR3C625LS5AVO41NccTRl7bIKfcgIQGVahZr+JsFfLwdIcqxkKLW2Mt0Z1jQx3NhHuKQS
sDbI5XD32gZV9gbCGPv95bxaSxAVdv4eAleBlRI5BdTEwbAwJ8m31S+CgjozBpbs6lOFoDzk3g5A
IjRZI8Mp9sY8SVmcTUwblKuekhm+o/ODtJJIVGBfRvkybWQnDHJeAAYxOD2Lgh7M9j/CKkbQ1OmK
OC1N5TpOtydid7c/9ZAHGVCiIN8JTudylhGjGn9ERrx4JhCzUOJLe63zxITy1xMtts/RFemLoxBr
nYv5XvOJyu/5uvEdGBNUhY9WRI4FgpipMyylbYBAF3N20V70+iRd+Q4+5+lCxVOmlQkZUij77akB
ABXy6j4ZZRGkBaKgR32JmNp/okgYZC+96nxKgXqEXtXi1XwuFQO1haQxACKKf97haV7Kae2scOAe
Fh6CExqPzulF0Q0bfPTAOJuQa5qW0w67nTGCGnMNDMDYWJp+m4ML/cW0NjW/Hq0jyLs1i/PlbI2B
RlNqvhHtm7Nf93SbAmMj2yJZt/PK9EmA6ptvUNT+gicCys1zgPwlBrQU0Ttrb6NWoz5g3MT7abQ1
J+m7lUINAvzuO+BD0ZYFq8ZNa1SkKsmSJNjYBuYhWKjps8QFiUdIEsO4iFIxbooy1VUZQsmEmKLX
AQ1zMiGShfkA4GG0txsMrh9kh2w5BNnhxBtYg49nVPhBUaEa/e5eSNGTnWn0ih/A4Nj3DEtEHqvz
XFVfyejf1DmWbm7tHWc/hiMqDPVpdFrhpamF7OpD1mGp1cQY0Aou+K92toeAPD/5vwv5vWXC7xqb
BpTEXNjQJOMGWgXFniKJBeshlyMVolIP26ykx++RNTVYL+P3iTP/NYj0NeRhnivuAj1NL6k+M4tP
QnJHMwyD3/Ql/VL1Q988nbUAvvl7KiUe7BUPnmM6zNNFN1WR/2Dq8Vb+CQmRcMqEeyUHoquZFvfy
NbzqWK0m827cNsLwg/yxJAcBGBdYMWlYrePboHA150SVw92dt+HVxKh3vHolm3nQzruSaFjLhRrj
EgKQ7Cj70/6UVKkL5semU8AryIWsCmHge91+vlVchPPfh7oMmIXThB1306ScRs8qIkIPniFxSC6w
2mEvdsaiE3t5hGRJb6SUYuBfY7nJ+0B+GKEdUFuEi1lQAoQxaFJdzoO4NAqKZUZsq/jbViOHFpZP
g0Yp+WPjoKX2lwMfTpsh1N5HXy31VgZFz0Ueyh+kn8F/64bkK/cAd9tACAneVPmQepcziLxLSvLw
GZVuI7XclR3qicvG5zRgDlwM4edo36/mKE538dI/sMPSon9qcHt2VAAUbk8PRh3uWm8fH2zxrFbm
EmsYx4BrQB9KV6hronzkqqvkUVZSi5I/BI35PJ5VRMZ9PMLn0QpKLb81iCpnELmbAy/cBvLzQmVR
ngDcyCnjJo1jqpIBkqYd41YVfffD9+w06qZnEalyRzCQEDw2Enze47ZJQRDN6oF7fTTpeQhbespp
CIejKcYNCGZRUUXEWiN3viM5vHCDqncmBj/9VxQeyPfjFL5HlK90Oy1vtrcjxvWoAsTxfzCEm7aA
a70qytqehAOOtTbmOMunrJ+3YgqMsq78Dwfbw0ONDrEiuSh0EftOdwyS2vqrdn+A6rpuKZbMZSfz
vP9gh3UPDi9x7rcclNyKQYhvvMCE+2sAd7gN5lOLe2B7OhfI1IqDdYv+7SwN70ZE7kKmYG++qUUy
YPbljlzinfsg8ayoe3rVhE9UJoX0rKoUTFBxY2rN1H54dCl0rki75ZKGwXoM3i/sKf068mpy9ofA
fJgGMQLKU+SrjNurTlRgQiPiaIwHf7CjK7RK3IGkMPWz2tXvXhQmCI7qXSVF9hWx9La6K7Ut9bf+
awIvWVT3e5ZoOob4A+liOvuFIhyU1IUpoK6gPeKBRTVuf+T0Qs3zdd6GPcML2GqEZWsRmaf5NYsU
mKvY+pXMYzssGTL54c+cpjgaYfcqPB/aWip2G8v1/Sntgi90pm3025Ahba85I5Q/VIvTx7qFjTKS
cZFv8d/TAcQAbym0njWDHBJP3AsSqp/fuqDySba7wsG/kBq8VUCOGV+EQ1I3JTqbGpcvKDQvBWnU
u2FEzOkFM9LF4uwL2KDkYtLqa69kKZhEoD7BdKxwBcJEyJqMNwSP03edYXqzmvGAmUeg079h0BMr
B7E2SdcBRIKd9ql3ZNzNjvYJZNDvNnfytllkLYii3Q8qUgoRL9nvtUOarCxHJ1w1s7WwMoer01Py
L6AwzNUPDjeNet2E4q0L1D23JLusiRQk4DDYqeb/wTPcsLkKfkN9r51JL0WJB06rPQIGFvSZl/vc
do9A8CbBIx15IMzRUnjdOeHFTHS7vtxBFMYyyaTDflbjYIIFQg6csG2nPa78gqBCGAKTPNQABdxI
oncAYCsUmyC3tZ9qN6RXEM3cOi7ttCnWuC87yo8katcs1uBelK5PfQ2B/LL8rFxCNAlZUDMuUqEz
yzjfCMOiyFB7kYj04QUsg/4viDxrYU+rQnT2UfL8VRIx9CNOORJP5/HdJHdNZ5tmVJ+80bUw6fiC
t/TFxwmEz3agivlEOsAYBnCwJRQtuN/PsUo4zRdRTUGjUlhpCsqf/w4FGl9qqtaVEUDGs2v63aem
4FhX88EPrZV4/zAu4CNKYNEVbUVP0HuYSLlw3S+vcWVEIfZIchbFst/RjLUH+Q51g7RxUoFSrTwD
u3URUpnaFJ8QFzUPN5cX5Vzlz6oh/9Z50yLd7mvecTKvJF1YilYddw4FNXSRkPKX6ZQls/nOtn6j
jKGqAhGRSeWD/wpgz8AaZz//k//kvh17e+6GolVg2JRgjOtkbqLEf+I6sR9BbwEBqVS/hocJjQUQ
JAqKKRXi3g+tZiMJB6nbmR6K3yleTHGccMolIaVLZH/d99xNjgMOZ29pWDTNjOgX9w9UmobbjSdG
jvPr7O8z2gaWFRlgcaUdt4Vtrw5LDly67o551/5hOm6c/UPgBurbW86XOnQLR4r450tVSEsj/w0x
PKpqHOuA+nz/uqm2SPtbNEgi7DSO45tXPfebtEV1uku6qpI5ABvey7ob45+2FJhaCca0eCMV/2tb
E1rTrxZUtUKuGxI7Q2vXCQd+dt0OfaATVUOXFahL1kBmRlSW9M1bdsyhgn9sVZWK//8OV1qli0Qh
sC0zosAWXq2515iL25OKEWgqmcd/vUm3tXNLqg+W6OpE0B2IrdnZmTI02vwR2zGKhzvhT6n+yYx2
G57VvhlCv5gZ9VwC8hY5CNA0sYgdAAzOCqrS0LzkgKbXQ1Nhx5ntXMGaHtUS5jJtES60+Tk8avRl
Wwuv52VKGasaKkSbs94/uyRzPj9HWojl0Ab0mOYqtrI6EcinRLiHF2LJo7uzETjHd91aP/JRo8MT
5RZOf45W81PQAKfi7+0MQUzJ1O+dDTTeR7EHk5+Vmfx/0WjV2OBUny/vS5zlzkaQzmQbtfePxDht
RPN/+VwW/XxDW+/6IbHHPMxwsYwyJWQZVvt2Oukj9JuVOaukuED90S/KBYdIXbiGweYbLw7k2KG6
cfE1XkyGXQoup/yViOW6vXh42tFWkJrUHSWtqaN4s3Y2CmbgWosBQ6ZyTavmLbCq4r1e5rCMZPZs
CgP1WWRPw20h2MUz1Y9Dup9HS30x/dFPg9VNGrutlb0xf9jNc6MgSW4fmiSMJFLxHGxaqe7v6h8N
xtM9748y8Hjgax2z7IdSJPf3i00p1JRD6dNBXBdI9+FeYoKu5XWIvJ2zJNE6+F5zCRpze92hka3Z
80Jz3d10iLqu5URwhbFIYuJPqh4UJxRlomjNYDLXvYAZYvqnvT5+XuV1UfgWMUqwD/Z/ZcTg1fbe
NPf9AlnKg5D1FTuOGbRRmOGQj9rX85Vu3olusEFbNN+VvfoujTWUqjRaIbcRdbDJrLlbBNzynBtd
TfpgZ6fmSOaRVVYonpEVeK5D4fbfdRwl3xO2fm45SByxoZTcYztoWyFkK4t6VoYDJ4Jv0WE4rAiN
lhCBCrx2k/ROjp0GncvWPihlhQJuL23uGP9HZilkf6Z1fOoM4vQ4gQaJY9weuKVuL3PnrVf01KbD
BO6S3x7d2kDO690UKd6h2RgxTbC/qh3hljSQxGf7YB44LEp7V7WHbGguWk1NlB4osjLTcbU6DQQ8
h/Fx2bWsgEJXWdGjJLv9CK55k4q4VdfkBH6ZqNYMBpz8At9L5f/J1May3BFHhCuQBnulafnChy8s
jYJorwQd2mLSIxJgyN3m236BYjb9BYFIGvc3Y1nlaIrDTRhFD8K9ZPVR/vVaF8xuBkw0Uta2LEn8
shPItqJNVwuHzRg+JxjjUt6iCfxXlykS+uIz7il9yBSinjIeQrVcOsXfJ48G3egLNFAEjTVlBMgR
DSVBJifBVoGR5xXhXlkK0B6mtUMueAvYRYuxBNTHZ34461OIJj3h9UU4HtXX4hKMu08TH+tfXGfT
ecztcAZFKqhAR1axvazM+OKuoPeA4PNJnGhpdlXe2MmKyd2gs0yzwDdzk8HPKOn3Q7CwLKv5C7da
1gN3oNWJ4k1whneKqjtZx61D5tiPCxq9wlK/3DWmbyuy27zA2ymVgv/2G1LUiK9NiG8auYPbd1Cq
ifnniUfag9ZIXvh/wfpNwZnC6YE0i/k2SMZ4fD0IL9nam1ZwBVy88AFe0ngk/N5MNccD00xONIKn
1i0FSzck8tzBZHI4loa8igSPMsRJFUtOU/pOJyA81cDSRzOeSQs2rxds4ZAIqD8BYhHbuqJ5VRUH
jaOLHQGZb0JX+bkQ1KQlQCwXjlpncUjPXCYULPvgUl9tWfs79KgMSdVceOF8Go2hCFtZVvGe2lB6
Ul+Z3yLmr6Rt4+NplGCi5cj8D8LTHrYS9F50YltiuqV1jmt8pOE28C4229NlBsg5/1OVZTZTI4hZ
7lizpeWV89wJOPE1RTkAXjhEc5suO1P0AuQFXA/p8PrwAHJTd8My31haD1lHlTrPZ7mKYs14mRjq
PMUyU6MDim8AJqlMBS+mMYm/INGuWqmIu9vDjDVT2FUNm0Y2IeCyWUMZzgHTvxjnory5L5QDYnRv
GcuEplrVKo69gwPRycLGiTAiq532wfndwp4On9ZccmL/pFZA2zHbx0yJNe7npHFSRX6g6GLD2v78
XWLIkoigV0U9ggzCncZo7j/JJcBc3tWeKuPG3sOT1KHEkkClbGPoFOvo4jhDG1BY4D606udd/aLT
1ZRUgXlFtjB3c1isBaQxBg0d9qwbD9hHJtGGNvWGBs54OZUM5KE44+pob6ibI2WrP/qhRJvKsfv9
ukfTYEE7xFyc3xHXaDb10OJA3Lime3h56UcKYAEMZK1QHz95LEP5rthsI6SXcmmxlkaMNmaW8OFH
V4kzQ6VCsgL+0awpNcu8YZd3h3ZuKnNdpOsqT5tVnyKIAo+dGHPedplFMmR3ktYGNsiVBjmDyxBk
eB/5B6VIHLlOo8cAaLUr4FHT+ErwAaS1rwU4YHVq2a48f8jrQTSLj50zSKAalyQfNdQTHKjgrbss
VPFKwbxdhb2r0jho07USQnYakKNjEEsDILGm8QI9G3Tc0zArsDRL11OKD7RhuvU/fzPicIMunvxD
34jfrdOhkYEsZ1h0TT0oWYOjtCqRcOBMghJ4juiqRSl94/fqQFLMtHSFQa6hfEnOdDRLVAJz0BHW
0VA88f7S7kg35dUmFPzS5d2peLL9oBOVgDOcCQcTVJXDxmjw90yeBzttGlsqyVEFr3EhpL5Ei0hy
NKJpGuWvsNjcRTXKmVmYXAhrz9cyx7NqShPTc/+Dyhjr/wMa/9bixyZ4qe2s/FjsXWz1+I/b64jE
uHSpL/YjP7KRo6hyZHwMGw2VrebirBJvzpvTztWyckT0uW+F/74qqEx66q2Op5aY6pBvoS/yUoPc
DTdfUzlr34hxxtl1jAaT8AnSVVeaTgFrOyp7afJYbW19t3ocqunrVhS00V8qdvcZYnSwi32AkVZ+
oxPcZlkoLKlBQLaq42zSlHRYMOjLaKeRVbJtco/SELZ5CJtA+wC/jX60r1BA5uSQ2h5FTPFYpZ1N
6K05k1h7tyTH89KyhsCkW9k28tTQOYt/Kwo3zrm4IwKD2ANXOcxPChDQtoFGf1CNEbRs6FOjRxjg
Bc7WxLVO7DH+jci6CxXZbJr3ApIrmbhAvZjqqcFoVe/0VmdstSpCY4DlGMtC/GBbCljdwahAJ4x6
/lotxf2oIhy2HjU5RPL91xH75hOU+02qELDs13pBLyg/R32CvrM8ZAu0TN2VmD0FjkOy1m+Dsp52
LRmu4Ze3412kre06rL0F33qHa1QRUxl6AWqLODzToui8fgizJsiTK1q8SYIgrKUiPIoRuFb2XZ7M
s3d7HJP1vhVeYCE4LnaBbiCElk7nXstmDMUwPMYwKS65uMIu3aiBSnQl7j7bh1nwf2RfSUNMlPaH
+Z1gF/SYW4HpHJpuCOj+rcNGurltSioT0RAvpWOdcdBeC3vwc0z4ow1/FiogA1EjCM2IT2U5A+8l
tCNG7mjTYPJ4SQzktuqPypC5rMtp3xMxI63nB24BUxoUB9JBwM8twGWIAxCSk7YiIrRWKgGlHzuU
nsDKyghnxYnLInFMPpBg5gqfbrsNk+2fppi1Uv+b/2MacRc5lDwwOtJ02NQ5MdbMj194thv8ggEg
UuL+OOOxPtwEauWa8JNX1TGnP+pZaUR1zU8IiaLqhqmLbX1UPU8N6251NzrelS0RMzO6fohdqWnt
us2m70aU/RmlfPkR592ABuTxUs60z1cDx9TDGkRDkbDyTTCTMmwJbYyzrySTPV8OpFXCfGYdltg+
cZByg48+RWiqDkczsAU116TbW0iakJWM0IWcXEK+BHWxDHWwar3MBGKxtfOFaudV4DBO8iHcV1lF
LRtNH4YbcZwv35Vq0OaUaY9oXzZtjaGt5yjltblwhPhOpTUwzj30XLujqU2nxC4IKq0AFqdtngDz
gBZnlD/PGRAgbct9FtCkPpIbzZ7PNlfm/oDmnEfwIATYOWyuB/tUSKMnl1d7Obisv5KP+mu98mO6
nKGnaBCxRfgxPwdNpQgvzI5r+Kq9ho+C1DNDI8GMFfJkzrm4WxI+N9wt3Ux5mJGzrmwD01hBFa9h
5cwj1d2k3Ce22bblGh1Tj23qYnAt5uf3qU4BiF3AsEb47IVQwFCwHy6WntlRCEYutae3mTEY/NQg
bXA2Di2o8Z/43Yc+jPj/+XoFhgVjelWhVsVetUbSkUwTvBSU5Pw3leQDWDP7SCnbm92vJDRNtnj9
t/mOivwluGXbm6J7qtEjrCIe7rv2ZVyBfOtThNASkwXRz6FPZYl5eBtRscWc95M/8H741D9lSZdD
bCOuBpZeKl2GRQBiGpp0+OsDS8q5KvKMb0csgAN4oWASjhWk4FJcNHX4MU4RZVdUBSxDvxHe9U3f
RQRog/ZjPWPubpIAk0FUwfjm3BTwsE1TA3dWRn1Jj5jfILKTB633MCV8wpi31zJIEr60hhWXvmmm
k36RW9QnLmsQcHioK854dTZ3GOXKtC9IDBJzIIoqfOFNZuSda7G0f6U7efJb1eb0JX10RAGC68u+
+LCVcdk9Cs+zB917nLjwIAa7ZjyvLpHlb1PIMQYEMHT66NqBWMwtavsERIqV/Sg+PqZgHT8sWkUR
fI3dDjxTx5GcicEuty/gH4S56vVWDPF5AGR2qWF5rCZJ/xpJZirj2Nd4By+pS5pK6e+Xfp3w6cQk
I81/F/MHYJaIjUGRLX4h6I2ws7kOdrT5nBjWD8vWtFbRTfZpiyKAVxDA07yywOSJ28tZwi7iLFIy
aXpHv6vBdkQk4P09HrafE/QkSYjYgCRF2niiT88I9qVo3mWbdokFdEipxxmrO4jUjrWmEjaZYL4v
TlLDAwdakjvSTwwDBhvMwHCUsWkVnQAxpi4ZOxL/OmM1NTVwzEvnzIudsne+VZ6QEW6SOaTQQ8K6
g1ELzw6Ygy5kpEXIs/BT5nQSgypVMGV73ngn9x12K2vRIXYiVmoSDvrQqBfW7euij9x1DSw0cY/3
J7c6iSIqVjmnWZejL0EMd7Z3/e7KPFBJq1rbd7PZ4D0Rjko2HHglPMTNHx/Ehai9DBulTT6rtMXY
jYWc5Rv9nnwBnE8pc37m+0tEn2VxEJJ1/Ms3A6xQn9htGsIC9y11tIqhZdFY1xs1cqbSD6/v6YsK
WhC68U8nGWBNuaMNqP3x51mDKTKPqA6wwQqPUuvxJ8fdIj9AuWpHPL6LzpCY38WiUTfZoDdJ29QR
u07WOMwUPNQeGMdXRIjLPFgHTF4x8YDkMmDBbNncJdiDGXJDgtxon8vp0DY40j8mTftwoMqbSrKg
ZbcJTSt1YtpuH47Dds2SG8gwpT2zhUA7dHgWPjeYb/LWQXbrQ1rRLs6j3JcB5569Hil59G1GyMDP
Wu7CSESqUgVZeW3dExl73x6yz79NcqSUI5Sy6mxetbwjA1v8bbT7LjvSY0VYjGeTJVCajTKsCNU9
F8CEJzjOCWMvpr2027SppQFkasDa5/XdBGKDtZkLkCTjPGv1O4/ljKnkqjrl0UDttrNCGJqX0fkR
3Q1VJvnlWQU5xlT+4B/8KiorSeOI01lUgqiOMXvNO1r01Se40NXx2oqEWEiZOSN/GPQqvEe4LCXk
tSyORYbdHFlSWQQvvCWH+ubyBb27fCfQIgr1s0af+iqQ3hpddoRmOYUPv3VraUGE6c24az2ggN6L
0MfO/xilHSrqOPosE4wHS966ciZQbMhYmO/LJUlwEh2QRwnCsLKsIySgr101deASV3p21wHKHbhe
BuQANxIJ4LpLICrJPaiUno0r4H8x26YlRCqtTPFXvXjVTX+kVi4J1w2ZdVhqf5/1eP/Rr6RXFF2d
UIcTEAA4SQtcMGP+6w1sKVzAbMz3SkH4OSHWlFGPvloV9wvl9bLi+P1y6U4JN7VgVGlVat2+6tHl
Qrl79Im/H/oQqWYBCWLFnT0lu+diee9/klFngY3tpySC6shRNcN64DJmWKt7WKD8oOzNQR4P7JVj
MCo6cK3ZEWVNqOv2lRsEIhfuYzOWnZ6K49RNwP2EqxWcALm9tgDzyxy0LBIftPQfYTQrdbobMr7/
ooWniCqfRp1yGKErpqrFEHqPLmQzT/CbN95M+qwCbt5cRQz6FWbvZPJwNHFgDhaq94JlbjzCAohB
PyRqeK8kjcLOzpNC0Gr0wMtVEUjYvd4AYyp9K6LJjhUcLa8p0i0hSUsxcWJfu4Gf/eeVnyxPkoYU
lOv8JsfBNr6tNhaTg2X4uuOEkTT0Eu/xq9G8kMnsYm1DxN/ZgFEYMXuv/SLdWXzNoJ0/FS03/lzF
yx+JyKVSxXHGgNfyaCnY5F0gsjMJwok8pJZfjVItQKHnk2SBjTr26cIkVmQNck7ujYvmjkHMH8OF
mGApW4gV55Jj08rZiDjzr3goGxNbbQl0sUSjvbrKY5cL1g9CmtvExSPwaKu8j/mO1qzdY/ZW8NFb
Lau5TN7gDWlAJegXiel5tUBI1mrRI9YN75qLYI7urT87K44Q0CUBWfvSUUHMO574b2LWRFYHHC9Z
R1MHPXph3CEbbEnr0MkjvvlW5h2v19Ue/98EGkQuXJ9lRYhx2FGxSmowK8jBd7KN1fBdrdMsxHVS
QdVmbrKg1YnEPwJQ/D+emoccPdpNb7vS1ZvsjgkIirmBJx5RBCQGrQJqhWV4fPbranNCn7d/MFDd
CUDK+CkUXvEtPD+bSoUBg1NTYoSvQgOxsNJ6lkP4xyP5dpvlgOx129C/7Lc21CxOpQjVxNrZNelO
FuWd7FwN2WbscUN4neq/OlN2SukKVTfPZNx/Gz8AsflgV5vtNKZpZj/ktRqnffL28raPLPKlTi/E
2VIBF20WLHndOj+95k/LsVObfNYuNTAeMyemjV8cHKeB8HsTRtZbZKP7/psRs6adcjnXDr81r+gL
r4cbY6cZPEVeXSHc053rlKxihhKcqkFbL07zXeixfRrGIMU55Ae82x1Qbn3R2mhoRnH/7fDevPTG
GViMu+0gwWUTJtZxT3SCGpwX3duVE/SSjKHktwY4Qji0j2t9hphrYOy/Rr2E62CwlzrNdg/pjqrx
zDVNoEtGirF5OK5B6TOUXyS+0YFJnSVnj2aa5i8U/bjDq3+IrF+Bi74y/hR2N4fxM7FN7sOrNRb/
XPg8z20tLbCgz1hnYTpCbNqNBnu3BqNEZOQ7fmnz0mrvZpPiG5vsxfSL5p6zFKpAEEYWgueBiBs5
mMAoTwsJTnte3hZ9cW3uPwrS4EDKpKGiswESKolQ3BGQfybxUdMP3xy0HpMVth26RDVlgKzgja7A
qlLrm4SpJTGFvygb2r3icExdUoUO8haTW7zd4W9VePpcj5Cjn4OgXed5sZeQfFEyzRtvVM8V4gbh
w8UBJtDDp1zyIJljW0KQhTMr6EPKIsZ7hgAcJfoA8ZzdCnvQ8aY9PhxDUHEIz5m2q70E5XMsvGJq
RkPLj1Rk27VC9IrjfWavtZ4QTjeVVwX/5XH8p4BI+O/zD1NNYWcAmUQAKiG0fztXnlqkuo2Srx7S
oYdoZ8Vmm0G8JPmHfIpAWqJZjW3lixV1citEzxxsKs4Ifhuj3uKLTK2b08tMY2umuvbmYO91lwKt
Fji0wNG4Mn+N7BksnhpVFWyD5SquXaVBJtH40NPl4gy+zOS3z9f+uIVC/GZDFStBgE1FwAQnWXTK
sRhdSJKV6kJjGYIsLC6on/V2+WzxwMzP2jDd9g9J8pEmF9MIjLLSfu8UEP7jqsqI7/hXAuwdqh4w
VahqCaU/EzYi/smY0FTl3wvQS6V59rKhNJrRWv0Gdm7GP2VJQi1zgQ1EHM0krEL0g/o5ubsc1IR0
xuvfpiS9b7RDFkqXoQmbLUE1grP+yS9A9wN0BXP1iAp71kJBzVrFPJ8icOmq5o6V28QLOU1+rl7u
SIffALLoEO6Fug5cuO0LcB/WY6wo72UidXMW88PLchCeZsutotWovvIQmi/nsuJIBfHVkAzEyzeW
gTNMSZcq8fCwjR7n47iCEeNG+tRPdFUmsWXYMKwMreEByK4kUVBRHNvO1u/uuLT01DuP0jhwFbWb
qNff+QqRZuH5wOv/2x6xctBb1Yr93+LEkwJB0+/5JznjQZPR1nblWWe2MB5TaNzR2If3ajRVPwrN
FBEgtCU8zlozjF+sR0vot3NMwnI89jIl9zc7zHwoNf8pURCWnYXg7htc2a+6A39/uymBpKBq8OBa
4eBGkCt/UtXRVpVfWDpSbF6QFOEOpBqOwD3R5lBaWx+UfkpWRSG7CqX0yRD4crRBmBWtibpV6tT2
rFPxkdoCxnynktvWqYV0LKM1cB4h/XSkIZxWFdWPbj61BG/lhvFg4rTebS1losU8WV8loTEnWA4b
BnRry9VyDkaEI0NCblbgIReKMBRQEUJBqPyCNYim3DTi4LYfsDxem8JVxXRSuy0qy1FsGWL/sqSm
UAeOsgMVipGGEA97oz5uPn67vfy93a0v3MsdN+AfCV/G3H0Pk2eApqzecZWbdpGcyyOueK1FN+8n
Us3z6kP4pbSAr15W9GE6EWBrxv5ApICUJHLAj0ryWnY6rqB35yD5ALJI+1UJ7B9sZ61RDEGcKiSg
3fw42b7ACi0Am8x2hxIlYT3/nt9lnK0TqbAzRsicRjvMK2Kfk3s5+tUeCS4IdMQWqQlYuilifKx1
nFQTK2OfzZQ2+lPdqPu2D+tt963X8+wRvNf9KFfs2oyQUrIU8jHG/5QvIq1mKSIFE2Vb6hDQtJwd
efIktbahhhCY6WaGA8u2DFx0J9hZcyMS8EbHq3yuYfMvNwFQIgoLvWUSiG/wJKWW1GKHmHrbSXQz
9fGR/ZSbLr0A/LZImgjMdhzkI/vxsMjSkvbGHsztKnCeTLjIypOaPx40bot4sq+5rPOi2GYDWmfJ
FXvs0/REVBDDIhFdLtDSS5QRRtMOnSAWMeZ/QmQz+91TjIlS5zDkXxVZh7tCj4qk76ptLA/03aqJ
QIhL2b8RqhtNRTEgs9JW/Fs/YnGOANPgR4kkPPAE79R5yobi/5Blof5eilDQGiIYRH3d6LeKjPwn
83G32Z4OCA9gDFOOqKHFB3Y2DHk8GHK89YGtf1TQCN3epnTph4qCM6JPQUjyEjRNpTI1CgNO/HOR
Lj/UnsSZV0Uzati2jn3ItJ3Lsm4/b+6in3ENDSTc4ov0LiOUAmbmZUUl2KsS2cBa8e6LXPXFt4Ds
O++07e7ZPi8ivL06i189D6b9ksGTnUXxesww7XeNhRm47tmXPMAzjeNCEPFmi/CgRGPrJHGJrfy8
ngKtG4alNN/h/L9AWLxkmL+YmKKwyZ1ykPEkyjcCBFRcDLgzCbYEWMdDPKOP0ddNEmzlggTUC64A
oLIcIbuhY8yF0ylJ4VFGL9OftFcc6GM/EojsR24UzVQGFFQ8m8UOGRPGhdi6wIhtDtyQSeAhrapz
cLeDHTpIKnzbIXAu7vbFznqhshTpiMFEa+ADHuiJssWtPk4ipn7NPrXy/+WA71GVGxjNeBmNPKfu
IO4t93FDgTLcZILPR4Ws89V9uLaa6OZyg1/lffe0Q/bsVOZ7+m1uM4+SsXXk2vI77D4wNb+ACCta
4DYZXVFqwMQo0cPWNI8KSxgYw7LuBxqMdnAaJj1y7U/AJ6KyYt6SnRmiYNbAKi/T/k5ERevPpsHF
5xoGV0DCKubOpXP7c05FL+RlY6Aa5GdK0FlxbC5Yrg0GnMKc4554WULNqj9/9ZEzxJPhNB+G3NZ3
Oy3lupgf+khX8Nc4z1lY8idmNebjLiN/Lz39U2uQ/8En33Bj0cM4BKJKDB2KxtT+A/Ue7PP0Zgh4
G+JhxeDrUlmBA2xpBE7ig9u5+XQymXpRY53k7dE96OgFtLPhazNxXVTIXXom+WwWCsNqIosUwWn0
3ptjdnGHaAAd1tB1zsSAz1IQTn09IIWj0DaJmF/ITxclil8D4qNoTZLXck9B8T5CmrX133GiTl5N
UpUtWxWgp9a3kHTQHoqlJF+nSU5cw8M4I8OoElJcl1eCGUYM75rrFRv98GOZJbI1rQr/PoBMqhRE
a905MrRBSE3zK/Mdq36BNPMeW/cXiP/PzkjCml0QRf4huqjo4P4lKQ1GCjcxa4/zIznk4ej/cKKV
c70nN9T8NkSHXwbffFBFUA8T6ONaAJ8n0G/1lx2QxXUJO+NINr3ABuZomL0J2dWHjNg/OpK1o/Qg
kjkD8tDyXEEBWFhBugxQ7PpKOd5OEy6aVtuPC2MJsxWJsBg1xP6B1BNRrWNx5vK6zutBl4kzwrs4
5GmP+aqUHQgcbY9vGYtSOWmrVg93yo76dZCQRaScgwpvfPzY/X8x7wM9T2leghy671p83pNrjDyH
gQS6FioCqDB2GJe50dnD8IBkHUwihpZLuwbMXyEJdh5fRTKWJsbiUEJt0QvQj6EF2nujfRtrXUvF
ZNmTbm6jsFhzEo82xD2zqLIyS1wcu2f1iT2anImwWbt7b2sllcUZ8ou9zXwH++4L7VPFSrs0KPet
8e7mW5i85/kTQP9nylaO3LTksf7lFO9rZ4m5dKoTKh/PRhEzvFBfVtw8cuo99OCulvyiEsBYOCmW
ylZ5IN7JU62QTUIAN2Z9XdgNzhFIuzqPRcTh5dl7jFJZ8+RXd2nr7ORuytq7Eqza5lMUchZ4t5PT
gJJzhyFriLyg7q+vMhx+gf+5a2gmjwdAPUNn/g0Um9rlhB9lkt7KYv8208KUhh/I27KAc+6XmdfL
7/bubDDCF5gpYz/ke3G639eY9WVuYbIfE3k0+Hljic0fT1mcUdS3YhVuRG/6YJhVNOQOI+xosunN
3vLjYB4CQSzwi+nL6NpU6sa+y2getWgwuto9K1fYGUwPHRd91B7reo6my/XwM536deLmCwEsI5AX
Rka0/6g0rUzw+sVhVadDQKcSQRFvh5cgv3yCU7zEcbWdj8odXPW1y10ALT+LqYTYnpY9mS7fAfXg
0kkiPWc+qTGhGdBuGyQnZ+SYN6qB13+oHpP4BDGzqdTfsBDKadBlkU9WlG6TaZrndensaDLu+dZl
sWF8+FQ2pWIq9MnJHhppFeHsvKVN+8orrgxpg24UEeiHuvYqG37hhF1zqwh5E2rDFnSa/DVyx14d
zinZs9B1SYQ4MQYtiwiuhcb8bsqtU8X63vELwsDcEwpQ5mzyESkeWlecgsiIaaEfFdOz0DQY+Csw
AxiBLdeLhh3rwUmC8zSDyWN7/U0CSzUumdOo8uIoan7KXO/z2uO7AqFWfexyxHaqzgV7HQCMYdbx
XgwIg6GfgPk2Eqgw7UiQHhMi8qSKqhrpvLTGcNS540hKeiKFCLOiyG/4Xm1Rj+c2j8AnwtMdIp2D
k2AwNd/7UKvejUs6tJb0ZzpVx3xFhefCPHUICOIQhbz9GL7Wi74vTivub8yzVyeZ8o7hzvjn2sD+
JRDkStah5ASHviK5UiKSd5Ux4QdrFIhz9s8LYQr1nTvnoxbOah+o5+KAK8r1hhChSoO+bne+ut4j
Vi9FuSmLGiO2xkMaomMY1QTRigvxkCVOSsWJMNBbWsTERIvfmgaml/xcsU9grj4Xr/hGqvX5gHzb
3DQhteMMaJJ8M6E+VzXAdHcNIa0Zakfy8GbAHMra4qwL5Iij8HnkirgXZk3ohnoFBDGzu9XyXDIE
5tS4+56PP5axFmvCyvDlDVm7rrNHhOXf2UgxwbuMD4DmHE8WGBxktz+Ajkqf4QZX9nGLlKdGoI6J
vrK1tDrvdYipfGNT444ww7M2qAeNJMx/PZsuc8w+zHkJ1IOR6xe2R8weiW6wMRZXqYsWNsbObiZ4
O0vTnFRiF9zb9nCz3njgPfAruyM7eyeQyF4R2Y0beCC3JJAkF0iuL6n8NEKHd3yIaxiipIsnS3SZ
e8trFYouWq0SJXOsL+SnXXZgzMDss31EbLmhg3Yrqe1Dbi1sc6Pccj9JBahDt8LTKOiOsolRVMEi
DFTzoO45in1O6Djxl/h4nIq7lrZ/4B0buK1+N5ldvvV28hau8W6KZYcNKXURy1NBI9mqTDhXaEJG
rhvNkKqWyBBqBv0/R09Yojk8/954JtcwnWcgiOT14ttbMUL8AN1aVeOpyFrID/H+1aJqHZoUz5dS
yKoZLsy0MCGvgd15sCveRwWKk3Q7Y0Sz3X+iDu8VPvWpr0j0uFhjzic3XZmoKktDDIgoj/w9uq2A
seP4uBZGeOf/riKGeyy2MzBzmg9Q+ekWhwx11xkSMKGxr5TMw621l6bd1OMUOHehYp7Wqaiz2IUc
8iiGciCPXzLRF1hyAeWiJx4hpY7+eqSslSEurHByQR7dubr/5QetWhdzAlo5QQCP5TQJnYJPSfJK
4PXInEjdE19foqnrdFitUH8HJI8SVZzSVpQ1X0JS4Ci3n/DjRd6DS8uPTY2CBEitQLUkhFPyF319
/JsBuEpd8gypifYA8NTT8hILmVxZHD519PdgJGidi1xoYbaolCcE5H0qmMkOLgHOqC3TTqUFWil8
fFdvXaMuAAwPmKxpVIXQhAodABvkwXz840dzKmhQJfEQ1sUWHD+QwVMyHvs6zMFJJhyjJetjQz3l
i57C6FEIaWHZpa7m3lOyrqT9yFOEkN2ICK8Zgj1fgBPW1ZojKPhxNJuomkJpE+o7OM1pGe2XUY02
hHtChPO5ABIkxRcmOF6CnWynyh0ITa9Fe7VmS+xZ9sqfIjViYwCeLOSwPBRpqLAXeIJaFPLF+Sy1
V3us4z7gCmP5MC1eZOs0aDix7qL0t10O0OqgfqcDT/ZO+AYYsqvSzHbMOCYmasXo1naWv1DQ1mC/
KZWH1mRNxXKdEe/O6uiChRFmF9DYDDeAhUqVt1oXNtOaGKC8Nr8umaqPAWCgHsZe3t7r+0sBZHJg
2jaSPAOwcNq3/cfUee23+VwTEJ/4XIxqyvgL1b0h1aI/lSU1yv0RzR7mwn4thv+ZP+J+/wt0gzzU
dyLFhQUpxbFu2TqUKpsZA6DbLscBPW8pBi7T0lGgibK88Ls4NVHCu3790Lu7jXt+Jx3WQmV41QZQ
i+O42NVKPtDxGRaa6du7l0fblR3OYitna7bOfkGaEs7K932DEm8HgKVjgKAYMtLUfKOiICXv8JdA
ny+XvJrSE4kvROdMao/T0FEmNDnugNXgQGLTSatWKovoHg4e3N11ujfCLdjv30oOBSWdtfm+YHLy
QYydoonMtTDCJ23TMotu06rUjrc+dwV/SZFXflPIwT8JWaSkxquajbD5TU9XR6TjUwtMRZh5aO1X
i011Dy0T0sbcgCnI6exWc93znsLLFL8K6pIs/5cizdhTyZNA4Y5UQDXUE37mGTc8LHae8E6V8Ukd
GLEUN7LGEpbHB7W756jgMFE9shaSIdusZ15yLnMIXQCAzcBWrSzSXFLTgLgzx77csZMCR4KCJseb
BvNKeC8N+zhu3+8aisnNy112UHCh26gJPqXEs4oRxDoxNxKOCdcqIAuKt1mEnPB3gbPbvG8Frgxv
0vtloTdODuO7m+vl2pSR9XmzcvQZT2bWAZML+2jgNKrJ599QHG8op9uJ1YJDf0edVquRTOkQ3tm5
3w8nY8EF7rDME/3wT8H+xvde9SEboyS5MZXkOrTcxujfmU/X4i4pdCnmF5WCDneRu9z+vCY5OFtZ
vRaMlGWqAXU9ZiqfALjXHCk40jZCKSJXJErfsLvpR85ATiq8HV+wnb5iblsbGF+R8RWqeT7XV78v
hYIrFJ3bbGjsPHq+sJwlHli0hYjqmyXFQa6HHiWNZUMfMo5b/x29o3JbTggC6KrzeK2+knXEIzP7
E7PwyakLU+In7Ylby9D76EcE2tr0EDhXIuMIdMmFT35KprShxZQVOQe4+C4TLiXTRXEIroAIDULW
lCDXuGw+2uFSrIXZ40PWRvEn1O2TZ4rFnm+IWpEYFjOuvKMsFMnRVXVD5JYpl1/N71IikOMuISOQ
KJXAcA11LTadF/jOLm0YvnMrAHdUfhzwmmGWg0aQ1EtkxvZNvX607ebEZSMNfp0qE1XM4xjWgtM2
lDEyha2Dw3zjDUjwD5rnGmf8Xk3Z1S95flT6yB5+D+heF52h4PyW2RB492UJVPjAQyLCO7xtIHtB
sepPf3/8tPws611vXVKJtRks3+RTm/UlAlH/K4TZ+gKVSeN2os8sR1AtHVkKbo4/jMw3Wmfz4wFw
Z3Y29v5Ey5wTcLBlU3uQRd2Cq+Cx5gRNXxvoio0doaM86LEghX/KcDIQAWDvN+NMfPcwAHK0Q1hO
jfPzzdsfkWfFxN/+ytYiyEUonEcQUkKokOBiUyVbBSKjTWUuIH0y/hrvCGuSsQ+EAnw0F8Up5gCa
VvkzWX2SHnq8H34P6jrifLXnMu4TTNVSsUGn8MSIZOH2iV5Yv+hxv/56Dt3LuRu8Fza+aLIrZfm/
31TSinu6vXl6K/g6GUwYRL63l9+cG9h6NoluGJHJXqrYGmL+OuYdaoLbQQjNgy2DvFhFRH4+x2m/
RdWKpbS6+ME1tnyUOxur8Jvt2EvNoXFmU75smpH9yfW4mNoH2SV6+VMCBe/TAJwQa+B86axs6a8V
ckOiJEJdocNEll4NbluWhKBqy9iUC+rrfbtiAtz6ETYXjljn8VY56SHpZYgKOp+85oRizvLQmIyS
qJ/tZqQUCjlp27CCFL3AKxRzr1rbrdAbJrnILvPm9SdgOiQWm415WCm2Di2D4+EJc1mgmbDcZcU2
uTl4enf4XZ1j8gh/fnvr1Ss58PpdNLkp6W+uWO5DbRlnXa+H1IG4EUBIj9OorGbeQlWf6gtha9O+
k+wnrAnD/2hLhQNIiRZANWbp4j7JeAF05Np2J1kjB7GrhEPH338A3d4a9TGgzxORa03aP0Viouha
z3hjxgcLPgZCZqstSu3XaZkgDOKfm58wUH+F1L1GjGOuSuldF3lbCoX9d4gpk3YInS9G2zg7sIW1
P64WB0FAV5KELc7g61aw7S4DZ6u9Z8OjXgQDj6mxTr8gfxoVMBBtUovdgNHIweXOrunp0uxMdOZl
Hn+imrB7Uy6jl7kzaxiwol8jT4E4+CApAoKuFbrSkCsNqpP2lKBDyrSqorRquoLxoOhhgSVd/Ulc
rXOHESoaB37IEB7+Qmh9F8KIHqtdYxvJGLveyC4sU9ynfSF/VG98D9LRgLS3NdM4J+W33ke/GWRl
49RiYjBRyVuBdrTlwOKsGzH/6lPsSSzrGKuIh3EXmQtsmrfNulkC+Avy6CDWOLynvPWKP1OIT4Xh
OlnL5iEDKmSozwtcdQrsX90EL7jrEE+6gQ0xWLHhBJlWtCoimtssrd3csaNCiGqug83YJMEHeWwM
JZS2H00HMB6XC38gVL40LhfDgLbwHF6ytsw7955ORY06yEm//RyOqHjS0NzRXAWa2pP4YMPS9VNw
agPU64P1ao8P3J4gmoLM4GctYLzWOfEetNLMmMv8Q58qGgdcJ+V0bbXJOD6Y6kuUdaS2hVZ6+60g
c9RQalsJqcTPXoInHFEce9i6mFIe1AIQubvaNfjUfzWY+nrZF7sYhalbivZehNTRyF1SyZBdmbHL
m5VomngpCVwHEOe7lbAFBZXTufbH5+HGkLG/sDBTLqrO+a5t6lVCZ1vDeu+LgdCaarh0DoZmgUwO
TIcFXqGhLBei+B6/4YA/LKGBUcdHFwcWbSzJz2eeoc6UQmM45UwGPoIkAPnbR6PaGTgXafF6qBqf
jFyZ7ZpWVeMme5IVIOPFgqikyE452fQMnauYiQju5WmVC6BjdX+O0NWwfjWP6x5Ie6vQBWG6i1v1
YYDmmMFbHsbDmvbow5vmC2QVwlCVXdwpqNAxBj1GOERVeIzOASxEaM/bpSnXmRtl86V3OA5ateNI
72htk4v4WikXrsAvHR0UhR1jS1RsftbFq4cclHdnmU4tAkli1oAUiva3cP5iidClautfrBXMHHyN
Ppv4QVDwng2prRT94dZhnfKRUI8PIuLKQCrZ5lN+24m+UCmJf0eH/deEbbtlUcD5wf8sjgGmuses
7qTitYcQpeafty0y7WVRlRfntrki0agDZhmCJTQwjRxMQ6jdMQPSx6DEmTZtZHveyHtRCxyysu8m
oB7M1znC9cfaB4ycJzEQDgOdHgHdqn2qif/7vYb3g5L14ZLotRD3WGOnwMgK/vs49v8Cc3qK5bjg
3/B3+uyO0YW2byIx/k7XVZ6N59E6hw67DiNiosJsCRpaRsSNpRsjQX+F00NHDQqkX13kbURDy6v5
N5dHFLIbYMW7m9cyc/HGTxfh1oEsD++gHZVlpr16SrTM+i/IywkvceDwwoi4DPQe/58ZAY6xnrTf
tn9xeSu2YZeYzO613kjpRFZs+IPe2Ni0q9VleaJ3p06NTO9apv+/RU64547+jQ6JWWJpz7VgrkbO
3AbLfvjeMvzYdTDb327FiNr3pR9dLsSKRE/8vf8bk+k256OXqd2OKgcRT7p47ULkrcFRD9ub1sgR
kkv2e8aNBziqtMFwAubkHXwMlh6ToVWdMLI5Nnhes3wJGgyFXUv3jZnRL9QJ5QnQzzJHx+GKMQRH
46oIYfvUHEDPVtDPxQvLkOzG5nkSmBUviUppQ/Yk4H6uWW45a7uYuLvu3Wwf3yz4X42iOORUrIOj
AgTtLA/G+aa6VCELr41MeFTQWQL0fbuYDjMmG3cfI3Lv/AGM35+H1tj1OIXAfRfj/K2PYov4pARD
2VK2pzFDZQRo3Q5ZA72xofWI5kJIrjf83Hq87ap9eDaWnmUTErwlzUAOtDntU8zmcb9mv7A9BP9Z
pmM9yxY240mfBftmDKTvdK97uVdF3rVMjvBMhEcnq30fc7MG1DE9MpBlHeFVjMk45cQstgIqY/qF
Z4TezeiBbW0+2YpbkNBNPXynsUgrhwMINYMdVlsO6lOli8Y3nPHWKZY0zQStErpcM5Qot+fZrCVH
iWdjGNm0q30/xX01TuRkR8mO5j/bTux44p3U9MONlLLwG7ZjPxH7g6HOaEkwOKIuYQOkluLJczlh
piXPyQ4t+smRHUM0FybLJYbpEScQrww0SXf/hadT3PYDX3mo1VW9ii5CnOqiSV8hO7WmUsaGOcbq
p1CH7gfVOz1bYs0+k6qyf6cks1KkYpqaXBMQVwvNdatmCUXxtgQLqBhhnAQzJide+Q5lpE79+WyB
pqp6ETAZRnB2VFpqqe3T9tngkJYOB4tMVYcwZYDlHPbR2uIx3kE6m0NP9jKRIxOzfiqPuXvckTtv
SERcYvyeOs/6B3ha42ZNzx0/+h8XGuUBooH63vrBNrQrNze1dFNzINGwCyqluslt+YC66PZ+bqgG
yvUzBDBkmd0NawtHZFjI/mZmr+FLicA7gZAQ8oKlkWO+Res3LmO3SMeB/aBT8Q1czpSp80fQDvDN
Lt8ompITaen+tfu87lBXOH3Ow3UPt9a4jEAa/ewY9VbwPxtKXcSeV5grn6CfzxXNOUXFDZQDad6i
bT5GgRyYW/R0/tmb1NQL81HSnr2xjWRNvfZ2oaDWvcyCqz2HS5moRZaVfMOMxTlQn0iSfbzwFm39
pQv98Fdh43jGy1rDmDsgspZ5DpAc21kl18TK8R4+Gpk0TKNRHDyj7pIKNAEG7cYbmUghLCCBmUH9
HXFo8xTAjVqJrw0oBEcx8cI4UuUuF0o65dUgGaPDtyHYY5eCq9u28M9IHQdppUe5wHsMzwgkEinj
sLTeN8/F3FxfOGnPEwtZe3n9ROPI3nTHqeMTsWDMdMTQdfmXHl/EfIDEYJ+9wg8/uw49vrR1Y8oN
nr4m3ziTgmGDYU+4rJ5PvocI33foP5uJPEd7ZxV6hUUmYD9RONfylmRUo3joteWiqO4laCavhoWH
UizabQgqTNr38SNAT+2USXgFzZmadgqX7gbOKRa6xPjDAw+3n7qnQLN1NCGhjgIt3U3o8nUuy85s
ddULcUboOWiNvEgZN8H53Ojzxs1eoCoRnZ5xPcrDMfuyNvNfoFtKmDvUOKmQsYlSUZ+FkuQYSGiB
v3Brfb+keAAwsvwoEMQubvdnJUWr/7ZUR1rZ3JyYGRyZFlt31IG9j+ySfxAkl3h4CohPCdjUwac4
ESt0SJsxCNwWYhZsjklHZlHoK8vWsdU5DAhs8udvg25bML5RmVDwz5SG+W9KVtFE/gVyjK61z6Lw
UodU8mKjXkRGbYYN8SYtHSQ+RuFkh2o74/ZpE8mcbhj+22Hw9kwwbcvE7nml/fHXOOGMEfCTpZ30
psLNRdRvClLfT5EuMpx2u7gvD71ayxo02dr+IbbeNwzd7zSgAfAmmSHlQ3yZsOENlRlyBBzkGNwR
uXB0WvGFS7EIjCdn2xu/KH1IBAYoxbW7Sh/91iMsLenUCCO0dycc0r9cgyfWb0S2jPFLaBE3H13c
keMlBECuNF2r38uOYRcEd8KKhQguGdmWpM/8VbzZAsDyQ6T8CRuUrxhditHysbTGOx571bXKGR45
UyTHbFyGaxbpFDkA7Rq2YxDZXMljB+VMJHF5MGL/Y/M+srQVnSQragOLp/EzzKtiKbCixay8EIwJ
tWsTr3QdI+V2cohSSkwr2Uhs64PQGu0VtDGwOOJcw93wnduTyWwjbu4f/aDNExA+tin/phyDVRWN
jO6dKdO1xi43feRK/vSsVm0LDJbDD1bIhU2j3wxS79oq5ARW8NAC1cmw2dz9GwKmwUju8Vw4qL4A
eAul+VyL4INu5UzoeoeCqug1Yq7J1nexEpYCpH94roXfRmA9ACg43JeCkhr0smHRAWdZwLGq5IzM
Xmt4bX7M0G6PpUo4sOOs6o1nvFRkmiKBce5qquKUolKZNKYeM/UmSNrhrX0bwjVJImhpJpGxdtSu
/qDXR6EZnNiNZxtElwLEt5meidtHwRuHcoI5zXDAzllJ+Fnyr006Ug+DH6auu3ng5DG0MLiko64P
OqJ/dSJmAb42doxbdChls11mdwxDwFD0L5NPAViMdG8LqdZd9cByimbIGdHkTNBCa7sunGkj6JV2
2YkfC/CcpKMVzFFofPLJDdeSNQA/e2DhlO062gP68TMjWJxFGWB/yk8VMDuURF0z56hWLu5F1h0n
cjiF5KkzTpwitDbwhKNkUjYF3g+/snvSh2LdCd47e3i/GHjnc/6DYnXYD2TKGJE7deR9BTcMKRK2
h0hPftPMav6qCmyPhqbkWVdfB04sUzCIn/CY8t+u+G0+ks+0BZ/F9XUi1LOJ64HeXO0L9pfpp9ZO
xF8Na2GChwa9BxnTOPT7oWqf46KL/J13hvd5LGHKFNcHbwo0ccFzakeStCvncqLHKQtBqBPkfPf2
gHwPfEo7d3nr6TzHKnRE7bLmUA2fs0zLVtoaa99BTjsU0pgqAwi2hi+eBxFDmMsOjJG3XNryqKcb
k0UgdrR98a4hy0O2g3mNJ7o4osXyMHftXLnMSkwwHBNVYyXMxpKfJ3fz6Opl00pzp2LeQrl27y/X
qG8XLjg6OfgxxX/nb2UUSl5HYIX47GtuScXGX6rxn+LB3c6aT1uTI8W6WubnGrhkpD01Q/KDWE6k
2DtYUBpFVyLKdnNLf6Q/zGY7+6p2P3uybY8NmewIJJ5W8Pp8QhJigwpfMzlcezheM3k8Jp83irtC
ea3qsSyebGPnOU1rv/dTUypahYWw40MgwRLHZJv/JwaGz9MxnSyJylbBWJsZ8CmLA8/ovnvLs011
f2hmCdEv116sM9z3hq1l+FZDeuOTS10D3bEJ8auREVkKn1rOq7N6VPKxx9nZAhfz47Gs6JKyCWrV
vmkiztLKRjZcHprPjk7wmM5b1HP/+tNpZ/QbpNs11cXDKtExTFrREakuIcLZ4diGr+dZp1oAjPqK
AeIeUdHIScsvPr9ce+FPIT7Bc8ATKWHNBsaRijodM2TvL8p0FQJKF8D7gFLGFD2V0GpCJlpAA8yV
8KIxofaawRTV0MpDe8IHCzkL7KwZrJ5VNv8juZbhvfTDd+vfTHqYAssFTJqn7cNVGrNuxJ9W8ku6
LzUfZOOQdYw5eUpMTTbhNFZFGGL7XGzXn6yxzGSpWbAzb4mIKF0JvOgg04j6aEeHmqV4X83CPXNq
dVEg01qQcWhpYXhvvv5SKITWupf5J9OyRJOxPO1Hr3GIbtZxRdwdUjT0MPU26keXLw/V4dVCJHF2
0cP9TjyGMBDMNUztMgJHZPDqhBbj1u9KPl2d4gCkUBZQuFL8W6rAkfpOfzHEQE1ot7cCDkKrg7sU
ESkDMkNSYwnkRZ9KypW9eo9iv4y16VJqBv5x2Vr6Lm/ETUe0LP4Ez6rubNStzD9kOCNPJS9m0PWV
1j7jLuwESffsY9BO1pfgvLY13yI1J1/JOjsFZwkbvUir+RmMOvR+U1g6lxmV+TxZDEC+QNP21rxd
utEdnppJX7xfIMLmGqtU2jSSkSc73DPUYRSDDfLEHPailvNKoKlYjigCGFPAi0JbhFTR+/lCv5Ir
m7usU5U2TW68QUHUSrBe5Af7rVTRUYPHQNjZmaHYDUmeowNi8+pBIs2wUyJHl5rsw5eHMUi6floD
h2V/EL8UPtmiaz0DxgTs5Ewi/iEPsniN5bmm6rdC0r8Qp6iPdBRrI3b8seD12R+RUaQhkOtMvR71
3lQs2xBs448kU+0Ab131TAiDAQud7mXIoK593CJUiaKQiksYyKGsZiONfTshV/nUNi2MZL6EOyaW
mKZf8xukc/dCzUEfXnmkN11PyKgYQZ6xzwD7cFyK+ku011XOC9ZGO13dkiTR5mkC+jPH5OUqA5ZX
NlXv7pMAkUmAkeZW1tGYM+j1e6SNmS8eXiSRX8IWiXwc7Q79xBD9Opk6Id9j9wcVDEJSqeEuyHdJ
Px2CSWETElD45xCpRD5yFzyV/vKDCMe0zvk3MzsG0/XpfgHC3LF5gJMUa/FhspY3lNCeDwDxm4W+
uAYmWpJEyQ32VFKtIcyx7CQd2u60qUMBP6GmOSNlJtxM4XY6/Pqh5tZjC447MsAhNswl7bT+7Qf2
jrSI1zQmW3y2S3WoNrD9zEjNVuymlp2rJhC4OIELBzjJ3itkAM4ZQPD4ev24h7w7xVtZHTcQ4sFT
LCSUdHpghVVixcJaL7vAkk4zalM+io1PI+Zrui6tEYihOk8zv23HulEAok4LTlst4x1zROIpltj2
FFhpsYVCzhM0YbkZlyxCCH0L8KpTfsUKk1QVRNy2rgocRl/fGr651wYteufvmmTTn3T37gUJpeZP
xmOKwvownBPmif40J9e8oXlgrEWJftjLc7sjbwfgsYyenJwfVyAIn6JiJHDktn9n3ngnMu6j0Rir
uJnIszdILaKGqekMEpmEMSrvzEj3nyDlrz8YcY8hZZjaM1wT8Aa5W0WuPfUrL54KZ+UbDorvq7HF
Gcz3y6CdhKM/O68lp4oewxJPo2DJ7iTduE2Xo00piHkW8ZyVYw6H9F9o41LYYMDMnfd6U7133rk/
Urz1UJ/GJ4iTe9xCuAn5ydU766WS0PG15tXCSPNd4QIWH1+YxiQlQEZ2fHzR7xWlttRS0zDXrKkb
JJiY4otrQz+hu0AGuSBt2aN99tYjl1kNNzWcIaSJtoZfIQVy17zLazp8XiUfw5kJi1KuNW6GO7XD
CZYLt3tUgVLHdE2kuzTdglkWib2r94w4xTQH/dJKVP81JIzPPuCiFeIEMKW/cECqa7anNsNKdeLT
4X3MwN6IWTHHULwJPHnKOkknWGyfKvzs/VLr4XL29HebuOWtFtJXtrXOjSqHYczX43WBAZoHCqXj
GTUerbN8FVjU3kCB2xCw1LxDuSPszad6zbYfBc6rAnWRBjqFtCKS9aMsYNbwl+VH7Fm4BrHHXNxL
JGkgcZxreWCWWzhhZ2R+3hxhp0zkI0j3oeUsE24QxUqPHm5p/y+4YhwHkPUllSOv2b3NCeuPcxGX
nsxrVd0PLFRRraGX60FhYs7Hb6A6sVbI9DQaQI8Pd9FaBQsjuvNApnWc/wb5HbYG4wYhawBlMG8G
2v2uVme8/sR7sTxxlkON9qr5y0bVBEtDxqzvRBYVI7Z0i7rMs87zn7JbbyoYZkjunTjeK9ssPW4A
u67y36tNN7tmgi0/QNA2k2T2s2gkz+jmidERxSUuXrPNjWfsUdarezuwE8pTFQyPaYDzRoalb8kq
pGhA9kEQSOAFg+Us6YUwGB/H887Pb4k58QqSdEUYiPpOTHCjhOXS7nUKhJgakceCEpeaUoPxmoQJ
m3wMpZZHcn7ed/+5fgl4sP+F62JU/N0WXlXea+YdJg3YLvveLOW/96FKSXzdNTl27UwWKrZTyvtI
AFFWZafOe9YXi/VEJkLDiGVwc05yjDg9jb4dvU+5BqxfVzXk8G+nm3k1UpjEb2hJ6PP1zfnD9k/S
1V4IE4ebjMPT7dzWfy7bPIgKn1dr3ZfYvOKx+2CCYzwGG5OW6n06oQwdaqPX3pKF3G7U3dhon0Yd
VLrYX/oHMtSV0RNjzYSgSa+n9BVUrlCtKPQuZauqV1ynedbwMNF6Srbj2aG+rVQG5+8qqvhVf+ND
L1/DjAhuVTAZ0HuIHWwnbaDWv4DegVGYy6klZu5vaGORXGwrZ7iysgyHxlXrk0Efy+thibRvPl7x
Utwp9XfY3zRM2rVhHurAWbpe+js+iAXmfz542yKmV8KMEwyHn8B48Kzp//mkm2nT51yBo5KjjdhF
xIAx8XhglaNzt0/88AF4yO+kqqOPNHZjG4H6bX+QbmnfT5BruYdvY+ICnFqwwv2EGC36bqRUS9fC
fJrBJ6dwn/Hi1cSkqZ6ZgrlYk9udQdUGVbyp+TpWp09bMqS1UTwldCgCybeBkHkHqrX04iU3kWCI
8qEXBP69RWQGzqrGmB4neOvR3sTBZ0owU/Mv/0upeeS1/o3y7rzcM89+MvGsKc6oKfkYv9qTTIVG
qmS6MFLaXFX8cykqPVdODQSOcnOVoEDn0n+qLAMMVavkVCRbGIGyBW3Ky9cHK4a78pCzM6Ko7xIr
IW2KHOpZjBKASkmRKRJ5KJwzrn1yME1Q+ThWouTt/BLhAANIBDVVt+gLF4IcHvwb1LbrXYazsJRt
5lMoTI7eX1X22Ued8vH6Hyb/RCedsjrmadVGQ0AXfyWdAWdhkNaT7OqXLMatL2vCRKUFGhvKVwLP
0y+S3ylbFbtHtxTyLD/R917PkwSVGejqR5V60Z0A8IQTuJsqEEDj/qlNGtrRg4T0UsKtR6RWuC7o
wxpSh+EqqU/ZiHGmg7YzGRzFjRVO6hZQ8+Fn3Illz0UgK3WR36yEpV66HCs01LOwfyjPbpoHuoa+
abeuR+IZLwJKRk2hKSOxqAg+cWsbsaitKc12sjTx+5hK8zTHft6SfgNfSnlLm6fVaY6HvbZ9mYHW
4+SMuGCLQ66Hb99xUnirrumsyz95ymZ/RnF2PealTwbe8rb8E1C4lGXZP1k1FHs9fDLm6WafpSJU
/tWz0X1F2g6VyuwsXUsgsm8qZPOg7R1NhPKNQc4Y1752XQrwAgYOV79D3l8FD33WdXNrLRNt43Jx
IAECThr1dHsAlK0iinnWYwSwWDfK/K9Dw29vWGpGy8TTTO2YNlLKv/uJoXOrWN+CVu3FSErBAMgk
9660EzLI+1Qw4+6x/3e+RzzriNmCcg6aAEo3u9rkHAaCDHfpn2z8tluEtO84nhvLpqtdreaKdkym
3Ar8ciYq+7qWK7k4SOKoZHDKWrj3uMNp4npLA1xKJgYR/SccdOkkUzo9ome60MkWYu9rLFxF9A7+
+F3t7KS3eHFYljoWKG8aCUUxRueUKwpIf7QF0NsGBp38R7GgXkuad+S+RVGAZEHKfX6/1EoX87bN
Ei15nXATPFjo+vb9RcbudrWoJ3InrhbB14RpUNiRBWob3Mqp0e8enX4poDJSGSgTlxA3bp66Om4Z
N12qmzEVY9HB/yTMHQmeu5u6pp4sdkiDo9lvDbsJPF6I9g1hoy+JNdKwYRGgTAn9/ycP6B/Iec+c
0sics30qTFXEydIT8KSixWVSO5rfTZ8QggaYDZQAd918blAOmEl0L5s7PyxKiev3+N10KFQiahnO
ZC8d5gVFfoQ/bnQz2Sq2ySQGsDkEiBFtxzltV42XFId3VoJBrgYRalIUwBGiPcxWZ9TDIokIOvDN
U/kxcDW+SprgVGlO4NnyrdcluEhnsg3Chup9UooxStb/EQGNeaiqqSePygartWnEnmz772iScnYE
+V/XjhNnyyNtctZ7ktMg7Kb70UG8x2oJBJcDNiCZ4GrNxeS9m7sIaDAmlQd0ubjmOXybs+5Kmn9U
YY8SwpMS37B/Q+QlzvtNCvGoAejxABUF9rQ/sPFuAWz+DRPXCNe9Hy1Ccj2ef3IWQcWHHklDrjEa
7XcpVT5owDnGK2LCgkDAx2/ZsQdVYCV5Waq2codnUTzBr2/B6RaI9nA6dOuKCBo+H0oq88MJf1+x
hEGMVuu3JXHWpclYK1hD5Nkx2GmEVIXYzI3I7uoFCnmiiAl0YrWfQfuJXBT/FYCSQfSXNjZDHdEm
qicKsiAOV46nS1KSFZcn8ij5tJ+8ZOU8jEkmlvQy7EplCApCR2FQ51xw7xcA4hVnsMcVzwVnnoLD
v8aFMrKZpp56q1K89bO2nBt2c+8geMAhpkOY3n2gaxtPUlK+IhqOqoluimogGPH7iqeXQlqnP+Xa
zj8xZN+fmRwbLYFLJrfKTNPnoSM9fDBv5dQNrVbTb+7+CFKRB5K/wH5EhM0rmtPqmoM+tRHbf7Yd
uSJ8wxpduv6Zm23gyyugJQSOmezF9bS74EIWSVjSM09KY86jfykJ969+kkGyzdx2vdEQZrtY50+D
7z4jbwACgMGHdmkXMZwHhR/e1yIARKhSdMdz6akD2DaImIJKmuPS4vUNeSyZ2Yq7Ojj/yZFxKdD6
GF7FAjIvPogjNkVh2Iv+TJxUZieYP/FD5pbQiRdziin1w8YSCG0X0lHmZe2SAB8XbG6E0TA7++KF
vC7mQu52KxqLLmlPop57QA6mi8Banze/7UvwVSznl1Um2MWHhLxBUYHvbzv4pHEDVZOKzKb8v8Jj
M3784kCs7fz0NEFHJhj1HMTgnbByCf95PQ586pkzD9Z+aguSspf9Zlf/637hhmyKbIU66ufqucPK
GB2R1B560dZev+6ESJe1lWHFpwUOSrseyKkunNwTZ6P5NGuFqrHZKV6BHjsDWeQLrh13ydg6TozF
cAEKGrgyIvB6MH+JipMWkd8GIo+RY4sO1ZrO+XIlxDxs9TAIpY6YhM+FG5KTqZpxY+06U9D77si4
m0USVCGKCj2LjglbGw39ysIN5nHdMRE/49WB59emfCAoMrNdAvdT8Ez4zbNoplTpd9H/s2Q841JR
RNOzp68EsOcaeFhZuXm+n/7/4yRkiaavVFc9+dIAwmuUgh4SDQVJ0/eevvBoUgBe4TaFtaxm3ISB
A+x5yLVjyCs+vpixcghbry6+qYM/wegvrFFr7UAaOs1lNv3qzkwkBo2VUhrIR/KZYPiAQyqPwJtQ
llspse4THXno84Pj9N0QqfAZq9KRbjUT6ixNCra0bccrqx2suKwnyy/dqjLDBNCjbo80y0kWB+0d
jre5zmdoFI7tne4tvLCigPsNAIljF+ounRcY5mnvULQXdn/Xp5wK5/Oug+oVUyGmIopvQ2C2Kyrl
m8tCOfV9OHXFPRjsrD9TvYpK35SazGGYDVgAHarOHo9LFd16r28mHrrKdIeYUQ7fpWvfBv8Y9yUY
8j3FHr9N99kxyYPlg8jiBzxAHXNXfbq5V7OtnmySj7PVk3rj1c7dd8zYIq+WCAI3q1sk8CAP3xKf
e0fPagZiwlsXpKRLgMAB+TFN4h1/mOWeO1cvaBsAycAt1knaq4dqrR4GCHt4BpTjtO4Nqm+hI2pq
buNuAxPi1Z+zOVfezjpPnaeUJPFDNI1ts+yN2/nQqubWjGJGwUQ/rpGlGZ8+K0WEpZ2aUfbWTZqF
AvKJtdd04m8Iv5KNUE/9PThVnM1wuaT9ZMO5+PqkrXs4YGGuw5xW5AoViilm9hrOQ0+A7TDIkLQt
R/5Rabv07alHgyC94RTnqTGArN+hrm2IqJWcZAcqOv/71i+sK/p1dsgcpI4/8UA5WEjFnvJBq3YP
rHZt1f0Wc+XGbUwEjKUykMn+0NogntG22ksmJ2W551E96u8X1PU/Op95cO7JC89AwOUOux6fNEJl
drRw9wJVuz96sa05iCD9F0yzVV1FjjEz+MgjtR0/WIpg+VPgWVuxUMtrtwyiZih0NDBWuaWrFJPh
EUnpnAX+Vp4mSS70WWkQs0f1giI2t66JtFEfM7UxSdRKLcliwfjNtbD97fRDwpwoPvinb/0tVy2c
MFjiGIEYqiKkxOnOkAjZxQBrWXrGRZ8VUwYTEnOagufc9UcUyxq5ICkUBbCJdhVTzJeFfryZIpw2
xs7gsSmPIgL0yy3A9CI3Ne/UtWnyo2A3Dr40R3uuNEeNwq6DSDhCvWZpB5XHWH1ub6hwt7qfVKRv
rWAnwvVBfjNj3563AyefzuDxUjVZ0/DlsskPSgAzph1Hdb7WbcPLoHp50MXBxhQzHNCmmyDB3DGG
duPDISoE5vUXNOLE1NYLhB9XRI71EEjL8jORI6iovKaLHHRmLj0bGpNpG86yFPYkaQuAwb068dOY
qq6TwYKJlalszNRLQq337L69iShTc2ubQtOV0XYYGReXg/vABJe/FqpAxNn4asYRk4c8rfFHK36f
ns2iq7jkqI47s6tpdy/6JHdVjVfLYooUUHhOHHek5coS1rw0nd+XJgyVVyh5DflOT18jzoYsm2CH
3U7n0HCKBte8nMGKyQIEjJHlHBAlxSjzCawgQybDv7/Vv2IxXkyM6wv0wD8LfzrpNv2GfL95m75V
ev4y2RVR3HmN0lL7SOjA1sDEgFnH/g4U9WhSKaxP4gNzdotxAC/3pxXl+80D68EAIq+Xhwg7B+UM
si7Ko7M/AcTltyUi39IrlQ8002dwKsiFuWiXGhCRXBmK+DDkqiSrMvzwI6lxq/CPa9mDyYwExMIl
M10ip5N1gBXhOWKRLDLbaDjg+CAfYqHjB60jFZHDEmRBiDV9ZtTS/FSYg5RRcAK2+5gwhO9j7xv4
gLr4OB5dUWcJQBlHWh2mgBYfAN8CLdGUwYw+XszsiAvhWpkH5dWohMxmcID+gMKloZS3ClHOA3G9
+ARmJofUsG3Nqgf4uv3QXJ17pkRoBp64i8k6K4Q5qKskefnnniK1DpGNAD1qkHBbOB3AG8q+/7UC
dkV0oTEl1Id7NUzwz1ZXMG3acYY3IX90GBXhXnoJgRnb4t4Y/+AMnRssocAHjZ9vLVEy3PV9d8Ks
jOTnMWb5I4iIGgwImZ/4e7713k2twh2eD0tR2d4NE1TFs6XPHlPhB6hWvKlTFHhrWIWYCm9bhB81
dv8m7GyB62lmNw7NLC/o9MDrRUcSO7oa4uwtDjJQ5Eo1iqJdUDgRpQkI2CG94k5JaV9fhV4n0c1l
rZTlWBcc+AEioXX/GeMJteLbAU/Rj3iHSzJjTa5VoPxDhbTQFmfNFT3Ms40ws2KdZEYAz7LKkdO7
g18UA17Zy+vUikcV1cTk/S1tyrc5mjE81t/bKbzVGjFmQL6y4C9qfO2N9zqgbRB16l21o544PDk5
rltstS4E6btI7loRcLZBYgKFumOlMzZElZqYQyryVR9skB9xG0t8zeovQVrJIb/zsWgYqFDyU5hs
BETxrcJewgSZECWkYLahFr8Sq0YznsdzwxuecPsaeE/myASqxEGTX5gHOOFLPYMhc/g8LxaEXeBk
jQMRJvsO91W5JggC4j00DzFxTWXoW7uccjse9Y9ZlOfproISL6n5XDZ2VnZ69082NN6o6PPk35ru
UWaM78Brr85zwI18HG98AzNf7S9Ubhi4rbIVhJ2XjdKN+mMbdFEvhvI2vFpKLTm04tdPVAeEPYln
zEStjNi/U1uvUED3FBXqIWv60hABdUEHSkpL/bh2Tz5G/lZx0X3HHsXQOMqj6qTottkWLoCIaLjw
BsLctqpuROGvFBwXvX/ddm0YIAim5MUMW5S9EajsgTB9dNBeDFSpyZUEmdFl0v/naoYe+mVRS2Xu
6nM8FwTmAWxq1Am3ZdbzM8SZvJxprk/XUR5GFeX/BnbJBo0VxzzUeMuT9PqZEM2OpxNSxM50pSg2
NCM1S3WU7MgGBlIk7bPJEEPVJct1B0EGA6fKkB7las0J2Y+DaXZ1HN6vQqLBSLrNjKXozJ4SHCUL
A39a11W4QgPkLGp97QrmkK7+LRh5MS1S5o9pJaDdD1AZaNPcYPDOnQaeCcL1pZQ6Cc8tFu5JLFlQ
D0piy9jSdixf42HycjrzeZmOIJ7+yZkfJdbr4jt8tT5MVIhkuQURV2qxbPAMJCvRv4OYac9SGcBB
bCfMXevBEizOLMdUu4peQYWOgOyn/RUH9ZSdzOvkTH3Uj3/AqSx63thNPuKVdtiHnET75qNIIQPu
lGdGi4fCh1P9aLMn3yoraufWaC339bvgNxfiST7lozM7KA+wMlm0vyxbnXc+Gu7D1Jm9zixG9NrZ
4BLZSA+m4P+suGPR8vQxZLOWs8JetF4RJIxtH9XbliqPgOeen0z0dwCfAw6ZWoz6D7FOUZOsbT5t
1oMHsv/F1Pt0B61QshXV9sr7vKYGskDViMmhrDVsGWMNCwTJ0v0E28DYth9+16X5SXSaNdtQnF/4
SZoQgRg7mfjYuc//j/CZs2UHGrTgz9KJ7VJoCvQLkuVLN+FXpl/2iRmMdiJHjIeeOiGUif+d7DH6
4mHxHlhE5KJXa07glPetjqjUfUxQz+cVwTI3Z+G9oH4X22SnNjRosXVg+M+b3zohnarZLK1qa0dP
gsUGQlS997kHaQscvTJgjAlrhNM92AA6c61QD3gqwfTang0RBEQ1aDiMJbxalWOT25uKzN4oF6hG
i17Ju5CrP543/qKsEQV/a1PYaKK6REOafua3uajZJDyQvkoyzGj5jtAWOpVdndjAKGBGClxMR0ML
WgT9oNKAMSfZym5tjvAYE0eU1WfpuQBTpufNHfT0erxydhWeZ/xaPQx1diFiYvUxlSAe4FLsrxnm
cz+KemcSrqGcOCEjL8akD4fXEyObLyd6F7SYGUlS58IvrvehCHMnLK5rYGDQVUF5zAeESoh2pdKr
7cF+jqnPZdWn2qkLeyomNKwFeO9e1gilJSuTFm/0OxXeZlVEl+APA1rFc/zSJIlO9hwrkrAVhTJ/
KhXnDp1C9fh07kFkrVKTM0rrLgVNJZ2Vr0eq3R3FakOL436IuxIWJRCBboNuW4Nsrp8lr0DxjvIn
jNzdWZDE/0E1OCOaR7tfRUmd6e0SKmqdoO9tmyrC+Jdx0UNT8mZBjQX7XAdMzcLMa5R23ksy4nW9
rMTbGmHk6NAPsPsc317PBgnccLl4ivW11zRm/KYJCgAZaejWv+eIdPOrUQ0X/awWk+OFGofNmbai
AC0kKiBQel4cURNRTNThRjuoEwcZJ/sV5yOD0xYoXmjPWMHG59lrXmZmJsf/9DiX58ULCi1KVX6w
ojf5rlvIQxiRygpzt0hq+E8OTKsy/JO/leqdnuR8H04Op/otMLV6RoykNciF/zaU183/Fd78zJzL
F8o16c+0Mo4QUbM/5HueOh2cZqVq8nrZRrxz4K92Q9r9UN9ZnPiiC1+Sw33bBG6E0igGcp9Cmi1C
oNCNAHHhgQlAI9g4GPm4lnOUGfrts/7gSpvuHwhaQv16m7PdxUby1Gh1Eqrcopho99VCDUAToDW4
rlDTU2RMiU62RI2gDfI6cpJeUUnwKVsRK3hXaG0tHpLPtoz0U2MdlunDG23EV4Saal2ybG/N8Wf9
tXvswk7qmTE5S2tIZAGB8pEKhdpP/o+cwC+j4EYWRqNfmMBU+jGqgCvT+NU1T2bfoPRsTvSn1Udd
EZRjLYQ3N+h4i2IRpx5KHwawzsRiplhItnNkktpxRv0NArvMp8Sh1Qv4H0Qor7XTrtWSmty++u/k
d0NF/5IDnH+LlWRhdyUPVq3W0TgtAadNQgL6ZKQ9yPlFslJJ2vxZvDBLdgWC77ODM2U3ZmOaqU2C
SiCMRvOJYxYcmD9V5BuErX28DNYw7JqBUfXAqNASQNkmK4E6JKIwP78TuieQWur6VRbma3aTO+c6
seXVIIi04aheDznIsD4CKn4tluIGZ9ziXGoDmV24sNwLjfmaX9yEmkZdMDjJxFXbt29suRHEH6nY
Y4IeDUl1l5tXR89rWrchxfKEt/rsLog/XG02FqlkwEASCBUGjXdEcmliJm9TpVpbJUP+HND+Hefx
DtBkCcmGi+UqAPD462mR/iDCBZZeEDQ0LfUQ2hgS5DgdtoAeoezpLVuPgM+w1GmN7iKbcAMK+ApL
PbD0TJG0Ou73y10B0ZpmpVzZmnxypkCS+3g3k53wGQjkmLumgQ6FFszrnawHEF37kNCYexdtwHSI
S68ACTGmUiDo376ldnMbBtEVtp6v8LGgATJaF5OiDT3z2gF9i3OLIxdFLH5mR0O0g4XNIe0BOI6b
S58WlLdav+twgH7ZQ/rt0PPwMmxM+EC0EogTxlgAMvXVnamNKie1TK246+wN5arNHn70Gm/DrMfZ
lXk6eTXFZ4pEiqPTDfiengMsmcWcVipGkPxAf3qB3UTnrSgV3r4n2D6Nk4iHmJ9snauzb75UU1JF
a/hh2f7CB4aQSgkpG7DqLmYbkLD4brnQ8X+Y5DgRM0mcZ1+fs5rR1F8r4E7SeEDvX2z9wUWFVpQ4
FwAmBRF/h85njhb/jfywnV+DxmLPOg95Hwt/rrNs0bExXuLNAV2+qp2bHL+I+dc0ROvTkMwMsgnj
2Echu1QN9GWj8BHcVWYym1QHnuI+iLDIR7BejDfFH8mhATqpb1oV0O/TSQ85GQqIafp1pEcBfBOz
Qq0GimzxvzsxPikQFqNypX56BjS5l6InkD1kADs0C8Tb+91ry1e60cqCa4zsHUmy+6VhkFbE/HNj
MLwOFh+jNJVelp0CM+TxJTURDSXBiWkxkhLTpa8u8kSJOAqe5kT6SLQF64sLB6nUyGePGj3vz3wx
T/csLiumXEjsNDWAsIxnl4wGZAkhOtC1gwG2lPgS6qh/vOfppeZw9HS0uJrR1q31Zgee18ekomxo
jczXHIMKohWdpJ6HIGxbpkIDropMwfvQMQYTxQfpwCgN259/DVSaK4VIMhd3wTZsPmizT1LfWiWg
L/Ju4WjYAF+nMZdv9ucnN6+yKw0k5e2WlYncqjlfMsS5B82YYZRS043XVUTmLXYPor18Fz9vGgxc
1iQ/gd1XmxMmEHZOWXMP4s9DXnTw1VHLcdT1jH4b5nc9yhGmePnZjghiqnvKmHsbf9RX9uBKJwYv
QPNCUlr72bzSq+zjkn5zS2m9BxdCLVCrnI9vRowum0Y4PsPQE/xNShliqpd0lBl/PGR4M/FSpp7Q
GCe56cEE6pgDWef8ouw6w+5qtGA01zF0pQ2UbFEo6es7Ah+hTZtNHpXh3dQpaeI1N6Hz2B6PoiSz
SVvfY0x6q4BbXAMgmoIr+akY4MnXRMKGbM5U4kh7LEJ+lx1S5Kt/ie49TmvcF3oniRGEP77WQyiQ
AezWCUS+JiP18JmTjXjXHlSfoZCJXfZ8zVCOlrmEMTnCreL0rriGEu3UC611vU/UhZtz4mxdDuh8
q21pK6EdfO5EN4Gc+2MWxF03r0eBgshCxDL1LbJKKf2ovb5bGIFPqIn8gvxVbLTKg4npBiBcUP72
GInpWSHBv/nffh7eDRbeAM9NSrt42vCnQJJo4SQmb5K+q3FMUMYIs00hpoE4hNJqbKhTMM1RNydi
a95ABb6WRfDgcSylr2VkbwAVnGp0EYojJmyYMlWujx5vwU1mR2VDMavw/FwQJ61JLBVLd+CqEJsI
iNCPik2HUMPtibxwU6i3qJ2bNijfM5b0903xNenozgC3bpph9fBXmT7WMSzMsQGQ517Y8FJ/8E9w
tCoztM2DWA9Bq/bB4g6a8jSdRxRvqEx5C5CXR8Jm73YoInWRgzgj0HbxPCJa+UCL/p3/c9ydodbo
BrGGbGC+Ce6mLx86svXuaAQWIQgy/yL+yTuW/RgbfFlBdXAtaSB3zArlHOtKWKI89sCfFDSp0XEM
KWZewnmiwcMkS60QdYMyAx19PxSFEmAvqU2NGoSqr/OLPXdhWwT3lGPp1njIXjcBjv1YGEnsPDJJ
xusAxEgytLPitR8SrlzQ4Ruuck75F5PyXG8C/VvCqi04J3ANfTIei4FoIMllSofynT1s3HLipUu1
ec9GykWpTQeevVgePshuuQMc1IKf/6s0PIG/Hf4wLWk28jtt91HZnRy9lWmWkwGpsBW9teA9SZSL
/qRBgUy79i774e65KT+3Ydk2cDlIeQLYDQHxY2TpR6IYEapexuk8iAWJCBf0tmGyzB2A2rCFe1x5
9mE5jil7AuVf8PQBxKtPY04iL9+ehOwRoROa34hmQsImw/sUQ4wUp6RNUKwEwu4PHl//LlTV5QXn
5iHBI+u4QTfD79lU+dcKbABRfUnaJFYfwCtptLXo5z3PKuXZ/yTLNl4M+iU5zLF5pv+iJ3sKuICc
8tcGbx3DI+JDhN4kS5YeU11/a2Z+KOnGPM61FWVIFgyomP+YhJUKlEw9ws+eLKFIlpwqRoF+7C+f
UB1MnfHsqp8cwFVWVxJeTJUiN3XfdYnfMfcYhv3d26hZT0B5K9LNW6zLRqB7eXv5phnUJoBmPi3t
U+BoIFQpxy88Dq+U6vrYrZ9UJFXb0FLpWTwcPpERiY8NjJoNtm5XWet7H1pA7hhHgyK16Pg3G98d
5welaIercpO+zoTK41upz+oZj1B48QZ0hUUIlUJwva1ghDEeAo+KpikRuDOCWxzGyZ0EcA79SKdP
CysTxbhCfTzQvg3wBRpV4v8KyzFLr24jjBMvszpZ2Ay10KnWiFCay5HVIUTe0+FJKVvnICtPHu+v
9oSkaBhXcrfnIWuejVCE4H8LhwEBRv7GrurbxHWE4+5e4o5psP6dN99B3ShzHkkO7bo4V3M550dP
zTMy8FI/ghzYpB98t2bO7qagftn9Su7oDpw9MJWd3pxMx2lI0eSa1m3iNAP5m0aFd3fMzXRYzo93
keOERwcI/XfYDrB1ZVJP4jsRCD/XYuLSWsFenvgPK/I0DWkcMfH/QsygV28nQuRhmD3U+qfT96BH
2onoxZItjWfOhGnJIF5YkV0ZSqr6K2ibkj6XMCP8sh+tyTfPvXr9Q33iYOvODwV60dKq9oojk4uR
ryVNXroUTQ5CojslWRsaNx9T7c7kcvJOO4fekHCc/kXhXW7U2aEi2tiV1xQnrWgy9sym/2RN4cLv
VhIJD3uQTqqT6KBFyOEUfQFEtVj2WLE++uyTPevLu8/Vi8CJGa+OSOfXVablVE15cN3vcdc94BPt
4UYGcqvj3pUeegc33k/pyJKiX2mMa62L8TbRTdbirlZWJRvci/8d0+wvesZzlnGjILDsJtcyOkqr
KcKDbkxiaCKwlsCXXdRl/xH+xtYEJuD8iW4kuM0zDyl8qR6KNZrvxBivbzXrBXDiqtSBFeA/aBWV
AX1YPYIKMHFrxZ0IGm5RLQUMMSECZBKrPQd7sMSeGQdSoG2N+PeFWWtf45EPMwWK1woHM0FpDY6p
Afsh/XF+OTVT7VGPLi3xfJ5IYhr0++LCHPmzooSK66MiUCidogr8QUtFM36o7bMzscz2gksrAd4i
Zqnd8XbDzGKC+J0IZeN+o7FJ6uEmTzKsQ7wLutH2YIrdn418WBJosvXuD+jdbf28obx1+7PdHGTu
jg+EgRkPDRf432UtCQFap7ztSHeaTyfGhZO11SYzkFtsphsgdL4QtCV4suHWvAfr+HQX9eqeWnQ/
b40AsboDQKqnkcGKfwDGHNlmO3b6fqgTp4XFCKYJpfFL8JjpMynyvmGlNEaYTggnp5i9RmEsWw67
exDQe/oUu01DIEAk2yCnz/HRKjD9g0qsPsdYq/eawtXsyCyM+n1jF1sVRxFy4ch/LLKYVkQoK3MH
QKmi/RO1gLhlu9g9NKZmjILWUtcS/jcZ1a3QWzkLwVR7kXSjRJllCqLSW9jtHPEhXzYnjAQAHIi0
Go+s62BZ7sMvOzrHPzABxwPwGcLhkUwd07FePdTkqhPt8zNGIR2B0BTq/Gwe0qxhMgw5yAKxI2oh
T/sKqlbUq6KAHI1sgXbEeP20+12cvBNb+wLx6DGtK4bE7F9ohQqxgTmGVcx+a7d+wP4geGuP+Nox
OpHqCsbeNtzKdt8hcEIxZOI9GIDPatV627dqQcrXl0iGDfOuGC4ZWFYEcDKtGnccghRQzy/5XAzU
1AiSpiuJk0PODeEKfrprVyxjf4P5mqzLeLJp/cH3ardzIDyzSVGcsUX/vlymfsvoxuC0QLAKbr6j
/kMO5SkQLYONweoXArXnsaN3KTWSBCimG93zoi9u263N4sMQNZHvSo47vixd1gBdZpbY9GFRy0jI
25jhSwAjrFrrR1auSWJ1Oe6c2aESEVwFgaC8AHf0TuNBrYIPwXhq49kptdcje0DvJqxEdO3ygZlr
g2wrob48eu9qJKFaIoKQm8RPuBnNYrR76xUDrg0JbEwryTWjlXwXjM2v2iVYsZBGOkIa16gxL6Tt
A+zfdSOTXwh//GASU9eIGlYKScwDasa/oIXLeEgRusQ9AYUU1MVN6Uy8gsT/2z91RzYtmVtIaRyc
MfKWmw2ZCUyGzFqs2Rjqc8JPzhQU4D5MgbXUxnB/5Cd+WK5XpoPwULgU50eEpNtCB8FriXJoWQme
jBBSBZHvzl/pBtW4TLF6Pwg9WaDA7j+RApfuZNvP/lRNK42TomMKTfg4/NY3fE9IjmnOzI8uONzv
K1YR6V0TaDqxG0eBfAtnx/CO6cqFQfCINWh1fGXqTsTCkH73ONYaGp/I0Dz+FIN0kWcpIIkvkYOO
/JKm/mxE8cOPahMMLthNQOK2YRmGIZDfAp3i40wOytqj/wqFK0Q5HG3LF/RR67dB5gwL09Ag3zpE
LX/iqhjPOAoTQArfjBhfjGbr2TZqL7/WRc7awP0SgLmU4ScIzxqdGiJTXdEjsV3w79s8M0NVYkid
3KeyRbQcBs5kw4ObrPAoQuKLkc1ej1IyDH2RlH9746O6lyyfTN6srzkXb9vWHI43F0kaHJ6nz2cD
Iy0xMJ58FJ39sBVdJCen3S4FrV1CfO18xriDJ2eShe1vyzIaxw3N1VFtP9mBGS46TS0Oy8kK4SAZ
m4Ucg7wkMbDAkn1FjLvDL3K9vjOgJpEDGPyzx6cysf1oNyyg/niQ1/dSshmiLIkE4bEHKskm+/JD
NIaIsw9Q23gNqmd/1wgOkPWuALZZa1fVsWT3sI+5LYq1FLiAMMu4/LfUjc+GH0RfTnzMjr4ICmZu
PTtE3Eq67F3r4lazGoq1jvYAvRCOYDGmwxRrZ2T8GE/qWyD54gLp/nxhQjbaik4c6bXPiAecz3Yq
Za8MzmFIPAe5lm67U+V1SMAD4kn/CX6fgybMG3Vl0WBm7KNmvjMRTYWUWljquJc+8aqg/i+VN3GZ
+IQCtkX9y1tIuY8FHzI6Q2w2rC9NcitL0VOUuE2PkVicWesZ21SugQGVweNW9cv5gx8sKBezRoO6
flxNYMv0UN83wCZxqpX/GiZ+TlYfDsGbYpsch/AQhNpCJYnNZKVIr4lO60LfN+173doVnUndDOPg
OEMiSFOyl2ksF7kAz8omrZDaJ/+pYFZkVHO/2uuMddjB9qQRBkEDtBW1RQzDcUPWhKCMKp2cQJcZ
mY7iUzthrGRAcfutYoOQOMA6lIvbtbH1pz/6yKKsmaz/j5DedNOmcsZCRQEcjgq0I5EdYcRolcKb
ZEGt7B9LvHcuHVswi1EeqNfxjh5dDum03sP24skqQp2O4xdfqtVyOBvyRjYPpt/10EKGdXB75y7R
kiCDJ2SWfJNIKUWlvbN6FLu6QWq72zoFpzbAlZ7mlt5U+lhgPExyKn0KdVjT/uI2hzYYP6dViZp4
o8szEmY3TJoqjj0r5vY/VxricxPsgTGp/nWIQDxM7LRC25SqUMwh5xn0UESZXcW3OAgr3xvTQX+c
5fJttju6txEapFkkzeOTgF2wbL6HoRTnpiSa+IFbjGuSrn3uQndWrX+xZF/hhDefILNlvWPP3e1N
X0ZKZKXLlDwoQWmt1WUS3dnlapGFW6/tz1VHWVnRosjZHGi2bYfCe2jE9CpVCuqtNyqaRqnFn2GB
zyc8JFv7Dk6MpGAQW5W/MH3b1V28+VxbK+CXmD5HzgA7A2bZuuOHEIePmUVLCAR9SpeXoxUYwZyk
BWKjE5KC2QV2eaOjJbdLAJPjcBdnp94eP3Fxy7dAap2gOyQblmT/h4FE/9NFEaamBe1Q0ur2gF7S
OIeo769AJPRNPbFzt2ACkKmtA0L8BtsCqt5xA3gKYggF3TwK5i2/Px3/qT+w4s0SG9leJyJSIDnV
8xNMWjns0k6OEXzSSdql3hCuOQd3rCgbCKv70BrN1044VyboYtdW28dtAldk08XKNLSeL44XzAs2
7zp+KvZ2VrGE987MjuM47xzt7YZOr9xYzmSqKJ8/5giNh2Cg+M+VudRE49/4WPxbP4gBhEsNjNzo
Upa4h5U9VIPbfJNM6FYlkpV+3K4UMcqjOuExbrAHc4+BLK7nky9INFQ4AY+f5K30JCpEe37MYsDP
p7UMML+usoOFZYBME5b7+lY8Ii2iXTlTBK7n34BJbPKyZ1P4DFe5uT0W/aRxv4Wy4vUniEtqRDGc
uRs4bewPBNQIg313C4+R9R6P0uwG7Yvqc41nSqAL8YV4JorgZNGof9mJLBrDVuB4XFzl0phwtN3Q
tUWHCVWp7k76EM1ARTL4ib61hrT41x36Y4uRgkTt6dXvhwD15sxeE+ZLnz3ZPQyZuVHWtHS99UwM
CoQbe5vuLzPd6dRteL9nypQY8LSkFd8Smj4TKT/xjjgzg5VdqH+EFg6+YwCEuXT7Lvwto6cAKaO8
8+54Hrx01rBpS1h5QJ7jhMuyL+ltsyuQ2O4KTS3ZxeOaA6zMAz9t5oc19piYlIVInU5PC7Yp9Mh5
LvhZsaUwJkv1PlvEfK8spbocU+VCt6a89SzNC7qcHCa3fWp3txDd3stGheXYa8w32WU5RhaeJvj4
VrvguXW2hoKz8XGeLhtP/kBJZHMta3lTuR8/lx4pCorGNkuaaRA81IZ1jJua8ulVjafRyZAjXVMU
QvSRboe5qjNJOegBngPofBAogazzL62VdIxdaFhP3qMi44a40J8WLHEiqZWuBz0E1nu8ACaTJrxI
Dehn424fJ2H/4zD6ER1lyc7twCUVapH5Sic9MztbeaoTrjXt5fVinRW7FVmrZ3IdW09QBJaoJCnO
S4URjDuVblflBKgP6xaCpiHR6IayEtoAXijlr9bvxxPlYagkTdfh5psBI9E1fsDSGI0Jn0uo0rrG
8KAli9mUKGDv/OENz4D/riSetLAgFR9rLY6eIhTRSXE38B42ljJkeV3198IPvHPBNfv2G1XXD8/2
F9VAcLl+u8tG+B5NwEvCBTaDZ2mG9xfrng9INClENwEKg/Mg0O/RuS7Gd7WdL459TiCnTMZj1mJN
Ctdq8uIRu8GOlcc597Kx23tsmftKkydM3BVq4YPcZcQL8U3tZzHeoIID5DMyR1GNhcTNa1R4ZriB
6qx9WcxAiAPwotnb6mOuaM/EU5EOnYY+QhUnecnRvOG5Nleo8rMhD/VNG2JB3Dnnp/lkdXdanewn
0fTEgTlbeiWA8C7n+wvYjCmqT8fAR6oausk3UfI+Dd7/0/RmFeDcJAnCW1Xl/p6W0Hhaw6zSM0Ud
3mtTz0Las/m9bdbjKfRXM5vjxaYcT1dZfzRBYW9rZOUBYwoRfyJdfalLOXNWriQ6dz54yme99Fkd
mUNvsNTh7pec+mPW6Kjr2D7pCx+3/R72d6cVlqA2LvbH3GtQU/DWWkXgIeq2b7oT+NWWNZYdha3Z
M/92wOkVUKDlWEnJj4qPwqsobsBZvkQksRmNVUy64Vwf1I8f0JfgS3HsiLNQHsNJUHvI8xkn1McU
ZtNHZvI7qbXa1jm1U1o1Dq7in5GZy5rW5TjRYRZco7pIvlES02/3Xo/am9blmTJJJ8YGv8jHub6n
aQIGHOLNRm5VfcXqVBusr+l4U3IGr9MHMmqV7Xuo0UuA/EzVOVjBa0XMNlzyyhcx9p/HaiJEbcVY
2eYkWIXOj60JPb3Jq69aQUMa1Zn80RzCGCQ0MkMcGddLueiLuMwqyjFQodYOLI8H7hw10OV9VB1a
5mjqeGW/fuqGTo6vCTNkS8upSLaqA66iQR8x6Qax8RRfVgeJKnJefl55Odn6jgR6l2puUySx4dnK
1PRIySWLnVqtC6/gI9TGutg3lnYUS0ezV/+w9K/8mFo+8Hn6KHRkIQRAb0GMU6pWQ5c6noOcrugl
8nhMv0o9XCnl/6Cmxk4EdcZ5898qXQRJMMv294GgBGlgCTbs8gIUC+Z7Q7QygFpgCK/sFrg6rdop
ULvMN0wSyEEqeLYJq35Roz1n8XKNZWZ1K3CaL9j2hS29ZJ2Nxb+22oB7tLkzoTBp5RPnf3yFc9xj
CP1hwk8KRSM/inBiPje30jXHqo8ONBbQt8c9Y8NNCqe+q/nSPspdNcvdj1YpAgBDwR7Wv3tzaFv9
fnhRWynTCG/ow0MQzuso7ZJN54vHvkVnhZ+tXppPVnXwFs8Y9uP3DvKOnw01P1kKvSHxLNXzMtlq
iK+b+CM5HnFUcDmLQfOYn+Kymnu77s9MzdPU0Uyvg6IDUkYm2lY/4WBQsYEDWFDwy/hMGr2XRPUd
lilc6W+qaFRjmqRUMJFzVNFeFgLMCmjT6Y5Cy593joWVysy6HnUakhaOQaoE4jJIye/9wQbtRir/
M8XmW5wiHAbutE56aauCbG++233D3vQIbp6bVNGaKBypwGCv63fQdusofovDoopUAVkGu79p07vg
uod0WlnKZHWD1RniKLRtETCxE3jqb+bgCFqQvFjH1mzJUu4CF7uo4dzUrXg3HFdbwlPZGPF537Rj
sZv1iFmGNbvM0QWGvzjbffSbu+/ObOzhPGRgKNNjgXaK1sRmnNg/WEJIzqPRh//YgxadN9u369Oq
GuGf6279fW993kiT06ydrswJjPtvlFG4dck5JMDwEO7jgQZpR4Vrnc/iF0c2tDLTm2lKW/cJmW9a
Gedr8CeQFzkEOyLqoMN4rue/cFLekbqBVo+P8l9pQsU110Pgb0uG3nQe/IVxNtXfC0qU/EO8qYPd
HPImpSRLjNbwdZ7zy6Ug8Sva3ECDPr+7Wy7gbqtUXZW2kUtM8PwCqc0vj4n3kXmYmiPuvZfnLpJM
ZtSUH7IX+iq645jOHzA4IdvTFBbgfuzzLqOLkfAx8cHVr7LL0Yhjv6jLlYcPuk2B50NTeaLcMIwm
gkw71kC62G2EjMRPV+8KGTTMgfOgjRESIhTP7ZA9WZfUETF5aL6+w72gce8dXLdISIZoKrz3wsyk
Xs9TAaCz09miAze2A60y4j9QmRbc0H2efUbBtqqg1SGmtThTIdWVEPdjUtyTQGXkAm6Dch5Kza/H
HKOoHJc5T3T2B3fjLxD5c3Cyeu9MWMOtvmXac7/TiOtyMrB8Axy8GXLOO7w+UBJSl0ETpzGYIftD
CgyTS1QL+5aL9Oo/GFjwTrW1QfWxywoe3df6YJKSxniOU7UYjHNtHNMt7krrWi6ePvw4hogbJcYm
KPWANO/fN51ozQsu60r6CxfpLcJGDy/937EVmQqvVkMkKz1fVfN5m68Ji6FPBoCJ2ybMKZU/k22a
rDZCzdFlK/q6qB4MhJpgRNBMUDF7IeM32kZ3+DDKxBqyskymupo3XnzR/MQ5KNhroCnLSl2hITjI
H10I0nORDT9Q9hxMAI/Q3C+V+7EFtHfqVqoFnxaPRrtTTaMQbqFjUId90tq4Douq+zXpRC0Z8lWW
BajDWv2gL5zpRLebGqiX/xf8V/kfXS84s2Xirnyvwwor/BdtLFhA78L6PBH1jCcqGl9jdDIhIi4x
e9LTQYUoqwUZvTeHE2h3WVNZHlvrnfQZIF6pIQB4JlqxiSwKyiuAPchz/bh120seS3y8o4ihfbIT
Gwoi30eX40dQ5+Z5RAednn36TahD5lK7G54keDHoV4+etXP+cYzx1ZrkAMFPg7hLQWdkvHW8+q3R
clEWR+W8hUgZ8a9YpArl12k6LCPf+jyAqak6FxOPzc94ZeFHKxi+cIgWSnjjvbYiPhE5jY2/FEOg
EvervGYFhDBKUMwZ6jX6iYvltuRFFdfHLpasHUn1uLKBsfjofrJS/OQk3fjQHxzJRS9tKsWZBKx8
pQyGq9gloIJRA4I1Fh2NlmHMKO26f6WEVsd4o4WKZDoUtBoPQwbXYSJlAG+TnPrF8yhwb3on1pVW
CA03qI94if+f0OU2BboxBo3bYBaTJOtlAqTx4pt4mbUJpcm6hMFO8GFT+KDgAz0cYtLTahXxpgFt
tRyg4GIdv+PGiSJiF/zIL+q89Tw8Ifxc8/cqnK2wgrz2bmtC60k1ZabRAPAW2XxVPQ6oXNWnmUnW
5ZcmsO9h6cQdJjhnQxRaBOHy6n9hmW/fGSlepaw9/Mjz+0ZaR1rfMVjedRNMuvS2cNfFtlyHjtOc
c35Lh477qSBrVufJzYZdaQaJVtoubSlKl4xwozO6AY0rNjNtFbqs+Moz8cZe/xGJ+pFu2bBAofWa
TH7bZn9YACLcmYtJ+mGR/ycF5X1h7ushyk/cOG/NwRA6eH55FngcjLganwWpfOhQ2RL+R5e7PElL
mwM025tc3nByQqsMiPxeYSK744+2cyl6MxNSf2O2tnnrmX2/Og36qYCJdYwhvicNcueTUjn7hxp3
XJ+MuzGAFnPXe+KLMcu9261NZdv9JYViXnQSF0RlUq8JahbU7m+o9kCDilc6om0QBC/LPfcBaPFK
0PWq9CGlrF43qxU7ERk3LmEzdY7u5SYdGaU8DdGbOcHezeCY0524nmqJws56QzZ9ZgUCsX/XD1EA
tsOREBkkQwg2oa6jgW0Er4AJzCvhhRLzWjZW9dFi4I9924rztrtaYL+vUhtwlAkIwkgxSxecc9JZ
jF58Nt0GSmCaZEK9Crp9Dvf527xbndUiFrpBBIcwOoGlPA7ysh59WZJY+59M6nq7JtPbXTFzEYKU
WnetFXFfDlfYUBPm2WHNvXgqYUw6SQKY8o7xYRiYj0sUWg1pqcDqRrWBZjUEVhuqsSggCc4/p61b
cQBWXvM0eku5O8fRxNshxLXwUMl4ndSo4hgvaC7xTluLg8YIj+3MMDMmMpXEZZXG/Vhdmir0d5dw
UJGlzNwyDY26CGii0ZmxTLyheVHHliBa5ESDwHNkRTcMvT8xWerfCvItGQ9YcNxwKM91X+PmIufS
3DZdbzt6SjAEPS6+td4cEsYZwkV0/UZvq45pUPRd92bGyLS2v6s6Z9BnLjSxOpYrOUsYUZCCxQcT
xvjP1J18Xk+IoA+rUNtCBQFtGEMW4VtCUjhBkH9LnKfHs4yxu5RMu2D//uCuYQ+1fY+WFnn/n2z/
cmHQRMzKhHo8PPnUC2DkOkfUCbwQX1VLAG2G6JMzqinkqhc9Gsj17ErWpUtAHstWBvTzIx5m5Ibt
6FLjfk7Wtan5bkPoPhmLTLAEBfOoAv0MlQAb1WfGEQBsIP+yXqm6FqptR5RwT5LPy/QYCffTyr/8
43MQXHmEEp9ueqoyE1sTQGkNdl8hWDx5VAIKk6P32npjh7cEXnEi71J00qxTlLvw3+ypgjUZrDVy
vb5vM8O28gM1yGu11Oj8LmpE9z5OkJ4a3iXyZjMOh2n1hkzvbQWwf+80IDV07ooIOyMSXwsKwWaz
A8o05pPA0LSsRYM0UFEj+gAh2b9mxfDnBpmO1VmiNkyh97uv2tmRa1GXRgwNOfrgfGXlnGbD7xtg
tllcaQRkmw+zerqEFD42vzGv+xA5ba6igpTfzwWjP2yJvUdurjF3cmCzTB4xqZYaNqWVfj84JYDN
tYKFucMu/DuVzPuZUNEiMVAowZVe3gYnqM0Sd3BwgMW5qeFLedfNtB2Igo6XA4DzXhVfe2sQLZk0
bGg7zouPO2PXVg2Kx6GwhMafKLdBrjVBntrI+qIyem5h2Q9BJz2R+F6kseL+3qvoUF6wZ4xogjbp
05NlES5klfVhw1B+f4yTwlOK4K+miglHHscisX36BufpJIG/aWYdMGSYknX3db42I/mFKMZSXHeh
I9S8ebdY1+ry2OqqlDwdR+R9Lz64ID5hQxu/eDn9cUcrnm4+sxFJPuK/LONlW+gaf54iz6q4ziBr
yoJNPTb5WzsZBnmQ8kE0AOwQih4poy6GTQR6oxKBJinlNvEceJjVrJLVkSCtM1mn9SVbB0At6dSD
8b2aJ9Dp2tkc9LniJFGRenul/NCtdsY/HUBOB/j5U8ti0vEAF5ms3biCbU2pCx/337M0BGfCYNLq
pL7vDaMQNHva5xZOGK/kK2YT79BsDIlYWfnrJSXYTExR5ZERCdsTfxFElLEjkyHVA37kOsNSRW9J
hXobVOXIo/AixWafT3laH5/Wcq45YmLW7ZZ7Y6H6kuPFITJlDw0fgAtrgVqwcbWtiEZYZ1+gYBwS
Sb6MWzqDNxnvf+6TM6xI2Q5sZZqTglnAJDD8nrg0myp3sRtXGAg9JFBEJEny7DvmRK3Euk3MGP4s
Sr31RACvzenb+yOBilq//h2dhmO1VV8wSpEeOqcJSZ4G+vkEX2eQViy7Tkodn4yqIbwh7n8cqUAd
4HOlUKqyBGdsRX0HyxEsKqJXbMBU04rMV15xYekZX8qs9ExfvaQOnIAhhXMg9yefaARfcBr90/DB
SxTGk6tLE1bbpxYe9FgqTVQO6ll73H7oxueOeyvr4v0e8IzDIyQRJn94k63rwLOzlfJqnDYLTMDK
s3HeAMTt+xGL1zHjloxJWJ4y6BO3xCpglLUFjws73+CjKIvgVDNbtbL3+3cLYa/bYfGO0DdZMhz9
5vsU6ZEK2sxZgkzAYCUdwTSGAA+f300tDJddkfGAwn3bmxjD1bvz/uo7J43T94vLP7CvK7b6byYH
VFtneqbcYmoc3Pldw9Ko45YDzhO9EHtFyfnqxiHcEbnBaqnOqOvr4FUWw9t+voOWH0UodxheEtTe
omnnXFn/WdfNVEDQdUP+Ph5YmiMkv1AQLAfBzSgZoml5KJ1zaCwl8F9OKx00zKgTRo/zLV3scy4W
MuNZnwPz2qxgXQ7kf9rDJLcqxNIrCvtGPCCD1pjyhFmxQNgD5oXRSStM2RSgHOaGj+TuZyydMlTH
KT8QFv0UUDtPGsaK7DnUOsBgDLZOOYu50otI3T4nNFgtgONG7h/L/rWVPKs2hdCSDi7LiWPLM5rz
AgEeL9/fTMAZ7iV00jOyhfAavpb4lxkhCXyob/1hp8Gg0qj5XEXr6sJdd/jP/7li3Hvl5pRt0Yy2
0VJSDQ4k7xO9JifZD3begtwXFIgDjrrmDeMg4P7A9uJZPpZduD6cUntG0VMM7zz+uboZKQdCZJE7
NnIKx6zDJa2Ky1d+GsMyYyMP+PLe7SZSm0lmPf/edJRJbCpafYlLBBrXqRJlWOK6UqwuQNGYrQzx
eCW2T31a7Lhvz6KSd287Nllozd2USjYF5pduXY5kBza1uaRMY+ucjnQ61EWF+dn/jsDI5L770+Cv
EuxtNSJxKC4HJ4D+X+zNKtolt7Or6I7DtHN+ufXVzZfO2DDc+Gsv3tWBDQQXfWdK/Wn4LSI8DhHE
vvxnrW63zllAtCZ7FRv6LwnBGyvWvJhzIuW+/WTJrBDKMbc/oAcd86QDzFTM649riFKKq+bjAjnV
egEJzVIJnEdiO1J6a45O8irPk+4U1hKfP5ixZPxBdnYmN1mUMOCSsL+QZH7M5ENWzF5i0qUmhf6f
2RNCmD4ojfcrFudMgeM2YUfVCcToj3+CyWgq7Pno0b9MI2JFBFE0QQKZ1lFBaUaEEfOPrE7P3Pim
aatBBD/WrydIQgEY9qCMHbcQ55rt80syfTpj893GsBc8RpNSUSWc8Ozb9Lxy+CeRO09QLRVZz//v
vF9ZJPT3eNg0ugefGCLVe/gJq3geX+O6uirAXAejYSl22W+V1AZD8F4bkPQb5jEQU3doQP8sSIFJ
xH3RtBXmRpQWuukSLVSd6EoV57Z1eFWcop+WrU5KeZYp5zlRq6x89jr755MckYZcwDVUMv9zuMR5
Dw+JCuXFoX1OgqGkNYOaX1WxZV+Nq6NH/JrbETCGGXyIPbzPwKv3c99IBj6gnjF3oDvSzd2u8EG9
PHoeIiTjr8j4nEO2ayEJJoyIPIwwUolUZwCqISTW5QlotACbDSrw0DixmxSePOF7EK11dfElLqDx
FqMRdjt3MQKspyMG+/rUpx9sg6ln/u/4px3V/+sPtOIm1/Px9QoPPKHj7bujhAF7JW3py1vURais
958K7fpxGTIhHeO9Q43iWnxeRDsnvNwEgPMfnJkLNHkbU8riIb1VADHYzcNY2tI38e0/rSDmb7zu
dC9sTNXZ5DPUjDR/SDIexTGlq6qxsZ0JBti5mTWDrB9vUdnxGGCTeyRiHMJZV8iIVhuoISXPkKjG
YYOqt9VlHggHYQtylahN6nThkAuRpT0H6ET++M+gOqKlAZLlZrfUUhuHlv7D9+ZBurfMgvnzCZUL
oonclo+lJdmb+4M06uxHjbL4azStD0OnXP7/f+AscSfF6jM+mjO0VjKFfTKVZJAOAsEkHnE5gwyq
IHSEoMapBkML07I4u9A6EVZKT18LA3ZNZ4cOFPFSpXqT/45iDbcY92st8uG8iErHzn/XKXssGV8c
pZivv/9473ZITAPotaKfETSTy4lsbgI6flq3a2Lst8GLWp4JbrCqP3e23SMJAxtvOC3cnW3ZW8Xr
u9fGacvglGMJSa8QTUGVM3kchVQzzND2SF5UDNDC5oUikPLIL5D678NVX2YrEKXcXT68k5n+15KU
XfN/EFiSPM1w62/i4PJD0te8H3JgLT1ieKEtj8lLzd5eCde/VJKTU8WvhLWIKVK6ZFl24zXUau+M
muNSLa7o8ta9MD2tlCm9JcC8CRnGf5jdVMPFSxlO1NSjmlcggYuXxdI3UwQtQwbf8gsj3K5ZLrSQ
qRwmwOM2IXFhpmKzPRLqwjzVuaJanl9047UdpUNb/xKSzW9chLId2nakri9KeQtN3evzuKAtLO8G
WINatnak5avLhSO3i1VoK6hrYjPHDKmoJgnvvmHPt1lWaF87DzuFFVZJRXx23Rpb+MJz5k3OSimt
Qwq6qk1bzDNh65WErgeN0TKuuGb1xU4+xrHPrdoqrX3Wd/ZCVlLXwXU2zJiYut7bK5qUlzgJJVBP
L/uO4fPtMK7TkBOypHeics5WNqKbMjdk9i7q879HO7ybuRKJiNf+K8OcY37NZXD7AkxYkkM8oqwh
z98x62wPmV+O6GqVKNTJJkxucX3XeRRoEEOBtYEPHOGm2C0NDR+1s7hMbe5akItkvAKmhl4F/vYc
eXzRE284GfIK72XYq0/8GOD2HmLdrPbHhYeGhgNQAcPAgFOZzA/wPWLGnpXH5usZmkKd381zSX5V
IDdaxrDsJriSHn9VoM0RW6h4ZOId8EOr4fqQ8sy46DJ1BwahGnCcL/G0Wzi/fOJWezjBo+1Ka5FW
DUQYh5ucROQlglEe2sgtXoQfYFjnAhX8ITza5YBkbwI8D/tkLuU4SPRgciOEAdevanwQ9vKH93Do
GVHbC4b3/9Ag9wzstKlnWo/hUEuWt+vFC5+BeR65swclw9HVJG0AEHFHv78Xf8R2BjHL3X+2HGxd
3yLpIzUc6YPiozNMQ3SmP2PYrUTiybvZIrF2h2lVbiYTkPIxuzSGKPYGKoSDrBuzHNNZHHDWc0eH
lPp29NKysSvTfDD3V+XXyZ2Lnmi5m1J73FlAUQicAdhDSdqy2F15uruSvACGracz5q7aCKzsra8M
5uGMtmk90jt45SQP5bzarnZdLwvpPBhzqiuvnj4y1qEdgMzBVq8SgF68LX//P5559DKVx6bep3K+
cHwijXxMbsY5MR1peZAhIW2wYdp5lWRs50pbtApFepxJsrmVwyqFJi3/4JnUL0T2/2tZw1HcLseX
M76MkvTwe0l23ur1x0hXNbLg32Ou+ZsEWDE1x6Us9rZhAeJ62Xo0HM+KPqVZJDL/1JPqEDWt7JeN
WNkSE8FGbYwT0sPKij6HlrruSDUSHfblIjKiJAYaoCM3qJUuaSAvWXAXPV7htx4+gTuVJGK3+Gl7
DmJ7tTWA4ieFMB/eX1Jx5TCoJizFSMGUi/mcH6LA3zXtfAmuKz9TuGz9ACuyZBZM9wcUuAqBhW0F
TR4adhEjxhg6khNhXP6BOz4laoiw4/z5vrRgUcmngGDLEvtPTKz4rxsCaAyqYorDcwh9uovBM0//
iD1ttikq5cGO/DX5zZA/3ZXI/pGkbUDh7pHwVW4gjDMk82vJ73URHDLprGQWq8oCXtZVUu5QhHTq
cN2gPKeUM71XyxacQ+rJ6/9MyIuKcwnbKH2wTwD0u6PWUDur0dedexyWusQ1ITuHlupTEfwBe7p+
SaGHkzdj8IyzWrCvnyUMeCx3wRgRKYxzU9//R1caDgv/gTimOUQCFSkH6BPhgO9yGn5qGecXmepO
QLWQv5ixX0VIBNSDU3Rc8xmQ2oIjdN6vFG2Jpv9wbadO9pvSIXYUxfAAiuDk96erhEQ5phmqEE+G
fAxHMZhH2IdGfAJ2/iRPcxusCLlJfmP1UiI2CgkKRv/b6x1SLOCkOQHDocNSpoA6UHQ2+WzKMREK
EGSU3CFQ4FuLEKDveQdEczmA+1E26pG4SPoTaudvxwYn67vTNa5mP5pxa2WNJJ8O1PX8rajaqqDR
nBP6lufxPxnLs1Z71uxMCEVEQeJEd/1cokItJgLsqC1vZHt9mRol69sk00Y6ZTVL27jtKWmhPT5H
acn0muB67HfEc/g8mcKOZLG1vQKaGDm/tvd6PBKe6UMkKFoNADoyzC2lyLJIxcpQX1iyurmd5Bl0
v1ladhZCLfOBADdsIUGET7nin1ULZpcr4RiwfkKaWrp4mbf1i4KwBeyx2crc7ZSOenPuB+EWael1
WzHi8q2OYKK4zu6wXNOgkdBd88D06ypSQRUpZ4eMXBYrzKXrdrfNqodiGqJ6fOSeUpm2H1UfidEv
5LMgLTIVS/LQ0pAXjf4yXjyOySBuxOdRpdTvKHzU9LdXwMk3C+DtWQROlpdfebCNt2kAQCY/412E
ghMxU9sfhtbO9gJWxZoQgBr6GISm8ILAAmmEfwh0+YLHcAEZfEUbCeQMsFGGvxLJ+IWcQWPDWIYF
6v97wP6sNxx6k1xTvWofjLYK6VBNZyRDf17uJTn3DYns4dGCBFaCF/Fe/6JbjU8xOFUmmxAqsUjX
akZ6Tgj05x6qOv6xASNsVbcSAqa5BghTho/pzVI4TYMZ1CN6nj9F5jUgtCha9EgjDqzQe+0VsLUb
5aNhF4pF1VMRli0B9kIL3dN4ChH08kmxC3HnNn7UIQ6/GI6c2DxaHIxXdzpbsEOIiz1kFH1huoqj
ZxfmZp84zwddSgDBz0/87AXRSZr6J1darsXRpEvN42IB5m1wajjStwvdy+SiqRDrB3iM9uqZfs3I
ZyF+i7Sb9KHOozf99xzCYQk6AkKiRPpZStOQGFr//JHphWb5Ky9uqnv9Acoz6p7AL9mf91Q8HKPH
wBOpx6fBwkgMHm/0yZQA65bpPASlnz5RQpqZpWTWLdEwNWokOxBeJcJSLXF5nS2JCMBSwRKjTxj/
wt2pd7Z2605sa4DW4kpTLkscnBQpNbbVXjCvJVN5KTkwuXBbVQj9FEYVqA/HetFED0qE5WU6txTH
r0BnOZgWjxKerAKT8kQN0mpAHCUe10KDSkO8vOdHSz+9YaoAPFy4ArHLRy/SSNsJL2R1g6alTBgu
LstTeByZdQ7Sn57vmdzxVL87LZpLqoANf08yj5FXS+lqkJ5GGowq/dE8k2xN4NLt7w9rMcVFBtKN
9P7hRYNEappQgZSD8l9/WzAXlXQ+vTbiDS2lIF0GNmY9CWzwQZgTOCpiBz4WPTvtQd5NVoOiHPKl
3IXHGzxq9n5YZiKpf0iwj1i5xUEWgV8ZK7N0hzhTQUr68a7BWRjGSjRRB5zXfrud9PVZH/v/u4xQ
DXpIZ9zJuwlpmsR6V6e3+GQlwaWT8QaRK2QR3RhTr6RT9hoVsOeKctwPioG71uYqSSg3+GhRgfI9
6g7mi7OWnYo1dT0QQyvyUb0A3bwuHqKbFaB8z6n2DPHPEQFy2K2fINlCEaSEZKqNkSQEST7Gctuu
1vM7wIDYeGfE3CAjj0VLzlVR6FshHNsxn8vkyCPYalRqPIkYZkg/SSJqwduqlNHKi2nBlpYTYXeA
47qu5m2fMM3byEtGagfdc0yYi87Vty50Xzz0+kg8dE+ZRe87xyE+Pb1VFNFw799hfEnGsLsmQG3g
Df3f3JxJauHJDh0Fx+nywaEzUXzFZNW7D0dn9axTs0nkP/e60eFmfAR1h9qp8AsM+B/L54wBVo7F
RmP0v23hT9M1JROfnaJ/BvbvhizGiC3c7tjDyPhy5+5ModJH1A7zEWexKbTGXGqf4FG/GjxxV48F
mnMcdpOZI+KGfLLssM3XjAJyHeikQ44v3Zhdb1qwRW+vdscJgF6exrfdFTYjXCzrGvVu4V3RjMd/
ubonFsmKq22Qp3o02PwfXbLMTCl+qVJuvS8c1S86dke+wz45maPci4IEXORuzbEpngz5pl8TDsCC
cZCBZKwzcNSzQ2SnU9ImETxAMPyyVAMLXW+nF4Q5g+n06vJ/SJs49TMkExlmSGiVu8+cpeycYbkI
I5xNaAZBp+Nn3cL6XrqEHYAAuC4Yu+48e41mzOlB/ukom9z8C3AW5lQE/ysIBReD3aYC2E73KyN8
AFLeq9dOGhk4cEUNN/WhgbgSl6G3aH8TSbBgV3bPnBUaLQsolXxTfbPhABQBbtIaOHElwCGXq2e/
bLq4I+cXPnmRC2d+gxqTdwiATREsmfhrEI32EB7sszZtPwOkfo0PMSXZmHftLCztYp9MQlv9TXOk
2opfy5D/FdGYaOzJymFQFtk11mTT/4XfAnQWZ5Q5k7XxIrocJcLES7Fcn+2Wt9cpSlfKHYHopG1C
sPXuhz/B5GdPWNpLDYA7uOtVZx+v19rKLBBZV2SA+AAy5/jUSvwcqU9gotlQ5tR3NIcAGD0PNSRx
WxZhwRHNOStGIQBa8HCRt2zOyNviWPtgGdhqFWjsq1r16457dhuVXHMCZuala9d+gO5d+t49sQJ3
Dp4+NLuj9U7DjzmoNAklyk4zXfJwbVPtLcUptsD063C+1OmNQmYSRm8h96wSSpVKSG/PIArhBD8R
zTiEfPYyFDtO7ApmJ3bYsv0tTV6o0jkxPfBIvRtDwzNfGO7s8OIP5XNeYBLTYZyzZp4o99+MsXiy
6OjV8UHhDkrtiJ2iqw24ZObPpZ4xoqbMwaDm7URc3FxcdcI25iD6dSgWylPEBND4MzKXvp1WWSj7
RQhAF0JXu0tXNirE4/8zqYxsEH+t/E40jbVfP4QS1Tf6vxQAFIRs84hMLop1yxoLc4Ck9qa3L+AD
57AS6II0kzuw9OfgV/QedvOiUF7nyxqkiiaCwfaijAeWF4YmNIfUWPUcUwm5JRbXOBsqQO3AujES
W39E5tL/ObBo0dwQ95VQLNiwmubSJuvY1/ekYV54vux1wiBRvkxX0rFmYYo/QnJOe6UIuqTxseyW
6/48xrBmcJQGeCtKZw8UZeObKtWDGzWyKs5Nips2NdzPu8DpfUzhJpHMqkFkbOTiVl1QvP6/PhGd
lAmON5+RRWxLn8eeyG9ObYro9w6WBekNhONmJgJHDsHk/W5GSgn6iY9K0lEyWfcjcsUM1xCCMxAv
i5RWJ3FX37WLN0wYz3UeV4VZazJoqtyVN1LFajDESwPnq03F6TYsRtLrRp8h29ErS5Tdk75yezQ2
DC6+Acw2mpBPIJKZAEdxxVs5ZIt8dQTGCEVqV69oQ/wLwFd06n/sWf/kteXOneDU17t8KSMRWQGS
BQyZR5IiFrYJhIOElctEYWCl9xHnU6R+ddPP0Q5o2Cv3Mucw+8NvJzmDlZAnuGFi1hfKEFJDi0D6
oGpJOgmoNSQynm3Yz3elIzwMmiNVGTIY3SZDPMi5MG9YO7q7+kdOVcBWGT/2SlEFad34Sfv/yz74
ppH5iFLbZjO+TjpkpsdkNTZeLyZFvPpYnEuNnbnHoJaPygfSC76LygXVcJgIjVa6CzjbOSMp7g7h
OWNb6ixZJF9UK7+eiuAC0R50nolJx2t1Thl1U3VcFL9aKcA1wPc7SaoWIICNQplPz5Gbx1kcHNti
ZmyNqEgGj2LkncxVvRvMOEyew7dTph62iZ6FRa2dDlvzmtw5y0kFKRmAOwKNNXAb76+3Hd0Z9CLX
oq4gd/bO9+NhI8b782pKoR+nzmLSMO40+UTRhz6KWDSPjb27WZHcZVcZxoDxi7stBJf8/AipdunU
XY8OgE6Cmk8RRohC8sgFoy+aDSL7PGNuGkzcOeYohYLib6tq3tkUsRwJ/1ruMbV1de42vr0vYahV
+MTJGjbw/7XtadZnBWAfJ9xPUfDsnny2LA6jAcbl0t8gZMo1hsa1wovBjSwxUsj0Td1DAYxh8nFU
HZ2kiolgcN/vfDNypAf/PCKVcdetdskYEYOxl8zk2ZlXMsql2y4qjjzwC2FkiBPks0N8WDg++wdI
jSn9ZmEtujciFxwbDhbF9aEniJJhHURaKbnaas9JSVuD0RiloyaaRxAR59gPaIfdWFmxw7W0ccgr
xJYM6ECo4nuZT5KPMR9LCiaRB8A5fWoiJWtlHXWRvis5Sx1IO4qXq57bvKQMT78geZaFxBy1bx+2
ZSZ3xiGy2ctWU3NWer1ToAZ4ldajPlq/2mfUMN0MClHek+HM+9qb1QregaBDEnP6fINr0Ggm9zWi
y6cxFBqEGjYlAM5gJ58TmnncIVKkv+2Jp2vgDgXoaJAvS2v5m6PcRDpvm8wlW6fDkmD/v67Jqmu0
bHUoJhE+Fz4JYUQlPcUl/Gj3C6enQRnEkMUCHa4vm5oqjaHYHdiO6pzn/EYmy9AO4LzyrGX6ob9e
HiTA04+3dCFRqWLOogd9llOzOCng+mVic7FLhVX1xjOP0mjVsBPdbiisHEKSyPGLVqHMi1uqUBRc
cA76kmHrD1pSdqZePci6tqSKahJwehQAMq9QC7mJWC+gS2F/r2LeXz+JnGHvLzGR/scuc7lU3Nvd
cQn8raOmgbZfUZUYJMxEAjWA9fDlJdjz8ubxsmMw71t7lzFjmWjQ/c1c7RPnN+1z2j9gs0NNFibP
BZpRBd9nlhT8vSpcuiFis8nBuf1fxYaE5j1rh11ZbopWSVJWpUA1+XjmmZMHQdQHEoJetEZA5QB9
WfSbHrogJYiFqOoWYj0xoRjUOFjcBCiu6WYhGVYA/dK7w7TmG0ynURM7ytOV2x1l3FsIHGTd6j8/
R4k2gw03d0AJgUEOPJkrouVxKPPpkmkwCOGZuF/DyLVae0XQw19WByrh6/0UnuqXyMGs6HFSxs11
B4awvjZwmMPaWih0NYfctXx3jPFJz8DiJbmbB0OYwT8OwudTz/HQg/AZZXyRIxZtAJIeZMvBKPNF
XdDLpTFrmB6Feis67HXBBCEH9IgM1HrTbEsRsrg2lYD4O/MYvf0agjMzQLbiMHS5k95/4pbra6ib
vILmoTuKysp8J0wF59ZXJLWrwCAGT+SYSPALhV9khN1o33YD+3C5wS3ZxvcW09NujPUlX5nO5C/l
LkXARfrS+AnERm+mo4cq5VwDzrvxlWA36YkfatZbdtffO+D+NmjP4VMAdo7v1U2lOlUGLT7kFt7Z
Xx68EOZQ9De35V2kItZSfq7/AfjwL67XyiPkQXOypd7w5qg4YkjTfuDLbmG7ukN2vHgK1ulN/3jU
piK0bew7/6QZY7JIYkcOvad5QPUnghVElu2WNXNcHjn8p++6H1cL1e1cxltmnfml/+DBN83AXlYj
71JLe4FIgi0nml/LG2hSprKBjPOVPwcXNIs+qLwyGDobxKk0Qi+706y3PeJxcBHlK8e3S4JvIoRA
8YQApUTZFSJ+EFC1em/4fQrX/QUHWNqsfKTMepXaJzXF2lskCmlRErb8f+lhNnuKiJyvRsGxteBE
MmExoYtuJOvEMRCtid5x12wDDpR73htFjzF25O8sPHVUwjgj71Kqsd7tOM09MWyp/YGZa1Tbdcnn
fb/glE1gMghCGwp2RONBW/1K3FEfi73qKDmcf3Nh6ko8xZ0J0EN0CAvj0kBYj5QnfzbX3I4rWTec
RQ7MjYP35UZFrsEaFg9CS6bzWGfwu8dXb2TtXmlQ+7UL05iyUpqQzVwzQBXzgprYTMx+gjly9Rfb
VxIgqG5aZ+KkEMzgyMvV6+vd8+CgtdjcNQmhRtkNUhofDEyPET9AWBVVUIzxSRYscr5c8MfuA1QM
7K3F79PxiVTIiuaLA/9usMfi+LD84IC9NP4KTugIwetG5g6Q4emO6fM+apIqasrY4RoAY2oBcGpS
EUqW+0CCy8wmIHV0sW7moOHz64zhF5RwiguOAo9SW0e0D+C635icd/cncbffEaWt3uC5A0h7PI4x
JCruYyGhK4WTIDioN3oNxMcBqkwHKVBPoa1ESMpuSTqUcJS1sYwMvXR/Wg5CzZgnzPC1y6xTVy7i
t3/w2VAT2g5Nz4k2Sg8hhmLwwzmeQF9e85NGQ+ahcfebGlJUbvLgrZUGBbBJMGlU5m4j+xo3KA5n
nREmSYzF/sRdKpq+e+MIzSEfpDxzRcPT/CtbCJt5hKYQ6d7eb2I1WwBne1HUGvawfWR9eMnHQ5AU
PB5Q4L5MeDOyYewXFCC2w0ncEr0Unxmv3Ki2BIu7v7tGNnQbCQMga+K5ZMEu98DJhZxRNFFcedkx
rNelS6bp7cj1rNZXmqNQ+u571Vce/Mn7Y3xbKwPBOaR6zeayC7lbXeXhJqH3tajqgmwefpdRMVS+
9gpM+1Syf/ZTdEIKA/ghu93voZy2sqivwNGA7f8OaNPiWstpugk0bYd6lynrXtAHK2J3vs62cIK/
s7TnTSrh+XoKxOZpG3aPS1FY/kO1jrH44H3djimH93SM0nYRcn5AQfib5KpA6JKHM0H/rvuu7s+I
T6KrXi/mw7Qu+ld+gRK5Rv3aNomrPXBoN2oozkt6eECuvept0T6zfqQYg0ayhyBlvhYWcIJhQT3l
PD/zaohyDMb25ZO+avn3K0DSE77AKMl+hNllo8ZShtGQiZIM0E7tKirJkdWS8mWem8pctQVrMgL2
AcJ430ogk+zWM5aw4C4lFw4+zUKWYsUHK5mVQKbMF0TqESvaMlV0p9LZ0N8y1rYXSHiY5PUJFJnu
muY8KEd1XVq3E5YtJoj0q0NcWLUx+V2yIRnm1XkhhqOOB28oBesIlmxDUZygRs9lCRAFkiojK8wl
abSpHqnP/wgWY5MiSMk65xKQcdjLYbEqM/GexoZecw2jL2AFwBLkqjy3z2a6VRxrI26fJ5phlmnX
+XVZpY//k8X7R8ASEzixKU/3AT4cUaWI/EPBU76lknOJdoeu1JeppTP36GzEkOFp7Wgnt7wILOnR
qxiZRVZOlKiIDbjo/kULPLbHspbH7mYJ5UyFBYGV2zPezVHhsUtxQBd624X2SY61RchYhFYKZVlj
7M3Ps5CCuIF75nyDBXPxpYWreArs7MWXadO+7WM2r/GtLyRx5zj72+N4f1vgYgAekaHFd3FmvFZg
C3NgPzpPikuH5f6qsslmYTyHgJy4uhHawGOAWZc9orm1KJ/wmWTvg6lmDls9hYfhgxMUH1XVUut3
m5FuvrjD/b5dlIJq0Zgs6KLNE4/UptLBS8wxfr2k9g0gx5mJPD0dD625Qj9VxFSM7C82mZ9AdAv5
G69JnvjoC1jYVWqMe3JhfB3qmofBPcexSLi5X3fb+kpdCu9/fh3J7KQmFDNR3QfFi+F8JyKNEV8z
yyqPadzZzrycCQNFNgaWeZpJPkArwgNJeq9LmcCl/IiIK02CcI0lcgUlGfBIEX9OB2KTjOTAoAnX
72hKdMG3cDHNiR7teeLpl76sJxmt/yuhlJUVQYO0Qq8gIePo4DqQWr2zOpIrAgrTeXczV6V0h/P/
8jCdUvYcOlUcM1nILLS8tSRIaDMG3EfVq8ABUDDR8AE4GiZxqDW2RXkHtl3jtohG5QZkQPfRdwPW
3I06mxvLjQHa71DNXiL//Yh40zetZIMbE1sNMyKTGNWJhZ1e9R8mVcfNlMxeM98RUM0DIg4oQh5t
r3LuBrHphR/fvqNeJ0qcKB3icIjvMP+VbfG59xooJXtHs2hQGhHpStOj8Nx0BhmitV4Il9tAp71D
FrsiCaKXBp7E5N675ePcZ62V0hN5Xd7mQMEv1qiLsGp4kzklX6gLp6rZm4f+Pim4MQ9Kzxa0Ls3P
rCnKqdYinJ1QK+RDRLD4beY0fygCYKkeKYCGxFb79PQ1/5WdY5/gqgOpjhNoIzQXCIF3i/OObTGA
28efRDCQutl2GBds1C/0C/6wJ2OxZemVjwq3SsGnqcknS6iay5rF+7itl7zVC6vfiTfj2aXhrAny
+GpmztRjLf5AqLUMUe6k4y1VO/E9zSO0cH/TdmtXwPlfDN1rwYpu/5sghwzEynERuCIU7p0EEAmJ
/NkWK11J2VGVMJemrmQMD6rhAvkMCC4iT4voWMjlR9Dou5JLzCIrEpTOojQS3EGc9uc+9XovOPDl
8a9ii+2TtfsJJS8rN7MlRy8UNZ8u5vl/8DGT0wyww2NmSOqCRj1okV0Y3UZ8TumKmpSZwFooIevX
Sj6/HHkwICExQCN5V80vNzLYwMA+00LUfC8eFbQDBlWfUnYOz0WVggvpQeM7MMIlKqqXmMU5catM
m9tYqc3i4KsD/doEuhZAsT3UO63czTCyKgZGY+YyFWfHRpL80xu6fqItKCHVeLEJcfKuvl2yRlGG
3cjoh+rwWVX1eF1mO1BLfWWx+uzUazDrnYhViXqm31Hajq12Q1xRqWLPcuDw8Prx2aBqwoXBvuGt
gSpNIgag0Kbpsdx/axTTR3gswiHZhzM2yp9QbMegdEp04cItQ0FYh+rBxEXyNsUVCLCiswvhovIh
/vE4hb77wOUpdqh9f2SuFtOPm0SBZojmsqe0oW6uhMzEAdFpV4/y4NFRBtx1InA8mbJlYIYQ8SJr
gWZEDYlfax8Q7umjWSWOWoF/2cPYOwRR7lRwK/1HKIjrN2AoGRrVVPs1Pc45KK4NgRZo2BJPXRho
6l1BSibP/OqHPg0fcXX3LDy0fYvp062JUIBmKY8t8Fjor4HRG53JQIWX6RgEd11ttYgM/vD/EDsO
msEiG4DcFoNRxuEvnIA/GuAug1De3FsK0VV+C/J7dMSuiyc6oBEMx9gIlJmn4jJSwmOxpPwf8Xec
wWZXeSfCxmcvpKVlRIm9DBr0covZIIbViy/N+/SHuFYJFICf5NcEOG6iEgSFPo/5uVUZd8sltxct
JxatmGlno5nl46MHXKvlDdpKZwADizUB46+SSjIFC4OJI60sUGpzRv4mb3JUrArR9Imm2S1mrMJE
E8qMwPwUTQM0l1I+ZjQGC7+PEvdCpCbUqh1+efQ8Yza4/EOk7qDHwxduA2J4rhQLn32dr5QeGd+S
BadFhTEbctnI6i3NGIHQPtVo4vM7XxLKGYJISGwkaiZJtk1dhkeAsdyYwa31sAy/IxFZkR9p9U48
60VAr8VTzj9IjWXCcYHctJKnp6g2hxrh1jz6/lY5Ea9F+Y7N8J7GSrvRUU5vsVZpvTZgYAaWEonK
N3gaYFWXTZwIrsci2Hw7L8kHRTE+865ZrvNloK1zDaiQlsMiQnAvnmTL3GHEGN6zZFrh54vqPvAr
vINQgX7X6/NI+lhObLtA6FLv1ZETdPhS8lri/o6lvMosEE9RGld9yiSvmB0/v3owIb+1FZ74Xke5
Clf77wYuz+XqyImbV4sBpFPb+Te7haF+WhXCWdTzU+pylW/r1tndzsW/JC9H69klNvXT/HmSxWe9
eEjHfIsU/8/2UzIrp112+1rvLmPrTvGvnyrSlxx3jxvDBHnHPjy5GQzWERWmgrCrUHXGqbPWMcOQ
yIGpWxXh8z3Z+IVOVpZ6G5siieJVgcOkxwMC0OloiTIEVsbxjjLY+BlCkOik1wGexdwN1uS0yURC
rrn9AmN5+ncjUuA1r6pRMxfyomIPXfQ9r+uGusQbOB6romyibszFFhuPJFz35JterULZDjDUu6MW
caAqsQLKJCxvxXmyVW0ADb1lrWVOUmHzQCe4EQNDDDhztE4qemvoXBrw6VKmbFCWItZN6G9wPVTu
PeDnB6ge6k0aJoHbA0nvwv3L0dt6nCLVrIb//JxgSHQ+yCuwR8Ang2kIYVcBGSDwEADMhg9+JdeM
Zi80eP7Laa8YW9B/avHJZWC2eMHsyzbRsuIkkCCoH3//CENcaPU+KCKN8TALMUSYm2v/qLN/lWpm
B5mpydoxIiS57wWMF6/U/8wsed2rqTHRdstrjH1dKCKM1Pnk57ZYyUdcqHFmtMi3eLQu5Iykz1+p
BLLe8ooreHHF4w74DxsUQ8+mXbhmYvvWO0Srv/euPjZQig0cbxD0lgmgfl23HBuRutsLIvRJiXre
bz5FkmpiIImecR24i46vN+CGOwOX8EiPsasr7nsahKRE5muT991LGfQpXb8Tr8ZOu4ctX1jAbmY+
YES3N0ZgnY/eBz2UIWVF9yj/1Ozl8PY5IO/H3PUyYpRfMcd03Z3Dn5C6M/EfK+U8/riHgd+51rYx
jx+377ZtWGMCNBuzY5t79r3cQi2E8IZur1xDA2r2Y7X+bHMZsStBpHo1Q5ukgxTRQIMmy2FWOvhz
lVuyt1d0EDT8K2jeLzKzVzoLA7M6YyFSKR6nNRRhakNobqFFmDy3mphghq80P2P2AoskwRyYuXn2
h6B+e4RrKX1sx06hiIcDWp7EgjWK3cCw8sqRKzBl+i6/nII3sfkUfhRyrixSRM8rU7NKTRgzYgrS
ucYjocScsOil/nt6NpwtoarxakPT1lPihI2zqUw4AUjW6rby+qJDFW89/un3ojFLRzYHH8/0GL7d
FGyWYKJPIx/x6onbtgrlCclapoLXC/sxqNY5mOyymWsdKdu7R8pps9Kj1ZAz1YO8kBOl3pVQlzrR
FJAIcAgPDuqiiXhFh2hW7HkDNcT+W28u1kJJwU5Fx5rxpI1b16BYfeKOvbEpWKHtaUB8B0xxtZaA
OU/EGc9p8yH4XxF1Ayp02Fi23At4uSdSjvpa689ohkE3+zGeJhOizPJg57/o7dty1XJLNzTxgaN/
ZHG1QSNo5RCaYcM0smM/AM5B1HdnYw6nVKWDixIQZm3DsoZeEPGjYk+o8TYHNBxY4Obv3UN6qk2F
5lTjahuxRGvgRxK8UpeukSZso6ZjHfz+kOVaF/nVktFrYU/hCX1G6ey2wDAT0EugX1NZEssXVkjK
lZhIYPo6HBJdGIVxZJSZ+ass+DwaFQFWEgMyw636ZPZqRfon8PwOcE4rIlClgHlVCI87jJSmg6LL
KqjVlY5DBdebb3EMlHX8V7bPVqxYKVRkbDeI7JzURIeJV4N9i9gKkbD0HkUIF2fdfd9VdcQVu7Sd
R9YNvAQ/FPq4Vwd/Xi624mfLU5gfm+c5+eZ1EJ47yQDA7pqxNeXnjgWbshiCbzLjd052oPd6O2zS
IjpA++QI12GXdhqqmpTTwiH5whT3ZVi1ZgxEHiihtQgNOXuH0zvWZJp5DyAP5hUKXOkxSHMG+BrW
2T8OauK7kqo2cn6lFYy0p+ZPAaarWoxdgCs/HqbKFBpL7HtFdS4vLsMCY6yFNfOjhxg+fDgcj7Xk
N7YZEhu9aGiaTeqMWNAwuJF4pCuYR8T1hueYM23oC/vZTw3gveChivhT8VPmBeIcWIvdB9Nw+pY5
AReKnWHD+dVMT9DNkG/i60z5nFhZjQYCniHodT8u02UtYh7/5KTeyqP4gN8W8lYIwvrcnn7qlkZq
gEBZ+DJ6gM7IXKTvYmZqBYxhGhN4al0E/1BHRxOjq3k8YLVeqfCutj5vSA0WZYmKwrcHNa3miDM6
3z29XX6xbxEGmpik9zwNw9nA8R9AIijY//b1x+a0LlY/2Z/bpaMlCcOPm+S2aAMyS0Bum4rrliDl
t8JjhQzqGMNsoUdpJRi6SJXtxAZrahob5N11Rrqi7rVYlqd4r412yqss3+YqOaKCX2IkgS7+Wxqv
lG+HcvdoMZx5W9gx71NqLwVeUipBCD0p56RTo2JH0TBvwJt4zKrb1PJKLym+67luBRX8TqIBgDz9
2+DZByxka5zfdrOtDVYfrfctvB0hfQVEljDVl5bT5+p/A99XfXRbfuk9ginra4yFWWkM1mJ3FHYO
YE75JJ/KvCjq2sCyrxR22osP25A80oIyckibrJUWTCD0nwGsymCOJZ5EOcKuw+1i57QC9T78D6i2
P1j/637dS0qkOYDQtC21wACPMnCHpBk9BEsIEFoPuOyJIDAefcy6lp4r42xtEXWja2AWlLZLRcBn
mbO+ogHqS2kXv6DedOclSYG9SEKjYxK0GBg5ZOsCWhEpW9757qtsmdjPog0sLrepTZiMMFtdnmvf
PpihpQmdpJ3ilB/K4YJ/4MXD+j58NdGshwwyBdJs2d3W92maF4eQc68G/FYiSrohUXqz05hl2LUU
0evgun4xWvljIcVRrj1x0IAmKbnF5v2E4Xwdt2a2SO3iMB5cPWzE1WuaXJy3p4gs2HUbQejnS2oZ
9gX98Mo13TdRcgH6dj+K/FHVhZ9hpdK9uE9lTxXhqjvFYENsOWbC2QDyGVVt8ErEn+QUAPyzgpSZ
u2agapweZpVoqJcfGE2fT5ErSCwBgjEWl/WtFIr1mt/0cbx6P8m+ejmRbCk5aYj0wsUG5ZDyUS5p
7cGzz8B2pm9MrhX0fJ9qFAFRa6U9MXsqTtwcLdHAfB9MKgw1YAvTmIBi+nY6W5sxyJprCdeK2IXy
FgvlnlekGDbonV8gMQf8EbaNFcZt4BXekXzD0RNfaEgoFJQ1qnGl+pcDAXFkRp8MM0YzR9Ul7m2A
oY5H9p86Pxx4R6WH1UTp2QrTj9/rXgHGWHe6vdwL644cFPXMIPDKSaDWQ2BmTSYtqJl2XytR0kyc
c2oSbheW7LzOi63ENJ6CPwSszTlW96+gGe6kLKdWkOGumvvPpD9hk1tsaS4XtdfvcSkah9/llaiP
ES9LTfCEyp01bvW8wOnWgHEyxzkqeVeboZllUmWGMCZ/H40xvQNXwAMwGtSGpvhht++nwG3LG3U1
JVnzUNIwwNXs+NgJTtogv645D4Yww4+StpFwZGcdUNuoVw2qoJjkIKkdpMUm2qsllbriw+O+tmYO
iZSoxMjiZ2are3xiClarM3dUbcvUlRn0nIywK1zR3ikdLAgRLZke3gmeVY75HsUp0bw4R4tcSYvQ
jWVof+k0u60huMG2E/Lhmqin4fDHmeOdN9uxGXd2wHk/dxE0WvHxC9R5/p5hszeUjK6rUM5d/Za1
JR1hXI7GULsPyLJ3cYOC5w5JyalrSwcccZ+qlwtVtFKme6TWCoMTo14fnP5sfVWnN7+AIwYNL8iT
i1A1Mr0Y6u6lIJ1QlcfeLspTCHYhRP2r2sTKjHCG1oGk3j0pO4zWy0bLXFJWIOL7ltC1E2hC8zM6
fHxpJq89FN9HNJwKNbsPtP+IHRnTzfDCNV/hTtkqU+23JlimhiUp+raGsymF5JNUzn1JmqgFJjVD
ljgUPlB7JfklgYQy9fCMhb6a8DxqA8xDb/V7IV4aHfe4kur+F2wMb41n8tZLRix6lsppKyMqR2Rl
MKsw1vQ3anWI73il/QDC+5RywCyGkZOkJGUzhPXrFhVudCKHjVAue5o8TUM/GX/7sFczk7Z2rlIa
FotZUcS+h95M+7pbCklNDMI55fChI0kKmPNURvmHttoyf+VXiBnyy7ksF69SBZQ9QIjyrg8NyBUz
2DkTXhy6zEjSH2QOSJeCosEX2Q3hr4MMAw6LdBp8V0PIg+dssygc6UMZ067gb2q/vm9jAxXy/5PC
caFVmafQq7LwwcenSspIbTZP/3H0C4PtdbWjPfptFKYb1ssajIFiVw2BY/vo6w6T0J/fWtgB4Y5r
i4PwldPQSdasY08TVy6f++HFUJVDFm0Y05US0wcitm0gAMi8Hie4ZG3/Mocs6TNPq0V31/pRJxMd
B3JWOb3Tx5xyrk0V7CgWvuqlOGEjP62k6Xpgwuvbwrc0wEM9QTgYX15/GvQYR/wGxJ5QQ2XWGbER
cEaGs6xQvXWRYYMxJcsk3OV85WfZPDU/qhERG709Bub9gkbaKSPn4KV9fyKppXTU08355GATUpzu
tXOjJynyPOCVS/Kl0m81ck+Zl8Gdg0Ud1l6H+SGncPu/GUsqAFLJHpyaAHr/73tLDSMXWPHg/oNm
DkLIXnQ2rEkD/sjpl5dSF28NYE1m+XDn2gXyzVk38rHiHA46zrbhOhbRtxsNLkC4JVztXOljkFGQ
JppjN8MvR8xGhALO7FuC/BS52pNo2fJcvRn105vQeCeBXZa42E0HXjdGeNAEmYkZWEsDNtg/T+7j
Ebz5sUtOp+Cgjx2KDlXllMyohYqrXQ4CU9wKUsECH9jX0qQYvuC8DWQ9IGcDa2BHpxi7E4NimWwy
+N2FvTcH0wArPJiohd4JqY+TIUC1rOWUqYqXUmbfosOaap+TcjgdfvGFrX8OfdKZ3raA8vkOYPo6
qVLs9C+V88tf36p03Xw16FUTlpbTWvmVedel8qX0GI/C4xYjk6q10zwiDwPOlVaItcSFuNm3sDym
idTwMyN00a0cbdg9kDX4WV5y6LpQJSazhh0vqa6EA+3D7Gr1p0xSTpZ3+vXF583KWxZAWaUsjjAA
rF6RzOacos9bFm5WPj1ZYsFdPoTlyGvJGcqzC0WoUleiYbdHB5wBcXP1vT1lMRfX/jcjGydhHLPd
NuRvVXsxDAOqtL1PdfENRyXhr+0OArJQ5EQ3JcDaR/nAM20/TtTWdyjfyDj7/gj//oNAqVG0//p4
Asa1DMSwwb5wpDs4lq/1acoz8i3HRR05LpZmP2hHiFjXe/JyF19mojRGHIbM++sF0Vte6wMsAv2s
+WzhB3xCuA8WPJLDrtAenTMXhW2CaeFUm3h58as8ysphGXRsJJcFxksFTFYqVVTvCrL2D7sT3BBs
byS3lvYLDwd12l+7yy+sb4Dq/dtln1rcLDpcvd4eKX+rVD9q1po0RtCDahC0gSdqPCLz4I3WhmfZ
8mqqGWrZqJFI08Dm2vGgA9J6KtVqeajG8e7yKdlCQNQHLRHqTDLk76rGxyBAFukl0n1aBZrTd/hr
xk5doga9glFgVho8WnqIzZ3jPFASVrtQoZMW8lB4l3Dhs+2Z7+1ko/ak094OnuI1EtSDKbTbzPr2
g2cTsM8DPU+iyTQ4iXRXfDHMLezmZ9f0yRKl33KkXuCtj/RoA2jChh7po8/LH4e0tr9mQ+yH+Ljv
JoT3uapxz2CJjTJ5qQiSyZsSY10qKyY4wZ87jXH/ApHa/vQOPGTntr1ZgOJjW2z5zNlc0ZXeGhoc
DCWrsv8z4hTqkWp6DhF2aRUGxAfNokkcxCqZBhJC6DL9cETC6nF/ldPwfERRJFLYBxdDHULM28KC
rWlvwJpeG52thrGSgl6hTUqAbexne5/lw30Ov4UIH08pMimbtUXIXLsS0QTNkCA4eVHgky5QVqX7
ukM2RZvR7h5bsZNqsCFpQpm9Tav7ZajLc9S5l1WZgikPfZQHpr2iITGoGeR3KHRimpMJ59HPkaSc
QBVePyL2iRuColF1OnetrmwDO1s20TzFdi3XNwZTGQoAaDjPE3HkZyze4FUv0peegu/85fITyCVV
o5wpvN/dJk9cgjikwxNot6UxCRR5K+Pcv6WQqWqL49gbbf8AB3WVKfRXi54OgaRC3GxyZH9uncT0
xwPbX+mFm/gulPwjFwBhPOdAoafyHW4KZT/aX5e8FP82c83wsNUbZ3pD8TVGs570hDg+Cdrk0frY
O1QCXLMPVcYE2g1MuTR2WDFXsLeymuPVyqh4pfnzsTC6VVu8etx7w0vp6VcIVuZpVFPTJlVHjaL2
G2neAC9BuxqSjg6Dpds91AvW5y6kcAKM6zcEly1tAOtTt6BXzji7UOJVINNQGs7krlB6VozRYSI8
k3hXMV2MzNGJAVPibocjgdoI+wmhL5jGhabasFHLbOWtjLbSm1JLduGs1zIVKiL6d1ClSQlFLHpQ
ke2PgnBUZfvaoRhQF2HBhiskLJORcTHxc04UZ8AQcpgG+xZVmpr1E09OeApoVN9GUdICmRqB0vL5
d8VKePFoJQGDKubOO9o7XjR4xXy5haomCWBJKtwzoAuBYb1UnT1RzAkzO9zhaugNjjIRg0wKlTDI
XJbrDRc1ZQpLWJ3KpE657drRbu4kisXK7NBTDVQiBL8pNLLF/Zd23cdX8mTBoSdKzL9iDg2a9yjI
PTlZ0m/pUPRYadK1/e8gMtZh1dW7I+8+LqMl0ha7J3bDTh6sjeDpuYb2xdmI3FNDdCpKxXGtCE/A
sUae1yFXShIQ66omr3XEplLy+VMKgPu/+1SPBG9PNQskJ2HN4cDZtjSOhuJdEqI9kIpAfncM6m/8
YkSxvyf0QNXKNDPZeIjksTifvaVDgC913kaJthg/x31g001OBRdyzVs4V2htCL+YxZT0sOqrV34l
qdusM8AY1YmaRabN7fjOSXPVIKNaPCu0IBkzoB6XBzPBTLnAU+W1DacYT/IhABhDFDjTzJQJalYX
vL0XedmaeyxExbVhsFm+HdgaG2+9CulsK9ghcL6ljelwoIjZCt5rekB2bUuf7gE9XFWlbc2m2rj/
qhoHy0XO9Lq856n93m2WuUXJ6kzUorWsk3g+zjImpoI9Jx2Zxx5MtJ4fZ58QAMlks5b89FfkASD3
NZkWAe7DzTUTVcW8mpKqHPGCWHLoiCyfeWdpaPg+nXdSYnh20ynzJpP9dgy81mK6k4O0CulBiJ/y
UYqo/wPNkB96HrXelhVqRy9tLRgvtLwooqAsHc0MUWlaAyBYUUvyVuI0z9BiMQvlSvsUrIUSazkT
u7FyR6TIJg+WKloUmm+7uYwcdugxkX/xmv/GmBrUkmPW6BLxYdcWGFqg2YEd88Nl0FSzaXspznrP
f9yQI/vDhbKbTMFBq6W6nNSnmcEKgd7YOMyuaOD9cOCgpJOjk7dEj2xvWISU8HFFYstCLuqPlQ0Y
JhvV7kjTkUouFrr7Qnt9NB0qvMUjJFVqWeHs1f3GydsC2f/Hod+F8o5SJZS9Sr/lrM3OAzQozCGQ
syLBtTqYHCEDAhevdDkjWTz3/yzkXQUKdHB8XDF0bzIliXo8CoIHIrTWVpyxrR/h9IRMoKlZ1z+G
Fwoa5ewzod4asvTOpkugdZLDBNvXjsJ/Y52UBuQXw2lM4FPvqB/k7LGoX2mC72cCXImRYroTEoVm
v+9c/JEWcjNYWwgC0gviMVwLkhzlmWq7duD7qKwU0cEj0zkz0+249SH4+TN9XT7e2a8uKHP3hXSW
RK7/CqmPVEmJVYUGxtiiWxtuCagYVYsFbO9HqwLHf4B0r8ePdXLJpWjlj6EZGgsxqtjyWLG7d8dP
YtpMtviiNj2vfSdSXpS6lbZr76SyvqpgMcNBlb+uRmCPpfMcV+6oKeZFUz2nlefa07rp0Uz8seHB
1csrXaxuTA1/2FV8gVP31JDfeayuxYuR59655g/AKlxxXZU9eTRAdJKSfrtLfRuQq4XHYYOy8mmx
YTfrwgUI5mUFDJWPhhfoMcdyRQb3xYrHpVGWLfdz8Y4+0gK+RHklImSoe+5w8hFZXWISi420bQ3p
+c++IMD1avrbBZAHMaQKpwKebtjyhgdhmpE7OgicOjny18cP2EOoZXhR6NX0ZxhfZGGsynb6TDs+
eK+OxeZImpheyfTYoN2LOnuAMN6mNqzRtNpOY2U1YWmXPNnIFRrFFFk5GJgNBeCF9gZTAdGBDdXw
Aa6VGoy1XylvELJkNy0xC+n93PNoYAVrWlEPBXQifxwOhzRbNnps93fi54+iaGU/+w27KtFFQmBB
19FHXIkUZmQzpA10ruQVvXovmFtCMWr6/86FBOOcMLSbtQH9IzPWnvr0v6tpuQmHzb2uvCyGDf7s
COhURtal4VxWNAHP5oGQ5NVcKDxXvnCeWtyc/sO9dqYIgPHMjDPemZw6vRqIlgT91uUUp71Kd/mf
bFGludrieUwZ97kvZvqCfNyiKFZoSivp/lH+Kiom1/yffJlf4LiHF4crhoOak6B9yP6yAmhuQXHd
x0BxfUeB9xvbp0tD67V08cPo8OjIkop04WsBVFbG33cIGqc9wf0KkCau7W4POgkbAh2ip2kAWh6x
iK9OiO2lWquW/NaDTc7aXpGl48MgdNrhcawZNKlOyKmFqq9rvSUQ5NTS22IcWbVUUUGe4RiJmsNW
c7CINMg76blPcLTK3fxNurOBCcmCN0f07hOxqlXmz6l72adVLJ8wRKLjRg+Hr97KkMvt79TTkDrL
6FrRb+b7OEVZoC64/HFU3v1prwq1l8/T72kUpxUqA658tv4/CDSZIWQs/FBGjLGxXfYQKxt8GZ/P
6Ipx31i2GXDLJSZAFnaLn0EcTPPrchvwUBq9TW4H2ItaDiSTMTY6vnEzrMhVFCfkZ13htfUqFKFh
Rqwnq6UGO68B9mLRUOS3axF6GfiCqYBaFh4PtHitb4ltPhiTkAR4AMf6puwI6oGiggfkixeXavNI
OIXEwism1CaJK3rfJ7s2STezSS2LY4/gmQS1xLFE/g1/3Hq2gSMV0wRT1u2LPp2FaDQFSTrk3Jj+
UnxMESSfrOKQ7UDWUb8n/JQvMIa6DLzIasZ8NaTDzHrYOIrfPLAfLAqxSfpOrpBQNMmTiMe4vdCy
slGTQKhdlq5h4cHDlipKayxicS5Gs1jhgMbCQ2e+1Y+s/jLICa6NG2b4Qmewk4FQVtRwtfR1GveS
niuUzExQrabPGbNHB44s55Qk98yQEhI9TlkU5PeCLELSXnd8FnQ5TslCWQvwIWznbLTpHYgJCTvq
p+lS5A7GCiGiifEC7lPr9900wfYJIN6Aa+bzjAC/FZdUepuglPyubdHdQhMC1O4GjUaTMC9CVbqk
j7gzb7718Dz9qjlJD0WMyao79g8UzsUedHDvlXcm3elftBG0KIEkEuwiuBmvn9m35n95u8KwUZOK
UsdWZAamlgHm85vvFo79B9f4dVPB5mdM7eSnIh2kjH6mx7h9clwQAV/RtlU3rrWByb/ObiigXuRU
9lk3Y592tgznwc6hszP1CscLQkCqjmzjH9gwL/BuzAQE3FM5TZsAWRBa/qrynJPCWIwoBclTRuAl
eqmC829a6X4JHqPr4aB0GlK0GHXry+JhrXZid6u3MosZUhA6Eq2y0oQ1jHsl0zFWnipEwl30KlN7
r1usskn3Od3nuBYr1Iad/u4AwktLYrTDQa0rb2SEC2/4Tkr5/JqnVZ6mM4O5/Hoh5HQLlxzdQCQF
lj5a+MhKTSR8T46/qNrUzQjcfQf+2dV5QuuK7qt3j9nf+893Yk/5tg+sZOoaBZirbzKm5HyWc8Uk
4vgJo7rtNorO5+0qosI7z7vgbRDuWxPGrnKFsd5YTr1fFi6C/tErMHGZgww+txj0EczOZlyAkdWZ
7cvY0HzoxwVl6mbWUmqq1jTjvZ2Z+KyjNYVHSy9Jwm8uudRUd5rq579259upotcUvmGy8whe+7LU
7hlVCR2V3uyyntsLcVx8I0ISn+mTryHfn4Fdd1d4U1VBxkZ9+FXy8bFnbr6hEe30LeJCyGuoWhnw
Q1eSzXH1FPZgj329b/YOAfXEywMdQfIeeTrBHRTRV3CxTzwia4m4pv8Q0SAedNCe5OdEFM4EhEC3
rndmtbWN5DgmCYOksA84WyFkGhBBkD5PLkKnvji1Ue3/GcjP97EKnvtjOeDvyqmsxINa6ekl/BCN
aH0/85yj3fQC15KshuaAd9RpPM7rMisABnf0XRvxQ8PBw+skLJpIIiML+BUDz1qEtWCf5/l0ldQU
pOU2mrjbxmWa5txhrZZyyRDfgb/w4/VAktzLkswCWB91fHzhrruN8cn8CqEcjzx/A3HYGJrwVGHp
eUj+jLi8FOfh3RwQpgtyUUQqhNztn3htjOoveod8UAT3flNsqyo05CS1aPewT5N9EJ2pVLtBJ3gP
/3JlDtwzP0EpQWURR2U6+j6IHWslzL9LOve7+bJosOzEUWSuCW5Rro8IflfwvANAhOtB7xNxqt0G
OqHlDXsJO+ttLjLx+Z96aTtA+Ds/ig1LR8bWadfmTrHEvxZU5IbiPmiifR7BMx3cgxG13YpJ7pP/
NT0ZaS+pDO+w2gJ58E6EuhVuBO2OyygwcHrCbUl15vbx+bUIdTzhmmmhFFbMNS/0khmMtUA1TS9S
RJc8gMy1FsMQymUWKV3MY0cogVDXAKKuV6Qblyk3/Mt6roswzQFYrgo7wEVIa8KssyRd4B5TEHGQ
YtMRa+W2eZS2srVdyr9u+2Uq6/S920JPgEDsFUAqmPUSrUPewq4XzTNjurQoC5ms4WbwqVjB/NjL
Z81rmdkaczk7un5SPJjLoPkES2KpN6Tl3d2zbCtv+88qRPE7IJjtCWRqr+6xPtLqgVTnx3N1eqCA
UHh8RVZmqI9Iz5h8BDCTGH9nakBJazRrArxEBq16BKpLavuT1+E3Q+m4BboN4SC2aS+qCGIXUNHX
NWKokdUpnoGRrORjEpaVeCI6qicYEYuoJlv06mzwmxagjEnOYhxnucQZTUHtHEwGJ3Keb5wFHASS
1cs0BHFjGgKkPBIKS/6c35hzke4AT0V9uwLw53quLHR0brObZ8Hv+9f9bxj/t3fdWwJC128/gx86
3SIBNkNYyanZNMmq5tXXeITeeHdD0CL4rZyZB5Ma13GrETOZwx78io+SY4d9rRkPnfyGjqPEnH8y
mLtGYz0gZZiaLeCvHV1/UdJXBomyB2qlNExTDR86U0m9b4vWezSub/q1XFxmT/Ucc5JZh91+IwE8
6tFy1F5XOarfB1d/kZk0Nr15DX8PzvkHOQ+uPV3dO8M0csGpD/d5Joq0G1ZmizzW2sCGddpxCaKe
4yGVqYbejiIg6/G62vUvREFtXrgAm38WSWhIsv6hG0y2cPhmzwoqGmmIr+PSPlYI2QCUd3RgWuwp
XxX0fFwwX48P+v6extG+Nzo+em45aDm6tDeETd3s+r/4S6uGYbpnwVAVuStvjKcwOJ2RmeoSjKoS
QzEutxpngfRXyeJL0AddUsvxsD4E0C9UFWv9pqSqrarg9DvL4i4moQgFAGmhPosOBtP2nWT7sYTL
jq7OrWPXW9UO8WQ2kYN9L5OtCvEgkIQRBCIVtruO1pCfy59PISFgG9C4wE4lYlYShOYpHUyApRXD
OmcJC7SEW/8olsb0vysBf087skjOJEls7WZz8ITQ2tGbwq2CzYv4aUPQBN6yHz5xQEkP7Xpn4Pk3
jKmGTvgjo9HBMUzjcdEvdZlJyxIaakYjd583e3lsKVjePMFqxSOUp6Kuo7GOUapY+7cdOYhthqtp
3Fgim0Zi+k6dbs4UaSSQssJvtQPNFFRerdkrYrPy+2BJE5YAVFqCKZ5EydrwZB0iVFVVvp6Oovt4
ObJNPB8KATsHl4YsIKO12xcY1wL6O2ux5dFW85dkUORS+uxM0hOoiRVakCLM4SR6hIravHBBEEoX
GblQY40OlvEXpvRTULW2hzoa1QJwhOtCOHbuX9OW2te1+T5b0BvU7Tm4k9JsVvVIyGAmz52MSKje
D/Em0vjTgPlWyV2Cun8q9kr9hIGJdeFy0O2mbQpEFdalRRLBEuuowgQ3z4ex6dpwnLg/pvImojr7
vUxa3M6hVabGU6ij8d0w/aTxveQoLNng1c4TbkUPbV+Z0C8gKAY09AtEElb/gAeETFOOy+8PgqXb
quwJE1IgpKU2r6xMcy+HziEx2+qYycQEt00g0I5GT/y3p4rLL67S3V9zUuM4YbQgbGWqXVJrA1lN
vTqEX53E6hNuI4WupU9Wpl5Uu3Ji50t2rVRSNL6MkIIBSnNF0hJ4t+s4SzIk6eRDrOAZc95l3d/C
yUVCNVm9f1kYzi2yOxz+kT+KqPJe3vHvKWXV2pjSa+sO/DaFlr/+fkyi2eZwNLevkvGPTWJ3RAn6
sKb+yer9Erkg0s+M/qnwQ0xkHIF2uYydIf8BPcErk5zW0KI2QrXHOgFrIwoxEj5RakSbjwDyYZYd
Xy33EKgfk1ALfSOjBEaG88XKtzn41m7AG5NekkquEUdrSku7kD2+gQr0a1IJq9zJ2YXEdZAwE2yq
Pb3bgPYoYmsbAbrzaX4mSNRB77HIycJnhP9/zuhuoBybLlYrewNGJwcJue7+QfiWuNBUFPbm35Il
Ul0hlp6qfuk+lztBHChxLKVeTEzei5hSl1muas/5sAwaBxlVrfI8IYIWWfDbFtBATwUH0/dODr76
v4RrOgJVdK3WoG2/1riTXAt+K8H+W0QL+E5ubT9xsBz3aj1pHlMSPVGbHwLmcFUYaouxNLf/Creq
OmA49z8Vome5zgCweR0zboNkgDAQV+uIYQZEo01asJx2cUmxOjyTCQmpg6yzQps9lVmv/qOd/i2m
OJZcFgMRAxGc415vXl1Kz8rkm1mGodghQW/4gA6cdM+/duGT43I9ij+dxccWwehURq+6MaFfZBid
OmZDQF4u4lBn6E1COGseAVTjOHnrhFezi6Va+nnmCBu1KQUli01dVa3RdMvVHKrtJ4bn4wsocqYJ
C/BHbsb056jc1XwdEwEPz/Rg4auTc9OYq+zk19vMCMzEvdQpIZ7VwSrym/cs6TROdGjP4a1iQoB5
YhzP8B13PNGsWfgX/9juQgRI8mgQMI1vmF0ISxtc6o7tojYLiWouNlkiqOMYuhL7GM48rCaCbaWd
DGa/bHGaynrls27z5+R7ZkAt0QZjb+hGsVZadLYLLbykcUiSaSVoNFjhvoTqCmfEeXHQuiqDOcMS
XXaEV2DVnkIqUjw210M6RwC6CqZG/RkOQgzW8ooBqJ8NWyKlZa70qtSYF0E1wNRK/3ETMsimhFM9
dFiqNz1vznA5bwlvg7jYD9Ir2uEGqnd3rc6cV6P4uoS7/DW6VS81q9NB/fQ4XyqRdsdWfIItLSYt
XMdsS2VKLIvMJqCvtPd2uaQV3RFnzUEh922uQz1wpWaIHCQ0ygxboWYhscs4AOId0+uYRHKnjMvs
oawKaXwNPlzaFq2LHWQy6GAyGYJDyMljUMfisx/esek+mGB6O0ebmwYs6w0fZG/BM1MY7mk65tGJ
QXkc+HON7sInXDPFIzSengtAVTsCb+XVxKtPTGVTsXYwTo6fr4ZAzurzhCjSsoRLYQ4+XEhejWeq
Z5NGudvRkB1uacmxD/C3X7/quqREfAYe6LHC2hsKxu3TM4N/3tOYuK0K7zB3576OCK9bj1j/Tzso
ZUBUcCUsqL44lZneSGLfoz9s2jd9rbicEeAeZuwwG8gdtjEadkqdAW0jifWw852LI96AxVpEMfyY
cbTAg+V5QbWSzdPbMWheMr828ptiSjEkQsHOwbXKQnT+mVUKk4UZkqN8MiRL2Qf3GtT8YAYMBxz8
2JPwqooarxd1YR+ZroIhRtxp+THweUrku0Aqix4gReFXd0FRI1uU17dztGnu34wOtW6ZkFGozsar
4VFMz+/03GXvCpb/BDXMDvjR+6nXO7YuMCKFKi183idpXQ6+OTFRhwDWFqnuVz8vBXM2ZJkcdROp
mSkUKi9fevPRPHd8XcO4QSbIhApjksnx983qcimGNVHZ/YkRwBn4RwKiwa0kPvi6o7cv2juT9UKG
8yqLKjTYfUWcVS2zimUiPgZahuc9OUhagZQhQSV6kcieyjazxKMZjE6Abc5YD5hQU4NnphdJSte7
Dz9CQvc35L7655abnXvjQP7skRMpxUAyMswfcgudHs/Mx5m/tKqv4wqCPcbtf/qEqcLcbya9WIRy
NDFpari/kpBqvj8zFrMobTn9fVtl2cHp1fC5/sXehiCKxW4opXY7sEqdY9hkI5usqJcnkysNhdS3
s+TmBqXQ/nNcAo8Wh4kdR6UnUpZRyc+I60m3mVKE4GkaKW13FT4BEfCs+8PYIR403XKFOu6R9V5h
3zhlx4I3leFxAn/6J+ga3QfHrIARI6S7coXECbv2ShmaIME4Khuo4m6u+IYonZQGzfXPsNCR7ntg
ONEOZod6HCA1IWB3ift7G3lI5m+sZ93wQnhVdm++hLFA+F8eLfIkVER7+knVWb202R2BBErXraSW
X+KDLIuUqFiA1vzmZuQXZech9ErOPMnnKJnsEeboTeXJpxkEshHqVCwmITKCqLDMueCM2pxir8U8
afFzl3mWKzCxNSbVcoO862sxG0kTQTP/76CKPD6idtQ8faWyI/mYeZ0w/X+YEhICHrOX2IR38Qw+
gFe9HCDaMpf54XcAmru6ewQ9cWbumWzA/uqcyz9ArGyFoAIZEZrdaURpLkqwecK5bK0UDtc0ofZm
1U7DV6F+4ljMZJeyTElTQtYJ+4c2J8bOjc6/B3CBPrOPa4E/c/bTx1FC458/IlhxG6tOJPTbjmxb
GLWXUg6/xa46JLHpbvbI4iguBnEEipQShiwJOzmmRJ2y3JdI88p0fe8jMeB5/rTyFeeW0seePSss
DO1rklL1rpUmekFZyCzEbAMkXTYU7JbGrpg1oSAgqIqZbJOoNEnJhBRt+b9FL4byq9XFvxFawbve
Eh0iaUil4WslGegjiR71hh7ZdM+4tDiSE+3EYlHjJ0XfCf+NZUcAyEAk08gAhRVjZgLrGekCE9Bk
QQ3i21t9ihy1p3US3JahuSf4K4r94s2whg8jTjkb9PkvDRUigKKOvCics9rBNoB/HgmGsVlxDHgc
40w8mwKJsrn+WNXoxwLTTPOFWdirwz6Vm880KByZ7i0hHVaDtOWvnCgjkWPa4l9F8pKRDswfVUZP
VQvoPI+Kp/2+Ttktq66fWhQ3R5KWjoZIykbtkioFTscMp4u0HQ2OV2QShsTZeiyFijIlEISU4iEo
NIeLSsUY2w/+e8pVMKdQnYw8TwM3nYYplkqstVK4V0JcZwlqI1NWfyAxNS7qUM1fBGrdziO+x64y
XFv71dqcusKMO0S1DX/cpG3CYHwrDx3yTftkx2Z1iTPHxhPN9Kyn1NFX0Sa9b8lY7eepR4oBVIpe
Lw3GDA36YFK1o4gq0QgvLU/8EOeJHIgxNoqYwhzAQ9eZzPkoFDp29lb05oB2WagPJ3SHv59w9NcO
24h+xPDJk6WwD2kNCALMDbL7VkY+DYlYHkjQt9MkJVQMibTHbJZ5w5nXY86JNlPBzfjbxZ6guwgd
UL7dM4o+qZ6z7WrdBHg+lgu0Cn+XRME7TVpB98p5rM42N+g6ta6Hyy4JkHCbVl4YJg4ELV8AIEt2
TqoTh4R9JjpSydBREpQpkilGk9V1zkOklvN8z/6ou+7TB7R8miUbIULLrCDDP6rTFww68+B+DEGW
+rvZNK/ftbzetPC9+mwF/PfcFXOdZMwfEAMUPZUr7bG8QYs0Lq6CSZilOvpKUnQStRpFm3QNk5x+
G0O4oUcgcwoaDkBpWWUYZFuwfXsMscILA8BvlE4blBw+JPMhqij3V5rS5Nte8K/3q9o+UkJWNVM1
y+B9J87SFccuv0ohV7RdaiVMoAxE/QVAU0fXKKgq4f3i+h2h4aAk1x8ZIO/TqX6Fc6EEeQ8iCjcH
rG+yFhSnNNu/53RGMj+HzpklfunOcK4mSrkiK6BnZvzMG2z/ezsfRIMoDKshPM5E0Pq1GNJB+kdA
Pym3nFAJNPFXI4XWr3puj1zHrhEn4ViEmbnoaz0tCiIWnDskZCIlscrPCsDveDF05AYNkutcIjSU
dx6mrea/GsrvfAyDLRHJnfimcxKIGypR/i5IdEbAjUh/jJSM83ngp/cyf22QDszUp/ti1/qaTrKr
P/+RYqZboad98/HGTEm14zT4cTaJCo0jFRXPbuWuZjf+MQ2Y5ua+YpNc6cWlHLDEdapj3po/J3A0
2SPGlDU/7uEVs6NL9+OI9JDZ+Z8yHtw0zi9LFPxmCEechBW0etMfZhvQIH0rKtgwI00vTFBkzQz7
f0DyZiPdhVi95kJH3mxDGaA0gsRhkHddse4ASYMAc/8pxGwjzjbowU46woICPgOc/vntvQJjwfGV
dJZE1Jg26KSRdGEzm82l9cL7SPajU/hJiDAAkWZspTpBOxoJMPQI7GpYAqQ46VYbdOBPO73eRL+i
lyNGWPRU5jKEVS6f49KSxiGu5sG0tKpuAoh24X0qNT0qGTBOBWmj/x1uSuxoDiAcmniEPDmyvITW
UQ8TIc0rCNJsqrX/M1qdsIW744/yI8q0O+mk94aHxhrKAY/KIiB3KldjVOoi/43eGfHQ4zAUnfa3
RSxtRG5llAG7VTOuuLm98GeU8AkAUyGyHD8yVtBjS69CqjD3htOSgPF2bWnrszebs3MUK4EEDiOk
jdzT9mG3cyWN3wGCpq/62vxuFc3eBMdN/fXffySsihNGowawwl1bpt+F4ORbpvvGhHMgJFwU0mRU
mb1lwMyf2VnlABTzXpaPMUtjFUWNLNKFxNciwaV5Nh4M+LeuavGTZLUJgy8NcyeaDPG5luL6DwfW
8zA/hSZ1FMb7jL/DKrf9y1YW0RXIEyGeWezs6TqcXopa2ncTAuk2ExcSeFtC924sWG1y12/M7bKT
Zt8N42YadeYHgCMUG5aJhuP4QGe7dwI0vrfl3OJuycwGJ3tD/E//6mLgP6yKHjE2IBmtLPz2xznj
8PDxrwJLITs2WfOfM/A1QPl1IxJbRvc7oppLeot4UEStVr8R4HjyIoKAFdKgTc+ysBSQwJTKQvF2
1yL8HyCtlDNm/jUjCJwLZT+IeVd3kSTq/CMHY0cWzC9IAUQVruL1d/dqFLvKTeq4IfQZi5Vsst5k
v8tEReKFM2g252Fo51IKqm4oO02QA/LPuwpw+aHYbUiP4cnLwHott6G23CTo/s3ajwI3PXp41VXD
wO0HBiJ1wr6a7C6snJemUOJyw1FbReVu7PISyfbYAw6bl946uAB0xbSZZ26XvEoAsUew3G+H7Jql
voET0/+LolfuYwB+39istR8lUfzMlsw7SHmK5YQTlgDYORzq2kcoA+Yy4C5p3e5QOpTqrJwQK9CI
bYCRDwEhnCh6yky5djXW7S6JHQinIOM+zMxplJ3yOrET5C1IzRfYn+gOz1qvBinhtrGabC2CIfWM
c3O3Xa+k4khcJdTxVURbDECRzpu93xTuLNlk2+N6wsE63v6lNFoSkZMRVUEQSKSbFUmYqDoFau4H
3MZFORgS180VcbLoFtzsdKGeQpjhfnP0jzdV2FflL1vUG/xRW7YZAQUPijOk8Wm/GrLDQergneH6
MVd/Ct4MohNB/Km9TZfLo+tFi4xK/29qLwAXTbz01VVkyrrOZVNsvJnyeEkkdmVT1TCjOmUHf/ca
fy0Jxl1tj+FwefSOiRNlrvw++kv8IN+5fOZw6ysBcRT4ATuF4tLLjyYABFc7fe2IExmvHVws25LR
CbqtTF6oDd8/qnuESrs9+N3oActQOsZtS5MLd1iSDsBB5j7ccD70M2AdxDiqnHcPAkk0F3y5wGCu
ByClrnKgGd4Rc1OKCZJSh0LbrNKWZ/qIznw5U/0yLV+1S4d2Y6Ld3IPLIeo5vNOoHKQxBvGbZDmd
h6IwUiWylJfTDInBM+NiCuVKxhgo18ThXNPZPBzNXoTloacClCHQh/SmuKN6M8p9QWntUweVJd+B
PqfxaB2wRBvHaNHaXKMdw6Ay1B6HvyWWewdIOJEGJMoLGzKXbSNIi12CX5blGGMlX5LcIw34YV2e
UPln+iGPtYx03KHx0q968zb/9Q8f9gh6ga/kGb8UpSh9HQihlhagiWsT+yS/DF2HfMofFUUIqP28
Hep6oRsjdwP/Dpx9mrpcKWPzSWu0oQHGyYU7P0mpsWNC+H42CdpofXf/RBNsiEHWaISvtCmpRX7h
zBrfIKLQK8Qc+nPL7gt+XJUQmgU53DdnjZaaQ4ZJ1k4h/nlBDfSJfV1GLAJcjH1HIs+eDX3WIEeK
77jR8p7rFEHGuGwAa2U8/Keplk+Utefeu77yYc/ruedVwfD+lAOtvZcd++Zco3Qd5ATvGtgjDcBi
gdt2VGBFSmONVHg0CmwZnCl7T/K9meV2PlK/j+m59sThFodR9vj/3t9oziYj6+KVLTtFkXjPWsP+
kQczTz2rNTpt1GcVcUxCnCFx/n0RsfR48C+Uc+gE2j54VB1aY/hUq3DBuIm96oOo2gv9EoiVMgBm
w5Pkpyu2P1jzCNbN+Ph0pLXTnkejvy4vsDvD43i6NxX/yUWH1rYcjruZEeL5WrwCqDTy4wqXvOnn
H6rXBzDo9hTMdUQlPjaIbhgBxf3nLArz+NXp8qM/guG0OQFpHwmLuZYM41PrIyrrNSN/fijC9ucx
IImlr2MsfZ2lauPLa9rM3erfpV7LHw/Xzv/M1uyDCfUjvoW6DF+tZoIzwLSG/njtgf7oXo+MdazW
5H2KFysoOnukoPwfpkBebPOSVLjDA1oBx6hN4+8ZeP79a+w8PkbF8XwBu9EK4eJ/+OTBUdDe2bsh
xjjc68lzXxTZ7XC1Z/t/HZHucAnB/UKcK8ofmen0V+McHFdt911n9PGEnzWZ8d+QlPFFfV0ciVuk
xkfYrj7K2sJ6ehGDees/aPXcB7PrY93TmVwpRPshh4GGR1aY0XiI0ebsejXVH9SNdu1xU1UGHxb7
hzcq2M90Dt+B1eaHKNLKIebBMkluaEwWFvi8j+/eC2bZKv7aYnmEMPwXdLjIB41uZPF1MMMPhp3T
JJtcpZ5feqmlIq+jfJmZIH0+kbPP2G/4qd1bBbqb0mSc5WzQcmEvGDxwbT4Yc5xNBujNMupCRBuY
bN0JieHyCdElU59bWWK4ql4k4b4xMokEY1r7uF0HHwnaSxGxoQG8MSsx31N6pIo4vmxuKx7vJNpO
ehdcQkoBG8OQKOQwHeiGqC+WeXhO3MUxAzxVsxzzPXxTjtOqGCLN+t9E4cxmvOTJk9bQpY2LhjC9
oJoKClOZYG4JihWv70iOAmBlPdsrPbQr7+PjHePnS4OW7vxNQmCm9wJJidUBJSWBLtjR2dbjLCsL
xMjKc5KJlTUzFvBOc7zGiCBwipBrRnvyVfrcgKXsMpN1wNyDhIn+WeMRsT2Uwblfou2wnXNGh2lh
xByc9p3FsjPSHg1IQoiAacY3f1OPv35vVkKhLQrkPqbmk+0KqWb1E4h5le46RtGAG6/akoNArvSc
9ZCJs8IEtFt5zm2DWw0gSVCSeq90cXWFuux2x61PpIl9g6RhQlliFfhYvWypAhEuH/CRrKSGpTd9
V4ULOyGaUbbuLAxLOpm75ahrAS+TU0H0NPNulcfeb10NY8Md0yXtYMtiffxpXP55Phh7dvhqKJdQ
wiK3oNX3YPvIL+ty8TdhJJ6n5YYnGhGvvtCm4tvMuyeSbEqhpo49oipVx3IYeITBGsB9HiwrL6WU
GqrGIB+5+GPDPAe0HcaE4+kducmOH6wOH36t7BPT6sqDWu5uVYs+RBSlPQ3UFYHB/V9O4Y4KzVRp
N/3P4m5+4zWnpa5ynU0Em7eskMoggP3NIl9Ie5/lWwwn3VL6jO1r+Kfjx+IOcrgDyNIrVa4h1Sow
EIldldpS8HyePe2wI1wVu744QZ/Iq01mcPIW1jxT7wex1T+DSpckwjB6ntTeKdC4KqA3jeJ57PH7
KGlfo3Dg18jeyh/3cndqRe/6KNsRkcQLh1CnVQ26C9TmExkHSf8hI/YgktqBfbHDREbxILac+Up9
QIVfB99td1QI8OKlEhv0oamhVIRmor9Ecm5VinYtcn8nOJcCa9YMoyrv6fMy3ZofRPZV37oIyG43
NgRgaMLRlKs6id4TMvZ770MpYL4XXVn/2lFecGjL0N/UKuLEfaXOqKKwAm1HPiqUWhjqiVyBfsTL
zHIHaEu8zMcvNLO04/8RmRZ5bc/vWw81Ct+Fudl1FEtqKASDBdfxpLc4ZlIo4GgW3b86Q1GI5zXy
v9oq+qwgpMpq2V7Jmy+H9KPoKk/D/MF+psLKNNyPXWBByQg3XD4AfFmU9ucpgEOSA5hW6nWuvw3G
fDMRobGxJa3ZSLBdUWq2/70D7She5kKNn1HTGaCOsDYRGJKCU2Ks7OKvHkdES0wuRQafppFj43mi
ela65/IirWwjnfrOoG2BtSoPzoJu92RSB+yxZQEMXv6X0EbPl73cjUKtVzZoIMEie7IGM6cWlX24
wzRg88Bk+hTBhqyUUPGhtRBJIlbjskxcn5rZr1fEBVbe2bI6+VuVeXi0SNo5H1q0OLPdg5lwVf4T
iYGnJDkyFCbAxjKyVJZhZo00Wx1mz2+hrWGGLbdih9W1yR8rY9BCoZXOkrgYLQxaxikwgUjdtbU0
M+riZslwsU/sWE5NH+jFVr1xjRrN+sbEpHKxP0EIqZqsYsUSIKddlb8LInDdEKEkt+3bgTF5rqdW
KzKSd4uCmw8C6n+D9T77yZhnmu8y88WcPWv4TfsouMC0e76ibmr+4X6G41nn903zq8rhUfvOCsyi
KyoZCq+12xZPhgwgtmi4l14yTML7cs/jMrHUtk+fUlVKNWTkmPjMj9eXjkFy86tiSg2sj7vbpdIn
2SZahmklPY719ubfnz0c5Fq6rSR6QCrVI+VAxEWLXp0WLm5W+yq/5MPrZOZ+0PwCyGFAMhz13apc
qQ27B3d2ikTYee2xEdgMpzlETJ6wtg+/EYPwQwaOuADWftIbLB0pr/HVdb3ksJdihbFl22N4ppRM
ygxGoGiI4aItOmmgN+JKhUWqra3+gh9fl40KsLtQwMndzlRoUgQ12n3Itt3bbKpz3cba+savT603
9A0PPRQzWivhaBOU6i+tqtIcMvwg3kAsPcVA+3PD3Wuk9QaUGrboJLaN/9ttDzABMjQZndGSLJl/
F0ueHZXV8tXchTf8zIk6NBa5OCdj0wwXpSNCzg1kkIabzsLtmmkbUkM6ej6mB9IWSmiZqqkaE/5H
yvO5uMhbOupuZrmrp73HSca3IhYah+UArHEWwTM7l8Q1DNW9q3Dg5AxQRMZyAv+mw0InvmdYT/NA
vY2Bbxapg51YVZrbLG8sm+pyZJEj6rEn0ajC72v/GqBa5N7mkDO9TB1af5nRH8CvcfA1m2/Q1l0j
7JtTsNoMSAFrOM41STrvSyaUeJXhbAc7eG/3sgopTrIjRpdRr1L0+5UUKtkfNUCgEuYbhcVOqH/Q
Zs5R5ac62aOhvqN4SWq/duqEThSjhepSITHTRW7g2Z6f9PmJZu2lRDH4ZtPdOEQEwdmwoxt0FirI
H4/ZyaX0Of+3OLdKRmt34jAmAxjt6f9l0F+80mRn6Znn97fb5WKpH+IUk6fA1aFdjNO8Lih6jDCe
8YINPTm1cVCaY/0xn07s+H4DQIr69PqW+tYqzawRI+dV8oseZ7TeKgx8ONUPjv17zURGoCcDtK3T
QWFLnE/zo6hP0Yft5nA+xX+WAVTTBo4iTr29JT2gE6cPYqWJ/MzX6L8cPKEeYCt01uUE/JMXYrSz
6pORNqJEWJWt3iDI7TCLZJzX30bCQEcEHiCwVzrVIJnq8UWLH2+U/lbaHYQ4YGf2WIVp0i7Q9Qoc
QublUzGNfXd84Mf7cwt3Xd0mwRn9xajv/qMnZ85sDXOguNRoo/SutTzOyma7DimKxALZQURWrM9Q
BO5XqvrfPhzDs10wkugJ2u3kAhrCRxDP9KLlcyIqwoCVuJsyU8qPLMSHjm3yUr7s3siv7upzeVpr
F8LwiQbB9N5u8JhOwFZEKrAqlk8LjcdbvpIq25xT1dP40NtPqCeW39H0QiZBCzO+uoZZ4vLhBP36
DO0E+vgQ6ysLm8MeA+/B7qgSRbWXfujvd8QSR/+d63+WCuwII16DgvF6VAzAmRX/MPD4is7XiYIJ
+JSgq5aXJVhphUlpbU88LyuKE3R6gRG3B4JA1EaizwbrOPPfjnapQTyAg25tAYIE277sUctUo5hr
Pfnd0EbuMj4YxfVs66BWiV1F8wuH5kdNm81kupHdTxRlx+WdSjQon2mjP6/qzSfVT+7wUa5q4pMs
qM81LxpqSVHPsXbvm6mKgXa4KixEINPaRmQoEtYCnu9kWqKoLKp158EwYh2t/StVyRi+uoTFM5zk
wchWnBd8O8jybOUffoEHyV+3LbVlZ6KYI3M8vJWfclndgU4/vJfidvf84u7tJzvRVCnxWebAuv6M
dLsZRXo50LrrbobHvtLcAX+aLWXuh/Hoy0wxG9nxsUI1RpCoMnuX4L97oIbFUqh6j34kTfzc/5M9
gbuBcA4mh0ygkuXElZCNdBZRyt9yYOJS8W0Lk9LPiWD8VjtNMaaoNoux9v4NJ+zzsM8XPKbDIH3l
O6smW5G60+JTJklLAWKgRq5Yiut3KJBAxAVWW/v9Fz03ZF0Y83WEh9QuozFkxMr8MwI6T0t3YvwY
c1Ldyrw2M7/NbxM/V2Qc1Qm0QE9kniYyQ54CDi4MyI9LTzCfLPuFXnxE1FCZyh4bIvKGeM6i7S6K
lML30YVUi6OsKvn5cKtGU9LRkLmbikYjPWvLk6laUikvopnyRj3EYxMCzHLccrplzTCiZCgot+V6
/+3LC3lHT5LD8zSa5ZTxIp2k5+p3kvEpIsScUMrrR2oaWtr+t47BsZBv2xOD1DdyFpMLZy5of9G0
0O6diR1M8NFJax8unCd15/8e9732pQvgibwWchxwB0aNVWUWzDNKr/ruueJ/sz5jpXFKO7rCTPdl
wGR1sJf/mscukmse2dbzAFDV9z8J07MLF/pv4DQssDEqFFskF7LOaUKfJTyuovG7KlRnPDg1pfTW
gu+FAxI8e4SRAZix8Uzb8xBrouv2UszrG7HuInfqTQw5wF/bL+g8lmnPz1Pj6LDXNR22R/2zPcIf
fuOReavAl+MB4hW7t7NkojYMoJUhpqEnaktr/QSjMYyfOYTzjXMmxCjaLLwHao3vZ5v4ZzlVSba4
sT55MvLfei6F/ka3s5RuDA5yiZ7pvuSVb3/k5Avckslxd4qy9ykM/RbX+m90z1d2o0eZFnYaaoFk
iCYZTEDWyHPvQkXjrffcyq8rGvaWbQr4tZqHIuUldwSm0QM9v3c5eHM35U7a7oij/XK1c7T9crds
bXlJaWyuoSu0IIdPbexgmYsW4rLL+EWtBLBHnpczd1JzKLXmMrrmDtzsV3r62f1OaeCnBlcdMt+F
vviyu7+0oVXd9WTENBs65orI13D+37TvsGMeO1TQ2fnVPchr2wzHXT5/14vQvdMxe4dAxElKvvr1
ry8msye1NJjQ4vL9n2KFHZyOhWV53ITrGcyDEjWsFgmx4glD9p4/hlSSmMgNLxD4gu7APks6NYgz
JndDV9qqbQH2kZJ79iiu1CQV8jRLYtONYKWUcoC4E8M8TlKTprhSZC2y3FXVRAnbpFPtKKzx31ai
qANB8zdIMwzFA32qtAflX4rObrIqMQlAGy2Klvv9bocNjXZATNmPoMup2FaC1jEdAmLo1Z0wP8ss
9MLs+8tabWWYMQxonvS7RWwCw9NYEJasrP2UeaU5x0vJtbhY6+BLSWPvKf10ceLXyl2Nlo9j5fmP
MkzU9JffaRzUtb4TMNJ0sBKpMrk0KU0yl0uReHYkhyuFXHZX+4fT3VDtxRb2Ha4aCM+9L5V1e/v2
evg+MPE7A8VDMOz3r4h9N3FYMJJjYlK5zc+mKucMvjj2Qlu7toHvkd6WR9jUoROdQQXN233/JAW7
dHcY+Km+5ENRREpJlTC4pt8mBg1d6mfooKGDNnaVjQ2ZOjzU3S7l0uZHiHh+S8sL8o8lnqVybgxy
8uxcb8M4M6CwpK5Fz5Q8V5JHk8zjnkQ/LJLAGMEXpE+BvSM8/BVpEYXFBDxnZFfjG7eUJ8lnAvnR
OtMTQsw0p6I+FhZFo7o1dLL0VH+5mGh2ITEQ6AJ4v4XaZo2E2WNmNDWR1nsfPxzwH/cxg2lUQy1z
CiUU0E1gmRshaiOz5vmOW5MQflA8swIr7CjpLEaWFIiBywXPCw6u6aeL39u8O/7962CMe8G6usn1
VKeFLH0vTzR1aiG65q1OWy+qbR0YIaYGtiiFG5O2KNgoXDAQZ2DqMOUwvQj7vcOXoMh/mKgJNNHe
vOMG2OK0ge4KMqeGBd2lQE1YH3YN1z1tO71+kh4JxhgLG8tyiyu44OlGwCgEyhpQGpkV3wcb0IbS
oZnPfgWFhX0H84FOtLhT4NTJuhsrDwg33VmvB6zVcaJ/CE/srgeo2EwZcMjQSHr3uDmecUnF57pH
8KGUjUhct9V4dT3OL4I5DYF5LDhyhnNHhx3blLq+7CfonzOa6PSi1mD5jbyE8gWZqUUvZTN856M+
Us57Ry3KHcHo3wD01QAIyqUvj6fC0y++W7HvQvUuXo+DLP/9C144aHSGfvc3ROM/+xprkohmbPaW
K0lr0GlKO62KDjczewlwKj/yKkybdgFR7TEhzZvmjhdDEOChHw7ISSSCOim3UB1FxP8+0adgRxB+
7omnYDwHaO7N2AgYvhB5XWPCIWxyxAQmubRwL12OfrvXIv5j5LOZnbrTkfuZFVl7C3DD8WjD4APJ
RUXcwT51N0lI0c9Jf5MMUQ/92Oj1EpBbopcaRhyo1/m4812v7tQKVfwAKDErqRnrco91ZOwsW7zy
de3yhr6W4AQpojcNPhQTWccp6kyjceLpVl6XSQjwXPc46/1JZwZc2P0l6Q3EXYDidmfYDKKI5WBP
LgeQsoTNoXvnkEhNW4pDTRYR/EG/fAKJNed2bLUI+YWm47KKy5dt9OQ/+C9aVZhU8eytzbI2oxnM
kUc6nKzvR+1kbuaBJxknaSjeWf93R4zlAkNdX6x6hyeTGGx9tklR26InPKKvwPdnVkMxvasmRYQF
+Agm4NEeuYi7Isqel66o8QG5GfnyVh7r1oLhkWncJxh5W1T+EXsJW4DlK4pWjobo+b8h5V4qbHbO
Wi75ik6ysBlGMiqnCjrMr5XsikfjWDZUlh1/6mp6jfF29PK54cUbqP3K8JV+8zoxwX5vPhri1RfF
XJ4vPB/4oslSyzD69eOjI4+pgmOl683ecSgV1l5YHnuupypMdEAMjHkNshk5QO/Sgwq+aQQ6zRdB
RTymzzq5Mz41LZPLifAsoU4UUwBztGlrseWiFXey9pmFAOYwYRUz39PgAg+LXeL4+U7Q7LjbS0e4
FdjdQaMckeDYYKUaqs1wIr2MmSxCSNqluCt8ud+uOGoR3xEJVpyyv9uZ8Bj/WEWhd+HiER9P/rpa
alBW7HVbf4XnMC8TTAwIdq825iDtPFtPP6fblaiCjBaEtOfvdGnsxTQUtvKg4p3P5J0ESWvwEnIs
0TWxzXol1TI60PJSpY2cB9s6w2TFBdBFG1e2Gr/SmiR7JIREVh2JXz+VnN0eNrM8LpEh2p2VioAX
wEcCniiWxJnLPf2JM8BKRkpQL8Jpm3PhDHt/M/X7sc+GC0HVsWtaM7LAvIq/KyLtsQH2ywLkRDvv
w+bhqe2FlIwfJWDR1klzOYy5RBzHDzgSuoET1SytXBmI4ZK72RzmxwEyXMa4m1dZafn14kqdnaCR
zlmNOjJcik0mI8CIfxLID9zaWAMdBTloBdfyrjLC0D5y0BGJ/BleLoLdwHP+VMDBxSul6/loWoRE
WuW77BAIAuxuSCuBksSxHSIUABrhN1WpwQ1OG0SjHugBAVOx/FDGKCRhkqUjPPB9rylDgm22lP3o
gQRC1TjQRfZaahjhXYsoFZ6XJmWmJiEBlwSBil1Ne+aDvZyzxjehd7GUZDTnTMB4noxpJhNzo7GS
TKzKssDPQSlEauivA+rp6ySzyV5nKwZOUONoiDyYN0Zq1YUUqSRWyomt4xi9gq1O7rFhz8/wBkfh
9GNvSjLmxsnX4Ua58yg+Oj+J1o1ielpRk2uLb/Uc40qQlhG5X0WgsdQy9+OXGXD4rLbW9P9FTEFu
Rf1u077Ba2SSjJ22j1rqH8tH+ue98Oni2YVQenQc48kQ98VwpJaSu2naA7SkJLdkFxAlgISljSrb
NE3sobleNol2JCZWd0KDAnT6wbSlBQyNwRRbimy1j8IvqgaddqM7seZrGBJXJvHwIqZkEi9Q0Bh2
ESV/FRTaUg/kzaHCSKwZzvzH5A+uOPqSzN9qC35t+h3ZwgbkNjG2mGowCdx7RvV2/XSDqhuFdRVs
ewpTVW+Aw9cWl2bych8Zcs2WCbiIflG0Lfj0yhpoMcHKhwr+5sm2pOiliRfrrNhwKRIAYyamksk1
Dvvm5DVFg3FP8DNN8U9K3xYKZg4v9+wkwsPxdQu6rtys1/UEmNbLDVrxTP+uVtrcF6a3aGENatZL
gxUYj/XpmC/AVYEgmrOzd7SxUXJf/Nucj+XJtQf8iEKmIXDDegdCrfRUOxFh+gfKmX7EmFSmLVJC
bMK4wA5wa8su5QfkwBNxolPSLaaLHiJFBpX69VjBkspkGyDsUnBXJoT5RovOMSzX56KybPcfHD5l
zOewqj0laQk9FtJ31HOmsWHjRb7k+1HEBlwpPaBT9+f/qabVT0ksTM/iAj28lUVBGsxgwQaVX5YN
ml6HchxtD1yapyKv3IYgLNQibCzsekaiAdp2r3e6FlqO1aS4XIlCGNxYaByEsA4suraqIrL7fo/1
QUxKVN76ftHDJ/ZR1GAeJ6fuh53ty5JpAR2/iC957m3MVBdiDDStBU2GEvSAeXNgHw547soXDLvk
8E19DdasbFKxtqp0hPxe1cAWUWinY838lTJ4dnA6/y8uQVCUUyaUruPM1eESGNkfh7uKGyEuihdZ
Hmx88E2yqFmssru3VMrcOgsHm/9fqHqhJHJzxJgQYXho1g4Ywr0Wk9sD6pUX9IeYxykyn8bcuGN5
4NXm4Whrg0r0xzU3K/rUbgocINgwyLx/IZUJ/GWJZ2CwXaQT+lc7p8fR/JdfLSm1/jbFOibnOno8
+LkTlyXlMeiuBtqIXbbXgpwWwZO9okNzO1Db+sacpPLSq0ODPImUHEZ7ASgmBILDdEud0OvogNiA
JaPMQc8fIpwXUY5ZLuZAyp7/srOgb+eGxKdF3B5NHjcObU7NK7eHXAzLwf8DjHwIOOedcaYWEAIi
tutu9eJ3mUxsUZm0yElrKc9bKv7RVpwcam9R6G2eHGLiQBINGPB2r6cM9s2Pj+ekYWT9zHR+zcNO
2yZLPXv99vmarGsvLG+9Pvf/U+O8R4+WWlGXfpWnqql6xbfKk7tyKO1FaEvijFuuejRhYico28Nr
qG28yIwke/3lNajIV9swcR1iFo8mevnzFnkTlDQGCuQI1J8oJwvDobZsu/SsdUaApgnvYgj8dAXJ
mRpXx/aPv6zDx0aDkt1tlivAq9WYi9Kz2b4oRaC4sBGIiHYKJwbpT7Nc7W0lmYxf9UDiS21RlTC2
0V2rxy2xe2K+wGIVhmvUR4xFVAfcYWBflN7v3ODL2DljhYFwdSGnQMXaGFNH4w5Jc8swee6/S6NW
XAFugeXMmRxTqMfzJ4xsCXcImTzRD+Hofn0+2r17iMCAsSpESnbn7YDAhukA7hFWo5irGCJdzrtB
yM+vApiT8dKc0FMjrD33xf6hNPkxXpmZNwoj2AaW3BMuXqKhcGUVHnQvGh+p5VJyTKFIsUwBzyOw
mTL5X7IagVTkii6dnWh87+32SrIkLBXiNYxdWEhH5G/E8TXWBcB3+Y8YDhUNAWBj7OIdHPxisV5E
vqMt1epdO44f0I5tVMOdd9sKotX8I1Ifp7QoNptpqWUCU1SIzzgp0cfW52zwDbMjEP8i1Lgawxbm
b1DAeAE0q3B8hPXWAJNBtEKEi8icOHITC9bWM6fL7rPiguOgzYjVjr33dpcz4iRrEE81d0FTtsSh
2n/p+Z0yB9xVm7Y4cr9/Ld0OFhtfglTmtiGrW+PGlYbUzxRGT9QZwbI5D3kOj8QuN0zU8ZpYk1+F
T1IXD0UlmT0Bpn7ugTvfY3X9IsEYYgvVS/x5XFbWbaOyiSrl3bKaaol6tNsYKeXE25BygkYfSzL0
7UZorkN00/+H2PxTo2v08ig7D2iSvN/vdCcH+MYQUtQ4s/h2rQHo7bsbm0S814ohwR1Zlcvsy61V
nY+JTz1QRKB07j5JDnjFzWnAYZIvQ/lbr1YskrFMkDm9VdlqJe0QAgwTQJGqXyIIt9DA3ChRIsRz
lHg1kijsDl2B3uVw7RMC3vyYffXnOjQszcuGX4jC1iK9mn8KtlzGAlz+U1SWB1njHw6vB/hM1iW5
fu75cniaDDGHmYjZdbH587BgNe9MK0P+e5r94EcpKgq9bUKrgpHS13zMnKCArem2iFbpeOO1uZ2/
CO9XsGqQJVmkJFO4TDGAfVnryWKVxu0NUnXC7/fKa2Z4FQoB90m1oelPhVlBUnVHpgruJy0I8916
8Vu5/gQlc7HuXSvLsjkpKoWzVjgyXpr+O1WoVnEae8E2NNE2cGJ2DldEicP0ZecGeJzwYWRaOAqp
MODke13yPL03UkHvj673veeBwewmpWwb6u/YVTZhLtgQP0Gvz1HVna8c6TxAl8U3mnCC+utkqZJc
01CAL2nRF6oiuuDBFXj3qYoJ2qXTbPVQOGwrawEqCZpm5crLfwD4emrTZz6qlxWteQ/TptO/5FVH
nkLLYty4BCXy88x90Zl54wdrNJN7a6Gy8iklUy6qet8PhQ3chANEIKMCMal8wG1SePkeBKvq0IO+
cRYcKDCfi++GQO5Z2WDyFQSyhzmzA/t4Yfjq18NxpVgHeAkRkP/THDKGbxv84nqnm5lctWwTdJYg
GNYmVdtFPXckmBT8/YwufPzS5jkIRE45+kzOcvrk7a4OTRVi8/DUJQE+PqBe8VfrIQxWjGLmCrPC
6Xz0inLpisBwcQqqN0ZIR+POaK8Lya6woedxw6uA5ipJn7ZuvHVm9qOYTd1kAX0ty/0arxkA/2R+
p/zySHaC7CTd7wci29meYQKrotUyADVjC7AoFnTlxuuMV5PYRTYOobVIhGhuB7qPTHTc2VwpR4+m
C/NN/Uk5Ro/9RTOhvJMhHJcMfX+1XvyXmC36tgpnYYQsE9mMkPa/qTVequRUnR3iNkWNHJuocLSf
uxniaO8ML6nySjdc4qOSG2OZS/TzQz6+x4hsUCcNcSnwZYbTV2Eg/FXRdAZAFKkDzd3ffP6YrmkB
qcFHxSKI9BkT5sdgKra75kc6eS8yUHazwbWV3kJU5uyOZpCmR5RFYF17oBREZs58CB8spcrMvMxS
R/Fvwyhz5HzdGQSnZ7Ren8fEOGSRyLtbgDGTxHJTJSvJl9wofdpVkVv9EpiHpwnPUbm0n7X60TyV
YYMGJkkUlUlz5Q+yS9HJIBg9fFJuVLTPF9kPolphzFOjSJ+wXnA6yM87vw+evyRAL5mVdzmCSOtp
MgcyNqpNC7AZIN/H88QiZEc/2eM7yZfZdeqMC1R4ie7J9TD7NiBUAl6SF67Pzjo7I0AhqUs25dit
UOy+EebSCMpuFepPJQyRPiyZ1G474ytRYtNq36q38vUuQsvhf9+ZyXcY/sD8cebfn9EWcBeD10m4
5Ixt0ULwoQSD7Ydzu7tRyfPBmeOz2mWm0Gx0CVbZo8gIoW3g6AzdEIxgvP66pZ4euW2g/okZIuFI
Uo3Kxp+Ebw1J732deQdPSxNbdvyijqUe1LuNZaIjiEhWUoMsaKabDWNyHuj5U4WV9KPfG5Xrtx96
0Int8ffesxQNqrwY9te2/+v1d15wJqvlbVlJ67Hq5yYGG0V+n3YQwdDPoa68SmJcHAlyIKuegew7
NvJwLqZCZ2CPNTtz6Izvb2OsUM42p9vnIZSkde67aFlj/nqHs+vdwGUuYGQG4GDzePVuIb3Pakrp
Rlz9eGh24XkpjsG3kxFrnnv+UvemDwZEJ33du/DKfzvs3tqzZjIPeAj5HnoEDTmmE5+hAXAjxyIL
7T2emOwtmrZxPaFdHBh23N2/jK3dFqmMayGDWN26vYWKkPGsn7oezDA6S4Q7eeOXF4kqoVq0pXfL
QU5Adusq3EwM6YDDksnvR1rlWI1dNCKbwqPj3SV4H86c3699TNUnf8GkNir92ZtUq/f6GF9lMEh/
Ns+KdE+Ebgc5aV0e6pPq2MA4CBw56BUg+uQTdideYyNtodlX88dR7TFLywa+KaLL87KyNW/fWBeu
uVW2WD+qkdkhZja6FPWnLtJ43grkC05/NOlr1QEFny2Rm+tn/SmJ06yJs1uBXHG8wevaLaK4iUIa
YCYrq2FWeCo7rp1l2zYwr//4djIkj3z1XXYLI80To5D7oK31waRAbBSERwwvIwxgm08z/RP3FGNa
iwe5J8ekwxbk/34pI3mSa+3ahwakGUiR6h4X3FMhPQd85ygRi9OkiAfoTIgb7nowH3pK9SeuaqXu
S1fcKZxzP3P5DKuCAkuYGIhRNpGKTGFLLD7GjgB7KpxqyAxHZQymAe/ABjDeN9UCfdBydI+dF4BN
cQ9XwwTZJ99EyjfH5BtwEzTokPIFsDCJb/krnqGE/TatH7NlxJOFuMvd6GQkzAWPippMXYAq9BeS
3GIedrMPE5fXwmi6WRlg/GjlZcnE/dyzpfkbT4O1GPYQvTWBBCmyTOVoS5ZkNa9HD/fosyoPUAJC
Cr/rDukFIVfBqNM27TpuptGQK4czsUHoG6eQMZPKp32H0Qg81AAobGUM13v3MkF1ngT+gwFq0RJw
7NkTR2ZjHPZ1FrH4dLr0dG3Z5jxxwwIvro5WB7ef1Ji97E/V99FDXj6hr8SH44fIcW3k3DTH+X6g
I/Y4fSrO+Kj6whXVwGGGodcYCFru3DK9K/iUnQHmaUqDDNqfysil7gdtEbBWYpx5b3RVAZbelzD1
tpE76BDnrjqnICXwCZf8U5/quj3ZULUlgI2LgKkN+dYOgWqSAGx+LTDMAhxWxBEIdnb6dKIp0rfN
Gp2NNgjA8d3GaWvieC951qLblT+AN9cAALL0Dzd0oxILqoiVc99kKy/elOBUWvMnUeJ3ERKA7X7l
eDxkKpgYUyw12shfsJH0idqmCtxTFIY5gsccwmSotyHb4Wj70WOPlbtwIZ7WdVoaWSC4DrwL5oNt
EWP0CkurqFlLvmnDHSy8XBvHnuwBXgQyJZMKWg0udB/RyepMA3538oS7YgptVpWbFD+huNXKMEcx
zFxYLZGQTKfRGFGBeTmLcf1CyQYsD2RPA1swqBjafv5aKb5rUgsEfr8NIMvHysrFY4JDrQ/W8Unj
7tjD2xUOoP6ICSKNHhGtideO5uv1A6SeQB3xG0xKvTPwxq8JHHxL9yn57kXla3ZPn/Qqe1xBLM9m
uKq4VB2y4EHIxTKmOviz40kjkh7hVI0OlJuuWP9UR3g0JqcHGLPcqLB9q2kF8k/ZYFFibXn+Q23a
A+EbN/zi/9RYUwKVzEQcb/uWA1cEzEy9BcS+lonqWm2JoLaqMFG5Gt0q2jIei7yPkmsg/q9bTBRI
urqN8veC4+rxqOxQVhVReA1iETDAq+CiSA8NOmupFOzah9sAXLaqb73BUdS7G93wtCEChvkTWNdI
Z3jYUcRoA4h82eygCD3Ysj76zQiZtaOYDSv+tMcYIyOBmeGb3FLJtA4Mvncw6BcPFL6qrCHC1+LP
70z9qV+2HFxFf5zFsbrZNAHxTX7/JeyjMyPykA8txhqkiujeBErUsGPBJbKEhofdTCMw8k3pWuem
HhKlirNjFpirA13ce9mUWa+E/zncj/VRkdNMDH1/WgPmZdr3bsGeXTi4cxTRHgbLMgqa7ssdUPkF
d3Rn6nssSysfJoB6FN403gKDNL38/8Beic5CviEF2gvDxQOvK5cdEgZy3CiD+fts0oMeMeBGagRh
CLrg27PP7lXCZ1QSEhGy1oQQm1s5i3Aa6RU+Ij9xmutxjd0gxUVBuBt4Xn/doKfe9PnqmD703KLd
8aoxBRnSIQlf2iOsTAjTEHscUGAtNtSUeO59g6bHxyJ5/oK3qSCujELK6Q66ZW0BQIpQmpLV6Kzr
HAjH4fTGkoRMjK58IVa2EJlG5F8WLu7LevKOLoO3CMN8xdOWVYZ1GkwLalIDH1XRjxGMwqkxJGF5
mszsR/weAh1Fgr6Av8vfw+2p5/2FuXhvNgq8Pu4A5ijrap6JB9xHbSNk6N9tqJXM4CSRoHZ9qJX6
B+HYYoe4HabFImDkg6Yc0UX0C5In6YK8LPyE1+lHNEN9/sq41idrJh/s1JQewGGQG+sy09moZeNI
42B3AYOVrtmc1frUFcbEKyAbbj2fxtamzs8rk/jcYZljtb41Fzp8u4keucXWRWWsnKH8fOSbWPYX
lT6AoEDI7utLpPAPpixo8mByxVd+9Kz2qmo2240S83yy5mFte3w4JsQp42EuxQGziV/ZCT8C8UCw
YbkN7lUjJGWIl+Dy3TVttYsBRPYgLZ4GE0y34kcZKDys3vsVoCiOfas7jK9TyZX6H+G4gFTyssKT
0X/Q3VKJhNumPERIoj7OqX05kyKgmvvoae9QfncvvdNWZzTA+WFXY+kGjApGiljxfNYeZjAv9Wk3
pr7YwbJXJJNBmORti9hRWgdk5jVqtipE84VitCcCYjavZrXPyPCQnR5D0wVXv3AyZCY7QIoD4FYc
H8amdpKmPn2ErRCxrQvJ+FgOgBmXG9vh874iEIkIzx9etbN8vIj7z1yHJyU5MHzjmY5Ttwxa4F3q
G2rPDhYDFg+AoKt0V9chr9H8+LByadkBWe1b5UhLLj8C5LqjdmcoFE3ED0UMTlJJoBwmOMwJbjsP
L6WY8SEcFSNCZuQYxCLseVtVRrRiYF9LaZouCnWQzFC1wrT5vETT/HGCYZjqqkZ/0HTFO8Fdkmt7
JVdKQuxD5vh0DGLOqDe6IvRS+ymwGYedq252eAjJqSFK91e3EE3mWyIVK+8AD/Kt+cfCkj59QRl3
i28QNacByNqOBqZ2vURsWGMzZx+c89TBPdqdlzlbTieCnBlhBbVXVZVBsbk6f9Jf0IhLhjwtb8xH
Yx5J4HGzOoozuJJcF1q1OM8m2RTzepx+TEeZy8ghGnd8+xol0LljAqYpLXb/ujB+8te40xGsdtBd
aSYTioqq2UipZbMdK84+5y/hXJUClG1/Dk0eQh74ki9rxflwcicnpPWPVlEUJ821S/hbp1lFk7vs
UxENP3tRYbbwHkQ5JO1deIMYv9YRTZLwTQ4eu07sDZCmhBqeDZg+ieYoLvnRtCXT1hWSKXCc8LkI
X84lGPlhNiesRF1qL9Eg1hWeUBsiUHyMY1+gNe0EljNRdLSelDTwBnoqAoum9Z91xGJv4nLSTEUc
XtjocwNv5+vx6LC+SIojbOdJqdjEyj8tivXz3aD5BAH4Wp8NNMNQeVTBOX08TRRuRHgQx270myAB
1zNJB6TtpQ8dTLSl+CWI1CFAK0z7qam1uHP+j52+drNHrTy7UQLXZFXAML0d7AzEv14G5mhUqBN1
cnZElVJy17XyemJ3IpLIgxB5pem5Ot/grOzdkjOZPQiONYjG+ucp+l1Xhf5NPgxaelrPTON2ggdS
HZSfIG3dS4UwQURFpeq9TOkojDUjsYoORWz/+DoOyOZDKaeWetOOJ2pIQLhoA41dSGOa5czvJdPv
3h0EbTVB37c4k47jwkzKd7cYlmvBJYWhwz97jY/6mCKzZYEqWAc3RT3fc65BjiQvWstICHYvLu4v
pVmZNSLr9muNrYKzop7ITn7A3SRn/vNdD5untX8HGUeA9LcYgZf2m550zQHw5vKdRtbKajigRuVM
5x7h8EAsokgWld5FJrgNeArHXncWxNvJToFI8TV8aPF+SUKjPq5+7mUGASquCqHQ/dQ8o4etzW/Y
OvmL9jO2tdISaOPUiQTwSA1ykfvvwvs+ksBc1WuRSDV0C2IsiwKFHZ/uehTgh9XxueTOvLCBsIMa
IY8imdG9+xX8Z8vEmeAIXwrMbPWdaRQgmkfA6JVxyJ2uTuzPKnHZEDgJSryiyqJS+umbhPgveSw4
o+oszBwKEqVeusQVvH74BtEBVCmRkidS/0yblIE7a3dFZiUSwmGq1V/I/5jB4ESS2cbSuZbnBrgk
tL9hj+Gh1DscYi9DhcEpua+kRTRiPBz50WJHrrwdJkbODh79vcs/VpUdW0ih2aiq6rtAKCLpcn5y
fLmX+axc42dDDmj6SNoBjyvhQLOiUzHq0yjhG/KF5K3ATWVsxpNXODc+kcmPv/8J8D/ZdboQcJpX
7YrB766q0wAKMG8OcpyhQ2qLoe4yRwKKDsdhRpG5M26zz63uKtS1zi+Bmyr8XvlMK4+7ltpBDgPN
RCU39NkR3eIKaWgYCndtipgaiRV6SjyPc/3uFKpVHqsGvXOw23IOsDUGLFwlI6gX1IGTYHZ+uJjD
Cy3Z1DQRvfERiKHwzYWlmBcYO43QqB3lbFTme12D1Z+mvRxdoApbepAWBPbaMAvoH5oKrxvaJ86p
iY1MOOCDZbe1pCg/p9e7oq1p0rZTGrfPHymJbTZyaAddJOHFRFDT+yexZrIJoyTjwgtcFbzSX5DS
Hs/adGXf5CjiwEyb9YRnG2Fqap2/M4ZPFvHOlOYEhdLYKKvBqFbz/pHUUsti40Jjd1wYoc2+zL1o
4HPy7KWV7GLvTlazMWcsEgNS+Sf2Wbk7tuaNPPiEVxIfhDVLYBRyuwVPgs/2nU8dmknhZ+50+v0D
B9x2B6aeQec5v5GyoncLgVIswGt/xzSPQ5GJdB2+Q7GfoXRPJFYCnENVbWNs3zYZb9v6I8nhlcF2
tF4hjUnlPD6OL5r5KONNdrPcnbS0c6g2L/UG8DUK5aBkzAK4+2FEOXCBueuBnZy7glrCboUKAsVW
+2QaIAOr3q/MQcQKTQJiIBvEn1JC921chq3knPc/IFHQgkTdi+vTkTmDk/x15huk9Wu9GNFnz2KR
2nFHg2hTElongjIUSA29vLdE9xA3gtqNlpMf+fKVlNNN7Ohf8onXAX87/LSnY+/66cy2KpDA1M07
mEO4DZY71UGBJgYI8zKxmWOknv9X/A8CqL7ANizIGzVWOjDou5BKOl5hRtw+Fib+BenxNRPbuXij
R/Vi0doiwKY/sRqCVH2rMOrNl6qtrJ32qQZNjD6XQdCbo7c2klCqyChdVMxO1WiKAJwINID6tO79
zJhzIYMEeGzQoJZOkmJ0Qhfeqax14dLS+Nru/wCIQBX+LB2ROTZPKvApJIQPzVl/G5LVQxO+Zncg
oX0xbJpCZP9QiApVkPnZS38w81qxSyabNTqyQXcEz7VcTf4jmiTye4ATJZVb3C+epQhEX9ebJMIk
CCWI6ZdoPS30zeB6FhnvBexfhGT1kW+LVf+EuqYR2qne7s6j5Z8ih0mbDH4iddkHkEKrQpoD1q47
2Gqjl3DY8iS0vcYTnecfvhxi5J/Z9UttNukKde6dLBvWCJBzMq4de9/32fBBMctT2qHUSZBG4uwi
WDNkXrud96v7iy38zYn+0mtRVVjTakK25gMCvSYo0LcOny4P46dBcnWa0dNIf2cBOK2mwScjgyvz
FJLTDQdYDbu39nRSkYsgJVLl3vXlyXyZzrpmUztrOYmgEyNMv9WO97hCWI2Q60N7kpOuvIe6mxX0
oTE4bkWuNmyRVKzQt+0vZwMZX96U7LSR2n3HbJTK5gRjNIqV5b3DyDNUdtKqnlqOQTZ+pDEm1ubD
NDpMIs3fJM3jaUg9b+4WegZZHkZfqkh8UC83oPXxpvouNsUeHEt152UdbhdNK7DK5fTxK447a6O2
8s7BtIIAAWP1h9yms5pgbfIF03cmt0c9bgatt/1sk6dVvRvfbzJ6cUiaoPk4iMrtNSmK+RLjYm05
ner1Il/B5IYqeKmeOtMHIFssUtX3GlbJ7Z2esOALpLWcIbm3BGLv/p4iDTHthDLGezl+7zyUw15e
8v5kiIU1LvlpYvwTSpQT/qi9D/To8ELtK88n96QjgnVc/vuwTJb6J7aL0+m88XMl+V7cueHwANb+
F8USZgVbfoXFovKPAUZWA8O/TIpCgIr34gj77MfUHuYvL/iHQsYomluv742gMyMoTTRKOkHJfkCE
H/KciL4dESMCS4S8gkDlfZPXwher6hgJcTGTejmJ+W+sPJcEjGyYBHM0DvVaGCahr0m0CrevGjBA
wFjEPKrTFIGQWmUFG6psIrSeIqO85HSmyOdm180DSVMWaKDP9CBmiGbzF4Qr1VSLC+6DYwIJiv8Y
WwZG/nYK25i/DYeq8b6XPfaFAIpx++TcsF8PwXyR9X/Vu7wWzMBhj08LbeWA57+Kpt0FFPEH+sWW
vjTOC4d6EWj1cayo+etydTmQukwLppZ7NZiNv//O0YPZNV2sJkPGySpSWLHyq4x5E9Xp8/TTWw4l
WhTcNke+zlt7DIwlASq2Htk37XZjDZq7ww8ef3j3S2VPnRUPw8o2ZpMbfiYtR7lye01TCG8f30O0
ECZ4wlkuvcSuuFFSIB8J9kMG3jR7/qs4YKEmKnlundY4eqTu/s3sJm2axC3rYSxONxwKfnMFQNuu
hVEmgnhXIum5jjshBRShpGgL15SBTZtWDrP/5r1c08zaIiNe1QZheZmKFRxXcn2ep5T4SoH0hVR5
OThmfCRUhHZsfcSA4xHffvZvpQXWrC5gR33yMvaIDrD85eQpm8wKCU4QMiWRVJfjl47PH8SDQkOf
3nj8LlaONmC6rv4hwhksnMHuCpyruTNU7q5br/HT+gzK1r+QvTrxuJ4eOa4KbkSTwbCqb+Ny0Rgm
UeCX+9zRfGwqmtqp/po8lpi/FGbc8WuhMO5uAg5WDsn5M4qwXM7UKMA10GJAY07PADZXeI7SSK8F
QhYg1GeWjZV7Whq2pBKvQDnLBZZtXvOF2xFS7F3mi5u/62tHHBP56eAUJwIWiVSnxh0gsVZB2g89
4apx5yw2Ng6RJqGCLINd7O011NIgh69yLK30Mf2loEMrbEdcMoFly2ePLaa54uDFZotECMa+3kcb
rvMG1HtRKIjhBWmqrmUy8SjZfKhcYDMw5SVHXAfFCxM7lhQBGLJSco1lujjCy4uXN3hpE1aPgtkq
QinlIwV+dOX7EiOrj8i7Y/KxM15lG7S2uLTXiaV6Y6/SaH1HxgDz2jVfOvdp2MOnfGpZH1xHaJEd
Pj77rgqXKO8E+tLZ0DLPk4HF0qN++nhehsSjH1ysnaXz63qJ1LSoKN4uTLaQP1OHDTf5auDZNT9d
VUaIkCcZq+3cJbTxWi5f5OSOOejna5EstoBnQSEUx4x6i9rz0iGmkvTOSfVGMiIuLhTqsfAzBfax
hp02TNxsOB0pnLOshLYaNu93M+UPQHSOA2v2v3lV28EKl3I/jEwbN0jm2raHreNx36dMkmt88tl1
q037QOyfz/KzQYzBJfA8HH9IJisVFYeaGaQsbteyh9DTC0MI3Rm/Sj4STYtCNz4fu4C0ZR3vfwr1
ar7JEsIV/R3tq2qb3Bvlq/9xwYHpR70yMgBMl1J//KRCTsfa9RNXwFT2XPICxVS27WMgAN7gvdef
KfjSe/895s7aonZHCQJcaE7N35cMjWTBUsw/9zH3kbmeSgRG6fbI8ofnH8Nskj3X4k+r0s7PhV3W
J+MNdxhx9VqJnQJvOPAT82MasvgcdxipnixBih//G7vSVIT6AtCtaGMBy/TX7SWG/xA8esupkiOf
g8V8ryu+DHKmK7z0jagtXL1WnhDy/jLQ3acM9aec5KlB/0NcIk8u/ISpPb00i36xHoU7LZ0N5lrm
PMUiy10g3QXvngKpyVHeC2Vk/6nze8cykkcU4cCdkBqaj7YOz5ggSWOuu1tkGQu7H0TC2aCGopBc
yKt/Ayy98Uo2HtLAv4w3KobheEHAxvXQFtSShEcUAOvpNEMdaUpmA0iQvO7fS+TBoBm5tp+hA5IB
9YibKAUvzsrVe9L/XWe6ZWDOO0TqjbrkKGIfmI7bQ4SYitIwaUz0WMjw5upnlTcQRXppARjlxRuY
eF5ZhFV4eomOWEQypFhfzkILvBSnAU4B0aYqWmboNoPRw8PpQihHEps0ZaE8T4XFHEZjDVzqandf
Z+SffpGeeGZHiv//lpqnnN8HAyqHHmmpUFz+5mtJ8JM+xK9mM6k9kb+4NJkhKtAPDqTo4LXy+1FJ
uNnH7oY8hLo1wXl9ZHhDNI4ubwMN0XVj74KtQBfekVOsKtkxLVgjev2/CXWz/2gOT8+qY+VHdc8r
BL0tMxspaJ0DCdsRWdPY/RnPmOkGw1bboNe41kstBJhEqE6Ou0d5Iv8g9UbEVQWKfURMhMZE5RO4
LYtdj61IooGiOVK6qOHeUfff0hK7wwhOg+CCn13nfyRjvqN0W69vxt6ooQ2p/i7uxNGQDrafp7iY
PCKtcnLRGf9WII2JwO+Eii+VIou5+CgcRRP8mofpyeRWjQQ35YCSvCb4uzMSB7ahltJSVOOsJOy+
362uxyvn69HgzKXNLopUkRU1D3wPcUCCRZvD9r9cNrO0NmglVLXbzpIxahzVaqiraZvD6FIvcCZO
iiNCboUg9amBkwMYBvahxE73pVEFQ8za1GIx7AhORoKGnyo9+bwmtPZhyTEvgV1p5mRdiyJkwjlp
PNmcuj7HoD3uArEtBg2E5HHhwqYhSj1YoNvLPcl3xwDetKD4gkAS4LmLqJ4yNEiWkK9xAXHtNegz
IWyY0Lw6cDrQQmZpVu7KYKvj8xg7R3itlV9gKnkGnctA7GFiRwgU49deylBtx7oP8ePvxy1LRkCG
zrm0dJBE7E6nJAQZEwyqorYilIQ2XtCE8H4pZVvvG1x6pQYBzE0WlI2n3qfBecFFvZ/hq2sM6TAS
6BaE6N+uQqfTaYY5OgmtC9KH5Zs3CXnDJ+C5one0v+VxsYfxnPoEezkcNmIRQWXv6lTmdloOD2vw
5LxgvioxERgVFeo3uwEhJxaNvLLLh3VxqbytW/f2QAniRRGKrO0AMfRHoR8TXHUxWl1O9WtmQomY
a7ywn3j9wUHcGDFXk5Wr18uZMmsaLRyrCVqfz3Ae5fVndNpECeeSe/Q781nF9OrYnxRXnB113hx/
S84+yMntF7okIRRnfoy+8R2TI3j7nqfX23RcvX2fLzhRTUgmdwLs7JAxsSiDApmm/k/SvE/xPxHf
JX1dIDO+NQLqfcB2/lne3gglHkVzxHgvcvPH0oOebz0lc/u009DKN8zLprKZRrjVqm91AyoNhOl2
maA4YoJ7IMt/buFccqIsGrs7Ztc4OYI8DbRmwFKaDk2uLiwfCHLUU87dnlcttuSLxa2N/k66pPeh
Hate2soil2d41g5cjpTMvzk+dN2wgO3w0s1cp+504o0ZeYiLjF0HtkCDjIr3uLt4ozRVxbmp2DpG
zuS+1OJfoEg6qVRpje7mGlm8e0LnLzywOfWJMa4YmRPcVWN+LyoNdAOLg2FYTUp4T9eeSeEONO3+
l6ymsZfCcdCTfYFmproHZb3rm/yJPHnALCJCA7yif8niuuZXIyTjtZrOPhuww9K0f5OJ6Wl/GLfd
k7ZexvAyZM96XhBm8R6EvByRS4KaIkSYonJk2eDORBWcW4033/30nNtsjddko6+TmqBjdi09Carl
f4K7DZXXF7CCEnZEItOwmoZZrABnrgEArhC/4Qg0Ft3NgKSXs6FbbaJ4RouyJeduS2sDntwfgnPl
ht9vGGwIJRGdol/F7R5hkNK4Xxb08ELPSOexwe4nLeDyL2Badc4ts6a5pLpDpFhHcXOa/M++v7pe
buu5aMtNbLr59j70Ag2ifSd695SnsMpmqVx2EIJ0bdLRZC8Xcxvuxr3HfxnjpLFqXnFgI8hktbFa
81vAbyUtMC1w9xtobsw+J2KRbOoGFIL7Z8nKQdxMEic2weNkXg65p6ijbKJgefawE6m7tnVMCBV8
rH5DAhlP44Jqx6G596VgKKDDO3MbH+pyiAeGnpkRpK6SmQPAKmhTG8+Q72i/Pzz7uCLwj91aLI8y
Zga9eKYYxKpI+ej8OybGSrYcXFeaxbpeMcjA+A+YQm1VS5EUkJSX3nW9xiikcNRBlTLkYkuNT01q
Vuf41Tl189alLxiFhE/wCU8z7n1taq08YgtW8PsB+/Sp4lxPiEX0JSMmyr43r+sW7LgV7avdUjmz
KICfgNJN905EFHOnut66al0cMn6d+FjZ9IjJJHSZlgVxZ1/Xay8Vv3Jqdc6akw4QBpMdw2CF0SPL
vXBEZy5X0wqf6edscOf0jn6mpdvhmIZn1O1JlAtldN7pnDfVGO4KSDzdUoDqRbNdGF3O9fj5mYxA
mbwuAKLENN4zlP/7U21sKpO8v1I2+f3DUD4lczDB9ekC6hH9qSokbh2K8UmF/1kLhDDRZTu5o2nm
/l9Tic9aZ95CiqQDnlBBq3X9J23s4Mgf7ZeJ7M7vxuEh797sk43zQpQrqTIlRnPq1n7bPfDmRIUF
2rj4QkEusKWwwKHzmHUN+SP6cCEZX3m1ieHNG/RQb4YBhbojFj42eAiAxXjpK4Tgd7MJzg9bqr8d
f2yFq938Wipi93+iNUB0WP7Zvd29LUTxnYEu/YRFkTBpq8bC0GVCNmARJDatJEYxVHhGE/LBdIy8
5Y3iGXdPT/gGKDEry7y1Yms+G7Kr5fkEm7boHAezvANYDDoNDx+w0JLjc/K91qmz4KH79C8OIgLS
fY3OrlTSsnggpY3g2LnS65WZr5i2FzLtTVgcxcDx4iS1IUjic9rk9UztcyUTRDzuDePlJztINs5t
gT7+kqjD5Y8TvBk9p3jpLgZi69sFqcZB/Qj8Bi4Hau3T8gFu2DW8jB62uokN2qxuxv9E9DllpmTH
teQsSg1Aiox7FO/C6Msmta50fHSJOGk/LUEmRxTRIzcckQA4N+Iafl/4wxWk6wI3UwIJlHGkLuCt
0YTPyALZehaDQS5UmtizoWHF6bRjuU0qVNMgMX2H3JJqEB3UB5nvbZ9ne9TINADCCULD3PRpBtYk
fI0UsbftGZAcaCRyozL1CFmvcX8H8okVsubrjYhWuDKpsXTHq8r5SEs4GXWXss6ILimqFB66kGRM
2oDJYawA1Odfo4iGp2QQRomjciKQJtvzrqQwwj+HruCh5czYKCJyF7dOCFDI8Q/RHAAACmKRPGyG
Cp8tcgWMyA89c9VdmObaT33E0l0zePSuPlpKB/V1dMiTpl4C++zzr9+ofM+2uM7TAPkaE4HDLqrH
Wg67wCrPTO7ImFD7rb2mTd0o4XWlba0Xg+mn/HQzZD2BxueXXHApAK8JWJBUWIN8GtFAruEfxUug
/46m4m2rD8hc6vgnLz30bTQ3pOMYkKHK5svKM3OnTHI4SCGlOJxjJrUJb7vKlSPFCJ3m9r15AQUl
lSEnIMbRYGsMXFfPKbcA/KQ9lZAFZKiv519VTSZuOYi980NTf8UfdZX/1wPL6oLjJU4hxq1iAz/I
zfWV+yqLwyIbYlltODB2mx/AQ39MaAV5r/UVUHVw+V3WQrX/l3lZPmQUl4gdyDvk9o0Epf5T2WVI
6yqZlMMQGfsguzOlIeB0V0gB8WWIK6gwTXvHNqEI999F4yFgypsqYgoJwmCfQKaMH6237MvCyKGo
mJONMQTVi3vfGn7+uW2FGQKG0YWWxu7gkCpMQazpKOj3x/NsUsbp3SICkbHdA7rC0W1HROqsMtNR
O3Pf4x69zUnsvDMk6HvprIOqkCfMfCnqp5d7y4t6Ctnei3A1O0uKcqdQxcMa3Ixf95M+K8p9Hx5q
UnKLgf92tBCJ1ZKx5IXxTNa4Q2BZMNqjObTCMxaKIbruWRfg+4/YkoGyrkbRkUuHa40Ixpyin2I5
9MAWTVyts0+N3jE89KQKQ3WZSOF2Enc6vlbxHVQRtgMzg3zVv8hmMVXcYEOksXSTi29oAN7c8QzE
9qc5W7sOC6vvh71m9+CiWBQE+rOLuPH+mdhj8Fr7h6nSpnTnQutC6FENjmTWU7n+6WK+fUO34voa
Qh/bO+q1VZs54oLy5SF4bzzyywUkYqIdzAHxaUMbPP/kr5QbXsNM+991no2fA457LOEN65WITTOZ
RCTrOeIpl6gK0xAmpGv0nzBClZRH19Zp+72GEzlWbW8PyvkWU+4ORaNb0iVPKYbHr7TSwCQl/wFi
14aM2PN0HERn+lDBVLDxCQOBrEPRh83NnH06Fiyvin53NMtpwnq2QIJXub9RORnEi7jyR/ZDeX+r
z2suqLX/LEbx/C0RZarfDnKiFqMX12PelJ1O9LOcD1oSRtPxBK4uQmcwsCjp6JdAsl0ZzCNZr6cy
8WaOZaqrbdWiH91OJ5LIsz7SFRlSKt2GXJTYiF3zBQ0kzHS3wqSnPt2TnhPKtGGK6yHUXJh8x8z+
bYs7mjZqDDp3ZiD4v/PExj9mOcsqqGReb21zkDeY8oyCHiftZ1IHZC7gJ34mwZnqPeZEShb9qEw/
Jbf8E9PJKVhAPbaQE3kQj+2IsPfF8krCLbDI9WNhF+9c3lO2xHb4wUNZQiSp/n2E3C2dJG6hMLOr
DotSEgkL7jfgOVUtH+2CxcStD7rTpaVJcK+dBz3stz00EWQVSnANwQq47mvpumeWm52UsiVCOIP/
CybkQFCXm9SS+OhZrytE3/kMwkFn0Iqh22b4b7ItNWiCWrh+ynbbYzDhiJg0fqUleiOzd5ltMB+X
emfWkI44TtjlZ2eoJSAxzJzsVw4jnpekwCdiGb8N+JmBa7N4nE8QvLX3KLY79AbDnlmIn52hg3iz
exxLbj5p1VoyEpZTXxl2uYcWSLJBPbD8XGvdov5Bpd2yRx6AkHoiSIWScYG+kwt0foJoNhqgyTk7
wLXRZFjjRenuLEDAEt1w8cuQ092UpB9crElGG/ArMU02Oww0w8k6lxnjVKQQcwfMvJwNFLXnRJVI
q7bBm7/0An4DsnKlPadaZi6wnc8hHk7E983Fendj0iZDKeDNqocxKFZQszbuh9dVMp7yTUTR+lQ+
XqmtBvIQlSNbR19m1mcvQ5+vgo9DXRqycTxyai57Ajh0z1Ku6AwguwSTe3UGVuEzpODrrVBR5MIy
28/ejc/hF43dFzuPuI/tx+72R0qoIU1AmQXzhN9F0z1X6cxK/FNLJIYX2HuI2IGb+lNrPyZEeTP7
Oxke9tqsDPXgokrAwjNoXjbj/jjbjME8UXAwZOO8SKxDDhGF55dS7bvrXKvUS/QR6lygkxdKn+eP
Vq6V1hXZMvEldvyDEu8T/b1gZihdwo+VxysW0Z4pb+YXFVgLErJtqmgLMuKx5XxfyoqKEpcbBRQ1
hDiQKYgrJgfAhEBVj/PBJ6GW/LuNQ6Hx1dn2eU/wsaoV2zGujRlDqqGKGS+KdJdbv0LGP104nwqY
hMTRA3HVNXOIn2oPtjnEZVCyUm9CImF+NQZx6shWu6+QVPrdKsO6Has511Ws43khvSvnI7CzAxcn
+ZMnV0queBr7RDYaT58pJh0EGlB+E+hVFz95e1ukd3CQvZvRTITnA/vpmUIj5jaK6HKxyzBGtyNr
R1dk0nucbr9lZSUvWnCqtQjx65ewvtZ8EGRy2snmkwgPcL6YZ3lnLS++FsngYy5QnB9o21l5Sm66
mvj5bmm0U3/2MErYkoq5QF1o7BnUe+7q2VBdZVfJ865K0MsQBcNptBRDJpod8RhBGRfSt2kasyeI
CMSNk669XZdpB3ZiSEzYPPWswAsJUwktJSM9zHnnvdyBYLDbBO5+04Gl0UoDkLCWzkPyNqDOS594
Tlv/Ir8Xfel2KiMNR0MR2shpIxpoMG7eyAxctTsHk4jSAvpYyAWpzk+vH1rUix2cK7aTO2p0sHu3
YfA8sF0NdOlnibYzb5oE2wpLSaXulxNCBVI3aiorV90j3iq/IMQ+a0CyvrJ4nJxjJhenep35FxX7
yAvP6Work3QjN/2o+Fp0ZUK4H0RSWTcL7Et5GYfGZTqzPTgm/1bqBpKbUABgZPijAaz/KyBbcdpy
Gx8ygocD/rRlzTpV1gKkUhI4uJsUGgDvQ93A56zpc76Fb7plXs+wO2+MsmDJ3xjK2KQYqxdMFgZm
k8APcjz1aIwLDziGCSaxzpmfaGz3kL03+e0aBvr+ru4As9VJ03gO1q0dbOTlANXxQyLqYBh4XjiK
j7mJvs1IA3eb4qc6x1jM5D+2KuQO3iqnS3uS0anRJfzfK7MJklHf2IIvwxrAzubo4ZQtSnSmkWpr
GG2yWO0dXTY3/+/6lEpJkaJyM26zxBu962POIIua1FJynD38c+4zdE7nDiqzbKoSptTtkNdLZD7j
7PHYYZKtS7ivGf8b49dA3XEotxAdQVw5L19JMfgfk75Au0I1QaiZnEcx5fXNNXSispYJWRI8DDKF
0rUF3u4a3tZwNQ5o0MK8GKUC4t8Ab46SGLZGsQ+wFc+wdtaLafbJLuINBxPKAY5U4quRugAA8WZU
+7B6mp4nTPsHyS9vziBGb9jpuDnNmccONEfLANXiN6hHzFjTgjw1TjPlor7jxwK4Em07H8H9kmu9
chDmjgzkiMVO6ASCB60iqX7tQpP9uqnj+QhOdPT8WgHjcgH3Mk2RwG8qISmHwxQkXvul2/JWTzOz
NX8pwWjxK2U7zegP1AJ73O0VdC/utvvl1Aiv+IMze+3e8AUHyJ2zIpqNvg6BsH5r7CpV7ZImzQwG
a4i4twf7gtx2uaDNiJ6NrbfUvjPo4F8S0vi/6HW5oM7BGMrQg0SANl5ABXy5n2kbPyE9IUiAAaQZ
90Y5qFoWvoSHVn1CbhDXl5R45AvX/m/4IlmJmlvPv3iHkk3OjXWRR0ds0HMRIo/zcpLs54ZYUUg4
GsQbPsu5ML5mXpg22fSv4h5vrkF+7f7rH4DboCxMEjC9oqHL71Ww2OxsG+gXpgL3yYhxcUEazg3n
daQVZde8Ccm4tTUhAI+VM1oAJFDlh761b9EoG4aTYBRk1UlFduXQatmCkIK3xJEkPUtu+ug3guHh
hYsxnZikHUya7bQza1NCP84Q9eGKsJdFec3hZ6uxM8L7ZPjFuJcZnFJFFrf/uucaxafOzsfjFpLI
U0NLKbor5HZQCMxQyJq5jkW2pliyoahCio08vICZEhVLVEHCObEZOghz6T9WYYBWwFGgmYhwSbAF
dnRo9i9QXzUpWGQXVBm5apYeQWHSL+E+dyE6wjLEZuBZ5SUojbhGhxw3fNAo9BB8X4FQn3r7gc2h
y0CsJl0LFxphMWdLdWnh+XGWj0knyAAQoRv/X0tKj/iQI2mGzBIq1DLcNk72tkkhqCIql468dtML
mX+T4zf2owKxawsbHRy+hqFxrcwXNTla+GvAtAadOD+3JfFVPSbf4BgWVGVyIpIZjemumBzMdO11
y129+F/oI6YCpLnDfRF5ILDWVtKkrO2P1nc2aFYtB9y//nEg5hkUYsEinZOpSEeqt15Mh4iEiKAM
sw/vFL5t1ff6g5WjmEU5JhB/+ESSf5CRcqXq7SJyBQbN6zpcOrnVjajjHqa9IL3JrgoYyTSsgbCb
9Mj2ANQD8SNZ4YB4tS7U/lya5Gqe6s2PdnUM0ZaRtSoEOUUafLHD/dz57Q70HCDEOejjvrbTUb+i
EBu5vIHfJ+wXQW2T431DusoMqxr7ukZN1eO9lz4yE6x8KGENBUaiRSPI226/gI5IuONk9yYn0yKg
RFTqhpbvw/cWsT1JK3r8EAQ2EU6DbgQ23qWo/I1NNpYZAukOsdb19oty1DwsO+ORCRsTbkK/pI4K
v4Tq2meATvhE/AjHehxxC2cEBKZrzsjKh4N/N5mwMZ5ow4q2EtGHA0ONWVqXHUnPySgXuLYbBg09
NgpsDrP62+nlFWb+ItVhDTr6cxZyvpVJ9/WG3XNXVFGTPpaV0htT3VjNEnhT/qwsh12Q95mDnKmd
qMusZ2iIBCLRkCmUlapeowvlMXq20IkvxYDeP1Rza9ULNdEKu60F/kyESNfQXSfF5tl3XMdMgfq5
XhkAup8SG/UslX3TUJxw2GnWr8BIPR9eetZPJvS4PaE694sN4vxX7Og3t7ViwFqmll0DTiEcQjQ3
oOXQxZ368DsamlepsbqFdKSgg20pZuIFcP3Yx7a7w16NdQi7XqSkds+IcHeqjd5eirbZ9d4iJnpS
ly2PdbMsocPJxeREHhFAn7OdPP3SXTrUaBcX0qLsNTd1y78YETOk2B03MH7kzros0DgDGHJ+W/fH
Ylsi+h/Tl7qSA+1LOApUXssu8O2PKAyae1meSwjjRLp4ciPsrUDNeuPjpiVhqw78toPbfKUzQKLo
zzW81hXC5GDrresmReRcjciN2dnFswcVYaSImfhKyibZn1eU+dgyRnJ20eykDdarhpUECevFG/M6
wr6XzECzVTWByDK0VeKS6r9Xg9WrBUFFFJK/ySvTpeSz6c5Jn90JZ5M/DJv5uoPa4Ex9xyxLJAGe
wL8M8+mkGm/joPaHdOg0g21hkpkREc06rbnbybawHHD1D1rvUjj+dE8ExEOzt1mqntPx6/n4yWSc
v2uNh3wkTVkmbq2kLM45Sa4jj7BYEKjVntIJ6Gu5F2FFTLJjxLFqc6VPoD2kUeMF1UYd5dipVEF7
Vi7U2pN07ONcv5Ea5H3dMAyv8k+hsPQUpGKr637b57URNuUKpV6/J9QFFB6i2TKk1OOXs56jWyeO
+LP1o4ia2HuPv4zi1sWvHyp0piPgleRBs82EI/RB5Bs1lR8zZ4U3B6MZm4fLufATQGWW0dAZq2Ul
81g1lFAJJyOaV1zq7bAENJmfoGmpHLDMB1vFH9l7O8N+EQDNdvBurCb2ionyDhoXneEkh1QmevVs
O7UX4aavSi+pzSzRFqQZUdNK0bvJv4kt4Rps4cr8OJuJrTZUHId7tzyA9D91AaErK7hCyUpvuH+C
UInDRHKndpvfF700hOuoPWF8Ut3Qx6gjinXWQhAdRtwnQykC52tSwY9KqExyDjkMMgmNTqus2Q2t
dfwKofF/SGPI9a+mEnWH6I8+9h2j/qhIEKRciFNhB6Wn+B+hWO9b4VpwCRsFGJBrY5oLha98/N1C
OfLOdusdZOkv4pw5fIEI09bIxesiekfKySM2dT+RIZ8hHvRS0eOdQrfWk3ma24pFnIBpreUVdnsh
D5/CRVTVMD/c59HExfm9S7E6MghxAqk6977hKLafC60FlszPuODHdDws0KSRK1oa3LhqpCMBrnEP
REsE8TSEYZG+cMElaXL04RkN+tz+svGaxwlpgYmcjiseqjB7I4oQNwZndWM5NNbLyu63f9FiBcRO
Sd0Pq3RkU9ZqqO1JybyRVPrjDQ84f6nyFT8KK5xgH2u0lqMaBNMmvNjOk5wd6g0PZaDYs8KrLmDE
w4PPhC/vi6pnFQlU9jfJ+HeGaXdkAjjuVPRf4nq6XwyPxQ7JbttjvQe31aAkGA1k3m3EOq+WaslN
i9q+JtnCZwxVwtRr08u81qiNN34cQKSlWRIU15E/qsYo0HadKC6NtU+Y/fi+/uivCs569ELgPDlY
pIIlFDFlhTkGgT+zB92N706z37+N36e9v/6qKgzhGZAEyg8ii8zX+bd5qB3q8rC6IqK4WZXAH99h
VRafQM+Z8ot8YpWl3KW9Y1zzmEyFX49HS463BZlk8NaTOMcFtoGGpFbgTYYUp43v4FfGYRaer/y1
fWVlHhnTG5Cc3BRG9lyKqjor+BXGV6O4htMgNETjZFnVLRnYhie9OhBas2t9TWByhzXak6KtTKwB
/ZzdGi+uONtVTsMKNX/XNmJprwhSOKla2m5liGJsg9i4cxjTHNsUUlxbWMzgjW5omGlPRQY7SzPS
HcHI1diZncCYVPKo8AkYi6jOaifJIHtuJylrUBhjtUQK8UNs8DomlbttuMPJrTavbY4Vn+09ebmu
cY6tm7aky6E0w8+Hk8Lv1SkGCQq+RP6DnD5XRvRczXiIir/cpmnUUkjxlbW/tgxFbeX5TVRAlqZx
C3IiwHhS1dl/IZEqiYg9J5OHO0dTS9lN2ZThgImPK5aHGO3rCHfxXYA0refMTGqJZe9Fv3x+Te+E
2pAAxGHPD7sJsbubc/Jwlt+CFkUDeH5ad2/zQa+73FLhmHedqrJkeLbbqRv2pPlquzv5JnYuxzGI
wH+9OBDbzqMQsY7bKy/42xXIfCzxqzgsTRPKVRzC46br5kgo/GzzBMNY4UCCUzPPevnmT6OFYwfo
k7+g+NRbIGPctso/syqwJyIJO7mHWnGwOdGBpEe2nLKj8yJZHOThBJNrHEofH74HTwrLuZ3qc+76
jsfwY8M98rAKwccts3VcTy5RRuznB7QTPwZQNKNSGHtLIDyqbABGoTWSoNWQ/mwT4Olg94p1gpO7
sqdDcMYEFVf5/ABaMQ8sqOoIDhh4VClSRhfn/QEPsiO9krnKDQhJKZmsp4QCjvq7OTrZfmyrTn2c
FtTvDORgpIDgzR/i7xESvvZRK5Bc9Ulzb0ZZ8bxq1ot0UALGY8kbZ7Z90HnYlMwXyP1r73A62XMw
dDRQxmbsk3aeJltaL0nEtuSf1ACEq5x1AEHJM6daJXQgI5gkibiYsjcOxMa7QmJeItDPzyd41MyW
Iyi9dXyDpwtVuMJSTNg7jLJflN8Vgh4+kBB46fsunYrYhaPoMGooWJ9Qb+WrvGEs5gC3XbmKjuVV
pII4dJq6dE1tnuS3Hzspn76o8tMgOkH13ga97+BCq0/ReTm+vUYcH76zXNr9Be+SxFMmCaaY4K9M
PpMh5tAeO7WOJzBldVo8vv3jVzS+AQSGSAQZKskcQGxbDsyxtPxFYsATyr6uY02jN2TLwxrJBKBX
hkxkuoH77/ufp4oYghi5SROFLaNC14B0xcgBoP7mshZb+iWtBbS9EPioJAljWCWcAUNlZQIgzTjW
9J3k+Fc8pfFYemaWJpTqIDvvf+6TXflapLZ6Fm2Qumho6WiT5nh2Ds3GSVvK+G1gLNRdwY5BjQWP
F3mj4aLLEqdCWprmb8RKpOnbuVkFxgU6Zzy4DDPp4F2EplEVJ/ggvOlZCSFlsxZTlMG0X4pT3jxS
+b6yMRTBPRWCZbUa0aceI7qDm01Z3R8tdfmuE20jTSfqpzf6CQemPX7r9h78XUxnqGtRxDd56RzO
Jzyhg/80R5pRWwk957EPa5umPHEWHApN2sQhH49qDgmfKjaef0EZH3dcty35SypUq/6wBhYVcJ3P
3u0vVai+3pUJMTxflYvLBRQMDYG39m/DQX6Wjh9Q5pzdcHVEhx5/DUSol0jBkLq7MN1LDJlCaEt0
Db0ce40+MQc0aBI8SUn6HvKbvm0/8l9qp9NI4m//NBVCXWq83PR4Be4rYA6z8vovK3H3+7+R9pm9
HQWePglpsQluUCATbblEfrIz506EU/PXos64EmPLBCoR2TIx2nob4XohauVxtrhi/YRw1j/02z3I
Dzu3iQau6VoyfdHlZfR5feoCsyMdrmAZwkGv8C39jrAwSNg+aYRlFf1pEvQB4BPlyckOfgiKUtnW
/mHdwF4d/AmRa0PuS7WHCJUOdJ7UZTEaSwE+evrhqVB2REzK0UAl1qqi9EnIJqDPtxVcEBkMFpuo
hssOjhnf4Ldb6xpyZpRPzy8jof12L7PfM0EbvWKepzBmJLhAVXUKClRUD2kv9NjnQ/+++9sZtkbo
YDQPUH5Nbh/llRw57GtuWB0QHmUNxr8vBYA7PJgDZC29/tI+HxTpraY824eHKmlIAeuJqzozl05N
lMFOCPxW5sNOswzf3kceZySWCJWvKUIT6slZVFPwiwJtJzClvrijgvomipAZMkOwkcWkgGO58u6u
y/OIbMupJxW6867b1BajahRdmY50kJNMiG8dbTVDqQCac1Lnrqf/oZbP2fP1oDClfRL5UwULU0CC
PxQ0Iu8aXUBawlqqf+7LD1K3jn8tdXAewpIyHyiL2jT4/yJQqCQtYEw8yS4klupmsIssoB3cyDrV
mCRZ/xYUPzZ5W72WBPkWQCIpC/zhNx9dAkNM32Wr8kftM0mQGVyCk20Lpd75UXl1JjZzghOwXsdb
8yEIhw2CFLsHjhuDE8qtncfEN7IgptiSG7E/FlrsZNI9pO5Fg3R8jsD4R2oHfSi07Q2C/0irTFAB
iNpAaUYnHHlp2nNU0d2PgBbwLN2j/4vXb8OQ4KhaB7RRN7HTxzVU6mzUKR0eeF8LMDC436XgEJmR
yVAaykXR0DiqUL4DUB76lAWIr4xKtg/eFrwtWCgFjS3PwCrhnzs1vas40aMSF0Oe3AIHVQ32tfA3
8RSRNvvJ45Vc5tPCwhMYmETHy2ONHfsv43juCXliO2WG/I1fhpX3m04jABC726v5BEaCJwu0cMMe
Q6+GMb0D5kXbiffM8Kgic8f0Hi02Q0ZpR6xnp+vQGdxvCJw/tQadqzbPv0uil+RYtvky7AMu94nA
F3LxYQaYV+iRujduP0eFc+agyBS6yfUuPF18e7XX2sJql+GHAuYWoLeKOfUvKyU5BoOHD13hXjXo
svNZXSIE9FI95FM3tVhyJdCCdEes/RXGl+NOZ+Yb00mkOB4Uzy0aKVGooaKJ/jeU33/hCE8w7E3k
hmhK43cyUxo6VrSfIH8CiDPibXSRNuc5YH8bLiN7XCILVT0QdLhY9VICgomdjNEaQ4wJPFEYSz9+
KfVnql2Pla4FUdTvpHTKaihwcbfNUEUMGxyFch28rQoE+ShuCHguDpo76y8/EyxWQaPXr73boLfN
9f0C6bF7oSl8SJxuNl5rJ8leLA7U8CGPQrN4/3E0JP9LNizd8rNssuwv0dGMZOfB9Ko4JrZj9u1D
e62DeQFUO6NifJ7C1tD6wDgCIMwC9BvuG0YXfBKUIJ+GAq4JInu4nnsXwKXavW1M96qx8a3IsFl5
M2jWxioToIADXHtA4uhg2wpt3hFey2P23/LLYqMk4nydun4kSgNAM5UBm+wzDtmvTTsRCGmBzDps
CKArTi0en0jlOlJGDpAYGulVHJ/jxgt+OtrCds/G/fB8gwGUXTh8BupMup817yWAycw2bxMWNYtV
tXf2IYKrckfuFQyOc7iQZrBiIBvwkn/WP8HunUQwmNUnkYLtQemvsagmjW9GCgnXkbz1NZ2orkUb
imElfw+QgfGG88Erlev/5Qo0NbFuHdvoioR6nLhGz3+A1aur2qRjxZGqfRhZoO/+4BYyovz6CF80
mMD+lLFhC2TfL6KqxOmEjHCy9otbNzdPz263WkMPTqNFeljfvrzZRlNSBhxo1Kh4+PzTziXlapBV
fqTetcxVH9iGFIwIkcO7d2lEmol3CHyggblQY+GQaaSe2fc6WSv14H0m/K51qzU6ysf8VB8hG7Mn
NsZbw2x4hNEHtDgyB1yczVvcSX0rS6S02kOnJyZBsYAcOqU8sJxEkuV+8ikR/0v2uA9JxSwL3Wf5
o6S3g5Lmp+Nrb0eSyF5Kv0uCpcnAmsll2yHGCOUA8llUR4iz7QlySbiUaG6iDa6qMbvlyc9zwKdK
cjAb2Z24/hAHJ2i9MU5VAs/82D1oNaAxyUuGjOaMU7dbWxDGd81RNrEqRIsN/toz2TbsRJJkhmT7
vhnQuhCe8HnHl3VqR6kfjfy2HgEMefNJCleHX3mgC7yPJ7Bl0ApjvBWTRC2sLRxs5MjC+2rQDOtY
zInI0gSUr1Dj52665rWYzrKWJGeHEImTzurRIg/hxnpVucUf7gg9elcNSEeXBS2j2jyZ8RiFRxpo
UYTCpBBsRAkPFSLHpcUxvDYlib4yRsG5xMd8k94u1KdQ/NDEfCTXNME946LGuiqDnGUbMWMl+jqB
pTwHfS7rlXo7FrWqGtLQ9maeSSdOoiwsRxBYgKfXD6pdtM5cVnD3J9chdSOpIZl7067Fev4MHtJQ
fdXsHy5n8mWioMdxdhPo0BZ0fKvkkMiAzZWU3DqewXsGW5SfDJVsaUvDuwPrInPb9ZkKPIczuVWy
KmyXSrm/3kFWQToIV8iemTie0sZNaWOdpZAzyTKCW/kO+WddlDMO8HfKS2KN3WBzfxEm+34pZ5Uf
TIupcaOGUAkdizFhIaw90mUn1DoWTcr/LPyA9Q3h/coHVsqSnqoH9mvmWNaO7Z0p3rxxvp/P8bJB
Mmw76fwifhH1s0lUtfoEuRoMVCGrOPPFX7eTAyuTD4y/NTKSySJnT67me5uegPj0aJtxI9yXoahu
yGMq/z4p45/SYBBTWrpPkMkqxzj8iJTSvQxPrN2nYzrJx2mAS6sT3qabx33JgLN4kheuJcS5NdX7
6utXSyAf0KHq2tHUKP0k6m5LDiq5Eb19AI8Ge7IiKAde82ytSQdSbLAJiQsmW07OKIFJFFq/9i/H
9Qv3i4bRjs8sQbFULdCbDD/MIfbB4zF5me1wgB9c73kRYMK/iGxHsSTqHcHw6COdOfLYVDbJu7QA
vRQK/+xax5oWvJc6Ka+UVgyEp4GF8ZxywbPl2MMSzYVPHlXp2+JoZhBrzbHpGdzJa0k5lkkWzxlc
7GbtTEdougsEWohYXvD0VEPzRXskPO76eMB7g4quUCMzDlKHvmUfYzTOV09xYgxjpjvbn8y7JqB8
WbPrR+rKdJWyQ52GOQFLJJ0tcfn8+35g7yroCalq4ioqY5u4/8wOlXVOuoBE6kCOXhytlprlsI2J
j8N72vcpSdAM3WLwbUFnFV5AppZPDWStO3W4NtBKcZqY8t0r52urCAVkDFxWU3av3i4BBDT88Jxm
2FVp2B9XkPknq5/I91j5Mq1nfF8DW1cWSm4YeO6CMsx4B5wEOZgeEo3XWQgnZwb3l0+h2NuA99EZ
AS/DPrRgv9uJJMFsiPmtXH9bQOFyWRilAm98arl+TPX1xg5pvER5uFA5HIgD1lwHfgEL8NYMaOqw
u79i4l4Osp+lEYWx5aGbws25UWEDj3UNCfJZIC1FJA54c7UDDZAwQuggenJ0Vfso9M+EHw+8uZIQ
rPKaZdPzFnH7YNreVapKoRdSe1XASXLATrXsOsPj1AgcUOGeEG6Iytdb2ZZKmITkHEorvhjRkz/W
DJ0h2MQ0KGpcpj3iojlJOpP1h/gMJfx8+iVhFBuMLbjh7us1mu+CoiFzytAyaC0gj0ak4+ffJidO
kPlJm8wWEe8oDqhngiB91z2euFh/3z3ADlcLLbjWg3bpG+aFoVQWucttkd280jApR/S99n7qpcXe
uksBRtY1vHAaoYvanFQM1h5+riL6f7/wBohXcvLyeddqeNwy5HbQpd0Bat1OJpVgJNTMGN84wNap
iq89gEo4+0Bs2UEVCpEjoQMeZNkpVL56HB68PmqqaC2o0m6KJYPO8OXwUeINiUuKYnjOsIKxydc+
PXxb0aUqd2NLGU6dQLkP4+g7k14EGgRky17WjELOss+Jh4HSCwKOfGZ2h+yYZY8jBRg+iaUWqrgf
q0loP6OGb2uTqMK9aIaYuRREnGJwT1p5RKCGhQLQ9b6xkDEUsV8oybWbijCpnJ/KB7H3g5ItdBbi
Jc8B6J+h9CF0KfJ07IYG6OTRAkiALZ7C/wl1/tHTrJShpUhbY/dUHVTbbkGcZZfRrDX+BzKd8F3m
PaNW8nKmHrr5ExKjk3SbRDspFaCS9IVRxBrkb/4zrRi3d7SRL+UXhE7g19kmSRr79fzXnommam7q
2rl34h/FspZBobzdSWyZPKJifJY4wnxP5iHMTRTY02WOj2uBqtHVu15gSG5Wb+a+hCn37mwM3eBw
U/DtP+6OmeRJgQmN1TulVbOvaQnu7VrnJfm4dWd4eCE6KDAdmTzFM17A6+nCF0fZ6ucnH6UAS7Wh
d1gFvraJU7dMdKkrwtaWAz1RpPkJZuwlMV34XDI1cubbiymbtyj8UOcxupywXzdXqOaL/aNPWdLD
r03xXjYvv0T/8SSpUuvcYj7XmLpajIdQ6B4BLnu64Qur1NorcyK+wveSpxJhdXiDnrYctSQrxZdK
xZnovKsjYDfSq+WpizASuuwi1LYM5aibW7pAT1Y2Sc8XqaKSpcYrruxSC6PMShwhulqdwKqgbqcB
3bcnIqN2wXERRjYUlq65Ggki/N7JEkGVAoGftFwZetDULnmD3mXclu0X+PBXQBDaVK0NV676CnQp
wbvyy31yympzxekN4qbWv+8n67dhGuOMEp2cpkDJy8EkwOuUyWFw0V0cI2qW9NKLfsZVgPSqUk8n
VLspEz6rzfGqe4zvpuE6dfuGD/Vb+mavvK8+mVDszuVnQWYm15q2BO3buugisgOWJTkpgI7q5Cre
ml5SGunbho4VZ4UOvLFd6wIYFDh/sUkcKSnqpcZYCOLNLLe6EIIVRLmhXEEjStMYdIOqMdl541a8
jfev+iY1n5xYu4EQeGGEQz9kJ5L0QBXUbeV9rR+JvieB/cT3AwREpRzftZa7e+2+dwSNnQGr4RPz
dkX1EIgJ+KoSm1zv0oJuuSckiGOEelPBPWWCbA4qesL16M7nsVbGTKl5DVhKpJsKgJQlLP4cAGgS
VxSEuIpYm3nisX7a8rRfvqnEmPA+ubjxkRhI6axO32wfk4q1sVGvdNNuJnUotnxh/DJt++LWCAMx
ZkxOAeNdHs4cuRk4WYNlJ6jUoQ0oe4QcrxyYxQ0MocezcA6nrKWM2xSm0QThXo9aauBYGILPkj7Y
y3gHwIJQLTWFvvU2cJeb96SSYLn8nnyVjA/Nnne7JB6HnulE2SrZRhQ1rxZK2fDMI7CwaNFePzag
W6kH4xV2HcXJ0zYOYKRxA0ibwjK3CAq4437M/jH3ogj/I87BYvPBtfVz/mJL1eysUjMQ8eHM1cYi
sgM1IgJrAcbmk9VKFE+Wjq6fFla3Hfr9zcCvhobo8SuLRZvUcKAkPeEbMO8iVg4CLF0g6P0L8yvV
oT7c5Prjvui+xnwRnaq5FbJq2f4YJgGVqzIr2kgr4QZBSKkWWUVyMjrNuynFwnRNR7CknI5bPYai
JB83g/jq9CEubL2J8BnSef6dqSNMiSHiApNRHd1ay1aZidS8WiQCOZy6A10zwZTqk8j/dcjsRbhL
+lm8z0Z2YrWIYFxBPrazEu+S/6iEwzLPWHlGiqjQ/u7BhEkbDuUf+zXfVLeuBFeRtAo3ktEY7vcm
WTHCF8V0faistU1zi4L2ckHJB6Vuo/Wy0ubbhfwcQOmeub+hXfW17vfXzfTlZYtG6RxPe8Uo3HzR
b/lKJt+Ie0sTYHBxWOEVRUv+HS4DlxcX1/z+nX9jM2d7aOmwLpy70eaqeX/ONI3YqGO3JtUNq2eB
QzUof3MLpz4/aDsM45++ERdy4zQ96D6kfUjmHBrrj8FjSwi3569Vzv9j28UgWug0bF909BYpPoDL
HuUVnIFTR5JN6fJwlF68R794j1PGvEs2wFXPCV4rliHyyUhu88MBAmYJzHdDlgBrccGjJoKU97MU
aho9u4JJy/t+GKafMnLr/fW3tJp4bwg6uzkYxffX12oKD54vAnggai5oMVE3FXdfvWCAjdOF4QeH
Dk94Uzp3gSfFbinxNS+xFKOzyyOpObRVtw8FjEHTZgJHu30yufm1oiXrht/vhNxe+96xuAgKVMkY
NczJZ9xHoJY3yaRj2ODE/rf/ceQRZO7Tb24gqV6uE+yCdJ2k0VKm9h9etftr09BCiJh0ZVfQTJmn
IteN+RtXWADPyt+ftfgc5n8lmWzfJZT4xcfSman93KWe05Kz76AnVz99V02UqgfFc1BLo/ymrI2I
tWdABxV7qfftwex6tL5TexS9KBUfRdDTuUrRZK0huGdnDsdmweenqCiwG/BVVNtWDnt6RxBVGi62
Fs1Cvz0kkHVzFkSApzJFILDWum16YiQyr38rugEf7lkRLF8rtGpbwZqADhP5V33wdhjncDAIstTw
UQL53OyZdWpzqzxBadaCAxtAs7OJYhRCqWtT66c911GuyG0rGjqgERlPC+xlHqPAqSsMaEM7i1SR
vKr+l1RmYLk+Yq4s4WZ57M5PQVYs2oBLZRzLmxVSTSznR5il0L5fWPDZFj6jUJk0qKJNmRiEr4Lc
xFmUzkAl4xzJDj3LO/VPxNZGm0UfSfcCObyLqjwPVBFMNpvU1OBFdZooj4wlkEeyi9d6FMmP5xLl
coL3SiBs+WXbKDh86srD/xONuSl8KhZCtRYEUeVrjjyXkYD5weVSPCAbV09j/fO9fCjV3ojosvNI
tw52D7gDOIHwQyDKmAvWZy6SsmuinQSXsxsKrNkh+VfX4Gmllg+J50AmG2cZ2nhUWXo9TBjUzCsR
K3yVPwylsZG0rgNBtq5PnwzqNydZpQMVCUKHrUABJy7yE9HLduVrmk7AeE0i6zXWuuBG3NqxURKk
IPVIQxxoJFFFtoZncgB0Pp+I5dfY7XYPGaf/fdYjU9xTOEeipd6NQyHBpy4hM5S7fTB8WDXKqFNp
1PCH6NBCEtUiXRVgZlBZNS7oiEMX21GMTuOgORgDxd7zf1B4n8uAH19seq2/QffFmA5usSVzLNqz
XBDwBI9737ffG6jqXxdA1nCYT+hwMK1WpldersxQp63LhfyHnicofpct6bcuLC3uRjlk+8f9oFMs
IBynI5r3I+f/L69Z5HnkBLVoSdFMTJo2F5A3sg6/YPdzsPSDjuVv83iPd22cHXeg+79krMdXHKDo
q4ZFxNQZkC5hV/6CLQ0qga+yDj6WWOUvqiC271ImBFZL5ndahsEetfCrdkhUwJAXLg2kuFYYmYXC
64wwS1p7xTP/zCV9WRx1nDahUHhppHSEApS1Dd1i2zAGWlMHlKJeKT/X2u+iUX15AyaCca7Uuikg
s1HQXSy9wcITBO3mkNotYNOWUQhqwh+P9/Ab39A84qxyQxvHmoh7PixjQ1Kzb4U3RQBMfWKRMie1
afKB4myCk0A6NBULQ+CpMZ207eC1XXADqNbWVHecNQDVT7Mre1Sd1RwX7KQ2Kki+E8d2WxHsWR7H
r8wOTsXxAA79cLO/4CSXEPacP4sKv9B9QXShwViZe+VN9c6TfLjLbZ0l2a2kC8tHuqRUbryqe08T
k3Gx5MQ2fH49vWnhr9lwhjZb8XaXak/Kda7otn2g9dTCmjVJNf9IP4Sqp/bN0qft2BwwQv2cH0vQ
9X0Gt6/rBmrOZpkWYrpdcSmvAnRoJYX/yS6zPlgL/i85fkZV3GxmNK+gdIQ+Umi+KcwHfGSr748E
Ar6fxfcZdexK/VJiz2Zvj1UfzR1v2uAWfigVMfFRMuYjPirWovD7Qx7mOFMecBUKce02PEoUZyYu
c1vuNKKOe6D7hGRoQDwY97F9xOEJDMdl/RRg1MJZ1LbxcMeh7fvEJcHVmVyUNLcuApZi/563gvDg
DyXcqupNhyPKfNhB0bymuJSF1xndYiVDuvp+0zGAHaaKCX13+hotRMwKG0gM/iWm2WSG9zEs/iiS
kY+g7wHj+UP2vK/XML5ZEDLS/qacp1PjUDpWLQahzYb2b9ToP4W7rMy2RR4hBRzU6ehUaC5atdtR
SycSggfOaSW9Cax9NXoMzn8eNFL11wyfBdC0YdWXmxGO9vjs8s9uaqeFMAv/u/hYdVUZ9nngwStt
FEtVbuOe23JOOW0Vy+M1/Tnjs9onQhJlku1nesUXL7TbCYFfM+8uuhvjU5otpYyLpACNq6w3Tdo1
+kwarveO0kT+FZwNEkjz9HAEjoFCNC6kIgB8FO+X9NJikjT1lgPBdlDe3iSjmF1CIvdiJhYK1Sdx
9sBLxDD0k3c0Nv7Joy0hnYnEaYWMeXehB8+vrZpVaHI5j5X+MoR5jkGn0tiNTjKrFe7QSAx7DIxa
VrsRkQJ17E7++BttqKhbVcTV/c6cHNYXVbvl9CavhxWcKdKgUlYY0QkfCXXEvJWdaQhhSBBlu99o
zp4X/I6r++3iWFShcQdlWXshcKpysDEN1w5yVgikrQ6r15bxaxoPUjHRWIQbTt6+8otBfpk7ov80
FPWgrq2LRPrQpEiNBvWswNxRIiRHqxU2Op0agflui2JvZvuAYTWsf2pW1dyKMive6JRploU9bzgu
7QfVNpGLJpbFTFjFSpMVd0eaYXpuwYrjSOx1ay16UkJufXJcDok/Q8jd7OlswvU4jllVrAoT1ND9
4uiGl06OE4Z9rw1TkaIXPYMJySpFyVIuIaeRMXiGAwiiJDBl0aoU1yBRws9VKdViVvEvjCqflAhf
0IEIniH+tnDq+1vqRbVZPm87te8cf+2Xhrz7IXFXikzkq3ug+BsPaBGfOrzvRFYswAH5vTk+6CLp
bRCtbMBy4bcPhjWCGA4mox6c2gXCblYixGXyIf3PjoJbEht14kFsc99Fpa9mYJrvoI/3fizgkpAm
j0S9+vGYN2TOTUWmst7eHl7xaemjvNCCca0Ca6jAeVbx/0pFlS3+8PYvri4miK+2o+I0VtCRwA5c
VY70THZKqPUFHS7h+XlPtQ8pLeuvULkUr/fnxLcAinXLTnpQLimMoPypZg9lIG6ea9NemDUCJQ7j
Ugq8U6eGp5HgfuKdZ3W3P+qIY1ronCQYza2UCyR7PD8MkSNQGa8TQwyaLFNc7MTHKQoUimFgi9+4
jTF5dKnwxlCact7xAjXqm/E2QtqqeQqwc5UDCYZfoNO5Ndkk5BOg80h3g00jzH02EQ/TUoj886u9
PJIlBNT17XjxanfEiaxqnIG9PFoeHfwwFrSbhvlqeCzguKGsWwyH/M79XzE6spymoQiabLXOg0Z3
XgGMxQCv4vOeYACKiNu6DMWL7YQT6WWPm/NWN8IXcxe8rir2YCEjmA2o6rhbnOt1DAouyW7AejKt
KU7+3Bdr+jikcZor81+AJNCOzovaMp/veRMV5mhiO7DL6jccqkljhkhds1SbZXdxYImEBqhM1pCs
cFcc4B70O97PuyxGf6KVjSecCd08DHyzyhDdC3c3NLKWIk5o3JTqQYRpycL8H8mhzfYYXapMOJiS
uinojvkc61v6Sk1p7zHPSUmWMq6u1UdgbLtooMNZvAy6w0GfINzLe/E9q3sQe5PBaDdTq1PsUnH+
KYChQVAMB+64otZlrF9J8EaD5sZUTpXtAWaWy8CvZTXJfC1p8ewbfoIQ9EmMViEXtzHlAQqskuaO
puffJzm2byq/zvgwtuVDxzHiu0d9K6l8I+M3YMA7HoAfj1W9SMROJHJVw65Rr0MEitZNwR1Ybfs5
wJaXm1xVoygy4SylSBMMqqaZNPdms762I0A6DiAfJNiFa2yOHdRTu+806lqI91KQ+j8mMrLDZYEQ
Ar82swIfLWsWDdN8KOdUuB0qckHyZitngj+XZiujM4Gsz5+9K8Z4rY2FBnPfWEg+jciwP00mNVEn
+3t17PpYs18iuj4ADCMti2CV/8J8XMrdjEMC7VBKXk7TEBKwbh4Ck2NNuG2CukxrH2ss49psYx+B
RY4JQnb1mZUiTSdXyZHCTeksu4tNESz0NC7iViJ0Dzkv9EykpmdPN/m8kJv8aYx4oQrpgx0okmCf
QtdbLse1CJGucNQCeiRdqAeqaY6s5idoLGU6Gupztq7PX7SZnXn1iiFyGMPJiP/LwZB3DXjBBXBG
KHM8AuYsEz+rf22DJ+/323hdtkVFDYuU74GEzaPSr4E7I8hbDDgzEmqn2HdhvfBUyNPkjWTDsBHJ
s9C1tYlqf56UzXhLKiEUSIH7i/+B6D0UZjxftaX5QyZgpNOiAnf8jaBWOi0TTWUOEuBjCJTu4rb2
Vkl/vHPeXO93OJQU1PEdGqheNqRTl/LrYxUcledtDxkSQGYBlcYrGN8M1L/ULqX1aOuycsQMBHal
3+nxDe+JXnXWobEDZx5TeOyi6Ifj8R5lTVq0RJXHvRfOBJv7l+fMwv964BJyGdM8+1OHkOE4SG1I
PX5YYtrYDxux3TtBifyBDPisYjXyGDOPCmHUTV12kDix1a/HyiN60oRIu++7gBpDL9qSdOuewaqF
IZ0ywWeCvOJrIhUADZU36cvSN7p6ygncgVJoX+eu59X+RL5mx2C6LoDj8XdeZGLWoBBATIfmi3Kv
kViW8CkwuTMyEwZC4NdRMSFMPjcMd1hu22U/M6OfXM4P2xXOdiZSTgAhQspOqqsBJynvcp/MIrsn
tIyKIqxbun0J/lemunrFBqwuWkRBWZv7zleSnqavE0zfR1aZaoHwbOuAU8EhG64RLyET3WZVRSRp
vOFVTwBXGENf3tmD6UtfYEkvoGKzWaoXd6MjPAtzIiIMYPlhIO1/8P2+06f1fOgdjqYaQ6MckNBy
G5auUXq/9AGbvGwApeVJaRGuc7VGE8YLbl5YSbkAVwWnyP80D74NiWM6iU4KxTOcyxGue9z6N2Ha
FRzIhJjlslv+hBWRaNPgKTSX18V1g2v5X1QGSdu/vQUZR1Vk9HU5m79ViPqWVbqf15jRdE4HRRZX
Y/LG4M7p0VuSFR5pzUDYKuPpaPsNjizKEnFi1sE6jdzqswir0YQrL9VMiROorG6MmnrHjBHQ10gu
k1z4a9jrrtyQzl+7SaFjllmphfMEFKP7u/7NthnJO9nEz0sw3VIz7TIHsaoKjWW+VYs70hGRTlOf
vsacJLuVHGQf4Dz3v8c/II+3e5dPVulGMqeQlVrIA/XZb+YfyX7zorXjSM2hDE+xJOnFSAQXpzsr
WGZu+ja/tBYKIEbbTeNrc6zloE0qFAF5XqRMNsMnnVYRcwy4HaV4Y7f6uCalo+MJ0OMQffPKtc+U
dhB7xTD1iF8AFjqeyV9KPHM8KeU5C5FYzGOJsgHQv3gZalRLq/t/w4ys9i2lPBQOdjGzYR95aLEZ
X2hSHqVpog5D+cnPHDHdrDF931DQFwEX1PGOiwDGEU1lYOnGYqCUzNRJdqbGyX4CZvKZIv4FNXTI
AbInVDh9DfFOadmoUC4dzewHPddgPFBAkMkYwbwYsERLJYyi8o6FaGn0SKk0hggikHDJXnYBt/S1
28VMRDeGAzbB96ulFVcsewil0ZSoNYXA0uq3WbRVA1ApyYzC/R9ibLlHMKynVLyhI4FhIpNcI+1e
JTnSQdI9KolrpcOMLXZMLldBk81AqPESR00atYlK939J20M2FBoEhzm3fa5sj+NPBweTOXCqIxC9
h9WEbOS1mZhgqm6+K8P7dft5eAqbpyccjsNXmKyeJVgsIrfL4ZbBqTYuE+iYtqNBDzAbKfSvSln/
GAwO/yZx8rkHUFWGw8DBx+0LpOW6eDb48qsAtFfreouSsUTjUzLcDlGn82zkYpuAA20rPRe11yKZ
ADEkb/77JgJaS1ITtm2yFYqUtF2sdFYcCdq40lZYILso31+7Xz9C+e3OO8SW6KTY/2dMB606VymS
XMJo3UZQui3HUJPCOw3iAz3Z6mLUVt7BRRC+DOwx2fAorVIf4frWtcMZ6r9YT75jBBzmARidwNhx
aC/8hKX3SWxfB9zJn/xcTmXUiSXnxf6cM77PEvJC5SBmHI+hxPPexYOWui4dVHoihuas7v74b6zK
63ZbkJENCWijS46YvCqhM7lKQs8OruXrlF7MO83lGJIUlT2qaTcj+oofb3W0woOVspN2vNB25ls4
YAq/5ZKiHVLgiGQvnIRWcBLzmk/VLAkmk7Md8UBFgPkX8YgoxsAfKEKyFoNFvX+xBPdxBq/Sm70U
9ZdibwQ8y38OkeIrcDYSpXz/HsFshUep/6UXVvc/WMSuFJKxQjcegP9lUJ25YRmv2NxCeaY/1IaU
6Kx+EB+wrUFLAxsoHhi+gOCuXvejFSxu1ySnx8HKwYA4R4W1lY1viR2M8PuChlC2nF33ZVHXJ2nQ
DxarSQnqlpDvrVKLkU2no5WIDQVmbynt8DSAEWqJngB5ZQVFTPDbPjf3OOZnWb+g4ylAEOal1IXh
r+ahBktvSdSsEAC2ipxUYh5vhu1j+0r6OxU9kBmqYhZBF/s74/sJsAtGTaDVGape1/a59ZypC1nQ
a4D88MU3fMEgDrq0KgimV80qiyoAPyZCyhwNF3cNSAwyqR+CsVMcIkkiGwcGPnCdGLVm2FusRjW8
B2vMSrX2MX5TTJqpjhQcfRdfv5pu/zQAEnVSxZzlxA9KkeurwNCXlZH9NrHf483tKikgz82uYpcr
zmAqP173dzzYrKulO4X433vMGW3EBZkHDoF3OL2nH23aJzfyF7QGWCQPpQQEUdhsxg1x+qA6dwQV
m3+P/8NlNIJxzxtijOTfeJfd+nyUfR2ZCFanVjxzJSKuzL+Ct1zfEIR3ffngBmiuSyRUbU5bYQRz
IA/4fNLcSS7HcLapT68DmS3fX7pLI1HUuNDBJgz+k6VTYN+0acyYZ3FWskY2A3HpNtvN/2zik8zT
sOrrenvlS2J8NoyzpLHEbSeF0JF8jYJMPOCobq6j7D0IoLbYOiibljzBYuatKndGDJDPB+++UTuJ
y+GSDRe6P2f7DIAVe78um4Zer6v4q/qudlM3gSdq/mVXxUU5msmjvaXmA2o46Ez9uyFccZOrHDEQ
EFaFOh9cJI/8L09LsH3BU9gnTzzpe3Y0D1hpP5YfrRGI1pLdw4yzXFKfnHEyE9cOT3hWlmMxFLSP
6xo2+MkB2vhVC+Tq5fOO/otnFzBncr+pwQBjXDvLwEm22FtdlQ+qH3fsTIW0UMYVEV/bXwN0NUg+
FSe0yQ9TfVRbenHnro4OIizPQz66l6HvZtj5Kj+I+IFtpTmMpGCf4mY87j5pHG03Sn1c5cys+ugh
16d1BadISCfGGGHOfOn0lIAzL68iqa4mvxE6ls0GYHe4/ymZ6liKE8x/37jip2+IovIQmiabDtyC
3Ru1E7nU+eBK01YnsUxKHmKZPfvQpMmGtfN+aQPq5woabaJk7J5Q/eb4kUFczyux1u10U8fT2dG8
Nqkd2o5wN4oHfeq9lwBjgFOnh9+ei0Z3z9Rqw3zd4uMZSC7FAqht4ztzl/ELMdIuBxTSJ9jiUASe
w1WnYXBc9X+EZybEnUwa4ZaMczdCqWfvQOR2HPnAf9Zzt/8zyXW3QfJXBNDHqr5zLsh+fAoHi5aL
6exI9KLDetduu+CAaCC8xj1IDKZdu/QDqxB7yed6jOSiTVIUUer17bE5JwtDElWwpM9LRXFkNhj0
WY+RE2IYkH/QIwHi2zRrX8hL7ief0FH4m+MaJVXMltKIxM+Jof3IX4tyryjg8pyFE1QDmXQXeGij
Ns7vatC0noLvq91xL+pEOCRIUkyrmh9gw6r0w5p5h+dwmMahv9DNDj3zP8ZvLIo86jhKtpKvPKd7
09EPCG2ELXFpqIZx52sT7yKI31aeHcPZLyR5qUbSpdIuHnA68X0PpQi8Wj8jdJlbGOsMNHRITdCv
TOqyiBxfRy2Msv8F7uVyRG3FMzIxYkUfM50hLEsa5U3kiD31pXL3RwXJ4aTV7UjagZAg31hB3Ild
R8u2GEXmePCvaPYJUQKS/PSFf9n6gu3Y3Xx1yhQ+WqU780l2MklO608HvMmeqIIF2ba1ZZlgW5F6
6R4EZGB3JzF3PFttbqEwzjArAreaUVIh53RvKsJKyai1S/UWH8DXNw0RFueEO5h8DC8ScLyX5xgr
6pn8IOo8TWqxOLL7OffYMIBTgvllZ5enpdzNAvXuHM95eW0sUOnyMI9wR86+m1mH1W9Z2CF7ccOM
4jmjwPE2pgnO/oPnZlFUNt5OcMMSlscStgTIBc7vCbu8QHX7Kn6fqcYD1yqzNfoJ9k/68jmPJ9JF
ubiorVUxDc4NFYkQYg1XMoBTYrJgxUuwUc4eHkK/A9uYzvRrTYKo2N3lLWdpGoD7/nuM+8PvrlUq
sVeDz/ivIMG61J+DruIquOqTOB57hODWG3k/dZ7Z8jqmK1q7Vf0zuRkRoL7T1ArTKz5ApG/i6kx5
yPDD5MnVi7RXgoa54lfAtWbAOuD8AjKX+bfr0bGB4MR/YitnTd/oKVoVY5og3Y3tP5ClO+krsB0U
VEqZuFcS71qdCihUmMh9V1qg0cCxims1ouFLb193uyUr+ZwIP1UdQvF9gYh1nOKlI1a4vzNAG7c1
q2CM2NyTi3vRy/j5k1lL8ASWqIOZnvMXadqZkHnPs79OEOeBsy+e2QlQ7BjWBLZD+1Zou8o39J2D
ZS01idcS5wxp/OVmHgemnovw/1EDeStzjU/3yDdY66DwuC9JFHJ5Rilu4GT3Wpurm9USlRh0PYw8
4W8Lwuy9mAq1r864Emp9QafoOdRLyxMd+SCwFuHpe44o4PEyUziPk/E1qx+rPh4mkNq/j2K3HM9e
ygkO6e2oZi3tC4WL/Glnf6H4MzdSKBKc2LGEOhLAH5Qp6owSMMiWxn3qmXDtVKiJVhGF2okvP6jD
iv8JIE/cLYY+E/ke4P8OJpFkzQ5XLdiptkBoEi+IVo4PcU8GFCk052KfUWriliMWlS64tYPVuXc4
btUSo8QEuJseZYBdeJfVxyf041ZjjpPqXooo0UbIpb5DwAeRxwkjI+WG2b5dsvdNaHdQxCYY8AT+
jdKfhVWgS/F/mRYSjGN+Ii90ZU1loCr206UmQaiBYcuJ4G28kqNU84ZSMMfeI2Ha5kdJwt+29u2U
zQwiGh06Lqjjt1CmwbAVkwNib4NM1JI7VfUGxE3ze4TBXvScJaSVNM3nhGM7uTtr+jFhiPUYCoUg
OhqgqJxoWbFyh4dojGcgIh39AZOE0QL4cNdkBjvmCMFCh/ODXqVJMTZmj0w28BhmYRSufA3Z8x4t
X82anIQeAm9K9361F75Auxyqyhuy50tor6mU5FzVLJ0P2E8EdRWIP2Q28Awkai1hFUbzfSMaRWMh
/9Rl5ajLhoBwPBPGOXd+66Bkyk7KAlWlYwORkCNaPZ7N7Nwv2KWsLv4wvWP+NRY/7iB7/wHS2BzW
0I8n8H/LTzomvpGhndanUlOo1fzPEwsCxyhKiv1fNPVjGPRWy1DQmzfh677UuIV60+b1Yq1QNhd+
A4aK52YMVBNVQDbA6AcQ7UPWJOcWdL4sIRy8WQaAFGpQarZRII5rNoegkDyW/5uRgxFuBLamNHfg
yys0iN646sR2VHZjqnXef7iH41VfcqxrFT/COlqZWD3URI10w2efrp2fa9MOq+c31i4nabNAqn0E
AsLk8MglKsUVvrBe9HwiKgS6hJUkHU7FQxjVd6axw50GHDzKflbxvA79pxL+8c4xpw0OHPeTZjJt
lc/M1EgKXMMFlWPqKadxQgsPRk1sf/56YXa8q+JLUtLxi1TqYPoLhngVy0cLAz2jWU/7ia6KMQis
9I/gNrcDj0i/cS2zckfavnxdCQFnqAkodHS/K4JnWWvrWeZkR3yzrzlRVWVayVG+2yjY+qjjfHJ1
liwtLB1gyzoyRjmyahRv91hFAQ2FNW7fixjrnpUWqiUJ50GuNJ0UHQSPdwuDgx+/1qPF7tRDniY0
cFWTppHFTsYu3C0XfOiW7kPQuDzNgHvr3znndPrj902II2f7H8z6sxvsy4goC8VwfbBGgC2ZZXVI
gs0R8bhss40ZS8TOpQu1s25uAqOAMShokL4SzDu0CfYihXOcYunTloX4OdDtCWqyNrg5gC1KOkXZ
jMImIMxrpamHFmk19lG5ujK5+XhoATjBO09Ba4ryH9M27mPOputQ4FQaLnR1EqTOJIB4Ac6UudIZ
YrkDMHwazJYGIISjn4d51xC6d85H4YwXjMsDgUgPuBaq/6zL0J8XNrCD004rxZSIfs60JgJnO6nk
ew5oTCycQydceRErbNJMhk83DNTZcJL7tRBe0yTCdBp+ARYgOVKiobd2XrBAuqCwidvCwqAJJ0+2
DbIr8umW4LlGDVFjCw195ionMjuVc3p7CewrE6bPGjrAo7uTmjdhS4n80XH4EYz57NqWSLPksJxi
zKZEQego5efST8JJNksgIGqOnMIc1gtjmJO+51dq70sQRh/iXMwanLQJx1wdZ2S8ZLx/1oJCJ8CC
3thQQg/0wUWDzVgM4Wjp51wbYZyh0E70b62kbBtQKVfs2quYDOvDajg+Xh6l54BnC5oWBteK6xLr
hFPnMyFu5beCDYvxFz8nA4TVoqR7u1EwW83PgAp7Gpwby8Y8Dk6CH9ayO37Il4TElcSSwQgZh/s0
Qxe6wK/1hx/PNEPXIpr9wUEQ6tzm7Gh2KWGFCi4LnV3HgoU3DJILLPrd0/8oP15KxkFJ4mFIzhaO
MiXEz6BLLpQvkQD5Zvk5O2UwQt1I1K6KHDgI2RYuiXjdXAr+guayI2RcwOECpmXqIHd903xtN5M5
MQRqLaiWPKofYXrlAnmGOnOykrERifgNKEeStUtFp92Pu8lqAcN8XLdeQfwFB4fEOkhcJLfXo/q6
/yZlU60KSaqbO5AcQpeqkRk2AAv0YHthIUFNAmcMh4ZK9c+ou5CcmIT3g9xBNVrBy5qBACa008HB
ndFG4zMYNf55I/JYjH3qKqaH/bGO8bPXG11x9X0uea70k/yAQXkHKvOUYOgln7HQnv+ooaPPUE10
Up9q8PzbSJ2a46YJeOHxdHZhzs2VmlALkymXe0qYVpqBojS0GWci9WBGpiMwGVhRJxZK5qH9kCFe
U46tYpbs+eB+47hE43BT26GAANsit6+hg2/N7tlvxZR1Mxn3NAKTAnJk1Rw6dhEOymVrH3H/sPtv
+IGViMVEtOtHVnLNh/1mDIVp7O6NWdVeFKlIA5agBsTbLm84F1NQ6cJeUfLcOZwS8jzgqhKDcpXW
5R0RapE9nb8+X5oOeePEx6WY2c3/zq4nXMZMV5plYpx4dJUekfgzkiOWEzfuhOlwg3l6f9XD36Wh
0CwFqJYeDQHEJkMrEP2ngAWsZsf4EvLNVQFQHHvhAi8+JUc1kJB94yz2zjtj5gF2rDfj+Vciw+cl
vu4XR41zko7yk8xq2r5CRAYgKMjZZgDLI6fAN37aJpOR570675h4PTe5WzBKxVtDmi/a0Fil1LTd
MA1xKXv1Vsn/JKS8cFOlZSpcvu8Jv/geN12GVYhTFW2GGNfaer41QROPpaDV+eU9lKzIQRWikUu8
nW6224v5foM9VkYgmaTKKBRFc1YpjBgj2Ls/hMUz9xvW5QpZ9Z2uzoPXLcpww3EeAu0EOfiL7Xik
PIp8t165OBIV7gnDpfbybrwddZyPlhf9b2yw2ScnuIldYocYohV6CTCwGUkZf032s/ubfDkG3CWP
U/DqE50Y/cgUEbI9V3DMi3DcTfn+tXHPQnCczlP0hhJnNrbGSix9wYHhpHsYNVyFyx/He5PUDe98
XK4IYAM/qwIWY5j9X3MVOzGVjvLPflHQC0XpufO41lWrxr3JO2TNZPIoWZx+LUmuZJajQqWjaVH9
SabZJ5Uoi353tuNgdyv6eBtYkSqSPn6hmts4SpQYf8iojrcpAmzrJHxamxqBeZr1cCvrVh3pgMCk
NkVH75ulR45p7VrM8OAk8ToeY7xzr5rDj2CfWelqE+QgPIfZVCQGdyS802k6n7Y99Fz0TGNZur4a
LEXT5bYcxs4lOXfhRcJN0eqzmI/ThDQMFTrpV9xVcXOecCzIpqDdvfKzxmUHUKMptLzyJ4kaNs2u
gxboDbocjxMJ8Ypx3hNT/itzVXmHEnsfEwQeSoQtLNeBFWP3Q4wkpFk+NKFQMU3eu1ZUPQdPLfpY
gHnl+DVeW+ErhqwUE0CQBmWKUfZ8kbWjXcPh42rJG4R525FUqaCZbBA4XOq+i01s07/sR2YlNjxv
5HeXnBa1W9XFcc8ro1H4kF3Hk0j7hYM8JcDa0MN2PrGEfegqo4J2UOGQdJN/2IQpa2ZCbnsF+kFV
9MT4+mp847QRT425Z0zt7c3W32IRGNkOzgRIMvW4tqSDwkEzUP3gIrePmVSBEYAvRF1oOQf3vUSr
9AbOK9vL94siJ4q7Bn9NvnyP/Kv1aPHMc43lHbtG6UwS1tGvG131UIBsVsI6tx4J0tiTNtGvvaQr
DyWCM7hG1UEs9iEoWrTwn14coYG2souQvXtPmWRNJpHdNAvXgxmqJfCVuPY25jrO0jxR2iSXzhXZ
R1rgefkpkYXtA7cZhzGNxbNF4XatilgZcRIE0SS2kApJ+D+0I1EYua0d2ypk7ohdBaTCdHOE13qS
kQ+xNXPU79rJW3XXqKL9pfe4IVs0eSAeCNeVGdkfr0uTX8z9vDwUJk29k+JmhjBtbHd3I5NFKmyZ
AGaRXwKJPhDTzN/gAlpUUjBml2erimqNbrGddvkkCaFylQoSa4b6cZk5RFSBmWbjSN9WWQGz+tCP
R/itpil2wdAv2USX4q2CY3pqZYdg11nRgtw0YT432Ukdh4advgToIQFBC3JX4nB1lVDVERE0PuUc
3Vho2LKsgWMhssHzLBKkFHFs/3kpcTwtxnpDBE2sFnGBgjB3eBlmx+qILO8JdjPUYQ4qvpuTayW5
qlxWf4l10JHK5OfoBixDLLriqE3bWE65m8w0geQ0USeV9sm8YIonOR/nYB4jGIAeMMdJmvl01Mhy
BGeqU6SiMV9prts33K7oMACYEi79gVnskqiweqUEsOVDdIuOCDjXqq+hjC9S11NRMxp3Y4nzxuzp
6YRcYSgSZom8KARNnu9zkdOSyWHE4jhYehLOxx8qEme3SSKjI/1FuQvfMOOEyewPVj2E9IKGT73P
S+J/iohHuWuk7cKlr7BbNejIgTkB+W9nXNewB5kQIiVtefmvqijJCLh+ezbF862lXf5RPCQF6fmu
JInym+zjO5WCU0ZMjYqbdIxXa9h5ZL3EYlZYdDYmAuzfh2y35yr38XY42NfUFj35/l34mbdjOyoJ
02fUX3QFDIM6grZBhlHs90muYZFKRMa7L2KrmjmbeilaUVaHh8twnUmO0ehfgJQBQHrS+vQT9K3q
AYyd/EmbpZDUJG9pgq51wltoXRD5TkTSzcIx6kXDBOVmohdMHmA8h5NizpF19QKjbGNHavySr3jh
fV8ahO/ThA0fQoSY1gf/Xz2fr16JiM6RtVClfyp6XXCpQbXwrtOw6R7dkEmKdbgh/uAPGzyPRtVH
mnUg2vFNkxnMFPeci8+MJJGvlELa/EVYO/FmrmTRTeYy8Chcak/X/gvjQSKkYScbnqzCyiszRENf
sNkntAqxBN+Hto6OP/3fToRI3VDHcgpKBQqHKwqGLj0KaTLue8IStnQvIZdngX2cPK7EkxbjpT1T
y1WjXKkqK/D03x+SvdYkoB6tlngR1t0+UeB3l9Df3IgDGo2rqyaYnT1jun1skRlEATCxHjnP4zUD
WgrvEF9yK8M75p0V4izNEk1JENFrYSgBHi2MHY/KUQuTxddizRz6lajeRdc5VMmMt3eJsnrR4cj/
cpcnB4SENBIFbNn6sKid7wPub7JHv0rxNtx7TNZwE5svnuko5I6D1lcidf1k40YZ9aW4+3IHHZzq
malcWKU/3aZa/uS9g95D3ZdYU+S2U1qXdwsqIhI0+6r/zHwtDGsdgebytGdezwsySgI7DHT2r7Ki
3ZOrSuAO69jnFQZkIZx16EgXSW/uVvpRL+h54Lomg0EekcHKJdeTQDAv3gIb5N8m9wuuPYXSi4WT
yV0Tc7P5JafQDprhyPiJC2qxU9ACkB0BMl/Lju+PGnoxZghR8wkWLYtZv6Nj0uQKl3itgXG1jpRJ
5B3z0cKH4nwdvwH19ZwoahMIh37DXYyzDq9bubcHNycXkD1e21/8zl+ubEJdXZQ8FcbF6MMuh2OL
EzvtZUpfiqhbWxpv5K5cpdI+jGp93jWdnMiX8dSW2/jVyGq1xntYct61M+E8GlpNu9/lMumnQMit
1Iw0KQzlXIcrM8U1j7ZNKbTh9YrDvHXM6b4zNQYHKwVdS1ptyzp5cHT5umT1peUmSPo1FeznfWL6
+Uw+H38QrQPRpSAKGVnamnpQNJ0B4bKBv94ROv4fd3/S3Lg6X4BtyjVPfR/ljKF1gSHFaAJefKPy
/l4Sn8p0ZXeW5gJXotZ7DMBuPFGcVEwcaen7tirsXpjRlcML/PDiuYo2Mc2gN5vdnvecpy6b8odh
U0TenaTB8oCS0wsiUWOR1dncWObt2tFuJU7tIRPBoiRAUrFoaZWv7BltlG6c0XvCNfrU8pP1CjIZ
yQq3d/k0FlNOM9tb76Ua6wmvwZTFwP7xlVPG0YF60MfIGHtiUz9d48QQgKmR6GNdpOCsdypykwkO
2sE07eQ5lEMXWmaiIOZhbl/s2OXxOwKDhNviL2K7poVNHEPwUokPa0tC966i6hNicI8LJmwz5zcM
NtFimIhQPkAWHClabpqKTXOGENIAh7wyLWPC0SCpsKr1XW8WnmeqBbvDGAlnXRjK7vHD24Ra4nNZ
VBCUgvbyubgx8iuk09LkYhneYe0rHy+uULF1Zcsplg27QxQ3rGqO+VNixOnITc25dgsu/PXd50lT
0ZBBQTMToK3qM1RlG27b7YZ4bvzICM/3ol8ir5XGh+clGMdJBSErfKaAb30cVyYgck2O2dinctzX
tbkGdK1tXULdHBKMlrjiFUREjTDue03RJXY75YD5IbSiyPlJ2hGAgudvyoAptytLwEhSDMt3tVmT
+7AP7jVa1aKUXtfhFl/CN7KhMkMHFoJ9HdLNWzdqeUHAJQ+tl4jM1p7yOGpEXDSSBQB/g3HIe+lR
WpVB5xN1QKp5TzEimxsG/AGWE6i3c4IXyzJMxsCz+HZG+e/J/KLijk0H9jt1lSgYAUPLHfQk9zPK
SVDItu6kiVJELIeoIPmMG+ZrY5qvRweNKVEJH1IYhRrMqAtvYLSu8/awRx20rzY6CE9sW4YLECmf
mz0TUtE7DVPjS9hQOyuSMFSUuevk15/kSZLWNVSEBw9buSTL53uq0792fxOb4J0VPhZiKuHVW8g3
fSU8/x3wgH5X1qqEAVo2gsVcFryJUKPs/yZHB55kkJzQ8qeFmRAmYXx3XFbKhObp2Kv/xF/k20aV
BLrZ2imkyBAMI2QXByjy2JXnDO7MGPBeah6dvHEJVj7ZF5n0D+Yk8TrUplNrJrkWnlLNMj5GPdQi
Ids2XJxet1NXHT1qdapov82lGJAA3mZGBk8uDVC7qVnzxGcIB74cZEODcO89PPNhc9ip2x2Yg9eJ
OWys3fOtjvW5xyl1pdI9pKcQL4hBNjyOfb0Kn/zwqMheSWKvNR0g3qHTWDrB+Gfc7fmq9DIre7vA
QelXtL8Vr7v4E2R72LxVi0tFL0QP2y0wEGiFlGOJiuU1HOepD/BSdmVRpktrdqrkRN6geUGK0B3s
CQr34k3d2dWbZMd3Ea1RnQq6Lhd9z7CaTJsTlxVqdeCkjZhxZYvHuP/ma/jn1uwudOyozCU/RW/j
BN0pfjdNkeqDg2gjmnWNwTcIU/cUlI0/6RQAuSCO7cUdK+V0KndkzIOeiT8l/6CtShKhhcUA83Xh
3AXRA8c41GTeHyUwOWaRqwBhhw/oPB/xYkSrPInyepS2o40Yy9Ca5rStGxj1NeFDL8ULS5coZXva
E/UAO+Rx2W/LQczutZAQ9uhMXrXuyVedAbN87WA69nINXtxLOXTOy11nXAjMSgmSNngUxzKDLmvM
PPhfaoG/8y1ZSa3JOGBDEIwntZtrcBAk7SZcfb+J4/hK5nxu/HYRY38FW1vXtI9qYHWJCDOrBGUU
G36iymA79d/AvKq0uvzpCDLHv0d6pNCUtLILTNFCpe1SokYnRK9yFAOYI8rZ1vehpGngFafEHSd+
IefRpvtFYyg6ii2OYL4VTgqEQ5sjlqWHkSWG2uJga1VH+nhQk24MolvTqvlHhHw0Vf97wc4XcU/O
KVSOKJ/Ry19spFZ0Xlz76NsEFh4ynIMiAX10WETAXEbjB82pYH8n0NpyWG9RJ5gugGIOC7yx1TQ1
4VlhMcziwSMg/eki95FZEVD2NNYCl0i0Hh/jyGDvFQARYkpvfg6SysdaAfGEXGgAUt3caNqnvRJF
FNYRVpE8a4pjm2oExESrQWmPdp/K2muwm0ooXAFVhtJ0k2rMIwtKEc65gRRx1kXmqVjbRRPWkDg9
rm+EJlFcksw1AzuxoMqbu2onilAAvECazTt//TONCQqzJt70KsBKuz62EQ7/L0Wf0w1h0Z3bgzMG
Bck88/sxqtSxGy/moFP6gRAh3xDbPudzSedU9MO0DacguOq+IVEUq5Tm2b0DdrpcpO7XNuxuUEDw
bI9/EfpB75GSOt7RexkRtApH8fvmry4FwpaunS5EDS4Mn/Zmj3bCjsbuMzzfFIE7dfrfq+8Fa82G
rOZHc4zlzYF7vNwuSewwChmb9V6QMdJ2+sIcjmsx0lGuHSFDSXllZaF7Lu6Y3o+TCa34e84e+wLH
galZiXISN6xFi89f40ppLwCiRuw2Jhq47Fw67FtO4AGLLVWc+JFtqztItY5T6ccSW5GtVNeNbetJ
ZOTWTGLUeBlW/TGHULtf5CegHujabj8px3gaJpd5tf37Kvr0fZUiVkUnRH4eqZhQJWsWZ6N+YYT8
77lsCQkrWDwzfxscn0K/GXw45z/vKp4VSfczJD8LvK4U5xC4Czpr+lxZ2XqbVbs+V0/gPZwNijuK
r2c6xoDqYQsoKbheagZOcwf3jsKrTFTJ0Llguwrnn+IPuYtbRVwF7hi21is/0TdE8PREgXFgHCpz
80LVMm+DIO7wO7wkqliWwmof2KcHVOkl4UFy1J4gPvEvpUwYex5Vmw2r7FrzjLnVe6ke/gxMU73o
zNkuut+cPwPcU94dhk5ELsMnmiclRwHr0jxNnb+MrJV2YM6yaOWNUQ5Y3ftu3QGULlM5Z9Rj5y2Y
UUUoWjVSg+IiSIBNGOd3l83e2/+mrIx6zCrazxMrsxOuPcSeSDH5/YxeA6ZEEGzpAfmUAmsRbbTF
zCrvbHvfiDZ6bZDZSVhqfHofVWBJtZK517Zv330wgMCQd4/rqBxdPJiujDrrWcY5w7eJJHUMWrbf
iUVc1rngwUQhozhMqXes6VghBb8SDvgB3Sar6PNRrH6nM60jd3xPmHA/OQIipgpwBEehiXPL/l8U
YOGulv0k4ad7nlBLo20o04+51XfJqe3fMFuPLxAa9hm5c9jJIERKfejF/4mmhyUyI2ybjCIvMHr1
ZssmZ/HoDL9+R7OOovxj8A1Be6T2tvD8B1xW++HDvbBkgyevM0vbPv3DZm39F/z8x9C73cbgeNL2
USmUEu1imeVh/rGPxXCAuDlOKMnVKMi/YyG2OGJWUdJb6ZJg/lyNr0noYbO92zdVfbpTEWBji3oa
H7CO4pd4okMRXQwNxNr5HyDjccrKbJLvRYEB5vJMLEgvpt3H+CKP1kyfgBa/iH3UzaT9f8Z3Q+Ye
Z9FUbAvucYbsqftGDvoMLjHPtdQ6ND/GbgtvjZw1DaJWH7eRVj8vP8D3lhufeVwQ+bxSMLheCShT
Y7x5gtGB/ZpNvkUw4b9zNWXDHuSQRm2NJOHMAO8Ek1S34FdSob2N+NksF7X/6BbU6WpsXzLXlYdc
CGsiv2ZKgHRO01XCPmQsyyu6D2GliAzCkTXpY28HmGbUQ2PuF8xMC4gBEW55+xQeIwxGEt4jXOLf
x+XppTextgzyIpIdRCMiGpe8JUfjrWPnBr4JWkmZl71XsvE8/TFZwMRUN68pD5j8IMminVZ3N366
Dvhgp/8GIaQjuJWnOmxrA4dGsCCYCsbZxYwgSS3YK1T/m8PtCWEdi0WzoJdHTP8IJ0T749S9yswi
3GEoidw5GebgWjfj8ENwvyC5p7u2vOLJMUdOvMHINbMXBYBu3HhwFW6MSnCgEmaNB1aFgGqWBZFt
sQlY7Sg478rInqmlRLtvl7019OI5QmejvvQFtv7TAsa0EpDO7zRdX6ubZMD94Bn2qbaWnERQF3IR
dUfjOPRU7za1jE8OhUz4BVVsuTloa069O5iBQGFZ30os/hcadV6vAcoOGlWhBqXvNRkygRSL/m3V
Vu+VMjGCV2MHz3KOg+NfRQGswTG4qMZkhjpA1hXpWKP0Kl//UknI2TwoWv8c7rhWE01lGm2N4x/k
ecYdLfMDq/pOpdZxMAf2b2un9aJI04gKigsuUFfop9Ndg0E+e0AL7L6vm4rgsnqzMe8gxx1YQRAy
Dlt9UOFM8/9LCN+tqXN80H/CHzWStOnwWPUttj1X0pt8yis7kJk+rRyIaKlweX6YG/MNWMulht0H
AfR8JKGMy3fGKiYv1OyT5rXWWGvs7RbvS7q7OZvRwZaDLqXqvPh6pJjt8kDV53lvOzxnoXvOmnhu
TpMaHoLIPz9bLEatmmnP8n/kvkMHUpg5rM3Do/4/rtQxt4YI2IlZp9+k+CVMRWkFrJOhDjIH/U/W
gW5Nu84GDujyysAG/7vhksHikCyUmWxAwpedDTie8r54P5VesbIlV1OWhC6vpxTD5tbV2XDF81nX
fS3zAYj9RZjliPyYfjl7f0mQd5Pf3ZElsWopof1DiBd2ScJnaG0ZI/C4VsUHz2GBlPR+RAStbSHd
MqGRWX8mj6fOsyh83LaYiXbNFt+FdJlMCaV+rHmLMCWM6YLgtqIi0FhozjUK4UpBlwRU3GEYIjtV
MqxKv9umG7o9npFhaeMynI/BtnPv1vdDWQwSqBKbzdLkl1UkNJuPG5xT/LYPherWKgmGA91xxKoB
ysVCocoEPBVQsuRTkj2rG6ksvPB/rSClHkky5abseDiit9gzuE8wFDbrmhSk6tzclUTX/3OXvVuT
4+xX0hpX5k38hvwNJuQ1Lq0Y+hM39rylGx2FU7cD6jfHjbu8nwDWuv5m8pQcGCqRqBi2zddZB1nv
DHsm+nWaw2NVgZRj9jukWOx+05N1KElDTiAGt0PJfYVC71Pnt2Hg99W9dn8S3CXHfnhnuXc34q8Z
Gj17jsDCXmZV9IEgcOPUup18jY5n/KgKcC0qfqpxMAGp1mKjnpQx2hKi5aGETTGk6G7MYR4hEFjn
oOKbTYlYPiMpeNNhNSe85/AfF4c82B2tR8Oui1njMF0s8uJnTRUe+CaaBdvOxu9ianfB9qzNVSkS
+/+xTF97PbMqGko5C8+I5hA/sZO1hLPaR0TxECY20Q8fefV2t856IfxJgYk2c+xFN07qYhzwEgXl
plzMoh+eLK7bquErcBb5oVM0WEeRKIq3EWEaPfRXwqIf7n6L1gjNmiwB2maSlDAA6KxYYGT0BrRc
ajBaE+e653FV2mqIXE+kyJ79M1T1u90/WWqHosvCwhbdobuCvXlU2tEnMTcvAP2VhL6z6Q1YGS1A
ExSFBkxbHtgUKEXMS+hmj7Jm9l5bejy6ZtfMYvG1l+Qt1dg5QDOpN5r5cjgPeuw18ndWFKrqpiLL
chMxaFe6Mw1od5Hx3rkkk1Ouqv99p1m51WtpegYgheNZHls8FFaKnpmJB2RazNOkztO+4gHF6Nj0
PJTbCmSWO5mV8FJQDM6HAsnn1ahEsIUhQPGI9DqxuUR0yq9vkWzdOpDJN6b6lYeBf5kZz2V83WDS
EPs/RFmD/ewnHja95y2fRHo82j0X+bxHyvCYBXnOiYuHjkHiMvVTXU1uVTtjzVbj+vjStMzN+6v1
VADIshGETMhZ5WaVekAq0sfgTc7wCcwimivDl18irwz/9lHsG4crZgmmCB5aWkaFUIWcQ28U7f6k
9t0iGt/OSs2KyUcVDxrnSglRWfAluAMRop/FKFDMGXHYJVloL5Zh3V/h4OSf6R/PU3VH3IAoNQe/
/iasigl9YgFWViBbdbhk2Fqi0iK5ZJa9y2sKIFMGnoaJQvPdO+gMkjWav9Cl5E4R0Ztn5OuzN3vU
lbPd5VFL6naoBIsR9u/gbaefKzXtvw69YCciDM0zY3+C+eZg8H0c8OsjlMITO42PzD9IFM7p+b3F
tPBDoDmwgjmv5TapvwrKn3AORmr++JlTrJcUV2VTS9wXUIFjfrT9DILCaPJpW+rn8ffJXekCUnk7
6mVbhHUXF4XlIzgRruWv+gvmx+XRopfqEdC7DxwEgyDNdyL2wSrQn6ZYriHMeS6eFdg02Ss3hB21
g6HRk9olsnhhhHsfxb5ShzVELj2nRXePHMeG2m6BmzYsFnrfyjEMJYMq3EDqukZDhKhBHJpbVru9
j+E2z3ODfUq8ruhrBjPJTFAqJQ4UzDbGonI0jzOXDi2NRJK/EbABeI+PhSEXwzpK/V7B/WkRtYpk
2rs/4zQNtADc2m3XbS+uBxce9xJ41MeOvs4MEWoxtsWtZOJOAioeIwx1BXA/4T1j+F0B9oVl9swd
Ecn8ZtReAXy5gbg5oodqlKODGOktfxYgOv89yk7HUS5bOETiaoKFwyQiNRIP51OwynOy1HxxAJvv
GY7/zWQnL/5hEdsoTOCvpwI+fGz8N4uhT104egaGxm8VNTwcNgtr+QtGRlR9e/ZXlBHgg1DJulgR
tLofmwz9nTcK71HEqK9dMJvHXO/Gh3bM5Z1006hl9sUgS/dSdf0pWwpgM8M8Fni3eW+d2dUQmcgu
Cg62SHEd7szCHjqszRbnHzGb93M904usWahUP2hivWivG02vfJaDsJesjauCj+oZZW2o8Cw55DCE
u1OuWfNLB8wYUAAbjS+qvrZS8vBF8BEGUBJW9b8yCzteZ/ldkXFq1Ql+K+2xhbsvxAQWJ5PSQpwt
kLSOtj/oeGCbNpoEN1Fj+fMPaLgIudgr+ZfyV3G87SUUtu05I+T8yPs/1tbQGqX8qqIqPTc1UKO3
7AjSXL6sTyDRkdIv5h0fpIim5cGl8N6PsAhvhMu8cYpYuAhlbzwSXYzqn988Eeqxv3/nxulLy6Tg
48HIXXqrBNiS3h+MPkvktm/WE/84j/3/bQ8Y6iyaRa6NHqiTIHVXCj8yJtvcEOw90r0C1yl4MKvS
nUMlWPe6i6rHLi4zvxPBc8heCfZvVr6prbLpnC7Ru3ufpdPA8H1MJShaulaEEYsOsCQX847pyO2x
JlbY2QP8IppyKXlLXun1DegPIimm5qdHB6FW9ymgoWsbWA+VVBnkiOAGE17oddM7+WPHUQl7AA88
QGm2mcw/WwZt2kJVJ8BSWZc2GDByWU7wYEZJ2HwHDlWBJUPNdN6DqcS1PtY3CRJozy8xYjh4B9Wo
VTeOOE65TlXUfkAc0s9aTWhPRz93hcb2X3noz2sxVbetcgVhINCieHgBb7WtBxTBgu+NzDMKr1qP
Rk6bC40Ql5/r5rAIwUtgLZlBNLmuzQVR3vf5bvvkj6+O5pgT+zCwZCKfAzp5VJQ66nxxdHrmq7B7
1g/EkMLVbZP/cu+AX0B0MzCp3JJpNzmsTMPExtptl7ZzNMANef8sREQjH6sgybcMQOVv5vmqVs9h
qKDu5FbNKV5Pf/g14kHe8DvwSwQlgBOtdEkTxWYutWaG3L9JiGT5NdqTJHzCqAyxilBwJB8Ab7rl
3G1dYuNaemU1Qe3NPfrU1TRHBhjoz3xVSAjaUwQFrR53E929D+rQU4ETP0mpPa+znUMNlfSHWKYz
L/KUULiUFUhy1z0OfiSHtXFH1kthQAw4AFncP2/j5QYNpuunJIo7LeDjGEu9h9hEAzpd1f3vc/aX
It3KnfPHnOxFDCV0Z18YNZFmezDby1NRPHeY3YtrSxbc/hqN7Ri6KBrfqitwE6iYpxeAL2OuSdxW
ThfakPVrI01fHaZsHX5n82/GyPiiu5kkFlRVs8+MCpH7dujNf7acp63MgwWXfQlhFjr31ABK+B7n
kpgq0XkP59x9WXnmQwt5gCh7qgWaV5sCSCvDV2hh4FUhxIl0++VfG1Wvkp9IUbZgB/f0bHlcNwE5
idBZAsq67vrtBcVFYxqS9r5JShdp4IhLWQOjTcQfrQ/PQopKkGE3Kiwwb+rmb7AmsKtUZoUnpWEJ
nyTob7UTvwxllMx6js9vd7Knr5QW/wmj6llZFj7dcTuRWfHKT5osO8BrXT5vSAFwpgFvFFrbG6oU
ha/IrE19iFaEGsjZ/l0+/BJisobHk2Rz18UrGEpMQgqYwJzSt3YNj/6GlL+EU0SQ6J1b0yMzqMhk
Ki+HUEblC4c1kHpXznOzDWPw6lWpowAB+rVw7M+eTjuuhNxcLA1TOHpYG7/M+vGl6ZIg81flaCbs
Ok/GE/yRx6m9Zkrx05XQIFZg5H0RQ91iZBlPiSYC2+0fEtx76VMOx4Jhq637OcYwTXa3EfBtHLfv
Ov5Pwe/h/BBS8t4o+i5GTVgwOmxOPzp5x0zyikXGoPIb+qjVCUOSGMHqIhq7frHrnY78bKzwkrkl
FwY1RlFd7U0szgkFHTvjlp/2D7Zc6AMq1br5q+vfljvfpZRFr5pkFF1ltwgj64AD+w89zzBrInoK
ErX30GRM/5bQLqkVPOKs/IN3odSUYWE3LnSA2EFXuoOUmGz5rK9WoVVZAeJHHt0nRS/94GojO6Zz
Dxs6iybKoIlxfFypwduhegIf+KOoquAj69CTtoj2pnU3C/FFlOTOUCb6j0DveBtOLevYtpw6km/W
lqYdOgObl3d6+et1O1WiEMnbyTsHQ8oBUipKSjr64vSNkQkKuqmPkOSlmIaUO0vFT9PA5DtqPlbX
1359inrLLDyW85QT4UCEILtSGZ4U/TSHL43EsT2d+M8yrqdd4uuNiRBd8BUWvrsJTghGmu8DYaxD
ODrMWpL9sHCdBBLX9Jj8pEAdqvJFMcwKVr1ltd1ZtRieFuZItvmrzpGeQkKtP05CKwbLgIU3xSkv
Xv3jK3+b8FbNj7W2W5hNGMl7K3mSQ/0az/9fwXqksKcuAqxjK96xvZGCrViCsbT9YW6SAay3/lOT
eStfuejkqv1jSXCz3il2jLwNFSh6FkYe6THBn3DIE/aJuSjOeXv5MzYk030lZ902KTrgVI7kr0cT
vA4N5OMBGW70gZ6eK7wHlRr3YKscXEWGY1zAcJZmB5uGKXFA2zKkR9F+VXWkcfElK7uBilg15GxR
rnIODoGgJSeqJaJ6unL0tK/Z/qsjfDipbzkb/x9ABonXMB7hJPjTidUiRxUB+Zkmml1Wt9nu2/xG
7X5MGLVGYGB/ix8DgAUr4qXYGoPJmTUIaRsri0iq6L/UPSD2zGBZOH/4fD53zcdWusr1fsw3wwdX
sihec1oRJIpQ4LoAlYvl44KIjd1+otTQeZdg75fO+0NYbwZh9EOXJjan7XYxD8LHkCRgGk2/jaC6
vmEwdYK8a6dpo9iwVf8naw7sgmTIKn46ERwy/aoRWKZop/L0tyRsCg2r16iJkqm8rPXLg7CWlos2
Va/yVDYjHalgA28kgzEThtqNG+XooeO0waCA34KVvy3b7R6e9iV21eoNFj+E+9Uc4HpoqhSu/Fn2
QzTZF2EeEGsZJ+KQooY6lq6GLzH15pjkPVROvjzGEZ0jLXO1rooBlwN7dQSLgVh+alR5rqguYeSp
a/1XQH0vRCrfF3blcbTwwx9X08y3PAQEC0//tvtf45ipH028e37uIsOHH6fr3qrUULtOVDGlYx5f
55rVcUN9febPy++iw7+819fxElyZ0p1JR0R2EsEB/QOd3ed67v4JPSld6CkqZnOcPQQpRA2t1qI3
f79QKcx7GVXx4UnR7HKt8lCsAGjlpGHMfNeFdYTl+lyT1vEPxZ+AoEaMkLN0DY97zyyeYBOPjRkX
MDMLADU3gGY0BNOWblPfQe3/BIrwIS4atNVFax+5UZXQ3L7nMDutFDQl6DUsPJ+fEM8FItdFLqC9
+dmqak+Z/P7tBgTLFRow04UdtoBfZc++S11K78w+/B6m0mzEhUkGideHLs/0JgW46Z5ezAee140U
PbhecKNEMqSM8T5h+jmXT70x2vjJLrDWUWCDVV3a6jcm4YbPM7HG6ooxOiD/FUgULze4JbuB3JgP
KfDugW7Gqlr4Gh+JfjBpCCWL9Ll9Pmw3F4016M2JuIbY/AQI6WsomAyWRdQ/Nr/sXYHpAsL1TFxP
UQoqgFmtayZKPC2O8Tk1KWd729CYi8dHKpZ0jfcAa5biiY79w88anEG4mmH/iTtgiU1gw+TC9QGS
xKf30pmLfhPAOMQtu+ZfN6dmcobEA43zbXpOk2gh26hYcSyU7owdca9Pn9UQ64lktyA0lYRCUN2q
80lMlVP5RxM4KFgpod+Rcl9fqrZP60I9F7vWotvEb4nZwbLiGObFQ8DpIcLupGNg9KTynZGglN8F
5mUocXUCsfbKrchJ1/653kVJH40tK62nX/ICi4HqD0vrZLWlKGAFTxmhNdxI5kMD8iuC5WmED/b0
fxRQQTfiOaNwZxkE48m3AbngTnYudtwr51ql03OoLcRBH9oR7nCtm76aU5geltL0DVrgfidhP4kP
nY3EFc542nVPbEpRHbfwbDkGAbMpZtNk/OJv4j/dmwBDD8WBmkYzv4JwmKHTh6kQg8QXSBejTjTu
FO1vN+b+pTggOC2UVkUKeBSs5atppAtc9r2xbXT+zaP5UhI4olRJ1iPiHkzV4fWrMqQ3uzG3LL9D
QbLEZjPyu7ywKqL/bX7IDXlb8Sh4/tOJGZL0r4LileGBktVPRUvQ+VGQlsMB4Hy2ywGPL6jiOvJu
gfygnG5mEnyHfSV4qACl7fnUJqZFd1TN0DAST0mVDvgWa6iu2Y7w18tQLt5z+RLUSDY0qb0mEG1a
I+O+GCFUtorC/uB+4VNjpT3rkqZjx5aE6n6X4hjRziJiMX/37v/RlfpHJphvwv9WhLp7Sl9pfq0l
PXY5ApO6SOSu9oUn9Gmxpo5YcTW1HdvqK1iDiVI8s8xVkQAoBYhDJexXnE2Eb9hGabevY/+kazqx
p9Fw7sOvdHcxo+NZloy8FSe3Z0Yc676bcQ6GwfI6WofI5jyGoLM4sNxrCUJopV9IM1ebC3qCf/4n
wOALx7Qsrc3e64FcqxudYUNUlf8QjTx+F7bcK5muL3KgfIfkRo+dkBn+K1NkPVMZNydN2hPC18xm
zUT9KOcMC1D6OeIAr/4GFUxTraLhZMjwgSUVtSv9vRTOKBYlG8GRZwOzEfF+9uPlDa86jkLuHkV8
qMMCtxoq7vSjZGeJspS4IqavQe0nfZ1sEgA3hdh5a2qhWqNUmCvWqy6dK9ZJb1q8btStrXUzSQHx
BBGpnrwkmTlNkHnqFdnVJ272W5iHp5A6TEPbUMEEbxdT7HY8bKVQHgGEJ91zJ7q2xDeD2fa87tD3
8Pb55c7qwuESlb12B7f7qy3lZpNHKNh++md8NbVEdrqHgC/oo7fk/9hFKOmBPs1bML1+pOMRiHAJ
2/CFB4QC+8TzWEBE3z3WrH094C/B4eC2hJeZ/R76Q5EkzkZh2DTnnctk202jDK2rOHHHG7hC63uJ
+i4DbL5yGjcQUR6crYEC81aAXSlrEI84u/TPJ0ovUvbgGqPLef5hXQrQSeksF937P8PQWIjq3zr0
MGp/jRRZlqceKLodpeAH0gtqzVUa6ZosiYWLL+p8KjG9Q5SUNYkrkwDT+iV29TMHu3Qs7KRPKn2S
/aKmjax4pK0w0DMMPwXUT67+Bb3IzBsMcjO2g2tqZHvOJKJrdilrfL3/qLhAaYD0KLGCqu1QXEBS
5zHrgURv1XL5jK3VJagG7tJ8+edWnAmISD5iwmM61siIvVPwdLacidKRtgWy1HQGGIl0O6VaCqFW
fPGW+t7ze9hmmOacdD+rmWq6b8nRk4WHCCxDd7Tefe0e3IZB9XIWDIIM7pvy8aLPeUnt7I5GQq2U
fX70qLrtHR6UiQeTqjCNtaqH9v0CfLBENHnJJFh5vCtbFF1JHt4PWQz7tDkTZ0z5t5zxSiPVTOMi
Pg8DwsKyu8NrNfmMek9mJyc177uCCcHlST7vg+dYcrUQRkOj17cUAzQDcA6EbrT5gxWMBkQxZ9Wf
ufdi9IqlLroGamiMeIVhJyhaLLETDr5zsANaGp3YuZnODesiWqMTxDFjTPyrZGs/RX9H0M/DuzfT
ZMOcjHOp8q2EsYMGSiKRogcxYsvRjkAdz9ezO+iR+OJhfT8vSQLiIkY3Mo9rOvZWhTLfgAz9HY7f
J18RrYqck39i7McHq2MrHs7Nbma4zbagYY64DfeyNcMZ12RNBVuO/mgtQD2aZDA78fEOMBRyCH1l
g+OH0aAdUnuC4N4QY3lI5lu+6CzHBT1vyDkLGGv0xAGA6sVci8cw0md9qFwNfIqSLKS6oGCofhmn
Du3+AGFRJADwj3QMojWf14C2XCeLG8VPIgFEZLs269saNUPMOwYZC2XxuOumXU5a2y0xhEorbOOf
rHyHU4zPRqt0H7u9ezRS26TieiubvhRswfZpcRxUZyfwQvg1WvOlFF8bKmUJ1iU5zdv+lpNr7QYe
KCLLDZB0GgjVIXgQCq5Y1O1TNklGrowoua8pxMatEZV8h7yFQuBqT3xGOBSD+i2u6HPig1rw9QHQ
aOW1YUtZ8F290ECg3P/MywCBwFo7cnYAPNSYuUQR80H8p3b17GC6cjiL4kP4EFziy0i+OG8GnA2Z
+tGXqDR726ecxb1hijp2nlN5WbXBA4Br5gLIQNk5JoUANYyI0TFKajUN8anL0YJDkXQPyeP7JO7Z
c+JhQrh/ookbm3QPXmIK896VS31NnUvmPl6KYtYMy9nA4Nd6nnerXHgkpizHTZgkCZ5ToOuzzb5O
jZsYLaU9mtVvKKaeJZ7YO6tsiGsGfDGcfj5Hkfzw3lbZ5L0+A/sf1APCLpmwtjL4qhlNfR1kwK4h
Zx4lRQ0TqDWr7QMyLeNTXWdmugScgks0bjhX8rp4FWYBjXmhJFaf08kQHkW1OFQve0D8wukxlEWu
kW5N3V8lN9DMReJDhR/pgYpsj8HrcPRD6EVK0OeLjqv3kVRHuEr4QDCcFVtzTgqVfnbpeiTAVNla
5SxFSlQSewY1krLnnInkP6BcoSiK4+O6toFPxGIQOkqeagHr2QCc133ATKpHYGh8Cj/7ZgmkPQ1q
VMYQCFTzyZRyhA50mD/wRLm8vsTBeuLlmg2BIsFlb5mCCY1K46nu4/nIWDoUxnPOrSCna0H3Oyvf
+9W/D0up/RdjfcCa3iceO6N1ZWua5uWuIbmwtxL8p81FaUqRJ7MrhmNwHnhCOYhT9YS3vyhFRWdo
Ht0Hq0b2flppUyAv2wpVgyO7Pn2n6tOdUjw7i7NXXVfgE7PnhumF3d8jbT0any/wfSsWvGWutysy
zRNa3v2PthUiey8Gs73n+Oww7VWqe2cl5PFnHXb9TpI86jDJlBiBJwzU0clHYxn2tOpkwOoiDFuV
WvVhYTGDK79CKEXVxgpC+Uxhe+P0cwcHr0z+/qrtGcGE1+qhhoC2QO/tkLpic2yZj33ExzZeaeLm
2pem0D22P4Nzj4Mb+9oGqQxa0jifMN7IMa+qdLV5PuSfpV7QzWfLOClGon22vtWXt+Ym2SKQBtd5
GlfLEZHwRhVeP2RDCG89M36MCinjBJvwb7E9xXNiBmQdJ+nZWI5R3tIEOV5+mjGcOIPDw4W5qIjl
Ee76pE979I4j5vJadDPT1N7tCOA4FnDoNUFUpi8MFq5j+O9UlHZENo2XRWh4SIAqoauMlJtFe6dB
Z8l1m/aUpjr+//yxGM4dTUCYOcwPGG4U+r+lziVQzKXp+cmfJXR1nsRrR5Lf5t8tSNgQfb/aF+86
hlbXzih2PFujf4g9DBvpS0pUufACCq6q/L7iUZyKBJ1UYTMJ5XGwHiJei+22JCa34MdcfbC1DSa1
fhABDCiqKNia2fnCsfoB1ch4etH9SVes/QhaZ4HzrDmE44kvDz6ChfySLUnF5jzUZSoxw25k+L5I
p70eIRYP14S0S/CtJJqPSEURen3WEvqyJqLeXw/gFYhvqou+U1bDZjpDG2gj5MY9W2OS4MYfIjra
WuSCFPYo8+BwliTtmPgxst2YearOn75K3h17dNItsDKa4fmdvRQB4jpladikxQ3+nt1QKYG9U6LM
HSs6JO8yeFmCSKtEzyZaiCebFd+PCF0pfo9WURqHlHT6pf+A/uWjsDuDPyxilRB3jm6OCy+kG1ef
N1UxZWj4f9PJwSvd5wq3QTBHSfbVM5HUqdsNITlBfZkcHejcMgPRnehzgAKnSlrGzKrcXNn2Q0vr
kSCs2ALY7liprjTxXxYa92y/CRVcMpvEXnpaotNHhSDvIqbZeYldDXObmzgLNXTiULVcVp1avei9
ftHy5idj0hSVHayJbSCRTMvdQmsgBW11Idl6OrxjqYFCcn0WGFup04yqtgMzVPXhdHxZkNPYGWSR
S359zPbiQ1KX1zwW3Oh6F+OI6B1eIGWBDGYNqyxVeqY33AVvdAvHicCpfBXVET7F9aDBsQUSMLYH
ijaPTdnouo5sH+VmrAC5HPyZ3NLU7ePLQfbM5D5IKnh36N/gtCrQ1dybAftTgqicCZuEfPh9pr+Z
YxnP4DZ5d9KGbVTNrPw7oQ1Wi6yFmqhT9Z819DmdNrMShbag77rSdB2PgmW42d9FB+yb763UBkPc
p+ssRT74gj3RQjwJ/BDOZVlXI7+WNGp3CkV7jpInpniyYhhUTDnS2whIGyZ72xUGowuNs1VAXyEi
PGdm97Ry/BSaMrRCs6ClUexRJgN+Hu0PYdfCntK1GydwnX/WuSdLRDBWSLbJSac/hYj1xCWOb/tX
4JLFlGNFE5fhckWhanvSX/DZ2A0OAciLfh3CYnSOWvHffXtkGzgSrXQ4HjfBECfjBNLQIX9r3uPq
OU/f8poo+Y8ujmsKqHWQc1TUZzFJBDMINjjBdmm0fnfQqtqQBUS2ykqrMmwdK/0pqksIj9BNWnE/
V4g1JiK5mQapuUm765E7za4gIVegGKne99xrdF5a6srNr7V7ufgeTwpU8Ud/NhHB765EpympST8P
Aa+EDqsZ+eFPMGhEteXJS8U85pTjQX1/MEH2Fm9XY1EKwlmr47BBRc+yT7NUEOiEL+OXeAQyOCTA
f8071WVvfX/nJfpXcyxnfIdx9ehnj1JW6nVK1LLBgE7WP883AEoRMC/NpwZwos1ooXA18nJqOyNO
IvHKoCAD5K3PXxCnZdZXL4mYpzb7yrJoqczO+NRtDB8m3YgW5wsi3OGzWYnUEb5TuPQdPFpeRCZW
1msfYAM2zIG95WOahi0Ukq1El8AhXbNXqKv/9YFibIuIAC+AAAtvZ/wNoq9PW++6qQS+CCt/S3Eq
MrH+fKwQlZ74ee3KnzD541a3bWWGM3igX26ziq07gx3u0TWI+nEEEXbUMu1ZINr+wybrstGxizlw
FA05FN76MWtBW/MwdaCCsFEKBeu8doWs/eTfMX/w4deY3De4CmRGozmX1jixvucTT51PuWfbjMZX
nK12PzfXpIU/mw3r4+lx7Sm/UWbI6mMxOCz6zgMcy2bM9GDl6CJW6fzXkVQZpKB8y055MWtfmdd5
4hcltmR9g2o74DrElKGIObuDXZ8Dwgr7PjYnIAstWVQbI4E8u3ZK1/LQm4vD8i2HK7MtM8GrDjg4
oBsL+3c3zWPyW5l/NipvQE0w6Dx5H+XVjQe5wJB7EkzT/3kSreLKLj76utHnTGJsTiXzVvE5a+Eo
pCsI1wVh/EwXQEBpScyPup5YEnhLcra+ptKHj1/CgXb5ooUCo9ZB1vljF+F2L5APDHHKdq3A8ArK
el1jtQSOh+GN+EEJL67F8KVjjJwUZkyAA7QzJz/VhLcG/rZmLzaaDvfWha2t4HFDXj+fEFZkWwUU
KQTMXVvpdv6BwZmT6Auy1GsMaz1ny5dSOK3EE+RimnqXn8mkHlI4gQkcVMSXMx3fdgz5IUnYoV0s
iz1XuWrRJK0Pty3CdaP8a3owo6fsTIZYZCIszMGz8BVOnN77bn8tBqxCfii8xH+qsqF0CxkXEQOm
cKTP2HFsJWQpKepZbenWwBhd9w6WBVwubgy4z61idhWhvC0qhlyn7XKCOWd6LzAYBqz6WxWj4hwL
PsxUSGYW51yV1wVebtjPGtDQSZYntTkoXwSfBve8WiKtD4utaM+hloB5afQjYF1ufbPXt5me0gj0
H7DDwbLK5BYlO7IlqVD514zHpc3C/raBiAG3ShnwvgfCcA1xxHlzzxbmPS+70fd8xT+fW3yaP2T/
M0HLKRVu0e6SkO1+TUTYG/MAKAHO9jcLaHOcYmM7CEMwE04nYw1gqMf6F+RENiO+eT5ZWnQaRZVt
J0il55TulgqcObo++jgvStfeIxEBTK4M3rG61g/YZOZ7Uuu7ANQgw94q5nqR2fpjufRUQNqTRtdO
I4BFjVtvbAfX+CtrVJdBvAfpRtwcF+YmAoyZY07DvBr1I75tSMjcKCJevyoLJO+aHGXSJQ1LzZbD
1OGepjL+3yKhciaxwNCzWVkN3MJAV9OfKc5eTaGsvZRBxwATemMYqtWC7DxySEnbFenRCoDtaTyQ
Ll5OzIQfB8XSSuOXjkCg0ZpECbvF2Ugm8QqfVTUZzBncGKuYMP0dhZeX0Q64Vadr62iZLUb+JdNe
yjv8qPN6OoG07r+fzlA7Q5/c/f666klzW7MWQ8u7FHE6eIvSZtrwOn4UONEJubLRcjNfKAU7TXr1
hQP/rt0yGCZeuNquFeXoliewNJogIeWoU/+8HE1JaKPryup0A3sjuYGO2LdQ3HjBG0yg1DWNYCJa
FX30HZFFtYmGL3BNxB1TGBDQcOfFeJN3U7R2gKmo68XKFSkda7EHiqiNgQO24aG6zsjQ1OUNm5wV
W/m5WnAQ6qRZbdyiRvbOacfoQtlSJzMyI+Ag7a6M3JCJj/zVUIyr2QD9hzbrBMGS+ADjRdj3KL4K
bwCZjMIyfEG97M+hsOPjYOJimTZr3N7zaD4buq7ILxaDrLTEHqktFeHK+R6vM8pikMojv2W/FuMx
6NjGjrYrNj8A6jQFA0tTxWVReyhdb2mOykOjksi5rhZ1ozwlvXZ80fHITJOLkR5NJ76fjkfwB6KE
RXdbtppbbCcesoIn4WtGhWDrnvENae1ifc6Y6XIXgHmID9mwsQRvR+1+zgjO7KFGgF0UfnZTmpXe
aZKH5elTph8RO+nMhkMit181nSYqMRk73A+/O+F6q0YU1SdriUr9BFSkCM0tHrDVUZwPjD7ImkSc
9UhnvIgKGg/Qx6afGvhuiCVd7R+o8FDyBJGtX9W39vagmdjWcnXEIorCC3ON4kSQChkE/wafQMAS
Bkpzf3Mep3ItcjZ4hVt9MZIyrBl6aVY9YqOMtNADiaDR/EghU33GHybUbZFT2dkzHcz8yO+9ZLh6
abihUwL5bRBiVFrmkZm/Wxfqa+Kd3WL2kAX4lJa+M5CP0W1YhJJY0G/mTaqkl43R5785uRqcgKNK
bSpUKi8T2N3FAamSK4aBK5pYl/nG8LvapmCmPJmfxhDoN3jwjyqSc/gDc5tZXmOf1M91UFIHB864
NpfxbQ95UmUfBYF0Awyd6s/TNP8L83zjJH+9hjZ2E8YCzwNvdZjlvsc4xULDd0ZSBvHikX/eV5KQ
1OpfpyjFf1FL+9k7wmGkHmz3Yzyx/QBmBMPJlLYQCXTxI1+7cjptHlmk7OAn+5yNP1udSzWiGdrL
rhyU0XTuEkwCIrJ1JHeoEcPfEYYv5vzVEpgGhC8DUlUxC0j7dw6rb0c+M6fVNUkNpsjNGKwwuM0x
rLSjNlLOrVoZ5h5EufJT7zEZraef/9Dxr++s58FHefRphtK84eSZS60Li56HcABHh+ngEGwh+DrA
7ymBpFxShrF/2PAAeKZpDet4VHxbpSAC23RGkHwslKCiUAqZdWQAhP4QQo+mEEhojISOyvc2I2bs
o0Do8MsDY6FrxHkkbgtD3tUUprDfdgv0nqlFPx1Oe5TRdjgI9K800ihMFRbXh7BcsqVFKoxscrlW
mnp+MrsT59tHR9rZjx1cjxFvUYopPbPTsoJiFM2KtfVfX+N/jbfyVcgqy/Z16+wKHLFT+75QSUGv
ro5wYJJGevohPtD86S/6cN/rUYnAkl+3iR8idLIQKHhoIWydcWN5SOZvuvEbfz0/1viy4gXRx0HF
cX8SxGxfAErXpV1LyuWZQgwzL+GXCg9Pa2Pa6BrbkDir3BLJ2XD2vfshFvc2gJaiHA9B2ck1F/Zx
pINgucK7eorhjlSMEU1PImcD9tAF80+fbCBOUTF86j2yShw3NLVYTASVfw5Hs24zAabze2pSdKlA
S/cGmAYD8DZv8tSyH+hwSU0aAiE3D2a+3x/GbDxcB5XnpBt/3aZ9yLiFrbyqvEj1kSp2JKvUmkYQ
YwuLwg7VPQg7g0jSpxdIbnE72Cet0L28U5P+rxVJCxXHw0mlhONJrIfBOw4f8YmI/rLX8+CJlJnV
IfVr/XN77XV2R6lbx8VkkAFukIcL26QEXUQijAhoaCL24PRNQIww3iLepSy4TiLDp/wmtRsL2hNT
e7Ax3/F0lWSbzw4U+lovmWcoMF5WVmXDvkjYLw3LFlVyktTcmRkfU330TKXiEQYKEEq83T23krjy
3ygvw4mO5x0g+vcJWOf8p9biMcd4rVaXOggGv/aYRVcWNylOGcBu9k7ZJiWHbYojDqbvGaPCHVIj
tz9/UPpl/Yu1XBbl2EFLsNeG3N56bhVCbaYCeP0B9t8EJyCB2UimYAdmYXEOC0HhKKdhGxDWfb8B
/7N8Byvlkx2P9NWZ8RiMBnC/xY6Z9qoeZ2ICmhnXSLYjKA8BwwC15l864fK7j4rnB0opSk50poFz
GrRGtJtDoOC8/j19utS9EnunnOPe18OsBPeslkBXJJamB4pvvVPwO8P2G+YGCpc5xGcIFOYOqtMP
P5Yi/99gBdKk1CVGxP65zGqKCuZNoos/Tqyc8VqkLC30HFDs55m7zmYSROSmAFqDk69q6mLq820F
/m0UWL2975HvxFKojGxGb1REuirROKaNZfJO4gMVU1N8lIC+fR9FRp8i0pcl95spjd8essRXPOSJ
4xmTGXeew5OC3C/xROWD38vetjcqtyEoTNS8wRrgg7CQv1beaZ1SAwJasEt80Er0sphUxaTi/rUb
7OWAI9lOZLxQpCHZXAd/FeQ/Et4r2oAYbqazEuIm0QDLt0QvckROGwn38UiECyVmdr/LQMQp3ZdK
Op/MTwpkZOr9YdxqRisLv0AZCUZNNuWJEi0ajTWI2muINYJrY03AhefhvZSfhUIxoijAgryPdYUi
/sT0l77/bKXL1JtWrwAJkh3s0VS/Ri0ZRQYD2MBgektNU+l1+1/VTU+Z9AD2g/oAEalh3kElcUQb
5VbYOicKx6rohet3dmeFBmsz3QX53ANm6FqKg/B3S9z35apt3kbov59fY1y/s3qhjcAq+XuLOReX
9ZHg8cUXmedKjkejNTUrV4OYSju8Yh/hMXzf88xauco92/hL1nODXmwyPi4wDQLO14RCMmjjDs8z
GFTLIsoWz34wE0epEVbDNY2hurIWj1ThA+jF2uo5njhy1fUIAnw0TFC19n/QTjgQZMCcU7oo/VYB
wJWn1FU1tSOQXtzE5ULj4YELn+O5LInBH6L0QGHqP8gYRA3tZ9Jmotz6bES1i0XTroezgSXENVDS
9jVMgkzpj+KTBnxtE6q1PnHyopkQipyHrNgzU/EYya7Mhyhh0MZG9phRpAg8iHSYPSu38egXwaOF
os9IiC0/pVPbPCfwISkpgDCFNXuF3/Lm8hG/2IJOq5+3lJmK54yRwLCASyH3Q+cP6xz17aNky3Hd
Z0otPJxfySdCr2eVZ/d+e12J0EzXbOknhqCjXi38xmB1UpCzztB/AJ8x+2EXTe1jeskl90BmCInQ
obfPv8f2qivseuu0CaL3pl+3tKYFOur/pw2b6EidblMf+wf80whjWKAmArxQPLG/zmWOsmg6jIRl
TKROuy4tKX5aZ9JoctCKX7UJL7qe8oKUw3IVHsE8o60Br9NjNLIJytbF7pGn9Cif6x/33CpZoa1c
1WccnzvyrTDK21c6x259JV2rTjrd3Bln+qFQx0VEtiY3ORZUugmPRmU1OBPQcQE2dKdUJmWEuKmi
mLuLiqrEu7pwGaq6B2fDJ7xsCO1Idx6emt0jYQMYpHxmMEXRvIQZyI5kg2a3nuz4KaKao+ndt+TY
JkH+vRUO9n7gXxTPtmHSu308pHvH528J0MEsvCCU3bTeXmUAEH7uVsOMgUeeqAq7SPWVfsAqnZh4
JgtriXU9M3cxHeHTOeNjTdH81eX5mHMuBuTzVdVjbq7EJOQazWMRRAzvTm6Ib/VF7ZQPp4L+FZeU
fMZYPfF9llUXU50lqtJm+W1hoYrnRkiYQWTWhwTcOve33WtuT5SOYNySwNpcG9WvwGIlJJu3D7/G
kAvWkNVffFhkvIlymz1cEKSy1bbOURoybsMxH9V8FWkz2J+ct2pIEJtML/Z5tH9U/KJ223PnMV+g
4At5RqGBQO1ikHC/KIdw25PNHOXpTXPbQlfLGpHqT1LRAp/hQts6I5dBuwZ6o5+tdKWU0tGinwhT
BbGl1tfxL6XbgMxKVn68tdp1rTOr14Nm+qEYkPL1pZflDZN1iqVbk4eNT6wGj0U+DlHuBaKK5vLs
A4BjX3JaXsa2NR2YRcRuod5RAYlj6RtxkGRTqki99deY7QanbHTZ1jPIg7cNE7kTz02QsizI8nLk
KSBusMH6UGk946b+mGZcWyl0cAd3Yeju/qaheBe0+/vfFMcGChUx4WE5EHQ+EPyjxyaL0s0zgywj
GXGeZX6JeRU9pTnlnnvCq0O8flkDNk3+tn3fq1HMqg9hhugWSVxAlaVOkdCUvTpo5eQ+EfIBLXDn
7pWpKkh02vCrkZcMs0Es4yBZtNaErP7E6Vn0m2HL3SYhY1Pj2WGEI1O2mh9Q3sqz3mY+Ldv5l9J2
aYZko8YA3sVFG4RR+yceBGG2o7C0g62PJrogum6S91vJ42KPwBN/nMKDfbfVkNvaV//6KBaNV+L6
mUDgMbCtF1ORMp3VRwPB5WJBlZR8+petTVjkEu1woor4b6735q3N1aogNLDYtEs9DQvwQcQ1S8oN
JkT0c4qq5BVzAI3P43sLw6prccNHm8rSIIPzf0c51/8AAz3BlI2E3OIDB3vFgQbZkd99hAl/oWmx
mUHxKPzjUpp/KiNJqj4mVmlZOl41R1IrBlainHyz+7VnwmMFBuTeLH/RHHYXEtfZ79r8+C2x34xR
kfeKTbyj6ww2EVL3AguIfwKA1KG0HtI2fjfLdBGkmcEVdBzEaJGsJWczrB74g1cm9YwUOw/gn+kU
Y0EVO99+SaCFmHhdeXTeEwo2iUAMU2EWR+WmL2BFYfLsh/qqUGO9OKhv2/DjmcxceWC4dApuZ7Cc
WoRSZi79rV/bhoUeHLk7dSY+xUfxjciMatuVn1ArDYMym69AAflY7YMnWD4lP6sb7LOEIbwgdphy
gxXoWedwA5lQCljkLJIOSMB/I3h+stDHLg0L8lweaXHdShmlwn/1rh9wijhMUOMtjpEez8UNLJAU
fBfYaaSBYhPJllbTOxeF3mccCG/UGuWod1Ifbq9ELWSjZqs3lq5luRv9VX/UP4meuEF1qg72D07h
gGkOR8IM1Hv3jRVfLOUKKNRbzo1f7Fhr+J0mrfHj1vAPPwhwweAvzBm8iZyJVH7M1uADTP8bF8k3
JJG5CuF+HPNg4LTmYYVZgOh/QhmKiqbKazWLnU3IFLqVG8MTsvNyqaw0fDJrHi3Uv9RX4TzDtI2N
lA+nft5kTvX/LvfXsgT8GymTajQt6YiZDtJORlYIMXPj9jMn2Xd9Jw9m75IhYe4N6hCCPMHp0BNC
/yC/m4xrI3S/QbQLuJ9+8gK6B/JmGIZAFEIVLBo4m7Sew0ChRDdO6dEn4vZ/wSex/XUbDDD5yeDe
tmKsTHAvO9bKmboU2NRK/0LAHe7sHYsBXZf2dyiMV+vs94cgvSi2dx7HQJqCPRA2whqCZKJkaClH
PmkZE29aVlUrcNZ/wVtrzNYCLRV+nhOfy2iBwfRWq2jViunen5U/IYkLXJ/c+CirN+azrRBIgMUi
Nq7OXDwpMe2EFWlMCr8iGOgBeA/r44Fp6IaZpcWpxFZRLRIZbZObMBDH/hQpUiDcy/Pf8T71sChm
s1V6FRNJLcCpi9xvuLjSs/LCQkCzpUmecT9TDnig7hnquiYnZJODjq7BQUBZVsLCwfoe+neNxkDk
afBvTKpmoscUGrzSU6Zhtd1FmmDIE5n33LvvVAG2sa9Gb4ifzLzzv7k9I8f5i2qk7jBIUDUQBMwx
ozfZyRJf3SR4bH4gSs0XhTFlD9EAM8ZzeeH2+usexVd9qPyTOPY8FURy10kSN79Uo5dyiSA1BuOY
YPB4QtfV5gfg2BuMQ+N94sF7VcifAB5CB/HzFapiV34dY6ACkbttHxNPOpu7gG2EarAgp1HVko4J
5Xqm0cBoNX+DNL82bmFeZIIpGf32CTlpYoewNUyKOzNvkOm115Bpg60cljKCkvbH3GrEo76LZ2cg
VY/rPWn9hUvdcYNbD5i2RHzHS8QqGWsS2DXL0HJefrgOldgXpKInt77P2GQgNzXykLSiQ72oiLDy
q3zkMZ3TiePP0UXWRD2C+hh04ddvVLcjmFr2AXmYYEhpJlBqCtlb3tB5QBTeocCGymxhyVDZMMMy
FW3AjkJ6kocw6h6LcvcaCOXkSHZryRqUSS7emNHY8exV1MXqVfBbhbCRFpK9cCFbBUKy8xPERDV3
vPtXV9xQ9aJ5Ro1JouABIE9nSL6s03/L8CODSRJV1X+Fsbd0fAVINJU1XpLRSupNelIKaQhlf0+n
BAs0aeoGzgpYLOTRB7DdM8Vj7zC5DiOGlrk7MtoaYpGJ7bhlMg6jKWVCyYkzfCVZlJlvyrpxhNnL
FLNCQ+NTAtOTx+tP9psIki6CNzRTM263pcsSW1H24ad+fHQtALXe0rjfk9PXAxNahI4knI0XIS50
MzT7MF3L+xqZvNUQKnBit5ntP9PJjGOzIxsaIZiy9lokqQf2M7HYjyuawBHEKft/B2Yz+MafRAZj
ESzKDMlsElasLoDo7LU7Nz/HyugOc7W5R+T1ErG/gqMaA9h6k7ZKHVHrHk+otV4H4aySHiyYg1VI
8n9N799uW5RgWZ7V6BdiJ2IdPep7HJOGvtp4F7uQJHoKCNBfhjgew6bMKpZajq/rnHs28yhmXNLY
Yc5mfoZeMwqM9yqrby6bH2G9B/jN8mN7AJcFUC5259tQlH/9TXDv1h/8RiMSkQauzZ69XKuglo+x
q1opttF0PFyMOPv+7RNOIlfz9Hk04MlzO864FrXUAQJ+eMtTf4iQ93euPW73jPSUXwsgrKKtSyIP
R9psf6ljEqgHhOwni0nikAv20AaPGX/736YhUjNB6GqQ8BgUX3W5b6VZ9Mya1I4TDkEkyBd16t/7
TvSSUlGRlE2/EVtOzv/i0x/5xC7iWkF/iKYy/TMrQWL8dy288Jlrhyxb8LX6qMYpOAVlowqBZd1g
yTZ/9XEpnb/isQ1Nc6UL4zki32OfRbzjzvnX3v/on/7p69g68tTGBy3Rhqz5Q4vWfpbfDfDhoX0X
JZAaUUVOq4j5A1Vbd7YjFiU7IbBktjAX3SjpavakGKMDDuJr2wxcLk9TjPOnKd5nnVH5kE2GKqNe
3bQKS/fJgclKH3nxSGXBv4p3d21Fz7Xc4rWSgXv43f+Ui1g3QDsmRKW5AvxeJ8sIP22WhhmdIUyp
taV6teFhvkivGQphq8Er2Ky+wbo/tJ2s6PHI0/jY93V+lOja2HkC4b6Jd0I2FAI7QQ2XLJSSorUm
V+qPI2+oycjAA7uXquXBs0lYIVogbCuqRB6Oq4bL9i/GE0CTeFlrGHL4OI4lItcOpjNVnxQfEvgS
iuymyclV+3CXzpiUEZ039C1NgCmmIUVrTQIv0uAL3uuQSPXOoXJTOw8lMwSzd2RfQGPA5e75N5qe
Q02pvrXS7k/t6E2f+cxP27o7Jl4dbgVGy+vpej261vun65gZEwhn9PLI3/y6xP69aNHkfEA+GtT1
v8ejxrwUl1wTTlVOIVgBAdCB7xNrg0jFlTjk2RCpBnZrDSeANF0xtT0NqGiGDNPSDIwBkNtCTkJ2
0Ant/w7/Hu0jZSoo5iMnbzsPY9E2iHetKPOfFhBt74ZN5p/l0gZ2mezwpB7RxvpvEYHpXGQvKWcq
BR+wpMZxFq+FnqgRDGaJYwcw56j1vWIx2jb8KD64V8aq2zSeIk/dan/Okiv1ZgzgNWr1PBmnspON
xeQE3wQueelZlI8kn/C1B+v50qWsX6k20nHer03Bm5UzbPVeXWlNNPc/JVl0RLqmY2zytyct1YXu
96kKABu7JqZFWOX4O0OVEYUpmLBMLcHIRWsW5rJ8BIQWf4XrdZJcN2zlVdfgJMxeTrsZvxrQ+Sd2
Y6lonFD6l8UxSIBKxfFornEjX8MOcemZFvcf9aXtEzkYa5CUlsbOQsj3Js8W9lCgPRPNU3DSHtFT
dCVbjzgX4B4DLNoQjODq/V2yDJoWyIma9DpR3zDhsoacMOI+7fqI3UTTlyAv85DJt0Cr4GFQ1zmh
b3jxJrjKfEdt8bvhK24BXBhs4N4OoQdBAa8Cdn/8dCk0nH44Y5HB1AqApndAzQPqmsRXEo2QQ0uk
dG0EhegKl86FKRBr3oI51Ab4zXu88khoXHw/A/MeerczwFUfHR4dRYZsIl5Jzm3MF7iZ6a0hJ+ee
gER4XF5c5FOlcxgTho4zQtozDIMgqHkVZHpoa8VTKMGguItjuRVxkU5W5jFMc/yNBG2I9IImlGsd
5BDUOz5A/6GGqApXEa38977Rb1IDFOdTnDsBwfXLHn1IPPmvw786bP1atnBiOn6iz38b0m7cbtVM
LqxqQvnApoAry01JH7cQmFDpSGBPC5RqSjbJPadPlysWRsf7ySwsWAPUN+a6kPwX+3MvgyIIXQGG
KN09NKsGk6afAqk5i3CvVsDURh71yVj2caUl3e+lV0NkPTW8kxLEGUdo76TpluO6c+wYUoLW9xFx
RWTOlRsrcetvpP8VQJtMCGDhF+cz5izi35Xetm/fH8ykaoQC4pmcAtUuW8aCHZYtxrl2PYmv0xx7
sgcCQ+A75COLgdaGqUSvkrikKzYzGxV/v1SeXGg19z/UGBj3+a0+rH1HFl4cjxndCNrH24VYU0Uw
7iOyAgEt9VieKdsEVpHDPVIMuQU41ZzwbnLqi+gTDoqTupOMGk7ZM7ZMAALKWwrzst51dyW73uR1
feK7WOYX9ts976NQfnMWWjfwc6cLhHf2h6yFc4a3yXptIy2dmYi+tVVuhJooBMfGqVwkc8Eg7ZLZ
GNcFZszMZ5dQq9Jzl/tibnFx9zRgHQtfDaStsWDZ5dB+/cr9LsuQgm49or/vesq8kDGx/uOk+ar6
9TNVq8E9QcRGd+ISzOR4s8BljS0CakpllSjHa1hv0IYdyknhWeHmfRQz0j71+EpdBvkg9ZAtMArd
fRIiEFruT9fWOTYD/cKIsYnyQHHGKpa2ixZo7e8On9ebj+kMIfJRPuEZLvzWy2GmP0mK9R0Zkhev
3r9PEWzWdZd3fyrHmy/NKEB88H7z6Ok1pChkQHcZMLqxoQ5mOrgc14G+uAoMhrUrM9Fu6EqzcshQ
wAjOrM3TtS1YNH8cobBh7lupW6o3eyCLwHOsm3+9IqlyWASQ2Ak7B1no8CXrbgmFWEyEfsjsxdZP
WV2tIE/M3iIc9NVSImuPw6+WGCbisT7vXlB4piDqBXVg3rRiHUq6prDMKY3gb/mndx4XGHeg7Kli
4tuO59HFl08aa+lPuT6tbfz1koPWigQLAdpO0Jy0MaRgzeywcE4zILEthLoeWlLcWPjmaCZBck65
wi38yJo7wOa57SvJtCcCo/w1F4Rjep0fBud6AEZ8EChVAOR1yM+0/Q5Se6il+dJQPSj2z1Gq9P0J
Z7YZBxc0j8pKOdQaPTDUfyTDiZJarjwxIUwzZnr9LNc74GUOoxaSPUHQnKCW67Y9Sqp4YIysUfuB
yXPi9X/q+lzgjoh4uY6hzojapaD5VYv1Yn/a/CS/EhWGGTa+n4hugeMSDW8xAFmxm7nPeiIKWjIj
cOQswqQZKn32HZtinijhQpeofNDsKiB5lGtdjavuwuOTpZqxZ72JbYhEuU/JvSu3Aay89bhZZSCu
BpaFVVTs1N57p4PvfeAtnahiLvOHMFQvPAthOAkFxFNpuASEF3SO8zZv14b6R02WZmlHWc+OYhq9
mlo81a9itXcD1e4UXOYln4HWxPK68OCGDoxHZYzr1mRfxk/nbaRt0AFnXo5tufziLZE+pmqeUO2G
zyoNyHvRPKoAYg5LCfWJJYkEhZC39CyWL7workvLXMglH2gB6Mg/XrswhCGBmUa1Xki7bdBjyT99
xHEarF9lMI/0u3SUgeylE3V60MUjnhOaAuVj9unX240A5vC6hr7jMIKsBxDzzepJwjdkDzsLeJ79
h0rtVGDhdSe0N+Qq56E2PkT6cN5XW9yQXxmOyhndNOiQXlrSAItCHMWkWHIyjWQ3Zvf0ho7AyWwX
T/5eDMeG8Uq+ybjw+k8M1VBgFMxdLHG8O3PYs3FRGjFooPoQrDXFaLBo/LFWWeFsQ0cENnRAqq+V
jDiq/xjgsLvzN3v1XhLA9TJ6VD05iaLk2zdDBYK2DZCOgjoVUK2YgSYxgJvGXYBqxAu62Skmn5+C
pIkrMAXi82r/Z12grrN564D1KVP4q01huf1JeV8LZCiUIdYXgOXWRNW2URD3ny2czdXSY8KiNATE
aPhiUJak4XHFp3HXU32MRyDmaqwdtqVMJni599qGeHS+SKE9v/6YBcWnHehko5za6LqeNUWgJ3iN
TXiWk000+ajG4jak2vu2HTnFdAMXwKtrlTIBG1twO9vFFewTZscCvTl1R56ZY+o0hDKGsFbjpkHb
0lMOLiR+mtRci5+vg5/IAY/M80RXF2YGM/kMpUytbGUcj4ibZmko/+Pha9vEpvVNhf4Yf1Bx4YS+
mQBQ3xD0PQnVH3HHYE+yX0IazY9LsiMuUzbQ5QfH+rKnQhGua1BJKl1eHfdT2mkxlcCzZFGstYZb
Wtei+HU4G4vuVy3QryCrc0MU+83AEu3tagqiMWTSUb/peAqzLQp5q7Sf7DKqk9fz8klGyx/s600V
4lYTFADUJAy5SU2ZxeU1+KKeqAtcJ10+1jyHl8LHkFIhPS+JEXOLwC8hQqqJU1Bys1c2j51jiOnS
FIJCOyV+VI7tFLjMLIbTLwbVs4Qbg3zfGkV893HKWtUhRBKmEZ4VZSav0t9pL+zPsI9rRJ9j6LXK
zhMmKC2yJ4wniA/WWhtfBwzPc/PblQEiSVu/GpfLWfEpjG48w/TFN0PWwaI5V1OZhntI03QLujZy
s3QaxVWaQI+8ObFrfiQazTY1pNulYoqUWpBkFRl7KC2rZJe5FOtth78PAr/TSvzuiZDgMTxlFp/O
Ur1Fr3mOoC1a0mCYVw2FcPhv/idKcRcOzslHzk+q7imI/IFauDvsFYoBNCTdpWX2dTs2mtQw2pED
JALzuQb3sJTplSgmAyeRAgn7sm3ch7YZmCzWJlim1/zbMH7utWYXKFxBRs0xC+33weLPF1AmpfKl
AU0v3kCtfe/gIAeqctM9aIcvE3M7n96lcClvTqBqiVynOjKT0p/HObz7qoZbDhgVrRTLlvMbol0a
5FPkAQoZMrLWIvgT7q3pAQm56QqrwvPpHS23xVZUYTFlYBjyKRBYNwrrQGXWhs3Z+xv2xlPJwoN3
I/dVyv3ZVf9McGZ402QGNMkQCquUGHr/Gn/cpsNnHnIcA56ukMD78KbxHPGFaJHbHoZMpfOfRzOt
cPlEKDmjnlJwoe8yDtJolQ+KEs7ujqbt8hvWlLCLHTZZeKXNkPpPywcyTVgGvkXXs2GDWvrFOEaQ
Qc02JXZCME/dpNVgwq1uzrweHl5AI1MzujKixk0Kw4x419c32O+8JMnACG1dgxAgldoC880cLvIW
tIyeFP7W3QSOaLc4Wi9ZI9DbdSylOW9d8/UbD6X4vNzyZYpzzEq/1CUn2j5ZVr0TAYJCNcBh4fT8
Xd2kP+MjN3WYB+t5ABT2RZDM6TFKBU1Rejj4VxV+vQe736PsXm1C4eJU+AoyvSl7TWwB60sQaXZu
uLuZOIUsS9wT2qMTlmZ5T6ejVdCapKDScedAgxIuYUGXvCvrUQJRFBX0yHo0u+hRowVOOARmwtm6
Aojhotm6I59GZdVDKcaNlqoOp9cl5oUrzk8iamtFI+j2IRbnYiPDdQa59//cSgAxge5fD7VLMe3q
iTv4D85kakd6puLuoNguhxxQw/R4CSrFpVVAXMFciULnnhi3g+MhQG93/9aIoGn620gbCUU5cAcx
KGJ5I6X4yuWJARvM88IYnUfe0LflbijBvugAyou1Nwbfr6fn3fo8ZDunyBGmyHvcHWi+TKXnRYWH
L6KC1qG5pQ91dvJgYfIWf8hYi/cU47volRAkFmmLAWtB9J0gJFHQEMWk94/qiszKnkwBH3mQCrPo
UbHNoIuq8+ADmzD1zbjWSnDbNzY6w6jR0ZL4T00lRPP8Uw5K9i3W3GIiwnGdwupnOjTa6wnITRMe
JJIZXjXipDtMymxn0SLS5eVTPXHZSXfUgqzboM2BcadpqVru+6eKeURwU5cgrNvksVstmI1SUIhn
CILL8Cg1d/Y5PNYF4Wt9l5a3DlqIp1quBiZ5Kz1yIuEK/WZx6xbdkDIl3P9c5hB8FY886TrLH4ji
WpWX/C5j7COSycLRTvY7i7LvB2T2o5KvaL9qoX9dVtnfeoF/aF6+4uRZIvigvibD5+Wwr/ayhneI
x1QCyWNHki0PPpdTKqYmT820pt/hno2vOpqA1Mok4eP7e2txFuegN4yuzs18/U3cxaLR+PmFPGd4
Z5Rgi4b63qUSLOm0SkKSs2WTbPUjT0qseJvO5tcVEzGFpLBLUIQK0C4LoQBvdTbkq3LlPgaqYdka
DlQbA4NMAo4nnSrrzS5d7r5oYMcyQTf+0ZPNQtiCz98hlEYI2ZPYtepJ17LbhECeHG/d8Jzt7MbF
5/PxVGIe52Mq8yhoEXPWsjz0nqrIIQXIjfvTVU2BtwcwZNNawHtNsYPfXu9IBqNCG393zzmiul0y
G0/HJTaWz3GXBZpUVD+UK5qZ0RgNe37s7xTWsQcNtPZfLurvWh+s59bZBNxd2qIj96XBjb4w16nv
GOWSfsX46lYrIhU65LTzIkS3cu+ClTOz7tFYQKqGfrRBJ6AbpEdFjs67Nsp3U6x0wgs9e1QAEoOr
tHSQKr6W58tigWAmeXSBObYufxGPi7o7pLTexsZIzGtLIxF8TdQ/XwBTWj94fUugw/gYRZDGEWGK
jQfwdmmgVsPwGqr5KvO8bTCkol/3ilYRktrJs36PzQ/DNtnITlTuRYZ4DnL4jp2XlGR3zVEtKfD1
hfwzsQ1dKeE/nPOvzPL89XIOA5MJAtsJqfPOlY6YcMwZXThO7dZlWIzdpIAVj3gSnkboXmMq8N8B
m7vGFkyxjKLWnwWQ4QkBwEIornZUWD4pp+RYqExVMpf2Dl3LbJLeF3lbgUbkloverclvfTKY8nfF
fDOm2VErR4sG2werQLP6e3LD/TIYNP7Ohl33LNRR4roojTRD82Lugqs0UK0xmGOjlqrLfsrh0ZlS
hkCW+P4Jq2bUk8kGw2bxGaqPVr+NOZe3q+oRlrnFymjFGOj8cl7oqaf3Avi0CLHQQAy3g87wfZbU
oZA6cnoOMr2CE4D1opDHnq+oBHKTk9INx1qHk7p4wdBztIjyF5lffwiKaJQMPJWc83OToldxSWZE
L02qho/OJzP4Wv5os1nlKgFNYyGgTH8SYfe7lLbtd/iQs2V7+rcW5vs5Qgamkc+XBTGKtLpyrBsN
7+Und1UT9X7UDX7myjf4EJjPbNv333CQj1CfzC5fS5Af2jN55uJJuxokLIWMBB+9P+nBbuSaiWAd
AOM+bJrkp18lTHgpQXpdwoIeUl6EXal68qkExTbX5WEMfxFEwpYG88Qys8P5BPjsWNcAe/DMi+AO
flcPUZBQHU5EKtaC1YO8By33l8VEdetaQ8ZpCMU4SfY0sgO5NE6QuLGLT1EN8DDJL/NpVG9nxtaO
tFUt2ZK6ZUCyGmmj4Mm7phOw4VwDymoFer9HmNbHtv7mUJfVURCpcCRX9oEz8mDA9fPURPdDBEO0
XHsyP/xGa0rVUaxxu/cMVfMfjBNIHHAIoBOWCZAuaVIGh5xnQg4Qesc/qwNCfwmfxFXsxoQLmVnt
WN4umr4zF+zo7kwlrLYGWzhaJeI/6mYkPXmEdfY1t7+XP4VYtvyzdj+W/hF7SgkwPcKGdapmImHN
6M+nqk7NLED7X+0bas4bDINHRkNA8sSVl8Sh0lt0B9l06krZHMInBy97p+A16P7p/Pav/IDGmFLh
Wt3pve9XiA4n/XdCUYUpJ0Q228gTy/5gMGKO1NNPEXe2cYh0brwgxnljhoDrcFHYf05o48iK35Gm
0I9yZcMA670XpbK+ORxlZafPOqweevFXHmr3CGxYxhst7ipMaI/fNBSDdoa3AFgtDzz1/g1kNMKZ
bDGqN4NtTdqbFotF3Fnk8J6p3fb8K7J4ZOQbNH7armVxmO/oufMhnPxqNdxEVBX5jKaCKGXjxDrY
ZAU/PHUP7/AcCTyr81BRQZlNMd98n+6uEIdRpzv1j3uZDssD8uvoNnNJt8TYeNTv8JjED1oewsBl
bqBUiQ0IyWBf/wSRSBHQDExQlrx9s69YX5yHCzDT1jCFZn3RddV5plKzHCZcb1UtrxnJgFIcvQ9U
c8wXXFvtPZUyRgiAoRvCgzgDxSWcRtJv8ulbUdXWuaK8ZZtk85a2QolvC5Y+zQu53L7pNe6V5w9O
SiCydSDz/ppE9sAwSB4w2PA+eKxHVB9kOnuOIZGFcef+WjLS+DKJkM5V4hOtAILmDsQVzvut9cNA
0Sn29B78HFG6m86n6YSr/R1mI/1oVqBGG9drJmL5RuKCNn629w5hgjNYIBpW7Bu3qz/Nxo+we77t
5LzAsRPgv3Lc3ZNTbrY8qzJlds18yQAv3CXbkA8+EaJQFUNpgSN+vUfGCo17wfbHcrAZpaUGAuMF
qY9KHyqpedsPdlunju97l3MsiUbh3tUikwVDHT8XKfYZBIuJx6FjwqCwZzy032IeEqtQTtF1/3mg
XKbJ39+U7O8C/TWrSPLBmCfn91GhWjFOfeGROHp5C+Fc3Z04Fi+LfdV4J99rk2jHNcu/l0J2GPdA
FR3vb6vfRcmd8E1+S0fQSu7E+auxlwaFJB76THrJOYRL8z+w5kVE5ArHervlpZQRp4TN5QRhRzKT
pyYoiEXlS4o/KyZOECSJWBLs78/XjJLWuNpU6GtWSdwOZx4YzUuRA1lU5VTz1oS3EevpRIT98Q90
4U2pBq3VWvBok3wA/QkK9Nt1Si4zRbD776nZgaQb+pHSEEKPV8ni0f1WjnGYTDZqqZicdp7A8i+E
3wpoku597y2di41dla9OQNVXwLruwdHg+tQLKOa6qKHMDhKhyGVYC6hnUjlKLSvlaMMTEw2LspAp
w9Xz+LMu/Dh0mI4PHJfWnM4XblaaAkKCs9oafI3UCSYNTEAaDEG2QyjLvKFkZyV/9TnEGdnC8bDX
viXVtubuk1QXKG16bS9xr7D8dGxEUiosjqz5IMFB094uT6L9pWO0DQvchHC7r5v5AHITnhug/sL+
+z1q1EUtJJ+wryvA34MWwMts6YYLX9evJZVXxLCst0gaG3oVj6X0PrjPXUuqiMK0zkyme52eOGIG
UvrK3mVlFcc1gBN2vfP8KyrDhjh47Ivi8GTJe77cUxNZ7QMCTKTOjZhof34KDag9ZluTTvQ9tBJ3
XPj6E5JPFr/IdbMU7Sj8r0UEeh1u+FLdbXONu67WKa9OWU8TIeY5r33iwCbSgLkzEMsLQXyh7Exy
VcNBuvMtARlqFpelbEgZdNHWcOPLgnrptcm/Gg7o5OSwyv0tTnb1AAt8gG46LMF2grnSuQH6Rnvm
o/rrGqgp5hGRX5+TxallveZbc+5gck6WJ1+NPSHu5FtYFLyvjnBU5b7cYlhaIoyLSKw+R27R6/+F
rkVEK9Ta5cXu0NoFk3YELqQAZjmrRfYuzOe4KXU1O1IPigHxffLH2jmT0K+5BnULQWmCLRsKurJT
XXgN7dUSlGAw7+bX0CUxyoXix4AyCsjenB7C+3FmVp9AQT+A6MQPJ6TmUHK+lwFOfcrQvQcgncLo
AKoifYOHlQ5PPHcTGRkCtBKMJiO6YNUxizP1+przyclAjIlk0IJ5PpZiYnq2GCSV2g1WCXFEFKPd
2FbYZLbzTsNQZhYQ48ibqcagbojfL+dcNBDK26x5LGBHipaxKnxMEk1TPQZA
`protect end_protected
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd | 16 | 292080 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YNZOfwFmq+EKwX1iXTqpnCzO6NCkg8iVZ15wmEqF2fK31FdwL7p+998IAHTcmvJXXulOlBvS6vH1
+iYCkUubZg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
fSuLWicvAgz15dAyaBM1McguU+c1OlTxM3rwIjZed+XVwT0aj3kC8vBXZpS89nkrz4cH1M3IFZBK
zd+c70XrF2f50b7PhHzi1/zvy7zfnrDsI3RQtNlcdzxESKaNa2OVRlTl1FiVvvM0flfMEoGOVBEg
CInpOdHF1+GNpH3Jzc4=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
c0YpjGsmE6XFKBplkrecWMiGPy4/BXTRGoswHI3n2HH7rRfRrIKKFBskl5r4MXDh+36ObQ/r4PAk
tfwFXdRBQQdjX794wIxcy6RXY7xcRmOpxCWwo0hF7M+Du5JZuTdvu5waK1k3RHlAIf9fMqtpFqa4
/KglkgOK46YLWOg98V4=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cUsDUT+TuVyMSf/EEh3e3oVg55uMy42ju7dn2qfNxoV/6aNQsmopR/owNzHJ8w2iRIbnD/sWUeVD
YfC5Nh9wQkO+W++ModGSDC7LnmRkQos1o2QXsyGO7CwRp+BAnJvattDBYemVwv4BYerghJyYxugG
VuaHyMph06OOJqTM01KRiHL1l6599aYPL6x1/zhvgxuLp5p+bcz4yWnxtE0ZoamT2LCdP7gM6f6C
edWtC0tvUpoBL6a3+CkNW424HNzG7euC5cgFf3whD5KjxK0sgU3DOgHfGxtZT3pY69/36mu756TX
JZSijhFRV50xlcUra7R9ar0hdrBRjEOSw7W3vg==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
msL2o+GmDoFk+NL6vgip8zUMztiw6jKP1JrnEkE+4rDO8UAEw73Bp+XaWDJ56xzku7n2eZey3ZXo
5t0kzk9ueKFNecgIlJ+KU5U2yQqYWSItsRIQuSu4rKPl8Rqn+dE0pcawYSBPhVOsFFtaXlpfXI5E
/6dCGckETNQ7yeYg58KrKQfp5W9zaaEw+sE6ym7QBzCBb3dmWjdUqH7paIeYhjytGjAkhoofSzNg
g8k2NBO+eeLdDWD+xxiRjuDbJXen+TTEMwG3QFWPP6FJTr097RR19HGV0ON+WT7z7zJCaS6N+Ajv
3OxS7NRyD6qW0oN/CBWf8OZtJ5pG6dKBLcxCJQ==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
kXQIZv8mrCnXdeUXTei22vQEDigOjr4M+bzu4+tut8y+H4BU8tqpgWzAawYjBx0Q9HqqEYYKSACf
UeawwsHxb2466iL/YrIN9+RqC9NKqlbJC0Gk251C/dmXlDQUuvsewDbLU4g9y+zb3nua3y4dKwNC
QE25LX/Sa3SyQazOgoFWwhfEsmEbi2LDvoNJWIuq7sSOK2Awu1VlnbJcXjjblq6y0akDL9wLxa0z
9pb1oK/XSraNLnR9asMy7i1xZ7fwmuxwLowdIK1CU6T/qtrhXctBLMsJlQ3gnD7FJ2klrTuK3ilX
2lNAz+VBfdEokkhLi1QPBxGu0q6x58LkOoJ5Fw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214080)
`protect data_block
BR1Q16Lyg5zz6kUNIT1/rUVWp1M1MAxsi8GRvHObVeRDDhUtG4HwVLWBhwN7oZq1PeZ8fiBCeUnY
GLuxSH6VPc7Ep4Q2rDBs7DAz8dfWQb1LnMEB4lXwtXR4DJwittOqTklXJ0bv8Wt7aEyWWhCNKKio
v3x8RzWi4xSeOJTcl7VvmVRF4ZCSbzSi3gwZ5D7NkqnN78x7qvs9IaZ7+sUk9tqvRGcTKJb8mFeh
383QXS2Odp82BtHJontYNTFemShoOdmQUtt3TCT3z8DS6apGPx2XCsSyUzLnhCPQB3RG5LJgLaKP
OSpTiGNIs2Y3voZU7+8ATsTkko+1szYoG32QramG3zNz5HnHxcasFU56LZvQ8G40S1vZWwZaqbpq
8FBRHEi/CRkCJq+z1w4DxVQv/FvnFyfVVglAS7WHs7TgafDag4ZAgpiyOlP1hBy8c95JR4kv3SAX
8ASRqInPYY8HLN6A4mImkIX3YQge6uPjx3Gu6yzUIpcL3Dr+qgq+kNiKu7UQnXZ86IMYeiZz9Uw3
gEpnq00YIaccHMXqAvjBrljJuBAy+QEKZ0tmpaJhzBUNRwpW8pRZXpzPb8SssWvQHQF6UpTw1Ncn
cGF+TveIZkx6u8CbTof5tY+pGoxAwbKXVHpQGy8JI/YApoM4gFB3kO0yGeMVsEZ6pMWHyLr+uWJY
hJ8LQYicN6CtmGkdKgHYp0WH0W9QuE2bz2A7lCwsTey9NpPVppgw13WRweaZoOO2bmrhmQWM9Ste
Pz14BsSz5StRO6emnbc6g/bg8wdkdEUhAdg3Q9gAtUTtKtAgdOTaq6S1h5z7163v1gYg8jJnuO5t
i+v8FpXHhjWKetJLwjJu3wgfhG2zeWQ1zr6+2nEoZFSBlEpocREGBPBbqTENGBxOmiXeuVQj+j4F
hbS+n41nPbaFEmm4MxwCOWF8igwSUN/QjN9RA6wqjcY1G88cFeF7SLMqFlNsxA/c0WnJlC2jCcIg
ZkkIvUPBeBe0thAxkSB1NNfFBTgW15BCD2inpCFzX4HWWiohnhEyKmMlXI2DhNvCr/da0JkOPpXV
ZK4qG1nHxY9afOsdsr80zjOklpilxqv1yA3GqC1jjsoN2G+7DFX3MqT3WLtZgO0c+TAfh2/YjkHM
z4dIoFMrYz6JqFxWCDU80e37UuuU/V56w4SSzUlFxsxVc8sj7JnVC0D/2lhu5i/csncT/1QkLvsA
gQailKvcsWcH4cZJTvwNlohWvjVVX69oAcJTWtA1Qsn10vQ6FaOXar7rHmSYrLDJwVikZQHM2JsH
o8zcngFSO71GAzB9lRx4jbVjOVYo/t1aAuHH9XQwiuba6il3yIkWmxvPy7VPc7WuDA4fIl2eG1gi
pSPrK/2o+scJ9NR627nnUkBLSc0GcZBgHSbbtf6kLV29YdIe79rruwgANFjTRsaQJxmTbh6aDwTQ
ZgiOSUj7Yh27d1GhU1TEhmP/HLBjnCXWkmjt3lIULjR6ktBzulf5nK4uONilkUrrM84BUGhj8Ctg
JpYEu0pQ9fhtHvZdagKs/4f59HU4FwCDsgBf7yOBSMG08gfNK38kT4uWzO0sSGjO6z0cgtf4UzgD
gJdAncHFQU0XDg4+Uh58ldqUQNs+xj+Gb2OoaRKW5ThG2u1VPGGuFOud/11QuHb3xnhkzxImMims
JGdrAQ8/zlZghI+mQGI7fugi5U6o2hgiR52YSPou491jSs69Hr4o9+31Uk/O2+qLgB0iQmroafVA
HvURSCmLQ5OVjH3GMi1VJ8/dY0i4kNxTnGpYwr36q1VjxeCN1JJuCtw+jH14xC9dd7jY9NsIBATU
dwyw2D8vSx+m55g1+FMlj2WirC2fToU/EXBnCCy3xvbCX2T9mIAwti69ziGNJanstLKrNns3dfwE
IVjvXIkrI1fmrovyFJQUV8zFtnHZjK7OLB/dL984VmPVLS14K+yPbVUR7HF8452myt8FGuqVhOma
D1tGpzWIc2qwTVa4CFgAQWbmMoVAt2bULpy88F9NQ1B+6OAUd0g/4SQZmrhfL58W8ddIOZSMd/nA
zaHh+zUH/+N7+lwGQ4lF7cHnp1Jc+tEbssDNxGqVPsYrCXb6M9Vyxqh0GOZtoJr4l00CLF5fn2Ho
6G86be4szTVe4TZheAT55nK431wWiuDCR8SjHJxkPpPxKtEki14IsUrRhnnQdk+ubjbnS4Vnjo2x
JwlMSHr/W6IFPk88iQDjUYXQKDhZpyfvQqKIVhGDTzOuB43or6wt/Yay2Ux+VfGU6907WqjZu/ft
+LH63N7k2ySUbOlK5OLz8k4mcRRTDDXaCDs1lc2h/Bv5LQ3Rmr9iF1TXBeEGwcV80HtDxjP4vD4w
JIwiZc3ypYouya8NtbvXbbfEdVh/Vzrx4CVGHybD5YXCvQHABHcgRdP2wxRSTlc1favJyU58gsxf
lZDwsfuuV/mc+SZuYxo+kZQNcd7J9AxSRO21OVPVdlNnVk2b3e7NsVF9yMhVALs6co2FWrca9rYr
QawDNpQD3RhrhzSDsuOglPMxsX4IF4GLNfENamVh3pHmXbD+3aR0Rz6ziB8GOP2A/EWbuBfBX9jh
AS5KigAYwf4UIvSm6+U3s6wCeSpP6O4dci0rL3jo4bKllVNcPuO4/tweZKafgFdyn48e8XM9f6zq
abEfoNT7izTjBdJfzh5oiahi2U0Yy5LWL+tvdkEjSMgE9iQ7A30yHXo8MfSb3haME8n4wfZP3WH4
w1BcU7EWYn4hozbJ7omyOudp1GyROpgMVVZtu4HfXuKxGblAIg1irSg7Vk8x2xm16H08bRDJZp9Z
v7UDskSoLjQ+0I+VjEHdumlOpUA07/Yw1x7NBJ43pA6M1w5hJjpawm2AJJYPGemTfWW6DhNy0Yh5
CO5E+SwQymR9rDhe+MjDXrfNxESS7eQXm4rUkLOP6BzHTmgQ3ULwlx7ChIblxiTtu/j5JndaJoho
YS3ugUPcZSA/XygT/BP6faJkR4UkGzweUH3OO2tSWp53KMC8sqKhYfMiArPqMK3eDozMEyoeJ2so
C4DiAjJG4mZzRBAPzl2RtgWDEE9gmZNHKa3NltxA73dHrad9qdKB0OMtOmLX2HfYIpu24JqX7FGa
h0+NWZlBRPuTGV5WdZUg6M724pJHnG/9PDhseTqjG/LfXITjD0pE1Pv4G6PyDJ1D5YrDrsgdrtBE
RACjmYj8jHAbj9QiMFM4U1a77UkcLLacxkIxiv32FLOoYQI5LYfkrZprtuLbekpq5HUVRua0D65r
SBRRnxHR0s4Evm32yhGnoGGhGMqHzl/OmBs90jbLwXQa+yR6Jku47XStOziHBtfOteQ2EWlswhdo
Tft1JOCce9uxEwjAOJTOlaQg7sayhSE8KkF2qllY3lPwez+bCMkWvC9KFX4UXq4ToWvh/gIwVuSP
LkywPwXZoLN3hZjmhrSUQmsrNp/JBoGW44jCtuuvyczAnkqguIFjVdEhfRkty8QFHlTFz7GqkeEE
1HrV6ffDOJOYdRndqdHVNdp9SOqGWmJ+dfT5BURCdTxdgjqw4iRIhBdl9c+O5eA8+H2goPsL9LUK
6tx4uOx+g6Pr4/01+Bp5aCrsiiqqDpTGi4/Y9mR1YZn7n+njtA9gm+BAbDO6EzSmPe/fa9Cn+cZF
ndzAjkZ0GOWi6Nv4QXM3FffCCAWUYKejbzS769+rXZZc91akEUpG92iPuEykeg4KAy3pZZh6Afmo
z/ja7wBXeuLFxNZ7LHfkNAqq/PL9DfVYuotgjxQ/UCXTluPo9u4hVyfN85EmjeiVIchysrlh4V3u
d8FDTTeRaODMPl/Us0F899qnepstx8W4ZdpONVMxlOf9hP1+anC1iN2h5gauKgqQ8YAh/L+xLJ/K
3MUh8jRw9EHg88NeL2wIex80Mx76AwGb2S62cSO3f0yYUkvAJsC3NydRwpf4qgGvMtgfxVKmwYl4
RkLPmCWhAnoLuhqveWvvEirP5txkHZd/tYJ3VRCS+1hl+Lb/IRXNEOEdH55W9jtAdN5JqITmjk6O
cxpT3R0ez6GY+q32Q+kPul9ER1gBzPPMWWdPBxZ7CJsDJMJLRCK3f9bJPCHe/y3cI/gWF0fY4iM3
QGgheDrSUeVKrTSCjHiGE5qJ6vcA/ddJMQnDeuF/24AOK6iNHHIkxrCuVy5hkKvG6Y4sryVOLEUV
alshUJM4J296SJjxNSVpd4q9u2jTvwQY1mXbp3umx2105H7FO7ThU/Lf/rNpdGOy0yWFUvQ13lIM
C9bCmhkkpFvo2h9F1YvJmvHRDK3NZkq5xgYxb8WH+1vryrbA+Aliop5YaAAIXTxQwJt2lfJJXcfZ
dg66dTBJ95Kq+2Tp1z7vhggalibPOttGx5XYAwCpYXZXmdMnNLUSTCOXDWQQWvubRgfD+MuspBqV
2eu2FAgn/cYid4mIoubRztD2SXVIVfeZYAgIJIVcHbb+AZeBRsM/DfmhFUdYm8uro/43s2ez1Sgo
+Tn77TR4umfbvll/IwKyfUoME0HDLt1S+zmis+8rkOGun8nBqMSgybe9vSm4nXad2M1oZWyUoaOx
7KPbT5Tt0RXXtivmmKbchL8FmSr8niyjjMG6CSyEQL46lY3Y5KfUI6TwGLAL47EyiL1CbNxfnKa+
B7XbCdYnLY8PuZjNP3ntyEhDr9mJr91uK7HzfKrEFrI/Do6H4rDHlWUDKC95gLcw3bqAV56/0bZP
UT2NY8IRAZGwi11YmDzanMy56oAh0WIcJAkNGhzwR4ozuIIdxVoJUXMiL38hK15jsEo8nf4jeCnq
WkltNuQmtGJP0xbWtSiBCKRBu0ezci/ky3LKU0EjH+TbfHfEObfYiLjz5ElVb24XOEHLbCk8BrRj
8CqPuFOIcWe9ex3VhVrOWKYPCuqVwxwhiwZKhvUNMUs2pwa5XQB+OK5Yxwly/OMX/G3zJ4qgz024
gTmOrJ+Y9ft6HTFBhrc5DCEstIxR7IbJlVGgzwaaW2LWZ0YLhFOQ1gMQFqKS86tu+gISs1LgdPP4
QAIWY26C9rDbWuZeBNI6KdhbmL8c+yAnQ1ir2qPeiz0JP3KZZlKfTECbgM24FsfdEIr1pt7Rx9Qt
3rTY8qmkAwcNEUxK4BDAEWw23aNimVxXO4yPkXJ8Dc+q0ietgW9mXaFJTmJvHSl24sOVmwIzcjUQ
MwbyjdFIObPlwr4G6oAsbwDjN8rvhq/UOU2rPvyGkuk0otim4do5ul2aXX80gok+vLMiA3XZyob0
izSnDBk5ooYfqlaPDPFRqdFfNU0eGzb/t4HvCl89qT4FKsRynkgxAjbja0JPUlJJP6Eqm2sH8aU2
0BOYSTbCABhunP6NNdJ17SEbCwVVN709q53ZplfzU6yllCARZRm3jBLbUD/llpf4a30wAUmYI3xu
XV3OfrRJZSMSUIGn0mDnILPtm1vCGKhH4RHXskwhrU0EgB11kkjXJ37ecmoUQGrMQcNV0pflIxtp
w4STGBZXkv70WzmKYYExXcTPk3gGl9DQytj9KCAzEF0N5gxYp2ir5xX6d2UZFIxtZSZcITsSYC3X
2lOeEiNDos6nP7/+yJXBgI2zsHZ3jSX6VIgSCxkW7QtUFpZ/VMm6kZJYzerC4Hnbn6T4RKaoQDVz
OfQMsqW+asrudukxZyEC6/gaG4uFNNnXkV7VseuNqdOiwA0iluvBsFFgR/01tkTvYaAnxCHYG8vW
sSMQKzPQNrvqasDXpoM0abfGqR9GvvVFMsXuLw1PhArVu2x9oWXun4bmI1XrE8lbbK4CbWce8HsS
/j4XE1OhmU53iPAx1e/8pXTvjv58aJ72SNEEfoWH88qQFvij56nlmlHiip9aHa2S7bqss2d+2qrg
4DcxLoR9LKCoMD1hO8OOrh5kUnAkEj9p0K+FLGTRJR5dq1Xw6s4eCBrWgEi0KI1ZMm++K6sJ8c09
Hj1byKlobPmK1sAcsfq8503siyNJpuDWKVvuAr9whRVZHmYIH0EQSO8N0bp717j9/g/8I3OnDl5j
vsJwl8u47w04HivS56Veunvx/zcR68IjyKcVGYXcwG3pObmVfe3KphK+YmG0k4Ddjbp7xnu23wH6
b/bLqE1+5+DfzDXTsMIAg87Yt2dDx0+y+5/pi9cZHLlNsxIbcaorzv1PpsLGZyd1qY2gGM/d79rd
LIwsvbVZaiWeaIa9evyy7jALJvJvbe7UU645i/lquN3Ilk7dE/RDGcJerMdIl3J58p2g6X7MxCXW
4W91NZNcn2BcWkOMAGIJkigeaLdWQxy1v9phJiORHqbdIoeLQn1avPCJRCnWTnWDVC6hE9dT/Ury
JGJMLDADdMQBeJIc8eKG2SM2K92fzdf3AuF78MDM3M1J7SDtVU9J/7qN5Rzdg4rS64rhT+EnGByn
uHAUKs/RrJJx+TtTvLiSNid0zMNMKH05qriw0EdMEw83hm6wkeNEooEi5ltcziCMsLTXgVmAj2pc
Bid76IQYvZZg+GfVyuZCfpVrcmislWROpw3fKv4FIlyq49ZY3zdyUvtnCMZkNcNekmvy0R7I2quR
Kh45SfO7PcOGrubW4H9Vnt95GtCLiVvelbNsh0Bumk6op8caUIHyedpcFM8VVE2HxYpx3NIhqBdh
czVivuiMfKTaSzODkrOyY90DAA5EqKF165SThok/x6K7yPVOuZnu0LxEIlx9arnzNN7cSLwx460e
DiRbDg1y65vPJ2WJ+N0OG+o097XNEfFcJUIUQhOqaPFMQhU7ynav9TYRbjlSu/EuGnCIqvBZn4oM
4VwFtb0xlVSXLIrcSqKOgGWlhGum/OID3NsCWVSRIgn92x9Kl60ar+2j7Uqt/kMMK/Pyufmkz+6P
UQ2le0WoYXUrF9ORuuJaPklkt6iA7w0niMGUDw7S3EYjE6uOrcanqez+KlbxFxb75o97uFesk+Pb
b/0V4O7S5WAuJ4qVQd3300ZYN0EULUMc7uzvcDTkk+Gw2EaWoYSJHanMWhHklnDeQ4t5SrIQUwwb
O3Qmx1XoOTwGghv2ytqJdiZI5z113urzEe/srCkZ3fsatvrnFYtpvQFFxkIPp5oP16C3sNn3ADbC
ur3kqqVEzwwuS5KM1qQKNKsOh+wiF5efUSGb6wKxhhkihGdV3pzZniEWucq/o2dAF6rL7UeB4e82
TTjMWOtRM2oGA2+KGV/mpAAcZt290vstpOy2RBHsVJDp59Bf2tnHIuy5Ls6xjAi7urOVolMW11Ee
Uel2oDZzh6DQBC81Lsl43LFFHLdDjPcs695d8qRgWbonBfNpvVBDUdPdGBrGm3lSRw6FsIH4A1DQ
Ejpms6oNu1PFQtmnpzBtEGdsrIfFbNfBYEeysNl5/q/Xu44H7+hxLFwwVKr8EpVFRdtnF23lvn2Q
rHwnY17jlXivPgIN/p+woSEHgre+iTgC3h0ndrn2j20kgSGdD37jJJJ0H6c8OqaJEWvFKhAN8enT
cyvM7c+DqjY8GtaECTPEr1NJ7gqvKVc8u+vXGgHZ1oAsP0UdTFu3aDeD03oqVxC+wFqdvG3yqCZK
bvoUNNYE5c86giQjQUK+JKXR+8EbziMeQPE0VdCxuW1KNtECcSR0rEzGFIFT01lvBjy4VX305CDf
ediwWyRxsCmix8XY/dlBw/+h9Al03W9j0bHCgYZHSVt2SRrTLufj1s7LOJ66pt5u0v+fk1N3vZK2
Qotq4LBIQ0ku5Htl3QMnDz3XUs2jijaAQ1M6L465ssh4gTdeJKbQDw/c5ByMgi+70xDwLoGY/X00
uDGsPygdyUUNz88waf5cPGEepMsJLEDcpj6YHe2DsYdlFWycZG89UWkbo05tXz6qVmZZS10MN66e
FejGWBBmymaZOAtCKnMUKNCTT/z56pDIG3vsRQMQLn0KbyO2EOyvy08GWu9gvRyT8SyCNrVozvjR
xPJe5FhgrJyq0utal5efWvLR3QKxTY08V6ht56rLgANt7lipYph1UG9rmj/DRghRCTXeYpP/V1EN
o3fOEUUQ7UbhDjwJ44RVWYPaAUjhm4EoiginyoIBmejWCTPOIaRQHb/wBx5rwkEKHtCTaojAn0JZ
TiXOmZL80zhhPzroti+QMveCnqoH04b9TpmMsJOYgN9+5b0OQb/G5FROgOjhTxD0LK4lh2I2LUGy
eTQWGCvkN010fYgI6IbPybY7K5NL3fNBXQ45WxJ26tkQBxRQHj+1CeOvk53vKYbhT66mCKsszJO6
RW2RE56pGRNyIjZjXqf+IMw6G77eRalpb2hUdCQR7t4HYbbER4dgSZfzKpY+SFNaqpaG0L2ha5t+
Q5blpq887kdWGy3dRetuvQCvcFnlZ7pkrxWt8+Q/GbBaBxX3t4O62bFc/eqyWu480q2ImQrDiLy1
Opt7t1hJQd91KHTE7ffxwB6DF75xAp37OZKz7ixS0lAGtOCcvV+EkthiaohMUhEClI2XaUt8Hzh9
pxoy5FyNajYfN6n6iMaQs74Y5rqpmBHAU4jovBoci9jlNGSiZUm3gPEQmAGCvAfbGXB651m46TS1
iiGCDrqwouZmI4S1jDva8Ie592zfDxWf+ArGULOeEM2DJN+r/3nkgIqfBNXLwUl9QfQMyN5dsli1
NoQ4cZ6butVnpxZzfRybrUE1mSaMZyEekOK3fGbsMq05mjfRMEZC3A10eaBdqhGQ26WywsWgRSwQ
Xb0yuCveCNh0stJZwyZnFXTL4qGfFdjCcrwE2XDUD0tMORbLKwyX1WycEDw4AUbLKAL32pqX9gSJ
pZvGKhwjcHTjpN95xYpEC+TVW44V3P1XbNc2ofI77ewBhtb8hmEIHbxF0pHp2c3cCvgog79SYUPx
3KqZ+GmpM/x3jRvQvyW3E+0jIyNYOFTA5S3Tf6tVM/fCMMYU5AeyuB3fi4HOl85XVPp4+tZc+BnW
vEyV0GuhLBOgySvGNOa1Cz0gKw47ISsJYysuPzW5ruDYidh0zeToG6+iQXXN/HrBMbqzmIuAAV42
BgaPudbEg5SXPHpAPaGxfSULJMlSu+6mklELSTEh2mbetT6IE6nL3v2ipVMZ7OoflRLY2CX7IRpI
u4ucOEppIDYNbGjbPit9BJlh0mSN0ONclQvNZ8pGFP35m4Q/95B5yMFSKjrZrhy6U92RajzXAFCo
aSTGbehpMVwRxQFs6I8RplcpwPOQGfUccd8vqa+9MS46DfWD9pQIWfoyIcIZPCFsWpUgoe5iumyJ
EsdBFGaKmhyF4+S8umgUae+SWZa1NOrALEyg6eo+pVjo2q0/T6wPNCWNu/yQ93vXvKuUYtXyAlNt
tQbXbPcCQVFUi+/aFFpPKXfaso9lcJrpJcsmb+OwL68Jx/x5am61Gu5f6jneS8ZkKVU2XSpg4svK
MWSMzmFr1Cf80ByP/yRB+68Kh76zInmqgEuroh4PUhbUG2rUqFu4/XcjODWfKe0a8vXaK8RMP/1b
cABZeqpjaQxEv3lZ3vW/lwjW7HBcLMZ+kbTKRyD1DHQ4K4mRfZiyrY9vQg5k7A1LTHELWij8rcl3
ti0ly7F2lVxJ5Gz57Ab8WjXT+jKw4ARichRj3uiIGZhVdY88TTfQHJ3MdLfOOBcyaA5jtXkxUrTO
6eED548WTN06oK2ijnkJeVy9A1vjrETB2DFdVY3svHV1S7e3z1yX1Y1woOvM8Ki/fqQMfhTBFV9M
A6l72IMYBEvn638kzyU7PxG5dqFypWtuO0hLTXMQcBJBZBTZzi+LjUtsOSE0dcqWAM4m3OxMFNek
tpNdczeLp66j8GnPxQ+TTYXGiaLgbSKiXoXzrj+Omg2CylIYeNoMBJrC8vVELBjf56l+SIfATDIu
lfOZYktfRRRHt7vPWrGjoROzh2+BOurZW0eoXyeryqT+0ZvXsI6uEyqVYElm5URg+2zfPh5Fq19T
efd/xfIl6nKLEtCgDlzZe3/dQajmCCrr4moMTIvxsiNf5EYpPEclw5XWwPxxlZEWlWdmkWgQ99Tk
1ho4KFPoYNRvbTTibS5avBmy17dx287+MGFzCzRv3DQZ7rTsvIWDchECwikCQzJoOQyMuJ3R0zAR
9GGspEw9LIEoWj/JgodLPbFosEQTWVi1F/x9P+DgFFVrBKtA3CNxhdv4JQstFtZXvl8q/TrVoSh9
XGl7wO9jlKLlnlfpU+9wi5WhdVH4vm4/2dPgt4pNStp6E2VX2CaYl0H2fN6oemDnd8pJ8reRcGQ2
pOfpY66VANypT9SwD2Noqt8M00XJEdnC6fsFQr2THr90SovPaN3USHB58a5o8tFrrDBc/vukCVQi
Q9BaBEc3qtJ/165NG8DcTMo1dFS+QL4LWgQnR5hgZngI1DB1OUqFvIOD7oTJZN2MalwR3pfD5cZS
WHVX0fn8m/zWt+3ZxrPpeHySd+NUlSoins1W9npHgfOPN47JUGjoguf1t0CYmZsWg0xLbFgF38a2
dEJVWP6HJKaoP+7cQa1bXlrPCvqrORZUl7gNhaakOEnbaQft9dviaKbCXsUTuUFJ94+Hj5sCz/2f
tAoF5O6F2YWUC/MCZEPqJeXfN/GGrpBwjAhiuN8a+uIsJ2bdyd0+BezcPB1VAZu0ydkM4SVxt9K8
hteRBmwGiZuYfba+lZ6jXv2GftfJB3NnC0oRw2/yUjRLozuPeTl8Kq+PguNorq2dttQqK4o6BANB
u6gCzHptqiex5iIINKjG/emYNszSeK6y2PbQ+uS4wDBRy5JIABsIiZXG2l5jy/CZA3jKUHnI+EB2
go2sF46w2B7820BLpmaNUSt4e4SfO0W5lZjICuy1HjZOWeUvg3IWESvV4E0erd7gXsM65jbpIDfb
Di66ZzaXKaULR45IwARDLF41WT8C4FK+zVhClH/jam32idL5dxFDeqMMLrJj5Ue8ol+UYeRerH8C
y3hOzyJsaxXb+Ojtk62SN3fqT6XTpM4O7WUMkhWbg2YJ+wHaF/i5Y6kgFe9VteBSDwhqFY40QKzZ
ojHRssGWIcKCbErhHV2b+mBEesS6b0ZlPq6+Ufw4AzdJuSqaFq0jZ9uZKqW9neBsrNl+dkeuDSLY
QBRzQW/wH2+pzqrR7yaxAzPhZifCJ1RGxYzptPc1MjuMYwvWyYZwPoWBFCyj4ib53eVNpVwMqEV9
hF46W7XVJ9S0yseIR6MWy/nqMh7lKh2DzJjubOksTZwUzqoI5MIdy7xgnFfZnNKFkTlO8I+LeGLq
/jsgorocKI/eaov/kH+p4ntxzZ2eM41lz+N1QYJKm//9E/1yDNS1HYLQA0z/qfuAjQVirAuz9iFY
iDeQivkBtvCIIL/7ldw7oe9lkOLnR5c6/3Ggl+QOxUQhqSqmyoizhlgbR01UJ4/rd8lhAIdNaYX6
2j5HjYgOpipKXpNXNpi6W9G5cfmiFZxDCnfeYCeUXaVOHrIwHmleu3W2s2Jspjdp/Q8235xlaDLS
337LfEB45lHJJUJ7K4j1IgI0gm+WC8rAZpyW3Rahx7nFtdvFKvlvq6/FdMmIGDUvNwTz5R0YId4s
wjuznAOX12wmI8WCXw3garUvcqrw0R+/9JF9qboMeSCq8uLLuHnbkJ8luo9lbrt1q4VebTpjVQLG
uswwTq8H99BlrUOMHMCp9UIoIIutSzKCeleC4xGT/ETiik0cU9CcdiTzzOr+XRsRI3Y7u30ex+VI
13DMpNY5pjqgYejMTGu7I+Fuw5PwnE25c0YCeAG8aoBhZn4e3Va0omVuXU6m4ZApuTTvQor7tov3
gaO+afdxAStccTq/tE4BQr8dc7NS/rQlxnSImjoi1DZP/u3Zs8lj/4MlcqqMVKsrHhMACKCulB46
ZBSm97bVlvrjKNksWETEWJCWFn+8sNZru6JnwGHleZ8hEJyEAv3tD/YJ+7bwozZczuNu3NELNw3s
LAAI/AE3xroPjH4LQN5P3rNmzw5lpiXe8l8wvKkKR0V8KvuRFNF5XkAMhH0Bb7qQG5a3yAZWsgw1
i0wpcaKzB414famGkPjln7BW1kY76iVZw353waeulfHtb4WztHYOOLg7760vtlQovtCMjwjRAkNC
ZOuMG+wywM79FUuj4ReVVKt7+m5pGMoi+WI9y8bzhwxVWbgc/loPe/Yvjt+oronMcI00tXJTyDU2
R7Ov4VakyfpYRV3PY11paB+SAS/NDLZTQYes0/YTq3ZZOEn/dqp0blwhLxFp7fHSFzSNMxdfUPEM
IIDeo9W+JyBH1rdrAwVbKjv+Odx9TdlYSj7sAuWsM4xi+eZ2M8jbfb2nYrSTxdCDz7FEq6GhgJXn
KCnAweiBPct+i8HLZiOUiYrm5zg6AF5Dtt+xRKJu4dywIxT2bLZCryxJ73Onp9ps0jmrdb7ashpM
h0XROh6oj+Xh2tDZjQ7UI4RGqq5+vqEoke2ldswDEQN3cT2neGB+wnBkBXWQz0TFQoIhqTGgfuiZ
CZcpaMkGEhmhrqThGsGuV3rHtVdHrF+lPfe0uPUCCag6vlrFP4doB3cuykeqX5OrcwrwImcF20Wh
zLMIO9WsfIUDCI3DUXnF74fGl8ZH2jOBAl1cuPlpFqjd41dhQ8cP4ocpXK0Q44xu6uIPaMvk20yC
L5C4x0D8YXF8ccFVEeD2Hk40HD8yBljjdj56lX4MV/5Dmpp6E39OhOBiBiDHwR2f/orM2pOp3mTw
ny97EnuNlEDlraUJnSzGZb9l3ny3b+7Ip0aYLrz0wp5aNqVmLxythHDztQVKs4hQY9tncW8Ngp3Y
pdz+I8m1zt4YANLqt9ssiovGfOmzGYR18a/VBTzAfjrD3V+mQyRRYNzs52cIqVzY7twTYr5A97Fq
5TyD/4SiJ7V/TQoztW6D4lNxjp3pbKM/UZyLZXWOu9UAVHi2F7yRTFl7zBmxfJkUeIJ/kVfDxAR5
Mnx8kWqVGv+Fa5md8zEOdAmjYJioNq0wjFqRmbgZxXbuLKwEtqRZThkZqblglD8LjAeRH5HW1ISN
FY/WPenQIfK0ABpH+Pjtp2MsWKyQMrD9uYpjB7s3TBU1s0bOR7eBaP1Wh3R7Ks3NBQayXMoYRcZG
/LN11EMPKhIoKw+4xVHp49S/TsKGe6ENnbOIodklKMW72XqsJe3H8lihpnKFj3WOKkKWklRXAide
I5NHqwNbw5SFg50mhmHf4HdmJ12lLycmEVUneAw0zB39kXODgDUyhrqAsCtUUKUAWIZVlnnHze40
h1tDWQwYIYiEvhDi+Dl/MXqqK+4OVZTojBBW/Nlbp7lWU2ERiH1812YY+XC4wrUlpEbBQEHLb4ir
HiqWsSBOx4OlsQPJ/arBaR6LkNHsp3LjNbkPyAjFEjuGjIvDBzHTJsSQZON4sZf6qwH4Yo97O+3w
5PLLOhbKmyTmwmwofUmnYYQfShUofVkqZ3p/HaLDcB6zlPZ8+dq0jBdTQeOHOfoA+L5+4cltfdYn
lzh8qmLhaK9NChE7JC7oT0o/uCkM0+0baDl5YaN3hrh4e9puX3A7OJsOID0JILtIjBzqVStwjIzB
+rs2qRVPRYrx/74OGfBRAH4hODkDzXrFk1bjd2RizcQEGkjc2+Ahww9R0tI0BxBMaeMnCbSkWJqO
jwG8Rj4kGkeWnBbMlQUPsh+DNaYAK8bHgM/cU03ebESCMbI3pExG69Rum7kw8BgVXO4eCYeZvmoE
CQPoxfWynx/s/v+kZ+Z81UzlKRYFRgouM6Prus+IY52y1eUlDYcVZ76TEGWPVFvPZ65ggiuMv235
kBtv7b2ULT5ipo+jGdj7zeLMN5In3drVfejlLyiz1jE753uWpfrGWf2aGpcfxgOIYhuwrd9aBz7I
AJlpthPKUFh4adlPRPvfrS0UZauQlWE2/9zH4TfbaO4MaAPPM0qDRwbnlK648Fd8COVmjjEsFvqv
2odIbgkqQgJUybr9vXa8SmWQbE+VPAjDdqrpzN+C/ajN85Cynxo4FxJVsOmG2qteFuG8KU0plB74
0sHJFpCBMm6h3XttFDCU+z1Ehm5cfiWEI+lZQduafxcOiYvidh1lcmoZEd08FoRsQ6/z8G7rKkYS
sU5dvHiyo26iS7oPjbtmLJQ9RkLuutvCSl2cW3U0Dja9nRBFnCxB6VjmnLs1vwxOp88I+IgXqcM6
Lg1RmpYf8YQe5WkT2Yz5CZAr7We0eIu7dP8RbJIpNjF1LRlHcxwAA17Rr8309XjWbHI8bjJavEro
TrqVAJNBk/mqJQhp76ZDJsruF0LhenCB/ryuNV7jd2lscNldk8f8cscYfT6muEnFn/dn1/fWru01
sKm2YIshX97C9Sucan1iDlAWbYx/7VFI3MeBZFKs8geSxCh2I0uBxaR6lkQk87GBzOF7CBcHChRm
4p8r4iuZfdpYNLzb49wTcx8g8D8P4ejI0+qPe1byIN8yTLnfNHe+n5fhNUUFo4YbNQPV7epZi0eg
mdo4n3xonZhNLyg4XFHnRRMxUa/CPu+wqw4TLXkkNqu63MoZu4AjyqGlpvvFNSL3BuD241TnedT5
XCxBhkuy2yHQgBno2JGQXliDhUZB4mkJbYf8qyRl9Y65IqgOnWUrvKWiQSEBaBztwrC4D4T5uDB9
1tSdbdiCP3ghr3REsmohLXbf8aTwPxcqAltP4+09zSBv49qmccwxeLNrgnyO0IfYTr3Yc0VVsp93
2agbHLDW+h5HIv58tHEUzRBVWXLYDyCfUzY+8WDpMBnWO0ddOMhWBuw8OcxfgtvR2rfpuqIALcIL
IGc+IOxczLbpVYo/NYlxyZB+uCHSXKdLI1djJh4R7HrLC44z7UtDZsVlabok0bUzIm9lfNPW78mE
22nOkhotTmlugk/4BN0nLNjv2JqSeagKPJUKeJd3G59D40OQw43k0x+HRYOCGD+eSr0Lp2mhcup2
e93to1buNpWkZskuLZNnOX1tOe2L69k4snN77yZAFdd55PNggrkpp+A/ltHDc6oDiCmc46DbaNjj
nnYRmu4WzerhLgvpFpByYP6uXiEVIauntwb3hhMcaJKf2t1VzQLOf2ThGXhzZuspJ89Ytb4gHsGk
zhGhKAd7dnyNz1cWlCD0M9PwXWJAsGs1ryLDJsP4GvGY1BOvBMRGwTADTEXo5Nw924xG7QieYiyl
87qUUiPAizlK/kqLFA8/CyHIllXLlgjybNI5aIaDKw4+OilEA0kfT6rvJNNthDE2ooTTJdFkKXPV
xozbJFBSaS41v0eRIqs8HfaX/hz+2NE0iN1aR2PKmuIOXsRPDmhEorMs0QZNFVYxw2sKqJVVeya2
S8+YWZ5/4m7B9OPlJUZZ9+w9GvpfQMmBlnslL6rhGqadgxl5GOzIH8xfqhmOUc8vbMTTAnrbko9N
NcIvIzmwv8GXHXv8Yk4sNou0qLBM/S0DJN2LtNueZgjtzDGx3PSkPkORIy/fdtHySF1WIaFEbxWM
GeaQl08L6OCggFEFaAB8O9Hz+ESJxq5IG6LKM729dH3ycwG/SsW2m8euBghWHyTDtc94eaubFxc4
B5pT6Q/puOmvKfnmB+CRXoVOgfQonp/zSaw4aoNvbK/Pnd2GdgBzjl3gK5NBzS0dTiPVLB0aXQvH
ppTlTBTKipY0AB2s2Vy/Hkm1gne6yNKVzy0HcB4Hsj7hCQHI7pXeFQtqE4bJ9TK9KldnJ3/6Ezer
MGlfiKLyhvoqbYUJjqipyZUj25WLXo9uS2Hb7DUgK3Tec7z1tyvaiOZJVZ3ckFey+xxxKYLLXVD3
osimiQafaIdpxTcnMG7Q8pAnM7WcRCgS7Ha9O4sOyPAA5XLDrO9mxZAfjLrRMt+WpmzxlVYkSUtb
bKHUZgiGNuNEpBsbVVVQ3GWmK5hVkvzKpcfY79ZHKdAj57VKyEAyocIFoSBOGu3DXRkjKs1k96EA
S6MlfzZq2kstnUKN5J8tMXtsEXmldmk6y/79ir2M+TiZRPV+cCapva6DQhp1lx/F5ZDkq5j0rpYW
LxPwCvDZ2lbX5mwVxWr4J0p6E6waq2DQOury5z8nTR1oR4g33TNuGsaGDXdw3LmBkwpEKHmtULP/
Il4557HRkFG+1vlgfF3NDJkhVNmpKnAoPqziWahQ/NwTQu8GeOTmFE0ZU3MBe77KcK9AUey6cmDX
5iR+5uwi+cIkhXY9gG8gVu5f/c8AqTRuYJem7623NsIrj0Biu+rQuMPxES8kw3+xxf2oK0+5Sg7e
lh2Q2oHbSBySsyKl9vmPTPnp1L4QDRO/PnZwoeB6aj4Y2Fas9SQyP50vIYJXGqdsG1jvIjUzE8PK
Wyupp1KBka20QhUAWtFklTHVYYzZzBrfWQnOIUzqyj9ZwJlO85xuc6X4ecULUcsA+oq2kPSKpVMv
S6vtRE7xAzcG0bWXPSomBVkPyUpQRXHaAtUw5p/s2fd+PTyurGn+lduIe20Fu2Z+ygsoXHmyeEla
NvjNFCnjGSegbQZfcbGXIa3JiVzw4eaElRW4gOweydy2z4bWRVTGGqh2uVZnE0LaSHgWS4dOxVDG
FCsFqmTYdtL1cZnJqxOpprcD5gNEohq/DEcf1tDvKsAwbIGBwXYzje8BgDppDgGe+CwH5Jcal7Mn
N/L1IcLt+BGzEZ7FQHA4f2b4OJFyh/ZO/8Ro9IXi8HQ99unPVV8tMcaZKJZwB0ZQhrS7JUo+UWsf
qRttZaehFc9ydHWPVm60AXjIbTyLENtkw6URiESoQfXu5Y4D0DyHZiaNnGAeJgcpV9DWV38wBqdU
z27cezYkDijbn0Z73Y20LQV+/MsbTJ6ta/iXTSxhFSXV4JCmwxqTykoN9+8rDZZoM4vYu8a4/TAu
OVq+MqQ1r2ZG5Gf7UMaKu9ptjhzq1pp5HznvJMTc5y2F099OwCGVjNx70Obc7RUPe8DcSFGX7oID
zP6h0Rr627dcA8swpckTxaS5hJmQ3DOVGlE+rOoJ8BD1XafRMdpZ+bABSvkKLSJMuXZyYHbVc2gR
IhTfR89qnIe0wuxpiuRFlkSk5mb2efvxQMnkNS/MUmfPbmujR7pBCTGFneyuJM1WJdHEF/KxV1Mz
RCqCQzUAspZqfHEsQvNqSldFnNKoF2UOyf5Ku6NP3YtPa3Xviq+/UNY+Rlw9lkhf/jIGqibsCj8e
m1ebY93RaKKTJsmBcNKnh3nkrhqypRce3d+OX7rVnnsf0ae9CTxJUA8Xcsjc5DF0ohtK9StrEqvj
LXttVmYZjJBSamcyXy7CIcnMnT5ErK1cUp7p3GyBz0rvKRw+LuPmUkswLVsSxNv14784Xs61UMzJ
eqHtD+VaMaCPGAH24JQVGs9UF3X0XdODHdZMAjeWcekRgDZfRy5mzro0t52xgXYwSvTQpBbbBmqt
wZtFwBFD9+a+VqR4HtUFd6iQVU9JnpYaUmOaHA3oMImswNZcuidBpObdTC4ZyGqRZSaxbzHJOrqx
oAh1YYi2XOEztE1VxOolr6oZm8G6CoTuyPulTVBmiEp6HIq0WpYyAwTI/SUxlaYoAehiCAelne0W
mLDHkHA3ABngf3xugiLJcP82O/ptbCj213/czV7YkfyLzSosKz1U8CTXuuIhlbpq61gabbrajSVf
xuElqyS6XmFZgdZihNcsx3mJj3i20UJLHmNh2rYXamubvnYodBAWZVro45+7z/A5krtiPswxs8qR
9T6+TJOzXvxd+4aXO8+EI8BbTbzdkHHzhnMonq4YB367ArwhaLpCT0RmsloHXV9KuBdLUxRK7hn1
TgYGudARTVNLsGtnoxcmIJqGtf1J+2n20ZB6cT5zTVrsBhdAe9+2V7EBTWfyI6AuYeM6ldLzSD4U
3RH19HueRmxth/xYoQYqsUc9iH35QBn5dyyz29lioUnB6NPQ4K27atyStIuu7WDnCRqNxH4cT9dv
pv69TnBNKwUruCciAcdFKQb+nSf1MCjfK9Hp786aBBeftQwJ+Kywf+V57Z1TmmSO1qV/EIulb74D
1qS6vcFmIwL3cs8oKk7nED4Fp9STXHlAXCnayIuZRCyvfMpHtX7bBCpXwYinxXApdl1cZXCod2IL
2U0Pdb8GPMjSfsGhr4LNzV8m/z6Oi8a02BvXRGXkuLp1pcYwBypec9oSCX9P1GWsb07gBw9/qS6y
AMLQm0D1W8k9E4u65rwE1emd6sAA7sQMITlil12acAOHjL5fVz2DaeJWLysEr2+NwrRlKTbHlUJU
c8ugXijABJx5CesNS0SJDvTx6o4qinsGxL6+ivs9EiWTyRIzOZvKRatnmP2NAGYaLMGz/cJIQoCC
8lXT43jRNGfy0TNHzhPbloPIPick10fW/fbfEQ4RROH4qpkXAT+6wfycHevxzMSptLaOYjk1UbeN
WwZZoMNxSIQvpuHjUtiWkcvVtJ5ENKQilIMWwusLtRF8jDp58sdA2GFBDKRqIVLOUXtqvb+QUXOo
53/abJzr/s65zoX9zMMxn9ldGS4AECKSYwgcSbg6PkVQvdWyUiRk/h8KLzQxsps5ZPrg9m5KUhbU
swk/U2Mxhi5Ehzq44cGKuBgsuykW6dYSmpRKL9WUcYdEXwArNXuLz0wVPGikgd5WhJcLxXSmVmZK
GPI5TnVHsC+F5NdgmG+ZAztyMfEmd1JwPCX9ZUrMuI7CCUj2S806Z4Z6Hlfgt2xEtKm0Ugl1XY9g
vpqCOYNEllzYbnbPsaCHMt8A8a15cC/HELXUd8LNygJFw8HnDjahWwhC95o7hq8GrTp1aQsLwE+w
WN0of3wn7EbHuxQDuHO3mojnJDgGINYLDqJZiHJlSHWfzzIaWyhqTT4RqpOxg8RB2Q6Bfp74ZLbN
Y5q4rYB2TxHDMsjDJmaqTHKHFI48IBDvT3aJtncNd4aXYKKb1QF+BLyM8H26gGhfS3dmwXIqxxqs
NFG38QgCVwWr6VIR3dBozX9N4xiZkrX7h+JcCIt/FUrsA6CeJX/2pJbdoMhDujgyWrCDXjUXn0Mv
UFyOadyq0DIfmrRWgewHjeWEMdR3mlWomXBOKEh0PlHk7mOlc6dddaR5e10adx5sQkpKEPmhsZcf
jjm5r47zPERRLJ7VGRIER43MXL+j9AjYO6Jz2YQuMCSsPh0zruRYgVi5CWOBKOTxPyVXyDbwbP24
Myu2VHjWWlQcJ0ohres5FVzMFMikVeWhYQTD1WRmvYDb1ckVG9c/NvvrFzf07Vt+hj+wducefDjC
V1XUvsNL5QM15dE0hjuMqoc5tlhM1752Ov8QH/HsEJvpiuW+fpG1O4e6DTiTg0XN4w9gvM9p+oVu
qScs6f53ngh/p9oLsKBLoBLcxS+0ivgvv2IoXgPJp5SgN10w1IgWVy3EniacTBiyOWsWdkPFNF84
MJ36xXNTIU7AH9DFvnhvirP+vzX8hgsIqEkE0oH3gI07WdNNdtV2jYwnZAIs/uMWJm1n2zfa1qed
HjdgHC5vaiag01/9gZ5oUy8vXDqS1kMVy1NGH8bW2uWmqUTW+rnS3H4KU0Y6Wxk54KPK8dDCo83G
9GS3ed4niBKgnHLYFeIrGEon6KmaAVYP0ZIQs8Krgms3HeFvIclNM34SwSdPjqZVc6Ecz2YQNMer
RsqwTEck+XYWjSvhSeRJnZAJ7dQ/n+EMqPyQjHhFTcnjM+2MYVpCRPSVGXt3U6HUDqAQxN3+Oi0L
y4XvQy9ssyLoLdVdleRC7BOQOzXnkBbfHDjK9z64v/E/5S6sHTCvE4pveSIO4uk6PMsj0u0ZBFjK
dtwUvKPa0SNF9uOj7lN4ogCY3gYC5SB35dywSKSYC9h6cC7kyNYGaeuZVPB55wM7D0NnAHsWDxCd
u7ayrBlLY0KAMNQPsaxqHR3ItfZPXbmOuMHKhCxD/rJ4k9HAFW9eAC5weEM0am3IXHx9WDVhFecx
dSsUGzqN2xRcwUXF97f+hNGInABUpuJ+/Rlx3ka/sYsRPMcHwsumg95pcXwiWgTFXdjTgS+fIP7f
IH22fgWIrJGPbG9ftNum8CNJCT+hAPJqtCjvy3HtrjR2z7WkcfUnislZXL56iiEZY1iB92b8603g
Jdb5kP6IId192oVNogWcxyOv92cvZdTNfOd5zoASt8JlJaypEsGJjzCFTEm7/aZqpYTTxueWL33A
voBy2fthhoxPcdXjxwShRTpuxdg8nlWR3vTi7at2jaP/OG7uW9q3JkZpGEgAhyr+2kMVGS2nntAI
LFe/0/xSGUYhA23go0ZKieIjly5L7ZpfHDnpy0duvBHHl525hhwaGaie4zvRb2k96kI3CoKLtE6q
s+mlI6BehpNQ2aii6x5befLITXinFLyY191Y7BuQg7i8llzQQO9V8nJLWYzDr8Rc4suqTmBwQ4M1
6HnmAFmfeUKTeR+USIwm1ULuGPBst94YMmoaXUY/k7s+nBPo7jogyx1pCxQ5BCiFfR3Ug/I+0y3j
rdrXAThSGQz7moZWNLiTh4QIkDPoC7uBHmeJVe5sFYnBd6hPZAcgtGjN8YPPj84fnX7JNXqq9d+B
9GOSJBP3C8DnyjHH2KUfJOEhHg0O9MGjnBk3gDjQxEyFelasUuF1WqELrA53C0R2XzI11bd+2oUQ
PGHrqWXcb547PlRLnoRfcXEBtuOqpva2I4PzSlikIFaIek8+lL7AR9d9A6PDFVrcwHK/0Y4I9s6n
tGYxd9KqeadcJFELD3oioMmEuE5Y5btnNOwYCNFjrIbb1KHTc6Rg8PSDm/X1Hu0WlRfPeVWu/+kO
Nlh1GMpGQryzu7KupxLqqIaxNa8m3UuNvoexwPLYwjWd1ihN/H1U+77rkO9Kq17qWDYGSAb+AesR
gw9JU+bax+lId4zWbLVKBaF6/V3CWNmjvIpfHWw1L07lmg3OLqD2ZbZvR0xKy3sOlW5vgJGXZLJF
fpUxPaHtpXyFJ5HsghTpU9kPhYhEm99pYs9Srn6YSQw3PTRanM4q8w0yykGITF7LR0zyu5ZK+bzd
IQVpj9Cfz1hHuhIMEGaeCGRRiaD1/5CeEsVRbcx03pjHfXEVfKG5m4DfnjYPIFSDXZ6nTypPSgd4
fq9YDb3RH3OXly+wVlODDcKDyynvC2f22aifmrHPtuh+aGWTXShqMRNTum9b7QFVS1qwv5mRkjtt
dH2hpKfnjaaN85ei9YcJsBpcwc3SjWoK/Dr5GOOQgTLM2QyKc9b6Y/wbvPmkrgiv4b75t+AROZwc
HHMuQqdUUlT67P8bbbKHrTh2m2XwOgsBfDkEXz6yzMr+HBjj0hkKdo5hE2Bbu1/UOoyYcGIsCoLj
6e1Uvx8LsJ4KWa5z442mRMd6i5LKVj3rW78uB1MJy3wcAlvyeQQHCadP3rmNdDg5Kj2gJgbvSCq7
IUu5dSY5K9nf/n8cG8rgsEDE9evLMJnrK9GUNPgq8CmxuOQ0SqRsvRcDrC0H7MKhiu32zs+hh4Z5
m+oKE+yXXoytnz13IrqX6p/uWgeGV9D8PmZ1Fn7dR4lLt1E1ns3/lve3t1CxGVnNxczP9g1ApYpH
b/wNqb/o+/g5OdBLAxzHhF2HImH+dMvmZUEOO8Ad5a2+wsVNaLfoMdWDM80eqcaY9zAp/JwGarJQ
d0fefX/MO9RgZl8eCHrKgv/eOohQekvToh45eNQ6CITkmze4NsxTGpSoLsbMNx1siKxaJlVZW+bm
/wqTUxtkUpV6wD9DL/Ie8rCLeC66RMBrlIgUnFRXI/Om8quJVKEWjXtWEybWV8B0nPcIfmNuFuFt
+GaighWyJu55mud3EDDgXquXI9sgZTibmlDQ4+eSCcAvGFEPu+B4AEJB3xp388ocNOeUQUS+X262
ouTfr6PUvrrYIVg80kehoHvRzgwMErtpdMUDqi2ZdwNzg1pEzYkDid+SFCcuh1Zdvsc8BsnJ0GWs
ikitNbqGd8W33fU5wcGs/9iUSD5YieTI9C9HxtrRJSzGshwNeE4Dv8lXf2HTJgPhhXGNNs12NcDI
Q8P4HC4lGzAiNcKi4ZyQ/smqgULp1Rsh2yG2KpMfnTpz1CkwiQ9kcBBoAt8dErDHXQbkOZgxcnrU
0CqKbQ5rH8R1eIcw0sCjkgXo+jlTMOSh8K65csa9YfXfQebgLb84HN7NvG6jpGvsaVgPI2H9ynHs
AWiqxvbvDYP5HIScXIkEQFE2iTuUx3qv2V0b8TlMLmtHSu8RqyiXAnFgNWA3/UvKKVLAne7rgxID
zFCx//ERLy7aUkdzzCe/Rx5k6noSMYvl/GN8kSztOxlxo0CLxj66khk5ymzPs+uwUGbw1qryCys9
jBKs9qsls9L/F6J4Y9y/Sp4D6Mqpf3l8QdWmcnpyPyhqlLl0Ue+9kGOTWgcJ+Jg69DivdVLv10Ab
Cd4APD73053yTHGZ9TMAm5beQUGfD1/7+4SjOQjEv8TZ2AKkgZ7FSX8sWCi+AcJ5E8c3GnM2oEkT
JCvvPHGB2wE+qko7VPfLPn4NOLV6vkIC+EHsO7fBtwyPpRlSlevLm9h17R/TU7VP5vJkGKxVWnPV
kE2wHeSUqwOD2kDZ6cW0HpkSozkn1XlvLINSQ4DycXce5Xh7g8d3IS3Koe0wkRUMmcaAa3A+Nw5q
iJqgr6Ym5lsBKHnT+2gXDqh14CDf4pE+uBtcieeqo2LgeOdDDXvuBiSTwWMlDJocMwLNXvGdAVgS
l0pEWJDQDCr/HZuIkSvVjbpWe4nrYvI4PH19eZuZktcKaRmyNBPn12Ma+WAxDIKoVBlqk+PNKl/H
kH+7ydNkEn0oPPkcokHoY1PYAZExvDsmV3A4eFVuvgkruiXHLNkypKj/UOEWc105UW8V4sJaMltl
hXQze+jIDUpw9NB1U5gwkFWjyO/5wtV2Xwfo8pEfOhd+12fEJuH4utOQS6hLCOdDLzTZaJw6i7hs
lINZEUFwpnleNdX5emr63MWDxml0Gqr6EcybRBG0/0VY8Lymn4POlYBOWFS/cE0M3fCcOeJboKIO
ZHzl7JCeHcYhqwKZKcMe2CTE29w0+pXp7KkMKBJQqwTb06JHgrC7wi9Frxx1pJ/uWcN6kVqSjfsp
QY1TLuaZL4scUEn37f5zBvCJ5V/9wqPegPVWn4Ku74R+Rn54iVjNkxDPLO+UpuD19wXSUgjAzEJo
Pe8YNWHN4IkuI6ofclCv04xzOlC5dCRnUe440pbZVfJ7V+DWVs90NdnYqSpvkGHsiQjGM4VeZK+k
YijH+wzUaVu7HJfNyVQtDD7WEvYoTnI7Kkma9/puBybP2+Dtsi6/KP9RU45Hvo8MdHlhd1tY4kN9
Le2eX3MVr8HwgbUBNVxqGZR5e+MPo6NnXcEOqjDXSEdrC7fTnCgy2vkyLWHT5qZ3vpCFq5pmVEFo
cU0us7ELWeLfbluwi7tnGfl5tPgEtr6kAB9HiPaDoZRWuG04HjnYYKnGeS3xhkR3hDpum1cWq6Tq
w+TOFxWOEA4vfpbqXKde84VROmxcYpJsGCjK2FiPcUmw2FzFpPY/fksrR7m4xkW8GBRFbqGFW8ns
QvkswlkokT5boSfsiltaBRSEhlpb9k8gEKjNADiIM2ZAWcDZbzDAZ9Td9XrBo/zN9FO5l9bygJ0W
060RHjEZaIbyu6ssFjSraiO7s4XEvTrGC+YxHG4t1fCXtS3nx5B8JBnh8Q14ZeoTmV+bGBKiE9/h
bydceh6l+3ZQR0B87sBGQVm97Yxuof4voqq4RDD5kWDRtJG14d9mGEqQzkOXjEp0J6PZ7W6ul8yl
/SNCD8RVR1GJHsbnxVN6uKpWf/Eg2qi52/LIBfg4f2rTbOX83GPffJ9A6DOPTs9VHOhee6l1qz+B
SZloA/s1d4JxNgbi6iiG/NRc2NOYUhdojat89qbBOb+uB4n9ABlLXO2D98IbfbaienbPBPf3n+uZ
mrlhMlBcUlaJJFKLD0rd4ff+jKVYmbA/Ne7Xc2RIqQDHvTRQeVjY8YpUJWUVJKnDxtwO0/BZ0/Zt
KwaipXjaoAPXZveaSvMrndhLn6RThDjMwTt7zqlrsWuhCv8JRYy2riNGnEl1FmUUIe+ciydnY+/G
cqNBk6PgeOXSiLvTbrFHA2ZJF/nYbo9ZXPz1/8FFC4CrgpsZPPoHN/TlsucQeXlggrvAIJ95bkUd
8GshnN3CFqE9I3IAx1WFpT4OncoeQdYZB2T+DREmAWn8JBYRMwf45fw1L20eXMGDXW8MHaRkHvdw
nqkBci+3V1h1cq2mkuB9usDY3j6r9ZiSBeEYmXzQBDNzsEtjmmtFj4tHL8ig/6ZTHZ8k7EXhDCOj
GtALGaEuO3zAJfDE4lP/LR7EFJlepGgy61f+6wvgNZjWaS93qlPDnpKSeY1+8J+sn2VRcE9PLWew
hiFzkCFnhMAphsyhpTGvy08KhB9G2upq+bYgTlU8zzSSmKpkpnw394nGENvGosvlvTbA5jeks3y8
aMeH5D5xJ95h3zZZ7qRXw0VDpbtWA34rbKN0Hv5Zvw7/qfpH5jX5isfIQtJvYrWtiRiuqVSNEzXa
uhUtTs8g5sYxsUgeEtgilzWw1VmZtfcxhgv2DGDqfNO6rV7tCVs08uA6A3EVvhBnUlsklYd1ZMGz
rlx+2nT6eWxpCrfzfj1rln7dC3j+TlE5/ESeaQa30Db+I32a8FDrIe5/zLEFMwS0Y2DLvDzRHkaF
59s5zpJtO5wHezQNAoQFpSSNgotRWUo8ao6ElKv17Lvk+fUGDH10EJ8jjochPWQVR9fLbmc9gApZ
CdrZGXxzfiq9I2C+ADsIkB5ZxUZQiAUM5n4oGY1FqUtLwYlhFZSKL6AScoDkrG2fJRnxTdbz3sin
g8oJS4eugIdwHb0W/Oamw7pkhau962nAv8w8rkHANoOwXoriLitR3W+pKWV2SjlZ1LxxK8lvemY5
af77JkBu4pDWXODeKwljS/t8JpBGSPD1Qnu6A69FLbSN7Ml59OV9jcTOnBc7R4xRztLBzHenXVeT
x+L4+xILlDg/LGuUmPKUB2X5rTAq7ZCsFuuYqqOc37pBQtkI2/01l1O+0bsUmUWowY0MUB9gM/xo
fjoHsQnCKP8YVXMckz0i0xgquRm5nCThCA4Ke7wul3aF3c1Dq5QYKAEghz8x5zQtezZonz/6zOZ4
frznn17J+T1D6/lutSyFW3hzaMRrpaeiPrVLVyVcHDOVJl1VnKfc6l9Bsc/rKiUtpzYlDz+zvPTt
KRSFsdJ3hV/OEPyQk8Zp28Ay3to40Y/kXxuLrJs8JxUuW3oo2BIRwY9KswDOariPre82yD7SVqFl
xrz/n40W3nijAYiRk+7vbac2dwtb1HDdiw/BT9l8ikrRzf0h8gDjWxQ8XrbOwkd9J+QbmPHHl3Na
zSXxqdImqmJKxNKtGDvs3vkWij+Zj/SbaBI4wP+1ZfpuUPODuPvtWmuzGnEyP3YoO6U+f5em16CO
iCFattt+DhZ6t2bWOssuI/zjvItFVfX1/gTCOtv/2oTRrZ6aCQPCPpuiyIyz75bG1MiiBe2fOi4P
k53TlZZSr5PnU/v1Q1UT/QLaTEU+GsgLUfRIkjDrjbZm5fkXBCch9UUCv3jcXxWunNAv6DGEYxtF
Fs2g8SJ1f3iBoG7M8UTvcd7H8HQbxsnD3v6zN9oa/RaM4GE/XTHmXQvfMArpQF5tjXNPS5S7lbmO
D2zJU6OnZu/XQTpNA2lGZkV2tDXeCiw/W29sRpaDYb4iFnNYg0uVXHLszQbsxeo48MgWUWpFMkKG
BupZ0CI6peYp2xxkMIyi7+sKuR0RUVAgM3fYCCjCh0DMo9hriKbgcrIcdR7PLai2cdfq48FHUE1O
qOjl17mG30PZHVu9eoFm5BB1eXjEQWTpFEDaYC6FGoOAfaOFgjZ09F9pOvWAMKTR1LrbSD0L9ZJr
5N1HI5hLxOd6rvslxtXcJPKNUyufisKLeO2yA/ysj5FtQ+qh8B+p6KJHSxJ0WsrVtAFgPWKd9UzG
JcYCoHDZ9PDDK+bZsqil+ZtOVlhpG/Px82jFj0dxFvEHMYhMNRhFIAVkoCv/dhDbSZuSCihVZaKJ
yHz6AxK3shbXIDgI1hOlKMTBIJ3+iKcW8wRLRe9PZOgp3a5O6w5aM1ZcYjyhwMVVc6fAlFya6suf
bgO68cA+KZuAHd+YoXUSrp2KIljmsGmlJ67rAlVJusVS4P+8+iNS/hnDuwtzf2AwcgrV2NNDxOBw
j7RigMiH2lel5+/+gC9yzlt6sLauPmZtuZ9b3iblpc6JOCfowJLGZEd8Fnly1vD9MF8m+8vcHcX9
IIic98omcmrESSpcaWCIcGzmfC5QQbh9oiGYAiD5SrfE/s4luC7KRoRseC+mi7UO4gXOGt79cbnC
cHFXEOkV73XAquxm/Kh7HB1x9k5BWB9ZwstpNTj/uibo7fhfTt22qjUSPYG8jnnxW2zGv9zdXdIC
aQd2XXPsCi8BR0DSGWYHMA2xFJ9Q2xhcjhzaG08bpCchXULGJTGtclrOmtRWBHRtGrpMXFI6tvs0
5bBpUxI5GPR6FOGBoKW6JMy0HGKH8mtvFM5ZRJfpiEGchtjlJiFF+OWu7W/T3Esn+tLv6NHaAKaO
CA0Z0mevGMi3wwFbksEiqCw1FR0mjrPOQ8SRx6GIKB75Xe6ztzkmA4Dw8yJyku49M9nu+L6mTKMU
LJ2Y+WH5CxdOfNB9n4oCGxrsZtvQLcDgkyWV723DJQjeylC7J8VCEiQllzwnURhHPZLSTwwd3Axj
L74LUKDSNWVflFOkzaNg2F44TKbG/yyKow5atzLk3GRtITK/RVRLgGujzQENKO8vqCjj81oBkd6j
skKQpH0jsxynpVakJkPf9ztfwX1MlMuHtZ/hqOq2TnW7d66Nr1o6tHfIIreEUCXr/VoLaBDVIOuN
JYF8JXJM4yL3jtkHVDCDxGqdNyIrbvgenuMFc5pr2w5DlYqLMVdS+4ZkolbpleDiMlstrw00zWTY
PUZiRZNPU42Zty1ivm56AUkSkNyL9UHR6tMca1Qc+moc4ZVIt0fUvxQm0hndYS8nI6fpPpa+2G+Z
fyC3MECf89vF9PuQtFVNvy9XqnuRBLLdq8GHQg4Y5xNRrRj3jLR235vlPkcAJ0SjzLAxmCfydheP
nnZxUtqaD4X1XKmkEN++8bDwkiLxFoVOICjfKL7P1kcjYHs9U9AiAftb1K8A3kO2BNaV8r5OJ2S1
uCgHPTAVKgPBreD1qE9Y7TRv1lIM5NaA26jGynjqGHwWln4wQi9DB8iEqi6UQ3VJvb+0i2kpj1pa
Kxg6wiyLtv0RP4KbFTVoslj1w8yjJg0wEqoc45+M70IzaysmTCguo+ZX7Gg1+hzyjvw2GN4NpeDr
WfRK1nkbfHpChkc4kl6LaRHxJYfyXwD/iB7JMIikghPv72BJuzmKZjD26o+leLyKlGJZ2XLqnQ2p
6T8sgoqsmYueUEcz3jdOiVtXhlSelRSRlOpW9PxDNzGpjsK2129aB9ggtCHjTRCqhTxYgAxjVhWW
8r0eFwRKEES+34bbRiA17G7kZKNU8eF2x1j3P5Ze8AHfp1ETV/05clkHvCNkYnPYMjwkKiEcx5dC
ibYu+XrFMoAiv2Hp0isPHlhYIRFH1OdQEdMOlAOSn8deidaMOfP08m4XlPqIuN+CgosszSyh5gD5
kr1J4YqLKDf2DYggEwdZZypwdkHniiv6wfc73zSgUAUKpWa3qL6oPFBT4WqNqGCagkd80y4635z4
bH5BV2qyhSQLNGB3HSS4RIfl/ltdlzbj9v7/Hy34sn/HZyJsNhZlpSimSZCMegxYmoshZZdHlkMG
zsZVb285nhW81XRtygX7xyOZhvTSdWyuqUrygXZ+j7ea+IEJS3WHWd8rMwmX8aYNBDmGmlLl3OfR
1QVTheObOAFMEFVJUXmIbCW+Z2hR2YiEDMcyLG2mALnmiKDxcUZewoikpSfDK1NuIpga24EiRqig
nvsM6zz3anLtzQ24SGvngg90cOwuqYUzwODs1JXO/UmKgyQNnHjFP6Q9FAqPLyqRobRDBeSPuJ1f
dQgAjaaLSomgAW5u+HQ7YlDbfXZmEN3jqoyk/ZA9c4umby42eNGvlwWUMcEJHj4V4jF1ZANKcEQt
2Ah36JoriVzBIukipoBNvmQ9iTTWFJiDf5ygo2QPNxwF/ets/kXk97ww7xhZEngGk2V6HWKmpQVT
UViLjh8Ndr62YQfYkXtH5HNl8hQXsjpdUdjqdciSJoFbeZo6tyGRnf6Kgi04PICkjYcFSawgyho6
YAyZ8DePhlookH5CMXMnOHKXaZ9PDvKGfMelz5QmLfYnK0eEn+WC9lG2o0ds1SzsYU7ykquzSfN4
4FKsHIRVOqAOUWp4dSZSS7nonBeKxy0S1Efa1KG4PXcQ3o2M6a+WHKleVmf64nixYZ1bCmEA7Lb/
U22k09GR14L2O0/dgfrXvTMAQ5x5SuN790HviOS828uP5YSiLoFzrl/gRImHEzesnXLqpJkxYikb
HIiaWVqAqaV++3ealRoqw5rk4LheDxL15yJxDCX9+mnVlIlNp10RFArS/Gvvb/mLqHOjQCEjdXwc
+nIY4rJTwimFGWg/UeY0q2RybR8EL6/AAmDNptKs0BwVP5BSBIEEUfZZb9oh2ZVT/3vyzoHhb4cJ
UU2nGvK8Ze14/BO9E6DzU3MJ9V6QimXrTLbahfLpThnmtAONf3WtVxKii+H8c4NeiBmD5t098/06
/3AlStUMharR9vXb2ysVTinmPBG04o214LAQhi5chNznwMBZs2xnqNVahFn7kUI/176+cVJLMjL+
mQ+pMZqCvNJIdCFYa0Up80lmzy1Kvx3S2qVHIC+smtPckHBTtymzJtMqvgoutLblehTkr9VDxWTW
2FzJSFe6i6ud1Ks4MbDMBYp9BAw+e0rA9V+RGYvnVaDm1tbRCZRTS7LWsvA10MfpcsXPI1uPNS1S
otlDdvn6lkkwXU0PjVrpDO/fsGB+oRA3zu60I8rUNaPc8Y3/x4AKeHgGP+55KWXa0Ijps/bQtMgU
xRcD6leAr/ej7TbjIK/lIVfcncD/SJCdYKaG7zb8BnakKPWLDYCpCGGO/2cW9jv5WgcDeSybO0qa
tQLq8TUNiSzPR2QokXhE72s3bwhbijxUMDv9eMLltm8VUeeyZRs3v5W8SlsIXxMANc2R80ILp+4V
VwMl66CWGKk+iRmYMA1qC5jmwQfTnut2YI3ZcGYuqyHprazNRr4muT6Tb+HwFb2Odpu2AFe8WLem
IFfPmEXIVHRqMlmMPZaqDuchIBo9Qip134y1sPqqijHbS8QeM8bsKJDPZLl0/LObaokfAhn3bIjC
KXEOZZyLVzWDyXOTG4/S28UX/IymQkQtrchAa4MAGvkG4hVwpnkJ4Ws6uB7v1QUPuwcRbXw+HPE0
O9oZUEX0GhbdvsKCeW8Gh85U14ql5C9spwH156xgscVM0rLpNjiUCvXo8py86o628QV9hfU7dPRB
tPo2obolMpWJsKuMxYSGHH7ey2b7lhvoERtMRtGBpt0J/nzwtdKcgd1f940UsCUeQkBXk0FH6Qbt
kbtV+5kyKK15FqScqnQU5dPkPv2JPUjj+zSiwHiTZ/mTH6luIC8MwdGVEacLPxUJTjZ3lCJF79tH
w9bNbUxMSxTrKwIhSImdHcQKqsrmRNJWKINeyhgmzcqM7zFjXS8aik9pFDk8bk18lzKfOpwxHwSt
6iABG35XFbVpAcbQ4mI76mEtQaIOp6uRvjrtLDZPj5eYnHF1j58hn6xdKyXWCjymf+8eoGshU3t7
wa51CKUWqr5xMZEwhcfCfdW6PTURUBikmR/VvHR0ArJ8XK/Xucy1nj3jXrA/GqKKVliR68CC1fEA
ViTBVKqwXg009AnLhTkUFD3xzjBdmGfybm9C0vqAkxtHmms2laiLoc9E4+FLkf6OK86TFuUyI+is
+7XSVFevBRiJrGBOsayAqvOeKg3wcBaIzL88HJkA/Ls+j2tt6PthTmzeTuQTeEgHhqVwb88eRBwy
xNBZLfgARUBmMQt5Wt2xCAAkYwFNMyUFLopZtSnEWTWGVVxxT9IVINFX3S+wDJAjpc5e6nsoTgTh
sC2DW0Uvg+WSgvwJ+cStLhYuMOQa54LQQQzlAbE8wIhFzc2Aq2ehqBTaJCPUwaH/NoKC4V8cFORS
DEOpSUJzEmAQOOvp8TKFj6iZ36GWuhLetIenFZiRh/KPjkDofO4stPeIruF1vtEk7dkBPr7N3Ew4
9zsJx7JQqYOSzmSUYemQpMwFOsQwN8mTGEqYS0MVEWuJYqKgO3Ge92Aaqq3BTcHS6uX4S8SgLmlp
arHKzh3zM9l4sXwOdUqjZKMMz/jOYjt2ySTeVRdM3J90nE11KmmQGKgSLT+7tD2mkev3ivvaYlJk
Tffn+JuSzEGY3/py8MobWelNMZNYHZa8jN5yADpR2WuLHi13Rtg1tkqr5XGx7B/HW8wVrGAm5v2O
iACHKGAuSs6L+MA3e7QirsLdi9hbZzXFmQgxmiwVuHVJ1va29Tm7KOrU6u6QdogzR2wRaKkJRlU0
dmXY7YXpY7qiJ+3BBSHaKAQpXIotqZXJm9PF/cdX0BBY6Nru5PjxZ67TinIAnzENgi7IsPRuJ+cr
tMZQFE5UVKT/tGhb3/xcS4nOD42zB9lizjxeGp7YASRA7CZLldvs910MyEbo+siwQnZk5hRW+Gnq
j/iUgRgSylJE6WjpkPsYar/SSBtBAZVydm0uBAKuGijmhYN0ilz4wI/TiEIRJ1eSj8nka4Ycbkjj
ZFj7FS08fjE51DQDsS7U5Uf7J1Tz9Vx40prxxPQ1j3mnQivgXwCW4PAud1Ka24Nzar94wOz1BNq8
eiV1c8ZNoJJc9At4QeiKj3ZWr7/xpojGAaUMxYsJ3j193/SFLclEpJWwBxJQUKNWh0fDkryDvQZc
ByWZr8jG8dw6ykSgR/RbZvc9GBvfj/fqhOnw4DADOxBxImBdHjAS+Fe27kYXI854hIHf0pWKZtQf
tb5tqHn0gS2tkXq95AIBp/cQs+LYqjWgSA9Z8hB6AYh78RxhzL01RkmyFqRkbI6K42LmVoAoLRXH
i/23lnkiUir/vbO/ujR5CXanKCWD0IdSldXreGXBPE5R9p3pFeBe4FrXsQE8QqU3m4356LqGG+FC
eknB+1F2Bmsj1TDPR9UVzt6sw8eA/4RLxXM3xsZLIO0DzddC6UrrKeuU24z2tU/ArEESNhULA8EU
sA1Pq/j0ef3IJk4XzoMF/EQ/5y/JZj5Io+PADT+6zdz8vkAC9g5G8P6VjOuNb51h1wMTVb6cpXZP
3AfqsTcJTHhOL6Z9gPJp0MoudRiWprbpQwaeEutrmMZtWGdg6czpwfkBOBLwUr6717O/6gH8jyDg
/z+ibpDaGVhujYb8xv3x4ht+Pm92vjVxKK9hmGqeCBFiXa7WDBIOpax/iT8K8y5Ae3jrvB/w9zne
VjY4asxAxbpImv8+gEk1rRM+aeyQlcadZc04JCGCv6wN4q+Bkc1gIYDR5gk+ChMVj7bahZ9dEGCq
HWDRJEcg7kdE8f7sOGR1KOojmoDmf/ZKGJdK2EojdJnpQDfRoFMyW0225cXqqYao8XI5NrLMph0z
8CQx2rJyxJUAw4FKdLJzkze8lhjyh1SwSFs5q5nkxbbPsPM5BwaD3bHuvzgv2+6ua8Hld736/eD2
C3Py1ei1d3NQIsM7zad53GmQKHkl6Gdnn5YOqXBrF4G3nK8HK/Zvy/NO4xNunHhdDGi/FU0UlHH2
IUXcdEON7eUgKvPSbiL5jB0/aWFZns0Y0RNEQkRyhCbRtbTBcV/3BdStrC9FbMSm0U8y7g7BV7qi
1vL3nKZuX4QxG5iqEmKieNZ3ZTjaih1eezKMgCNdqVzjTWg0AuvT43hqvQcmvj92cfJ6SNq3JRp7
bLSA3Cq3HyYocQSX57sgaar3CdArQywnWGdxQ2ShDeDzOif3aaE+iYyLRbhKsI2YSzICZuPrQG6t
4ot5jyrkZNWFuM7JEBI1pV1UmKe9Arh8zcIfBs50wAJrDJkLoIlBkYSUSPRcTabAbhbi92rvENYS
mBj/phes1eXAMK0nhq1A+UcxbNX6fdvPhNwtO5y2ApqzO4mzjQoxqBAnY5dMVfB1Zxu9vDL4ZcnO
ApKLQQ+mL+31DP6mqZPvH/ZWPcRXbTVYqippO0jYCQBZJMrKpPxLgQZbt1ExzNVYNwcQb2TI75nQ
slGvl0TDR5gItBZhpLpvtfvR/JGtPjZrkZpSatOi+uGPYsNGC/D/3HBEhSTBIOxrINBTGbjxFt2C
LHoadyyrQxB2zyLVBxGT4NpNCXzQri3Ay+ixLvyIM64pz4wAzvWvuq5WccX9wLdJyTHr7W+f7OvL
iJ7I/n/l34Rv1I9KmyPI8Y4wRHTMxptwpUbXKOq6HndDAKk2wTlhEtwRTA8wJ+kBVfxPJ0tQXly0
WujqQhOY1gsYcfL2ijM48tf6827w190SH0pvtoXh3VsLbWenVmYLRpy9vtWZS0mFHjQzcOFZz/U1
2qSUWbL7GDOOM6D9Mbbc3d46yROBG7pF2JwdvO8U8EUYL/YvgcNdaBWpRvXXP3e2vq0CwJHSK1R8
yPO6zBowXtbRaGSKK6dgn5oRDBdYHMiMiSvOxn2PWz5swk9vcJkUtYv6jJRdxTChB/T4ExdPgu6R
WRa8jyYnVQUdekA2zn6Z9/YcabqdpsZH8A3XadO/LW8PZAReqEeU0TipxF7Zlb7UD112WmzxgTHp
0sDTkCjpmlljLnlbPEKSfpcDNl6RvR38GpixIpyTKAl0h+yINM+OdNcDl9dACLnHX/67AyDPjr3b
6NYLMPnhGmMRvtwneyndKY0ZEzzLYWHhPthCh04Rzj2n+QhuelFkNnPdm4NIg3wIV9eHUHDhGkKJ
HAComoCtci5KpFV3fd7g4JMZh+0XCIMgEyQ8c583aRu23wLwz7YVVBPdABx84Ruu/McqiUdPBVLe
9j6xltC/dMjxU4F4wuHiKBZzLZ9WiryeYU2MPlsc5V+XkhniztaicjmlkGRrLffJi9HTHJAEXSuq
hZBfEWmrQL0lP8iTzFHHUFeXYIvKE2vnsJR1t5BzHf6ZES6XH3pHYbYR7xpXSn0K3uH8sQeG9GUj
FCXktjHYa7CUzD1yZYLYktVTiaoVnIr5YZKDZhRW7MKpCRpuM7ChcB1bPYTvHd/nuwlxxmOw9PHD
7NGQg0Bn8l7CTudOdIt02jyPK6ygwpGU+M2+RH2NgWChCZLEpu9m7tMmdmhKW91Z1ePKyXeIhH6U
Ie4HZhtRhQebVqMubE86rkq1xj43gsXJYzfcDEUtdk9CjUZi4KNtP5SaOk+wX1iSsxazKO2miAKZ
9zC+EarXNyCyavwO2FZ2bqCJcyWgRUT7a4fFvLuj7oQOw9TfQj/MTMUoetJ4QEcMdaxIY7h8dciY
pSaCseVBB77HaeSu0ZpyqYlSepEKz+3horcG2mCey+7dpv2HRHaQxxc/79Stczvkf2z1EMfIOrTv
ITWkTVKP9bvyJ20cOChsxJoP/dtq41y1tzJmxK8ANjQJnR7YNuH680mxhynERwxyxbKSWm+CGyrl
KC5H/MDt6PnGyXc1OMkOoNxBuMcNrLFJRwOs566FxyxPBBwBZKz9pCRmHbYzqguPcgyDtnc1VXno
IaADgUZ5WbweeoWYRSnH4ZdWgDrqkHkp26P+8/B27x7MH7nRSzFwYQI/dBus/ZD7e4AVs2EhD+28
H/05/osi1Pfb2xns1tDfCS3C0iTJg6pmSPVo49mcNrNjxFj871GLh2qBKm+FSUT5/96BC+gUPBx+
p+TEsZ7VQ62M9LNrWEBfmWj2M02FFtWqCVkpZXiclCMKFbRf/whsnYkYZnqvHrV3Jw4V7VOJ5q4w
NTiJRRKcEyhfmZpaIcc6YIaRrp3CZshV+MoewWtCrkQfxZnJinFy9OOqQBNd/96tBiUJufXlb5O5
mHDxmdM83QRsfT806CiSovBtrv3jsiJ37jFFU/TuT8UTHzqJbA5ruUa5YRY/QghEOdw3cQ2bI2G1
Uh8hOxEyg/gusnZEcA8ExPn9D1x9IYOPMexOMZr6s1nK6sk10+gmVHV5G7arCwDc37UCyJAz1HV8
YT3jPSwSgXpm0vFfbSqt2S3Zco/sDh0sTCXtSH7/LSXLA5M/FKucmwXrjuaDEnmDN268MWX/30k0
NB7smsq0hImaqBWej8yyLeBWhLt44Ah0oOqhZF/+RhfWOnRPluXfsCjErfsHZ7P5krdaNGaxyHZg
YS2DEvkcGD5EOyxK6waOqjrlocYuHtCCzEZnseeAq1p4na2kEBr1XKZPxHdnl8GL6smI4CQHE9Ie
8QeEnmRdsMyph6XVwlOiAloWnfisw/FMzzuEdpU4nW7PZ9fdcdZ/PclPxDgf0UxgcPBCmGO8i/F0
zSUULu2claNtSeMDr8Vvv0Wev8caIfT3P4yQQaCNwZ3UFMrmGMIKHdt9SS2ZCYke81nFv10jDmyw
/nEX+/SO7UZVCnbHEKfhXLMJcDX0pkJfxgGZxYhZUXjyAMTVA5i4OFp+QuxEvskVSxHzJjio9crO
QQIAJNIWwzZ+Ayk2/5+LQAShRYDKBa5ZesMBJ6CcxW+AL2fwBVS2AZxDEdgq3YBo107OA+Dp7xMb
JkQYHVBuQOGmh7/gya84mntEfW5p4/eAgeaJ/xR1lb0/x6Z/JW1foU9yBT5iQLZe5XDbYN2ysp+G
xHsFdwgvdpM6Fou3/Xxoq7O2nEoNwrm7jE7WygRVVtR+bOWw7GYIFjnHGsnllqghKZtb8WQjUEN2
wr47saf+8FGDfm73rGtSdW1d95yj36rhHLlcMfEnFMWReCh8JbIHRJCMlmCdRpDuforB9rCfN0f3
LXElhJHZvVNu+PYs1+OLnS4JwHJVkm7sC6ZSD9S+NncPZ1T+ADbzBZ+evNIl+zPuMSfgkICX1iPZ
Jk7k9Yb9YmyqF8gCTr3u+MjEihRSA15tWH2gyDTRDPUBA076EAaE+LrPuJ4eyFTT5eKTFkQ0JQI4
xE95MLfs9P8a/cziEKxbcl0pXnABbtq1L1Ban9Y5rgdL8nTXbR/u9Se5i/aS3LVdEr+JAj5yCsXk
7VT0zOsgnBOr0+hPwx9RqY5AhFbc0SPdeQYRbA/RDgzltz+Uop8Iw/DKLNSzIxHNXe+5gArYZuy+
gAVcKIwkFebK2rBg5+FleiVlaj17ZqI0WaaMX/fbGHMHYFAY5qAywCwKZiK7phfQsbTMGt9DgXhM
CNEIn78hTvmCe90eEgedIC+3j6rABJDOhd4OMHjkIiq1wdURGvNAxJU5ovPTgWPILHGdBA2jC0Xo
2TlLxBmeqi105x8deCpC6ncdhgz2XBggcqwZXgucTp4lzXUBbyBmxfAg3zl78B6ZMeB0mtSRy8cY
9c5GrwJWmUfmzKg7PX8LKh/P6YkJVoA+ytdlmx3Tk5nBXiBTmCZOv08lBMlI9HwlduRUs92THNH3
vlFSQv7zT5iPr5FQcmi2tKNegfHtFYaZ79mwlicsHxCMAaNXE/sIUnrGBMi98kRTkFekhxr7yq1h
sW0vJt3eDHk8EIu5rmTjaXIEReYZZU7VrwDa3gQbWpt7rhdjMxe5tuhZ7qUzjJDxFakyHAN8Wq5f
/FvtEkTWJEtE6zi7mm16NGJ/Rqk62TCTAWT/4DU+MjVoroEimgRfV57KqJnffFe+dnMpih+IBRYv
PKU8AL3ZL1mUtIhnmKWliyzlt6eM7R7+tWJNro+4UH81Btayg6jMy7Lqipp1kTxCp/QzW8hQiFw+
9sX8tu7P5kDnV3mDAvL1LV/LYKAHyPUkksLEjWEtvHXQ8beKMjP4ma6/OtYZrB4GA3hDxLdEfx5j
nPUkpsp2iWcUbJ+dRyIPGIteYqPi6x8N/PRCevYNYsnx6gccV09LEWik/fU0NNr3i9n26bD9X1+s
amD2xuqoOQVw4gFcEyN955gYwEqj3cogdb2EeplwJcQqfVhHJ8pxF4a7kVx8NEaNg9tiSJbclwci
kwbPG1MnVQAfBYMkuCJG+5pm9kx4c2vkbdt6vapBh9Aj4MQ+O4aZ8G/vTNdfBzF41qwaJnpraND5
d7wmoDB7xvCJsdEreCZdKys8FqgM6pMi3iBSyLtLHOqACZjByq8x7MSW/4RvL6njS0NQKWZzWIBo
eC5Q2urhE4FnXWt05Ce46cCYHEbXoK+CdzQRqrq2zxIwhcaZmzUzEOOf2l+cZtNcJXKfUMKSpheg
hdzdH2ya1EME/xOn+LSKGag/23nFwDBATsoe8fUgGfV5/4eCuAD609SYFUEhDFCZJe25lJemAxba
7lOEDHSqzZJteVxYDBvOZbGeyOivCCKn8FLe4p5QwoaazQCTNEKUHeDTMp/32NW/qCC7i1MFsDRA
BOcCZoacQmyo1n8Elvmc7qBbzn2lTJb3mIQh2hFUs9/n+MSpcfOCrmOK70XT+LhEtSRxM+gc5Vdf
eQGBLNywAE0rKJj+uKade4tiG1PAWKyh7z5pPvTWT4BmFUWonE/M9PQQwkDKTthFeduaLgH9iiwa
InLIYHqjXa/O6rhfUqDCTMLRg9r/Duz+Qg3onT8SxM5Hr/e6SEKUzrqytPnR4ynkjcROOKOv6HzA
ZC152JknN2xrWYewIBF5JpwCaUEqhugDg8F1IoMiJ14w9Y4kQxtPJA7Xk53ITBj19+miqTyMokG+
kg+JSEOZzKB5dRKmFcGeKL+sIfsw2/86LB11Zg5grfVhvA+4Wjz49eSY/ZS7QBjSaFTJF+6nd/Wa
HdvBbKP1YUfkO/pf1RAHGlZNJcj394P4C3sjzWM+Bex1zyfiE3NL0MfTFDHSsdDlx1oQwAy5FkKB
f8FXIeiTjgdQEj4u57sjN0Xqn1sOqYMaF+4/OPreF2mG2trdOD4ftzICHCMy2w90ioGGLoAJTJuq
11hATo5Gzi0s4a6GGWXbqH4/T3BHDwJQLctK4GVk7czCDJ+OvcWlRBRuWgtuEpZwCIuYoGgI0+cM
6ABi138+vsO6CdFfANMZSaepO9rnHx6OsH4cV7Zz7o01B0GomexCIBZKpDdOuzL4DfMnAWMw6uC7
oE51RoQicBVQ5/6azypr1229KbWRO9s0duWLn0Md2Bq1CH+aJ3gRoByOUwydP7iHos7jM4G4joJh
lCfJC8pRp987mGbySdaWrzt3DsuY69Zq+1nfRys5S01D2iVBu+diAyGgO6aVTBeye9VsKwFp9BRt
0Ola34WeDggRjXPaLfYNI3t+Y/XWZdYEPwUgEHB0kB6N5okLqIUNFSE9bR24rFSyZ/7/IeEPPGBr
laqUZ/LUXyLQfmiFlfq4rkXSgoFiXtG00idVhJ6WXnhrRi0iJyTsDNB3bEhHgEIR/qnlXjib/ScP
3bgb6E4TDfPi2BWrsS7x927a8ujU9V7HxTJw4lw7bILygrFGWeW7DJr1SNOX8zDPrQFnKSe3tT5c
gJIMVMlORcUz+BdVAfgzuC/iZbQhF4lDH6NQj7RPgGbOtYW2M0mb/upSUNwBJ7+3Qmo7Yb16SNrd
rn0FV+1vPNncz6WhkKh2cTSKwALfB2HovcYRkWGH9z0lMlQPGYeHGsk82FYnrLEBL64dBRuT6U/8
dK1D5w2DYwVTVI70T1lVuCAtUgJPLgVcmKzBsRRRyx08REhYQtQFXFpU76jqzhjAF70WzyTDkegO
6xFdq5YXayP527tyhlUraFlYlv5JdJK2F3YPjFMxuQ9O7lCm7FEyAjQLhv+W6aEoxR0EBsYiTgH1
O8fgdk/8h+w+VAEvWVkgfVBdQ4GngiyPKq+WDIV4uQUF2KLlHURaq7u2vDXaZplJBIKsxlG0lV4I
BQqaCPaPQneSF86N1CRoAUrOSAshg+Mzgf6h9uvRmXwuY+n78Y/tSeE6FIzlI/jPb2OmwIcPMvl5
0MvC+gpeDatmPQQv5bUPiDEIm2fsNSdS3AwIyCcLn5ine5LDyho5L8UEhC/swEDgI+UFj6svE7gG
p4xKPJ9Qv+o83A8DdXtiW7wMWM11G+YYsB/joCsBcMy7roweP/PEXC6lOVa74aJddnEc17SuqKJ2
0NyuZEyWPUsLpArzZKKD+mvkjqt42erLXidrTtk0wR3aO/4kJfhzP9VZS0R8aKRbd+meJjQ4Y0tQ
Er95XiYDrm4mwZIPzHFeHteU6VQ/ds3uiDRnPzeXwbww+BenFRqGr7AK6JhylAdfnmuZNm0T5bkq
G1i3KNLPXPwpCA4yC/tH+ZJ2rNXwGQT4hiopJkf73kgST7vI9iywN2OWGEPYYlGp1Dv/j5RtABYR
62mlGFgcGdz9Mq3qSWjjg3ycr8JL0LJa0Xw9IXOR71d95yq1gHv/OwQBzrxE9n1g+O3BbjWYrCxe
fia5SWoGceZIZRcUWlBADsBEvCO+75hGIDzQ7n6x+Db8gMYDWjTkaCq3ITWC/gZ+YM+68X6rSkMX
AJe/B5zYwjV2LnAwlBGJuUaZoIePEp62lYHrHLHmFJHXrdoPvmEVVpljowTyRqgfILtYBCKC6Llm
qz+XGVxzk/dMH7n5NRz4GI8Xxony8jqM44UCN9YlUPlTZwvzGiikLJ0rFaue7pHE+Mm9kMP5zUa7
8CS22ibhUvNPkyPP1SC7CQm9YAbPlT80ziSF6CjezR4lVkPWUytVQ1pKQp6NblqwJCIC7yyu19lY
pCPBfYzWeh/c5ojZUt/xSVT/CTctwIICyIRlAEGp38lhZeLXA6jFJNlo0ISEovHhHHfwYQtkI2p6
wgOUn5ALNQo75/vmh0esXN57ZUh/kOhcqvOmvIayDmoDHLjhN+XFeECAM2MRBinQimRlwo+8ic0W
nsE6oy4orxDb6zKguiDOsiIGO3p5QiNP6CDdTAx3x3+FVXhlz3rZzVtcM1MWmvaVz273XgOYok2p
edKS8tyKdVOyn9AKnR3sTdUbmJ8KjnsVydvBVw4qfO9feXnEGHyBMbXJr3yYUKTqGleowOogK1bu
mIy5miaIRqTA61KeHIc5D6tb9X8UktP/pd+5jEst7nPUD0f3FLYIcNWcOSBMqnMeKDw2eBx5Oo9j
MXty5J4F14asaUMNQMChgEH7UBd2TMLw4VopxBWZSRlsINAG20F4AD3MNauYAM07e/DfHbkYrdDD
pV1gkPZXnYQ/qU0Dnb+uVOZwYFSxNUljvzwSxtjuiQ2xjrwyQRFO45jSenTC4dHEVvu+w8XSJ/TY
ZWa50wCMyQj7WNLtyp4lNWzMhfKd7Gt3zbvy+uTeFEYIrIYgvez/yfPo24YpnE6K1TRRb1aLkZZt
1VPR4MF2QL4ipC8hxAX7m9u2XHCCHccbiOIis8sm493qnUGsQ67kxL8yA9uN5TO+X43f7ewbZhiP
WTBBxk9tSDIE5uJ4zP3Ugvv67KiP+XXd5kNE8DlghaBYfB5U5f5bYcKzOWH77R4iM3sX3GvcfIEb
YVLbp5n1spvsrzKEvbjHTlOg7+d3T7MOBa//sqe5vldL80b7D++gG/rvyMeDAH3u3rH5+gKu+V6x
brbkzleCYETNEp3q88xZWecoOi2Vg2IRTpZWIQHtMH2P9tFkf9288vuFfTasjz+4ryxViXj1S1BT
bpHaHrcqm/P6ovNlBjSDnTKnQd3hmy4IqapEmJEtZLV1L0n7dFIzVEd0a0cOdbwPwyNY/EelxGi2
GAfHXGVxXRsgUX8rOizQWuulHXJVLDH3UsOCo/2cStnK0fboQL8KavRFQ3c8//v5SYUUz4Ch4LmB
pBmR5uLOxybiBLR9k9mHpMx3TnCMJsqAWqncgWqg+9oh2b/FiXXANC61LRfam8hD5RfdI6HJlvSl
i13HX7kdHdDY/bSRj/rRcgR1lu9NqG8Vy3zbmqgc2stxpCMQLyH8MHD0Sp4w2KCXJADRfh9cfcoj
0yRhkzLhffxFxmZ+MdZdtMz9fae+PTTD+9EN/nAuxBEclLpkEkMNk7o7FzoiRC38yc2qeMJe+izL
PUjJ2MNHjqsA+AiyYJojzh/bi0r7y1jSQEqul6iUXdPslNtIVAP8tuSE4K/9bK7vmKIzsLBmepCj
ZkKDPUhhbeVfOpMA1LV7xwalgXlrOIHyCMJttmhK1/IB6rpwsQyRIXqKve8npVqVYZ8v3BluDoDK
m7LzFTcpzWAWzBXoc7fEm8z4M77eIJjlG4AXGtbFrrOmVhH/q9iCJ3ejjffvOAKgh9ua4I+pxFpT
m45IpPFCdQWHKlgxfjsKzboWJTX5xP1k9vIXdqqoYRxkAtoLk5lZJUuICBBHVYKrcR+cQxkq0Ksy
hS6QaTE1CeGcN8PH6s1uC7CTkK5Qt0AKFy90SMYILB8OtpajOUSLia/PRDvtfewBxXyfz/iUH0df
4+32Ai3x8mQ/JDVVaxNbnezAFmxdUnjY/n267JhNF3tm6bx+Tf5rxzUmJUOD7lnjah6QkLv8svog
QUqMiRswqwsAeOkvWzvFjD0nOTofNdVG+s5Hm4tK7iKzn6aS56g7e6IHxpzGG/FZ7HoBywZkfDRL
H2qI8v+Z42zpNj8VHROXC51qojiZmtcAt6CIT0bJifPlM5nAi1LxdyLuZxavCWP9wP/GsBaKJPbR
BOcYxzCdA9HZLvwfYnYwINQAcDxf9BvxrKt6B7zEFlXoCP1bfgVcj2AfLTFluj0TZlJirISuhn1n
P7TlABqhPe3tJQqJPYEFhiFalwG40TX+eCaVrhK74bC7fQ3uaOWaorLsjzQ9fgFbbwwyd68d694F
vDGGqI2gem+mTvfpmGULYpry51//17O6VBX1CpTqm+diVFskaGwYqwxfSwyeoNs0NHncY0ZjMdMK
bfrAD2JnZ31tScTVYF6YVnSjy/p2gGiHR2b5nxUS2Lav4SjzoK4jvzVFICE6UMrDygIBGZIn6PBr
yBtITb9UzsT6QilR7058w6jL/U5l0UKNG+7ROE9CAiUc/P2aF1TyP39DlmyCR9k2rJRSu4vwpog9
hlpUZCa91yVqPj8qjcmzUE5VyWDl9PMB1MD6yTYvD+UULCRFxY2OT2cYeans6lr3vKMQQ1NPlXx+
x/VMojZp1+ShaSpV9fftSaX5E6hxQsxGcjcAkIF7d19kNHhVNgaFIZipLecipVaAqVitTANEO3J8
kulZlYwd0WGoxRzjXepzEXx/wlVWo1Li8k3xwZSnRZX0PvCDdALOiHyRug3N3rtXXGimynb+QgfS
ttn66jWbuI4gRwZUCNgD8CYMhTgWkNAJsoaKgHdsZa0xicMxhqm3flWqFe+9/VHETzvTSy+DhN3F
NkL7pYKfk2z7SM2D+sdN1nLDRCNui7hSuW7nlPJyUXtGADIsE6Cbo5TkE+U9/vt1poEM1o4Iej0n
rlHvXRh13lcEVwpLS62gXqGgCPJLOsxPhYcwVC+EfCUxsUvHCaEwPOV4L5zWvH4y19mVdDRoOpdQ
0e5CbkXm+933X2KogjEpEABlpEcSkgBJ7R1pj2iiis/wf/Brb/NjBpb2kt4LY/Pbcm3mxRS2CvAQ
DIX+6Jy5k5opU9JokAGMekVNgABrD7o9K1P7FYHyQjvbPNjKMnEDozQDfgmWft36g4kaHUzjH5CV
7f5VjpwiaAolf6Am6tjjf93g7R3BUr8enbPvi4rW2U+VAPjJvDwrBd1ZRtmkKo8NV4KmQLi10bKd
EVrR9WSF9aZdQEv6yL7cUdSRLYSxh93hVoIWEv2w26OGLvC7tPXxtj2Xxfd+7RoTO28Ooa7Sy7pn
kFGYrhfrwaM07r6YdeYE6q3NtL2mGFyjRb4mSKB2sZbRBBZPadKNsV3udkewtOqK112C9iUl1YMJ
wszepCzXy89zO+18t7G/HlYMVA/Awe7psc+yakFvuD/FzYOoL2SZQ9RKf4eEPKS2boivDAwIPb4g
q1miBip+TyKDN2EsHz5bLdYcwbJCS8eQ4fOjeTg4xu2uwgyeoISJ5FCIBlaXSbnNN17tF0NNNC3O
OEESFmcuSrG9LUKPjWgKWqX3hgfW8mqI2ozkf1nsBnDmmQRTVBUOr+rhcg1a4pecoORp5bs0oKn3
EtcIVYTetrM6R5lkpnDSoZz4YpAxih7JmUxsgu6ia2HnHtWpgyRShUwwRFrDws91XIURIFVpODbL
gwpVS0okehJFk36jnoWn2xPbuFUBLwFA+oECS6/wXi3xkELUnVWOjfVs92DyHIFSLKtafotUZDR3
fwna8lHrZFHPVQQ5TBF/hrUn0m2eztZ9P2AoCx6mHRg8IW6s9nBG3SzYcqsRGcTd3VfVCbCgPAhM
mm8ocndQSHO1hQ1BYsj/d6c7XLvJHCJgo9oN8U/nXXuSFpT56zTaG7JV9dmmEcdI04xCMvrqYzmN
0zTt10s8FjcXaVrBZIUznLqHGTEj22LtRRQKXQr3nRN1Fbrc1UpgyfjptsXvWH8v7PeRToxVVY6d
Us/DDJdjV81rIp4cFr4q8s/2LHTVDn//Jfb/EtMSzGDuWVxn6KU46o61nE73I/HBTT5rriHsPsse
Uuv/7RlOBEer2mqVhJ1WJFR6TlYDWIHXTXbZOk80YNBS+tAlZzsrK4z4Y5mL/IRItf0UjZ18zm3k
0yy3+NpyqC/G8I8i5V+oQxvH6KGoXmOzLdlYWQ2ogrMED2LDO9121JCKDnX+xdB35WTh8ugypfoj
QDuQZdFuvoM9oyrCUw5EDubrOMX7f2Ngz2+8ZSRWU5kpwKXUMtAmcLssUCKZXj/7zrtxa20xrWSb
+o8US6h+phl4MSSv+FEYT5DcGeEJhaM5uhlgkJ31FjGYH2WhtlpK8Q3f5AYYI0cjPEflIDgpiUzc
NQOfQ1+LyzBAiRMqkmkc3o6wSjBgm20HRrTOSLWH1Bt2lSWsFiyMfzhOpj2JF2d6DQZMGNpwwVUm
9Xo9Hf8lZR+VR5pC7n4BHDalZVi8qchdZcMhQyh3968UqpTGOZfFsDuPgDh+GgwastzII/6nCYCv
w0fngQkz9SHkSY25WMJthPoFRGEo8hwEsQcDMf55QYVndee37JTS7spISJ3lVnU0ia5qpoes1K95
ggjL9RgxfS79oFVPK27+pv4OdjqGpymDrhObiG3Jpys3CZFi31TRaSRt1+VIK7VO9LVjwEUXUrPB
q8QdyNp6NWNIjMvFOGqyzTfJdve3c44PxIr5Qod0MwJGobIyyoJIDgZrjAHFWf5dFUqIYfhZgcmF
Bidt2bVPRmWX2FFMe75eqYlk0/498dYfA5mYy1fhg3JxMvJFl2Pf6SY1+fxMMOteLQ5ohHJgpB0j
d7iPnW17pA/WfGF7/pPYeReeqa9DlIEKprymubqcz0NsCR2e9CJyACEyeJM34ljiv0nSgyI6Csyw
VOd4FdeucGG0k9sVBs5f2N+hAGRK+Wy0ZmJJ6XtU49jo/x5SUXldF5gReQ6q368dReQUC/2Vkqan
4bgC1ghQ9V0EhBkFONwP15RUqhkv1WEvfd0yJK91/OSkIDY5Kx/wz4sPRy/NJTInbf0w/5B81+xK
iPdJRR2MYRtZ2vXg6m16EahAlnIPFO0zkbYoozG1ygS7d4SqYC76LFd7CaR7YWG4CSG5y5awqPP3
x8mS/SFbWufQ/eZZJsblxBuZ1FUU0M7UN/JH4JdcLWn5EVLNpReDFYyd0RjqESvoLRyU3zxEGWUN
1muxYNFga7a43UK5t4zX5/piqz5Lcx5+ZFJKOGdgVSjDYim5afrp4pWi/iQJs9KGMKVFsYkqX99H
bRPen6L1hd4TAqqtk6eFMfyazS1fd7vuPUR6uiX+hCTd0bQzvP3hD8o8tz+C7djE7dSHhArFibnI
zcSQijGIzDsfi7wFuaRHb0cNa1bp0fTLmsNfnXG71j9AIME1yCDgwFxs6I9Q7IBhCW0fyDF6Mc7U
xcw0Gm66yRXnf9XhnTZXqjvENAgpCIySlGDjF/oHimMObS6unFcD5qk+L6nrqmAVGmX4d3U16bKu
7NcV2HBArN6/5jUdYOCMvuPUET6lhtPFqW2ua+2gmwMXhHaDwnGjj6ZJmOU30CaTE9EGt6/qN9im
jXfoVieKntnMNVqXYzyWBIN9/7DMbRVcHeCjFghfQt+8nJolb0cn6q+ltXIYNBlYScDopqvGs7LT
dZF8tQmn6IZx8V5DlD5MH3o7x1btSnr43j6If6p8rNzgGhIrRD3P2PQ/VWMJCl5Cp+F1lsla+M00
gGdAK/DsKcCLEUlnHBhus+qDUABWOBzd/IFuDE4yn+pKXlo5+NgbhZQBAsR0rhXaZqeFUtCETb7o
aWF2YC7hjYF9WxniooD1TSbPQSRKOMcJ8atOSZfvsvoJ1R6hHs0KwQxP9zdYt26E9MeHelmpU6/E
fjcfVEM3bgEdppvYXxGyoJdsRwcRT69OxYh97BvP6XC9du706hlONIwgSyCQGBV3jxwoPjgSCcsh
IklpKZ+/fvDfyS1TcuA//S5Nfngdx7lsL3uO8yIWMLs2Fvngyl03s8wz5BOQqL47l9o1SQuLJe3j
nUgZHGHuPwZ/sJsBWJNFw51uXivqo+f3hPK80Qy1I0gW+aZe2fS435jUlJbZWc6KJQYm3+3nEmYz
CBnZ+bOQ2BHLiKfd06qm71UhZeSgcahMOy2qFI9Wh0R3W7xhE5zwRizM1o6e+8piRTB51beJN9Sd
b1VLfCLbaC5mknYr3InIZSKiHMAYocNeVIz+NnDh1ErdB3UHOXms3kHFl9bEPxhEfUO+QzEUgMPZ
JdboMif0sm7O1q8erkgef8VgvpzAcUKetrTDqfUgogJfhV2iQL45ROT3vTOPuEB+AHEypKzLrd1F
Am+hhln4n+isu92ID1HK/Tzm6kSqoC47VL2vNsdieMHO8of9AZ0rfaGfg1JWmQ+cFRryt7ekmbgq
Rj3PHylb9F3Hrt5Vsa0lQD5rri3idleINXWDaWT3tzEK3dnmW/NOjBVBGfzBjZhspuOJH2EEKR4o
sH6H4Bde7rvE9eMxVS35RDeLh6GjN4dxKmBD+ZqcoWm8YM5Wc6+wa7WzRYSkcwaOUsmhKJJ9QYYE
+L+gs3JPra/2qy7xlh34nW3YEaCpJYIDOEdJhh9GcWLHCLsVnpbz8+eXlDt2Xtgz53WnadrB9nXE
K7QxwccbIUDv8hIJGSFtfo+/lAdGKScQQAq+vkDSSTd5c678vUBn6UuEZXNCn/HO0Qzpqnmp5fKl
sdL6jtgowVcnF/gLh96lV6ZR4Tj95da9zMBdzr8jEwv/Y4IJj+Z7Fzyd3rKqAfwl+LMKup3+dJmU
Hz8SNLtUNM3jYYHrIlfIRjVp++bp1s6Dlq28u6tsG0FDHR0iY3vZU+5aGEoCr/xHvmYkRLqxgL/t
7KIO5qwullQxoqmaaGy6aF/xk/OaZctDZ77uk1DioYUvNp/r52CiK0VUqp0OYz/aMlisuMWWiW/d
hgTVdSyQi21h7MY//66zamh2BF9KvuyZpst5NpXT4aQANAKMWiA1EdaUCQEAzWU5nRoRa3/s5DsL
mCt1k77uL3pAqCdwKItSNqHdqqsYRf3OtNpfCfq+iF3ZN7+kuaQjf6YMjK+jbiBWFZPK+AuMGzVP
DKdvdi/dLIV7u/38ochaN7SvmMPLr232o1BoRnacD45Z7Sk3o0SHI0XrE366HKa82xVLfZybKTiM
54lFppu592UCczLwcHoGkmb8Noy9KJmCxP7WzmDbQUNiA/HETn3dCXcYl7vjs7+3++3OSUA7Qshq
oR0l69aK8/T+uTPFLTsZMtALBkOgyQZMrhTkn8YVM+MDJAnKqk5foiDt2h61+AldC5dGyadWnsEf
uIGjhWzzj4SVPBJLKINSwwVvLPTGZpONjioE5KdTJnjJC5fmVajvtBXvFzHW11CGXJW1FNbxfsgf
s8p4ExVq8ccdSF5CQmIdiT8yxD/uWJXmAgqhcniBLAa0Skj2fqEz6okf8b4pjWxtRVnu7/nvXOGR
zLFpgIm5WH9UJvDm/dHGeSuIODRhtUckr0WYhyW5k0dPS1fNwkTGOkOsVCsEDcmiHdDm8KHeSSlj
xhj//7KwNxEp0c6C3zPPs//FgTIDnznd88C1kkQOCu1TYM57xggAgb1mx4/pAxKH12yYDB1E0KOo
tfNOj6aWk1CXL36umTUfP/Jrt8Wj244bExV05f3yDofqaPgnvhXvBzFPw+IYZz7eF+TBcn8PsefZ
WtQORcVF9z9znvK41Clk8psH4mX4PJElPyNzYsCmy4hPgydSyspG5tI5uWSSN3uSe9VOqWR6P7hx
IfIUXYDmRpODKZeRAlwtcKVABL7i7NFKlsReS9n7J8xLX2mmDJ58W8vLkMKDhIpDsxE3I9r/Rhqg
Xi/7exuynZjifsF/x2C6IRIarUa//RYPTL6yKyp/NSAX9mWTBh2NFcdux6ZpUfPN5sojBGh7HS54
EXVjVvQ23FPUeeve3IBFtdvDm8cOtre6I7xY+YToS18E1gWj4EAkU2IwhLeuAvMQkThMFxykITXa
NrqJKcHXxCaZwgZZPwDev+ZeUFdVmg46TxqPKOy0ht1KH4Uk8Wyvl9sC+7EfA7MIYM3ef+t68FBJ
l8BQukuo0+G2haitke8kAPI7ID9cmfJGWIpvZCy8IB3OVuEIGu3yuFWMCDjQSy3/PZy2X7fdhRzb
4NLA1HMhyoHSawfhfk/fLlEJh9DGxvnJWghKab68ChB3O4NhwF627qUccxuaMlOPrFnNsEE/vosm
zlSPnogI1//qUKiMgvFx67QH4yUcGRokH1rPXrlQ7eb1iq2J8JFLOfe47f+rALxUxfiB3J9U3RiH
DOvNvdfCSAt5QXQMyj/ESByyMPnXNLmSdBcihfLibL9Nw/drLN3umxGHDAiocuptqRVuhVvnvzfb
49TR5cG+UbhDzBu9F4maKi+NfZFptKqlKDtuIohLoUK5s8x1aqun9lwlH1DhVgJ+wLmR3JjrcRlo
OaIuwwfroDqiK45tYiT1hBeYkH1qLcX8x2FeGYkq5vJLrjP87du/Kr7TS4GuAYGTKosdMPSwMARM
T2btHWtOGvxthHoJc4Lym/EWbkWVR2dOF0xfPSqLj5RSnO2/dvcv8OQnYRvKWjH/AmGphKs1zwFJ
+bOlTEyxY3sDgrdDnNKCWXak8dbKl9gucATWcGuWiJUfELkO1IJzJv37GWvf+kUAz2DDOI1BhH/A
HUx7XD7CnHgRd6mr5tNeNQW3u1cZxH5LVpWajdphrBJYL3vQ6wBikS58uMCBPI18wMKn4YnHrsqi
d7MRaHUSZi0EZx+opVav24ehRFGqveGL4zBw7tv4IYwp/1Su3NgD43fGy8tyGku5/vNzzcFf6rwg
NOxcq9/h69rPfhO1V2lpHjQjjMwSg76GvcTWJ4WbCTr6Dyi0pJJjUS4O7L+D2GRQXJfAmdlswxTW
Kzga60BxkTECWDppECZYdFXBEthhU5ZSmoeIj+nYFPkyqDBJECKx5n0nrVxlJSsfK0mp5tegbs/U
abfMzsByQbHNUEe77FG9d4BjvnXZN8fKGMg4YPAcDdDWS7ifCyOAyVH6Uk7Angh3jhjwYnngAEw0
t/hwUyMAvVOgSIX020OjiwoRetZQOMLDlbSv3SbaGgjpyiy+pMjYW8WOf8ELpNgyOza4+wPbOSv5
gneQ4eIyvH2EKItBcFWa08zcxl4bdg7PURMMoPewlWbUwln6IhxfzIxCA8vOuCxPmoWpSHhcvqq6
fCu2o79LfPUczZYMZrsFlx9AAASZnZPnnwXsYIrrKmoHHzFTuMYJxxOKc4kZRN3OyS6hKbPV11hl
IGsqApg7kl36pw/1B5p1rocd55WA8CVfzXCbhCLpbLascrENdTfi4zZbVLWLIc4NhvwUxXvxNp5O
A04TZ84PcPoVxnsJQ3+0TBp5fZf4c8mNaRA6ooPoP3kHAASBRmN2pk7KACzA8PvBidWS/59vHMhA
+4PafdD5583oMKETnkavNqiN1C5XZ4yY0XoRWHY4GgV8S1FkiAIppHTiH/0M7C0H33VqvV9IBJOq
vHzPlKalPDhLGGZ2eS39G5yWvBEamK2nhKYWuBR6YIzv09mf10djsoUTp5vYju/JdYcvu+ACypvq
pBRA/2pPKlShDtM/vuYfWV8rlwFeuGV0qnzID2mGNKmhrR0G6Av2orzRGBqGGs6KAb5dBgxhF9VJ
+ngZb3mGypkF2oEsryyZOpC7b+XWZ1DeniLVkJpKNFIT7vdLiRqYR2F5caAEo6B1DLKdaSs3ztX2
H8/Dkn4ZiJedn6EmO9zBhC1CYWJcozdZzeT98XvqALjrx3b83MM4Ir6ge9u99gghE3XE3b55gM4i
/Ijw+TJ40E/JcYnREI0JY3AWe0w1aNo0+Ckdd2uG3w5r0R2BEroCa7YKQ7SWjXgmg0d7YkeQEaoe
cxuIbMGJTiQ516Dm3N5nCP2Q3czUe6PfSAX1faNyS9VGwe1Sz45PjyCR9opNTFzWRDOX7q6n6hs0
cYoUAeIOjvWrcMst/wmj4vv8o7VMGIJBCo/YPbA6/hpnVFK00jpJueZ7SMvWlcHR0JvEq4q46rLW
fO40H8C3AccYHTBhkocTIFCD/LHM73PS8psMg1+zFPlFxWO07a85sfRq+GWr7Yi04tas0+324dkT
gR8Wn/gquFDckDywC15yHvNVSnrv/EvMsBzPAu0zGsGkVdo5VHWkPB5z1ErREwSx4uQMAA1gIPAg
t/ACxxhC/wLNe9kZ5iN0emVp66xvvV7PSb92jNwLStA9Mqbs7vc3ZkERcWwO8td+rq26kwj0z4be
eBt8KzKaIH+4HWzWt316Stt0fXyPbW1uTFV2sc4yXoKvG6DlkMxXzs/m0cyDtuFYUl3S5tzCxIRp
KE6Qh7b/dSPXNXK4iex1ttUMqwPY/7h/WNg9C3ZP6DjtpL8+eG4u0EGlMUiYdf6R1/t7EqEE4NK2
1Qzma2HxAzil7GrnUfynfdnDZM5TuDZYafHrBTLxgwmIgieWNv3c3yfo0zJr2N2RIwlJ5yKb0hd5
1wRFybfHqsbL01V2hOl3P/xdsPQ3j3spUwsFYS92xDuJBdwZmAR+wmBbzFss174KcMyc9m1ADacn
HkpnaUTgIN490uUrzYKpddh3E1UzJP94QIiyzI9fKSdgwLod6gLXmLnNHTp1tSEecjOoMIEapO7J
8zClL+7532D3xzPYLwB7nxq8ASzqx7X7Wkdf9sMNlhmhLNoEyuvyjWvDceT6IEG5/DOL6/YVetMm
6jgulfEnUc3ymmRuKJ8+acIFItmKwMaIJW6ZoLb+s1hy3UFtyCgEuDPnXQdIz41+KtgCosyMWiNB
JLjeP64jPqExdZFTCNFCEnnwDh3Ha/aE1XzS6jWMTPaIMK14nMvoMnoOKk4WgqReTlPap63aC0pQ
ttINxgzcPo8DYH+lXiby1VVP3snyvd161rnUV7M8KZqPMHxgNB7D/j3JizAlv1FEszYCgVaYx89r
lkXThPwRx9OwfgMa0lwM89tKEP+wNBNjyFNzwmIuJ49KumxpK3uSAHw4sFT0WWl12iJt+OG+rxzF
ROI8XP3c5ZJjmJnSmSzHIeFv1NefDY6HhsIEaX3PBzQKj2I6mrlpqtRTkZ65sj7WUvBtYc8UEW3e
lETz7k/o40qqiCRk3QZqXL/ZvCYQKYyKu4qnjF0gd2yNjufecVN7kKxkUM6mdHGcOcwU1FdW2csl
5y1mIGqi90m8I5AtUVrY58b78TGmpAuIlsMvZQnD99Qrte4n0ru2/N1SIc56u8Z0692Yg+6lcowa
MdFRX3pcVr/dMUX7ZvcdwW0mjYGaObWmtKFPEMJP8UuKjQyLc8oN29MMNiyIU28iV/YizZTKk4mt
Ai24Zi7r13sqmlzWUUlRRMim/Mq4W/bHDW9VAcF+WJmelhP3arFGR5PgAfgAu9nELyIfr6McfcU6
a7O0MyNGzUiKj7pWjaYFw/e6w8XvsArxtnH0/5SPnRO6z8qp3BUJU1sLYTT7fuFQPUQdRWrAfEud
pCiuXmnZu3OfjM1avNwbGumTRXvFXF9UvBVDIYf/O4CrvebII1eaAwEzqGM6F0pJYmLVVaHJNcDL
zVN+Qb4ac/AfIskEDzdpovQbXj91RGoicDVRX5lqFOWFBVi0CW6kDxS2klSM9FJSlRWfQ/qwC0b0
huRIhkPhHvr17dUmCv/wwTzuzaod019ahsjGFD62Jw7BuSqiaBxOrcvSZKxrvHT2xhJztfZVSdAM
VsERJv+R6FIX/meJ2gzHctY7ToGFCAqJ/9gDqlGJY6EEdvdkmE/akHTbJ6pJ+aqmmPKDwSYIgtBn
cCOYdwIeRUDlVqXNvzRRxbE3Bf9TZXn1NTjku5WE/uNF9d5/rng2AIqrZR2zILTYl9GQI4dOhbPC
ZoKXr2wULSI7lRriV4fKBqNM+lbIT1Jlkk2PaGTCOKu4xbmJPFTTzlVJ7FesA9VmmNVQsI91lqeI
MGJvcRho4kvZjRY6MYDgh/3m1s+7IopUJlEB6nsqU+/cyVT24zQoJcHEWNC+VFXB3WUUrSJb7uGW
06IYmNbZxBCq91GoooA6ZiP8B4rrcUwlM/UcJWs52jLlu8aIsTt4wE4K8BHB8r24AG8hDjDhuSxA
GXpmijhVRMNy1NUo8QcUzSZqirpVUeyD10lkhGQP4qJ1QV7iJ7PP66UH+2rW9MwnkXKHkb/1lsaE
n9W/nsOZMPBT1Y6sMDwHeccyyR1BG7tlB/6sLEWKl8AIsuy22XvmIl6hCyZ3npBATGkpmxyM3JxH
c5E8pu+2tPAKoCLqI9RzQL7BXbH1/5fjAa7qMSRdroQYuFasSmx9zawDiuWEHRIUOnrkbCKlxFou
/Z9jCSEHw7dCfdpgwcdC0jC6RU9MpwvfvotboRI+CzXvyxhcZjI8WzDQ0CX+7RhXjmxB3NTf67QR
1ucntA6P8tBNvFmNOxszp1ncoaa287/S6LRBSmt/vn8EuNvfsqrfmAVBOVLvCLYTviYXfVBqB9P9
6IE+eyeE0D0UlNkrDDjXkCwOuCHjlzSrIrEQiNIfWEPBqhRMRnZOqtp1COYCOrGGR2qvI9gRiUx+
Mi7koSh0z1NcPo24n14xoquHFdPsi2Ws/TtySqmkk9dCOAl2CYfk5vQfRqxpui+bwvSikuy8WmSs
D08xaPVsObStjINXsB5iWp0Ih1WlW9HPL+aGMM6CIh6/NH3D003p8L/V+Muj0uTO1hMuc9kVSDIT
Tk5QxwKh7iF9vcR05kvmcLRaiHGuEKeosWa+z6IsMzye8+bp3X2TVnCfCVxi3wongNcBO04uYi0D
EGKon4mW4Ojwg7xROOQMSsqAq2l12/uQwocSjI6LulV9IJXklaKXDPy1akzDrzRmM9PXBuWeJzUS
+XHGJk9JwAPC4TpBsj9961cdpUvnWVt6Mta7TkjkN9UwgbFJprwI4kXpRA0fWM6Jn/kdfvri0w9g
tSXb5nUIucGwAsF+7x0TJ+mKbR03iQRxSr2kw96+klsfACsZyVZ0STqI3p7R61EkT580KmJeoig8
uWKzoixn0V56JtMa2tTSJEK31V3qQ4acpg/Ga3Y1B7uQ2oToiPyQ1pMH+m3gMLVvclrymCNVmmsd
s/UrfvTZaBMce2GKa7pwCxLCzXd1TMvPxeHVANCM684wi9NTG+blgNg6SkmFn29IXf1dLBi7HeLt
fuS03SncLiYQkAXQp7XLl3BdoUXq514EMSXs+rNktP2cC2i+4MaEwfClMYBu4VzO96plcaTAbU8w
TtiX3P6ae9jdrZQ1M7xTVAXX8Vyrt84loPfJhUcJ6Tt+cfkBYzrXzhMwc0vs/3Czjolgz08/UAhY
sqJ8c7bSvUxZgoMilOQVvwEyP+Qkh6IMJWYbv7amaNLk8f6L8g77oVH6u/KcCkl4VlK+JGg8bznu
jQr4kTpVOZhmZ2PJsvW54CF6leFaEOELFxC2fk4Le8N0JMgyamyEbW5xDisifNGH381lxNBaUH77
ZtwRoW0pQBoQ/sWnst2BIMN5Np6DlvZvxZpb172tJyvckq41eJNpXrP3hAiXNQyslE6pUmTPtCrJ
GxqJW+ETDwp1QuvwKLG59b159aqEEFk6jO4LVChM1175a3tRQB3hzgAa/OVp8uNwQrsdHN1orFet
z7JSRyuTEa9ERnbINEAp7aspE5KJJoI0MnIYMLwe4iFTWbbHaKpalwtcvacKvDR2GtvuZrDzSwCb
TKo1shC5epUwJRfyM5k7gGg+e8Gmos662UFUrJEGHGKKaOGj6TYIRsBKQRIw7T6SCd542Hr5ORXK
EI2kTLSSYsNfBCIblXa62djJT4HjgAdoaSk/rGFdj0LzQl5OKFsiVh0py13q+PdmLtcpvbmhs7J6
HZry+z7rN3BoKL4nhgT91HmPkGZghJzv+oOBx+kovG4JtZC9C1DhdzDt2E52AfDnp1eRbCenaWYN
U4cwCqzCtdDwbKBHiH5CPI/kAvgthIYUBNq/NQSfSwvCxB7wNMvF4cLlw6u3SSPcsdS8xzqTSHxR
sVZuZ5pl1dmkMofyZOXjwZD4IEiTCn3NHbC8SdE5rAmCamcoYQXBzksda9aLg3jICzCWoNAcrckY
jexEs0Dnm/TPTelpVkznm848aM4sKJa4NJfIvwT5dvWdelrH+G64tjLWsuoOxH0keWSKFVCNFTUc
9D+vzaLiYInm/TqW+dOngNaJTHjNlvf8E6BgNDY7+EQB6qgRDaNphbJQiCZyxpNdpTsmCVmM7qFl
3bf5te76lTz5m5D+06ZyjC/xwwhtrumzLmk5NUqopK13RCb/ugYdNi4beMwWcuNj/jhB0eqhkqwN
ABXsIGHiYDQ3wx06QJ6myDyFdLgMeBxspKS1oWZe+SWzSwNCpy8xXm4RUL51gu0m8HgivWXunJhL
pWfzGo70vnzQpBDoFEtVO48YRyQv74DMpGoT2Q93pLW8B44kALL4XxYc7XSZNC77K0wNFwf+vb0h
Fpx4RpYEeB3YhF3Vhj1hvjIq7iEpVDBEM2ujYe9d2ItsOrkqNrSroN0BSBq82wmYhSIsiqWvkP5q
2lU7kBa0gUmVWQxKSsyrlLniZDJXf4HLOz8wbeHTJmukzIsabuxWT9gBjOzBMDRzN8rbcZlJFC0R
UU23vT7d8E0X8JJYMy0I1mYQu3QmO8cwpcieNiY+3gFGBQNReK3ozcZShkoxMHRWuq4Ff7zI7l0y
+fpL6bpUQvP8KwzpOMgKwLvvNn9sEPmBTBixfQjRcW8VZLgMPA4OI0f6pcrbLzIMnsP8iury4aPg
CrsVFTYXODSD8lklbzM5b8y5DOuVtwP/rxI+kkAaABO6xC6+5ZR66gUYZCgeqOuYwunJdsiLLh50
TzwGp1jX1kAgbof+h5H27FZtqKHU8JZZTafH+6ahc6GEmJxMzWsScgY+JqrkTfeW+FhihIhTmwjr
RwEjnYWW/MYIhkORIb35OiR+mtfBYrGJX8RcMIEa8dMe+XIfTSTJcknf9bIk561mjr+Ir4Ayg07O
Au03Hph2369D/PoirNx0N2qUo5xcWxQOqkPyl8tdWN707zXOGSc/a0YAzJXjEX5/j0I/QQmjhMkL
ecnQFICbA+i0O7fPi+bvir3cXHBT7TtqMEXU+0umDbYllIjl1hux4xVlKEIlUKWjcH6PLo/eFafh
dRxZemOQtsgBfNHND+Or/z1t//8hSp/jHw8KH5h3EehziGqnOUSKFc1DSYpt8Iji68xQh3h2OiWf
zqw86I+JutMx5NNb6gJrGurk9ZjC0xwno1imTxeOSxe/o6/X5ZrHD7/AgdJz+UR7b/MGpZwUJLQj
mq73UKYdTqSfVVtnJefrC+0NDx7svKCVoaVpbAeKrhVLghQrbOy4APXIRsyOflU7T0YXlyl9jigI
bi8LOiRe8KNxvCAmRVMdMgQV1sBV3VuWGoDwbc7ld0WIs2//vd9MpSQ5n/somaRZFIJTMRiYl8xn
JJdo+9hHuEyjFexVTyTcyQBeebA2QAy2TAQgP5YA/Z3QUEoQFyW49SFREs4wa6+n8XYIWm7wPmSX
JQGIp2+0XESXOLoYzdMI0a+BsE3vJ+IxDq5t8tdnqgOTmmhH6qAJua5rGUFsDMqqJpSt7XgtdNlb
u7cUGuckGXuH1g88D7Krfj0/B95dnTn66U2/IqEkdpGLXJtqDgH2xVkgLf6+5UqfPf8xQo84m2qA
UGkXmK8n9m1ti8LUtaQi7q579+F8La7/O3NRch6B/NNEZKIwlPnpM8Yz0K2Yq0yNHvDe4BWck4ZT
V/CHbVIsWQGtojYUQbQ3pBEPUdFiKI+w3mf1GsArGPaswWp2W7zQFbQB+In1c8K2qWXgfdSwBezr
BThGQ0E71Vz+50tCDuh7esqJq1thNG+KUKLiN0XZ3DTKc9mc2KLbNb3wDJ4oqkqtmu7k5UgbMflP
uzdVdEyfMlKb0CDXJ/3MoRhjtjKpZbkJM96ZKCyXhGZGkO6jgyi8Sf4nl6IkEAGhX52qE4usVvjx
QU2fgJRcgxUM88kddoxCM+Sxx4/BnrDI8R+qC8T7V+r+qnQMFYabWPbiMNpPy5hfD9j7emYQ2di3
Y8ZxUazSKB7vI+quhD5sTsjLlgjw4Ve8RG4AESbzg57izfnKOz/Ru9DodDWBoidGwFrAs+L84Ufb
/F+mZN9WeuKEa/B6wtQxeXGbztVVU5fR2V03LcZDrnaA6JVLkK1cUh7oP1M0zT7Fa8Bd+Y+GTRnm
S8cl+9jnu3eLp5JE37hiDNSCAFewbFP/DrsrLiU4lJ/9jlr/Fpyp4wTSAM5N1QVlWLMk7lKITjho
CR2JvjRu9X7tm5gZVESfrHuKdYNG+NJb7F04iURLinPV5cfLzYHp1w/FY+ol7my1LhvrN3sWsXRv
RAWhOmxvAKkLmVWbleiVw6BuIRfe1+rI5Y46PvGiFJEEjmgAJL7DvPD2T9o6xVAYlz5PH0XK9HGQ
o/xDDtvCBnQ2fEL7FGronU97O/VYZbtb05jsAkFTnlUrLWzL3tkV6GgyvfwZsx4UYT9wQZvmBHPO
oInZLd7pQMARj8kc2iVJR1qBUr4jm9UcT2u5xVyckFJoRcpWJnFEbP6rw91FTARIMQUu31Gn/nGM
SUUnsOzhps7i3o20xk7y/FY7xdam+4/INiP5Fy97yOMZGrbat5dqnhvhj+if8Qn5Zl2OKjDMqXqf
8R+B2VtkDiKvKNV8AZgiSJLMSko4xmwObuRlDQwV9UG0D4q9lor4GDK486escIx7Gznmpfni8NtO
s1Vbg8XY4uZ1lV1mHNs6L66MyB+nJXe4I/K+yEiaD6fMsDvkDJ0UJshrnWsBu/TBIxVvxBUPQVR5
qcsOVJkRAnXHBot9bH1sv8hTSGVd+bd/+GWdEtiU6YkefnW/IvMdA7o+7qwUcWZtcnamU6+1LJEb
dNdqeAqrer6t8pN6kqpm0XIzd/CAbv3Z5CmVyKyyLxR1tzcsmq3IxF8vzH9i+I/UvVr0a+ZSM/SU
gTm8a3BATXyoOtfmJ0dUIUGAUvOxDJWXeJor0atlCP/JsXXfDCBWJRnxmf+lAjrvdOjp+Z4cSl3D
qM97XqO+wXsdheWurtk+6X4B4SMZAhB5ZbAOEp/HYakl+SlzHuguFloemO7t4oRDnLxpB0sm71KD
whDfzIpWWYYHiu1APBO6far4tX8DvHsqwVs4PoZ1qSl6wAPdAH/n80B3FZ8yWScOJ19J3prgZX61
bIhrGoHzXrtlL8VUjWe5k/dbimIlqs3e2tkuCPlqVh7ClZXxTk19nLT14WLF7vsXIjKxyhX9RfL5
bXX03JO+D9pob4KX3+O3Y+ddwy+fCQCBG5OWJe1nPfM7mC626e6e2824G3MDb8IC3HQDV/OejwzS
bvmJpbCPqwotsSibH0yzkuB0LbXXPF7Pdg7rZqA/+1nQswWiwqgf5lRanqNG/890zxWxqr0wqnyC
7bpeOxQTRmBYFFsVc5A8lL0qjnPg70m2S0g7Mrt1PT5EzLtAnJ0JqfSQlorfpYTHDkeohuuYjNm3
hMGrncMR5zuw3+JX01LWfRvRFDLWlW7v1aHMEEWi5eGQbNnMP1tP8p9s/uJ8/1R9K0SxdfSf4Pti
752+7nQGCjiMajQYNhE2whhWvCHUj0DpV1wZbQ/G2axsQRHJMV6cjBbCQkQ7z1QbFiAR1UcVU9Gx
11nozMi0D51G070r+HIcs/Egahdg0Z4YGnf9yxGbgBTJVMwmLvEZ+dbxgmrQc8S0YZsOh3QovIgN
M7qFOZw8lqtm4s8rZcxiNBMJeqhqD2Ngmeu3NhPxWMuXDXQ6ArJUbn50nnsJDAshVu+6j6cJEpom
AaSqKCGzVp3LWu4u85HUp0k7L0AJpp41ZP6BVsqLeNAgF7dkg9FTx+xSfr7I6in9vJ6hRi53mBqs
TRRvp4iTbd4tsEHph9ETUZK5si6mVG6KxAzn1YT/5WhsNO7kZDvY1ctzopf8cyQWe07sctK7YVKn
LXABIa75L91nTxF9s4zp2pM1NJFXSV0On0EHUmmIt+ggKS9QwR6EmC8NnzjDZiLexJmHDkyOOb6S
7fh1IPrMrh5AdnXZ3nBNP/AEgDC+OHoW0uj7rEZLp82ZslN8gfLLtIcEpap+5FduZYCGRB3SyqwK
ta9OpYBEHVmfOX4g/iWFFRJMJfVR5TeLSXaQHfdVasJiifFramR00Xmlw22rkt9jcl9RWy9AT0xv
0xvvxHz1kl16SjOHscnPekNzlEAiceBbqU7ez5rphHI/JnxveCsoWXQZNOyHWfKw9qnbGFr1/6sl
PzQdgQxzwiKusIFk+kjIy4bNd+/tZokPhfE2yPQHbLYIyttjtPLN2NxlZ7qBOxf88p6TDgSaZTHS
NHqwmdIKPraPmNhJ8t+FTDepO1i4ggwT6OHpOkCML18gq0RpJGTZYGYl9HBmYG4cCn/jcON3+/ql
c7sTdxRnpAqgTpf9SlC0QadOnYwWSqdCnc1NDt9hhZYWiKvfM3S7RRfQBqMihkac0lIfBOBj+IOb
uZvyWLexQQsp1BlQCZbwE4LS+9dDSkiFr7j7O7Gqadk3N12JIT+YGJt9N/u10B5uQnXSDNRKWWBj
fepbcOVOIPvn/0e2KsC0vB7HwB0/Kt/P8TmUaDKj1I5Jc712ZUAs+6UGe2+sbGoZ1PTnwrXuTP1F
o1iymYdvE4fnZr+OeOS/6jcYwSU+yKeccEMRD9D6inH21zLgYW/Lup+oj17tGpM38aNNxKmDlFV5
Kt/RIZMqvIEooJ0U2RBfj1ImD6Zk6OyBIjb39NppT+8UuC0Omr1tbG+WLXebc2YXQZght5cCA9j1
kkAB8EdnUx8lPYmSVIJxIzLfD19vGPZp5V/5Y51VXBUv8wfkCpZjegvIeVhex3M4q9IFem7n31x+
rIFTpWTXqk2mRkt2ARsoKEF5PypwlpGXUsfIfqiFfVgju73CXqtbsUWcm46D/KuqSZdQ7WehQ6DT
UPInqZlJmsdsxS2jk/yJ1wZWLdyKG3H57JJXF7GXTFtvLmkb/ZE8gJ5FP9lvQ26FfYyhSB/71L7x
MOFKbI8Qs0F/3QGm7IBGerit6/oqATXHqgv7R3pR5b/hYLCdTAjtSfAQycmnY+peY/EwJNZhoK0S
rIPN9Bc2egcc8EVjIWDTm9jzkIHLReEfNzfcNvKq/dOtZtRI7lPlQ5OcwfHpbqCusmvKY822iYmi
WzVyVfTLdbUZ7mTbSv7xdGZgMryI6cSWjqIcKBI5wTcqbUMlOa72SMFI3STrfkDQ7I93Xyjbwgeo
Plyq9Ow5q9rMDQfF19+BoXRU+fxVMi9AOB4CVEONVQ8D8a+9ZeN67ZWkTJFO8givk2FLvtSGINXv
exdQT36BSGKpJ2Ow/EREYlXqEfxKr0WodzjQLKTNScDZ+qfLDeJJCZohjpTptqXRuer61wTqOYTx
vDZCQbI3dX+JBCCsHPaXra3rf0fvbhaIm6IDcQpwBkWJNXd9QBVSMtZgz9EVn82+BYfVeYJk88b2
g8nSCg8YeVsbt2oLkj0dOftfYlJLIlWkSK2wgD9BGmiEN7PEjvKeAAZTkIMsTNwLGa0lMZtYJeJJ
BBQ5PcWhArqYoME/9U2dJAznNG5ikVQO1+0307/TFW4xm1jl9Gts0Gu+55RjCHHUQF7BVkQDpkGp
MKD+t76gzqPJL6OPoGz7TEbbOHko0dTbJTUYb6McPDThEHpmwf74UGcKoagcOoiCURxwDzYfUUML
KsZm/R+PPXz8N0gPbayYUSDNGgsFu52clDX+A0SjZyV+B3ontpEd6MKs8R8cSP9Ic9EyUH/vO1aS
lB+T9YKV4RVklFL2kXZzl9ay9B0xBcFI17v5S55ldYbzQnREltdMNFr4Um48WiFbXVIQ9iMEDvm+
YOpy+lU1hX2T0ZTyHOt5CHLwVwot+Op4tOFwLJGoMpuDB+Er1A5uRaHNxjZZk+LsfCQajUydFcS0
/p/RPERNNu8d2gjrFTVNAmxuT0GwQQO1/hapAByMc64gJGqi9mOzhDk8fUsSYDfgaXLrwUFHUbfE
xCUCPQQvgS/bpLpx51dtyUzY2fJ3ZuyhDDBXeuLvjH576u02K+UsheqsPVUj60tOp/cII6BkhUs9
IbFnpwZdlXeSuXj36461jkSBTVHwWo3NlUwhwaBBHt3nn1i80YQ5ZzOjOVYlmRTg/N+2QZQ5Ci7a
b8IoB6Kj0aOW4sopkU0lxyyrGVkHFWEuIYDFUspROQ/PZKMGUylgjD2nZT5/f8A6xdyjoDKnxvwy
YJT0wJBOa/g/qMM9O8ICukzdmA0ef6kYitIastVChB54RY9+2L9E+ORMNJcVDaSzNte8BtRPSbJR
rFwx1irZU5OfYVqZr1oiHSJUm4Kqz9T8iI1mreOu/U5THDaVNRkobEj0QG4e5n7/YIYUi6jbXdD1
0QLn1UeiI3Y6bns2zx2iY0S1s1mPtcLPCjZKH4M1Ylz1KfQ4kQmNaMUDx8LxmK/XNmflZO82f+Gf
rYBuJndLUcimiPzoUrWC+1gfZdC+5VsaqzVNnKI4tDmibF/pSIR3U4NUKj1RRPgCxi56VyiL992H
Y4W886sCYrF10wcMlDd35R9gI6w4vTD3iRFoTgGymcuogqaOoquLrwkHFY1XG8cSixUl9D2AVyXw
EfgYpCEBYgpn7z5kT9kSVU34XLIJNqSjv4zkyZFnxlVXCvE0B054m+PbvL2Lb0xLM+QBSAZqOrmm
/+2ChEfBrFDCfaKqXl3fkfuX0JpN+Yxf4+5ZMEV4Az8N1jQc5AzfBMNEzJvLC5mBoB780MVJPou9
VuRPtljZ2tBXe0QmkuL0vGRw/Jn6VCwtj8I0lMJ4v1OTl+ZfMZEhVq/cgktE1r3IknoUs+tGv4Gl
92aB1K6EiL+VsxxOQlsmOKQDRP6vMTBAw/i/bEZJA80mQ9ibOT+uS669/wy4BbDJuAtujTiS4CB2
4rpimwD8HV5OJ0Fp0iChtkLHvY7csw6mB12bwDXl4drxDi0vlpeIirabh7eoymx1hxP6pkstxukQ
+Omr/WgfTXx5PdqunxTAF04JiO2pQwv/vfte7wiax3zMWu9PryLbnCiE1N9/97fdQXxgBE4zzOuY
jMqpPlhZ4u2baZjJZt9DNBaxtvANOg0lcAN8Mo5T7JRsJRVDuyWzMbrlXeC8sH35emTqRU5nM6eq
CkZvxrGajNsDygahSERv/lKh0E5kJ+E49gAFmfDiBNjHp9BAFm00BNWfthSKSIWVQKS9t5LQ49RD
jKOYKRBuDYX65dZ9PSwca+ZJHuMPBy1OCoguZASfnY8o8tKALzev3QgEugWCvtS/B9YeY+1tZele
F3qagS5JwNM2Br7wtsqyCMaDAe9PlyTMU8OXbGYriIuvvVB3B1T+qfojF/XXHcgDcEK3hJKr0gXz
+bX2jc6BvgKRt6EOvw9o6EUGv4cVxiPCBtSF80WakBCvmJkqL8yf+M5f+sPLYH8nc4UghlPrrKFm
2EWanw0CDtABEBx8gs43KKhIOGpmh5CoA+wd/zykBpjUz/ivh2417bNxoWzBec6cSlanh4hThw1k
/5PPyLReagH65LN3MINCXeVj08s/cOuLg+SM972Ql5jliZLdsA+MuGaVYHjXbL7wcYo16YVGK1Dt
hOF6kTw/iMYzwg1oh4xs+22S+eJmLJ+5jdGKkgV4g5MAvRf1wyRwjbcX1vDTz/F99vG0r2eGU5JR
aMWaB2THoLOBw4w081lWNQwxp2Zyg6FTEAAO34XwQrwjzG/Git5ZRMJUBBGolfu/Ti2d2rvSY/s4
76B7cNP/Qptw88jkDVU77SoCcrbQkFVoJKeNrRGiiQGPHPX/70OzzgerKbRerSa1l2m9wz+sY5ol
2g6zasN8EJyB8XQ+EmNJukh5poo41Ytq2VTyVw5lFDlR7BvZ9xUHw1kR1Mm9g5fOsu0scc5iuG6r
f3XrETqG5s0ixPvLMgbRvnj4CHElxsia6YtPgDM7RmKwsZScXKYUnPKQ33b9SXodoUrsLat0846i
pvCO7dMqaeSJdWB3pPf4XCSDoPGdSlyLswHkPl7KmQlLJG46ONAHas5cbLhtIbQrzX9nu57n6r43
DfrXv/sgeWKVmhEI8jPX6GDQJVo+e1YCweqnl7FGtX7CVa2+mTXqLxSXXjGo/XWg9y0rw/XcHoE+
sJbU1AyuxUDzqSGDyil0kwGiqfAw0Ge83KQdc+ItOebvRvhw5ck6IN6bwjY/K5kUbTp1D0yeFyfZ
a3JzuefjCLWTHL66RMg9BlhoRwgdIRnTMwolgVgWCXK+VbjMFeeSg1eRT8c55lHKtrg+4rMDLNa0
uGz6jBBGLs51ulRDIpXiCbvv/XsGdAvD5zZVcG+HHZ/+R73m7/u8LI4HNhMnvcHy73VeqV39Df5y
bcGxyUKLuOs2jECqzztD4N7EdMRrsYDzakSCkeyWlucohYFSdrGEOi1G+ZSecVjtTBZxxXOVzc5Y
6X8lCxjZHn4VL549hXRSIeKCHIBOIiKmb+bPDe6mYvUoWHihY9QFL0G1MFIIQCAS9S1M2A66flax
pzqxH/eNZ6dX3wbH2vzF5fa/o5RnAXWxCuvXLW3qp0GnUbmZysm3WiwDikDoZ47EalPvn2irH63R
sar4KW6x+NJJt2XnctuejHfmxSs1yMAWwQoCLlsZLkbKQTFCX+HzngdfUapzPgC0BRgXy5Z08aV1
RSWjHySERY+OiGTnpre6dhORBXCVXEt+57ODeivvOt6uW5+O/adFzzC+raZK8+XIeNNztZuZLi1s
r9G9CvnMR2FZxrxI/KwRm7Ft3PmTZifAtJPsO4iYZmUek0ON/TGWrmaE91f4RF4hQ3EydFHSnoW3
VC+4ZgK9dfUaSMQXG0QFMU7y111h0cx2zFuNX5NycrcgpU0Dcfz4D2U3fG9RSjiM128cid/sg/YD
/uC1tunjASz7FmWGeLIUesHEQltfdQk92oUpcAq/KBdtHk3HeyauzEfwECOlRTTwstvLThuJS2n/
ksjcIr3UwzV7SgcEdbsFATMMGkhIAyd4CvXIqd3z65sYGqgxdVkubDb5D1zTq+t8Me2SjhXbZrNV
iRwE2WFO5zA+Hl6K1yH+xpz2xj3tn06oaMabzc3kGQnOWePsrHAHRrUIuBh3byOdM+eo63yVDbdO
QFjcMHWL8VM+XSUEULxVqRcwkS+lNiZdD1vFaFVx84O/c8/+TtwXqHL71R3qjrW4cMtIQ0NnJ2FT
lYeVUkUYMhbGBzGGNmx+kt1l/ADjzIt0RxTvK3/e+EWiGSPl36u2m9d5+nen7IIRHijzJc4Y+7YU
+gGnH4unSNiZJpAHfkFZ7FrJcMRIV+9VYvvNC769w7tKKWl0HVvvwEfAJFIuaq/fmqsBz4j8b9US
wlc+bZEjEvIXtcipo5UxqyUaV7NImZOr8BD6EfbGhxJK2GGtqK6q8/yVwZrBtAzcXUR5hGPA8Ibe
ZEeVQSX39g8bRufWoqRPfjIlvkRM+hudM+fHfbpZii4CNgHU19hjsYwNNY7tvHt18oODhHkMFEKs
MXaEwMT7QVroboUVii0+pKYZxRn3RcQ1iu3ueasHW5piaXT2q50Hi5s8mxjtVdhp3B8q3HbhIqEH
vjzv+NDHb0jI6CYhIhJ37lexysjkQSqrKY+rk42WXZ8CjpjPhzMikHzkCPVZKksBBqWqp83kKuWC
tfiixBBUiV/px7WqsfIhwT3t/7H3oc3WQ6CJYweW0ESq/DRxQyE/uWNrTmR92uqn3YUVzjR2vojP
qnQJUyMhXiZ9uMS1iCC81yr8hxIGZBWz0+/Bbpg3FkNx5Uu84rzxhGVGqlGYeTQa2hJCHfYK+T5M
7G/dCzoKO3t6bo7MQG834nhlyYBcDPsk2MlFGPWnLqfPY5Czj9eBru2CsYPtlj9ZCvuagqheV1Ex
C3Ufh+RjxJdWpHEl8Eb7KtoL/79cPuRdTNqTAQ03aoesKmzF5gOuZsP9OSOb5Kffm5hZRCqk8k7k
scOJeHGRiw4M1BG3AqJheICbeAoMzvQD+JgOZrHruGVxXtXrfasE1EhExYDbtUhSsNCMq9LmJZ/Z
dQmd6HPbjL2nuxNZC/7nxbJ5rjgdWA/X++vMFWC/QubNO7+zH0iB7/whk4+w49OAc0j9pvw0NhR8
lHgECZ0AfcqCxEe0xxqlYajb6pqnJ70Fn06I89obBPHrn8LYxQVzE1ihAZv1l9ErGi3yyS5Ubd9V
6VlGYR7OJ78mYx+qfLuWPg+YdDUT+FtKuVihJ6CjNv+hBnqR71nvsJwWn7lpyGEAQpC1b7gCWK+X
aWUgvETSHR+bwmJ97rVyOZUG3QXlckWskb2jQJ35sVQpJFTC0DSj36YdF35Xun0BDiYJ0MRtvve8
0U+SP6nCmUpytL7+yztjnJ05F9PWn7i3pCdPalK9xl7kA8rxXFyLw/TV3VeJW8rOAF0dg6od61aX
neXCZPxYD6GmBcuVSqinoWkVaTs2pMKu3mtbmqF4/ZklwGvxvJfRRxobbeTRE25P1k1e8Pqxa/1P
8UdJzhaaVUSQwzL784pUd3bqQ1PBWHWCda+IQBzsSv4piwxe8qDS8s6tNaSQRr7buZGeXPRplzyY
kUCzdIsQiLb/4oJhf6O5UbsOORA5/29gYXqZ7v3+OCphoBkBx8lOXPDvdk3zMvYaoAanIO1Jhlp6
TsQAN4xhhM1FeWmxXm8VLyX8+WOyZmsyKSBCnklhZRPp1beReEn+op/oKoGOz5sMARyShAEdAuun
lQFWpfhvH9JdWgZ89bJftG2Rocm6qF0VBZK2sYektEABMaUzIEp0tjmkbCfXm1ZuaydI1YVdaFdi
zCIxOCkF7hYa1FFZN9s/cWZiacmG+Zh3Kt0jhh2GjJ0jMbB/GskJQTzZEdtEiBYM6iLgCb2P8n+q
5VpeiAw89kSLNdVeuKyElTt1x454wJjZxczg8QHjvnDXJpzk2qn/O3ukvNg913riain1JxF0epTn
70mHaNdW82ix21sQb5WeeW5lroSOeH07WHEQPp4SDy7xeNQDMkNoGTEmiKXhsjyS7nO1+sz2i+8z
40QVqWlwxXD7c53X/Z7ZDlGo2WGUp2RRMRKTnt8y9jTeuBehIAsqn+fs0ya4L0Gjwdv1mft7JuVa
9LftL8K/Hhqpvy0IRyLTpfCIKh73I0DOT+2qOvJB+xGNZLvJ7mVYCzIWq0M6Nil0hl4ZYy3y1d3F
1eHiuHVSiJO964aBQQ1JYIBTgX0kY2ZSdBNDyJVn7QSx+r5jpNu8shwRtHaYM5ipFdUzCGf2pg9C
ddyXFwt2wbKff/nj3RWaSLU+X2aEsbBX4B6Er0ByuVoO+Nq2Melq9WnPK0PzT0YeNYqTvV4tp//C
I9ls0r+L/9saowEZBEDthr0gIYPKyvZBVfPfoGmAxfTAZ8WPUf5+1EGRHSX1vokGzLhvLuOMgaH2
YqF9FaDhHy99JqU3OgUolKxdTHN/swjZ4sPu/GUeHRnqHp/P2iPu5//TWGevIAO9SmJ8MWy5WoRU
5Gv/+UU6l60Pldw6LDns4FfPG2UtlkUwewDQkLsQJnGLfNsypSRXRupG+1FixMfkOV6RokVJZKUm
C2XpRy8T8RjdB7S+lzbhVH1147RKFnJ0VCvrCFj17BCwsZMjlQL15mn8b7AnSueE5TisUBGPT0Am
RobjQXwTRgD0cl3E786d7UcvKSrT263feD/VXo8oMjpd1lJq92iunl/2+yKd7+G52D5oYVEF1gXH
9Mdp3PW9sHZ/lBsVC3ZifTTW9fELNreDeVMintepagSeQNQfHB0Dt6W/7+W//xyyNh9GG6DEtuXc
12qA12TDDIZuoBKZnwjgszDsEjaXVGWuLuUagrDZrXozGIiDn2ZsdIB4IeueIPWO6cJhbiyUaVSP
KQzxK6AyjqLHls9QzqkUQQz4Va7h8JPADNXg8ZmxeR7Sqs0HpwNPEi1mJ4dDEb5fpfkd2YErAz1C
oRBZRcIbvsHLUeLvcz4m8ML3wAPWhKcEyx98Jn+DoGeIhFE/SPTvrzinxMAN/9c89O/EGSIipuss
Z3ofHGQXjAtmjuMuZ6/DFynoc1nZ8hPZjkhBQcxOkN8mMoZw4cVbrK1H5owpvnPFDvKhxCRytsai
tdjr4RmZQr1l8v7t9f4XDmOsTsm+AEdN3/cBJdMtJKTUvh+OroxcZcV8uikt9GoKkyjmxSVy8Y/Q
5L1xoux2W49ause+wawS4Z0r/RbqYxrPHJkM1lyOLvXwzxSUeAbQ6LR2gGGEH0CIaLL3bqOIvG6N
3/F2Q5rCdlxL49wwlFpb59zoQciXEFZN1e0RKqXg18VkaCu/tDXNyOrp46iYzOQLJxPmYiPYwRDL
9/oMiiqi/WF0TAmHBoK0g9McTcknmH0+GNBfyya3oPLV3VIJPkEfE+cdSxP866VhjRS8arSgybgg
auDeA/ueYGSbHq/oKU/Yh6ZyEGDgayYnc+23WT3e9RSE2vcV7U3Mqk4Eo9J7yxhDraB94JR+cKXc
gI/Ug19oQOWYfQpj5NDB5LsGWGWGLnj6WMGlp5oMVDSVXaig6LQ4/FK2MpjWPMKjDTAssSn0fvnw
f3pQZAXwJ6fBA9r0NGChMPW+NK5mI2kPn3JAZgNngzutwbwFHY1tb38mMludvGAxKTiOyTBhHOF5
mXktR+VuWHdJ55LM5MRKv5HgzNHWv1+OMvIB7ukxtV44PUsTyULZswQ6h9Tin4J7gIXGgdytrjO2
DuTGfXHTZv1nZK7j6c4nZBlyUiMc94CFy/xUJvw4cOw1+z+4IkrnEO/04zvw0bWvmqNcQjkbdNZA
R3tkJhnb5N7YJGMTRbwF/6iM3kHmjtgh5tL2ldkHKBoIgJDFVRwYlDM1507kbyL2NI0fKa2PtEqI
mVIh7zSIX2LaYHfH7Se4p4HlbwW8HWW7U8WLu3QkBh538UjN/cvd6Q1Yr+53tSiHS1huLd5umAj3
V6Hu7hqE2UnvL02dqytnkDgu7bUH9hBrpMa9iauF99qklBGPVqY/aKl99Rj1edWZGDQwBqUZmU8g
lYfJ1eJ7QJ7rKvhnJ4kC2YlUuadRIytYnLo54M4FgG4xHoIvMFIvABj2AZXY0hqkfLske5oI/A/D
z46W6LYNZ0foHp5ekO/60uil9d4GNfqeDzkY1A4PThN8e77CNzRE9+Txupe5I+1uAc5NOYiExDRv
WltXManIJJiQpsBJktO3fB+mgibDXYdptfXPuamUH/Ilxx6mowYRM/gMMhIQxRfxksITx4fhiZy9
O6CgitnBeLVLWbxl9QVreGuI0WKGSW5pUoLrVMVInEqCl95o+gIO7OK0G/sQeCudV4107Qxn9rrs
YnaEJ51JnsV+PAd9SfVFgc2EA9BaI11tCI2ylfllXFX39BvkR7yx5EeRCmWIo6+yaycf08V9YREk
Mw2cvMsw7YrkoD3GauR3IEwnt78+NvdpIM4pouByJh+Paoqt9xEBU5G3dRgW8vHkOcuSllWssIXJ
D7z/p+1djr3ul+OD1xSEhXd40FvuTnsKxZsOD1FmcMGKNDIxGohu5UvXk5V5Yg1ONI5LZbNp/mza
0NkQoxlqau3gNqLGDZnPDDQvuPR9ObMbVI8gLKg4ntHVZ4iVjAwwC6kkOeJVuR1JCrhGdHtDS8jS
uRMluRFdzpwuq/7tI+cLqy+vCShRSUw2cxAqqmE7ZYQA6CSfey0PBCMLjLck+mXxCDoZHhgIIjpg
ziN4I9S4KXKzE27b7FZ/tqPngO46H9t5Gbgg8eFsRqiDocONPX7xGP/p3AT5yyCNcTbOaqBttB6H
ofBWUHqwJi9hTbsVOUefqhQKPiBq4bSvascjyEFPknE7xpk9Z7qltnaBOjlGGj/Y87EeQCF+uY3I
3h7wZKjVVJ0kiGO+y5gYUB4cJprzTf/3nZbO+0ERE4PocVGXCJ/nM4uecER/m1aydOnLwRegzodz
6JhfXOZSvjTcpsIrYNiy+NPilRVm7jZkXd9+ZMNmbTu4y5T15oUxMwnnkwgTKvCT/HpBaaulgCdl
Fl2T0k22odBSqcjYGDhy43EiVBDgrlc+J6rU8nJxcXLxexObCHjmTQj2WK6yX2sQSbnxvChUMJ0o
t7IAX1A5OV+jRFJFyjiDhvZAvACCVk74WnltWL3ERGRYBBZxVeFpoXUbWVz7oJvi84XcGOR/OP5g
kfa0lEAZ2NHVq9Ul5ewARAOHDcHlGbfHWhKni6O0Q/Yl6qEy5ptrkEApkd5+VlziTlnTRFlTFYrT
hWyjwMP4Up3YYily7ykKpcCulODimT+rqDLR3sY9ARkGaqaP/fvw103pz9kdcT23fnpnTOMRxTHH
t/LSvFxDXHt680UbCz0xZbAbLn0J+O36hlpjEiLyNpdv8AdjpAOa8lDcw/hkMsi5gLnwiyHPtQnF
vQ/EiMDiouWKgLQe2NrkakbmDWmMCfdblMj13QrWn8PEiGnjufZa+in2bgAtP+C1IID0HCGKALVn
8tC+HDM5aow6ysm9CITvUBcDP4/zOMkdW5wD3ICB9KJai9Up0RDHf83oJq0390rxwUz5WECA64Tb
rzm0EIrChD3914kaBuzHX5fWHgd7lK5GiNJH47wE92B12Or7zsvD+U9sFB4oiMOSK2CXrKaM087i
KPVjB62nXQ7j8uRjf+wwsgs+7JQqcCfTMdA7QCwvWkl7Bs1j9fBpstDl8MW9ZdgyqRE8ofSYDywF
MVtiVp/LMpIJIXTuh/wOql3xQA3VAqABlS7baR/c5Vjpx1SUpNfFsWxfqIdCk11RxjbOfvuqgswE
MpauWiZGIdkZLgkuiM5CjAKI9zyJlm7t8/miLUxH3uUzb24aBowSYG68COTNsKXDhlnFcg7W42Yu
WFx/Phaw6RCJlUMCmto5I0zhk2YshFkCPa4rXf0L4KzhV+RqBFrl+udvemXyS0s2jJh3ODcPEbpF
71uqpu/CzQ9XgqCC+2y7bKKS4R2G2lUIjYxPTmbYiSp4poEsNjWWUzFq6y5r7tk36RjeZZEICmKT
n7VZADG8HCmnI3HowwC2XWNC1eTuWuc13tNZZO5IEViUSgkA9gUNPHKStMwXceNRK54CeIbKBqsU
or2/3RYFLIrMyIPnN+31YDH6Jd6CC3Ado3yOxSZc1Z+NNchkAJ8/ZN7RtJn53Ex4mVFjiNsYAGj6
mI6hO2+/JT29skAzJJ8az8VqcSYYRs7vC5yfqInp3Iu8ncxRG0/RJWPaIHry+ZX5Ynav4MXwl6En
fjbCFGzAh4uANKUlpcEt08fw96eGjtEmKzkGIHf3R1X/N/HWiTPHyhgnv/5sL3w10E9PSYccUNlz
CyM59af/GG+9r1dwpz02q2s/GnbSW7pRHpIELfNO0cFRA5Ejx4Jup448qtGwtLYoEGdg2k09HT0Y
AUJ5yAKxDZWFqYlgCpUk6iEXUEJMeagDRAHO7vtCYrZyewvkYWEIWG6H51CQHoH15IviV0SKR+Z5
y6SkvRXwxj9xQq7ylruWNRUUuaDlkaaAyuByAs7In2bmukayU7wopmn2dGG2u4w6me42vO1Rsy/2
MoqrumWRgIo5jx7LzxUr/DOXSci/07l6tNFSUH8L7Ym5XqHaKFV95Nb3Py1LancYZucI9jq3lKOz
U1pFMX8OsIXGjASYSKA2TCaFtrRd2e55Hz6Alu4qW0ZtT/lVe3L4apSpWs3kWfUL+geCpgWao96o
woSeEVne1w4ao3EYrYhcPRmVcvSJTDakW6XtstmvXdptcg/PhHI1b7zWQj1yKJAnWweqM0k99Uwh
kNUB/2xqbbyeCf8OcAgarmarVV96NZlXhxEBvyIJoaU10X09OMELd9IidKBAAjm0/F211wAZHGii
tCpSA9ivif/VwMfOEtMbt5hZwoqEc0oGZ/FtiQUjhDTZ4dMTyrm2awGIzDQd9MkQ7PMxVTc32TIr
RkQYtKSZOgIlWKeHiWHaT3PmGiWxPE1gXiVxlR70URfI0hLbaYFLjhzzACuC73E5yoxZu0BFiEpK
ecq41ZM8lYa0Kb0/iCtl1WgwKqrpgR5Vy7+gTat9pqDnkbzouXZut2dsxU4J+leB8yTFWu7eo95b
YnoJ9pKX162rPuc91veQkFCi2ihyGRUPgybnIXoOypK8b87mA6oM2RVd54ehjKtg7yJAf2KmAbFy
QeWiygNe6h6vEceoeMj2x9c1L+p+JrOMwHmtc3ZG0dhrmNBpd/CmVjOTytAhTqXd7JHqFNGaTV9E
Y03B0oW5PTslA0UpsnlJtl1sSBXH4Xz0U6SCE7f8hCc5RO/MgWNGPURuKtP9hAUlrTnuk8EAOfJ8
d1f+h7PVOYsJPIDHULpxU5Hyo7xVltRl1U8MfHP5+HAXCh92gAcB0Qv/bv9tIZePiRyZWermbyqo
RU8b48+C9auggDkGhGddDJDmez3kQatfJf4W4z+n1dHKdtIJw2hlMEAYHsBR1JK4X5U2ReHLNyT1
YiBsYEa5CZ0ehe2B5hN4KffzMf6OvfuJxe/0fEBcgxK5MWB1k5nd8Iy0lqOLhEoiFdEqbq09UYQa
RHizrgGtvWePRI7ib9EkDQ87Hz3H2ycz1NyhFn7EBAs+Xf6wWhSgsTb19C718eW7z1S1Cw7Yx2jp
AhLvW+1xE4BnWdGdT0fftElZSSLyqWtkufrQbCY/+eu7Hf/cVi2VL6Yp0HK9Hz+zHmj+LFkQlJf6
uOe6wF9IzGZC7sxX2IZ3H52gSrSm08+WZ5YWhh9vpe9i+/uryAykwSMMIykdffj/Yw0SqqpT/TkR
UQcWTbENWu1bZjzMPSZ+hfha7rtgI7LmEjhcOiEr/aGTpPQuVh499lajBFYR2XX5sbyi2xWzh/hx
bO4xWlKJVGD64oeip79AsoxNkHmka+1wjE7oUn77O3Qmrfhd9mylxrN+F3BR5XfLbeboOSW8COMA
ubfApjdqSD0uySJJTY+er+Ir9TNNhWijUMKGybs9hIZhEzH/53X/I3tc+1hBq58V07JWPZMTDdJB
gnQGlSGDlHfCjWNEQD+N+hTvlM1mLGT6Y75vW3wzY0AccKgRMmE02619nkT/mQw8amzUzBu6q5OK
raH4UVlFbjDAANkbKsWKBCokT0h7ooUVg9PCaRtzCjY2+/sN6oZvRdLjodHBYwqMaVpW1AC7n84H
HhFJ7WdkmE4og975zVS6HQ2myTjZvMB7MhHUnajvxgP4IQ3qJE885YEVUmF3C4aDvEytaPpFn5m7
+hDOBruM1OcUhAor1kjgqd4nyRLGSbU7oq5aNQEjgin1aO0P41G8NyZyTIR6UykYBt2KhnDZ8Bra
kg9pCW57mKz2iXyMDRti72LehGSt6T2MYmbi18WBFZHi9BJp/OvjW6OHJWR5BKALLndjrEINLdu/
O2aA+RDeLPB9rt/w1hhDi7yz7L65D5H4vAxsygdoXF+aTSB47NUzK0CZKdGO3/T/K+4TIsxCeKEr
9Aw7SnIYR+NMVsyMTE3MbF/IqGO5wZrf/LLcJkGGXs2lJwPXd8cseOy6BgPeHZH4ES16OxLsNBJI
TgsNXiDLJ4MSDKZtTbTLn2+R0bfjhZY/vyVc+YKVMv+R0ySoqjpyAXlL5gupQVIECJOgPUdJZttH
Clv/njsBR6RTliMQjPqRvnfAUqUSm88Q59Gfpr8AgkdHqwqhhlpQFdrzjt5odLQq9HRIs+1WrfLT
DyqBtpQLGdO5rhO0HLukZxyN8JKT+WvDhbKYC3OMF2WhKQe4nD4z+3Xdf2SKRmK5V+oxUdduWC0/
HFGCgzIu8XunpoPmkInRc9gQ1RBzkE8hQVfZe9Q+Ny7JwFxYFvCNJATvC3vI8uFDiANwWTaK2KDF
TJ+sPePOjqbbDsSndbnfuAqnuiRNEnBVH+rcWBSDDkdxDFh7OL8qWqJRAlhWVnCzU/ORWYMtDpDa
TXAQ4+aDslTUMjjOAev+F48RF0I0+XohObJpDrx2w5LCO9nFMDhu3FX8vjDoZoMg2nIpdYIOP0J6
5AmGWWAy4QDgdHePlEUTaL/7LoBiv+zdziVXzUV7TZaUG4MRWpHB0pl9MW5Q4QKLmzTteGcwMWlZ
oX7BjdLIG00LiuDb+strw/s7opk2Q2qcYH84UzSXfK1gb+kyS3qhmk8jGJTKiWP7AjgHbXTOYBH8
MRvuP1A53GnTdNM+q+awjw0hGfKJ96V3JnmqjeQn+S93LvrNTEpcUpaQ0HQ3CQESFuuQHJ3cvixk
nEYSC8/g1G2UI6c1isNe7YyodmrYWJ58OL8pnw7Q1ZlwOa5UUxOhQm3xVCyOzXnWZN9fGX2bOkob
r2KjuL8xgIYhtqOTEwwHys3yfDVHUuSaE0s//9noEiireHROUrTHufnzwnbQI5MnkoC5gVvnN8yx
lkLMsrIHzGFPhEMQaqxfSPxvl0yB/6WPwlvcHkmY4aH41ykfBItlEFfnWbugSupcdWUEcuezw04j
TazN9MdVzHtL1rjXdv9LSZyw1fVlssLgRgp6MTd+6tDaBxtKuVY7zNtmaTU7zD+Te9nFJ6r91vKA
xKH90QkQNVmc/RDewKcVlV1zd8CnT9e9rMOdTUnbm0Fg4JyE30TiRZ/NZ1WO2P4Nf4n4qOk0vUB+
BhSe7LiN0OS5k/5IPv3KOl16/WZ7S9cICcb2xh2iHC1opWLYSFp+rqbEsj7jdUNIkEZP0HuyP1Mw
DDdMqLJYakq3LHNX/Iw0vw2mux9rHL57UXNBLKH3i3/+MGRq8L4hnZGCyVLntXOYmrxYSdwdyf8w
K1pvYuzKLFtYOkp5t5COb8RDaBbevsXQPnDJ1CLZ6ixlWTg2wiRWRaCkJzRH7yeC8m3Lzp2dKAps
5s/pCAURpyJgl6MbvPWeQKoxI5B8DKuDvZ40khbkDSfOolzgKMsk2LozgE97xvpwT4YnzrBt+YpF
VCza8WUbhLFK1pVsh1xMze4oBIA6iTLHwwX0cBrQxo/vCli46kuyxVSNookkaUOACyft8eoOwB6E
n5MLm56P4ImVTSbQ0BnBxkWD6h9AB+IpUMcsgvAiR4ecPZZEGRayxfbaRPqkwXOFB90H4xs4bL2w
uOC/YGXyiCP9hEk4I0d9lU1ek/7xcTDJjnf6XWiTU9F1J6AHmlOTeyUFGOGwyZRbFL0Z2rN4vgvY
r2XPOd6vLhbju+xwsnOFVHphEy6Ov9kx5NQfehY1DLAEzEmfSZnndkD3VAOeI5pNL4hHLA+7Uepz
Sj9ck2YOzpthQ3Q24GzOxRT+V2yn5bkeYJOU6e8a8QBIR48JUCxejb0Rfg/mKW1/2umUkmFIG0f6
OXBPcX3kjc+fNp7tnxxCbsKMr50R5Fynz73ONriQVtrfqZf8cGISGdtculbCowyVZlY4f6Qzzncl
UhG+9KOlCzl7Zgap4UsCbUX6mCUK+U7gYldcN8KbrQWPgXDIfM+v5Dz+YODPxmYdgWHI5O28T5xF
703u0Xsdcw1F10iu4ljubef135W/VSUxx3AgMKExZpmUsnlNuD+50NBgwZTNd7Yz1/2G4XP3+jXt
dKSx3hLfXgV7yNx/1zQnBkOTsOuviY+QSluXLZad8FrcR899QTabGj63B+l4eWHE8wofMsCMBahj
6E2UV8Prn4+Fs/+KZxIqDb9DvCJJV8lh4XhIUvut6vkYDjqawm64LfirjLlo89fz2fwAxe7xWHrT
3gapBrJ1ZBAKCoNH73obW4zx1iDPDajj6/NowUbXEk+TXGYWMzedNMo0b0InxgNo4EV/IBCCX9qG
21XYRlr1wwp8kjQH+Hkp3ZxA8NNSlggB++gSL3E5WukGNIH/V5saUPSjxd75DEBUAPCQw0clq0nx
XCpdmYmDaKOpuDnbBAah1eHBnVoHW1Fd/GCYWJU6w+ItBdjx5R2iTUCFdLEVyDo0SeX2d8rFV+ck
78Z0an65S5eBSthMYT3tnPMbDcBf/h2Voa0WyDJYIK24hEk8xqwKrLyac8JlErQ/DryVrZCYuLum
XCPMXthxc9lNe9Z9WvGI2CMLqROEjexrTnYp+oZo8DY7XqFe+lELkmXkUxnDgfuvu7aJ/OGOR4pj
qkBsN6qqZSWtEAzhe9+EFe2YrWFacEm/ijC8PneMdiv3ZQhYSrFYVZzXIE8+j3rrTbe3iw2rErGF
paJQC2ke+3iHYFKMdk+Cveq64JzXHdmx+Lhf10dBGNv7WCexEW9YhHt72Buvj5wIRc6osCIeHIbF
AxnBI6NduojYV9eQhiWdHmzCYMAxYYkUvTcSY+c+Y2HSaBfRi0Oq0f4fa4nJcbTrhLv9kj7z4IWg
zEYxO/MK8shE5mQLM3rWAbbhWuokRAWDViwuUhB0tNQDdKSvZ3XEpwQslzVGW363pDcMVyeRKL+O
nA6NXN+5gPV+Gly3wQEKA5Q15Y5K0CpWMfuH4ibICXy+I9bIMdmSLQxM05BTqGseiDW44Cc5xyra
BjycK6gMS7zyU+so1nDI2IIiKR7JNQD2yWk15V5iivd2qEpRITMQMUiXwJnCL5dXy5GTjab7XVQT
qNjQF3IPteYImCRnD1M5o/cqhN7qxWpHXbj0s/H1GZGi1ILELvn3EDkKm5I3v6wFH0OIvidzbieT
rIu53MBI0SqsKsADD2Bj24hpJoI5hnJ1+PkuZ8Q3WzD4TUEirWD6q4sqcPBwteMZlw1zUqaq9Z+w
dIx9J1tRbF5N4jfkDuX5aN3daIFJqd6qPKse0AH6lsczHy+HXjLiEvmP4VdtV/WquIiA91zVJjZl
eu8O0lNTab80Wm02AzwEC7FgtObisc0lFTf8o5z1rdCmzurdtsi8khb4T8IBbmz7V6kIZe33IYwM
zXeFGQwdhsH+rBHt/TZYKzkGoGkaDsrJBAZfnaQnmpcC8A3awpUJv59DToz1ZWmXtfZITApOSOgP
vBiSW7OixymSkyGsw+Io17nzubmufxDjZLJP3Xv3gtGRJZA3w7ttLPCQjhmbCHq2SYUDUJF5PVMl
MjNrOZELMmefG7VEegsjxdrYTX7ajX3LZw4z4Pzm/yLQNLFf8IgbU1AakCKzZ0i4JiVUr9tM3jLv
sLVB7qPOlBTBdD6a2K9a3arU33zTWCaJcAd5v8W5reAEKfZ0M5LxXFlZ10Xm6uc23qFIJ3r1dTUP
Mn/UgHWlkOrg9uBLoHktX1vqSOEf1KNN3om8NCq5xf5ZuAYAK2bCH1n3iAmOMzTBl09wKYf30Mw0
4zoXZSY4Tg5bZlBXqYCDDlsmfSJpenoFG4EuG59fkHTAmsdOj8qe+f2aJzq/cp0k8LwWGQdb85St
r9ERY37hfcEcD77v6LIdOPjKBa4PHpRT2EI3MqcKaRVqlgsLn+oQZ3gBjPTzmGhB9XwzLpMU0BPX
6SHUwLdD5jhLB6KSp38WuGCPF7NQMaOUcyYR63x4GUAiM8oEgoV8CR0IG99/8q14MJR5paY7zKoP
mfmvisPUrLFzrOTA5SEONZ/q+iR1s18yeL0m/4tgFa7kytmcc3B7qjb+JR5PxEzwYnICRV5345ON
Y7S82gI0iQbECG4RHU14st3abWm1uaoF/kipdfopvLoO8BUn9yE7s6ThIxKEvVSSKEsbueO4uYv6
6LyE/8PTSmaUTMBIKoOVfdQ/h7nuhMHHZqK1zlkzdXprCOTzm6K79E7FDSUM4ZdLMQscZm/sasUW
PFlVZ5GfdIdECYvdAcNv6KsZnQ3K4kpLJFKq6fMFh5j4heiaOb2U3O3lfcqu34VkL7Fc3+uaw7zj
NucA6qUEQAz2FXuS9/EkY66eRgXoPn4r4DUDR9N28lR3KFdsrU/NXBT0sDYLn+gpDsPhaEoCCoyX
v7dnk9kRvBmg/Scnipm5uAn8MmOAYcB+gtDwXSfbFAV9P4RPy1bZAj8hbqqmwiB4VkOVLCoKTN20
F3BjqQWkspuebfYglskYU5uAuSnd4B/Z2OyNx4KtIY1oTJDjoHUAcTQZRRwk0uG1Whr8l4LCS+Og
1lUSI157JV4wpF581ZR0Cixis2S0pMpLfCUt1d7sAyvgrhOi/EMOH48WZxlXD7YtMl+JDnWY5kww
ImB4DWEj/CiYikEkQqtuTEsmFm2tawbg/V3etpD5k2p6DELtpAeYrGbmbkl8ObrjuwHPhmps3ONW
bDg1tKTUZGYmvH2nHHps+VnHa68vRd3bHTMo8VwjW3XVQCJiYisBGx2PiS1vDISOrJIkIzm7+dlr
UkZ6DyaRn+Oo2ytippDW4N6tOnS1vu4YlL6iB3YfC4o4C2fhzRD3WVzze5VDEM1tb5Op1MqAniFg
JOA2NjVrC5F5pdwscKRplEZbKAg+mSLgkG6Q6AJI59ZU+vIjGS4OwntFOquRrDu4zJrj4MSNmhSU
XvhrdryRZG2PuJymbAlKtvwLTWV4o9Mact28JlkoqLbHB3zHsPDpJ5e7ziYv4WHLHssOj6+QI5uB
WIla/pU+C7b9uW0g2nCasTIY6DzJxqip0OvIVxcm73sNvf5F5LAjE8u8WJPE9UuajwboCPCeD+S4
g1a9r8FaOSVJfIOa5LkAfY71hUe4TkRpWEQLEY8CxXn67UOgrCdh8lVqAxN1qFICCsprk/BP9xqa
F0O4V8foSjSYBM7M0PjnyE6CKdoYla/w69YUJ/KdABlD7OjfFWgWDXrDoW82uI39SubLZQoMvlQ2
fe2fKJmzbh7cnBwnOhSOnnp2n4QAdBHZdllq0TR4HIT9R5wQhEmjGjsDDyfAoDi3W9xfVplGr7qr
74Ixo0fB2NukfGY9XiQwwrP1cgzcwvXGiaxOXtyTleUxS5UltZoUS0mG3wBo7h56IJSAS+3TTddO
Lrly8WrFZEZkSZmX+f18g85FryqYfRddsvNyfgz/5FX0t2mchZXH1+hE/hakwvzWIgnClLboKkeP
YNBSC4QkziOOMwUBN50UjnoKSVGr24XFwIUhtrjnon4CUFUrF9/gn50N7HZ+oyUMS/X/d10oYTvz
uhj5diXqXDBYuQjJYAKevQuZ/e7/oAAN0hZY2vot2ubNMX9YFIKSuC7FpHFey4z1N/3FzsRszo95
QjxYa91DZLvK4oQtYOaJf01IJ1LQdhvBE2Pf4d7ZoNx0mtBcJMGzuufD1ShgxGoZ47LI60jJBejJ
7dv5BO3FAsgUUOD3pTuPuemsp/dFC3tCRNGiH5eGQ+rMZBCGYeYFtR9vnd8M0i5IYv+4fVyO7ufh
7VeNFWtBD6QzbZpjpqn7U7vnAvL6dR7prDA+T8DmzyS5cOPmpXJ6HJXK/8SxFaZz+yErb+9vmqsl
cNAK0y0KZ3YjxjqVUlGzj/0rYn7xBLLu+5MHr424dGf8VveJhwFs8zIRZClq6UVbP5dVygGjv3nb
jsDT357RPKOQh0pNiYRBs5P6CbXwS1FOQWOioOqHvPcbmeB3LZlW6QROrl12gnT5O4c8sUwRCBVv
imSeigwBeYZsH9/6ymN/Dws5TYoDr3YpXHDGAptTTrzGqkr8vDSXjnM8jvIbveVoxq22ssoiA+VI
1nEv5yNJSIdNkDaCsn+lGFsW1J1IyA9z8FuVCfC1j0ebwj4Dt5pOMhHJef630yBRhcNoKUhJCM5G
TXFHUdT0JSX4PY5xyEta6OpW2MqLabuVLHgiTnt2j2+CLqP94nDQjEku6CQ33jVlWluHKcVS+3vY
x/B0MbuAI/edab7rEyE5XBuds7AiER6RZDIW5rVI10ixiFwJunjdQXW7R+e6Uhr5xYPcvGvtAhmf
4WfV49OqAtYpvyuOw1c3EWxqMUiN08Kmm+0v5BhBwsc+03GMyczqC1DTgI6/uNDE3NNPjKjAEwBd
q+Zawrf+3cSkh5bktHnbloOx4XL2UN2HLjc8D8tBbvPijU2fTRglLngUi894Rl9VLKr4bz8MKKsz
rTmQF9Bxw7cogZhbXicpem9btCBxj7ZoM0sOKpLwBsleFFCRxwnf5EFpS0CvzpCudtfkzx/4e26Z
/hup5dthcX2anUoI8r06dFNDuy06dm7JUjjUpzr965GW9yiPdQj8ROfZLnNz+iLHyvTvPq9ghkyJ
S5qKcwzcqLyye+mHd+NQw9lU5hJn1PbAilDYo0cA5Sr7OuAFDSfbzERq+n6ugBbJ5pwiD3aT4rwB
jnWuzsQ0C8yiNwss1pECMjQ1j9flO5jsoPhZ9HrOikdUTBQZ7DB6U4lT/kSaiM37U3y1plHKX6QU
/dp5rTnAIFwbqdXei8Bv8vXnb3eU8WfMO6K2IAW//YXlYZr8ajfiP9nPeRFqMqlKbszaPZMyk85C
/WKJj4aq29FITRDN8J5AuhXvOg12euxhzIIbfn2ce/lyQvEsPhTbGlr462SMUSsJoOcpMr7i8DSP
4dLoLWMfTCjYYNrfBM6ca14awVfcxgYVr0kOGVJKk4DcitMLK4w+ujIZXtlJgMRDrmpGo+J1s0n7
gHTYRd1FY23pWRjZOvXOEg1xVo4wGVTV+MaxQ/MWqI7PTLhwRvh+lnS+1P/sVy7O+2qyNYly5F82
c4G3Xt9UZbVHT1lbkby0lfXiZsJec2pfku0atkCL7SGO3UCSRjXPYV7RFCRVFD5W/zTLwPw6Eck+
LThlsPbze9DlbvG3weK9U3LVN+vuKlkBsnDrhp5uDdu1xiI2w0ewHA2gh+d5HeOP0sGExihXwRVf
cHGGXx5eCwEOaJ9k0g/0SlsrKD/0Lxx4Hm5BHAMAs+BuMz3etA1ECXTEKQ830E9+GsD3rsCr69g5
gFpbXVWqjPz/U5V8j/rMT472ypbWDpFZ1mRWd/b8XF9KmUq4WLfrfSj0WIbdmZcyjnl/XKIFupU+
rRL4tzwlfqGyb5gDE4j43LQ9pkoRMfq5kww6GMowP/vKlf3tiDtIneKZVcZ7ae3HucQY4RoRaunY
QHkR3TiHgZ1xW/fw3TSN9libmYR3ougAtzji0zJ8YlWO+6yAOb87aPwzP/nqxQFR3sxXfuTxTmBC
mxtCZO2HhF3+3FprykDq29CkZkmD1hMy7gOeWC9wmTj2vHpbeS4jmURguyk79avMTTbEN8A6AmRp
5+SYMmqAwsquY3TykBKhXmcnPliXvwufHjlZaby1Xuw/xgVgL7ctEnoEFNXDL/+8rHyOJ0UBkjGU
jOpYySlbJBlnKx6L1rrCb1QNVhGNLZo9tAcizRhMPNt9lNRPPu5/YQMPiPtNnjvWu6o8OKLowFOy
Yd8V2GVkEPbauUxjYPd7W3E0+j9mXZWRVA1pRqCk9XNcTsUG4uEPV9T1cvC6EVhSaGi2ytz0ugI6
TXIBkbfqcqbrjS2442odWZVZpwUx2nFPu2sQBWosda9AK7HZnvaNb+5dd9GN7Qf9OPNll2NzLDAr
XCIwGRQyaic/IHs7dISf5Thk8JZjQVjwBnn4Ubf3ZaC8b2UQtbbU3K/Rk478GTgDk73nxGBA4PgG
Ck+3nTKyz0pJ9owZ0ioGin3Hy81Pq+Ef5I9C74MMsB3Ex2weiWpKlUVFOqLkFV0vrTjMf3JAPjWw
Qfl6PxFBaXhD2Iv7HL11F3+rFlbjQtmre/uCEdVpC8vsws/WxxjoanY9lEo76paQqHocaqaexmO0
7mjTfCbjlj2hOM++rdJoI/B6FMs5yz/+JAPuDhrwXQ3gA0egx674j7gdquvbrh5PBjIqWjemu2Rn
vq3dmOP3jaKUQGafchQwY4IPqUueV/90SnPvMjbs6GWpOiJUrmz+Mj8m3uYQ/IwSvhrB4LCRxpSV
1nhgTCJGQWEO995mg/LgFHXIYwtXM5IlajyETBuBEhecyyRP1+6LXlR+HVEFBSkqpDb0FxpmUxtG
zxIP1/Zr3oInyQeHz34ZiM/nttuMco8Etn7sl7a2IX5NlDgczJsAlCXOTGJbysV0AkjUP8/52oad
0m8m3sg6Q9s7uR0tO9cMO/O8EIrj18zGalOMw+HMpXn31dblYFcl0dr+3nVB6w7CbCOPMhYZ07OO
WQ1HiefL/oPHSxa77Hjo8ya+/LwAdLQJfzYgp4uCu7NMEYYKN2vVOdNggBrQyRZgnHcW8HZpjJQl
oSd93N/6jBMRIdBc4VOYlLpEv4qbv2nvW200+dT5W/aiITgb7QM84q6n2zCZLyyY7pMmSFQSmWmt
lOBYRuEuBFRYKKgjRKuGz0jn3jwhxvxXdd68J7UsLpJSgRIjg5MSn6tUg3JdcAE6R7dEN8A3xNB3
nERpkWRh8LDwaDlwv6oI/9RjdIJlDh+SYICRgU8I/ol0CRTwnHPtukfnC8wCeyAzcj3tRQReN4Qw
65mWDjB6MRG6b8qLm0Rv5OzpeCHSJeFDSdwshKigb/CAeFUpGgW8MSpKZscFrLb46kyNTeKT0Zs4
zk3KW/NMep60LS6cKe6r9EN/3g80uRHqzOQcoLAmWXOOtKKK3MsTyhMzt7QXwxAwniWSoWybLF/G
NaOko8epFPGf3lapQIOPiFZQYzBDUqcAfgG22GXKjyESKXkIrCidhlwzAVOEQzjlpHamPXBrrqaF
emmWiBOtE9RqkArcl7NQmZNN/rnDHjy2VOiw6s8DDWyvhNpbu3Lgjjo2HN7d+Hpwzzk+YK5D0r5j
zQsig53Ruq7FDMwU2ry+Xf8hUaBR5boZqoq4CdGPD8dqX56ZwjmatPN3fPlAVQPuY2alSfxWIpWL
/FNkm65vgQ5fbhzrhRhLw7nyiAJMr5K9u2kQN1TNzXcDJBiucwcrsvj+0bjkVueiEh+8ILcRXyiv
aQzZC/diFhRcRLenGTsRZn6h/TrhzgL1+2IBs1olEwsRZO/msg0YdlCExc4N81G6dIsiwNMlT50c
cOEcS4QTTkeoE6Fe/1NS2WuVGQ+DhUiRRO3NKHULnS6todeiwISN+CMMxQJVXu37hAvLhWDR+BD9
t3ubny07gvOhYfzV8fld//jRS8N+Scoi7VDoa5Yxk/YHW8de9N6s6I8hRyWckFS5Rbg7lt8jhZhn
OqTT6TTH7xlhf8iSU71IXuYrkJ72tJaNOrQyRh24kSFCrTAHeZCUAId3oaeC1cvaihroFOgkT9I3
XTeMTZw27i9Eh0bUZoqbB999UAhW/u2ip8Xk6lwvv3P+XUkspqcy4rGqe8XdZlxO4czJhyIopgZb
AfmawCDoPmNwQR+2dDAS0lhY7U+kNvQNpl+lrSUaFAdhWODyzpLQVaFLIhbO1xRxK4/iQOY4jvB+
kbdj613NcAwswUgkL1lSfPxiFsjtuvZN3G6+692kbrEv9VC8QlDdIEc3kiksJjgeGlO1bhmaLsFf
YcmJ6OXl7ZoYVdqgUzh7g6wjCutrCAR2AeTOMu2g4XnBwoT+zKrq3a9gQIkfmgnuc8/oDkjj5xuZ
LloR/r8diMP9ykpaA/bkRaBEGrzd7/bJWciwRaq++3M1d4ckqTbExBo6n8wlm3P7LXyVv45c3L8m
wZNbg4kSRijHewiFFqGJJ/ZqVjwfATk6w84ihbD+HiKE2s49+Tpsf4EheuaLOTg3Quq7/5aP58O6
qirmYYcYLpcFky3imnU4z/T207K3rl6r4cmuiNgESJ/DMV7l385H2dWE2Wqrdm7z+78sfTNGIjvr
ytqZrFNoemZDVnFTQGy/H9t2FXTpRBzHC38SYO+cTv8dHkPD4oQ4xW3T3UDV3aOE38cT7Z3Jg/IH
eR9Yi9qf+CD576wAb+oh3jLqurPIA/k1/0+6Xg/ohwPlg6Yq0Ss22POZoHMI0zCQx/3/GvnRDT1j
4WyvESTKVyJreF2/D1ljT2SJ9zTtf9QDN0ZicgDUak0Sgy0E5CnisFHFeCaAuR8HwRRpCqsnPuzI
yGW2NF+DHbvRLZjxs3wk92BgAq/ga8YGIBiWT5uumYMdtcEKL2X2+cSBr8haCQoBnHqMUlkKQLiL
Fdhws/2dnA2/IxeRrJoxr7HahyuK7xk6uTMLcdwAfTPT7xFT9hSKVsPDq7jntf2pQvHqKQoy2YNc
BFNDZDrFiGIdkuoWb1th4jR7+4hN6BIW6VtmF4wwlux2AzvAq7aC3BC/QLioow7klHyBeo7KiiRk
fAIzkRGx3muGwPlDPPSkIbmWgoHAJYjPHjRlcLa5dHFcrQ2IcR9X7DILo9Nedngp0WrZY8AYY65L
Zv6ov0C/M/PruUoftrd9XVDL7WKV6f0keiTWc+sCvCrtEldNDcLsUy+YLCxMomGLo9t6ORqfgS5w
z+Sk5TbFIIdm0vr9h61G+KG1xbgya+qNWU6c+0WuxRH49ior2amFpCHPBvMOjq+NSkOF3grNf9FU
ZsBNj9eDYcA3MErWTOjWis02oNHdVnMnIHwiEC9VEARYmEXDNsmxNtpb1ziJOC1tGpa4zE+IcQA6
mgsfPzyaObUqCsg8KgrtDdMwyeaW/V5EW+B+Gm6bPtRWIqkruKpKQRWx5tFjujVqF6FGCD3b7vXi
sE70IINUyUEiWV15yYFNr6fv4btk3T6RAa6ckM34s3K/MWORCanSOTF7JHChtUocfL+jBkRLoIlq
3VTlLqBbrhzDRVBj+ye66mGQFUHUIbnbHb9aNjpfjdAmiwGKffwt5HNagPOcACPbMga4YFqYfbtK
nbHhUOZWMVPGeTSDTwRA5jxjv47Hld+8gSt5kKnWQHxdSNdM6co6hW2UxK9T/BPGXxrU1lG0Fx1d
AOfz4CZUh/2TLWDh0RLMtjhEXwnQmr0nxYSOOGrrtRE/rOWcG+LAsh7XWtSEJfq9nSrTb0Zz7cIl
tELBomGnjpwCURyOOY1oMLEGknvCEd1u5tPY00moyjYAbHfblg9j7s/vfb09nyvZTAU52ZrcSUyK
atBR0Y2nFxPjKLn54gZcsYJuzyItLDHbqdCWC4rpi4hYDVvAdQTobSLPbc4Zs35o0osT5oGckAxI
iZCT7hCKTExGIudAjqMmEGTQH/CC+z28q8uGNmls2e8lh3QKTIlpScMR09oP55wFjaWLcmbQd/bf
PiqbqfqGIo70vmdSXZs4sYcqmm9e/7d5pg3br9VShrayv1lYJaweP0RdtVPrS+qDrZf/Q+v51wQj
+DebySAoH3phq2DTHPGJf7/Hr+Lx287MidOxjqhgzWZ+29Tyub4v68mvrTv3y7LAbdv0IeKbBLBz
1MiPhmVvOv1wqM2C4BHVtkMiEVVH7TKiY2NOtwkYsgdox8oswlUS5tzECEZ9kkIA9/yGhG1oo3e+
lvWX0+osv5fRC5wbEy8XTkiDq7cF/fG1D2jXxMcRd+pFC9Kx/uPEpiNuKHAdTHh3xhziGFqzSNVk
2K0wZeV89oPLKBCLJBibDEB/3AqoSM6vqkeXnX7U1ERn/Ba2QKGM0ea+48/bzb/Lt5vuzQqAeWb9
m8CsjQav1B6pzEzuBon9U3Q5mC8CMuMgH8Clbu2pSNtui5NVNiPEatBIzfMdY/GXCJg78wndyt74
yeTdrdLW2Nt6g0dFfvEl/LuafobvsxTzLxrNJJ0Q6c7NP/ZNGzSlmbWA1CeG6dHnN5Gh0wLGTKQk
aWHweXFxrftF5rcWRysutuWZ9HRLpTTC51life2Ns3pU8URl2ofIP/F2gRn408itlPRkrad378xL
SNboBooVooWqEuGfEOTuMOTRaOgtEmX6WcYsfUjs1z+NZ1s9DP21ATHOkxVI2SF6qhevxdk9yTAJ
XuTBnU9gjDEu5o9tZrM1QwwyESPXEa1iXW4IVt/Kmao/+Ntd9hg4JR2YEt/XP0eK4A+Vrp5FdvRj
+4WdIoQ6s5TyElBtW+qk4nYZEkKSVOzoZT53qGsvkC+nAR/1R/Zqwg9ZPcTpeBBDS71fmCroRfva
5MOLewWGSzaVD37UPxBtn8vOE0zhcPzpPyDLHk3lUY48CqLMCLkDrtdZC/1GYjOF69VD0vuPQ3LV
8kl0mALRfyqefuXHoGzrdD3EbWZafTC1SnUoIeeV0YWsMylTZ6XVbqPLRn/K2PYdi2UgKkAc+SC1
J+zLd0X5WzkC3X5L4HTMufZtuhGzb2uBovU22ucT1zDeNCHeyNSRWNQXZaTIam1YmnyatkcKn55c
bv7wil+dTUynluKX5Ey7t3XL9s0ahWjZehHrsAoK5GQnws4Y7qviwGMElGxYNIBQG7l7rMuEbtFi
6oVZAJ3vHxq4EVzWX3x2TH6bRa3j3XhRaPDZrnO4o1hbqShWoKFAiWymh8CSX0dWUQj5viXwqbi4
9m08/7eBfgpcYJpud/025X3ZDftqRC7BG5Q6Qn4D3r4fY3ETtHnUFImk0q+JG4xmJlE3UxzkNFNp
syo8mCNnXPBd92n+Oz1B7fxR+CbEIk7Pww9+ltyiVXx4tSsvU1cgfKVpyotAI46BsIbm4OMkJ3L7
sgGnvo2ae/Zsvc9YaRXZN5tQB5Vldc4CunlSx88499SXu8KLWOStnhx4D/RagmTGwkjKBXX7M65W
WWg9urbUy0vhBe6zRSrb2tTcI6kNAlJlMNzdiL9vtvkhzDrkcAfFC5QqwwFUR28q1ebOBt2pz1T2
z2qpMhLLl3DLQLCaEvkTm9xKL+FKJaCvMlvQKYXmrq5YKmxKcQdcGZWyyHjQoIarbQJnJ3nTbVW4
ZOdzsGG30wXbbQed2Br7nuaSiQRJSyrLDkJ0mlrMiruTZF1/fAfeGUbABXaLAQxe2EBsDb/KcOz4
BsEzpBfD5L/qNeosfL/1vcH6IvOhXeLvST25G2We0CHJhlrrBtvHQRNfsVsISo2Yp2sz6Puh9ONU
Im+jaz0CjsG8Tk80mZQAEQDOJuwVzXEgadP+GeEvQ7dtQHx15S1NZEKtI7COYMTb6WkCDg0rU1YR
EybVQQV9yT52bW2WkKGnJyfs2JIRE9TKASzc4ECc5WxnSHjTugwGOwnYQkJHmwRm9tZp5zm35eQW
o3fz1PO6xKH79jX3Wl9dPtcKDpbAArgdiTALLqgPa5GGTNBnttamUFU0iU1w1Q8DGif8KsA6oQwY
MkKMtw87YUDzHNbR5iVi7YosuobKTWzWB2uM0YwZ4ansDvat6ONeUqoe9i+V9MNM0plzoEl0jE4M
wDmqLCfrbWYxMUwSQM42ekaakWd57BFZcCbGIPnusaPdITCzBMyJ+l7M/hBGQ4mLctRf7+2+4WCx
8z91PyX7xYOlkZXN4eNjAOMWjZuzzRN25tz2x7piIN72n/FX4f74ivzKknZCCsE2exsJAOy6Gc6Q
c5OHfqvjGpLx168+ecuPrDQGTofyWKlSH+MMQLK/tCXjscFnFVhwn4BMWHwRh1B0atjKHtXjOrv6
w5bQvqay6Q0OE75m/O47oZwyQ8Np1I5KJtjCnnhEolnELMR9eAFe2MDzTMz7cklv/OUIEn4Knm1S
bXJj9bisSTtfNVSBOoCgTVEl9z9fHdytpkgFTBG8uOz248UWaB1tTc6tHGmFn8J8S5gY8jaEINjM
woO3RJwt4/Vz41sMFtO8gZhJ2Z4L/zGx5yG3oq8qjNNuCuNb6OOjAAHD+IajJ9FE7qEB5v+BqA1P
2ZBXZDok1UsDXx6sAbkB9b0/4oAba6D0KrN4fCLV2kM3BIOLGdHVeC2Px/Xw2ZCfwBy+41xBX1ga
rE6k9PLV2nt+88j8jJh1bvs/aQIh/1y4ZvhGRP8EoeDSdlBb9NUCnkr3IuMiIHJEL9m2JpYQH3p4
UExDM4AFeMZefxvhVdu8obQ+fa8jdFm84h/Dd92YwWUZN7D5n5/LrG30eZ3T4kIzfw/8XqIT5Op3
GBsNqiSEF5eYa970TcmFHacRshJNIWguAIw666wZkSH7IX0uljrDTA92CRfy0zCmBmqapqUleUCr
jDIlMefGq1Cef372wltK3XvS7sZDvRnG7oc6q9YNRetHCzPl1u8i/vkhtXQgvo9g21CSukUzE3PU
xOwvdOPER7l0EWB9YFbXWeRaAaMmo1qL97wIh0Ipf4dP5CxKFVtclMfCy+TUoSk8BT3UD/HMRCG8
jl1Zk2deIQ6WfQX7TgxTa9+uhje6qbEAI2fWp//cxomkUcOqJF0tgiPKujThi6VOce2oR/MgfMBt
EPGStiAIe6KCYMfyLm2QjckW/nTjgCdLi8jATEfrMEtxL8ysxfVUVm9W/FIc+cGSegMSXU0MJ0dw
AxdvNBE14urf5ZZPoLkwvmU2AlaN5MUHuquMUn5viw2Yxr4Kpa2D7oWV4lhoGs69G1JntWnYJiJW
9mOk56oMyg8IJLyCyGxAwJvVac3LjFLJemGPYB5s40WnpHVDYenR0cX3JOrxwSc47bEqnSaRaqP+
87fhZg0yrHTcWkEUU6UmT3dPosiDZG8m3FlMsAyoBrYz+e8QhrbQnfd+O748PR+72YShH34nL2aA
SuVm7orL1TCV7sD1sBaB3w2yHhjL3X7lTeoaraW2hh9+m4BpP15WBQ6Q6jWG080LbvBzUHQ8ND7s
qQSzLwXQqbOdtQ3yOyYfMoQOJfkhAZLA/DtKHjhFE7gg9Ju6FH8/MMSxt16qXrXKywIt4FqKFzNi
jtgMk2W8MFG9Z2w/cjnZ25iik2stIQLa2KsUe43nbOr9pL3fmt8cdu67+evDVrntP9JPfScot7/L
8oMs0A3nrAb/N01dDgjGoJ3c6lWfJ4lM82D7UcmNNmiYBmiuROxS9lvKLoQJ0OXAeIu2SnHCCELE
k3d0q4WqbOBrz9lL5QCLewmgAt7fuVhFMDFu0+bqoulT0xkqwKefU3dBp/AD5aFSt/1fMP645YnS
XQyRbQZImKcJmbpM5okXNv4bpM6xGu1RYW3IZ+Nf20EbHRVZcPuviLh/xRzDWbzjnpSKh63R5VMG
Nx8eJL+Uk9IRukTTqVop7AoDdnMR4t6cpaDXNYZH9ec+10FJzTuupCF9kbUrDGHgZQ8Bu0zYgr6c
B4pRvn4F/PMzb/A+S6TriLSzTR95SzuOSc4Is6qnLygBrlsoBiKfwEdf83muY96AYoZo0jIfckJp
luL8zv3KksuEWySC/vMsTcI2chYi+Z1eypqJWV/6k58JlEEKEuJTCbqBgS3Ykd3Diw/iBTEdfAHE
WvZ2gS61rBzNfoCiBebihxLeObJG6vcUI4UsXFhFqDAF6vW7Zg2M7HMvJvQEc5Pm+xsXaZEULsed
Wfj9q0sOB837rK6Do9V/Pyy039eQLot31yE+nCTDyU+AeUPOpsk7LSvW3gbDqwkLBd5eJhDlvGhc
h8VqrBBeaq5q0CvFQenYMhE5WQpuC7kZxnDBsRMDionW5hV9ltQ1LhyqzGnSR31hhwFYsAFG7d3D
H3aGy1uTTfe6871wF4bbViycKYS6XgTqgk+2pwXHmNQqZiL5zEvdbnurIsOZlVW+GnVEZz8T4kUG
3T/lMuj9yU8mo/WM4oh8O96qv+5GsZrSnwYos8fOoiTQtOdnIv/5MD2Ar4x0xMQgT/H7wE9DUJMu
qoUs4Ucnen+WWpllNGujHNqKQuxcTG7QLK6rCq0TkX4ibM8hjlIAMWPBBVW8/iiAGJ8L3A9uW2HB
yO21b+ZluvboMdW4fCQA0Xf4T6SSc7VGL7+OuDgfTWL8/xj/bxMv9Fs9peuBygK7FUlWPgEwO0Ks
m0j+xfeLkv6GH3M9BeXtJvraX68GwX7tKlymckj1x8e96GwOE/T7Poqs3Yy9Ypvax6TeUmRPWNTy
NSlIgyZiw/cfPwSlLzINyyB2wHs55dQcHA1lu4WjPdnMtCdCq9uHz56xCXzr7Ct15LulKVcj41CQ
M6HKCX8iCiadHBvShLe1Yu6gC9ExMqAI4DuoG8qAHIVJ7C5zRuTJWcnvdN/9RyJ8ClFNmTzoXgrY
16BKcrIwPIyaKBgWb9SZXy2Wa0yeE9XeX9ESiXxDvqOpToL0C6KGBG8zhhPqar85cdc4kdIIHWWS
ZDvi7C0EEs3+6WUv4j9bE+/Ad5m8M/Eas1ztEzqnxdirbj8CcgwvYvJlpGrNR05/licCapsRpWKr
vWxXJwg99RXh/bsaA1tTX03o3gfm4wmjjJE0b5+dwnAAy4+ysvi07uIow5EG/Gws/F8fJ5vCZGfV
AmlK2fBnq6tUl2/XVnjqswl/L6xsARFfLhK59zLLeE+5Ick6X0X4mMefKrnQvYqIANYnC6iaKwDe
C022jePsMynATgsVuHQtYL3GG3A/+sndnDNvdSRH520t0gSrx6KRGa4SbvH5OvjwMND72x3dM9uL
CtM8xiKQD4bC0Pdf7qIuvre0843vT0ZL7J2jl1Hh+xMxaQfYgF9U2P3f7jVOgzetRoRvSmdPRglk
lsF11/tRRTHKKI36YoDhWc8HS6j7rsRDUpp2GLwx3w0U0v8azkyb4jWtgTM7jfmdGTCMluuOenUH
Jc1GVYLiPi3rnZBmZ1AcX6tC2h8Mo+UvuEK3gV3Puh6JwSXYLm28gjx0lNmaYMeUGLXDRVLcTnpc
rO+N3P3eisxWz8WHldWPxpJZiSkbTyX3mHsR5jl4m3QTqrqhuXFSY+PkQI600Nv2KAG9N/+NHEvY
HxqQxKoX7iesOUeVXhqVD+gYB3o3UImk8UcxVx/jRoIYMNMIlHOu5C19pPxzA5TnQlw1wbALuQlV
8eHk9XEsIp/1aIwlnQ6K3CfUXDrZen/Rb10JwE0hCinKdztg2BPKrwDIwO+PPdbStQ3yMW3vdtIO
EUUgpFfEJ9xjo+j0DimBunmY9XHngQkgWa35l9Bmjwsks5ZORWj/QbQCt0y1hYEXYAFY7gfKpg+3
JlqR75bHE5V9iU1V08W0bvlpOgXz4iG7DLBFLVfS3cTQIUV7uVtMxQ96Apd8eNNoBnzARoBPgvpT
MLdeqZY5Ib9My9TqIfe8pyqgK7eja47xicZC+1AFbabBVpq9YgIUluKQzr5ZH5Wll2z9PZp2vntl
PCzYmy0tle99CSGtCN5GQMYNtfR/QD62XvrOFzyMghpwxm2jqfLrgQ2ACsUaEvJjyrHqIGxAxXx6
gJz5boPBqVSSnRZ0lYYgu+g4pL88ToFMOyxCDy60EEvcRU0KHzbX7IsxdTvvAYGWd0ahsyY9LWQF
LGCazjJfjnILPd4eVR1psr3ZUdJBld0PlUmOfgfgpM3E7sF0h6EovoFWZ+QbS9MQyHRBwTuvu3f0
zxnCTs8ff9rU1z4ZmeMTQ0OkltLYa6y3v0LNIGlVwFg1BV7fteJDZy5vok54kN6Z//xQf2OtjmTc
p2WBr9c9Zo7g7RkKuKrKG0Ualihn+WaB/lFelCByk+2J1sM6fLrPsUaJPRfalRknrtv9lsBih/FS
pjC8yGCdLFyObbvP+uOJ2724csGGgFS9iLlsV9A9iBNoUD0Vtg3GvFxjeIWMbs7cWUUby/mH1iS6
jGQfxCpUQLTAYfIkUOBGPzUVBmeiMvoKC5u0RA6/Ki7yVnMZ/ZbcE++e5FKS/bbi9VJCYeWFbW8B
Gu9JjVsjbuQ2neqaf+bOlKVS30uClvlEUbncQMvANPaRP+6bixPRQV54WAUW0hGBsPzGmAt8ZLGP
df4U/a7qvWhFfPOUxUdovjDhhoV2Ev1rlQC74xrJpoQtUGn8p0qJWAaY6vCZ7rg/1T5JvQwWsJpV
xaUlsKEIUGAsjGkWsNoOxBkecYuP++s7t3cjsmu5plDwa36I6RX9RSVDlfYe43sXW2b+LODCq50I
D86YJ8oz1+yX1XYL5ZvCWjV5ObFv7Riwv8xi9sv1G6lIHUXVOQ1Q9w9UlIO8DAKBRbQCkfLRHaXj
yYJqzu3iHdk3R/zX2+9x75izTLurdHf8YMAVR/nDG/xd7yrDenLkmyIutX5UiXr9wYzbzkQGZWtC
Lkb/Nm71DrkqBDtVzCza876PmKfqUILIJ716+T6ZJkMutcP0kMT+eN7kKN9f/B0v+nBjduhEmV3M
AHuaXhZsupsAc8JG1chCJcRkAwSU/IcaATWtO546uwTIG/1lHDrwXxLJFN/rMTWpnTgjTfTJEemI
64clXK2pPZO4Cz4IoYaNYGyf6ijghNNDOxz5r1beXEokGL4D5hHjQ+a1ioEYC9KaZIAT85XmubyW
wXM2v4CZMen6gjXxZcGWfmCoxIUsKPCFEM5qCwkOYCEMxayHV5yCy/RUl6CB3YQQOsGRL3gK66mv
MkrwNPEersF9iugI0Sb/UzzxJ9LWOnIqF9EEvSlvMwh8oblysYot7RVGyLO2GjLVcg/eQh1+id3X
Y12/c/iKoHavT22ZZi8EXzHUJz0p8ex8XwwldTZ/o9bdcW5lyr+t1RBy06iH1r8dY/CLHFBXKDja
OrbQvma3303Z+EPt4X/I1nJ9JpYr/bSHl+UFouFpqOiw6cntqi7+Lct8sbE8ElfMxpG0oD2NWyu9
UtnAt1Ogm0jra3qq1cPzYWmkHfEwcSTn1g7ZzgoUD1fywQ9TgKIDjGHwwYBqwT5DlNRSxRjic8Rx
E7a8k51IpsXInkUOPmtubMAJFYugoRP28LrbSEuZau+zdFraK1xwYeeU6bsv6MBmgCAEMCHhqOeT
cz/zyfx2bwWBQHUMq78gHq5fkVGKXU3f8JRwi4bli2xUGyk84jns3scR1nNCUTbqbedOv4lFd+Q7
8lNsSibr9yZnP4zD+jvacjobaryYzDgahNS6r2vLpRYvJY0G8VfbIHX8C8cF5b4Q7wb0dZvCSB1d
rPVfFiQznJB2eL+UX1plB5YALYPyLIhy4rf2Uyx3AicY1OAh8iquoYh3B2b/kMhIRzTFIlmYYaAL
zI39gHISi2AIGTEmMePqp8LoRfANoMp6de+LSDI//SEhDJaPy1GtGZmycBZbDmYJojTxZZwrvcQu
/N+y8AmlKmrJ8VXoZi97fDd/iQcsjtdeLvFfOIVi/S5b5JxyX3A9D2Kmbci5i+F3jkJxE64YX+Jr
e6aUFA9N/xAj+AbszMYdjrIlYdk9AA4XD7mrMSQHHh4BkY08B8PvbFUDkaO67clBX5wGbelDE3tz
Ok52rbdH5U8ulvwj8HYEqBpMwT0GFGfcS1hT23j654Xj4LN/KLbmvdKwc8T7xiPjU2SoJ3ifZiRP
CK4x3g/OpgSBL16ltZJWaDJRD3XLeq69Hf61X59qPn8ESf/14rIBtJjjp3aokRfilgEGYU06W1Dk
pIAvTnVAHDPgb7gn3Q1HUL+7ZiWOZgKnt9bHlrAmCxs93Bqnhusnus0Ci04kpWABOJYu31F5KdCz
i7leAqe1ZdAa0vgvTk97zy+S2fbqF/oF1Ouf+J9iE3VIbe5AO2fTam7GUDGB7nICX2KRvjpLgzQS
qyxbOIVXdaVRRoFsGLfnwWnqpGsHYbqumigFb4ViMMt9sLDEOy1zyqiDp0MpzvS/KnGpJ2kvW2RL
O0B3G1GizIFs7T6lArOwIHSmIJthudSyC+juLgrl1FbyY3JChf2d143O9uHara+rML50+IdFjtwG
WU3EO1LYYkMzET2l6bBBo0SkNs3gl+3MeBZfI47k1JLu+s7FgGLb3HnY6FrHIXuSxs0YHZtNBM12
0IdyplOJZH41ieranKrSClqlyQ7oB+wUTWjuEeUOFfU8jxt19x0TNwRdHluJCgVHIME9R53SSaOp
tcWsZobB7U7fe8K5J8YJCENKTUf+vOcHWFDCWIe9h8XJEkYx0stuaj5fW1KNxFjfAieG9SKxk/wb
ymGCUe0SHoXLaXruayfIAVPy+PNRSPinaF4/hIl340SX8UIt6Fq4aWZSxBZBEEZmMpWlteNuSMU6
0CHnUwBGaDO+/6KQQQCP2VQPuEVmfCxGhbd12LIpzFmuOXubi5i+DQveLlVrL8raBf9G3O0b0SgM
MV87bSE3nZLh8b8d4BG4/zQEDgZkStq8sctNYmtVi7ZmMuVV37I2gBW0ASd3DYedNewun9gvpOt8
k9HAatUOqlBAhZRC7djhDTvq8lz14tvOXKb86GqbFGXYDFQWuqnYIHW3gy23P7kH9Rdcvoa+UacW
2djJyoIRr2LHTg7Jeo+AF1/5fFcbATQ/dsAnXX913xiH/vgG9k3GFMzcLzWNZu5xfMxL/E2ajgoM
gqcOgamJT3PLGyS8mxwBBl+zgghFoQaizIfcyYz5mZ0bhlxC8bi6cHFTr/MJ3zFN+p6UqLTE+BgT
AKTu/q9cIIP0SExgc8w9qcGBRnljIBsL4lV/eLJy1KeeDlEXRjRgxJDmcwnAG5PA3lxGkfiwFU5W
7tBQLOe71Te1hVUMffFFnlkiODY0JRJadj2NkDbPFDi1DBu2mtLCsxclpf0K0noh1YzR4gttr7kU
2Or0XmmJyDdpw7lwoy1c7sWfU6wr1gA+3SiqZg9SKaw6txRvj8nfFqFvAaEl/KcjQVtAbP6DcSt5
XBO8Fgp1Q9xrkSf03K2KYxKCo4KuNc0uh0grQ9Kfhh1tyYH8/WWM0wxm+r+4odOzH5c+EXbGbtjM
mfE16i/Dil137bJZuws+U96YLJyqQ2g24JHIDkwoUTcLr+dp/vEQ1uilctXKeYQ+MXaUC0JphdhA
MzE8tnXOcjmvEB3+14/aXPeIDYbXPNTd2Mq0RQVEF639RWb2UZi0nDCqJHD2pE25NgoZswMxeicT
LJ29DWozMeVoVBGHhQuPUsfLWItO4hg1cV5ZEjtfgIPjgxTyQQuB95H5nhiy3mRjcK+F5YK7Yr7y
jNBxK1EqHYQIwV8otDxlS+mEeiY33FX3ge4GEVUrhppLP7hnjE+t7E4KiZyoNkJMwvjpdzqe3sPU
OLznimH709/E4jMvjJtZ33LJz/dux73DLAJmlv3GERc3Ldm44XQc2xTJGE/8i92A0u0f1DL+bIHB
iRs0CWNkAVUw0lheVzk9SDujGGcf4H67EYMHxKy3/1iAoZ0G1CYYIE4h/rDOXooD8lD62nd3H8Fl
3NXbcSM/1Fjwl14p+XVSvPIBHwyOjtb6f2bpg0Voonwr9V7nz7cQGQjgcPRgXmBHsqHigBb+a4jG
tfHUuyOjZMlUIxAno6gsP7dAUfvJYusLWEAs+GL5hPsDYW2bKQ3Js4rYu6AehNIkZs0oZ0rP1Bxi
W0bxaKe3lDpIEicvwXtAoIVBnFPZA5ctju0kC0oODEbW09Nhv2E6GDMkHdMHgnFvSsd9+v/rtXDL
XGiC+hvgGbNGx0hvEdM93234O77Vvie60tQxkfcX0KOGqjE+1DbaQadN4a/vZvtS8hicRjQErLLo
BQymdnNLCnUiKutkI2Z7/sJzCnlgsIAiCQMuZ0uwH8hs2PFPgkCnFWxW0fQv0K4Dym1RJXfCtVPx
0PPZMYr6lyp/S+yThka7ifmAe25rAZdAE7d34jMB5C7YuDtM0P9NH9NhWByyCRFT8vPHHmt8Qp8S
U4f/X7w2cgkOs+k45yb1TLlFKYhNm653UcYs44sX6EbUiMCCVtE5HaH2n5nyF1dMa2nLHfDpoA6n
/a+ey+Ght+AunfyBfGmMyDSPEk9Vc2LxJMGoz7uEK1MeLuAPOY8VqsK1k+0iyvDeRl/vfCBJDpwv
eO+J8Q+YKaJCBiJWszmbjrhkX4sU5hUNojVbvw2P2UrItaGi06Le/AGHxoi8L6gvk/7ob2vuw0W+
g8rsbVRO+En4+ab84q23etiO3XLNZO1istrAcTfIqd+Tuos5mVwuWh7/DWWaL0obBBBQ7G4wLT44
9ZT8S9rkbjUa92tovY4aKOGg+ffhOoZ4YSP6y3yFn+AK6+8hNrIGmtu1RUckThEJZqgIh8WZxlB4
6nxOq7n8dHdDSTXg4U4oCFZsxS2u6Z5h16oxtpUNImP57K7m38ejrWDt4ESONb+XbG9T/FfCJ9VD
A9m2tBc41mV81CFRdLS3c0WKzlT37MBkDvTYUlpLTfVK/kfJdNXP8PmvhRERvd4Y9HCyUnKpzdEw
ra/oj2NrmEnB4ZKuwAz2n0ARh4QHnUS9IwfT6E+7yesppqZgy/PBjlAwFLEbE+z3vVGgGOGrppLA
Eu5CYtftEizNKYgSysUAXjwrA2JkfJ0fbco/sK7lZeiPID7KelgDhTXbiwgCLzUYDp/IkOcodc2L
v5684KGXpAqg8nCO5pkE6H/uddEA5N610leAkaCEb5k5NDWCWFQijNiW8DqT2AoZ/PYmYSr8eeZQ
3wBRpKAhTna87HfHDIAg2Pk972+/K569sy+9TeZJI0vr/tAxYgP/TH3K1g2Zcl62pjcZfMioOrTR
xJdaDhvtYuDfov73f4oj41MzGEp5G+I9bUE8phubR8ycxx0drEeCMkUkFMwBvoJs9WO0nbwnWGir
bt4z3CP/8i27wHxMSuRCCPGuFsW7MLhtq6eGfwBG5yuK2eNLIauU89z/6xRo1ADW9DFUiMSgMw0J
Rffv1x+KziAAu2hchhuebOaoMCR+U6JEP7xx8uT9GyYaSC2dLToegrJZjEYzO2rPT4xOsAsRaO7j
DlTwsYy/P0mH5AoRW95H9IGvbVq6cE29YIy5ax5GC9xLLAnrXx8SIpdOZVvj9E808DawXpuYI+Q6
5uXXn0Bnpe8QeyzJu0MwTM35D3pW0LpSA6bjRHwoPo7qgsJ1NF5LWtCyu+ynfSmau7wwhMFijeJI
1P9cygfqBjCOS38Bwm1cHBIz6DUXSjU03VihIekExpbqb0J7PD+00CkJU1s9vYJNcbPzl8DArz4p
BsUs/NfZBn/3ovcYElsmVB9TqSGg+hw6fsAFHanfAEVb2PU0RxUaESS0M5HUp9MUQ/ifE9mPsLqz
Kp5atXu+/wddt751KwoddBLzZaHI+WvvjDZCzr390tCezGZoGlTCk/QdfRy7K+gG3c6NyjHbMpzH
wG5aCiQcL3b7D+QO8zGnjgP5j+8gz7GSKZd+VzNXoWBOuHcvDCvf9YdanNRQCVuoA5PzQv+eZDVL
ptycPMsn6bSnaIErlYvRwYuAWLUiAlT8lKJUIBST/QKRBirP/tH0KfBzUP/9qUvgQM4IEd3f4G5C
GpSL076VQLhGgPqATpHs9HTlZ8UBWjyQSoVJJmDpu9dcxVfKhMQjhr10gCOdtr8u5qJgB2Akz002
qw31KypBGw66kCu4EJBhqlHd6NjMD2fB60tbXck6W24CDRFMgyi9zegR7zZwhKI9556yUUW/RXcy
OymGF5Uava2uZCA+ZBCt3Akp74/0qRlTDx9oD/i6Q7//IX9fXBsRec2dWmXJWDLEEpIWtV4MA6hm
8hDCg0s+7AoUAb19Cr4BCdPJHvYEODXFvN53TWzrP0a05kkpwPjnPugvVPcjD93aau3+I2Ofkz0F
GeLYadsQzQncBiVt5MG4gf8hctDYI7sefEzM8GOwxs/v71s5Ra+PI4rbnVvQmhCDpbwSEmV1ffHi
e/L8hCUuSvVz13Ije1OPujPCiQhVFQplLUx1zoH1/7em2gk5soiAuN1XIQ30VhBLaQZffoBzR9dE
waBiFSc7IitRKGbEAJy12p0Z1zaIjxW0toJc0cC5/ueeJKfZvs68GDybg4Sd5i6US1+CrRj/YHGC
ty6cXPpdF6fxzbT/0H8VH8iAhM/ZLUJRc20Kz+0Y/RborqqKL8x/9j0caJLuUUms6qlwlO1tlsRd
43Fqzcoo1dOiWygVUz4StBb0ndjtywHfDqs+gn1bJSk3iy5VwY7oVhkeRKKx9o95NsCfJyOH2R1h
Rr0hu/a9THwbOwa9biQrMFe4kwNdXXqtE+ul8qa2W8RIHmiyscBPgasBmdzzINs9fn8Ab+ghSY+b
hit19ThFapHz/EmsxNLjljal3oXsEv/IIXd5QvRDdwPB7MF+kgs7U/qcVvKboiM+N0qNy6ihwQDK
wh0iPxUTyw4WQYqe/BYCw4z/eJMkYtjxseec8JkqvM2YfSlG4RH05qOvgDCxJppMRAWxilCwyEea
xbMhXB8R6jXt2EW8bUp+MmGMWdV1yVdDdwEf3rTRzcsYMP+ZnESqC11j0G/DIIP8cDA5qoOvARiV
jNgHCm4EbIAHCJB6q2wZoS8/UXxgWXYVPmRR6fR28P8uicTCJMtgL+B1cMSNKwCHzgIakpL978HP
5cdeE3NeS8gpvHjWA29urUbBr1pfcqsglYcSgDhSWjghyywC4AfY0tUGHt3M+onX2lm78SWWsJ+m
uR4puk2+cU3x+iuhivKPP+xvtAPFOGKpuITI+hulEbLXexTlS4ovLhe0BQFtnYW+o/RMmKF7ThQW
CUSy78xm/sDO+JsqkJn5dHy0tJb5HFBTBrL63FMwh+wub6NfZzB3fbNY+byUIqLU96728d+7bXg7
G84kIqS0yuZczOrUYAyBFxOuJUwKf/55SBMWmhA+5ee/l78Fkl+F2xLZhw2xZ9yd5zeSTsQwqsNi
eKq7SMV5w/2t1Mq1zWNIE/nK8hQXsEUCl1E501/vsThecuX/40XOM94oDTcYBkp1kfkF2TLyKQRk
iDZZa+Pw3rrsNCufKj/RQhSxcndpnqBVmL6hSh7P+Q+nEHTEaYJtmnjAL1Vv6ZzPWIWXkikguP6t
GdfDg41FSPImdg+zzyGI6Y2vnfx/7n3kfQtWFbCRgY7D8h4ttn9josPvjsdijtNaRsZtcoA0XIzo
DbEoISVYnFcj32BK/62sS+O2Rw3svFa6j5XvaR0z022zD0Ia45ZeMnjL6fOcZDAnvSEsoiavxCO6
Wy14FkTepz0Y7w8aWt4qVoDvxG4qsNhm01l78yKpsM8+nI+Q2qekAdaHtsNvk4pX8PRK5Dk+FwAe
ElCsHkkJiZfS15W8IXKJt6Y3FlqAttJ89G+drZeunYvzRncvRCQdNX8Hh3mVVVcEyULr5ocuv1sv
aeI+HEnayUfgKTpQUVS4xDr6j2QeGXaFT79apwomWuRxZAzBJNsDB8VC5p6ighSrjPbTvOMmK68r
fwkQppygamXqNpm6tOIzOOOsoVXmqWgI4mJNmXjlhQKbIiT+HDXPrkpOFKa/Sl6unaSLEUph081Z
c9qVVxOAl1ogONC6+k2G6PdIz3GwhbvSkUzDOl4NpYARvW6/rtaj5CYOniujRLH+e9H3Jd7KX/dX
Q1dyMh00aUj4/deFvTuys7oS48vmFxu4l61CTTfo98ZiK1JIsHj4bxMDLvrEgUR4K5/TQWb3VmpH
Y809Jbj1cmhdooyUFnydrDEZmwVzyg7Me3+wlEZ+Y/9YjXwXeFL2wa7EORT5a8bKNU4NBQFWd8jR
bW/+033pUpLtSl/kq6DjqSw/fFSM0bhNx4p9KfOjAEYWuLDHh5G38dwwEe1eo3JuLXwRwGX4oty7
daYpklWmZpAaGrupQ+vA3ZrdhQvHQxBuN+aLw4HfTNY+cEILlAL3ElYyOe5LQbptWVNjFt+gL6lX
y8lzGG/KWJtWYfP/lZoCvjgTudLal9MVS/WiaI6wk1WGDLRItdeKaj5MQUuCpFv/kvHOjY7u+0X1
MRSwomxUWHh9ACI6nVD/aaG5rkIpyA5mAGDgWiHC8//RlK7h5yQMswuKFu6BkCq7JYHN9qBq3NCp
pacmu4o2TxU8daFGLW2tywgHWK6KWQiOSX116mEa5OCQ5eglpYk92lYZwjBvJ30J7P6aMSWF5aoO
XB2jXVZoyslqbHhKXxBhBrO/ER8gIa2nVPN/t0iEFF/IRSEVtBmiLPm0qj5c2QG59BQ6gt9Hywwm
X3XgtjKUImbwRHcgsjnFGTN2h06YmjVF1stUXZuboWKbZylRMpyEwxiyywBKSWU4LCmmIawcjB8T
uQ32whRXVsUGvstlJAREiwBKLlY3dScxzC0mj3OCneRmrj4LpXJvezGbNOLXudZa1ARQ87vCqKv5
l0t7QhawrMXLPejl3KBrdnFgbuFtFLuLJsqs0szvze9e5DS1znamizx/TfdiCdiw9GPisG2/lKta
t7fvuMe0TJEbD3ZDZx8Ry5w8tZhgBjou1oByh3DuQxhzO/oiaWONr1Kp1ebzWQFPtK2h5Vd1GJ2A
m3YCKjEsoNlefUPoC07mj0C4giQcRKv2DTXD887iP1TvR2bSQP5VNKe96KxKXlDpHJ2QElkwMebb
7esh2JijA5hGtWC/PI5szezAOKTJuQBBg2pVx7v1qSgN+RGkl//Odw59zdKy6LyAwRp2jeq6y/UZ
C0aVWjm/uGldCZG0oHK594Qn1GM6Y6loSclZmQTaVk4WVmCr3CrwDMELnEYfbs5jstJ6EbcxcePo
cQ0DqM1vJOdJQd4pSXwD/xq8vnohFY0nXwg/Nzb68++2d7HQdNgyntYxkEwNm4jtLv6NBQQsnX9W
mB1TJHZHESRq+ufTnKrH3YG2ZIb+GfnPBhPVAtfwRJTy2zeLlfZ4wUzB4k7/ir9Rk2h8m/kw5HAn
PEe95PhWJOU6kKOSfh8dznPQLqEKwyrLFqtZacPA5+HSmsHQoNBd/dJJ2W6m+zySwqo36xesNX5a
TDcggHZcCZ+5Q2PmMIaxjkleCIGT5HUOSPkV7U5hLfQ6W+VY6BvVizzcUZiW2jxUbvGyWydqJ+Yc
v1jHj2HDXsUD/PnuIiRtjXoN8hbQ6b6VgGa06U86lxRFS0xLaTZ+YlwRXwNwKk92ry70yBfR7f5k
yCRXqM5NA3f0R6NXEO917GNKYH8GZV8ZEvWAt5rKLcOAgBSl2MGwnpRORMWAlHRUzzJxsGnAmA+e
PVlpY+CfZorez5PAq8NmfUuJGUo0z9Rejz2MsO0++Ct8UAM4O0HJ4t//iHB/D9b8Tp3Bg5FkTPId
lSRRY/Iev8wl6BrxBJ/K5UzbmnpHfU9l2z5gHLIYP8AH1htqZTPUgWcc/kMemIC0lvz5JMNVzrXL
x/YBm/xLL3LvsaowvMlIRip7araP/IWIt5DPrYpHJf9gAz3A6iB0e3FDF/qOlXXi/UNz3VniaFdJ
lvYEn+CkORaMMOilNuD/OXb+3UxrgccyToxmadJIP99x7LTL+7AiLPt3LOPzMeLNJNN0EYsLMBdy
Ul6bqL4yxAHxCXyHgu4dZJRHY12TspteIF10jF/kx2Ydn1QctUl3d5rN8ctHWTvRl20AmIAvvsHl
uK+vzqa1AyvMJTJQumrbeh0LoS9bVik7b6IhVRrTAyiXZ3i6OivR+7TlUps7IPJUDQ/qG5Y8IJfP
5lOtWpINfglhz7QFz+LW4WuRh0fZrQtfzntCqeDyVjJFLspn3yZWQVjWGVZi5UK1egpAAi9r37ER
2Pu0bZTswHLW/Vq6aMb08BjV103fjATv/foOeLk8JdvLFkg0W9ib0hbXNE26P/y+uZ5Q0GVu61qO
K2GG+yTjMRtHjm1YAVj49gU3qM8rSwmST3j2z9ry3xI9gad548BeSXXV5kqfzunjbXkcX7sWPG0J
DCTYoSNk80IK3KfUgTAUhgP9FwgwzP2oH1hZPMEyYWeRDRDxoaApTxM3mNydJBuNY22dGrCX6Tp8
gkK4NCI3K8csU21e3FAJ5J+WjKMthTzRgcjxL1/q62VodkHM/IV6mzXXmoMA5K+B+Z6z5RY0Ojq9
xH3cRvRf4nemPFjiaHD5kB46oLBs516D0Fc9RFx5xtkSfe6ULZpI7Srg5RfmmkPz0wfXgOB+plES
7wLkQ4yoJQIrCdGp/SOgZDqItvieI8ExXECrV/xa6fxydFQTunvKzOiZ64KFnJMzNLzDSEH1+LRO
ETedBwDA/+FLUKFfEBWBJJ54x6GfIE1KXgdiYI5/cDdGXHhRpU5Tl35k+a4iRlx0ZXFbkTa5D1KK
5PoZMWdtt/KuxJ0vNJbE5WFatsQrQH//brnRZus3qOAAqb0uiK8JL2c1nd19TTpLmlZlVxI+jg6t
RJxO8u0u7Fcw5/NIjxznfQNEc23On9ZjDNPjytwZXUoigQ+guWlEkKa7TvrIQAWGSl5dRmM7jBjc
akPraY2K1AhE6Xm4rxKMJYFk2UJ8qU9jvBIwPAMAXQY5dGHPs6ZhMIYOANb38ofH+6Gig6jriiWP
Oeel2HdbGCQpRfFjONEF7DKz+B0+ld/SELe7nodHT9IOfcA/rOXjKSvPHTPLpwMSNnblDa3faoHS
7Ldj5sqHLD6ZqprkQSxfwZD9LpsGIUrGx+npyXMwnxr3ixqIQ0P+xTKpBTdSIIPayQXFAa+8fEtQ
nqZtkEbjbNCK6tMVGX6n9hElvAbxcL+xSh4upCzfz8LsF5uidIH1/YXa9+B6eDW4Q0YzRS/rmbxU
iVD56ZJIu+nS66vP5bWfSCFgvQSvFPYgX3ESn/prVeCRsTnAi110kw3EC6hoSjmt9FtwXkFxYOeu
UY4XIt3Domg3b6WGv7j+OvEBzhAXf7mj80/YG/tkeG/dnw94Z9nnsyDJL+1XRk/nYFdBP7EHdB0O
/ZxoCWn88ZMFvwtMnoOZYJqxje94v5fpKAGA9jkf8Kv9HvGuiZPTqE2L35o0STVivUPGRdjaZ6+p
bVBg5zB1cQhrS56Glu56ktfw+iXj97LfTWcdSHLI8depvGSfme96OMmhTauuEx5iOkvmt3UWWzV+
E9xINbG3dVsmDNupdaRelfzrwmThWNTnVAooB47tpd/Bx0MsCyrUf/RBs75sc3M9VsrXRk24qo+Y
UA+2N43jE/XRkr8sHyQKXgyI5RAXgdNT3ycND3XFzSzvs9bJpA5jLy7ZgdDxGtLluJseDlwoTzSF
Jgt97p91a4t7CMl7rs1Jtpx+Y6GZ2RFDNfodq8XBNgWyBRJFygEFs3HDP1Y33FUkZMkLX5gP66WC
2FLRTKCoHc6gb6FPenVzHOtfw+dUqXBFMcvHS0hEvg2HFj3iyIO5vlCxWmcvDl6H+jMeNnGA6ccY
5wtPcyenvrokvYXyIe1hJ2hbze7srLikobL+U+hKFhRZY1u4p2cphcsQaY76DNs1qvIwWo2ueHc8
B+dIYvQ+UyA9slpZE2RP2uLUdmC+WO28gRy8WD2Q7BaQ4A8rEmKTBfgqtbbv7JlZbhgPPsZ+gTsP
1I4S5TYcEGCVWTDp/h9ecPt5ETvxIye6i4THpn/bivDE05V9ALjz2ZQKAMn/hdekOffKAWLYWd9M
ZRfUdRXDLrWrRoB8KJm7LAV3j7t+1/xpNIIiZtG533n+qTWHVCTuLlfatvj1PQu8ic+c9LqTgcta
6uW3zy2NcQVXnIom2phw4wcP9JSb8e1jE1ePiNNsQmKviSARst8yAvKNNKik3E2/adl0d6ELo25i
eId9viJlg159XNdkxaQjD+8AcCSbeUJ8sOZ274B5oCjbEu9dUpVUiODbcX3jBW08QtNEFUjg9Ns2
JuUEKB2KlcZxWnF4EkrEeaz8QlQ3r3s0DyUhJ1KUmqIWBNkemJmll3o82R4185nfk5PfB/eUwUuX
T9hkdNqiESsGK9bB87xkAHbiiHU1/GDn2VpAN02tFI8M7LgCowfXpu3qnc1spGFwWewHpoC3HmuM
LSw8RH0uy5+88PU20OsH+0PeJ/PyDnZ3HMnZXpyeemol+Er2ftbKMQ5sLK+FKxZ4iDMdidZLI385
bmaQ9PFqNM7WM4YrVzgEf/KWH/hRzkUNKyMOjbBPXKljIVgAS0T7hi6BeP3ze6ISoM3nY/mc1cpS
U0wv1vrZoeVDyTzaCpwtWBFC8tix5DpJJ6UwryA1ZMVnv/MXfd/4gqp16kM6ua1bvYEImcwM81Td
zVcR+7n4Bb1twtaSBH0ff36c9slU2i/zn41DIh3C8/3CDwM1fsPuaHSOQu96qB1c1IBGbRh8Gchq
2k7BsaDydEl6QyPnazk4mpIv5f+sHpbt5R6x3Gis2JzscFLSinSqat4oi0GOKOSopt8NQ7T+sIxJ
67SoDdQcNuNAA93LyFsRR8LJL3OeXtTAL8RUfrgp2v/pUl3AS4JzyU/wy7ZSSY7drSeSSSPQkJUl
SA14is9IDZ1FAfZKHPeVajxTl2DMoG1S9j+nF8eIGApq2a9qca7sKP5tcYZ9eqdon7jNjQjhz1PY
RXURwuykuwc9qFXpsrQ3y0h6Gmc+Q5ngzEp1IzoxTgf+FQXBNxRHWY/tpS6a/0AAwO0UEGZGr/8T
OiWTQF6R8kiVk7dvtX4rduksQTMYlO95mpyR9g+8qIiJUMEPHABHSV1jDcFDIXo8FGwixf1+yXE0
QJu6ev/EHgiA6g+sKliZA0UxigdgSSRnx0xztscyWs+xMT5J4FMm67Q+OuEEUhozr/7/JipFMYUs
uoQg4oX809M6bF6uM/4AuGRRxCTdfOc0fkXYW3qLqZ24duUbyODSlogwyH1ml4IAZ9SJVzs42R9j
UEiflAxdyTAkXDMTLb7RxV8H6dcTzeaRXOhUpnZpeZkfmm8kQY4QoefjLhvwXS0k10FMelkYxiIY
VkZCf6K3u1MOlJq2c2WKMd1ogaqKKgTFRxklHFmiBclOvMse2XCpt6RQ1xMUdCpsjomLn0L0Y7Ta
83aR1L5X8Y/e6WPVSbUp1VhIFYIis0BwZmotbKpIwRybMwMEekjbv+QqxJFfzd5Bczmac9MfpgsQ
9omePawxZSpcBFwMF1J5NmLXV88560oFjD9KkJQdKNmAzfNM30QfGNCARH/Q2p+kVxArqdjtIfu8
tOHoRYatNHxSotKMtMEwIu9491bUtcparPbiGIcHS+eU1JBLNEt70pfMI+2w48uZwLi8QSsLhTZd
ziNfjnNKqHUqV+RDx/3SBte8iTa2Js+AkIF43O/Ra6OaEtqlre0mUfCIoBuMS4TmL9XQ3NQg/d9b
b7gjEV0khpxISbyxdh8e4CHrT2ViHpUG9DafnQhZvvaffstCIOqPxe/XBJFDpPBUJ+p7Jbj/MaGS
h3/zn+ia6f8ougnnzmmZ+gh2yNNNfJqzb9YXgFRuK0ekYwej/fAs7B8uU4gpscP/vNxixp9WXUeA
eeHDeMwr8wmZDeQJMO+PxJa08eIkStRCAUyRUntVmKvgqWZ4m/isnCfzhVvaJw2eqb4ASkA6iR3L
dbFbKEwn0kJ+8C/6zT7CrNuR4VUnDHqQVO1kDg2Z9iL/LD2kGYK0wg/iUmvqLlS0AAIAo406x0tl
bYRftU4q9n74Ln54RCwpHeUz9xzRT5KHO8c8p4apS6FknniNQeqig2sBDuZ+HuWcxlXqFzgV2nQi
gGb9nA9O1CdAogn4/mdSY1/MFVAjYbeFUXwhxJbH9ocmpQl+cuHs09hTN+TQJQynQAivVw0pzlfG
tT8Uj0K+f6D88BjI3P4Zh6MXob7OxmDiRHutB7+S04LfwWKjx4A5USNDac6mIdjO5NfmoxBsAU8E
2LuB1TC8g8bGaG6iJYQ6YyI9ho2xL+zmncIsrUQqrDZGRzByt4gFhMgeBoAuAuGM/6K3qyS3QUGI
nCA51JFFN71PI0urYmAwbQPH0ZO5PX2McxWIDP5SdWid32HR1tcPN7T4wqM2zb9n57sqnfbAaxMl
c76pVtNgzRytRPAM5/ueGU32mIuZOlqMQskDobhpJxoMOD430zwLpnOpRC7CtZWerPNmYd128/F1
RKe7NjyrSEMTM6VnDgi7ioSwPOkU3pBS8eFims9AzCV2xZbMjgSRzj1HAhC3lsxmjzLgmJJQq7Co
D4knj08vJjbDmyxbggqjdfB5isiNcb4TryjL57BP5MFiW+fL3yvbgcCiE0WTno+cE4TQPD5R+H14
a9t+zMvj0PtbQknDoxr0MeFWRLO50PvRiPiaDLm7AV+PmyvjLaGPuh9Me5BzBVTPIiJzmm1ocHCW
tVp9tu+DqEFx90j6AR5lMCc2oQNhOr17wAO1Pldbctk5vgimPvD7Z2Pjf+HA+DYXSUUnKns+K7UU
Uv4Kmy2XyVX6YPZl9BuMpgwWR00SGvpTSefzKgVnBN7J4JeVjomtfhmPL9a0LstNuZK+zpEdvEu1
Q+LKkIpg542JZ2eO8ZvSdPVSL4XCLapxIYjsH4xOl5PNEBXms1eNedcQKoDuJy4J5IZMHf+s23OP
mG1d83w0q0sJBMU3ue75upcdB5Yrcb3uU/fTcjCXjc3KqloMBUbtyAUgIKNvHhHhm8awUUFRiU/g
GiTPqa/8Sow5pvaTrq8xen+SVwO3Nusjz5Z+1QJTWO4I+HZGI8fcz1Kno523K7AJfvy+VelIHS7C
By5qHTs4GIX5SBV+Rpy9V2r0PgcJeHu0I131jFiAMcTo+N1MB86R/9xHpY+SQAwUazuwYoyz8l2D
G4KhuC8bev1cEiC2Pxcxqf2yGnmZPrkRrl5xb5qGdlV61fv/Ove0WJydbRT50sYpqPvio1z36zuq
/YBDPTW+gpxlPS7huODyEoF5SJ4lXYVrR3iCHyi6bUiLoxboZ0RanOINFGozFNk3ObmcvZeBcazk
7Sc4jJ+yaXhlwcnk/m0ttgWFqinmBt23g/d4zY+oyqCJPakuz5yvo/Y3NQbCKzXncWgmSVGBax7d
zyvJbLZZ+2ruyLjuwrEb+iCiHV18DwQFx3b+hzbZ5jJYoBhBmD5nctXKyWZmrBXLMvtfigcp33qI
rpR20rYK8hTQuiBO6FD0u3IslFkd1FHSEyFLiKiMJ2Uaa9xBMEXwa2Tbdx+cldBYWqqDE6lz9ro/
BcdRUE6d8P2dqon6d2In6JWzLM7xRYLzAnUoFo1/nj7S92qaAks1sz+0p0pRv3tTk0Ay/fvlxmKF
l3Zauc92bPUEvSSp3+INPG95Fr+XILXsYTUbpn7MNI91ceE+5ozaUuwgsvLrdxjCppULyuu3RUNl
b8aXtjGQSb9fSpN6wb+AuCaZ04Wwc+cWQjCNpKWpSazSZRKiZ7Ji4V9Tr8SswhE5I3hRmP5psi22
GO+bzATAbZ9CqMRTxHEWhzpCGYtF9OnFjPXPoQF/cbdaT8eVSkZAiT6dtfOXsJvPZ3RQuttZ8Tml
d/P0h8HzLcHaJbro34xLZx2NYpsqmd1Y6VfUrm0t028LTA93ZVIGqjETF4/tWS9PXrWaHjLL1Qkj
Hs5ONVVev5ByWJioeMwEp22J4PpvEK/vrfE0yv1pZ/rrTI5kWKH+l4VCP2f4e75Vg11LpZxWmnOq
3JzvhLyNvyo7n/d7KhPN0S4PdsBtzEhV40roeBd96D2xe9Nx5qfGzQVoOC97FPkSv6yYIFJPn+Os
IwY58CaZAsiuN1lT+kUbhgSY022LkUs37HxMRX8a1lRwFiF2+h9nHIj3ooyv1uLbdKwddLcDFZus
+nZHS7zL1YygxpVZMaDsf8Vk48kdeWw6dIXHrrJKCpX2f/WdOEqJUlJN7RcyqEd8e4jL+9gINyvR
ULr4JR05u2LLpJ4cAc4mikgYySBrsnnqHpwfXm+AejZMGuFzw782bb+qMCWbct6OtUA3YewU8Ius
JfDEXpznxaatiQZF6Q7CTveBhDFNqKfGVr2wzvb4B17yNpJI6G7mAjrD96BRcrwii+X2ZXOhqXqx
toe74Lgj8JPOCdMimsAahgGuwvrmED3lmsHBYebmOP+ZJ01DVhuKMpzruiQccPW2C3EzDoVAzBkX
j02JxjwKHmu3xKx31AJRGSFte/mXg0mPMRui7xLuiX+XvQmJaVImMOfh1w935LxXZICL3CG+rWe2
yGBydcEwpWM9UTb2P6DSFKKYo9cAyEACKRhZtQ86RNf9l+vBroST0SGfjWHaVwR/53Ie0lzz3s/j
c8r1NLL7oCRVW0MDdwHyNhmVz+3STH5zxMhnD1D2cNs/kgdfYgGy2haxj7qP1ohWr7vf++sMhTWT
hMUoH3UEOqOsj2PuhUTERhcyRJ3YwO+hQjIO81JZS2dx0ktaECsidPbzJIrAb9Ck4nRNnV53p9V7
w0SI4zucdB7i90jSVZoLwZ2wcVFRIxP1MBUcmcJmwee0cN9mGSpyGlfQdAWIdGzcYtvDNLMI/BQ7
LngTHyn/OFayawPuRaC79vSqhvDsXD5hyH3NRPTU5fIFivpPhFh26GpUCRKkhMnBujCv1l26gVD5
wHkg3wxCTmn+r9xMulgAKXY6tpNrvY+xhWcY6NxI6NpvjVeAX2vCrgXFiJzQueCsckyDZ66Fyx6B
t5yTVJ1CjJCNMTq+lbcA+KhQP2OFI+kUn8kEWQK4T6rXSbpuKUI10r88emSxzpT3ybh8qb0EW+jI
Ubuu/kyx47KufdSk8Iyr28Z7xClV/ecmZb4PLk2IjwnrAEyMuGeU+D6oHDLq6AKqaAqxRGiAJRm/
KucylbKBHAfRhmNFyzNSQ8IcMlmnqtOjNU3EfkVP9t9K92W+61SCQqS57PibQIbVrGVN+pV6r/4J
HO/vT8PXcsx3MmF4ppXNcnKK+uu1/Y96ERyBuTrTmDye8x2R27Il8ddE+cYnsE5dzmhJCzgQziLw
aXFTCmO4zt8NoNjSzWrjTD0eFHkaPKe8LwGC+t52J3BX7Tep6wOhx8XQgBQDsP0GCYy0i1oOlE9v
0tvBWuB/UeAtGEerPfTtymEG/TngLr3AxhyoLA7TwgVsLnOZfbxp3JH28IreFgzODcGWteNDKT2N
F7AGuFr8VmC5NbrviPbP1RS42lYzCahTI5K1Z2/qawO40p7SDeOzxbT0GJRdWD5RAYvcxhL2mRjg
oJW2flz/4b9KH80fK0EJ+UYZrAFiCjtlOfYtG5+0JO0pqMRCGtJ8RL3yaxJ48HonFqnKYoSige36
quJRo2LGT04HH7BhzJPU6pLeP0v8QC6vDuLH5gHVCx07paCA+LeXbV8tcxYyJGItP43t8uvU9JTT
XXn9WMGs++5nmJee6ouBE1cFxZlIMrWZf1G3cE9T2Be7/ZFwp1vdQqMLXAk9tYPw4hQTMqUTgAKy
mAxscjt5oodKhwjcvIt2qrM9oNdcUr6fUHWj3i7oN3DAB5toissQEvI9inPPsSwjuBiT9N+gSH6m
5K1qbka5ivwfUSTO05d+fXMY42SXJGFHUhEh2IhePfx8sQ/0GN5tgFxbcxzkCt9TycrbSk4bPEyv
4p0hM3ZfTUjB2wdtxi+WbJSF4szPLKBfw1hcJLuFdzO12SwEX0+m+szbC5HxUuYTRfEUMrRiUTMC
EYZrz+FrABl9rXZs+aZdnqIUkIBKodbr3s2+oBojqAHUAjS/tvAStR5jV2J+YlDt7lZAMsE+cReV
EnrXK2S77AWvpv/iapDcLoj6c0XKxBM3dwtrhCo3yBZ0+DLJPrIChGGdB096IQ3UziDpmEZgVib+
5/jhpybZi3hww1fgwyR1n1vxn01WdgdK7kNueD9kpZkBnRLXI7pZ9XaqWgwPYPgksATsYqeBr8zi
z3BiKKZwh7cT9ShNzPnwSrI3zMJNC+FkldOjEnmqamX2rpruDRvzBKC3VrCbLwYIKftED19HqTnv
Gx6KDt088lqOe1V05/hzGsR/1QspgjdTfXHmCQtGsHygeyomBM9hjz81vkMUbe9Gv6UCf2cQYuxD
O4x80NBkrf/mWuaspEglNBXAjQzwG7+eHWIPMzmvRrPD9GSeqnsjRTv1ij7rCum9/D1nDontiUtg
Ec0yiA70yzcrFmn6uNbJLLqwajhwPMNZZh+Ihm6goNCwOVKkjN4qE9luNu3+jODL88YusXgJ6gIX
MJS87Th3rjeKtwpiFd44jR3SKrtJJw3D5L7/tmobk3RUKbAwpuWkDwpPjnt/lXDZ0U1Ker7znMip
vKDfBxQn1wkERefegVASNQebhraZwvJEIXPkyVGu01/vMtTBFGylhN8S0d4VacXYHXg8aFG84oh4
bjr0msT495AutuZf9hlrJ/OJB8QLgXztVHGLGG9Qvj9199HxjxCng5jntDcuGwX+1ZU6PLjQvXGY
oVipJpM6jH+IWqkyRKp3G8jtoUFZ5zCFSaVDq866XoTCIVi4Zp0/8zSYa0N1o71mvISuiIGAHb/X
C58DEXv7dlPKrm/QuXhlOZKhNg5NNy29k28Kc8CxuKR6Rsp8cthqdAhZMYZ8c9N4GPejVnIrpD6T
SOjiPJmW/Otl6wbTiPTppKdBTWlvWzdwRKg0z0lnIKs9h5XLINavLDctChSQo7EUlARNcYgU88zM
xr0WPagZqKkyJu0IEm8/C41Q/6lPQyXID5Z58Kfhfe2Ryw6+HHOZEJY8BzaL75avkH9xPqBxsn4W
dvnK51nWDqj6jlYep6M07UpTxHeIiRJRo4bsDlctoYlfyO0jEnqFE2YbVRPtFvcK2foRDyI9BoD9
H4J5vblGZDos5pSt8LdND5zCawJJtTOokjv40ZHc0MuLO1h2NAB586Cb8RaLkePvQWJnoWsR9eEn
mVKGeMtIqQZ9f32RDOM+qR37dxob6klgapHt3CnXhu4zQZEhSgfhplQMfuzLcFDCR7d+8ozFnxtW
j05LXgDXg9C7j7ZSnqCYBavByoK4vhepoZZlc4r+lJ+d0miKEenVQKw7dpQA6F0ab/ENgZjNqF1Y
TD0t1P+Pym0PCjvyYOpNTFJvKKF/+LH0w+2ocz8/F9Av3WNRjqutoXxDlwkL0po3tD5cxoQHRS7k
NY5BS6lqqF/E2Bxs9/jjOOPfUyPN+j5ahbW423Tsy2RsRVv5rYWTacgmKuMnAHTSuXfehGgmH5WU
D6NYVh6ncfWt7Rxwx/A95CG6p3U6K9lhv6nvsxJSeR3ay6XosO4T4RPcneNozkctzw96j+yzr96v
lO0bg48lZO1K5Tr741I+dWyFhENr/dieIg5xWPIQjgxqTuXURaB7JFK187yipmIyIki9f/Kk5xJC
ujKcnxrg1SGh5WROzMxcujRXkCeV8blBTuXreiqH63GvpdO6bbF9ovcSyFiLe7CEE2vPVebNNNAK
pxEjv1KGdGQIeYJ7xrU9+1jWgdpksjfwscGo7kinpRBHY38RlpnuS8WaeGvaGJ8oDpPYPltBrBef
hIY4CEkR50B+EAUks6Y9gk6DJw9m8YdpeJEhlLh1HuvMmuJ2z+LI0oV/II1SlVKISZqrPDNTd5fp
fsM7FGKZfxxvPpvOA/umyo3NeKO5HyOCYng2XHJRyQwZM2PPKuhgmAYQH9GppGOEwAS+rfsfESQl
HqnWIbh/EZPl6IGtBG7RQ3lJD1kCOfRMPSdgpX4rrd1Wm67VYBudV9IwVWvmqtdZvB8vVHigpYDg
bvw0RvknrE2WxE79NNXsosDL8Qz1BCmqLRL9Y3nS05VAJuQb4iDZlPpglq4bIgRfbqTRZk3vKz8D
7sHRn//SFGDIi7bEdFkMfO9iABXKgo4TPPU1tPDbC3ARPttPSG9qXT0Ac1GtpfD6x7rYSN8tROYf
qMb2Fq6+tTErujjazwrV0zcz2Us3sYKDwndXKJFRGijYUgLFFRXWd1qLliR8HUAwi7XINuvgg7no
Egh0ytZkHnPQZklTDMWCRRtAP+qoJAXLQqajdSd0Xmcoyk2kV5dWzri7Lohe4FL0+Bzv9YoChHQD
HzkpROKMA1HRnH8LTVzjmFLqnZVdW8crAURsy8+/+iqzs2CZyhPfaNVP16Sz51cyLD1W+gqgfgXl
UWESTufPRpbBXosoETTKnIzvUJQLHP/5dIvYMUHBO92Am+0HXIuyQc8ScAZAg9ccnLgi6zNEkby/
Kgyjz9EjlBAcLumrjxiGjGGSzU56pn3IdA3tAuDykjTPHdDeCQIwJgvFW962G3UFyHG6ob0Hxlel
VhKfCdOGAbLP98RfoFTu4EoqxZqg7Nz8sewedZBydSsJSgbVJrxO8RnnvniCAt+8pboQAwTWAbhi
mo54soZDR1OZ89lzLZW/8D0ntlxi2tVDkovFMxHnbqilsLBjnk679daTJEQuuSUeyqyltC7PUkde
bKHuv41fcfMHMUS762pPjMZ3X4B64CCykQbHpj+S5DzPmhiOO+KxrHAaHCvk3OxQj2QBV9hcuNN5
Hp7s76Zukp4FAE6a4//EEVj18yJWE8jQ1pFeGsETljjRDduAhv7Zkk3vqMvO9GOLdZ0dvmwvd0Et
MQGyYQh8i3yYvHCF00adMuYhp2HDuGuq/ZTva1TMPDMvmweferLPY2aqrIPXp98nO2hX3940Hczl
8xvzeow6b5kXXi9MmczBAr+tuy8Pz7OGM4xBV5AjVgGELzCeUgsEv889S/cncdWJlHJZ/LYPqas4
YvPol/B0m3S0GtbjcFZ7ytuMCUz8lLz8kojqNgqj7CiF0AHiXkR7ZOl6Xm6/IP+0h+gyi+t97bIn
GgIbEEzkBCbmqKxC/uWmM9sM8DrqPqoMqKn/xbNvunBwqV3G+zGHyXGsTbISV9+r7vaWE7PDB13c
A/aRiVRsc3viXd1tbrNp7FEyRW0/YjXMidKejFXCiUhagKQlE0/rxWqTRvhtwz6VJ590G0MydmNc
/jq2x//mxaMdhYLBYu2gSSbyMggfQMNO7zAfeMfwDyGs85CT1E60CFusMHwwsd9CJRiY8xcsEYeH
mW1UWirao3OKjyX1xTKPR9whMw/UlF+wh5aegjAGjHLPnfFyH0q2Kml8xTe7jAWGpOhXJ0EHBdR7
YW95I04jMUI9DoNus4lrYswhvk4DuTVA0okrDzP0odDMi6Ezrgcni8dSXVdG8GJOs+thEk6/U0SE
rwkfywbHxYcUfbs4ypuyybN0/A1/wGgephQdCoN84hdufUVbUxLHhaHIqNWxQrjT2x5iu+mcpBET
dIc8Xr0xJvsCKIUu46ywDrfjrWFHs2Y07o8f4DbWvkXn27OhVGhP7e0zuq+OCpdI34S0NztLHPBp
2l3KWvmSKN7/fUpipnLIvOlK5VJXcm072qwCxTkrtCJ5vAmjNyLiSdvB6PLzdQsWty1+XEOA0iT2
lMh6f+nKzhAe/1g8WSAkgr8H8mRDIbHUauaniXXPEcfrIxzJhyQGoArTp8B8REv7uvlmm7bq3ahs
xykbiWEjV1ZBiQX5HQ7PG4dJzZ6au0sCY7k+TMdXuhw7CL2jrzY/RtMUaZBqICQqE31q3YvHd8Fp
WID7/jBHtT2D9bSuaJQARIziy0EqxijE4LF0YmVAHX/tDenFOe12zm0PzrOvUP1KY/t9dJs1TvXn
j8vE4m0Zl0hJ9pElGkn2P1MkXyynOT9dZRGC0LZPEgrUGv1yY/9tyFpbm628C+XqcAswKlmPThAS
xzSHLXokVH4ob+gDgmdSM4RiHVDhPO2H2gNXfxhECyWfvE3JP6QgNENKft15KbXNp2tZs2PoWaJ9
X4y65c83rNVU8U/vZJK2FjJXilLXcBKqVOl3CleRkgD3Nh4iQHJPosakpXmGm2XNGHTTHZHseKi7
m5AfopOrcWe/ntc5/ZaV9ZOXmiswjAiQohTfjcaUN5MQteVXGYWDZEGUtueZ99uDHVYYfDaBOZkt
MVayzBB9iOaJbIKWoj5lKKAV0AvUaXL4sysPolvH02pxbztQ0rtZbv4aAd+vrUruLASD1hGhbm27
HJgheBS0L73kQircD9aR2WP3VFuoVMN8l8bof2+YUPYIrp09Q398+FfUMnM4N+LtYeeOTty7vxl2
jN4t444hOfKbCxTX8ClteOWDKlZRjG0smZySrvG/irPR5el2QIDTWEZgAoe54DoJupoEpG0xM0WH
16VPA2KwZvsoXTTHvHFdS4KkLsAMzmyXQwoauAIxWgTPKRq6AvJtWlTRLYt7EYOyzQQ5e7WpQ244
9UchZdocrkYDVjuPbqA8S9N7oHWQAxtjoiX85Kcawz4FaZW1RhJu6d6YVL6DA7KZ3S7cpaLRO/KT
abGI3rFPKskokklPfHMiUYxr9OLKMf58rmaM+XqrE45qG/VUHvOnn48KGWl5bSPEFBT5XFtR0K5u
bxaKXJE4kRMdgxfrFKToccxYK53dwXGX+celbwjAbXfmbeSlJRyJenITOFk8c29UvDxRWtJvDs4i
1jGut2rPg05ZAre2afIJ/gZ3x7UA+MgQ0S3jxIhL+qpvAY9y0fIn4tTV/EEUduNaYGl9ZTODLJ3G
jG7UYp7kQLqA/81mLmKyETVU4907brzfeLyRkcFzX8BxE7qraq/7BKxdUJmZyPVzSZIu/zicityg
3xTrcCZ1qVbMo8GimC6CJ07PpIjgbQpCOXaM0crGurEpEVTFUtfZGkcqa3zoi3KSjx9/SdzOtLri
33TmamW0+R+NN/pZMO+DxPN6njc3launsHHrO+g+9HAHqWT6iWH8IredD6Fhi44tbVZjWCdD48uk
8JNYUOlgS1Wkuy+tqWfsoQkkQureY6ivzEY4VJ4rqQajuXFpWcHP0KVMlX4HM2Zi4dOeIaY12tjC
An6JsuZjOJNyx5ijxivdmuGaEHEsiVYiFZf6TzQc3qbdjX7JY9xEek64TO1zv4KUuY+qxSt0rWkd
eG8cGDRftrxR4cyKQQUDWoD35B3SqExK8zELXZ6QUjTx2iP4N0mK0ypzZRqvEDJou4bctxq2Y8Vf
TMTksc9LM7i3ZxS966AhaPqULNR+S+k9WyiJ0YUTE3IjSWq4DYrU8ryIajJIZQDUw2CpfZratmuH
iwF4+dyy72ynvez56n0WYDksE+9bhE/AxrZUeCeCwehd8c+6GEA43Un+/vHitYVrEY9c9etSaeJJ
Og6XULhzL5XR8llB/cbHtuIO7o5HyWdnYPRcWL/nqV/mGiDfg5Kccw8ZwOGX8x4hKjCw2c9Jel/a
XbYukQZpfZXQyCVnKjVRDX93rQV1emRII8iygUPX932PLLNVCATjl5PVCQ8dKD01AM8yDFZQoWj1
DpURpH55IW9XhQTNgQrn1Ai9dTLiFMumczDyGq1iHGUL4ItHnYM4LbMFifvk22UMPuAZVoHtO/Xf
D+lOHM+/4bHyEmKewLpQF2S6Qo/7q7gyvafMr8xZ4EgdTyxoDazVQXkWBHYhDCItVfBtItCfZjMj
2y5cvngwEKcA2HBMx/5GK4WNDUgFG8kJGMqLOnhSCTtqUrfUkXWD47xLeQupxoqGhc38UJxGjelW
Nhqsps0Jp7tyHYF3dHlpd/bUT2YaQ4mOYnxRPAAqjfI8zdQfJiw15JE42L1J7LpYCW8z+N4yjwEV
QcOlaC4SZVB3m11brQqYxh3sJKFPBKP1ZqGRbLaBRYPFD8xFvHwicQva4RebHYJfYuMwTZI0rnGZ
8cdO6Y836IEaYn5J02OrG075M3LL6h1hjGmHOQ5KFXqKF5k+c8M5jd71w5ccBTg2TS/C0xOd2/vb
otgkPAtcaIJT8uRcD5vw4Q5wgl93Xk5g3gubD1DoGXgcifXmpPOY2DISAe7ud4enrTZnTvMv3Tun
lv2iEeAXsOFzPoCERDrt2rL6PaWAnB288iH5PQ2BXviXufYwTg7R3TDUsxFSU/B4e52hIW7pkpBL
VW8ZwySVu4jYO4UcJDMPHdI1qDumF5L5SBSLmWStpwKHK5IkfGru8oHl5Lw1Anz5pQ22hMbQYPkx
WGqLoXkdzyfc/NEP3KTE1k8M7xtjRntB8QoZvapv0B5fBENb3DDsUtK57qIPRfZgwTQip9ZzXnQR
0sherIeVkcvTUD+fPvcc1XCTb6vqqVtlFJvkl1NIH95AQhoARIZ86kfLm9Kdf6skvGkbTzM5Kaee
BUdgGQC//8cUC2wK1xD0K+H74jYy95hyjsQB4QiZUSEdEAaUiWCGkjobCnjyQpxTKndJplxQoiyc
9pgCR7yaFXwB5evKVDxMUa7/B/TnphueXXIauszwIVhC59+QG9ISe2pHN+6c8fSsAPv81l9Q4zxc
U37SMdFDQUdjMcfR7+OlVEtibnOuoAlwSb1FSNNGTjKaU1yda113rvVQglAGUnwQvAmJWjvcAH9b
OeMk7wU6+ljbgl451v0WDUJNpl4kpGvhYA/SJ3zi5tpANgKE7PL1PIvCBu+IJlqkhRs/9t2j/AY2
q8671/MT3qJZfhAOTlUCm+aVMebxXvA4tJVz4V9Pp6n7NAUqr4Q/AmAfd+iqe6oLmjXQn/Ww7I17
34gSN1GoO0MergWI0MA7oD/KUPyQeSNzYGl/vzTCapqS8Uu68RnFZ3WL3G5ItcUWGLsHfAdbBxgd
/yHqTTwP6iyPEbM69oRUQPoEgfjcY6eg5Tcu/H2/QedpDPVIGvW1+rtDM8/wOtFds1icCM3letzW
rM46W8zWR+23+rBuYJm3bUXk1Hz9Qh+cEnk7H5u0mG+NeuynQYOwZrCQfUMGfP5eaf1cV5YSxIaT
hwMSzBw9eBvpwU0K7ie302hIllx3V1ztUPUwFn+A/+ZXDfJ8ocKeV63+Z9LuafrOybMJzy+Kd7Cb
jfly4jvVlh1cDAiuzdd1iZdD7/FN0S3m039nKi+L7J5F1Z6ulrKH6YDAI6SCQgX/m0okluvbBCrB
uSbe5y6O46Nmj7Jop5SnCPfIpquLiLx0MmWLjQc7qFaM9Aq25GvaCgfNkMxcHZa6ZbgZjuvPC2jW
qYadK0yfo94u8IjH3d1vJwLrbrgeW92bJH91/0n/1ZLg8awJdgbo19MbNDOOVRVsF2NOh8sYXIiM
asnwl4MsN1Ss1g9uHQ3DaujEugCyZjYlsbgHisZqe6WoOHdY3E2r2tfrnvGiQbpDdvMWF+xDVJFm
dApZLJEbWqVI3ABZyEOoytdWDdP303pvfLTEC1wWvCq/JUS7h0WMSJBTfi9CmZI+DkAaoJFCvad+
KOXns0VNaY8gTTQ5MkKdNJcIKX5nZsKI+1ar0mPgxGmaOR2qzu5HX9oL5YomUb0+JVW8MKtx913E
TZTFJQtXaPCDQvbEICF0hKGe6RtxpNjy2BlQPD0nzG5AU28vUf7e9T7bLvAkBZFX4ykQHeQbjT6M
VCvqJD/fCWMuiDZi8mO+L7S17MThw1/+lG4Orp3uZKao5uW0lEBdNZnt1U35I8rr6dshEJekYIYD
eiZYhzW0Iv7oTElDiVE9NG3bS72Ipuyf9YVNosg3w2Wybw7EshEGsYbA20r2s/qwrQChOE23G5ru
+0wZxWLrcS5IrXLPcyF97gnGIqLARjNkFEUpXhll6XyQ4plX6OlTosq2gXhjeFZ7ZAdQRlIlvLOP
PfzrU2mgkkMpSNkUyVtR3kMdD9XqZXwC3lezc1QP1Dm6Rte8eTjOnzHM3FGE0nwL2sGmjveDaXpc
zhdqeomTA50zEHOpK1oCgESipT3hCJLFpaJIt67nVR2Q67s9B7ELaGZeNHxnXSCZuBBmglJmRJw/
iOSGeN7MITM05Z7LA04BJGQWFp0uLxsWDXkrSJSzYHqLGGb3U3HUUL++p8BqCvufSD8Z/D/0BJwO
K53fR9vY2Ukvpym4Z9C8SUt0eQDZjFpsgcVmNFjAbK6mtFPwxchA8HImRBExbhrXxr4lpCH+iloG
FE0VsagMFvdaLWAEwAsAhI8/22wzMslke3bv8Bo3frW6knz1C1udGtNSF5Q3o5PPrBW53/UemHcH
o1RXNnfU+nyRdWiV/zXWp2exmhI1xM2VZ6LHlUQ6iCqD0P1Z5rZ8l/TroQmYi52YxQkYGvz8HI0U
JKkxwv6QvI8YEdztj0WIfk+XvuwHw6tGtfNCTb7z38JYUMf8R9LMH+fyp2C9RRv9DNhRVpxv3pzL
V/5zrIFdzheA+3SZUdcKjPY7yk6nmG7vJexmF3t48tpGtaa50RL7WZerfE6fZPBrsdjDL06LPGE1
7ApnIqH/fwhjNXxTKLGOxQp8oLVN/i0Vz0q3dgQs/+ldrQn4DX5X4irbLvPSbMOSeZ3i2CWn0Niw
5kiAQaX75xNISsLPHRMjWGhGGdr8lxyrbD9btpEjXqofNh64HE7AmEVXfhII7TEHT9HrI4QqZQff
qRT46c0UuyAfS4vATINpagWFolaoFDvUWBv79q+R8UZum3rFuxGC238h2ny036oM/51Uy/xjz5Oc
PojGUgpv13fFR+QALioMQmtg2igchBy7m6zAp3WWwHtje1ECZnmckLfE4cNG309nds7Os9XRSDrC
0tYZRMvzKgdJM+CYitxjXoGvpOJ9GjFtyX6CG2YbMCkEL1JVsfmmUTihW00qUyaKh0pHRKlPhdZ8
YFvYCHCma88GRuWwn9eKL51IHHnXSze2YlOMuBLYTHyuDsoZ7vbWbwatTGXAbF6MNIoxo0NA7i9b
FdWO/8+BUm0mT8mq6X/HLK+a/1tTuLW9Axv2LW0Dkd5q1BqtJAPBqB8/kPpTNnDqEGaCl3vK98dQ
IwCmtZje3OeZf8hTy63YanWUJESho3K8wAZrxStThB6cycxy1luRFe9r0veAZpdeRRusIRl+7fks
GDniwh78VAtdNQhbGeTzGABllmahMW+cIjcW3CAtcuwAaxEIuAOnWZjwOsLUcMfxEYIO7qLQ03JU
7zgaN9KOG1q7j4qrh1MsfxY7rKK42m82Z9JvT3Hq9we7KzPHEARCe96FJ4Ytq+CjAZvQGCX1U/9Q
AbfadGw9pUidCZ8sj9taWrScAJOfSNlXvn4zPN9e7ntI2Pe0lOwdibZgoqJcrUi0BNIauvQjetTM
L5+rXm0Xp5gmHUxk27VqJ+bcdQxaw1W/XzhjfntnOGhSEAiXAN5opgJOP4VK2CobSkdss3ZL6sxe
8JjMiDZ1ZHnYVE5zZ+1fSYJoNkxIXI9kOlIOb4IBsns1rIKW+w2poLeBUSa9wyZM2Ps2F8heXY4i
vRiFccBdcqnjICqLn1/PbWzLjZMKAm9b5G4TebfMqErAfH8X5a8Ybb90z+/6lRvAYzelDW9pcqZb
pOHBr+uKvcES70+x4QJiq7qt6neGStyeRn5h6yX2HHb0ihbBfjeOgI0zwZ/0g4Ue0hWVmsjHupZf
EEGu9u7H8PXCrnDgxhyAzjp9+a/BiyM0T3TFIvt2TrOHcYDDX6UP0oRuub7FCiwsESCebTj2M7t7
sn0SuJcfSO1WeeotgJEwpSamAdPLBuEb21A6nHdVUOE/0dWYoJPiGTPp9tx6hdYz4DWkHFPwsxrc
AcvpNp3zaJwvqIEuXXPXVRXWdJT5tOCDBrHHa0jf7WPf2RgnNmaRGkVvNeFxfuQJjG8iQMxBNjbV
EtMRYJDcfoeH/obJUjrLXOGoIjcDjvnK2viaBc6fRfAUVbKlkgNmy9ytb17sBhnEmbiEfKqQoY3q
KJ9+K1j3Uhbb+vWr7g56V3TeO1vET2HKE8JSZw/aU/TBAV4x74vDLy5H1CXWh5Enh3OZIEHVI0ZD
uVwEFYWfKec4HutBoHUzd2fMQBqxHcnKFBWR/jMX/36xlAfdRrNr9A5SoiePai8//4IWZjTgVPUG
hftVBrIpNe9UPrq49wjHXjbJOlVopDph478M8n/YQEXsYbuszrs2kTMgLI5nOZjF/rkM2vnvYxRV
U9DualOx3vDivWTbCi6POGtY1a/TjWYSmDV0fOq2/wseRxv3JXTdUDuk45vbfxwaOKcWW5et03s6
u6cbV8S0tRQyggJ5NdQ0w96l5QKNLIj6+FNnuyIBebL+ejDU2Zgi0WAQAYg/dagjEq7b+d3Zwo4l
h8k72tyvIU9Pkze0DpRqvAHLzHt4CO5vj3ec5UDwSxq0e8hq6q/iMSSSTZIxbFkRvYzUVu0yOaIH
WLgxaZh9ULrAF2HPj/XojG6AYmttxz2wvEylU3pd/4tDiKAqeD6wxg0AEC4O2aPqSKI9Q56o8oFT
DklrXhar/UBzh1z7RdwAqM3NrG/9HcXsA1IfngSYAiN4BSDxRQDwj/MoEBFcIzO7bpQA1oeuKnKr
zDFbAaGslFMuIhnekNaWjM+tkAOK06JzMtSsmUHZAaGc4/NxcuD9nJXg/roGGLS1CrlDhcvhCEpu
Lq29XbT2zIGNKzGBuhPkN3hjUU6KHRSg+brqdIWvKimiZTvR+73oN/ise7+vMafdXozbKZ/k0xjz
iM3Ozk+n7xWjnJAW3E3FEm9dImgcsES7ymNYYJAoh6vHzM79KD/mjMtFp/F/o7Cx9G954U6lzXwx
dFCYUrMcUWGDzVW5AN89uYZxTT1Ly3wwml9ux887wo4X5i5jEgRHaurBMiOUcS/Ej8aDeCdcEA8K
2za0NneZ8RUPK4sFEKr1Q9zEiJXfHVb70mZq86mXOT5NMUfcxRJQ1HcHiGv2gPGq+12KjyU0HNej
Ofo9JcwIrrH2WvHKY9s6K6hhsA85m9LZw+503zDPfNH515SySiDV0GzWqaB/1+QXTJO/wEywi+R4
Lkak6HmwLTz4lUuajLVS9SaLbHvD8F2rRnpu1qSMoascrJKEyKQ66I4zJstehW/v07uiVFTLJSD8
nxLACALU+xXEM7IMRZX3P69GUsdLTNThoHfNnSmxp7N99zYXZQPD+8NW2Pqx6rOIGLBMXtQ5FFEl
7TgOGbS95286FDop6Ot41vPEn6IQfmq7wAM3u7hZtyJzEpgMkjJcFLSItfKCWcLleiBGy7qiTjfb
pSiZ4R5K3JZFCURcsZyxIK1+p/5L4Kr6zTRVhK365kuNT12pT3hmnDYtgXDZKAfnJ7gvxA52dVo4
+x+S3b65ZhRA3kYP3avVLPITFH1hrVugNfDI6QT4ZZk2uOyla/h7avaSouK+fznKo+x0mmAIjYED
c6kV2LGP2qU4i+fZKU0tAfLCFAVDIfzEFoFG8vGAdlIJH7VuIA/h65Ir8r9MTxbik1SXLpC/+6L7
wf44nt2pvy0M+evtI0mliaOCTeurlU9WyBxiRYumPv3PzseuB2gQP/VgVx3SKi8PGFI0rPB244yV
iHHTK1fBEoHWVueO4PQiNkZiu5nHfdTAqrw0xx22nIsoRC9e1Tr/luXvQrsIbQuneCs4XRjcnODh
x9ZjBP6UnfMOA0nexvOz719/CSw3tgXCayDbFW3E7QxkTalGiP6dBGrEn8As5mdP5zGE/TnHJtPo
57sOv7XgIV8ILwveltGUtcwfn5C8q5lNFe1LHtyPmFOJn3olQw5XS7AwoZaYRMLxYvJ5kpndaTEd
JnZJnHdQsHj+kRXiAPAuY69IIYZIqo+CZUHdHyYEzd8smrW+/VsD7NwolV0bYDb52nhkL2KfY8xo
MNw0O21pc1WqUUGNxzfQ3BMe7gsBTIxIaFbr9/lHqOVf4DyUgbqCggEAX/rnwDCiUjaDZMWwgIO7
KkWWHrrS10Hu2T9t2bFA0kxmSvyw45F1CTmE46IJLBcxXb0s/17WpFAQBoX444xSovptdMQ/Zz2B
OIKcaEOhqD2CcQXydvzazZAhcFdcqhmjnh80GV5BdZ0aanpznanAdAepxkzEveUGeaKFEA7MVFLo
wwBp2DKeOLT5pPQrVhILBIskwEOB783QyI4yzUeqWYzS2hwWX93Ytc5BqlrxUS/17+krT3xU496w
LuRSRiimX5FPvXz4PP4AnVr1dg9sYjJUuumx/KP2T04eDYzPRsMEZ/NxprWttr6ZHRpfNdlq2WsN
OV3NbM0Pt4UqU486O1/VIkm5vawNLe550WpMbd79Ou7cJEI17mKquQDf4vr3WsuWgppy9rU7XapE
8oz+cpUyIqVz5sTgjR57JXZMuD0YKCoXmios2Wd6R++PQV5rwipBoS7LO/h/0DnTOutPNIgwtEV6
qqGnYSByWqnsYMEMsjzXm5F+0uBNl/uFBNTRpBhMVAempIuzWLnp3xxR/paE49Pp1InDQXKH64oI
H58zlMMblzlU6vgJzwzZL88VUa5MM2e+CILm/4q4QRbP8l0GrrLLdi1YJvYf5wzbrmCSLoz1JegF
g8u9jVt3tTq1GMzthiXQ8fYC+sSzOsZXFUlMlXgBM+VNSUYl4/FfQSrZO9CfLdZ+BBAb7JCRJLV/
xQJpoC/bWK+3vsmTQvrTcQoZP17KvxGDKVXVNSfys8WxFqJXli3DXD6HOh/zMlpihVAdPE/a2Pba
naQqSjQoyTZv5STDm346HPE3QBxddgJwqKfCqT3N2MVb+6V0ld05p0UQG0zmq6HCCPgYNaXnOZop
xClXsc1P5TbHIYMqEMdt6baWE0G0dWDhw1VktUxfvMwlm/YcLyy6OR5EOpb/MrUF4AO3XaL4KzyE
9a6VEkmDMub86L3kc654KIDRtvYAbCYQsYYWIiUb5yWrvOym7oXbntp5QK6FNIij0plGZLdCrxL5
y/lD8uKWcwS8ys48Ty+2cVnYZR4jajvfyUxbekY0OqSC/5/nIC7BKextu3eJVZU4rwDxhpi8F0yT
Hoe+pZjQeBzaauD43DWzOjOfrRtBzRz6CLSg1gtkCWK9Nyw4+amtQp5a5YZWugaWwuFxuDE9v2Wi
FX+uBwRKXmitWkqt2W6eJFwjQ7ohw9cGlQwcweXaCqNuQ9B5nQHttlyvwGlwwS01YdaaCbcx02nv
Fm9a5izj2yCTqcX/WthRrsgmY65WKUtt2fhGddWzNrAdzWfh26I9UMN0sSntbHwLgLysdmmDJuCl
kO1ksY7F/2RcNuX6KPiEjaGioCd2tXw2T6zB9ZIUFEoAwmHr/oZ+dolEsVGGmKcQhJ+1sBvUtJXw
HNcRC04JksWLkFOvIZsZ1CmZ/I5faGfX+yP4IFRdixbxyrp0wNY/ATdRbU4jS6QRgLmpMWm9ZsgT
85OzGLArqIIJ9mz/0mvg3nkJhuDexWyzxF5Vqow5xZ5UzpA18ePyChTgfSylDxDsHVETBQaDyQ0o
Y5fNU9kEyRm16XiD/1uaKbNvVI34mnNoqFAimaRInch36S2vOETZM0dgUBJtNdiMk75o35WLQkwW
MBZeiHgYHOx5GN8SGCZNbBkHelUaTht1fwmy7r3DOCugYpFiRxocrKJLBL727lU8qDMhfGXd54Wd
TLcSqmcfAF8MG3H4BgSUCaaZlyL2xlaXKRhxOYceYSkTblxKxks4aTsIgcY3A3uGc0u5GKctfJId
boYuIvskQyYXtOUxp1lDp91aS6f4uQT2a+/6smQbVTTVmdshHxlalZKdbNcSr/tWCpQ3ccKCwTrm
+nXIStUAc+FsyzR2QItl9gvUhRfALTazqr4euwtYPMu5IhzxBu7danklPsFuStny01e8N8q5aV9y
Fev+cD6LRzZGf17OKFKrMMhUi9DsfsA87bAcSU2mdTNbguu4ua7YWhzGEDkLz8v2bvgjVgPYi+m6
5bzwX90PlJ0hHHvbYkYPm3GUBWhJgVAw394zUXtS0o+uwZWxBDl5ln+WlReCUOGnr2sz3Vr9V7JT
ncH5sfy4GRZIXG3WF9ade9XDFRjkXgy9sjUJH/yU44zNX4JTpBkvjgjivg5P3RjHZAfAnKlsIN44
Q0IEo4ptYiDAiBWL+7UjZkDESJ9pwKY+6ixsN79WrsTutW4S1/TmMX5nbOhZ5COtxEnbxZRVL32Y
TKB9KO4A9sg93Wws5GzjrAnMCTIlpFlXjj//ECuNIPGIR8VKv3lqpXpU19Lj3tYJNYS5s4jAgc/T
KYS3ub9hTOIIqF8KUkIRz4H4FvO9WjeLx16IdDAAG93YUzSfo6E4m9KYiJ2xLkOO0H05UK7Wj8xq
S9TiC5oie0vGeXYLir48UlswgEPcyLhhjHzYX4lVl+9EHF1pVNn+RUF+jOUK7auiWZQwLHxgn2nn
Uh5WJ8W86tOFZVk2Kjhlrwi/bsqhhCeYuEKeo/1r4MypbKw/LNgVyLclTHiQafjPbTthzdoREGiF
G+Yyh944cG2dqr7aTSLuauRXKAdQlYOSNCyXDeNYM3vkLoQ1ifofa80so21MKPSCazH7aebF/YoB
2+mX+ZGZC6A+ZEwFEmBQra6GB13PLJWGGi3KBLbt8t3me2YzQNdK2kc2AajTANi8lrQ6x8b4FqT2
YZgOMm25roFWoSvcjgWLEBpvxtoMtfwPmcyZWqAK7QlewEgoq5t/VsIz4hsxJEkC1TbA5AjBSLOT
UEUfYPV1EcO4duc4/IFWFgPsv0u6O+WBr+wZ5rmiw4LVn3fSIBNyVObSCJr1QObAosKty0kMBtSt
Wg7L8nwyZeZcG5puVEX4yqYFE2dyrk6fEE7+Oi51WZJmwJai7F87SKQiEeWkhqhXZm2fR2dJFN0U
+cgVHveuc2qa1ZZyB8j+haJMkuy0e27ZgKOz7CiTbDN+PE5amoMRuoaNQxcwrnF0xniXK0iLi/ud
HoOfdI+uQFA6dAQIkMdrcgGt6cJdavk0otHveApS6U8z/mycsqL4JuVHDKGzXk7SnAGcV0akZkdE
/K2HdKsOdarlV0m3K+HaQepMCk34wjoN8KD/tAWmCTsvyosy/H7pinGnoWogDGTQs5VWh7dpfrh9
gV4+6ZQ/+WM9aXHXhP8uWLAsFZqkghhH61aD/Vz5tnPnzXOt/bIv/Sc8nKdgTm0/KKfzfsxZCeFa
Yzt650q+nklTgZbYLjek83Cac0n3oPmQ7O1ggNGg3297HRHDQo7bULzwqkk7rPU1aSdIPijrHXKZ
r3POfzrgYXA5TAa/Nj2dbRvMPDMdK+x8LghTPHfeswSMKEaIEBkcKTMlKuAFBg+A6vi8sojK48Yl
gRbGw7D9d8Cf81QghbJDb33OOaz/P7zBFgzS1cvircdqkqYDH/y9xCsrIsxH0Vm7Nb3gTBnSl9ET
rUBM8MFcbPO33yAfXn2/50FfsoP3BECKMKXxwM5Z+yO6zauPRQMckcDAdCUstQTocaYLZF1g9Pjq
tBoaeyeMd9JEZvwdBiIMnNJdlWJCP0ygo+Xm5lfbv6cmmSRsF6L0p2EoT9LLTZNPPD4SJ/r6Aar6
3AOu2UPBO8OPiVKZTiDDra/pZnqcm4c8JVgBNf4oAGAK/ykX5QrEoHoVHgDoB+Foh5586huyxs0w
1ZMl9R5o/8PDSI5QTKxbCPrtibs/7BRPiVClR+kXd3L6sXDqsynQ3VAttDgAgmYcD0bEdISGSxcn
v+GQshK0khRXgm2Z7WLzd5IoeuH2LPDmDiyxbUlBJkHYEuP+aUGvOrDPaYSgQSy4bwb++fJJi9On
w9jHNcnggbjd+00PW50PidyzArMdgo4wkIwYAn+8wUW+dYF759qyspZdKN7KMCTIrV2yrHoEbGym
b87YjygJVl5yBafgC6ZfCwyqykFSf8qTAXDArEcR4CvG4IcT+TPRAHPyvy78mtMsaYTTXbySmN+D
0x+s/zi9Az5BEJiKdtlI/yUCdtMvAtMWQ3Xv1sDYLm4Yd/GeT/tzm42sETjgNNiADleq/2cfiard
9OMnuJaL3ccmk603gCSMagsF5aTQSRpvkt9gjbTnJ6/Gl/RvAROFLye/JjrYlqsQZV0vHu10Oq5R
44p3E34RD32cCqpotVZYaBE77FmJcChXIq84N60BTcjXlnl6UVeGrD0TDFls2bjbmP0vrwsK41fJ
cl1SdDwNaFV4ewWTOAGUj8yLD9Ret6Yd5yCSktPZ/iIf+ME1OS0iONjzpUW5UOvevBN9vdbWqBo/
gDzl8ISskLS9erYmCzADfU8qkGhh4w4ijYoubruPlrTiKHAtGAmiLikpSQ2hI0rFmSvPiM+cezC7
4s5/1FajcUWAZZiwiTwO9ZtRfwIXbeU83PxQfkoGvlSf8/BRlhnV1mm/lhqdlXSDC6TeQ5+92KQD
FG+1qQuDuuhklFrADsXmYtsVR2QbtnIleZVWqm0fq66/mtWOv0FJcABveQdM46kiYd0CDFIYFW4C
W1WLG5L3aSTHgFJEnh2Xyy16gwaW4OQ8YF2rFPkWGgawBsY7d2y2DepOO/t2FJ9oE4lZny43Qqvr
PFE3Tb/4IYSG/tj5NVC3gsfMjT08AyGqNNJyQh3BXPDsx93opLN2R/cutRXkkOmMd6GJQwtF/S2W
rfg+XsbuuLBGaGFJPyGgew92B0hciIvqn84VEMbwJknFVnrrOL2VPe+CK7Zen1EfPwODWyOnTGJT
2x1bBErZLTeO/myCIVLiGF/9UbLab1/uFN2t3QykDE4UM/GtprMgMRN19wXd3hEhclk0AuuCqXTh
XVbn6qFkIjjoIW3NL3qSgzgZBymgxsF5SQYSOhAYV4uOtd3njJb2d98Ipg6kMw8Zq/h1yAr0k9g+
VrfZF+I4bqhtwAtDD8Y0QBxtjimSYwfIktlVdm6xddGBZgalKehd/YtIIuIdvxMLr1zO/gS9StNw
sJQeyxAh8h71GpQ60Z6oyzNvOeX067QWmMEvYb7DROkCNIZQUyuFAlOvb1lDx1knNH4yd2WaZK8r
r+CkmikoRvzvI4eU/o+jOsvVFSWgrydlGdapIL99qPTQneQcc611Oon/Ab3JGfqeMX1ao+o06umh
8vZGBYpMgKlvfN3niid4OiEjPn24owe4P/wf0BcEtzsUH7lWsUWB94z498es+fxDQnuoDh/nY4gE
ajogxrVEIHqfTctwuMob0UDFrvsIzKwQf41Lv1n0nRBcPxJLM5UJ4FJlZIFS2RYIJdrd7gF+hih8
YTOjIoV2JrfBdD0xK//SdmI0GUXHf8DOIxI5kGMsMA2C3TGy4lOGqx/ul4Vad3YQV9RCGKNSBSmP
swelcc76ZHQsfBv+R3E3Qhj5zVjf/K6AoZcuRmOR8oDZH3kuE+SAguAzah/7ESvKGl/2j2XOqDzR
8iiw4nialt0pWtCS6tkAYDgNFRgBuQ3JSTGYVBXjfuzTxw2isrqagSJPHE99MTW5AL6pXUJymVgE
5paNBZsADMcR1hyMFUpH7GPeGsBLRgE/AKMgA2GARIoaY0qLY7Q2ngQkpZxzDK+JTkB2d9bPAKqB
xP//3NfAVyngOJmT505S7l2pkRJA3zrYI5j1lANxGFxyNlWR9ZV+jIsmSRw08iQNYJKeIVFvFn5l
1qGHvHHovG+z6dzxC01rj9zFwVtlh+QuGUZJ44LULZ8d9NIxqFBTw6hzTFEuL46TS4KITWMTa2iG
iawcNB64KNCr/hxLVwfmEPiO7V96PBbe96vC5j6ZdJ9pZkuDE6tWqujrPd9sPbGbOKfqfCMu1lqr
gnQGK2zc+8TwEh7mbOGCbkbR8rdZ+ejP/5kyj5vlz/VpfsT3EioUydZUsNTWnKPuMXaHjUC3y2/b
GmPmlTvqKIvOTpMd1gLCqFjYWWqhpTrAlg0gDtNHHujuUhV37JUpOgQyqvu2yfL0ys1KBhX+KKzc
fwwwsbhs1XqR56X2EuKNYJNJlfGn0h4d68iUsAfHFhWSxteq/l50Xe9B75wleo0rPLXaLl0cZ4/D
+TtblDQbPjt5GD6CqdaoLwzNDp7sbMuVyDrKgABFbLepWep5iWe3Gx/9AEaAD+qIz0TQtdMLG3Xt
s56GGUY7kKfin1p9z+rCo/yd0eak92VLYq1YxTUoSy/7gKhZBLIovInn1DYeF2RcZSBCqIdzpQJ+
98rQYHmzURIhcv+960/FqHzeLpfZn/4+jZ+K0qq++ARWl56UCMS/tsJWH18ASjhi3yXtTN/dMk8p
hr363JRUnazoPzjnW+sZCU0jaw7fLxTzW6MNxyBoD+X/7zjjs2QTAfKiYAfG04VO3HS8raJF/m49
XxPD/s+Yn+z9K8/o3QiY/hQ2Owp6xlB73PLx/Ldb/KPzdc7AsBfkkQr3xJraAEhegTtvnN8n6oXO
vRF3Rv82uX3wiPSBbdaYW9949zkFf3UcjE8vnGI7jymx5eK+9sj/L/mOK4+TluKQDEqo6yIHAnq0
GhXokouz+YH/biv/1C3pYYmZtYMP46TSbHeTg9Lhu/ryEUFxRs9tGTXErY0InTDpXqBpQf9mHK6P
2jF7bW0saKO+hhkzIRYnsVhMC41X+i1uG0CBOfDFgVwiXx1PXdcUY3Ez4N4DDDaZZ8lgUhbTvAyQ
vaX8ZCRa6AUOrcqYzmY0xNkF2vkalIbqfrKwMkpYQOB+740RvNloTG/JSkfhyn4cBdhsahtu91ea
NNcFiukrOsYLZKcNdJ45Mw2NjqFrOf/v4RBHpRrZh9lgJn/7ua1KojRK9Shb/LC1mdgBwm4ut5qC
IbuNjzS9FRojFqDP03lRHGq2/iEdHIVGJGJ08AW1CU1R+RE/psouENV28DWBBZTGfc97O0HqTwnW
mmdM9wjCsukKN2qX0U6w7ELJHDTzEcQ5PcP6FZVEVoF/J4LzSwcN/07lodkHJjQVOBy09bSBymwP
QIi03OlXCj6VclHKBXXmuRLluQ5iYY+6KbY1FV8ra1GBaJKT0AOSlGoamYWc8oO6xCHOKG7sGpeF
8wCJMwwQ8RJ7jyvvcot+FtgRD22B1nO1yYoWSlyaYksIIDvyyJhSaUOyZcQY4nvJh4mgvZq9WZd9
MPAFAVLirpMKVk06BhngHG87iAJIS4VLaGq4T142hdx6ELiOJ9khhoKcF3yNDGZBnvbwk+gu7J6M
Pb/65XDtDlI12Cnzk5bMFf/GQLhNv6s6MLKvmxj6J5L6KuSr+q/BDVn++YqfxqNImu3kEBDwVBuH
Dd3NiFcUx767NF70AigpY2oH0AC1ZlEq/SGw5vX1bsCM7QfGyshRT9Sc6NBeE/hsEPYj7ILxy4Ms
NDFqF8UK8Xz2RAFmlDgidkRzc+8TGyiT/micX2rDw8NJHyKQcgHDOitN4jL3dPvwmmpcrpckFLGQ
fH1WLGzW9XDZt9DvTmixYAMDT9v2pQiljs3DP8jv6K8yG8SEK/knm6eGOCKXIK3Nbrz31rA0RMjQ
hXPUP6pXE2X0ip4wyYPH+mZVWJbfCum6iggLnX0+IlHo1eSy62FretQ1DKarwuuBIDwT5TFv3o2I
b9wLS7pSHXvZ1Ezg4YlR0fwpS6NGbJUqya1KAEEFau4X5/julyKFyZik8Ymji16aK+ZFB2Q0SkvU
x4TZk7vbIW5+fQaNMU5aZ40/8jjF9mHUwLdb+wbhYbiPCifDEpf8HpUin95IbDmOeUgVLwSMQCg2
if98VusA6LtGOrR6gRvGyr1fgVGJKq5faC7rEWJQfjjoA0dfwUP8VtFCtYNdF9uyCSOUGW3JgHia
QB+aEgcH3S/CsD2251pJYmuUqcJl/UQ3pmj/HoRRHPA8YurEr4364AJZbu9d1W4Ngzhej4Rk1E8j
YFELlaWcBJQBz70sR1QSHA5icHPAc7NNhdfD6kg6v6vdizL1Ke9Fg9E3GciCp08XdjNSQyzJW7ew
1mk/IoOn9NCX4Pg2XFLSni+Ar0wGZjnOvHIYafxt5Qu4JADtchbzzQT22asOMpAP8IGbBtuj4ZCL
cPZq19fb6qMemofTQ5dyIfyjSk7oNXijwYi9+CkefHNgDugJjjyPRepN37jTWB+FmEI8rUp3dmWo
4IoutAZtR3C625LS5AVO41NccTRl7bIKfcgIQGVahZr+JsFfLwdIcqxkKLW2Mt0Z1jQx3NhHuKQS
sDbI5XD32gZV9gbCGPv95bxaSxAVdv4eAleBlRI5BdTEwbAwJ8m31S+CgjozBpbs6lOFoDzk3g5A
IjRZI8Mp9sY8SVmcTUwblKuekhm+o/ODtJJIVGBfRvkybWQnDHJeAAYxOD2Lgh7M9j/CKkbQ1OmK
OC1N5TpOtydid7c/9ZAHGVCiIN8JTudylhGjGn9ERrx4JhCzUOJLe63zxITy1xMtts/RFemLoxBr
nYv5XvOJyu/5uvEdGBNUhY9WRI4FgpipMyylbYBAF3N20V70+iRd+Q4+5+lCxVOmlQkZUij77akB
ABXy6j4ZZRGkBaKgR32JmNp/okgYZC+96nxKgXqEXtXi1XwuFQO1haQxACKKf97haV7Kae2scOAe
Fh6CExqPzulF0Q0bfPTAOJuQa5qW0w67nTGCGnMNDMDYWJp+m4ML/cW0NjW/Hq0jyLs1i/PlbI2B
RlNqvhHtm7Nf93SbAmMj2yJZt/PK9EmA6ptvUNT+gicCys1zgPwlBrQU0Ttrb6NWoz5g3MT7abQ1
J+m7lUINAvzuO+BD0ZYFq8ZNa1SkKsmSJNjYBuYhWKjps8QFiUdIEsO4iFIxbooy1VUZQsmEmKLX
AQ1zMiGShfkA4GG0txsMrh9kh2w5BNnhxBtYg49nVPhBUaEa/e5eSNGTnWn0ih/A4Nj3DEtEHqvz
XFVfyejf1DmWbm7tHWc/hiMqDPVpdFrhpamF7OpD1mGp1cQY0Aou+K92toeAPD/5vwv5vWXC7xqb
BpTEXNjQJOMGWgXFniKJBeshlyMVolIP26ykx++RNTVYL+P3iTP/NYj0NeRhnivuAj1NL6k+M4tP
QnJHMwyD3/Ql/VL1Q988nbUAvvl7KiUe7BUPnmM6zNNFN1WR/2Dq8Vb+CQmRcMqEeyUHoquZFvfy
NbzqWK0m827cNsLwg/yxJAcBGBdYMWlYrePboHA150SVw92dt+HVxKh3vHolm3nQzruSaFjLhRrj
EgKQ7Cj70/6UVKkL5semU8AryIWsCmHge91+vlVchPPfh7oMmIXThB1306ScRs8qIkIPniFxSC6w
2mEvdsaiE3t5hGRJb6SUYuBfY7nJ+0B+GKEdUFuEi1lQAoQxaFJdzoO4NAqKZUZsq/jbViOHFpZP
g0Yp+WPjoKX2lwMfTpsh1N5HXy31VgZFz0Ueyh+kn8F/64bkK/cAd9tACAneVPmQepcziLxLSvLw
GZVuI7XclR3qicvG5zRgDlwM4edo36/mKE538dI/sMPSon9qcHt2VAAUbk8PRh3uWm8fH2zxrFbm
EmsYx4BrQB9KV6hronzkqqvkUVZSi5I/BI35PJ5VRMZ9PMLn0QpKLb81iCpnELmbAy/cBvLzQmVR
ngDcyCnjJo1jqpIBkqYd41YVfffD9+w06qZnEalyRzCQEDw2Enze47ZJQRDN6oF7fTTpeQhbespp
CIejKcYNCGZRUUXEWiN3viM5vHCDqncmBj/9VxQeyPfjFL5HlK90Oy1vtrcjxvWoAsTxfzCEm7aA
a70qytqehAOOtTbmOMunrJ+3YgqMsq78Dwfbw0ONDrEiuSh0EftOdwyS2vqrdn+A6rpuKZbMZSfz
vP9gh3UPDi9x7rcclNyKQYhvvMCE+2sAd7gN5lOLe2B7OhfI1IqDdYv+7SwN70ZE7kKmYG++qUUy
YPbljlzinfsg8ayoe3rVhE9UJoX0rKoUTFBxY2rN1H54dCl0rki75ZKGwXoM3i/sKf068mpy9ofA
fJgGMQLKU+SrjNurTlRgQiPiaIwHf7CjK7RK3IGkMPWz2tXvXhQmCI7qXSVF9hWx9La6K7Ut9bf+
awIvWVT3e5ZoOob4A+liOvuFIhyU1IUpoK6gPeKBRTVuf+T0Qs3zdd6GPcML2GqEZWsRmaf5NYsU
mKvY+pXMYzssGTL54c+cpjgaYfcqPB/aWip2G8v1/Sntgi90pm3025Ahba85I5Q/VIvTx7qFjTKS
cZFv8d/TAcQAbym0njWDHBJP3AsSqp/fuqDySba7wsG/kBq8VUCOGV+EQ1I3JTqbGpcvKDQvBWnU
u2FEzOkFM9LF4uwL2KDkYtLqa69kKZhEoD7BdKxwBcJEyJqMNwSP03edYXqzmvGAmUeg079h0BMr
B7E2SdcBRIKd9ql3ZNzNjvYJZNDvNnfytllkLYii3Q8qUgoRL9nvtUOarCxHJ1w1s7WwMoer01Py
L6AwzNUPDjeNet2E4q0L1D23JLusiRQk4DDYqeb/wTPcsLkKfkN9r51JL0WJB06rPQIGFvSZl/vc
do9A8CbBIx15IMzRUnjdOeHFTHS7vtxBFMYyyaTDflbjYIIFQg6csG2nPa78gqBCGAKTPNQABdxI
oncAYCsUmyC3tZ9qN6RXEM3cOi7ttCnWuC87yo8katcs1uBelK5PfQ2B/LL8rFxCNAlZUDMuUqEz
yzjfCMOiyFB7kYj04QUsg/4viDxrYU+rQnT2UfL8VRIx9CNOORJP5/HdJHdNZ5tmVJ+80bUw6fiC
t/TFxwmEz3agivlEOsAYBnCwJRQtuN/PsUo4zRdRTUGjUlhpCsqf/w4FGl9qqtaVEUDGs2v63aem
4FhX88EPrZV4/zAu4CNKYNEVbUVP0HuYSLlw3S+vcWVEIfZIchbFst/RjLUH+Q51g7RxUoFSrTwD
u3URUpnaFJ8QFzUPN5cX5Vzlz6oh/9Z50yLd7mvecTKvJF1YilYddw4FNXSRkPKX6ZQls/nOtn6j
jKGqAhGRSeWD/wpgz8AaZz//k//kvh17e+6GolVg2JRgjOtkbqLEf+I6sR9BbwEBqVS/hocJjQUQ
JAqKKRXi3g+tZiMJB6nbmR6K3yleTHGccMolIaVLZH/d99xNjgMOZ29pWDTNjOgX9w9UmobbjSdG
jvPr7O8z2gaWFRlgcaUdt4Vtrw5LDly67o551/5hOm6c/UPgBurbW86XOnQLR4r450tVSEsj/w0x
PKpqHOuA+nz/uqm2SPtbNEgi7DSO45tXPfebtEV1uku6qpI5ABvey7ob45+2FJhaCca0eCMV/2tb
E1rTrxZUtUKuGxI7Q2vXCQd+dt0OfaATVUOXFahL1kBmRlSW9M1bdsyhgn9sVZWK//8OV1qli0Qh
sC0zosAWXq2515iL25OKEWgqmcd/vUm3tXNLqg+W6OpE0B2IrdnZmTI02vwR2zGKhzvhT6n+yYx2
G57VvhlCv5gZ9VwC8hY5CNA0sYgdAAzOCqrS0LzkgKbXQ1Nhx5ntXMGaHtUS5jJtES60+Tk8avRl
Wwuv52VKGasaKkSbs94/uyRzPj9HWojl0Ab0mOYqtrI6EcinRLiHF2LJo7uzETjHd91aP/JRo8MT
5RZOf45W81PQAKfi7+0MQUzJ1O+dDTTeR7EHk5+Vmfx/0WjV2OBUny/vS5zlzkaQzmQbtfePxDht
RPN/+VwW/XxDW+/6IbHHPMxwsYwyJWQZVvt2Oukj9JuVOaukuED90S/KBYdIXbiGweYbLw7k2KG6
cfE1XkyGXQoup/yViOW6vXh42tFWkJrUHSWtqaN4s3Y2CmbgWosBQ6ZyTavmLbCq4r1e5rCMZPZs
CgP1WWRPw20h2MUz1Y9Dup9HS30x/dFPg9VNGrutlb0xf9jNc6MgSW4fmiSMJFLxHGxaqe7v6h8N
xtM9748y8Hjgax2z7IdSJPf3i00p1JRD6dNBXBdI9+FeYoKu5XWIvJ2zJNE6+F5zCRpze92hka3Z
80Jz3d10iLqu5URwhbFIYuJPqh4UJxRlomjNYDLXvYAZYvqnvT5+XuV1UfgWMUqwD/Z/ZcTg1fbe
NPf9AlnKg5D1FTuOGbRRmOGQj9rX85Vu3olusEFbNN+VvfoujTWUqjRaIbcRdbDJrLlbBNzynBtd
TfpgZ6fmSOaRVVYonpEVeK5D4fbfdRwl3xO2fm45SByxoZTcYztoWyFkK4t6VoYDJ4Jv0WE4rAiN
lhCBCrx2k/ROjp0GncvWPihlhQJuL23uGP9HZilkf6Z1fOoM4vQ4gQaJY9weuKVuL3PnrVf01KbD
BO6S3x7d2kDO690UKd6h2RgxTbC/qh3hljSQxGf7YB44LEp7V7WHbGguWk1NlB4osjLTcbU6DQQ8
h/Fx2bWsgEJXWdGjJLv9CK55k4q4VdfkBH6ZqNYMBpz8At9L5f/J1May3BFHhCuQBnulafnChy8s
jYJorwQd2mLSIxJgyN3m236BYjb9BYFIGvc3Y1nlaIrDTRhFD8K9ZPVR/vVaF8xuBkw0Uta2LEn8
shPItqJNVwuHzRg+JxjjUt6iCfxXlykS+uIz7il9yBSinjIeQrVcOsXfJ48G3egLNFAEjTVlBMgR
DSVBJifBVoGR5xXhXlkK0B6mtUMueAvYRYuxBNTHZ34461OIJj3h9UU4HtXX4hKMu08TH+tfXGfT
ecztcAZFKqhAR1axvazM+OKuoPeA4PNJnGhpdlXe2MmKyd2gs0yzwDdzk8HPKOn3Q7CwLKv5C7da
1gN3oNWJ4k1whneKqjtZx61D5tiPCxq9wlK/3DWmbyuy27zA2ymVgv/2G1LUiK9NiG8auYPbd1Cq
ifnniUfag9ZIXvh/wfpNwZnC6YE0i/k2SMZ4fD0IL9nam1ZwBVy88AFe0ngk/N5MNccD00xONIKn
1i0FSzck8tzBZHI4loa8igSPMsRJFUtOU/pOJyA81cDSRzOeSQs2rxds4ZAIqD8BYhHbuqJ5VRUH
jaOLHQGZb0JX+bkQ1KQlQCwXjlpncUjPXCYULPvgUl9tWfs79KgMSdVceOF8Go2hCFtZVvGe2lB6
Ul+Z3yLmr6Rt4+NplGCi5cj8D8LTHrYS9F50YltiuqV1jmt8pOE28C4229NlBsg5/1OVZTZTI4hZ
7lizpeWV89wJOPE1RTkAXjhEc5suO1P0AuQFXA/p8PrwAHJTd8My31haD1lHlTrPZ7mKYs14mRjq
PMUyU6MDim8AJqlMBS+mMYm/INGuWqmIu9vDjDVT2FUNm0Y2IeCyWUMZzgHTvxjnory5L5QDYnRv
GcuEplrVKo69gwPRycLGiTAiq532wfndwp4On9ZccmL/pFZA2zHbx0yJNe7npHFSRX6g6GLD2v78
XWLIkoigV0U9ggzCncZo7j/JJcBc3tWeKuPG3sOT1KHEkkClbGPoFOvo4jhDG1BY4D606udd/aLT
1ZRUgXlFtjB3c1isBaQxBg0d9qwbD9hHJtGGNvWGBs54OZUM5KE44+pob6ibI2WrP/qhRJvKsfv9
ukfTYEE7xFyc3xHXaDb10OJA3Lime3h56UcKYAEMZK1QHz95LEP5rthsI6SXcmmxlkaMNmaW8OFH
V4kzQ6VCsgL+0awpNcu8YZd3h3ZuKnNdpOsqT5tVnyKIAo+dGHPedplFMmR3ktYGNsiVBjmDyxBk
eB/5B6VIHLlOo8cAaLUr4FHT+ErwAaS1rwU4YHVq2a48f8jrQTSLj50zSKAalyQfNdQTHKjgrbss
VPFKwbxdhb2r0jho07USQnYakKNjEEsDILGm8QI9G3Tc0zArsDRL11OKD7RhuvU/fzPicIMunvxD
34jfrdOhkYEsZ1h0TT0oWYOjtCqRcOBMghJ4juiqRSl94/fqQFLMtHSFQa6hfEnOdDRLVAJz0BHW
0VA88f7S7kg35dUmFPzS5d2peLL9oBOVgDOcCQcTVJXDxmjw90yeBzttGlsqyVEFr3EhpL5Ei0hy
NKJpGuWvsNjcRTXKmVmYXAhrz9cyx7NqShPTc/+Dyhjr/wMa/9bixyZ4qe2s/FjsXWz1+I/b64jE
uHSpL/YjP7KRo6hyZHwMGw2VrebirBJvzpvTztWyckT0uW+F/74qqEx66q2Op5aY6pBvoS/yUoPc
DTdfUzlr34hxxtl1jAaT8AnSVVeaTgFrOyp7afJYbW19t3ocqunrVhS00V8qdvcZYnSwi32AkVZ+
oxPcZlkoLKlBQLaq42zSlHRYMOjLaKeRVbJtco/SELZ5CJtA+wC/jX60r1BA5uSQ2h5FTPFYpZ1N
6K05k1h7tyTH89KyhsCkW9k28tTQOYt/Kwo3zrm4IwKD2ANXOcxPChDQtoFGf1CNEbRs6FOjRxjg
Bc7WxLVO7DH+jci6CxXZbJr3ApIrmbhAvZjqqcFoVe/0VmdstSpCY4DlGMtC/GBbCljdwahAJ4x6
/lotxf2oIhy2HjU5RPL91xH75hOU+02qELDs13pBLyg/R32CvrM8ZAu0TN2VmD0FjkOy1m+Dsp52
LRmu4Ze3412kre06rL0F33qHa1QRUxl6AWqLODzToui8fgizJsiTK1q8SYIgrKUiPIoRuFb2XZ7M
s3d7HJP1vhVeYCE4LnaBbiCElk7nXstmDMUwPMYwKS65uMIu3aiBSnQl7j7bh1nwf2RfSUNMlPaH
+Z1gF/SYW4HpHJpuCOj+rcNGurltSioT0RAvpWOdcdBeC3vwc0z4ow1/FiogA1EjCM2IT2U5A+8l
tCNG7mjTYPJ4SQzktuqPypC5rMtp3xMxI63nB24BUxoUB9JBwM8twGWIAxCSk7YiIrRWKgGlHzuU
nsDKyghnxYnLInFMPpBg5gqfbrsNk+2fppi1Uv+b/2MacRc5lDwwOtJ02NQ5MdbMj194thv8ggEg
UuL+OOOxPtwEauWa8JNX1TGnP+pZaUR1zU8IiaLqhqmLbX1UPU8N6251NzrelS0RMzO6fohdqWnt
us2m70aU/RmlfPkR592ABuTxUs60z1cDx9TDGkRDkbDyTTCTMmwJbYyzrySTPV8OpFXCfGYdltg+
cZByg48+RWiqDkczsAU116TbW0iakJWM0IWcXEK+BHWxDHWwar3MBGKxtfOFaudV4DBO8iHcV1lF
LRtNH4YbcZwv35Vq0OaUaY9oXzZtjaGt5yjltblwhPhOpTUwzj30XLujqU2nxC4IKq0AFqdtngDz
gBZnlD/PGRAgbct9FtCkPpIbzZ7PNlfm/oDmnEfwIATYOWyuB/tUSKMnl1d7Obisv5KP+mu98mO6
nKGnaBCxRfgxPwdNpQgvzI5r+Kq9ho+C1DNDI8GMFfJkzrm4WxI+N9wt3Ux5mJGzrmwD01hBFa9h
5cwj1d2k3Ce22bblGh1Tj23qYnAt5uf3qU4BiF3AsEb47IVQwFCwHy6WntlRCEYutae3mTEY/NQg
bXA2Di2o8Z/43Yc+jPj/+XoFhgVjelWhVsVetUbSkUwTvBSU5Pw3leQDWDP7SCnbm92vJDRNtnj9
t/mOivwluGXbm6J7qtEjrCIe7rv2ZVyBfOtThNASkwXRz6FPZYl5eBtRscWc95M/8H741D9lSZdD
bCOuBpZeKl2GRQBiGpp0+OsDS8q5KvKMb0csgAN4oWASjhWk4FJcNHX4MU4RZVdUBSxDvxHe9U3f
RQRog/ZjPWPubpIAk0FUwfjm3BTwsE1TA3dWRn1Jj5jfILKTB633MCV8wpi31zJIEr60hhWXvmmm
k36RW9QnLmsQcHioK854dTZ3GOXKtC9IDBJzIIoqfOFNZuSda7G0f6U7efJb1eb0JX10RAGC68u+
+LCVcdk9Cs+zB917nLjwIAa7ZjyvLpHlb1PIMQYEMHT66NqBWMwtavsERIqV/Sg+PqZgHT8sWkUR
fI3dDjxTx5GcicEuty/gH4S56vVWDPF5AGR2qWF5rCZJ/xpJZirj2Nd4By+pS5pK6e+Xfp3w6cQk
I81/F/MHYJaIjUGRLX4h6I2ws7kOdrT5nBjWD8vWtFbRTfZpiyKAVxDA07yywOSJ28tZwi7iLFIy
aXpHv6vBdkQk4P09HrafE/QkSYjYgCRF2niiT88I9qVo3mWbdokFdEipxxmrO4jUjrWmEjaZYL4v
TlLDAwdakjvSTwwDBhvMwHCUsWkVnQAxpi4ZOxL/OmM1NTVwzEvnzIudsne+VZ6QEW6SOaTQQ8K6
g1ELzw6Ygy5kpEXIs/BT5nQSgypVMGV73ngn9x12K2vRIXYiVmoSDvrQqBfW7euij9x1DSw0cY/3
J7c6iSIqVjmnWZejL0EMd7Z3/e7KPFBJq1rbd7PZ4D0Rjko2HHglPMTNHx/Ehai9DBulTT6rtMXY
jYWc5Rv9nnwBnE8pc37m+0tEn2VxEJJ1/Ms3A6xQn9htGsIC9y11tIqhZdFY1xs1cqbSD6/v6YsK
WhC68U8nGWBNuaMNqP3x51mDKTKPqA6wwQqPUuvxJ8fdIj9AuWpHPL6LzpCY38WiUTfZoDdJ29QR
u07WOMwUPNQeGMdXRIjLPFgHTF4x8YDkMmDBbNncJdiDGXJDgtxon8vp0DY40j8mTftwoMqbSrKg
ZbcJTSt1YtpuH47Dds2SG8gwpT2zhUA7dHgWPjeYb/LWQXbrQ1rRLs6j3JcB5569Hil59G1GyMDP
Wu7CSESqUgVZeW3dExl73x6yz79NcqSUI5Sy6mxetbwjA1v8bbT7LjvSY0VYjGeTJVCajTKsCNU9
F8CEJzjOCWMvpr2027SppQFkasDa5/XdBGKDtZkLkCTjPGv1O4/ljKnkqjrl0UDttrNCGJqX0fkR
3Q1VJvnlWQU5xlT+4B/8KiorSeOI01lUgqiOMXvNO1r01Se40NXx2oqEWEiZOSN/GPQqvEe4LCXk
tSyORYbdHFlSWQQvvCWH+ubyBb27fCfQIgr1s0af+iqQ3hpddoRmOYUPv3VraUGE6c24az2ggN6L
0MfO/xilHSrqOPosE4wHS966ciZQbMhYmO/LJUlwEh2QRwnCsLKsIySgr101deASV3p21wHKHbhe
BuQANxIJ4LpLICrJPaiUno0r4H8x26YlRCqtTPFXvXjVTX+kVi4J1w2ZdVhqf5/1eP/Rr6RXFF2d
UIcTEAA4SQtcMGP+6w1sKVzAbMz3SkH4OSHWlFGPvloV9wvl9bLi+P1y6U4JN7VgVGlVat2+6tHl
Qrl79Im/H/oQqWYBCWLFnT0lu+diee9/klFngY3tpySC6shRNcN64DJmWKt7WKD8oOzNQR4P7JVj
MCo6cK3ZEWVNqOv2lRsEIhfuYzOWnZ6K49RNwP2EqxWcALm9tgDzyxy0LBIftPQfYTQrdbobMr7/
ooWniCqfRp1yGKErpqrFEHqPLmQzT/CbN95M+qwCbt5cRQz6FWbvZPJwNHFgDhaq94JlbjzCAohB
PyRqeK8kjcLOzpNC0Gr0wMtVEUjYvd4AYyp9K6LJjhUcLa8p0i0hSUsxcWJfu4Gf/eeVnyxPkoYU
lOv8JsfBNr6tNhaTg2X4uuOEkTT0Eu/xq9G8kMnsYm1DxN/ZgFEYMXuv/SLdWXzNoJ0/FS03/lzF
yx+JyKVSxXHGgNfyaCnY5F0gsjMJwok8pJZfjVItQKHnk2SBjTr26cIkVmQNck7ujYvmjkHMH8OF
mGApW4gV55Jj08rZiDjzr3goGxNbbQl0sUSjvbrKY5cL1g9CmtvExSPwaKu8j/mO1qzdY/ZW8NFb
Lau5TN7gDWlAJegXiel5tUBI1mrRI9YN75qLYI7urT87K44Q0CUBWfvSUUHMO574b2LWRFYHHC9Z
R1MHPXph3CEbbEnr0MkjvvlW5h2v19Ue/98EGkQuXJ9lRYhx2FGxSmowK8jBd7KN1fBdrdMsxHVS
QdVmbrKg1YnEPwJQ/D+emoccPdpNb7vS1ZvsjgkIirmBJx5RBCQGrQJqhWV4fPbranNCn7d/MFDd
CUDK+CkUXvEtPD+bSoUBg1NTYoSvQgOxsNJ6lkP4xyP5dpvlgOx129C/7Lc21CxOpQjVxNrZNelO
FuWd7FwN2WbscUN4neq/OlN2SukKVTfPZNx/Gz8AsflgV5vtNKZpZj/ktRqnffL28raPLPKlTi/E
2VIBF20WLHndOj+95k/LsVObfNYuNTAeMyemjV8cHKeB8HsTRtZbZKP7/psRs6adcjnXDr81r+gL
r4cbY6cZPEVeXSHc053rlKxihhKcqkFbL07zXeixfRrGIMU55Ae82x1Qbn3R2mhoRnH/7fDevPTG
GViMu+0gwWUTJtZxT3SCGpwX3duVE/SSjKHktwY4Qji0j2t9hphrYOy/Rr2E62CwlzrNdg/pjqrx
zDVNoEtGirF5OK5B6TOUXyS+0YFJnSVnj2aa5i8U/bjDq3+IrF+Bi74y/hR2N4fxM7FN7sOrNRb/
XPg8z20tLbCgz1hnYTpCbNqNBnu3BqNEZOQ7fmnz0mrvZpPiG5vsxfSL5p6zFKpAEEYWgueBiBs5
mMAoTwsJTnte3hZ9cW3uPwrS4EDKpKGiswESKolQ3BGQfybxUdMP3xy0HpMVth26RDVlgKzgja7A
qlLrm4SpJTGFvygb2r3icExdUoUO8haTW7zd4W9VePpcj5Cjn4OgXed5sZeQfFEyzRtvVM8V4gbh
w8UBJtDDp1zyIJljW0KQhTMr6EPKIsZ7hgAcJfoA8ZzdCnvQ8aY9PhxDUHEIz5m2q70E5XMsvGJq
RkPLj1Rk27VC9IrjfWavtZ4QTjeVVwX/5XH8p4BI+O/zD1NNYWcAmUQAKiG0fztXnlqkuo2Srx7S
oYdoZ8Vmm0G8JPmHfIpAWqJZjW3lixV1citEzxxsKs4Ifhuj3uKLTK2b08tMY2umuvbmYO91lwKt
Fji0wNG4Mn+N7BksnhpVFWyD5SquXaVBJtH40NPl4gy+zOS3z9f+uIVC/GZDFStBgE1FwAQnWXTK
sRhdSJKV6kJjGYIsLC6on/V2+WzxwMzP2jDd9g9J8pEmF9MIjLLSfu8UEP7jqsqI7/hXAuwdqh4w
VahqCaU/EzYi/smY0FTl3wvQS6V59rKhNJrRWv0Gdm7GP2VJQi1zgQ1EHM0krEL0g/o5ubsc1IR0
xuvfpiS9b7RDFkqXoQmbLUE1grP+yS9A9wN0BXP1iAp71kJBzVrFPJ8icOmq5o6V28QLOU1+rl7u
SIffALLoEO6Fug5cuO0LcB/WY6wo72UidXMW88PLchCeZsutotWovvIQmi/nsuJIBfHVkAzEyzeW
gTNMSZcq8fCwjR7n47iCEeNG+tRPdFUmsWXYMKwMreEByK4kUVBRHNvO1u/uuLT01DuP0jhwFbWb
qNff+QqRZuH5wOv/2x6xctBb1Yr93+LEkwJB0+/5JznjQZPR1nblWWe2MB5TaNzR2If3ajRVPwrN
FBEgtCU8zlozjF+sR0vot3NMwnI89jIl9zc7zHwoNf8pURCWnYXg7htc2a+6A39/uymBpKBq8OBa
4eBGkCt/UtXRVpVfWDpSbF6QFOEOpBqOwD3R5lBaWx+UfkpWRSG7CqX0yRD4crRBmBWtibpV6tT2
rFPxkdoCxnynktvWqYV0LKM1cB4h/XSkIZxWFdWPbj61BG/lhvFg4rTebS1losU8WV8loTEnWA4b
BnRry9VyDkaEI0NCblbgIReKMBRQEUJBqPyCNYim3DTi4LYfsDxem8JVxXRSuy0qy1FsGWL/sqSm
UAeOsgMVipGGEA97oz5uPn67vfy93a0v3MsdN+AfCV/G3H0Pk2eApqzecZWbdpGcyyOueK1FN+8n
Us3z6kP4pbSAr15W9GE6EWBrxv5ApICUJHLAj0ryWnY6rqB35yD5ALJI+1UJ7B9sZ61RDEGcKiSg
3fw42b7ACi0Am8x2hxIlYT3/nt9lnK0TqbAzRsicRjvMK2Kfk3s5+tUeCS4IdMQWqQlYuilifKx1
nFQTK2OfzZQ2+lPdqPu2D+tt963X8+wRvNf9KFfs2oyQUrIU8jHG/5QvIq1mKSIFE2Vb6hDQtJwd
efIktbahhhCY6WaGA8u2DFx0J9hZcyMS8EbHq3yuYfMvNwFQIgoLvWUSiG/wJKWW1GKHmHrbSXQz
9fGR/ZSbLr0A/LZImgjMdhzkI/vxsMjSkvbGHsztKnCeTLjIypOaPx40bot4sq+5rPOi2GYDWmfJ
FXvs0/REVBDDIhFdLtDSS5QRRtMOnSAWMeZ/QmQz+91TjIlS5zDkXxVZh7tCj4qk76ptLA/03aqJ
QIhL2b8RqhtNRTEgs9JW/Fs/YnGOANPgR4kkPPAE79R5yobi/5Blof5eilDQGiIYRH3d6LeKjPwn
83G32Z4OCA9gDFOOqKHFB3Y2DHk8GHK89YGtf1TQCN3epnTph4qCM6JPQUjyEjRNpTI1CgNO/HOR
Lj/UnsSZV0Uzati2jn3ItJ3Lsm4/b+6in3ENDSTc4ov0LiOUAmbmZUUl2KsS2cBa8e6LXPXFt4Ds
O++07e7ZPi8ivL06i189D6b9ksGTnUXxesww7XeNhRm47tmXPMAzjeNCEPFmi/CgRGPrJHGJrfy8
ngKtG4alNN/h/L9AWLxkmL+YmKKwyZ1ykPEkyjcCBFRcDLgzCbYEWMdDPKOP0ddNEmzlggTUC64A
oLIcIbuhY8yF0ylJ4VFGL9OftFcc6GM/EojsR24UzVQGFFQ8m8UOGRPGhdi6wIhtDtyQSeAhrapz
cLeDHTpIKnzbIXAu7vbFznqhshTpiMFEa+ADHuiJssWtPk4ipn7NPrXy/+WA71GVGxjNeBmNPKfu
IO4t93FDgTLcZILPR4Ws89V9uLaa6OZyg1/lffe0Q/bsVOZ7+m1uM4+SsXXk2vI77D4wNb+ACCta
4DYZXVFqwMQo0cPWNI8KSxgYw7LuBxqMdnAaJj1y7U/AJ6KyYt6SnRmiYNbAKi/T/k5ERevPpsHF
5xoGV0DCKubOpXP7c05FL+RlY6Aa5GdK0FlxbC5Yrg0GnMKc4554WULNqj9/9ZEzxJPhNB+G3NZ3
Oy3lupgf+khX8Nc4z1lY8idmNebjLiN/Lz39U2uQ/8En33Bj0cM4BKJKDB2KxtT+A/Ue7PP0Zgh4
G+JhxeDrUlmBA2xpBE7ig9u5+XQymXpRY53k7dE96OgFtLPhazNxXVTIXXom+WwWCsNqIosUwWn0
3ptjdnGHaAAd1tB1zsSAz1IQTn09IIWj0DaJmF/ITxclil8D4qNoTZLXck9B8T5CmrX133GiTl5N
UpUtWxWgp9a3kHTQHoqlJF+nSU5cw8M4I8OoElJcl1eCGUYM75rrFRv98GOZJbI1rQr/PoBMqhRE
a905MrRBSE3zK/Mdq36BNPMeW/cXiP/PzkjCml0QRf4huqjo4P4lKQ1GCjcxa4/zIznk4ej/cKKV
c70nN9T8NkSHXwbffFBFUA8T6ONaAJ8n0G/1lx2QxXUJO+NINr3ABuZomL0J2dWHjNg/OpK1o/Qg
kjkD8tDyXEEBWFhBugxQ7PpKOd5OEy6aVtuPC2MJsxWJsBg1xP6B1BNRrWNx5vK6zutBl4kzwrs4
5GmP+aqUHQgcbY9vGYtSOWmrVg93yo76dZCQRaScgwpvfPzY/X8x7wM9T2leghy671p83pNrjDyH
gQS6FioCqDB2GJe50dnD8IBkHUwihpZLuwbMXyEJdh5fRTKWJsbiUEJt0QvQj6EF2nujfRtrXUvF
ZNmTbm6jsFhzEo82xD2zqLIyS1wcu2f1iT2anImwWbt7b2sllcUZ8ou9zXwH++4L7VPFSrs0KPet
8e7mW5i85/kTQP9nylaO3LTksf7lFO9rZ4m5dKoTKh/PRhEzvFBfVtw8cuo99OCulvyiEsBYOCmW
ylZ5IN7JU62QTUIAN2Z9XdgNzhFIuzqPRcTh5dl7jFJZ8+RXd2nr7ORuytq7Eqza5lMUchZ4t5PT
gJJzhyFriLyg7q+vMhx+gf+5a2gmjwdAPUNn/g0Um9rlhB9lkt7KYv8208KUhh/I27KAc+6XmdfL
7/bubDDCF5gpYz/ke3G639eY9WVuYbIfE3k0+Hljic0fT1mcUdS3YhVuRG/6YJhVNOQOI+xosunN
3vLjYB4CQSzwi+nL6NpU6sa+y2getWgwuto9K1fYGUwPHRd91B7reo6my/XwM536deLmCwEsI5AX
Rka0/6g0rUzw+sVhVadDQKcSQRFvh5cgv3yCU7zEcbWdj8odXPW1y10ALT+LqYTYnpY9mS7fAfXg
0kkiPWc+qTGhGdBuGyQnZ+SYN6qB13+oHpP4BDGzqdTfsBDKadBlkU9WlG6TaZrndensaDLu+dZl
sWF8+FQ2pWIq9MnJHhppFeHsvKVN+8orrgxpg24UEeiHuvYqG37hhF1zqwh5E2rDFnSa/DVyx14d
zinZs9B1SYQ4MQYtiwiuhcb8bsqtU8X63vELwsDcEwpQ5mzyESkeWlecgsiIaaEfFdOz0DQY+Csw
AxiBLdeLhh3rwUmC8zSDyWN7/U0CSzUumdOo8uIoan7KXO/z2uO7AqFWfexyxHaqzgV7HQCMYdbx
XgwIg6GfgPk2Eqgw7UiQHhMi8qSKqhrpvLTGcNS540hKeiKFCLOiyG/4Xm1Rj+c2j8AnwtMdIp2D
k2AwNd/7UKvejUs6tJb0ZzpVx3xFhefCPHUICOIQhbz9GL7Wi74vTivub8yzVyeZ8o7hzvjn2sD+
JRDkStah5ASHviK5UiKSd5Ux4QdrFIhz9s8LYQr1nTvnoxbOah+o5+KAK8r1hhChSoO+bne+ut4j
Vi9FuSmLGiO2xkMaomMY1QTRigvxkCVOSsWJMNBbWsTERIvfmgaml/xcsU9grj4Xr/hGqvX5gHzb
3DQhteMMaJJ8M6E+VzXAdHcNIa0Zakfy8GbAHMra4qwL5Iij8HnkirgXZk3ohnoFBDGzu9XyXDIE
5tS4+56PP5axFmvCyvDlDVm7rrNHhOXf2UgxwbuMD4DmHE8WGBxktz+Ajkqf4QZX9nGLlKdGoI6J
vrK1tDrvdYipfGNT444ww7M2qAeNJMx/PZsuc8w+zHkJ1IOR6xe2R8weiW6wMRZXqYsWNsbObiZ4
O0vTnFRiF9zb9nCz3njgPfAruyM7eyeQyF4R2Y0beCC3JJAkF0iuL6n8NEKHd3yIaxiipIsnS3SZ
e8trFYouWq0SJXOsL+SnXXZgzMDss31EbLmhg3Yrqe1Dbi1sc6Pccj9JBahDt8LTKOiOsolRVMEi
DFTzoO45in1O6Djxl/h4nIq7lrZ/4B0buK1+N5ldvvV28hau8W6KZYcNKXURy1NBI9mqTDhXaEJG
rhvNkKqWyBBqBv0/R09Yojk8/954JtcwnWcgiOT14ttbMUL8AN1aVeOpyFrID/H+1aJqHZoUz5dS
yKoZLsy0MCGvgd15sCveRwWKk3Q7Y0Sz3X+iDu8VPvWpr0j0uFhjzic3XZmoKktDDIgoj/w9uq2A
seP4uBZGeOf/riKGeyy2MzBzmg9Q+ekWhwx11xkSMKGxr5TMw621l6bd1OMUOHehYp7Wqaiz2IUc
8iiGciCPXzLRF1hyAeWiJx4hpY7+eqSslSEurHByQR7dubr/5QetWhdzAlo5QQCP5TQJnYJPSfJK
4PXInEjdE19foqnrdFitUH8HJI8SVZzSVpQ1X0JS4Ci3n/DjRd6DS8uPTY2CBEitQLUkhFPyF319
/JsBuEpd8gypifYA8NTT8hILmVxZHD519PdgJGidi1xoYbaolCcE5H0qmMkOLgHOqC3TTqUFWil8
fFdvXaMuAAwPmKxpVIXQhAodABvkwXz840dzKmhQJfEQ1sUWHD+QwVMyHvs6zMFJJhyjJetjQz3l
i57C6FEIaWHZpa7m3lOyrqT9yFOEkN2ICK8Zgj1fgBPW1ZojKPhxNJuomkJpE+o7OM1pGe2XUY02
hHtChPO5ABIkxRcmOF6CnWynyh0ITa9Fe7VmS+xZ9sqfIjViYwCeLOSwPBRpqLAXeIJaFPLF+Sy1
V3us4z7gCmP5MC1eZOs0aDix7qL0t10O0OqgfqcDT/ZO+AYYsqvSzHbMOCYmasXo1naWv1DQ1mC/
KZWH1mRNxXKdEe/O6uiChRFmF9DYDDeAhUqVt1oXNtOaGKC8Nr8umaqPAWCgHsZe3t7r+0sBZHJg
2jaSPAOwcNq3/cfUee23+VwTEJ/4XIxqyvgL1b0h1aI/lSU1yv0RzR7mwn4thv+ZP+J+/wt0gzzU
dyLFhQUpxbFu2TqUKpsZA6DbLscBPW8pBi7T0lGgibK88Ls4NVHCu3790Lu7jXt+Jx3WQmV41QZQ
i+O42NVKPtDxGRaa6du7l0fblR3OYitna7bOfkGaEs7K932DEm8HgKVjgKAYMtLUfKOiICXv8JdA
ny+XvJrSE4kvROdMao/T0FEmNDnugNXgQGLTSatWKovoHg4e3N11ujfCLdjv30oOBSWdtfm+YHLy
QYydoonMtTDCJ23TMotu06rUjrc+dwV/SZFXflPIwT8JWaSkxquajbD5TU9XR6TjUwtMRZh5aO1X
i011Dy0T0sbcgCnI6exWc93znsLLFL8K6pIs/5cizdhTyZNA4Y5UQDXUE37mGTc8LHae8E6V8Ukd
GLEUN7LGEpbHB7W756jgMFE9shaSIdusZ15yLnMIXQCAzcBWrSzSXFLTgLgzx77csZMCR4KCJseb
BvNKeC8N+zhu3+8aisnNy112UHCh26gJPqXEs4oRxDoxNxKOCdcqIAuKt1mEnPB3gbPbvG8Frgxv
0vtloTdODuO7m+vl2pSR9XmzcvQZT2bWAZML+2jgNKrJ599QHG8op9uJ1YJDf0edVquRTOkQ3tm5
3w8nY8EF7rDME/3wT8H+xvde9SEboyS5MZXkOrTcxujfmU/X4i4pdCnmF5WCDneRu9z+vCY5OFtZ
vRaMlGWqAXU9ZiqfALjXHCk40jZCKSJXJErfsLvpR85ATiq8HV+wnb5iblsbGF+R8RWqeT7XV78v
hYIrFJ3bbGjsPHq+sJwlHli0hYjqmyXFQa6HHiWNZUMfMo5b/x29o3JbTggC6KrzeK2+knXEIzP7
E7PwyakLU+In7Ylby9D76EcE2tr0EDhXIuMIdMmFT35KprShxZQVOQe4+C4TLiXTRXEIroAIDULW
lCDXuGw+2uFSrIXZ40PWRvEn1O2TZ4rFnm+IWpEYFjOuvKMsFMnRVXVD5JYpl1/N71IikOMuISOQ
KJXAcA11LTadF/jOLm0YvnMrAHdUfhzwmmGWg0aQ1EtkxvZNvX607ebEZSMNfp0qE1XM4xjWgtM2
lDEyha2Dw3zjDUjwD5rnGmf8Xk3Z1S95flT6yB5+D+heF52h4PyW2RB492UJVPjAQyLCO7xtIHtB
sepPf3/8tPws611vXVKJtRks3+RTm/UlAlH/K4TZ+gKVSeN2os8sR1AtHVkKbo4/jMw3Wmfz4wFw
Z3Y29v5Ey5wTcLBlU3uQRd2Cq+Cx5gRNXxvoio0doaM86LEghX/KcDIQAWDvN+NMfPcwAHK0Q1hO
jfPzzdsfkWfFxN/+ytYiyEUonEcQUkKokOBiUyVbBSKjTWUuIH0y/hrvCGuSsQ+EAnw0F8Up5gCa
VvkzWX2SHnq8H34P6jrifLXnMu4TTNVSsUGn8MSIZOH2iV5Yv+hxv/56Dt3LuRu8Fza+aLIrZfm/
31TSinu6vXl6K/g6GUwYRL63l9+cG9h6NoluGJHJXqrYGmL+OuYdaoLbQQjNgy2DvFhFRH4+x2m/
RdWKpbS6+ME1tnyUOxur8Jvt2EvNoXFmU75smpH9yfW4mNoH2SV6+VMCBe/TAJwQa+B86axs6a8V
ckOiJEJdocNEll4NbluWhKBqy9iUC+rrfbtiAtz6ETYXjljn8VY56SHpZYgKOp+85oRizvLQmIyS
qJ/tZqQUCjlp27CCFL3AKxRzr1rbrdAbJrnILvPm9SdgOiQWm415WCm2Di2D4+EJc1mgmbDcZcU2
uTl4enf4XZ1j8gh/fnvr1Ss58PpdNLkp6W+uWO5DbRlnXa+H1IG4EUBIj9OorGbeQlWf6gtha9O+
k+wnrAnD/2hLhQNIiRZANWbp4j7JeAF05Np2J1kjB7GrhEPH338A3d4a9TGgzxORa03aP0Viouha
z3hjxgcLPgZCZqstSu3XaZkgDOKfm58wUH+F1L1GjGOuSuldF3lbCoX9d4gpk3YInS9G2zg7sIW1
P64WB0FAV5KELc7g61aw7S4DZ6u9Z8OjXgQDj6mxTr8gfxoVMBBtUovdgNHIweXOrunp0uxMdOZl
Hn+imrB7Uy6jl7kzaxiwol8jT4E4+CApAoKuFbrSkCsNqpP2lKBDyrSqorRquoLxoOhhgSVd/Ulc
rXOHESoaB37IEB7+Qmh9F8KIHqtdYxvJGLveyC4sU9ynfSF/VG98D9LRgLS3NdM4J+W33ke/GWRl
49RiYjBRyVuBdrTlwOKsGzH/6lPsSSzrGKuIh3EXmQtsmrfNulkC+Avy6CDWOLynvPWKP1OIT4Xh
OlnL5iEDKmSozwtcdQrsX90EL7jrEE+6gQ0xWLHhBJlWtCoimtssrd3csaNCiGqug83YJMEHeWwM
JZS2H00HMB6XC38gVL40LhfDgLbwHF6ytsw7955ORY06yEm//RyOqHjS0NzRXAWa2pP4YMPS9VNw
agPU64P1ao8P3J4gmoLM4GctYLzWOfEetNLMmMv8Q58qGgdcJ+V0bbXJOD6Y6kuUdaS2hVZ6+60g
c9RQalsJqcTPXoInHFEce9i6mFIe1AIQubvaNfjUfzWY+nrZF7sYhalbivZehNTRyF1SyZBdmbHL
m5VomngpCVwHEOe7lbAFBZXTufbH5+HGkLG/sDBTLqrO+a5t6lVCZ1vDeu+LgdCaarh0DoZmgUwO
TIcFXqGhLBei+B6/4YA/LKGBUcdHFwcWbSzJz2eeoc6UQmM45UwGPoIkAPnbR6PaGTgXafF6qBqf
jFyZ7ZpWVeMme5IVIOPFgqikyE452fQMnauYiQju5WmVC6BjdX+O0NWwfjWP6x5Ie6vQBWG6i1v1
YYDmmMFbHsbDmvbow5vmC2QVwlCVXdwpqNAxBj1GOERVeIzOASxEaM/bpSnXmRtl86V3OA5ateNI
72htk4v4WikXrsAvHR0UhR1jS1RsftbFq4cclHdnmU4tAkli1oAUiva3cP5iidClautfrBXMHHyN
Ppv4QVDwng2prRT94dZhnfKRUI8PIuLKQCrZ5lN+24m+UCmJf0eH/deEbbtlUcD5wf8sjgGmuses
7qTitYcQpeafty0y7WVRlRfntrki0agDZhmCJTQwjRxMQ6jdMQPSx6DEmTZtZHveyHtRCxyysu8m
oB7M1znC9cfaB4ycJzEQDgOdHgHdqn2qif/7vYb3g5L14ZLotRD3WGOnwMgK/vs49v8Cc3qK5bjg
3/B3+uyO0YW2byIx/k7XVZ6N59E6hw67DiNiosJsCRpaRsSNpRsjQX+F00NHDQqkX13kbURDy6v5
N5dHFLIbYMW7m9cyc/HGTxfh1oEsD++gHZVlpr16SrTM+i/IywkvceDwwoi4DPQe/58ZAY6xnrTf
tn9xeSu2YZeYzO613kjpRFZs+IPe2Ni0q9VleaJ3p06NTO9apv+/RU64547+jQ6JWWJpz7VgrkbO
3AbLfvjeMvzYdTDb327FiNr3pR9dLsSKRE/8vf8bk+k256OXqd2OKgcRT7p47ULkrcFRD9ub1sgR
kkv2e8aNBziqtMFwAubkHXwMlh6ToVWdMLI5Nnhes3wJGgyFXUv3jZnRL9QJ5QnQzzJHx+GKMQRH
46oIYfvUHEDPVtDPxQvLkOzG5nkSmBUviUppQ/Yk4H6uWW45a7uYuLvu3Wwf3yz4X42iOORUrIOj
AgTtLA/G+aa6VCELr41MeFTQWQL0fbuYDjMmG3cfI3Lv/AGM35+H1tj1OIXAfRfj/K2PYov4pARD
2VK2pzFDZQRo3Q5ZA72xofWI5kJIrjf83Hq87ap9eDaWnmUTErwlzUAOtDntU8zmcb9mv7A9BP9Z
pmM9yxY240mfBftmDKTvdK97uVdF3rVMjvBMhEcnq30fc7MG1DE9MpBlHeFVjMk45cQstgIqY/qF
Z4TezeiBbW0+2YpbkNBNPXynsUgrhwMINYMdVlsO6lOli8Y3nPHWKZY0zQStErpcM5Qot+fZrCVH
iWdjGNm0q30/xX01TuRkR8mO5j/bTux44p3U9MONlLLwG7ZjPxH7g6HOaEkwOKIuYQOkluLJczlh
piXPyQ4t+smRHUM0FybLJYbpEScQrww0SXf/hadT3PYDX3mo1VW9ii5CnOqiSV8hO7WmUsaGOcbq
p1CH7gfVOz1bYs0+k6qyf6cks1KkYpqaXBMQVwvNdatmCUXxtgQLqBhhnAQzJide+Q5lpE79+WyB
pqp6ETAZRnB2VFpqqe3T9tngkJYOB4tMVYcwZYDlHPbR2uIx3kE6m0NP9jKRIxOzfiqPuXvckTtv
SERcYvyeOs/6B3ha42ZNzx0/+h8XGuUBooH63vrBNrQrNze1dFNzINGwCyqluslt+YC66PZ+bqgG
yvUzBDBkmd0NawtHZFjI/mZmr+FLicA7gZAQ8oKlkWO+Res3LmO3SMeB/aBT8Q1czpSp80fQDvDN
Lt8ompITaen+tfu87lBXOH3Ow3UPt9a4jEAa/ewY9VbwPxtKXcSeV5grn6CfzxXNOUXFDZQDad6i
bT5GgRyYW/R0/tmb1NQL81HSnr2xjWRNvfZ2oaDWvcyCqz2HS5moRZaVfMOMxTlQn0iSfbzwFm39
pQv98Fdh43jGy1rDmDsgspZ5DpAc21kl18TK8R4+Gpk0TKNRHDyj7pIKNAEG7cYbmUghLCCBmUH9
HXFo8xTAjVqJrw0oBEcx8cI4UuUuF0o65dUgGaPDtyHYY5eCq9u28M9IHQdppUe5wHsMzwgkEinj
sLTeN8/F3FxfOGnPEwtZe3n9ROPI3nTHqeMTsWDMdMTQdfmXHl/EfIDEYJ+9wg8/uw49vrR1Y8oN
nr4m3ziTgmGDYU+4rJ5PvocI33foP5uJPEd7ZxV6hUUmYD9RONfylmRUo3joteWiqO4laCavhoWH
UizabQgqTNr38SNAT+2USXgFzZmadgqX7gbOKRa6xPjDAw+3n7qnQLN1NCGhjgIt3U3o8nUuy85s
ddULcUboOWiNvEgZN8H53Ojzxs1eoCoRnZ5xPcrDMfuyNvNfoFtKmDvUOKmQsYlSUZ+FkuQYSGiB
v3Brfb+keAAwsvwoEMQubvdnJUWr/7ZUR1rZ3JyYGRyZFlt31IG9j+ySfxAkl3h4CohPCdjUwac4
ESt0SJsxCNwWYhZsjklHZlHoK8vWsdU5DAhs8udvg25bML5RmVDwz5SG+W9KVtFE/gVyjK61z6Lw
UodU8mKjXkRGbYYN8SYtHSQ+RuFkh2o74/ZpE8mcbhj+22Hw9kwwbcvE7nml/fHXOOGMEfCTpZ30
psLNRdRvClLfT5EuMpx2u7gvD71ayxo02dr+IbbeNwzd7zSgAfAmmSHlQ3yZsOENlRlyBBzkGNwR
uXB0WvGFS7EIjCdn2xu/KH1IBAYoxbW7Sh/91iMsLenUCCO0dycc0r9cgyfWb0S2jPFLaBE3H13c
keMlBECuNF2r38uOYRcEd8KKhQguGdmWpM/8VbzZAsDyQ6T8CRuUrxhditHysbTGOx571bXKGR45
UyTHbFyGaxbpFDkA7Rq2YxDZXMljB+VMJHF5MGL/Y/M+srQVnSQragOLp/EzzKtiKbCixay8EIwJ
tWsTr3QdI+V2cohSSkwr2Uhs64PQGu0VtDGwOOJcw93wnduTyWwjbu4f/aDNExA+tin/phyDVRWN
jO6dKdO1xi43feRK/vSsVm0LDJbDD1bIhU2j3wxS79oq5ARW8NAC1cmw2dz9GwKmwUju8Vw4qL4A
eAul+VyL4INu5UzoeoeCqug1Yq7J1nexEpYCpH94roXfRmA9ACg43JeCkhr0smHRAWdZwLGq5IzM
Xmt4bX7M0G6PpUo4sOOs6o1nvFRkmiKBce5qquKUolKZNKYeM/UmSNrhrX0bwjVJImhpJpGxdtSu
/qDXR6EZnNiNZxtElwLEt5meidtHwRuHcoI5zXDAzllJ+Fnyr006Ug+DH6auu3ng5DG0MLiko64P
OqJ/dSJmAb42doxbdChls11mdwxDwFD0L5NPAViMdG8LqdZd9cByimbIGdHkTNBCa7sunGkj6JV2
2YkfC/CcpKMVzFFofPLJDdeSNQA/e2DhlO062gP68TMjWJxFGWB/yk8VMDuURF0z56hWLu5F1h0n
cjiF5KkzTpwitDbwhKNkUjYF3g+/snvSh2LdCd47e3i/GHjnc/6DYnXYD2TKGJE7deR9BTcMKRK2
h0hPftPMav6qCmyPhqbkWVdfB04sUzCIn/CY8t+u+G0+ks+0BZ/F9XUi1LOJ64HeXO0L9pfpp9ZO
xF8Na2GChwa9BxnTOPT7oWqf46KL/J13hvd5LGHKFNcHbwo0ccFzakeStCvncqLHKQtBqBPkfPf2
gHwPfEo7d3nr6TzHKnRE7bLmUA2fs0zLVtoaa99BTjsU0pgqAwi2hi+eBxFDmMsOjJG3XNryqKcb
k0UgdrR98a4hy0O2g3mNJ7o4osXyMHftXLnMSkwwHBNVYyXMxpKfJ3fz6Opl00pzp2LeQrl27y/X
qG8XLjg6OfgxxX/nb2UUSl5HYIX47GtuScXGX6rxn+LB3c6aT1uTI8W6WubnGrhkpD01Q/KDWE6k
2DtYUBpFVyLKdnNLf6Q/zGY7+6p2P3uybY8NmewIJJ5W8Pp8QhJigwpfMzlcezheM3k8Jp83irtC
ea3qsSyebGPnOU1rv/dTUypahYWw40MgwRLHZJv/JwaGz9MxnSyJylbBWJsZ8CmLA8/ovnvLs011
f2hmCdEv116sM9z3hq1l+FZDeuOTS10D3bEJ8auREVkKn1rOq7N6VPKxx9nZAhfz47Gs6JKyCWrV
vmkiztLKRjZcHprPjk7wmM5b1HP/+tNpZ/QbpNs11cXDKtExTFrREakuIcLZ4diGr+dZp1oAjPqK
AeIeUdHIScsvPr9ce+FPIT7Bc8ATKWHNBsaRijodM2TvL8p0FQJKF8D7gFLGFD2V0GpCJlpAA8yV
8KIxofaawRTV0MpDe8IHCzkL7KwZrJ5VNv8juZbhvfTDd+vfTHqYAssFTJqn7cNVGrNuxJ9W8ku6
LzUfZOOQdYw5eUpMTTbhNFZFGGL7XGzXn6yxzGSpWbAzb4mIKF0JvOgg04j6aEeHmqV4X83CPXNq
dVEg01qQcWhpYXhvvv5SKITWupf5J9OyRJOxPO1Hr3GIbtZxRdwdUjT0MPU26keXLw/V4dVCJHF2
0cP9TjyGMBDMNUztMgJHZPDqhBbj1u9KPl2d4gCkUBZQuFL8W6rAkfpOfzHEQE1ot7cCDkKrg7sU
ESkDMkNSYwnkRZ9KypW9eo9iv4y16VJqBv5x2Vr6Lm/ETUe0LP4Ez6rubNStzD9kOCNPJS9m0PWV
1j7jLuwESffsY9BO1pfgvLY13yI1J1/JOjsFZwkbvUir+RmMOvR+U1g6lxmV+TxZDEC+QNP21rxd
utEdnppJX7xfIMLmGqtU2jSSkSc73DPUYRSDDfLEHPailvNKoKlYjigCGFPAi0JbhFTR+/lCv5Ir
m7usU5U2TW68QUHUSrBe5Af7rVTRUYPHQNjZmaHYDUmeowNi8+pBIs2wUyJHl5rsw5eHMUi6floD
h2V/EL8UPtmiaz0DxgTs5Ewi/iEPsniN5bmm6rdC0r8Qp6iPdBRrI3b8seD12R+RUaQhkOtMvR71
3lQs2xBs448kU+0Ab131TAiDAQud7mXIoK593CJUiaKQiksYyKGsZiONfTshV/nUNi2MZL6EOyaW
mKZf8xukc/dCzUEfXnmkN11PyKgYQZ6xzwD7cFyK+ku011XOC9ZGO13dkiTR5mkC+jPH5OUqA5ZX
NlXv7pMAkUmAkeZW1tGYM+j1e6SNmS8eXiSRX8IWiXwc7Q79xBD9Opk6Id9j9wcVDEJSqeEuyHdJ
Px2CSWETElD45xCpRD5yFzyV/vKDCMe0zvk3MzsG0/XpfgHC3LF5gJMUa/FhspY3lNCeDwDxm4W+
uAYmWpJEyQ32VFKtIcyx7CQd2u60qUMBP6GmOSNlJtxM4XY6/Pqh5tZjC447MsAhNswl7bT+7Qf2
jrSI1zQmW3y2S3WoNrD9zEjNVuymlp2rJhC4OIELBzjJ3itkAM4ZQPD4ev24h7w7xVtZHTcQ4sFT
LCSUdHpghVVixcJaL7vAkk4zalM+io1PI+Zrui6tEYihOk8zv23HulEAok4LTlst4x1zROIpltj2
FFhpsYVCzhM0YbkZlyxCCH0L8KpTfsUKk1QVRNy2rgocRl/fGr651wYteufvmmTTn3T37gUJpeZP
xmOKwvownBPmif40J9e8oXlgrEWJftjLc7sjbwfgsYyenJwfVyAIn6JiJHDktn9n3ngnMu6j0Rir
uJnIszdILaKGqekMEpmEMSrvzEj3nyDlrz8YcY8hZZjaM1wT8Aa5W0WuPfUrL54KZ+UbDorvq7HF
Gcz3y6CdhKM/O68lp4oewxJPo2DJ7iTduE2Xo00piHkW8ZyVYw6H9F9o41LYYMDMnfd6U7133rk/
Urz1UJ/GJ4iTe9xCuAn5ydU766WS0PG15tXCSPNd4QIWH1+YxiQlQEZ2fHzR7xWlttRS0zDXrKkb
JJiY4otrQz+hu0AGuSBt2aN99tYjl1kNNzWcIaSJtoZfIQVy17zLazp8XiUfw5kJi1KuNW6GO7XD
CZYLt3tUgVLHdE2kuzTdglkWib2r94w4xTQH/dJKVP81JIzPPuCiFeIEMKW/cECqa7anNsNKdeLT
4X3MwN6IWTHHULwJPHnKOkknWGyfKvzs/VLr4XL29HebuOWtFtJXtrXOjSqHYczX43WBAZoHCqXj
GTUerbN8FVjU3kCB2xCw1LxDuSPszad6zbYfBc6rAnWRBjqFtCKS9aMsYNbwl+VH7Fm4BrHHXNxL
JGkgcZxreWCWWzhhZ2R+3hxhp0zkI0j3oeUsE24QxUqPHm5p/y+4YhwHkPUllSOv2b3NCeuPcxGX
nsxrVd0PLFRRraGX60FhYs7Hb6A6sVbI9DQaQI8Pd9FaBQsjuvNApnWc/wb5HbYG4wYhawBlMG8G
2v2uVme8/sR7sTxxlkON9qr5y0bVBEtDxqzvRBYVI7Z0i7rMs87zn7JbbyoYZkjunTjeK9ssPW4A
u67y36tNN7tmgi0/QNA2k2T2s2gkz+jmidERxSUuXrPNjWfsUdarezuwE8pTFQyPaYDzRoalb8kq
pGhA9kEQSOAFg+Us6YUwGB/H887Pb4k58QqSdEUYiPpOTHCjhOXS7nUKhJgakceCEpeaUoPxmoQJ
m3wMpZZHcn7ed/+5fgl4sP+F62JU/N0WXlXea+YdJg3YLvveLOW/96FKSXzdNTl27UwWKrZTyvtI
AFFWZafOe9YXi/VEJkLDiGVwc05yjDg9jb4dvU+5BqxfVzXk8G+nm3k1UpjEb2hJ6PP1zfnD9k/S
1V4IE4ebjMPT7dzWfy7bPIgKn1dr3ZfYvOKx+2CCYzwGG5OW6n06oQwdaqPX3pKF3G7U3dhon0Yd
VLrYX/oHMtSV0RNjzYSgSa+n9BVUrlCtKPQuZauqV1ynedbwMNF6Srbj2aG+rVQG5+8qqvhVf+ND
L1/DjAhuVTAZ0HuIHWwnbaDWv4DegVGYy6klZu5vaGORXGwrZ7iysgyHxlXrk0Efy+thibRvPl7x
Utwp9XfY3zRM2rVhHurAWbpe+js+iAXmfz542yKmV8KMEwyHn8B48Kzp//mkm2nT51yBo5KjjdhF
xIAx8XhglaNzt0/88AF4yO+kqqOPNHZjG4H6bX+QbmnfT5BruYdvY+ICnFqwwv2EGC36bqRUS9fC
fJrBJ6dwn/Hi1cSkqZ6ZgrlYk9udQdUGVbyp+TpWp09bMqS1UTwldCgCybeBkHkHqrX04iU3kWCI
8qEXBP69RWQGzqrGmB4neOvR3sTBZ0owU/Mv/0upeeS1/o3y7rzcM89+MvGsKc6oKfkYv9qTTIVG
qmS6MFLaXFX8cykqPVdODQSOcnOVoEDn0n+qLAMMVavkVCRbGIGyBW3Ky9cHK4a78pCzM6Ko7xIr
IW2KHOpZjBKASkmRKRJ5KJwzrn1yME1Q+ThWouTt/BLhAANIBDVVt+gLF4IcHvwb1LbrXYazsJRt
5lMoTI7eX1X22Ued8vH6Hyb/RCedsjrmadVGQ0AXfyWdAWdhkNaT7OqXLMatL2vCRKUFGhvKVwLP
0y+S3ylbFbtHtxTyLD/R917PkwSVGejqR5V60Z0A8IQTuJsqEEDj/qlNGtrRg4T0UsKtR6RWuC7o
wxpSh+EqqU/ZiHGmg7YzGRzFjRVO6hZQ8+Fn3Illz0UgK3WR36yEpV66HCs01LOwfyjPbpoHuoa+
abeuR+IZLwJKRk2hKSOxqAg+cWsbsaitKc12sjTx+5hK8zTHft6SfgNfSnlLm6fVaY6HvbZ9mYHW
4+SMuGCLQ66Hb99xUnirrumsyz95ymZ/RnF2PealTwbe8rb8E1C4lGXZP1k1FHs9fDLm6WafpSJU
/tWz0X1F2g6VyuwsXUsgsm8qZPOg7R1NhPKNQc4Y1752XQrwAgYOV79D3l8FD33WdXNrLRNt43Jx
IAECThr1dHsAlK0iinnWYwSwWDfK/K9Dw29vWGpGy8TTTO2YNlLKv/uJoXOrWN+CVu3FSErBAMgk
9660EzLI+1Qw4+6x/3e+RzzriNmCcg6aAEo3u9rkHAaCDHfpn2z8tluEtO84nhvLpqtdreaKdkym
3Ar8ciYq+7qWK7k4SOKoZHDKWrj3uMNp4npLA1xKJgYR/SccdOkkUzo9ome60MkWYu9rLFxF9A7+
+F3t7KS3eHFYljoWKG8aCUUxRueUKwpIf7QF0NsGBp38R7GgXkuad+S+RVGAZEHKfX6/1EoX87bN
Ei15nXATPFjo+vb9RcbudrWoJ3InrhbB14RpUNiRBWob3Mqp0e8enX4poDJSGSgTlxA3bp66Om4Z
N12qmzEVY9HB/yTMHQmeu5u6pp4sdkiDo9lvDbsJPF6I9g1hoy+JNdKwYRGgTAn9/ycP6B/Iec+c
0sics30qTFXEydIT8KSixWVSO5rfTZ8QggaYDZQAd918blAOmEl0L5s7PyxKiev3+N10KFQiahnO
ZC8d5gVFfoQ/bnQz2Sq2ySQGsDkEiBFtxzltV42XFId3VoJBrgYRalIUwBGiPcxWZ9TDIokIOvDN
U/kxcDW+SprgVGlO4NnyrdcluEhnsg3Chup9UooxStb/EQGNeaiqqSePygartWnEnmz772iScnYE
+V/XjhNnyyNtctZ7ktMg7Kb70UG8x2oJBJcDNiCZ4GrNxeS9m7sIaDAmlQd0ubjmOXybs+5Kmn9U
YY8SwpMS37B/Q+QlzvtNCvGoAejxABUF9rQ/sPFuAWz+DRPXCNe9Hy1Ccj2ef3IWQcWHHklDrjEa
7XcpVT5owDnGK2LCgkDAx2/ZsQdVYCV5Waq2codnUTzBr2/B6RaI9nA6dOuKCBo+H0oq88MJf1+x
hEGMVuu3JXHWpclYK1hD5Nkx2GmEVIXYzI3I7uoFCnmiiAl0YrWfQfuJXBT/FYCSQfSXNjZDHdEm
qicKsiAOV46nS1KSFZcn8ij5tJ+8ZOU8jEkmlvQy7EplCApCR2FQ51xw7xcA4hVnsMcVzwVnnoLD
v8aFMrKZpp56q1K89bO2nBt2c+8geMAhpkOY3n2gaxtPUlK+IhqOqoluimogGPH7iqeXQlqnP+Xa
zj8xZN+fmRwbLYFLJrfKTNPnoSM9fDBv5dQNrVbTb+7+CFKRB5K/wH5EhM0rmtPqmoM+tRHbf7Yd
uSJ8wxpduv6Zm23gyyugJQSOmezF9bS74EIWSVjSM09KY86jfykJ969+kkGyzdx2vdEQZrtY50+D
7z4jbwACgMGHdmkXMZwHhR/e1yIARKhSdMdz6akD2DaImIJKmuPS4vUNeSyZ2Yq7Ojj/yZFxKdD6
GF7FAjIvPogjNkVh2Iv+TJxUZieYP/FD5pbQiRdziin1w8YSCG0X0lHmZe2SAB8XbG6E0TA7++KF
vC7mQu52KxqLLmlPop57QA6mi8Banze/7UvwVSznl1Um2MWHhLxBUYHvbzv4pHEDVZOKzKb8v8Jj
M3784kCs7fz0NEFHJhj1HMTgnbByCf95PQ586pkzD9Z+aguSspf9Zlf/637hhmyKbIU66ufqucPK
GB2R1B560dZev+6ESJe1lWHFpwUOSrseyKkunNwTZ6P5NGuFqrHZKV6BHjsDWeQLrh13ydg6TozF
cAEKGrgyIvB6MH+JipMWkd8GIo+RY4sO1ZrO+XIlxDxs9TAIpY6YhM+FG5KTqZpxY+06U9D77si4
m0USVCGKCj2LjglbGw39ysIN5nHdMRE/49WB59emfCAoMrNdAvdT8Ez4zbNoplTpd9H/s2Q841JR
RNOzp68EsOcaeFhZuXm+n/7/4yRkiaavVFc9+dIAwmuUgh4SDQVJ0/eevvBoUgBe4TaFtaxm3ISB
A+x5yLVjyCs+vpixcghbry6+qYM/wegvrFFr7UAaOs1lNv3qzkwkBo2VUhrIR/KZYPiAQyqPwJtQ
llspse4THXno84Pj9N0QqfAZq9KRbjUT6ixNCra0bccrqx2suKwnyy/dqjLDBNCjbo80y0kWB+0d
jre5zmdoFI7tne4tvLCigPsNAIljF+ounRcY5mnvULQXdn/Xp5wK5/Oug+oVUyGmIopvQ2C2Kyrl
m8tCOfV9OHXFPRjsrD9TvYpK35SazGGYDVgAHarOHo9LFd16r28mHrrKdIeYUQ7fpWvfBv8Y9yUY
8j3FHr9N99kxyYPlg8jiBzxAHXNXfbq5V7OtnmySj7PVk3rj1c7dd8zYIq+WCAI3q1sk8CAP3xKf
e0fPagZiwlsXpKRLgMAB+TFN4h1/mOWeO1cvaBsAycAt1knaq4dqrR4GCHt4BpTjtO4Nqm+hI2pq
buNuAxPi1Z+zOVfezjpPnaeUJPFDNI1ts+yN2/nQqubWjGJGwUQ/rpGlGZ8+K0WEpZ2aUfbWTZqF
AvKJtdd04m8Iv5KNUE/9PThVnM1wuaT9ZMO5+PqkrXs4YGGuw5xW5AoViilm9hrOQ0+A7TDIkLQt
R/5Rabv07alHgyC94RTnqTGArN+hrm2IqJWcZAcqOv/71i+sK/p1dsgcpI4/8UA5WEjFnvJBq3YP
rHZt1f0Wc+XGbUwEjKUykMn+0NogntG22ksmJ2W551E96u8X1PU/Op95cO7JC89AwOUOux6fNEJl
drRw9wJVuz96sa05iCD9F0yzVV1FjjEz+MgjtR0/WIpg+VPgWVuxUMtrtwyiZih0NDBWuaWrFJPh
EUnpnAX+Vp4mSS70WWkQs0f1giI2t66JtFEfM7UxSdRKLcliwfjNtbD97fRDwpwoPvinb/0tVy2c
MFjiGIEYqiKkxOnOkAjZxQBrWXrGRZ8VUwYTEnOagufc9UcUyxq5ICkUBbCJdhVTzJeFfryZIpw2
xs7gsSmPIgL0yy3A9CI3Ne/UtWnyo2A3Dr40R3uuNEeNwq6DSDhCvWZpB5XHWH1ub6hwt7qfVKRv
rWAnwvVBfjNj3563AyefzuDxUjVZ0/DlsskPSgAzph1Hdb7WbcPLoHp50MXBxhQzHNCmmyDB3DGG
duPDISoE5vUXNOLE1NYLhB9XRI71EEjL8jORI6iovKaLHHRmLj0bGpNpG86yFPYkaQuAwb068dOY
qq6TwYKJlalszNRLQq337L69iShTc2ubQtOV0XYYGReXg/vABJe/FqpAxNn4asYRk4c8rfFHK36f
ns2iq7jkqI47s6tpdy/6JHdVjVfLYooUUHhOHHek5coS1rw0nd+XJgyVVyh5DflOT18jzoYsm2CH
3U7n0HCKBte8nMGKyQIEjJHlHBAlxSjzCawgQybDv7/Vv2IxXkyM6wv0wD8LfzrpNv2GfL95m75V
ev4y2RVR3HmN0lL7SOjA1sDEgFnH/g4U9WhSKaxP4gNzdotxAC/3pxXl+80D68EAIq+Xhwg7B+UM
si7Ko7M/AcTltyUi39IrlQ8002dwKsiFuWiXGhCRXBmK+DDkqiSrMvzwI6lxq/CPa9mDyYwExMIl
M10ip5N1gBXhOWKRLDLbaDjg+CAfYqHjB60jFZHDEmRBiDV9ZtTS/FSYg5RRcAK2+5gwhO9j7xv4
gLr4OB5dUWcJQBlHWh2mgBYfAN8CLdGUwYw+XszsiAvhWpkH5dWohMxmcID+gMKloZS3ClHOA3G9
+ARmJofUsG3Nqgf4uv3QXJ17pkRoBp64i8k6K4Q5qKskefnnniK1DpGNAD1qkHBbOB3AG8q+/7UC
dkV0oTEl1Id7NUzwz1ZXMG3acYY3IX90GBXhXnoJgRnb4t4Y/+AMnRssocAHjZ9vLVEy3PV9d8Ks
jOTnMWb5I4iIGgwImZ/4e7713k2twh2eD0tR2d4NE1TFs6XPHlPhB6hWvKlTFHhrWIWYCm9bhB81
dv8m7GyB62lmNw7NLC/o9MDrRUcSO7oa4uwtDjJQ5Eo1iqJdUDgRpQkI2CG94k5JaV9fhV4n0c1l
rZTlWBcc+AEioXX/GeMJteLbAU/Rj3iHSzJjTa5VoPxDhbTQFmfNFT3Ms40ws2KdZEYAz7LKkdO7
g18UA17Zy+vUikcV1cTk/S1tyrc5mjE81t/bKbzVGjFmQL6y4C9qfO2N9zqgbRB16l21o544PDk5
rltstS4E6btI7loRcLZBYgKFumOlMzZElZqYQyryVR9skB9xG0t8zeovQVrJIb/zsWgYqFDyU5hs
BETxrcJewgSZECWkYLahFr8Sq0YznsdzwxuecPsaeE/myASqxEGTX5gHOOFLPYMhc/g8LxaEXeBk
jQMRJvsO91W5JggC4j00DzFxTWXoW7uccjse9Y9ZlOfproISL6n5XDZ2VnZ69082NN6o6PPk35ru
UWaM78Brr85zwI18HG98AzNf7S9Ubhi4rbIVhJ2XjdKN+mMbdFEvhvI2vFpKLTm04tdPVAeEPYln
zEStjNi/U1uvUED3FBXqIWv60hABdUEHSkpL/bh2Tz5G/lZx0X3HHsXQOMqj6qTottkWLoCIaLjw
BsLctqpuROGvFBwXvX/ddm0YIAim5MUMW5S9EajsgTB9dNBeDFSpyZUEmdFl0v/naoYe+mVRS2Xu
6nM8FwTmAWxq1Am3ZdbzM8SZvJxprk/XUR5GFeX/BnbJBo0VxzzUeMuT9PqZEM2OpxNSxM50pSg2
NCM1S3WU7MgGBlIk7bPJEEPVJct1B0EGA6fKkB7las0J2Y+DaXZ1HN6vQqLBSLrNjKXozJ4SHCUL
A39a11W4QgPkLGp97QrmkK7+LRh5MS1S5o9pJaDdD1AZaNPcYPDOnQaeCcL1pZQ6Cc8tFu5JLFlQ
D0piy9jSdixf42HycjrzeZmOIJ7+yZkfJdbr4jt8tT5MVIhkuQURV2qxbPAMJCvRv4OYac9SGcBB
bCfMXevBEizOLMdUu4peQYWOgOyn/RUH9ZSdzOvkTH3Uj3/AqSx63thNPuKVdtiHnET75qNIIQPu
lGdGi4fCh1P9aLMn3yoraufWaC339bvgNxfiST7lozM7KA+wMlm0vyxbnXc+Gu7D1Jm9zixG9NrZ
4BLZSA+m4P+suGPR8vQxZLOWs8JetF4RJIxtH9XbliqPgOeen0z0dwCfAw6ZWoz6D7FOUZOsbT5t
1oMHsv/F1Pt0B61QshXV9sr7vKYGskDViMmhrDVsGWMNCwTJ0v0E28DYth9+16X5SXSaNdtQnF/4
SZoQgRg7mfjYuc//j/CZs2UHGrTgz9KJ7VJoCvQLkuVLN+FXpl/2iRmMdiJHjIeeOiGUif+d7DH6
4mHxHlhE5KJXa07glPetjqjUfUxQz+cVwTI3Z+G9oH4X22SnNjRosXVg+M+b3zohnarZLK1qa0dP
gsUGQlS997kHaQscvTJgjAlrhNM92AA6c61QD3gqwfTang0RBEQ1aDiMJbxalWOT25uKzN4oF6hG
i17Ju5CrP543/qKsEQV/a1PYaKK6REOafua3uajZJDyQvkoyzGj5jtAWOpVdndjAKGBGClxMR0ML
WgT9oNKAMSfZym5tjvAYE0eU1WfpuQBTpufNHfT0erxydhWeZ/xaPQx1diFiYvUxlSAe4FLsrxnm
cz+KemcSrqGcOCEjL8akD4fXEyObLyd6F7SYGUlS58IvrvehCHMnLK5rYGDQVUF5zAeESoh2pdKr
7cF+jqnPZdWn2qkLeyomNKwFeO9e1gilJSuTFm/0OxXeZlVEl+APA1rFc/zSJIlO9hwrkrAVhTJ/
KhXnDp1C9fh07kFkrVKTM0rrLgVNJZ2Vr0eq3R3FakOL436IuxIWJRCBboNuW4Nsrp8lr0DxjvIn
jNzdWZDE/0E1OCOaR7tfRUmd6e0SKmqdoO9tmyrC+Jdx0UNT8mZBjQX7XAdMzcLMa5R23ksy4nW9
rMTbGmHk6NAPsPsc317PBgnccLl4ivW11zRm/KYJCgAZaejWv+eIdPOrUQ0X/awWk+OFGofNmbai
AC0kKiBQel4cURNRTNThRjuoEwcZJ/sV5yOD0xYoXmjPWMHG59lrXmZmJsf/9DiX58ULCi1KVX6w
ojf5rlvIQxiRygpzt0hq+E8OTKsy/JO/leqdnuR8H04Op/otMLV6RoykNciF/zaU183/Fd78zJzL
F8o16c+0Mo4QUbM/5HueOh2cZqVq8nrZRrxz4K92Q9r9UN9ZnPiiC1+Sw33bBG6E0igGcp9Cmi1C
oNCNAHHhgQlAI9g4GPm4lnOUGfrts/7gSpvuHwhaQv16m7PdxUby1Gh1Eqrcopho99VCDUAToDW4
rlDTU2RMiU62RI2gDfI6cpJeUUnwKVsRK3hXaG0tHpLPtoz0U2MdlunDG23EV4Saal2ybG/N8Wf9
tXvswk7qmTE5S2tIZAGB8pEKhdpP/o+cwC+j4EYWRqNfmMBU+jGqgCvT+NU1T2bfoPRsTvSn1Udd
EZRjLYQ3N+h4i2IRpx5KHwawzsRiplhItnNkktpxRv0NArvMp8Sh1Qv4H0Qor7XTrtWSmty++u/k
d0NF/5IDnH+LlWRhdyUPVq3W0TgtAadNQgL6ZKQ9yPlFslJJ2vxZvDBLdgWC77ODM2U3ZmOaqU2C
SiCMRvOJYxYcmD9V5BuErX28DNYw7JqBUfXAqNASQNkmK4E6JKIwP78TuieQWur6VRbma3aTO+c6
seXVIIi04aheDznIsD4CKn4tluIGZ9ziXGoDmV24sNwLjfmaX9yEmkZdMDjJxFXbt29suRHEH6nY
Y4IeDUl1l5tXR89rWrchxfKEt/rsLog/XG02FqlkwEASCBUGjXdEcmliJm9TpVpbJUP+HND+Hefx
DtBkCcmGi+UqAPD462mR/iDCBZZeEDQ0LfUQ2hgS5DgdtoAeoezpLVuPgM+w1GmN7iKbcAMK+ApL
PbD0TJG0Ou73y10B0ZpmpVzZmnxypkCS+3g3k53wGQjkmLumgQ6FFszrnawHEF37kNCYexdtwHSI
S68ACTGmUiDo376ldnMbBtEVtp6v8LGgATJaF5OiDT3z2gF9i3OLIxdFLH5mR0O0g4XNIe0BOI6b
S58WlLdav+twgH7ZQ/rt0PPwMmxM+EC0EogTxlgAMvXVnamNKie1TK246+wN5arNHn70Gm/DrMfZ
lXk6eTXFZ4pEiqPTDfiengMsmcWcVipGkPxAf3qB3UTnrSgV3r4n2D6Nk4iHmJ9snauzb75UU1JF
a/hh2f7CB4aQSgkpG7DqLmYbkLD4brnQ8X+Y5DgRM0mcZ1+fs5rR1F8r4E7SeEDvX2z9wUWFVpQ4
FwAmBRF/h85njhb/jfywnV+DxmLPOg95Hwt/rrNs0bExXuLNAV2+qp2bHL+I+dc0ROvTkMwMsgnj
2Echu1QN9GWj8BHcVWYym1QHnuI+iLDIR7BejDfFH8mhATqpb1oV0O/TSQ85GQqIafp1pEcBfBOz
Qq0GimzxvzsxPikQFqNypX56BjS5l6InkD1kADs0C8Tb+91ry1e60cqCa4zsHUmy+6VhkFbE/HNj
MLwOFh+jNJVelp0CM+TxJTURDSXBiWkxkhLTpa8u8kSJOAqe5kT6SLQF64sLB6nUyGePGj3vz3wx
T/csLiumXEjsNDWAsIxnl4wGZAkhOtC1gwG2lPgS6qh/vOfppeZw9HS0uJrR1q31Zgee18ekomxo
jczXHIMKohWdpJ6HIGxbpkIDropMwfvQMQYTxQfpwCgN259/DVSaK4VIMhd3wTZsPmizT1LfWiWg
L/Ju4WjYAF+nMZdv9ucnN6+yKw0k5e2WlYncqjlfMsS5B82YYZRS043XVUTmLXYPor18Fz9vGgxc
1iQ/gd1XmxMmEHZOWXMP4s9DXnTw1VHLcdT1jH4b5nc9yhGmePnZjghiqnvKmHsbf9RX9uBKJwYv
QPNCUlr72bzSq+zjkn5zS2m9BxdCLVCrnI9vRowum0Y4PsPQE/xNShliqpd0lBl/PGR4M/FSpp7Q
GCe56cEE6pgDWef8ouw6w+5qtGA01zF0pQ2UbFEo6es7Ah+hTZtNHpXh3dQpaeI1N6Hz2B6PoiSz
SVvfY0x6q4BbXAMgmoIr+akY4MnXRMKGbM5U4kh7LEJ+lx1S5Kt/ie49TmvcF3oniRGEP77WQyiQ
AezWCUS+JiP18JmTjXjXHlSfoZCJXfZ8zVCOlrmEMTnCreL0rriGEu3UC611vU/UhZtz4mxdDuh8
q21pK6EdfO5EN4Gc+2MWxF03r0eBgshCxDL1LbJKKf2ovb5bGIFPqIn8gvxVbLTKg4npBiBcUP72
GInpWSHBv/nffh7eDRbeAM9NSrt42vCnQJJo4SQmb5K+q3FMUMYIs00hpoE4hNJqbKhTMM1RNydi
a95ABb6WRfDgcSylr2VkbwAVnGp0EYojJmyYMlWujx5vwU1mR2VDMavw/FwQJ61JLBVLd+CqEJsI
iNCPik2HUMPtibxwU6i3qJ2bNijfM5b0903xNenozgC3bpph9fBXmT7WMSzMsQGQ517Y8FJ/8E9w
tCoztM2DWA9Bq/bB4g6a8jSdRxRvqEx5C5CXR8Jm73YoInWRgzgj0HbxPCJa+UCL/p3/c9ydodbo
BrGGbGC+Ce6mLx86svXuaAQWIQgy/yL+yTuW/RgbfFlBdXAtaSB3zArlHOtKWKI89sCfFDSp0XEM
KWZewnmiwcMkS60QdYMyAx19PxSFEmAvqU2NGoSqr/OLPXdhWwT3lGPp1njIXjcBjv1YGEnsPDJJ
xusAxEgytLPitR8SrlzQ4Ruuck75F5PyXG8C/VvCqi04J3ANfTIei4FoIMllSofynT1s3HLipUu1
ec9GykWpTQeevVgePshuuQMc1IKf/6s0PIG/Hf4wLWk28jtt91HZnRy9lWmWkwGpsBW9teA9SZSL
/qRBgUy79i774e65KT+3Ydk2cDlIeQLYDQHxY2TpR6IYEapexuk8iAWJCBf0tmGyzB2A2rCFe1x5
9mE5jil7AuVf8PQBxKtPY04iL9+ehOwRoROa34hmQsImw/sUQ4wUp6RNUKwEwu4PHl//LlTV5QXn
5iHBI+u4QTfD79lU+dcKbABRfUnaJFYfwCtptLXo5z3PKuXZ/yTLNl4M+iU5zLF5pv+iJ3sKuICc
8tcGbx3DI+JDhN4kS5YeU11/a2Z+KOnGPM61FWVIFgyomP+YhJUKlEw9ws+eLKFIlpwqRoF+7C+f
UB1MnfHsqp8cwFVWVxJeTJUiN3XfdYnfMfcYhv3d26hZT0B5K9LNW6zLRqB7eXv5phnUJoBmPi3t
U+BoIFQpxy88Dq+U6vrYrZ9UJFXb0FLpWTwcPpERiY8NjJoNtm5XWet7H1pA7hhHgyK16Pg3G98d
5welaIercpO+zoTK41upz+oZj1B48QZ0hUUIlUJwva1ghDEeAo+KpikRuDOCWxzGyZ0EcA79SKdP
CysTxbhCfTzQvg3wBRpV4v8KyzFLr24jjBMvszpZ2Ay10KnWiFCay5HVIUTe0+FJKVvnICtPHu+v
9oSkaBhXcrfnIWuejVCE4H8LhwEBRv7GrurbxHWE4+5e4o5psP6dN99B3ShzHkkO7bo4V3M550dP
zTMy8FI/ghzYpB98t2bO7qagftn9Su7oDpw9MJWd3pxMx2lI0eSa1m3iNAP5m0aFd3fMzXRYzo93
keOERwcI/XfYDrB1ZVJP4jsRCD/XYuLSWsFenvgPK/I0DWkcMfH/QsygV28nQuRhmD3U+qfT96BH
2onoxZItjWfOhGnJIF5YkV0ZSqr6K2ibkj6XMCP8sh+tyTfPvXr9Q33iYOvODwV60dKq9oojk4uR
ryVNXroUTQ5CojslWRsaNx9T7c7kcvJOO4fekHCc/kXhXW7U2aEi2tiV1xQnrWgy9sym/2RN4cLv
VhIJD3uQTqqT6KBFyOEUfQFEtVj2WLE++uyTPevLu8/Vi8CJGa+OSOfXVablVE15cN3vcdc94BPt
4UYGcqvj3pUeegc33k/pyJKiX2mMa62L8TbRTdbirlZWJRvci/8d0+wvesZzlnGjILDsJtcyOkqr
KcKDbkxiaCKwlsCXXdRl/xH+xtYEJuD8iW4kuM0zDyl8qR6KNZrvxBivbzXrBXDiqtSBFeA/aBWV
AX1YPYIKMHFrxZ0IGm5RLQUMMSECZBKrPQd7sMSeGQdSoG2N+PeFWWtf45EPMwWK1woHM0FpDY6p
Afsh/XF+OTVT7VGPLi3xfJ5IYhr0++LCHPmzooSK66MiUCidogr8QUtFM36o7bMzscz2gksrAd4i
Zqnd8XbDzGKC+J0IZeN+o7FJ6uEmTzKsQ7wLutH2YIrdn418WBJosvXuD+jdbf28obx1+7PdHGTu
jg+EgRkPDRf432UtCQFap7ztSHeaTyfGhZO11SYzkFtsphsgdL4QtCV4suHWvAfr+HQX9eqeWnQ/
b40AsboDQKqnkcGKfwDGHNlmO3b6fqgTp4XFCKYJpfFL8JjpMynyvmGlNEaYTggnp5i9RmEsWw67
exDQe/oUu01DIEAk2yCnz/HRKjD9g0qsPsdYq/eawtXsyCyM+n1jF1sVRxFy4ch/LLKYVkQoK3MH
QKmi/RO1gLhlu9g9NKZmjILWUtcS/jcZ1a3QWzkLwVR7kXSjRJllCqLSW9jtHPEhXzYnjAQAHIi0
Go+s62BZ7sMvOzrHPzABxwPwGcLhkUwd07FePdTkqhPt8zNGIR2B0BTq/Gwe0qxhMgw5yAKxI2oh
T/sKqlbUq6KAHI1sgXbEeP20+12cvBNb+wLx6DGtK4bE7F9ohQqxgTmGVcx+a7d+wP4geGuP+Nox
OpHqCsbeNtzKdt8hcEIxZOI9GIDPatV627dqQcrXl0iGDfOuGC4ZWFYEcDKtGnccghRQzy/5XAzU
1AiSpiuJk0PODeEKfrprVyxjf4P5mqzLeLJp/cH3ardzIDyzSVGcsUX/vlymfsvoxuC0QLAKbr6j
/kMO5SkQLYONweoXArXnsaN3KTWSBCimG93zoi9u263N4sMQNZHvSo47vixd1gBdZpbY9GFRy0jI
25jhSwAjrFrrR1auSWJ1Oe6c2aESEVwFgaC8AHf0TuNBrYIPwXhq49kptdcje0DvJqxEdO3ygZlr
g2wrob48eu9qJKFaIoKQm8RPuBnNYrR76xUDrg0JbEwryTWjlXwXjM2v2iVYsZBGOkIa16gxL6Tt
A+zfdSOTXwh//GASU9eIGlYKScwDasa/oIXLeEgRusQ9AYUU1MVN6Uy8gsT/2z91RzYtmVtIaRyc
MfKWmw2ZCUyGzFqs2Rjqc8JPzhQU4D5MgbXUxnB/5Cd+WK5XpoPwULgU50eEpNtCB8FriXJoWQme
jBBSBZHvzl/pBtW4TLF6Pwg9WaDA7j+RApfuZNvP/lRNK42TomMKTfg4/NY3fE9IjmnOzI8uONzv
K1YR6V0TaDqxG0eBfAtnx/CO6cqFQfCINWh1fGXqTsTCkH73ONYaGp/I0Dz+FIN0kWcpIIkvkYOO
/JKm/mxE8cOPahMMLthNQOK2YRmGIZDfAp3i40wOytqj/wqFK0Q5HG3LF/RR67dB5gwL09Ag3zpE
LX/iqhjPOAoTQArfjBhfjGbr2TZqL7/WRc7awP0SgLmU4ScIzxqdGiJTXdEjsV3w79s8M0NVYkid
3KeyRbQcBs5kw4ObrPAoQuKLkc1ej1IyDH2RlH9746O6lyyfTN6srzkXb9vWHI43F0kaHJ6nz2cD
Iy0xMJ58FJ39sBVdJCen3S4FrV1CfO18xriDJ2eShe1vyzIaxw3N1VFtP9mBGS46TS0Oy8kK4SAZ
m4Ucg7wkMbDAkn1FjLvDL3K9vjOgJpEDGPyzx6cysf1oNyyg/niQ1/dSshmiLIkE4bEHKskm+/JD
NIaIsw9Q23gNqmd/1wgOkPWuALZZa1fVsWT3sI+5LYq1FLiAMMu4/LfUjc+GH0RfTnzMjr4ICmZu
PTtE3Eq67F3r4lazGoq1jvYAvRCOYDGmwxRrZ2T8GE/qWyD54gLp/nxhQjbaik4c6bXPiAecz3Yq
Za8MzmFIPAe5lm67U+V1SMAD4kn/CX6fgybMG3Vl0WBm7KNmvjMRTYWUWljquJc+8aqg/i+VN3GZ
+IQCtkX9y1tIuY8FHzI6Q2w2rC9NcitL0VOUuE2PkVicWesZ21SugQGVweNW9cv5gx8sKBezRoO6
flxNYMv0UN83wCZxqpX/GiZ+TlYfDsGbYpsch/AQhNpCJYnNZKVIr4lO60LfN+173doVnUndDOPg
OEMiSFOyl2ksF7kAz8omrZDaJ/+pYFZkVHO/2uuMddjB9qQRBkEDtBW1RQzDcUPWhKCMKp2cQJcZ
mY7iUzthrGRAcfutYoOQOMA6lIvbtbH1pz/6yKKsmaz/j5DedNOmcsZCRQEcjgq0I5EdYcRolcKb
ZEGt7B9LvHcuHVswi1EeqNfxjh5dDum03sP24skqQp2O4xdfqtVyOBvyRjYPpt/10EKGdXB75y7R
kiCDJ2SWfJNIKUWlvbN6FLu6QWq72zoFpzbAlZ7mlt5U+lhgPExyKn0KdVjT/uI2hzYYP6dViZp4
o8szEmY3TJoqjj0r5vY/VxricxPsgTGp/nWIQDxM7LRC25SqUMwh5xn0UESZXcW3OAgr3xvTQX+c
5fJttju6txEapFkkzeOTgF2wbL6HoRTnpiSa+IFbjGuSrn3uQndWrX+xZF/hhDefILNlvWPP3e1N
X0ZKZKXLlDwoQWmt1WUS3dnlapGFW6/tz1VHWVnRosjZHGi2bYfCe2jE9CpVCuqtNyqaRqnFn2GB
zyc8JFv7Dk6MpGAQW5W/MH3b1V28+VxbK+CXmD5HzgA7A2bZuuOHEIePmUVLCAR9SpeXoxUYwZyk
BWKjE5KC2QV2eaOjJbdLAJPjcBdnp94eP3Fxy7dAap2gOyQblmT/h4FE/9NFEaamBe1Q0ur2gF7S
OIeo769AJPRNPbFzt2ACkKmtA0L8BtsCqt5xA3gKYggF3TwK5i2/Px3/qT+w4s0SG9leJyJSIDnV
8xNMWjns0k6OEXzSSdql3hCuOQd3rCgbCKv70BrN1044VyboYtdW28dtAldk08XKNLSeL44XzAs2
7zp+KvZ2VrGE987MjuM47xzt7YZOr9xYzmSqKJ8/5giNh2Cg+M+VudRE49/4WPxbP4gBhEsNjNzo
Upa4h5U9VIPbfJNM6FYlkpV+3K4UMcqjOuExbrAHc4+BLK7nky9INFQ4AY+f5K30JCpEe37MYsDP
p7UMML+usoOFZYBME5b7+lY8Ii2iXTlTBK7n34BJbPKyZ1P4DFe5uT0W/aRxv4Wy4vUniEtqRDGc
uRs4bewPBNQIg313C4+R9R6P0uwG7Yvqc41nSqAL8YV4JorgZNGof9mJLBrDVuB4XFzl0phwtN3Q
tUWHCVWp7k76EM1ARTL4ib61hrT41x36Y4uRgkTt6dXvhwD15sxeE+ZLnz3ZPQyZuVHWtHS99UwM
CoQbe5vuLzPd6dRteL9nypQY8LSkFd8Smj4TKT/xjjgzg5VdqH+EFg6+YwCEuXT7Lvwto6cAKaO8
8+54Hrx01rBpS1h5QJ7jhMuyL+ltsyuQ2O4KTS3ZxeOaA6zMAz9t5oc19piYlIVInU5PC7Yp9Mh5
LvhZsaUwJkv1PlvEfK8spbocU+VCt6a89SzNC7qcHCa3fWp3txDd3stGheXYa8w32WU5RhaeJvj4
VrvguXW2hoKz8XGeLhtP/kBJZHMta3lTuR8/lx4pCorGNkuaaRA81IZ1jJua8ulVjafRyZAjXVMU
QvSRboe5qjNJOegBngPofBAogazzL62VdIxdaFhP3qMi44a40J8WLHEiqZWuBz0E1nu8ACaTJrxI
Dehn424fJ2H/4zD6ER1lyc7twCUVapH5Sic9MztbeaoTrjXt5fVinRW7FVmrZ3IdW09QBJaoJCnO
S4URjDuVblflBKgP6xaCpiHR6IayEtoAXijlr9bvxxPlYagkTdfh5psBI9E1fsDSGI0Jn0uo0rrG
8KAli9mUKGDv/OENz4D/riSetLAgFR9rLY6eIhTRSXE38B42ljJkeV3198IPvHPBNfv2G1XXD8/2
F9VAcLl+u8tG+B5NwEvCBTaDZ2mG9xfrng9INClENwEKg/Mg0O/RuS7Gd7WdL459TiCnTMZj1mJN
Ctdq8uIRu8GOlcc597Kx23tsmftKkydM3BVq4YPcZcQL8U3tZzHeoIID5DMyR1GNhcTNa1R4ZriB
6qx9WcxAiAPwotnb6mOuaM/EU5EOnYY+QhUnecnRvOG5Nleo8rMhD/VNG2JB3Dnnp/lkdXdanewn
0fTEgTlbeiWA8C7n+wvYjCmqT8fAR6oausk3UfI+Dd7/0/RmFeDcJAnCW1Xl/p6W0Hhaw6zSM0Ud
3mtTz0Las/m9bdbjKfRXM5vjxaYcT1dZfzRBYW9rZOUBYwoRfyJdfalLOXNWriQ6dz54yme99Fkd
mUNvsNTh7pec+mPW6Kjr2D7pCx+3/R72d6cVlqA2LvbH3GtQU/DWWkXgIeq2b7oT+NWWNZYdha3Z
M/92wOkVUKDlWEnJj4qPwqsobsBZvkQksRmNVUy64Vwf1I8f0JfgS3HsiLNQHsNJUHvI8xkn1McU
ZtNHZvI7qbXa1jm1U1o1Dq7in5GZy5rW5TjRYRZco7pIvlES02/3Xo/am9blmTJJJ8YGv8jHub6n
aQIGHOLNRm5VfcXqVBusr+l4U3IGr9MHMmqV7Xuo0UuA/EzVOVjBa0XMNlzyyhcx9p/HaiJEbcVY
2eYkWIXOj60JPb3Jq69aQUMa1Zn80RzCGCQ0MkMcGddLueiLuMwqyjFQodYOLI8H7hw10OV9VB1a
5mjqeGW/fuqGTo6vCTNkS8upSLaqA66iQR8x6Qax8RRfVgeJKnJefl55Odn6jgR6l2puUySx4dnK
1PRIySWLnVqtC6/gI9TGutg3lnYUS0ezV/+w9K/8mFo+8Hn6KHRkIQRAb0GMU6pWQ5c6noOcrugl
8nhMv0o9XCnl/6Cmxk4EdcZ5898qXQRJMMv294GgBGlgCTbs8gIUC+Z7Q7QygFpgCK/sFrg6rdop
ULvMN0wSyEEqeLYJq35Roz1n8XKNZWZ1K3CaL9j2hS29ZJ2Nxb+22oB7tLkzoTBp5RPnf3yFc9xj
CP1hwk8KRSM/inBiPje30jXHqo8ONBbQt8c9Y8NNCqe+q/nSPspdNcvdj1YpAgBDwR7Wv3tzaFv9
fnhRWynTCG/ow0MQzuso7ZJN54vHvkVnhZ+tXppPVnXwFs8Y9uP3DvKOnw01P1kKvSHxLNXzMtlq
iK+b+CM5HnFUcDmLQfOYn+Kymnu77s9MzdPU0Uyvg6IDUkYm2lY/4WBQsYEDWFDwy/hMGr2XRPUd
lilc6W+qaFRjmqRUMJFzVNFeFgLMCmjT6Y5Cy593joWVysy6HnUakhaOQaoE4jJIye/9wQbtRir/
M8XmW5wiHAbutE56aauCbG++233D3vQIbp6bVNGaKBypwGCv63fQdusofovDoopUAVkGu79p07vg
uod0WlnKZHWD1RniKLRtETCxE3jqb+bgCFqQvFjH1mzJUu4CF7uo4dzUrXg3HFdbwlPZGPF537Rj
sZv1iFmGNbvM0QWGvzjbffSbu+/ObOzhPGRgKNNjgXaK1sRmnNg/WEJIzqPRh//YgxadN9u369Oq
GuGf6279fW993kiT06ydrswJjPtvlFG4dck5JMDwEO7jgQZpR4Vrnc/iF0c2tDLTm2lKW/cJmW9a
Gedr8CeQFzkEOyLqoMN4rue/cFLekbqBVo+P8l9pQsU110Pgb0uG3nQe/IVxNtXfC0qU/EO8qYPd
HPImpSRLjNbwdZ7zy6Ug8Sva3ECDPr+7Wy7gbqtUXZW2kUtM8PwCqc0vj4n3kXmYmiPuvZfnLpJM
ZtSUH7IX+iq645jOHzA4IdvTFBbgfuzzLqOLkfAx8cHVr7LL0Yhjv6jLlYcPuk2B50NTeaLcMIwm
gkw71kC62G2EjMRPV+8KGTTMgfOgjRESIhTP7ZA9WZfUETF5aL6+w72gce8dXLdISIZoKrz3wsyk
Xs9TAaCz09miAze2A60y4j9QmRbc0H2efUbBtqqg1SGmtThTIdWVEPdjUtyTQGXkAm6Dch5Kza/H
HKOoHJc5T3T2B3fjLxD5c3Cyeu9MWMOtvmXac7/TiOtyMrB8Axy8GXLOO7w+UBJSl0ETpzGYIftD
CgyTS1QL+5aL9Oo/GFjwTrW1QfWxywoe3df6YJKSxniOU7UYjHNtHNMt7krrWi6ePvw4hogbJcYm
KPWANO/fN51ozQsu60r6CxfpLcJGDy/937EVmQqvVkMkKz1fVfN5m68Ji6FPBoCJ2ybMKZU/k22a
rDZCzdFlK/q6qB4MhJpgRNBMUDF7IeM32kZ3+DDKxBqyskymupo3XnzR/MQ5KNhroCnLSl2hITjI
H10I0nORDT9Q9hxMAI/Q3C+V+7EFtHfqVqoFnxaPRrtTTaMQbqFjUId90tq4Douq+zXpRC0Z8lWW
BajDWv2gL5zpRLebGqiX/xf8V/kfXS84s2Xirnyvwwor/BdtLFhA78L6PBH1jCcqGl9jdDIhIi4x
e9LTQYUoqwUZvTeHE2h3WVNZHlvrnfQZIF6pIQB4JlqxiSwKyiuAPchz/bh120seS3y8o4ihfbIT
Gwoi30eX40dQ5+Z5RAednn36TahD5lK7G54keDHoV4+etXP+cYzx1ZrkAMFPg7hLQWdkvHW8+q3R
clEWR+W8hUgZ8a9YpArl12k6LCPf+jyAqak6FxOPzc94ZeFHKxi+cIgWSnjjvbYiPhE5jY2/FEOg
EvervGYFhDBKUMwZ6jX6iYvltuRFFdfHLpasHUn1uLKBsfjofrJS/OQk3fjQHxzJRS9tKsWZBKx8
pQyGq9gloIJRA4I1Fh2NlmHMKO26f6WEVsd4o4WKZDoUtBoPQwbXYSJlAG+TnPrF8yhwb3on1pVW
CA03qI94if+f0OU2BboxBo3bYBaTJOtlAqTx4pt4mbUJpcm6hMFO8GFT+KDgAz0cYtLTahXxpgFt
tRyg4GIdv+PGiSJiF/zIL+q89Tw8Ifxc8/cqnK2wgrz2bmtC60k1ZabRAPAW2XxVPQ6oXNWnmUnW
5ZcmsO9h6cQdJjhnQxRaBOHy6n9hmW/fGSlepaw9/Mjz+0ZaR1rfMVjedRNMuvS2cNfFtlyHjtOc
c35Lh477qSBrVufJzYZdaQaJVtoubSlKl4xwozO6AY0rNjNtFbqs+Moz8cZe/xGJ+pFu2bBAofWa
TH7bZn9YACLcmYtJ+mGR/ycF5X1h7ushyk/cOG/NwRA6eH55FngcjLganwWpfOhQ2RL+R5e7PElL
mwM025tc3nByQqsMiPxeYSK744+2cyl6MxNSf2O2tnnrmX2/Og36qYCJdYwhvicNcueTUjn7hxp3
XJ+MuzGAFnPXe+KLMcu9261NZdv9JYViXnQSF0RlUq8JahbU7m+o9kCDilc6om0QBC/LPfcBaPFK
0PWq9CGlrF43qxU7ERk3LmEzdY7u5SYdGaU8DdGbOcHezeCY0524nmqJws56QzZ9ZgUCsX/XD1EA
tsOREBkkQwg2oa6jgW0Er4AJzCvhhRLzWjZW9dFi4I9924rztrtaYL+vUhtwlAkIwkgxSxecc9JZ
jF58Nt0GSmCaZEK9Crp9Dvf527xbndUiFrpBBIcwOoGlPA7ysh59WZJY+59M6nq7JtPbXTFzEYKU
WnetFXFfDlfYUBPm2WHNvXgqYUw6SQKY8o7xYRiYj0sUWg1pqcDqRrWBZjUEVhuqsSggCc4/p61b
cQBWXvM0eku5O8fRxNshxLXwUMl4ndSo4hgvaC7xTluLg8YIj+3MMDMmMpXEZZXG/Vhdmir0d5dw
UJGlzNwyDY26CGii0ZmxTLyheVHHliBa5ESDwHNkRTcMvT8xWerfCvItGQ9YcNxwKM91X+PmIufS
3DZdbzt6SjAEPS6+td4cEsYZwkV0/UZvq45pUPRd92bGyLS2v6s6Z9BnLjSxOpYrOUsYUZCCxQcT
xvjP1J18Xk+IoA+rUNtCBQFtGEMW4VtCUjhBkH9LnKfHs4yxu5RMu2D//uCuYQ+1fY+WFnn/n2z/
cmHQRMzKhHo8PPnUC2DkOkfUCbwQX1VLAG2G6JMzqinkqhc9Gsj17ErWpUtAHstWBvTzIx5m5Ibt
6FLjfk7Wtan5bkPoPhmLTLAEBfOoAv0MlQAb1WfGEQBsIP+yXqm6FqptR5RwT5LPy/QYCffTyr/8
43MQXHmEEp9ueqoyE1sTQGkNdl8hWDx5VAIKk6P32npjh7cEXnEi71J00qxTlLvw3+ypgjUZrDVy
vb5vM8O28gM1yGu11Oj8LmpE9z5OkJ4a3iXyZjMOh2n1hkzvbQWwf+80IDV07ooIOyMSXwsKwWaz
A8o05pPA0LSsRYM0UFEj+gAh2b9mxfDnBpmO1VmiNkyh97uv2tmRa1GXRgwNOfrgfGXlnGbD7xtg
tllcaQRkmw+zerqEFD42vzGv+xA5ba6igpTfzwWjP2yJvUdurjF3cmCzTB4xqZYaNqWVfj84JYDN
tYKFucMu/DuVzPuZUNEiMVAowZVe3gYnqM0Sd3BwgMW5qeFLedfNtB2Igo6XA4DzXhVfe2sQLZk0
bGg7zouPO2PXVg2Kx6GwhMafKLdBrjVBntrI+qIyem5h2Q9BJz2R+F6kseL+3qvoUF6wZ4xogjbp
05NlES5klfVhw1B+f4yTwlOK4K+miglHHscisX36BufpJIG/aWYdMGSYknX3db42I/mFKMZSXHeh
I9S8ebdY1+ry2OqqlDwdR+R9Lz64ID5hQxu/eDn9cUcrnm4+sxFJPuK/LONlW+gaf54iz6q4ziBr
yoJNPTb5WzsZBnmQ8kE0AOwQih4poy6GTQR6oxKBJinlNvEceJjVrJLVkSCtM1mn9SVbB0At6dSD
8b2aJ9Dp2tkc9LniJFGRenul/NCtdsY/HUBOB/j5U8ti0vEAF5ms3biCbU2pCx/337M0BGfCYNLq
pL7vDaMQNHva5xZOGK/kK2YT79BsDIlYWfnrJSXYTExR5ZERCdsTfxFElLEjkyHVA37kOsNSRW9J
hXobVOXIo/AixWafT3laH5/Wcq45YmLW7ZZ7Y6H6kuPFITJlDw0fgAtrgVqwcbWtiEZYZ1+gYBwS
Sb6MWzqDNxnvf+6TM6xI2Q5sZZqTglnAJDD8nrg0myp3sRtXGAg9JFBEJEny7DvmRK3Euk3MGP4s
Sr31RACvzenb+yOBilq//h2dhmO1VV8wSpEeOqcJSZ4G+vkEX2eQViy7Tkodn4yqIbwh7n8cqUAd
4HOlUKqyBGdsRX0HyxEsKqJXbMBU04rMV15xYekZX8qs9ExfvaQOnIAhhXMg9yefaARfcBr90/DB
SxTGk6tLE1bbpxYe9FgqTVQO6ll73H7oxueOeyvr4v0e8IzDIyQRJn94k63rwLOzlfJqnDYLTMDK
s3HeAMTt+xGL1zHjloxJWJ4y6BO3xCpglLUFjws73+CjKIvgVDNbtbL3+3cLYa/bYfGO0DdZMhz9
5vsU6ZEK2sxZgkzAYCUdwTSGAA+f300tDJddkfGAwn3bmxjD1bvz/uo7J43T94vLP7CvK7b6byYH
VFtneqbcYmoc3Pldw9Ko45YDzhO9EHtFyfnqxiHcEbnBaqnOqOvr4FUWw9t+voOWH0UodxheEtTe
omnnXFn/WdfNVEDQdUP+Ph5YmiMkv1AQLAfBzSgZoml5KJ1zaCwl8F9OKx00zKgTRo/zLV3scy4W
MuNZnwPz2qxgXQ7kf9rDJLcqxNIrCvtGPCCD1pjyhFmxQNgD5oXRSStM2RSgHOaGj+TuZyydMlTH
KT8QFv0UUDtPGsaK7DnUOsBgDLZOOYu50otI3T4nNFgtgONG7h/L/rWVPKs2hdCSDi7LiWPLM5rz
AgEeL9/fTMAZ7iV00jOyhfAavpb4lxkhCXyob/1hp8Gg0qj5XEXr6sJdd/jP/7li3Hvl5pRt0Yy2
0VJSDQ4k7xO9JifZD3begtwXFIgDjrrmDeMg4P7A9uJZPpZduD6cUntG0VMM7zz+uboZKQdCZJE7
NnIKx6zDJa2Ky1d+GsMyYyMP+PLe7SZSm0lmPf/edJRJbCpafYlLBBrXqRJlWOK6UqwuQNGYrQzx
eCW2T31a7Lhvz6KSd287Nllozd2USjYF5pduXY5kBza1uaRMY+ucjnQ61EWF+dn/jsDI5L770+Cv
EuxtNSJxKC4HJ4D+X+zNKtolt7Or6I7DtHN+ufXVzZfO2DDc+Gsv3tWBDQQXfWdK/Wn4LSI8DhHE
vvxnrW63zllAtCZ7FRv6LwnBGyvWvJhzIuW+/WTJrBDKMbc/oAcd86QDzFTM649riFKKq+bjAjnV
egEJzVIJnEdiO1J6a45O8irPk+4U1hKfP5ixZPxBdnYmN1mUMOCSsL+QZH7M5ENWzF5i0qUmhf6f
2RNCmD4ojfcrFudMgeM2YUfVCcToj3+CyWgq7Pno0b9MI2JFBFE0QQKZ1lFBaUaEEfOPrE7P3Pim
aatBBD/WrydIQgEY9qCMHbcQ55rt80syfTpj893GsBc8RpNSUSWc8Ozb9Lxy+CeRO09QLRVZz//v
vF9ZJPT3eNg0ugefGCLVe/gJq3geX+O6uirAXAejYSl22W+V1AZD8F4bkPQb5jEQU3doQP8sSIFJ
xH3RtBXmRpQWuukSLVSd6EoV57Z1eFWcop+WrU5KeZYp5zlRq6x89jr755MckYZcwDVUMv9zuMR5
Dw+JCuXFoX1OgqGkNYOaX1WxZV+Nq6NH/JrbETCGGXyIPbzPwKv3c99IBj6gnjF3oDvSzd2u8EG9
PHoeIiTjr8j4nEO2ayEJJoyIPIwwUolUZwCqISTW5QlotACbDSrw0DixmxSePOF7EK11dfElLqDx
FqMRdjt3MQKspyMG+/rUpx9sg6ln/u/4px3V/+sPtOIm1/Px9QoPPKHj7bujhAF7JW3py1vURais
958K7fpxGTIhHeO9Q43iWnxeRDsnvNwEgPMfnJkLNHkbU8riIb1VADHYzcNY2tI38e0/rSDmb7zu
dC9sTNXZ5DPUjDR/SDIexTGlq6qxsZ0JBti5mTWDrB9vUdnxGGCTeyRiHMJZV8iIVhuoISXPkKjG
YYOqt9VlHggHYQtylahN6nThkAuRpT0H6ET++M+gOqKlAZLlZrfUUhuHlv7D9+ZBurfMgvnzCZUL
oonclo+lJdmb+4M06uxHjbL4azStD0OnXP7/f+AscSfF6jM+mjO0VjKFfTKVZJAOAsEkHnE5gwyq
IHSEoMapBkML07I4u9A6EVZKT18LA3ZNZ4cOFPFSpXqT/45iDbcY92st8uG8iErHzn/XKXssGV8c
pZivv/9473ZITAPotaKfETSTy4lsbgI6flq3a2Lst8GLWp4JbrCqP3e23SMJAxtvOC3cnW3ZW8Xr
u9fGacvglGMJSa8QTUGVM3kchVQzzND2SF5UDNDC5oUikPLIL5D678NVX2YrEKXcXT68k5n+15KU
XfN/EFiSPM1w62/i4PJD0te8H3JgLT1ieKEtj8lLzd5eCde/VJKTU8WvhLWIKVK6ZFl24zXUau+M
muNSLa7o8ta9MD2tlCm9JcC8CRnGf5jdVMPFSxlO1NSjmlcggYuXxdI3UwQtQwbf8gsj3K5ZLrSQ
qRwmwOM2IXFhpmKzPRLqwjzVuaJanl9047UdpUNb/xKSzW9chLId2nakri9KeQtN3evzuKAtLO8G
WINatnak5avLhSO3i1VoK6hrYjPHDKmoJgnvvmHPt1lWaF87DzuFFVZJRXx23Rpb+MJz5k3OSimt
Qwq6qk1bzDNh65WErgeN0TKuuGb1xU4+xrHPrdoqrX3Wd/ZCVlLXwXU2zJiYut7bK5qUlzgJJVBP
L/uO4fPtMK7TkBOypHeics5WNqKbMjdk9i7q879HO7ybuRKJiNf+K8OcY37NZXD7AkxYkkM8oqwh
z98x62wPmV+O6GqVKNTJJkxucX3XeRRoEEOBtYEPHOGm2C0NDR+1s7hMbe5akItkvAKmhl4F/vYc
eXzRE284GfIK72XYq0/8GOD2HmLdrPbHhYeGhgNQAcPAgFOZzA/wPWLGnpXH5usZmkKd381zSX5V
IDdaxrDsJriSHn9VoM0RW6h4ZOId8EOr4fqQ8sy46DJ1BwahGnCcL/G0Wzi/fOJWezjBo+1Ka5FW
DUQYh5ucROQlglEe2sgtXoQfYFjnAhX8ITza5YBkbwI8D/tkLuU4SPRgciOEAdevanwQ9vKH93Do
GVHbC4b3/9Ag9wzstKlnWo/hUEuWt+vFC5+BeR65swclw9HVJG0AEHFHv78Xf8R2BjHL3X+2HGxd
3yLpIzUc6YPiozNMQ3SmP2PYrUTiybvZIrF2h2lVbiYTkPIxuzSGKPYGKoSDrBuzHNNZHHDWc0eH
lPp29NKysSvTfDD3V+XXyZ2Lnmi5m1J73FlAUQicAdhDSdqy2F15uruSvACGracz5q7aCKzsra8M
5uGMtmk90jt45SQP5bzarnZdLwvpPBhzqiuvnj4y1qEdgMzBVq8SgF68LX//P5559DKVx6bep3K+
cHwijXxMbsY5MR1peZAhIW2wYdp5lWRs50pbtApFepxJsrmVwyqFJi3/4JnUL0T2/2tZw1HcLseX
M76MkvTwe0l23ur1x0hXNbLg32Ou+ZsEWDE1x6Us9rZhAeJ62Xo0HM+KPqVZJDL/1JPqEDWt7JeN
WNkSE8FGbYwT0sPKij6HlrruSDUSHfblIjKiJAYaoCM3qJUuaSAvWXAXPV7htx4+gTuVJGK3+Gl7
DmJ7tTWA4ieFMB/eX1Jx5TCoJizFSMGUi/mcH6LA3zXtfAmuKz9TuGz9ACuyZBZM9wcUuAqBhW0F
TR4adhEjxhg6khNhXP6BOz4laoiw4/z5vrRgUcmngGDLEvtPTKz4rxsCaAyqYorDcwh9uovBM0//
iD1ttikq5cGO/DX5zZA/3ZXI/pGkbUDh7pHwVW4gjDMk82vJ73URHDLprGQWq8oCXtZVUu5QhHTq
cN2gPKeUM71XyxacQ+rJ6/9MyIuKcwnbKH2wTwD0u6PWUDur0dedexyWusQ1ITuHlupTEfwBe7p+
SaGHkzdj8IyzWrCvnyUMeCx3wRgRKYxzU9//R1caDgv/gTimOUQCFSkH6BPhgO9yGn5qGecXmepO
QLWQv5ixX0VIBNSDU3Rc8xmQ2oIjdN6vFG2Jpv9wbadO9pvSIXYUxfAAiuDk96erhEQ5phmqEE+G
fAxHMZhH2IdGfAJ2/iRPcxusCLlJfmP1UiI2CgkKRv/b6x1SLOCkOQHDocNSpoA6UHQ2+WzKMREK
EGSU3CFQ4FuLEKDveQdEczmA+1E26pG4SPoTaudvxwYn67vTNa5mP5pxa2WNJJ8O1PX8rajaqqDR
nBP6lufxPxnLs1Z71uxMCEVEQeJEd/1cokItJgLsqC1vZHt9mRol69sk00Y6ZTVL27jtKWmhPT5H
acn0muB67HfEc/g8mcKOZLG1vQKaGDm/tvd6PBKe6UMkKFoNADoyzC2lyLJIxcpQX1iyurmd5Bl0
v1ladhZCLfOBADdsIUGET7nin1ULZpcr4RiwfkKaWrp4mbf1i4KwBeyx2crc7ZSOenPuB+EWael1
WzHi8q2OYKK4zu6wXNOgkdBd88D06ypSQRUpZ4eMXBYrzKXrdrfNqodiGqJ6fOSeUpm2H1UfidEv
5LMgLTIVS/LQ0pAXjf4yXjyOySBuxOdRpdTvKHzU9LdXwMk3C+DtWQROlpdfebCNt2kAQCY/412E
ghMxU9sfhtbO9gJWxZoQgBr6GISm8ILAAmmEfwh0+YLHcAEZfEUbCeQMsFGGvxLJ+IWcQWPDWIYF
6v97wP6sNxx6k1xTvWofjLYK6VBNZyRDf17uJTn3DYns4dGCBFaCF/Fe/6JbjU8xOFUmmxAqsUjX
akZ6Tgj05x6qOv6xASNsVbcSAqa5BghTho/pzVI4TYMZ1CN6nj9F5jUgtCha9EgjDqzQe+0VsLUb
5aNhF4pF1VMRli0B9kIL3dN4ChH08kmxC3HnNn7UIQ6/GI6c2DxaHIxXdzpbsEOIiz1kFH1huoqj
ZxfmZp84zwddSgDBz0/87AXRSZr6J1darsXRpEvN42IB5m1wajjStwvdy+SiqRDrB3iM9uqZfs3I
ZyF+i7Sb9KHOozf99xzCYQk6AkKiRPpZStOQGFr//JHphWb5Ky9uqnv9Acoz6p7AL9mf91Q8HKPH
wBOpx6fBwkgMHm/0yZQA65bpPASlnz5RQpqZpWTWLdEwNWokOxBeJcJSLXF5nS2JCMBSwRKjTxj/
wt2pd7Z2605sa4DW4kpTLkscnBQpNbbVXjCvJVN5KTkwuXBbVQj9FEYVqA/HetFED0qE5WU6txTH
r0BnOZgWjxKerAKT8kQN0mpAHCUe10KDSkO8vOdHSz+9YaoAPFy4ArHLRy/SSNsJL2R1g6alTBgu
LstTeByZdQ7Sn57vmdzxVL87LZpLqoANf08yj5FXS+lqkJ5GGowq/dE8k2xN4NLt7w9rMcVFBtKN
9P7hRYNEappQgZSD8l9/WzAXlXQ+vTbiDS2lIF0GNmY9CWzwQZgTOCpiBz4WPTvtQd5NVoOiHPKl
3IXHGzxq9n5YZiKpf0iwj1i5xUEWgV8ZK7N0hzhTQUr68a7BWRjGSjRRB5zXfrud9PVZH/v/u4xQ
DXpIZ9zJuwlpmsR6V6e3+GQlwaWT8QaRK2QR3RhTr6RT9hoVsOeKctwPioG71uYqSSg3+GhRgfI9
6g7mi7OWnYo1dT0QQyvyUb0A3bwuHqKbFaB8z6n2DPHPEQFy2K2fINlCEaSEZKqNkSQEST7Gctuu
1vM7wIDYeGfE3CAjj0VLzlVR6FshHNsxn8vkyCPYalRqPIkYZkg/SSJqwduqlNHKi2nBlpYTYXeA
47qu5m2fMM3byEtGagfdc0yYi87Vty50Xzz0+kg8dE+ZRe87xyE+Pb1VFNFw799hfEnGsLsmQG3g
Df3f3JxJauHJDh0Fx+nywaEzUXzFZNW7D0dn9axTs0nkP/e60eFmfAR1h9qp8AsM+B/L54wBVo7F
RmP0v23hT9M1JROfnaJ/BvbvhizGiC3c7tjDyPhy5+5ModJH1A7zEWexKbTGXGqf4FG/GjxxV48F
mnMcdpOZI+KGfLLssM3XjAJyHeikQ44v3Zhdb1qwRW+vdscJgF6exrfdFTYjXCzrGvVu4V3RjMd/
ubonFsmKq22Qp3o02PwfXbLMTCl+qVJuvS8c1S86dke+wz45maPci4IEXORuzbEpngz5pl8TDsCC
cZCBZKwzcNSzQ2SnU9ImETxAMPyyVAMLXW+nF4Q5g+n06vJ/SJs49TMkExlmSGiVu8+cpeycYbkI
I5xNaAZBp+Nn3cL6XrqEHYAAuC4Yu+48e41mzOlB/ukom9z8C3AW5lQE/ysIBReD3aYC2E73KyN8
AFLeq9dOGhk4cEUNN/WhgbgSl6G3aH8TSbBgV3bPnBUaLQsolXxTfbPhABQBbtIaOHElwCGXq2e/
bLq4I+cXPnmRC2d+gxqTdwiATREsmfhrEI32EB7sszZtPwOkfo0PMSXZmHftLCztYp9MQlv9TXOk
2opfy5D/FdGYaOzJymFQFtk11mTT/4XfAnQWZ5Q5k7XxIrocJcLES7Fcn+2Wt9cpSlfKHYHopG1C
sPXuhz/B5GdPWNpLDYA7uOtVZx+v19rKLBBZV2SA+AAy5/jUSvwcqU9gotlQ5tR3NIcAGD0PNSRx
WxZhwRHNOStGIQBa8HCRt2zOyNviWPtgGdhqFWjsq1r16457dhuVXHMCZuala9d+gO5d+t49sQJ3
Dp4+NLuj9U7DjzmoNAklyk4zXfJwbVPtLcUptsD063C+1OmNQmYSRm8h96wSSpVKSG/PIArhBD8R
zTiEfPYyFDtO7ApmJ3bYsv0tTV6o0jkxPfBIvRtDwzNfGO7s8OIP5XNeYBLTYZyzZp4o99+MsXiy
6OjV8UHhDkrtiJ2iqw24ZObPpZ4xoqbMwaDm7URc3FxcdcI25iD6dSgWylPEBND4MzKXvp1WWSj7
RQhAF0JXu0tXNirE4/8zqYxsEH+t/E40jbVfP4QS1Tf6vxQAFIRs84hMLop1yxoLc4Ck9qa3L+AD
57AS6II0kzuw9OfgV/QedvOiUF7nyxqkiiaCwfaijAeWF4YmNIfUWPUcUwm5JRbXOBsqQO3AujES
W39E5tL/ObBo0dwQ95VQLNiwmubSJuvY1/ekYV54vux1wiBRvkxX0rFmYYo/QnJOe6UIuqTxseyW
6/48xrBmcJQGeCtKZw8UZeObKtWDGzWyKs5Nips2NdzPu8DpfUzhJpHMqkFkbOTiVl1QvP6/PhGd
lAmON5+RRWxLn8eeyG9ObYro9w6WBekNhONmJgJHDsHk/W5GSgn6iY9K0lEyWfcjcsUM1xCCMxAv
i5RWJ3FX37WLN0wYz3UeV4VZazJoqtyVN1LFajDESwPnq03F6TYsRtLrRp8h29ErS5Tdk75yezQ2
DC6+Acw2mpBPIJKZAEdxxVs5ZIt8dQTGCEVqV69oQ/wLwFd06n/sWf/kteXOneDU17t8KSMRWQGS
BQyZR5IiFrYJhIOElctEYWCl9xHnU6R+ddPP0Q5o2Cv3Mucw+8NvJzmDlZAnuGFi1hfKEFJDi0D6
oGpJOgmoNSQynm3Yz3elIzwMmiNVGTIY3SZDPMi5MG9YO7q7+kdOVcBWGT/2SlEFad34Sfv/yz74
ppH5iFLbZjO+TjpkpsdkNTZeLyZFvPpYnEuNnbnHoJaPygfSC76LygXVcJgIjVa6CzjbOSMp7g7h
OWNb6ixZJF9UK7+eiuAC0R50nolJx2t1Thl1U3VcFL9aKcA1wPc7SaoWIICNQplPz5Gbx1kcHNti
ZmyNqEgGj2LkncxVvRvMOEyew7dTph62iZ6FRa2dDlvzmtw5y0kFKRmAOwKNNXAb76+3Hd0Z9CLX
oq4gd/bO9+NhI8b782pKoR+nzmLSMO40+UTRhz6KWDSPjb27WZHcZVcZxoDxi7stBJf8/AipdunU
XY8OgE6Cmk8RRohC8sgFoy+aDSL7PGNuGkzcOeYohYLib6tq3tkUsRwJ/1ruMbV1de42vr0vYahV
+MTJGjbw/7XtadZnBWAfJ9xPUfDsnny2LA6jAcbl0t8gZMo1hsa1wovBjSwxUsj0Td1DAYxh8nFU
HZ2kiolgcN/vfDNypAf/PCKVcdetdskYEYOxl8zk2ZlXMsql2y4qjjzwC2FkiBPks0N8WDg++wdI
jSn9ZmEtujciFxwbDhbF9aEniJJhHURaKbnaas9JSVuD0RiloyaaRxAR59gPaIfdWFmxw7W0ccgr
xJYM6ECo4nuZT5KPMR9LCiaRB8A5fWoiJWtlHXWRvis5Sx1IO4qXq57bvKQMT78geZaFxBy1bx+2
ZSZ3xiGy2ctWU3NWer1ToAZ4ldajPlq/2mfUMN0MClHek+HM+9qb1QregaBDEnP6fINr0Ggm9zWi
y6cxFBqEGjYlAM5gJ58TmnncIVKkv+2Jp2vgDgXoaJAvS2v5m6PcRDpvm8wlW6fDkmD/v67Jqmu0
bHUoJhE+Fz4JYUQlPcUl/Gj3C6enQRnEkMUCHa4vm5oqjaHYHdiO6pzn/EYmy9AO4LzyrGX6ob9e
HiTA04+3dCFRqWLOogd9llOzOCng+mVic7FLhVX1xjOP0mjVsBPdbiisHEKSyPGLVqHMi1uqUBRc
cA76kmHrD1pSdqZePci6tqSKahJwehQAMq9QC7mJWC+gS2F/r2LeXz+JnGHvLzGR/scuc7lU3Nvd
cQn8raOmgbZfUZUYJMxEAjWA9fDlJdjz8ubxsmMw71t7lzFjmWjQ/c1c7RPnN+1z2j9gs0NNFibP
BZpRBd9nlhT8vSpcuiFis8nBuf1fxYaE5j1rh11ZbopWSVJWpUA1+XjmmZMHQdQHEoJetEZA5QB9
WfSbHrogJYiFqOoWYj0xoRjUOFjcBCiu6WYhGVYA/dK7w7TmG0ynURM7ytOV2x1l3FsIHGTd6j8/
R4k2gw03d0AJgUEOPJkrouVxKPPpkmkwCOGZuF/DyLVae0XQw19WByrh6/0UnuqXyMGs6HFSxs11
B4awvjZwmMPaWih0NYfctXx3jPFJz8DiJbmbB0OYwT8OwudTz/HQg/AZZXyRIxZtAJIeZMvBKPNF
XdDLpTFrmB6Feis67HXBBCEH9IgM1HrTbEsRsrg2lYD4O/MYvf0agjMzQLbiMHS5k95/4pbra6ib
vILmoTuKysp8J0wF59ZXJLWrwCAGT+SYSPALhV9khN1o33YD+3C5wS3ZxvcW09NujPUlX5nO5C/l
LkXARfrS+AnERm+mo4cq5VwDzrvxlWA36YkfatZbdtffO+D+NmjP4VMAdo7v1U2lOlUGLT7kFt7Z
Xx68EOZQ9De35V2kItZSfq7/AfjwL67XyiPkQXOypd7w5qg4YkjTfuDLbmG7ukN2vHgK1ulN/3jU
piK0bew7/6QZY7JIYkcOvad5QPUnghVElu2WNXNcHjn8p++6H1cL1e1cxltmnfml/+DBN83AXlYj
71JLe4FIgi0nml/LG2hSprKBjPOVPwcXNIs+qLwyGDobxKk0Qi+706y3PeJxcBHlK8e3S4JvIoRA
8YQApUTZFSJ+EFC1em/4fQrX/QUHWNqsfKTMepXaJzXF2lskCmlRErb8f+lhNnuKiJyvRsGxteBE
MmExoYtuJOvEMRCtid5x12wDDpR73htFjzF25O8sPHVUwjgj71Kqsd7tOM09MWyp/YGZa1Tbdcnn
fb/glE1gMghCGwp2RONBW/1K3FEfi73qKDmcf3Nh6ko8xZ0J0EN0CAvj0kBYj5QnfzbX3I4rWTec
RQ7MjYP35UZFrsEaFg9CS6bzWGfwu8dXb2TtXmlQ+7UL05iyUpqQzVwzQBXzgprYTMx+gjly9Rfb
VxIgqG5aZ+KkEMzgyMvV6+vd8+CgtdjcNQmhRtkNUhofDEyPET9AWBVVUIzxSRYscr5c8MfuA1QM
7K3F79PxiVTIiuaLA/9usMfi+LD84IC9NP4KTugIwetG5g6Q4emO6fM+apIqasrY4RoAY2oBcGpS
EUqW+0CCy8wmIHV0sW7moOHz64zhF5RwiguOAo9SW0e0D+C635icd/cncbffEaWt3uC5A0h7PI4x
JCruYyGhK4WTIDioN3oNxMcBqkwHKVBPoa1ESMpuSTqUcJS1sYwMvXR/Wg5CzZgnzPC1y6xTVy7i
t3/w2VAT2g5Nz4k2Sg8hhmLwwzmeQF9e85NGQ+ahcfebGlJUbvLgrZUGBbBJMGlU5m4j+xo3KA5n
nREmSYzF/sRdKpq+e+MIzSEfpDxzRcPT/CtbCJt5hKYQ6d7eb2I1WwBne1HUGvawfWR9eMnHQ5AU
PB5Q4L5MeDOyYewXFCC2w0ncEr0Unxmv3Ki2BIu7v7tGNnQbCQMga+K5ZMEu98DJhZxRNFFcedkx
rNelS6bp7cj1rNZXmqNQ+u571Vce/Mn7Y3xbKwPBOaR6zeayC7lbXeXhJqH3tajqgmwefpdRMVS+
9gpM+1Syf/ZTdEIKA/ghu93voZy2sqivwNGA7f8OaNPiWstpugk0bYd6lynrXtAHK2J3vs62cIK/
s7TnTSrh+XoKxOZpG3aPS1FY/kO1jrH44H3djimH93SM0nYRcn5AQfib5KpA6JKHM0H/rvuu7s+I
T6KrXi/mw7Qu+ld+gRK5Rv3aNomrPXBoN2oozkt6eECuvept0T6zfqQYg0ayhyBlvhYWcIJhQT3l
PD/zaohyDMb25ZO+avn3K0DSE77AKMl+hNllo8ZShtGQiZIM0E7tKirJkdWS8mWem8pctQVrMgL2
AcJ430ogk+zWM5aw4C4lFw4+zUKWYsUHK5mVQKbMF0TqESvaMlV0p9LZ0N8y1rYXSHiY5PUJFJnu
muY8KEd1XVq3E5YtJoj0q0NcWLUx+V2yIRnm1XkhhqOOB28oBesIlmxDUZygRs9lCRAFkiojK8wl
abSpHqnP/wgWY5MiSMk65xKQcdjLYbEqM/GexoZecw2jL2AFwBLkqjy3z2a6VRxrI26fJ5phlmnX
+XVZpY//k8X7R8ASEzixKU/3AT4cUaWI/EPBU76lknOJdoeu1JeppTP36GzEkOFp7Wgnt7wILOnR
qxiZRVZOlKiIDbjo/kULPLbHspbH7mYJ5UyFBYGV2zPezVHhsUtxQBd624X2SY61RchYhFYKZVlj
7M3Ps5CCuIF75nyDBXPxpYWreArs7MWXadO+7WM2r/GtLyRx5zj72+N4f1vgYgAekaHFd3FmvFZg
C3NgPzpPikuH5f6qsslmYTyHgJy4uhHawGOAWZc9orm1KJ/wmWTvg6lmDls9hYfhgxMUH1XVUut3
m5FuvrjD/b5dlIJq0Zgs6KLNE4/UptLBS8wxfr2k9g0gx5mJPD0dD625Qj9VxFSM7C82mZ9AdAv5
G69JnvjoC1jYVWqMe3JhfB3qmofBPcexSLi5X3fb+kpdCu9/fh3J7KQmFDNR3QfFi+F8JyKNEV8z
yyqPadzZzrycCQNFNgaWeZpJPkArwgNJeq9LmcCl/IiIK02CcI0lcgUlGfBIEX9OB2KTjOTAoAnX
72hKdMG3cDHNiR7teeLpl76sJxmt/yuhlJUVQYO0Qq8gIePo4DqQWr2zOpIrAgrTeXczV6V0h/P/
8jCdUvYcOlUcM1nILLS8tSRIaDMG3EfVq8ABUDDR8AE4GiZxqDW2RXkHtl3jtohG5QZkQPfRdwPW
3I06mxvLjQHa71DNXiL//Yh40zetZIMbE1sNMyKTGNWJhZ1e9R8mVcfNlMxeM98RUM0DIg4oQh5t
r3LuBrHphR/fvqNeJ0qcKB3icIjvMP+VbfG59xooJXtHs2hQGhHpStOj8Nx0BhmitV4Il9tAp71D
FrsiCaKXBp7E5N675ePcZ62V0hN5Xd7mQMEv1qiLsGp4kzklX6gLp6rZm4f+Pim4MQ9Kzxa0Ls3P
rCnKqdYinJ1QK+RDRLD4beY0fygCYKkeKYCGxFb79PQ1/5WdY5/gqgOpjhNoIzQXCIF3i/OObTGA
28efRDCQutl2GBds1C/0C/6wJ2OxZemVjwq3SsGnqcknS6iay5rF+7itl7zVC6vfiTfj2aXhrAny
+GpmztRjLf5AqLUMUe6k4y1VO/E9zSO0cH/TdmtXwPlfDN1rwYpu/5sghwzEynERuCIU7p0EEAmJ
/NkWK11J2VGVMJemrmQMD6rhAvkMCC4iT4voWMjlR9Dou5JLzCIrEpTOojQS3EGc9uc+9XovOPDl
8a9ii+2TtfsJJS8rN7MlRy8UNZ8u5vl/8DGT0wyww2NmSOqCRj1okV0Y3UZ8TumKmpSZwFooIevX
Sj6/HHkwICExQCN5V80vNzLYwMA+00LUfC8eFbQDBlWfUnYOz0WVggvpQeM7MMIlKqqXmMU5catM
m9tYqc3i4KsD/doEuhZAsT3UO63czTCyKgZGY+YyFWfHRpL80xu6fqItKCHVeLEJcfKuvl2yRlGG
3cjoh+rwWVX1eF1mO1BLfWWx+uzUazDrnYhViXqm31Hajq12Q1xRqWLPcuDw8Prx2aBqwoXBvuGt
gSpNIgag0Kbpsdx/axTTR3gswiHZhzM2yp9QbMegdEp04cItQ0FYh+rBxEXyNsUVCLCiswvhovIh
/vE4hb77wOUpdqh9f2SuFtOPm0SBZojmsqe0oW6uhMzEAdFpV4/y4NFRBtx1InA8mbJlYIYQ8SJr
gWZEDYlfax8Q7umjWSWOWoF/2cPYOwRR7lRwK/1HKIjrN2AoGRrVVPs1Pc45KK4NgRZo2BJPXRho
6l1BSibP/OqHPg0fcXX3LDy0fYvp062JUIBmKY8t8Fjor4HRG53JQIWX6RgEd11ttYgM/vD/EDsO
msEiG4DcFoNRxuEvnIA/GuAug1De3FsK0VV+C/J7dMSuiyc6oBEMx9gIlJmn4jJSwmOxpPwf8Xec
wWZXeSfCxmcvpKVlRIm9DBr0covZIIbViy/N+/SHuFYJFICf5NcEOG6iEgSFPo/5uVUZd8sltxct
JxatmGlno5nl46MHXKvlDdpKZwADizUB46+SSjIFC4OJI60sUGpzRv4mb3JUrArR9Imm2S1mrMJE
E8qMwPwUTQM0l1I+ZjQGC7+PEvdCpCbUqh1+efQ8Yza4/EOk7qDHwxduA2J4rhQLn32dr5QeGd+S
BadFhTEbctnI6i3NGIHQPtVo4vM7XxLKGYJISGwkaiZJtk1dhkeAsdyYwa31sAy/IxFZkR9p9U48
60VAr8VTzj9IjWXCcYHctJKnp6g2hxrh1jz6/lY5Ea9F+Y7N8J7GSrvRUU5vsVZpvTZgYAaWEonK
N3gaYFWXTZwIrsci2Hw7L8kHRTE+865ZrvNloK1zDaiQlsMiQnAvnmTL3GHEGN6zZFrh54vqPvAr
vINQgX7X6/NI+lhObLtA6FLv1ZETdPhS8lri/o6lvMosEE9RGld9yiSvmB0/v3owIb+1FZ74Xke5
Clf77wYuz+XqyImbV4sBpFPb+Te7haF+WhXCWdTzU+pylW/r1tndzsW/JC9H69klNvXT/HmSxWe9
eEjHfIsU/8/2UzIrp112+1rvLmPrTvGvnyrSlxx3jxvDBHnHPjy5GQzWERWmgrCrUHXGqbPWMcOQ
yIGpWxXh8z3Z+IVOVpZ6G5siieJVgcOkxwMC0OloiTIEVsbxjjLY+BlCkOik1wGexdwN1uS0yURC
rrn9AmN5+ncjUuA1r6pRMxfyomIPXfQ9r+uGusQbOB6romyibszFFhuPJFz35JterULZDjDUu6MW
caAqsQLKJCxvxXmyVW0ADb1lrWVOUmHzQCe4EQNDDDhztE4qemvoXBrw6VKmbFCWItZN6G9wPVTu
PeDnB6ge6k0aJoHbA0nvwv3L0dt6nCLVrIb//JxgSHQ+yCuwR8Ang2kIYVcBGSDwEADMhg9+JdeM
Zi80eP7Laa8YW9B/avHJZWC2eMHsyzbRsuIkkCCoH3//CENcaPU+KCKN8TALMUSYm2v/qLN/lWpm
B5mpydoxIiS57wWMF6/U/8wsed2rqTHRdstrjH1dKCKM1Pnk57ZYyUdcqHFmtMi3eLQu5Iykz1+p
BLLe8ooreHHF4w74DxsUQ8+mXbhmYvvWO0Srv/euPjZQig0cbxD0lgmgfl23HBuRutsLIvRJiXre
bz5FkmpiIImecR24i46vN+CGOwOX8EiPsasr7nsahKRE5muT991LGfQpXb8Tr8ZOu4ctX1jAbmY+
YES3N0ZgnY/eBz2UIWVF9yj/1Ozl8PY5IO/H3PUyYpRfMcd03Z3Dn5C6M/EfK+U8/riHgd+51rYx
jx+377ZtWGMCNBuzY5t79r3cQi2E8IZur1xDA2r2Y7X+bHMZsStBpHo1Q5ukgxTRQIMmy2FWOvhz
lVuyt1d0EDT8K2jeLzKzVzoLA7M6YyFSKR6nNRRhakNobqFFmDy3mphghq80P2P2AoskwRyYuXn2
h6B+e4RrKX1sx06hiIcDWp7EgjWK3cCw8sqRKzBl+i6/nII3sfkUfhRyrixSRM8rU7NKTRgzYgrS
ucYjocScsOil/nt6NpwtoarxakPT1lPihI2zqUw4AUjW6rby+qJDFW89/un3ojFLRzYHH8/0GL7d
FGyWYKJPIx/x6onbtgrlCclapoLXC/sxqNY5mOyymWsdKdu7R8pps9Kj1ZAz1YO8kBOl3pVQlzrR
FJAIcAgPDuqiiXhFh2hW7HkDNcT+W28u1kJJwU5Fx5rxpI1b16BYfeKOvbEpWKHtaUB8B0xxtZaA
OU/EGc9p8yH4XxF1Ayp02Fi23At4uSdSjvpa689ohkE3+zGeJhOizPJg57/o7dty1XJLNzTxgaN/
ZHG1QSNo5RCaYcM0smM/AM5B1HdnYw6nVKWDixIQZm3DsoZeEPGjYk+o8TYHNBxY4Obv3UN6qk2F
5lTjahuxRGvgRxK8UpeukSZso6ZjHfz+kOVaF/nVktFrYU/hCX1G6ey2wDAT0EugX1NZEssXVkjK
lZhIYPo6HBJdGIVxZJSZ+ass+DwaFQFWEgMyw636ZPZqRfon8PwOcE4rIlClgHlVCI87jJSmg6LL
KqjVlY5DBdebb3EMlHX8V7bPVqxYKVRkbDeI7JzURIeJV4N9i9gKkbD0HkUIF2fdfd9VdcQVu7Sd
R9YNvAQ/FPq4Vwd/Xi624mfLU5gfm+c5+eZ1EJ47yQDA7pqxNeXnjgWbshiCbzLjd052oPd6O2zS
IjpA++QI12GXdhqqmpTTwiH5whT3ZVi1ZgxEHiihtQgNOXuH0zvWZJp5DyAP5hUKXOkxSHMG+BrW
2T8OauK7kqo2cn6lFYy0p+ZPAaarWoxdgCs/HqbKFBpL7HtFdS4vLsMCY6yFNfOjhxg+fDgcj7Xk
N7YZEhu9aGiaTeqMWNAwuJF4pCuYR8T1hueYM23oC/vZTw3gveChivhT8VPmBeIcWIvdB9Nw+pY5
AReKnWHD+dVMT9DNkG/i60z5nFhZjQYCniHodT8u02UtYh7/5KTeyqP4gN8W8lYIwvrcnn7qlkZq
gEBZ+DJ6gM7IXKTvYmZqBYxhGhN4al0E/1BHRxOjq3k8YLVeqfCutj5vSA0WZYmKwrcHNa3miDM6
3z29XX6xbxEGmpik9zwNw9nA8R9AIijY//b1x+a0LlY/2Z/bpaMlCcOPm+S2aAMyS0Bum4rrliDl
t8JjhQzqGMNsoUdpJRi6SJXtxAZrahob5N11Rrqi7rVYlqd4r412yqss3+YqOaKCX2IkgS7+Wxqv
lG+HcvdoMZx5W9gx71NqLwVeUipBCD0p56RTo2JH0TBvwJt4zKrb1PJKLym+67luBRX8TqIBgDz9
2+DZByxka5zfdrOtDVYfrfctvB0hfQVEljDVl5bT5+p/A99XfXRbfuk9ginra4yFWWkM1mJ3FHYO
YE75JJ/KvCjq2sCyrxR22osP25A80oIyckibrJUWTCD0nwGsymCOJZ5EOcKuw+1i57QC9T78D6i2
P1j/637dS0qkOYDQtC21wACPMnCHpBk9BEsIEFoPuOyJIDAefcy6lp4r42xtEXWja2AWlLZLRcBn
mbO+ogHqS2kXv6DedOclSYG9SEKjYxK0GBg5ZOsCWhEpW9757qtsmdjPog0sLrepTZiMMFtdnmvf
PpihpQmdpJ3ilB/K4YJ/4MXD+j58NdGshwwyBdJs2d3W92maF4eQc68G/FYiSrohUXqz05hl2LUU
0evgun4xWvljIcVRrj1x0IAmKbnF5v2E4Xwdt2a2SO3iMB5cPWzE1WuaXJy3p4gs2HUbQejnS2oZ
9gX98Mo13TdRcgH6dj+K/FHVhZ9hpdK9uE9lTxXhqjvFYENsOWbC2QDyGVVt8ErEn+QUAPyzgpSZ
u2agapweZpVoqJcfGE2fT5ErSCwBgjEWl/WtFIr1mt/0cbx6P8m+ejmRbCk5aYj0wsUG5ZDyUS5p
7cGzz8B2pm9MrhX0fJ9qFAFRa6U9MXsqTtwcLdHAfB9MKgw1YAvTmIBi+nY6W5sxyJprCdeK2IXy
FgvlnlekGDbonV8gMQf8EbaNFcZt4BXekXzD0RNfaEgoFJQ1qnGl+pcDAXFkRp8MM0YzR9Ul7m2A
oY5H9p86Pxx4R6WH1UTp2QrTj9/rXgHGWHe6vdwL644cFPXMIPDKSaDWQ2BmTSYtqJl2XytR0kyc
c2oSbheW7LzOi63ENJ6CPwSszTlW96+gGe6kLKdWkOGumvvPpD9hk1tsaS4XtdfvcSkah9/llaiP
ES9LTfCEyp01bvW8wOnWgHEyxzkqeVeboZllUmWGMCZ/H40xvQNXwAMwGtSGpvhht++nwG3LG3U1
JVnzUNIwwNXs+NgJTtogv645D4Yww4+StpFwZGcdUNuoVw2qoJjkIKkdpMUm2qsllbriw+O+tmYO
iZSoxMjiZ2are3xiClarM3dUbcvUlRn0nIywK1zR3ikdLAgRLZke3gmeVY75HsUp0bw4R4tcSYvQ
jWVof+k0u60huMG2E/Lhmqin4fDHmeOdN9uxGXd2wHk/dxE0WvHxC9R5/p5hszeUjK6rUM5d/Za1
JR1hXI7GULsPyLJ3cYOC5w5JyalrSwcccZ+qlwtVtFKme6TWCoMTo14fnP5sfVWnN7+AIwYNL8iT
i1A1Mr0Y6u6lIJ1QlcfeLspTCHYhRP2r2sTKjHCG1oGk3j0pO4zWy0bLXFJWIOL7ltC1E2hC8zM6
fHxpJq89FN9HNJwKNbsPtP+IHRnTzfDCNV/hTtkqU+23JlimhiUp+raGsymF5JNUzn1JmqgFJjVD
ljgUPlB7JfklgYQy9fCMhb6a8DxqA8xDb/V7IV4aHfe4kur+F2wMb41n8tZLRix6lsppKyMqR2Rl
MKsw1vQ3anWI73il/QDC+5RywCyGkZOkJGUzhPXrFhVudCKHjVAue5o8TUM/GX/7sFczk7Z2rlIa
FotZUcS+h95M+7pbCklNDMI55fChI0kKmPNURvmHttoyf+VXiBnyy7ksF69SBZQ9QIjyrg8NyBUz
2DkTXhy6zEjSH2QOSJeCosEX2Q3hr4MMAw6LdBp8V0PIg+dssygc6UMZ067gb2q/vm9jAxXy/5PC
caFVmafQq7LwwcenSspIbTZP/3H0C4PtdbWjPfptFKYb1ssajIFiVw2BY/vo6w6T0J/fWtgB4Y5r
i4PwldPQSdasY08TVy6f++HFUJVDFm0Y05US0wcitm0gAMi8Hie4ZG3/Mocs6TNPq0V31/pRJxMd
B3JWOb3Tx5xyrk0V7CgWvuqlOGEjP62k6Xpgwuvbwrc0wEM9QTgYX15/GvQYR/wGxJ5QQ2XWGbER
cEaGs6xQvXWRYYMxJcsk3OV85WfZPDU/qhERG709Bub9gkbaKSPn4KV9fyKppXTU08355GATUpzu
tXOjJynyPOCVS/Kl0m81ck+Zl8Gdg0Ud1l6H+SGncPu/GUsqAFLJHpyaAHr/73tLDSMXWPHg/oNm
DkLIXnQ2rEkD/sjpl5dSF28NYE1m+XDn2gXyzVk38rHiHA46zrbhOhbRtxsNLkC4JVztXOljkFGQ
JppjN8MvR8xGhALO7FuC/BS52pNo2fJcvRn105vQeCeBXZa42E0HXjdGeNAEmYkZWEsDNtg/T+7j
Ebz5sUtOp+Cgjx2KDlXllMyohYqrXQ4CU9wKUsECH9jX0qQYvuC8DWQ9IGcDa2BHpxi7E4NimWwy
+N2FvTcH0wArPJiohd4JqY+TIUC1rOWUqYqXUmbfosOaap+TcjgdfvGFrX8OfdKZ3raA8vkOYPo6
qVLs9C+V88tf36p03Xw16FUTlpbTWvmVedel8qX0GI/C4xYjk6q10zwiDwPOlVaItcSFuNm3sDym
idTwMyN00a0cbdg9kDX4WV5y6LpQJSazhh0vqa6EA+3D7Gr1p0xSTpZ3+vXF583KWxZAWaUsjjAA
rF6RzOacos9bFm5WPj1ZYsFdPoTlyGvJGcqzC0WoUleiYbdHB5wBcXP1vT1lMRfX/jcjGydhHLPd
NuRvVXsxDAOqtL1PdfENRyXhr+0OArJQ5EQ3JcDaR/nAM20/TtTWdyjfyDj7/gj//oNAqVG0//p4
Asa1DMSwwb5wpDs4lq/1acoz8i3HRR05LpZmP2hHiFjXe/JyF19mojRGHIbM++sF0Vte6wMsAv2s
+WzhB3xCuA8WPJLDrtAenTMXhW2CaeFUm3h58as8ysphGXRsJJcFxksFTFYqVVTvCrL2D7sT3BBs
byS3lvYLDwd12l+7yy+sb4Dq/dtln1rcLDpcvd4eKX+rVD9q1po0RtCDahC0gSdqPCLz4I3WhmfZ
8mqqGWrZqJFI08Dm2vGgA9J6KtVqeajG8e7yKdlCQNQHLRHqTDLk76rGxyBAFukl0n1aBZrTd/hr
xk5doga9glFgVho8WnqIzZ3jPFASVrtQoZMW8lB4l3Dhs+2Z7+1ko/ak094OnuI1EtSDKbTbzPr2
g2cTsM8DPU+iyTQ4iXRXfDHMLezmZ9f0yRKl33KkXuCtj/RoA2jChh7po8/LH4e0tr9mQ+yH+Ljv
JoT3uapxz2CJjTJ5qQiSyZsSY10qKyY4wZ87jXH/ApHa/vQOPGTntr1ZgOJjW2z5zNlc0ZXeGhoc
DCWrsv8z4hTqkWp6DhF2aRUGxAfNokkcxCqZBhJC6DL9cETC6nF/ldPwfERRJFLYBxdDHULM28KC
rWlvwJpeG52thrGSgl6hTUqAbexne5/lw30Ov4UIH08pMimbtUXIXLsS0QTNkCA4eVHgky5QVqX7
ukM2RZvR7h5bsZNqsCFpQpm9Tav7ZajLc9S5l1WZgikPfZQHpr2iITGoGeR3KHRimpMJ59HPkaSc
QBVePyL2iRuColF1OnetrmwDO1s20TzFdi3XNwZTGQoAaDjPE3HkZyze4FUv0peegu/85fITyCVV
o5wpvN/dJk9cgjikwxNot6UxCRR5K+Pcv6WQqWqL49gbbf8AB3WVKfRXi54OgaRC3GxyZH9uncT0
xwPbX+mFm/gulPwjFwBhPOdAoafyHW4KZT/aX5e8FP82c83wsNUbZ3pD8TVGs570hDg+Cdrk0frY
O1QCXLMPVcYE2g1MuTR2WDFXsLeymuPVyqh4pfnzsTC6VVu8etx7w0vp6VcIVuZpVFPTJlVHjaL2
G2neAC9BuxqSjg6Dpds91AvW5y6kcAKM6zcEly1tAOtTt6BXzji7UOJVINNQGs7krlB6VozRYSI8
k3hXMV2MzNGJAVPibocjgdoI+wmhL5jGhabasFHLbOWtjLbSm1JLduGs1zIVKiL6d1ClSQlFLHpQ
ke2PgnBUZfvaoRhQF2HBhiskLJORcTHxc04UZ8AQcpgG+xZVmpr1E09OeApoVN9GUdICmRqB0vL5
d8VKePFoJQGDKubOO9o7XjR4xXy5haomCWBJKtwzoAuBYb1UnT1RzAkzO9zhaugNjjIRg0wKlTDI
XJbrDRc1ZQpLWJ3KpE657drRbu4kisXK7NBTDVQiBL8pNLLF/Zd23cdX8mTBoSdKzL9iDg2a9yjI
PTlZ0m/pUPRYadK1/e8gMtZh1dW7I+8+LqMl0ha7J3bDTh6sjeDpuYb2xdmI3FNDdCpKxXGtCE/A
sUae1yFXShIQ66omr3XEplLy+VMKgPu/+1SPBG9PNQskJ2HN4cDZtjSOhuJdEqI9kIpAfncM6m/8
YkSxvyf0QNXKNDPZeIjksTifvaVDgC913kaJthg/x31g001OBRdyzVs4V2htCL+YxZT0sOqrV34l
qdusM8AY1YmaRabN7fjOSXPVIKNaPCu0IBkzoB6XBzPBTLnAU+W1DacYT/IhABhDFDjTzJQJalYX
vL0XedmaeyxExbVhsFm+HdgaG2+9CulsK9ghcL6ljelwoIjZCt5rekB2bUuf7gE9XFWlbc2m2rj/
qhoHy0XO9Lq856n93m2WuUXJ6kzUorWsk3g+zjImpoI9Jx2Zxx5MtJ4fZ58QAMlks5b89FfkASD3
NZkWAe7DzTUTVcW8mpKqHPGCWHLoiCyfeWdpaPg+nXdSYnh20ynzJpP9dgy81mK6k4O0CulBiJ/y
UYqo/wPNkB96HrXelhVqRy9tLRgvtLwooqAsHc0MUWlaAyBYUUvyVuI0z9BiMQvlSvsUrIUSazkT
u7FyR6TIJg+WKloUmm+7uYwcdugxkX/xmv/GmBrUkmPW6BLxYdcWGFqg2YEd88Nl0FSzaXspznrP
f9yQI/vDhbKbTMFBq6W6nNSnmcEKgd7YOMyuaOD9cOCgpJOjk7dEj2xvWISU8HFFYstCLuqPlQ0Y
JhvV7kjTkUouFrr7Qnt9NB0qvMUjJFVqWeHs1f3GydsC2f/Hod+F8o5SJZS9Sr/lrM3OAzQozCGQ
syLBtTqYHCEDAhevdDkjWTz3/yzkXQUKdHB8XDF0bzIliXo8CoIHIrTWVpyxrR/h9IRMoKlZ1z+G
Fwoa5ewzod4asvTOpkugdZLDBNvXjsJ/Y52UBuQXw2lM4FPvqB/k7LGoX2mC72cCXImRYroTEoVm
v+9c/JEWcjNYWwgC0gviMVwLkhzlmWq7duD7qKwU0cEj0zkz0+249SH4+TN9XT7e2a8uKHP3hXSW
RK7/CqmPVEmJVYUGxtiiWxtuCagYVYsFbO9HqwLHf4B0r8ePdXLJpWjlj6EZGgsxqtjyWLG7d8dP
YtpMtviiNj2vfSdSXpS6lbZr76SyvqpgMcNBlb+uRmCPpfMcV+6oKeZFUz2nlefa07rp0Uz8seHB
1csrXaxuTA1/2FV8gVP31JDfeayuxYuR59655g/AKlxxXZU9eTRAdJKSfrtLfRuQq4XHYYOy8mmx
YTfrwgUI5mUFDJWPhhfoMcdyRQb3xYrHpVGWLfdz8Y4+0gK+RHklImSoe+5w8hFZXWISi420bQ3p
+c++IMD1avrbBZAHMaQKpwKebtjyhgdhmpE7OgicOjny18cP2EOoZXhR6NX0ZxhfZGGsynb6TDs+
eK+OxeZImpheyfTYoN2LOnuAMN6mNqzRtNpOY2U1YWmXPNnIFRrFFFk5GJgNBeCF9gZTAdGBDdXw
Aa6VGoy1XylvELJkNy0xC+n93PNoYAVrWlEPBXQifxwOhzRbNnps93fi54+iaGU/+w27KtFFQmBB
19FHXIkUZmQzpA10ruQVvXovmFtCMWr6/86FBOOcMLSbtQH9IzPWnvr0v6tpuQmHzb2uvCyGDf7s
COhURtal4VxWNAHP5oGQ5NVcKDxXvnCeWtyc/sO9dqYIgPHMjDPemZw6vRqIlgT91uUUp71Kd/mf
bFGludrieUwZ97kvZvqCfNyiKFZoSivp/lH+Kiom1/yffJlf4LiHF4crhoOak6B9yP6yAmhuQXHd
x0BxfUeB9xvbp0tD67V08cPo8OjIkop04WsBVFbG33cIGqc9wf0KkCau7W4POgkbAh2ip2kAWh6x
iK9OiO2lWquW/NaDTc7aXpGl48MgdNrhcawZNKlOyKmFqq9rvSUQ5NTS22IcWbVUUUGe4RiJmsNW
c7CINMg76blPcLTK3fxNurOBCcmCN0f07hOxqlXmz6l72adVLJ8wRKLjRg+Hr97KkMvt79TTkDrL
6FrRb+b7OEVZoC64/HFU3v1prwq1l8/T72kUpxUqA658tv4/CDSZIWQs/FBGjLGxXfYQKxt8GZ/P
6Ipx31i2GXDLJSZAFnaLn0EcTPPrchvwUBq9TW4H2ItaDiSTMTY6vnEzrMhVFCfkZ13htfUqFKFh
Rqwnq6UGO68B9mLRUOS3axF6GfiCqYBaFh4PtHitb4ltPhiTkAR4AMf6puwI6oGiggfkixeXavNI
OIXEwism1CaJK3rfJ7s2STezSS2LY4/gmQS1xLFE/g1/3Hq2gSMV0wRT1u2LPp2FaDQFSTrk3Jj+
UnxMESSfrOKQ7UDWUb8n/JQvMIa6DLzIasZ8NaTDzHrYOIrfPLAfLAqxSfpOrpBQNMmTiMe4vdCy
slGTQKhdlq5h4cHDlipKayxicS5Gs1jhgMbCQ2e+1Y+s/jLICa6NG2b4Qmewk4FQVtRwtfR1GveS
niuUzExQrabPGbNHB44s55Qk98yQEhI9TlkU5PeCLELSXnd8FnQ5TslCWQvwIWznbLTpHYgJCTvq
p+lS5A7GCiGiifEC7lPr9900wfYJIN6Aa+bzjAC/FZdUepuglPyubdHdQhMC1O4GjUaTMC9CVbqk
j7gzb7718Dz9qjlJD0WMyao79g8UzsUedHDvlXcm3elftBG0KIEkEuwiuBmvn9m35n95u8KwUZOK
UsdWZAamlgHm85vvFo79B9f4dVPB5mdM7eSnIh2kjH6mx7h9clwQAV/RtlU3rrWByb/ObiigXuRU
9lk3Y592tgznwc6hszP1CscLQkCqjmzjH9gwL/BuzAQE3FM5TZsAWRBa/qrynJPCWIwoBclTRuAl
eqmC829a6X4JHqPr4aB0GlK0GHXry+JhrXZid6u3MosZUhA6Eq2y0oQ1jHsl0zFWnipEwl30KlN7
r1usskn3Od3nuBYr1Iad/u4AwktLYrTDQa0rb2SEC2/4Tkr5/JqnVZ6mM4O5/Hoh5HQLlxzdQCQF
lj5a+MhKTSR8T46/qNrUzQjcfQf+2dV5QuuK7qt3j9nf+893Yk/5tg+sZOoaBZirbzKm5HyWc8Uk
4vgJo7rtNorO5+0qosI7z7vgbRDuWxPGrnKFsd5YTr1fFi6C/tErMHGZgww+txj0EczOZlyAkdWZ
7cvY0HzoxwVl6mbWUmqq1jTjvZ2Z+KyjNYVHSy9Jwm8uudRUd5rq579259upotcUvmGy8whe+7LU
7hlVCR2V3uyyntsLcVx8I0ISn+mTryHfn4Fdd1d4U1VBxkZ9+FXy8bFnbr6hEe30LeJCyGuoWhnw
Q1eSzXH1FPZgj329b/YOAfXEywMdQfIeeTrBHRTRV3CxTzwia4m4pv8Q0SAedNCe5OdEFM4EhEC3
rndmtbWN5DgmCYOksA84WyFkGhBBkD5PLkKnvji1Ue3/GcjP97EKnvtjOeDvyqmsxINa6ekl/BCN
aH0/85yj3fQC15KshuaAd9RpPM7rMisABnf0XRvxQ8PBw+skLJpIIiML+BUDz1qEtWCf5/l0ldQU
pOU2mrjbxmWa5txhrZZyyRDfgb/w4/VAktzLkswCWB91fHzhrruN8cn8CqEcjzx/A3HYGJrwVGHp
eUj+jLi8FOfh3RwQpgtyUUQqhNztn3htjOoveod8UAT3flNsqyo05CS1aPewT5N9EJ2pVLtBJ3gP
/3JlDtwzP0EpQWURR2U6+j6IHWslzL9LOve7+bJosOzEUWSuCW5Rro8IflfwvANAhOtB7xNxqt0G
OqHlDXsJO+ttLjLx+Z96aTtA+Ds/ig1LR8bWadfmTrHEvxZU5IbiPmiifR7BMx3cgxG13YpJ7pP/
NT0ZaS+pDO+w2gJ58E6EuhVuBO2OyygwcHrCbUl15vbx+bUIdTzhmmmhFFbMNS/0khmMtUA1TS9S
RJc8gMy1FsMQymUWKV3MY0cogVDXAKKuV6Qblyk3/Mt6roswzQFYrgo7wEVIa8KssyRd4B5TEHGQ
YtMRa+W2eZS2srVdyr9u+2Uq6/S920JPgEDsFUAqmPUSrUPewq4XzTNjurQoC5ms4WbwqVjB/NjL
Z81rmdkaczk7un5SPJjLoPkES2KpN6Tl3d2zbCtv+88qRPE7IJjtCWRqr+6xPtLqgVTnx3N1eqCA
UHh8RVZmqI9Iz5h8BDCTGH9nakBJazRrArxEBq16BKpLavuT1+E3Q+m4BboN4SC2aS+qCGIXUNHX
NWKokdUpnoGRrORjEpaVeCI6qicYEYuoJlv06mzwmxagjEnOYhxnucQZTUHtHEwGJ3Keb5wFHASS
1cs0BHFjGgKkPBIKS/6c35hzke4AT0V9uwLw53quLHR0brObZ8Hv+9f9bxj/t3fdWwJC128/gx86
3SIBNkNYyanZNMmq5tXXeITeeHdD0CL4rZyZB5Ma13GrETOZwx78io+SY4d9rRkPnfyGjqPEnH8y
mLtGYz0gZZiaLeCvHV1/UdJXBomyB2qlNExTDR86U0m9b4vWezSub/q1XFxmT/Ucc5JZh91+IwE8
6tFy1F5XOarfB1d/kZk0Nr15DX8PzvkHOQ+uPV3dO8M0csGpD/d5Joq0G1ZmizzW2sCGddpxCaKe
4yGVqYbejiIg6/G62vUvREFtXrgAm38WSWhIsv6hG0y2cPhmzwoqGmmIr+PSPlYI2QCUd3RgWuwp
XxX0fFwwX48P+v6extG+Nzo+em45aDm6tDeETd3s+r/4S6uGYbpnwVAVuStvjKcwOJ2RmeoSjKoS
QzEutxpngfRXyeJL0AddUsvxsD4E0C9UFWv9pqSqrarg9DvL4i4moQgFAGmhPosOBtP2nWT7sYTL
jq7OrWPXW9UO8WQ2kYN9L5OtCvEgkIQRBCIVtruO1pCfy59PISFgG9C4wE4lYlYShOYpHUyApRXD
OmcJC7SEW/8olsb0vysBf087skjOJEls7WZz8ITQ2tGbwq2CzYv4aUPQBN6yHz5xQEkP7Xpn4Pk3
jKmGTvgjo9HBMUzjcdEvdZlJyxIaakYjd583e3lsKVjePMFqxSOUp6Kuo7GOUapY+7cdOYhthqtp
3Fgim0Zi+k6dbs4UaSSQssJvtQPNFFRerdkrYrPy+2BJE5YAVFqCKZ5EydrwZB0iVFVVvp6Oovt4
ObJNPB8KATsHl4YsIKO12xcY1wL6O2ux5dFW85dkUORS+uxM0hOoiRVakCLM4SR6hIravHBBEEoX
GblQY40OlvEXpvRTULW2hzoa1QJwhOtCOHbuX9OW2te1+T5b0BvU7Tm4k9JsVvVIyGAmz52MSKje
D/Em0vjTgPlWyV2Cun8q9kr9hIGJdeFy0O2mbQpEFdalRRLBEuuowgQ3z4ex6dpwnLg/pvImojr7
vUxa3M6hVabGU6ij8d0w/aTxveQoLNng1c4TbkUPbV+Z0C8gKAY09AtEElb/gAeETFOOy+8PgqXb
quwJE1IgpKU2r6xMcy+HziEx2+qYycQEt00g0I5GT/y3p4rLL67S3V9zUuM4YbQgbGWqXVJrA1lN
vTqEX53E6hNuI4WupU9Wpl5Uu3Ji50t2rVRSNL6MkIIBSnNF0hJ4t+s4SzIk6eRDrOAZc95l3d/C
yUVCNVm9f1kYzi2yOxz+kT+KqPJe3vHvKWXV2pjSa+sO/DaFlr/+fkyi2eZwNLevkvGPTWJ3RAn6
sKb+yer9Erkg0s+M/qnwQ0xkHIF2uYydIf8BPcErk5zW0KI2QrXHOgFrIwoxEj5RakSbjwDyYZYd
Xy33EKgfk1ALfSOjBEaG88XKtzn41m7AG5NekkquEUdrSku7kD2+gQr0a1IJq9zJ2YXEdZAwE2yq
Pb3bgPYoYmsbAbrzaX4mSNRB77HIycJnhP9/zuhuoBybLlYrewNGJwcJue7+QfiWuNBUFPbm35Il
Ul0hlp6qfuk+lztBHChxLKVeTEzei5hSl1muas/5sAwaBxlVrfI8IYIWWfDbFtBATwUH0/dODr76
v4RrOgJVdK3WoG2/1riTXAt+K8H+W0QL+E5ubT9xsBz3aj1pHlMSPVGbHwLmcFUYaouxNLf/Creq
OmA49z8Vome5zgCweR0zboNkgDAQV+uIYQZEo01asJx2cUmxOjyTCQmpg6yzQps9lVmv/qOd/i2m
OJZcFgMRAxGc415vXl1Kz8rkm1mGodghQW/4gA6cdM+/duGT43I9ij+dxccWwehURq+6MaFfZBid
OmZDQF4u4lBn6E1COGseAVTjOHnrhFezi6Va+nnmCBu1KQUli01dVa3RdMvVHKrtJ4bn4wsocqYJ
C/BHbsb056jc1XwdEwEPz/Rg4auTc9OYq+zk19vMCMzEvdQpIZ7VwSrym/cs6TROdGjP4a1iQoB5
YhzP8B13PNGsWfgX/9juQgRI8mgQMI1vmF0ISxtc6o7tojYLiWouNlkiqOMYuhL7GM48rCaCbaWd
DGa/bHGaynrls27z5+R7ZkAt0QZjb+hGsVZadLYLLbykcUiSaSVoNFjhvoTqCmfEeXHQuiqDOcMS
XXaEV2DVnkIqUjw210M6RwC6CqZG/RkOQgzW8ooBqJ8NWyKlZa70qtSYF0E1wNRK/3ETMsimhFM9
dFiqNz1vznA5bwlvg7jYD9Ir2uEGqnd3rc6cV6P4uoS7/DW6VS81q9NB/fQ4XyqRdsdWfIItLSYt
XMdsS2VKLIvMJqCvtPd2uaQV3RFnzUEh922uQz1wpWaIHCQ0ygxboWYhscs4AOId0+uYRHKnjMvs
oawKaXwNPlzaFq2LHWQy6GAyGYJDyMljUMfisx/esek+mGB6O0ebmwYs6w0fZG/BM1MY7mk65tGJ
QXkc+HON7sInXDPFIzSengtAVTsCb+XVxKtPTGVTsXYwTo6fr4ZAzurzhCjSsoRLYQ4+XEhejWeq
Z5NGudvRkB1uacmxD/C3X7/quqREfAYe6LHC2hsKxu3TM4N/3tOYuK0K7zB3576OCK9bj1j/Tzso
ZUBUcCUsqL44lZneSGLfoz9s2jd9rbicEeAeZuwwG8gdtjEadkqdAW0jifWw852LI96AxVpEMfyY
cbTAg+V5QbWSzdPbMWheMr828ptiSjEkQsHOwbXKQnT+mVUKk4UZkqN8MiRL2Qf3GtT8YAYMBxz8
2JPwqooarxd1YR+ZroIhRtxp+THweUrku0Aqix4gReFXd0FRI1uU17dztGnu34wOtW6ZkFGozsar
4VFMz+/03GXvCpb/BDXMDvjR+6nXO7YuMCKFKi183idpXQ6+OTFRhwDWFqnuVz8vBXM2ZJkcdROp
mSkUKi9fevPRPHd8XcO4QSbIhApjksnx983qcimGNVHZ/YkRwBn4RwKiwa0kPvi6o7cv2juT9UKG
8yqLKjTYfUWcVS2zimUiPgZahuc9OUhagZQhQSV6kcieyjazxKMZjE6Abc5YD5hQU4NnphdJSte7
Dz9CQvc35L7655abnXvjQP7skRMpxUAyMswfcgudHs/Mx5m/tKqv4wqCPcbtf/qEqcLcbya9WIRy
NDFpari/kpBqvj8zFrMobTn9fVtl2cHp1fC5/sXehiCKxW4opXY7sEqdY9hkI5usqJcnkysNhdS3
s+TmBqXQ/nNcAo8Wh4kdR6UnUpZRyc+I60m3mVKE4GkaKW13FT4BEfCs+8PYIR403XKFOu6R9V5h
3zhlx4I3leFxAn/6J+ga3QfHrIARI6S7coXECbv2ShmaIME4Khuo4m6u+IYonZQGzfXPsNCR7ntg
ONEOZod6HCA1IWB3ift7G3lI5m+sZ93wQnhVdm++hLFA+F8eLfIkVER7+knVWb202R2BBErXraSW
X+KDLIuUqFiA1vzmZuQXZech9ErOPMnnKJnsEeboTeXJpxkEshHqVCwmITKCqLDMueCM2pxir8U8
afFzl3mWKzCxNSbVcoO862sxG0kTQTP/76CKPD6idtQ8faWyI/mYeZ0w/X+YEhICHrOX2IR38Qw+
gFe9HCDaMpf54XcAmru6ewQ9cWbumWzA/uqcyz9ArGyFoAIZEZrdaURpLkqwecK5bK0UDtc0ofZm
1U7DV6F+4ljMZJeyTElTQtYJ+4c2J8bOjc6/B3CBPrOPa4E/c/bTx1FC458/IlhxG6tOJPTbjmxb
GLWXUg6/xa46JLHpbvbI4iguBnEEipQShiwJOzmmRJ2y3JdI88p0fe8jMeB5/rTyFeeW0seePSss
DO1rklL1rpUmekFZyCzEbAMkXTYU7JbGrpg1oSAgqIqZbJOoNEnJhBRt+b9FL4byq9XFvxFawbve
Eh0iaUil4WslGegjiR71hh7ZdM+4tDiSE+3EYlHjJ0XfCf+NZUcAyEAk08gAhRVjZgLrGekCE9Bk
QQ3i21t9ihy1p3US3JahuSf4K4r94s2whg8jTjkb9PkvDRUigKKOvCics9rBNoB/HgmGsVlxDHgc
40w8mwKJsrn+WNXoxwLTTPOFWdirwz6Vm880KByZ7i0hHVaDtOWvnCgjkWPa4l9F8pKRDswfVUZP
VQvoPI+Kp/2+Ttktq66fWhQ3R5KWjoZIykbtkioFTscMp4u0HQ2OV2QShsTZeiyFijIlEISU4iEo
NIeLSsUY2w/+e8pVMKdQnYw8TwM3nYYplkqstVK4V0JcZwlqI1NWfyAxNS7qUM1fBGrdziO+x64y
XFv71dqcusKMO0S1DX/cpG3CYHwrDx3yTftkx2Z1iTPHxhPN9Kyn1NFX0Sa9b8lY7eepR4oBVIpe
Lw3GDA36YFK1o4gq0QgvLU/8EOeJHIgxNoqYwhzAQ9eZzPkoFDp29lb05oB2WagPJ3SHv59w9NcO
24h+xPDJk6WwD2kNCALMDbL7VkY+DYlYHkjQt9MkJVQMibTHbJZ5w5nXY86JNlPBzfjbxZ6guwgd
UL7dM4o+qZ6z7WrdBHg+lgu0Cn+XRME7TVpB98p5rM42N+g6ta6Hyy4JkHCbVl4YJg4ELV8AIEt2
TqoTh4R9JjpSydBREpQpkilGk9V1zkOklvN8z/6ou+7TB7R8miUbIULLrCDDP6rTFww68+B+DEGW
+rvZNK/ftbzetPC9+mwF/PfcFXOdZMwfEAMUPZUr7bG8QYs0Lq6CSZilOvpKUnQStRpFm3QNk5x+
G0O4oUcgcwoaDkBpWWUYZFuwfXsMscILA8BvlE4blBw+JPMhqij3V5rS5Nte8K/3q9o+UkJWNVM1
y+B9J87SFccuv0ohV7RdaiVMoAxE/QVAU0fXKKgq4f3i+h2h4aAk1x8ZIO/TqX6Fc6EEeQ8iCjcH
rG+yFhSnNNu/53RGMj+HzpklfunOcK4mSrkiK6BnZvzMG2z/ezsfRIMoDKshPM5E0Pq1GNJB+kdA
Pym3nFAJNPFXI4XWr3puj1zHrhEn4ViEmbnoaz0tCiIWnDskZCIlscrPCsDveDF05AYNkutcIjSU
dx6mrea/GsrvfAyDLRHJnfimcxKIGypR/i5IdEbAjUh/jJSM83ngp/cyf22QDszUp/ti1/qaTrKr
P/+RYqZboad98/HGTEm14zT4cTaJCo0jFRXPbuWuZjf+MQ2Y5ua+YpNc6cWlHLDEdapj3po/J3A0
2SPGlDU/7uEVs6NL9+OI9JDZ+Z8yHtw0zi9LFPxmCEechBW0etMfZhvQIH0rKtgwI00vTFBkzQz7
f0DyZiPdhVi95kJH3mxDGaA0gsRhkHddse4ASYMAc/8pxGwjzjbowU46woICPgOc/vntvQJjwfGV
dJZE1Jg26KSRdGEzm82l9cL7SPajU/hJiDAAkWZspTpBOxoJMPQI7GpYAqQ46VYbdOBPO73eRL+i
lyNGWPRU5jKEVS6f49KSxiGu5sG0tKpuAoh24X0qNT0qGTBOBWmj/x1uSuxoDiAcmniEPDmyvITW
UQ8TIc0rCNJsqrX/M1qdsIW744/yI8q0O+mk94aHxhrKAY/KIiB3KldjVOoi/43eGfHQ4zAUnfa3
RSxtRG5llAG7VTOuuLm98GeU8AkAUyGyHD8yVtBjS69CqjD3htOSgPF2bWnrszebs3MUK4EEDiOk
jdzT9mG3cyWN3wGCpq/62vxuFc3eBMdN/fXffySsihNGowawwl1bpt+F4ORbpvvGhHMgJFwU0mRU
mb1lwMyf2VnlABTzXpaPMUtjFUWNLNKFxNciwaV5Nh4M+LeuavGTZLUJgy8NcyeaDPG5luL6DwfW
8zA/hSZ1FMb7jL/DKrf9y1YW0RXIEyGeWezs6TqcXopa2ncTAuk2ExcSeFtC924sWG1y12/M7bKT
Zt8N42YadeYHgCMUG5aJhuP4QGe7dwI0vrfl3OJuycwGJ3tD/E//6mLgP6yKHjE2IBmtLPz2xznj
8PDxrwJLITs2WfOfM/A1QPl1IxJbRvc7oppLeot4UEStVr8R4HjyIoKAFdKgTc+ysBSQwJTKQvF2
1yL8HyCtlDNm/jUjCJwLZT+IeVd3kSTq/CMHY0cWzC9IAUQVruL1d/dqFLvKTeq4IfQZi5Vsst5k
v8tEReKFM2g252Fo51IKqm4oO02QA/LPuwpw+aHYbUiP4cnLwHott6G23CTo/s3ajwI3PXp41VXD
wO0HBiJ1wr6a7C6snJemUOJyw1FbReVu7PISyfbYAw6bl946uAB0xbSZZ26XvEoAsUew3G+H7Jql
voET0/+LolfuYwB+39istR8lUfzMlsw7SHmK5YQTlgDYORzq2kcoA+Yy4C5p3e5QOpTqrJwQK9CI
bYCRDwEhnCh6yky5djXW7S6JHQinIOM+zMxplJ3yOrET5C1IzRfYn+gOz1qvBinhtrGabC2CIfWM
c3O3Xa+k4khcJdTxVURbDECRzpu93xTuLNlk2+N6wsE63v6lNFoSkZMRVUEQSKSbFUmYqDoFau4H
3MZFORgS180VcbLoFtzsdKGeQpjhfnP0jzdV2FflL1vUG/xRW7YZAQUPijOk8Wm/GrLDQergneH6
MVd/Ct4MohNB/Km9TZfLo+tFi4xK/29qLwAXTbz01VVkyrrOZVNsvJnyeEkkdmVT1TCjOmUHf/ca
fy0Jxl1tj+FwefSOiRNlrvw++kv8IN+5fOZw6ysBcRT4ATuF4tLLjyYABFc7fe2IExmvHVws25LR
CbqtTF6oDd8/qnuESrs9+N3oActQOsZtS5MLd1iSDsBB5j7ccD70M2AdxDiqnHcPAkk0F3y5wGCu
ByClrnKgGd4Rc1OKCZJSh0LbrNKWZ/qIznw5U/0yLV+1S4d2Y6Ld3IPLIeo5vNOoHKQxBvGbZDmd
h6IwUiWylJfTDInBM+NiCuVKxhgo18ThXNPZPBzNXoTloacClCHQh/SmuKN6M8p9QWntUweVJd+B
PqfxaB2wRBvHaNHaXKMdw6Ay1B6HvyWWewdIOJEGJMoLGzKXbSNIi12CX5blGGMlX5LcIw34YV2e
UPln+iGPtYx03KHx0q968zb/9Q8f9gh6ga/kGb8UpSh9HQihlhagiWsT+yS/DF2HfMofFUUIqP28
Hep6oRsjdwP/Dpx9mrpcKWPzSWu0oQHGyYU7P0mpsWNC+H42CdpofXf/RBNsiEHWaISvtCmpRX7h
zBrfIKLQK8Qc+nPL7gt+XJUQmgU53DdnjZaaQ4ZJ1k4h/nlBDfSJfV1GLAJcjH1HIs+eDX3WIEeK
77jR8p7rFEHGuGwAa2U8/Keplk+Utefeu77yYc/ruedVwfD+lAOtvZcd++Zco3Qd5ATvGtgjDcBi
gdt2VGBFSmONVHg0CmwZnCl7T/K9meV2PlK/j+m59sThFodR9vj/3t9oziYj6+KVLTtFkXjPWsP+
kQczTz2rNTpt1GcVcUxCnCFx/n0RsfR48C+Uc+gE2j54VB1aY/hUq3DBuIm96oOo2gv9EoiVMgBm
w5Pkpyu2P1jzCNbN+Ph0pLXTnkejvy4vsDvD43i6NxX/yUWH1rYcjruZEeL5WrwCqDTy4wqXvOnn
H6rXBzDo9hTMdUQlPjaIbhgBxf3nLArz+NXp8qM/guG0OQFpHwmLuZYM41PrIyrrNSN/fijC9ucx
IImlr2MsfZ2lauPLa9rM3erfpV7LHw/Xzv/M1uyDCfUjvoW6DF+tZoIzwLSG/njtgf7oXo+MdazW
5H2KFysoOnukoPwfpkBebPOSVLjDA1oBx6hN4+8ZeP79a+w8PkbF8XwBu9EK4eJ/+OTBUdDe2bsh
xjjc68lzXxTZ7XC1Z/t/HZHucAnB/UKcK8ofmen0V+McHFdt911n9PGEnzWZ8d+QlPFFfV0ciVuk
xkfYrj7K2sJ6ehGDees/aPXcB7PrY93TmVwpRPshh4GGR1aY0XiI0ebsejXVH9SNdu1xU1UGHxb7
hzcq2M90Dt+B1eaHKNLKIebBMkluaEwWFvi8j+/eC2bZKv7aYnmEMPwXdLjIB41uZPF1MMMPhp3T
JJtcpZ5feqmlIq+jfJmZIH0+kbPP2G/4qd1bBbqb0mSc5WzQcmEvGDxwbT4Yc5xNBujNMupCRBuY
bN0JieHyCdElU59bWWK4ql4k4b4xMokEY1r7uF0HHwnaSxGxoQG8MSsx31N6pIo4vmxuKx7vJNpO
ehdcQkoBG8OQKOQwHeiGqC+WeXhO3MUxAzxVsxzzPXxTjtOqGCLN+t9E4cxmvOTJk9bQpY2LhjC9
oJoKClOZYG4JihWv70iOAmBlPdsrPbQr7+PjHePnS4OW7vxNQmCm9wJJidUBJSWBLtjR2dbjLCsL
xMjKc5KJlTUzFvBOc7zGiCBwipBrRnvyVfrcgKXsMpN1wNyDhIn+WeMRsT2Uwblfou2wnXNGh2lh
xByc9p3FsjPSHg1IQoiAacY3f1OPv35vVkKhLQrkPqbmk+0KqWb1E4h5le46RtGAG6/akoNArvSc
9ZCJs8IEtFt5zm2DWw0gSVCSeq90cXWFuux2x61PpIl9g6RhQlliFfhYvWypAhEuH/CRrKSGpTd9
V4ULOyGaUbbuLAxLOpm75ahrAS+TU0H0NPNulcfeb10NY8Md0yXtYMtiffxpXP55Phh7dvhqKJdQ
wiK3oNX3YPvIL+ty8TdhJJ6n5YYnGhGvvtCm4tvMuyeSbEqhpo49oipVx3IYeITBGsB9HiwrL6WU
GqrGIB+5+GPDPAe0HcaE4+kducmOH6wOH36t7BPT6sqDWu5uVYs+RBSlPQ3UFYHB/V9O4Y4KzVRp
N/3P4m5+4zWnpa5ynU0Em7eskMoggP3NIl9Ie5/lWwwn3VL6jO1r+Kfjx+IOcrgDyNIrVa4h1Sow
EIldldpS8HyePe2wI1wVu744QZ/Iq01mcPIW1jxT7wex1T+DSpckwjB6ntTeKdC4KqA3jeJ57PH7
KGlfo3Dg18jeyh/3cndqRe/6KNsRkcQLh1CnVQ26C9TmExkHSf8hI/YgktqBfbHDREbxILac+Up9
QIVfB99td1QI8OKlEhv0oamhVIRmor9Ecm5VinYtcn8nOJcCa9YMoyrv6fMy3ZofRPZV37oIyG43
NgRgaMLRlKs6id4TMvZ770MpYL4XXVn/2lFecGjL0N/UKuLEfaXOqKKwAm1HPiqUWhjqiVyBfsTL
zHIHaEu8zMcvNLO04/8RmRZ5bc/vWw81Ct+Fudl1FEtqKASDBdfxpLc4ZlIo4GgW3b86Q1GI5zXy
v9oq+qwgpMpq2V7Jmy+H9KPoKk/D/MF+psLKNNyPXWBByQg3XD4AfFmU9ucpgEOSA5hW6nWuvw3G
fDMRobGxJa3ZSLBdUWq2/70D7She5kKNn1HTGaCOsDYRGJKCU2Ks7OKvHkdES0wuRQafppFj43mi
ela65/IirWwjnfrOoG2BtSoPzoJu92RSB+yxZQEMXv6X0EbPl73cjUKtVzZoIMEie7IGM6cWlX24
wzRg88Bk+hTBhqyUUPGhtRBJIlbjskxcn5rZr1fEBVbe2bI6+VuVeXi0SNo5H1q0OLPdg5lwVf4T
iYGnJDkyFCbAxjKyVJZhZo00Wx1mz2+hrWGGLbdih9W1yR8rY9BCoZXOkrgYLQxaxikwgUjdtbU0
M+riZslwsU/sWE5NH+jFVr1xjRrN+sbEpHKxP0EIqZqsYsUSIKddlb8LInDdEKEkt+3bgTF5rqdW
KzKSd4uCmw8C6n+D9T77yZhnmu8y88WcPWv4TfsouMC0e76ibmr+4X6G41nn903zq8rhUfvOCsyi
KyoZCq+12xZPhgwgtmi4l14yTML7cs/jMrHUtk+fUlVKNWTkmPjMj9eXjkFy86tiSg2sj7vbpdIn
2SZahmklPY719ubfnz0c5Fq6rSR6QCrVI+VAxEWLXp0WLm5W+yq/5MPrZOZ+0PwCyGFAMhz13apc
qQ27B3d2ikTYee2xEdgMpzlETJ6wtg+/EYPwQwaOuADWftIbLB0pr/HVdb3ksJdihbFl22N4ppRM
ygxGoGiI4aItOmmgN+JKhUWqra3+gh9fl40KsLtQwMndzlRoUgQ12n3Itt3bbKpz3cba+savT603
9A0PPRQzWivhaBOU6i+tqtIcMvwg3kAsPcVA+3PD3Wuk9QaUGrboJLaN/9ttDzABMjQZndGSLJl/
F0ueHZXV8tXchTf8zIk6NBa5OCdj0wwXpSNCzg1kkIabzsLtmmkbUkM6ej6mB9IWSmiZqqkaE/5H
yvO5uMhbOupuZrmrp73HSca3IhYah+UArHEWwTM7l8Q1DNW9q3Dg5AxQRMZyAv+mw0InvmdYT/NA
vY2Bbxapg51YVZrbLG8sm+pyZJEj6rEn0ajC72v/GqBa5N7mkDO9TB1af5nRH8CvcfA1m2/Q1l0j
7JtTsNoMSAFrOM41STrvSyaUeJXhbAc7eG/3sgopTrIjRpdRr1L0+5UUKtkfNUCgEuYbhcVOqH/Q
Zs5R5ac62aOhvqN4SWq/duqEThSjhepSITHTRW7g2Z6f9PmJZu2lRDH4ZtPdOEQEwdmwoxt0FirI
H4/ZyaX0Of+3OLdKRmt34jAmAxjt6f9l0F+80mRn6Znn97fb5WKpH+IUk6fA1aFdjNO8Lih6jDCe
8YINPTm1cVCaY/0xn07s+H4DQIr69PqW+tYqzawRI+dV8oseZ7TeKgx8ONUPjv17zURGoCcDtK3T
QWFLnE/zo6hP0Yft5nA+xX+WAVTTBo4iTr29JT2gE6cPYqWJ/MzX6L8cPKEeYCt01uUE/JMXYrSz
6pORNqJEWJWt3iDI7TCLZJzX30bCQEcEHiCwVzrVIJnq8UWLH2+U/lbaHYQ4YGf2WIVp0i7Q9Qoc
QublUzGNfXd84Mf7cwt3Xd0mwRn9xajv/qMnZ85sDXOguNRoo/SutTzOyma7DimKxALZQURWrM9Q
BO5XqvrfPhzDs10wkugJ2u3kAhrCRxDP9KLlcyIqwoCVuJsyU8qPLMSHjm3yUr7s3siv7upzeVpr
F8LwiQbB9N5u8JhOwFZEKrAqlk8LjcdbvpIq25xT1dP40NtPqCeW39H0QiZBCzO+uoZZ4vLhBP36
DO0E+vgQ6ysLm8MeA+/B7qgSRbWXfujvd8QSR/+d63+WCuwII16DgvF6VAzAmRX/MPD4is7XiYIJ
+JSgq5aXJVhphUlpbU88LyuKE3R6gRG3B4JA1EaizwbrOPPfjnapQTyAg25tAYIE277sUctUo5hr
Pfnd0EbuMj4YxfVs66BWiV1F8wuH5kdNm81kupHdTxRlx+WdSjQon2mjP6/qzSfVT+7wUa5q4pMs
qM81LxpqSVHPsXbvm6mKgXa4KixEINPaRmQoEtYCnu9kWqKoLKp158EwYh2t/StVyRi+uoTFM5zk
wchWnBd8O8jybOUffoEHyV+3LbVlZ6KYI3M8vJWfclndgU4/vJfidvf84u7tJzvRVCnxWebAuv6M
dLsZRXo50LrrbobHvtLcAX+aLWXuh/Hoy0wxG9nxsUI1RpCoMnuX4L97oIbFUqh6j34kTfzc/5M9
gbuBcA4mh0ygkuXElZCNdBZRyt9yYOJS8W0Lk9LPiWD8VjtNMaaoNoux9v4NJ+zzsM8XPKbDIH3l
O6smW5G60+JTJklLAWKgRq5Yiut3KJBAxAVWW/v9Fz03ZF0Y83WEh9QuozFkxMr8MwI6T0t3YvwY
c1Ldyrw2M7/NbxM/V2Qc1Qm0QE9kniYyQ54CDi4MyI9LTzCfLPuFXnxE1FCZyh4bIvKGeM6i7S6K
lML30YVUi6OsKvn5cKtGU9LRkLmbikYjPWvLk6laUikvopnyRj3EYxMCzHLccrplzTCiZCgot+V6
/+3LC3lHT5LD8zSa5ZTxIp2k5+p3kvEpIsScUMrrR2oaWtr+t47BsZBv2xOD1DdyFpMLZy5of9G0
0O6diR1M8NFJax8unCd15/8e9732pQvgibwWchxwB0aNVWUWzDNKr/ruueJ/sz5jpXFKO7rCTPdl
wGR1sJf/mscukmse2dbzAFDV9z8J07MLF/pv4DQssDEqFFskF7LOaUKfJTyuovG7KlRnPDg1pfTW
gu+FAxI8e4SRAZix8Uzb8xBrouv2UszrG7HuInfqTQw5wF/bL+g8lmnPz1Pj6LDXNR22R/2zPcIf
fuOReavAl+MB4hW7t7NkojYMoJUhpqEnaktr/QSjMYyfOYTzjXMmxCjaLLwHao3vZ5v4ZzlVSba4
sT55MvLfei6F/ka3s5RuDA5yiZ7pvuSVb3/k5Avckslxd4qy9ykM/RbX+m90z1d2o0eZFnYaaoFk
iCYZTEDWyHPvQkXjrffcyq8rGvaWbQr4tZqHIuUldwSm0QM9v3c5eHM35U7a7oij/XK1c7T9crds
bXlJaWyuoSu0IIdPbexgmYsW4rLL+EWtBLBHnpczd1JzKLXmMrrmDtzsV3r62f1OaeCnBlcdMt+F
vviyu7+0oVXd9WTENBs65orI13D+37TvsGMeO1TQ2fnVPchr2wzHXT5/14vQvdMxe4dAxElKvvr1
ry8msye1NJjQ4vL9n2KFHZyOhWV53ITrGcyDEjWsFgmx4glD9p4/hlSSmMgNLxD4gu7APks6NYgz
JndDV9qqbQH2kZJ79iiu1CQV8jRLYtONYKWUcoC4E8M8TlKTprhSZC2y3FXVRAnbpFPtKKzx31ai
qANB8zdIMwzFA32qtAflX4rObrIqMQlAGy2Klvv9bocNjXZATNmPoMup2FaC1jEdAmLo1Z0wP8ss
9MLs+8tabWWYMQxonvS7RWwCw9NYEJasrP2UeaU5x0vJtbhY6+BLSWPvKf10ceLXyl2Nlo9j5fmP
MkzU9JffaRzUtb4TMNJ0sBKpMrk0KU0yl0uReHYkhyuFXHZX+4fT3VDtxRb2Ha4aCM+9L5V1e/v2
evg+MPE7A8VDMOz3r4h9N3FYMJJjYlK5zc+mKucMvjj2Qlu7toHvkd6WR9jUoROdQQXN233/JAW7
dHcY+Km+5ENRREpJlTC4pt8mBg1d6mfooKGDNnaVjQ2ZOjzU3S7l0uZHiHh+S8sL8o8lnqVybgxy
8uxcb8M4M6CwpK5Fz5Q8V5JHk8zjnkQ/LJLAGMEXpE+BvSM8/BVpEYXFBDxnZFfjG7eUJ8lnAvnR
OtMTQsw0p6I+FhZFo7o1dLL0VH+5mGh2ITEQ6AJ4v4XaZo2E2WNmNDWR1nsfPxzwH/cxg2lUQy1z
CiUU0E1gmRshaiOz5vmOW5MQflA8swIr7CjpLEaWFIiBywXPCw6u6aeL39u8O/7962CMe8G6usn1
VKeFLH0vTzR1aiG65q1OWy+qbR0YIaYGtiiFG5O2KNgoXDAQZ2DqMOUwvQj7vcOXoMh/mKgJNNHe
vOMG2OK0ge4KMqeGBd2lQE1YH3YN1z1tO71+kh4JxhgLG8tyiyu44OlGwCgEyhpQGpkV3wcb0IbS
oZnPfgWFhX0H84FOtLhT4NTJuhsrDwg33VmvB6zVcaJ/CE/srgeo2EwZcMjQSHr3uDmecUnF57pH
8KGUjUhct9V4dT3OL4I5DYF5LDhyhnNHhx3blLq+7CfonzOa6PSi1mD5jbyE8gWZqUUvZTN856M+
Us57Ry3KHcHo3wD01QAIyqUvj6fC0y++W7HvQvUuXo+DLP/9C144aHSGfvc3ROM/+xprkohmbPaW
K0lr0GlKO62KDjczewlwKj/yKkybdgFR7TEhzZvmjhdDEOChHw7ISSSCOim3UB1FxP8+0adgRxB+
7omnYDwHaO7N2AgYvhB5XWPCIWxyxAQmubRwL12OfrvXIv5j5LOZnbrTkfuZFVl7C3DD8WjD4APJ
RUXcwT51N0lI0c9Jf5MMUQ/92Oj1EpBbopcaRhyo1/m4812v7tQKVfwAKDErqRnrco91ZOwsW7zy
de3yhr6W4AQpojcNPhQTWccp6kyjceLpVl6XSQjwXPc46/1JZwZc2P0l6Q3EXYDidmfYDKKI5WBP
LgeQsoTNoXvnkEhNW4pDTRYR/EG/fAKJNed2bLUI+YWm47KKy5dt9OQ/+C9aVZhU8eytzbI2oxnM
kUc6nKzvR+1kbuaBJxknaSjeWf93R4zlAkNdX6x6hyeTGGx9tklR26InPKKvwPdnVkMxvasmRYQF
+Agm4NEeuYi7Isqel66o8QG5GfnyVh7r1oLhkWncJxh5W1T+EXsJW4DlK4pWjobo+b8h5V4qbHbO
Wi75ik6ysBlGMiqnCjrMr5XsikfjWDZUlh1/6mp6jfF29PK54cUbqP3K8JV+8zoxwX5vPhri1RfF
XJ4vPB/4oslSyzD69eOjI4+pgmOl683ecSgV1l5YHnuupypMdEAMjHkNshk5QO/Sgwq+aQQ6zRdB
RTymzzq5Mz41LZPLifAsoU4UUwBztGlrseWiFXey9pmFAOYwYRUz39PgAg+LXeL4+U7Q7LjbS0e4
FdjdQaMckeDYYKUaqs1wIr2MmSxCSNqluCt8ud+uOGoR3xEJVpyyv9uZ8Bj/WEWhd+HiER9P/rpa
alBW7HVbf4XnMC8TTAwIdq825iDtPFtPP6fblaiCjBaEtOfvdGnsxTQUtvKg4p3P5J0ESWvwEnIs
0TWxzXol1TI60PJSpY2cB9s6w2TFBdBFG1e2Gr/SmiR7JIREVh2JXz+VnN0eNrM8LpEh2p2VioAX
wEcCniiWxJnLPf2JM8BKRkpQL8Jpm3PhDHt/M/X7sc+GC0HVsWtaM7LAvIq/KyLtsQH2ywLkRDvv
w+bhqe2FlIwfJWDR1klzOYy5RBzHDzgSuoET1SytXBmI4ZK72RzmxwEyXMa4m1dZafn14kqdnaCR
zlmNOjJcik0mI8CIfxLID9zaWAMdBTloBdfyrjLC0D5y0BGJ/BleLoLdwHP+VMDBxSul6/loWoRE
WuW77BAIAuxuSCuBksSxHSIUABrhN1WpwQ1OG0SjHugBAVOx/FDGKCRhkqUjPPB9rylDgm22lP3o
gQRC1TjQRfZaahjhXYsoFZ6XJmWmJiEBlwSBil1Ne+aDvZyzxjehd7GUZDTnTMB4noxpJhNzo7GS
TKzKssDPQSlEauivA+rp6ySzyV5nKwZOUONoiDyYN0Zq1YUUqSRWyomt4xi9gq1O7rFhz8/wBkfh
9GNvSjLmxsnX4Ua58yg+Oj+J1o1ielpRk2uLb/Uc40qQlhG5X0WgsdQy9+OXGXD4rLbW9P9FTEFu
Rf1u077Ba2SSjJ22j1rqH8tH+ue98Oni2YVQenQc48kQ98VwpJaSu2naA7SkJLdkFxAlgISljSrb
NE3sobleNol2JCZWd0KDAnT6wbSlBQyNwRRbimy1j8IvqgaddqM7seZrGBJXJvHwIqZkEi9Q0Bh2
ESV/FRTaUg/kzaHCSKwZzvzH5A+uOPqSzN9qC35t+h3ZwgbkNjG2mGowCdx7RvV2/XSDqhuFdRVs
ewpTVW+Aw9cWl2bych8Zcs2WCbiIflG0Lfj0yhpoMcHKhwr+5sm2pOiliRfrrNhwKRIAYyamksk1
Dvvm5DVFg3FP8DNN8U9K3xYKZg4v9+wkwsPxdQu6rtys1/UEmNbLDVrxTP+uVtrcF6a3aGENatZL
gxUYj/XpmC/AVYEgmrOzd7SxUXJf/Nucj+XJtQf8iEKmIXDDegdCrfRUOxFh+gfKmX7EmFSmLVJC
bMK4wA5wa8su5QfkwBNxolPSLaaLHiJFBpX69VjBkspkGyDsUnBXJoT5RovOMSzX56KybPcfHD5l
zOewqj0laQk9FtJ31HOmsWHjRb7k+1HEBlwpPaBT9+f/qabVT0ksTM/iAj28lUVBGsxgwQaVX5YN
ml6HchxtD1yapyKv3IYgLNQibCzsekaiAdp2r3e6FlqO1aS4XIlCGNxYaByEsA4suraqIrL7fo/1
QUxKVN76ftHDJ/ZR1GAeJ6fuh53ty5JpAR2/iC957m3MVBdiDDStBU2GEvSAeXNgHw547soXDLvk
8E19DdasbFKxtqp0hPxe1cAWUWinY838lTJ4dnA6/y8uQVCUUyaUruPM1eESGNkfh7uKGyEuihdZ
Hmx88E2yqFmssru3VMrcOgsHm/9fqHqhJHJzxJgQYXho1g4Ywr0Wk9sD6pUX9IeYxykyn8bcuGN5
4NXm4Whrg0r0xzU3K/rUbgocINgwyLx/IZUJ/GWJZ2CwXaQT+lc7p8fR/JdfLSm1/jbFOibnOno8
+LkTlyXlMeiuBtqIXbbXgpwWwZO9okNzO1Db+sacpPLSq0ODPImUHEZ7ASgmBILDdEud0OvogNiA
JaPMQc8fIpwXUY5ZLuZAyp7/srOgb+eGxKdF3B5NHjcObU7NK7eHXAzLwf8DjHwIOOedcaYWEAIi
tutu9eJ3mUxsUZm0yElrKc9bKv7RVpwcam9R6G2eHGLiQBINGPB2r6cM9s2Pj+ekYWT9zHR+zcNO
2yZLPXv99vmarGsvLG+9Pvf/U+O8R4+WWlGXfpWnqql6xbfKk7tyKO1FaEvijFuuejRhYico28Nr
qG28yIwke/3lNajIV9swcR1iFo8mevnzFnkTlDQGCuQI1J8oJwvDobZsu/SsdUaApgnvYgj8dAXJ
mRpXx/aPv6zDx0aDkt1tlivAq9WYi9Kz2b4oRaC4sBGIiHYKJwbpT7Nc7W0lmYxf9UDiS21RlTC2
0V2rxy2xe2K+wGIVhmvUR4xFVAfcYWBflN7v3ODL2DljhYFwdSGnQMXaGFNH4w5Jc8swee6/S6NW
XAFugeXMmRxTqMfzJ4xsCXcImTzRD+Hofn0+2r17iMCAsSpESnbn7YDAhukA7hFWo5irGCJdzrtB
yM+vApiT8dKc0FMjrD33xf6hNPkxXpmZNwoj2AaW3BMuXqKhcGUVHnQvGh+p5VJyTKFIsUwBzyOw
mTL5X7IagVTkii6dnWh87+32SrIkLBXiNYxdWEhH5G/E8TXWBcB3+Y8YDhUNAWBj7OIdHPxisV5E
vqMt1epdO44f0I5tVMOdd9sKotX8I1Ifp7QoNptpqWUCU1SIzzgp0cfW52zwDbMjEP8i1Lgawxbm
b1DAeAE0q3B8hPXWAJNBtEKEi8icOHITC9bWM6fL7rPiguOgzYjVjr33dpcz4iRrEE81d0FTtsSh
2n/p+Z0yB9xVm7Y4cr9/Ld0OFhtfglTmtiGrW+PGlYbUzxRGT9QZwbI5D3kOj8QuN0zU8ZpYk1+F
T1IXD0UlmT0Bpn7ugTvfY3X9IsEYYgvVS/x5XFbWbaOyiSrl3bKaaol6tNsYKeXE25BygkYfSzL0
7UZorkN00/+H2PxTo2v08ig7D2iSvN/vdCcH+MYQUtQ4s/h2rQHo7bsbm0S814ohwR1Zlcvsy61V
nY+JTz1QRKB07j5JDnjFzWnAYZIvQ/lbr1YskrFMkDm9VdlqJe0QAgwTQJGqXyIIt9DA3ChRIsRz
lHg1kijsDl2B3uVw7RMC3vyYffXnOjQszcuGX4jC1iK9mn8KtlzGAlz+U1SWB1njHw6vB/hM1iW5
fu75cniaDDGHmYjZdbH587BgNe9MK0P+e5r94EcpKgq9bUKrgpHS13zMnKCArem2iFbpeOO1uZ2/
CO9XsGqQJVmkJFO4TDGAfVnryWKVxu0NUnXC7/fKa2Z4FQoB90m1oelPhVlBUnVHpgruJy0I8916
8Vu5/gQlc7HuXSvLsjkpKoWzVjgyXpr+O1WoVnEae8E2NNE2cGJ2DldEicP0ZecGeJzwYWRaOAqp
MODke13yPL03UkHvj673veeBwewmpWwb6u/YVTZhLtgQP0Gvz1HVna8c6TxAl8U3mnCC+utkqZJc
01CAL2nRF6oiuuDBFXj3qYoJ2qXTbPVQOGwrawEqCZpm5crLfwD4emrTZz6qlxWteQ/TptO/5FVH
nkLLYty4BCXy88x90Zl54wdrNJN7a6Gy8iklUy6qet8PhQ3chANEIKMCMal8wG1SePkeBKvq0IO+
cRYcKDCfi++GQO5Z2WDyFQSyhzmzA/t4Yfjq18NxpVgHeAkRkP/THDKGbxv84nqnm5lctWwTdJYg
GNYmVdtFPXckmBT8/YwufPzS5jkIRE45+kzOcvrk7a4OTRVi8/DUJQE+PqBe8VfrIQxWjGLmCrPC
6Xz0inLpisBwcQqqN0ZIR+POaK8Lya6woedxw6uA5ipJn7ZuvHVm9qOYTd1kAX0ty/0arxkA/2R+
p/zySHaC7CTd7wci29meYQKrotUyADVjC7AoFnTlxuuMV5PYRTYOobVIhGhuB7qPTHTc2VwpR4+m
C/NN/Uk5Ro/9RTOhvJMhHJcMfX+1XvyXmC36tgpnYYQsE9mMkPa/qTVequRUnR3iNkWNHJuocLSf
uxniaO8ML6nySjdc4qOSG2OZS/TzQz6+x4hsUCcNcSnwZYbTV2Eg/FXRdAZAFKkDzd3ffP6YrmkB
qcFHxSKI9BkT5sdgKra75kc6eS8yUHazwbWV3kJU5uyOZpCmR5RFYF17oBREZs58CB8spcrMvMxS
R/Fvwyhz5HzdGQSnZ7Ren8fEOGSRyLtbgDGTxHJTJSvJl9wofdpVkVv9EpiHpwnPUbm0n7X60TyV
YYMGJkkUlUlz5Q+yS9HJIBg9fFJuVLTPF9kPolphzFOjSJ+wXnA6yM87vw+evyRAL5mVdzmCSOtp
MgcyNqpNC7AZIN/H88QiZEc/2eM7yZfZdeqMC1R4ie7J9TD7NiBUAl6SF67Pzjo7I0AhqUs25dit
UOy+EebSCMpuFepPJQyRPiyZ1G474ytRYtNq36q38vUuQsvhf9+ZyXcY/sD8cebfn9EWcBeD10m4
5Ixt0ULwoQSD7Ydzu7tRyfPBmeOz2mWm0Gx0CVbZo8gIoW3g6AzdEIxgvP66pZ4euW2g/okZIuFI
Uo3Kxp+Ebw1J732deQdPSxNbdvyijqUe1LuNZaIjiEhWUoMsaKabDWNyHuj5U4WV9KPfG5Xrtx96
0Int8ffesxQNqrwY9te2/+v1d15wJqvlbVlJ67Hq5yYGG0V+n3YQwdDPoa68SmJcHAlyIKuegew7
NvJwLqZCZ2CPNTtz6Izvb2OsUM42p9vnIZSkde67aFlj/nqHs+vdwGUuYGQG4GDzePVuIb3Pakrp
Rlz9eGh24XkpjsG3kxFrnnv+UvemDwZEJ33du/DKfzvs3tqzZjIPeAj5HnoEDTmmE5+hAXAjxyIL
7T2emOwtmrZxPaFdHBh23N2/jK3dFqmMayGDWN26vYWKkPGsn7oezDA6S4Q7eeOXF4kqoVq0pXfL
QU5Adusq3EwM6YDDksnvR1rlWI1dNCKbwqPj3SV4H86c3699TNUnf8GkNir92ZtUq/f6GF9lMEh/
Ns+KdE+Ebgc5aV0e6pPq2MA4CBw56BUg+uQTdideYyNtodlX88dR7TFLywa+KaLL87KyNW/fWBeu
uVW2WD+qkdkhZja6FPWnLtJ43grkC05/NOlr1QEFny2Rm+tn/SmJ06yJs1uBXHG8wevaLaK4iUIa
YCYrq2FWeCo7rp1l2zYwr//4djIkj3z1XXYLI80To5D7oK31waRAbBSERwwvIwxgm08z/RP3FGNa
iwe5J8ekwxbk/34pI3mSa+3ahwakGUiR6h4X3FMhPQd85ygRi9OkiAfoTIgb7nowH3pK9SeuaqXu
S1fcKZxzP3P5DKuCAkuYGIhRNpGKTGFLLD7GjgB7KpxqyAxHZQymAe/ABjDeN9UCfdBydI+dF4BN
cQ9XwwTZJ99EyjfH5BtwEzTokPIFsDCJb/krnqGE/TatH7NlxJOFuMvd6GQkzAWPippMXYAq9BeS
3GIedrMPE5fXwmi6WRlg/GjlZcnE/dyzpfkbT4O1GPYQvTWBBCmyTOVoS5ZkNa9HD/fosyoPUAJC
Cr/rDukFIVfBqNM27TpuptGQK4czsUHoG6eQMZPKp32H0Qg81AAobGUM13v3MkF1ngT+gwFq0RJw
7NkTR2ZjHPZ1FrH4dLr0dG3Z5jxxwwIvro5WB7ef1Ji97E/V99FDXj6hr8SH44fIcW3k3DTH+X6g
I/Y4fSrO+Kj6whXVwGGGodcYCFru3DK9K/iUnQHmaUqDDNqfysil7gdtEbBWYpx5b3RVAZbelzD1
tpE76BDnrjqnICXwCZf8U5/quj3ZULUlgI2LgKkN+dYOgWqSAGx+LTDMAhxWxBEIdnb6dKIp0rfN
Gp2NNgjA8d3GaWvieC951qLblT+AN9cAALL0Dzd0oxILqoiVc99kKy/elOBUWvMnUeJ3ERKA7X7l
eDxkKpgYUyw12shfsJH0idqmCtxTFIY5gsccwmSotyHb4Wj70WOPlbtwIZ7WdVoaWSC4DrwL5oNt
EWP0CkurqFlLvmnDHSy8XBvHnuwBXgQyJZMKWg0udB/RyepMA3538oS7YgptVpWbFD+huNXKMEcx
zFxYLZGQTKfRGFGBeTmLcf1CyQYsD2RPA1swqBjafv5aKb5rUgsEfr8NIMvHysrFY4JDrQ/W8Unj
7tjD2xUOoP6ICSKNHhGtideO5uv1A6SeQB3xG0xKvTPwxq8JHHxL9yn57kXla3ZPn/Qqe1xBLM9m
uKq4VB2y4EHIxTKmOviz40kjkh7hVI0OlJuuWP9UR3g0JqcHGLPcqLB9q2kF8k/ZYFFibXn+Q23a
A+EbN/zi/9RYUwKVzEQcb/uWA1cEzEy9BcS+lonqWm2JoLaqMFG5Gt0q2jIei7yPkmsg/q9bTBRI
urqN8veC4+rxqOxQVhVReA1iETDAq+CiSA8NOmupFOzah9sAXLaqb73BUdS7G93wtCEChvkTWNdI
Z3jYUcRoA4h82eygCD3Ysj76zQiZtaOYDSv+tMcYIyOBmeGb3FLJtA4Mvncw6BcPFL6qrCHC1+LP
70z9qV+2HFxFf5zFsbrZNAHxTX7/JeyjMyPykA8txhqkiujeBErUsGPBJbKEhofdTCMw8k3pWuem
HhKlirNjFpirA13ce9mUWa+E/zncj/VRkdNMDH1/WgPmZdr3bsGeXTi4cxTRHgbLMgqa7ssdUPkF
d3Rn6nssSysfJoB6FN403gKDNL38/8Beic5CviEF2gvDxQOvK5cdEgZy3CiD+fts0oMeMeBGagRh
CLrg27PP7lXCZ1QSEhGy1oQQm1s5i3Aa6RU+Ij9xmutxjd0gxUVBuBt4Xn/doKfe9PnqmD703KLd
8aoxBRnSIQlf2iOsTAjTEHscUGAtNtSUeO59g6bHxyJ5/oK3qSCujELK6Q66ZW0BQIpQmpLV6Kzr
HAjH4fTGkoRMjK58IVa2EJlG5F8WLu7LevKOLoO3CMN8xdOWVYZ1GkwLalIDH1XRjxGMwqkxJGF5
mszsR/weAh1Fgr6Av8vfw+2p5/2FuXhvNgq8Pu4A5ijrap6JB9xHbSNk6N9tqJXM4CSRoHZ9qJX6
B+HYYoe4HabFImDkg6Yc0UX0C5In6YK8LPyE1+lHNEN9/sq41idrJh/s1JQewGGQG+sy09moZeNI
42B3AYOVrtmc1frUFcbEKyAbbj2fxtamzs8rk/jcYZljtb41Fzp8u4keucXWRWWsnKH8fOSbWPYX
lT6AoEDI7utLpPAPpixo8mByxVd+9Kz2qmo2240S83yy5mFte3w4JsQp42EuxQGziV/ZCT8C8UCw
YbkN7lUjJGWIl+Dy3TVttYsBRPYgLZ4GE0y34kcZKDys3vsVoCiOfas7jK9TyZX6H+G4gFTyssKT
0X/Q3VKJhNumPERIoj7OqX05kyKgmvvoae9QfncvvdNWZzTA+WFXY+kGjApGiljxfNYeZjAv9Wk3
pr7YwbJXJJNBmORti9hRWgdk5jVqtipE84VitCcCYjavZrXPyPCQnR5D0wVXv3AyZCY7QIoD4FYc
H8amdpKmPn2ErRCxrQvJ+FgOgBmXG9vh874iEIkIzx9etbN8vIj7z1yHJyU5MHzjmY5Ttwxa4F3q
G2rPDhYDFg+AoKt0V9chr9H8+LByadkBWe1b5UhLLj8C5LqjdmcoFE3ED0UMTlJJoBwmOMwJbjsP
L6WY8SEcFSNCZuQYxCLseVtVRrRiYF9LaZouCnWQzFC1wrT5vETT/HGCYZjqqkZ/0HTFO8Fdkmt7
JVdKQuxD5vh0DGLOqDe6IvRS+ymwGYedq252eAjJqSFK91e3EE3mWyIVK+8AD/Kt+cfCkj59QRl3
i28QNacByNqOBqZ2vURsWGMzZx+c89TBPdqdlzlbTieCnBlhBbVXVZVBsbk6f9Jf0IhLhjwtb8xH
Yx5J4HGzOoozuJJcF1q1OM8m2RTzepx+TEeZy8ghGnd8+xol0LljAqYpLXb/ujB+8te40xGsdtBd
aSYTioqq2UipZbMdK84+5y/hXJUClG1/Dk0eQh74ki9rxflwcicnpPWPVlEUJ821S/hbp1lFk7vs
UxENP3tRYbbwHkQ5JO1deIMYv9YRTZLwTQ4eu07sDZCmhBqeDZg+ieYoLvnRtCXT1hWSKXCc8LkI
X84lGPlhNiesRF1qL9Eg1hWeUBsiUHyMY1+gNe0EljNRdLSelDTwBnoqAoum9Z91xGJv4nLSTEUc
XtjocwNv5+vx6LC+SIojbOdJqdjEyj8tivXz3aD5BAH4Wp8NNMNQeVTBOX08TRRuRHgQx270myAB
1zNJB6TtpQ8dTLSl+CWI1CFAK0z7qam1uHP+j52+drNHrTy7UQLXZFXAML0d7AzEv14G5mhUqBN1
cnZElVJy17XyemJ3IpLIgxB5pem5Ot/grOzdkjOZPQiONYjG+ucp+l1Xhf5NPgxaelrPTON2ggdS
HZSfIG3dS4UwQURFpeq9TOkojDUjsYoORWz/+DoOyOZDKaeWetOOJ2pIQLhoA41dSGOa5czvJdPv
3h0EbTVB37c4k47jwkzKd7cYlmvBJYWhwz97jY/6mCKzZYEqWAc3RT3fc65BjiQvWstICHYvLu4v
pVmZNSLr9muNrYKzop7ITn7A3SRn/vNdD5untX8HGUeA9LcYgZf2m550zQHw5vKdRtbKajigRuVM
5x7h8EAsokgWld5FJrgNeArHXncWxNvJToFI8TV8aPF+SUKjPq5+7mUGASquCqHQ/dQ8o4etzW/Y
OvmL9jO2tdISaOPUiQTwSA1ykfvvwvs+ksBc1WuRSDV0C2IsiwKFHZ/uehTgh9XxueTOvLCBsIMa
IY8imdG9+xX8Z8vEmeAIXwrMbPWdaRQgmkfA6JVxyJ2uTuzPKnHZEDgJSryiyqJS+umbhPgveSw4
o+oszBwKEqVeusQVvH74BtEBVCmRkidS/0yblIE7a3dFZiUSwmGq1V/I/5jB4ESS2cbSuZbnBrgk
tL9hj+Gh1DscYi9DhcEpua+kRTRiPBz50WJHrrwdJkbODh79vcs/VpUdW0ih2aiq6rtAKCLpcn5y
fLmX+axc42dDDmj6SNoBjyvhQLOiUzHq0yjhG/KF5K3ATWVsxpNXODc+kcmPv/8J8D/ZdboQcJpX
7YrB766q0wAKMG8OcpyhQ2qLoe4yRwKKDsdhRpG5M26zz63uKtS1zi+Bmyr8XvlMK4+7ltpBDgPN
RCU39NkR3eIKaWgYCndtipgaiRV6SjyPc/3uFKpVHqsGvXOw23IOsDUGLFwlI6gX1IGTYHZ+uJjD
Cy3Z1DQRvfERiKHwzYWlmBcYO43QqB3lbFTme12D1Z+mvRxdoApbepAWBPbaMAvoH5oKrxvaJ86p
iY1MOOCDZbe1pCg/p9e7oq1p0rZTGrfPHymJbTZyaAddJOHFRFDT+yexZrIJoyTjwgtcFbzSX5DS
Hs/adGXf5CjiwEyb9YRnG2Fqap2/M4ZPFvHOlOYEhdLYKKvBqFbz/pHUUsti40Jjd1wYoc2+zL1o
4HPy7KWV7GLvTlazMWcsEgNS+Sf2Wbk7tuaNPPiEVxIfhDVLYBRyuwVPgs/2nU8dmknhZ+50+v0D
B9x2B6aeQec5v5GyoncLgVIswGt/xzSPQ5GJdB2+Q7GfoXRPJFYCnENVbWNs3zYZb9v6I8nhlcF2
tF4hjUnlPD6OL5r5KONNdrPcnbS0c6g2L/UG8DUK5aBkzAK4+2FEOXCBueuBnZy7glrCboUKAsVW
+2QaIAOr3q/MQcQKTQJiIBvEn1JC921chq3knPc/IFHQgkTdi+vTkTmDk/x15huk9Wu9GNFnz2KR
2nFHg2hTElongjIUSA29vLdE9xA3gtqNlpMf+fKVlNNN7Ohf8onXAX87/LSnY+/66cy2KpDA1M07
mEO4DZY71UGBJgYI8zKxmWOknv9X/A8CqL7ANizIGzVWOjDou5BKOl5hRtw+Fib+BenxNRPbuXij
R/Vi0doiwKY/sRqCVH2rMOrNl6qtrJ32qQZNjD6XQdCbo7c2klCqyChdVMxO1WiKAJwINID6tO79
zJhzIYMEeGzQoJZOkmJ0Qhfeqax14dLS+Nru/wCIQBX+LB2ROTZPKvApJIQPzVl/G5LVQxO+Zncg
oX0xbJpCZP9QiApVkPnZS38w81qxSyabNTqyQXcEz7VcTf4jmiTye4ATJZVb3C+epQhEX9ebJMIk
CCWI6ZdoPS30zeB6FhnvBexfhGT1kW+LVf+EuqYR2qne7s6j5Z8ih0mbDH4iddkHkEKrQpoD1q47
2Gqjl3DY8iS0vcYTnecfvhxi5J/Z9UttNukKde6dLBvWCJBzMq4de9/32fBBMctT2qHUSZBG4uwi
WDNkXrud96v7iy38zYn+0mtRVVjTakK25gMCvSYo0LcOny4P46dBcnWa0dNIf2cBOK2mwScjgyvz
FJLTDQdYDbu39nRSkYsgJVLl3vXlyXyZzrpmUztrOYmgEyNMv9WO97hCWI2Q60N7kpOuvIe6mxX0
oTE4bkWuNmyRVKzQt+0vZwMZX96U7LSR2n3HbJTK5gRjNIqV5b3DyDNUdtKqnlqOQTZ+pDEm1ubD
NDpMIs3fJM3jaUg9b+4WegZZHkZfqkh8UC83oPXxpvouNsUeHEt152UdbhdNK7DK5fTxK447a6O2
8s7BtIIAAWP1h9yms5pgbfIF03cmt0c9bgatt/1sk6dVvRvfbzJ6cUiaoPk4iMrtNSmK+RLjYm05
ner1Il/B5IYqeKmeOtMHIFssUtX3GlbJ7Z2esOALpLWcIbm3BGLv/p4iDTHthDLGezl+7zyUw15e
8v5kiIU1LvlpYvwTSpQT/qi9D/To8ELtK88n96QjgnVc/vuwTJb6J7aL0+m88XMl+V7cueHwANb+
F8USZgVbfoXFovKPAUZWA8O/TIpCgIr34gj77MfUHuYvL/iHQsYomluv742gMyMoTTRKOkHJfkCE
H/KciL4dESMCS4S8gkDlfZPXwher6hgJcTGTejmJ+W+sPJcEjGyYBHM0DvVaGCahr0m0CrevGjBA
wFjEPKrTFIGQWmUFG6psIrSeIqO85HSmyOdm180DSVMWaKDP9CBmiGbzF4Qr1VSLC+6DYwIJiv8Y
WwZG/nYK25i/DYeq8b6XPfaFAIpx++TcsF8PwXyR9X/Vu7wWzMBhj08LbeWA57+Kpt0FFPEH+sWW
vjTOC4d6EWj1cayo+etydTmQukwLppZ7NZiNv//O0YPZNV2sJkPGySpSWLHyq4x5E9Xp8/TTWw4l
WhTcNke+zlt7DIwlASq2Htk37XZjDZq7ww8ef3j3S2VPnRUPw8o2ZpMbfiYtR7lye01TCG8f30O0
ECZ4wlkuvcSuuFFSIB8J9kMG3jR7/qs4YKEmKnlundY4eqTu/s3sJm2axC3rYSxONxwKfnMFQNuu
hVEmgnhXIum5jjshBRShpGgL15SBTZtWDrP/5r1c08zaIiNe1QZheZmKFRxXcn2ep5T4SoH0hVR5
OThmfCRUhHZsfcSA4xHffvZvpQXWrC5gR33yMvaIDrD85eQpm8wKCU4QMiWRVJfjl47PH8SDQkOf
3nj8LlaONmC6rv4hwhksnMHuCpyruTNU7q5br/HT+gzK1r+QvTrxuJ4eOa4KbkSTwbCqb+Ny0Rgm
UeCX+9zRfGwqmtqp/po8lpi/FGbc8WuhMO5uAg5WDsn5M4qwXM7UKMA10GJAY07PADZXeI7SSK8F
QhYg1GeWjZV7Whq2pBKvQDnLBZZtXvOF2xFS7F3mi5u/62tHHBP56eAUJwIWiVSnxh0gsVZB2g89
4apx5yw2Ng6RJqGCLINd7O011NIgh69yLK30Mf2loEMrbEdcMoFly2ePLaa54uDFZotECMa+3kcb
rvMG1HtRKIjhBWmqrmUy8SjZfKhcYDMw5SVHXAfFCxM7lhQBGLJSco1lujjCy4uXN3hpE1aPgtkq
QinlIwV+dOX7EiOrj8i7Y/KxM15lG7S2uLTXiaV6Y6/SaH1HxgDz2jVfOvdp2MOnfGpZH1xHaJEd
Pj77rgqXKO8E+tLZ0DLPk4HF0qN++nhehsSjH1ysnaXz63qJ1LSoKN4uTLaQP1OHDTf5auDZNT9d
VUaIkCcZq+3cJbTxWi5f5OSOOejna5EstoBnQSEUx4x6i9rz0iGmkvTOSfVGMiIuLhTqsfAzBfax
hp02TNxsOB0pnLOshLYaNu93M+UPQHSOA2v2v3lV28EKl3I/jEwbN0jm2raHreNx36dMkmt88tl1
q037QOyfz/KzQYzBJfA8HH9IJisVFYeaGaQsbteyh9DTC0MI3Rm/Sj4STYtCNz4fu4C0ZR3vfwr1
ar7JEsIV/R3tq2qb3Bvlq/9xwYHpR70yMgBMl1J//KRCTsfa9RNXwFT2XPICxVS27WMgAN7gvdef
KfjSe/895s7aonZHCQJcaE7N35cMjWTBUsw/9zH3kbmeSgRG6fbI8ofnH8Nskj3X4k+r0s7PhV3W
J+MNdxhx9VqJnQJvOPAT82MasvgcdxipnixBih//G7vSVIT6AtCtaGMBy/TX7SWG/xA8esupkiOf
g8V8ryu+DHKmK7z0jagtXL1WnhDy/jLQ3acM9aec5KlB/0NcIk8u/ISpPb00i36xHoU7LZ0N5lrm
PMUiy10g3QXvngKpyVHeC2Vk/6nze8cykkcU4cCdkBqaj7YOz5ggSWOuu1tkGQu7H0TC2aCGopBc
yKt/Ayy98Uo2HtLAv4w3KobheEHAxvXQFtSShEcUAOvpNEMdaUpmA0iQvO7fS+TBoBm5tp+hA5IB
9YibKAUvzsrVe9L/XWe6ZWDOO0TqjbrkKGIfmI7bQ4SYitIwaUz0WMjw5upnlTcQRXppARjlxRuY
eF5ZhFV4eomOWEQypFhfzkILvBSnAU4B0aYqWmboNoPRw8PpQihHEps0ZaE8T4XFHEZjDVzqandf
Z+SffpGeeGZHiv//lpqnnN8HAyqHHmmpUFz+5mtJ8JM+xK9mM6k9kb+4NJkhKtAPDqTo4LXy+1FJ
uNnH7oY8hLo1wXl9ZHhDNI4ubwMN0XVj74KtQBfekVOsKtkxLVgjev2/CXWz/2gOT8+qY+VHdc8r
BL0tMxspaJ0DCdsRWdPY/RnPmOkGw1bboNe41kstBJhEqE6Ou0d5Iv8g9UbEVQWKfURMhMZE5RO4
LYtdj61IooGiOVK6qOHeUfff0hK7wwhOg+CCn13nfyRjvqN0W69vxt6ooQ2p/i7uxNGQDrafp7iY
PCKtcnLRGf9WII2JwO+Eii+VIou5+CgcRRP8mofpyeRWjQQ35YCSvCb4uzMSB7ahltJSVOOsJOy+
362uxyvn69HgzKXNLopUkRU1D3wPcUCCRZvD9r9cNrO0NmglVLXbzpIxahzVaqiraZvD6FIvcCZO
iiNCboUg9amBkwMYBvahxE73pVEFQ8za1GIx7AhORoKGnyo9+bwmtPZhyTEvgV1p5mRdiyJkwjlp
PNmcuj7HoD3uArEtBg2E5HHhwqYhSj1YoNvLPcl3xwDetKD4gkAS4LmLqJ4yNEiWkK9xAXHtNegz
IWyY0Lw6cDrQQmZpVu7KYKvj8xg7R3itlV9gKnkGnctA7GFiRwgU49deylBtx7oP8ePvxy1LRkCG
zrm0dJBE7E6nJAQZEwyqorYilIQ2XtCE8H4pZVvvG1x6pQYBzE0WlI2n3qfBecFFvZ/hq2sM6TAS
6BaE6N+uQqfTaYY5OgmtC9KH5Zs3CXnDJ+C5one0v+VxsYfxnPoEezkcNmIRQWXv6lTmdloOD2vw
5LxgvioxERgVFeo3uwEhJxaNvLLLh3VxqbytW/f2QAniRRGKrO0AMfRHoR8TXHUxWl1O9WtmQomY
a7ywn3j9wUHcGDFXk5Wr18uZMmsaLRyrCVqfz3Ae5fVndNpECeeSe/Q781nF9OrYnxRXnB113hx/
S84+yMntF7okIRRnfoy+8R2TI3j7nqfX23RcvX2fLzhRTUgmdwLs7JAxsSiDApmm/k/SvE/xPxHf
JX1dIDO+NQLqfcB2/lne3gglHkVzxHgvcvPH0oOebz0lc/u009DKN8zLprKZRrjVqm91AyoNhOl2
maA4YoJ7IMt/buFccqIsGrs7Ztc4OYI8DbRmwFKaDk2uLiwfCHLUU87dnlcttuSLxa2N/k66pPeh
Hate2soil2d41g5cjpTMvzk+dN2wgO3w0s1cp+504o0ZeYiLjF0HtkCDjIr3uLt4ozRVxbmp2DpG
zuS+1OJfoEg6qVRpje7mGlm8e0LnLzywOfWJMa4YmRPcVWN+LyoNdAOLg2FYTUp4T9eeSeEONO3+
l6ymsZfCcdCTfYFmproHZb3rm/yJPHnALCJCA7yif8niuuZXIyTjtZrOPhuww9K0f5OJ6Wl/GLfd
k7ZexvAyZM96XhBm8R6EvByRS4KaIkSYonJk2eDORBWcW4033/30nNtsjddko6+TmqBjdi09Carl
f4K7DZXXF7CCEnZEItOwmoZZrABnrgEArhC/4Qg0Ft3NgKSXs6FbbaJ4RouyJeduS2sDntwfgnPl
ht9vGGwIJRGdol/F7R5hkNK4Xxb08ELPSOexwe4nLeDyL2Badc4ts6a5pLpDpFhHcXOa/M++v7pe
buu5aMtNbLr59j70Ag2ifSd695SnsMpmqVx2EIJ0bdLRZC8Xcxvuxr3HfxnjpLFqXnFgI8hktbFa
81vAbyUtMC1w9xtobsw+J2KRbOoGFIL7Z8nKQdxMEic2weNkXg65p6ijbKJgefawE6m7tnVMCBV8
rH5DAhlP44Jqx6G596VgKKDDO3MbH+pyiAeGnpkRpK6SmQPAKmhTG8+Q72i/Pzz7uCLwj91aLI8y
Zga9eKYYxKpI+ej8OybGSrYcXFeaxbpeMcjA+A+YQm1VS5EUkJSX3nW9xiikcNRBlTLkYkuNT01q
Vuf41Tl189alLxiFhE/wCU8z7n1taq08YgtW8PsB+/Sp4lxPiEX0JSMmyr43r+sW7LgV7avdUjmz
KICfgNJN905EFHOnut66al0cMn6d+FjZ9IjJJHSZlgVxZ1/Xay8Vv3Jqdc6akw4QBpMdw2CF0SPL
vXBEZy5X0wqf6edscOf0jn6mpdvhmIZn1O1JlAtldN7pnDfVGO4KSDzdUoDqRbNdGF3O9fj5mYxA
mbwuAKLENN4zlP/7U21sKpO8v1I2+f3DUD4lczDB9ekC6hH9qSokbh2K8UmF/1kLhDDRZTu5o2nm
/l9Tic9aZ95CiqQDnlBBq3X9J23s4Mgf7ZeJ7M7vxuEh797sk43zQpQrqTIlRnPq1n7bPfDmRIUF
2rj4QkEusKWwwKHzmHUN+SP6cCEZX3m1ieHNG/RQb4YBhbojFj42eAiAxXjpK4Tgd7MJzg9bqr8d
f2yFq938Wipi93+iNUB0WP7Zvd29LUTxnYEu/YRFkTBpq8bC0GVCNmARJDatJEYxVHhGE/LBdIy8
5Y3iGXdPT/gGKDEry7y1Yms+G7Kr5fkEm7boHAezvANYDDoNDx+w0JLjc/K91qmz4KH79C8OIgLS
fY3OrlTSsnggpY3g2LnS65WZr5i2FzLtTVgcxcDx4iS1IUjic9rk9UztcyUTRDzuDePlJztINs5t
gT7+kqjD5Y8TvBk9p3jpLgZi69sFqcZB/Qj8Bi4Hau3T8gFu2DW8jB62uokN2qxuxv9E9DllpmTH
teQsSg1Aiox7FO/C6Msmta50fHSJOGk/LUEmRxTRIzcckQA4N+Iafl/4wxWk6wI3UwIJlHGkLuCt
0YTPyALZehaDQS5UmtizoWHF6bRjuU0qVNMgMX2H3JJqEB3UB5nvbZ9ne9TINADCCULD3PRpBtYk
fI0UsbftGZAcaCRyozL1CFmvcX8H8okVsubrjYhWuDKpsXTHq8r5SEs4GXWXss6ILimqFB66kGRM
2oDJYawA1Odfo4iGp2QQRomjciKQJtvzrqQwwj+HruCh5czYKCJyF7dOCFDI8Q/RHAAACmKRPGyG
Cp8tcgWMyA89c9VdmObaT33E0l0zePSuPlpKB/V1dMiTpl4C++zzr9+ofM+2uM7TAPkaE4HDLqrH
Wg67wCrPTO7ImFD7rb2mTd0o4XWlba0Xg+mn/HQzZD2BxueXXHApAK8JWJBUWIN8GtFAruEfxUug
/46m4m2rD8hc6vgnLz30bTQ3pOMYkKHK5svKM3OnTHI4SCGlOJxjJrUJb7vKlSPFCJ3m9r15AQUl
lSEnIMbRYGsMXFfPKbcA/KQ9lZAFZKiv519VTSZuOYi980NTf8UfdZX/1wPL6oLjJU4hxq1iAz/I
zfWV+yqLwyIbYlltODB2mx/AQ39MaAV5r/UVUHVw+V3WQrX/l3lZPmQUl4gdyDvk9o0Epf5T2WVI
6yqZlMMQGfsguzOlIeB0V0gB8WWIK6gwTXvHNqEI999F4yFgypsqYgoJwmCfQKaMH6237MvCyKGo
mJONMQTVi3vfGn7+uW2FGQKG0YWWxu7gkCpMQazpKOj3x/NsUsbp3SICkbHdA7rC0W1HROqsMtNR
O3Pf4x69zUnsvDMk6HvprIOqkCfMfCnqp5d7y4t6Ctnei3A1O0uKcqdQxcMa3Ixf95M+K8p9Hx5q
UnKLgf92tBCJ1ZKx5IXxTNa4Q2BZMNqjObTCMxaKIbruWRfg+4/YkoGyrkbRkUuHa40Ixpyin2I5
9MAWTVyts0+N3jE89KQKQ3WZSOF2Enc6vlbxHVQRtgMzg3zVv8hmMVXcYEOksXSTi29oAN7c8QzE
9qc5W7sOC6vvh71m9+CiWBQE+rOLuPH+mdhj8Fr7h6nSpnTnQutC6FENjmTWU7n+6WK+fUO34voa
Qh/bO+q1VZs54oLy5SF4bzzyywUkYqIdzAHxaUMbPP/kr5QbXsNM+991no2fA457LOEN65WITTOZ
RCTrOeIpl6gK0xAmpGv0nzBClZRH19Zp+72GEzlWbW8PyvkWU+4ORaNb0iVPKYbHr7TSwCQl/wFi
14aM2PN0HERn+lDBVLDxCQOBrEPRh83NnH06Fiyvin53NMtpwnq2QIJXub9RORnEi7jyR/ZDeX+r
z2suqLX/LEbx/C0RZarfDnKiFqMX12PelJ1O9LOcD1oSRtPxBK4uQmcwsCjp6JdAsl0ZzCNZr6cy
8WaOZaqrbdWiH91OJ5LIsz7SFRlSKt2GXJTYiF3zBQ0kzHS3wqSnPt2TnhPKtGGK6yHUXJh8x8z+
bYs7mjZqDDp3ZiD4v/PExj9mOcsqqGReb21zkDeY8oyCHiftZ1IHZC7gJ34mwZnqPeZEShb9qEw/
Jbf8E9PJKVhAPbaQE3kQj+2IsPfF8krCLbDI9WNhF+9c3lO2xHb4wUNZQiSp/n2E3C2dJG6hMLOr
DotSEgkL7jfgOVUtH+2CxcStD7rTpaVJcK+dBz3stz00EWQVSnANwQq47mvpumeWm52UsiVCOIP/
CybkQFCXm9SS+OhZrytE3/kMwkFn0Iqh22b4b7ItNWiCWrh+ynbbYzDhiJg0fqUleiOzd5ltMB+X
emfWkI44TtjlZ2eoJSAxzJzsVw4jnpekwCdiGb8N+JmBa7N4nE8QvLX3KLY79AbDnlmIn52hg3iz
exxLbj5p1VoyEpZTXxl2uYcWSLJBPbD8XGvdov5Bpd2yRx6AkHoiSIWScYG+kwt0foJoNhqgyTk7
wLXRZFjjRenuLEDAEt1w8cuQ092UpB9crElGG/ArMU02Oww0w8k6lxnjVKQQcwfMvJwNFLXnRJVI
q7bBm7/0An4DsnKlPadaZi6wnc8hHk7E983Fendj0iZDKeDNqocxKFZQszbuh9dVMp7yTUTR+lQ+
XqmtBvIQlSNbR19m1mcvQ5+vgo9DXRqycTxyai57Ajh0z1Ku6AwguwSTe3UGVuEzpODrrVBR5MIy
28/ejc/hF43dFzuPuI/tx+72R0qoIU1AmQXzhN9F0z1X6cxK/FNLJIYX2HuI2IGb+lNrPyZEeTP7
Oxke9tqsDPXgokrAwjNoXjbj/jjbjME8UXAwZOO8SKxDDhGF55dS7bvrXKvUS/QR6lygkxdKn+eP
Vq6V1hXZMvEldvyDEu8T/b1gZihdwo+VxysW0Z4pb+YXFVgLErJtqmgLMuKx5XxfyoqKEpcbBRQ1
hDiQKYgrJgfAhEBVj/PBJ6GW/LuNQ6Hx1dn2eU/wsaoV2zGujRlDqqGKGS+KdJdbv0LGP104nwqY
hMTRA3HVNXOIn2oPtjnEZVCyUm9CImF+NQZx6shWu6+QVPrdKsO6Has511Ws43khvSvnI7CzAxcn
+ZMnV0queBr7RDYaT58pJh0EGlB+E+hVFz95e1ukd3CQvZvRTITnA/vpmUIj5jaK6HKxyzBGtyNr
R1dk0nucbr9lZSUvWnCqtQjx65ewvtZ8EGRy2snmkwgPcL6YZ3lnLS++FsngYy5QnB9o21l5Sm66
mvj5bmm0U3/2MErYkoq5QF1o7BnUe+7q2VBdZVfJ865K0MsQBcNptBRDJpod8RhBGRfSt2kasyeI
CMSNk669XZdpB3ZiSEzYPPWswAsJUwktJSM9zHnnvdyBYLDbBO5+04Gl0UoDkLCWzkPyNqDOS594
Tlv/Ir8Xfel2KiMNR0MR2shpIxpoMG7eyAxctTsHk4jSAvpYyAWpzk+vH1rUix2cK7aTO2p0sHu3
YfA8sF0NdOlnibYzb5oE2wpLSaXulxNCBVI3aiorV90j3iq/IMQ+a0CyvrJ4nJxjJhenep35FxX7
yAvP6Work3QjN/2o+Fp0ZUK4H0RSWTcL7Et5GYfGZTqzPTgm/1bqBpKbUABgZPijAaz/KyBbcdpy
Gx8ygocD/rRlzTpV1gKkUhI4uJsUGgDvQ93A56zpc76Fb7plXs+wO2+MsmDJ3xjK2KQYqxdMFgZm
k8APcjz1aIwLDziGCSaxzpmfaGz3kL03+e0aBvr+ru4As9VJ03gO1q0dbOTlANXxQyLqYBh4XjiK
j7mJvs1IA3eb4qc6x1jM5D+2KuQO3iqnS3uS0anRJfzfK7MJklHf2IIvwxrAzubo4ZQtSnSmkWpr
GG2yWO0dXTY3/+/6lEpJkaJyM26zxBu962POIIua1FJynD38c+4zdE7nDiqzbKoSptTtkNdLZD7j
7PHYYZKtS7ivGf8b49dA3XEotxAdQVw5L19JMfgfk75Au0I1QaiZnEcx5fXNNXSispYJWRI8DDKF
0rUF3u4a3tZwNQ5o0MK8GKUC4t8Ab46SGLZGsQ+wFc+wdtaLafbJLuINBxPKAY5U4quRugAA8WZU
+7B6mp4nTPsHyS9vziBGb9jpuDnNmccONEfLANXiN6hHzFjTgjw1TjPlor7jxwK4Em07H8H9kmu9
chDmjgzkiMVO6ASCB60iqX7tQpP9uqnj+QhOdPT8WgHjcgH3Mk2RwG8qISmHwxQkXvul2/JWTzOz
NX8pwWjxK2U7zegP1AJ73O0VdC/utvvl1Aiv+IMze+3e8AUHyJ2zIpqNvg6BsH5r7CpV7ZImzQwG
a4i4twf7gtx2uaDNiJ6NrbfUvjPo4F8S0vi/6HW5oM7BGMrQg0SANl5ABXy5n2kbPyE9IUiAAaQZ
90Y5qFoWvoSHVn1CbhDXl5R45AvX/m/4IlmJmlvPv3iHkk3OjXWRR0ds0HMRIo/zcpLs54ZYUUg4
GsQbPsu5ML5mXpg22fSv4h5vrkF+7f7rH4DboCxMEjC9oqHL71Ww2OxsG+gXpgL3yYhxcUEazg3n
daQVZde8Ccm4tTUhAI+VM1oAJFDlh761b9EoG4aTYBRk1UlFduXQatmCkIK3xJEkPUtu+ug3guHh
hYsxnZikHUya7bQza1NCP84Q9eGKsJdFec3hZ6uxM8L7ZPjFuJcZnFJFFrf/uucaxafOzsfjFpLI
U0NLKbor5HZQCMxQyJq5jkW2pliyoahCio08vICZEhVLVEHCObEZOghz6T9WYYBWwFGgmYhwSbAF
dnRo9i9QXzUpWGQXVBm5apYeQWHSL+E+dyE6wjLEZuBZ5SUojbhGhxw3fNAo9BB8X4FQn3r7gc2h
y0CsJl0LFxphMWdLdWnh+XGWj0knyAAQoRv/X0tKj/iQI2mGzBIq1DLcNk72tkkhqCIql468dtML
mX+T4zf2owKxawsbHRy+hqFxrcwXNTla+GvAtAadOD+3JfFVPSbf4BgWVGVyIpIZjemumBzMdO11
y129+F/oI6YCpLnDfRF5ILDWVtKkrO2P1nc2aFYtB9y//nEg5hkUYsEinZOpSEeqt15Mh4iEiKAM
sw/vFL5t1ff6g5WjmEU5JhB/+ESSf5CRcqXq7SJyBQbN6zpcOrnVjajjHqa9IL3JrgoYyTSsgbCb
9Mj2ANQD8SNZ4YB4tS7U/lya5Gqe6s2PdnUM0ZaRtSoEOUUafLHD/dz57Q70HCDEOejjvrbTUb+i
EBu5vIHfJ+wXQW2T431DusoMqxr7ukZN1eO9lz4yE6x8KGENBUaiRSPI226/gI5IuONk9yYn0yKg
RFTqhpbvw/cWsT1JK3r8EAQ2EU6DbgQ23qWo/I1NNpYZAukOsdb19oty1DwsO+ORCRsTbkK/pI4K
v4Tq2meATvhE/AjHehxxC2cEBKZrzsjKh4N/N5mwMZ5ow4q2EtGHA0ONWVqXHUnPySgXuLYbBg09
NgpsDrP62+nlFWb+ItVhDTr6cxZyvpVJ9/WG3XNXVFGTPpaV0htT3VjNEnhT/qwsh12Q95mDnKmd
qMusZ2iIBCLRkCmUlapeowvlMXq20IkvxYDeP1Rza9ULNdEKu60F/kyESNfQXSfF5tl3XMdMgfq5
XhkAup8SG/UslX3TUJxw2GnWr8BIPR9eetZPJvS4PaE694sN4vxX7Og3t7ViwFqmll0DTiEcQjQ3
oOXQxZ368DsamlepsbqFdKSgg20pZuIFcP3Yx7a7w16NdQi7XqSkds+IcHeqjd5eirbZ9d4iJnpS
ly2PdbMsocPJxeREHhFAn7OdPP3SXTrUaBcX0qLsNTd1y78YETOk2B03MH7kzros0DgDGHJ+W/fH
Ylsi+h/Tl7qSA+1LOApUXssu8O2PKAyae1meSwjjRLp4ciPsrUDNeuPjpiVhqw78toPbfKUzQKLo
zzW81hXC5GDrresmReRcjciN2dnFswcVYaSImfhKyibZn1eU+dgyRnJ20eykDdarhpUECevFG/M6
wr6XzECzVTWByDK0VeKS6r9Xg9WrBUFFFJK/ySvTpeSz6c5Jn90JZ5M/DJv5uoPa4Ex9xyxLJAGe
wL8M8+mkGm/joPaHdOg0g21hkpkREc06rbnbybawHHD1D1rvUjj+dE8ExEOzt1mqntPx6/n4yWSc
v2uNh3wkTVkmbq2kLM45Sa4jj7BYEKjVntIJ6Gu5F2FFTLJjxLFqc6VPoD2kUeMF1UYd5dipVEF7
Vi7U2pN07ONcv5Ea5H3dMAyv8k+hsPQUpGKr637b57URNuUKpV6/J9QFFB6i2TKk1OOXs56jWyeO
+LP1o4ia2HuPv4zi1sWvHyp0piPgleRBs82EI/RB5Bs1lR8zZ4U3B6MZm4fLufATQGWW0dAZq2Ul
81g1lFAJJyOaV1zq7bAENJmfoGmpHLDMB1vFH9l7O8N+EQDNdvBurCb2ionyDhoXneEkh1QmevVs
O7UX4aavSi+pzSzRFqQZUdNK0bvJv4kt4Rps4cr8OJuJrTZUHId7tzyA9D91AaErK7hCyUpvuH+C
UInDRHKndpvfF700hOuoPWF8Ut3Qx6gjinXWQhAdRtwnQykC52tSwY9KqExyDjkMMgmNTqus2Q2t
dfwKofF/SGPI9a+mEnWH6I8+9h2j/qhIEKRciFNhB6Wn+B+hWO9b4VpwCRsFGJBrY5oLha98/N1C
OfLOdusdZOkv4pw5fIEI09bIxesiekfKySM2dT+RIZ8hHvRS0eOdQrfWk3ma24pFnIBpreUVdnsh
D5/CRVTVMD/c59HExfm9S7E6MghxAqk6977hKLafC60FlszPuODHdDws0KSRK1oa3LhqpCMBrnEP
REsE8TSEYZG+cMElaXL04RkN+tz+svGaxwlpgYmcjiseqjB7I4oQNwZndWM5NNbLyu63f9FiBcRO
Sd0Pq3RkU9ZqqO1JybyRVPrjDQ84f6nyFT8KK5xgH2u0lqMaBNMmvNjOk5wd6g0PZaDYs8KrLmDE
w4PPhC/vi6pnFQlU9jfJ+HeGaXdkAjjuVPRf4nq6XwyPxQ7JbttjvQe31aAkGA1k3m3EOq+WaslN
i9q+JtnCZwxVwtRr08u81qiNN34cQKSlWRIU15E/qsYo0HadKC6NtU+Y/fi+/uivCs569ELgPDlY
pIIlFDFlhTkGgT+zB92N706z37+N36e9v/6qKgzhGZAEyg8ii8zX+bd5qB3q8rC6IqK4WZXAH99h
VRafQM+Z8ot8YpWl3KW9Y1zzmEyFX49HS463BZlk8NaTOMcFtoGGpFbgTYYUp43v4FfGYRaer/y1
fWVlHhnTG5Cc3BRG9lyKqjor+BXGV6O4htMgNETjZFnVLRnYhie9OhBas2t9TWByhzXak6KtTKwB
/ZzdGi+uONtVTsMKNX/XNmJprwhSOKla2m5liGJsg9i4cxjTHNsUUlxbWMzgjW5omGlPRQY7SzPS
HcHI1diZncCYVPKo8AkYi6jOaifJIHtuJylrUBhjtUQK8UNs8DomlbttuMPJrTavbY4Vn+09ebmu
cY6tm7aky6E0w8+Hk8Lv1SkGCQq+RP6DnD5XRvRczXiIir/cpmnUUkjxlbW/tgxFbeX5TVRAlqZx
C3IiwHhS1dl/IZEqiYg9J5OHO0dTS9lN2ZThgImPK5aHGO3rCHfxXYA0refMTGqJZe9Fv3x+Te+E
2pAAxGHPD7sJsbubc/Jwlt+CFkUDeH5ad2/zQa+73FLhmHedqrJkeLbbqRv2pPlquzv5JnYuxzGI
wH+9OBDbzqMQsY7bKy/42xXIfCzxqzgsTRPKVRzC46br5kgo/GzzBMNY4UCCUzPPevnmT6OFYwfo
k7+g+NRbIGPctso/syqwJyIJO7mHWnGwOdGBpEe2nLKj8yJZHOThBJNrHEofH74HTwrLuZ3qc+76
jsfwY8M98rAKwccts3VcTy5RRuznB7QTPwZQNKNSGHtLIDyqbABGoTWSoNWQ/mwT4Olg94p1gpO7
sqdDcMYEFVf5/ABaMQ8sqOoIDhh4VClSRhfn/QEPsiO9krnKDQhJKZmsp4QCjvq7OTrZfmyrTn2c
FtTvDORgpIDgzR/i7xESvvZRK5Bc9Ulzb0ZZ8bxq1ot0UALGY8kbZ7Z90HnYlMwXyP1r73A62XMw
dDRQxmbsk3aeJltaL0nEtuSf1ACEq5x1AEHJM6daJXQgI5gkibiYsjcOxMa7QmJeItDPzyd41MyW
Iyi9dXyDpwtVuMJSTNg7jLJflN8Vgh4+kBB46fsunYrYhaPoMGooWJ9Qb+WrvGEs5gC3XbmKjuVV
pII4dJq6dE1tnuS3Hzspn76o8tMgOkH13ga97+BCq0/ReTm+vUYcH76zXNr9Be+SxFMmCaaY4K9M
PpMh5tAeO7WOJzBldVo8vv3jVzS+AQSGSAQZKskcQGxbDsyxtPxFYsATyr6uY02jN2TLwxrJBKBX
hkxkuoH77/ufp4oYghi5SROFLaNC14B0xcgBoP7mshZb+iWtBbS9EPioJAljWCWcAUNlZQIgzTjW
9J3k+Fc8pfFYemaWJpTqIDvvf+6TXflapLZ6Fm2Qumho6WiT5nh2Ds3GSVvK+G1gLNRdwY5BjQWP
F3mj4aLLEqdCWprmb8RKpOnbuVkFxgU6Zzy4DDPp4F2EplEVJ/ggvOlZCSFlsxZTlMG0X4pT3jxS
+b6yMRTBPRWCZbUa0aceI7qDm01Z3R8tdfmuE20jTSfqpzf6CQemPX7r9h78XUxnqGtRxDd56RzO
Jzyhg/80R5pRWwk957EPa5umPHEWHApN2sQhH49qDgmfKjaef0EZH3dcty35SypUq/6wBhYVcJ3P
3u0vVai+3pUJMTxflYvLBRQMDYG39m/DQX6Wjh9Q5pzdcHVEhx5/DUSol0jBkLq7MN1LDJlCaEt0
Db0ce40+MQc0aBI8SUn6HvKbvm0/8l9qp9NI4m//NBVCXWq83PR4Be4rYA6z8vovK3H3+7+R9pm9
HQWePglpsQluUCATbblEfrIz506EU/PXos64EmPLBCoR2TIx2nob4XohauVxtrhi/YRw1j/02z3I
Dzu3iQau6VoyfdHlZfR5feoCsyMdrmAZwkGv8C39jrAwSNg+aYRlFf1pEvQB4BPlyckOfgiKUtnW
/mHdwF4d/AmRa0PuS7WHCJUOdJ7UZTEaSwE+evrhqVB2REzK0UAl1qqi9EnIJqDPtxVcEBkMFpuo
hssOjhnf4Ldb6xpyZpRPzy8jof12L7PfM0EbvWKepzBmJLhAVXUKClRUD2kv9NjnQ/+++9sZtkbo
YDQPUH5Nbh/llRw57GtuWB0QHmUNxr8vBYA7PJgDZC29/tI+HxTpraY824eHKmlIAeuJqzozl05N
lMFOCPxW5sNOswzf3kceZySWCJWvKUIT6slZVFPwiwJtJzClvrijgvomipAZMkOwkcWkgGO58u6u
y/OIbMupJxW6867b1BajahRdmY50kJNMiG8dbTVDqQCac1Lnrqf/oZbP2fP1oDClfRL5UwULU0CC
PxQ0Iu8aXUBawlqqf+7LD1K3jn8tdXAewpIyHyiL2jT4/yJQqCQtYEw8yS4klupmsIssoB3cyDrV
mCRZ/xYUPzZ5W72WBPkWQCIpC/zhNx9dAkNM32Wr8kftM0mQGVyCk20Lpd75UXl1JjZzghOwXsdb
8yEIhw2CFLsHjhuDE8qtncfEN7IgptiSG7E/FlrsZNI9pO5Fg3R8jsD4R2oHfSi07Q2C/0irTFAB
iNpAaUYnHHlp2nNU0d2PgBbwLN2j/4vXb8OQ4KhaB7RRN7HTxzVU6mzUKR0eeF8LMDC436XgEJmR
yVAaykXR0DiqUL4DUB76lAWIr4xKtg/eFrwtWCgFjS3PwCrhnzs1vas40aMSF0Oe3AIHVQ32tfA3
8RSRNvvJ45Vc5tPCwhMYmETHy2ONHfsv43juCXliO2WG/I1fhpX3m04jABC726v5BEaCJwu0cMMe
Q6+GMb0D5kXbiffM8Kgic8f0Hi02Q0ZpR6xnp+vQGdxvCJw/tQadqzbPv0uil+RYtvky7AMu94nA
F3LxYQaYV+iRujduP0eFc+agyBS6yfUuPF18e7XX2sJql+GHAuYWoLeKOfUvKyU5BoOHD13hXjXo
svNZXSIE9FI95FM3tVhyJdCCdEes/RXGl+NOZ+Yb00mkOB4Uzy0aKVGooaKJ/jeU33/hCE8w7E3k
hmhK43cyUxo6VrSfIH8CiDPibXSRNuc5YH8bLiN7XCILVT0QdLhY9VICgomdjNEaQ4wJPFEYSz9+
KfVnql2Pla4FUdTvpHTKaihwcbfNUEUMGxyFch28rQoE+ShuCHguDpo76y8/EyxWQaPXr73boLfN
9f0C6bF7oSl8SJxuNl5rJ8leLA7U8CGPQrN4/3E0JP9LNizd8rNssuwv0dGMZOfB9Ko4JrZj9u1D
e62DeQFUO6NifJ7C1tD6wDgCIMwC9BvuG0YXfBKUIJ+GAq4JInu4nnsXwKXavW1M96qx8a3IsFl5
M2jWxioToIADXHtA4uhg2wpt3hFey2P23/LLYqMk4nydun4kSgNAM5UBm+wzDtmvTTsRCGmBzDps
CKArTi0en0jlOlJGDpAYGulVHJ/jxgt+OtrCds/G/fB8gwGUXTh8BupMup817yWAycw2bxMWNYtV
tXf2IYKrckfuFQyOc7iQZrBiIBvwkn/WP8HunUQwmNUnkYLtQemvsagmjW9GCgnXkbz1NZ2orkUb
imElfw+QgfGG88Erlev/5Qo0NbFuHdvoioR6nLhGz3+A1aur2qRjxZGqfRhZoO/+4BYyovz6CF80
mMD+lLFhC2TfL6KqxOmEjHCy9otbNzdPz263WkMPTqNFeljfvrzZRlNSBhxo1Kh4+PzTziXlapBV
fqTetcxVH9iGFIwIkcO7d2lEmol3CHyggblQY+GQaaSe2fc6WSv14H0m/K51qzU6ysf8VB8hG7Mn
NsZbw2x4hNEHtDgyB1yczVvcSX0rS6S02kOnJyZBsYAcOqU8sJxEkuV+8ikR/0v2uA9JxSwL3Wf5
o6S3g5Lmp+Nrb0eSyF5Kv0uCpcnAmsll2yHGCOUA8llUR4iz7QlySbiUaG6iDa6qMbvlyc9zwKdK
cjAb2Z24/hAHJ2i9MU5VAs/82D1oNaAxyUuGjOaMU7dbWxDGd81RNrEqRIsN/toz2TbsRJJkhmT7
vhnQuhCe8HnHl3VqR6kfjfy2HgEMefNJCleHX3mgC7yPJ7Bl0ApjvBWTRC2sLRxs5MjC+2rQDOtY
zInI0gSUr1Dj52665rWYzrKWJGeHEImTzurRIg/hxnpVucUf7gg9elcNSEeXBS2j2jyZ8RiFRxpo
UYTCpBBsRAkPFSLHpcUxvDYlib4yRsG5xMd8k94u1KdQ/NDEfCTXNME946LGuiqDnGUbMWMl+jqB
pTwHfS7rlXo7FrWqGtLQ9maeSSdOoiwsRxBYgKfXD6pdtM5cVnD3J9chdSOpIZl7067Fev4MHtJQ
fdXsHy5n8mWioMdxdhPo0BZ0fKvkkMiAzZWU3DqewXsGW5SfDJVsaUvDuwPrInPb9ZkKPIczuVWy
KmyXSrm/3kFWQToIV8iemTie0sZNaWOdpZAzyTKCW/kO+WddlDMO8HfKS2KN3WBzfxEm+34pZ5Uf
TIupcaOGUAkdizFhIaw90mUn1DoWTcr/LPyA9Q3h/coHVsqSnqoH9mvmWNaO7Z0p3rxxvp/P8bJB
Mmw76fwifhH1s0lUtfoEuRoMVCGrOPPFX7eTAyuTD4y/NTKSySJnT67me5uegPj0aJtxI9yXoahu
yGMq/z4p45/SYBBTWrpPkMkqxzj8iJTSvQxPrN2nYzrJx2mAS6sT3qabx33JgLN4kheuJcS5NdX7
6utXSyAf0KHq2tHUKP0k6m5LDiq5Eb19AI8Ge7IiKAde82ytSQdSbLAJiQsmW07OKIFJFFq/9i/H
9Qv3i4bRjs8sQbFULdCbDD/MIfbB4zF5me1wgB9c73kRYMK/iGxHsSTqHcHw6COdOfLYVDbJu7QA
vRQK/+xax5oWvJc6Ka+UVgyEp4GF8ZxywbPl2MMSzYVPHlXp2+JoZhBrzbHpGdzJa0k5lkkWzxlc
7GbtTEdougsEWohYXvD0VEPzRXskPO76eMB7g4quUCMzDlKHvmUfYzTOV09xYgxjpjvbn8y7JqB8
WbPrR+rKdJWyQ52GOQFLJJ0tcfn8+35g7yroCalq4ioqY5u4/8wOlXVOuoBE6kCOXhytlprlsI2J
j8N72vcpSdAM3WLwbUFnFV5AppZPDWStO3W4NtBKcZqY8t0r52urCAVkDFxWU3av3i4BBDT88Jxm
2FVp2B9XkPknq5/I91j5Mq1nfF8DW1cWSm4YeO6CMsx4B5wEOZgeEo3XWQgnZwb3l0+h2NuA99EZ
AS/DPrRgv9uJJMFsiPmtXH9bQOFyWRilAm98arl+TPX1xg5pvER5uFA5HIgD1lwHfgEL8NYMaOqw
u79i4l4Osp+lEYWx5aGbws25UWEDj3UNCfJZIC1FJA54c7UDDZAwQuggenJ0Vfso9M+EHw+8uZIQ
rPKaZdPzFnH7YNreVapKoRdSe1XASXLATrXsOsPj1AgcUOGeEG6Iytdb2ZZKmITkHEorvhjRkz/W
DJ0h2MQ0KGpcpj3iojlJOpP1h/gMJfx8+iVhFBuMLbjh7us1mu+CoiFzytAyaC0gj0ak4+ffJidO
kPlJm8wWEe8oDqhngiB91z2euFh/3z3ADlcLLbjWg3bpG+aFoVQWucttkd280jApR/S99n7qpcXe
uksBRtY1vHAaoYvanFQM1h5+riL6f7/wBohXcvLyeddqeNwy5HbQpd0Bat1OJpVgJNTMGN84wNap
iq89gEo4+0Bs2UEVCpEjoQMeZNkpVL56HB68PmqqaC2o0m6KJYPO8OXwUeINiUuKYnjOsIKxydc+
PXxb0aUqd2NLGU6dQLkP4+g7k14EGgRky17WjELOss+Jh4HSCwKOfGZ2h+yYZY8jBRg+iaUWqrgf
q0loP6OGb2uTqMK9aIaYuRREnGJwT1p5RKCGhQLQ9b6xkDEUsV8oybWbijCpnJ/KB7H3g5ItdBbi
Jc8B6J+h9CF0KfJ07IYG6OTRAkiALZ7C/wl1/tHTrJShpUhbY/dUHVTbbkGcZZfRrDX+BzKd8F3m
PaNW8nKmHrr5ExKjk3SbRDspFaCS9IVRxBrkb/4zrRi3d7SRL+UXhE7g19kmSRr79fzXnommam7q
2rl34h/FspZBobzdSWyZPKJifJY4wnxP5iHMTRTY02WOj2uBqtHVu15gSG5Wb+a+hCn37mwM3eBw
U/DtP+6OmeRJgQmN1TulVbOvaQnu7VrnJfm4dWd4eCE6KDAdmTzFM17A6+nCF0fZ6ucnH6UAS7Wh
d1gFvraJU7dMdKkrwtaWAz1RpPkJZuwlMV34XDI1cubbiymbtyj8UOcxupywXzdXqOaL/aNPWdLD
r03xXjYvv0T/8SSpUuvcYj7XmLpajIdQ6B4BLnu64Qur1NorcyK+wveSpxJhdXiDnrYctSQrxZdK
xZnovKsjYDfSq+WpizASuuwi1LYM5aibW7pAT1Y2Sc8XqaKSpcYrruxSC6PMShwhulqdwKqgbqcB
3bcnIqN2wXERRjYUlq65Ggki/N7JEkGVAoGftFwZetDULnmD3mXclu0X+PBXQBDaVK0NV676CnQp
wbvyy31yympzxekN4qbWv+8n67dhGuOMEp2cpkDJy8EkwOuUyWFw0V0cI2qW9NKLfsZVgPSqUk8n
VLspEz6rzfGqe4zvpuE6dfuGD/Vb+mavvK8+mVDszuVnQWYm15q2BO3buugisgOWJTkpgI7q5Cre
ml5SGunbho4VZ4UOvLFd6wIYFDh/sUkcKSnqpcZYCOLNLLe6EIIVRLmhXEEjStMYdIOqMdl541a8
jfev+iY1n5xYu4EQeGGEQz9kJ5L0QBXUbeV9rR+JvieB/cT3AwREpRzftZa7e+2+dwSNnQGr4RPz
dkX1EIgJ+KoSm1zv0oJuuSckiGOEelPBPWWCbA4qesL16M7nsVbGTKl5DVhKpJsKgJQlLP4cAGgS
VxSEuIpYm3nisX7a8rRfvqnEmPA+ubjxkRhI6axO32wfk4q1sVGvdNNuJnUotnxh/DJt++LWCAMx
ZkxOAeNdHs4cuRk4WYNlJ6jUoQ0oe4QcrxyYxQ0MocezcA6nrKWM2xSm0QThXo9aauBYGILPkj7Y
y3gHwIJQLTWFvvU2cJeb96SSYLn8nnyVjA/Nnne7JB6HnulE2SrZRhQ1rxZK2fDMI7CwaNFePzag
W6kH4xV2HcXJ0zYOYKRxA0ibwjK3CAq4437M/jH3ogj/I87BYvPBtfVz/mJL1eysUjMQ8eHM1cYi
sgM1IgJrAcbmk9VKFE+Wjq6fFla3Hfr9zcCvhobo8SuLRZvUcKAkPeEbMO8iVg4CLF0g6P0L8yvV
oT7c5Prjvui+xnwRnaq5FbJq2f4YJgGVqzIr2kgr4QZBSKkWWUVyMjrNuynFwnRNR7CknI5bPYai
JB83g/jq9CEubL2J8BnSef6dqSNMiSHiApNRHd1ay1aZidS8WiQCOZy6A10zwZTqk8j/dcjsRbhL
+lm8z0Z2YrWIYFxBPrazEu+S/6iEwzLPWHlGiqjQ/u7BhEkbDuUf+zXfVLeuBFeRtAo3ktEY7vcm
WTHCF8V0faistU1zi4L2ckHJB6Vuo/Wy0ubbhfwcQOmeub+hXfW17vfXzfTlZYtG6RxPe8Uo3HzR
b/lKJt+Ie0sTYHBxWOEVRUv+HS4DlxcX1/z+nX9jM2d7aOmwLpy70eaqeX/ONI3YqGO3JtUNq2eB
QzUof3MLpz4/aDsM45++ERdy4zQ96D6kfUjmHBrrj8FjSwi3569Vzv9j28UgWug0bF909BYpPoDL
HuUVnIFTR5JN6fJwlF68R794j1PGvEs2wFXPCV4rliHyyUhu88MBAmYJzHdDlgBrccGjJoKU97MU
aho9u4JJy/t+GKafMnLr/fW3tJp4bwg6uzkYxffX12oKD54vAnggai5oMVE3FXdfvWCAjdOF4QeH
Dk94Uzp3gSfFbinxNS+xFKOzyyOpObRVtw8FjEHTZgJHu30yufm1oiXrht/vhNxe+96xuAgKVMkY
NczJZ9xHoJY3yaRj2ODE/rf/ceQRZO7Tb24gqV6uE+yCdJ2k0VKm9h9etftr09BCiJh0ZVfQTJmn
IteN+RtXWADPyt+ftfgc5n8lmWzfJZT4xcfSman93KWe05Kz76AnVz99V02UqgfFc1BLo/ymrI2I
tWdABxV7qfftwex6tL5TexS9KBUfRdDTuUrRZK0huGdnDsdmweenqCiwG/BVVNtWDnt6RxBVGi62
Fs1Cvz0kkHVzFkSApzJFILDWum16YiQyr38rugEf7lkRLF8rtGpbwZqADhP5V33wdhjncDAIstTw
UQL53OyZdWpzqzxBadaCAxtAs7OJYhRCqWtT66c911GuyG0rGjqgERlPC+xlHqPAqSsMaEM7i1SR
vKr+l1RmYLk+Yq4s4WZ57M5PQVYs2oBLZRzLmxVSTSznR5il0L5fWPDZFj6jUJk0qKJNmRiEr4Lc
xFmUzkAl4xzJDj3LO/VPxNZGm0UfSfcCObyLqjwPVBFMNpvU1OBFdZooj4wlkEeyi9d6FMmP5xLl
coL3SiBs+WXbKDh86srD/xONuSl8KhZCtRYEUeVrjjyXkYD5weVSPCAbV09j/fO9fCjV3ojosvNI
tw52D7gDOIHwQyDKmAvWZy6SsmuinQSXsxsKrNkh+VfX4Gmllg+J50AmG2cZ2nhUWXo9TBjUzCsR
K3yVPwylsZG0rgNBtq5PnwzqNydZpQMVCUKHrUABJy7yE9HLduVrmk7AeE0i6zXWuuBG3NqxURKk
IPVIQxxoJFFFtoZncgB0Pp+I5dfY7XYPGaf/fdYjU9xTOEeipd6NQyHBpy4hM5S7fTB8WDXKqFNp
1PCH6NBCEtUiXRVgZlBZNS7oiEMX21GMTuOgORgDxd7zf1B4n8uAH19seq2/QffFmA5usSVzLNqz
XBDwBI9737ffG6jqXxdA1nCYT+hwMK1WpldersxQp63LhfyHnicofpct6bcuLC3uRjlk+8f9oFMs
IBynI5r3I+f/L69Z5HnkBLVoSdFMTJo2F5A3sg6/YPdzsPSDjuVv83iPd22cHXeg+79krMdXHKDo
q4ZFxNQZkC5hV/6CLQ0qga+yDj6WWOUvqiC271ImBFZL5ndahsEetfCrdkhUwJAXLg2kuFYYmYXC
64wwS1p7xTP/zCV9WRx1nDahUHhppHSEApS1Dd1i2zAGWlMHlKJeKT/X2u+iUX15AyaCca7Uuikg
s1HQXSy9wcITBO3mkNotYNOWUQhqwh+P9/Ab39A84qxyQxvHmoh7PixjQ1Kzb4U3RQBMfWKRMie1
afKB4myCk0A6NBULQ+CpMZ207eC1XXADqNbWVHecNQDVT7Mre1Sd1RwX7KQ2Kki+E8d2WxHsWR7H
r8wOTsXxAA79cLO/4CSXEPacP4sKv9B9QXShwViZe+VN9c6TfLjLbZ0l2a2kC8tHuqRUbryqe08T
k3Gx5MQ2fH49vWnhr9lwhjZb8XaXak/Kda7otn2g9dTCmjVJNf9IP4Sqp/bN0qft2BwwQv2cH0vQ
9X0Gt6/rBmrOZpkWYrpdcSmvAnRoJYX/yS6zPlgL/i85fkZV3GxmNK+gdIQ+Umi+KcwHfGSr748E
Ar6fxfcZdexK/VJiz2Zvj1UfzR1v2uAWfigVMfFRMuYjPirWovD7Qx7mOFMecBUKce02PEoUZyYu
c1vuNKKOe6D7hGRoQDwY97F9xOEJDMdl/RRg1MJZ1LbxcMeh7fvEJcHVmVyUNLcuApZi/563gvDg
DyXcqupNhyPKfNhB0bymuJSF1xndYiVDuvp+0zGAHaaKCX13+hotRMwKG0gM/iWm2WSG9zEs/iiS
kY+g7wHj+UP2vK/XML5ZEDLS/qacp1PjUDpWLQahzYb2b9ToP4W7rMy2RR4hBRzU6ehUaC5atdtR
SycSggfOaSW9Cax9NXoMzn8eNFL11wyfBdC0YdWXmxGO9vjs8s9uaqeFMAv/u/hYdVUZ9nngwStt
FEtVbuOe23JOOW0Vy+M1/Tnjs9onQhJlku1nesUXL7TbCYFfM+8uuhvjU5otpYyLpACNq6w3Tdo1
+kwarveO0kT+FZwNEkjz9HAEjoFCNC6kIgB8FO+X9NJikjT1lgPBdlDe3iSjmF1CIvdiJhYK1Sdx
9sBLxDD0k3c0Nv7Joy0hnYnEaYWMeXehB8+vrZpVaHI5j5X+MoR5jkGn0tiNTjKrFe7QSAx7DIxa
VrsRkQJ17E7++BttqKhbVcTV/c6cHNYXVbvl9CavhxWcKdKgUlYY0QkfCXXEvJWdaQhhSBBlu99o
zp4X/I6r++3iWFShcQdlWXshcKpysDEN1w5yVgikrQ6r15bxaxoPUjHRWIQbTt6+8otBfpk7ov80
FPWgrq2LRPrQpEiNBvWswNxRIiRHqxU2Op0agflui2JvZvuAYTWsf2pW1dyKMive6JRploU9bzgu
7QfVNpGLJpbFTFjFSpMVd0eaYXpuwYrjSOx1ay16UkJufXJcDok/Q8jd7OlswvU4jllVrAoT1ND9
4uiGl06OE4Z9rw1TkaIXPYMJySpFyVIuIaeRMXiGAwiiJDBl0aoU1yBRws9VKdViVvEvjCqflAhf
0IEIniH+tnDq+1vqRbVZPm87te8cf+2Xhrz7IXFXikzkq3ug+BsPaBGfOrzvRFYswAH5vTk+6CLp
bRCtbMBy4bcPhjWCGA4mox6c2gXCblYixGXyIf3PjoJbEht14kFsc99Fpa9mYJrvoI/3fizgkpAm
j0S9+vGYN2TOTUWmst7eHl7xaemjvNCCca0Ca6jAeVbx/0pFlS3+8PYvri4miK+2o+I0VtCRwA5c
VY70THZKqPUFHS7h+XlPtQ8pLeuvULkUr/fnxLcAinXLTnpQLimMoPypZg9lIG6ea9NemDUCJQ7j
Ugq8U6eGp5HgfuKdZ3W3P+qIY1ronCQYza2UCyR7PD8MkSNQGa8TQwyaLFNc7MTHKQoUimFgi9+4
jTF5dKnwxlCact7xAjXqm/E2QtqqeQqwc5UDCYZfoNO5Ndkk5BOg80h3g00jzH02EQ/TUoj886u9
PJIlBNT17XjxanfEiaxqnIG9PFoeHfwwFrSbhvlqeCzguKGsWwyH/M79XzE6spymoQiabLXOg0Z3
XgGMxQCv4vOeYACKiNu6DMWL7YQT6WWPm/NWN8IXcxe8rir2YCEjmA2o6rhbnOt1DAouyW7AejKt
KU7+3Bdr+jikcZor81+AJNCOzovaMp/veRMV5mhiO7DL6jccqkljhkhds1SbZXdxYImEBqhM1pCs
cFcc4B70O97PuyxGf6KVjSecCd08DHyzyhDdC3c3NLKWIk5o3JTqQYRpycL8H8mhzfYYXapMOJiS
uinojvkc61v6Sk1p7zHPSUmWMq6u1UdgbLtooMNZvAy6w0GfINzLe/E9q3sQe5PBaDdTq1PsUnH+
KYChQVAMB+64otZlrF9J8EaD5sZUTpXtAWaWy8CvZTXJfC1p8ewbfoIQ9EmMViEXtzHlAQqskuaO
puffJzm2byq/zvgwtuVDxzHiu0d9K6l8I+M3YMA7HoAfj1W9SMROJHJVw65Rr0MEitZNwR1Ybfs5
wJaXm1xVoygy4SylSBMMqqaZNPdms762I0A6DiAfJNiFa2yOHdRTu+806lqI91KQ+j8mMrLDZYEQ
Ar82swIfLWsWDdN8KOdUuB0qckHyZitngj+XZiujM4Gsz5+9K8Z4rY2FBnPfWEg+jciwP00mNVEn
+3t17PpYs18iuj4ADCMti2CV/8J8XMrdjEMC7VBKXk7TEBKwbh4Ck2NNuG2CukxrH2ss49psYx+B
RY4JQnb1mZUiTSdXyZHCTeksu4tNESz0NC7iViJ0Dzkv9EykpmdPN/m8kJv8aYx4oQrpgx0okmCf
QtdbLse1CJGucNQCeiRdqAeqaY6s5idoLGU6Gupztq7PX7SZnXn1iiFyGMPJiP/LwZB3DXjBBXBG
KHM8AuYsEz+rf22DJ+/323hdtkVFDYuU74GEzaPSr4E7I8hbDDgzEmqn2HdhvfBUyNPkjWTDsBHJ
s9C1tYlqf56UzXhLKiEUSIH7i/+B6D0UZjxftaX5QyZgpNOiAnf8jaBWOi0TTWUOEuBjCJTu4rb2
Vkl/vHPeXO93OJQU1PEdGqheNqRTl/LrYxUcledtDxkSQGYBlcYrGN8M1L/ULqX1aOuycsQMBHal
3+nxDe+JXnXWobEDZx5TeOyi6Ifj8R5lTVq0RJXHvRfOBJv7l+fMwv964BJyGdM8+1OHkOE4SG1I
PX5YYtrYDxux3TtBifyBDPisYjXyGDOPCmHUTV12kDix1a/HyiN60oRIu++7gBpDL9qSdOuewaqF
IZ0ywWeCvOJrIhUADZU36cvSN7p6ygncgVJoX+eu59X+RL5mx2C6LoDj8XdeZGLWoBBATIfmi3Kv
kViW8CkwuTMyEwZC4NdRMSFMPjcMd1hu22U/M6OfXM4P2xXOdiZSTgAhQspOqqsBJynvcp/MIrsn
tIyKIqxbun0J/lemunrFBqwuWkRBWZv7zleSnqavE0zfR1aZaoHwbOuAU8EhG64RLyET3WZVRSRp
vOFVTwBXGENf3tmD6UtfYEkvoGKzWaoXd6MjPAtzIiIMYPlhIO1/8P2+06f1fOgdjqYaQ6MckNBy
G5auUXq/9AGbvGwApeVJaRGuc7VGE8YLbl5YSbkAVwWnyP80D74NiWM6iU4KxTOcyxGue9z6N2Ha
FRzIhJjlslv+hBWRaNPgKTSX18V1g2v5X1QGSdu/vQUZR1Vk9HU5m79ViPqWVbqf15jRdE4HRRZX
Y/LG4M7p0VuSFR5pzUDYKuPpaPsNjizKEnFi1sE6jdzqswir0YQrL9VMiROorG6MmnrHjBHQ10gu
k1z4a9jrrtyQzl+7SaFjllmphfMEFKP7u/7NthnJO9nEz0sw3VIz7TIHsaoKjWW+VYs70hGRTlOf
vsacJLuVHGQf4Dz3v8c/II+3e5dPVulGMqeQlVrIA/XZb+YfyX7zorXjSM2hDE+xJOnFSAQXpzsr
WGZu+ja/tBYKIEbbTeNrc6zloE0qFAF5XqRMNsMnnVYRcwy4HaV4Y7f6uCalo+MJ0OMQffPKtc+U
dhB7xTD1iF8AFjqeyV9KPHM8KeU5C5FYzGOJsgHQv3gZalRLq/t/w4ys9i2lPBQOdjGzYR95aLEZ
X2hSHqVpog5D+cnPHDHdrDF931DQFwEX1PGOiwDGEU1lYOnGYqCUzNRJdqbGyX4CZvKZIv4FNXTI
AbInVDh9DfFOadmoUC4dzewHPddgPFBAkMkYwbwYsERLJYyi8o6FaGn0SKk0hggikHDJXnYBt/S1
28VMRDeGAzbB96ulFVcsewil0ZSoNYXA0uq3WbRVA1ApyYzC/R9ibLlHMKynVLyhI4FhIpNcI+1e
JTnSQdI9KolrpcOMLXZMLldBk81AqPESR00atYlK939J20M2FBoEhzm3fa5sj+NPBweTOXCqIxC9
h9WEbOS1mZhgqm6+K8P7dft5eAqbpyccjsNXmKyeJVgsIrfL4ZbBqTYuE+iYtqNBDzAbKfSvSln/
GAwO/yZx8rkHUFWGw8DBx+0LpOW6eDb48qsAtFfreouSsUTjUzLcDlGn82zkYpuAA20rPRe11yKZ
ADEkb/77JgJaS1ITtm2yFYqUtF2sdFYcCdq40lZYILso31+7Xz9C+e3OO8SW6KTY/2dMB606VymS
XMJo3UZQui3HUJPCOw3iAz3Z6mLUVt7BRRC+DOwx2fAorVIf4frWtcMZ6r9YT75jBBzmARidwNhx
aC/8hKX3SWxfB9zJn/xcTmXUiSXnxf6cM77PEvJC5SBmHI+hxPPexYOWui4dVHoihuas7v74b6zK
63ZbkJENCWijS46YvCqhM7lKQs8OruXrlF7MO83lGJIUlT2qaTcj+oofb3W0woOVspN2vNB25ls4
YAq/5ZKiHVLgiGQvnIRWcBLzmk/VLAkmk7Md8UBFgPkX8YgoxsAfKEKyFoNFvX+xBPdxBq/Sm70U
9ZdibwQ8y38OkeIrcDYSpXz/HsFshUep/6UXVvc/WMSuFJKxQjcegP9lUJ25YRmv2NxCeaY/1IaU
6Kx+EB+wrUFLAxsoHhi+gOCuXvejFSxu1ySnx8HKwYA4R4W1lY1viR2M8PuChlC2nF33ZVHXJ2nQ
DxarSQnqlpDvrVKLkU2no5WIDQVmbynt8DSAEWqJngB5ZQVFTPDbPjf3OOZnWb+g4ylAEOal1IXh
r+ahBktvSdSsEAC2ipxUYh5vhu1j+0r6OxU9kBmqYhZBF/s74/sJsAtGTaDVGape1/a59ZypC1nQ
a4D88MU3fMEgDrq0KgimV80qiyoAPyZCyhwNF3cNSAwyqR+CsVMcIkkiGwcGPnCdGLVm2FusRjW8
B2vMSrX2MX5TTJqpjhQcfRdfv5pu/zQAEnVSxZzlxA9KkeurwNCXlZH9NrHf483tKikgz82uYpcr
zmAqP173dzzYrKulO4X433vMGW3EBZkHDoF3OL2nH23aJzfyF7QGWCQPpQQEUdhsxg1x+qA6dwQV
m3+P/8NlNIJxzxtijOTfeJfd+nyUfR2ZCFanVjxzJSKuzL+Ct1zfEIR3ffngBmiuSyRUbU5bYQRz
IA/4fNLcSS7HcLapT68DmS3fX7pLI1HUuNDBJgz+k6VTYN+0acyYZ3FWskY2A3HpNtvN/2zik8zT
sOrrenvlS2J8NoyzpLHEbSeF0JF8jYJMPOCobq6j7D0IoLbYOiibljzBYuatKndGDJDPB+++UTuJ
y+GSDRe6P2f7DIAVe78um4Zer6v4q/qudlM3gSdq/mVXxUU5msmjvaXmA2o46Ez9uyFccZOrHDEQ
EFaFOh9cJI/8L09LsH3BU9gnTzzpe3Y0D1hpP5YfrRGI1pLdw4yzXFKfnHEyE9cOT3hWlmMxFLSP
6xo2+MkB2vhVC+Tq5fOO/otnFzBncr+pwQBjXDvLwEm22FtdlQ+qH3fsTIW0UMYVEV/bXwN0NUg+
FSe0yQ9TfVRbenHnro4OIizPQz66l6HvZtj5Kj+I+IFtpTmMpGCf4mY87j5pHG03Sn1c5cys+ugh
16d1BadISCfGGGHOfOn0lIAzL68iqa4mvxE6ls0GYHe4/ymZ6liKE8x/37jip2+IovIQmiabDtyC
3Ru1E7nU+eBK01YnsUxKHmKZPfvQpMmGtfN+aQPq5woabaJk7J5Q/eb4kUFczyux1u10U8fT2dG8
Nqkd2o5wN4oHfeq9lwBjgFOnh9+ei0Z3z9Rqw3zd4uMZSC7FAqht4ztzl/ELMdIuBxTSJ9jiUASe
w1WnYXBc9X+EZybEnUwa4ZaMczdCqWfvQOR2HPnAf9Zzt/8zyXW3QfJXBNDHqr5zLsh+fAoHi5aL
6exI9KLDetduu+CAaCC8xj1IDKZdu/QDqxB7yed6jOSiTVIUUer17bE5JwtDElWwpM9LRXFkNhj0
WY+RE2IYkH/QIwHi2zRrX8hL7ief0FH4m+MaJVXMltKIxM+Jof3IX4tyryjg8pyFE1QDmXQXeGij
Ns7vatC0noLvq91xL+pEOCRIUkyrmh9gw6r0w5p5h+dwmMahv9DNDj3zP8ZvLIo86jhKtpKvPKd7
09EPCG2ELXFpqIZx52sT7yKI31aeHcPZLyR5qUbSpdIuHnA68X0PpQi8Wj8jdJlbGOsMNHRITdCv
TOqyiBxfRy2Msv8F7uVyRG3FMzIxYkUfM50hLEsa5U3kiD31pXL3RwXJ4aTV7UjagZAg31hB3Ild
R8u2GEXmePCvaPYJUQKS/PSFf9n6gu3Y3Xx1yhQ+WqU780l2MklO608HvMmeqIIF2ba1ZZlgW5F6
6R4EZGB3JzF3PFttbqEwzjArAreaUVIh53RvKsJKyai1S/UWH8DXNw0RFueEO5h8DC8ScLyX5xgr
6pn8IOo8TWqxOLL7OffYMIBTgvllZ5enpdzNAvXuHM95eW0sUOnyMI9wR86+m1mH1W9Z2CF7ccOM
4jmjwPE2pgnO/oPnZlFUNt5OcMMSlscStgTIBc7vCbu8QHX7Kn6fqcYD1yqzNfoJ9k/68jmPJ9JF
ubiorVUxDc4NFYkQYg1XMoBTYrJgxUuwUc4eHkK/A9uYzvRrTYKo2N3lLWdpGoD7/nuM+8PvrlUq
sVeDz/ivIMG61J+DruIquOqTOB57hODWG3k/dZ7Z8jqmK1q7Vf0zuRkRoL7T1ArTKz5ApG/i6kx5
yPDD5MnVi7RXgoa54lfAtWbAOuD8AjKX+bfr0bGB4MR/YitnTd/oKVoVY5og3Y3tP5ClO+krsB0U
VEqZuFcS71qdCihUmMh9V1qg0cCxims1ouFLb193uyUr+ZwIP1UdQvF9gYh1nOKlI1a4vzNAG7c1
q2CM2NyTi3vRy/j5k1lL8ASWqIOZnvMXadqZkHnPs79OEOeBsy+e2QlQ7BjWBLZD+1Zou8o39J2D
ZS01idcS5wxp/OVmHgemnovw/1EDeStzjU/3yDdY66DwuC9JFHJ5Rilu4GT3Wpurm9USlRh0PYw8
4W8Lwuy9mAq1r864Emp9QafoOdRLyxMd+SCwFuHpe44o4PEyUziPk/E1qx+rPh4mkNq/j2K3HM9e
ygkO6e2oZi3tC4WL/Glnf6H4MzdSKBKc2LGEOhLAH5Qp6owSMMiWxn3qmXDtVKiJVhGF2okvP6jD
iv8JIE/cLYY+E/ke4P8OJpFkzQ5XLdiptkBoEi+IVo4PcU8GFCk052KfUWriliMWlS64tYPVuXc4
btUSo8QEuJseZYBdeJfVxyf041ZjjpPqXooo0UbIpb5DwAeRxwkjI+WG2b5dsvdNaHdQxCYY8AT+
jdKfhVWgS/F/mRYSjGN+Ii90ZU1loCr206UmQaiBYcuJ4G28kqNU84ZSMMfeI2Ha5kdJwt+29u2U
zQwiGh06Lqjjt1CmwbAVkwNib4NM1JI7VfUGxE3ze4TBXvScJaSVNM3nhGM7uTtr+jFhiPUYCoUg
OhqgqJxoWbFyh4dojGcgIh39AZOE0QL4cNdkBjvmCMFCh/ODXqVJMTZmj0w28BhmYRSufA3Z8x4t
X82anIQeAm9K9361F75Auxyqyhuy50tor6mU5FzVLJ0P2E8EdRWIP2Q28Awkai1hFUbzfSMaRWMh
/9Rl5ajLhoBwPBPGOXd+66Bkyk7KAlWlYwORkCNaPZ7N7Nwv2KWsLv4wvWP+NRY/7iB7/wHS2BzW
0I8n8H/LTzomvpGhndanUlOo1fzPEwsCxyhKiv1fNPVjGPRWy1DQmzfh677UuIV60+b1Yq1QNhd+
A4aK52YMVBNVQDbA6AcQ7UPWJOcWdL4sIRy8WQaAFGpQarZRII5rNoegkDyW/5uRgxFuBLamNHfg
yys0iN646sR2VHZjqnXef7iH41VfcqxrFT/COlqZWD3URI10w2efrp2fa9MOq+c31i4nabNAqn0E
AsLk8MglKsUVvrBe9HwiKgS6hJUkHU7FQxjVd6axw50GHDzKflbxvA79pxL+8c4xpw0OHPeTZjJt
lc/M1EgKXMMFlWPqKadxQgsPRk1sf/56YXa8q+JLUtLxi1TqYPoLhngVy0cLAz2jWU/7ia6KMQis
9I/gNrcDj0i/cS2zckfavnxdCQFnqAkodHS/K4JnWWvrWeZkR3yzrzlRVWVayVG+2yjY+qjjfHJ1
liwtLB1gyzoyRjmyahRv91hFAQ2FNW7fixjrnpUWqiUJ50GuNJ0UHQSPdwuDgx+/1qPF7tRDniY0
cFWTppHFTsYu3C0XfOiW7kPQuDzNgHvr3znndPrj902II2f7H8z6sxvsy4goC8VwfbBGgC2ZZXVI
gs0R8bhss40ZS8TOpQu1s25uAqOAMShokL4SzDu0CfYihXOcYunTloX4OdDtCWqyNrg5gC1KOkXZ
jMImIMxrpamHFmk19lG5ujK5+XhoATjBO09Ba4ryH9M27mPOputQ4FQaLnR1EqTOJIB4Ac6UudIZ
YrkDMHwazJYGIISjn4d51xC6d85H4YwXjMsDgUgPuBaq/6zL0J8XNrCD004rxZSIfs60JgJnO6nk
ew5oTCycQydceRErbNJMhk83DNTZcJL7tRBe0yTCdBp+ARYgOVKiobd2XrBAuqCwidvCwqAJJ0+2
DbIr8umW4LlGDVFjCw195ionMjuVc3p7CewrE6bPGjrAo7uTmjdhS4n80XH4EYz57NqWSLPksJxi
zKZEQego5efST8JJNksgIGqOnMIc1gtjmJO+51dq70sQRh/iXMwanLQJx1wdZ2S8ZLx/1oJCJ8CC
3thQQg/0wUWDzVgM4Wjp51wbYZyh0E70b62kbBtQKVfs2quYDOvDajg+Xh6l54BnC5oWBteK6xLr
hFPnMyFu5beCDYvxFz8nA4TVoqR7u1EwW83PgAp7Gpwby8Y8Dk6CH9ayO37Il4TElcSSwQgZh/s0
Qxe6wK/1hx/PNEPXIpr9wUEQ6tzm7Gh2KWGFCi4LnV3HgoU3DJILLPrd0/8oP15KxkFJ4mFIzhaO
MiXEz6BLLpQvkQD5Zvk5O2UwQt1I1K6KHDgI2RYuiXjdXAr+guayI2RcwOECpmXqIHd903xtN5M5
MQRqLaiWPKofYXrlAnmGOnOykrERifgNKEeStUtFp92Pu8lqAcN8XLdeQfwFB4fEOkhcJLfXo/q6
/yZlU60KSaqbO5AcQpeqkRk2AAv0YHthIUFNAmcMh4ZK9c+ou5CcmIT3g9xBNVrBy5qBACa008HB
ndFG4zMYNf55I/JYjH3qKqaH/bGO8bPXG11x9X0uea70k/yAQXkHKvOUYOgln7HQnv+ooaPPUE10
Up9q8PzbSJ2a46YJeOHxdHZhzs2VmlALkymXe0qYVpqBojS0GWci9WBGpiMwGVhRJxZK5qH9kCFe
U46tYpbs+eB+47hE43BT26GAANsit6+hg2/N7tlvxZR1Mxn3NAKTAnJk1Rw6dhEOymVrH3H/sPtv
+IGViMVEtOtHVnLNh/1mDIVp7O6NWdVeFKlIA5agBsTbLm84F1NQ6cJeUfLcOZwS8jzgqhKDcpXW
5R0RapE9nb8+X5oOeePEx6WY2c3/zq4nXMZMV5plYpx4dJUekfgzkiOWEzfuhOlwg3l6f9XD36Wh
0CwFqJYeDQHEJkMrEP2ngAWsZsf4EvLNVQFQHHvhAi8+JUc1kJB94yz2zjtj5gF2rDfj+Vciw+cl
vu4XR41zko7yk8xq2r5CRAYgKMjZZgDLI6fAN37aJpOR570675h4PTe5WzBKxVtDmi/a0Fil1LTd
MA1xKXv1Vsn/JKS8cFOlZSpcvu8Jv/geN12GVYhTFW2GGNfaer41QROPpaDV+eU9lKzIQRWikUu8
nW6224v5foM9VkYgmaTKKBRFc1YpjBgj2Ls/hMUz9xvW5QpZ9Z2uzoPXLcpww3EeAu0EOfiL7Xik
PIp8t165OBIV7gnDpfbybrwddZyPlhf9b2yw2ScnuIldYocYohV6CTCwGUkZf032s/ubfDkG3CWP
U/DqE50Y/cgUEbI9V3DMi3DcTfn+tXHPQnCczlP0hhJnNrbGSix9wYHhpHsYNVyFyx/He5PUDe98
XK4IYAM/qwIWY5j9X3MVOzGVjvLPflHQC0XpufO41lWrxr3JO2TNZPIoWZx+LUmuZJajQqWjaVH9
SabZJ5Uoi353tuNgdyv6eBtYkSqSPn6hmts4SpQYf8iojrcpAmzrJHxamxqBeZr1cCvrVh3pgMCk
NkVH75ulR45p7VrM8OAk8ToeY7xzr5rDj2CfWelqE+QgPIfZVCQGdyS802k6n7Y99Fz0TGNZur4a
LEXT5bYcxs4lOXfhRcJN0eqzmI/ThDQMFTrpV9xVcXOecCzIpqDdvfKzxmUHUKMptLzyJ4kaNs2u
gxboDbocjxMJ8Ypx3hNT/itzVXmHEnsfEwQeSoQtLNeBFWP3Q4wkpFk+NKFQMU3eu1ZUPQdPLfpY
gHnl+DVeW+ErhqwUE0CQBmWKUfZ8kbWjXcPh42rJG4R525FUqaCZbBA4XOq+i01s07/sR2YlNjxv
5HeXnBa1W9XFcc8ro1H4kF3Hk0j7hYM8JcDa0MN2PrGEfegqo4J2UOGQdJN/2IQpa2ZCbnsF+kFV
9MT4+mp847QRT425Z0zt7c3W32IRGNkOzgRIMvW4tqSDwkEzUP3gIrePmVSBEYAvRF1oOQf3vUSr
9AbOK9vL94siJ4q7Bn9NvnyP/Kv1aPHMc43lHbtG6UwS1tGvG131UIBsVsI6tx4J0tiTNtGvvaQr
DyWCM7hG1UEs9iEoWrTwn14coYG2souQvXtPmWRNJpHdNAvXgxmqJfCVuPY25jrO0jxR2iSXzhXZ
R1rgefkpkYXtA7cZhzGNxbNF4XatilgZcRIE0SS2kApJ+D+0I1EYua0d2ypk7ohdBaTCdHOE13qS
kQ+xNXPU79rJW3XXqKL9pfe4IVs0eSAeCNeVGdkfr0uTX8z9vDwUJk29k+JmhjBtbHd3I5NFKmyZ
AGaRXwKJPhDTzN/gAlpUUjBml2erimqNbrGddvkkCaFylQoSa4b6cZk5RFSBmWbjSN9WWQGz+tCP
R/itpil2wdAv2USX4q2CY3pqZYdg11nRgtw0YT432Ukdh4advgToIQFBC3JX4nB1lVDVERE0PuUc
3Vho2LKsgWMhssHzLBKkFHFs/3kpcTwtxnpDBE2sFnGBgjB3eBlmx+qILO8JdjPUYQ4qvpuTayW5
qlxWf4l10JHK5OfoBixDLLriqE3bWE65m8w0geQ0USeV9sm8YIonOR/nYB4jGIAeMMdJmvl01Mhy
BGeqU6SiMV9prts33K7oMACYEi79gVnskqiweqUEsOVDdIuOCDjXqq+hjC9S11NRMxp3Y4nzxuzp
6YRcYSgSZom8KARNnu9zkdOSyWHE4jhYehLOxx8qEme3SSKjI/1FuQvfMOOEyewPVj2E9IKGT73P
S+J/iohHuWuk7cKlr7BbNejIgTkB+W9nXNewB5kQIiVtefmvqijJCLh+ezbF862lXf5RPCQF6fmu
JInym+zjO5WCU0ZMjYqbdIxXa9h5ZL3EYlZYdDYmAuzfh2y35yr38XY42NfUFj35/l34mbdjOyoJ
02fUX3QFDIM6grZBhlHs90muYZFKRMa7L2KrmjmbeilaUVaHh8twnUmO0ehfgJQBQHrS+vQT9K3q
AYyd/EmbpZDUJG9pgq51wltoXRD5TkTSzcIx6kXDBOVmohdMHmA8h5NizpF19QKjbGNHavySr3jh
fV8ahO/ThA0fQoSY1gf/Xz2fr16JiM6RtVClfyp6XXCpQbXwrtOw6R7dkEmKdbgh/uAPGzyPRtVH
mnUg2vFNkxnMFPeci8+MJJGvlELa/EVYO/FmrmTRTeYy8Chcak/X/gvjQSKkYScbnqzCyiszRENf
sNkntAqxBN+Hto6OP/3fToRI3VDHcgpKBQqHKwqGLj0KaTLue8IStnQvIZdngX2cPK7EkxbjpT1T
y1WjXKkqK/D03x+SvdYkoB6tlngR1t0+UeB3l9Df3IgDGo2rqyaYnT1jun1skRlEATCxHjnP4zUD
WgrvEF9yK8M75p0V4izNEk1JENFrYSgBHi2MHY/KUQuTxddizRz6lajeRdc5VMmMt3eJsnrR4cj/
cpcnB4SENBIFbNn6sKid7wPub7JHv0rxNtx7TNZwE5svnuko5I6D1lcidf1k40YZ9aW4+3IHHZzq
malcWKU/3aZa/uS9g95D3ZdYU+S2U1qXdwsqIhI0+6r/zHwtDGsdgebytGdezwsySgI7DHT2r7Ki
3ZOrSuAO69jnFQZkIZx16EgXSW/uVvpRL+h54Lomg0EekcHKJdeTQDAv3gIb5N8m9wuuPYXSi4WT
yV0Tc7P5JafQDprhyPiJC2qxU9ACkB0BMl/Lju+PGnoxZghR8wkWLYtZv6Nj0uQKl3itgXG1jpRJ
5B3z0cKH4nwdvwH19ZwoahMIh37DXYyzDq9bubcHNycXkD1e21/8zl+ubEJdXZQ8FcbF6MMuh2OL
EzvtZUpfiqhbWxpv5K5cpdI+jGp93jWdnMiX8dSW2/jVyGq1xntYct61M+E8GlpNu9/lMumnQMit
1Iw0KQzlXIcrM8U1j7ZNKbTh9YrDvHXM6b4zNQYHKwVdS1ptyzp5cHT5umT1peUmSPo1FeznfWL6
+Uw+H38QrQPRpSAKGVnamnpQNJ0B4bKBv94ROv4fd3/S3Lg6X4BtyjVPfR/ljKF1gSHFaAJefKPy
/l4Sn8p0ZXeW5gJXotZ7DMBuPFGcVEwcaen7tirsXpjRlcML/PDiuYo2Mc2gN5vdnvecpy6b8odh
U0TenaTB8oCS0wsiUWOR1dncWObt2tFuJU7tIRPBoiRAUrFoaZWv7BltlG6c0XvCNfrU8pP1CjIZ
yQq3d/k0FlNOM9tb76Ua6wmvwZTFwP7xlVPG0YF60MfIGHtiUz9d48QQgKmR6GNdpOCsdypykwkO
2sE07eQ5lEMXWmaiIOZhbl/s2OXxOwKDhNviL2K7poVNHEPwUokPa0tC966i6hNicI8LJmwz5zcM
NtFimIhQPkAWHClabpqKTXOGENIAh7wyLWPC0SCpsKr1XW8WnmeqBbvDGAlnXRjK7vHD24Ra4nNZ
VBCUgvbyubgx8iuk09LkYhneYe0rHy+uULF1Zcsplg27QxQ3rGqO+VNixOnITc25dgsu/PXd50lT
0ZBBQTMToK3qM1RlG27b7YZ4bvzICM/3ol8ir5XGh+clGMdJBSErfKaAb30cVyYgck2O2dinctzX
tbkGdK1tXULdHBKMlrjiFUREjTDue03RJXY75YD5IbSiyPlJ2hGAgudvyoAptytLwEhSDMt3tVmT
+7AP7jVa1aKUXtfhFl/CN7KhMkMHFoJ9HdLNWzdqeUHAJQ+tl4jM1p7yOGpEXDSSBQB/g3HIe+lR
WpVB5xN1QKp5TzEimxsG/AGWE6i3c4IXyzJMxsCz+HZG+e/J/KLijk0H9jt1lSgYAUPLHfQk9zPK
SVDItu6kiVJELIeoIPmMG+ZrY5qvRweNKVEJH1IYhRrMqAtvYLSu8/awRx20rzY6CE9sW4YLECmf
mz0TUtE7DVPjS9hQOyuSMFSUuevk15/kSZLWNVSEBw9buSTL53uq0792fxOb4J0VPhZiKuHVW8g3
fSU8/x3wgH5X1qqEAVo2gsVcFryJUKPs/yZHB55kkJzQ8qeFmRAmYXx3XFbKhObp2Kv/xF/k20aV
BLrZ2imkyBAMI2QXByjy2JXnDO7MGPBeah6dvHEJVj7ZF5n0D+Yk8TrUplNrJrkWnlLNMj5GPdQi
Ids2XJxet1NXHT1qdapov82lGJAA3mZGBk8uDVC7qVnzxGcIB74cZEODcO89PPNhc9ip2x2Yg9eJ
OWys3fOtjvW5xyl1pdI9pKcQL4hBNjyOfb0Kn/zwqMheSWKvNR0g3qHTWDrB+Gfc7fmq9DIre7vA
QelXtL8Vr7v4E2R72LxVi0tFL0QP2y0wEGiFlGOJiuU1HOepD/BSdmVRpktrdqrkRN6geUGK0B3s
CQr34k3d2dWbZMd3Ea1RnQq6Lhd9z7CaTJsTlxVqdeCkjZhxZYvHuP/ma/jn1uwudOyozCU/RW/j
BN0pfjdNkeqDg2gjmnWNwTcIU/cUlI0/6RQAuSCO7cUdK+V0KndkzIOeiT8l/6CtShKhhcUA83Xh
3AXRA8c41GTeHyUwOWaRqwBhhw/oPB/xYkSrPInyepS2o40Yy9Ca5rStGxj1NeFDL8ULS5coZXva
E/UAO+Rx2W/LQczutZAQ9uhMXrXuyVedAbN87WA69nINXtxLOXTOy11nXAjMSgmSNngUxzKDLmvM
PPhfaoG/8y1ZSa3JOGBDEIwntZtrcBAk7SZcfb+J4/hK5nxu/HYRY38FW1vXtI9qYHWJCDOrBGUU
G36iymA79d/AvKq0uvzpCDLHv0d6pNCUtLILTNFCpe1SokYnRK9yFAOYI8rZ1vehpGngFafEHSd+
IefRpvtFYyg6ii2OYL4VTgqEQ5sjlqWHkSWG2uJga1VH+nhQk24MolvTqvlHhHw0Vf97wc4XcU/O
KVSOKJ/Ry19spFZ0Xlz76NsEFh4ynIMiAX10WETAXEbjB82pYH8n0NpyWG9RJ5gugGIOC7yx1TQ1
4VlhMcziwSMg/eki95FZEVD2NNYCl0i0Hh/jyGDvFQARYkpvfg6SysdaAfGEXGgAUt3caNqnvRJF
FNYRVpE8a4pjm2oExESrQWmPdp/K2muwm0ooXAFVhtJ0k2rMIwtKEc65gRRx1kXmqVjbRRPWkDg9
rm+EJlFcksw1AzuxoMqbu2onilAAvECazTt//TONCQqzJt70KsBKuz62EQ7/L0Wf0w1h0Z3bgzMG
Bck88/sxqtSxGy/moFP6gRAh3xDbPudzSedU9MO0DacguOq+IVEUq5Tm2b0DdrpcpO7XNuxuUEDw
bI9/EfpB75GSOt7RexkRtApH8fvmry4FwpaunS5EDS4Mn/Zmj3bCjsbuMzzfFIE7dfrfq+8Fa82G
rOZHc4zlzYF7vNwuSewwChmb9V6QMdJ2+sIcjmsx0lGuHSFDSXllZaF7Lu6Y3o+TCa34e84e+wLH
galZiXISN6xFi89f40ppLwCiRuw2Jhq47Fw67FtO4AGLLVWc+JFtqztItY5T6ccSW5GtVNeNbetJ
ZOTWTGLUeBlW/TGHULtf5CegHujabj8px3gaJpd5tf37Kvr0fZUiVkUnRH4eqZhQJWsWZ6N+YYT8
77lsCQkrWDwzfxscn0K/GXw45z/vKp4VSfczJD8LvK4U5xC4Czpr+lxZ2XqbVbs+V0/gPZwNijuK
r2c6xoDqYQsoKbheagZOcwf3jsKrTFTJ0Llguwrnn+IPuYtbRVwF7hi21is/0TdE8PREgXFgHCpz
80LVMm+DIO7wO7wkqliWwmof2KcHVOkl4UFy1J4gPvEvpUwYex5Vmw2r7FrzjLnVe6ke/gxMU73o
zNkuut+cPwPcU94dhk5ELsMnmiclRwHr0jxNnb+MrJV2YM6yaOWNUQ5Y3ftu3QGULlM5Z9Rj5y2Y
UUUoWjVSg+IiSIBNGOd3l83e2/+mrIx6zCrazxMrsxOuPcSeSDH5/YxeA6ZEEGzpAfmUAmsRbbTF
zCrvbHvfiDZ6bZDZSVhqfHofVWBJtZK517Zv330wgMCQd4/rqBxdPJiujDrrWcY5w7eJJHUMWrbf
iUVc1rngwUQhozhMqXes6VghBb8SDvgB3Sar6PNRrH6nM60jd3xPmHA/OQIipgpwBEehiXPL/l8U
YOGulv0k4ad7nlBLo20o04+51XfJqe3fMFuPLxAa9hm5c9jJIERKfejF/4mmhyUyI2ybjCIvMHr1
ZssmZ/HoDL9+R7OOovxj8A1Be6T2tvD8B1xW++HDvbBkgyevM0vbPv3DZm39F/z8x9C73cbgeNL2
USmUEu1imeVh/rGPxXCAuDlOKMnVKMi/YyG2OGJWUdJb6ZJg/lyNr0noYbO92zdVfbpTEWBji3oa
H7CO4pd4okMRXQwNxNr5HyDjccrKbJLvRYEB5vJMLEgvpt3H+CKP1kyfgBa/iH3UzaT9f8Z3Q+Ye
Z9FUbAvucYbsqftGDvoMLjHPtdQ6ND/GbgtvjZw1DaJWH7eRVj8vP8D3lhufeVwQ+bxSMLheCShT
Y7x5gtGB/ZpNvkUw4b9zNWXDHuSQRm2NJOHMAO8Ek1S34FdSob2N+NksF7X/6BbU6WpsXzLXlYdc
CGsiv2ZKgHRO01XCPmQsyyu6D2GliAzCkTXpY28HmGbUQ2PuF8xMC4gBEW55+xQeIwxGEt4jXOLf
x+XppTextgzyIpIdRCMiGpe8JUfjrWPnBr4JWkmZl71XsvE8/TFZwMRUN68pD5j8IMminVZ3N366
Dvhgp/8GIaQjuJWnOmxrA4dGsCCYCsbZxYwgSS3YK1T/m8PtCWEdi0WzoJdHTP8IJ0T749S9yswi
3GEoidw5GebgWjfj8ENwvyC5p7u2vOLJMUdOvMHINbMXBYBu3HhwFW6MSnCgEmaNB1aFgGqWBZFt
sQlY7Sg478rInqmlRLtvl7019OI5QmejvvQFtv7TAsa0EpDO7zRdX6ubZMD94Bn2qbaWnERQF3IR
dUfjOPRU7za1jE8OhUz4BVVsuTloa069O5iBQGFZ30os/hcadV6vAcoOGlWhBqXvNRkygRSL/m3V
Vu+VMjGCV2MHz3KOg+NfRQGswTG4qMZkhjpA1hXpWKP0Kl//UknI2TwoWv8c7rhWE01lGm2N4x/k
ecYdLfMDq/pOpdZxMAf2b2un9aJI04gKigsuUFfop9Ndg0E+e0AL7L6vm4rgsnqzMe8gxx1YQRAy
Dlt9UOFM8/9LCN+tqXN80H/CHzWStOnwWPUttj1X0pt8yis7kJk+rRyIaKlweX6YG/MNWMulht0H
AfR8JKGMy3fGKiYv1OyT5rXWWGvs7RbvS7q7OZvRwZaDLqXqvPh6pJjt8kDV53lvOzxnoXvOmnhu
TpMaHoLIPz9bLEatmmnP8n/kvkMHUpg5rM3Do/4/rtQxt4YI2IlZp9+k+CVMRWkFrJOhDjIH/U/W
gW5Nu84GDujyysAG/7vhksHikCyUmWxAwpedDTie8r54P5VesbIlV1OWhC6vpxTD5tbV2XDF81nX
fS3zAYj9RZjliPyYfjl7f0mQd5Pf3ZElsWopof1DiBd2ScJnaG0ZI/C4VsUHz2GBlPR+RAStbSHd
MqGRWX8mj6fOsyh83LaYiXbNFt+FdJlMCaV+rHmLMCWM6YLgtqIi0FhozjUK4UpBlwRU3GEYIjtV
MqxKv9umG7o9npFhaeMynI/BtnPv1vdDWQwSqBKbzdLkl1UkNJuPG5xT/LYPherWKgmGA91xxKoB
ysVCocoEPBVQsuRTkj2rG6ksvPB/rSClHkky5abseDiit9gzuE8wFDbrmhSk6tzclUTX/3OXvVuT
4+xX0hpX5k38hvwNJuQ1Lq0Y+hM39rylGx2FU7cD6jfHjbu8nwDWuv5m8pQcGCqRqBi2zddZB1nv
DHsm+nWaw2NVgZRj9jukWOx+05N1KElDTiAGt0PJfYVC71Pnt2Hg99W9dn8S3CXHfnhnuXc34q8Z
Gj17jsDCXmZV9IEgcOPUup18jY5n/KgKcC0qfqpxMAGp1mKjnpQx2hKi5aGETTGk6G7MYR4hEFjn
oOKbTYlYPiMpeNNhNSe85/AfF4c82B2tR8Oui1njMF0s8uJnTRUe+CaaBdvOxu9ianfB9qzNVSkS
+/+xTF97PbMqGko5C8+I5hA/sZO1hLPaR0TxECY20Q8fefV2t856IfxJgYk2c+xFN07qYhzwEgXl
plzMoh+eLK7bquErcBb5oVM0WEeRKIq3EWEaPfRXwqIf7n6L1gjNmiwB2maSlDAA6KxYYGT0BrRc
ajBaE+e653FV2mqIXE+kyJ79M1T1u90/WWqHosvCwhbdobuCvXlU2tEnMTcvAP2VhL6z6Q1YGS1A
ExSFBkxbHtgUKEXMS+hmj7Jm9l5bejy6ZtfMYvG1l+Qt1dg5QDOpN5r5cjgPeuw18ndWFKrqpiLL
chMxaFe6Mw1od5Hx3rkkk1Ouqv99p1m51WtpegYgheNZHls8FFaKnpmJB2RazNOkztO+4gHF6Nj0
PJTbCmSWO5mV8FJQDM6HAsnn1ahEsIUhQPGI9DqxuUR0yq9vkWzdOpDJN6b6lYeBf5kZz2V83WDS
EPs/RFmD/ewnHja95y2fRHo82j0X+bxHyvCYBXnOiYuHjkHiMvVTXU1uVTtjzVbj+vjStMzN+6v1
VADIshGETMhZ5WaVekAq0sfgTc7wCcwimivDl18irwz/9lHsG4crZgmmCB5aWkaFUIWcQ28U7f6k
9t0iGt/OSs2KyUcVDxrnSglRWfAluAMRop/FKFDMGXHYJVloL5Zh3V/h4OSf6R/PU3VH3IAoNQe/
/iasigl9YgFWViBbdbhk2Fqi0iK5ZJa9y2sKIFMGnoaJQvPdO+gMkjWav9Cl5E4R0Ztn5OuzN3vU
lbPd5VFL6naoBIsR9u/gbaefKzXtvw69YCciDM0zY3+C+eZg8H0c8OsjlMITO42PzD9IFM7p+b3F
tPBDoDmwgjmv5TapvwrKn3AORmr++JlTrJcUV2VTS9wXUIFjfrT9DILCaPJpW+rn8ffJXekCUnk7
6mVbhHUXF4XlIzgRruWv+gvmx+XRopfqEdC7DxwEgyDNdyL2wSrQn6ZYriHMeS6eFdg02Ss3hB21
g6HRk9olsnhhhHsfxb5ShzVELj2nRXePHMeG2m6BmzYsFnrfyjEMJYMq3EDqukZDhKhBHJpbVru9
j+E2z3ODfUq8ruhrBjPJTFAqJQ4UzDbGonI0jzOXDi2NRJK/EbABeI+PhSEXwzpK/V7B/WkRtYpk
2rs/4zQNtADc2m3XbS+uBxce9xJ41MeOvs4MEWoxtsWtZOJOAioeIwx1BXA/4T1j+F0B9oVl9swd
Ecn8ZtReAXy5gbg5oodqlKODGOktfxYgOv89yk7HUS5bOETiaoKFwyQiNRIP51OwynOy1HxxAJvv
GY7/zWQnL/5hEdsoTOCvpwI+fGz8N4uhT104egaGxm8VNTwcNgtr+QtGRlR9e/ZXlBHgg1DJulgR
tLofmwz9nTcK71HEqK9dMJvHXO/Gh3bM5Z1006hl9sUgS/dSdf0pWwpgM8M8Fni3eW+d2dUQmcgu
Cg62SHEd7szCHjqszRbnHzGb93M904usWahUP2hivWivG02vfJaDsJesjauCj+oZZW2o8Cw55DCE
u1OuWfNLB8wYUAAbjS+qvrZS8vBF8BEGUBJW9b8yCzteZ/ldkXFq1Ql+K+2xhbsvxAQWJ5PSQpwt
kLSOtj/oeGCbNpoEN1Fj+fMPaLgIudgr+ZfyV3G87SUUtu05I+T8yPs/1tbQGqX8qqIqPTc1UKO3
7AjSXL6sTyDRkdIv5h0fpIim5cGl8N6PsAhvhMu8cYpYuAhlbzwSXYzqn988Eeqxv3/nxulLy6Tg
48HIXXqrBNiS3h+MPkvktm/WE/84j/3/bQ8Y6iyaRa6NHqiTIHVXCj8yJtvcEOw90r0C1yl4MKvS
nUMlWPe6i6rHLi4zvxPBc8heCfZvVr6prbLpnC7Ru3ufpdPA8H1MJShaulaEEYsOsCQX847pyO2x
JlbY2QP8IppyKXlLXun1DegPIimm5qdHB6FW9ymgoWsbWA+VVBnkiOAGE17oddM7+WPHUQl7AA88
QGm2mcw/WwZt2kJVJ8BSWZc2GDByWU7wYEZJ2HwHDlWBJUPNdN6DqcS1PtY3CRJozy8xYjh4B9Wo
VTeOOE65TlXUfkAc0s9aTWhPRz93hcb2X3noz2sxVbetcgVhINCieHgBb7WtBxTBgu+NzDMKr1qP
Rk6bC40Ql5/r5rAIwUtgLZlBNLmuzQVR3vf5bvvkj6+O5pgT+zCwZCKfAzp5VJQ66nxxdHrmq7B7
1g/EkMLVbZP/cu+AX0B0MzCp3JJpNzmsTMPExtptl7ZzNMANef8sREQjH6sgybcMQOVv5vmqVs9h
qKDu5FbNKV5Pf/g14kHe8DvwSwQlgBOtdEkTxWYutWaG3L9JiGT5NdqTJHzCqAyxilBwJB8Ab7rl
3G1dYuNaemU1Qe3NPfrU1TRHBhjoz3xVSAjaUwQFrR53E929D+rQU4ETP0mpPa+znUMNlfSHWKYz
L/KUULiUFUhy1z0OfiSHtXFH1kthQAw4AFncP2/j5QYNpuunJIo7LeDjGEu9h9hEAzpd1f3vc/aX
It3KnfPHnOxFDCV0Z18YNZFmezDby1NRPHeY3YtrSxbc/hqN7Ri6KBrfqitwE6iYpxeAL2OuSdxW
ThfakPVrI01fHaZsHX5n82/GyPiiu5kkFlRVs8+MCpH7dujNf7acp63MgwWXfQlhFjr31ABK+B7n
kpgq0XkP59x9WXnmQwt5gCh7qgWaV5sCSCvDV2hh4FUhxIl0++VfG1Wvkp9IUbZgB/f0bHlcNwE5
idBZAsq67vrtBcVFYxqS9r5JShdp4IhLWQOjTcQfrQ/PQopKkGE3Kiwwb+rmb7AmsKtUZoUnpWEJ
nyTob7UTvwxllMx6js9vd7Knr5QW/wmj6llZFj7dcTuRWfHKT5osO8BrXT5vSAFwpgFvFFrbG6oU
ha/IrE19iFaEGsjZ/l0+/BJisobHk2Rz18UrGEpMQgqYwJzSt3YNj/6GlL+EU0SQ6J1b0yMzqMhk
Ki+HUEblC4c1kHpXznOzDWPw6lWpowAB+rVw7M+eTjuuhNxcLA1TOHpYG7/M+vGl6ZIg81flaCbs
Ok/GE/yRx6m9Zkrx05XQIFZg5H0RQ91iZBlPiSYC2+0fEtx76VMOx4Jhq637OcYwTXa3EfBtHLfv
Ov5Pwe/h/BBS8t4o+i5GTVgwOmxOPzp5x0zyikXGoPIb+qjVCUOSGMHqIhq7frHrnY78bKzwkrkl
FwY1RlFd7U0szgkFHTvjlp/2D7Zc6AMq1br5q+vfljvfpZRFr5pkFF1ltwgj64AD+w89zzBrInoK
ErX30GRM/5bQLqkVPOKs/IN3odSUYWE3LnSA2EFXuoOUmGz5rK9WoVVZAeJHHt0nRS/94GojO6Zz
Dxs6iybKoIlxfFypwduhegIf+KOoquAj69CTtoj2pnU3C/FFlOTOUCb6j0DveBtOLevYtpw6km/W
lqYdOgObl3d6+et1O1WiEMnbyTsHQ8oBUipKSjr64vSNkQkKuqmPkOSlmIaUO0vFT9PA5DtqPlbX
1359inrLLDyW85QT4UCEILtSGZ4U/TSHL43EsT2d+M8yrqdd4uuNiRBd8BUWvrsJTghGmu8DYaxD
ODrMWpL9sHCdBBLX9Jj8pEAdqvJFMcwKVr1ltd1ZtRieFuZItvmrzpGeQkKtP05CKwbLgIU3xSkv
Xv3jK3+b8FbNj7W2W5hNGMl7K3mSQ/0az/9fwXqksKcuAqxjK96xvZGCrViCsbT9YW6SAay3/lOT
eStfuejkqv1jSXCz3il2jLwNFSh6FkYe6THBn3DIE/aJuSjOeXv5MzYk030lZ902KTrgVI7kr0cT
vA4N5OMBGW70gZ6eK7wHlRr3YKscXEWGY1zAcJZmB5uGKXFA2zKkR9F+VXWkcfElK7uBilg15GxR
rnIODoGgJSeqJaJ6unL0tK/Z/qsjfDipbzkb/x9ABonXMB7hJPjTidUiRxUB+Zkmml1Wt9nu2/xG
7X5MGLVGYGB/ix8DgAUr4qXYGoPJmTUIaRsri0iq6L/UPSD2zGBZOH/4fD53zcdWusr1fsw3wwdX
sihec1oRJIpQ4LoAlYvl44KIjd1+otTQeZdg75fO+0NYbwZh9EOXJjan7XYxD8LHkCRgGk2/jaC6
vmEwdYK8a6dpo9iwVf8naw7sgmTIKn46ERwy/aoRWKZop/L0tyRsCg2r16iJkqm8rPXLg7CWlos2
Va/yVDYjHalgA28kgzEThtqNG+XooeO0waCA34KVvy3b7R6e9iV21eoNFj+E+9Uc4HpoqhSu/Fn2
QzTZF2EeEGsZJ+KQooY6lq6GLzH15pjkPVROvjzGEZ0jLXO1rooBlwN7dQSLgVh+alR5rqguYeSp
a/1XQH0vRCrfF3blcbTwwx9X08y3PAQEC0//tvtf45ipH028e37uIsOHH6fr3qrUULtOVDGlYx5f
55rVcUN9febPy++iw7+819fxElyZ0p1JR0R2EsEB/QOd3ed67v4JPSld6CkqZnOcPQQpRA2t1qI3
f79QKcx7GVXx4UnR7HKt8lCsAGjlpGHMfNeFdYTl+lyT1vEPxZ+AoEaMkLN0DY97zyyeYBOPjRkX
MDMLADU3gGY0BNOWblPfQe3/BIrwIS4atNVFax+5UZXQ3L7nMDutFDQl6DUsPJ+fEM8FItdFLqC9
+dmqak+Z/P7tBgTLFRow04UdtoBfZc++S11K78w+/B6m0mzEhUkGideHLs/0JgW46Z5ezAee140U
PbhecKNEMqSM8T5h+jmXT70x2vjJLrDWUWCDVV3a6jcm4YbPM7HG6ooxOiD/FUgULze4JbuB3JgP
KfDugW7Gqlr4Gh+JfjBpCCWL9Ll9Pmw3F4016M2JuIbY/AQI6WsomAyWRdQ/Nr/sXYHpAsL1TFxP
UQoqgFmtayZKPC2O8Tk1KWd729CYi8dHKpZ0jfcAa5biiY79w88anEG4mmH/iTtgiU1gw+TC9QGS
xKf30pmLfhPAOMQtu+ZfN6dmcobEA43zbXpOk2gh26hYcSyU7owdca9Pn9UQ64lktyA0lYRCUN2q
80lMlVP5RxM4KFgpod+Rcl9fqrZP60I9F7vWotvEb4nZwbLiGObFQ8DpIcLupGNg9KTynZGglN8F
5mUocXUCsfbKrchJ1/653kVJH40tK62nX/ICi4HqD0vrZLWlKGAFTxmhNdxI5kMD8iuC5WmED/b0
fxRQQTfiOaNwZxkE48m3AbngTnYudtwr51ql03OoLcRBH9oR7nCtm76aU5geltL0DVrgfidhP4kP
nY3EFc542nVPbEpRHbfwbDkGAbMpZtNk/OJv4j/dmwBDD8WBmkYzv4JwmKHTh6kQg8QXSBejTjTu
FO1vN+b+pTggOC2UVkUKeBSs5atppAtc9r2xbXT+zaP5UhI4olRJ1iPiHkzV4fWrMqQ3uzG3LL9D
QbLEZjPyu7ywKqL/bX7IDXlb8Sh4/tOJGZL0r4LileGBktVPRUvQ+VGQlsMB4Hy2ywGPL6jiOvJu
gfygnG5mEnyHfSV4qACl7fnUJqZFd1TN0DAST0mVDvgWa6iu2Y7w18tQLt5z+RLUSDY0qb0mEG1a
I+O+GCFUtorC/uB+4VNjpT3rkqZjx5aE6n6X4hjRziJiMX/37v/RlfpHJphvwv9WhLp7Sl9pfq0l
PXY5ApO6SOSu9oUn9Gmxpo5YcTW1HdvqK1iDiVI8s8xVkQAoBYhDJexXnE2Eb9hGabevY/+kazqx
p9Fw7sOvdHcxo+NZloy8FSe3Z0Yc676bcQ6GwfI6WofI5jyGoLM4sNxrCUJopV9IM1ebC3qCf/4n
wOALx7Qsrc3e64FcqxudYUNUlf8QjTx+F7bcK5muL3KgfIfkRo+dkBn+K1NkPVMZNydN2hPC18xm
zUT9KOcMC1D6OeIAr/4GFUxTraLhZMjwgSUVtSv9vRTOKBYlG8GRZwOzEfF+9uPlDa86jkLuHkV8
qMMCtxoq7vSjZGeJspS4IqavQe0nfZ1sEgA3hdh5a2qhWqNUmCvWqy6dK9ZJb1q8btStrXUzSQHx
BBGpnrwkmTlNkHnqFdnVJ272W5iHp5A6TEPbUMEEbxdT7HY8bKVQHgGEJ91zJ7q2xDeD2fa87tD3
8Pb55c7qwuESlb12B7f7qy3lZpNHKNh++md8NbVEdrqHgC/oo7fk/9hFKOmBPs1bML1+pOMRiHAJ
2/CFB4QC+8TzWEBE3z3WrH094C/B4eC2hJeZ/R76Q5EkzkZh2DTnnctk202jDK2rOHHHG7hC63uJ
+i4DbL5yGjcQUR6crYEC81aAXSlrEI84u/TPJ0ovUvbgGqPLef5hXQrQSeksF937P8PQWIjq3zr0
MGp/jRRZlqceKLodpeAH0gtqzVUa6ZosiYWLL+p8KjG9Q5SUNYkrkwDT+iV29TMHu3Qs7KRPKn2S
/aKmjax4pK0w0DMMPwXUT67+Bb3IzBsMcjO2g2tqZHvOJKJrdilrfL3/qLhAaYD0KLGCqu1QXEBS
5zHrgURv1XL5jK3VJagG7tJ8+edWnAmISD5iwmM61siIvVPwdLacidKRtgWy1HQGGIl0O6VaCqFW
fPGW+t7ze9hmmOacdD+rmWq6b8nRk4WHCCxDd7Tefe0e3IZB9XIWDIIM7pvy8aLPeUnt7I5GQq2U
fX70qLrtHR6UiQeTqjCNtaqH9v0CfLBENHnJJFh5vCtbFF1JHt4PWQz7tDkTZ0z5t5zxSiPVTOMi
Pg8DwsKyu8NrNfmMek9mJyc177uCCcHlST7vg+dYcrUQRkOj17cUAzQDcA6EbrT5gxWMBkQxZ9Wf
ufdi9IqlLroGamiMeIVhJyhaLLETDr5zsANaGp3YuZnODesiWqMTxDFjTPyrZGs/RX9H0M/DuzfT
ZMOcjHOp8q2EsYMGSiKRogcxYsvRjkAdz9ezO+iR+OJhfT8vSQLiIkY3Mo9rOvZWhTLfgAz9HY7f
J18RrYqck39i7McHq2MrHs7Nbma4zbagYY64DfeyNcMZ12RNBVuO/mgtQD2aZDA78fEOMBRyCH1l
g+OH0aAdUnuC4N4QY3lI5lu+6CzHBT1vyDkLGGv0xAGA6sVci8cw0md9qFwNfIqSLKS6oGCofhmn
Du3+AGFRJADwj3QMojWf14C2XCeLG8VPIgFEZLs269saNUPMOwYZC2XxuOumXU5a2y0xhEorbOOf
rHyHU4zPRqt0H7u9ezRS26TieiubvhRswfZpcRxUZyfwQvg1WvOlFF8bKmUJ1iU5zdv+lpNr7QYe
KCLLDZB0GgjVIXgQCq5Y1O1TNklGrowoua8pxMatEZV8h7yFQuBqT3xGOBSD+i2u6HPig1rw9QHQ
aOW1YUtZ8F290ECg3P/MywCBwFo7cnYAPNSYuUQR80H8p3b17GC6cjiL4kP4EFziy0i+OG8GnA2Z
+tGXqDR726ecxb1hijp2nlN5WbXBA4Br5gLIQNk5JoUANYyI0TFKajUN8anL0YJDkXQPyeP7JO7Z
c+JhQrh/ookbm3QPXmIK896VS31NnUvmPl6KYtYMy9nA4Nd6nnerXHgkpizHTZgkCZ5ToOuzzb5O
jZsYLaU9mtVvKKaeJZ7YO6tsiGsGfDGcfj5Hkfzw3lbZ5L0+A/sf1APCLpmwtjL4qhlNfR1kwK4h
Zx4lRQ0TqDWr7QMyLeNTXWdmugScgks0bjhX8rp4FWYBjXmhJFaf08kQHkW1OFQve0D8wukxlEWu
kW5N3V8lN9DMReJDhR/pgYpsj8HrcPRD6EVK0OeLjqv3kVRHuEr4QDCcFVtzTgqVfnbpeiTAVNla
5SxFSlQSewY1krLnnInkP6BcoSiK4+O6toFPxGIQOkqeagHr2QCc133ATKpHYGh8Cj/7ZgmkPQ1q
VMYQCFTzyZRyhA50mD/wRLm8vsTBeuLlmg2BIsFlb5mCCY1K46nu4/nIWDoUxnPOrSCna0H3Oyvf
+9W/D0up/RdjfcCa3iceO6N1ZWua5uWuIbmwtxL8p81FaUqRJ7MrhmNwHnhCOYhT9YS3vyhFRWdo
Ht0Hq0b2flppUyAv2wpVgyO7Pn2n6tOdUjw7i7NXXVfgE7PnhumF3d8jbT0any/wfSsWvGWutysy
zRNa3v2PthUiey8Gs73n+Oww7VWqe2cl5PFnHXb9TpI86jDJlBiBJwzU0clHYxn2tOpkwOoiDFuV
WvVhYTGDK79CKEXVxgpC+Uxhe+P0cwcHr0z+/qrtGcGE1+qhhoC2QO/tkLpic2yZj33ExzZeaeLm
2pem0D22P4Nzj4Mb+9oGqQxa0jifMN7IMa+qdLV5PuSfpV7QzWfLOClGon22vtWXt+Ym2SKQBtd5
GlfLEZHwRhVeP2RDCG89M36MCinjBJvwb7E9xXNiBmQdJ+nZWI5R3tIEOV5+mjGcOIPDw4W5qIjl
Ee76pE979I4j5vJadDPT1N7tCOA4FnDoNUFUpi8MFq5j+O9UlHZENo2XRWh4SIAqoauMlJtFe6dB
Z8l1m/aUpjr+//yxGM4dTUCYOcwPGG4U+r+lziVQzKXp+cmfJXR1nsRrR5Lf5t8tSNgQfb/aF+86
hlbXzih2PFujf4g9DBvpS0pUufACCq6q/L7iUZyKBJ1UYTMJ5XGwHiJei+22JCa34MdcfbC1DSa1
fhABDCiqKNia2fnCsfoB1ch4etH9SVes/QhaZ4HzrDmE44kvDz6ChfySLUnF5jzUZSoxw25k+L5I
p70eIRYP14S0S/CtJJqPSEURen3WEvqyJqLeXw/gFYhvqou+U1bDZjpDG2gj5MY9W2OS4MYfIjra
WuSCFPYo8+BwliTtmPgxst2YearOn75K3h17dNItsDKa4fmdvRQB4jpladikxQ3+nt1QKYG9U6LM
HSs6JO8yeFmCSKtEzyZaiCebFd+PCF0pfo9WURqHlHT6pf+A/uWjsDuDPyxilRB3jm6OCy+kG1ef
N1UxZWj4f9PJwSvd5wq3QTBHSfbVM5HUqdsNITlBfZkcHejcMgPRnehzgAKnSlrGzKrcXNn2Q0vr
kSCs2ALY7liprjTxXxYa92y/CRVcMpvEXnpaotNHhSDvIqbZeYldDXObmzgLNXTiULVcVp1avei9
ftHy5idj0hSVHayJbSCRTMvdQmsgBW11Idl6OrxjqYFCcn0WGFup04yqtgMzVPXhdHxZkNPYGWSR
S359zPbiQ1KX1zwW3Oh6F+OI6B1eIGWBDGYNqyxVeqY33AVvdAvHicCpfBXVET7F9aDBsQUSMLYH
ijaPTdnouo5sH+VmrAC5HPyZ3NLU7ePLQfbM5D5IKnh36N/gtCrQ1dybAftTgqicCZuEfPh9pr+Z
YxnP4DZ5d9KGbVTNrPw7oQ1Wi6yFmqhT9Z819DmdNrMShbag77rSdB2PgmW42d9FB+yb763UBkPc
p+ssRT74gj3RQjwJ/BDOZVlXI7+WNGp3CkV7jpInpniyYhhUTDnS2whIGyZ72xUGowuNs1VAXyEi
PGdm97Ry/BSaMrRCs6ClUexRJgN+Hu0PYdfCntK1GydwnX/WuSdLRDBWSLbJSac/hYj1xCWOb/tX
4JLFlGNFE5fhckWhanvSX/DZ2A0OAciLfh3CYnSOWvHffXtkGzgSrXQ4HjfBECfjBNLQIX9r3uPq
OU/f8poo+Y8ujmsKqHWQc1TUZzFJBDMINjjBdmm0fnfQqtqQBUS2ykqrMmwdK/0pqksIj9BNWnE/
V4g1JiK5mQapuUm765E7za4gIVegGKne99xrdF5a6srNr7V7ufgeTwpU8Ud/NhHB765EpympST8P
Aa+EDqsZ+eFPMGhEteXJS8U85pTjQX1/MEH2Fm9XY1EKwlmr47BBRc+yT7NUEOiEL+OXeAQyOCTA
f8071WVvfX/nJfpXcyxnfIdx9ehnj1JW6nVK1LLBgE7WP883AEoRMC/NpwZwos1ooXA18nJqOyNO
IvHKoCAD5K3PXxCnZdZXL4mYpzb7yrJoqczO+NRtDB8m3YgW5wsi3OGzWYnUEb5TuPQdPFpeRCZW
1msfYAM2zIG95WOahi0Ukq1El8AhXbNXqKv/9YFibIuIAC+AAAtvZ/wNoq9PW++6qQS+CCt/S3Eq
MrH+fKwQlZ74ee3KnzD541a3bWWGM3igX26ziq07gx3u0TWI+nEEEXbUMu1ZINr+wybrstGxizlw
FA05FN76MWtBW/MwdaCCsFEKBeu8doWs/eTfMX/w4deY3De4CmRGozmX1jixvucTT51PuWfbjMZX
nK12PzfXpIU/mw3r4+lx7Sm/UWbI6mMxOCz6zgMcy2bM9GDl6CJW6fzXkVQZpKB8y055MWtfmdd5
4hcltmR9g2o74DrElKGIObuDXZ8Dwgr7PjYnIAstWVQbI4E8u3ZK1/LQm4vD8i2HK7MtM8GrDjg4
oBsL+3c3zWPyW5l/NipvQE0w6Dx5H+XVjQe5wJB7EkzT/3kSreLKLj76utHnTGJsTiXzVvE5a+Eo
pCsI1wVh/EwXQEBpScyPup5YEnhLcra+ptKHj1/CgXb5ooUCo9ZB1vljF+F2L5APDHHKdq3A8ArK
el1jtQSOh+GN+EEJL67F8KVjjJwUZkyAA7QzJz/VhLcG/rZmLzaaDvfWha2t4HFDXj+fEFZkWwUU
KQTMXVvpdv6BwZmT6Auy1GsMaz1ny5dSOK3EE+RimnqXn8mkHlI4gQkcVMSXMx3fdgz5IUnYoV0s
iz1XuWrRJK0Pty3CdaP8a3owo6fsTIZYZCIszMGz8BVOnN77bn8tBqxCfii8xH+qsqF0CxkXEQOm
cKTP2HFsJWQpKepZbenWwBhd9w6WBVwubgy4z61idhWhvC0qhlyn7XKCOWd6LzAYBqz6WxWj4hwL
PsxUSGYW51yV1wVebtjPGtDQSZYntTkoXwSfBve8WiKtD4utaM+hloB5afQjYF1ufbPXt5me0gj0
H7DDwbLK5BYlO7IlqVD514zHpc3C/raBiAG3ShnwvgfCcA1xxHlzzxbmPS+70fd8xT+fW3yaP2T/
M0HLKRVu0e6SkO1+TUTYG/MAKAHO9jcLaHOcYmM7CEMwE04nYw1gqMf6F+RENiO+eT5ZWnQaRZVt
J0il55TulgqcObo++jgvStfeIxEBTK4M3rG61g/YZOZ7Uuu7ANQgw94q5nqR2fpjufRUQNqTRtdO
I4BFjVtvbAfX+CtrVJdBvAfpRtwcF+YmAoyZY07DvBr1I75tSMjcKCJevyoLJO+aHGXSJQ1LzZbD
1OGepjL+3yKhciaxwNCzWVkN3MJAV9OfKc5eTaGsvZRBxwATemMYqtWC7DxySEnbFenRCoDtaTyQ
Ll5OzIQfB8XSSuOXjkCg0ZpECbvF2Ugm8QqfVTUZzBncGKuYMP0dhZeX0Q64Vadr62iZLUb+JdNe
yjv8qPN6OoG07r+fzlA7Q5/c/f666klzW7MWQ8u7FHE6eIvSZtrwOn4UONEJubLRcjNfKAU7TXr1
hQP/rt0yGCZeuNquFeXoliewNJogIeWoU/+8HE1JaKPryup0A3sjuYGO2LdQ3HjBG0yg1DWNYCJa
FX30HZFFtYmGL3BNxB1TGBDQcOfFeJN3U7R2gKmo68XKFSkda7EHiqiNgQO24aG6zsjQ1OUNm5wV
W/m5WnAQ6qRZbdyiRvbOacfoQtlSJzMyI+Ag7a6M3JCJj/zVUIyr2QD9hzbrBMGS+ADjRdj3KL4K
bwCZjMIyfEG97M+hsOPjYOJimTZr3N7zaD4buq7ILxaDrLTEHqktFeHK+R6vM8pikMojv2W/FuMx
6NjGjrYrNj8A6jQFA0tTxWVReyhdb2mOykOjksi5rhZ1ozwlvXZ80fHITJOLkR5NJ76fjkfwB6KE
RXdbtppbbCcesoIn4WtGhWDrnvENae1ifc6Y6XIXgHmID9mwsQRvR+1+zgjO7KFGgF0UfnZTmpXe
aZKH5elTph8RO+nMhkMit181nSYqMRk73A+/O+F6q0YU1SdriUr9BFSkCM0tHrDVUZwPjD7ImkSc
9UhnvIgKGg/Qx6afGvhuiCVd7R+o8FDyBJGtX9W39vagmdjWcnXEIorCC3ON4kSQChkE/wafQMAS
Bkpzf3Mep3ItcjZ4hVt9MZIyrBl6aVY9YqOMtNADiaDR/EghU33GHybUbZFT2dkzHcz8yO+9ZLh6
abihUwL5bRBiVFrmkZm/Wxfqa+Kd3WL2kAX4lJa+M5CP0W1YhJJY0G/mTaqkl43R5785uRqcgKNK
bSpUKi8T2N3FAamSK4aBK5pYl/nG8LvapmCmPJmfxhDoN3jwjyqSc/gDc5tZXmOf1M91UFIHB864
NpfxbQ95UmUfBYF0Awyd6s/TNP8L83zjJH+9hjZ2E8YCzwNvdZjlvsc4xULDd0ZSBvHikX/eV5KQ
1OpfpyjFf1FL+9k7wmGkHmz3Yzyx/QBmBMPJlLYQCXTxI1+7cjptHlmk7OAn+5yNP1udSzWiGdrL
rhyU0XTuEkwCIrJ1JHeoEcPfEYYv5vzVEpgGhC8DUlUxC0j7dw6rb0c+M6fVNUkNpsjNGKwwuM0x
rLSjNlLOrVoZ5h5EufJT7zEZraef/9Dxr++s58FHefRphtK84eSZS60Li56HcABHh+ngEGwh+DrA
7ymBpFxShrF/2PAAeKZpDet4VHxbpSAC23RGkHwslKCiUAqZdWQAhP4QQo+mEEhojISOyvc2I2bs
o0Do8MsDY6FrxHkkbgtD3tUUprDfdgv0nqlFPx1Oe5TRdjgI9K800ihMFRbXh7BcsqVFKoxscrlW
mnp+MrsT59tHR9rZjx1cjxFvUYopPbPTsoJiFM2KtfVfX+N/jbfyVcgqy/Z16+wKHLFT+75QSUGv
ro5wYJJGevohPtD86S/6cN/rUYnAkl+3iR8idLIQKHhoIWydcWN5SOZvuvEbfz0/1viy4gXRx0HF
cX8SxGxfAErXpV1LyuWZQgwzL+GXCg9Pa2Pa6BrbkDir3BLJ2XD2vfshFvc2gJaiHA9B2ck1F/Zx
pINgucK7eorhjlSMEU1PImcD9tAF80+fbCBOUTF86j2yShw3NLVYTASVfw5Hs24zAabze2pSdKlA
S/cGmAYD8DZv8tSyH+hwSU0aAiE3D2a+3x/GbDxcB5XnpBt/3aZ9yLiFrbyqvEj1kSp2JKvUmkYQ
YwuLwg7VPQg7g0jSpxdIbnE72Cet0L28U5P+rxVJCxXHw0mlhONJrIfBOw4f8YmI/rLX8+CJlJnV
IfVr/XN77XV2R6lbx8VkkAFukIcL26QEXUQijAhoaCL24PRNQIww3iLepSy4TiLDp/wmtRsL2hNT
e7Ax3/F0lWSbzw4U+lovmWcoMF5WVmXDvkjYLw3LFlVyktTcmRkfU330TKXiEQYKEEq83T23krjy
3ygvw4mO5x0g+vcJWOf8p9biMcd4rVaXOggGv/aYRVcWNylOGcBu9k7ZJiWHbYojDqbvGaPCHVIj
tz9/UPpl/Yu1XBbl2EFLsNeG3N56bhVCbaYCeP0B9t8EJyCB2UimYAdmYXEOC0HhKKdhGxDWfb8B
/7N8Byvlkx2P9NWZ8RiMBnC/xY6Z9qoeZ2ICmhnXSLYjKA8BwwC15l864fK7j4rnB0opSk50poFz
GrRGtJtDoOC8/j19utS9EnunnOPe18OsBPeslkBXJJamB4pvvVPwO8P2G+YGCpc5xGcIFOYOqtMP
P5Yi/99gBdKk1CVGxP65zGqKCuZNoos/Tqyc8VqkLC30HFDs55m7zmYSROSmAFqDk69q6mLq820F
/m0UWL2975HvxFKojGxGb1REuirROKaNZfJO4gMVU1N8lIC+fR9FRp8i0pcl95spjd8essRXPOSJ
4xmTGXeew5OC3C/xROWD38vetjcqtyEoTNS8wRrgg7CQv1beaZ1SAwJasEt80Er0sphUxaTi/rUb
7OWAI9lOZLxQpCHZXAd/FeQ/Et4r2oAYbqazEuIm0QDLt0QvckROGwn38UiECyVmdr/LQMQp3ZdK
Op/MTwpkZOr9YdxqRisLv0AZCUZNNuWJEi0ajTWI2muINYJrY03AhefhvZSfhUIxoijAgryPdYUi
/sT0l77/bKXL1JtWrwAJkh3s0VS/Ri0ZRQYD2MBgektNU+l1+1/VTU+Z9AD2g/oAEalh3kElcUQb
5VbYOicKx6rohet3dmeFBmsz3QX53ANm6FqKg/B3S9z35apt3kbov59fY1y/s3qhjcAq+XuLOReX
9ZHg8cUXmedKjkejNTUrV4OYSju8Yh/hMXzf88xauco92/hL1nODXmwyPi4wDQLO14RCMmjjDs8z
GFTLIsoWz34wE0epEVbDNY2hurIWj1ThA+jF2uo5njhy1fUIAnw0TFC19n/QTjgQZMCcU7oo/VYB
wJWn1FU1tSOQXtzE5ULj4YELn+O5LInBH6L0QGHqP8gYRA3tZ9Jmotz6bES1i0XTroezgSXENVDS
9jVMgkzpj+KTBnxtE6q1PnHyopkQipyHrNgzU/EYya7Mhyhh0MZG9phRpAg8iHSYPSu38egXwaOF
os9IiC0/pVPbPCfwISkpgDCFNXuF3/Lm8hG/2IJOq5+3lJmK54yRwLCASyH3Q+cP6xz17aNky3Hd
Z0otPJxfySdCr2eVZ/d+e12J0EzXbOknhqCjXi38xmB1UpCzztB/AJ8x+2EXTe1jeskl90BmCInQ
obfPv8f2qivseuu0CaL3pl+3tKYFOur/pw2b6EidblMf+wf80whjWKAmArxQPLG/zmWOsmg6jIRl
TKROuy4tKX5aZ9JoctCKX7UJL7qe8oKUw3IVHsE8o60Br9NjNLIJytbF7pGn9Cif6x/33CpZoa1c
1WccnzvyrTDK21c6x259JV2rTjrd3Bln+qFQx0VEtiY3ORZUugmPRmU1OBPQcQE2dKdUJmWEuKmi
mLuLiqrEu7pwGaq6B2fDJ7xsCO1Idx6emt0jYQMYpHxmMEXRvIQZyI5kg2a3nuz4KaKao+ndt+TY
JkH+vRUO9n7gXxTPtmHSu308pHvH528J0MEsvCCU3bTeXmUAEH7uVsOMgUeeqAq7SPWVfsAqnZh4
JgtriXU9M3cxHeHTOeNjTdH81eX5mHMuBuTzVdVjbq7EJOQazWMRRAzvTm6Ib/VF7ZQPp4L+FZeU
fMZYPfF9llUXU50lqtJm+W1hoYrnRkiYQWTWhwTcOve33WtuT5SOYNySwNpcG9WvwGIlJJu3D7/G
kAvWkNVffFhkvIlymz1cEKSy1bbOURoybsMxH9V8FWkz2J+ct2pIEJtML/Z5tH9U/KJ223PnMV+g
4At5RqGBQO1ikHC/KIdw25PNHOXpTXPbQlfLGpHqT1LRAp/hQts6I5dBuwZ6o5+tdKWU0tGinwhT
BbGl1tfxL6XbgMxKVn68tdp1rTOr14Nm+qEYkPL1pZflDZN1iqVbk4eNT6wGj0U+DlHuBaKK5vLs
A4BjX3JaXsa2NR2YRcRuod5RAYlj6RtxkGRTqki99deY7QanbHTZ1jPIg7cNE7kTz02QsizI8nLk
KSBusMH6UGk946b+mGZcWyl0cAd3Yeju/qaheBe0+/vfFMcGChUx4WE5EHQ+EPyjxyaL0s0zgywj
GXGeZX6JeRU9pTnlnnvCq0O8flkDNk3+tn3fq1HMqg9hhugWSVxAlaVOkdCUvTpo5eQ+EfIBLXDn
7pWpKkh02vCrkZcMs0Es4yBZtNaErP7E6Vn0m2HL3SYhY1Pj2WGEI1O2mh9Q3sqz3mY+Ldv5l9J2
aYZko8YA3sVFG4RR+yceBGG2o7C0g62PJrogum6S91vJ42KPwBN/nMKDfbfVkNvaV//6KBaNV+L6
mUDgMbCtF1ORMp3VRwPB5WJBlZR8+petTVjkEu1woor4b6735q3N1aogNLDYtEs9DQvwQcQ1S8oN
JkT0c4qq5BVzAI3P43sLw6prccNHm8rSIIPzf0c51/8AAz3BlI2E3OIDB3vFgQbZkd99hAl/oWmx
mUHxKPzjUpp/KiNJqj4mVmlZOl41R1IrBlainHyz+7VnwmMFBuTeLH/RHHYXEtfZ79r8+C2x34xR
kfeKTbyj6ww2EVL3AguIfwKA1KG0HtI2fjfLdBGkmcEVdBzEaJGsJWczrB74g1cm9YwUOw/gn+kU
Y0EVO99+SaCFmHhdeXTeEwo2iUAMU2EWR+WmL2BFYfLsh/qqUGO9OKhv2/DjmcxceWC4dApuZ7Cc
WoRSZi79rV/bhoUeHLk7dSY+xUfxjciMatuVn1ArDYMym69AAflY7YMnWD4lP6sb7LOEIbwgdphy
gxXoWedwA5lQCljkLJIOSMB/I3h+stDHLg0L8lweaXHdShmlwn/1rh9wijhMUOMtjpEez8UNLJAU
fBfYaaSBYhPJllbTOxeF3mccCG/UGuWod1Ifbq9ELWSjZqs3lq5luRv9VX/UP4meuEF1qg72D07h
gGkOR8IM1Hv3jRVfLOUKKNRbzo1f7Fhr+J0mrfHj1vAPPwhwweAvzBm8iZyJVH7M1uADTP8bF8k3
JJG5CuF+HPNg4LTmYYVZgOh/QhmKiqbKazWLnU3IFLqVG8MTsvNyqaw0fDJrHi3Uv9RX4TzDtI2N
lA+nft5kTvX/LvfXsgT8GymTajQt6YiZDtJORlYIMXPj9jMn2Xd9Jw9m75IhYe4N6hCCPMHp0BNC
/yC/m4xrI3S/QbQLuJ9+8gK6B/JmGIZAFEIVLBo4m7Sew0ChRDdO6dEn4vZ/wSex/XUbDDD5yeDe
tmKsTHAvO9bKmboU2NRK/0LAHe7sHYsBXZf2dyiMV+vs94cgvSi2dx7HQJqCPRA2whqCZKJkaClH
PmkZE29aVlUrcNZ/wVtrzNYCLRV+nhOfy2iBwfRWq2jViunen5U/IYkLXJ/c+CirN+azrRBIgMUi
Nq7OXDwpMe2EFWlMCr8iGOgBeA/r44Fp6IaZpcWpxFZRLRIZbZObMBDH/hQpUiDcy/Pf8T71sChm
s1V6FRNJLcCpi9xvuLjSs/LCQkCzpUmecT9TDnig7hnquiYnZJODjq7BQUBZVsLCwfoe+neNxkDk
afBvTKpmoscUGrzSU6Zhtd1FmmDIE5n33LvvVAG2sa9Gb4ifzLzzv7k9I8f5i2qk7jBIUDUQBMwx
ozfZyRJf3SR4bH4gSs0XhTFlD9EAM8ZzeeH2+usexVd9qPyTOPY8FURy10kSN79Uo5dyiSA1BuOY
YPB4QtfV5gfg2BuMQ+N94sF7VcifAB5CB/HzFapiV34dY6ACkbttHxNPOpu7gG2EarAgp1HVko4J
5Xqm0cBoNX+DNL82bmFeZIIpGf32CTlpYoewNUyKOzNvkOm115Bpg60cljKCkvbH3GrEo76LZ2cg
VY/rPWn9hUvdcYNbD5i2RHzHS8QqGWsS2DXL0HJefrgOldgXpKInt77P2GQgNzXykLSiQ72oiLDy
q3zkMZ3TiePP0UXWRD2C+hh04ddvVLcjmFr2AXmYYEhpJlBqCtlb3tB5QBTeocCGymxhyVDZMMMy
FW3AjkJ6kocw6h6LcvcaCOXkSHZryRqUSS7emNHY8exV1MXqVfBbhbCRFpK9cCFbBUKy8xPERDV3
vPtXV9xQ9aJ5Ro1JouABIE9nSL6s03/L8CODSRJV1X+Fsbd0fAVINJU1XpLRSupNelIKaQhlf0+n
BAs0aeoGzgpYLOTRB7DdM8Vj7zC5DiOGlrk7MtoaYpGJ7bhlMg6jKWVCyYkzfCVZlJlvyrpxhNnL
FLNCQ+NTAtOTx+tP9psIki6CNzRTM263pcsSW1H24ad+fHQtALXe0rjfk9PXAxNahI4knI0XIS50
MzT7MF3L+xqZvNUQKnBit5ntP9PJjGOzIxsaIZiy9lokqQf2M7HYjyuawBHEKft/B2Yz+MafRAZj
ESzKDMlsElasLoDo7LU7Nz/HyugOc7W5R+T1ErG/gqMaA9h6k7ZKHVHrHk+otV4H4aySHiyYg1VI
8n9N799uW5RgWZ7V6BdiJ2IdPep7HJOGvtp4F7uQJHoKCNBfhjgew6bMKpZajq/rnHs28yhmXNLY
Yc5mfoZeMwqM9yqrby6bH2G9B/jN8mN7AJcFUC5259tQlH/9TXDv1h/8RiMSkQauzZ69XKuglo+x
q1opttF0PFyMOPv+7RNOIlfz9Hk04MlzO864FrXUAQJ+eMtTf4iQ93euPW73jPSUXwsgrKKtSyIP
R9psf6ljEqgHhOwni0nikAv20AaPGX/736YhUjNB6GqQ8BgUX3W5b6VZ9Mya1I4TDkEkyBd16t/7
TvSSUlGRlE2/EVtOzv/i0x/5xC7iWkF/iKYy/TMrQWL8dy288Jlrhyxb8LX6qMYpOAVlowqBZd1g
yTZ/9XEpnb/isQ1Nc6UL4zki32OfRbzjzvnX3v/on/7p69g68tTGBy3Rhqz5Q4vWfpbfDfDhoX0X
JZAaUUVOq4j5A1Vbd7YjFiU7IbBktjAX3SjpavakGKMDDuJr2wxcLk9TjPOnKd5nnVH5kE2GKqNe
3bQKS/fJgclKH3nxSGXBv4p3d21Fz7Xc4rWSgXv43f+Ui1g3QDsmRKW5AvxeJ8sIP22WhhmdIUyp
taV6teFhvkivGQphq8Er2Ky+wbo/tJ2s6PHI0/jY93V+lOja2HkC4b6Jd0I2FAI7QQ2XLJSSorUm
V+qPI2+oycjAA7uXquXBs0lYIVogbCuqRB6Oq4bL9i/GE0CTeFlrGHL4OI4lItcOpjNVnxQfEvgS
iuymyclV+3CXzpiUEZ039C1NgCmmIUVrTQIv0uAL3uuQSPXOoXJTOw8lMwSzd2RfQGPA5e75N5qe
Q02pvrXS7k/t6E2f+cxP27o7Jl4dbgVGy+vpej261vun65gZEwhn9PLI3/y6xP69aNHkfEA+GtT1
v8ejxrwUl1wTTlVOIVgBAdCB7xNrg0jFlTjk2RCpBnZrDSeANF0xtT0NqGiGDNPSDIwBkNtCTkJ2
0Ant/w7/Hu0jZSoo5iMnbzsPY9E2iHetKPOfFhBt74ZN5p/l0gZ2mezwpB7RxvpvEYHpXGQvKWcq
BR+wpMZxFq+FnqgRDGaJYwcw56j1vWIx2jb8KD64V8aq2zSeIk/dan/Okiv1ZgzgNWr1PBmnspON
xeQE3wQueelZlI8kn/C1B+v50qWsX6k20nHer03Bm5UzbPVeXWlNNPc/JVl0RLqmY2zytyct1YXu
96kKABu7JqZFWOX4O0OVEYUpmLBMLcHIRWsW5rJ8BIQWf4XrdZJcN2zlVdfgJMxeTrsZvxrQ+Sd2
Y6lonFD6l8UxSIBKxfFornEjX8MOcemZFvcf9aXtEzkYa5CUlsbOQsj3Js8W9lCgPRPNU3DSHtFT
dCVbjzgX4B4DLNoQjODq/V2yDJoWyIma9DpR3zDhsoacMOI+7fqI3UTTlyAv85DJt0Cr4GFQ1zmh
b3jxJrjKfEdt8bvhK24BXBhs4N4OoQdBAa8Cdn/8dCk0nH44Y5HB1AqApndAzQPqmsRXEo2QQ0uk
dG0EhegKl86FKRBr3oI51Ab4zXu88khoXHw/A/MeerczwFUfHR4dRYZsIl5Jzm3MF7iZ6a0hJ+ee
gER4XF5c5FOlcxgTho4zQtozDIMgqHkVZHpoa8VTKMGguItjuRVxkU5W5jFMc/yNBG2I9IImlGsd
5BDUOz5A/6GGqApXEa38977Rb1IDFOdTnDsBwfXLHn1IPPmvw786bP1atnBiOn6iz38b0m7cbtVM
LqxqQvnApoAry01JH7cQmFDpSGBPC5RqSjbJPadPlysWRsf7ySwsWAPUN+a6kPwX+3MvgyIIXQGG
KN09NKsGk6afAqk5i3CvVsDURh71yVj2caUl3e+lV0NkPTW8kxLEGUdo76TpluO6c+wYUoLW9xFx
RWTOlRsrcetvpP8VQJtMCGDhF+cz5izi35Xetm/fH8ykaoQC4pmcAtUuW8aCHZYtxrl2PYmv0xx7
sgcCQ+A75COLgdaGqUSvkrikKzYzGxV/v1SeXGg19z/UGBj3+a0+rH1HFl4cjxndCNrH24VYU0Uw
7iOyAgEt9VieKdsEVpHDPVIMuQU41ZzwbnLqi+gTDoqTupOMGk7ZM7ZMAALKWwrzst51dyW73uR1
feK7WOYX9ts976NQfnMWWjfwc6cLhHf2h6yFc4a3yXptIy2dmYi+tVVuhJooBMfGqVwkc8Eg7ZLZ
GNcFZszMZ5dQq9Jzl/tibnFx9zRgHQtfDaStsWDZ5dB+/cr9LsuQgm49or/vesq8kDGx/uOk+ar6
9TNVq8E9QcRGd+ISzOR4s8BljS0CakpllSjHa1hv0IYdyknhWeHmfRQz0j71+EpdBvkg9ZAtMArd
fRIiEFruT9fWOTYD/cKIsYnyQHHGKpa2ixZo7e8On9ebj+kMIfJRPuEZLvzWy2GmP0mK9R0Zkhev
3r9PEWzWdZd3fyrHmy/NKEB88H7z6Ok1pChkQHcZMLqxoQ5mOrgc14G+uAoMhrUrM9Fu6EqzcshQ
wAjOrM3TtS1YNH8cobBh7lupW6o3eyCLwHOsm3+9IqlyWASQ2Ak7B1no8CXrbgmFWEyEfsjsxdZP
WV2tIE/M3iIc9NVSImuPw6+WGCbisT7vXlB4piDqBXVg3rRiHUq6prDMKY3gb/mndx4XGHeg7Kli
4tuO59HFl08aa+lPuT6tbfz1koPWigQLAdpO0Jy0MaRgzeywcE4zILEthLoeWlLcWPjmaCZBck65
wi38yJo7wOa57SvJtCcCo/w1F4Rjep0fBud6AEZ8EChVAOR1yM+0/Q5Se6il+dJQPSj2z1Gq9P0J
Z7YZBxc0j8pKOdQaPTDUfyTDiZJarjwxIUwzZnr9LNc74GUOoxaSPUHQnKCW67Y9Sqp4YIysUfuB
yXPi9X/q+lzgjoh4uY6hzojapaD5VYv1Yn/a/CS/EhWGGTa+n4hugeMSDW8xAFmxm7nPeiIKWjIj
cOQswqQZKn32HZtinijhQpeofNDsKiB5lGtdjavuwuOTpZqxZ72JbYhEuU/JvSu3Aay89bhZZSCu
BpaFVVTs1N57p4PvfeAtnahiLvOHMFQvPAthOAkFxFNpuASEF3SO8zZv14b6R02WZmlHWc+OYhq9
mlo81a9itXcD1e4UXOYln4HWxPK68OCGDoxHZYzr1mRfxk/nbaRt0AFnXo5tufziLZE+pmqeUO2G
zyoNyHvRPKoAYg5LCfWJJYkEhZC39CyWL7workvLXMglH2gB6Mg/XrswhCGBmUa1Xki7bdBjyT99
xHEarF9lMI/0u3SUgeylE3V60MUjnhOaAuVj9unX240A5vC6hr7jMIKsBxDzzepJwjdkDzsLeJ79
h0rtVGDhdSe0N+Qq56E2PkT6cN5XW9yQXxmOyhndNOiQXlrSAItCHMWkWHIyjWQ3Zvf0ho7AyWwX
T/5eDMeG8Uq+ybjw+k8M1VBgFMxdLHG8O3PYs3FRGjFooPoQrDXFaLBo/LFWWeFsQ0cENnRAqq+V
jDiq/xjgsLvzN3v1XhLA9TJ6VD05iaLk2zdDBYK2DZCOgjoVUK2YgSYxgJvGXYBqxAu62Skmn5+C
pIkrMAXi82r/Z12grrN564D1KVP4q01huf1JeV8LZCiUIdYXgOXWRNW2URD3ny2czdXSY8KiNATE
aPhiUJak4XHFp3HXU32MRyDmaqwdtqVMJni599qGeHS+SKE9v/6YBcWnHehko5za6LqeNUWgJ3iN
TXiWk000+ajG4jak2vu2HTnFdAMXwKtrlTIBG1twO9vFFewTZscCvTl1R56ZY+o0hDKGsFbjpkHb
0lMOLiR+mtRci5+vg5/IAY/M80RXF2YGM/kMpUytbGUcj4ibZmko/+Pha9vEpvVNhf4Yf1Bx4YS+
mQBQ3xD0PQnVH3HHYE+yX0IazY9LsiMuUzbQ5QfH+rKnQhGua1BJKl1eHfdT2mkxlcCzZFGstYZb
Wtei+HU4G4vuVy3QryCrc0MU+83AEu3tagqiMWTSUb/peAqzLQp5q7Sf7DKqk9fz8klGyx/s600V
4lYTFADUJAy5SU2ZxeU1+KKeqAtcJ10+1jyHl8LHkFIhPS+JEXOLwC8hQqqJU1Bys1c2j51jiOnS
FIJCOyV+VI7tFLjMLIbTLwbVs4Qbg3zfGkV893HKWtUhRBKmEZ4VZSav0t9pL+zPsI9rRJ9j6LXK
zhMmKC2yJ4wniA/WWhtfBwzPc/PblQEiSVu/GpfLWfEpjG48w/TFN0PWwaI5V1OZhntI03QLujZy
s3QaxVWaQI+8ObFrfiQazTY1pNulYoqUWpBkFRl7KC2rZJe5FOtth78PAr/TSvzuiZDgMTxlFp/O
Ur1Fr3mOoC1a0mCYVw2FcPhv/idKcRcOzslHzk+q7imI/IFauDvsFYoBNCTdpWX2dTs2mtQw2pED
JALzuQb3sJTplSgmAyeRAgn7sm3ch7YZmCzWJlim1/zbMH7utWYXKFxBRs0xC+33weLPF1AmpfKl
AU0v3kCtfe/gIAeqctM9aIcvE3M7n96lcClvTqBqiVynOjKT0p/HObz7qoZbDhgVrRTLlvMbol0a
5FPkAQoZMrLWIvgT7q3pAQm56QqrwvPpHS23xVZUYTFlYBjyKRBYNwrrQGXWhs3Z+xv2xlPJwoN3
I/dVyv3ZVf9McGZ402QGNMkQCquUGHr/Gn/cpsNnHnIcA56ukMD78KbxHPGFaJHbHoZMpfOfRzOt
cPlEKDmjnlJwoe8yDtJolQ+KEs7ujqbt8hvWlLCLHTZZeKXNkPpPywcyTVgGvkXXs2GDWvrFOEaQ
Qc02JXZCME/dpNVgwq1uzrweHl5AI1MzujKixk0Kw4x419c32O+8JMnACG1dgxAgldoC880cLvIW
tIyeFP7W3QSOaLc4Wi9ZI9DbdSylOW9d8/UbD6X4vNzyZYpzzEq/1CUn2j5ZVr0TAYJCNcBh4fT8
Xd2kP+MjN3WYB+t5ABT2RZDM6TFKBU1Rejj4VxV+vQe736PsXm1C4eJU+AoyvSl7TWwB60sQaXZu
uLuZOIUsS9wT2qMTlmZ5T6ejVdCapKDScedAgxIuYUGXvCvrUQJRFBX0yHo0u+hRowVOOARmwtm6
Aojhotm6I59GZdVDKcaNlqoOp9cl5oUrzk8iamtFI+j2IRbnYiPDdQa59//cSgAxge5fD7VLMe3q
iTv4D85kakd6puLuoNguhxxQw/R4CSrFpVVAXMFciULnnhi3g+MhQG93/9aIoGn620gbCUU5cAcx
KGJ5I6X4yuWJARvM88IYnUfe0LflbijBvugAyou1Nwbfr6fn3fo8ZDunyBGmyHvcHWi+TKXnRYWH
L6KC1qG5pQ91dvJgYfIWf8hYi/cU47volRAkFmmLAWtB9J0gJFHQEMWk94/qiszKnkwBH3mQCrPo
UbHNoIuq8+ADmzD1zbjWSnDbNzY6w6jR0ZL4T00lRPP8Uw5K9i3W3GIiwnGdwupnOjTa6wnITRMe
JJIZXjXipDtMymxn0SLS5eVTPXHZSXfUgqzboM2BcadpqVru+6eKeURwU5cgrNvksVstmI1SUIhn
CILL8Cg1d/Y5PNYF4Wt9l5a3DlqIp1quBiZ5Kz1yIuEK/WZx6xbdkDIl3P9c5hB8FY886TrLH4ji
WpWX/C5j7COSycLRTvY7i7LvB2T2o5KvaL9qoX9dVtnfeoF/aF6+4uRZIvigvibD5+Wwr/ayhneI
x1QCyWNHki0PPpdTKqYmT820pt/hno2vOpqA1Mok4eP7e2txFuegN4yuzs18/U3cxaLR+PmFPGd4
Z5Rgi4b63qUSLOm0SkKSs2WTbPUjT0qseJvO5tcVEzGFpLBLUIQK0C4LoQBvdTbkq3LlPgaqYdka
DlQbA4NMAo4nnSrrzS5d7r5oYMcyQTf+0ZPNQtiCz98hlEYI2ZPYtepJ17LbhECeHG/d8Jzt7MbF
5/PxVGIe52Mq8yhoEXPWsjz0nqrIIQXIjfvTVU2BtwcwZNNawHtNsYPfXu9IBqNCG393zzmiul0y
G0/HJTaWz3GXBZpUVD+UK5qZ0RgNe37s7xTWsQcNtPZfLurvWh+s59bZBNxd2qIj96XBjb4w16nv
GOWSfsX46lYrIhU65LTzIkS3cu+ClTOz7tFYQKqGfrRBJ6AbpEdFjs67Nsp3U6x0wgs9e1QAEoOr
tHSQKr6W58tigWAmeXSBObYufxGPi7o7pLTexsZIzGtLIxF8TdQ/XwBTWj94fUugw/gYRZDGEWGK
jQfwdmmgVsPwGqr5KvO8bTCkol/3ilYRktrJs36PzQ/DNtnITlTuRYZ4DnL4jp2XlGR3zVEtKfD1
hfwzsQ1dKeE/nPOvzPL89XIOA5MJAtsJqfPOlY6YcMwZXThO7dZlWIzdpIAVj3gSnkboXmMq8N8B
m7vGFkyxjKLWnwWQ4QkBwEIornZUWD4pp+RYqExVMpf2Dl3LbJLeF3lbgUbkloverclvfTKY8nfF
fDOm2VErR4sG2werQLP6e3LD/TIYNP7Ohl33LNRR4roojTRD82Lugqs0UK0xmGOjlqrLfsrh0ZlS
hkCW+P4Jq2bUk8kGw2bxGaqPVr+NOZe3q+oRlrnFymjFGOj8cl7oqaf3Avi0CLHQQAy3g87wfZbU
oZA6cnoOMr2CE4D1opDHnq+oBHKTk9INx1qHk7p4wdBztIjyF5lffwiKaJQMPJWc83OToldxSWZE
L02qho/OJzP4Wv5os1nlKgFNYyGgTH8SYfe7lLbtd/iQs2V7+rcW5vs5Qgamkc+XBTGKtLpyrBsN
7+Und1UT9X7UDX7myjf4EJjPbNv333CQj1CfzC5fS5Af2jN55uJJuxokLIWMBB+9P+nBbuSaiWAd
AOM+bJrkp18lTHgpQXpdwoIeUl6EXal68qkExTbX5WEMfxFEwpYG88Qys8P5BPjsWNcAe/DMi+AO
flcPUZBQHU5EKtaC1YO8By33l8VEdetaQ8ZpCMU4SfY0sgO5NE6QuLGLT1EN8DDJL/NpVG9nxtaO
tFUt2ZK6ZUCyGmmj4Mm7phOw4VwDymoFer9HmNbHtv7mUJfVURCpcCRX9oEz8mDA9fPURPdDBEO0
XHsyP/xGa0rVUaxxu/cMVfMfjBNIHHAIoBOWCZAuaVIGh5xnQg4Qesc/qwNCfwmfxFXsxoQLmVnt
WN4umr4zF+zo7kwlrLYGWzhaJeI/6mYkPXmEdfY1t7+XP4VYtvyzdj+W/hF7SgkwPcKGdapmImHN
6M+nqk7NLED7X+0bas4bDINHRkNA8sSVl8Sh0lt0B9l06krZHMInBy97p+A16P7p/Pav/IDGmFLh
Wt3pve9XiA4n/XdCUYUpJ0Q228gTy/5gMGKO1NNPEXe2cYh0brwgxnljhoDrcFHYf05o48iK35Gm
0I9yZcMA670XpbK+ORxlZafPOqweevFXHmr3CGxYxhst7ipMaI/fNBSDdoa3AFgtDzz1/g1kNMKZ
bDGqN4NtTdqbFotF3Fnk8J6p3fb8K7J4ZOQbNH7armVxmO/oufMhnPxqNdxEVBX5jKaCKGXjxDrY
ZAU/PHUP7/AcCTyr81BRQZlNMd98n+6uEIdRpzv1j3uZDssD8uvoNnNJt8TYeNTv8JjED1oewsBl
bqBUiQ0IyWBf/wSRSBHQDExQlrx9s69YX5yHCzDT1jCFZn3RddV5plKzHCZcb1UtrxnJgFIcvQ9U
c8wXXFvtPZUyRgiAoRvCgzgDxSWcRtJv8ulbUdXWuaK8ZZtk85a2QolvC5Y+zQu53L7pNe6V5w9O
SiCydSDz/ppE9sAwSB4w2PA+eKxHVB9kOnuOIZGFcef+WjLS+DKJkM5V4hOtAILmDsQVzvut9cNA
0Sn29B78HFG6m86n6YSr/R1mI/1oVqBGG9drJmL5RuKCNn629w5hgjNYIBpW7Bu3qz/Nxo+we77t
5LzAsRPgv3Lc3ZNTbrY8qzJlds18yQAv3CXbkA8+EaJQFUNpgSN+vUfGCo17wfbHcrAZpaUGAuMF
qY9KHyqpedsPdlunju97l3MsiUbh3tUikwVDHT8XKfYZBIuJx6FjwqCwZzy032IeEqtQTtF1/3mg
XKbJ39+U7O8C/TWrSPLBmCfn91GhWjFOfeGROHp5C+Fc3Z04Fi+LfdV4J99rk2jHNcu/l0J2GPdA
FR3vb6vfRcmd8E1+S0fQSu7E+auxlwaFJB76THrJOYRL8z+w5kVE5ArHervlpZQRp4TN5QRhRzKT
pyYoiEXlS4o/KyZOECSJWBLs78/XjJLWuNpU6GtWSdwOZx4YzUuRA1lU5VTz1oS3EevpRIT98Q90
4U2pBq3VWvBok3wA/QkK9Nt1Si4zRbD776nZgaQb+pHSEEKPV8ni0f1WjnGYTDZqqZicdp7A8i+E
3wpoku597y2di41dla9OQNVXwLruwdHg+tQLKOa6qKHMDhKhyGVYC6hnUjlKLSvlaMMTEw2LspAp
w9Xz+LMu/Dh0mI4PHJfWnM4XblaaAkKCs9oafI3UCSYNTEAaDEG2QyjLvKFkZyV/9TnEGdnC8bDX
viXVtubuk1QXKG16bS9xr7D8dGxEUiosjqz5IMFB094uT6L9pWO0DQvchHC7r5v5AHITnhug/sL+
+z1q1EUtJJ+wryvA34MWwMts6YYLX9evJZVXxLCst0gaG3oVj6X0PrjPXUuqiMK0zkyme52eOGIG
UvrK3mVlFcc1gBN2vfP8KyrDhjh47Ivi8GTJe77cUxNZ7QMCTKTOjZhof34KDag9ZluTTvQ9tBJ3
XPj6E5JPFr/IdbMU7Sj8r0UEeh1u+FLdbXONu67WKa9OWU8TIeY5r33iwCbSgLkzEMsLQXyh7Exy
VcNBuvMtARlqFpelbEgZdNHWcOPLgnrptcm/Gg7o5OSwyv0tTnb1AAt8gG46LMF2grnSuQH6Rnvm
o/rrGqgp5hGRX5+TxallveZbc+5gck6WJ1+NPSHu5FtYFLyvjnBU5b7cYlhaIoyLSKw+R27R6/+F
rkVEK9Ta5cXu0NoFk3YELqQAZjmrRfYuzOe4KXU1O1IPigHxffLH2jmT0K+5BnULQWmCLRsKurJT
XXgN7dUSlGAw7+bX0CUxyoXix4AyCsjenB7C+3FmVp9AQT+A6MQPJ6TmUHK+lwFOfcrQvQcgncLo
AKoifYOHlQ5PPHcTGRkCtBKMJiO6YNUxizP1+przyclAjIlk0IJ5PpZiYnq2GCSV2g1WCXFEFKPd
2FbYZLbzTsNQZhYQ48ibqcagbojfL+dcNBDK26x5LGBHipaxKnxMEk1TPQZA
`protect end_protected
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd | 16 | 292080 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YNZOfwFmq+EKwX1iXTqpnCzO6NCkg8iVZ15wmEqF2fK31FdwL7p+998IAHTcmvJXXulOlBvS6vH1
+iYCkUubZg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
fSuLWicvAgz15dAyaBM1McguU+c1OlTxM3rwIjZed+XVwT0aj3kC8vBXZpS89nkrz4cH1M3IFZBK
zd+c70XrF2f50b7PhHzi1/zvy7zfnrDsI3RQtNlcdzxESKaNa2OVRlTl1FiVvvM0flfMEoGOVBEg
CInpOdHF1+GNpH3Jzc4=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
c0YpjGsmE6XFKBplkrecWMiGPy4/BXTRGoswHI3n2HH7rRfRrIKKFBskl5r4MXDh+36ObQ/r4PAk
tfwFXdRBQQdjX794wIxcy6RXY7xcRmOpxCWwo0hF7M+Du5JZuTdvu5waK1k3RHlAIf9fMqtpFqa4
/KglkgOK46YLWOg98V4=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cUsDUT+TuVyMSf/EEh3e3oVg55uMy42ju7dn2qfNxoV/6aNQsmopR/owNzHJ8w2iRIbnD/sWUeVD
YfC5Nh9wQkO+W++ModGSDC7LnmRkQos1o2QXsyGO7CwRp+BAnJvattDBYemVwv4BYerghJyYxugG
VuaHyMph06OOJqTM01KRiHL1l6599aYPL6x1/zhvgxuLp5p+bcz4yWnxtE0ZoamT2LCdP7gM6f6C
edWtC0tvUpoBL6a3+CkNW424HNzG7euC5cgFf3whD5KjxK0sgU3DOgHfGxtZT3pY69/36mu756TX
JZSijhFRV50xlcUra7R9ar0hdrBRjEOSw7W3vg==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
msL2o+GmDoFk+NL6vgip8zUMztiw6jKP1JrnEkE+4rDO8UAEw73Bp+XaWDJ56xzku7n2eZey3ZXo
5t0kzk9ueKFNecgIlJ+KU5U2yQqYWSItsRIQuSu4rKPl8Rqn+dE0pcawYSBPhVOsFFtaXlpfXI5E
/6dCGckETNQ7yeYg58KrKQfp5W9zaaEw+sE6ym7QBzCBb3dmWjdUqH7paIeYhjytGjAkhoofSzNg
g8k2NBO+eeLdDWD+xxiRjuDbJXen+TTEMwG3QFWPP6FJTr097RR19HGV0ON+WT7z7zJCaS6N+Ajv
3OxS7NRyD6qW0oN/CBWf8OZtJ5pG6dKBLcxCJQ==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
kXQIZv8mrCnXdeUXTei22vQEDigOjr4M+bzu4+tut8y+H4BU8tqpgWzAawYjBx0Q9HqqEYYKSACf
UeawwsHxb2466iL/YrIN9+RqC9NKqlbJC0Gk251C/dmXlDQUuvsewDbLU4g9y+zb3nua3y4dKwNC
QE25LX/Sa3SyQazOgoFWwhfEsmEbi2LDvoNJWIuq7sSOK2Awu1VlnbJcXjjblq6y0akDL9wLxa0z
9pb1oK/XSraNLnR9asMy7i1xZ7fwmuxwLowdIK1CU6T/qtrhXctBLMsJlQ3gnD7FJ2klrTuK3ilX
2lNAz+VBfdEokkhLi1QPBxGu0q6x58LkOoJ5Fw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214080)
`protect data_block
BR1Q16Lyg5zz6kUNIT1/rUVWp1M1MAxsi8GRvHObVeRDDhUtG4HwVLWBhwN7oZq1PeZ8fiBCeUnY
GLuxSH6VPc7Ep4Q2rDBs7DAz8dfWQb1LnMEB4lXwtXR4DJwittOqTklXJ0bv8Wt7aEyWWhCNKKio
v3x8RzWi4xSeOJTcl7VvmVRF4ZCSbzSi3gwZ5D7NkqnN78x7qvs9IaZ7+sUk9tqvRGcTKJb8mFeh
383QXS2Odp82BtHJontYNTFemShoOdmQUtt3TCT3z8DS6apGPx2XCsSyUzLnhCPQB3RG5LJgLaKP
OSpTiGNIs2Y3voZU7+8ATsTkko+1szYoG32QramG3zNz5HnHxcasFU56LZvQ8G40S1vZWwZaqbpq
8FBRHEi/CRkCJq+z1w4DxVQv/FvnFyfVVglAS7WHs7TgafDag4ZAgpiyOlP1hBy8c95JR4kv3SAX
8ASRqInPYY8HLN6A4mImkIX3YQge6uPjx3Gu6yzUIpcL3Dr+qgq+kNiKu7UQnXZ86IMYeiZz9Uw3
gEpnq00YIaccHMXqAvjBrljJuBAy+QEKZ0tmpaJhzBUNRwpW8pRZXpzPb8SssWvQHQF6UpTw1Ncn
cGF+TveIZkx6u8CbTof5tY+pGoxAwbKXVHpQGy8JI/YApoM4gFB3kO0yGeMVsEZ6pMWHyLr+uWJY
hJ8LQYicN6CtmGkdKgHYp0WH0W9QuE2bz2A7lCwsTey9NpPVppgw13WRweaZoOO2bmrhmQWM9Ste
Pz14BsSz5StRO6emnbc6g/bg8wdkdEUhAdg3Q9gAtUTtKtAgdOTaq6S1h5z7163v1gYg8jJnuO5t
i+v8FpXHhjWKetJLwjJu3wgfhG2zeWQ1zr6+2nEoZFSBlEpocREGBPBbqTENGBxOmiXeuVQj+j4F
hbS+n41nPbaFEmm4MxwCOWF8igwSUN/QjN9RA6wqjcY1G88cFeF7SLMqFlNsxA/c0WnJlC2jCcIg
ZkkIvUPBeBe0thAxkSB1NNfFBTgW15BCD2inpCFzX4HWWiohnhEyKmMlXI2DhNvCr/da0JkOPpXV
ZK4qG1nHxY9afOsdsr80zjOklpilxqv1yA3GqC1jjsoN2G+7DFX3MqT3WLtZgO0c+TAfh2/YjkHM
z4dIoFMrYz6JqFxWCDU80e37UuuU/V56w4SSzUlFxsxVc8sj7JnVC0D/2lhu5i/csncT/1QkLvsA
gQailKvcsWcH4cZJTvwNlohWvjVVX69oAcJTWtA1Qsn10vQ6FaOXar7rHmSYrLDJwVikZQHM2JsH
o8zcngFSO71GAzB9lRx4jbVjOVYo/t1aAuHH9XQwiuba6il3yIkWmxvPy7VPc7WuDA4fIl2eG1gi
pSPrK/2o+scJ9NR627nnUkBLSc0GcZBgHSbbtf6kLV29YdIe79rruwgANFjTRsaQJxmTbh6aDwTQ
ZgiOSUj7Yh27d1GhU1TEhmP/HLBjnCXWkmjt3lIULjR6ktBzulf5nK4uONilkUrrM84BUGhj8Ctg
JpYEu0pQ9fhtHvZdagKs/4f59HU4FwCDsgBf7yOBSMG08gfNK38kT4uWzO0sSGjO6z0cgtf4UzgD
gJdAncHFQU0XDg4+Uh58ldqUQNs+xj+Gb2OoaRKW5ThG2u1VPGGuFOud/11QuHb3xnhkzxImMims
JGdrAQ8/zlZghI+mQGI7fugi5U6o2hgiR52YSPou491jSs69Hr4o9+31Uk/O2+qLgB0iQmroafVA
HvURSCmLQ5OVjH3GMi1VJ8/dY0i4kNxTnGpYwr36q1VjxeCN1JJuCtw+jH14xC9dd7jY9NsIBATU
dwyw2D8vSx+m55g1+FMlj2WirC2fToU/EXBnCCy3xvbCX2T9mIAwti69ziGNJanstLKrNns3dfwE
IVjvXIkrI1fmrovyFJQUV8zFtnHZjK7OLB/dL984VmPVLS14K+yPbVUR7HF8452myt8FGuqVhOma
D1tGpzWIc2qwTVa4CFgAQWbmMoVAt2bULpy88F9NQ1B+6OAUd0g/4SQZmrhfL58W8ddIOZSMd/nA
zaHh+zUH/+N7+lwGQ4lF7cHnp1Jc+tEbssDNxGqVPsYrCXb6M9Vyxqh0GOZtoJr4l00CLF5fn2Ho
6G86be4szTVe4TZheAT55nK431wWiuDCR8SjHJxkPpPxKtEki14IsUrRhnnQdk+ubjbnS4Vnjo2x
JwlMSHr/W6IFPk88iQDjUYXQKDhZpyfvQqKIVhGDTzOuB43or6wt/Yay2Ux+VfGU6907WqjZu/ft
+LH63N7k2ySUbOlK5OLz8k4mcRRTDDXaCDs1lc2h/Bv5LQ3Rmr9iF1TXBeEGwcV80HtDxjP4vD4w
JIwiZc3ypYouya8NtbvXbbfEdVh/Vzrx4CVGHybD5YXCvQHABHcgRdP2wxRSTlc1favJyU58gsxf
lZDwsfuuV/mc+SZuYxo+kZQNcd7J9AxSRO21OVPVdlNnVk2b3e7NsVF9yMhVALs6co2FWrca9rYr
QawDNpQD3RhrhzSDsuOglPMxsX4IF4GLNfENamVh3pHmXbD+3aR0Rz6ziB8GOP2A/EWbuBfBX9jh
AS5KigAYwf4UIvSm6+U3s6wCeSpP6O4dci0rL3jo4bKllVNcPuO4/tweZKafgFdyn48e8XM9f6zq
abEfoNT7izTjBdJfzh5oiahi2U0Yy5LWL+tvdkEjSMgE9iQ7A30yHXo8MfSb3haME8n4wfZP3WH4
w1BcU7EWYn4hozbJ7omyOudp1GyROpgMVVZtu4HfXuKxGblAIg1irSg7Vk8x2xm16H08bRDJZp9Z
v7UDskSoLjQ+0I+VjEHdumlOpUA07/Yw1x7NBJ43pA6M1w5hJjpawm2AJJYPGemTfWW6DhNy0Yh5
CO5E+SwQymR9rDhe+MjDXrfNxESS7eQXm4rUkLOP6BzHTmgQ3ULwlx7ChIblxiTtu/j5JndaJoho
YS3ugUPcZSA/XygT/BP6faJkR4UkGzweUH3OO2tSWp53KMC8sqKhYfMiArPqMK3eDozMEyoeJ2so
C4DiAjJG4mZzRBAPzl2RtgWDEE9gmZNHKa3NltxA73dHrad9qdKB0OMtOmLX2HfYIpu24JqX7FGa
h0+NWZlBRPuTGV5WdZUg6M724pJHnG/9PDhseTqjG/LfXITjD0pE1Pv4G6PyDJ1D5YrDrsgdrtBE
RACjmYj8jHAbj9QiMFM4U1a77UkcLLacxkIxiv32FLOoYQI5LYfkrZprtuLbekpq5HUVRua0D65r
SBRRnxHR0s4Evm32yhGnoGGhGMqHzl/OmBs90jbLwXQa+yR6Jku47XStOziHBtfOteQ2EWlswhdo
Tft1JOCce9uxEwjAOJTOlaQg7sayhSE8KkF2qllY3lPwez+bCMkWvC9KFX4UXq4ToWvh/gIwVuSP
LkywPwXZoLN3hZjmhrSUQmsrNp/JBoGW44jCtuuvyczAnkqguIFjVdEhfRkty8QFHlTFz7GqkeEE
1HrV6ffDOJOYdRndqdHVNdp9SOqGWmJ+dfT5BURCdTxdgjqw4iRIhBdl9c+O5eA8+H2goPsL9LUK
6tx4uOx+g6Pr4/01+Bp5aCrsiiqqDpTGi4/Y9mR1YZn7n+njtA9gm+BAbDO6EzSmPe/fa9Cn+cZF
ndzAjkZ0GOWi6Nv4QXM3FffCCAWUYKejbzS769+rXZZc91akEUpG92iPuEykeg4KAy3pZZh6Afmo
z/ja7wBXeuLFxNZ7LHfkNAqq/PL9DfVYuotgjxQ/UCXTluPo9u4hVyfN85EmjeiVIchysrlh4V3u
d8FDTTeRaODMPl/Us0F899qnepstx8W4ZdpONVMxlOf9hP1+anC1iN2h5gauKgqQ8YAh/L+xLJ/K
3MUh8jRw9EHg88NeL2wIex80Mx76AwGb2S62cSO3f0yYUkvAJsC3NydRwpf4qgGvMtgfxVKmwYl4
RkLPmCWhAnoLuhqveWvvEirP5txkHZd/tYJ3VRCS+1hl+Lb/IRXNEOEdH55W9jtAdN5JqITmjk6O
cxpT3R0ez6GY+q32Q+kPul9ER1gBzPPMWWdPBxZ7CJsDJMJLRCK3f9bJPCHe/y3cI/gWF0fY4iM3
QGgheDrSUeVKrTSCjHiGE5qJ6vcA/ddJMQnDeuF/24AOK6iNHHIkxrCuVy5hkKvG6Y4sryVOLEUV
alshUJM4J296SJjxNSVpd4q9u2jTvwQY1mXbp3umx2105H7FO7ThU/Lf/rNpdGOy0yWFUvQ13lIM
C9bCmhkkpFvo2h9F1YvJmvHRDK3NZkq5xgYxb8WH+1vryrbA+Aliop5YaAAIXTxQwJt2lfJJXcfZ
dg66dTBJ95Kq+2Tp1z7vhggalibPOttGx5XYAwCpYXZXmdMnNLUSTCOXDWQQWvubRgfD+MuspBqV
2eu2FAgn/cYid4mIoubRztD2SXVIVfeZYAgIJIVcHbb+AZeBRsM/DfmhFUdYm8uro/43s2ez1Sgo
+Tn77TR4umfbvll/IwKyfUoME0HDLt1S+zmis+8rkOGun8nBqMSgybe9vSm4nXad2M1oZWyUoaOx
7KPbT5Tt0RXXtivmmKbchL8FmSr8niyjjMG6CSyEQL46lY3Y5KfUI6TwGLAL47EyiL1CbNxfnKa+
B7XbCdYnLY8PuZjNP3ntyEhDr9mJr91uK7HzfKrEFrI/Do6H4rDHlWUDKC95gLcw3bqAV56/0bZP
UT2NY8IRAZGwi11YmDzanMy56oAh0WIcJAkNGhzwR4ozuIIdxVoJUXMiL38hK15jsEo8nf4jeCnq
WkltNuQmtGJP0xbWtSiBCKRBu0ezci/ky3LKU0EjH+TbfHfEObfYiLjz5ElVb24XOEHLbCk8BrRj
8CqPuFOIcWe9ex3VhVrOWKYPCuqVwxwhiwZKhvUNMUs2pwa5XQB+OK5Yxwly/OMX/G3zJ4qgz024
gTmOrJ+Y9ft6HTFBhrc5DCEstIxR7IbJlVGgzwaaW2LWZ0YLhFOQ1gMQFqKS86tu+gISs1LgdPP4
QAIWY26C9rDbWuZeBNI6KdhbmL8c+yAnQ1ir2qPeiz0JP3KZZlKfTECbgM24FsfdEIr1pt7Rx9Qt
3rTY8qmkAwcNEUxK4BDAEWw23aNimVxXO4yPkXJ8Dc+q0ietgW9mXaFJTmJvHSl24sOVmwIzcjUQ
MwbyjdFIObPlwr4G6oAsbwDjN8rvhq/UOU2rPvyGkuk0otim4do5ul2aXX80gok+vLMiA3XZyob0
izSnDBk5ooYfqlaPDPFRqdFfNU0eGzb/t4HvCl89qT4FKsRynkgxAjbja0JPUlJJP6Eqm2sH8aU2
0BOYSTbCABhunP6NNdJ17SEbCwVVN709q53ZplfzU6yllCARZRm3jBLbUD/llpf4a30wAUmYI3xu
XV3OfrRJZSMSUIGn0mDnILPtm1vCGKhH4RHXskwhrU0EgB11kkjXJ37ecmoUQGrMQcNV0pflIxtp
w4STGBZXkv70WzmKYYExXcTPk3gGl9DQytj9KCAzEF0N5gxYp2ir5xX6d2UZFIxtZSZcITsSYC3X
2lOeEiNDos6nP7/+yJXBgI2zsHZ3jSX6VIgSCxkW7QtUFpZ/VMm6kZJYzerC4Hnbn6T4RKaoQDVz
OfQMsqW+asrudukxZyEC6/gaG4uFNNnXkV7VseuNqdOiwA0iluvBsFFgR/01tkTvYaAnxCHYG8vW
sSMQKzPQNrvqasDXpoM0abfGqR9GvvVFMsXuLw1PhArVu2x9oWXun4bmI1XrE8lbbK4CbWce8HsS
/j4XE1OhmU53iPAx1e/8pXTvjv58aJ72SNEEfoWH88qQFvij56nlmlHiip9aHa2S7bqss2d+2qrg
4DcxLoR9LKCoMD1hO8OOrh5kUnAkEj9p0K+FLGTRJR5dq1Xw6s4eCBrWgEi0KI1ZMm++K6sJ8c09
Hj1byKlobPmK1sAcsfq8503siyNJpuDWKVvuAr9whRVZHmYIH0EQSO8N0bp717j9/g/8I3OnDl5j
vsJwl8u47w04HivS56Veunvx/zcR68IjyKcVGYXcwG3pObmVfe3KphK+YmG0k4Ddjbp7xnu23wH6
b/bLqE1+5+DfzDXTsMIAg87Yt2dDx0+y+5/pi9cZHLlNsxIbcaorzv1PpsLGZyd1qY2gGM/d79rd
LIwsvbVZaiWeaIa9evyy7jALJvJvbe7UU645i/lquN3Ilk7dE/RDGcJerMdIl3J58p2g6X7MxCXW
4W91NZNcn2BcWkOMAGIJkigeaLdWQxy1v9phJiORHqbdIoeLQn1avPCJRCnWTnWDVC6hE9dT/Ury
JGJMLDADdMQBeJIc8eKG2SM2K92fzdf3AuF78MDM3M1J7SDtVU9J/7qN5Rzdg4rS64rhT+EnGByn
uHAUKs/RrJJx+TtTvLiSNid0zMNMKH05qriw0EdMEw83hm6wkeNEooEi5ltcziCMsLTXgVmAj2pc
Bid76IQYvZZg+GfVyuZCfpVrcmislWROpw3fKv4FIlyq49ZY3zdyUvtnCMZkNcNekmvy0R7I2quR
Kh45SfO7PcOGrubW4H9Vnt95GtCLiVvelbNsh0Bumk6op8caUIHyedpcFM8VVE2HxYpx3NIhqBdh
czVivuiMfKTaSzODkrOyY90DAA5EqKF165SThok/x6K7yPVOuZnu0LxEIlx9arnzNN7cSLwx460e
DiRbDg1y65vPJ2WJ+N0OG+o097XNEfFcJUIUQhOqaPFMQhU7ynav9TYRbjlSu/EuGnCIqvBZn4oM
4VwFtb0xlVSXLIrcSqKOgGWlhGum/OID3NsCWVSRIgn92x9Kl60ar+2j7Uqt/kMMK/Pyufmkz+6P
UQ2le0WoYXUrF9ORuuJaPklkt6iA7w0niMGUDw7S3EYjE6uOrcanqez+KlbxFxb75o97uFesk+Pb
b/0V4O7S5WAuJ4qVQd3300ZYN0EULUMc7uzvcDTkk+Gw2EaWoYSJHanMWhHklnDeQ4t5SrIQUwwb
O3Qmx1XoOTwGghv2ytqJdiZI5z113urzEe/srCkZ3fsatvrnFYtpvQFFxkIPp5oP16C3sNn3ADbC
ur3kqqVEzwwuS5KM1qQKNKsOh+wiF5efUSGb6wKxhhkihGdV3pzZniEWucq/o2dAF6rL7UeB4e82
TTjMWOtRM2oGA2+KGV/mpAAcZt290vstpOy2RBHsVJDp59Bf2tnHIuy5Ls6xjAi7urOVolMW11Ee
Uel2oDZzh6DQBC81Lsl43LFFHLdDjPcs695d8qRgWbonBfNpvVBDUdPdGBrGm3lSRw6FsIH4A1DQ
Ejpms6oNu1PFQtmnpzBtEGdsrIfFbNfBYEeysNl5/q/Xu44H7+hxLFwwVKr8EpVFRdtnF23lvn2Q
rHwnY17jlXivPgIN/p+woSEHgre+iTgC3h0ndrn2j20kgSGdD37jJJJ0H6c8OqaJEWvFKhAN8enT
cyvM7c+DqjY8GtaECTPEr1NJ7gqvKVc8u+vXGgHZ1oAsP0UdTFu3aDeD03oqVxC+wFqdvG3yqCZK
bvoUNNYE5c86giQjQUK+JKXR+8EbziMeQPE0VdCxuW1KNtECcSR0rEzGFIFT01lvBjy4VX305CDf
ediwWyRxsCmix8XY/dlBw/+h9Al03W9j0bHCgYZHSVt2SRrTLufj1s7LOJ66pt5u0v+fk1N3vZK2
Qotq4LBIQ0ku5Htl3QMnDz3XUs2jijaAQ1M6L465ssh4gTdeJKbQDw/c5ByMgi+70xDwLoGY/X00
uDGsPygdyUUNz88waf5cPGEepMsJLEDcpj6YHe2DsYdlFWycZG89UWkbo05tXz6qVmZZS10MN66e
FejGWBBmymaZOAtCKnMUKNCTT/z56pDIG3vsRQMQLn0KbyO2EOyvy08GWu9gvRyT8SyCNrVozvjR
xPJe5FhgrJyq0utal5efWvLR3QKxTY08V6ht56rLgANt7lipYph1UG9rmj/DRghRCTXeYpP/V1EN
o3fOEUUQ7UbhDjwJ44RVWYPaAUjhm4EoiginyoIBmejWCTPOIaRQHb/wBx5rwkEKHtCTaojAn0JZ
TiXOmZL80zhhPzroti+QMveCnqoH04b9TpmMsJOYgN9+5b0OQb/G5FROgOjhTxD0LK4lh2I2LUGy
eTQWGCvkN010fYgI6IbPybY7K5NL3fNBXQ45WxJ26tkQBxRQHj+1CeOvk53vKYbhT66mCKsszJO6
RW2RE56pGRNyIjZjXqf+IMw6G77eRalpb2hUdCQR7t4HYbbER4dgSZfzKpY+SFNaqpaG0L2ha5t+
Q5blpq887kdWGy3dRetuvQCvcFnlZ7pkrxWt8+Q/GbBaBxX3t4O62bFc/eqyWu480q2ImQrDiLy1
Opt7t1hJQd91KHTE7ffxwB6DF75xAp37OZKz7ixS0lAGtOCcvV+EkthiaohMUhEClI2XaUt8Hzh9
pxoy5FyNajYfN6n6iMaQs74Y5rqpmBHAU4jovBoci9jlNGSiZUm3gPEQmAGCvAfbGXB651m46TS1
iiGCDrqwouZmI4S1jDva8Ie592zfDxWf+ArGULOeEM2DJN+r/3nkgIqfBNXLwUl9QfQMyN5dsli1
NoQ4cZ6butVnpxZzfRybrUE1mSaMZyEekOK3fGbsMq05mjfRMEZC3A10eaBdqhGQ26WywsWgRSwQ
Xb0yuCveCNh0stJZwyZnFXTL4qGfFdjCcrwE2XDUD0tMORbLKwyX1WycEDw4AUbLKAL32pqX9gSJ
pZvGKhwjcHTjpN95xYpEC+TVW44V3P1XbNc2ofI77ewBhtb8hmEIHbxF0pHp2c3cCvgog79SYUPx
3KqZ+GmpM/x3jRvQvyW3E+0jIyNYOFTA5S3Tf6tVM/fCMMYU5AeyuB3fi4HOl85XVPp4+tZc+BnW
vEyV0GuhLBOgySvGNOa1Cz0gKw47ISsJYysuPzW5ruDYidh0zeToG6+iQXXN/HrBMbqzmIuAAV42
BgaPudbEg5SXPHpAPaGxfSULJMlSu+6mklELSTEh2mbetT6IE6nL3v2ipVMZ7OoflRLY2CX7IRpI
u4ucOEppIDYNbGjbPit9BJlh0mSN0ONclQvNZ8pGFP35m4Q/95B5yMFSKjrZrhy6U92RajzXAFCo
aSTGbehpMVwRxQFs6I8RplcpwPOQGfUccd8vqa+9MS46DfWD9pQIWfoyIcIZPCFsWpUgoe5iumyJ
EsdBFGaKmhyF4+S8umgUae+SWZa1NOrALEyg6eo+pVjo2q0/T6wPNCWNu/yQ93vXvKuUYtXyAlNt
tQbXbPcCQVFUi+/aFFpPKXfaso9lcJrpJcsmb+OwL68Jx/x5am61Gu5f6jneS8ZkKVU2XSpg4svK
MWSMzmFr1Cf80ByP/yRB+68Kh76zInmqgEuroh4PUhbUG2rUqFu4/XcjODWfKe0a8vXaK8RMP/1b
cABZeqpjaQxEv3lZ3vW/lwjW7HBcLMZ+kbTKRyD1DHQ4K4mRfZiyrY9vQg5k7A1LTHELWij8rcl3
ti0ly7F2lVxJ5Gz57Ab8WjXT+jKw4ARichRj3uiIGZhVdY88TTfQHJ3MdLfOOBcyaA5jtXkxUrTO
6eED548WTN06oK2ijnkJeVy9A1vjrETB2DFdVY3svHV1S7e3z1yX1Y1woOvM8Ki/fqQMfhTBFV9M
A6l72IMYBEvn638kzyU7PxG5dqFypWtuO0hLTXMQcBJBZBTZzi+LjUtsOSE0dcqWAM4m3OxMFNek
tpNdczeLp66j8GnPxQ+TTYXGiaLgbSKiXoXzrj+Omg2CylIYeNoMBJrC8vVELBjf56l+SIfATDIu
lfOZYktfRRRHt7vPWrGjoROzh2+BOurZW0eoXyeryqT+0ZvXsI6uEyqVYElm5URg+2zfPh5Fq19T
efd/xfIl6nKLEtCgDlzZe3/dQajmCCrr4moMTIvxsiNf5EYpPEclw5XWwPxxlZEWlWdmkWgQ99Tk
1ho4KFPoYNRvbTTibS5avBmy17dx287+MGFzCzRv3DQZ7rTsvIWDchECwikCQzJoOQyMuJ3R0zAR
9GGspEw9LIEoWj/JgodLPbFosEQTWVi1F/x9P+DgFFVrBKtA3CNxhdv4JQstFtZXvl8q/TrVoSh9
XGl7wO9jlKLlnlfpU+9wi5WhdVH4vm4/2dPgt4pNStp6E2VX2CaYl0H2fN6oemDnd8pJ8reRcGQ2
pOfpY66VANypT9SwD2Noqt8M00XJEdnC6fsFQr2THr90SovPaN3USHB58a5o8tFrrDBc/vukCVQi
Q9BaBEc3qtJ/165NG8DcTMo1dFS+QL4LWgQnR5hgZngI1DB1OUqFvIOD7oTJZN2MalwR3pfD5cZS
WHVX0fn8m/zWt+3ZxrPpeHySd+NUlSoins1W9npHgfOPN47JUGjoguf1t0CYmZsWg0xLbFgF38a2
dEJVWP6HJKaoP+7cQa1bXlrPCvqrORZUl7gNhaakOEnbaQft9dviaKbCXsUTuUFJ94+Hj5sCz/2f
tAoF5O6F2YWUC/MCZEPqJeXfN/GGrpBwjAhiuN8a+uIsJ2bdyd0+BezcPB1VAZu0ydkM4SVxt9K8
hteRBmwGiZuYfba+lZ6jXv2GftfJB3NnC0oRw2/yUjRLozuPeTl8Kq+PguNorq2dttQqK4o6BANB
u6gCzHptqiex5iIINKjG/emYNszSeK6y2PbQ+uS4wDBRy5JIABsIiZXG2l5jy/CZA3jKUHnI+EB2
go2sF46w2B7820BLpmaNUSt4e4SfO0W5lZjICuy1HjZOWeUvg3IWESvV4E0erd7gXsM65jbpIDfb
Di66ZzaXKaULR45IwARDLF41WT8C4FK+zVhClH/jam32idL5dxFDeqMMLrJj5Ue8ol+UYeRerH8C
y3hOzyJsaxXb+Ojtk62SN3fqT6XTpM4O7WUMkhWbg2YJ+wHaF/i5Y6kgFe9VteBSDwhqFY40QKzZ
ojHRssGWIcKCbErhHV2b+mBEesS6b0ZlPq6+Ufw4AzdJuSqaFq0jZ9uZKqW9neBsrNl+dkeuDSLY
QBRzQW/wH2+pzqrR7yaxAzPhZifCJ1RGxYzptPc1MjuMYwvWyYZwPoWBFCyj4ib53eVNpVwMqEV9
hF46W7XVJ9S0yseIR6MWy/nqMh7lKh2DzJjubOksTZwUzqoI5MIdy7xgnFfZnNKFkTlO8I+LeGLq
/jsgorocKI/eaov/kH+p4ntxzZ2eM41lz+N1QYJKm//9E/1yDNS1HYLQA0z/qfuAjQVirAuz9iFY
iDeQivkBtvCIIL/7ldw7oe9lkOLnR5c6/3Ggl+QOxUQhqSqmyoizhlgbR01UJ4/rd8lhAIdNaYX6
2j5HjYgOpipKXpNXNpi6W9G5cfmiFZxDCnfeYCeUXaVOHrIwHmleu3W2s2Jspjdp/Q8235xlaDLS
337LfEB45lHJJUJ7K4j1IgI0gm+WC8rAZpyW3Rahx7nFtdvFKvlvq6/FdMmIGDUvNwTz5R0YId4s
wjuznAOX12wmI8WCXw3garUvcqrw0R+/9JF9qboMeSCq8uLLuHnbkJ8luo9lbrt1q4VebTpjVQLG
uswwTq8H99BlrUOMHMCp9UIoIIutSzKCeleC4xGT/ETiik0cU9CcdiTzzOr+XRsRI3Y7u30ex+VI
13DMpNY5pjqgYejMTGu7I+Fuw5PwnE25c0YCeAG8aoBhZn4e3Va0omVuXU6m4ZApuTTvQor7tov3
gaO+afdxAStccTq/tE4BQr8dc7NS/rQlxnSImjoi1DZP/u3Zs8lj/4MlcqqMVKsrHhMACKCulB46
ZBSm97bVlvrjKNksWETEWJCWFn+8sNZru6JnwGHleZ8hEJyEAv3tD/YJ+7bwozZczuNu3NELNw3s
LAAI/AE3xroPjH4LQN5P3rNmzw5lpiXe8l8wvKkKR0V8KvuRFNF5XkAMhH0Bb7qQG5a3yAZWsgw1
i0wpcaKzB414famGkPjln7BW1kY76iVZw353waeulfHtb4WztHYOOLg7760vtlQovtCMjwjRAkNC
ZOuMG+wywM79FUuj4ReVVKt7+m5pGMoi+WI9y8bzhwxVWbgc/loPe/Yvjt+oronMcI00tXJTyDU2
R7Ov4VakyfpYRV3PY11paB+SAS/NDLZTQYes0/YTq3ZZOEn/dqp0blwhLxFp7fHSFzSNMxdfUPEM
IIDeo9W+JyBH1rdrAwVbKjv+Odx9TdlYSj7sAuWsM4xi+eZ2M8jbfb2nYrSTxdCDz7FEq6GhgJXn
KCnAweiBPct+i8HLZiOUiYrm5zg6AF5Dtt+xRKJu4dywIxT2bLZCryxJ73Onp9ps0jmrdb7ashpM
h0XROh6oj+Xh2tDZjQ7UI4RGqq5+vqEoke2ldswDEQN3cT2neGB+wnBkBXWQz0TFQoIhqTGgfuiZ
CZcpaMkGEhmhrqThGsGuV3rHtVdHrF+lPfe0uPUCCag6vlrFP4doB3cuykeqX5OrcwrwImcF20Wh
zLMIO9WsfIUDCI3DUXnF74fGl8ZH2jOBAl1cuPlpFqjd41dhQ8cP4ocpXK0Q44xu6uIPaMvk20yC
L5C4x0D8YXF8ccFVEeD2Hk40HD8yBljjdj56lX4MV/5Dmpp6E39OhOBiBiDHwR2f/orM2pOp3mTw
ny97EnuNlEDlraUJnSzGZb9l3ny3b+7Ip0aYLrz0wp5aNqVmLxythHDztQVKs4hQY9tncW8Ngp3Y
pdz+I8m1zt4YANLqt9ssiovGfOmzGYR18a/VBTzAfjrD3V+mQyRRYNzs52cIqVzY7twTYr5A97Fq
5TyD/4SiJ7V/TQoztW6D4lNxjp3pbKM/UZyLZXWOu9UAVHi2F7yRTFl7zBmxfJkUeIJ/kVfDxAR5
Mnx8kWqVGv+Fa5md8zEOdAmjYJioNq0wjFqRmbgZxXbuLKwEtqRZThkZqblglD8LjAeRH5HW1ISN
FY/WPenQIfK0ABpH+Pjtp2MsWKyQMrD9uYpjB7s3TBU1s0bOR7eBaP1Wh3R7Ks3NBQayXMoYRcZG
/LN11EMPKhIoKw+4xVHp49S/TsKGe6ENnbOIodklKMW72XqsJe3H8lihpnKFj3WOKkKWklRXAide
I5NHqwNbw5SFg50mhmHf4HdmJ12lLycmEVUneAw0zB39kXODgDUyhrqAsCtUUKUAWIZVlnnHze40
h1tDWQwYIYiEvhDi+Dl/MXqqK+4OVZTojBBW/Nlbp7lWU2ERiH1812YY+XC4wrUlpEbBQEHLb4ir
HiqWsSBOx4OlsQPJ/arBaR6LkNHsp3LjNbkPyAjFEjuGjIvDBzHTJsSQZON4sZf6qwH4Yo97O+3w
5PLLOhbKmyTmwmwofUmnYYQfShUofVkqZ3p/HaLDcB6zlPZ8+dq0jBdTQeOHOfoA+L5+4cltfdYn
lzh8qmLhaK9NChE7JC7oT0o/uCkM0+0baDl5YaN3hrh4e9puX3A7OJsOID0JILtIjBzqVStwjIzB
+rs2qRVPRYrx/74OGfBRAH4hODkDzXrFk1bjd2RizcQEGkjc2+Ahww9R0tI0BxBMaeMnCbSkWJqO
jwG8Rj4kGkeWnBbMlQUPsh+DNaYAK8bHgM/cU03ebESCMbI3pExG69Rum7kw8BgVXO4eCYeZvmoE
CQPoxfWynx/s/v+kZ+Z81UzlKRYFRgouM6Prus+IY52y1eUlDYcVZ76TEGWPVFvPZ65ggiuMv235
kBtv7b2ULT5ipo+jGdj7zeLMN5In3drVfejlLyiz1jE753uWpfrGWf2aGpcfxgOIYhuwrd9aBz7I
AJlpthPKUFh4adlPRPvfrS0UZauQlWE2/9zH4TfbaO4MaAPPM0qDRwbnlK648Fd8COVmjjEsFvqv
2odIbgkqQgJUybr9vXa8SmWQbE+VPAjDdqrpzN+C/ajN85Cynxo4FxJVsOmG2qteFuG8KU0plB74
0sHJFpCBMm6h3XttFDCU+z1Ehm5cfiWEI+lZQduafxcOiYvidh1lcmoZEd08FoRsQ6/z8G7rKkYS
sU5dvHiyo26iS7oPjbtmLJQ9RkLuutvCSl2cW3U0Dja9nRBFnCxB6VjmnLs1vwxOp88I+IgXqcM6
Lg1RmpYf8YQe5WkT2Yz5CZAr7We0eIu7dP8RbJIpNjF1LRlHcxwAA17Rr8309XjWbHI8bjJavEro
TrqVAJNBk/mqJQhp76ZDJsruF0LhenCB/ryuNV7jd2lscNldk8f8cscYfT6muEnFn/dn1/fWru01
sKm2YIshX97C9Sucan1iDlAWbYx/7VFI3MeBZFKs8geSxCh2I0uBxaR6lkQk87GBzOF7CBcHChRm
4p8r4iuZfdpYNLzb49wTcx8g8D8P4ejI0+qPe1byIN8yTLnfNHe+n5fhNUUFo4YbNQPV7epZi0eg
mdo4n3xonZhNLyg4XFHnRRMxUa/CPu+wqw4TLXkkNqu63MoZu4AjyqGlpvvFNSL3BuD241TnedT5
XCxBhkuy2yHQgBno2JGQXliDhUZB4mkJbYf8qyRl9Y65IqgOnWUrvKWiQSEBaBztwrC4D4T5uDB9
1tSdbdiCP3ghr3REsmohLXbf8aTwPxcqAltP4+09zSBv49qmccwxeLNrgnyO0IfYTr3Yc0VVsp93
2agbHLDW+h5HIv58tHEUzRBVWXLYDyCfUzY+8WDpMBnWO0ddOMhWBuw8OcxfgtvR2rfpuqIALcIL
IGc+IOxczLbpVYo/NYlxyZB+uCHSXKdLI1djJh4R7HrLC44z7UtDZsVlabok0bUzIm9lfNPW78mE
22nOkhotTmlugk/4BN0nLNjv2JqSeagKPJUKeJd3G59D40OQw43k0x+HRYOCGD+eSr0Lp2mhcup2
e93to1buNpWkZskuLZNnOX1tOe2L69k4snN77yZAFdd55PNggrkpp+A/ltHDc6oDiCmc46DbaNjj
nnYRmu4WzerhLgvpFpByYP6uXiEVIauntwb3hhMcaJKf2t1VzQLOf2ThGXhzZuspJ89Ytb4gHsGk
zhGhKAd7dnyNz1cWlCD0M9PwXWJAsGs1ryLDJsP4GvGY1BOvBMRGwTADTEXo5Nw924xG7QieYiyl
87qUUiPAizlK/kqLFA8/CyHIllXLlgjybNI5aIaDKw4+OilEA0kfT6rvJNNthDE2ooTTJdFkKXPV
xozbJFBSaS41v0eRIqs8HfaX/hz+2NE0iN1aR2PKmuIOXsRPDmhEorMs0QZNFVYxw2sKqJVVeya2
S8+YWZ5/4m7B9OPlJUZZ9+w9GvpfQMmBlnslL6rhGqadgxl5GOzIH8xfqhmOUc8vbMTTAnrbko9N
NcIvIzmwv8GXHXv8Yk4sNou0qLBM/S0DJN2LtNueZgjtzDGx3PSkPkORIy/fdtHySF1WIaFEbxWM
GeaQl08L6OCggFEFaAB8O9Hz+ESJxq5IG6LKM729dH3ycwG/SsW2m8euBghWHyTDtc94eaubFxc4
B5pT6Q/puOmvKfnmB+CRXoVOgfQonp/zSaw4aoNvbK/Pnd2GdgBzjl3gK5NBzS0dTiPVLB0aXQvH
ppTlTBTKipY0AB2s2Vy/Hkm1gne6yNKVzy0HcB4Hsj7hCQHI7pXeFQtqE4bJ9TK9KldnJ3/6Ezer
MGlfiKLyhvoqbYUJjqipyZUj25WLXo9uS2Hb7DUgK3Tec7z1tyvaiOZJVZ3ckFey+xxxKYLLXVD3
osimiQafaIdpxTcnMG7Q8pAnM7WcRCgS7Ha9O4sOyPAA5XLDrO9mxZAfjLrRMt+WpmzxlVYkSUtb
bKHUZgiGNuNEpBsbVVVQ3GWmK5hVkvzKpcfY79ZHKdAj57VKyEAyocIFoSBOGu3DXRkjKs1k96EA
S6MlfzZq2kstnUKN5J8tMXtsEXmldmk6y/79ir2M+TiZRPV+cCapva6DQhp1lx/F5ZDkq5j0rpYW
LxPwCvDZ2lbX5mwVxWr4J0p6E6waq2DQOury5z8nTR1oR4g33TNuGsaGDXdw3LmBkwpEKHmtULP/
Il4557HRkFG+1vlgfF3NDJkhVNmpKnAoPqziWahQ/NwTQu8GeOTmFE0ZU3MBe77KcK9AUey6cmDX
5iR+5uwi+cIkhXY9gG8gVu5f/c8AqTRuYJem7623NsIrj0Biu+rQuMPxES8kw3+xxf2oK0+5Sg7e
lh2Q2oHbSBySsyKl9vmPTPnp1L4QDRO/PnZwoeB6aj4Y2Fas9SQyP50vIYJXGqdsG1jvIjUzE8PK
Wyupp1KBka20QhUAWtFklTHVYYzZzBrfWQnOIUzqyj9ZwJlO85xuc6X4ecULUcsA+oq2kPSKpVMv
S6vtRE7xAzcG0bWXPSomBVkPyUpQRXHaAtUw5p/s2fd+PTyurGn+lduIe20Fu2Z+ygsoXHmyeEla
NvjNFCnjGSegbQZfcbGXIa3JiVzw4eaElRW4gOweydy2z4bWRVTGGqh2uVZnE0LaSHgWS4dOxVDG
FCsFqmTYdtL1cZnJqxOpprcD5gNEohq/DEcf1tDvKsAwbIGBwXYzje8BgDppDgGe+CwH5Jcal7Mn
N/L1IcLt+BGzEZ7FQHA4f2b4OJFyh/ZO/8Ro9IXi8HQ99unPVV8tMcaZKJZwB0ZQhrS7JUo+UWsf
qRttZaehFc9ydHWPVm60AXjIbTyLENtkw6URiESoQfXu5Y4D0DyHZiaNnGAeJgcpV9DWV38wBqdU
z27cezYkDijbn0Z73Y20LQV+/MsbTJ6ta/iXTSxhFSXV4JCmwxqTykoN9+8rDZZoM4vYu8a4/TAu
OVq+MqQ1r2ZG5Gf7UMaKu9ptjhzq1pp5HznvJMTc5y2F099OwCGVjNx70Obc7RUPe8DcSFGX7oID
zP6h0Rr627dcA8swpckTxaS5hJmQ3DOVGlE+rOoJ8BD1XafRMdpZ+bABSvkKLSJMuXZyYHbVc2gR
IhTfR89qnIe0wuxpiuRFlkSk5mb2efvxQMnkNS/MUmfPbmujR7pBCTGFneyuJM1WJdHEF/KxV1Mz
RCqCQzUAspZqfHEsQvNqSldFnNKoF2UOyf5Ku6NP3YtPa3Xviq+/UNY+Rlw9lkhf/jIGqibsCj8e
m1ebY93RaKKTJsmBcNKnh3nkrhqypRce3d+OX7rVnnsf0ae9CTxJUA8Xcsjc5DF0ohtK9StrEqvj
LXttVmYZjJBSamcyXy7CIcnMnT5ErK1cUp7p3GyBz0rvKRw+LuPmUkswLVsSxNv14784Xs61UMzJ
eqHtD+VaMaCPGAH24JQVGs9UF3X0XdODHdZMAjeWcekRgDZfRy5mzro0t52xgXYwSvTQpBbbBmqt
wZtFwBFD9+a+VqR4HtUFd6iQVU9JnpYaUmOaHA3oMImswNZcuidBpObdTC4ZyGqRZSaxbzHJOrqx
oAh1YYi2XOEztE1VxOolr6oZm8G6CoTuyPulTVBmiEp6HIq0WpYyAwTI/SUxlaYoAehiCAelne0W
mLDHkHA3ABngf3xugiLJcP82O/ptbCj213/czV7YkfyLzSosKz1U8CTXuuIhlbpq61gabbrajSVf
xuElqyS6XmFZgdZihNcsx3mJj3i20UJLHmNh2rYXamubvnYodBAWZVro45+7z/A5krtiPswxs8qR
9T6+TJOzXvxd+4aXO8+EI8BbTbzdkHHzhnMonq4YB367ArwhaLpCT0RmsloHXV9KuBdLUxRK7hn1
TgYGudARTVNLsGtnoxcmIJqGtf1J+2n20ZB6cT5zTVrsBhdAe9+2V7EBTWfyI6AuYeM6ldLzSD4U
3RH19HueRmxth/xYoQYqsUc9iH35QBn5dyyz29lioUnB6NPQ4K27atyStIuu7WDnCRqNxH4cT9dv
pv69TnBNKwUruCciAcdFKQb+nSf1MCjfK9Hp786aBBeftQwJ+Kywf+V57Z1TmmSO1qV/EIulb74D
1qS6vcFmIwL3cs8oKk7nED4Fp9STXHlAXCnayIuZRCyvfMpHtX7bBCpXwYinxXApdl1cZXCod2IL
2U0Pdb8GPMjSfsGhr4LNzV8m/z6Oi8a02BvXRGXkuLp1pcYwBypec9oSCX9P1GWsb07gBw9/qS6y
AMLQm0D1W8k9E4u65rwE1emd6sAA7sQMITlil12acAOHjL5fVz2DaeJWLysEr2+NwrRlKTbHlUJU
c8ugXijABJx5CesNS0SJDvTx6o4qinsGxL6+ivs9EiWTyRIzOZvKRatnmP2NAGYaLMGz/cJIQoCC
8lXT43jRNGfy0TNHzhPbloPIPick10fW/fbfEQ4RROH4qpkXAT+6wfycHevxzMSptLaOYjk1UbeN
WwZZoMNxSIQvpuHjUtiWkcvVtJ5ENKQilIMWwusLtRF8jDp58sdA2GFBDKRqIVLOUXtqvb+QUXOo
53/abJzr/s65zoX9zMMxn9ldGS4AECKSYwgcSbg6PkVQvdWyUiRk/h8KLzQxsps5ZPrg9m5KUhbU
swk/U2Mxhi5Ehzq44cGKuBgsuykW6dYSmpRKL9WUcYdEXwArNXuLz0wVPGikgd5WhJcLxXSmVmZK
GPI5TnVHsC+F5NdgmG+ZAztyMfEmd1JwPCX9ZUrMuI7CCUj2S806Z4Z6Hlfgt2xEtKm0Ugl1XY9g
vpqCOYNEllzYbnbPsaCHMt8A8a15cC/HELXUd8LNygJFw8HnDjahWwhC95o7hq8GrTp1aQsLwE+w
WN0of3wn7EbHuxQDuHO3mojnJDgGINYLDqJZiHJlSHWfzzIaWyhqTT4RqpOxg8RB2Q6Bfp74ZLbN
Y5q4rYB2TxHDMsjDJmaqTHKHFI48IBDvT3aJtncNd4aXYKKb1QF+BLyM8H26gGhfS3dmwXIqxxqs
NFG38QgCVwWr6VIR3dBozX9N4xiZkrX7h+JcCIt/FUrsA6CeJX/2pJbdoMhDujgyWrCDXjUXn0Mv
UFyOadyq0DIfmrRWgewHjeWEMdR3mlWomXBOKEh0PlHk7mOlc6dddaR5e10adx5sQkpKEPmhsZcf
jjm5r47zPERRLJ7VGRIER43MXL+j9AjYO6Jz2YQuMCSsPh0zruRYgVi5CWOBKOTxPyVXyDbwbP24
Myu2VHjWWlQcJ0ohres5FVzMFMikVeWhYQTD1WRmvYDb1ckVG9c/NvvrFzf07Vt+hj+wducefDjC
V1XUvsNL5QM15dE0hjuMqoc5tlhM1752Ov8QH/HsEJvpiuW+fpG1O4e6DTiTg0XN4w9gvM9p+oVu
qScs6f53ngh/p9oLsKBLoBLcxS+0ivgvv2IoXgPJp5SgN10w1IgWVy3EniacTBiyOWsWdkPFNF84
MJ36xXNTIU7AH9DFvnhvirP+vzX8hgsIqEkE0oH3gI07WdNNdtV2jYwnZAIs/uMWJm1n2zfa1qed
HjdgHC5vaiag01/9gZ5oUy8vXDqS1kMVy1NGH8bW2uWmqUTW+rnS3H4KU0Y6Wxk54KPK8dDCo83G
9GS3ed4niBKgnHLYFeIrGEon6KmaAVYP0ZIQs8Krgms3HeFvIclNM34SwSdPjqZVc6Ecz2YQNMer
RsqwTEck+XYWjSvhSeRJnZAJ7dQ/n+EMqPyQjHhFTcnjM+2MYVpCRPSVGXt3U6HUDqAQxN3+Oi0L
y4XvQy9ssyLoLdVdleRC7BOQOzXnkBbfHDjK9z64v/E/5S6sHTCvE4pveSIO4uk6PMsj0u0ZBFjK
dtwUvKPa0SNF9uOj7lN4ogCY3gYC5SB35dywSKSYC9h6cC7kyNYGaeuZVPB55wM7D0NnAHsWDxCd
u7ayrBlLY0KAMNQPsaxqHR3ItfZPXbmOuMHKhCxD/rJ4k9HAFW9eAC5weEM0am3IXHx9WDVhFecx
dSsUGzqN2xRcwUXF97f+hNGInABUpuJ+/Rlx3ka/sYsRPMcHwsumg95pcXwiWgTFXdjTgS+fIP7f
IH22fgWIrJGPbG9ftNum8CNJCT+hAPJqtCjvy3HtrjR2z7WkcfUnislZXL56iiEZY1iB92b8603g
Jdb5kP6IId192oVNogWcxyOv92cvZdTNfOd5zoASt8JlJaypEsGJjzCFTEm7/aZqpYTTxueWL33A
voBy2fthhoxPcdXjxwShRTpuxdg8nlWR3vTi7at2jaP/OG7uW9q3JkZpGEgAhyr+2kMVGS2nntAI
LFe/0/xSGUYhA23go0ZKieIjly5L7ZpfHDnpy0duvBHHl525hhwaGaie4zvRb2k96kI3CoKLtE6q
s+mlI6BehpNQ2aii6x5befLITXinFLyY191Y7BuQg7i8llzQQO9V8nJLWYzDr8Rc4suqTmBwQ4M1
6HnmAFmfeUKTeR+USIwm1ULuGPBst94YMmoaXUY/k7s+nBPo7jogyx1pCxQ5BCiFfR3Ug/I+0y3j
rdrXAThSGQz7moZWNLiTh4QIkDPoC7uBHmeJVe5sFYnBd6hPZAcgtGjN8YPPj84fnX7JNXqq9d+B
9GOSJBP3C8DnyjHH2KUfJOEhHg0O9MGjnBk3gDjQxEyFelasUuF1WqELrA53C0R2XzI11bd+2oUQ
PGHrqWXcb547PlRLnoRfcXEBtuOqpva2I4PzSlikIFaIek8+lL7AR9d9A6PDFVrcwHK/0Y4I9s6n
tGYxd9KqeadcJFELD3oioMmEuE5Y5btnNOwYCNFjrIbb1KHTc6Rg8PSDm/X1Hu0WlRfPeVWu/+kO
Nlh1GMpGQryzu7KupxLqqIaxNa8m3UuNvoexwPLYwjWd1ihN/H1U+77rkO9Kq17qWDYGSAb+AesR
gw9JU+bax+lId4zWbLVKBaF6/V3CWNmjvIpfHWw1L07lmg3OLqD2ZbZvR0xKy3sOlW5vgJGXZLJF
fpUxPaHtpXyFJ5HsghTpU9kPhYhEm99pYs9Srn6YSQw3PTRanM4q8w0yykGITF7LR0zyu5ZK+bzd
IQVpj9Cfz1hHuhIMEGaeCGRRiaD1/5CeEsVRbcx03pjHfXEVfKG5m4DfnjYPIFSDXZ6nTypPSgd4
fq9YDb3RH3OXly+wVlODDcKDyynvC2f22aifmrHPtuh+aGWTXShqMRNTum9b7QFVS1qwv5mRkjtt
dH2hpKfnjaaN85ei9YcJsBpcwc3SjWoK/Dr5GOOQgTLM2QyKc9b6Y/wbvPmkrgiv4b75t+AROZwc
HHMuQqdUUlT67P8bbbKHrTh2m2XwOgsBfDkEXz6yzMr+HBjj0hkKdo5hE2Bbu1/UOoyYcGIsCoLj
6e1Uvx8LsJ4KWa5z442mRMd6i5LKVj3rW78uB1MJy3wcAlvyeQQHCadP3rmNdDg5Kj2gJgbvSCq7
IUu5dSY5K9nf/n8cG8rgsEDE9evLMJnrK9GUNPgq8CmxuOQ0SqRsvRcDrC0H7MKhiu32zs+hh4Z5
m+oKE+yXXoytnz13IrqX6p/uWgeGV9D8PmZ1Fn7dR4lLt1E1ns3/lve3t1CxGVnNxczP9g1ApYpH
b/wNqb/o+/g5OdBLAxzHhF2HImH+dMvmZUEOO8Ad5a2+wsVNaLfoMdWDM80eqcaY9zAp/JwGarJQ
d0fefX/MO9RgZl8eCHrKgv/eOohQekvToh45eNQ6CITkmze4NsxTGpSoLsbMNx1siKxaJlVZW+bm
/wqTUxtkUpV6wD9DL/Ie8rCLeC66RMBrlIgUnFRXI/Om8quJVKEWjXtWEybWV8B0nPcIfmNuFuFt
+GaighWyJu55mud3EDDgXquXI9sgZTibmlDQ4+eSCcAvGFEPu+B4AEJB3xp388ocNOeUQUS+X262
ouTfr6PUvrrYIVg80kehoHvRzgwMErtpdMUDqi2ZdwNzg1pEzYkDid+SFCcuh1Zdvsc8BsnJ0GWs
ikitNbqGd8W33fU5wcGs/9iUSD5YieTI9C9HxtrRJSzGshwNeE4Dv8lXf2HTJgPhhXGNNs12NcDI
Q8P4HC4lGzAiNcKi4ZyQ/smqgULp1Rsh2yG2KpMfnTpz1CkwiQ9kcBBoAt8dErDHXQbkOZgxcnrU
0CqKbQ5rH8R1eIcw0sCjkgXo+jlTMOSh8K65csa9YfXfQebgLb84HN7NvG6jpGvsaVgPI2H9ynHs
AWiqxvbvDYP5HIScXIkEQFE2iTuUx3qv2V0b8TlMLmtHSu8RqyiXAnFgNWA3/UvKKVLAne7rgxID
zFCx//ERLy7aUkdzzCe/Rx5k6noSMYvl/GN8kSztOxlxo0CLxj66khk5ymzPs+uwUGbw1qryCys9
jBKs9qsls9L/F6J4Y9y/Sp4D6Mqpf3l8QdWmcnpyPyhqlLl0Ue+9kGOTWgcJ+Jg69DivdVLv10Ab
Cd4APD73053yTHGZ9TMAm5beQUGfD1/7+4SjOQjEv8TZ2AKkgZ7FSX8sWCi+AcJ5E8c3GnM2oEkT
JCvvPHGB2wE+qko7VPfLPn4NOLV6vkIC+EHsO7fBtwyPpRlSlevLm9h17R/TU7VP5vJkGKxVWnPV
kE2wHeSUqwOD2kDZ6cW0HpkSozkn1XlvLINSQ4DycXce5Xh7g8d3IS3Koe0wkRUMmcaAa3A+Nw5q
iJqgr6Ym5lsBKHnT+2gXDqh14CDf4pE+uBtcieeqo2LgeOdDDXvuBiSTwWMlDJocMwLNXvGdAVgS
l0pEWJDQDCr/HZuIkSvVjbpWe4nrYvI4PH19eZuZktcKaRmyNBPn12Ma+WAxDIKoVBlqk+PNKl/H
kH+7ydNkEn0oPPkcokHoY1PYAZExvDsmV3A4eFVuvgkruiXHLNkypKj/UOEWc105UW8V4sJaMltl
hXQze+jIDUpw9NB1U5gwkFWjyO/5wtV2Xwfo8pEfOhd+12fEJuH4utOQS6hLCOdDLzTZaJw6i7hs
lINZEUFwpnleNdX5emr63MWDxml0Gqr6EcybRBG0/0VY8Lymn4POlYBOWFS/cE0M3fCcOeJboKIO
ZHzl7JCeHcYhqwKZKcMe2CTE29w0+pXp7KkMKBJQqwTb06JHgrC7wi9Frxx1pJ/uWcN6kVqSjfsp
QY1TLuaZL4scUEn37f5zBvCJ5V/9wqPegPVWn4Ku74R+Rn54iVjNkxDPLO+UpuD19wXSUgjAzEJo
Pe8YNWHN4IkuI6ofclCv04xzOlC5dCRnUe440pbZVfJ7V+DWVs90NdnYqSpvkGHsiQjGM4VeZK+k
YijH+wzUaVu7HJfNyVQtDD7WEvYoTnI7Kkma9/puBybP2+Dtsi6/KP9RU45Hvo8MdHlhd1tY4kN9
Le2eX3MVr8HwgbUBNVxqGZR5e+MPo6NnXcEOqjDXSEdrC7fTnCgy2vkyLWHT5qZ3vpCFq5pmVEFo
cU0us7ELWeLfbluwi7tnGfl5tPgEtr6kAB9HiPaDoZRWuG04HjnYYKnGeS3xhkR3hDpum1cWq6Tq
w+TOFxWOEA4vfpbqXKde84VROmxcYpJsGCjK2FiPcUmw2FzFpPY/fksrR7m4xkW8GBRFbqGFW8ns
QvkswlkokT5boSfsiltaBRSEhlpb9k8gEKjNADiIM2ZAWcDZbzDAZ9Td9XrBo/zN9FO5l9bygJ0W
060RHjEZaIbyu6ssFjSraiO7s4XEvTrGC+YxHG4t1fCXtS3nx5B8JBnh8Q14ZeoTmV+bGBKiE9/h
bydceh6l+3ZQR0B87sBGQVm97Yxuof4voqq4RDD5kWDRtJG14d9mGEqQzkOXjEp0J6PZ7W6ul8yl
/SNCD8RVR1GJHsbnxVN6uKpWf/Eg2qi52/LIBfg4f2rTbOX83GPffJ9A6DOPTs9VHOhee6l1qz+B
SZloA/s1d4JxNgbi6iiG/NRc2NOYUhdojat89qbBOb+uB4n9ABlLXO2D98IbfbaienbPBPf3n+uZ
mrlhMlBcUlaJJFKLD0rd4ff+jKVYmbA/Ne7Xc2RIqQDHvTRQeVjY8YpUJWUVJKnDxtwO0/BZ0/Zt
KwaipXjaoAPXZveaSvMrndhLn6RThDjMwTt7zqlrsWuhCv8JRYy2riNGnEl1FmUUIe+ciydnY+/G
cqNBk6PgeOXSiLvTbrFHA2ZJF/nYbo9ZXPz1/8FFC4CrgpsZPPoHN/TlsucQeXlggrvAIJ95bkUd
8GshnN3CFqE9I3IAx1WFpT4OncoeQdYZB2T+DREmAWn8JBYRMwf45fw1L20eXMGDXW8MHaRkHvdw
nqkBci+3V1h1cq2mkuB9usDY3j6r9ZiSBeEYmXzQBDNzsEtjmmtFj4tHL8ig/6ZTHZ8k7EXhDCOj
GtALGaEuO3zAJfDE4lP/LR7EFJlepGgy61f+6wvgNZjWaS93qlPDnpKSeY1+8J+sn2VRcE9PLWew
hiFzkCFnhMAphsyhpTGvy08KhB9G2upq+bYgTlU8zzSSmKpkpnw394nGENvGosvlvTbA5jeks3y8
aMeH5D5xJ95h3zZZ7qRXw0VDpbtWA34rbKN0Hv5Zvw7/qfpH5jX5isfIQtJvYrWtiRiuqVSNEzXa
uhUtTs8g5sYxsUgeEtgilzWw1VmZtfcxhgv2DGDqfNO6rV7tCVs08uA6A3EVvhBnUlsklYd1ZMGz
rlx+2nT6eWxpCrfzfj1rln7dC3j+TlE5/ESeaQa30Db+I32a8FDrIe5/zLEFMwS0Y2DLvDzRHkaF
59s5zpJtO5wHezQNAoQFpSSNgotRWUo8ao6ElKv17Lvk+fUGDH10EJ8jjochPWQVR9fLbmc9gApZ
CdrZGXxzfiq9I2C+ADsIkB5ZxUZQiAUM5n4oGY1FqUtLwYlhFZSKL6AScoDkrG2fJRnxTdbz3sin
g8oJS4eugIdwHb0W/Oamw7pkhau962nAv8w8rkHANoOwXoriLitR3W+pKWV2SjlZ1LxxK8lvemY5
af77JkBu4pDWXODeKwljS/t8JpBGSPD1Qnu6A69FLbSN7Ml59OV9jcTOnBc7R4xRztLBzHenXVeT
x+L4+xILlDg/LGuUmPKUB2X5rTAq7ZCsFuuYqqOc37pBQtkI2/01l1O+0bsUmUWowY0MUB9gM/xo
fjoHsQnCKP8YVXMckz0i0xgquRm5nCThCA4Ke7wul3aF3c1Dq5QYKAEghz8x5zQtezZonz/6zOZ4
frznn17J+T1D6/lutSyFW3hzaMRrpaeiPrVLVyVcHDOVJl1VnKfc6l9Bsc/rKiUtpzYlDz+zvPTt
KRSFsdJ3hV/OEPyQk8Zp28Ay3to40Y/kXxuLrJs8JxUuW3oo2BIRwY9KswDOariPre82yD7SVqFl
xrz/n40W3nijAYiRk+7vbac2dwtb1HDdiw/BT9l8ikrRzf0h8gDjWxQ8XrbOwkd9J+QbmPHHl3Na
zSXxqdImqmJKxNKtGDvs3vkWij+Zj/SbaBI4wP+1ZfpuUPODuPvtWmuzGnEyP3YoO6U+f5em16CO
iCFattt+DhZ6t2bWOssuI/zjvItFVfX1/gTCOtv/2oTRrZ6aCQPCPpuiyIyz75bG1MiiBe2fOi4P
k53TlZZSr5PnU/v1Q1UT/QLaTEU+GsgLUfRIkjDrjbZm5fkXBCch9UUCv3jcXxWunNAv6DGEYxtF
Fs2g8SJ1f3iBoG7M8UTvcd7H8HQbxsnD3v6zN9oa/RaM4GE/XTHmXQvfMArpQF5tjXNPS5S7lbmO
D2zJU6OnZu/XQTpNA2lGZkV2tDXeCiw/W29sRpaDYb4iFnNYg0uVXHLszQbsxeo48MgWUWpFMkKG
BupZ0CI6peYp2xxkMIyi7+sKuR0RUVAgM3fYCCjCh0DMo9hriKbgcrIcdR7PLai2cdfq48FHUE1O
qOjl17mG30PZHVu9eoFm5BB1eXjEQWTpFEDaYC6FGoOAfaOFgjZ09F9pOvWAMKTR1LrbSD0L9ZJr
5N1HI5hLxOd6rvslxtXcJPKNUyufisKLeO2yA/ysj5FtQ+qh8B+p6KJHSxJ0WsrVtAFgPWKd9UzG
JcYCoHDZ9PDDK+bZsqil+ZtOVlhpG/Px82jFj0dxFvEHMYhMNRhFIAVkoCv/dhDbSZuSCihVZaKJ
yHz6AxK3shbXIDgI1hOlKMTBIJ3+iKcW8wRLRe9PZOgp3a5O6w5aM1ZcYjyhwMVVc6fAlFya6suf
bgO68cA+KZuAHd+YoXUSrp2KIljmsGmlJ67rAlVJusVS4P+8+iNS/hnDuwtzf2AwcgrV2NNDxOBw
j7RigMiH2lel5+/+gC9yzlt6sLauPmZtuZ9b3iblpc6JOCfowJLGZEd8Fnly1vD9MF8m+8vcHcX9
IIic98omcmrESSpcaWCIcGzmfC5QQbh9oiGYAiD5SrfE/s4luC7KRoRseC+mi7UO4gXOGt79cbnC
cHFXEOkV73XAquxm/Kh7HB1x9k5BWB9ZwstpNTj/uibo7fhfTt22qjUSPYG8jnnxW2zGv9zdXdIC
aQd2XXPsCi8BR0DSGWYHMA2xFJ9Q2xhcjhzaG08bpCchXULGJTGtclrOmtRWBHRtGrpMXFI6tvs0
5bBpUxI5GPR6FOGBoKW6JMy0HGKH8mtvFM5ZRJfpiEGchtjlJiFF+OWu7W/T3Esn+tLv6NHaAKaO
CA0Z0mevGMi3wwFbksEiqCw1FR0mjrPOQ8SRx6GIKB75Xe6ztzkmA4Dw8yJyku49M9nu+L6mTKMU
LJ2Y+WH5CxdOfNB9n4oCGxrsZtvQLcDgkyWV723DJQjeylC7J8VCEiQllzwnURhHPZLSTwwd3Axj
L74LUKDSNWVflFOkzaNg2F44TKbG/yyKow5atzLk3GRtITK/RVRLgGujzQENKO8vqCjj81oBkd6j
skKQpH0jsxynpVakJkPf9ztfwX1MlMuHtZ/hqOq2TnW7d66Nr1o6tHfIIreEUCXr/VoLaBDVIOuN
JYF8JXJM4yL3jtkHVDCDxGqdNyIrbvgenuMFc5pr2w5DlYqLMVdS+4ZkolbpleDiMlstrw00zWTY
PUZiRZNPU42Zty1ivm56AUkSkNyL9UHR6tMca1Qc+moc4ZVIt0fUvxQm0hndYS8nI6fpPpa+2G+Z
fyC3MECf89vF9PuQtFVNvy9XqnuRBLLdq8GHQg4Y5xNRrRj3jLR235vlPkcAJ0SjzLAxmCfydheP
nnZxUtqaD4X1XKmkEN++8bDwkiLxFoVOICjfKL7P1kcjYHs9U9AiAftb1K8A3kO2BNaV8r5OJ2S1
uCgHPTAVKgPBreD1qE9Y7TRv1lIM5NaA26jGynjqGHwWln4wQi9DB8iEqi6UQ3VJvb+0i2kpj1pa
Kxg6wiyLtv0RP4KbFTVoslj1w8yjJg0wEqoc45+M70IzaysmTCguo+ZX7Gg1+hzyjvw2GN4NpeDr
WfRK1nkbfHpChkc4kl6LaRHxJYfyXwD/iB7JMIikghPv72BJuzmKZjD26o+leLyKlGJZ2XLqnQ2p
6T8sgoqsmYueUEcz3jdOiVtXhlSelRSRlOpW9PxDNzGpjsK2129aB9ggtCHjTRCqhTxYgAxjVhWW
8r0eFwRKEES+34bbRiA17G7kZKNU8eF2x1j3P5Ze8AHfp1ETV/05clkHvCNkYnPYMjwkKiEcx5dC
ibYu+XrFMoAiv2Hp0isPHlhYIRFH1OdQEdMOlAOSn8deidaMOfP08m4XlPqIuN+CgosszSyh5gD5
kr1J4YqLKDf2DYggEwdZZypwdkHniiv6wfc73zSgUAUKpWa3qL6oPFBT4WqNqGCagkd80y4635z4
bH5BV2qyhSQLNGB3HSS4RIfl/ltdlzbj9v7/Hy34sn/HZyJsNhZlpSimSZCMegxYmoshZZdHlkMG
zsZVb285nhW81XRtygX7xyOZhvTSdWyuqUrygXZ+j7ea+IEJS3WHWd8rMwmX8aYNBDmGmlLl3OfR
1QVTheObOAFMEFVJUXmIbCW+Z2hR2YiEDMcyLG2mALnmiKDxcUZewoikpSfDK1NuIpga24EiRqig
nvsM6zz3anLtzQ24SGvngg90cOwuqYUzwODs1JXO/UmKgyQNnHjFP6Q9FAqPLyqRobRDBeSPuJ1f
dQgAjaaLSomgAW5u+HQ7YlDbfXZmEN3jqoyk/ZA9c4umby42eNGvlwWUMcEJHj4V4jF1ZANKcEQt
2Ah36JoriVzBIukipoBNvmQ9iTTWFJiDf5ygo2QPNxwF/ets/kXk97ww7xhZEngGk2V6HWKmpQVT
UViLjh8Ndr62YQfYkXtH5HNl8hQXsjpdUdjqdciSJoFbeZo6tyGRnf6Kgi04PICkjYcFSawgyho6
YAyZ8DePhlookH5CMXMnOHKXaZ9PDvKGfMelz5QmLfYnK0eEn+WC9lG2o0ds1SzsYU7ykquzSfN4
4FKsHIRVOqAOUWp4dSZSS7nonBeKxy0S1Efa1KG4PXcQ3o2M6a+WHKleVmf64nixYZ1bCmEA7Lb/
U22k09GR14L2O0/dgfrXvTMAQ5x5SuN790HviOS828uP5YSiLoFzrl/gRImHEzesnXLqpJkxYikb
HIiaWVqAqaV++3ealRoqw5rk4LheDxL15yJxDCX9+mnVlIlNp10RFArS/Gvvb/mLqHOjQCEjdXwc
+nIY4rJTwimFGWg/UeY0q2RybR8EL6/AAmDNptKs0BwVP5BSBIEEUfZZb9oh2ZVT/3vyzoHhb4cJ
UU2nGvK8Ze14/BO9E6DzU3MJ9V6QimXrTLbahfLpThnmtAONf3WtVxKii+H8c4NeiBmD5t098/06
/3AlStUMharR9vXb2ysVTinmPBG04o214LAQhi5chNznwMBZs2xnqNVahFn7kUI/176+cVJLMjL+
mQ+pMZqCvNJIdCFYa0Up80lmzy1Kvx3S2qVHIC+smtPckHBTtymzJtMqvgoutLblehTkr9VDxWTW
2FzJSFe6i6ud1Ks4MbDMBYp9BAw+e0rA9V+RGYvnVaDm1tbRCZRTS7LWsvA10MfpcsXPI1uPNS1S
otlDdvn6lkkwXU0PjVrpDO/fsGB+oRA3zu60I8rUNaPc8Y3/x4AKeHgGP+55KWXa0Ijps/bQtMgU
xRcD6leAr/ej7TbjIK/lIVfcncD/SJCdYKaG7zb8BnakKPWLDYCpCGGO/2cW9jv5WgcDeSybO0qa
tQLq8TUNiSzPR2QokXhE72s3bwhbijxUMDv9eMLltm8VUeeyZRs3v5W8SlsIXxMANc2R80ILp+4V
VwMl66CWGKk+iRmYMA1qC5jmwQfTnut2YI3ZcGYuqyHprazNRr4muT6Tb+HwFb2Odpu2AFe8WLem
IFfPmEXIVHRqMlmMPZaqDuchIBo9Qip134y1sPqqijHbS8QeM8bsKJDPZLl0/LObaokfAhn3bIjC
KXEOZZyLVzWDyXOTG4/S28UX/IymQkQtrchAa4MAGvkG4hVwpnkJ4Ws6uB7v1QUPuwcRbXw+HPE0
O9oZUEX0GhbdvsKCeW8Gh85U14ql5C9spwH156xgscVM0rLpNjiUCvXo8py86o628QV9hfU7dPRB
tPo2obolMpWJsKuMxYSGHH7ey2b7lhvoERtMRtGBpt0J/nzwtdKcgd1f940UsCUeQkBXk0FH6Qbt
kbtV+5kyKK15FqScqnQU5dPkPv2JPUjj+zSiwHiTZ/mTH6luIC8MwdGVEacLPxUJTjZ3lCJF79tH
w9bNbUxMSxTrKwIhSImdHcQKqsrmRNJWKINeyhgmzcqM7zFjXS8aik9pFDk8bk18lzKfOpwxHwSt
6iABG35XFbVpAcbQ4mI76mEtQaIOp6uRvjrtLDZPj5eYnHF1j58hn6xdKyXWCjymf+8eoGshU3t7
wa51CKUWqr5xMZEwhcfCfdW6PTURUBikmR/VvHR0ArJ8XK/Xucy1nj3jXrA/GqKKVliR68CC1fEA
ViTBVKqwXg009AnLhTkUFD3xzjBdmGfybm9C0vqAkxtHmms2laiLoc9E4+FLkf6OK86TFuUyI+is
+7XSVFevBRiJrGBOsayAqvOeKg3wcBaIzL88HJkA/Ls+j2tt6PthTmzeTuQTeEgHhqVwb88eRBwy
xNBZLfgARUBmMQt5Wt2xCAAkYwFNMyUFLopZtSnEWTWGVVxxT9IVINFX3S+wDJAjpc5e6nsoTgTh
sC2DW0Uvg+WSgvwJ+cStLhYuMOQa54LQQQzlAbE8wIhFzc2Aq2ehqBTaJCPUwaH/NoKC4V8cFORS
DEOpSUJzEmAQOOvp8TKFj6iZ36GWuhLetIenFZiRh/KPjkDofO4stPeIruF1vtEk7dkBPr7N3Ew4
9zsJx7JQqYOSzmSUYemQpMwFOsQwN8mTGEqYS0MVEWuJYqKgO3Ge92Aaqq3BTcHS6uX4S8SgLmlp
arHKzh3zM9l4sXwOdUqjZKMMz/jOYjt2ySTeVRdM3J90nE11KmmQGKgSLT+7tD2mkev3ivvaYlJk
Tffn+JuSzEGY3/py8MobWelNMZNYHZa8jN5yADpR2WuLHi13Rtg1tkqr5XGx7B/HW8wVrGAm5v2O
iACHKGAuSs6L+MA3e7QirsLdi9hbZzXFmQgxmiwVuHVJ1va29Tm7KOrU6u6QdogzR2wRaKkJRlU0
dmXY7YXpY7qiJ+3BBSHaKAQpXIotqZXJm9PF/cdX0BBY6Nru5PjxZ67TinIAnzENgi7IsPRuJ+cr
tMZQFE5UVKT/tGhb3/xcS4nOD42zB9lizjxeGp7YASRA7CZLldvs910MyEbo+siwQnZk5hRW+Gnq
j/iUgRgSylJE6WjpkPsYar/SSBtBAZVydm0uBAKuGijmhYN0ilz4wI/TiEIRJ1eSj8nka4Ycbkjj
ZFj7FS08fjE51DQDsS7U5Uf7J1Tz9Vx40prxxPQ1j3mnQivgXwCW4PAud1Ka24Nzar94wOz1BNq8
eiV1c8ZNoJJc9At4QeiKj3ZWr7/xpojGAaUMxYsJ3j193/SFLclEpJWwBxJQUKNWh0fDkryDvQZc
ByWZr8jG8dw6ykSgR/RbZvc9GBvfj/fqhOnw4DADOxBxImBdHjAS+Fe27kYXI854hIHf0pWKZtQf
tb5tqHn0gS2tkXq95AIBp/cQs+LYqjWgSA9Z8hB6AYh78RxhzL01RkmyFqRkbI6K42LmVoAoLRXH
i/23lnkiUir/vbO/ujR5CXanKCWD0IdSldXreGXBPE5R9p3pFeBe4FrXsQE8QqU3m4356LqGG+FC
eknB+1F2Bmsj1TDPR9UVzt6sw8eA/4RLxXM3xsZLIO0DzddC6UrrKeuU24z2tU/ArEESNhULA8EU
sA1Pq/j0ef3IJk4XzoMF/EQ/5y/JZj5Io+PADT+6zdz8vkAC9g5G8P6VjOuNb51h1wMTVb6cpXZP
3AfqsTcJTHhOL6Z9gPJp0MoudRiWprbpQwaeEutrmMZtWGdg6czpwfkBOBLwUr6717O/6gH8jyDg
/z+ibpDaGVhujYb8xv3x4ht+Pm92vjVxKK9hmGqeCBFiXa7WDBIOpax/iT8K8y5Ae3jrvB/w9zne
VjY4asxAxbpImv8+gEk1rRM+aeyQlcadZc04JCGCv6wN4q+Bkc1gIYDR5gk+ChMVj7bahZ9dEGCq
HWDRJEcg7kdE8f7sOGR1KOojmoDmf/ZKGJdK2EojdJnpQDfRoFMyW0225cXqqYao8XI5NrLMph0z
8CQx2rJyxJUAw4FKdLJzkze8lhjyh1SwSFs5q5nkxbbPsPM5BwaD3bHuvzgv2+6ua8Hld736/eD2
C3Py1ei1d3NQIsM7zad53GmQKHkl6Gdnn5YOqXBrF4G3nK8HK/Zvy/NO4xNunHhdDGi/FU0UlHH2
IUXcdEON7eUgKvPSbiL5jB0/aWFZns0Y0RNEQkRyhCbRtbTBcV/3BdStrC9FbMSm0U8y7g7BV7qi
1vL3nKZuX4QxG5iqEmKieNZ3ZTjaih1eezKMgCNdqVzjTWg0AuvT43hqvQcmvj92cfJ6SNq3JRp7
bLSA3Cq3HyYocQSX57sgaar3CdArQywnWGdxQ2ShDeDzOif3aaE+iYyLRbhKsI2YSzICZuPrQG6t
4ot5jyrkZNWFuM7JEBI1pV1UmKe9Arh8zcIfBs50wAJrDJkLoIlBkYSUSPRcTabAbhbi92rvENYS
mBj/phes1eXAMK0nhq1A+UcxbNX6fdvPhNwtO5y2ApqzO4mzjQoxqBAnY5dMVfB1Zxu9vDL4ZcnO
ApKLQQ+mL+31DP6mqZPvH/ZWPcRXbTVYqippO0jYCQBZJMrKpPxLgQZbt1ExzNVYNwcQb2TI75nQ
slGvl0TDR5gItBZhpLpvtfvR/JGtPjZrkZpSatOi+uGPYsNGC/D/3HBEhSTBIOxrINBTGbjxFt2C
LHoadyyrQxB2zyLVBxGT4NpNCXzQri3Ay+ixLvyIM64pz4wAzvWvuq5WccX9wLdJyTHr7W+f7OvL
iJ7I/n/l34Rv1I9KmyPI8Y4wRHTMxptwpUbXKOq6HndDAKk2wTlhEtwRTA8wJ+kBVfxPJ0tQXly0
WujqQhOY1gsYcfL2ijM48tf6827w190SH0pvtoXh3VsLbWenVmYLRpy9vtWZS0mFHjQzcOFZz/U1
2qSUWbL7GDOOM6D9Mbbc3d46yROBG7pF2JwdvO8U8EUYL/YvgcNdaBWpRvXXP3e2vq0CwJHSK1R8
yPO6zBowXtbRaGSKK6dgn5oRDBdYHMiMiSvOxn2PWz5swk9vcJkUtYv6jJRdxTChB/T4ExdPgu6R
WRa8jyYnVQUdekA2zn6Z9/YcabqdpsZH8A3XadO/LW8PZAReqEeU0TipxF7Zlb7UD112WmzxgTHp
0sDTkCjpmlljLnlbPEKSfpcDNl6RvR38GpixIpyTKAl0h+yINM+OdNcDl9dACLnHX/67AyDPjr3b
6NYLMPnhGmMRvtwneyndKY0ZEzzLYWHhPthCh04Rzj2n+QhuelFkNnPdm4NIg3wIV9eHUHDhGkKJ
HAComoCtci5KpFV3fd7g4JMZh+0XCIMgEyQ8c583aRu23wLwz7YVVBPdABx84Ruu/McqiUdPBVLe
9j6xltC/dMjxU4F4wuHiKBZzLZ9WiryeYU2MPlsc5V+XkhniztaicjmlkGRrLffJi9HTHJAEXSuq
hZBfEWmrQL0lP8iTzFHHUFeXYIvKE2vnsJR1t5BzHf6ZES6XH3pHYbYR7xpXSn0K3uH8sQeG9GUj
FCXktjHYa7CUzD1yZYLYktVTiaoVnIr5YZKDZhRW7MKpCRpuM7ChcB1bPYTvHd/nuwlxxmOw9PHD
7NGQg0Bn8l7CTudOdIt02jyPK6ygwpGU+M2+RH2NgWChCZLEpu9m7tMmdmhKW91Z1ePKyXeIhH6U
Ie4HZhtRhQebVqMubE86rkq1xj43gsXJYzfcDEUtdk9CjUZi4KNtP5SaOk+wX1iSsxazKO2miAKZ
9zC+EarXNyCyavwO2FZ2bqCJcyWgRUT7a4fFvLuj7oQOw9TfQj/MTMUoetJ4QEcMdaxIY7h8dciY
pSaCseVBB77HaeSu0ZpyqYlSepEKz+3horcG2mCey+7dpv2HRHaQxxc/79Stczvkf2z1EMfIOrTv
ITWkTVKP9bvyJ20cOChsxJoP/dtq41y1tzJmxK8ANjQJnR7YNuH680mxhynERwxyxbKSWm+CGyrl
KC5H/MDt6PnGyXc1OMkOoNxBuMcNrLFJRwOs566FxyxPBBwBZKz9pCRmHbYzqguPcgyDtnc1VXno
IaADgUZ5WbweeoWYRSnH4ZdWgDrqkHkp26P+8/B27x7MH7nRSzFwYQI/dBus/ZD7e4AVs2EhD+28
H/05/osi1Pfb2xns1tDfCS3C0iTJg6pmSPVo49mcNrNjxFj871GLh2qBKm+FSUT5/96BC+gUPBx+
p+TEsZ7VQ62M9LNrWEBfmWj2M02FFtWqCVkpZXiclCMKFbRf/whsnYkYZnqvHrV3Jw4V7VOJ5q4w
NTiJRRKcEyhfmZpaIcc6YIaRrp3CZshV+MoewWtCrkQfxZnJinFy9OOqQBNd/96tBiUJufXlb5O5
mHDxmdM83QRsfT806CiSovBtrv3jsiJ37jFFU/TuT8UTHzqJbA5ruUa5YRY/QghEOdw3cQ2bI2G1
Uh8hOxEyg/gusnZEcA8ExPn9D1x9IYOPMexOMZr6s1nK6sk10+gmVHV5G7arCwDc37UCyJAz1HV8
YT3jPSwSgXpm0vFfbSqt2S3Zco/sDh0sTCXtSH7/LSXLA5M/FKucmwXrjuaDEnmDN268MWX/30k0
NB7smsq0hImaqBWej8yyLeBWhLt44Ah0oOqhZF/+RhfWOnRPluXfsCjErfsHZ7P5krdaNGaxyHZg
YS2DEvkcGD5EOyxK6waOqjrlocYuHtCCzEZnseeAq1p4na2kEBr1XKZPxHdnl8GL6smI4CQHE9Ie
8QeEnmRdsMyph6XVwlOiAloWnfisw/FMzzuEdpU4nW7PZ9fdcdZ/PclPxDgf0UxgcPBCmGO8i/F0
zSUULu2claNtSeMDr8Vvv0Wev8caIfT3P4yQQaCNwZ3UFMrmGMIKHdt9SS2ZCYke81nFv10jDmyw
/nEX+/SO7UZVCnbHEKfhXLMJcDX0pkJfxgGZxYhZUXjyAMTVA5i4OFp+QuxEvskVSxHzJjio9crO
QQIAJNIWwzZ+Ayk2/5+LQAShRYDKBa5ZesMBJ6CcxW+AL2fwBVS2AZxDEdgq3YBo107OA+Dp7xMb
JkQYHVBuQOGmh7/gya84mntEfW5p4/eAgeaJ/xR1lb0/x6Z/JW1foU9yBT5iQLZe5XDbYN2ysp+G
xHsFdwgvdpM6Fou3/Xxoq7O2nEoNwrm7jE7WygRVVtR+bOWw7GYIFjnHGsnllqghKZtb8WQjUEN2
wr47saf+8FGDfm73rGtSdW1d95yj36rhHLlcMfEnFMWReCh8JbIHRJCMlmCdRpDuforB9rCfN0f3
LXElhJHZvVNu+PYs1+OLnS4JwHJVkm7sC6ZSD9S+NncPZ1T+ADbzBZ+evNIl+zPuMSfgkICX1iPZ
Jk7k9Yb9YmyqF8gCTr3u+MjEihRSA15tWH2gyDTRDPUBA076EAaE+LrPuJ4eyFTT5eKTFkQ0JQI4
xE95MLfs9P8a/cziEKxbcl0pXnABbtq1L1Ban9Y5rgdL8nTXbR/u9Se5i/aS3LVdEr+JAj5yCsXk
7VT0zOsgnBOr0+hPwx9RqY5AhFbc0SPdeQYRbA/RDgzltz+Uop8Iw/DKLNSzIxHNXe+5gArYZuy+
gAVcKIwkFebK2rBg5+FleiVlaj17ZqI0WaaMX/fbGHMHYFAY5qAywCwKZiK7phfQsbTMGt9DgXhM
CNEIn78hTvmCe90eEgedIC+3j6rABJDOhd4OMHjkIiq1wdURGvNAxJU5ovPTgWPILHGdBA2jC0Xo
2TlLxBmeqi105x8deCpC6ncdhgz2XBggcqwZXgucTp4lzXUBbyBmxfAg3zl78B6ZMeB0mtSRy8cY
9c5GrwJWmUfmzKg7PX8LKh/P6YkJVoA+ytdlmx3Tk5nBXiBTmCZOv08lBMlI9HwlduRUs92THNH3
vlFSQv7zT5iPr5FQcmi2tKNegfHtFYaZ79mwlicsHxCMAaNXE/sIUnrGBMi98kRTkFekhxr7yq1h
sW0vJt3eDHk8EIu5rmTjaXIEReYZZU7VrwDa3gQbWpt7rhdjMxe5tuhZ7qUzjJDxFakyHAN8Wq5f
/FvtEkTWJEtE6zi7mm16NGJ/Rqk62TCTAWT/4DU+MjVoroEimgRfV57KqJnffFe+dnMpih+IBRYv
PKU8AL3ZL1mUtIhnmKWliyzlt6eM7R7+tWJNro+4UH81Btayg6jMy7Lqipp1kTxCp/QzW8hQiFw+
9sX8tu7P5kDnV3mDAvL1LV/LYKAHyPUkksLEjWEtvHXQ8beKMjP4ma6/OtYZrB4GA3hDxLdEfx5j
nPUkpsp2iWcUbJ+dRyIPGIteYqPi6x8N/PRCevYNYsnx6gccV09LEWik/fU0NNr3i9n26bD9X1+s
amD2xuqoOQVw4gFcEyN955gYwEqj3cogdb2EeplwJcQqfVhHJ8pxF4a7kVx8NEaNg9tiSJbclwci
kwbPG1MnVQAfBYMkuCJG+5pm9kx4c2vkbdt6vapBh9Aj4MQ+O4aZ8G/vTNdfBzF41qwaJnpraND5
d7wmoDB7xvCJsdEreCZdKys8FqgM6pMi3iBSyLtLHOqACZjByq8x7MSW/4RvL6njS0NQKWZzWIBo
eC5Q2urhE4FnXWt05Ce46cCYHEbXoK+CdzQRqrq2zxIwhcaZmzUzEOOf2l+cZtNcJXKfUMKSpheg
hdzdH2ya1EME/xOn+LSKGag/23nFwDBATsoe8fUgGfV5/4eCuAD609SYFUEhDFCZJe25lJemAxba
7lOEDHSqzZJteVxYDBvOZbGeyOivCCKn8FLe4p5QwoaazQCTNEKUHeDTMp/32NW/qCC7i1MFsDRA
BOcCZoacQmyo1n8Elvmc7qBbzn2lTJb3mIQh2hFUs9/n+MSpcfOCrmOK70XT+LhEtSRxM+gc5Vdf
eQGBLNywAE0rKJj+uKade4tiG1PAWKyh7z5pPvTWT4BmFUWonE/M9PQQwkDKTthFeduaLgH9iiwa
InLIYHqjXa/O6rhfUqDCTMLRg9r/Duz+Qg3onT8SxM5Hr/e6SEKUzrqytPnR4ynkjcROOKOv6HzA
ZC152JknN2xrWYewIBF5JpwCaUEqhugDg8F1IoMiJ14w9Y4kQxtPJA7Xk53ITBj19+miqTyMokG+
kg+JSEOZzKB5dRKmFcGeKL+sIfsw2/86LB11Zg5grfVhvA+4Wjz49eSY/ZS7QBjSaFTJF+6nd/Wa
HdvBbKP1YUfkO/pf1RAHGlZNJcj394P4C3sjzWM+Bex1zyfiE3NL0MfTFDHSsdDlx1oQwAy5FkKB
f8FXIeiTjgdQEj4u57sjN0Xqn1sOqYMaF+4/OPreF2mG2trdOD4ftzICHCMy2w90ioGGLoAJTJuq
11hATo5Gzi0s4a6GGWXbqH4/T3BHDwJQLctK4GVk7czCDJ+OvcWlRBRuWgtuEpZwCIuYoGgI0+cM
6ABi138+vsO6CdFfANMZSaepO9rnHx6OsH4cV7Zz7o01B0GomexCIBZKpDdOuzL4DfMnAWMw6uC7
oE51RoQicBVQ5/6azypr1229KbWRO9s0duWLn0Md2Bq1CH+aJ3gRoByOUwydP7iHos7jM4G4joJh
lCfJC8pRp987mGbySdaWrzt3DsuY69Zq+1nfRys5S01D2iVBu+diAyGgO6aVTBeye9VsKwFp9BRt
0Ola34WeDggRjXPaLfYNI3t+Y/XWZdYEPwUgEHB0kB6N5okLqIUNFSE9bR24rFSyZ/7/IeEPPGBr
laqUZ/LUXyLQfmiFlfq4rkXSgoFiXtG00idVhJ6WXnhrRi0iJyTsDNB3bEhHgEIR/qnlXjib/ScP
3bgb6E4TDfPi2BWrsS7x927a8ujU9V7HxTJw4lw7bILygrFGWeW7DJr1SNOX8zDPrQFnKSe3tT5c
gJIMVMlORcUz+BdVAfgzuC/iZbQhF4lDH6NQj7RPgGbOtYW2M0mb/upSUNwBJ7+3Qmo7Yb16SNrd
rn0FV+1vPNncz6WhkKh2cTSKwALfB2HovcYRkWGH9z0lMlQPGYeHGsk82FYnrLEBL64dBRuT6U/8
dK1D5w2DYwVTVI70T1lVuCAtUgJPLgVcmKzBsRRRyx08REhYQtQFXFpU76jqzhjAF70WzyTDkegO
6xFdq5YXayP527tyhlUraFlYlv5JdJK2F3YPjFMxuQ9O7lCm7FEyAjQLhv+W6aEoxR0EBsYiTgH1
O8fgdk/8h+w+VAEvWVkgfVBdQ4GngiyPKq+WDIV4uQUF2KLlHURaq7u2vDXaZplJBIKsxlG0lV4I
BQqaCPaPQneSF86N1CRoAUrOSAshg+Mzgf6h9uvRmXwuY+n78Y/tSeE6FIzlI/jPb2OmwIcPMvl5
0MvC+gpeDatmPQQv5bUPiDEIm2fsNSdS3AwIyCcLn5ine5LDyho5L8UEhC/swEDgI+UFj6svE7gG
p4xKPJ9Qv+o83A8DdXtiW7wMWM11G+YYsB/joCsBcMy7roweP/PEXC6lOVa74aJddnEc17SuqKJ2
0NyuZEyWPUsLpArzZKKD+mvkjqt42erLXidrTtk0wR3aO/4kJfhzP9VZS0R8aKRbd+meJjQ4Y0tQ
Er95XiYDrm4mwZIPzHFeHteU6VQ/ds3uiDRnPzeXwbww+BenFRqGr7AK6JhylAdfnmuZNm0T5bkq
G1i3KNLPXPwpCA4yC/tH+ZJ2rNXwGQT4hiopJkf73kgST7vI9iywN2OWGEPYYlGp1Dv/j5RtABYR
62mlGFgcGdz9Mq3qSWjjg3ycr8JL0LJa0Xw9IXOR71d95yq1gHv/OwQBzrxE9n1g+O3BbjWYrCxe
fia5SWoGceZIZRcUWlBADsBEvCO+75hGIDzQ7n6x+Db8gMYDWjTkaCq3ITWC/gZ+YM+68X6rSkMX
AJe/B5zYwjV2LnAwlBGJuUaZoIePEp62lYHrHLHmFJHXrdoPvmEVVpljowTyRqgfILtYBCKC6Llm
qz+XGVxzk/dMH7n5NRz4GI8Xxony8jqM44UCN9YlUPlTZwvzGiikLJ0rFaue7pHE+Mm9kMP5zUa7
8CS22ibhUvNPkyPP1SC7CQm9YAbPlT80ziSF6CjezR4lVkPWUytVQ1pKQp6NblqwJCIC7yyu19lY
pCPBfYzWeh/c5ojZUt/xSVT/CTctwIICyIRlAEGp38lhZeLXA6jFJNlo0ISEovHhHHfwYQtkI2p6
wgOUn5ALNQo75/vmh0esXN57ZUh/kOhcqvOmvIayDmoDHLjhN+XFeECAM2MRBinQimRlwo+8ic0W
nsE6oy4orxDb6zKguiDOsiIGO3p5QiNP6CDdTAx3x3+FVXhlz3rZzVtcM1MWmvaVz273XgOYok2p
edKS8tyKdVOyn9AKnR3sTdUbmJ8KjnsVydvBVw4qfO9feXnEGHyBMbXJr3yYUKTqGleowOogK1bu
mIy5miaIRqTA61KeHIc5D6tb9X8UktP/pd+5jEst7nPUD0f3FLYIcNWcOSBMqnMeKDw2eBx5Oo9j
MXty5J4F14asaUMNQMChgEH7UBd2TMLw4VopxBWZSRlsINAG20F4AD3MNauYAM07e/DfHbkYrdDD
pV1gkPZXnYQ/qU0Dnb+uVOZwYFSxNUljvzwSxtjuiQ2xjrwyQRFO45jSenTC4dHEVvu+w8XSJ/TY
ZWa50wCMyQj7WNLtyp4lNWzMhfKd7Gt3zbvy+uTeFEYIrIYgvez/yfPo24YpnE6K1TRRb1aLkZZt
1VPR4MF2QL4ipC8hxAX7m9u2XHCCHccbiOIis8sm493qnUGsQ67kxL8yA9uN5TO+X43f7ewbZhiP
WTBBxk9tSDIE5uJ4zP3Ugvv67KiP+XXd5kNE8DlghaBYfB5U5f5bYcKzOWH77R4iM3sX3GvcfIEb
YVLbp5n1spvsrzKEvbjHTlOg7+d3T7MOBa//sqe5vldL80b7D++gG/rvyMeDAH3u3rH5+gKu+V6x
brbkzleCYETNEp3q88xZWecoOi2Vg2IRTpZWIQHtMH2P9tFkf9288vuFfTasjz+4ryxViXj1S1BT
bpHaHrcqm/P6ovNlBjSDnTKnQd3hmy4IqapEmJEtZLV1L0n7dFIzVEd0a0cOdbwPwyNY/EelxGi2
GAfHXGVxXRsgUX8rOizQWuulHXJVLDH3UsOCo/2cStnK0fboQL8KavRFQ3c8//v5SYUUz4Ch4LmB
pBmR5uLOxybiBLR9k9mHpMx3TnCMJsqAWqncgWqg+9oh2b/FiXXANC61LRfam8hD5RfdI6HJlvSl
i13HX7kdHdDY/bSRj/rRcgR1lu9NqG8Vy3zbmqgc2stxpCMQLyH8MHD0Sp4w2KCXJADRfh9cfcoj
0yRhkzLhffxFxmZ+MdZdtMz9fae+PTTD+9EN/nAuxBEclLpkEkMNk7o7FzoiRC38yc2qeMJe+izL
PUjJ2MNHjqsA+AiyYJojzh/bi0r7y1jSQEqul6iUXdPslNtIVAP8tuSE4K/9bK7vmKIzsLBmepCj
ZkKDPUhhbeVfOpMA1LV7xwalgXlrOIHyCMJttmhK1/IB6rpwsQyRIXqKve8npVqVYZ8v3BluDoDK
m7LzFTcpzWAWzBXoc7fEm8z4M77eIJjlG4AXGtbFrrOmVhH/q9iCJ3ejjffvOAKgh9ua4I+pxFpT
m45IpPFCdQWHKlgxfjsKzboWJTX5xP1k9vIXdqqoYRxkAtoLk5lZJUuICBBHVYKrcR+cQxkq0Ksy
hS6QaTE1CeGcN8PH6s1uC7CTkK5Qt0AKFy90SMYILB8OtpajOUSLia/PRDvtfewBxXyfz/iUH0df
4+32Ai3x8mQ/JDVVaxNbnezAFmxdUnjY/n267JhNF3tm6bx+Tf5rxzUmJUOD7lnjah6QkLv8svog
QUqMiRswqwsAeOkvWzvFjD0nOTofNdVG+s5Hm4tK7iKzn6aS56g7e6IHxpzGG/FZ7HoBywZkfDRL
H2qI8v+Z42zpNj8VHROXC51qojiZmtcAt6CIT0bJifPlM5nAi1LxdyLuZxavCWP9wP/GsBaKJPbR
BOcYxzCdA9HZLvwfYnYwINQAcDxf9BvxrKt6B7zEFlXoCP1bfgVcj2AfLTFluj0TZlJirISuhn1n
P7TlABqhPe3tJQqJPYEFhiFalwG40TX+eCaVrhK74bC7fQ3uaOWaorLsjzQ9fgFbbwwyd68d694F
vDGGqI2gem+mTvfpmGULYpry51//17O6VBX1CpTqm+diVFskaGwYqwxfSwyeoNs0NHncY0ZjMdMK
bfrAD2JnZ31tScTVYF6YVnSjy/p2gGiHR2b5nxUS2Lav4SjzoK4jvzVFICE6UMrDygIBGZIn6PBr
yBtITb9UzsT6QilR7058w6jL/U5l0UKNG+7ROE9CAiUc/P2aF1TyP39DlmyCR9k2rJRSu4vwpog9
hlpUZCa91yVqPj8qjcmzUE5VyWDl9PMB1MD6yTYvD+UULCRFxY2OT2cYeans6lr3vKMQQ1NPlXx+
x/VMojZp1+ShaSpV9fftSaX5E6hxQsxGcjcAkIF7d19kNHhVNgaFIZipLecipVaAqVitTANEO3J8
kulZlYwd0WGoxRzjXepzEXx/wlVWo1Li8k3xwZSnRZX0PvCDdALOiHyRug3N3rtXXGimynb+QgfS
ttn66jWbuI4gRwZUCNgD8CYMhTgWkNAJsoaKgHdsZa0xicMxhqm3flWqFe+9/VHETzvTSy+DhN3F
NkL7pYKfk2z7SM2D+sdN1nLDRCNui7hSuW7nlPJyUXtGADIsE6Cbo5TkE+U9/vt1poEM1o4Iej0n
rlHvXRh13lcEVwpLS62gXqGgCPJLOsxPhYcwVC+EfCUxsUvHCaEwPOV4L5zWvH4y19mVdDRoOpdQ
0e5CbkXm+933X2KogjEpEABlpEcSkgBJ7R1pj2iiis/wf/Brb/NjBpb2kt4LY/Pbcm3mxRS2CvAQ
DIX+6Jy5k5opU9JokAGMekVNgABrD7o9K1P7FYHyQjvbPNjKMnEDozQDfgmWft36g4kaHUzjH5CV
7f5VjpwiaAolf6Am6tjjf93g7R3BUr8enbPvi4rW2U+VAPjJvDwrBd1ZRtmkKo8NV4KmQLi10bKd
EVrR9WSF9aZdQEv6yL7cUdSRLYSxh93hVoIWEv2w26OGLvC7tPXxtj2Xxfd+7RoTO28Ooa7Sy7pn
kFGYrhfrwaM07r6YdeYE6q3NtL2mGFyjRb4mSKB2sZbRBBZPadKNsV3udkewtOqK112C9iUl1YMJ
wszepCzXy89zO+18t7G/HlYMVA/Awe7psc+yakFvuD/FzYOoL2SZQ9RKf4eEPKS2boivDAwIPb4g
q1miBip+TyKDN2EsHz5bLdYcwbJCS8eQ4fOjeTg4xu2uwgyeoISJ5FCIBlaXSbnNN17tF0NNNC3O
OEESFmcuSrG9LUKPjWgKWqX3hgfW8mqI2ozkf1nsBnDmmQRTVBUOr+rhcg1a4pecoORp5bs0oKn3
EtcIVYTetrM6R5lkpnDSoZz4YpAxih7JmUxsgu6ia2HnHtWpgyRShUwwRFrDws91XIURIFVpODbL
gwpVS0okehJFk36jnoWn2xPbuFUBLwFA+oECS6/wXi3xkELUnVWOjfVs92DyHIFSLKtafotUZDR3
fwna8lHrZFHPVQQ5TBF/hrUn0m2eztZ9P2AoCx6mHRg8IW6s9nBG3SzYcqsRGcTd3VfVCbCgPAhM
mm8ocndQSHO1hQ1BYsj/d6c7XLvJHCJgo9oN8U/nXXuSFpT56zTaG7JV9dmmEcdI04xCMvrqYzmN
0zTt10s8FjcXaVrBZIUznLqHGTEj22LtRRQKXQr3nRN1Fbrc1UpgyfjptsXvWH8v7PeRToxVVY6d
Us/DDJdjV81rIp4cFr4q8s/2LHTVDn//Jfb/EtMSzGDuWVxn6KU46o61nE73I/HBTT5rriHsPsse
Uuv/7RlOBEer2mqVhJ1WJFR6TlYDWIHXTXbZOk80YNBS+tAlZzsrK4z4Y5mL/IRItf0UjZ18zm3k
0yy3+NpyqC/G8I8i5V+oQxvH6KGoXmOzLdlYWQ2ogrMED2LDO9121JCKDnX+xdB35WTh8ugypfoj
QDuQZdFuvoM9oyrCUw5EDubrOMX7f2Ngz2+8ZSRWU5kpwKXUMtAmcLssUCKZXj/7zrtxa20xrWSb
+o8US6h+phl4MSSv+FEYT5DcGeEJhaM5uhlgkJ31FjGYH2WhtlpK8Q3f5AYYI0cjPEflIDgpiUzc
NQOfQ1+LyzBAiRMqkmkc3o6wSjBgm20HRrTOSLWH1Bt2lSWsFiyMfzhOpj2JF2d6DQZMGNpwwVUm
9Xo9Hf8lZR+VR5pC7n4BHDalZVi8qchdZcMhQyh3968UqpTGOZfFsDuPgDh+GgwastzII/6nCYCv
w0fngQkz9SHkSY25WMJthPoFRGEo8hwEsQcDMf55QYVndee37JTS7spISJ3lVnU0ia5qpoes1K95
ggjL9RgxfS79oFVPK27+pv4OdjqGpymDrhObiG3Jpys3CZFi31TRaSRt1+VIK7VO9LVjwEUXUrPB
q8QdyNp6NWNIjMvFOGqyzTfJdve3c44PxIr5Qod0MwJGobIyyoJIDgZrjAHFWf5dFUqIYfhZgcmF
Bidt2bVPRmWX2FFMe75eqYlk0/498dYfA5mYy1fhg3JxMvJFl2Pf6SY1+fxMMOteLQ5ohHJgpB0j
d7iPnW17pA/WfGF7/pPYeReeqa9DlIEKprymubqcz0NsCR2e9CJyACEyeJM34ljiv0nSgyI6Csyw
VOd4FdeucGG0k9sVBs5f2N+hAGRK+Wy0ZmJJ6XtU49jo/x5SUXldF5gReQ6q368dReQUC/2Vkqan
4bgC1ghQ9V0EhBkFONwP15RUqhkv1WEvfd0yJK91/OSkIDY5Kx/wz4sPRy/NJTInbf0w/5B81+xK
iPdJRR2MYRtZ2vXg6m16EahAlnIPFO0zkbYoozG1ygS7d4SqYC76LFd7CaR7YWG4CSG5y5awqPP3
x8mS/SFbWufQ/eZZJsblxBuZ1FUU0M7UN/JH4JdcLWn5EVLNpReDFYyd0RjqESvoLRyU3zxEGWUN
1muxYNFga7a43UK5t4zX5/piqz5Lcx5+ZFJKOGdgVSjDYim5afrp4pWi/iQJs9KGMKVFsYkqX99H
bRPen6L1hd4TAqqtk6eFMfyazS1fd7vuPUR6uiX+hCTd0bQzvP3hD8o8tz+C7djE7dSHhArFibnI
zcSQijGIzDsfi7wFuaRHb0cNa1bp0fTLmsNfnXG71j9AIME1yCDgwFxs6I9Q7IBhCW0fyDF6Mc7U
xcw0Gm66yRXnf9XhnTZXqjvENAgpCIySlGDjF/oHimMObS6unFcD5qk+L6nrqmAVGmX4d3U16bKu
7NcV2HBArN6/5jUdYOCMvuPUET6lhtPFqW2ua+2gmwMXhHaDwnGjj6ZJmOU30CaTE9EGt6/qN9im
jXfoVieKntnMNVqXYzyWBIN9/7DMbRVcHeCjFghfQt+8nJolb0cn6q+ltXIYNBlYScDopqvGs7LT
dZF8tQmn6IZx8V5DlD5MH3o7x1btSnr43j6If6p8rNzgGhIrRD3P2PQ/VWMJCl5Cp+F1lsla+M00
gGdAK/DsKcCLEUlnHBhus+qDUABWOBzd/IFuDE4yn+pKXlo5+NgbhZQBAsR0rhXaZqeFUtCETb7o
aWF2YC7hjYF9WxniooD1TSbPQSRKOMcJ8atOSZfvsvoJ1R6hHs0KwQxP9zdYt26E9MeHelmpU6/E
fjcfVEM3bgEdppvYXxGyoJdsRwcRT69OxYh97BvP6XC9du706hlONIwgSyCQGBV3jxwoPjgSCcsh
IklpKZ+/fvDfyS1TcuA//S5Nfngdx7lsL3uO8yIWMLs2Fvngyl03s8wz5BOQqL47l9o1SQuLJe3j
nUgZHGHuPwZ/sJsBWJNFw51uXivqo+f3hPK80Qy1I0gW+aZe2fS435jUlJbZWc6KJQYm3+3nEmYz
CBnZ+bOQ2BHLiKfd06qm71UhZeSgcahMOy2qFI9Wh0R3W7xhE5zwRizM1o6e+8piRTB51beJN9Sd
b1VLfCLbaC5mknYr3InIZSKiHMAYocNeVIz+NnDh1ErdB3UHOXms3kHFl9bEPxhEfUO+QzEUgMPZ
JdboMif0sm7O1q8erkgef8VgvpzAcUKetrTDqfUgogJfhV2iQL45ROT3vTOPuEB+AHEypKzLrd1F
Am+hhln4n+isu92ID1HK/Tzm6kSqoC47VL2vNsdieMHO8of9AZ0rfaGfg1JWmQ+cFRryt7ekmbgq
Rj3PHylb9F3Hrt5Vsa0lQD5rri3idleINXWDaWT3tzEK3dnmW/NOjBVBGfzBjZhspuOJH2EEKR4o
sH6H4Bde7rvE9eMxVS35RDeLh6GjN4dxKmBD+ZqcoWm8YM5Wc6+wa7WzRYSkcwaOUsmhKJJ9QYYE
+L+gs3JPra/2qy7xlh34nW3YEaCpJYIDOEdJhh9GcWLHCLsVnpbz8+eXlDt2Xtgz53WnadrB9nXE
K7QxwccbIUDv8hIJGSFtfo+/lAdGKScQQAq+vkDSSTd5c678vUBn6UuEZXNCn/HO0Qzpqnmp5fKl
sdL6jtgowVcnF/gLh96lV6ZR4Tj95da9zMBdzr8jEwv/Y4IJj+Z7Fzyd3rKqAfwl+LMKup3+dJmU
Hz8SNLtUNM3jYYHrIlfIRjVp++bp1s6Dlq28u6tsG0FDHR0iY3vZU+5aGEoCr/xHvmYkRLqxgL/t
7KIO5qwullQxoqmaaGy6aF/xk/OaZctDZ77uk1DioYUvNp/r52CiK0VUqp0OYz/aMlisuMWWiW/d
hgTVdSyQi21h7MY//66zamh2BF9KvuyZpst5NpXT4aQANAKMWiA1EdaUCQEAzWU5nRoRa3/s5DsL
mCt1k77uL3pAqCdwKItSNqHdqqsYRf3OtNpfCfq+iF3ZN7+kuaQjf6YMjK+jbiBWFZPK+AuMGzVP
DKdvdi/dLIV7u/38ochaN7SvmMPLr232o1BoRnacD45Z7Sk3o0SHI0XrE366HKa82xVLfZybKTiM
54lFppu592UCczLwcHoGkmb8Noy9KJmCxP7WzmDbQUNiA/HETn3dCXcYl7vjs7+3++3OSUA7Qshq
oR0l69aK8/T+uTPFLTsZMtALBkOgyQZMrhTkn8YVM+MDJAnKqk5foiDt2h61+AldC5dGyadWnsEf
uIGjhWzzj4SVPBJLKINSwwVvLPTGZpONjioE5KdTJnjJC5fmVajvtBXvFzHW11CGXJW1FNbxfsgf
s8p4ExVq8ccdSF5CQmIdiT8yxD/uWJXmAgqhcniBLAa0Skj2fqEz6okf8b4pjWxtRVnu7/nvXOGR
zLFpgIm5WH9UJvDm/dHGeSuIODRhtUckr0WYhyW5k0dPS1fNwkTGOkOsVCsEDcmiHdDm8KHeSSlj
xhj//7KwNxEp0c6C3zPPs//FgTIDnznd88C1kkQOCu1TYM57xggAgb1mx4/pAxKH12yYDB1E0KOo
tfNOj6aWk1CXL36umTUfP/Jrt8Wj244bExV05f3yDofqaPgnvhXvBzFPw+IYZz7eF+TBcn8PsefZ
WtQORcVF9z9znvK41Clk8psH4mX4PJElPyNzYsCmy4hPgydSyspG5tI5uWSSN3uSe9VOqWR6P7hx
IfIUXYDmRpODKZeRAlwtcKVABL7i7NFKlsReS9n7J8xLX2mmDJ58W8vLkMKDhIpDsxE3I9r/Rhqg
Xi/7exuynZjifsF/x2C6IRIarUa//RYPTL6yKyp/NSAX9mWTBh2NFcdux6ZpUfPN5sojBGh7HS54
EXVjVvQ23FPUeeve3IBFtdvDm8cOtre6I7xY+YToS18E1gWj4EAkU2IwhLeuAvMQkThMFxykITXa
NrqJKcHXxCaZwgZZPwDev+ZeUFdVmg46TxqPKOy0ht1KH4Uk8Wyvl9sC+7EfA7MIYM3ef+t68FBJ
l8BQukuo0+G2haitke8kAPI7ID9cmfJGWIpvZCy8IB3OVuEIGu3yuFWMCDjQSy3/PZy2X7fdhRzb
4NLA1HMhyoHSawfhfk/fLlEJh9DGxvnJWghKab68ChB3O4NhwF627qUccxuaMlOPrFnNsEE/vosm
zlSPnogI1//qUKiMgvFx67QH4yUcGRokH1rPXrlQ7eb1iq2J8JFLOfe47f+rALxUxfiB3J9U3RiH
DOvNvdfCSAt5QXQMyj/ESByyMPnXNLmSdBcihfLibL9Nw/drLN3umxGHDAiocuptqRVuhVvnvzfb
49TR5cG+UbhDzBu9F4maKi+NfZFptKqlKDtuIohLoUK5s8x1aqun9lwlH1DhVgJ+wLmR3JjrcRlo
OaIuwwfroDqiK45tYiT1hBeYkH1qLcX8x2FeGYkq5vJLrjP87du/Kr7TS4GuAYGTKosdMPSwMARM
T2btHWtOGvxthHoJc4Lym/EWbkWVR2dOF0xfPSqLj5RSnO2/dvcv8OQnYRvKWjH/AmGphKs1zwFJ
+bOlTEyxY3sDgrdDnNKCWXak8dbKl9gucATWcGuWiJUfELkO1IJzJv37GWvf+kUAz2DDOI1BhH/A
HUx7XD7CnHgRd6mr5tNeNQW3u1cZxH5LVpWajdphrBJYL3vQ6wBikS58uMCBPI18wMKn4YnHrsqi
d7MRaHUSZi0EZx+opVav24ehRFGqveGL4zBw7tv4IYwp/1Su3NgD43fGy8tyGku5/vNzzcFf6rwg
NOxcq9/h69rPfhO1V2lpHjQjjMwSg76GvcTWJ4WbCTr6Dyi0pJJjUS4O7L+D2GRQXJfAmdlswxTW
Kzga60BxkTECWDppECZYdFXBEthhU5ZSmoeIj+nYFPkyqDBJECKx5n0nrVxlJSsfK0mp5tegbs/U
abfMzsByQbHNUEe77FG9d4BjvnXZN8fKGMg4YPAcDdDWS7ifCyOAyVH6Uk7Angh3jhjwYnngAEw0
t/hwUyMAvVOgSIX020OjiwoRetZQOMLDlbSv3SbaGgjpyiy+pMjYW8WOf8ELpNgyOza4+wPbOSv5
gneQ4eIyvH2EKItBcFWa08zcxl4bdg7PURMMoPewlWbUwln6IhxfzIxCA8vOuCxPmoWpSHhcvqq6
fCu2o79LfPUczZYMZrsFlx9AAASZnZPnnwXsYIrrKmoHHzFTuMYJxxOKc4kZRN3OyS6hKbPV11hl
IGsqApg7kl36pw/1B5p1rocd55WA8CVfzXCbhCLpbLascrENdTfi4zZbVLWLIc4NhvwUxXvxNp5O
A04TZ84PcPoVxnsJQ3+0TBp5fZf4c8mNaRA6ooPoP3kHAASBRmN2pk7KACzA8PvBidWS/59vHMhA
+4PafdD5583oMKETnkavNqiN1C5XZ4yY0XoRWHY4GgV8S1FkiAIppHTiH/0M7C0H33VqvV9IBJOq
vHzPlKalPDhLGGZ2eS39G5yWvBEamK2nhKYWuBR6YIzv09mf10djsoUTp5vYju/JdYcvu+ACypvq
pBRA/2pPKlShDtM/vuYfWV8rlwFeuGV0qnzID2mGNKmhrR0G6Av2orzRGBqGGs6KAb5dBgxhF9VJ
+ngZb3mGypkF2oEsryyZOpC7b+XWZ1DeniLVkJpKNFIT7vdLiRqYR2F5caAEo6B1DLKdaSs3ztX2
H8/Dkn4ZiJedn6EmO9zBhC1CYWJcozdZzeT98XvqALjrx3b83MM4Ir6ge9u99gghE3XE3b55gM4i
/Ijw+TJ40E/JcYnREI0JY3AWe0w1aNo0+Ckdd2uG3w5r0R2BEroCa7YKQ7SWjXgmg0d7YkeQEaoe
cxuIbMGJTiQ516Dm3N5nCP2Q3czUe6PfSAX1faNyS9VGwe1Sz45PjyCR9opNTFzWRDOX7q6n6hs0
cYoUAeIOjvWrcMst/wmj4vv8o7VMGIJBCo/YPbA6/hpnVFK00jpJueZ7SMvWlcHR0JvEq4q46rLW
fO40H8C3AccYHTBhkocTIFCD/LHM73PS8psMg1+zFPlFxWO07a85sfRq+GWr7Yi04tas0+324dkT
gR8Wn/gquFDckDywC15yHvNVSnrv/EvMsBzPAu0zGsGkVdo5VHWkPB5z1ErREwSx4uQMAA1gIPAg
t/ACxxhC/wLNe9kZ5iN0emVp66xvvV7PSb92jNwLStA9Mqbs7vc3ZkERcWwO8td+rq26kwj0z4be
eBt8KzKaIH+4HWzWt316Stt0fXyPbW1uTFV2sc4yXoKvG6DlkMxXzs/m0cyDtuFYUl3S5tzCxIRp
KE6Qh7b/dSPXNXK4iex1ttUMqwPY/7h/WNg9C3ZP6DjtpL8+eG4u0EGlMUiYdf6R1/t7EqEE4NK2
1Qzma2HxAzil7GrnUfynfdnDZM5TuDZYafHrBTLxgwmIgieWNv3c3yfo0zJr2N2RIwlJ5yKb0hd5
1wRFybfHqsbL01V2hOl3P/xdsPQ3j3spUwsFYS92xDuJBdwZmAR+wmBbzFss174KcMyc9m1ADacn
HkpnaUTgIN490uUrzYKpddh3E1UzJP94QIiyzI9fKSdgwLod6gLXmLnNHTp1tSEecjOoMIEapO7J
8zClL+7532D3xzPYLwB7nxq8ASzqx7X7Wkdf9sMNlhmhLNoEyuvyjWvDceT6IEG5/DOL6/YVetMm
6jgulfEnUc3ymmRuKJ8+acIFItmKwMaIJW6ZoLb+s1hy3UFtyCgEuDPnXQdIz41+KtgCosyMWiNB
JLjeP64jPqExdZFTCNFCEnnwDh3Ha/aE1XzS6jWMTPaIMK14nMvoMnoOKk4WgqReTlPap63aC0pQ
ttINxgzcPo8DYH+lXiby1VVP3snyvd161rnUV7M8KZqPMHxgNB7D/j3JizAlv1FEszYCgVaYx89r
lkXThPwRx9OwfgMa0lwM89tKEP+wNBNjyFNzwmIuJ49KumxpK3uSAHw4sFT0WWl12iJt+OG+rxzF
ROI8XP3c5ZJjmJnSmSzHIeFv1NefDY6HhsIEaX3PBzQKj2I6mrlpqtRTkZ65sj7WUvBtYc8UEW3e
lETz7k/o40qqiCRk3QZqXL/ZvCYQKYyKu4qnjF0gd2yNjufecVN7kKxkUM6mdHGcOcwU1FdW2csl
5y1mIGqi90m8I5AtUVrY58b78TGmpAuIlsMvZQnD99Qrte4n0ru2/N1SIc56u8Z0692Yg+6lcowa
MdFRX3pcVr/dMUX7ZvcdwW0mjYGaObWmtKFPEMJP8UuKjQyLc8oN29MMNiyIU28iV/YizZTKk4mt
Ai24Zi7r13sqmlzWUUlRRMim/Mq4W/bHDW9VAcF+WJmelhP3arFGR5PgAfgAu9nELyIfr6McfcU6
a7O0MyNGzUiKj7pWjaYFw/e6w8XvsArxtnH0/5SPnRO6z8qp3BUJU1sLYTT7fuFQPUQdRWrAfEud
pCiuXmnZu3OfjM1avNwbGumTRXvFXF9UvBVDIYf/O4CrvebII1eaAwEzqGM6F0pJYmLVVaHJNcDL
zVN+Qb4ac/AfIskEDzdpovQbXj91RGoicDVRX5lqFOWFBVi0CW6kDxS2klSM9FJSlRWfQ/qwC0b0
huRIhkPhHvr17dUmCv/wwTzuzaod019ahsjGFD62Jw7BuSqiaBxOrcvSZKxrvHT2xhJztfZVSdAM
VsERJv+R6FIX/meJ2gzHctY7ToGFCAqJ/9gDqlGJY6EEdvdkmE/akHTbJ6pJ+aqmmPKDwSYIgtBn
cCOYdwIeRUDlVqXNvzRRxbE3Bf9TZXn1NTjku5WE/uNF9d5/rng2AIqrZR2zILTYl9GQI4dOhbPC
ZoKXr2wULSI7lRriV4fKBqNM+lbIT1Jlkk2PaGTCOKu4xbmJPFTTzlVJ7FesA9VmmNVQsI91lqeI
MGJvcRho4kvZjRY6MYDgh/3m1s+7IopUJlEB6nsqU+/cyVT24zQoJcHEWNC+VFXB3WUUrSJb7uGW
06IYmNbZxBCq91GoooA6ZiP8B4rrcUwlM/UcJWs52jLlu8aIsTt4wE4K8BHB8r24AG8hDjDhuSxA
GXpmijhVRMNy1NUo8QcUzSZqirpVUeyD10lkhGQP4qJ1QV7iJ7PP66UH+2rW9MwnkXKHkb/1lsaE
n9W/nsOZMPBT1Y6sMDwHeccyyR1BG7tlB/6sLEWKl8AIsuy22XvmIl6hCyZ3npBATGkpmxyM3JxH
c5E8pu+2tPAKoCLqI9RzQL7BXbH1/5fjAa7qMSRdroQYuFasSmx9zawDiuWEHRIUOnrkbCKlxFou
/Z9jCSEHw7dCfdpgwcdC0jC6RU9MpwvfvotboRI+CzXvyxhcZjI8WzDQ0CX+7RhXjmxB3NTf67QR
1ucntA6P8tBNvFmNOxszp1ncoaa287/S6LRBSmt/vn8EuNvfsqrfmAVBOVLvCLYTviYXfVBqB9P9
6IE+eyeE0D0UlNkrDDjXkCwOuCHjlzSrIrEQiNIfWEPBqhRMRnZOqtp1COYCOrGGR2qvI9gRiUx+
Mi7koSh0z1NcPo24n14xoquHFdPsi2Ws/TtySqmkk9dCOAl2CYfk5vQfRqxpui+bwvSikuy8WmSs
D08xaPVsObStjINXsB5iWp0Ih1WlW9HPL+aGMM6CIh6/NH3D003p8L/V+Muj0uTO1hMuc9kVSDIT
Tk5QxwKh7iF9vcR05kvmcLRaiHGuEKeosWa+z6IsMzye8+bp3X2TVnCfCVxi3wongNcBO04uYi0D
EGKon4mW4Ojwg7xROOQMSsqAq2l12/uQwocSjI6LulV9IJXklaKXDPy1akzDrzRmM9PXBuWeJzUS
+XHGJk9JwAPC4TpBsj9961cdpUvnWVt6Mta7TkjkN9UwgbFJprwI4kXpRA0fWM6Jn/kdfvri0w9g
tSXb5nUIucGwAsF+7x0TJ+mKbR03iQRxSr2kw96+klsfACsZyVZ0STqI3p7R61EkT580KmJeoig8
uWKzoixn0V56JtMa2tTSJEK31V3qQ4acpg/Ga3Y1B7uQ2oToiPyQ1pMH+m3gMLVvclrymCNVmmsd
s/UrfvTZaBMce2GKa7pwCxLCzXd1TMvPxeHVANCM684wi9NTG+blgNg6SkmFn29IXf1dLBi7HeLt
fuS03SncLiYQkAXQp7XLl3BdoUXq514EMSXs+rNktP2cC2i+4MaEwfClMYBu4VzO96plcaTAbU8w
TtiX3P6ae9jdrZQ1M7xTVAXX8Vyrt84loPfJhUcJ6Tt+cfkBYzrXzhMwc0vs/3Czjolgz08/UAhY
sqJ8c7bSvUxZgoMilOQVvwEyP+Qkh6IMJWYbv7amaNLk8f6L8g77oVH6u/KcCkl4VlK+JGg8bznu
jQr4kTpVOZhmZ2PJsvW54CF6leFaEOELFxC2fk4Le8N0JMgyamyEbW5xDisifNGH381lxNBaUH77
ZtwRoW0pQBoQ/sWnst2BIMN5Np6DlvZvxZpb172tJyvckq41eJNpXrP3hAiXNQyslE6pUmTPtCrJ
GxqJW+ETDwp1QuvwKLG59b159aqEEFk6jO4LVChM1175a3tRQB3hzgAa/OVp8uNwQrsdHN1orFet
z7JSRyuTEa9ERnbINEAp7aspE5KJJoI0MnIYMLwe4iFTWbbHaKpalwtcvacKvDR2GtvuZrDzSwCb
TKo1shC5epUwJRfyM5k7gGg+e8Gmos662UFUrJEGHGKKaOGj6TYIRsBKQRIw7T6SCd542Hr5ORXK
EI2kTLSSYsNfBCIblXa62djJT4HjgAdoaSk/rGFdj0LzQl5OKFsiVh0py13q+PdmLtcpvbmhs7J6
HZry+z7rN3BoKL4nhgT91HmPkGZghJzv+oOBx+kovG4JtZC9C1DhdzDt2E52AfDnp1eRbCenaWYN
U4cwCqzCtdDwbKBHiH5CPI/kAvgthIYUBNq/NQSfSwvCxB7wNMvF4cLlw6u3SSPcsdS8xzqTSHxR
sVZuZ5pl1dmkMofyZOXjwZD4IEiTCn3NHbC8SdE5rAmCamcoYQXBzksda9aLg3jICzCWoNAcrckY
jexEs0Dnm/TPTelpVkznm848aM4sKJa4NJfIvwT5dvWdelrH+G64tjLWsuoOxH0keWSKFVCNFTUc
9D+vzaLiYInm/TqW+dOngNaJTHjNlvf8E6BgNDY7+EQB6qgRDaNphbJQiCZyxpNdpTsmCVmM7qFl
3bf5te76lTz5m5D+06ZyjC/xwwhtrumzLmk5NUqopK13RCb/ugYdNi4beMwWcuNj/jhB0eqhkqwN
ABXsIGHiYDQ3wx06QJ6myDyFdLgMeBxspKS1oWZe+SWzSwNCpy8xXm4RUL51gu0m8HgivWXunJhL
pWfzGo70vnzQpBDoFEtVO48YRyQv74DMpGoT2Q93pLW8B44kALL4XxYc7XSZNC77K0wNFwf+vb0h
Fpx4RpYEeB3YhF3Vhj1hvjIq7iEpVDBEM2ujYe9d2ItsOrkqNrSroN0BSBq82wmYhSIsiqWvkP5q
2lU7kBa0gUmVWQxKSsyrlLniZDJXf4HLOz8wbeHTJmukzIsabuxWT9gBjOzBMDRzN8rbcZlJFC0R
UU23vT7d8E0X8JJYMy0I1mYQu3QmO8cwpcieNiY+3gFGBQNReK3ozcZShkoxMHRWuq4Ff7zI7l0y
+fpL6bpUQvP8KwzpOMgKwLvvNn9sEPmBTBixfQjRcW8VZLgMPA4OI0f6pcrbLzIMnsP8iury4aPg
CrsVFTYXODSD8lklbzM5b8y5DOuVtwP/rxI+kkAaABO6xC6+5ZR66gUYZCgeqOuYwunJdsiLLh50
TzwGp1jX1kAgbof+h5H27FZtqKHU8JZZTafH+6ahc6GEmJxMzWsScgY+JqrkTfeW+FhihIhTmwjr
RwEjnYWW/MYIhkORIb35OiR+mtfBYrGJX8RcMIEa8dMe+XIfTSTJcknf9bIk561mjr+Ir4Ayg07O
Au03Hph2369D/PoirNx0N2qUo5xcWxQOqkPyl8tdWN707zXOGSc/a0YAzJXjEX5/j0I/QQmjhMkL
ecnQFICbA+i0O7fPi+bvir3cXHBT7TtqMEXU+0umDbYllIjl1hux4xVlKEIlUKWjcH6PLo/eFafh
dRxZemOQtsgBfNHND+Or/z1t//8hSp/jHw8KH5h3EehziGqnOUSKFc1DSYpt8Iji68xQh3h2OiWf
zqw86I+JutMx5NNb6gJrGurk9ZjC0xwno1imTxeOSxe/o6/X5ZrHD7/AgdJz+UR7b/MGpZwUJLQj
mq73UKYdTqSfVVtnJefrC+0NDx7svKCVoaVpbAeKrhVLghQrbOy4APXIRsyOflU7T0YXlyl9jigI
bi8LOiRe8KNxvCAmRVMdMgQV1sBV3VuWGoDwbc7ld0WIs2//vd9MpSQ5n/somaRZFIJTMRiYl8xn
JJdo+9hHuEyjFexVTyTcyQBeebA2QAy2TAQgP5YA/Z3QUEoQFyW49SFREs4wa6+n8XYIWm7wPmSX
JQGIp2+0XESXOLoYzdMI0a+BsE3vJ+IxDq5t8tdnqgOTmmhH6qAJua5rGUFsDMqqJpSt7XgtdNlb
u7cUGuckGXuH1g88D7Krfj0/B95dnTn66U2/IqEkdpGLXJtqDgH2xVkgLf6+5UqfPf8xQo84m2qA
UGkXmK8n9m1ti8LUtaQi7q579+F8La7/O3NRch6B/NNEZKIwlPnpM8Yz0K2Yq0yNHvDe4BWck4ZT
V/CHbVIsWQGtojYUQbQ3pBEPUdFiKI+w3mf1GsArGPaswWp2W7zQFbQB+In1c8K2qWXgfdSwBezr
BThGQ0E71Vz+50tCDuh7esqJq1thNG+KUKLiN0XZ3DTKc9mc2KLbNb3wDJ4oqkqtmu7k5UgbMflP
uzdVdEyfMlKb0CDXJ/3MoRhjtjKpZbkJM96ZKCyXhGZGkO6jgyi8Sf4nl6IkEAGhX52qE4usVvjx
QU2fgJRcgxUM88kddoxCM+Sxx4/BnrDI8R+qC8T7V+r+qnQMFYabWPbiMNpPy5hfD9j7emYQ2di3
Y8ZxUazSKB7vI+quhD5sTsjLlgjw4Ve8RG4AESbzg57izfnKOz/Ru9DodDWBoidGwFrAs+L84Ufb
/F+mZN9WeuKEa/B6wtQxeXGbztVVU5fR2V03LcZDrnaA6JVLkK1cUh7oP1M0zT7Fa8Bd+Y+GTRnm
S8cl+9jnu3eLp5JE37hiDNSCAFewbFP/DrsrLiU4lJ/9jlr/Fpyp4wTSAM5N1QVlWLMk7lKITjho
CR2JvjRu9X7tm5gZVESfrHuKdYNG+NJb7F04iURLinPV5cfLzYHp1w/FY+ol7my1LhvrN3sWsXRv
RAWhOmxvAKkLmVWbleiVw6BuIRfe1+rI5Y46PvGiFJEEjmgAJL7DvPD2T9o6xVAYlz5PH0XK9HGQ
o/xDDtvCBnQ2fEL7FGronU97O/VYZbtb05jsAkFTnlUrLWzL3tkV6GgyvfwZsx4UYT9wQZvmBHPO
oInZLd7pQMARj8kc2iVJR1qBUr4jm9UcT2u5xVyckFJoRcpWJnFEbP6rw91FTARIMQUu31Gn/nGM
SUUnsOzhps7i3o20xk7y/FY7xdam+4/INiP5Fy97yOMZGrbat5dqnhvhj+if8Qn5Zl2OKjDMqXqf
8R+B2VtkDiKvKNV8AZgiSJLMSko4xmwObuRlDQwV9UG0D4q9lor4GDK486escIx7Gznmpfni8NtO
s1Vbg8XY4uZ1lV1mHNs6L66MyB+nJXe4I/K+yEiaD6fMsDvkDJ0UJshrnWsBu/TBIxVvxBUPQVR5
qcsOVJkRAnXHBot9bH1sv8hTSGVd+bd/+GWdEtiU6YkefnW/IvMdA7o+7qwUcWZtcnamU6+1LJEb
dNdqeAqrer6t8pN6kqpm0XIzd/CAbv3Z5CmVyKyyLxR1tzcsmq3IxF8vzH9i+I/UvVr0a+ZSM/SU
gTm8a3BATXyoOtfmJ0dUIUGAUvOxDJWXeJor0atlCP/JsXXfDCBWJRnxmf+lAjrvdOjp+Z4cSl3D
qM97XqO+wXsdheWurtk+6X4B4SMZAhB5ZbAOEp/HYakl+SlzHuguFloemO7t4oRDnLxpB0sm71KD
whDfzIpWWYYHiu1APBO6far4tX8DvHsqwVs4PoZ1qSl6wAPdAH/n80B3FZ8yWScOJ19J3prgZX61
bIhrGoHzXrtlL8VUjWe5k/dbimIlqs3e2tkuCPlqVh7ClZXxTk19nLT14WLF7vsXIjKxyhX9RfL5
bXX03JO+D9pob4KX3+O3Y+ddwy+fCQCBG5OWJe1nPfM7mC626e6e2824G3MDb8IC3HQDV/OejwzS
bvmJpbCPqwotsSibH0yzkuB0LbXXPF7Pdg7rZqA/+1nQswWiwqgf5lRanqNG/890zxWxqr0wqnyC
7bpeOxQTRmBYFFsVc5A8lL0qjnPg70m2S0g7Mrt1PT5EzLtAnJ0JqfSQlorfpYTHDkeohuuYjNm3
hMGrncMR5zuw3+JX01LWfRvRFDLWlW7v1aHMEEWi5eGQbNnMP1tP8p9s/uJ8/1R9K0SxdfSf4Pti
752+7nQGCjiMajQYNhE2whhWvCHUj0DpV1wZbQ/G2axsQRHJMV6cjBbCQkQ7z1QbFiAR1UcVU9Gx
11nozMi0D51G070r+HIcs/Egahdg0Z4YGnf9yxGbgBTJVMwmLvEZ+dbxgmrQc8S0YZsOh3QovIgN
M7qFOZw8lqtm4s8rZcxiNBMJeqhqD2Ngmeu3NhPxWMuXDXQ6ArJUbn50nnsJDAshVu+6j6cJEpom
AaSqKCGzVp3LWu4u85HUp0k7L0AJpp41ZP6BVsqLeNAgF7dkg9FTx+xSfr7I6in9vJ6hRi53mBqs
TRRvp4iTbd4tsEHph9ETUZK5si6mVG6KxAzn1YT/5WhsNO7kZDvY1ctzopf8cyQWe07sctK7YVKn
LXABIa75L91nTxF9s4zp2pM1NJFXSV0On0EHUmmIt+ggKS9QwR6EmC8NnzjDZiLexJmHDkyOOb6S
7fh1IPrMrh5AdnXZ3nBNP/AEgDC+OHoW0uj7rEZLp82ZslN8gfLLtIcEpap+5FduZYCGRB3SyqwK
ta9OpYBEHVmfOX4g/iWFFRJMJfVR5TeLSXaQHfdVasJiifFramR00Xmlw22rkt9jcl9RWy9AT0xv
0xvvxHz1kl16SjOHscnPekNzlEAiceBbqU7ez5rphHI/JnxveCsoWXQZNOyHWfKw9qnbGFr1/6sl
PzQdgQxzwiKusIFk+kjIy4bNd+/tZokPhfE2yPQHbLYIyttjtPLN2NxlZ7qBOxf88p6TDgSaZTHS
NHqwmdIKPraPmNhJ8t+FTDepO1i4ggwT6OHpOkCML18gq0RpJGTZYGYl9HBmYG4cCn/jcON3+/ql
c7sTdxRnpAqgTpf9SlC0QadOnYwWSqdCnc1NDt9hhZYWiKvfM3S7RRfQBqMihkac0lIfBOBj+IOb
uZvyWLexQQsp1BlQCZbwE4LS+9dDSkiFr7j7O7Gqadk3N12JIT+YGJt9N/u10B5uQnXSDNRKWWBj
fepbcOVOIPvn/0e2KsC0vB7HwB0/Kt/P8TmUaDKj1I5Jc712ZUAs+6UGe2+sbGoZ1PTnwrXuTP1F
o1iymYdvE4fnZr+OeOS/6jcYwSU+yKeccEMRD9D6inH21zLgYW/Lup+oj17tGpM38aNNxKmDlFV5
Kt/RIZMqvIEooJ0U2RBfj1ImD6Zk6OyBIjb39NppT+8UuC0Omr1tbG+WLXebc2YXQZght5cCA9j1
kkAB8EdnUx8lPYmSVIJxIzLfD19vGPZp5V/5Y51VXBUv8wfkCpZjegvIeVhex3M4q9IFem7n31x+
rIFTpWTXqk2mRkt2ARsoKEF5PypwlpGXUsfIfqiFfVgju73CXqtbsUWcm46D/KuqSZdQ7WehQ6DT
UPInqZlJmsdsxS2jk/yJ1wZWLdyKG3H57JJXF7GXTFtvLmkb/ZE8gJ5FP9lvQ26FfYyhSB/71L7x
MOFKbI8Qs0F/3QGm7IBGerit6/oqATXHqgv7R3pR5b/hYLCdTAjtSfAQycmnY+peY/EwJNZhoK0S
rIPN9Bc2egcc8EVjIWDTm9jzkIHLReEfNzfcNvKq/dOtZtRI7lPlQ5OcwfHpbqCusmvKY822iYmi
WzVyVfTLdbUZ7mTbSv7xdGZgMryI6cSWjqIcKBI5wTcqbUMlOa72SMFI3STrfkDQ7I93Xyjbwgeo
Plyq9Ow5q9rMDQfF19+BoXRU+fxVMi9AOB4CVEONVQ8D8a+9ZeN67ZWkTJFO8givk2FLvtSGINXv
exdQT36BSGKpJ2Ow/EREYlXqEfxKr0WodzjQLKTNScDZ+qfLDeJJCZohjpTptqXRuer61wTqOYTx
vDZCQbI3dX+JBCCsHPaXra3rf0fvbhaIm6IDcQpwBkWJNXd9QBVSMtZgz9EVn82+BYfVeYJk88b2
g8nSCg8YeVsbt2oLkj0dOftfYlJLIlWkSK2wgD9BGmiEN7PEjvKeAAZTkIMsTNwLGa0lMZtYJeJJ
BBQ5PcWhArqYoME/9U2dJAznNG5ikVQO1+0307/TFW4xm1jl9Gts0Gu+55RjCHHUQF7BVkQDpkGp
MKD+t76gzqPJL6OPoGz7TEbbOHko0dTbJTUYb6McPDThEHpmwf74UGcKoagcOoiCURxwDzYfUUML
KsZm/R+PPXz8N0gPbayYUSDNGgsFu52clDX+A0SjZyV+B3ontpEd6MKs8R8cSP9Ic9EyUH/vO1aS
lB+T9YKV4RVklFL2kXZzl9ay9B0xBcFI17v5S55ldYbzQnREltdMNFr4Um48WiFbXVIQ9iMEDvm+
YOpy+lU1hX2T0ZTyHOt5CHLwVwot+Op4tOFwLJGoMpuDB+Er1A5uRaHNxjZZk+LsfCQajUydFcS0
/p/RPERNNu8d2gjrFTVNAmxuT0GwQQO1/hapAByMc64gJGqi9mOzhDk8fUsSYDfgaXLrwUFHUbfE
xCUCPQQvgS/bpLpx51dtyUzY2fJ3ZuyhDDBXeuLvjH576u02K+UsheqsPVUj60tOp/cII6BkhUs9
IbFnpwZdlXeSuXj36461jkSBTVHwWo3NlUwhwaBBHt3nn1i80YQ5ZzOjOVYlmRTg/N+2QZQ5Ci7a
b8IoB6Kj0aOW4sopkU0lxyyrGVkHFWEuIYDFUspROQ/PZKMGUylgjD2nZT5/f8A6xdyjoDKnxvwy
YJT0wJBOa/g/qMM9O8ICukzdmA0ef6kYitIastVChB54RY9+2L9E+ORMNJcVDaSzNte8BtRPSbJR
rFwx1irZU5OfYVqZr1oiHSJUm4Kqz9T8iI1mreOu/U5THDaVNRkobEj0QG4e5n7/YIYUi6jbXdD1
0QLn1UeiI3Y6bns2zx2iY0S1s1mPtcLPCjZKH4M1Ylz1KfQ4kQmNaMUDx8LxmK/XNmflZO82f+Gf
rYBuJndLUcimiPzoUrWC+1gfZdC+5VsaqzVNnKI4tDmibF/pSIR3U4NUKj1RRPgCxi56VyiL992H
Y4W886sCYrF10wcMlDd35R9gI6w4vTD3iRFoTgGymcuogqaOoquLrwkHFY1XG8cSixUl9D2AVyXw
EfgYpCEBYgpn7z5kT9kSVU34XLIJNqSjv4zkyZFnxlVXCvE0B054m+PbvL2Lb0xLM+QBSAZqOrmm
/+2ChEfBrFDCfaKqXl3fkfuX0JpN+Yxf4+5ZMEV4Az8N1jQc5AzfBMNEzJvLC5mBoB780MVJPou9
VuRPtljZ2tBXe0QmkuL0vGRw/Jn6VCwtj8I0lMJ4v1OTl+ZfMZEhVq/cgktE1r3IknoUs+tGv4Gl
92aB1K6EiL+VsxxOQlsmOKQDRP6vMTBAw/i/bEZJA80mQ9ibOT+uS669/wy4BbDJuAtujTiS4CB2
4rpimwD8HV5OJ0Fp0iChtkLHvY7csw6mB12bwDXl4drxDi0vlpeIirabh7eoymx1hxP6pkstxukQ
+Omr/WgfTXx5PdqunxTAF04JiO2pQwv/vfte7wiax3zMWu9PryLbnCiE1N9/97fdQXxgBE4zzOuY
jMqpPlhZ4u2baZjJZt9DNBaxtvANOg0lcAN8Mo5T7JRsJRVDuyWzMbrlXeC8sH35emTqRU5nM6eq
CkZvxrGajNsDygahSERv/lKh0E5kJ+E49gAFmfDiBNjHp9BAFm00BNWfthSKSIWVQKS9t5LQ49RD
jKOYKRBuDYX65dZ9PSwca+ZJHuMPBy1OCoguZASfnY8o8tKALzev3QgEugWCvtS/B9YeY+1tZele
F3qagS5JwNM2Br7wtsqyCMaDAe9PlyTMU8OXbGYriIuvvVB3B1T+qfojF/XXHcgDcEK3hJKr0gXz
+bX2jc6BvgKRt6EOvw9o6EUGv4cVxiPCBtSF80WakBCvmJkqL8yf+M5f+sPLYH8nc4UghlPrrKFm
2EWanw0CDtABEBx8gs43KKhIOGpmh5CoA+wd/zykBpjUz/ivh2417bNxoWzBec6cSlanh4hThw1k
/5PPyLReagH65LN3MINCXeVj08s/cOuLg+SM972Ql5jliZLdsA+MuGaVYHjXbL7wcYo16YVGK1Dt
hOF6kTw/iMYzwg1oh4xs+22S+eJmLJ+5jdGKkgV4g5MAvRf1wyRwjbcX1vDTz/F99vG0r2eGU5JR
aMWaB2THoLOBw4w081lWNQwxp2Zyg6FTEAAO34XwQrwjzG/Git5ZRMJUBBGolfu/Ti2d2rvSY/s4
76B7cNP/Qptw88jkDVU77SoCcrbQkFVoJKeNrRGiiQGPHPX/70OzzgerKbRerSa1l2m9wz+sY5ol
2g6zasN8EJyB8XQ+EmNJukh5poo41Ytq2VTyVw5lFDlR7BvZ9xUHw1kR1Mm9g5fOsu0scc5iuG6r
f3XrETqG5s0ixPvLMgbRvnj4CHElxsia6YtPgDM7RmKwsZScXKYUnPKQ33b9SXodoUrsLat0846i
pvCO7dMqaeSJdWB3pPf4XCSDoPGdSlyLswHkPl7KmQlLJG46ONAHas5cbLhtIbQrzX9nu57n6r43
DfrXv/sgeWKVmhEI8jPX6GDQJVo+e1YCweqnl7FGtX7CVa2+mTXqLxSXXjGo/XWg9y0rw/XcHoE+
sJbU1AyuxUDzqSGDyil0kwGiqfAw0Ge83KQdc+ItOebvRvhw5ck6IN6bwjY/K5kUbTp1D0yeFyfZ
a3JzuefjCLWTHL66RMg9BlhoRwgdIRnTMwolgVgWCXK+VbjMFeeSg1eRT8c55lHKtrg+4rMDLNa0
uGz6jBBGLs51ulRDIpXiCbvv/XsGdAvD5zZVcG+HHZ/+R73m7/u8LI4HNhMnvcHy73VeqV39Df5y
bcGxyUKLuOs2jECqzztD4N7EdMRrsYDzakSCkeyWlucohYFSdrGEOi1G+ZSecVjtTBZxxXOVzc5Y
6X8lCxjZHn4VL549hXRSIeKCHIBOIiKmb+bPDe6mYvUoWHihY9QFL0G1MFIIQCAS9S1M2A66flax
pzqxH/eNZ6dX3wbH2vzF5fa/o5RnAXWxCuvXLW3qp0GnUbmZysm3WiwDikDoZ47EalPvn2irH63R
sar4KW6x+NJJt2XnctuejHfmxSs1yMAWwQoCLlsZLkbKQTFCX+HzngdfUapzPgC0BRgXy5Z08aV1
RSWjHySERY+OiGTnpre6dhORBXCVXEt+57ODeivvOt6uW5+O/adFzzC+raZK8+XIeNNztZuZLi1s
r9G9CvnMR2FZxrxI/KwRm7Ft3PmTZifAtJPsO4iYZmUek0ON/TGWrmaE91f4RF4hQ3EydFHSnoW3
VC+4ZgK9dfUaSMQXG0QFMU7y111h0cx2zFuNX5NycrcgpU0Dcfz4D2U3fG9RSjiM128cid/sg/YD
/uC1tunjASz7FmWGeLIUesHEQltfdQk92oUpcAq/KBdtHk3HeyauzEfwECOlRTTwstvLThuJS2n/
ksjcIr3UwzV7SgcEdbsFATMMGkhIAyd4CvXIqd3z65sYGqgxdVkubDb5D1zTq+t8Me2SjhXbZrNV
iRwE2WFO5zA+Hl6K1yH+xpz2xj3tn06oaMabzc3kGQnOWePsrHAHRrUIuBh3byOdM+eo63yVDbdO
QFjcMHWL8VM+XSUEULxVqRcwkS+lNiZdD1vFaFVx84O/c8/+TtwXqHL71R3qjrW4cMtIQ0NnJ2FT
lYeVUkUYMhbGBzGGNmx+kt1l/ADjzIt0RxTvK3/e+EWiGSPl36u2m9d5+nen7IIRHijzJc4Y+7YU
+gGnH4unSNiZJpAHfkFZ7FrJcMRIV+9VYvvNC769w7tKKWl0HVvvwEfAJFIuaq/fmqsBz4j8b9US
wlc+bZEjEvIXtcipo5UxqyUaV7NImZOr8BD6EfbGhxJK2GGtqK6q8/yVwZrBtAzcXUR5hGPA8Ibe
ZEeVQSX39g8bRufWoqRPfjIlvkRM+hudM+fHfbpZii4CNgHU19hjsYwNNY7tvHt18oODhHkMFEKs
MXaEwMT7QVroboUVii0+pKYZxRn3RcQ1iu3ueasHW5piaXT2q50Hi5s8mxjtVdhp3B8q3HbhIqEH
vjzv+NDHb0jI6CYhIhJ37lexysjkQSqrKY+rk42WXZ8CjpjPhzMikHzkCPVZKksBBqWqp83kKuWC
tfiixBBUiV/px7WqsfIhwT3t/7H3oc3WQ6CJYweW0ESq/DRxQyE/uWNrTmR92uqn3YUVzjR2vojP
qnQJUyMhXiZ9uMS1iCC81yr8hxIGZBWz0+/Bbpg3FkNx5Uu84rzxhGVGqlGYeTQa2hJCHfYK+T5M
7G/dCzoKO3t6bo7MQG834nhlyYBcDPsk2MlFGPWnLqfPY5Czj9eBru2CsYPtlj9ZCvuagqheV1Ex
C3Ufh+RjxJdWpHEl8Eb7KtoL/79cPuRdTNqTAQ03aoesKmzF5gOuZsP9OSOb5Kffm5hZRCqk8k7k
scOJeHGRiw4M1BG3AqJheICbeAoMzvQD+JgOZrHruGVxXtXrfasE1EhExYDbtUhSsNCMq9LmJZ/Z
dQmd6HPbjL2nuxNZC/7nxbJ5rjgdWA/X++vMFWC/QubNO7+zH0iB7/whk4+w49OAc0j9pvw0NhR8
lHgECZ0AfcqCxEe0xxqlYajb6pqnJ70Fn06I89obBPHrn8LYxQVzE1ihAZv1l9ErGi3yyS5Ubd9V
6VlGYR7OJ78mYx+qfLuWPg+YdDUT+FtKuVihJ6CjNv+hBnqR71nvsJwWn7lpyGEAQpC1b7gCWK+X
aWUgvETSHR+bwmJ97rVyOZUG3QXlckWskb2jQJ35sVQpJFTC0DSj36YdF35Xun0BDiYJ0MRtvve8
0U+SP6nCmUpytL7+yztjnJ05F9PWn7i3pCdPalK9xl7kA8rxXFyLw/TV3VeJW8rOAF0dg6od61aX
neXCZPxYD6GmBcuVSqinoWkVaTs2pMKu3mtbmqF4/ZklwGvxvJfRRxobbeTRE25P1k1e8Pqxa/1P
8UdJzhaaVUSQwzL784pUd3bqQ1PBWHWCda+IQBzsSv4piwxe8qDS8s6tNaSQRr7buZGeXPRplzyY
kUCzdIsQiLb/4oJhf6O5UbsOORA5/29gYXqZ7v3+OCphoBkBx8lOXPDvdk3zMvYaoAanIO1Jhlp6
TsQAN4xhhM1FeWmxXm8VLyX8+WOyZmsyKSBCnklhZRPp1beReEn+op/oKoGOz5sMARyShAEdAuun
lQFWpfhvH9JdWgZ89bJftG2Rocm6qF0VBZK2sYektEABMaUzIEp0tjmkbCfXm1ZuaydI1YVdaFdi
zCIxOCkF7hYa1FFZN9s/cWZiacmG+Zh3Kt0jhh2GjJ0jMbB/GskJQTzZEdtEiBYM6iLgCb2P8n+q
5VpeiAw89kSLNdVeuKyElTt1x454wJjZxczg8QHjvnDXJpzk2qn/O3ukvNg913riain1JxF0epTn
70mHaNdW82ix21sQb5WeeW5lroSOeH07WHEQPp4SDy7xeNQDMkNoGTEmiKXhsjyS7nO1+sz2i+8z
40QVqWlwxXD7c53X/Z7ZDlGo2WGUp2RRMRKTnt8y9jTeuBehIAsqn+fs0ya4L0Gjwdv1mft7JuVa
9LftL8K/Hhqpvy0IRyLTpfCIKh73I0DOT+2qOvJB+xGNZLvJ7mVYCzIWq0M6Nil0hl4ZYy3y1d3F
1eHiuHVSiJO964aBQQ1JYIBTgX0kY2ZSdBNDyJVn7QSx+r5jpNu8shwRtHaYM5ipFdUzCGf2pg9C
ddyXFwt2wbKff/nj3RWaSLU+X2aEsbBX4B6Er0ByuVoO+Nq2Melq9WnPK0PzT0YeNYqTvV4tp//C
I9ls0r+L/9saowEZBEDthr0gIYPKyvZBVfPfoGmAxfTAZ8WPUf5+1EGRHSX1vokGzLhvLuOMgaH2
YqF9FaDhHy99JqU3OgUolKxdTHN/swjZ4sPu/GUeHRnqHp/P2iPu5//TWGevIAO9SmJ8MWy5WoRU
5Gv/+UU6l60Pldw6LDns4FfPG2UtlkUwewDQkLsQJnGLfNsypSRXRupG+1FixMfkOV6RokVJZKUm
C2XpRy8T8RjdB7S+lzbhVH1147RKFnJ0VCvrCFj17BCwsZMjlQL15mn8b7AnSueE5TisUBGPT0Am
RobjQXwTRgD0cl3E786d7UcvKSrT263feD/VXo8oMjpd1lJq92iunl/2+yKd7+G52D5oYVEF1gXH
9Mdp3PW9sHZ/lBsVC3ZifTTW9fELNreDeVMintepagSeQNQfHB0Dt6W/7+W//xyyNh9GG6DEtuXc
12qA12TDDIZuoBKZnwjgszDsEjaXVGWuLuUagrDZrXozGIiDn2ZsdIB4IeueIPWO6cJhbiyUaVSP
KQzxK6AyjqLHls9QzqkUQQz4Va7h8JPADNXg8ZmxeR7Sqs0HpwNPEi1mJ4dDEb5fpfkd2YErAz1C
oRBZRcIbvsHLUeLvcz4m8ML3wAPWhKcEyx98Jn+DoGeIhFE/SPTvrzinxMAN/9c89O/EGSIipuss
Z3ofHGQXjAtmjuMuZ6/DFynoc1nZ8hPZjkhBQcxOkN8mMoZw4cVbrK1H5owpvnPFDvKhxCRytsai
tdjr4RmZQr1l8v7t9f4XDmOsTsm+AEdN3/cBJdMtJKTUvh+OroxcZcV8uikt9GoKkyjmxSVy8Y/Q
5L1xoux2W49ause+wawS4Z0r/RbqYxrPHJkM1lyOLvXwzxSUeAbQ6LR2gGGEH0CIaLL3bqOIvG6N
3/F2Q5rCdlxL49wwlFpb59zoQciXEFZN1e0RKqXg18VkaCu/tDXNyOrp46iYzOQLJxPmYiPYwRDL
9/oMiiqi/WF0TAmHBoK0g9McTcknmH0+GNBfyya3oPLV3VIJPkEfE+cdSxP866VhjRS8arSgybgg
auDeA/ueYGSbHq/oKU/Yh6ZyEGDgayYnc+23WT3e9RSE2vcV7U3Mqk4Eo9J7yxhDraB94JR+cKXc
gI/Ug19oQOWYfQpj5NDB5LsGWGWGLnj6WMGlp5oMVDSVXaig6LQ4/FK2MpjWPMKjDTAssSn0fvnw
f3pQZAXwJ6fBA9r0NGChMPW+NK5mI2kPn3JAZgNngzutwbwFHY1tb38mMludvGAxKTiOyTBhHOF5
mXktR+VuWHdJ55LM5MRKv5HgzNHWv1+OMvIB7ukxtV44PUsTyULZswQ6h9Tin4J7gIXGgdytrjO2
DuTGfXHTZv1nZK7j6c4nZBlyUiMc94CFy/xUJvw4cOw1+z+4IkrnEO/04zvw0bWvmqNcQjkbdNZA
R3tkJhnb5N7YJGMTRbwF/6iM3kHmjtgh5tL2ldkHKBoIgJDFVRwYlDM1507kbyL2NI0fKa2PtEqI
mVIh7zSIX2LaYHfH7Se4p4HlbwW8HWW7U8WLu3QkBh538UjN/cvd6Q1Yr+53tSiHS1huLd5umAj3
V6Hu7hqE2UnvL02dqytnkDgu7bUH9hBrpMa9iauF99qklBGPVqY/aKl99Rj1edWZGDQwBqUZmU8g
lYfJ1eJ7QJ7rKvhnJ4kC2YlUuadRIytYnLo54M4FgG4xHoIvMFIvABj2AZXY0hqkfLske5oI/A/D
z46W6LYNZ0foHp5ekO/60uil9d4GNfqeDzkY1A4PThN8e77CNzRE9+Txupe5I+1uAc5NOYiExDRv
WltXManIJJiQpsBJktO3fB+mgibDXYdptfXPuamUH/Ilxx6mowYRM/gMMhIQxRfxksITx4fhiZy9
O6CgitnBeLVLWbxl9QVreGuI0WKGSW5pUoLrVMVInEqCl95o+gIO7OK0G/sQeCudV4107Qxn9rrs
YnaEJ51JnsV+PAd9SfVFgc2EA9BaI11tCI2ylfllXFX39BvkR7yx5EeRCmWIo6+yaycf08V9YREk
Mw2cvMsw7YrkoD3GauR3IEwnt78+NvdpIM4pouByJh+Paoqt9xEBU5G3dRgW8vHkOcuSllWssIXJ
D7z/p+1djr3ul+OD1xSEhXd40FvuTnsKxZsOD1FmcMGKNDIxGohu5UvXk5V5Yg1ONI5LZbNp/mza
0NkQoxlqau3gNqLGDZnPDDQvuPR9ObMbVI8gLKg4ntHVZ4iVjAwwC6kkOeJVuR1JCrhGdHtDS8jS
uRMluRFdzpwuq/7tI+cLqy+vCShRSUw2cxAqqmE7ZYQA6CSfey0PBCMLjLck+mXxCDoZHhgIIjpg
ziN4I9S4KXKzE27b7FZ/tqPngO46H9t5Gbgg8eFsRqiDocONPX7xGP/p3AT5yyCNcTbOaqBttB6H
ofBWUHqwJi9hTbsVOUefqhQKPiBq4bSvascjyEFPknE7xpk9Z7qltnaBOjlGGj/Y87EeQCF+uY3I
3h7wZKjVVJ0kiGO+y5gYUB4cJprzTf/3nZbO+0ERE4PocVGXCJ/nM4uecER/m1aydOnLwRegzodz
6JhfXOZSvjTcpsIrYNiy+NPilRVm7jZkXd9+ZMNmbTu4y5T15oUxMwnnkwgTKvCT/HpBaaulgCdl
Fl2T0k22odBSqcjYGDhy43EiVBDgrlc+J6rU8nJxcXLxexObCHjmTQj2WK6yX2sQSbnxvChUMJ0o
t7IAX1A5OV+jRFJFyjiDhvZAvACCVk74WnltWL3ERGRYBBZxVeFpoXUbWVz7oJvi84XcGOR/OP5g
kfa0lEAZ2NHVq9Ul5ewARAOHDcHlGbfHWhKni6O0Q/Yl6qEy5ptrkEApkd5+VlziTlnTRFlTFYrT
hWyjwMP4Up3YYily7ykKpcCulODimT+rqDLR3sY9ARkGaqaP/fvw103pz9kdcT23fnpnTOMRxTHH
t/LSvFxDXHt680UbCz0xZbAbLn0J+O36hlpjEiLyNpdv8AdjpAOa8lDcw/hkMsi5gLnwiyHPtQnF
vQ/EiMDiouWKgLQe2NrkakbmDWmMCfdblMj13QrWn8PEiGnjufZa+in2bgAtP+C1IID0HCGKALVn
8tC+HDM5aow6ysm9CITvUBcDP4/zOMkdW5wD3ICB9KJai9Up0RDHf83oJq0390rxwUz5WECA64Tb
rzm0EIrChD3914kaBuzHX5fWHgd7lK5GiNJH47wE92B12Or7zsvD+U9sFB4oiMOSK2CXrKaM087i
KPVjB62nXQ7j8uRjf+wwsgs+7JQqcCfTMdA7QCwvWkl7Bs1j9fBpstDl8MW9ZdgyqRE8ofSYDywF
MVtiVp/LMpIJIXTuh/wOql3xQA3VAqABlS7baR/c5Vjpx1SUpNfFsWxfqIdCk11RxjbOfvuqgswE
MpauWiZGIdkZLgkuiM5CjAKI9zyJlm7t8/miLUxH3uUzb24aBowSYG68COTNsKXDhlnFcg7W42Yu
WFx/Phaw6RCJlUMCmto5I0zhk2YshFkCPa4rXf0L4KzhV+RqBFrl+udvemXyS0s2jJh3ODcPEbpF
71uqpu/CzQ9XgqCC+2y7bKKS4R2G2lUIjYxPTmbYiSp4poEsNjWWUzFq6y5r7tk36RjeZZEICmKT
n7VZADG8HCmnI3HowwC2XWNC1eTuWuc13tNZZO5IEViUSgkA9gUNPHKStMwXceNRK54CeIbKBqsU
or2/3RYFLIrMyIPnN+31YDH6Jd6CC3Ado3yOxSZc1Z+NNchkAJ8/ZN7RtJn53Ex4mVFjiNsYAGj6
mI6hO2+/JT29skAzJJ8az8VqcSYYRs7vC5yfqInp3Iu8ncxRG0/RJWPaIHry+ZX5Ynav4MXwl6En
fjbCFGzAh4uANKUlpcEt08fw96eGjtEmKzkGIHf3R1X/N/HWiTPHyhgnv/5sL3w10E9PSYccUNlz
CyM59af/GG+9r1dwpz02q2s/GnbSW7pRHpIELfNO0cFRA5Ejx4Jup448qtGwtLYoEGdg2k09HT0Y
AUJ5yAKxDZWFqYlgCpUk6iEXUEJMeagDRAHO7vtCYrZyewvkYWEIWG6H51CQHoH15IviV0SKR+Z5
y6SkvRXwxj9xQq7ylruWNRUUuaDlkaaAyuByAs7In2bmukayU7wopmn2dGG2u4w6me42vO1Rsy/2
MoqrumWRgIo5jx7LzxUr/DOXSci/07l6tNFSUH8L7Ym5XqHaKFV95Nb3Py1LancYZucI9jq3lKOz
U1pFMX8OsIXGjASYSKA2TCaFtrRd2e55Hz6Alu4qW0ZtT/lVe3L4apSpWs3kWfUL+geCpgWao96o
woSeEVne1w4ao3EYrYhcPRmVcvSJTDakW6XtstmvXdptcg/PhHI1b7zWQj1yKJAnWweqM0k99Uwh
kNUB/2xqbbyeCf8OcAgarmarVV96NZlXhxEBvyIJoaU10X09OMELd9IidKBAAjm0/F211wAZHGii
tCpSA9ivif/VwMfOEtMbt5hZwoqEc0oGZ/FtiQUjhDTZ4dMTyrm2awGIzDQd9MkQ7PMxVTc32TIr
RkQYtKSZOgIlWKeHiWHaT3PmGiWxPE1gXiVxlR70URfI0hLbaYFLjhzzACuC73E5yoxZu0BFiEpK
ecq41ZM8lYa0Kb0/iCtl1WgwKqrpgR5Vy7+gTat9pqDnkbzouXZut2dsxU4J+leB8yTFWu7eo95b
YnoJ9pKX162rPuc91veQkFCi2ihyGRUPgybnIXoOypK8b87mA6oM2RVd54ehjKtg7yJAf2KmAbFy
QeWiygNe6h6vEceoeMj2x9c1L+p+JrOMwHmtc3ZG0dhrmNBpd/CmVjOTytAhTqXd7JHqFNGaTV9E
Y03B0oW5PTslA0UpsnlJtl1sSBXH4Xz0U6SCE7f8hCc5RO/MgWNGPURuKtP9hAUlrTnuk8EAOfJ8
d1f+h7PVOYsJPIDHULpxU5Hyo7xVltRl1U8MfHP5+HAXCh92gAcB0Qv/bv9tIZePiRyZWermbyqo
RU8b48+C9auggDkGhGddDJDmez3kQatfJf4W4z+n1dHKdtIJw2hlMEAYHsBR1JK4X5U2ReHLNyT1
YiBsYEa5CZ0ehe2B5hN4KffzMf6OvfuJxe/0fEBcgxK5MWB1k5nd8Iy0lqOLhEoiFdEqbq09UYQa
RHizrgGtvWePRI7ib9EkDQ87Hz3H2ycz1NyhFn7EBAs+Xf6wWhSgsTb19C718eW7z1S1Cw7Yx2jp
AhLvW+1xE4BnWdGdT0fftElZSSLyqWtkufrQbCY/+eu7Hf/cVi2VL6Yp0HK9Hz+zHmj+LFkQlJf6
uOe6wF9IzGZC7sxX2IZ3H52gSrSm08+WZ5YWhh9vpe9i+/uryAykwSMMIykdffj/Yw0SqqpT/TkR
UQcWTbENWu1bZjzMPSZ+hfha7rtgI7LmEjhcOiEr/aGTpPQuVh499lajBFYR2XX5sbyi2xWzh/hx
bO4xWlKJVGD64oeip79AsoxNkHmka+1wjE7oUn77O3Qmrfhd9mylxrN+F3BR5XfLbeboOSW8COMA
ubfApjdqSD0uySJJTY+er+Ir9TNNhWijUMKGybs9hIZhEzH/53X/I3tc+1hBq58V07JWPZMTDdJB
gnQGlSGDlHfCjWNEQD+N+hTvlM1mLGT6Y75vW3wzY0AccKgRMmE02619nkT/mQw8amzUzBu6q5OK
raH4UVlFbjDAANkbKsWKBCokT0h7ooUVg9PCaRtzCjY2+/sN6oZvRdLjodHBYwqMaVpW1AC7n84H
HhFJ7WdkmE4og975zVS6HQ2myTjZvMB7MhHUnajvxgP4IQ3qJE885YEVUmF3C4aDvEytaPpFn5m7
+hDOBruM1OcUhAor1kjgqd4nyRLGSbU7oq5aNQEjgin1aO0P41G8NyZyTIR6UykYBt2KhnDZ8Bra
kg9pCW57mKz2iXyMDRti72LehGSt6T2MYmbi18WBFZHi9BJp/OvjW6OHJWR5BKALLndjrEINLdu/
O2aA+RDeLPB9rt/w1hhDi7yz7L65D5H4vAxsygdoXF+aTSB47NUzK0CZKdGO3/T/K+4TIsxCeKEr
9Aw7SnIYR+NMVsyMTE3MbF/IqGO5wZrf/LLcJkGGXs2lJwPXd8cseOy6BgPeHZH4ES16OxLsNBJI
TgsNXiDLJ4MSDKZtTbTLn2+R0bfjhZY/vyVc+YKVMv+R0ySoqjpyAXlL5gupQVIECJOgPUdJZttH
Clv/njsBR6RTliMQjPqRvnfAUqUSm88Q59Gfpr8AgkdHqwqhhlpQFdrzjt5odLQq9HRIs+1WrfLT
DyqBtpQLGdO5rhO0HLukZxyN8JKT+WvDhbKYC3OMF2WhKQe4nD4z+3Xdf2SKRmK5V+oxUdduWC0/
HFGCgzIu8XunpoPmkInRc9gQ1RBzkE8hQVfZe9Q+Ny7JwFxYFvCNJATvC3vI8uFDiANwWTaK2KDF
TJ+sPePOjqbbDsSndbnfuAqnuiRNEnBVH+rcWBSDDkdxDFh7OL8qWqJRAlhWVnCzU/ORWYMtDpDa
TXAQ4+aDslTUMjjOAev+F48RF0I0+XohObJpDrx2w5LCO9nFMDhu3FX8vjDoZoMg2nIpdYIOP0J6
5AmGWWAy4QDgdHePlEUTaL/7LoBiv+zdziVXzUV7TZaUG4MRWpHB0pl9MW5Q4QKLmzTteGcwMWlZ
oX7BjdLIG00LiuDb+strw/s7opk2Q2qcYH84UzSXfK1gb+kyS3qhmk8jGJTKiWP7AjgHbXTOYBH8
MRvuP1A53GnTdNM+q+awjw0hGfKJ96V3JnmqjeQn+S93LvrNTEpcUpaQ0HQ3CQESFuuQHJ3cvixk
nEYSC8/g1G2UI6c1isNe7YyodmrYWJ58OL8pnw7Q1ZlwOa5UUxOhQm3xVCyOzXnWZN9fGX2bOkob
r2KjuL8xgIYhtqOTEwwHys3yfDVHUuSaE0s//9noEiireHROUrTHufnzwnbQI5MnkoC5gVvnN8yx
lkLMsrIHzGFPhEMQaqxfSPxvl0yB/6WPwlvcHkmY4aH41ykfBItlEFfnWbugSupcdWUEcuezw04j
TazN9MdVzHtL1rjXdv9LSZyw1fVlssLgRgp6MTd+6tDaBxtKuVY7zNtmaTU7zD+Te9nFJ6r91vKA
xKH90QkQNVmc/RDewKcVlV1zd8CnT9e9rMOdTUnbm0Fg4JyE30TiRZ/NZ1WO2P4Nf4n4qOk0vUB+
BhSe7LiN0OS5k/5IPv3KOl16/WZ7S9cICcb2xh2iHC1opWLYSFp+rqbEsj7jdUNIkEZP0HuyP1Mw
DDdMqLJYakq3LHNX/Iw0vw2mux9rHL57UXNBLKH3i3/+MGRq8L4hnZGCyVLntXOYmrxYSdwdyf8w
K1pvYuzKLFtYOkp5t5COb8RDaBbevsXQPnDJ1CLZ6ixlWTg2wiRWRaCkJzRH7yeC8m3Lzp2dKAps
5s/pCAURpyJgl6MbvPWeQKoxI5B8DKuDvZ40khbkDSfOolzgKMsk2LozgE97xvpwT4YnzrBt+YpF
VCza8WUbhLFK1pVsh1xMze4oBIA6iTLHwwX0cBrQxo/vCli46kuyxVSNookkaUOACyft8eoOwB6E
n5MLm56P4ImVTSbQ0BnBxkWD6h9AB+IpUMcsgvAiR4ecPZZEGRayxfbaRPqkwXOFB90H4xs4bL2w
uOC/YGXyiCP9hEk4I0d9lU1ek/7xcTDJjnf6XWiTU9F1J6AHmlOTeyUFGOGwyZRbFL0Z2rN4vgvY
r2XPOd6vLhbju+xwsnOFVHphEy6Ov9kx5NQfehY1DLAEzEmfSZnndkD3VAOeI5pNL4hHLA+7Uepz
Sj9ck2YOzpthQ3Q24GzOxRT+V2yn5bkeYJOU6e8a8QBIR48JUCxejb0Rfg/mKW1/2umUkmFIG0f6
OXBPcX3kjc+fNp7tnxxCbsKMr50R5Fynz73ONriQVtrfqZf8cGISGdtculbCowyVZlY4f6Qzzncl
UhG+9KOlCzl7Zgap4UsCbUX6mCUK+U7gYldcN8KbrQWPgXDIfM+v5Dz+YODPxmYdgWHI5O28T5xF
703u0Xsdcw1F10iu4ljubef135W/VSUxx3AgMKExZpmUsnlNuD+50NBgwZTNd7Yz1/2G4XP3+jXt
dKSx3hLfXgV7yNx/1zQnBkOTsOuviY+QSluXLZad8FrcR899QTabGj63B+l4eWHE8wofMsCMBahj
6E2UV8Prn4+Fs/+KZxIqDb9DvCJJV8lh4XhIUvut6vkYDjqawm64LfirjLlo89fz2fwAxe7xWHrT
3gapBrJ1ZBAKCoNH73obW4zx1iDPDajj6/NowUbXEk+TXGYWMzedNMo0b0InxgNo4EV/IBCCX9qG
21XYRlr1wwp8kjQH+Hkp3ZxA8NNSlggB++gSL3E5WukGNIH/V5saUPSjxd75DEBUAPCQw0clq0nx
XCpdmYmDaKOpuDnbBAah1eHBnVoHW1Fd/GCYWJU6w+ItBdjx5R2iTUCFdLEVyDo0SeX2d8rFV+ck
78Z0an65S5eBSthMYT3tnPMbDcBf/h2Voa0WyDJYIK24hEk8xqwKrLyac8JlErQ/DryVrZCYuLum
XCPMXthxc9lNe9Z9WvGI2CMLqROEjexrTnYp+oZo8DY7XqFe+lELkmXkUxnDgfuvu7aJ/OGOR4pj
qkBsN6qqZSWtEAzhe9+EFe2YrWFacEm/ijC8PneMdiv3ZQhYSrFYVZzXIE8+j3rrTbe3iw2rErGF
paJQC2ke+3iHYFKMdk+Cveq64JzXHdmx+Lhf10dBGNv7WCexEW9YhHt72Buvj5wIRc6osCIeHIbF
AxnBI6NduojYV9eQhiWdHmzCYMAxYYkUvTcSY+c+Y2HSaBfRi0Oq0f4fa4nJcbTrhLv9kj7z4IWg
zEYxO/MK8shE5mQLM3rWAbbhWuokRAWDViwuUhB0tNQDdKSvZ3XEpwQslzVGW363pDcMVyeRKL+O
nA6NXN+5gPV+Gly3wQEKA5Q15Y5K0CpWMfuH4ibICXy+I9bIMdmSLQxM05BTqGseiDW44Cc5xyra
BjycK6gMS7zyU+so1nDI2IIiKR7JNQD2yWk15V5iivd2qEpRITMQMUiXwJnCL5dXy5GTjab7XVQT
qNjQF3IPteYImCRnD1M5o/cqhN7qxWpHXbj0s/H1GZGi1ILELvn3EDkKm5I3v6wFH0OIvidzbieT
rIu53MBI0SqsKsADD2Bj24hpJoI5hnJ1+PkuZ8Q3WzD4TUEirWD6q4sqcPBwteMZlw1zUqaq9Z+w
dIx9J1tRbF5N4jfkDuX5aN3daIFJqd6qPKse0AH6lsczHy+HXjLiEvmP4VdtV/WquIiA91zVJjZl
eu8O0lNTab80Wm02AzwEC7FgtObisc0lFTf8o5z1rdCmzurdtsi8khb4T8IBbmz7V6kIZe33IYwM
zXeFGQwdhsH+rBHt/TZYKzkGoGkaDsrJBAZfnaQnmpcC8A3awpUJv59DToz1ZWmXtfZITApOSOgP
vBiSW7OixymSkyGsw+Io17nzubmufxDjZLJP3Xv3gtGRJZA3w7ttLPCQjhmbCHq2SYUDUJF5PVMl
MjNrOZELMmefG7VEegsjxdrYTX7ajX3LZw4z4Pzm/yLQNLFf8IgbU1AakCKzZ0i4JiVUr9tM3jLv
sLVB7qPOlBTBdD6a2K9a3arU33zTWCaJcAd5v8W5reAEKfZ0M5LxXFlZ10Xm6uc23qFIJ3r1dTUP
Mn/UgHWlkOrg9uBLoHktX1vqSOEf1KNN3om8NCq5xf5ZuAYAK2bCH1n3iAmOMzTBl09wKYf30Mw0
4zoXZSY4Tg5bZlBXqYCDDlsmfSJpenoFG4EuG59fkHTAmsdOj8qe+f2aJzq/cp0k8LwWGQdb85St
r9ERY37hfcEcD77v6LIdOPjKBa4PHpRT2EI3MqcKaRVqlgsLn+oQZ3gBjPTzmGhB9XwzLpMU0BPX
6SHUwLdD5jhLB6KSp38WuGCPF7NQMaOUcyYR63x4GUAiM8oEgoV8CR0IG99/8q14MJR5paY7zKoP
mfmvisPUrLFzrOTA5SEONZ/q+iR1s18yeL0m/4tgFa7kytmcc3B7qjb+JR5PxEzwYnICRV5345ON
Y7S82gI0iQbECG4RHU14st3abWm1uaoF/kipdfopvLoO8BUn9yE7s6ThIxKEvVSSKEsbueO4uYv6
6LyE/8PTSmaUTMBIKoOVfdQ/h7nuhMHHZqK1zlkzdXprCOTzm6K79E7FDSUM4ZdLMQscZm/sasUW
PFlVZ5GfdIdECYvdAcNv6KsZnQ3K4kpLJFKq6fMFh5j4heiaOb2U3O3lfcqu34VkL7Fc3+uaw7zj
NucA6qUEQAz2FXuS9/EkY66eRgXoPn4r4DUDR9N28lR3KFdsrU/NXBT0sDYLn+gpDsPhaEoCCoyX
v7dnk9kRvBmg/Scnipm5uAn8MmOAYcB+gtDwXSfbFAV9P4RPy1bZAj8hbqqmwiB4VkOVLCoKTN20
F3BjqQWkspuebfYglskYU5uAuSnd4B/Z2OyNx4KtIY1oTJDjoHUAcTQZRRwk0uG1Whr8l4LCS+Og
1lUSI157JV4wpF581ZR0Cixis2S0pMpLfCUt1d7sAyvgrhOi/EMOH48WZxlXD7YtMl+JDnWY5kww
ImB4DWEj/CiYikEkQqtuTEsmFm2tawbg/V3etpD5k2p6DELtpAeYrGbmbkl8ObrjuwHPhmps3ONW
bDg1tKTUZGYmvH2nHHps+VnHa68vRd3bHTMo8VwjW3XVQCJiYisBGx2PiS1vDISOrJIkIzm7+dlr
UkZ6DyaRn+Oo2ytippDW4N6tOnS1vu4YlL6iB3YfC4o4C2fhzRD3WVzze5VDEM1tb5Op1MqAniFg
JOA2NjVrC5F5pdwscKRplEZbKAg+mSLgkG6Q6AJI59ZU+vIjGS4OwntFOquRrDu4zJrj4MSNmhSU
XvhrdryRZG2PuJymbAlKtvwLTWV4o9Mact28JlkoqLbHB3zHsPDpJ5e7ziYv4WHLHssOj6+QI5uB
WIla/pU+C7b9uW0g2nCasTIY6DzJxqip0OvIVxcm73sNvf5F5LAjE8u8WJPE9UuajwboCPCeD+S4
g1a9r8FaOSVJfIOa5LkAfY71hUe4TkRpWEQLEY8CxXn67UOgrCdh8lVqAxN1qFICCsprk/BP9xqa
F0O4V8foSjSYBM7M0PjnyE6CKdoYla/w69YUJ/KdABlD7OjfFWgWDXrDoW82uI39SubLZQoMvlQ2
fe2fKJmzbh7cnBwnOhSOnnp2n4QAdBHZdllq0TR4HIT9R5wQhEmjGjsDDyfAoDi3W9xfVplGr7qr
74Ixo0fB2NukfGY9XiQwwrP1cgzcwvXGiaxOXtyTleUxS5UltZoUS0mG3wBo7h56IJSAS+3TTddO
Lrly8WrFZEZkSZmX+f18g85FryqYfRddsvNyfgz/5FX0t2mchZXH1+hE/hakwvzWIgnClLboKkeP
YNBSC4QkziOOMwUBN50UjnoKSVGr24XFwIUhtrjnon4CUFUrF9/gn50N7HZ+oyUMS/X/d10oYTvz
uhj5diXqXDBYuQjJYAKevQuZ/e7/oAAN0hZY2vot2ubNMX9YFIKSuC7FpHFey4z1N/3FzsRszo95
QjxYa91DZLvK4oQtYOaJf01IJ1LQdhvBE2Pf4d7ZoNx0mtBcJMGzuufD1ShgxGoZ47LI60jJBejJ
7dv5BO3FAsgUUOD3pTuPuemsp/dFC3tCRNGiH5eGQ+rMZBCGYeYFtR9vnd8M0i5IYv+4fVyO7ufh
7VeNFWtBD6QzbZpjpqn7U7vnAvL6dR7prDA+T8DmzyS5cOPmpXJ6HJXK/8SxFaZz+yErb+9vmqsl
cNAK0y0KZ3YjxjqVUlGzj/0rYn7xBLLu+5MHr424dGf8VveJhwFs8zIRZClq6UVbP5dVygGjv3nb
jsDT357RPKOQh0pNiYRBs5P6CbXwS1FOQWOioOqHvPcbmeB3LZlW6QROrl12gnT5O4c8sUwRCBVv
imSeigwBeYZsH9/6ymN/Dws5TYoDr3YpXHDGAptTTrzGqkr8vDSXjnM8jvIbveVoxq22ssoiA+VI
1nEv5yNJSIdNkDaCsn+lGFsW1J1IyA9z8FuVCfC1j0ebwj4Dt5pOMhHJef630yBRhcNoKUhJCM5G
TXFHUdT0JSX4PY5xyEta6OpW2MqLabuVLHgiTnt2j2+CLqP94nDQjEku6CQ33jVlWluHKcVS+3vY
x/B0MbuAI/edab7rEyE5XBuds7AiER6RZDIW5rVI10ixiFwJunjdQXW7R+e6Uhr5xYPcvGvtAhmf
4WfV49OqAtYpvyuOw1c3EWxqMUiN08Kmm+0v5BhBwsc+03GMyczqC1DTgI6/uNDE3NNPjKjAEwBd
q+Zawrf+3cSkh5bktHnbloOx4XL2UN2HLjc8D8tBbvPijU2fTRglLngUi894Rl9VLKr4bz8MKKsz
rTmQF9Bxw7cogZhbXicpem9btCBxj7ZoM0sOKpLwBsleFFCRxwnf5EFpS0CvzpCudtfkzx/4e26Z
/hup5dthcX2anUoI8r06dFNDuy06dm7JUjjUpzr965GW9yiPdQj8ROfZLnNz+iLHyvTvPq9ghkyJ
S5qKcwzcqLyye+mHd+NQw9lU5hJn1PbAilDYo0cA5Sr7OuAFDSfbzERq+n6ugBbJ5pwiD3aT4rwB
jnWuzsQ0C8yiNwss1pECMjQ1j9flO5jsoPhZ9HrOikdUTBQZ7DB6U4lT/kSaiM37U3y1plHKX6QU
/dp5rTnAIFwbqdXei8Bv8vXnb3eU8WfMO6K2IAW//YXlYZr8ajfiP9nPeRFqMqlKbszaPZMyk85C
/WKJj4aq29FITRDN8J5AuhXvOg12euxhzIIbfn2ce/lyQvEsPhTbGlr462SMUSsJoOcpMr7i8DSP
4dLoLWMfTCjYYNrfBM6ca14awVfcxgYVr0kOGVJKk4DcitMLK4w+ujIZXtlJgMRDrmpGo+J1s0n7
gHTYRd1FY23pWRjZOvXOEg1xVo4wGVTV+MaxQ/MWqI7PTLhwRvh+lnS+1P/sVy7O+2qyNYly5F82
c4G3Xt9UZbVHT1lbkby0lfXiZsJec2pfku0atkCL7SGO3UCSRjXPYV7RFCRVFD5W/zTLwPw6Eck+
LThlsPbze9DlbvG3weK9U3LVN+vuKlkBsnDrhp5uDdu1xiI2w0ewHA2gh+d5HeOP0sGExihXwRVf
cHGGXx5eCwEOaJ9k0g/0SlsrKD/0Lxx4Hm5BHAMAs+BuMz3etA1ECXTEKQ830E9+GsD3rsCr69g5
gFpbXVWqjPz/U5V8j/rMT472ypbWDpFZ1mRWd/b8XF9KmUq4WLfrfSj0WIbdmZcyjnl/XKIFupU+
rRL4tzwlfqGyb5gDE4j43LQ9pkoRMfq5kww6GMowP/vKlf3tiDtIneKZVcZ7ae3HucQY4RoRaunY
QHkR3TiHgZ1xW/fw3TSN9libmYR3ougAtzji0zJ8YlWO+6yAOb87aPwzP/nqxQFR3sxXfuTxTmBC
mxtCZO2HhF3+3FprykDq29CkZkmD1hMy7gOeWC9wmTj2vHpbeS4jmURguyk79avMTTbEN8A6AmRp
5+SYMmqAwsquY3TykBKhXmcnPliXvwufHjlZaby1Xuw/xgVgL7ctEnoEFNXDL/+8rHyOJ0UBkjGU
jOpYySlbJBlnKx6L1rrCb1QNVhGNLZo9tAcizRhMPNt9lNRPPu5/YQMPiPtNnjvWu6o8OKLowFOy
Yd8V2GVkEPbauUxjYPd7W3E0+j9mXZWRVA1pRqCk9XNcTsUG4uEPV9T1cvC6EVhSaGi2ytz0ugI6
TXIBkbfqcqbrjS2442odWZVZpwUx2nFPu2sQBWosda9AK7HZnvaNb+5dd9GN7Qf9OPNll2NzLDAr
XCIwGRQyaic/IHs7dISf5Thk8JZjQVjwBnn4Ubf3ZaC8b2UQtbbU3K/Rk478GTgDk73nxGBA4PgG
Ck+3nTKyz0pJ9owZ0ioGin3Hy81Pq+Ef5I9C74MMsB3Ex2weiWpKlUVFOqLkFV0vrTjMf3JAPjWw
Qfl6PxFBaXhD2Iv7HL11F3+rFlbjQtmre/uCEdVpC8vsws/WxxjoanY9lEo76paQqHocaqaexmO0
7mjTfCbjlj2hOM++rdJoI/B6FMs5yz/+JAPuDhrwXQ3gA0egx674j7gdquvbrh5PBjIqWjemu2Rn
vq3dmOP3jaKUQGafchQwY4IPqUueV/90SnPvMjbs6GWpOiJUrmz+Mj8m3uYQ/IwSvhrB4LCRxpSV
1nhgTCJGQWEO995mg/LgFHXIYwtXM5IlajyETBuBEhecyyRP1+6LXlR+HVEFBSkqpDb0FxpmUxtG
zxIP1/Zr3oInyQeHz34ZiM/nttuMco8Etn7sl7a2IX5NlDgczJsAlCXOTGJbysV0AkjUP8/52oad
0m8m3sg6Q9s7uR0tO9cMO/O8EIrj18zGalOMw+HMpXn31dblYFcl0dr+3nVB6w7CbCOPMhYZ07OO
WQ1HiefL/oPHSxa77Hjo8ya+/LwAdLQJfzYgp4uCu7NMEYYKN2vVOdNggBrQyRZgnHcW8HZpjJQl
oSd93N/6jBMRIdBc4VOYlLpEv4qbv2nvW200+dT5W/aiITgb7QM84q6n2zCZLyyY7pMmSFQSmWmt
lOBYRuEuBFRYKKgjRKuGz0jn3jwhxvxXdd68J7UsLpJSgRIjg5MSn6tUg3JdcAE6R7dEN8A3xNB3
nERpkWRh8LDwaDlwv6oI/9RjdIJlDh+SYICRgU8I/ol0CRTwnHPtukfnC8wCeyAzcj3tRQReN4Qw
65mWDjB6MRG6b8qLm0Rv5OzpeCHSJeFDSdwshKigb/CAeFUpGgW8MSpKZscFrLb46kyNTeKT0Zs4
zk3KW/NMep60LS6cKe6r9EN/3g80uRHqzOQcoLAmWXOOtKKK3MsTyhMzt7QXwxAwniWSoWybLF/G
NaOko8epFPGf3lapQIOPiFZQYzBDUqcAfgG22GXKjyESKXkIrCidhlwzAVOEQzjlpHamPXBrrqaF
emmWiBOtE9RqkArcl7NQmZNN/rnDHjy2VOiw6s8DDWyvhNpbu3Lgjjo2HN7d+Hpwzzk+YK5D0r5j
zQsig53Ruq7FDMwU2ry+Xf8hUaBR5boZqoq4CdGPD8dqX56ZwjmatPN3fPlAVQPuY2alSfxWIpWL
/FNkm65vgQ5fbhzrhRhLw7nyiAJMr5K9u2kQN1TNzXcDJBiucwcrsvj+0bjkVueiEh+8ILcRXyiv
aQzZC/diFhRcRLenGTsRZn6h/TrhzgL1+2IBs1olEwsRZO/msg0YdlCExc4N81G6dIsiwNMlT50c
cOEcS4QTTkeoE6Fe/1NS2WuVGQ+DhUiRRO3NKHULnS6todeiwISN+CMMxQJVXu37hAvLhWDR+BD9
t3ubny07gvOhYfzV8fld//jRS8N+Scoi7VDoa5Yxk/YHW8de9N6s6I8hRyWckFS5Rbg7lt8jhZhn
OqTT6TTH7xlhf8iSU71IXuYrkJ72tJaNOrQyRh24kSFCrTAHeZCUAId3oaeC1cvaihroFOgkT9I3
XTeMTZw27i9Eh0bUZoqbB999UAhW/u2ip8Xk6lwvv3P+XUkspqcy4rGqe8XdZlxO4czJhyIopgZb
AfmawCDoPmNwQR+2dDAS0lhY7U+kNvQNpl+lrSUaFAdhWODyzpLQVaFLIhbO1xRxK4/iQOY4jvB+
kbdj613NcAwswUgkL1lSfPxiFsjtuvZN3G6+692kbrEv9VC8QlDdIEc3kiksJjgeGlO1bhmaLsFf
YcmJ6OXl7ZoYVdqgUzh7g6wjCutrCAR2AeTOMu2g4XnBwoT+zKrq3a9gQIkfmgnuc8/oDkjj5xuZ
LloR/r8diMP9ykpaA/bkRaBEGrzd7/bJWciwRaq++3M1d4ckqTbExBo6n8wlm3P7LXyVv45c3L8m
wZNbg4kSRijHewiFFqGJJ/ZqVjwfATk6w84ihbD+HiKE2s49+Tpsf4EheuaLOTg3Quq7/5aP58O6
qirmYYcYLpcFky3imnU4z/T207K3rl6r4cmuiNgESJ/DMV7l385H2dWE2Wqrdm7z+78sfTNGIjvr
ytqZrFNoemZDVnFTQGy/H9t2FXTpRBzHC38SYO+cTv8dHkPD4oQ4xW3T3UDV3aOE38cT7Z3Jg/IH
eR9Yi9qf+CD576wAb+oh3jLqurPIA/k1/0+6Xg/ohwPlg6Yq0Ss22POZoHMI0zCQx/3/GvnRDT1j
4WyvESTKVyJreF2/D1ljT2SJ9zTtf9QDN0ZicgDUak0Sgy0E5CnisFHFeCaAuR8HwRRpCqsnPuzI
yGW2NF+DHbvRLZjxs3wk92BgAq/ga8YGIBiWT5uumYMdtcEKL2X2+cSBr8haCQoBnHqMUlkKQLiL
Fdhws/2dnA2/IxeRrJoxr7HahyuK7xk6uTMLcdwAfTPT7xFT9hSKVsPDq7jntf2pQvHqKQoy2YNc
BFNDZDrFiGIdkuoWb1th4jR7+4hN6BIW6VtmF4wwlux2AzvAq7aC3BC/QLioow7klHyBeo7KiiRk
fAIzkRGx3muGwPlDPPSkIbmWgoHAJYjPHjRlcLa5dHFcrQ2IcR9X7DILo9Nedngp0WrZY8AYY65L
Zv6ov0C/M/PruUoftrd9XVDL7WKV6f0keiTWc+sCvCrtEldNDcLsUy+YLCxMomGLo9t6ORqfgS5w
z+Sk5TbFIIdm0vr9h61G+KG1xbgya+qNWU6c+0WuxRH49ior2amFpCHPBvMOjq+NSkOF3grNf9FU
ZsBNj9eDYcA3MErWTOjWis02oNHdVnMnIHwiEC9VEARYmEXDNsmxNtpb1ziJOC1tGpa4zE+IcQA6
mgsfPzyaObUqCsg8KgrtDdMwyeaW/V5EW+B+Gm6bPtRWIqkruKpKQRWx5tFjujVqF6FGCD3b7vXi
sE70IINUyUEiWV15yYFNr6fv4btk3T6RAa6ckM34s3K/MWORCanSOTF7JHChtUocfL+jBkRLoIlq
3VTlLqBbrhzDRVBj+ye66mGQFUHUIbnbHb9aNjpfjdAmiwGKffwt5HNagPOcACPbMga4YFqYfbtK
nbHhUOZWMVPGeTSDTwRA5jxjv47Hld+8gSt5kKnWQHxdSNdM6co6hW2UxK9T/BPGXxrU1lG0Fx1d
AOfz4CZUh/2TLWDh0RLMtjhEXwnQmr0nxYSOOGrrtRE/rOWcG+LAsh7XWtSEJfq9nSrTb0Zz7cIl
tELBomGnjpwCURyOOY1oMLEGknvCEd1u5tPY00moyjYAbHfblg9j7s/vfb09nyvZTAU52ZrcSUyK
atBR0Y2nFxPjKLn54gZcsYJuzyItLDHbqdCWC4rpi4hYDVvAdQTobSLPbc4Zs35o0osT5oGckAxI
iZCT7hCKTExGIudAjqMmEGTQH/CC+z28q8uGNmls2e8lh3QKTIlpScMR09oP55wFjaWLcmbQd/bf
PiqbqfqGIo70vmdSXZs4sYcqmm9e/7d5pg3br9VShrayv1lYJaweP0RdtVPrS+qDrZf/Q+v51wQj
+DebySAoH3phq2DTHPGJf7/Hr+Lx287MidOxjqhgzWZ+29Tyub4v68mvrTv3y7LAbdv0IeKbBLBz
1MiPhmVvOv1wqM2C4BHVtkMiEVVH7TKiY2NOtwkYsgdox8oswlUS5tzECEZ9kkIA9/yGhG1oo3e+
lvWX0+osv5fRC5wbEy8XTkiDq7cF/fG1D2jXxMcRd+pFC9Kx/uPEpiNuKHAdTHh3xhziGFqzSNVk
2K0wZeV89oPLKBCLJBibDEB/3AqoSM6vqkeXnX7U1ERn/Ba2QKGM0ea+48/bzb/Lt5vuzQqAeWb9
m8CsjQav1B6pzEzuBon9U3Q5mC8CMuMgH8Clbu2pSNtui5NVNiPEatBIzfMdY/GXCJg78wndyt74
yeTdrdLW2Nt6g0dFfvEl/LuafobvsxTzLxrNJJ0Q6c7NP/ZNGzSlmbWA1CeG6dHnN5Gh0wLGTKQk
aWHweXFxrftF5rcWRysutuWZ9HRLpTTC51life2Ns3pU8URl2ofIP/F2gRn408itlPRkrad378xL
SNboBooVooWqEuGfEOTuMOTRaOgtEmX6WcYsfUjs1z+NZ1s9DP21ATHOkxVI2SF6qhevxdk9yTAJ
XuTBnU9gjDEu5o9tZrM1QwwyESPXEa1iXW4IVt/Kmao/+Ntd9hg4JR2YEt/XP0eK4A+Vrp5FdvRj
+4WdIoQ6s5TyElBtW+qk4nYZEkKSVOzoZT53qGsvkC+nAR/1R/Zqwg9ZPcTpeBBDS71fmCroRfva
5MOLewWGSzaVD37UPxBtn8vOE0zhcPzpPyDLHk3lUY48CqLMCLkDrtdZC/1GYjOF69VD0vuPQ3LV
8kl0mALRfyqefuXHoGzrdD3EbWZafTC1SnUoIeeV0YWsMylTZ6XVbqPLRn/K2PYdi2UgKkAc+SC1
J+zLd0X5WzkC3X5L4HTMufZtuhGzb2uBovU22ucT1zDeNCHeyNSRWNQXZaTIam1YmnyatkcKn55c
bv7wil+dTUynluKX5Ey7t3XL9s0ahWjZehHrsAoK5GQnws4Y7qviwGMElGxYNIBQG7l7rMuEbtFi
6oVZAJ3vHxq4EVzWX3x2TH6bRa3j3XhRaPDZrnO4o1hbqShWoKFAiWymh8CSX0dWUQj5viXwqbi4
9m08/7eBfgpcYJpud/025X3ZDftqRC7BG5Q6Qn4D3r4fY3ETtHnUFImk0q+JG4xmJlE3UxzkNFNp
syo8mCNnXPBd92n+Oz1B7fxR+CbEIk7Pww9+ltyiVXx4tSsvU1cgfKVpyotAI46BsIbm4OMkJ3L7
sgGnvo2ae/Zsvc9YaRXZN5tQB5Vldc4CunlSx88499SXu8KLWOStnhx4D/RagmTGwkjKBXX7M65W
WWg9urbUy0vhBe6zRSrb2tTcI6kNAlJlMNzdiL9vtvkhzDrkcAfFC5QqwwFUR28q1ebOBt2pz1T2
z2qpMhLLl3DLQLCaEvkTm9xKL+FKJaCvMlvQKYXmrq5YKmxKcQdcGZWyyHjQoIarbQJnJ3nTbVW4
ZOdzsGG30wXbbQed2Br7nuaSiQRJSyrLDkJ0mlrMiruTZF1/fAfeGUbABXaLAQxe2EBsDb/KcOz4
BsEzpBfD5L/qNeosfL/1vcH6IvOhXeLvST25G2We0CHJhlrrBtvHQRNfsVsISo2Yp2sz6Puh9ONU
Im+jaz0CjsG8Tk80mZQAEQDOJuwVzXEgadP+GeEvQ7dtQHx15S1NZEKtI7COYMTb6WkCDg0rU1YR
EybVQQV9yT52bW2WkKGnJyfs2JIRE9TKASzc4ECc5WxnSHjTugwGOwnYQkJHmwRm9tZp5zm35eQW
o3fz1PO6xKH79jX3Wl9dPtcKDpbAArgdiTALLqgPa5GGTNBnttamUFU0iU1w1Q8DGif8KsA6oQwY
MkKMtw87YUDzHNbR5iVi7YosuobKTWzWB2uM0YwZ4ansDvat6ONeUqoe9i+V9MNM0plzoEl0jE4M
wDmqLCfrbWYxMUwSQM42ekaakWd57BFZcCbGIPnusaPdITCzBMyJ+l7M/hBGQ4mLctRf7+2+4WCx
8z91PyX7xYOlkZXN4eNjAOMWjZuzzRN25tz2x7piIN72n/FX4f74ivzKknZCCsE2exsJAOy6Gc6Q
c5OHfqvjGpLx168+ecuPrDQGTofyWKlSH+MMQLK/tCXjscFnFVhwn4BMWHwRh1B0atjKHtXjOrv6
w5bQvqay6Q0OE75m/O47oZwyQ8Np1I5KJtjCnnhEolnELMR9eAFe2MDzTMz7cklv/OUIEn4Knm1S
bXJj9bisSTtfNVSBOoCgTVEl9z9fHdytpkgFTBG8uOz248UWaB1tTc6tHGmFn8J8S5gY8jaEINjM
woO3RJwt4/Vz41sMFtO8gZhJ2Z4L/zGx5yG3oq8qjNNuCuNb6OOjAAHD+IajJ9FE7qEB5v+BqA1P
2ZBXZDok1UsDXx6sAbkB9b0/4oAba6D0KrN4fCLV2kM3BIOLGdHVeC2Px/Xw2ZCfwBy+41xBX1ga
rE6k9PLV2nt+88j8jJh1bvs/aQIh/1y4ZvhGRP8EoeDSdlBb9NUCnkr3IuMiIHJEL9m2JpYQH3p4
UExDM4AFeMZefxvhVdu8obQ+fa8jdFm84h/Dd92YwWUZN7D5n5/LrG30eZ3T4kIzfw/8XqIT5Op3
GBsNqiSEF5eYa970TcmFHacRshJNIWguAIw666wZkSH7IX0uljrDTA92CRfy0zCmBmqapqUleUCr
jDIlMefGq1Cef372wltK3XvS7sZDvRnG7oc6q9YNRetHCzPl1u8i/vkhtXQgvo9g21CSukUzE3PU
xOwvdOPER7l0EWB9YFbXWeRaAaMmo1qL97wIh0Ipf4dP5CxKFVtclMfCy+TUoSk8BT3UD/HMRCG8
jl1Zk2deIQ6WfQX7TgxTa9+uhje6qbEAI2fWp//cxomkUcOqJF0tgiPKujThi6VOce2oR/MgfMBt
EPGStiAIe6KCYMfyLm2QjckW/nTjgCdLi8jATEfrMEtxL8ysxfVUVm9W/FIc+cGSegMSXU0MJ0dw
AxdvNBE14urf5ZZPoLkwvmU2AlaN5MUHuquMUn5viw2Yxr4Kpa2D7oWV4lhoGs69G1JntWnYJiJW
9mOk56oMyg8IJLyCyGxAwJvVac3LjFLJemGPYB5s40WnpHVDYenR0cX3JOrxwSc47bEqnSaRaqP+
87fhZg0yrHTcWkEUU6UmT3dPosiDZG8m3FlMsAyoBrYz+e8QhrbQnfd+O748PR+72YShH34nL2aA
SuVm7orL1TCV7sD1sBaB3w2yHhjL3X7lTeoaraW2hh9+m4BpP15WBQ6Q6jWG080LbvBzUHQ8ND7s
qQSzLwXQqbOdtQ3yOyYfMoQOJfkhAZLA/DtKHjhFE7gg9Ju6FH8/MMSxt16qXrXKywIt4FqKFzNi
jtgMk2W8MFG9Z2w/cjnZ25iik2stIQLa2KsUe43nbOr9pL3fmt8cdu67+evDVrntP9JPfScot7/L
8oMs0A3nrAb/N01dDgjGoJ3c6lWfJ4lM82D7UcmNNmiYBmiuROxS9lvKLoQJ0OXAeIu2SnHCCELE
k3d0q4WqbOBrz9lL5QCLewmgAt7fuVhFMDFu0+bqoulT0xkqwKefU3dBp/AD5aFSt/1fMP645YnS
XQyRbQZImKcJmbpM5okXNv4bpM6xGu1RYW3IZ+Nf20EbHRVZcPuviLh/xRzDWbzjnpSKh63R5VMG
Nx8eJL+Uk9IRukTTqVop7AoDdnMR4t6cpaDXNYZH9ec+10FJzTuupCF9kbUrDGHgZQ8Bu0zYgr6c
B4pRvn4F/PMzb/A+S6TriLSzTR95SzuOSc4Is6qnLygBrlsoBiKfwEdf83muY96AYoZo0jIfckJp
luL8zv3KksuEWySC/vMsTcI2chYi+Z1eypqJWV/6k58JlEEKEuJTCbqBgS3Ykd3Diw/iBTEdfAHE
WvZ2gS61rBzNfoCiBebihxLeObJG6vcUI4UsXFhFqDAF6vW7Zg2M7HMvJvQEc5Pm+xsXaZEULsed
Wfj9q0sOB837rK6Do9V/Pyy039eQLot31yE+nCTDyU+AeUPOpsk7LSvW3gbDqwkLBd5eJhDlvGhc
h8VqrBBeaq5q0CvFQenYMhE5WQpuC7kZxnDBsRMDionW5hV9ltQ1LhyqzGnSR31hhwFYsAFG7d3D
H3aGy1uTTfe6871wF4bbViycKYS6XgTqgk+2pwXHmNQqZiL5zEvdbnurIsOZlVW+GnVEZz8T4kUG
3T/lMuj9yU8mo/WM4oh8O96qv+5GsZrSnwYos8fOoiTQtOdnIv/5MD2Ar4x0xMQgT/H7wE9DUJMu
qoUs4Ucnen+WWpllNGujHNqKQuxcTG7QLK6rCq0TkX4ibM8hjlIAMWPBBVW8/iiAGJ8L3A9uW2HB
yO21b+ZluvboMdW4fCQA0Xf4T6SSc7VGL7+OuDgfTWL8/xj/bxMv9Fs9peuBygK7FUlWPgEwO0Ks
m0j+xfeLkv6GH3M9BeXtJvraX68GwX7tKlymckj1x8e96GwOE/T7Poqs3Yy9Ypvax6TeUmRPWNTy
NSlIgyZiw/cfPwSlLzINyyB2wHs55dQcHA1lu4WjPdnMtCdCq9uHz56xCXzr7Ct15LulKVcj41CQ
M6HKCX8iCiadHBvShLe1Yu6gC9ExMqAI4DuoG8qAHIVJ7C5zRuTJWcnvdN/9RyJ8ClFNmTzoXgrY
16BKcrIwPIyaKBgWb9SZXy2Wa0yeE9XeX9ESiXxDvqOpToL0C6KGBG8zhhPqar85cdc4kdIIHWWS
ZDvi7C0EEs3+6WUv4j9bE+/Ad5m8M/Eas1ztEzqnxdirbj8CcgwvYvJlpGrNR05/licCapsRpWKr
vWxXJwg99RXh/bsaA1tTX03o3gfm4wmjjJE0b5+dwnAAy4+ysvi07uIow5EG/Gws/F8fJ5vCZGfV
AmlK2fBnq6tUl2/XVnjqswl/L6xsARFfLhK59zLLeE+5Ick6X0X4mMefKrnQvYqIANYnC6iaKwDe
C022jePsMynATgsVuHQtYL3GG3A/+sndnDNvdSRH520t0gSrx6KRGa4SbvH5OvjwMND72x3dM9uL
CtM8xiKQD4bC0Pdf7qIuvre0843vT0ZL7J2jl1Hh+xMxaQfYgF9U2P3f7jVOgzetRoRvSmdPRglk
lsF11/tRRTHKKI36YoDhWc8HS6j7rsRDUpp2GLwx3w0U0v8azkyb4jWtgTM7jfmdGTCMluuOenUH
Jc1GVYLiPi3rnZBmZ1AcX6tC2h8Mo+UvuEK3gV3Puh6JwSXYLm28gjx0lNmaYMeUGLXDRVLcTnpc
rO+N3P3eisxWz8WHldWPxpJZiSkbTyX3mHsR5jl4m3QTqrqhuXFSY+PkQI600Nv2KAG9N/+NHEvY
HxqQxKoX7iesOUeVXhqVD+gYB3o3UImk8UcxVx/jRoIYMNMIlHOu5C19pPxzA5TnQlw1wbALuQlV
8eHk9XEsIp/1aIwlnQ6K3CfUXDrZen/Rb10JwE0hCinKdztg2BPKrwDIwO+PPdbStQ3yMW3vdtIO
EUUgpFfEJ9xjo+j0DimBunmY9XHngQkgWa35l9Bmjwsks5ZORWj/QbQCt0y1hYEXYAFY7gfKpg+3
JlqR75bHE5V9iU1V08W0bvlpOgXz4iG7DLBFLVfS3cTQIUV7uVtMxQ96Apd8eNNoBnzARoBPgvpT
MLdeqZY5Ib9My9TqIfe8pyqgK7eja47xicZC+1AFbabBVpq9YgIUluKQzr5ZH5Wll2z9PZp2vntl
PCzYmy0tle99CSGtCN5GQMYNtfR/QD62XvrOFzyMghpwxm2jqfLrgQ2ACsUaEvJjyrHqIGxAxXx6
gJz5boPBqVSSnRZ0lYYgu+g4pL88ToFMOyxCDy60EEvcRU0KHzbX7IsxdTvvAYGWd0ahsyY9LWQF
LGCazjJfjnILPd4eVR1psr3ZUdJBld0PlUmOfgfgpM3E7sF0h6EovoFWZ+QbS9MQyHRBwTuvu3f0
zxnCTs8ff9rU1z4ZmeMTQ0OkltLYa6y3v0LNIGlVwFg1BV7fteJDZy5vok54kN6Z//xQf2OtjmTc
p2WBr9c9Zo7g7RkKuKrKG0Ualihn+WaB/lFelCByk+2J1sM6fLrPsUaJPRfalRknrtv9lsBih/FS
pjC8yGCdLFyObbvP+uOJ2724csGGgFS9iLlsV9A9iBNoUD0Vtg3GvFxjeIWMbs7cWUUby/mH1iS6
jGQfxCpUQLTAYfIkUOBGPzUVBmeiMvoKC5u0RA6/Ki7yVnMZ/ZbcE++e5FKS/bbi9VJCYeWFbW8B
Gu9JjVsjbuQ2neqaf+bOlKVS30uClvlEUbncQMvANPaRP+6bixPRQV54WAUW0hGBsPzGmAt8ZLGP
df4U/a7qvWhFfPOUxUdovjDhhoV2Ev1rlQC74xrJpoQtUGn8p0qJWAaY6vCZ7rg/1T5JvQwWsJpV
xaUlsKEIUGAsjGkWsNoOxBkecYuP++s7t3cjsmu5plDwa36I6RX9RSVDlfYe43sXW2b+LODCq50I
D86YJ8oz1+yX1XYL5ZvCWjV5ObFv7Riwv8xi9sv1G6lIHUXVOQ1Q9w9UlIO8DAKBRbQCkfLRHaXj
yYJqzu3iHdk3R/zX2+9x75izTLurdHf8YMAVR/nDG/xd7yrDenLkmyIutX5UiXr9wYzbzkQGZWtC
Lkb/Nm71DrkqBDtVzCza876PmKfqUILIJ716+T6ZJkMutcP0kMT+eN7kKN9f/B0v+nBjduhEmV3M
AHuaXhZsupsAc8JG1chCJcRkAwSU/IcaATWtO546uwTIG/1lHDrwXxLJFN/rMTWpnTgjTfTJEemI
64clXK2pPZO4Cz4IoYaNYGyf6ijghNNDOxz5r1beXEokGL4D5hHjQ+a1ioEYC9KaZIAT85XmubyW
wXM2v4CZMen6gjXxZcGWfmCoxIUsKPCFEM5qCwkOYCEMxayHV5yCy/RUl6CB3YQQOsGRL3gK66mv
MkrwNPEersF9iugI0Sb/UzzxJ9LWOnIqF9EEvSlvMwh8oblysYot7RVGyLO2GjLVcg/eQh1+id3X
Y12/c/iKoHavT22ZZi8EXzHUJz0p8ex8XwwldTZ/o9bdcW5lyr+t1RBy06iH1r8dY/CLHFBXKDja
OrbQvma3303Z+EPt4X/I1nJ9JpYr/bSHl+UFouFpqOiw6cntqi7+Lct8sbE8ElfMxpG0oD2NWyu9
UtnAt1Ogm0jra3qq1cPzYWmkHfEwcSTn1g7ZzgoUD1fywQ9TgKIDjGHwwYBqwT5DlNRSxRjic8Rx
E7a8k51IpsXInkUOPmtubMAJFYugoRP28LrbSEuZau+zdFraK1xwYeeU6bsv6MBmgCAEMCHhqOeT
cz/zyfx2bwWBQHUMq78gHq5fkVGKXU3f8JRwi4bli2xUGyk84jns3scR1nNCUTbqbedOv4lFd+Q7
8lNsSibr9yZnP4zD+jvacjobaryYzDgahNS6r2vLpRYvJY0G8VfbIHX8C8cF5b4Q7wb0dZvCSB1d
rPVfFiQznJB2eL+UX1plB5YALYPyLIhy4rf2Uyx3AicY1OAh8iquoYh3B2b/kMhIRzTFIlmYYaAL
zI39gHISi2AIGTEmMePqp8LoRfANoMp6de+LSDI//SEhDJaPy1GtGZmycBZbDmYJojTxZZwrvcQu
/N+y8AmlKmrJ8VXoZi97fDd/iQcsjtdeLvFfOIVi/S5b5JxyX3A9D2Kmbci5i+F3jkJxE64YX+Jr
e6aUFA9N/xAj+AbszMYdjrIlYdk9AA4XD7mrMSQHHh4BkY08B8PvbFUDkaO67clBX5wGbelDE3tz
Ok52rbdH5U8ulvwj8HYEqBpMwT0GFGfcS1hT23j654Xj4LN/KLbmvdKwc8T7xiPjU2SoJ3ifZiRP
CK4x3g/OpgSBL16ltZJWaDJRD3XLeq69Hf61X59qPn8ESf/14rIBtJjjp3aokRfilgEGYU06W1Dk
pIAvTnVAHDPgb7gn3Q1HUL+7ZiWOZgKnt9bHlrAmCxs93Bqnhusnus0Ci04kpWABOJYu31F5KdCz
i7leAqe1ZdAa0vgvTk97zy+S2fbqF/oF1Ouf+J9iE3VIbe5AO2fTam7GUDGB7nICX2KRvjpLgzQS
qyxbOIVXdaVRRoFsGLfnwWnqpGsHYbqumigFb4ViMMt9sLDEOy1zyqiDp0MpzvS/KnGpJ2kvW2RL
O0B3G1GizIFs7T6lArOwIHSmIJthudSyC+juLgrl1FbyY3JChf2d143O9uHara+rML50+IdFjtwG
WU3EO1LYYkMzET2l6bBBo0SkNs3gl+3MeBZfI47k1JLu+s7FgGLb3HnY6FrHIXuSxs0YHZtNBM12
0IdyplOJZH41ieranKrSClqlyQ7oB+wUTWjuEeUOFfU8jxt19x0TNwRdHluJCgVHIME9R53SSaOp
tcWsZobB7U7fe8K5J8YJCENKTUf+vOcHWFDCWIe9h8XJEkYx0stuaj5fW1KNxFjfAieG9SKxk/wb
ymGCUe0SHoXLaXruayfIAVPy+PNRSPinaF4/hIl340SX8UIt6Fq4aWZSxBZBEEZmMpWlteNuSMU6
0CHnUwBGaDO+/6KQQQCP2VQPuEVmfCxGhbd12LIpzFmuOXubi5i+DQveLlVrL8raBf9G3O0b0SgM
MV87bSE3nZLh8b8d4BG4/zQEDgZkStq8sctNYmtVi7ZmMuVV37I2gBW0ASd3DYedNewun9gvpOt8
k9HAatUOqlBAhZRC7djhDTvq8lz14tvOXKb86GqbFGXYDFQWuqnYIHW3gy23P7kH9Rdcvoa+UacW
2djJyoIRr2LHTg7Jeo+AF1/5fFcbATQ/dsAnXX913xiH/vgG9k3GFMzcLzWNZu5xfMxL/E2ajgoM
gqcOgamJT3PLGyS8mxwBBl+zgghFoQaizIfcyYz5mZ0bhlxC8bi6cHFTr/MJ3zFN+p6UqLTE+BgT
AKTu/q9cIIP0SExgc8w9qcGBRnljIBsL4lV/eLJy1KeeDlEXRjRgxJDmcwnAG5PA3lxGkfiwFU5W
7tBQLOe71Te1hVUMffFFnlkiODY0JRJadj2NkDbPFDi1DBu2mtLCsxclpf0K0noh1YzR4gttr7kU
2Or0XmmJyDdpw7lwoy1c7sWfU6wr1gA+3SiqZg9SKaw6txRvj8nfFqFvAaEl/KcjQVtAbP6DcSt5
XBO8Fgp1Q9xrkSf03K2KYxKCo4KuNc0uh0grQ9Kfhh1tyYH8/WWM0wxm+r+4odOzH5c+EXbGbtjM
mfE16i/Dil137bJZuws+U96YLJyqQ2g24JHIDkwoUTcLr+dp/vEQ1uilctXKeYQ+MXaUC0JphdhA
MzE8tnXOcjmvEB3+14/aXPeIDYbXPNTd2Mq0RQVEF639RWb2UZi0nDCqJHD2pE25NgoZswMxeicT
LJ29DWozMeVoVBGHhQuPUsfLWItO4hg1cV5ZEjtfgIPjgxTyQQuB95H5nhiy3mRjcK+F5YK7Yr7y
jNBxK1EqHYQIwV8otDxlS+mEeiY33FX3ge4GEVUrhppLP7hnjE+t7E4KiZyoNkJMwvjpdzqe3sPU
OLznimH709/E4jMvjJtZ33LJz/dux73DLAJmlv3GERc3Ldm44XQc2xTJGE/8i92A0u0f1DL+bIHB
iRs0CWNkAVUw0lheVzk9SDujGGcf4H67EYMHxKy3/1iAoZ0G1CYYIE4h/rDOXooD8lD62nd3H8Fl
3NXbcSM/1Fjwl14p+XVSvPIBHwyOjtb6f2bpg0Voonwr9V7nz7cQGQjgcPRgXmBHsqHigBb+a4jG
tfHUuyOjZMlUIxAno6gsP7dAUfvJYusLWEAs+GL5hPsDYW2bKQ3Js4rYu6AehNIkZs0oZ0rP1Bxi
W0bxaKe3lDpIEicvwXtAoIVBnFPZA5ctju0kC0oODEbW09Nhv2E6GDMkHdMHgnFvSsd9+v/rtXDL
XGiC+hvgGbNGx0hvEdM93234O77Vvie60tQxkfcX0KOGqjE+1DbaQadN4a/vZvtS8hicRjQErLLo
BQymdnNLCnUiKutkI2Z7/sJzCnlgsIAiCQMuZ0uwH8hs2PFPgkCnFWxW0fQv0K4Dym1RJXfCtVPx
0PPZMYr6lyp/S+yThka7ifmAe25rAZdAE7d34jMB5C7YuDtM0P9NH9NhWByyCRFT8vPHHmt8Qp8S
U4f/X7w2cgkOs+k45yb1TLlFKYhNm653UcYs44sX6EbUiMCCVtE5HaH2n5nyF1dMa2nLHfDpoA6n
/a+ey+Ght+AunfyBfGmMyDSPEk9Vc2LxJMGoz7uEK1MeLuAPOY8VqsK1k+0iyvDeRl/vfCBJDpwv
eO+J8Q+YKaJCBiJWszmbjrhkX4sU5hUNojVbvw2P2UrItaGi06Le/AGHxoi8L6gvk/7ob2vuw0W+
g8rsbVRO+En4+ab84q23etiO3XLNZO1istrAcTfIqd+Tuos5mVwuWh7/DWWaL0obBBBQ7G4wLT44
9ZT8S9rkbjUa92tovY4aKOGg+ffhOoZ4YSP6y3yFn+AK6+8hNrIGmtu1RUckThEJZqgIh8WZxlB4
6nxOq7n8dHdDSTXg4U4oCFZsxS2u6Z5h16oxtpUNImP57K7m38ejrWDt4ESONb+XbG9T/FfCJ9VD
A9m2tBc41mV81CFRdLS3c0WKzlT37MBkDvTYUlpLTfVK/kfJdNXP8PmvhRERvd4Y9HCyUnKpzdEw
ra/oj2NrmEnB4ZKuwAz2n0ARh4QHnUS9IwfT6E+7yesppqZgy/PBjlAwFLEbE+z3vVGgGOGrppLA
Eu5CYtftEizNKYgSysUAXjwrA2JkfJ0fbco/sK7lZeiPID7KelgDhTXbiwgCLzUYDp/IkOcodc2L
v5684KGXpAqg8nCO5pkE6H/uddEA5N610leAkaCEb5k5NDWCWFQijNiW8DqT2AoZ/PYmYSr8eeZQ
3wBRpKAhTna87HfHDIAg2Pk972+/K569sy+9TeZJI0vr/tAxYgP/TH3K1g2Zcl62pjcZfMioOrTR
xJdaDhvtYuDfov73f4oj41MzGEp5G+I9bUE8phubR8ycxx0drEeCMkUkFMwBvoJs9WO0nbwnWGir
bt4z3CP/8i27wHxMSuRCCPGuFsW7MLhtq6eGfwBG5yuK2eNLIauU89z/6xRo1ADW9DFUiMSgMw0J
Rffv1x+KziAAu2hchhuebOaoMCR+U6JEP7xx8uT9GyYaSC2dLToegrJZjEYzO2rPT4xOsAsRaO7j
DlTwsYy/P0mH5AoRW95H9IGvbVq6cE29YIy5ax5GC9xLLAnrXx8SIpdOZVvj9E808DawXpuYI+Q6
5uXXn0Bnpe8QeyzJu0MwTM35D3pW0LpSA6bjRHwoPo7qgsJ1NF5LWtCyu+ynfSmau7wwhMFijeJI
1P9cygfqBjCOS38Bwm1cHBIz6DUXSjU03VihIekExpbqb0J7PD+00CkJU1s9vYJNcbPzl8DArz4p
BsUs/NfZBn/3ovcYElsmVB9TqSGg+hw6fsAFHanfAEVb2PU0RxUaESS0M5HUp9MUQ/ifE9mPsLqz
Kp5atXu+/wddt751KwoddBLzZaHI+WvvjDZCzr390tCezGZoGlTCk/QdfRy7K+gG3c6NyjHbMpzH
wG5aCiQcL3b7D+QO8zGnjgP5j+8gz7GSKZd+VzNXoWBOuHcvDCvf9YdanNRQCVuoA5PzQv+eZDVL
ptycPMsn6bSnaIErlYvRwYuAWLUiAlT8lKJUIBST/QKRBirP/tH0KfBzUP/9qUvgQM4IEd3f4G5C
GpSL076VQLhGgPqATpHs9HTlZ8UBWjyQSoVJJmDpu9dcxVfKhMQjhr10gCOdtr8u5qJgB2Akz002
qw31KypBGw66kCu4EJBhqlHd6NjMD2fB60tbXck6W24CDRFMgyi9zegR7zZwhKI9556yUUW/RXcy
OymGF5Uava2uZCA+ZBCt3Akp74/0qRlTDx9oD/i6Q7//IX9fXBsRec2dWmXJWDLEEpIWtV4MA6hm
8hDCg0s+7AoUAb19Cr4BCdPJHvYEODXFvN53TWzrP0a05kkpwPjnPugvVPcjD93aau3+I2Ofkz0F
GeLYadsQzQncBiVt5MG4gf8hctDYI7sefEzM8GOwxs/v71s5Ra+PI4rbnVvQmhCDpbwSEmV1ffHi
e/L8hCUuSvVz13Ije1OPujPCiQhVFQplLUx1zoH1/7em2gk5soiAuN1XIQ30VhBLaQZffoBzR9dE
waBiFSc7IitRKGbEAJy12p0Z1zaIjxW0toJc0cC5/ueeJKfZvs68GDybg4Sd5i6US1+CrRj/YHGC
ty6cXPpdF6fxzbT/0H8VH8iAhM/ZLUJRc20Kz+0Y/RborqqKL8x/9j0caJLuUUms6qlwlO1tlsRd
43Fqzcoo1dOiWygVUz4StBb0ndjtywHfDqs+gn1bJSk3iy5VwY7oVhkeRKKx9o95NsCfJyOH2R1h
Rr0hu/a9THwbOwa9biQrMFe4kwNdXXqtE+ul8qa2W8RIHmiyscBPgasBmdzzINs9fn8Ab+ghSY+b
hit19ThFapHz/EmsxNLjljal3oXsEv/IIXd5QvRDdwPB7MF+kgs7U/qcVvKboiM+N0qNy6ihwQDK
wh0iPxUTyw4WQYqe/BYCw4z/eJMkYtjxseec8JkqvM2YfSlG4RH05qOvgDCxJppMRAWxilCwyEea
xbMhXB8R6jXt2EW8bUp+MmGMWdV1yVdDdwEf3rTRzcsYMP+ZnESqC11j0G/DIIP8cDA5qoOvARiV
jNgHCm4EbIAHCJB6q2wZoS8/UXxgWXYVPmRR6fR28P8uicTCJMtgL+B1cMSNKwCHzgIakpL978HP
5cdeE3NeS8gpvHjWA29urUbBr1pfcqsglYcSgDhSWjghyywC4AfY0tUGHt3M+onX2lm78SWWsJ+m
uR4puk2+cU3x+iuhivKPP+xvtAPFOGKpuITI+hulEbLXexTlS4ovLhe0BQFtnYW+o/RMmKF7ThQW
CUSy78xm/sDO+JsqkJn5dHy0tJb5HFBTBrL63FMwh+wub6NfZzB3fbNY+byUIqLU96728d+7bXg7
G84kIqS0yuZczOrUYAyBFxOuJUwKf/55SBMWmhA+5ee/l78Fkl+F2xLZhw2xZ9yd5zeSTsQwqsNi
eKq7SMV5w/2t1Mq1zWNIE/nK8hQXsEUCl1E501/vsThecuX/40XOM94oDTcYBkp1kfkF2TLyKQRk
iDZZa+Pw3rrsNCufKj/RQhSxcndpnqBVmL6hSh7P+Q+nEHTEaYJtmnjAL1Vv6ZzPWIWXkikguP6t
GdfDg41FSPImdg+zzyGI6Y2vnfx/7n3kfQtWFbCRgY7D8h4ttn9josPvjsdijtNaRsZtcoA0XIzo
DbEoISVYnFcj32BK/62sS+O2Rw3svFa6j5XvaR0z022zD0Ia45ZeMnjL6fOcZDAnvSEsoiavxCO6
Wy14FkTepz0Y7w8aWt4qVoDvxG4qsNhm01l78yKpsM8+nI+Q2qekAdaHtsNvk4pX8PRK5Dk+FwAe
ElCsHkkJiZfS15W8IXKJt6Y3FlqAttJ89G+drZeunYvzRncvRCQdNX8Hh3mVVVcEyULr5ocuv1sv
aeI+HEnayUfgKTpQUVS4xDr6j2QeGXaFT79apwomWuRxZAzBJNsDB8VC5p6ighSrjPbTvOMmK68r
fwkQppygamXqNpm6tOIzOOOsoVXmqWgI4mJNmXjlhQKbIiT+HDXPrkpOFKa/Sl6unaSLEUph081Z
c9qVVxOAl1ogONC6+k2G6PdIz3GwhbvSkUzDOl4NpYARvW6/rtaj5CYOniujRLH+e9H3Jd7KX/dX
Q1dyMh00aUj4/deFvTuys7oS48vmFxu4l61CTTfo98ZiK1JIsHj4bxMDLvrEgUR4K5/TQWb3VmpH
Y809Jbj1cmhdooyUFnydrDEZmwVzyg7Me3+wlEZ+Y/9YjXwXeFL2wa7EORT5a8bKNU4NBQFWd8jR
bW/+033pUpLtSl/kq6DjqSw/fFSM0bhNx4p9KfOjAEYWuLDHh5G38dwwEe1eo3JuLXwRwGX4oty7
daYpklWmZpAaGrupQ+vA3ZrdhQvHQxBuN+aLw4HfTNY+cEILlAL3ElYyOe5LQbptWVNjFt+gL6lX
y8lzGG/KWJtWYfP/lZoCvjgTudLal9MVS/WiaI6wk1WGDLRItdeKaj5MQUuCpFv/kvHOjY7u+0X1
MRSwomxUWHh9ACI6nVD/aaG5rkIpyA5mAGDgWiHC8//RlK7h5yQMswuKFu6BkCq7JYHN9qBq3NCp
pacmu4o2TxU8daFGLW2tywgHWK6KWQiOSX116mEa5OCQ5eglpYk92lYZwjBvJ30J7P6aMSWF5aoO
XB2jXVZoyslqbHhKXxBhBrO/ER8gIa2nVPN/t0iEFF/IRSEVtBmiLPm0qj5c2QG59BQ6gt9Hywwm
X3XgtjKUImbwRHcgsjnFGTN2h06YmjVF1stUXZuboWKbZylRMpyEwxiyywBKSWU4LCmmIawcjB8T
uQ32whRXVsUGvstlJAREiwBKLlY3dScxzC0mj3OCneRmrj4LpXJvezGbNOLXudZa1ARQ87vCqKv5
l0t7QhawrMXLPejl3KBrdnFgbuFtFLuLJsqs0szvze9e5DS1znamizx/TfdiCdiw9GPisG2/lKta
t7fvuMe0TJEbD3ZDZx8Ry5w8tZhgBjou1oByh3DuQxhzO/oiaWONr1Kp1ebzWQFPtK2h5Vd1GJ2A
m3YCKjEsoNlefUPoC07mj0C4giQcRKv2DTXD887iP1TvR2bSQP5VNKe96KxKXlDpHJ2QElkwMebb
7esh2JijA5hGtWC/PI5szezAOKTJuQBBg2pVx7v1qSgN+RGkl//Odw59zdKy6LyAwRp2jeq6y/UZ
C0aVWjm/uGldCZG0oHK594Qn1GM6Y6loSclZmQTaVk4WVmCr3CrwDMELnEYfbs5jstJ6EbcxcePo
cQ0DqM1vJOdJQd4pSXwD/xq8vnohFY0nXwg/Nzb68++2d7HQdNgyntYxkEwNm4jtLv6NBQQsnX9W
mB1TJHZHESRq+ufTnKrH3YG2ZIb+GfnPBhPVAtfwRJTy2zeLlfZ4wUzB4k7/ir9Rk2h8m/kw5HAn
PEe95PhWJOU6kKOSfh8dznPQLqEKwyrLFqtZacPA5+HSmsHQoNBd/dJJ2W6m+zySwqo36xesNX5a
TDcggHZcCZ+5Q2PmMIaxjkleCIGT5HUOSPkV7U5hLfQ6W+VY6BvVizzcUZiW2jxUbvGyWydqJ+Yc
v1jHj2HDXsUD/PnuIiRtjXoN8hbQ6b6VgGa06U86lxRFS0xLaTZ+YlwRXwNwKk92ry70yBfR7f5k
yCRXqM5NA3f0R6NXEO917GNKYH8GZV8ZEvWAt5rKLcOAgBSl2MGwnpRORMWAlHRUzzJxsGnAmA+e
PVlpY+CfZorez5PAq8NmfUuJGUo0z9Rejz2MsO0++Ct8UAM4O0HJ4t//iHB/D9b8Tp3Bg5FkTPId
lSRRY/Iev8wl6BrxBJ/K5UzbmnpHfU9l2z5gHLIYP8AH1htqZTPUgWcc/kMemIC0lvz5JMNVzrXL
x/YBm/xLL3LvsaowvMlIRip7araP/IWIt5DPrYpHJf9gAz3A6iB0e3FDF/qOlXXi/UNz3VniaFdJ
lvYEn+CkORaMMOilNuD/OXb+3UxrgccyToxmadJIP99x7LTL+7AiLPt3LOPzMeLNJNN0EYsLMBdy
Ul6bqL4yxAHxCXyHgu4dZJRHY12TspteIF10jF/kx2Ydn1QctUl3d5rN8ctHWTvRl20AmIAvvsHl
uK+vzqa1AyvMJTJQumrbeh0LoS9bVik7b6IhVRrTAyiXZ3i6OivR+7TlUps7IPJUDQ/qG5Y8IJfP
5lOtWpINfglhz7QFz+LW4WuRh0fZrQtfzntCqeDyVjJFLspn3yZWQVjWGVZi5UK1egpAAi9r37ER
2Pu0bZTswHLW/Vq6aMb08BjV103fjATv/foOeLk8JdvLFkg0W9ib0hbXNE26P/y+uZ5Q0GVu61qO
K2GG+yTjMRtHjm1YAVj49gU3qM8rSwmST3j2z9ry3xI9gad548BeSXXV5kqfzunjbXkcX7sWPG0J
DCTYoSNk80IK3KfUgTAUhgP9FwgwzP2oH1hZPMEyYWeRDRDxoaApTxM3mNydJBuNY22dGrCX6Tp8
gkK4NCI3K8csU21e3FAJ5J+WjKMthTzRgcjxL1/q62VodkHM/IV6mzXXmoMA5K+B+Z6z5RY0Ojq9
xH3cRvRf4nemPFjiaHD5kB46oLBs516D0Fc9RFx5xtkSfe6ULZpI7Srg5RfmmkPz0wfXgOB+plES
7wLkQ4yoJQIrCdGp/SOgZDqItvieI8ExXECrV/xa6fxydFQTunvKzOiZ64KFnJMzNLzDSEH1+LRO
ETedBwDA/+FLUKFfEBWBJJ54x6GfIE1KXgdiYI5/cDdGXHhRpU5Tl35k+a4iRlx0ZXFbkTa5D1KK
5PoZMWdtt/KuxJ0vNJbE5WFatsQrQH//brnRZus3qOAAqb0uiK8JL2c1nd19TTpLmlZlVxI+jg6t
RJxO8u0u7Fcw5/NIjxznfQNEc23On9ZjDNPjytwZXUoigQ+guWlEkKa7TvrIQAWGSl5dRmM7jBjc
akPraY2K1AhE6Xm4rxKMJYFk2UJ8qU9jvBIwPAMAXQY5dGHPs6ZhMIYOANb38ofH+6Gig6jriiWP
Oeel2HdbGCQpRfFjONEF7DKz+B0+ld/SELe7nodHT9IOfcA/rOXjKSvPHTPLpwMSNnblDa3faoHS
7Ldj5sqHLD6ZqprkQSxfwZD9LpsGIUrGx+npyXMwnxr3ixqIQ0P+xTKpBTdSIIPayQXFAa+8fEtQ
nqZtkEbjbNCK6tMVGX6n9hElvAbxcL+xSh4upCzfz8LsF5uidIH1/YXa9+B6eDW4Q0YzRS/rmbxU
iVD56ZJIu+nS66vP5bWfSCFgvQSvFPYgX3ESn/prVeCRsTnAi110kw3EC6hoSjmt9FtwXkFxYOeu
UY4XIt3Domg3b6WGv7j+OvEBzhAXf7mj80/YG/tkeG/dnw94Z9nnsyDJL+1XRk/nYFdBP7EHdB0O
/ZxoCWn88ZMFvwtMnoOZYJqxje94v5fpKAGA9jkf8Kv9HvGuiZPTqE2L35o0STVivUPGRdjaZ6+p
bVBg5zB1cQhrS56Glu56ktfw+iXj97LfTWcdSHLI8depvGSfme96OMmhTauuEx5iOkvmt3UWWzV+
E9xINbG3dVsmDNupdaRelfzrwmThWNTnVAooB47tpd/Bx0MsCyrUf/RBs75sc3M9VsrXRk24qo+Y
UA+2N43jE/XRkr8sHyQKXgyI5RAXgdNT3ycND3XFzSzvs9bJpA5jLy7ZgdDxGtLluJseDlwoTzSF
Jgt97p91a4t7CMl7rs1Jtpx+Y6GZ2RFDNfodq8XBNgWyBRJFygEFs3HDP1Y33FUkZMkLX5gP66WC
2FLRTKCoHc6gb6FPenVzHOtfw+dUqXBFMcvHS0hEvg2HFj3iyIO5vlCxWmcvDl6H+jMeNnGA6ccY
5wtPcyenvrokvYXyIe1hJ2hbze7srLikobL+U+hKFhRZY1u4p2cphcsQaY76DNs1qvIwWo2ueHc8
B+dIYvQ+UyA9slpZE2RP2uLUdmC+WO28gRy8WD2Q7BaQ4A8rEmKTBfgqtbbv7JlZbhgPPsZ+gTsP
1I4S5TYcEGCVWTDp/h9ecPt5ETvxIye6i4THpn/bivDE05V9ALjz2ZQKAMn/hdekOffKAWLYWd9M
ZRfUdRXDLrWrRoB8KJm7LAV3j7t+1/xpNIIiZtG533n+qTWHVCTuLlfatvj1PQu8ic+c9LqTgcta
6uW3zy2NcQVXnIom2phw4wcP9JSb8e1jE1ePiNNsQmKviSARst8yAvKNNKik3E2/adl0d6ELo25i
eId9viJlg159XNdkxaQjD+8AcCSbeUJ8sOZ274B5oCjbEu9dUpVUiODbcX3jBW08QtNEFUjg9Ns2
JuUEKB2KlcZxWnF4EkrEeaz8QlQ3r3s0DyUhJ1KUmqIWBNkemJmll3o82R4185nfk5PfB/eUwUuX
T9hkdNqiESsGK9bB87xkAHbiiHU1/GDn2VpAN02tFI8M7LgCowfXpu3qnc1spGFwWewHpoC3HmuM
LSw8RH0uy5+88PU20OsH+0PeJ/PyDnZ3HMnZXpyeemol+Er2ftbKMQ5sLK+FKxZ4iDMdidZLI385
bmaQ9PFqNM7WM4YrVzgEf/KWH/hRzkUNKyMOjbBPXKljIVgAS0T7hi6BeP3ze6ISoM3nY/mc1cpS
U0wv1vrZoeVDyTzaCpwtWBFC8tix5DpJJ6UwryA1ZMVnv/MXfd/4gqp16kM6ua1bvYEImcwM81Td
zVcR+7n4Bb1twtaSBH0ff36c9slU2i/zn41DIh3C8/3CDwM1fsPuaHSOQu96qB1c1IBGbRh8Gchq
2k7BsaDydEl6QyPnazk4mpIv5f+sHpbt5R6x3Gis2JzscFLSinSqat4oi0GOKOSopt8NQ7T+sIxJ
67SoDdQcNuNAA93LyFsRR8LJL3OeXtTAL8RUfrgp2v/pUl3AS4JzyU/wy7ZSSY7drSeSSSPQkJUl
SA14is9IDZ1FAfZKHPeVajxTl2DMoG1S9j+nF8eIGApq2a9qca7sKP5tcYZ9eqdon7jNjQjhz1PY
RXURwuykuwc9qFXpsrQ3y0h6Gmc+Q5ngzEp1IzoxTgf+FQXBNxRHWY/tpS6a/0AAwO0UEGZGr/8T
OiWTQF6R8kiVk7dvtX4rduksQTMYlO95mpyR9g+8qIiJUMEPHABHSV1jDcFDIXo8FGwixf1+yXE0
QJu6ev/EHgiA6g+sKliZA0UxigdgSSRnx0xztscyWs+xMT5J4FMm67Q+OuEEUhozr/7/JipFMYUs
uoQg4oX809M6bF6uM/4AuGRRxCTdfOc0fkXYW3qLqZ24duUbyODSlogwyH1ml4IAZ9SJVzs42R9j
UEiflAxdyTAkXDMTLb7RxV8H6dcTzeaRXOhUpnZpeZkfmm8kQY4QoefjLhvwXS0k10FMelkYxiIY
VkZCf6K3u1MOlJq2c2WKMd1ogaqKKgTFRxklHFmiBclOvMse2XCpt6RQ1xMUdCpsjomLn0L0Y7Ta
83aR1L5X8Y/e6WPVSbUp1VhIFYIis0BwZmotbKpIwRybMwMEekjbv+QqxJFfzd5Bczmac9MfpgsQ
9omePawxZSpcBFwMF1J5NmLXV88560oFjD9KkJQdKNmAzfNM30QfGNCARH/Q2p+kVxArqdjtIfu8
tOHoRYatNHxSotKMtMEwIu9491bUtcparPbiGIcHS+eU1JBLNEt70pfMI+2w48uZwLi8QSsLhTZd
ziNfjnNKqHUqV+RDx/3SBte8iTa2Js+AkIF43O/Ra6OaEtqlre0mUfCIoBuMS4TmL9XQ3NQg/d9b
b7gjEV0khpxISbyxdh8e4CHrT2ViHpUG9DafnQhZvvaffstCIOqPxe/XBJFDpPBUJ+p7Jbj/MaGS
h3/zn+ia6f8ougnnzmmZ+gh2yNNNfJqzb9YXgFRuK0ekYwej/fAs7B8uU4gpscP/vNxixp9WXUeA
eeHDeMwr8wmZDeQJMO+PxJa08eIkStRCAUyRUntVmKvgqWZ4m/isnCfzhVvaJw2eqb4ASkA6iR3L
dbFbKEwn0kJ+8C/6zT7CrNuR4VUnDHqQVO1kDg2Z9iL/LD2kGYK0wg/iUmvqLlS0AAIAo406x0tl
bYRftU4q9n74Ln54RCwpHeUz9xzRT5KHO8c8p4apS6FknniNQeqig2sBDuZ+HuWcxlXqFzgV2nQi
gGb9nA9O1CdAogn4/mdSY1/MFVAjYbeFUXwhxJbH9ocmpQl+cuHs09hTN+TQJQynQAivVw0pzlfG
tT8Uj0K+f6D88BjI3P4Zh6MXob7OxmDiRHutB7+S04LfwWKjx4A5USNDac6mIdjO5NfmoxBsAU8E
2LuB1TC8g8bGaG6iJYQ6YyI9ho2xL+zmncIsrUQqrDZGRzByt4gFhMgeBoAuAuGM/6K3qyS3QUGI
nCA51JFFN71PI0urYmAwbQPH0ZO5PX2McxWIDP5SdWid32HR1tcPN7T4wqM2zb9n57sqnfbAaxMl
c76pVtNgzRytRPAM5/ueGU32mIuZOlqMQskDobhpJxoMOD430zwLpnOpRC7CtZWerPNmYd128/F1
RKe7NjyrSEMTM6VnDgi7ioSwPOkU3pBS8eFims9AzCV2xZbMjgSRzj1HAhC3lsxmjzLgmJJQq7Co
D4knj08vJjbDmyxbggqjdfB5isiNcb4TryjL57BP5MFiW+fL3yvbgcCiE0WTno+cE4TQPD5R+H14
a9t+zMvj0PtbQknDoxr0MeFWRLO50PvRiPiaDLm7AV+PmyvjLaGPuh9Me5BzBVTPIiJzmm1ocHCW
tVp9tu+DqEFx90j6AR5lMCc2oQNhOr17wAO1Pldbctk5vgimPvD7Z2Pjf+HA+DYXSUUnKns+K7UU
Uv4Kmy2XyVX6YPZl9BuMpgwWR00SGvpTSefzKgVnBN7J4JeVjomtfhmPL9a0LstNuZK+zpEdvEu1
Q+LKkIpg542JZ2eO8ZvSdPVSL4XCLapxIYjsH4xOl5PNEBXms1eNedcQKoDuJy4J5IZMHf+s23OP
mG1d83w0q0sJBMU3ue75upcdB5Yrcb3uU/fTcjCXjc3KqloMBUbtyAUgIKNvHhHhm8awUUFRiU/g
GiTPqa/8Sow5pvaTrq8xen+SVwO3Nusjz5Z+1QJTWO4I+HZGI8fcz1Kno523K7AJfvy+VelIHS7C
By5qHTs4GIX5SBV+Rpy9V2r0PgcJeHu0I131jFiAMcTo+N1MB86R/9xHpY+SQAwUazuwYoyz8l2D
G4KhuC8bev1cEiC2Pxcxqf2yGnmZPrkRrl5xb5qGdlV61fv/Ove0WJydbRT50sYpqPvio1z36zuq
/YBDPTW+gpxlPS7huODyEoF5SJ4lXYVrR3iCHyi6bUiLoxboZ0RanOINFGozFNk3ObmcvZeBcazk
7Sc4jJ+yaXhlwcnk/m0ttgWFqinmBt23g/d4zY+oyqCJPakuz5yvo/Y3NQbCKzXncWgmSVGBax7d
zyvJbLZZ+2ruyLjuwrEb+iCiHV18DwQFx3b+hzbZ5jJYoBhBmD5nctXKyWZmrBXLMvtfigcp33qI
rpR20rYK8hTQuiBO6FD0u3IslFkd1FHSEyFLiKiMJ2Uaa9xBMEXwa2Tbdx+cldBYWqqDE6lz9ro/
BcdRUE6d8P2dqon6d2In6JWzLM7xRYLzAnUoFo1/nj7S92qaAks1sz+0p0pRv3tTk0Ay/fvlxmKF
l3Zauc92bPUEvSSp3+INPG95Fr+XILXsYTUbpn7MNI91ceE+5ozaUuwgsvLrdxjCppULyuu3RUNl
b8aXtjGQSb9fSpN6wb+AuCaZ04Wwc+cWQjCNpKWpSazSZRKiZ7Ji4V9Tr8SswhE5I3hRmP5psi22
GO+bzATAbZ9CqMRTxHEWhzpCGYtF9OnFjPXPoQF/cbdaT8eVSkZAiT6dtfOXsJvPZ3RQuttZ8Tml
d/P0h8HzLcHaJbro34xLZx2NYpsqmd1Y6VfUrm0t028LTA93ZVIGqjETF4/tWS9PXrWaHjLL1Qkj
Hs5ONVVev5ByWJioeMwEp22J4PpvEK/vrfE0yv1pZ/rrTI5kWKH+l4VCP2f4e75Vg11LpZxWmnOq
3JzvhLyNvyo7n/d7KhPN0S4PdsBtzEhV40roeBd96D2xe9Nx5qfGzQVoOC97FPkSv6yYIFJPn+Os
IwY58CaZAsiuN1lT+kUbhgSY022LkUs37HxMRX8a1lRwFiF2+h9nHIj3ooyv1uLbdKwddLcDFZus
+nZHS7zL1YygxpVZMaDsf8Vk48kdeWw6dIXHrrJKCpX2f/WdOEqJUlJN7RcyqEd8e4jL+9gINyvR
ULr4JR05u2LLpJ4cAc4mikgYySBrsnnqHpwfXm+AejZMGuFzw782bb+qMCWbct6OtUA3YewU8Ius
JfDEXpznxaatiQZF6Q7CTveBhDFNqKfGVr2wzvb4B17yNpJI6G7mAjrD96BRcrwii+X2ZXOhqXqx
toe74Lgj8JPOCdMimsAahgGuwvrmED3lmsHBYebmOP+ZJ01DVhuKMpzruiQccPW2C3EzDoVAzBkX
j02JxjwKHmu3xKx31AJRGSFte/mXg0mPMRui7xLuiX+XvQmJaVImMOfh1w935LxXZICL3CG+rWe2
yGBydcEwpWM9UTb2P6DSFKKYo9cAyEACKRhZtQ86RNf9l+vBroST0SGfjWHaVwR/53Ie0lzz3s/j
c8r1NLL7oCRVW0MDdwHyNhmVz+3STH5zxMhnD1D2cNs/kgdfYgGy2haxj7qP1ohWr7vf++sMhTWT
hMUoH3UEOqOsj2PuhUTERhcyRJ3YwO+hQjIO81JZS2dx0ktaECsidPbzJIrAb9Ck4nRNnV53p9V7
w0SI4zucdB7i90jSVZoLwZ2wcVFRIxP1MBUcmcJmwee0cN9mGSpyGlfQdAWIdGzcYtvDNLMI/BQ7
LngTHyn/OFayawPuRaC79vSqhvDsXD5hyH3NRPTU5fIFivpPhFh26GpUCRKkhMnBujCv1l26gVD5
wHkg3wxCTmn+r9xMulgAKXY6tpNrvY+xhWcY6NxI6NpvjVeAX2vCrgXFiJzQueCsckyDZ66Fyx6B
t5yTVJ1CjJCNMTq+lbcA+KhQP2OFI+kUn8kEWQK4T6rXSbpuKUI10r88emSxzpT3ybh8qb0EW+jI
Ubuu/kyx47KufdSk8Iyr28Z7xClV/ecmZb4PLk2IjwnrAEyMuGeU+D6oHDLq6AKqaAqxRGiAJRm/
KucylbKBHAfRhmNFyzNSQ8IcMlmnqtOjNU3EfkVP9t9K92W+61SCQqS57PibQIbVrGVN+pV6r/4J
HO/vT8PXcsx3MmF4ppXNcnKK+uu1/Y96ERyBuTrTmDye8x2R27Il8ddE+cYnsE5dzmhJCzgQziLw
aXFTCmO4zt8NoNjSzWrjTD0eFHkaPKe8LwGC+t52J3BX7Tep6wOhx8XQgBQDsP0GCYy0i1oOlE9v
0tvBWuB/UeAtGEerPfTtymEG/TngLr3AxhyoLA7TwgVsLnOZfbxp3JH28IreFgzODcGWteNDKT2N
F7AGuFr8VmC5NbrviPbP1RS42lYzCahTI5K1Z2/qawO40p7SDeOzxbT0GJRdWD5RAYvcxhL2mRjg
oJW2flz/4b9KH80fK0EJ+UYZrAFiCjtlOfYtG5+0JO0pqMRCGtJ8RL3yaxJ48HonFqnKYoSige36
quJRo2LGT04HH7BhzJPU6pLeP0v8QC6vDuLH5gHVCx07paCA+LeXbV8tcxYyJGItP43t8uvU9JTT
XXn9WMGs++5nmJee6ouBE1cFxZlIMrWZf1G3cE9T2Be7/ZFwp1vdQqMLXAk9tYPw4hQTMqUTgAKy
mAxscjt5oodKhwjcvIt2qrM9oNdcUr6fUHWj3i7oN3DAB5toissQEvI9inPPsSwjuBiT9N+gSH6m
5K1qbka5ivwfUSTO05d+fXMY42SXJGFHUhEh2IhePfx8sQ/0GN5tgFxbcxzkCt9TycrbSk4bPEyv
4p0hM3ZfTUjB2wdtxi+WbJSF4szPLKBfw1hcJLuFdzO12SwEX0+m+szbC5HxUuYTRfEUMrRiUTMC
EYZrz+FrABl9rXZs+aZdnqIUkIBKodbr3s2+oBojqAHUAjS/tvAStR5jV2J+YlDt7lZAMsE+cReV
EnrXK2S77AWvpv/iapDcLoj6c0XKxBM3dwtrhCo3yBZ0+DLJPrIChGGdB096IQ3UziDpmEZgVib+
5/jhpybZi3hww1fgwyR1n1vxn01WdgdK7kNueD9kpZkBnRLXI7pZ9XaqWgwPYPgksATsYqeBr8zi
z3BiKKZwh7cT9ShNzPnwSrI3zMJNC+FkldOjEnmqamX2rpruDRvzBKC3VrCbLwYIKftED19HqTnv
Gx6KDt088lqOe1V05/hzGsR/1QspgjdTfXHmCQtGsHygeyomBM9hjz81vkMUbe9Gv6UCf2cQYuxD
O4x80NBkrf/mWuaspEglNBXAjQzwG7+eHWIPMzmvRrPD9GSeqnsjRTv1ij7rCum9/D1nDontiUtg
Ec0yiA70yzcrFmn6uNbJLLqwajhwPMNZZh+Ihm6goNCwOVKkjN4qE9luNu3+jODL88YusXgJ6gIX
MJS87Th3rjeKtwpiFd44jR3SKrtJJw3D5L7/tmobk3RUKbAwpuWkDwpPjnt/lXDZ0U1Ker7znMip
vKDfBxQn1wkERefegVASNQebhraZwvJEIXPkyVGu01/vMtTBFGylhN8S0d4VacXYHXg8aFG84oh4
bjr0msT495AutuZf9hlrJ/OJB8QLgXztVHGLGG9Qvj9199HxjxCng5jntDcuGwX+1ZU6PLjQvXGY
oVipJpM6jH+IWqkyRKp3G8jtoUFZ5zCFSaVDq866XoTCIVi4Zp0/8zSYa0N1o71mvISuiIGAHb/X
C58DEXv7dlPKrm/QuXhlOZKhNg5NNy29k28Kc8CxuKR6Rsp8cthqdAhZMYZ8c9N4GPejVnIrpD6T
SOjiPJmW/Otl6wbTiPTppKdBTWlvWzdwRKg0z0lnIKs9h5XLINavLDctChSQo7EUlARNcYgU88zM
xr0WPagZqKkyJu0IEm8/C41Q/6lPQyXID5Z58Kfhfe2Ryw6+HHOZEJY8BzaL75avkH9xPqBxsn4W
dvnK51nWDqj6jlYep6M07UpTxHeIiRJRo4bsDlctoYlfyO0jEnqFE2YbVRPtFvcK2foRDyI9BoD9
H4J5vblGZDos5pSt8LdND5zCawJJtTOokjv40ZHc0MuLO1h2NAB586Cb8RaLkePvQWJnoWsR9eEn
mVKGeMtIqQZ9f32RDOM+qR37dxob6klgapHt3CnXhu4zQZEhSgfhplQMfuzLcFDCR7d+8ozFnxtW
j05LXgDXg9C7j7ZSnqCYBavByoK4vhepoZZlc4r+lJ+d0miKEenVQKw7dpQA6F0ab/ENgZjNqF1Y
TD0t1P+Pym0PCjvyYOpNTFJvKKF/+LH0w+2ocz8/F9Av3WNRjqutoXxDlwkL0po3tD5cxoQHRS7k
NY5BS6lqqF/E2Bxs9/jjOOPfUyPN+j5ahbW423Tsy2RsRVv5rYWTacgmKuMnAHTSuXfehGgmH5WU
D6NYVh6ncfWt7Rxwx/A95CG6p3U6K9lhv6nvsxJSeR3ay6XosO4T4RPcneNozkctzw96j+yzr96v
lO0bg48lZO1K5Tr741I+dWyFhENr/dieIg5xWPIQjgxqTuXURaB7JFK187yipmIyIki9f/Kk5xJC
ujKcnxrg1SGh5WROzMxcujRXkCeV8blBTuXreiqH63GvpdO6bbF9ovcSyFiLe7CEE2vPVebNNNAK
pxEjv1KGdGQIeYJ7xrU9+1jWgdpksjfwscGo7kinpRBHY38RlpnuS8WaeGvaGJ8oDpPYPltBrBef
hIY4CEkR50B+EAUks6Y9gk6DJw9m8YdpeJEhlLh1HuvMmuJ2z+LI0oV/II1SlVKISZqrPDNTd5fp
fsM7FGKZfxxvPpvOA/umyo3NeKO5HyOCYng2XHJRyQwZM2PPKuhgmAYQH9GppGOEwAS+rfsfESQl
HqnWIbh/EZPl6IGtBG7RQ3lJD1kCOfRMPSdgpX4rrd1Wm67VYBudV9IwVWvmqtdZvB8vVHigpYDg
bvw0RvknrE2WxE79NNXsosDL8Qz1BCmqLRL9Y3nS05VAJuQb4iDZlPpglq4bIgRfbqTRZk3vKz8D
7sHRn//SFGDIi7bEdFkMfO9iABXKgo4TPPU1tPDbC3ARPttPSG9qXT0Ac1GtpfD6x7rYSN8tROYf
qMb2Fq6+tTErujjazwrV0zcz2Us3sYKDwndXKJFRGijYUgLFFRXWd1qLliR8HUAwi7XINuvgg7no
Egh0ytZkHnPQZklTDMWCRRtAP+qoJAXLQqajdSd0Xmcoyk2kV5dWzri7Lohe4FL0+Bzv9YoChHQD
HzkpROKMA1HRnH8LTVzjmFLqnZVdW8crAURsy8+/+iqzs2CZyhPfaNVP16Sz51cyLD1W+gqgfgXl
UWESTufPRpbBXosoETTKnIzvUJQLHP/5dIvYMUHBO92Am+0HXIuyQc8ScAZAg9ccnLgi6zNEkby/
Kgyjz9EjlBAcLumrjxiGjGGSzU56pn3IdA3tAuDykjTPHdDeCQIwJgvFW962G3UFyHG6ob0Hxlel
VhKfCdOGAbLP98RfoFTu4EoqxZqg7Nz8sewedZBydSsJSgbVJrxO8RnnvniCAt+8pboQAwTWAbhi
mo54soZDR1OZ89lzLZW/8D0ntlxi2tVDkovFMxHnbqilsLBjnk679daTJEQuuSUeyqyltC7PUkde
bKHuv41fcfMHMUS762pPjMZ3X4B64CCykQbHpj+S5DzPmhiOO+KxrHAaHCvk3OxQj2QBV9hcuNN5
Hp7s76Zukp4FAE6a4//EEVj18yJWE8jQ1pFeGsETljjRDduAhv7Zkk3vqMvO9GOLdZ0dvmwvd0Et
MQGyYQh8i3yYvHCF00adMuYhp2HDuGuq/ZTva1TMPDMvmweferLPY2aqrIPXp98nO2hX3940Hczl
8xvzeow6b5kXXi9MmczBAr+tuy8Pz7OGM4xBV5AjVgGELzCeUgsEv889S/cncdWJlHJZ/LYPqas4
YvPol/B0m3S0GtbjcFZ7ytuMCUz8lLz8kojqNgqj7CiF0AHiXkR7ZOl6Xm6/IP+0h+gyi+t97bIn
GgIbEEzkBCbmqKxC/uWmM9sM8DrqPqoMqKn/xbNvunBwqV3G+zGHyXGsTbISV9+r7vaWE7PDB13c
A/aRiVRsc3viXd1tbrNp7FEyRW0/YjXMidKejFXCiUhagKQlE0/rxWqTRvhtwz6VJ590G0MydmNc
/jq2x//mxaMdhYLBYu2gSSbyMggfQMNO7zAfeMfwDyGs85CT1E60CFusMHwwsd9CJRiY8xcsEYeH
mW1UWirao3OKjyX1xTKPR9whMw/UlF+wh5aegjAGjHLPnfFyH0q2Kml8xTe7jAWGpOhXJ0EHBdR7
YW95I04jMUI9DoNus4lrYswhvk4DuTVA0okrDzP0odDMi6Ezrgcni8dSXVdG8GJOs+thEk6/U0SE
rwkfywbHxYcUfbs4ypuyybN0/A1/wGgephQdCoN84hdufUVbUxLHhaHIqNWxQrjT2x5iu+mcpBET
dIc8Xr0xJvsCKIUu46ywDrfjrWFHs2Y07o8f4DbWvkXn27OhVGhP7e0zuq+OCpdI34S0NztLHPBp
2l3KWvmSKN7/fUpipnLIvOlK5VJXcm072qwCxTkrtCJ5vAmjNyLiSdvB6PLzdQsWty1+XEOA0iT2
lMh6f+nKzhAe/1g8WSAkgr8H8mRDIbHUauaniXXPEcfrIxzJhyQGoArTp8B8REv7uvlmm7bq3ahs
xykbiWEjV1ZBiQX5HQ7PG4dJzZ6au0sCY7k+TMdXuhw7CL2jrzY/RtMUaZBqICQqE31q3YvHd8Fp
WID7/jBHtT2D9bSuaJQARIziy0EqxijE4LF0YmVAHX/tDenFOe12zm0PzrOvUP1KY/t9dJs1TvXn
j8vE4m0Zl0hJ9pElGkn2P1MkXyynOT9dZRGC0LZPEgrUGv1yY/9tyFpbm628C+XqcAswKlmPThAS
xzSHLXokVH4ob+gDgmdSM4RiHVDhPO2H2gNXfxhECyWfvE3JP6QgNENKft15KbXNp2tZs2PoWaJ9
X4y65c83rNVU8U/vZJK2FjJXilLXcBKqVOl3CleRkgD3Nh4iQHJPosakpXmGm2XNGHTTHZHseKi7
m5AfopOrcWe/ntc5/ZaV9ZOXmiswjAiQohTfjcaUN5MQteVXGYWDZEGUtueZ99uDHVYYfDaBOZkt
MVayzBB9iOaJbIKWoj5lKKAV0AvUaXL4sysPolvH02pxbztQ0rtZbv4aAd+vrUruLASD1hGhbm27
HJgheBS0L73kQircD9aR2WP3VFuoVMN8l8bof2+YUPYIrp09Q398+FfUMnM4N+LtYeeOTty7vxl2
jN4t444hOfKbCxTX8ClteOWDKlZRjG0smZySrvG/irPR5el2QIDTWEZgAoe54DoJupoEpG0xM0WH
16VPA2KwZvsoXTTHvHFdS4KkLsAMzmyXQwoauAIxWgTPKRq6AvJtWlTRLYt7EYOyzQQ5e7WpQ244
9UchZdocrkYDVjuPbqA8S9N7oHWQAxtjoiX85Kcawz4FaZW1RhJu6d6YVL6DA7KZ3S7cpaLRO/KT
abGI3rFPKskokklPfHMiUYxr9OLKMf58rmaM+XqrE45qG/VUHvOnn48KGWl5bSPEFBT5XFtR0K5u
bxaKXJE4kRMdgxfrFKToccxYK53dwXGX+celbwjAbXfmbeSlJRyJenITOFk8c29UvDxRWtJvDs4i
1jGut2rPg05ZAre2afIJ/gZ3x7UA+MgQ0S3jxIhL+qpvAY9y0fIn4tTV/EEUduNaYGl9ZTODLJ3G
jG7UYp7kQLqA/81mLmKyETVU4907brzfeLyRkcFzX8BxE7qraq/7BKxdUJmZyPVzSZIu/zicityg
3xTrcCZ1qVbMo8GimC6CJ07PpIjgbQpCOXaM0crGurEpEVTFUtfZGkcqa3zoi3KSjx9/SdzOtLri
33TmamW0+R+NN/pZMO+DxPN6njc3launsHHrO+g+9HAHqWT6iWH8IredD6Fhi44tbVZjWCdD48uk
8JNYUOlgS1Wkuy+tqWfsoQkkQureY6ivzEY4VJ4rqQajuXFpWcHP0KVMlX4HM2Zi4dOeIaY12tjC
An6JsuZjOJNyx5ijxivdmuGaEHEsiVYiFZf6TzQc3qbdjX7JY9xEek64TO1zv4KUuY+qxSt0rWkd
eG8cGDRftrxR4cyKQQUDWoD35B3SqExK8zELXZ6QUjTx2iP4N0mK0ypzZRqvEDJou4bctxq2Y8Vf
TMTksc9LM7i3ZxS966AhaPqULNR+S+k9WyiJ0YUTE3IjSWq4DYrU8ryIajJIZQDUw2CpfZratmuH
iwF4+dyy72ynvez56n0WYDksE+9bhE/AxrZUeCeCwehd8c+6GEA43Un+/vHitYVrEY9c9etSaeJJ
Og6XULhzL5XR8llB/cbHtuIO7o5HyWdnYPRcWL/nqV/mGiDfg5Kccw8ZwOGX8x4hKjCw2c9Jel/a
XbYukQZpfZXQyCVnKjVRDX93rQV1emRII8iygUPX932PLLNVCATjl5PVCQ8dKD01AM8yDFZQoWj1
DpURpH55IW9XhQTNgQrn1Ai9dTLiFMumczDyGq1iHGUL4ItHnYM4LbMFifvk22UMPuAZVoHtO/Xf
D+lOHM+/4bHyEmKewLpQF2S6Qo/7q7gyvafMr8xZ4EgdTyxoDazVQXkWBHYhDCItVfBtItCfZjMj
2y5cvngwEKcA2HBMx/5GK4WNDUgFG8kJGMqLOnhSCTtqUrfUkXWD47xLeQupxoqGhc38UJxGjelW
Nhqsps0Jp7tyHYF3dHlpd/bUT2YaQ4mOYnxRPAAqjfI8zdQfJiw15JE42L1J7LpYCW8z+N4yjwEV
QcOlaC4SZVB3m11brQqYxh3sJKFPBKP1ZqGRbLaBRYPFD8xFvHwicQva4RebHYJfYuMwTZI0rnGZ
8cdO6Y836IEaYn5J02OrG075M3LL6h1hjGmHOQ5KFXqKF5k+c8M5jd71w5ccBTg2TS/C0xOd2/vb
otgkPAtcaIJT8uRcD5vw4Q5wgl93Xk5g3gubD1DoGXgcifXmpPOY2DISAe7ud4enrTZnTvMv3Tun
lv2iEeAXsOFzPoCERDrt2rL6PaWAnB288iH5PQ2BXviXufYwTg7R3TDUsxFSU/B4e52hIW7pkpBL
VW8ZwySVu4jYO4UcJDMPHdI1qDumF5L5SBSLmWStpwKHK5IkfGru8oHl5Lw1Anz5pQ22hMbQYPkx
WGqLoXkdzyfc/NEP3KTE1k8M7xtjRntB8QoZvapv0B5fBENb3DDsUtK57qIPRfZgwTQip9ZzXnQR
0sherIeVkcvTUD+fPvcc1XCTb6vqqVtlFJvkl1NIH95AQhoARIZ86kfLm9Kdf6skvGkbTzM5Kaee
BUdgGQC//8cUC2wK1xD0K+H74jYy95hyjsQB4QiZUSEdEAaUiWCGkjobCnjyQpxTKndJplxQoiyc
9pgCR7yaFXwB5evKVDxMUa7/B/TnphueXXIauszwIVhC59+QG9ISe2pHN+6c8fSsAPv81l9Q4zxc
U37SMdFDQUdjMcfR7+OlVEtibnOuoAlwSb1FSNNGTjKaU1yda113rvVQglAGUnwQvAmJWjvcAH9b
OeMk7wU6+ljbgl451v0WDUJNpl4kpGvhYA/SJ3zi5tpANgKE7PL1PIvCBu+IJlqkhRs/9t2j/AY2
q8671/MT3qJZfhAOTlUCm+aVMebxXvA4tJVz4V9Pp6n7NAUqr4Q/AmAfd+iqe6oLmjXQn/Ww7I17
34gSN1GoO0MergWI0MA7oD/KUPyQeSNzYGl/vzTCapqS8Uu68RnFZ3WL3G5ItcUWGLsHfAdbBxgd
/yHqTTwP6iyPEbM69oRUQPoEgfjcY6eg5Tcu/H2/QedpDPVIGvW1+rtDM8/wOtFds1icCM3letzW
rM46W8zWR+23+rBuYJm3bUXk1Hz9Qh+cEnk7H5u0mG+NeuynQYOwZrCQfUMGfP5eaf1cV5YSxIaT
hwMSzBw9eBvpwU0K7ie302hIllx3V1ztUPUwFn+A/+ZXDfJ8ocKeV63+Z9LuafrOybMJzy+Kd7Cb
jfly4jvVlh1cDAiuzdd1iZdD7/FN0S3m039nKi+L7J5F1Z6ulrKH6YDAI6SCQgX/m0okluvbBCrB
uSbe5y6O46Nmj7Jop5SnCPfIpquLiLx0MmWLjQc7qFaM9Aq25GvaCgfNkMxcHZa6ZbgZjuvPC2jW
qYadK0yfo94u8IjH3d1vJwLrbrgeW92bJH91/0n/1ZLg8awJdgbo19MbNDOOVRVsF2NOh8sYXIiM
asnwl4MsN1Ss1g9uHQ3DaujEugCyZjYlsbgHisZqe6WoOHdY3E2r2tfrnvGiQbpDdvMWF+xDVJFm
dApZLJEbWqVI3ABZyEOoytdWDdP303pvfLTEC1wWvCq/JUS7h0WMSJBTfi9CmZI+DkAaoJFCvad+
KOXns0VNaY8gTTQ5MkKdNJcIKX5nZsKI+1ar0mPgxGmaOR2qzu5HX9oL5YomUb0+JVW8MKtx913E
TZTFJQtXaPCDQvbEICF0hKGe6RtxpNjy2BlQPD0nzG5AU28vUf7e9T7bLvAkBZFX4ykQHeQbjT6M
VCvqJD/fCWMuiDZi8mO+L7S17MThw1/+lG4Orp3uZKao5uW0lEBdNZnt1U35I8rr6dshEJekYIYD
eiZYhzW0Iv7oTElDiVE9NG3bS72Ipuyf9YVNosg3w2Wybw7EshEGsYbA20r2s/qwrQChOE23G5ru
+0wZxWLrcS5IrXLPcyF97gnGIqLARjNkFEUpXhll6XyQ4plX6OlTosq2gXhjeFZ7ZAdQRlIlvLOP
PfzrU2mgkkMpSNkUyVtR3kMdD9XqZXwC3lezc1QP1Dm6Rte8eTjOnzHM3FGE0nwL2sGmjveDaXpc
zhdqeomTA50zEHOpK1oCgESipT3hCJLFpaJIt67nVR2Q67s9B7ELaGZeNHxnXSCZuBBmglJmRJw/
iOSGeN7MITM05Z7LA04BJGQWFp0uLxsWDXkrSJSzYHqLGGb3U3HUUL++p8BqCvufSD8Z/D/0BJwO
K53fR9vY2Ukvpym4Z9C8SUt0eQDZjFpsgcVmNFjAbK6mtFPwxchA8HImRBExbhrXxr4lpCH+iloG
FE0VsagMFvdaLWAEwAsAhI8/22wzMslke3bv8Bo3frW6knz1C1udGtNSF5Q3o5PPrBW53/UemHcH
o1RXNnfU+nyRdWiV/zXWp2exmhI1xM2VZ6LHlUQ6iCqD0P1Z5rZ8l/TroQmYi52YxQkYGvz8HI0U
JKkxwv6QvI8YEdztj0WIfk+XvuwHw6tGtfNCTb7z38JYUMf8R9LMH+fyp2C9RRv9DNhRVpxv3pzL
V/5zrIFdzheA+3SZUdcKjPY7yk6nmG7vJexmF3t48tpGtaa50RL7WZerfE6fZPBrsdjDL06LPGE1
7ApnIqH/fwhjNXxTKLGOxQp8oLVN/i0Vz0q3dgQs/+ldrQn4DX5X4irbLvPSbMOSeZ3i2CWn0Niw
5kiAQaX75xNISsLPHRMjWGhGGdr8lxyrbD9btpEjXqofNh64HE7AmEVXfhII7TEHT9HrI4QqZQff
qRT46c0UuyAfS4vATINpagWFolaoFDvUWBv79q+R8UZum3rFuxGC238h2ny036oM/51Uy/xjz5Oc
PojGUgpv13fFR+QALioMQmtg2igchBy7m6zAp3WWwHtje1ECZnmckLfE4cNG309nds7Os9XRSDrC
0tYZRMvzKgdJM+CYitxjXoGvpOJ9GjFtyX6CG2YbMCkEL1JVsfmmUTihW00qUyaKh0pHRKlPhdZ8
YFvYCHCma88GRuWwn9eKL51IHHnXSze2YlOMuBLYTHyuDsoZ7vbWbwatTGXAbF6MNIoxo0NA7i9b
FdWO/8+BUm0mT8mq6X/HLK+a/1tTuLW9Axv2LW0Dkd5q1BqtJAPBqB8/kPpTNnDqEGaCl3vK98dQ
IwCmtZje3OeZf8hTy63YanWUJESho3K8wAZrxStThB6cycxy1luRFe9r0veAZpdeRRusIRl+7fks
GDniwh78VAtdNQhbGeTzGABllmahMW+cIjcW3CAtcuwAaxEIuAOnWZjwOsLUcMfxEYIO7qLQ03JU
7zgaN9KOG1q7j4qrh1MsfxY7rKK42m82Z9JvT3Hq9we7KzPHEARCe96FJ4Ytq+CjAZvQGCX1U/9Q
AbfadGw9pUidCZ8sj9taWrScAJOfSNlXvn4zPN9e7ntI2Pe0lOwdibZgoqJcrUi0BNIauvQjetTM
L5+rXm0Xp5gmHUxk27VqJ+bcdQxaw1W/XzhjfntnOGhSEAiXAN5opgJOP4VK2CobSkdss3ZL6sxe
8JjMiDZ1ZHnYVE5zZ+1fSYJoNkxIXI9kOlIOb4IBsns1rIKW+w2poLeBUSa9wyZM2Ps2F8heXY4i
vRiFccBdcqnjICqLn1/PbWzLjZMKAm9b5G4TebfMqErAfH8X5a8Ybb90z+/6lRvAYzelDW9pcqZb
pOHBr+uKvcES70+x4QJiq7qt6neGStyeRn5h6yX2HHb0ihbBfjeOgI0zwZ/0g4Ue0hWVmsjHupZf
EEGu9u7H8PXCrnDgxhyAzjp9+a/BiyM0T3TFIvt2TrOHcYDDX6UP0oRuub7FCiwsESCebTj2M7t7
sn0SuJcfSO1WeeotgJEwpSamAdPLBuEb21A6nHdVUOE/0dWYoJPiGTPp9tx6hdYz4DWkHFPwsxrc
AcvpNp3zaJwvqIEuXXPXVRXWdJT5tOCDBrHHa0jf7WPf2RgnNmaRGkVvNeFxfuQJjG8iQMxBNjbV
EtMRYJDcfoeH/obJUjrLXOGoIjcDjvnK2viaBc6fRfAUVbKlkgNmy9ytb17sBhnEmbiEfKqQoY3q
KJ9+K1j3Uhbb+vWr7g56V3TeO1vET2HKE8JSZw/aU/TBAV4x74vDLy5H1CXWh5Enh3OZIEHVI0ZD
uVwEFYWfKec4HutBoHUzd2fMQBqxHcnKFBWR/jMX/36xlAfdRrNr9A5SoiePai8//4IWZjTgVPUG
hftVBrIpNe9UPrq49wjHXjbJOlVopDph478M8n/YQEXsYbuszrs2kTMgLI5nOZjF/rkM2vnvYxRV
U9DualOx3vDivWTbCi6POGtY1a/TjWYSmDV0fOq2/wseRxv3JXTdUDuk45vbfxwaOKcWW5et03s6
u6cbV8S0tRQyggJ5NdQ0w96l5QKNLIj6+FNnuyIBebL+ejDU2Zgi0WAQAYg/dagjEq7b+d3Zwo4l
h8k72tyvIU9Pkze0DpRqvAHLzHt4CO5vj3ec5UDwSxq0e8hq6q/iMSSSTZIxbFkRvYzUVu0yOaIH
WLgxaZh9ULrAF2HPj/XojG6AYmttxz2wvEylU3pd/4tDiKAqeD6wxg0AEC4O2aPqSKI9Q56o8oFT
DklrXhar/UBzh1z7RdwAqM3NrG/9HcXsA1IfngSYAiN4BSDxRQDwj/MoEBFcIzO7bpQA1oeuKnKr
zDFbAaGslFMuIhnekNaWjM+tkAOK06JzMtSsmUHZAaGc4/NxcuD9nJXg/roGGLS1CrlDhcvhCEpu
Lq29XbT2zIGNKzGBuhPkN3hjUU6KHRSg+brqdIWvKimiZTvR+73oN/ise7+vMafdXozbKZ/k0xjz
iM3Ozk+n7xWjnJAW3E3FEm9dImgcsES7ymNYYJAoh6vHzM79KD/mjMtFp/F/o7Cx9G954U6lzXwx
dFCYUrMcUWGDzVW5AN89uYZxTT1Ly3wwml9ux887wo4X5i5jEgRHaurBMiOUcS/Ej8aDeCdcEA8K
2za0NneZ8RUPK4sFEKr1Q9zEiJXfHVb70mZq86mXOT5NMUfcxRJQ1HcHiGv2gPGq+12KjyU0HNej
Ofo9JcwIrrH2WvHKY9s6K6hhsA85m9LZw+503zDPfNH515SySiDV0GzWqaB/1+QXTJO/wEywi+R4
Lkak6HmwLTz4lUuajLVS9SaLbHvD8F2rRnpu1qSMoascrJKEyKQ66I4zJstehW/v07uiVFTLJSD8
nxLACALU+xXEM7IMRZX3P69GUsdLTNThoHfNnSmxp7N99zYXZQPD+8NW2Pqx6rOIGLBMXtQ5FFEl
7TgOGbS95286FDop6Ot41vPEn6IQfmq7wAM3u7hZtyJzEpgMkjJcFLSItfKCWcLleiBGy7qiTjfb
pSiZ4R5K3JZFCURcsZyxIK1+p/5L4Kr6zTRVhK365kuNT12pT3hmnDYtgXDZKAfnJ7gvxA52dVo4
+x+S3b65ZhRA3kYP3avVLPITFH1hrVugNfDI6QT4ZZk2uOyla/h7avaSouK+fznKo+x0mmAIjYED
c6kV2LGP2qU4i+fZKU0tAfLCFAVDIfzEFoFG8vGAdlIJH7VuIA/h65Ir8r9MTxbik1SXLpC/+6L7
wf44nt2pvy0M+evtI0mliaOCTeurlU9WyBxiRYumPv3PzseuB2gQP/VgVx3SKi8PGFI0rPB244yV
iHHTK1fBEoHWVueO4PQiNkZiu5nHfdTAqrw0xx22nIsoRC9e1Tr/luXvQrsIbQuneCs4XRjcnODh
x9ZjBP6UnfMOA0nexvOz719/CSw3tgXCayDbFW3E7QxkTalGiP6dBGrEn8As5mdP5zGE/TnHJtPo
57sOv7XgIV8ILwveltGUtcwfn5C8q5lNFe1LHtyPmFOJn3olQw5XS7AwoZaYRMLxYvJ5kpndaTEd
JnZJnHdQsHj+kRXiAPAuY69IIYZIqo+CZUHdHyYEzd8smrW+/VsD7NwolV0bYDb52nhkL2KfY8xo
MNw0O21pc1WqUUGNxzfQ3BMe7gsBTIxIaFbr9/lHqOVf4DyUgbqCggEAX/rnwDCiUjaDZMWwgIO7
KkWWHrrS10Hu2T9t2bFA0kxmSvyw45F1CTmE46IJLBcxXb0s/17WpFAQBoX444xSovptdMQ/Zz2B
OIKcaEOhqD2CcQXydvzazZAhcFdcqhmjnh80GV5BdZ0aanpznanAdAepxkzEveUGeaKFEA7MVFLo
wwBp2DKeOLT5pPQrVhILBIskwEOB783QyI4yzUeqWYzS2hwWX93Ytc5BqlrxUS/17+krT3xU496w
LuRSRiimX5FPvXz4PP4AnVr1dg9sYjJUuumx/KP2T04eDYzPRsMEZ/NxprWttr6ZHRpfNdlq2WsN
OV3NbM0Pt4UqU486O1/VIkm5vawNLe550WpMbd79Ou7cJEI17mKquQDf4vr3WsuWgppy9rU7XapE
8oz+cpUyIqVz5sTgjR57JXZMuD0YKCoXmios2Wd6R++PQV5rwipBoS7LO/h/0DnTOutPNIgwtEV6
qqGnYSByWqnsYMEMsjzXm5F+0uBNl/uFBNTRpBhMVAempIuzWLnp3xxR/paE49Pp1InDQXKH64oI
H58zlMMblzlU6vgJzwzZL88VUa5MM2e+CILm/4q4QRbP8l0GrrLLdi1YJvYf5wzbrmCSLoz1JegF
g8u9jVt3tTq1GMzthiXQ8fYC+sSzOsZXFUlMlXgBM+VNSUYl4/FfQSrZO9CfLdZ+BBAb7JCRJLV/
xQJpoC/bWK+3vsmTQvrTcQoZP17KvxGDKVXVNSfys8WxFqJXli3DXD6HOh/zMlpihVAdPE/a2Pba
naQqSjQoyTZv5STDm346HPE3QBxddgJwqKfCqT3N2MVb+6V0ld05p0UQG0zmq6HCCPgYNaXnOZop
xClXsc1P5TbHIYMqEMdt6baWE0G0dWDhw1VktUxfvMwlm/YcLyy6OR5EOpb/MrUF4AO3XaL4KzyE
9a6VEkmDMub86L3kc654KIDRtvYAbCYQsYYWIiUb5yWrvOym7oXbntp5QK6FNIij0plGZLdCrxL5
y/lD8uKWcwS8ys48Ty+2cVnYZR4jajvfyUxbekY0OqSC/5/nIC7BKextu3eJVZU4rwDxhpi8F0yT
Hoe+pZjQeBzaauD43DWzOjOfrRtBzRz6CLSg1gtkCWK9Nyw4+amtQp5a5YZWugaWwuFxuDE9v2Wi
FX+uBwRKXmitWkqt2W6eJFwjQ7ohw9cGlQwcweXaCqNuQ9B5nQHttlyvwGlwwS01YdaaCbcx02nv
Fm9a5izj2yCTqcX/WthRrsgmY65WKUtt2fhGddWzNrAdzWfh26I9UMN0sSntbHwLgLysdmmDJuCl
kO1ksY7F/2RcNuX6KPiEjaGioCd2tXw2T6zB9ZIUFEoAwmHr/oZ+dolEsVGGmKcQhJ+1sBvUtJXw
HNcRC04JksWLkFOvIZsZ1CmZ/I5faGfX+yP4IFRdixbxyrp0wNY/ATdRbU4jS6QRgLmpMWm9ZsgT
85OzGLArqIIJ9mz/0mvg3nkJhuDexWyzxF5Vqow5xZ5UzpA18ePyChTgfSylDxDsHVETBQaDyQ0o
Y5fNU9kEyRm16XiD/1uaKbNvVI34mnNoqFAimaRInch36S2vOETZM0dgUBJtNdiMk75o35WLQkwW
MBZeiHgYHOx5GN8SGCZNbBkHelUaTht1fwmy7r3DOCugYpFiRxocrKJLBL727lU8qDMhfGXd54Wd
TLcSqmcfAF8MG3H4BgSUCaaZlyL2xlaXKRhxOYceYSkTblxKxks4aTsIgcY3A3uGc0u5GKctfJId
boYuIvskQyYXtOUxp1lDp91aS6f4uQT2a+/6smQbVTTVmdshHxlalZKdbNcSr/tWCpQ3ccKCwTrm
+nXIStUAc+FsyzR2QItl9gvUhRfALTazqr4euwtYPMu5IhzxBu7danklPsFuStny01e8N8q5aV9y
Fev+cD6LRzZGf17OKFKrMMhUi9DsfsA87bAcSU2mdTNbguu4ua7YWhzGEDkLz8v2bvgjVgPYi+m6
5bzwX90PlJ0hHHvbYkYPm3GUBWhJgVAw394zUXtS0o+uwZWxBDl5ln+WlReCUOGnr2sz3Vr9V7JT
ncH5sfy4GRZIXG3WF9ade9XDFRjkXgy9sjUJH/yU44zNX4JTpBkvjgjivg5P3RjHZAfAnKlsIN44
Q0IEo4ptYiDAiBWL+7UjZkDESJ9pwKY+6ixsN79WrsTutW4S1/TmMX5nbOhZ5COtxEnbxZRVL32Y
TKB9KO4A9sg93Wws5GzjrAnMCTIlpFlXjj//ECuNIPGIR8VKv3lqpXpU19Lj3tYJNYS5s4jAgc/T
KYS3ub9hTOIIqF8KUkIRz4H4FvO9WjeLx16IdDAAG93YUzSfo6E4m9KYiJ2xLkOO0H05UK7Wj8xq
S9TiC5oie0vGeXYLir48UlswgEPcyLhhjHzYX4lVl+9EHF1pVNn+RUF+jOUK7auiWZQwLHxgn2nn
Uh5WJ8W86tOFZVk2Kjhlrwi/bsqhhCeYuEKeo/1r4MypbKw/LNgVyLclTHiQafjPbTthzdoREGiF
G+Yyh944cG2dqr7aTSLuauRXKAdQlYOSNCyXDeNYM3vkLoQ1ifofa80so21MKPSCazH7aebF/YoB
2+mX+ZGZC6A+ZEwFEmBQra6GB13PLJWGGi3KBLbt8t3me2YzQNdK2kc2AajTANi8lrQ6x8b4FqT2
YZgOMm25roFWoSvcjgWLEBpvxtoMtfwPmcyZWqAK7QlewEgoq5t/VsIz4hsxJEkC1TbA5AjBSLOT
UEUfYPV1EcO4duc4/IFWFgPsv0u6O+WBr+wZ5rmiw4LVn3fSIBNyVObSCJr1QObAosKty0kMBtSt
Wg7L8nwyZeZcG5puVEX4yqYFE2dyrk6fEE7+Oi51WZJmwJai7F87SKQiEeWkhqhXZm2fR2dJFN0U
+cgVHveuc2qa1ZZyB8j+haJMkuy0e27ZgKOz7CiTbDN+PE5amoMRuoaNQxcwrnF0xniXK0iLi/ud
HoOfdI+uQFA6dAQIkMdrcgGt6cJdavk0otHveApS6U8z/mycsqL4JuVHDKGzXk7SnAGcV0akZkdE
/K2HdKsOdarlV0m3K+HaQepMCk34wjoN8KD/tAWmCTsvyosy/H7pinGnoWogDGTQs5VWh7dpfrh9
gV4+6ZQ/+WM9aXHXhP8uWLAsFZqkghhH61aD/Vz5tnPnzXOt/bIv/Sc8nKdgTm0/KKfzfsxZCeFa
Yzt650q+nklTgZbYLjek83Cac0n3oPmQ7O1ggNGg3297HRHDQo7bULzwqkk7rPU1aSdIPijrHXKZ
r3POfzrgYXA5TAa/Nj2dbRvMPDMdK+x8LghTPHfeswSMKEaIEBkcKTMlKuAFBg+A6vi8sojK48Yl
gRbGw7D9d8Cf81QghbJDb33OOaz/P7zBFgzS1cvircdqkqYDH/y9xCsrIsxH0Vm7Nb3gTBnSl9ET
rUBM8MFcbPO33yAfXn2/50FfsoP3BECKMKXxwM5Z+yO6zauPRQMckcDAdCUstQTocaYLZF1g9Pjq
tBoaeyeMd9JEZvwdBiIMnNJdlWJCP0ygo+Xm5lfbv6cmmSRsF6L0p2EoT9LLTZNPPD4SJ/r6Aar6
3AOu2UPBO8OPiVKZTiDDra/pZnqcm4c8JVgBNf4oAGAK/ykX5QrEoHoVHgDoB+Foh5586huyxs0w
1ZMl9R5o/8PDSI5QTKxbCPrtibs/7BRPiVClR+kXd3L6sXDqsynQ3VAttDgAgmYcD0bEdISGSxcn
v+GQshK0khRXgm2Z7WLzd5IoeuH2LPDmDiyxbUlBJkHYEuP+aUGvOrDPaYSgQSy4bwb++fJJi9On
w9jHNcnggbjd+00PW50PidyzArMdgo4wkIwYAn+8wUW+dYF759qyspZdKN7KMCTIrV2yrHoEbGym
b87YjygJVl5yBafgC6ZfCwyqykFSf8qTAXDArEcR4CvG4IcT+TPRAHPyvy78mtMsaYTTXbySmN+D
0x+s/zi9Az5BEJiKdtlI/yUCdtMvAtMWQ3Xv1sDYLm4Yd/GeT/tzm42sETjgNNiADleq/2cfiard
9OMnuJaL3ccmk603gCSMagsF5aTQSRpvkt9gjbTnJ6/Gl/RvAROFLye/JjrYlqsQZV0vHu10Oq5R
44p3E34RD32cCqpotVZYaBE77FmJcChXIq84N60BTcjXlnl6UVeGrD0TDFls2bjbmP0vrwsK41fJ
cl1SdDwNaFV4ewWTOAGUj8yLD9Ret6Yd5yCSktPZ/iIf+ME1OS0iONjzpUW5UOvevBN9vdbWqBo/
gDzl8ISskLS9erYmCzADfU8qkGhh4w4ijYoubruPlrTiKHAtGAmiLikpSQ2hI0rFmSvPiM+cezC7
4s5/1FajcUWAZZiwiTwO9ZtRfwIXbeU83PxQfkoGvlSf8/BRlhnV1mm/lhqdlXSDC6TeQ5+92KQD
FG+1qQuDuuhklFrADsXmYtsVR2QbtnIleZVWqm0fq66/mtWOv0FJcABveQdM46kiYd0CDFIYFW4C
W1WLG5L3aSTHgFJEnh2Xyy16gwaW4OQ8YF2rFPkWGgawBsY7d2y2DepOO/t2FJ9oE4lZny43Qqvr
PFE3Tb/4IYSG/tj5NVC3gsfMjT08AyGqNNJyQh3BXPDsx93opLN2R/cutRXkkOmMd6GJQwtF/S2W
rfg+XsbuuLBGaGFJPyGgew92B0hciIvqn84VEMbwJknFVnrrOL2VPe+CK7Zen1EfPwODWyOnTGJT
2x1bBErZLTeO/myCIVLiGF/9UbLab1/uFN2t3QykDE4UM/GtprMgMRN19wXd3hEhclk0AuuCqXTh
XVbn6qFkIjjoIW3NL3qSgzgZBymgxsF5SQYSOhAYV4uOtd3njJb2d98Ipg6kMw8Zq/h1yAr0k9g+
VrfZF+I4bqhtwAtDD8Y0QBxtjimSYwfIktlVdm6xddGBZgalKehd/YtIIuIdvxMLr1zO/gS9StNw
sJQeyxAh8h71GpQ60Z6oyzNvOeX067QWmMEvYb7DROkCNIZQUyuFAlOvb1lDx1knNH4yd2WaZK8r
r+CkmikoRvzvI4eU/o+jOsvVFSWgrydlGdapIL99qPTQneQcc611Oon/Ab3JGfqeMX1ao+o06umh
8vZGBYpMgKlvfN3niid4OiEjPn24owe4P/wf0BcEtzsUH7lWsUWB94z498es+fxDQnuoDh/nY4gE
ajogxrVEIHqfTctwuMob0UDFrvsIzKwQf41Lv1n0nRBcPxJLM5UJ4FJlZIFS2RYIJdrd7gF+hih8
YTOjIoV2JrfBdD0xK//SdmI0GUXHf8DOIxI5kGMsMA2C3TGy4lOGqx/ul4Vad3YQV9RCGKNSBSmP
swelcc76ZHQsfBv+R3E3Qhj5zVjf/K6AoZcuRmOR8oDZH3kuE+SAguAzah/7ESvKGl/2j2XOqDzR
8iiw4nialt0pWtCS6tkAYDgNFRgBuQ3JSTGYVBXjfuzTxw2isrqagSJPHE99MTW5AL6pXUJymVgE
5paNBZsADMcR1hyMFUpH7GPeGsBLRgE/AKMgA2GARIoaY0qLY7Q2ngQkpZxzDK+JTkB2d9bPAKqB
xP//3NfAVyngOJmT505S7l2pkRJA3zrYI5j1lANxGFxyNlWR9ZV+jIsmSRw08iQNYJKeIVFvFn5l
1qGHvHHovG+z6dzxC01rj9zFwVtlh+QuGUZJ44LULZ8d9NIxqFBTw6hzTFEuL46TS4KITWMTa2iG
iawcNB64KNCr/hxLVwfmEPiO7V96PBbe96vC5j6ZdJ9pZkuDE6tWqujrPd9sPbGbOKfqfCMu1lqr
gnQGK2zc+8TwEh7mbOGCbkbR8rdZ+ejP/5kyj5vlz/VpfsT3EioUydZUsNTWnKPuMXaHjUC3y2/b
GmPmlTvqKIvOTpMd1gLCqFjYWWqhpTrAlg0gDtNHHujuUhV37JUpOgQyqvu2yfL0ys1KBhX+KKzc
fwwwsbhs1XqR56X2EuKNYJNJlfGn0h4d68iUsAfHFhWSxteq/l50Xe9B75wleo0rPLXaLl0cZ4/D
+TtblDQbPjt5GD6CqdaoLwzNDp7sbMuVyDrKgABFbLepWep5iWe3Gx/9AEaAD+qIz0TQtdMLG3Xt
s56GGUY7kKfin1p9z+rCo/yd0eak92VLYq1YxTUoSy/7gKhZBLIovInn1DYeF2RcZSBCqIdzpQJ+
98rQYHmzURIhcv+960/FqHzeLpfZn/4+jZ+K0qq++ARWl56UCMS/tsJWH18ASjhi3yXtTN/dMk8p
hr363JRUnazoPzjnW+sZCU0jaw7fLxTzW6MNxyBoD+X/7zjjs2QTAfKiYAfG04VO3HS8raJF/m49
XxPD/s+Yn+z9K8/o3QiY/hQ2Owp6xlB73PLx/Ldb/KPzdc7AsBfkkQr3xJraAEhegTtvnN8n6oXO
vRF3Rv82uX3wiPSBbdaYW9949zkFf3UcjE8vnGI7jymx5eK+9sj/L/mOK4+TluKQDEqo6yIHAnq0
GhXokouz+YH/biv/1C3pYYmZtYMP46TSbHeTg9Lhu/ryEUFxRs9tGTXErY0InTDpXqBpQf9mHK6P
2jF7bW0saKO+hhkzIRYnsVhMC41X+i1uG0CBOfDFgVwiXx1PXdcUY3Ez4N4DDDaZZ8lgUhbTvAyQ
vaX8ZCRa6AUOrcqYzmY0xNkF2vkalIbqfrKwMkpYQOB+740RvNloTG/JSkfhyn4cBdhsahtu91ea
NNcFiukrOsYLZKcNdJ45Mw2NjqFrOf/v4RBHpRrZh9lgJn/7ua1KojRK9Shb/LC1mdgBwm4ut5qC
IbuNjzS9FRojFqDP03lRHGq2/iEdHIVGJGJ08AW1CU1R+RE/psouENV28DWBBZTGfc97O0HqTwnW
mmdM9wjCsukKN2qX0U6w7ELJHDTzEcQ5PcP6FZVEVoF/J4LzSwcN/07lodkHJjQVOBy09bSBymwP
QIi03OlXCj6VclHKBXXmuRLluQ5iYY+6KbY1FV8ra1GBaJKT0AOSlGoamYWc8oO6xCHOKG7sGpeF
8wCJMwwQ8RJ7jyvvcot+FtgRD22B1nO1yYoWSlyaYksIIDvyyJhSaUOyZcQY4nvJh4mgvZq9WZd9
MPAFAVLirpMKVk06BhngHG87iAJIS4VLaGq4T142hdx6ELiOJ9khhoKcF3yNDGZBnvbwk+gu7J6M
Pb/65XDtDlI12Cnzk5bMFf/GQLhNv6s6MLKvmxj6J5L6KuSr+q/BDVn++YqfxqNImu3kEBDwVBuH
Dd3NiFcUx767NF70AigpY2oH0AC1ZlEq/SGw5vX1bsCM7QfGyshRT9Sc6NBeE/hsEPYj7ILxy4Ms
NDFqF8UK8Xz2RAFmlDgidkRzc+8TGyiT/micX2rDw8NJHyKQcgHDOitN4jL3dPvwmmpcrpckFLGQ
fH1WLGzW9XDZt9DvTmixYAMDT9v2pQiljs3DP8jv6K8yG8SEK/knm6eGOCKXIK3Nbrz31rA0RMjQ
hXPUP6pXE2X0ip4wyYPH+mZVWJbfCum6iggLnX0+IlHo1eSy62FretQ1DKarwuuBIDwT5TFv3o2I
b9wLS7pSHXvZ1Ezg4YlR0fwpS6NGbJUqya1KAEEFau4X5/julyKFyZik8Ymji16aK+ZFB2Q0SkvU
x4TZk7vbIW5+fQaNMU5aZ40/8jjF9mHUwLdb+wbhYbiPCifDEpf8HpUin95IbDmOeUgVLwSMQCg2
if98VusA6LtGOrR6gRvGyr1fgVGJKq5faC7rEWJQfjjoA0dfwUP8VtFCtYNdF9uyCSOUGW3JgHia
QB+aEgcH3S/CsD2251pJYmuUqcJl/UQ3pmj/HoRRHPA8YurEr4364AJZbu9d1W4Ngzhej4Rk1E8j
YFELlaWcBJQBz70sR1QSHA5icHPAc7NNhdfD6kg6v6vdizL1Ke9Fg9E3GciCp08XdjNSQyzJW7ew
1mk/IoOn9NCX4Pg2XFLSni+Ar0wGZjnOvHIYafxt5Qu4JADtchbzzQT22asOMpAP8IGbBtuj4ZCL
cPZq19fb6qMemofTQ5dyIfyjSk7oNXijwYi9+CkefHNgDugJjjyPRepN37jTWB+FmEI8rUp3dmWo
4IoutAZtR3C625LS5AVO41NccTRl7bIKfcgIQGVahZr+JsFfLwdIcqxkKLW2Mt0Z1jQx3NhHuKQS
sDbI5XD32gZV9gbCGPv95bxaSxAVdv4eAleBlRI5BdTEwbAwJ8m31S+CgjozBpbs6lOFoDzk3g5A
IjRZI8Mp9sY8SVmcTUwblKuekhm+o/ODtJJIVGBfRvkybWQnDHJeAAYxOD2Lgh7M9j/CKkbQ1OmK
OC1N5TpOtydid7c/9ZAHGVCiIN8JTudylhGjGn9ERrx4JhCzUOJLe63zxITy1xMtts/RFemLoxBr
nYv5XvOJyu/5uvEdGBNUhY9WRI4FgpipMyylbYBAF3N20V70+iRd+Q4+5+lCxVOmlQkZUij77akB
ABXy6j4ZZRGkBaKgR32JmNp/okgYZC+96nxKgXqEXtXi1XwuFQO1haQxACKKf97haV7Kae2scOAe
Fh6CExqPzulF0Q0bfPTAOJuQa5qW0w67nTGCGnMNDMDYWJp+m4ML/cW0NjW/Hq0jyLs1i/PlbI2B
RlNqvhHtm7Nf93SbAmMj2yJZt/PK9EmA6ptvUNT+gicCys1zgPwlBrQU0Ttrb6NWoz5g3MT7abQ1
J+m7lUINAvzuO+BD0ZYFq8ZNa1SkKsmSJNjYBuYhWKjps8QFiUdIEsO4iFIxbooy1VUZQsmEmKLX
AQ1zMiGShfkA4GG0txsMrh9kh2w5BNnhxBtYg49nVPhBUaEa/e5eSNGTnWn0ih/A4Nj3DEtEHqvz
XFVfyejf1DmWbm7tHWc/hiMqDPVpdFrhpamF7OpD1mGp1cQY0Aou+K92toeAPD/5vwv5vWXC7xqb
BpTEXNjQJOMGWgXFniKJBeshlyMVolIP26ykx++RNTVYL+P3iTP/NYj0NeRhnivuAj1NL6k+M4tP
QnJHMwyD3/Ql/VL1Q988nbUAvvl7KiUe7BUPnmM6zNNFN1WR/2Dq8Vb+CQmRcMqEeyUHoquZFvfy
NbzqWK0m827cNsLwg/yxJAcBGBdYMWlYrePboHA150SVw92dt+HVxKh3vHolm3nQzruSaFjLhRrj
EgKQ7Cj70/6UVKkL5semU8AryIWsCmHge91+vlVchPPfh7oMmIXThB1306ScRs8qIkIPniFxSC6w
2mEvdsaiE3t5hGRJb6SUYuBfY7nJ+0B+GKEdUFuEi1lQAoQxaFJdzoO4NAqKZUZsq/jbViOHFpZP
g0Yp+WPjoKX2lwMfTpsh1N5HXy31VgZFz0Ueyh+kn8F/64bkK/cAd9tACAneVPmQepcziLxLSvLw
GZVuI7XclR3qicvG5zRgDlwM4edo36/mKE538dI/sMPSon9qcHt2VAAUbk8PRh3uWm8fH2zxrFbm
EmsYx4BrQB9KV6hronzkqqvkUVZSi5I/BI35PJ5VRMZ9PMLn0QpKLb81iCpnELmbAy/cBvLzQmVR
ngDcyCnjJo1jqpIBkqYd41YVfffD9+w06qZnEalyRzCQEDw2Enze47ZJQRDN6oF7fTTpeQhbespp
CIejKcYNCGZRUUXEWiN3viM5vHCDqncmBj/9VxQeyPfjFL5HlK90Oy1vtrcjxvWoAsTxfzCEm7aA
a70qytqehAOOtTbmOMunrJ+3YgqMsq78Dwfbw0ONDrEiuSh0EftOdwyS2vqrdn+A6rpuKZbMZSfz
vP9gh3UPDi9x7rcclNyKQYhvvMCE+2sAd7gN5lOLe2B7OhfI1IqDdYv+7SwN70ZE7kKmYG++qUUy
YPbljlzinfsg8ayoe3rVhE9UJoX0rKoUTFBxY2rN1H54dCl0rki75ZKGwXoM3i/sKf068mpy9ofA
fJgGMQLKU+SrjNurTlRgQiPiaIwHf7CjK7RK3IGkMPWz2tXvXhQmCI7qXSVF9hWx9La6K7Ut9bf+
awIvWVT3e5ZoOob4A+liOvuFIhyU1IUpoK6gPeKBRTVuf+T0Qs3zdd6GPcML2GqEZWsRmaf5NYsU
mKvY+pXMYzssGTL54c+cpjgaYfcqPB/aWip2G8v1/Sntgi90pm3025Ahba85I5Q/VIvTx7qFjTKS
cZFv8d/TAcQAbym0njWDHBJP3AsSqp/fuqDySba7wsG/kBq8VUCOGV+EQ1I3JTqbGpcvKDQvBWnU
u2FEzOkFM9LF4uwL2KDkYtLqa69kKZhEoD7BdKxwBcJEyJqMNwSP03edYXqzmvGAmUeg079h0BMr
B7E2SdcBRIKd9ql3ZNzNjvYJZNDvNnfytllkLYii3Q8qUgoRL9nvtUOarCxHJ1w1s7WwMoer01Py
L6AwzNUPDjeNet2E4q0L1D23JLusiRQk4DDYqeb/wTPcsLkKfkN9r51JL0WJB06rPQIGFvSZl/vc
do9A8CbBIx15IMzRUnjdOeHFTHS7vtxBFMYyyaTDflbjYIIFQg6csG2nPa78gqBCGAKTPNQABdxI
oncAYCsUmyC3tZ9qN6RXEM3cOi7ttCnWuC87yo8katcs1uBelK5PfQ2B/LL8rFxCNAlZUDMuUqEz
yzjfCMOiyFB7kYj04QUsg/4viDxrYU+rQnT2UfL8VRIx9CNOORJP5/HdJHdNZ5tmVJ+80bUw6fiC
t/TFxwmEz3agivlEOsAYBnCwJRQtuN/PsUo4zRdRTUGjUlhpCsqf/w4FGl9qqtaVEUDGs2v63aem
4FhX88EPrZV4/zAu4CNKYNEVbUVP0HuYSLlw3S+vcWVEIfZIchbFst/RjLUH+Q51g7RxUoFSrTwD
u3URUpnaFJ8QFzUPN5cX5Vzlz6oh/9Z50yLd7mvecTKvJF1YilYddw4FNXSRkPKX6ZQls/nOtn6j
jKGqAhGRSeWD/wpgz8AaZz//k//kvh17e+6GolVg2JRgjOtkbqLEf+I6sR9BbwEBqVS/hocJjQUQ
JAqKKRXi3g+tZiMJB6nbmR6K3yleTHGccMolIaVLZH/d99xNjgMOZ29pWDTNjOgX9w9UmobbjSdG
jvPr7O8z2gaWFRlgcaUdt4Vtrw5LDly67o551/5hOm6c/UPgBurbW86XOnQLR4r450tVSEsj/w0x
PKpqHOuA+nz/uqm2SPtbNEgi7DSO45tXPfebtEV1uku6qpI5ABvey7ob45+2FJhaCca0eCMV/2tb
E1rTrxZUtUKuGxI7Q2vXCQd+dt0OfaATVUOXFahL1kBmRlSW9M1bdsyhgn9sVZWK//8OV1qli0Qh
sC0zosAWXq2515iL25OKEWgqmcd/vUm3tXNLqg+W6OpE0B2IrdnZmTI02vwR2zGKhzvhT6n+yYx2
G57VvhlCv5gZ9VwC8hY5CNA0sYgdAAzOCqrS0LzkgKbXQ1Nhx5ntXMGaHtUS5jJtES60+Tk8avRl
Wwuv52VKGasaKkSbs94/uyRzPj9HWojl0Ab0mOYqtrI6EcinRLiHF2LJo7uzETjHd91aP/JRo8MT
5RZOf45W81PQAKfi7+0MQUzJ1O+dDTTeR7EHk5+Vmfx/0WjV2OBUny/vS5zlzkaQzmQbtfePxDht
RPN/+VwW/XxDW+/6IbHHPMxwsYwyJWQZVvt2Oukj9JuVOaukuED90S/KBYdIXbiGweYbLw7k2KG6
cfE1XkyGXQoup/yViOW6vXh42tFWkJrUHSWtqaN4s3Y2CmbgWosBQ6ZyTavmLbCq4r1e5rCMZPZs
CgP1WWRPw20h2MUz1Y9Dup9HS30x/dFPg9VNGrutlb0xf9jNc6MgSW4fmiSMJFLxHGxaqe7v6h8N
xtM9748y8Hjgax2z7IdSJPf3i00p1JRD6dNBXBdI9+FeYoKu5XWIvJ2zJNE6+F5zCRpze92hka3Z
80Jz3d10iLqu5URwhbFIYuJPqh4UJxRlomjNYDLXvYAZYvqnvT5+XuV1UfgWMUqwD/Z/ZcTg1fbe
NPf9AlnKg5D1FTuOGbRRmOGQj9rX85Vu3olusEFbNN+VvfoujTWUqjRaIbcRdbDJrLlbBNzynBtd
TfpgZ6fmSOaRVVYonpEVeK5D4fbfdRwl3xO2fm45SByxoZTcYztoWyFkK4t6VoYDJ4Jv0WE4rAiN
lhCBCrx2k/ROjp0GncvWPihlhQJuL23uGP9HZilkf6Z1fOoM4vQ4gQaJY9weuKVuL3PnrVf01KbD
BO6S3x7d2kDO690UKd6h2RgxTbC/qh3hljSQxGf7YB44LEp7V7WHbGguWk1NlB4osjLTcbU6DQQ8
h/Fx2bWsgEJXWdGjJLv9CK55k4q4VdfkBH6ZqNYMBpz8At9L5f/J1May3BFHhCuQBnulafnChy8s
jYJorwQd2mLSIxJgyN3m236BYjb9BYFIGvc3Y1nlaIrDTRhFD8K9ZPVR/vVaF8xuBkw0Uta2LEn8
shPItqJNVwuHzRg+JxjjUt6iCfxXlykS+uIz7il9yBSinjIeQrVcOsXfJ48G3egLNFAEjTVlBMgR
DSVBJifBVoGR5xXhXlkK0B6mtUMueAvYRYuxBNTHZ34461OIJj3h9UU4HtXX4hKMu08TH+tfXGfT
ecztcAZFKqhAR1axvazM+OKuoPeA4PNJnGhpdlXe2MmKyd2gs0yzwDdzk8HPKOn3Q7CwLKv5C7da
1gN3oNWJ4k1whneKqjtZx61D5tiPCxq9wlK/3DWmbyuy27zA2ymVgv/2G1LUiK9NiG8auYPbd1Cq
ifnniUfag9ZIXvh/wfpNwZnC6YE0i/k2SMZ4fD0IL9nam1ZwBVy88AFe0ngk/N5MNccD00xONIKn
1i0FSzck8tzBZHI4loa8igSPMsRJFUtOU/pOJyA81cDSRzOeSQs2rxds4ZAIqD8BYhHbuqJ5VRUH
jaOLHQGZb0JX+bkQ1KQlQCwXjlpncUjPXCYULPvgUl9tWfs79KgMSdVceOF8Go2hCFtZVvGe2lB6
Ul+Z3yLmr6Rt4+NplGCi5cj8D8LTHrYS9F50YltiuqV1jmt8pOE28C4229NlBsg5/1OVZTZTI4hZ
7lizpeWV89wJOPE1RTkAXjhEc5suO1P0AuQFXA/p8PrwAHJTd8My31haD1lHlTrPZ7mKYs14mRjq
PMUyU6MDim8AJqlMBS+mMYm/INGuWqmIu9vDjDVT2FUNm0Y2IeCyWUMZzgHTvxjnory5L5QDYnRv
GcuEplrVKo69gwPRycLGiTAiq532wfndwp4On9ZccmL/pFZA2zHbx0yJNe7npHFSRX6g6GLD2v78
XWLIkoigV0U9ggzCncZo7j/JJcBc3tWeKuPG3sOT1KHEkkClbGPoFOvo4jhDG1BY4D606udd/aLT
1ZRUgXlFtjB3c1isBaQxBg0d9qwbD9hHJtGGNvWGBs54OZUM5KE44+pob6ibI2WrP/qhRJvKsfv9
ukfTYEE7xFyc3xHXaDb10OJA3Lime3h56UcKYAEMZK1QHz95LEP5rthsI6SXcmmxlkaMNmaW8OFH
V4kzQ6VCsgL+0awpNcu8YZd3h3ZuKnNdpOsqT5tVnyKIAo+dGHPedplFMmR3ktYGNsiVBjmDyxBk
eB/5B6VIHLlOo8cAaLUr4FHT+ErwAaS1rwU4YHVq2a48f8jrQTSLj50zSKAalyQfNdQTHKjgrbss
VPFKwbxdhb2r0jho07USQnYakKNjEEsDILGm8QI9G3Tc0zArsDRL11OKD7RhuvU/fzPicIMunvxD
34jfrdOhkYEsZ1h0TT0oWYOjtCqRcOBMghJ4juiqRSl94/fqQFLMtHSFQa6hfEnOdDRLVAJz0BHW
0VA88f7S7kg35dUmFPzS5d2peLL9oBOVgDOcCQcTVJXDxmjw90yeBzttGlsqyVEFr3EhpL5Ei0hy
NKJpGuWvsNjcRTXKmVmYXAhrz9cyx7NqShPTc/+Dyhjr/wMa/9bixyZ4qe2s/FjsXWz1+I/b64jE
uHSpL/YjP7KRo6hyZHwMGw2VrebirBJvzpvTztWyckT0uW+F/74qqEx66q2Op5aY6pBvoS/yUoPc
DTdfUzlr34hxxtl1jAaT8AnSVVeaTgFrOyp7afJYbW19t3ocqunrVhS00V8qdvcZYnSwi32AkVZ+
oxPcZlkoLKlBQLaq42zSlHRYMOjLaKeRVbJtco/SELZ5CJtA+wC/jX60r1BA5uSQ2h5FTPFYpZ1N
6K05k1h7tyTH89KyhsCkW9k28tTQOYt/Kwo3zrm4IwKD2ANXOcxPChDQtoFGf1CNEbRs6FOjRxjg
Bc7WxLVO7DH+jci6CxXZbJr3ApIrmbhAvZjqqcFoVe/0VmdstSpCY4DlGMtC/GBbCljdwahAJ4x6
/lotxf2oIhy2HjU5RPL91xH75hOU+02qELDs13pBLyg/R32CvrM8ZAu0TN2VmD0FjkOy1m+Dsp52
LRmu4Ze3412kre06rL0F33qHa1QRUxl6AWqLODzToui8fgizJsiTK1q8SYIgrKUiPIoRuFb2XZ7M
s3d7HJP1vhVeYCE4LnaBbiCElk7nXstmDMUwPMYwKS65uMIu3aiBSnQl7j7bh1nwf2RfSUNMlPaH
+Z1gF/SYW4HpHJpuCOj+rcNGurltSioT0RAvpWOdcdBeC3vwc0z4ow1/FiogA1EjCM2IT2U5A+8l
tCNG7mjTYPJ4SQzktuqPypC5rMtp3xMxI63nB24BUxoUB9JBwM8twGWIAxCSk7YiIrRWKgGlHzuU
nsDKyghnxYnLInFMPpBg5gqfbrsNk+2fppi1Uv+b/2MacRc5lDwwOtJ02NQ5MdbMj194thv8ggEg
UuL+OOOxPtwEauWa8JNX1TGnP+pZaUR1zU8IiaLqhqmLbX1UPU8N6251NzrelS0RMzO6fohdqWnt
us2m70aU/RmlfPkR592ABuTxUs60z1cDx9TDGkRDkbDyTTCTMmwJbYyzrySTPV8OpFXCfGYdltg+
cZByg48+RWiqDkczsAU116TbW0iakJWM0IWcXEK+BHWxDHWwar3MBGKxtfOFaudV4DBO8iHcV1lF
LRtNH4YbcZwv35Vq0OaUaY9oXzZtjaGt5yjltblwhPhOpTUwzj30XLujqU2nxC4IKq0AFqdtngDz
gBZnlD/PGRAgbct9FtCkPpIbzZ7PNlfm/oDmnEfwIATYOWyuB/tUSKMnl1d7Obisv5KP+mu98mO6
nKGnaBCxRfgxPwdNpQgvzI5r+Kq9ho+C1DNDI8GMFfJkzrm4WxI+N9wt3Ux5mJGzrmwD01hBFa9h
5cwj1d2k3Ce22bblGh1Tj23qYnAt5uf3qU4BiF3AsEb47IVQwFCwHy6WntlRCEYutae3mTEY/NQg
bXA2Di2o8Z/43Yc+jPj/+XoFhgVjelWhVsVetUbSkUwTvBSU5Pw3leQDWDP7SCnbm92vJDRNtnj9
t/mOivwluGXbm6J7qtEjrCIe7rv2ZVyBfOtThNASkwXRz6FPZYl5eBtRscWc95M/8H741D9lSZdD
bCOuBpZeKl2GRQBiGpp0+OsDS8q5KvKMb0csgAN4oWASjhWk4FJcNHX4MU4RZVdUBSxDvxHe9U3f
RQRog/ZjPWPubpIAk0FUwfjm3BTwsE1TA3dWRn1Jj5jfILKTB633MCV8wpi31zJIEr60hhWXvmmm
k36RW9QnLmsQcHioK854dTZ3GOXKtC9IDBJzIIoqfOFNZuSda7G0f6U7efJb1eb0JX10RAGC68u+
+LCVcdk9Cs+zB917nLjwIAa7ZjyvLpHlb1PIMQYEMHT66NqBWMwtavsERIqV/Sg+PqZgHT8sWkUR
fI3dDjxTx5GcicEuty/gH4S56vVWDPF5AGR2qWF5rCZJ/xpJZirj2Nd4By+pS5pK6e+Xfp3w6cQk
I81/F/MHYJaIjUGRLX4h6I2ws7kOdrT5nBjWD8vWtFbRTfZpiyKAVxDA07yywOSJ28tZwi7iLFIy
aXpHv6vBdkQk4P09HrafE/QkSYjYgCRF2niiT88I9qVo3mWbdokFdEipxxmrO4jUjrWmEjaZYL4v
TlLDAwdakjvSTwwDBhvMwHCUsWkVnQAxpi4ZOxL/OmM1NTVwzEvnzIudsne+VZ6QEW6SOaTQQ8K6
g1ELzw6Ygy5kpEXIs/BT5nQSgypVMGV73ngn9x12K2vRIXYiVmoSDvrQqBfW7euij9x1DSw0cY/3
J7c6iSIqVjmnWZejL0EMd7Z3/e7KPFBJq1rbd7PZ4D0Rjko2HHglPMTNHx/Ehai9DBulTT6rtMXY
jYWc5Rv9nnwBnE8pc37m+0tEn2VxEJJ1/Ms3A6xQn9htGsIC9y11tIqhZdFY1xs1cqbSD6/v6YsK
WhC68U8nGWBNuaMNqP3x51mDKTKPqA6wwQqPUuvxJ8fdIj9AuWpHPL6LzpCY38WiUTfZoDdJ29QR
u07WOMwUPNQeGMdXRIjLPFgHTF4x8YDkMmDBbNncJdiDGXJDgtxon8vp0DY40j8mTftwoMqbSrKg
ZbcJTSt1YtpuH47Dds2SG8gwpT2zhUA7dHgWPjeYb/LWQXbrQ1rRLs6j3JcB5569Hil59G1GyMDP
Wu7CSESqUgVZeW3dExl73x6yz79NcqSUI5Sy6mxetbwjA1v8bbT7LjvSY0VYjGeTJVCajTKsCNU9
F8CEJzjOCWMvpr2027SppQFkasDa5/XdBGKDtZkLkCTjPGv1O4/ljKnkqjrl0UDttrNCGJqX0fkR
3Q1VJvnlWQU5xlT+4B/8KiorSeOI01lUgqiOMXvNO1r01Se40NXx2oqEWEiZOSN/GPQqvEe4LCXk
tSyORYbdHFlSWQQvvCWH+ubyBb27fCfQIgr1s0af+iqQ3hpddoRmOYUPv3VraUGE6c24az2ggN6L
0MfO/xilHSrqOPosE4wHS966ciZQbMhYmO/LJUlwEh2QRwnCsLKsIySgr101deASV3p21wHKHbhe
BuQANxIJ4LpLICrJPaiUno0r4H8x26YlRCqtTPFXvXjVTX+kVi4J1w2ZdVhqf5/1eP/Rr6RXFF2d
UIcTEAA4SQtcMGP+6w1sKVzAbMz3SkH4OSHWlFGPvloV9wvl9bLi+P1y6U4JN7VgVGlVat2+6tHl
Qrl79Im/H/oQqWYBCWLFnT0lu+diee9/klFngY3tpySC6shRNcN64DJmWKt7WKD8oOzNQR4P7JVj
MCo6cK3ZEWVNqOv2lRsEIhfuYzOWnZ6K49RNwP2EqxWcALm9tgDzyxy0LBIftPQfYTQrdbobMr7/
ooWniCqfRp1yGKErpqrFEHqPLmQzT/CbN95M+qwCbt5cRQz6FWbvZPJwNHFgDhaq94JlbjzCAohB
PyRqeK8kjcLOzpNC0Gr0wMtVEUjYvd4AYyp9K6LJjhUcLa8p0i0hSUsxcWJfu4Gf/eeVnyxPkoYU
lOv8JsfBNr6tNhaTg2X4uuOEkTT0Eu/xq9G8kMnsYm1DxN/ZgFEYMXuv/SLdWXzNoJ0/FS03/lzF
yx+JyKVSxXHGgNfyaCnY5F0gsjMJwok8pJZfjVItQKHnk2SBjTr26cIkVmQNck7ujYvmjkHMH8OF
mGApW4gV55Jj08rZiDjzr3goGxNbbQl0sUSjvbrKY5cL1g9CmtvExSPwaKu8j/mO1qzdY/ZW8NFb
Lau5TN7gDWlAJegXiel5tUBI1mrRI9YN75qLYI7urT87K44Q0CUBWfvSUUHMO574b2LWRFYHHC9Z
R1MHPXph3CEbbEnr0MkjvvlW5h2v19Ue/98EGkQuXJ9lRYhx2FGxSmowK8jBd7KN1fBdrdMsxHVS
QdVmbrKg1YnEPwJQ/D+emoccPdpNb7vS1ZvsjgkIirmBJx5RBCQGrQJqhWV4fPbranNCn7d/MFDd
CUDK+CkUXvEtPD+bSoUBg1NTYoSvQgOxsNJ6lkP4xyP5dpvlgOx129C/7Lc21CxOpQjVxNrZNelO
FuWd7FwN2WbscUN4neq/OlN2SukKVTfPZNx/Gz8AsflgV5vtNKZpZj/ktRqnffL28raPLPKlTi/E
2VIBF20WLHndOj+95k/LsVObfNYuNTAeMyemjV8cHKeB8HsTRtZbZKP7/psRs6adcjnXDr81r+gL
r4cbY6cZPEVeXSHc053rlKxihhKcqkFbL07zXeixfRrGIMU55Ae82x1Qbn3R2mhoRnH/7fDevPTG
GViMu+0gwWUTJtZxT3SCGpwX3duVE/SSjKHktwY4Qji0j2t9hphrYOy/Rr2E62CwlzrNdg/pjqrx
zDVNoEtGirF5OK5B6TOUXyS+0YFJnSVnj2aa5i8U/bjDq3+IrF+Bi74y/hR2N4fxM7FN7sOrNRb/
XPg8z20tLbCgz1hnYTpCbNqNBnu3BqNEZOQ7fmnz0mrvZpPiG5vsxfSL5p6zFKpAEEYWgueBiBs5
mMAoTwsJTnte3hZ9cW3uPwrS4EDKpKGiswESKolQ3BGQfybxUdMP3xy0HpMVth26RDVlgKzgja7A
qlLrm4SpJTGFvygb2r3icExdUoUO8haTW7zd4W9VePpcj5Cjn4OgXed5sZeQfFEyzRtvVM8V4gbh
w8UBJtDDp1zyIJljW0KQhTMr6EPKIsZ7hgAcJfoA8ZzdCnvQ8aY9PhxDUHEIz5m2q70E5XMsvGJq
RkPLj1Rk27VC9IrjfWavtZ4QTjeVVwX/5XH8p4BI+O/zD1NNYWcAmUQAKiG0fztXnlqkuo2Srx7S
oYdoZ8Vmm0G8JPmHfIpAWqJZjW3lixV1citEzxxsKs4Ifhuj3uKLTK2b08tMY2umuvbmYO91lwKt
Fji0wNG4Mn+N7BksnhpVFWyD5SquXaVBJtH40NPl4gy+zOS3z9f+uIVC/GZDFStBgE1FwAQnWXTK
sRhdSJKV6kJjGYIsLC6on/V2+WzxwMzP2jDd9g9J8pEmF9MIjLLSfu8UEP7jqsqI7/hXAuwdqh4w
VahqCaU/EzYi/smY0FTl3wvQS6V59rKhNJrRWv0Gdm7GP2VJQi1zgQ1EHM0krEL0g/o5ubsc1IR0
xuvfpiS9b7RDFkqXoQmbLUE1grP+yS9A9wN0BXP1iAp71kJBzVrFPJ8icOmq5o6V28QLOU1+rl7u
SIffALLoEO6Fug5cuO0LcB/WY6wo72UidXMW88PLchCeZsutotWovvIQmi/nsuJIBfHVkAzEyzeW
gTNMSZcq8fCwjR7n47iCEeNG+tRPdFUmsWXYMKwMreEByK4kUVBRHNvO1u/uuLT01DuP0jhwFbWb
qNff+QqRZuH5wOv/2x6xctBb1Yr93+LEkwJB0+/5JznjQZPR1nblWWe2MB5TaNzR2If3ajRVPwrN
FBEgtCU8zlozjF+sR0vot3NMwnI89jIl9zc7zHwoNf8pURCWnYXg7htc2a+6A39/uymBpKBq8OBa
4eBGkCt/UtXRVpVfWDpSbF6QFOEOpBqOwD3R5lBaWx+UfkpWRSG7CqX0yRD4crRBmBWtibpV6tT2
rFPxkdoCxnynktvWqYV0LKM1cB4h/XSkIZxWFdWPbj61BG/lhvFg4rTebS1losU8WV8loTEnWA4b
BnRry9VyDkaEI0NCblbgIReKMBRQEUJBqPyCNYim3DTi4LYfsDxem8JVxXRSuy0qy1FsGWL/sqSm
UAeOsgMVipGGEA97oz5uPn67vfy93a0v3MsdN+AfCV/G3H0Pk2eApqzecZWbdpGcyyOueK1FN+8n
Us3z6kP4pbSAr15W9GE6EWBrxv5ApICUJHLAj0ryWnY6rqB35yD5ALJI+1UJ7B9sZ61RDEGcKiSg
3fw42b7ACi0Am8x2hxIlYT3/nt9lnK0TqbAzRsicRjvMK2Kfk3s5+tUeCS4IdMQWqQlYuilifKx1
nFQTK2OfzZQ2+lPdqPu2D+tt963X8+wRvNf9KFfs2oyQUrIU8jHG/5QvIq1mKSIFE2Vb6hDQtJwd
efIktbahhhCY6WaGA8u2DFx0J9hZcyMS8EbHq3yuYfMvNwFQIgoLvWUSiG/wJKWW1GKHmHrbSXQz
9fGR/ZSbLr0A/LZImgjMdhzkI/vxsMjSkvbGHsztKnCeTLjIypOaPx40bot4sq+5rPOi2GYDWmfJ
FXvs0/REVBDDIhFdLtDSS5QRRtMOnSAWMeZ/QmQz+91TjIlS5zDkXxVZh7tCj4qk76ptLA/03aqJ
QIhL2b8RqhtNRTEgs9JW/Fs/YnGOANPgR4kkPPAE79R5yobi/5Blof5eilDQGiIYRH3d6LeKjPwn
83G32Z4OCA9gDFOOqKHFB3Y2DHk8GHK89YGtf1TQCN3epnTph4qCM6JPQUjyEjRNpTI1CgNO/HOR
Lj/UnsSZV0Uzati2jn3ItJ3Lsm4/b+6in3ENDSTc4ov0LiOUAmbmZUUl2KsS2cBa8e6LXPXFt4Ds
O++07e7ZPi8ivL06i189D6b9ksGTnUXxesww7XeNhRm47tmXPMAzjeNCEPFmi/CgRGPrJHGJrfy8
ngKtG4alNN/h/L9AWLxkmL+YmKKwyZ1ykPEkyjcCBFRcDLgzCbYEWMdDPKOP0ddNEmzlggTUC64A
oLIcIbuhY8yF0ylJ4VFGL9OftFcc6GM/EojsR24UzVQGFFQ8m8UOGRPGhdi6wIhtDtyQSeAhrapz
cLeDHTpIKnzbIXAu7vbFznqhshTpiMFEa+ADHuiJssWtPk4ipn7NPrXy/+WA71GVGxjNeBmNPKfu
IO4t93FDgTLcZILPR4Ws89V9uLaa6OZyg1/lffe0Q/bsVOZ7+m1uM4+SsXXk2vI77D4wNb+ACCta
4DYZXVFqwMQo0cPWNI8KSxgYw7LuBxqMdnAaJj1y7U/AJ6KyYt6SnRmiYNbAKi/T/k5ERevPpsHF
5xoGV0DCKubOpXP7c05FL+RlY6Aa5GdK0FlxbC5Yrg0GnMKc4554WULNqj9/9ZEzxJPhNB+G3NZ3
Oy3lupgf+khX8Nc4z1lY8idmNebjLiN/Lz39U2uQ/8En33Bj0cM4BKJKDB2KxtT+A/Ue7PP0Zgh4
G+JhxeDrUlmBA2xpBE7ig9u5+XQymXpRY53k7dE96OgFtLPhazNxXVTIXXom+WwWCsNqIosUwWn0
3ptjdnGHaAAd1tB1zsSAz1IQTn09IIWj0DaJmF/ITxclil8D4qNoTZLXck9B8T5CmrX133GiTl5N
UpUtWxWgp9a3kHTQHoqlJF+nSU5cw8M4I8OoElJcl1eCGUYM75rrFRv98GOZJbI1rQr/PoBMqhRE
a905MrRBSE3zK/Mdq36BNPMeW/cXiP/PzkjCml0QRf4huqjo4P4lKQ1GCjcxa4/zIznk4ej/cKKV
c70nN9T8NkSHXwbffFBFUA8T6ONaAJ8n0G/1lx2QxXUJO+NINr3ABuZomL0J2dWHjNg/OpK1o/Qg
kjkD8tDyXEEBWFhBugxQ7PpKOd5OEy6aVtuPC2MJsxWJsBg1xP6B1BNRrWNx5vK6zutBl4kzwrs4
5GmP+aqUHQgcbY9vGYtSOWmrVg93yo76dZCQRaScgwpvfPzY/X8x7wM9T2leghy671p83pNrjDyH
gQS6FioCqDB2GJe50dnD8IBkHUwihpZLuwbMXyEJdh5fRTKWJsbiUEJt0QvQj6EF2nujfRtrXUvF
ZNmTbm6jsFhzEo82xD2zqLIyS1wcu2f1iT2anImwWbt7b2sllcUZ8ou9zXwH++4L7VPFSrs0KPet
8e7mW5i85/kTQP9nylaO3LTksf7lFO9rZ4m5dKoTKh/PRhEzvFBfVtw8cuo99OCulvyiEsBYOCmW
ylZ5IN7JU62QTUIAN2Z9XdgNzhFIuzqPRcTh5dl7jFJZ8+RXd2nr7ORuytq7Eqza5lMUchZ4t5PT
gJJzhyFriLyg7q+vMhx+gf+5a2gmjwdAPUNn/g0Um9rlhB9lkt7KYv8208KUhh/I27KAc+6XmdfL
7/bubDDCF5gpYz/ke3G639eY9WVuYbIfE3k0+Hljic0fT1mcUdS3YhVuRG/6YJhVNOQOI+xosunN
3vLjYB4CQSzwi+nL6NpU6sa+y2getWgwuto9K1fYGUwPHRd91B7reo6my/XwM536deLmCwEsI5AX
Rka0/6g0rUzw+sVhVadDQKcSQRFvh5cgv3yCU7zEcbWdj8odXPW1y10ALT+LqYTYnpY9mS7fAfXg
0kkiPWc+qTGhGdBuGyQnZ+SYN6qB13+oHpP4BDGzqdTfsBDKadBlkU9WlG6TaZrndensaDLu+dZl
sWF8+FQ2pWIq9MnJHhppFeHsvKVN+8orrgxpg24UEeiHuvYqG37hhF1zqwh5E2rDFnSa/DVyx14d
zinZs9B1SYQ4MQYtiwiuhcb8bsqtU8X63vELwsDcEwpQ5mzyESkeWlecgsiIaaEfFdOz0DQY+Csw
AxiBLdeLhh3rwUmC8zSDyWN7/U0CSzUumdOo8uIoan7KXO/z2uO7AqFWfexyxHaqzgV7HQCMYdbx
XgwIg6GfgPk2Eqgw7UiQHhMi8qSKqhrpvLTGcNS540hKeiKFCLOiyG/4Xm1Rj+c2j8AnwtMdIp2D
k2AwNd/7UKvejUs6tJb0ZzpVx3xFhefCPHUICOIQhbz9GL7Wi74vTivub8yzVyeZ8o7hzvjn2sD+
JRDkStah5ASHviK5UiKSd5Ux4QdrFIhz9s8LYQr1nTvnoxbOah+o5+KAK8r1hhChSoO+bne+ut4j
Vi9FuSmLGiO2xkMaomMY1QTRigvxkCVOSsWJMNBbWsTERIvfmgaml/xcsU9grj4Xr/hGqvX5gHzb
3DQhteMMaJJ8M6E+VzXAdHcNIa0Zakfy8GbAHMra4qwL5Iij8HnkirgXZk3ohnoFBDGzu9XyXDIE
5tS4+56PP5axFmvCyvDlDVm7rrNHhOXf2UgxwbuMD4DmHE8WGBxktz+Ajkqf4QZX9nGLlKdGoI6J
vrK1tDrvdYipfGNT444ww7M2qAeNJMx/PZsuc8w+zHkJ1IOR6xe2R8weiW6wMRZXqYsWNsbObiZ4
O0vTnFRiF9zb9nCz3njgPfAruyM7eyeQyF4R2Y0beCC3JJAkF0iuL6n8NEKHd3yIaxiipIsnS3SZ
e8trFYouWq0SJXOsL+SnXXZgzMDss31EbLmhg3Yrqe1Dbi1sc6Pccj9JBahDt8LTKOiOsolRVMEi
DFTzoO45in1O6Djxl/h4nIq7lrZ/4B0buK1+N5ldvvV28hau8W6KZYcNKXURy1NBI9mqTDhXaEJG
rhvNkKqWyBBqBv0/R09Yojk8/954JtcwnWcgiOT14ttbMUL8AN1aVeOpyFrID/H+1aJqHZoUz5dS
yKoZLsy0MCGvgd15sCveRwWKk3Q7Y0Sz3X+iDu8VPvWpr0j0uFhjzic3XZmoKktDDIgoj/w9uq2A
seP4uBZGeOf/riKGeyy2MzBzmg9Q+ekWhwx11xkSMKGxr5TMw621l6bd1OMUOHehYp7Wqaiz2IUc
8iiGciCPXzLRF1hyAeWiJx4hpY7+eqSslSEurHByQR7dubr/5QetWhdzAlo5QQCP5TQJnYJPSfJK
4PXInEjdE19foqnrdFitUH8HJI8SVZzSVpQ1X0JS4Ci3n/DjRd6DS8uPTY2CBEitQLUkhFPyF319
/JsBuEpd8gypifYA8NTT8hILmVxZHD519PdgJGidi1xoYbaolCcE5H0qmMkOLgHOqC3TTqUFWil8
fFdvXaMuAAwPmKxpVIXQhAodABvkwXz840dzKmhQJfEQ1sUWHD+QwVMyHvs6zMFJJhyjJetjQz3l
i57C6FEIaWHZpa7m3lOyrqT9yFOEkN2ICK8Zgj1fgBPW1ZojKPhxNJuomkJpE+o7OM1pGe2XUY02
hHtChPO5ABIkxRcmOF6CnWynyh0ITa9Fe7VmS+xZ9sqfIjViYwCeLOSwPBRpqLAXeIJaFPLF+Sy1
V3us4z7gCmP5MC1eZOs0aDix7qL0t10O0OqgfqcDT/ZO+AYYsqvSzHbMOCYmasXo1naWv1DQ1mC/
KZWH1mRNxXKdEe/O6uiChRFmF9DYDDeAhUqVt1oXNtOaGKC8Nr8umaqPAWCgHsZe3t7r+0sBZHJg
2jaSPAOwcNq3/cfUee23+VwTEJ/4XIxqyvgL1b0h1aI/lSU1yv0RzR7mwn4thv+ZP+J+/wt0gzzU
dyLFhQUpxbFu2TqUKpsZA6DbLscBPW8pBi7T0lGgibK88Ls4NVHCu3790Lu7jXt+Jx3WQmV41QZQ
i+O42NVKPtDxGRaa6du7l0fblR3OYitna7bOfkGaEs7K932DEm8HgKVjgKAYMtLUfKOiICXv8JdA
ny+XvJrSE4kvROdMao/T0FEmNDnugNXgQGLTSatWKovoHg4e3N11ujfCLdjv30oOBSWdtfm+YHLy
QYydoonMtTDCJ23TMotu06rUjrc+dwV/SZFXflPIwT8JWaSkxquajbD5TU9XR6TjUwtMRZh5aO1X
i011Dy0T0sbcgCnI6exWc93znsLLFL8K6pIs/5cizdhTyZNA4Y5UQDXUE37mGTc8LHae8E6V8Ukd
GLEUN7LGEpbHB7W756jgMFE9shaSIdusZ15yLnMIXQCAzcBWrSzSXFLTgLgzx77csZMCR4KCJseb
BvNKeC8N+zhu3+8aisnNy112UHCh26gJPqXEs4oRxDoxNxKOCdcqIAuKt1mEnPB3gbPbvG8Frgxv
0vtloTdODuO7m+vl2pSR9XmzcvQZT2bWAZML+2jgNKrJ599QHG8op9uJ1YJDf0edVquRTOkQ3tm5
3w8nY8EF7rDME/3wT8H+xvde9SEboyS5MZXkOrTcxujfmU/X4i4pdCnmF5WCDneRu9z+vCY5OFtZ
vRaMlGWqAXU9ZiqfALjXHCk40jZCKSJXJErfsLvpR85ATiq8HV+wnb5iblsbGF+R8RWqeT7XV78v
hYIrFJ3bbGjsPHq+sJwlHli0hYjqmyXFQa6HHiWNZUMfMo5b/x29o3JbTggC6KrzeK2+knXEIzP7
E7PwyakLU+In7Ylby9D76EcE2tr0EDhXIuMIdMmFT35KprShxZQVOQe4+C4TLiXTRXEIroAIDULW
lCDXuGw+2uFSrIXZ40PWRvEn1O2TZ4rFnm+IWpEYFjOuvKMsFMnRVXVD5JYpl1/N71IikOMuISOQ
KJXAcA11LTadF/jOLm0YvnMrAHdUfhzwmmGWg0aQ1EtkxvZNvX607ebEZSMNfp0qE1XM4xjWgtM2
lDEyha2Dw3zjDUjwD5rnGmf8Xk3Z1S95flT6yB5+D+heF52h4PyW2RB492UJVPjAQyLCO7xtIHtB
sepPf3/8tPws611vXVKJtRks3+RTm/UlAlH/K4TZ+gKVSeN2os8sR1AtHVkKbo4/jMw3Wmfz4wFw
Z3Y29v5Ey5wTcLBlU3uQRd2Cq+Cx5gRNXxvoio0doaM86LEghX/KcDIQAWDvN+NMfPcwAHK0Q1hO
jfPzzdsfkWfFxN/+ytYiyEUonEcQUkKokOBiUyVbBSKjTWUuIH0y/hrvCGuSsQ+EAnw0F8Up5gCa
VvkzWX2SHnq8H34P6jrifLXnMu4TTNVSsUGn8MSIZOH2iV5Yv+hxv/56Dt3LuRu8Fza+aLIrZfm/
31TSinu6vXl6K/g6GUwYRL63l9+cG9h6NoluGJHJXqrYGmL+OuYdaoLbQQjNgy2DvFhFRH4+x2m/
RdWKpbS6+ME1tnyUOxur8Jvt2EvNoXFmU75smpH9yfW4mNoH2SV6+VMCBe/TAJwQa+B86axs6a8V
ckOiJEJdocNEll4NbluWhKBqy9iUC+rrfbtiAtz6ETYXjljn8VY56SHpZYgKOp+85oRizvLQmIyS
qJ/tZqQUCjlp27CCFL3AKxRzr1rbrdAbJrnILvPm9SdgOiQWm415WCm2Di2D4+EJc1mgmbDcZcU2
uTl4enf4XZ1j8gh/fnvr1Ss58PpdNLkp6W+uWO5DbRlnXa+H1IG4EUBIj9OorGbeQlWf6gtha9O+
k+wnrAnD/2hLhQNIiRZANWbp4j7JeAF05Np2J1kjB7GrhEPH338A3d4a9TGgzxORa03aP0Viouha
z3hjxgcLPgZCZqstSu3XaZkgDOKfm58wUH+F1L1GjGOuSuldF3lbCoX9d4gpk3YInS9G2zg7sIW1
P64WB0FAV5KELc7g61aw7S4DZ6u9Z8OjXgQDj6mxTr8gfxoVMBBtUovdgNHIweXOrunp0uxMdOZl
Hn+imrB7Uy6jl7kzaxiwol8jT4E4+CApAoKuFbrSkCsNqpP2lKBDyrSqorRquoLxoOhhgSVd/Ulc
rXOHESoaB37IEB7+Qmh9F8KIHqtdYxvJGLveyC4sU9ynfSF/VG98D9LRgLS3NdM4J+W33ke/GWRl
49RiYjBRyVuBdrTlwOKsGzH/6lPsSSzrGKuIh3EXmQtsmrfNulkC+Avy6CDWOLynvPWKP1OIT4Xh
OlnL5iEDKmSozwtcdQrsX90EL7jrEE+6gQ0xWLHhBJlWtCoimtssrd3csaNCiGqug83YJMEHeWwM
JZS2H00HMB6XC38gVL40LhfDgLbwHF6ytsw7955ORY06yEm//RyOqHjS0NzRXAWa2pP4YMPS9VNw
agPU64P1ao8P3J4gmoLM4GctYLzWOfEetNLMmMv8Q58qGgdcJ+V0bbXJOD6Y6kuUdaS2hVZ6+60g
c9RQalsJqcTPXoInHFEce9i6mFIe1AIQubvaNfjUfzWY+nrZF7sYhalbivZehNTRyF1SyZBdmbHL
m5VomngpCVwHEOe7lbAFBZXTufbH5+HGkLG/sDBTLqrO+a5t6lVCZ1vDeu+LgdCaarh0DoZmgUwO
TIcFXqGhLBei+B6/4YA/LKGBUcdHFwcWbSzJz2eeoc6UQmM45UwGPoIkAPnbR6PaGTgXafF6qBqf
jFyZ7ZpWVeMme5IVIOPFgqikyE452fQMnauYiQju5WmVC6BjdX+O0NWwfjWP6x5Ie6vQBWG6i1v1
YYDmmMFbHsbDmvbow5vmC2QVwlCVXdwpqNAxBj1GOERVeIzOASxEaM/bpSnXmRtl86V3OA5ateNI
72htk4v4WikXrsAvHR0UhR1jS1RsftbFq4cclHdnmU4tAkli1oAUiva3cP5iidClautfrBXMHHyN
Ppv4QVDwng2prRT94dZhnfKRUI8PIuLKQCrZ5lN+24m+UCmJf0eH/deEbbtlUcD5wf8sjgGmuses
7qTitYcQpeafty0y7WVRlRfntrki0agDZhmCJTQwjRxMQ6jdMQPSx6DEmTZtZHveyHtRCxyysu8m
oB7M1znC9cfaB4ycJzEQDgOdHgHdqn2qif/7vYb3g5L14ZLotRD3WGOnwMgK/vs49v8Cc3qK5bjg
3/B3+uyO0YW2byIx/k7XVZ6N59E6hw67DiNiosJsCRpaRsSNpRsjQX+F00NHDQqkX13kbURDy6v5
N5dHFLIbYMW7m9cyc/HGTxfh1oEsD++gHZVlpr16SrTM+i/IywkvceDwwoi4DPQe/58ZAY6xnrTf
tn9xeSu2YZeYzO613kjpRFZs+IPe2Ni0q9VleaJ3p06NTO9apv+/RU64547+jQ6JWWJpz7VgrkbO
3AbLfvjeMvzYdTDb327FiNr3pR9dLsSKRE/8vf8bk+k256OXqd2OKgcRT7p47ULkrcFRD9ub1sgR
kkv2e8aNBziqtMFwAubkHXwMlh6ToVWdMLI5Nnhes3wJGgyFXUv3jZnRL9QJ5QnQzzJHx+GKMQRH
46oIYfvUHEDPVtDPxQvLkOzG5nkSmBUviUppQ/Yk4H6uWW45a7uYuLvu3Wwf3yz4X42iOORUrIOj
AgTtLA/G+aa6VCELr41MeFTQWQL0fbuYDjMmG3cfI3Lv/AGM35+H1tj1OIXAfRfj/K2PYov4pARD
2VK2pzFDZQRo3Q5ZA72xofWI5kJIrjf83Hq87ap9eDaWnmUTErwlzUAOtDntU8zmcb9mv7A9BP9Z
pmM9yxY240mfBftmDKTvdK97uVdF3rVMjvBMhEcnq30fc7MG1DE9MpBlHeFVjMk45cQstgIqY/qF
Z4TezeiBbW0+2YpbkNBNPXynsUgrhwMINYMdVlsO6lOli8Y3nPHWKZY0zQStErpcM5Qot+fZrCVH
iWdjGNm0q30/xX01TuRkR8mO5j/bTux44p3U9MONlLLwG7ZjPxH7g6HOaEkwOKIuYQOkluLJczlh
piXPyQ4t+smRHUM0FybLJYbpEScQrww0SXf/hadT3PYDX3mo1VW9ii5CnOqiSV8hO7WmUsaGOcbq
p1CH7gfVOz1bYs0+k6qyf6cks1KkYpqaXBMQVwvNdatmCUXxtgQLqBhhnAQzJide+Q5lpE79+WyB
pqp6ETAZRnB2VFpqqe3T9tngkJYOB4tMVYcwZYDlHPbR2uIx3kE6m0NP9jKRIxOzfiqPuXvckTtv
SERcYvyeOs/6B3ha42ZNzx0/+h8XGuUBooH63vrBNrQrNze1dFNzINGwCyqluslt+YC66PZ+bqgG
yvUzBDBkmd0NawtHZFjI/mZmr+FLicA7gZAQ8oKlkWO+Res3LmO3SMeB/aBT8Q1czpSp80fQDvDN
Lt8ompITaen+tfu87lBXOH3Ow3UPt9a4jEAa/ewY9VbwPxtKXcSeV5grn6CfzxXNOUXFDZQDad6i
bT5GgRyYW/R0/tmb1NQL81HSnr2xjWRNvfZ2oaDWvcyCqz2HS5moRZaVfMOMxTlQn0iSfbzwFm39
pQv98Fdh43jGy1rDmDsgspZ5DpAc21kl18TK8R4+Gpk0TKNRHDyj7pIKNAEG7cYbmUghLCCBmUH9
HXFo8xTAjVqJrw0oBEcx8cI4UuUuF0o65dUgGaPDtyHYY5eCq9u28M9IHQdppUe5wHsMzwgkEinj
sLTeN8/F3FxfOGnPEwtZe3n9ROPI3nTHqeMTsWDMdMTQdfmXHl/EfIDEYJ+9wg8/uw49vrR1Y8oN
nr4m3ziTgmGDYU+4rJ5PvocI33foP5uJPEd7ZxV6hUUmYD9RONfylmRUo3joteWiqO4laCavhoWH
UizabQgqTNr38SNAT+2USXgFzZmadgqX7gbOKRa6xPjDAw+3n7qnQLN1NCGhjgIt3U3o8nUuy85s
ddULcUboOWiNvEgZN8H53Ojzxs1eoCoRnZ5xPcrDMfuyNvNfoFtKmDvUOKmQsYlSUZ+FkuQYSGiB
v3Brfb+keAAwsvwoEMQubvdnJUWr/7ZUR1rZ3JyYGRyZFlt31IG9j+ySfxAkl3h4CohPCdjUwac4
ESt0SJsxCNwWYhZsjklHZlHoK8vWsdU5DAhs8udvg25bML5RmVDwz5SG+W9KVtFE/gVyjK61z6Lw
UodU8mKjXkRGbYYN8SYtHSQ+RuFkh2o74/ZpE8mcbhj+22Hw9kwwbcvE7nml/fHXOOGMEfCTpZ30
psLNRdRvClLfT5EuMpx2u7gvD71ayxo02dr+IbbeNwzd7zSgAfAmmSHlQ3yZsOENlRlyBBzkGNwR
uXB0WvGFS7EIjCdn2xu/KH1IBAYoxbW7Sh/91iMsLenUCCO0dycc0r9cgyfWb0S2jPFLaBE3H13c
keMlBECuNF2r38uOYRcEd8KKhQguGdmWpM/8VbzZAsDyQ6T8CRuUrxhditHysbTGOx571bXKGR45
UyTHbFyGaxbpFDkA7Rq2YxDZXMljB+VMJHF5MGL/Y/M+srQVnSQragOLp/EzzKtiKbCixay8EIwJ
tWsTr3QdI+V2cohSSkwr2Uhs64PQGu0VtDGwOOJcw93wnduTyWwjbu4f/aDNExA+tin/phyDVRWN
jO6dKdO1xi43feRK/vSsVm0LDJbDD1bIhU2j3wxS79oq5ARW8NAC1cmw2dz9GwKmwUju8Vw4qL4A
eAul+VyL4INu5UzoeoeCqug1Yq7J1nexEpYCpH94roXfRmA9ACg43JeCkhr0smHRAWdZwLGq5IzM
Xmt4bX7M0G6PpUo4sOOs6o1nvFRkmiKBce5qquKUolKZNKYeM/UmSNrhrX0bwjVJImhpJpGxdtSu
/qDXR6EZnNiNZxtElwLEt5meidtHwRuHcoI5zXDAzllJ+Fnyr006Ug+DH6auu3ng5DG0MLiko64P
OqJ/dSJmAb42doxbdChls11mdwxDwFD0L5NPAViMdG8LqdZd9cByimbIGdHkTNBCa7sunGkj6JV2
2YkfC/CcpKMVzFFofPLJDdeSNQA/e2DhlO062gP68TMjWJxFGWB/yk8VMDuURF0z56hWLu5F1h0n
cjiF5KkzTpwitDbwhKNkUjYF3g+/snvSh2LdCd47e3i/GHjnc/6DYnXYD2TKGJE7deR9BTcMKRK2
h0hPftPMav6qCmyPhqbkWVdfB04sUzCIn/CY8t+u+G0+ks+0BZ/F9XUi1LOJ64HeXO0L9pfpp9ZO
xF8Na2GChwa9BxnTOPT7oWqf46KL/J13hvd5LGHKFNcHbwo0ccFzakeStCvncqLHKQtBqBPkfPf2
gHwPfEo7d3nr6TzHKnRE7bLmUA2fs0zLVtoaa99BTjsU0pgqAwi2hi+eBxFDmMsOjJG3XNryqKcb
k0UgdrR98a4hy0O2g3mNJ7o4osXyMHftXLnMSkwwHBNVYyXMxpKfJ3fz6Opl00pzp2LeQrl27y/X
qG8XLjg6OfgxxX/nb2UUSl5HYIX47GtuScXGX6rxn+LB3c6aT1uTI8W6WubnGrhkpD01Q/KDWE6k
2DtYUBpFVyLKdnNLf6Q/zGY7+6p2P3uybY8NmewIJJ5W8Pp8QhJigwpfMzlcezheM3k8Jp83irtC
ea3qsSyebGPnOU1rv/dTUypahYWw40MgwRLHZJv/JwaGz9MxnSyJylbBWJsZ8CmLA8/ovnvLs011
f2hmCdEv116sM9z3hq1l+FZDeuOTS10D3bEJ8auREVkKn1rOq7N6VPKxx9nZAhfz47Gs6JKyCWrV
vmkiztLKRjZcHprPjk7wmM5b1HP/+tNpZ/QbpNs11cXDKtExTFrREakuIcLZ4diGr+dZp1oAjPqK
AeIeUdHIScsvPr9ce+FPIT7Bc8ATKWHNBsaRijodM2TvL8p0FQJKF8D7gFLGFD2V0GpCJlpAA8yV
8KIxofaawRTV0MpDe8IHCzkL7KwZrJ5VNv8juZbhvfTDd+vfTHqYAssFTJqn7cNVGrNuxJ9W8ku6
LzUfZOOQdYw5eUpMTTbhNFZFGGL7XGzXn6yxzGSpWbAzb4mIKF0JvOgg04j6aEeHmqV4X83CPXNq
dVEg01qQcWhpYXhvvv5SKITWupf5J9OyRJOxPO1Hr3GIbtZxRdwdUjT0MPU26keXLw/V4dVCJHF2
0cP9TjyGMBDMNUztMgJHZPDqhBbj1u9KPl2d4gCkUBZQuFL8W6rAkfpOfzHEQE1ot7cCDkKrg7sU
ESkDMkNSYwnkRZ9KypW9eo9iv4y16VJqBv5x2Vr6Lm/ETUe0LP4Ez6rubNStzD9kOCNPJS9m0PWV
1j7jLuwESffsY9BO1pfgvLY13yI1J1/JOjsFZwkbvUir+RmMOvR+U1g6lxmV+TxZDEC+QNP21rxd
utEdnppJX7xfIMLmGqtU2jSSkSc73DPUYRSDDfLEHPailvNKoKlYjigCGFPAi0JbhFTR+/lCv5Ir
m7usU5U2TW68QUHUSrBe5Af7rVTRUYPHQNjZmaHYDUmeowNi8+pBIs2wUyJHl5rsw5eHMUi6floD
h2V/EL8UPtmiaz0DxgTs5Ewi/iEPsniN5bmm6rdC0r8Qp6iPdBRrI3b8seD12R+RUaQhkOtMvR71
3lQs2xBs448kU+0Ab131TAiDAQud7mXIoK593CJUiaKQiksYyKGsZiONfTshV/nUNi2MZL6EOyaW
mKZf8xukc/dCzUEfXnmkN11PyKgYQZ6xzwD7cFyK+ku011XOC9ZGO13dkiTR5mkC+jPH5OUqA5ZX
NlXv7pMAkUmAkeZW1tGYM+j1e6SNmS8eXiSRX8IWiXwc7Q79xBD9Opk6Id9j9wcVDEJSqeEuyHdJ
Px2CSWETElD45xCpRD5yFzyV/vKDCMe0zvk3MzsG0/XpfgHC3LF5gJMUa/FhspY3lNCeDwDxm4W+
uAYmWpJEyQ32VFKtIcyx7CQd2u60qUMBP6GmOSNlJtxM4XY6/Pqh5tZjC447MsAhNswl7bT+7Qf2
jrSI1zQmW3y2S3WoNrD9zEjNVuymlp2rJhC4OIELBzjJ3itkAM4ZQPD4ev24h7w7xVtZHTcQ4sFT
LCSUdHpghVVixcJaL7vAkk4zalM+io1PI+Zrui6tEYihOk8zv23HulEAok4LTlst4x1zROIpltj2
FFhpsYVCzhM0YbkZlyxCCH0L8KpTfsUKk1QVRNy2rgocRl/fGr651wYteufvmmTTn3T37gUJpeZP
xmOKwvownBPmif40J9e8oXlgrEWJftjLc7sjbwfgsYyenJwfVyAIn6JiJHDktn9n3ngnMu6j0Rir
uJnIszdILaKGqekMEpmEMSrvzEj3nyDlrz8YcY8hZZjaM1wT8Aa5W0WuPfUrL54KZ+UbDorvq7HF
Gcz3y6CdhKM/O68lp4oewxJPo2DJ7iTduE2Xo00piHkW8ZyVYw6H9F9o41LYYMDMnfd6U7133rk/
Urz1UJ/GJ4iTe9xCuAn5ydU766WS0PG15tXCSPNd4QIWH1+YxiQlQEZ2fHzR7xWlttRS0zDXrKkb
JJiY4otrQz+hu0AGuSBt2aN99tYjl1kNNzWcIaSJtoZfIQVy17zLazp8XiUfw5kJi1KuNW6GO7XD
CZYLt3tUgVLHdE2kuzTdglkWib2r94w4xTQH/dJKVP81JIzPPuCiFeIEMKW/cECqa7anNsNKdeLT
4X3MwN6IWTHHULwJPHnKOkknWGyfKvzs/VLr4XL29HebuOWtFtJXtrXOjSqHYczX43WBAZoHCqXj
GTUerbN8FVjU3kCB2xCw1LxDuSPszad6zbYfBc6rAnWRBjqFtCKS9aMsYNbwl+VH7Fm4BrHHXNxL
JGkgcZxreWCWWzhhZ2R+3hxhp0zkI0j3oeUsE24QxUqPHm5p/y+4YhwHkPUllSOv2b3NCeuPcxGX
nsxrVd0PLFRRraGX60FhYs7Hb6A6sVbI9DQaQI8Pd9FaBQsjuvNApnWc/wb5HbYG4wYhawBlMG8G
2v2uVme8/sR7sTxxlkON9qr5y0bVBEtDxqzvRBYVI7Z0i7rMs87zn7JbbyoYZkjunTjeK9ssPW4A
u67y36tNN7tmgi0/QNA2k2T2s2gkz+jmidERxSUuXrPNjWfsUdarezuwE8pTFQyPaYDzRoalb8kq
pGhA9kEQSOAFg+Us6YUwGB/H887Pb4k58QqSdEUYiPpOTHCjhOXS7nUKhJgakceCEpeaUoPxmoQJ
m3wMpZZHcn7ed/+5fgl4sP+F62JU/N0WXlXea+YdJg3YLvveLOW/96FKSXzdNTl27UwWKrZTyvtI
AFFWZafOe9YXi/VEJkLDiGVwc05yjDg9jb4dvU+5BqxfVzXk8G+nm3k1UpjEb2hJ6PP1zfnD9k/S
1V4IE4ebjMPT7dzWfy7bPIgKn1dr3ZfYvOKx+2CCYzwGG5OW6n06oQwdaqPX3pKF3G7U3dhon0Yd
VLrYX/oHMtSV0RNjzYSgSa+n9BVUrlCtKPQuZauqV1ynedbwMNF6Srbj2aG+rVQG5+8qqvhVf+ND
L1/DjAhuVTAZ0HuIHWwnbaDWv4DegVGYy6klZu5vaGORXGwrZ7iysgyHxlXrk0Efy+thibRvPl7x
Utwp9XfY3zRM2rVhHurAWbpe+js+iAXmfz542yKmV8KMEwyHn8B48Kzp//mkm2nT51yBo5KjjdhF
xIAx8XhglaNzt0/88AF4yO+kqqOPNHZjG4H6bX+QbmnfT5BruYdvY+ICnFqwwv2EGC36bqRUS9fC
fJrBJ6dwn/Hi1cSkqZ6ZgrlYk9udQdUGVbyp+TpWp09bMqS1UTwldCgCybeBkHkHqrX04iU3kWCI
8qEXBP69RWQGzqrGmB4neOvR3sTBZ0owU/Mv/0upeeS1/o3y7rzcM89+MvGsKc6oKfkYv9qTTIVG
qmS6MFLaXFX8cykqPVdODQSOcnOVoEDn0n+qLAMMVavkVCRbGIGyBW3Ky9cHK4a78pCzM6Ko7xIr
IW2KHOpZjBKASkmRKRJ5KJwzrn1yME1Q+ThWouTt/BLhAANIBDVVt+gLF4IcHvwb1LbrXYazsJRt
5lMoTI7eX1X22Ued8vH6Hyb/RCedsjrmadVGQ0AXfyWdAWdhkNaT7OqXLMatL2vCRKUFGhvKVwLP
0y+S3ylbFbtHtxTyLD/R917PkwSVGejqR5V60Z0A8IQTuJsqEEDj/qlNGtrRg4T0UsKtR6RWuC7o
wxpSh+EqqU/ZiHGmg7YzGRzFjRVO6hZQ8+Fn3Illz0UgK3WR36yEpV66HCs01LOwfyjPbpoHuoa+
abeuR+IZLwJKRk2hKSOxqAg+cWsbsaitKc12sjTx+5hK8zTHft6SfgNfSnlLm6fVaY6HvbZ9mYHW
4+SMuGCLQ66Hb99xUnirrumsyz95ymZ/RnF2PealTwbe8rb8E1C4lGXZP1k1FHs9fDLm6WafpSJU
/tWz0X1F2g6VyuwsXUsgsm8qZPOg7R1NhPKNQc4Y1752XQrwAgYOV79D3l8FD33WdXNrLRNt43Jx
IAECThr1dHsAlK0iinnWYwSwWDfK/K9Dw29vWGpGy8TTTO2YNlLKv/uJoXOrWN+CVu3FSErBAMgk
9660EzLI+1Qw4+6x/3e+RzzriNmCcg6aAEo3u9rkHAaCDHfpn2z8tluEtO84nhvLpqtdreaKdkym
3Ar8ciYq+7qWK7k4SOKoZHDKWrj3uMNp4npLA1xKJgYR/SccdOkkUzo9ome60MkWYu9rLFxF9A7+
+F3t7KS3eHFYljoWKG8aCUUxRueUKwpIf7QF0NsGBp38R7GgXkuad+S+RVGAZEHKfX6/1EoX87bN
Ei15nXATPFjo+vb9RcbudrWoJ3InrhbB14RpUNiRBWob3Mqp0e8enX4poDJSGSgTlxA3bp66Om4Z
N12qmzEVY9HB/yTMHQmeu5u6pp4sdkiDo9lvDbsJPF6I9g1hoy+JNdKwYRGgTAn9/ycP6B/Iec+c
0sics30qTFXEydIT8KSixWVSO5rfTZ8QggaYDZQAd918blAOmEl0L5s7PyxKiev3+N10KFQiahnO
ZC8d5gVFfoQ/bnQz2Sq2ySQGsDkEiBFtxzltV42XFId3VoJBrgYRalIUwBGiPcxWZ9TDIokIOvDN
U/kxcDW+SprgVGlO4NnyrdcluEhnsg3Chup9UooxStb/EQGNeaiqqSePygartWnEnmz772iScnYE
+V/XjhNnyyNtctZ7ktMg7Kb70UG8x2oJBJcDNiCZ4GrNxeS9m7sIaDAmlQd0ubjmOXybs+5Kmn9U
YY8SwpMS37B/Q+QlzvtNCvGoAejxABUF9rQ/sPFuAWz+DRPXCNe9Hy1Ccj2ef3IWQcWHHklDrjEa
7XcpVT5owDnGK2LCgkDAx2/ZsQdVYCV5Waq2codnUTzBr2/B6RaI9nA6dOuKCBo+H0oq88MJf1+x
hEGMVuu3JXHWpclYK1hD5Nkx2GmEVIXYzI3I7uoFCnmiiAl0YrWfQfuJXBT/FYCSQfSXNjZDHdEm
qicKsiAOV46nS1KSFZcn8ij5tJ+8ZOU8jEkmlvQy7EplCApCR2FQ51xw7xcA4hVnsMcVzwVnnoLD
v8aFMrKZpp56q1K89bO2nBt2c+8geMAhpkOY3n2gaxtPUlK+IhqOqoluimogGPH7iqeXQlqnP+Xa
zj8xZN+fmRwbLYFLJrfKTNPnoSM9fDBv5dQNrVbTb+7+CFKRB5K/wH5EhM0rmtPqmoM+tRHbf7Yd
uSJ8wxpduv6Zm23gyyugJQSOmezF9bS74EIWSVjSM09KY86jfykJ969+kkGyzdx2vdEQZrtY50+D
7z4jbwACgMGHdmkXMZwHhR/e1yIARKhSdMdz6akD2DaImIJKmuPS4vUNeSyZ2Yq7Ojj/yZFxKdD6
GF7FAjIvPogjNkVh2Iv+TJxUZieYP/FD5pbQiRdziin1w8YSCG0X0lHmZe2SAB8XbG6E0TA7++KF
vC7mQu52KxqLLmlPop57QA6mi8Banze/7UvwVSznl1Um2MWHhLxBUYHvbzv4pHEDVZOKzKb8v8Jj
M3784kCs7fz0NEFHJhj1HMTgnbByCf95PQ586pkzD9Z+aguSspf9Zlf/637hhmyKbIU66ufqucPK
GB2R1B560dZev+6ESJe1lWHFpwUOSrseyKkunNwTZ6P5NGuFqrHZKV6BHjsDWeQLrh13ydg6TozF
cAEKGrgyIvB6MH+JipMWkd8GIo+RY4sO1ZrO+XIlxDxs9TAIpY6YhM+FG5KTqZpxY+06U9D77si4
m0USVCGKCj2LjglbGw39ysIN5nHdMRE/49WB59emfCAoMrNdAvdT8Ez4zbNoplTpd9H/s2Q841JR
RNOzp68EsOcaeFhZuXm+n/7/4yRkiaavVFc9+dIAwmuUgh4SDQVJ0/eevvBoUgBe4TaFtaxm3ISB
A+x5yLVjyCs+vpixcghbry6+qYM/wegvrFFr7UAaOs1lNv3qzkwkBo2VUhrIR/KZYPiAQyqPwJtQ
llspse4THXno84Pj9N0QqfAZq9KRbjUT6ixNCra0bccrqx2suKwnyy/dqjLDBNCjbo80y0kWB+0d
jre5zmdoFI7tne4tvLCigPsNAIljF+ounRcY5mnvULQXdn/Xp5wK5/Oug+oVUyGmIopvQ2C2Kyrl
m8tCOfV9OHXFPRjsrD9TvYpK35SazGGYDVgAHarOHo9LFd16r28mHrrKdIeYUQ7fpWvfBv8Y9yUY
8j3FHr9N99kxyYPlg8jiBzxAHXNXfbq5V7OtnmySj7PVk3rj1c7dd8zYIq+WCAI3q1sk8CAP3xKf
e0fPagZiwlsXpKRLgMAB+TFN4h1/mOWeO1cvaBsAycAt1knaq4dqrR4GCHt4BpTjtO4Nqm+hI2pq
buNuAxPi1Z+zOVfezjpPnaeUJPFDNI1ts+yN2/nQqubWjGJGwUQ/rpGlGZ8+K0WEpZ2aUfbWTZqF
AvKJtdd04m8Iv5KNUE/9PThVnM1wuaT9ZMO5+PqkrXs4YGGuw5xW5AoViilm9hrOQ0+A7TDIkLQt
R/5Rabv07alHgyC94RTnqTGArN+hrm2IqJWcZAcqOv/71i+sK/p1dsgcpI4/8UA5WEjFnvJBq3YP
rHZt1f0Wc+XGbUwEjKUykMn+0NogntG22ksmJ2W551E96u8X1PU/Op95cO7JC89AwOUOux6fNEJl
drRw9wJVuz96sa05iCD9F0yzVV1FjjEz+MgjtR0/WIpg+VPgWVuxUMtrtwyiZih0NDBWuaWrFJPh
EUnpnAX+Vp4mSS70WWkQs0f1giI2t66JtFEfM7UxSdRKLcliwfjNtbD97fRDwpwoPvinb/0tVy2c
MFjiGIEYqiKkxOnOkAjZxQBrWXrGRZ8VUwYTEnOagufc9UcUyxq5ICkUBbCJdhVTzJeFfryZIpw2
xs7gsSmPIgL0yy3A9CI3Ne/UtWnyo2A3Dr40R3uuNEeNwq6DSDhCvWZpB5XHWH1ub6hwt7qfVKRv
rWAnwvVBfjNj3563AyefzuDxUjVZ0/DlsskPSgAzph1Hdb7WbcPLoHp50MXBxhQzHNCmmyDB3DGG
duPDISoE5vUXNOLE1NYLhB9XRI71EEjL8jORI6iovKaLHHRmLj0bGpNpG86yFPYkaQuAwb068dOY
qq6TwYKJlalszNRLQq337L69iShTc2ubQtOV0XYYGReXg/vABJe/FqpAxNn4asYRk4c8rfFHK36f
ns2iq7jkqI47s6tpdy/6JHdVjVfLYooUUHhOHHek5coS1rw0nd+XJgyVVyh5DflOT18jzoYsm2CH
3U7n0HCKBte8nMGKyQIEjJHlHBAlxSjzCawgQybDv7/Vv2IxXkyM6wv0wD8LfzrpNv2GfL95m75V
ev4y2RVR3HmN0lL7SOjA1sDEgFnH/g4U9WhSKaxP4gNzdotxAC/3pxXl+80D68EAIq+Xhwg7B+UM
si7Ko7M/AcTltyUi39IrlQ8002dwKsiFuWiXGhCRXBmK+DDkqiSrMvzwI6lxq/CPa9mDyYwExMIl
M10ip5N1gBXhOWKRLDLbaDjg+CAfYqHjB60jFZHDEmRBiDV9ZtTS/FSYg5RRcAK2+5gwhO9j7xv4
gLr4OB5dUWcJQBlHWh2mgBYfAN8CLdGUwYw+XszsiAvhWpkH5dWohMxmcID+gMKloZS3ClHOA3G9
+ARmJofUsG3Nqgf4uv3QXJ17pkRoBp64i8k6K4Q5qKskefnnniK1DpGNAD1qkHBbOB3AG8q+/7UC
dkV0oTEl1Id7NUzwz1ZXMG3acYY3IX90GBXhXnoJgRnb4t4Y/+AMnRssocAHjZ9vLVEy3PV9d8Ks
jOTnMWb5I4iIGgwImZ/4e7713k2twh2eD0tR2d4NE1TFs6XPHlPhB6hWvKlTFHhrWIWYCm9bhB81
dv8m7GyB62lmNw7NLC/o9MDrRUcSO7oa4uwtDjJQ5Eo1iqJdUDgRpQkI2CG94k5JaV9fhV4n0c1l
rZTlWBcc+AEioXX/GeMJteLbAU/Rj3iHSzJjTa5VoPxDhbTQFmfNFT3Ms40ws2KdZEYAz7LKkdO7
g18UA17Zy+vUikcV1cTk/S1tyrc5mjE81t/bKbzVGjFmQL6y4C9qfO2N9zqgbRB16l21o544PDk5
rltstS4E6btI7loRcLZBYgKFumOlMzZElZqYQyryVR9skB9xG0t8zeovQVrJIb/zsWgYqFDyU5hs
BETxrcJewgSZECWkYLahFr8Sq0YznsdzwxuecPsaeE/myASqxEGTX5gHOOFLPYMhc/g8LxaEXeBk
jQMRJvsO91W5JggC4j00DzFxTWXoW7uccjse9Y9ZlOfproISL6n5XDZ2VnZ69082NN6o6PPk35ru
UWaM78Brr85zwI18HG98AzNf7S9Ubhi4rbIVhJ2XjdKN+mMbdFEvhvI2vFpKLTm04tdPVAeEPYln
zEStjNi/U1uvUED3FBXqIWv60hABdUEHSkpL/bh2Tz5G/lZx0X3HHsXQOMqj6qTottkWLoCIaLjw
BsLctqpuROGvFBwXvX/ddm0YIAim5MUMW5S9EajsgTB9dNBeDFSpyZUEmdFl0v/naoYe+mVRS2Xu
6nM8FwTmAWxq1Am3ZdbzM8SZvJxprk/XUR5GFeX/BnbJBo0VxzzUeMuT9PqZEM2OpxNSxM50pSg2
NCM1S3WU7MgGBlIk7bPJEEPVJct1B0EGA6fKkB7las0J2Y+DaXZ1HN6vQqLBSLrNjKXozJ4SHCUL
A39a11W4QgPkLGp97QrmkK7+LRh5MS1S5o9pJaDdD1AZaNPcYPDOnQaeCcL1pZQ6Cc8tFu5JLFlQ
D0piy9jSdixf42HycjrzeZmOIJ7+yZkfJdbr4jt8tT5MVIhkuQURV2qxbPAMJCvRv4OYac9SGcBB
bCfMXevBEizOLMdUu4peQYWOgOyn/RUH9ZSdzOvkTH3Uj3/AqSx63thNPuKVdtiHnET75qNIIQPu
lGdGi4fCh1P9aLMn3yoraufWaC339bvgNxfiST7lozM7KA+wMlm0vyxbnXc+Gu7D1Jm9zixG9NrZ
4BLZSA+m4P+suGPR8vQxZLOWs8JetF4RJIxtH9XbliqPgOeen0z0dwCfAw6ZWoz6D7FOUZOsbT5t
1oMHsv/F1Pt0B61QshXV9sr7vKYGskDViMmhrDVsGWMNCwTJ0v0E28DYth9+16X5SXSaNdtQnF/4
SZoQgRg7mfjYuc//j/CZs2UHGrTgz9KJ7VJoCvQLkuVLN+FXpl/2iRmMdiJHjIeeOiGUif+d7DH6
4mHxHlhE5KJXa07glPetjqjUfUxQz+cVwTI3Z+G9oH4X22SnNjRosXVg+M+b3zohnarZLK1qa0dP
gsUGQlS997kHaQscvTJgjAlrhNM92AA6c61QD3gqwfTang0RBEQ1aDiMJbxalWOT25uKzN4oF6hG
i17Ju5CrP543/qKsEQV/a1PYaKK6REOafua3uajZJDyQvkoyzGj5jtAWOpVdndjAKGBGClxMR0ML
WgT9oNKAMSfZym5tjvAYE0eU1WfpuQBTpufNHfT0erxydhWeZ/xaPQx1diFiYvUxlSAe4FLsrxnm
cz+KemcSrqGcOCEjL8akD4fXEyObLyd6F7SYGUlS58IvrvehCHMnLK5rYGDQVUF5zAeESoh2pdKr
7cF+jqnPZdWn2qkLeyomNKwFeO9e1gilJSuTFm/0OxXeZlVEl+APA1rFc/zSJIlO9hwrkrAVhTJ/
KhXnDp1C9fh07kFkrVKTM0rrLgVNJZ2Vr0eq3R3FakOL436IuxIWJRCBboNuW4Nsrp8lr0DxjvIn
jNzdWZDE/0E1OCOaR7tfRUmd6e0SKmqdoO9tmyrC+Jdx0UNT8mZBjQX7XAdMzcLMa5R23ksy4nW9
rMTbGmHk6NAPsPsc317PBgnccLl4ivW11zRm/KYJCgAZaejWv+eIdPOrUQ0X/awWk+OFGofNmbai
AC0kKiBQel4cURNRTNThRjuoEwcZJ/sV5yOD0xYoXmjPWMHG59lrXmZmJsf/9DiX58ULCi1KVX6w
ojf5rlvIQxiRygpzt0hq+E8OTKsy/JO/leqdnuR8H04Op/otMLV6RoykNciF/zaU183/Fd78zJzL
F8o16c+0Mo4QUbM/5HueOh2cZqVq8nrZRrxz4K92Q9r9UN9ZnPiiC1+Sw33bBG6E0igGcp9Cmi1C
oNCNAHHhgQlAI9g4GPm4lnOUGfrts/7gSpvuHwhaQv16m7PdxUby1Gh1Eqrcopho99VCDUAToDW4
rlDTU2RMiU62RI2gDfI6cpJeUUnwKVsRK3hXaG0tHpLPtoz0U2MdlunDG23EV4Saal2ybG/N8Wf9
tXvswk7qmTE5S2tIZAGB8pEKhdpP/o+cwC+j4EYWRqNfmMBU+jGqgCvT+NU1T2bfoPRsTvSn1Udd
EZRjLYQ3N+h4i2IRpx5KHwawzsRiplhItnNkktpxRv0NArvMp8Sh1Qv4H0Qor7XTrtWSmty++u/k
d0NF/5IDnH+LlWRhdyUPVq3W0TgtAadNQgL6ZKQ9yPlFslJJ2vxZvDBLdgWC77ODM2U3ZmOaqU2C
SiCMRvOJYxYcmD9V5BuErX28DNYw7JqBUfXAqNASQNkmK4E6JKIwP78TuieQWur6VRbma3aTO+c6
seXVIIi04aheDznIsD4CKn4tluIGZ9ziXGoDmV24sNwLjfmaX9yEmkZdMDjJxFXbt29suRHEH6nY
Y4IeDUl1l5tXR89rWrchxfKEt/rsLog/XG02FqlkwEASCBUGjXdEcmliJm9TpVpbJUP+HND+Hefx
DtBkCcmGi+UqAPD462mR/iDCBZZeEDQ0LfUQ2hgS5DgdtoAeoezpLVuPgM+w1GmN7iKbcAMK+ApL
PbD0TJG0Ou73y10B0ZpmpVzZmnxypkCS+3g3k53wGQjkmLumgQ6FFszrnawHEF37kNCYexdtwHSI
S68ACTGmUiDo376ldnMbBtEVtp6v8LGgATJaF5OiDT3z2gF9i3OLIxdFLH5mR0O0g4XNIe0BOI6b
S58WlLdav+twgH7ZQ/rt0PPwMmxM+EC0EogTxlgAMvXVnamNKie1TK246+wN5arNHn70Gm/DrMfZ
lXk6eTXFZ4pEiqPTDfiengMsmcWcVipGkPxAf3qB3UTnrSgV3r4n2D6Nk4iHmJ9snauzb75UU1JF
a/hh2f7CB4aQSgkpG7DqLmYbkLD4brnQ8X+Y5DgRM0mcZ1+fs5rR1F8r4E7SeEDvX2z9wUWFVpQ4
FwAmBRF/h85njhb/jfywnV+DxmLPOg95Hwt/rrNs0bExXuLNAV2+qp2bHL+I+dc0ROvTkMwMsgnj
2Echu1QN9GWj8BHcVWYym1QHnuI+iLDIR7BejDfFH8mhATqpb1oV0O/TSQ85GQqIafp1pEcBfBOz
Qq0GimzxvzsxPikQFqNypX56BjS5l6InkD1kADs0C8Tb+91ry1e60cqCa4zsHUmy+6VhkFbE/HNj
MLwOFh+jNJVelp0CM+TxJTURDSXBiWkxkhLTpa8u8kSJOAqe5kT6SLQF64sLB6nUyGePGj3vz3wx
T/csLiumXEjsNDWAsIxnl4wGZAkhOtC1gwG2lPgS6qh/vOfppeZw9HS0uJrR1q31Zgee18ekomxo
jczXHIMKohWdpJ6HIGxbpkIDropMwfvQMQYTxQfpwCgN259/DVSaK4VIMhd3wTZsPmizT1LfWiWg
L/Ju4WjYAF+nMZdv9ucnN6+yKw0k5e2WlYncqjlfMsS5B82YYZRS043XVUTmLXYPor18Fz9vGgxc
1iQ/gd1XmxMmEHZOWXMP4s9DXnTw1VHLcdT1jH4b5nc9yhGmePnZjghiqnvKmHsbf9RX9uBKJwYv
QPNCUlr72bzSq+zjkn5zS2m9BxdCLVCrnI9vRowum0Y4PsPQE/xNShliqpd0lBl/PGR4M/FSpp7Q
GCe56cEE6pgDWef8ouw6w+5qtGA01zF0pQ2UbFEo6es7Ah+hTZtNHpXh3dQpaeI1N6Hz2B6PoiSz
SVvfY0x6q4BbXAMgmoIr+akY4MnXRMKGbM5U4kh7LEJ+lx1S5Kt/ie49TmvcF3oniRGEP77WQyiQ
AezWCUS+JiP18JmTjXjXHlSfoZCJXfZ8zVCOlrmEMTnCreL0rriGEu3UC611vU/UhZtz4mxdDuh8
q21pK6EdfO5EN4Gc+2MWxF03r0eBgshCxDL1LbJKKf2ovb5bGIFPqIn8gvxVbLTKg4npBiBcUP72
GInpWSHBv/nffh7eDRbeAM9NSrt42vCnQJJo4SQmb5K+q3FMUMYIs00hpoE4hNJqbKhTMM1RNydi
a95ABb6WRfDgcSylr2VkbwAVnGp0EYojJmyYMlWujx5vwU1mR2VDMavw/FwQJ61JLBVLd+CqEJsI
iNCPik2HUMPtibxwU6i3qJ2bNijfM5b0903xNenozgC3bpph9fBXmT7WMSzMsQGQ517Y8FJ/8E9w
tCoztM2DWA9Bq/bB4g6a8jSdRxRvqEx5C5CXR8Jm73YoInWRgzgj0HbxPCJa+UCL/p3/c9ydodbo
BrGGbGC+Ce6mLx86svXuaAQWIQgy/yL+yTuW/RgbfFlBdXAtaSB3zArlHOtKWKI89sCfFDSp0XEM
KWZewnmiwcMkS60QdYMyAx19PxSFEmAvqU2NGoSqr/OLPXdhWwT3lGPp1njIXjcBjv1YGEnsPDJJ
xusAxEgytLPitR8SrlzQ4Ruuck75F5PyXG8C/VvCqi04J3ANfTIei4FoIMllSofynT1s3HLipUu1
ec9GykWpTQeevVgePshuuQMc1IKf/6s0PIG/Hf4wLWk28jtt91HZnRy9lWmWkwGpsBW9teA9SZSL
/qRBgUy79i774e65KT+3Ydk2cDlIeQLYDQHxY2TpR6IYEapexuk8iAWJCBf0tmGyzB2A2rCFe1x5
9mE5jil7AuVf8PQBxKtPY04iL9+ehOwRoROa34hmQsImw/sUQ4wUp6RNUKwEwu4PHl//LlTV5QXn
5iHBI+u4QTfD79lU+dcKbABRfUnaJFYfwCtptLXo5z3PKuXZ/yTLNl4M+iU5zLF5pv+iJ3sKuICc
8tcGbx3DI+JDhN4kS5YeU11/a2Z+KOnGPM61FWVIFgyomP+YhJUKlEw9ws+eLKFIlpwqRoF+7C+f
UB1MnfHsqp8cwFVWVxJeTJUiN3XfdYnfMfcYhv3d26hZT0B5K9LNW6zLRqB7eXv5phnUJoBmPi3t
U+BoIFQpxy88Dq+U6vrYrZ9UJFXb0FLpWTwcPpERiY8NjJoNtm5XWet7H1pA7hhHgyK16Pg3G98d
5welaIercpO+zoTK41upz+oZj1B48QZ0hUUIlUJwva1ghDEeAo+KpikRuDOCWxzGyZ0EcA79SKdP
CysTxbhCfTzQvg3wBRpV4v8KyzFLr24jjBMvszpZ2Ay10KnWiFCay5HVIUTe0+FJKVvnICtPHu+v
9oSkaBhXcrfnIWuejVCE4H8LhwEBRv7GrurbxHWE4+5e4o5psP6dN99B3ShzHkkO7bo4V3M550dP
zTMy8FI/ghzYpB98t2bO7qagftn9Su7oDpw9MJWd3pxMx2lI0eSa1m3iNAP5m0aFd3fMzXRYzo93
keOERwcI/XfYDrB1ZVJP4jsRCD/XYuLSWsFenvgPK/I0DWkcMfH/QsygV28nQuRhmD3U+qfT96BH
2onoxZItjWfOhGnJIF5YkV0ZSqr6K2ibkj6XMCP8sh+tyTfPvXr9Q33iYOvODwV60dKq9oojk4uR
ryVNXroUTQ5CojslWRsaNx9T7c7kcvJOO4fekHCc/kXhXW7U2aEi2tiV1xQnrWgy9sym/2RN4cLv
VhIJD3uQTqqT6KBFyOEUfQFEtVj2WLE++uyTPevLu8/Vi8CJGa+OSOfXVablVE15cN3vcdc94BPt
4UYGcqvj3pUeegc33k/pyJKiX2mMa62L8TbRTdbirlZWJRvci/8d0+wvesZzlnGjILDsJtcyOkqr
KcKDbkxiaCKwlsCXXdRl/xH+xtYEJuD8iW4kuM0zDyl8qR6KNZrvxBivbzXrBXDiqtSBFeA/aBWV
AX1YPYIKMHFrxZ0IGm5RLQUMMSECZBKrPQd7sMSeGQdSoG2N+PeFWWtf45EPMwWK1woHM0FpDY6p
Afsh/XF+OTVT7VGPLi3xfJ5IYhr0++LCHPmzooSK66MiUCidogr8QUtFM36o7bMzscz2gksrAd4i
Zqnd8XbDzGKC+J0IZeN+o7FJ6uEmTzKsQ7wLutH2YIrdn418WBJosvXuD+jdbf28obx1+7PdHGTu
jg+EgRkPDRf432UtCQFap7ztSHeaTyfGhZO11SYzkFtsphsgdL4QtCV4suHWvAfr+HQX9eqeWnQ/
b40AsboDQKqnkcGKfwDGHNlmO3b6fqgTp4XFCKYJpfFL8JjpMynyvmGlNEaYTggnp5i9RmEsWw67
exDQe/oUu01DIEAk2yCnz/HRKjD9g0qsPsdYq/eawtXsyCyM+n1jF1sVRxFy4ch/LLKYVkQoK3MH
QKmi/RO1gLhlu9g9NKZmjILWUtcS/jcZ1a3QWzkLwVR7kXSjRJllCqLSW9jtHPEhXzYnjAQAHIi0
Go+s62BZ7sMvOzrHPzABxwPwGcLhkUwd07FePdTkqhPt8zNGIR2B0BTq/Gwe0qxhMgw5yAKxI2oh
T/sKqlbUq6KAHI1sgXbEeP20+12cvBNb+wLx6DGtK4bE7F9ohQqxgTmGVcx+a7d+wP4geGuP+Nox
OpHqCsbeNtzKdt8hcEIxZOI9GIDPatV627dqQcrXl0iGDfOuGC4ZWFYEcDKtGnccghRQzy/5XAzU
1AiSpiuJk0PODeEKfrprVyxjf4P5mqzLeLJp/cH3ardzIDyzSVGcsUX/vlymfsvoxuC0QLAKbr6j
/kMO5SkQLYONweoXArXnsaN3KTWSBCimG93zoi9u263N4sMQNZHvSo47vixd1gBdZpbY9GFRy0jI
25jhSwAjrFrrR1auSWJ1Oe6c2aESEVwFgaC8AHf0TuNBrYIPwXhq49kptdcje0DvJqxEdO3ygZlr
g2wrob48eu9qJKFaIoKQm8RPuBnNYrR76xUDrg0JbEwryTWjlXwXjM2v2iVYsZBGOkIa16gxL6Tt
A+zfdSOTXwh//GASU9eIGlYKScwDasa/oIXLeEgRusQ9AYUU1MVN6Uy8gsT/2z91RzYtmVtIaRyc
MfKWmw2ZCUyGzFqs2Rjqc8JPzhQU4D5MgbXUxnB/5Cd+WK5XpoPwULgU50eEpNtCB8FriXJoWQme
jBBSBZHvzl/pBtW4TLF6Pwg9WaDA7j+RApfuZNvP/lRNK42TomMKTfg4/NY3fE9IjmnOzI8uONzv
K1YR6V0TaDqxG0eBfAtnx/CO6cqFQfCINWh1fGXqTsTCkH73ONYaGp/I0Dz+FIN0kWcpIIkvkYOO
/JKm/mxE8cOPahMMLthNQOK2YRmGIZDfAp3i40wOytqj/wqFK0Q5HG3LF/RR67dB5gwL09Ag3zpE
LX/iqhjPOAoTQArfjBhfjGbr2TZqL7/WRc7awP0SgLmU4ScIzxqdGiJTXdEjsV3w79s8M0NVYkid
3KeyRbQcBs5kw4ObrPAoQuKLkc1ej1IyDH2RlH9746O6lyyfTN6srzkXb9vWHI43F0kaHJ6nz2cD
Iy0xMJ58FJ39sBVdJCen3S4FrV1CfO18xriDJ2eShe1vyzIaxw3N1VFtP9mBGS46TS0Oy8kK4SAZ
m4Ucg7wkMbDAkn1FjLvDL3K9vjOgJpEDGPyzx6cysf1oNyyg/niQ1/dSshmiLIkE4bEHKskm+/JD
NIaIsw9Q23gNqmd/1wgOkPWuALZZa1fVsWT3sI+5LYq1FLiAMMu4/LfUjc+GH0RfTnzMjr4ICmZu
PTtE3Eq67F3r4lazGoq1jvYAvRCOYDGmwxRrZ2T8GE/qWyD54gLp/nxhQjbaik4c6bXPiAecz3Yq
Za8MzmFIPAe5lm67U+V1SMAD4kn/CX6fgybMG3Vl0WBm7KNmvjMRTYWUWljquJc+8aqg/i+VN3GZ
+IQCtkX9y1tIuY8FHzI6Q2w2rC9NcitL0VOUuE2PkVicWesZ21SugQGVweNW9cv5gx8sKBezRoO6
flxNYMv0UN83wCZxqpX/GiZ+TlYfDsGbYpsch/AQhNpCJYnNZKVIr4lO60LfN+173doVnUndDOPg
OEMiSFOyl2ksF7kAz8omrZDaJ/+pYFZkVHO/2uuMddjB9qQRBkEDtBW1RQzDcUPWhKCMKp2cQJcZ
mY7iUzthrGRAcfutYoOQOMA6lIvbtbH1pz/6yKKsmaz/j5DedNOmcsZCRQEcjgq0I5EdYcRolcKb
ZEGt7B9LvHcuHVswi1EeqNfxjh5dDum03sP24skqQp2O4xdfqtVyOBvyRjYPpt/10EKGdXB75y7R
kiCDJ2SWfJNIKUWlvbN6FLu6QWq72zoFpzbAlZ7mlt5U+lhgPExyKn0KdVjT/uI2hzYYP6dViZp4
o8szEmY3TJoqjj0r5vY/VxricxPsgTGp/nWIQDxM7LRC25SqUMwh5xn0UESZXcW3OAgr3xvTQX+c
5fJttju6txEapFkkzeOTgF2wbL6HoRTnpiSa+IFbjGuSrn3uQndWrX+xZF/hhDefILNlvWPP3e1N
X0ZKZKXLlDwoQWmt1WUS3dnlapGFW6/tz1VHWVnRosjZHGi2bYfCe2jE9CpVCuqtNyqaRqnFn2GB
zyc8JFv7Dk6MpGAQW5W/MH3b1V28+VxbK+CXmD5HzgA7A2bZuuOHEIePmUVLCAR9SpeXoxUYwZyk
BWKjE5KC2QV2eaOjJbdLAJPjcBdnp94eP3Fxy7dAap2gOyQblmT/h4FE/9NFEaamBe1Q0ur2gF7S
OIeo769AJPRNPbFzt2ACkKmtA0L8BtsCqt5xA3gKYggF3TwK5i2/Px3/qT+w4s0SG9leJyJSIDnV
8xNMWjns0k6OEXzSSdql3hCuOQd3rCgbCKv70BrN1044VyboYtdW28dtAldk08XKNLSeL44XzAs2
7zp+KvZ2VrGE987MjuM47xzt7YZOr9xYzmSqKJ8/5giNh2Cg+M+VudRE49/4WPxbP4gBhEsNjNzo
Upa4h5U9VIPbfJNM6FYlkpV+3K4UMcqjOuExbrAHc4+BLK7nky9INFQ4AY+f5K30JCpEe37MYsDP
p7UMML+usoOFZYBME5b7+lY8Ii2iXTlTBK7n34BJbPKyZ1P4DFe5uT0W/aRxv4Wy4vUniEtqRDGc
uRs4bewPBNQIg313C4+R9R6P0uwG7Yvqc41nSqAL8YV4JorgZNGof9mJLBrDVuB4XFzl0phwtN3Q
tUWHCVWp7k76EM1ARTL4ib61hrT41x36Y4uRgkTt6dXvhwD15sxeE+ZLnz3ZPQyZuVHWtHS99UwM
CoQbe5vuLzPd6dRteL9nypQY8LSkFd8Smj4TKT/xjjgzg5VdqH+EFg6+YwCEuXT7Lvwto6cAKaO8
8+54Hrx01rBpS1h5QJ7jhMuyL+ltsyuQ2O4KTS3ZxeOaA6zMAz9t5oc19piYlIVInU5PC7Yp9Mh5
LvhZsaUwJkv1PlvEfK8spbocU+VCt6a89SzNC7qcHCa3fWp3txDd3stGheXYa8w32WU5RhaeJvj4
VrvguXW2hoKz8XGeLhtP/kBJZHMta3lTuR8/lx4pCorGNkuaaRA81IZ1jJua8ulVjafRyZAjXVMU
QvSRboe5qjNJOegBngPofBAogazzL62VdIxdaFhP3qMi44a40J8WLHEiqZWuBz0E1nu8ACaTJrxI
Dehn424fJ2H/4zD6ER1lyc7twCUVapH5Sic9MztbeaoTrjXt5fVinRW7FVmrZ3IdW09QBJaoJCnO
S4URjDuVblflBKgP6xaCpiHR6IayEtoAXijlr9bvxxPlYagkTdfh5psBI9E1fsDSGI0Jn0uo0rrG
8KAli9mUKGDv/OENz4D/riSetLAgFR9rLY6eIhTRSXE38B42ljJkeV3198IPvHPBNfv2G1XXD8/2
F9VAcLl+u8tG+B5NwEvCBTaDZ2mG9xfrng9INClENwEKg/Mg0O/RuS7Gd7WdL459TiCnTMZj1mJN
Ctdq8uIRu8GOlcc597Kx23tsmftKkydM3BVq4YPcZcQL8U3tZzHeoIID5DMyR1GNhcTNa1R4ZriB
6qx9WcxAiAPwotnb6mOuaM/EU5EOnYY+QhUnecnRvOG5Nleo8rMhD/VNG2JB3Dnnp/lkdXdanewn
0fTEgTlbeiWA8C7n+wvYjCmqT8fAR6oausk3UfI+Dd7/0/RmFeDcJAnCW1Xl/p6W0Hhaw6zSM0Ud
3mtTz0Las/m9bdbjKfRXM5vjxaYcT1dZfzRBYW9rZOUBYwoRfyJdfalLOXNWriQ6dz54yme99Fkd
mUNvsNTh7pec+mPW6Kjr2D7pCx+3/R72d6cVlqA2LvbH3GtQU/DWWkXgIeq2b7oT+NWWNZYdha3Z
M/92wOkVUKDlWEnJj4qPwqsobsBZvkQksRmNVUy64Vwf1I8f0JfgS3HsiLNQHsNJUHvI8xkn1McU
ZtNHZvI7qbXa1jm1U1o1Dq7in5GZy5rW5TjRYRZco7pIvlES02/3Xo/am9blmTJJJ8YGv8jHub6n
aQIGHOLNRm5VfcXqVBusr+l4U3IGr9MHMmqV7Xuo0UuA/EzVOVjBa0XMNlzyyhcx9p/HaiJEbcVY
2eYkWIXOj60JPb3Jq69aQUMa1Zn80RzCGCQ0MkMcGddLueiLuMwqyjFQodYOLI8H7hw10OV9VB1a
5mjqeGW/fuqGTo6vCTNkS8upSLaqA66iQR8x6Qax8RRfVgeJKnJefl55Odn6jgR6l2puUySx4dnK
1PRIySWLnVqtC6/gI9TGutg3lnYUS0ezV/+w9K/8mFo+8Hn6KHRkIQRAb0GMU6pWQ5c6noOcrugl
8nhMv0o9XCnl/6Cmxk4EdcZ5898qXQRJMMv294GgBGlgCTbs8gIUC+Z7Q7QygFpgCK/sFrg6rdop
ULvMN0wSyEEqeLYJq35Roz1n8XKNZWZ1K3CaL9j2hS29ZJ2Nxb+22oB7tLkzoTBp5RPnf3yFc9xj
CP1hwk8KRSM/inBiPje30jXHqo8ONBbQt8c9Y8NNCqe+q/nSPspdNcvdj1YpAgBDwR7Wv3tzaFv9
fnhRWynTCG/ow0MQzuso7ZJN54vHvkVnhZ+tXppPVnXwFs8Y9uP3DvKOnw01P1kKvSHxLNXzMtlq
iK+b+CM5HnFUcDmLQfOYn+Kymnu77s9MzdPU0Uyvg6IDUkYm2lY/4WBQsYEDWFDwy/hMGr2XRPUd
lilc6W+qaFRjmqRUMJFzVNFeFgLMCmjT6Y5Cy593joWVysy6HnUakhaOQaoE4jJIye/9wQbtRir/
M8XmW5wiHAbutE56aauCbG++233D3vQIbp6bVNGaKBypwGCv63fQdusofovDoopUAVkGu79p07vg
uod0WlnKZHWD1RniKLRtETCxE3jqb+bgCFqQvFjH1mzJUu4CF7uo4dzUrXg3HFdbwlPZGPF537Rj
sZv1iFmGNbvM0QWGvzjbffSbu+/ObOzhPGRgKNNjgXaK1sRmnNg/WEJIzqPRh//YgxadN9u369Oq
GuGf6279fW993kiT06ydrswJjPtvlFG4dck5JMDwEO7jgQZpR4Vrnc/iF0c2tDLTm2lKW/cJmW9a
Gedr8CeQFzkEOyLqoMN4rue/cFLekbqBVo+P8l9pQsU110Pgb0uG3nQe/IVxNtXfC0qU/EO8qYPd
HPImpSRLjNbwdZ7zy6Ug8Sva3ECDPr+7Wy7gbqtUXZW2kUtM8PwCqc0vj4n3kXmYmiPuvZfnLpJM
ZtSUH7IX+iq645jOHzA4IdvTFBbgfuzzLqOLkfAx8cHVr7LL0Yhjv6jLlYcPuk2B50NTeaLcMIwm
gkw71kC62G2EjMRPV+8KGTTMgfOgjRESIhTP7ZA9WZfUETF5aL6+w72gce8dXLdISIZoKrz3wsyk
Xs9TAaCz09miAze2A60y4j9QmRbc0H2efUbBtqqg1SGmtThTIdWVEPdjUtyTQGXkAm6Dch5Kza/H
HKOoHJc5T3T2B3fjLxD5c3Cyeu9MWMOtvmXac7/TiOtyMrB8Axy8GXLOO7w+UBJSl0ETpzGYIftD
CgyTS1QL+5aL9Oo/GFjwTrW1QfWxywoe3df6YJKSxniOU7UYjHNtHNMt7krrWi6ePvw4hogbJcYm
KPWANO/fN51ozQsu60r6CxfpLcJGDy/937EVmQqvVkMkKz1fVfN5m68Ji6FPBoCJ2ybMKZU/k22a
rDZCzdFlK/q6qB4MhJpgRNBMUDF7IeM32kZ3+DDKxBqyskymupo3XnzR/MQ5KNhroCnLSl2hITjI
H10I0nORDT9Q9hxMAI/Q3C+V+7EFtHfqVqoFnxaPRrtTTaMQbqFjUId90tq4Douq+zXpRC0Z8lWW
BajDWv2gL5zpRLebGqiX/xf8V/kfXS84s2Xirnyvwwor/BdtLFhA78L6PBH1jCcqGl9jdDIhIi4x
e9LTQYUoqwUZvTeHE2h3WVNZHlvrnfQZIF6pIQB4JlqxiSwKyiuAPchz/bh120seS3y8o4ihfbIT
Gwoi30eX40dQ5+Z5RAednn36TahD5lK7G54keDHoV4+etXP+cYzx1ZrkAMFPg7hLQWdkvHW8+q3R
clEWR+W8hUgZ8a9YpArl12k6LCPf+jyAqak6FxOPzc94ZeFHKxi+cIgWSnjjvbYiPhE5jY2/FEOg
EvervGYFhDBKUMwZ6jX6iYvltuRFFdfHLpasHUn1uLKBsfjofrJS/OQk3fjQHxzJRS9tKsWZBKx8
pQyGq9gloIJRA4I1Fh2NlmHMKO26f6WEVsd4o4WKZDoUtBoPQwbXYSJlAG+TnPrF8yhwb3on1pVW
CA03qI94if+f0OU2BboxBo3bYBaTJOtlAqTx4pt4mbUJpcm6hMFO8GFT+KDgAz0cYtLTahXxpgFt
tRyg4GIdv+PGiSJiF/zIL+q89Tw8Ifxc8/cqnK2wgrz2bmtC60k1ZabRAPAW2XxVPQ6oXNWnmUnW
5ZcmsO9h6cQdJjhnQxRaBOHy6n9hmW/fGSlepaw9/Mjz+0ZaR1rfMVjedRNMuvS2cNfFtlyHjtOc
c35Lh477qSBrVufJzYZdaQaJVtoubSlKl4xwozO6AY0rNjNtFbqs+Moz8cZe/xGJ+pFu2bBAofWa
TH7bZn9YACLcmYtJ+mGR/ycF5X1h7ushyk/cOG/NwRA6eH55FngcjLganwWpfOhQ2RL+R5e7PElL
mwM025tc3nByQqsMiPxeYSK744+2cyl6MxNSf2O2tnnrmX2/Og36qYCJdYwhvicNcueTUjn7hxp3
XJ+MuzGAFnPXe+KLMcu9261NZdv9JYViXnQSF0RlUq8JahbU7m+o9kCDilc6om0QBC/LPfcBaPFK
0PWq9CGlrF43qxU7ERk3LmEzdY7u5SYdGaU8DdGbOcHezeCY0524nmqJws56QzZ9ZgUCsX/XD1EA
tsOREBkkQwg2oa6jgW0Er4AJzCvhhRLzWjZW9dFi4I9924rztrtaYL+vUhtwlAkIwkgxSxecc9JZ
jF58Nt0GSmCaZEK9Crp9Dvf527xbndUiFrpBBIcwOoGlPA7ysh59WZJY+59M6nq7JtPbXTFzEYKU
WnetFXFfDlfYUBPm2WHNvXgqYUw6SQKY8o7xYRiYj0sUWg1pqcDqRrWBZjUEVhuqsSggCc4/p61b
cQBWXvM0eku5O8fRxNshxLXwUMl4ndSo4hgvaC7xTluLg8YIj+3MMDMmMpXEZZXG/Vhdmir0d5dw
UJGlzNwyDY26CGii0ZmxTLyheVHHliBa5ESDwHNkRTcMvT8xWerfCvItGQ9YcNxwKM91X+PmIufS
3DZdbzt6SjAEPS6+td4cEsYZwkV0/UZvq45pUPRd92bGyLS2v6s6Z9BnLjSxOpYrOUsYUZCCxQcT
xvjP1J18Xk+IoA+rUNtCBQFtGEMW4VtCUjhBkH9LnKfHs4yxu5RMu2D//uCuYQ+1fY+WFnn/n2z/
cmHQRMzKhHo8PPnUC2DkOkfUCbwQX1VLAG2G6JMzqinkqhc9Gsj17ErWpUtAHstWBvTzIx5m5Ibt
6FLjfk7Wtan5bkPoPhmLTLAEBfOoAv0MlQAb1WfGEQBsIP+yXqm6FqptR5RwT5LPy/QYCffTyr/8
43MQXHmEEp9ueqoyE1sTQGkNdl8hWDx5VAIKk6P32npjh7cEXnEi71J00qxTlLvw3+ypgjUZrDVy
vb5vM8O28gM1yGu11Oj8LmpE9z5OkJ4a3iXyZjMOh2n1hkzvbQWwf+80IDV07ooIOyMSXwsKwWaz
A8o05pPA0LSsRYM0UFEj+gAh2b9mxfDnBpmO1VmiNkyh97uv2tmRa1GXRgwNOfrgfGXlnGbD7xtg
tllcaQRkmw+zerqEFD42vzGv+xA5ba6igpTfzwWjP2yJvUdurjF3cmCzTB4xqZYaNqWVfj84JYDN
tYKFucMu/DuVzPuZUNEiMVAowZVe3gYnqM0Sd3BwgMW5qeFLedfNtB2Igo6XA4DzXhVfe2sQLZk0
bGg7zouPO2PXVg2Kx6GwhMafKLdBrjVBntrI+qIyem5h2Q9BJz2R+F6kseL+3qvoUF6wZ4xogjbp
05NlES5klfVhw1B+f4yTwlOK4K+miglHHscisX36BufpJIG/aWYdMGSYknX3db42I/mFKMZSXHeh
I9S8ebdY1+ry2OqqlDwdR+R9Lz64ID5hQxu/eDn9cUcrnm4+sxFJPuK/LONlW+gaf54iz6q4ziBr
yoJNPTb5WzsZBnmQ8kE0AOwQih4poy6GTQR6oxKBJinlNvEceJjVrJLVkSCtM1mn9SVbB0At6dSD
8b2aJ9Dp2tkc9LniJFGRenul/NCtdsY/HUBOB/j5U8ti0vEAF5ms3biCbU2pCx/337M0BGfCYNLq
pL7vDaMQNHva5xZOGK/kK2YT79BsDIlYWfnrJSXYTExR5ZERCdsTfxFElLEjkyHVA37kOsNSRW9J
hXobVOXIo/AixWafT3laH5/Wcq45YmLW7ZZ7Y6H6kuPFITJlDw0fgAtrgVqwcbWtiEZYZ1+gYBwS
Sb6MWzqDNxnvf+6TM6xI2Q5sZZqTglnAJDD8nrg0myp3sRtXGAg9JFBEJEny7DvmRK3Euk3MGP4s
Sr31RACvzenb+yOBilq//h2dhmO1VV8wSpEeOqcJSZ4G+vkEX2eQViy7Tkodn4yqIbwh7n8cqUAd
4HOlUKqyBGdsRX0HyxEsKqJXbMBU04rMV15xYekZX8qs9ExfvaQOnIAhhXMg9yefaARfcBr90/DB
SxTGk6tLE1bbpxYe9FgqTVQO6ll73H7oxueOeyvr4v0e8IzDIyQRJn94k63rwLOzlfJqnDYLTMDK
s3HeAMTt+xGL1zHjloxJWJ4y6BO3xCpglLUFjws73+CjKIvgVDNbtbL3+3cLYa/bYfGO0DdZMhz9
5vsU6ZEK2sxZgkzAYCUdwTSGAA+f300tDJddkfGAwn3bmxjD1bvz/uo7J43T94vLP7CvK7b6byYH
VFtneqbcYmoc3Pldw9Ko45YDzhO9EHtFyfnqxiHcEbnBaqnOqOvr4FUWw9t+voOWH0UodxheEtTe
omnnXFn/WdfNVEDQdUP+Ph5YmiMkv1AQLAfBzSgZoml5KJ1zaCwl8F9OKx00zKgTRo/zLV3scy4W
MuNZnwPz2qxgXQ7kf9rDJLcqxNIrCvtGPCCD1pjyhFmxQNgD5oXRSStM2RSgHOaGj+TuZyydMlTH
KT8QFv0UUDtPGsaK7DnUOsBgDLZOOYu50otI3T4nNFgtgONG7h/L/rWVPKs2hdCSDi7LiWPLM5rz
AgEeL9/fTMAZ7iV00jOyhfAavpb4lxkhCXyob/1hp8Gg0qj5XEXr6sJdd/jP/7li3Hvl5pRt0Yy2
0VJSDQ4k7xO9JifZD3begtwXFIgDjrrmDeMg4P7A9uJZPpZduD6cUntG0VMM7zz+uboZKQdCZJE7
NnIKx6zDJa2Ky1d+GsMyYyMP+PLe7SZSm0lmPf/edJRJbCpafYlLBBrXqRJlWOK6UqwuQNGYrQzx
eCW2T31a7Lhvz6KSd287Nllozd2USjYF5pduXY5kBza1uaRMY+ucjnQ61EWF+dn/jsDI5L770+Cv
EuxtNSJxKC4HJ4D+X+zNKtolt7Or6I7DtHN+ufXVzZfO2DDc+Gsv3tWBDQQXfWdK/Wn4LSI8DhHE
vvxnrW63zllAtCZ7FRv6LwnBGyvWvJhzIuW+/WTJrBDKMbc/oAcd86QDzFTM649riFKKq+bjAjnV
egEJzVIJnEdiO1J6a45O8irPk+4U1hKfP5ixZPxBdnYmN1mUMOCSsL+QZH7M5ENWzF5i0qUmhf6f
2RNCmD4ojfcrFudMgeM2YUfVCcToj3+CyWgq7Pno0b9MI2JFBFE0QQKZ1lFBaUaEEfOPrE7P3Pim
aatBBD/WrydIQgEY9qCMHbcQ55rt80syfTpj893GsBc8RpNSUSWc8Ozb9Lxy+CeRO09QLRVZz//v
vF9ZJPT3eNg0ugefGCLVe/gJq3geX+O6uirAXAejYSl22W+V1AZD8F4bkPQb5jEQU3doQP8sSIFJ
xH3RtBXmRpQWuukSLVSd6EoV57Z1eFWcop+WrU5KeZYp5zlRq6x89jr755MckYZcwDVUMv9zuMR5
Dw+JCuXFoX1OgqGkNYOaX1WxZV+Nq6NH/JrbETCGGXyIPbzPwKv3c99IBj6gnjF3oDvSzd2u8EG9
PHoeIiTjr8j4nEO2ayEJJoyIPIwwUolUZwCqISTW5QlotACbDSrw0DixmxSePOF7EK11dfElLqDx
FqMRdjt3MQKspyMG+/rUpx9sg6ln/u/4px3V/+sPtOIm1/Px9QoPPKHj7bujhAF7JW3py1vURais
958K7fpxGTIhHeO9Q43iWnxeRDsnvNwEgPMfnJkLNHkbU8riIb1VADHYzcNY2tI38e0/rSDmb7zu
dC9sTNXZ5DPUjDR/SDIexTGlq6qxsZ0JBti5mTWDrB9vUdnxGGCTeyRiHMJZV8iIVhuoISXPkKjG
YYOqt9VlHggHYQtylahN6nThkAuRpT0H6ET++M+gOqKlAZLlZrfUUhuHlv7D9+ZBurfMgvnzCZUL
oonclo+lJdmb+4M06uxHjbL4azStD0OnXP7/f+AscSfF6jM+mjO0VjKFfTKVZJAOAsEkHnE5gwyq
IHSEoMapBkML07I4u9A6EVZKT18LA3ZNZ4cOFPFSpXqT/45iDbcY92st8uG8iErHzn/XKXssGV8c
pZivv/9473ZITAPotaKfETSTy4lsbgI6flq3a2Lst8GLWp4JbrCqP3e23SMJAxtvOC3cnW3ZW8Xr
u9fGacvglGMJSa8QTUGVM3kchVQzzND2SF5UDNDC5oUikPLIL5D678NVX2YrEKXcXT68k5n+15KU
XfN/EFiSPM1w62/i4PJD0te8H3JgLT1ieKEtj8lLzd5eCde/VJKTU8WvhLWIKVK6ZFl24zXUau+M
muNSLa7o8ta9MD2tlCm9JcC8CRnGf5jdVMPFSxlO1NSjmlcggYuXxdI3UwQtQwbf8gsj3K5ZLrSQ
qRwmwOM2IXFhpmKzPRLqwjzVuaJanl9047UdpUNb/xKSzW9chLId2nakri9KeQtN3evzuKAtLO8G
WINatnak5avLhSO3i1VoK6hrYjPHDKmoJgnvvmHPt1lWaF87DzuFFVZJRXx23Rpb+MJz5k3OSimt
Qwq6qk1bzDNh65WErgeN0TKuuGb1xU4+xrHPrdoqrX3Wd/ZCVlLXwXU2zJiYut7bK5qUlzgJJVBP
L/uO4fPtMK7TkBOypHeics5WNqKbMjdk9i7q879HO7ybuRKJiNf+K8OcY37NZXD7AkxYkkM8oqwh
z98x62wPmV+O6GqVKNTJJkxucX3XeRRoEEOBtYEPHOGm2C0NDR+1s7hMbe5akItkvAKmhl4F/vYc
eXzRE284GfIK72XYq0/8GOD2HmLdrPbHhYeGhgNQAcPAgFOZzA/wPWLGnpXH5usZmkKd381zSX5V
IDdaxrDsJriSHn9VoM0RW6h4ZOId8EOr4fqQ8sy46DJ1BwahGnCcL/G0Wzi/fOJWezjBo+1Ka5FW
DUQYh5ucROQlglEe2sgtXoQfYFjnAhX8ITza5YBkbwI8D/tkLuU4SPRgciOEAdevanwQ9vKH93Do
GVHbC4b3/9Ag9wzstKlnWo/hUEuWt+vFC5+BeR65swclw9HVJG0AEHFHv78Xf8R2BjHL3X+2HGxd
3yLpIzUc6YPiozNMQ3SmP2PYrUTiybvZIrF2h2lVbiYTkPIxuzSGKPYGKoSDrBuzHNNZHHDWc0eH
lPp29NKysSvTfDD3V+XXyZ2Lnmi5m1J73FlAUQicAdhDSdqy2F15uruSvACGracz5q7aCKzsra8M
5uGMtmk90jt45SQP5bzarnZdLwvpPBhzqiuvnj4y1qEdgMzBVq8SgF68LX//P5559DKVx6bep3K+
cHwijXxMbsY5MR1peZAhIW2wYdp5lWRs50pbtApFepxJsrmVwyqFJi3/4JnUL0T2/2tZw1HcLseX
M76MkvTwe0l23ur1x0hXNbLg32Ou+ZsEWDE1x6Us9rZhAeJ62Xo0HM+KPqVZJDL/1JPqEDWt7JeN
WNkSE8FGbYwT0sPKij6HlrruSDUSHfblIjKiJAYaoCM3qJUuaSAvWXAXPV7htx4+gTuVJGK3+Gl7
DmJ7tTWA4ieFMB/eX1Jx5TCoJizFSMGUi/mcH6LA3zXtfAmuKz9TuGz9ACuyZBZM9wcUuAqBhW0F
TR4adhEjxhg6khNhXP6BOz4laoiw4/z5vrRgUcmngGDLEvtPTKz4rxsCaAyqYorDcwh9uovBM0//
iD1ttikq5cGO/DX5zZA/3ZXI/pGkbUDh7pHwVW4gjDMk82vJ73URHDLprGQWq8oCXtZVUu5QhHTq
cN2gPKeUM71XyxacQ+rJ6/9MyIuKcwnbKH2wTwD0u6PWUDur0dedexyWusQ1ITuHlupTEfwBe7p+
SaGHkzdj8IyzWrCvnyUMeCx3wRgRKYxzU9//R1caDgv/gTimOUQCFSkH6BPhgO9yGn5qGecXmepO
QLWQv5ixX0VIBNSDU3Rc8xmQ2oIjdN6vFG2Jpv9wbadO9pvSIXYUxfAAiuDk96erhEQ5phmqEE+G
fAxHMZhH2IdGfAJ2/iRPcxusCLlJfmP1UiI2CgkKRv/b6x1SLOCkOQHDocNSpoA6UHQ2+WzKMREK
EGSU3CFQ4FuLEKDveQdEczmA+1E26pG4SPoTaudvxwYn67vTNa5mP5pxa2WNJJ8O1PX8rajaqqDR
nBP6lufxPxnLs1Z71uxMCEVEQeJEd/1cokItJgLsqC1vZHt9mRol69sk00Y6ZTVL27jtKWmhPT5H
acn0muB67HfEc/g8mcKOZLG1vQKaGDm/tvd6PBKe6UMkKFoNADoyzC2lyLJIxcpQX1iyurmd5Bl0
v1ladhZCLfOBADdsIUGET7nin1ULZpcr4RiwfkKaWrp4mbf1i4KwBeyx2crc7ZSOenPuB+EWael1
WzHi8q2OYKK4zu6wXNOgkdBd88D06ypSQRUpZ4eMXBYrzKXrdrfNqodiGqJ6fOSeUpm2H1UfidEv
5LMgLTIVS/LQ0pAXjf4yXjyOySBuxOdRpdTvKHzU9LdXwMk3C+DtWQROlpdfebCNt2kAQCY/412E
ghMxU9sfhtbO9gJWxZoQgBr6GISm8ILAAmmEfwh0+YLHcAEZfEUbCeQMsFGGvxLJ+IWcQWPDWIYF
6v97wP6sNxx6k1xTvWofjLYK6VBNZyRDf17uJTn3DYns4dGCBFaCF/Fe/6JbjU8xOFUmmxAqsUjX
akZ6Tgj05x6qOv6xASNsVbcSAqa5BghTho/pzVI4TYMZ1CN6nj9F5jUgtCha9EgjDqzQe+0VsLUb
5aNhF4pF1VMRli0B9kIL3dN4ChH08kmxC3HnNn7UIQ6/GI6c2DxaHIxXdzpbsEOIiz1kFH1huoqj
ZxfmZp84zwddSgDBz0/87AXRSZr6J1darsXRpEvN42IB5m1wajjStwvdy+SiqRDrB3iM9uqZfs3I
ZyF+i7Sb9KHOozf99xzCYQk6AkKiRPpZStOQGFr//JHphWb5Ky9uqnv9Acoz6p7AL9mf91Q8HKPH
wBOpx6fBwkgMHm/0yZQA65bpPASlnz5RQpqZpWTWLdEwNWokOxBeJcJSLXF5nS2JCMBSwRKjTxj/
wt2pd7Z2605sa4DW4kpTLkscnBQpNbbVXjCvJVN5KTkwuXBbVQj9FEYVqA/HetFED0qE5WU6txTH
r0BnOZgWjxKerAKT8kQN0mpAHCUe10KDSkO8vOdHSz+9YaoAPFy4ArHLRy/SSNsJL2R1g6alTBgu
LstTeByZdQ7Sn57vmdzxVL87LZpLqoANf08yj5FXS+lqkJ5GGowq/dE8k2xN4NLt7w9rMcVFBtKN
9P7hRYNEappQgZSD8l9/WzAXlXQ+vTbiDS2lIF0GNmY9CWzwQZgTOCpiBz4WPTvtQd5NVoOiHPKl
3IXHGzxq9n5YZiKpf0iwj1i5xUEWgV8ZK7N0hzhTQUr68a7BWRjGSjRRB5zXfrud9PVZH/v/u4xQ
DXpIZ9zJuwlpmsR6V6e3+GQlwaWT8QaRK2QR3RhTr6RT9hoVsOeKctwPioG71uYqSSg3+GhRgfI9
6g7mi7OWnYo1dT0QQyvyUb0A3bwuHqKbFaB8z6n2DPHPEQFy2K2fINlCEaSEZKqNkSQEST7Gctuu
1vM7wIDYeGfE3CAjj0VLzlVR6FshHNsxn8vkyCPYalRqPIkYZkg/SSJqwduqlNHKi2nBlpYTYXeA
47qu5m2fMM3byEtGagfdc0yYi87Vty50Xzz0+kg8dE+ZRe87xyE+Pb1VFNFw799hfEnGsLsmQG3g
Df3f3JxJauHJDh0Fx+nywaEzUXzFZNW7D0dn9axTs0nkP/e60eFmfAR1h9qp8AsM+B/L54wBVo7F
RmP0v23hT9M1JROfnaJ/BvbvhizGiC3c7tjDyPhy5+5ModJH1A7zEWexKbTGXGqf4FG/GjxxV48F
mnMcdpOZI+KGfLLssM3XjAJyHeikQ44v3Zhdb1qwRW+vdscJgF6exrfdFTYjXCzrGvVu4V3RjMd/
ubonFsmKq22Qp3o02PwfXbLMTCl+qVJuvS8c1S86dke+wz45maPci4IEXORuzbEpngz5pl8TDsCC
cZCBZKwzcNSzQ2SnU9ImETxAMPyyVAMLXW+nF4Q5g+n06vJ/SJs49TMkExlmSGiVu8+cpeycYbkI
I5xNaAZBp+Nn3cL6XrqEHYAAuC4Yu+48e41mzOlB/ukom9z8C3AW5lQE/ysIBReD3aYC2E73KyN8
AFLeq9dOGhk4cEUNN/WhgbgSl6G3aH8TSbBgV3bPnBUaLQsolXxTfbPhABQBbtIaOHElwCGXq2e/
bLq4I+cXPnmRC2d+gxqTdwiATREsmfhrEI32EB7sszZtPwOkfo0PMSXZmHftLCztYp9MQlv9TXOk
2opfy5D/FdGYaOzJymFQFtk11mTT/4XfAnQWZ5Q5k7XxIrocJcLES7Fcn+2Wt9cpSlfKHYHopG1C
sPXuhz/B5GdPWNpLDYA7uOtVZx+v19rKLBBZV2SA+AAy5/jUSvwcqU9gotlQ5tR3NIcAGD0PNSRx
WxZhwRHNOStGIQBa8HCRt2zOyNviWPtgGdhqFWjsq1r16457dhuVXHMCZuala9d+gO5d+t49sQJ3
Dp4+NLuj9U7DjzmoNAklyk4zXfJwbVPtLcUptsD063C+1OmNQmYSRm8h96wSSpVKSG/PIArhBD8R
zTiEfPYyFDtO7ApmJ3bYsv0tTV6o0jkxPfBIvRtDwzNfGO7s8OIP5XNeYBLTYZyzZp4o99+MsXiy
6OjV8UHhDkrtiJ2iqw24ZObPpZ4xoqbMwaDm7URc3FxcdcI25iD6dSgWylPEBND4MzKXvp1WWSj7
RQhAF0JXu0tXNirE4/8zqYxsEH+t/E40jbVfP4QS1Tf6vxQAFIRs84hMLop1yxoLc4Ck9qa3L+AD
57AS6II0kzuw9OfgV/QedvOiUF7nyxqkiiaCwfaijAeWF4YmNIfUWPUcUwm5JRbXOBsqQO3AujES
W39E5tL/ObBo0dwQ95VQLNiwmubSJuvY1/ekYV54vux1wiBRvkxX0rFmYYo/QnJOe6UIuqTxseyW
6/48xrBmcJQGeCtKZw8UZeObKtWDGzWyKs5Nips2NdzPu8DpfUzhJpHMqkFkbOTiVl1QvP6/PhGd
lAmON5+RRWxLn8eeyG9ObYro9w6WBekNhONmJgJHDsHk/W5GSgn6iY9K0lEyWfcjcsUM1xCCMxAv
i5RWJ3FX37WLN0wYz3UeV4VZazJoqtyVN1LFajDESwPnq03F6TYsRtLrRp8h29ErS5Tdk75yezQ2
DC6+Acw2mpBPIJKZAEdxxVs5ZIt8dQTGCEVqV69oQ/wLwFd06n/sWf/kteXOneDU17t8KSMRWQGS
BQyZR5IiFrYJhIOElctEYWCl9xHnU6R+ddPP0Q5o2Cv3Mucw+8NvJzmDlZAnuGFi1hfKEFJDi0D6
oGpJOgmoNSQynm3Yz3elIzwMmiNVGTIY3SZDPMi5MG9YO7q7+kdOVcBWGT/2SlEFad34Sfv/yz74
ppH5iFLbZjO+TjpkpsdkNTZeLyZFvPpYnEuNnbnHoJaPygfSC76LygXVcJgIjVa6CzjbOSMp7g7h
OWNb6ixZJF9UK7+eiuAC0R50nolJx2t1Thl1U3VcFL9aKcA1wPc7SaoWIICNQplPz5Gbx1kcHNti
ZmyNqEgGj2LkncxVvRvMOEyew7dTph62iZ6FRa2dDlvzmtw5y0kFKRmAOwKNNXAb76+3Hd0Z9CLX
oq4gd/bO9+NhI8b782pKoR+nzmLSMO40+UTRhz6KWDSPjb27WZHcZVcZxoDxi7stBJf8/AipdunU
XY8OgE6Cmk8RRohC8sgFoy+aDSL7PGNuGkzcOeYohYLib6tq3tkUsRwJ/1ruMbV1de42vr0vYahV
+MTJGjbw/7XtadZnBWAfJ9xPUfDsnny2LA6jAcbl0t8gZMo1hsa1wovBjSwxUsj0Td1DAYxh8nFU
HZ2kiolgcN/vfDNypAf/PCKVcdetdskYEYOxl8zk2ZlXMsql2y4qjjzwC2FkiBPks0N8WDg++wdI
jSn9ZmEtujciFxwbDhbF9aEniJJhHURaKbnaas9JSVuD0RiloyaaRxAR59gPaIfdWFmxw7W0ccgr
xJYM6ECo4nuZT5KPMR9LCiaRB8A5fWoiJWtlHXWRvis5Sx1IO4qXq57bvKQMT78geZaFxBy1bx+2
ZSZ3xiGy2ctWU3NWer1ToAZ4ldajPlq/2mfUMN0MClHek+HM+9qb1QregaBDEnP6fINr0Ggm9zWi
y6cxFBqEGjYlAM5gJ58TmnncIVKkv+2Jp2vgDgXoaJAvS2v5m6PcRDpvm8wlW6fDkmD/v67Jqmu0
bHUoJhE+Fz4JYUQlPcUl/Gj3C6enQRnEkMUCHa4vm5oqjaHYHdiO6pzn/EYmy9AO4LzyrGX6ob9e
HiTA04+3dCFRqWLOogd9llOzOCng+mVic7FLhVX1xjOP0mjVsBPdbiisHEKSyPGLVqHMi1uqUBRc
cA76kmHrD1pSdqZePci6tqSKahJwehQAMq9QC7mJWC+gS2F/r2LeXz+JnGHvLzGR/scuc7lU3Nvd
cQn8raOmgbZfUZUYJMxEAjWA9fDlJdjz8ubxsmMw71t7lzFjmWjQ/c1c7RPnN+1z2j9gs0NNFibP
BZpRBd9nlhT8vSpcuiFis8nBuf1fxYaE5j1rh11ZbopWSVJWpUA1+XjmmZMHQdQHEoJetEZA5QB9
WfSbHrogJYiFqOoWYj0xoRjUOFjcBCiu6WYhGVYA/dK7w7TmG0ynURM7ytOV2x1l3FsIHGTd6j8/
R4k2gw03d0AJgUEOPJkrouVxKPPpkmkwCOGZuF/DyLVae0XQw19WByrh6/0UnuqXyMGs6HFSxs11
B4awvjZwmMPaWih0NYfctXx3jPFJz8DiJbmbB0OYwT8OwudTz/HQg/AZZXyRIxZtAJIeZMvBKPNF
XdDLpTFrmB6Feis67HXBBCEH9IgM1HrTbEsRsrg2lYD4O/MYvf0agjMzQLbiMHS5k95/4pbra6ib
vILmoTuKysp8J0wF59ZXJLWrwCAGT+SYSPALhV9khN1o33YD+3C5wS3ZxvcW09NujPUlX5nO5C/l
LkXARfrS+AnERm+mo4cq5VwDzrvxlWA36YkfatZbdtffO+D+NmjP4VMAdo7v1U2lOlUGLT7kFt7Z
Xx68EOZQ9De35V2kItZSfq7/AfjwL67XyiPkQXOypd7w5qg4YkjTfuDLbmG7ukN2vHgK1ulN/3jU
piK0bew7/6QZY7JIYkcOvad5QPUnghVElu2WNXNcHjn8p++6H1cL1e1cxltmnfml/+DBN83AXlYj
71JLe4FIgi0nml/LG2hSprKBjPOVPwcXNIs+qLwyGDobxKk0Qi+706y3PeJxcBHlK8e3S4JvIoRA
8YQApUTZFSJ+EFC1em/4fQrX/QUHWNqsfKTMepXaJzXF2lskCmlRErb8f+lhNnuKiJyvRsGxteBE
MmExoYtuJOvEMRCtid5x12wDDpR73htFjzF25O8sPHVUwjgj71Kqsd7tOM09MWyp/YGZa1Tbdcnn
fb/glE1gMghCGwp2RONBW/1K3FEfi73qKDmcf3Nh6ko8xZ0J0EN0CAvj0kBYj5QnfzbX3I4rWTec
RQ7MjYP35UZFrsEaFg9CS6bzWGfwu8dXb2TtXmlQ+7UL05iyUpqQzVwzQBXzgprYTMx+gjly9Rfb
VxIgqG5aZ+KkEMzgyMvV6+vd8+CgtdjcNQmhRtkNUhofDEyPET9AWBVVUIzxSRYscr5c8MfuA1QM
7K3F79PxiVTIiuaLA/9usMfi+LD84IC9NP4KTugIwetG5g6Q4emO6fM+apIqasrY4RoAY2oBcGpS
EUqW+0CCy8wmIHV0sW7moOHz64zhF5RwiguOAo9SW0e0D+C635icd/cncbffEaWt3uC5A0h7PI4x
JCruYyGhK4WTIDioN3oNxMcBqkwHKVBPoa1ESMpuSTqUcJS1sYwMvXR/Wg5CzZgnzPC1y6xTVy7i
t3/w2VAT2g5Nz4k2Sg8hhmLwwzmeQF9e85NGQ+ahcfebGlJUbvLgrZUGBbBJMGlU5m4j+xo3KA5n
nREmSYzF/sRdKpq+e+MIzSEfpDxzRcPT/CtbCJt5hKYQ6d7eb2I1WwBne1HUGvawfWR9eMnHQ5AU
PB5Q4L5MeDOyYewXFCC2w0ncEr0Unxmv3Ki2BIu7v7tGNnQbCQMga+K5ZMEu98DJhZxRNFFcedkx
rNelS6bp7cj1rNZXmqNQ+u571Vce/Mn7Y3xbKwPBOaR6zeayC7lbXeXhJqH3tajqgmwefpdRMVS+
9gpM+1Syf/ZTdEIKA/ghu93voZy2sqivwNGA7f8OaNPiWstpugk0bYd6lynrXtAHK2J3vs62cIK/
s7TnTSrh+XoKxOZpG3aPS1FY/kO1jrH44H3djimH93SM0nYRcn5AQfib5KpA6JKHM0H/rvuu7s+I
T6KrXi/mw7Qu+ld+gRK5Rv3aNomrPXBoN2oozkt6eECuvept0T6zfqQYg0ayhyBlvhYWcIJhQT3l
PD/zaohyDMb25ZO+avn3K0DSE77AKMl+hNllo8ZShtGQiZIM0E7tKirJkdWS8mWem8pctQVrMgL2
AcJ430ogk+zWM5aw4C4lFw4+zUKWYsUHK5mVQKbMF0TqESvaMlV0p9LZ0N8y1rYXSHiY5PUJFJnu
muY8KEd1XVq3E5YtJoj0q0NcWLUx+V2yIRnm1XkhhqOOB28oBesIlmxDUZygRs9lCRAFkiojK8wl
abSpHqnP/wgWY5MiSMk65xKQcdjLYbEqM/GexoZecw2jL2AFwBLkqjy3z2a6VRxrI26fJ5phlmnX
+XVZpY//k8X7R8ASEzixKU/3AT4cUaWI/EPBU76lknOJdoeu1JeppTP36GzEkOFp7Wgnt7wILOnR
qxiZRVZOlKiIDbjo/kULPLbHspbH7mYJ5UyFBYGV2zPezVHhsUtxQBd624X2SY61RchYhFYKZVlj
7M3Ps5CCuIF75nyDBXPxpYWreArs7MWXadO+7WM2r/GtLyRx5zj72+N4f1vgYgAekaHFd3FmvFZg
C3NgPzpPikuH5f6qsslmYTyHgJy4uhHawGOAWZc9orm1KJ/wmWTvg6lmDls9hYfhgxMUH1XVUut3
m5FuvrjD/b5dlIJq0Zgs6KLNE4/UptLBS8wxfr2k9g0gx5mJPD0dD625Qj9VxFSM7C82mZ9AdAv5
G69JnvjoC1jYVWqMe3JhfB3qmofBPcexSLi5X3fb+kpdCu9/fh3J7KQmFDNR3QfFi+F8JyKNEV8z
yyqPadzZzrycCQNFNgaWeZpJPkArwgNJeq9LmcCl/IiIK02CcI0lcgUlGfBIEX9OB2KTjOTAoAnX
72hKdMG3cDHNiR7teeLpl76sJxmt/yuhlJUVQYO0Qq8gIePo4DqQWr2zOpIrAgrTeXczV6V0h/P/
8jCdUvYcOlUcM1nILLS8tSRIaDMG3EfVq8ABUDDR8AE4GiZxqDW2RXkHtl3jtohG5QZkQPfRdwPW
3I06mxvLjQHa71DNXiL//Yh40zetZIMbE1sNMyKTGNWJhZ1e9R8mVcfNlMxeM98RUM0DIg4oQh5t
r3LuBrHphR/fvqNeJ0qcKB3icIjvMP+VbfG59xooJXtHs2hQGhHpStOj8Nx0BhmitV4Il9tAp71D
FrsiCaKXBp7E5N675ePcZ62V0hN5Xd7mQMEv1qiLsGp4kzklX6gLp6rZm4f+Pim4MQ9Kzxa0Ls3P
rCnKqdYinJ1QK+RDRLD4beY0fygCYKkeKYCGxFb79PQ1/5WdY5/gqgOpjhNoIzQXCIF3i/OObTGA
28efRDCQutl2GBds1C/0C/6wJ2OxZemVjwq3SsGnqcknS6iay5rF+7itl7zVC6vfiTfj2aXhrAny
+GpmztRjLf5AqLUMUe6k4y1VO/E9zSO0cH/TdmtXwPlfDN1rwYpu/5sghwzEynERuCIU7p0EEAmJ
/NkWK11J2VGVMJemrmQMD6rhAvkMCC4iT4voWMjlR9Dou5JLzCIrEpTOojQS3EGc9uc+9XovOPDl
8a9ii+2TtfsJJS8rN7MlRy8UNZ8u5vl/8DGT0wyww2NmSOqCRj1okV0Y3UZ8TumKmpSZwFooIevX
Sj6/HHkwICExQCN5V80vNzLYwMA+00LUfC8eFbQDBlWfUnYOz0WVggvpQeM7MMIlKqqXmMU5catM
m9tYqc3i4KsD/doEuhZAsT3UO63czTCyKgZGY+YyFWfHRpL80xu6fqItKCHVeLEJcfKuvl2yRlGG
3cjoh+rwWVX1eF1mO1BLfWWx+uzUazDrnYhViXqm31Hajq12Q1xRqWLPcuDw8Prx2aBqwoXBvuGt
gSpNIgag0Kbpsdx/axTTR3gswiHZhzM2yp9QbMegdEp04cItQ0FYh+rBxEXyNsUVCLCiswvhovIh
/vE4hb77wOUpdqh9f2SuFtOPm0SBZojmsqe0oW6uhMzEAdFpV4/y4NFRBtx1InA8mbJlYIYQ8SJr
gWZEDYlfax8Q7umjWSWOWoF/2cPYOwRR7lRwK/1HKIjrN2AoGRrVVPs1Pc45KK4NgRZo2BJPXRho
6l1BSibP/OqHPg0fcXX3LDy0fYvp062JUIBmKY8t8Fjor4HRG53JQIWX6RgEd11ttYgM/vD/EDsO
msEiG4DcFoNRxuEvnIA/GuAug1De3FsK0VV+C/J7dMSuiyc6oBEMx9gIlJmn4jJSwmOxpPwf8Xec
wWZXeSfCxmcvpKVlRIm9DBr0covZIIbViy/N+/SHuFYJFICf5NcEOG6iEgSFPo/5uVUZd8sltxct
JxatmGlno5nl46MHXKvlDdpKZwADizUB46+SSjIFC4OJI60sUGpzRv4mb3JUrArR9Imm2S1mrMJE
E8qMwPwUTQM0l1I+ZjQGC7+PEvdCpCbUqh1+efQ8Yza4/EOk7qDHwxduA2J4rhQLn32dr5QeGd+S
BadFhTEbctnI6i3NGIHQPtVo4vM7XxLKGYJISGwkaiZJtk1dhkeAsdyYwa31sAy/IxFZkR9p9U48
60VAr8VTzj9IjWXCcYHctJKnp6g2hxrh1jz6/lY5Ea9F+Y7N8J7GSrvRUU5vsVZpvTZgYAaWEonK
N3gaYFWXTZwIrsci2Hw7L8kHRTE+865ZrvNloK1zDaiQlsMiQnAvnmTL3GHEGN6zZFrh54vqPvAr
vINQgX7X6/NI+lhObLtA6FLv1ZETdPhS8lri/o6lvMosEE9RGld9yiSvmB0/v3owIb+1FZ74Xke5
Clf77wYuz+XqyImbV4sBpFPb+Te7haF+WhXCWdTzU+pylW/r1tndzsW/JC9H69klNvXT/HmSxWe9
eEjHfIsU/8/2UzIrp112+1rvLmPrTvGvnyrSlxx3jxvDBHnHPjy5GQzWERWmgrCrUHXGqbPWMcOQ
yIGpWxXh8z3Z+IVOVpZ6G5siieJVgcOkxwMC0OloiTIEVsbxjjLY+BlCkOik1wGexdwN1uS0yURC
rrn9AmN5+ncjUuA1r6pRMxfyomIPXfQ9r+uGusQbOB6romyibszFFhuPJFz35JterULZDjDUu6MW
caAqsQLKJCxvxXmyVW0ADb1lrWVOUmHzQCe4EQNDDDhztE4qemvoXBrw6VKmbFCWItZN6G9wPVTu
PeDnB6ge6k0aJoHbA0nvwv3L0dt6nCLVrIb//JxgSHQ+yCuwR8Ang2kIYVcBGSDwEADMhg9+JdeM
Zi80eP7Laa8YW9B/avHJZWC2eMHsyzbRsuIkkCCoH3//CENcaPU+KCKN8TALMUSYm2v/qLN/lWpm
B5mpydoxIiS57wWMF6/U/8wsed2rqTHRdstrjH1dKCKM1Pnk57ZYyUdcqHFmtMi3eLQu5Iykz1+p
BLLe8ooreHHF4w74DxsUQ8+mXbhmYvvWO0Srv/euPjZQig0cbxD0lgmgfl23HBuRutsLIvRJiXre
bz5FkmpiIImecR24i46vN+CGOwOX8EiPsasr7nsahKRE5muT991LGfQpXb8Tr8ZOu4ctX1jAbmY+
YES3N0ZgnY/eBz2UIWVF9yj/1Ozl8PY5IO/H3PUyYpRfMcd03Z3Dn5C6M/EfK+U8/riHgd+51rYx
jx+377ZtWGMCNBuzY5t79r3cQi2E8IZur1xDA2r2Y7X+bHMZsStBpHo1Q5ukgxTRQIMmy2FWOvhz
lVuyt1d0EDT8K2jeLzKzVzoLA7M6YyFSKR6nNRRhakNobqFFmDy3mphghq80P2P2AoskwRyYuXn2
h6B+e4RrKX1sx06hiIcDWp7EgjWK3cCw8sqRKzBl+i6/nII3sfkUfhRyrixSRM8rU7NKTRgzYgrS
ucYjocScsOil/nt6NpwtoarxakPT1lPihI2zqUw4AUjW6rby+qJDFW89/un3ojFLRzYHH8/0GL7d
FGyWYKJPIx/x6onbtgrlCclapoLXC/sxqNY5mOyymWsdKdu7R8pps9Kj1ZAz1YO8kBOl3pVQlzrR
FJAIcAgPDuqiiXhFh2hW7HkDNcT+W28u1kJJwU5Fx5rxpI1b16BYfeKOvbEpWKHtaUB8B0xxtZaA
OU/EGc9p8yH4XxF1Ayp02Fi23At4uSdSjvpa689ohkE3+zGeJhOizPJg57/o7dty1XJLNzTxgaN/
ZHG1QSNo5RCaYcM0smM/AM5B1HdnYw6nVKWDixIQZm3DsoZeEPGjYk+o8TYHNBxY4Obv3UN6qk2F
5lTjahuxRGvgRxK8UpeukSZso6ZjHfz+kOVaF/nVktFrYU/hCX1G6ey2wDAT0EugX1NZEssXVkjK
lZhIYPo6HBJdGIVxZJSZ+ass+DwaFQFWEgMyw636ZPZqRfon8PwOcE4rIlClgHlVCI87jJSmg6LL
KqjVlY5DBdebb3EMlHX8V7bPVqxYKVRkbDeI7JzURIeJV4N9i9gKkbD0HkUIF2fdfd9VdcQVu7Sd
R9YNvAQ/FPq4Vwd/Xi624mfLU5gfm+c5+eZ1EJ47yQDA7pqxNeXnjgWbshiCbzLjd052oPd6O2zS
IjpA++QI12GXdhqqmpTTwiH5whT3ZVi1ZgxEHiihtQgNOXuH0zvWZJp5DyAP5hUKXOkxSHMG+BrW
2T8OauK7kqo2cn6lFYy0p+ZPAaarWoxdgCs/HqbKFBpL7HtFdS4vLsMCY6yFNfOjhxg+fDgcj7Xk
N7YZEhu9aGiaTeqMWNAwuJF4pCuYR8T1hueYM23oC/vZTw3gveChivhT8VPmBeIcWIvdB9Nw+pY5
AReKnWHD+dVMT9DNkG/i60z5nFhZjQYCniHodT8u02UtYh7/5KTeyqP4gN8W8lYIwvrcnn7qlkZq
gEBZ+DJ6gM7IXKTvYmZqBYxhGhN4al0E/1BHRxOjq3k8YLVeqfCutj5vSA0WZYmKwrcHNa3miDM6
3z29XX6xbxEGmpik9zwNw9nA8R9AIijY//b1x+a0LlY/2Z/bpaMlCcOPm+S2aAMyS0Bum4rrliDl
t8JjhQzqGMNsoUdpJRi6SJXtxAZrahob5N11Rrqi7rVYlqd4r412yqss3+YqOaKCX2IkgS7+Wxqv
lG+HcvdoMZx5W9gx71NqLwVeUipBCD0p56RTo2JH0TBvwJt4zKrb1PJKLym+67luBRX8TqIBgDz9
2+DZByxka5zfdrOtDVYfrfctvB0hfQVEljDVl5bT5+p/A99XfXRbfuk9ginra4yFWWkM1mJ3FHYO
YE75JJ/KvCjq2sCyrxR22osP25A80oIyckibrJUWTCD0nwGsymCOJZ5EOcKuw+1i57QC9T78D6i2
P1j/637dS0qkOYDQtC21wACPMnCHpBk9BEsIEFoPuOyJIDAefcy6lp4r42xtEXWja2AWlLZLRcBn
mbO+ogHqS2kXv6DedOclSYG9SEKjYxK0GBg5ZOsCWhEpW9757qtsmdjPog0sLrepTZiMMFtdnmvf
PpihpQmdpJ3ilB/K4YJ/4MXD+j58NdGshwwyBdJs2d3W92maF4eQc68G/FYiSrohUXqz05hl2LUU
0evgun4xWvljIcVRrj1x0IAmKbnF5v2E4Xwdt2a2SO3iMB5cPWzE1WuaXJy3p4gs2HUbQejnS2oZ
9gX98Mo13TdRcgH6dj+K/FHVhZ9hpdK9uE9lTxXhqjvFYENsOWbC2QDyGVVt8ErEn+QUAPyzgpSZ
u2agapweZpVoqJcfGE2fT5ErSCwBgjEWl/WtFIr1mt/0cbx6P8m+ejmRbCk5aYj0wsUG5ZDyUS5p
7cGzz8B2pm9MrhX0fJ9qFAFRa6U9MXsqTtwcLdHAfB9MKgw1YAvTmIBi+nY6W5sxyJprCdeK2IXy
FgvlnlekGDbonV8gMQf8EbaNFcZt4BXekXzD0RNfaEgoFJQ1qnGl+pcDAXFkRp8MM0YzR9Ul7m2A
oY5H9p86Pxx4R6WH1UTp2QrTj9/rXgHGWHe6vdwL644cFPXMIPDKSaDWQ2BmTSYtqJl2XytR0kyc
c2oSbheW7LzOi63ENJ6CPwSszTlW96+gGe6kLKdWkOGumvvPpD9hk1tsaS4XtdfvcSkah9/llaiP
ES9LTfCEyp01bvW8wOnWgHEyxzkqeVeboZllUmWGMCZ/H40xvQNXwAMwGtSGpvhht++nwG3LG3U1
JVnzUNIwwNXs+NgJTtogv645D4Yww4+StpFwZGcdUNuoVw2qoJjkIKkdpMUm2qsllbriw+O+tmYO
iZSoxMjiZ2are3xiClarM3dUbcvUlRn0nIywK1zR3ikdLAgRLZke3gmeVY75HsUp0bw4R4tcSYvQ
jWVof+k0u60huMG2E/Lhmqin4fDHmeOdN9uxGXd2wHk/dxE0WvHxC9R5/p5hszeUjK6rUM5d/Za1
JR1hXI7GULsPyLJ3cYOC5w5JyalrSwcccZ+qlwtVtFKme6TWCoMTo14fnP5sfVWnN7+AIwYNL8iT
i1A1Mr0Y6u6lIJ1QlcfeLspTCHYhRP2r2sTKjHCG1oGk3j0pO4zWy0bLXFJWIOL7ltC1E2hC8zM6
fHxpJq89FN9HNJwKNbsPtP+IHRnTzfDCNV/hTtkqU+23JlimhiUp+raGsymF5JNUzn1JmqgFJjVD
ljgUPlB7JfklgYQy9fCMhb6a8DxqA8xDb/V7IV4aHfe4kur+F2wMb41n8tZLRix6lsppKyMqR2Rl
MKsw1vQ3anWI73il/QDC+5RywCyGkZOkJGUzhPXrFhVudCKHjVAue5o8TUM/GX/7sFczk7Z2rlIa
FotZUcS+h95M+7pbCklNDMI55fChI0kKmPNURvmHttoyf+VXiBnyy7ksF69SBZQ9QIjyrg8NyBUz
2DkTXhy6zEjSH2QOSJeCosEX2Q3hr4MMAw6LdBp8V0PIg+dssygc6UMZ067gb2q/vm9jAxXy/5PC
caFVmafQq7LwwcenSspIbTZP/3H0C4PtdbWjPfptFKYb1ssajIFiVw2BY/vo6w6T0J/fWtgB4Y5r
i4PwldPQSdasY08TVy6f++HFUJVDFm0Y05US0wcitm0gAMi8Hie4ZG3/Mocs6TNPq0V31/pRJxMd
B3JWOb3Tx5xyrk0V7CgWvuqlOGEjP62k6Xpgwuvbwrc0wEM9QTgYX15/GvQYR/wGxJ5QQ2XWGbER
cEaGs6xQvXWRYYMxJcsk3OV85WfZPDU/qhERG709Bub9gkbaKSPn4KV9fyKppXTU08355GATUpzu
tXOjJynyPOCVS/Kl0m81ck+Zl8Gdg0Ud1l6H+SGncPu/GUsqAFLJHpyaAHr/73tLDSMXWPHg/oNm
DkLIXnQ2rEkD/sjpl5dSF28NYE1m+XDn2gXyzVk38rHiHA46zrbhOhbRtxsNLkC4JVztXOljkFGQ
JppjN8MvR8xGhALO7FuC/BS52pNo2fJcvRn105vQeCeBXZa42E0HXjdGeNAEmYkZWEsDNtg/T+7j
Ebz5sUtOp+Cgjx2KDlXllMyohYqrXQ4CU9wKUsECH9jX0qQYvuC8DWQ9IGcDa2BHpxi7E4NimWwy
+N2FvTcH0wArPJiohd4JqY+TIUC1rOWUqYqXUmbfosOaap+TcjgdfvGFrX8OfdKZ3raA8vkOYPo6
qVLs9C+V88tf36p03Xw16FUTlpbTWvmVedel8qX0GI/C4xYjk6q10zwiDwPOlVaItcSFuNm3sDym
idTwMyN00a0cbdg9kDX4WV5y6LpQJSazhh0vqa6EA+3D7Gr1p0xSTpZ3+vXF583KWxZAWaUsjjAA
rF6RzOacos9bFm5WPj1ZYsFdPoTlyGvJGcqzC0WoUleiYbdHB5wBcXP1vT1lMRfX/jcjGydhHLPd
NuRvVXsxDAOqtL1PdfENRyXhr+0OArJQ5EQ3JcDaR/nAM20/TtTWdyjfyDj7/gj//oNAqVG0//p4
Asa1DMSwwb5wpDs4lq/1acoz8i3HRR05LpZmP2hHiFjXe/JyF19mojRGHIbM++sF0Vte6wMsAv2s
+WzhB3xCuA8WPJLDrtAenTMXhW2CaeFUm3h58as8ysphGXRsJJcFxksFTFYqVVTvCrL2D7sT3BBs
byS3lvYLDwd12l+7yy+sb4Dq/dtln1rcLDpcvd4eKX+rVD9q1po0RtCDahC0gSdqPCLz4I3WhmfZ
8mqqGWrZqJFI08Dm2vGgA9J6KtVqeajG8e7yKdlCQNQHLRHqTDLk76rGxyBAFukl0n1aBZrTd/hr
xk5doga9glFgVho8WnqIzZ3jPFASVrtQoZMW8lB4l3Dhs+2Z7+1ko/ak094OnuI1EtSDKbTbzPr2
g2cTsM8DPU+iyTQ4iXRXfDHMLezmZ9f0yRKl33KkXuCtj/RoA2jChh7po8/LH4e0tr9mQ+yH+Ljv
JoT3uapxz2CJjTJ5qQiSyZsSY10qKyY4wZ87jXH/ApHa/vQOPGTntr1ZgOJjW2z5zNlc0ZXeGhoc
DCWrsv8z4hTqkWp6DhF2aRUGxAfNokkcxCqZBhJC6DL9cETC6nF/ldPwfERRJFLYBxdDHULM28KC
rWlvwJpeG52thrGSgl6hTUqAbexne5/lw30Ov4UIH08pMimbtUXIXLsS0QTNkCA4eVHgky5QVqX7
ukM2RZvR7h5bsZNqsCFpQpm9Tav7ZajLc9S5l1WZgikPfZQHpr2iITGoGeR3KHRimpMJ59HPkaSc
QBVePyL2iRuColF1OnetrmwDO1s20TzFdi3XNwZTGQoAaDjPE3HkZyze4FUv0peegu/85fITyCVV
o5wpvN/dJk9cgjikwxNot6UxCRR5K+Pcv6WQqWqL49gbbf8AB3WVKfRXi54OgaRC3GxyZH9uncT0
xwPbX+mFm/gulPwjFwBhPOdAoafyHW4KZT/aX5e8FP82c83wsNUbZ3pD8TVGs570hDg+Cdrk0frY
O1QCXLMPVcYE2g1MuTR2WDFXsLeymuPVyqh4pfnzsTC6VVu8etx7w0vp6VcIVuZpVFPTJlVHjaL2
G2neAC9BuxqSjg6Dpds91AvW5y6kcAKM6zcEly1tAOtTt6BXzji7UOJVINNQGs7krlB6VozRYSI8
k3hXMV2MzNGJAVPibocjgdoI+wmhL5jGhabasFHLbOWtjLbSm1JLduGs1zIVKiL6d1ClSQlFLHpQ
ke2PgnBUZfvaoRhQF2HBhiskLJORcTHxc04UZ8AQcpgG+xZVmpr1E09OeApoVN9GUdICmRqB0vL5
d8VKePFoJQGDKubOO9o7XjR4xXy5haomCWBJKtwzoAuBYb1UnT1RzAkzO9zhaugNjjIRg0wKlTDI
XJbrDRc1ZQpLWJ3KpE657drRbu4kisXK7NBTDVQiBL8pNLLF/Zd23cdX8mTBoSdKzL9iDg2a9yjI
PTlZ0m/pUPRYadK1/e8gMtZh1dW7I+8+LqMl0ha7J3bDTh6sjeDpuYb2xdmI3FNDdCpKxXGtCE/A
sUae1yFXShIQ66omr3XEplLy+VMKgPu/+1SPBG9PNQskJ2HN4cDZtjSOhuJdEqI9kIpAfncM6m/8
YkSxvyf0QNXKNDPZeIjksTifvaVDgC913kaJthg/x31g001OBRdyzVs4V2htCL+YxZT0sOqrV34l
qdusM8AY1YmaRabN7fjOSXPVIKNaPCu0IBkzoB6XBzPBTLnAU+W1DacYT/IhABhDFDjTzJQJalYX
vL0XedmaeyxExbVhsFm+HdgaG2+9CulsK9ghcL6ljelwoIjZCt5rekB2bUuf7gE9XFWlbc2m2rj/
qhoHy0XO9Lq856n93m2WuUXJ6kzUorWsk3g+zjImpoI9Jx2Zxx5MtJ4fZ58QAMlks5b89FfkASD3
NZkWAe7DzTUTVcW8mpKqHPGCWHLoiCyfeWdpaPg+nXdSYnh20ynzJpP9dgy81mK6k4O0CulBiJ/y
UYqo/wPNkB96HrXelhVqRy9tLRgvtLwooqAsHc0MUWlaAyBYUUvyVuI0z9BiMQvlSvsUrIUSazkT
u7FyR6TIJg+WKloUmm+7uYwcdugxkX/xmv/GmBrUkmPW6BLxYdcWGFqg2YEd88Nl0FSzaXspznrP
f9yQI/vDhbKbTMFBq6W6nNSnmcEKgd7YOMyuaOD9cOCgpJOjk7dEj2xvWISU8HFFYstCLuqPlQ0Y
JhvV7kjTkUouFrr7Qnt9NB0qvMUjJFVqWeHs1f3GydsC2f/Hod+F8o5SJZS9Sr/lrM3OAzQozCGQ
syLBtTqYHCEDAhevdDkjWTz3/yzkXQUKdHB8XDF0bzIliXo8CoIHIrTWVpyxrR/h9IRMoKlZ1z+G
Fwoa5ewzod4asvTOpkugdZLDBNvXjsJ/Y52UBuQXw2lM4FPvqB/k7LGoX2mC72cCXImRYroTEoVm
v+9c/JEWcjNYWwgC0gviMVwLkhzlmWq7duD7qKwU0cEj0zkz0+249SH4+TN9XT7e2a8uKHP3hXSW
RK7/CqmPVEmJVYUGxtiiWxtuCagYVYsFbO9HqwLHf4B0r8ePdXLJpWjlj6EZGgsxqtjyWLG7d8dP
YtpMtviiNj2vfSdSXpS6lbZr76SyvqpgMcNBlb+uRmCPpfMcV+6oKeZFUz2nlefa07rp0Uz8seHB
1csrXaxuTA1/2FV8gVP31JDfeayuxYuR59655g/AKlxxXZU9eTRAdJKSfrtLfRuQq4XHYYOy8mmx
YTfrwgUI5mUFDJWPhhfoMcdyRQb3xYrHpVGWLfdz8Y4+0gK+RHklImSoe+5w8hFZXWISi420bQ3p
+c++IMD1avrbBZAHMaQKpwKebtjyhgdhmpE7OgicOjny18cP2EOoZXhR6NX0ZxhfZGGsynb6TDs+
eK+OxeZImpheyfTYoN2LOnuAMN6mNqzRtNpOY2U1YWmXPNnIFRrFFFk5GJgNBeCF9gZTAdGBDdXw
Aa6VGoy1XylvELJkNy0xC+n93PNoYAVrWlEPBXQifxwOhzRbNnps93fi54+iaGU/+w27KtFFQmBB
19FHXIkUZmQzpA10ruQVvXovmFtCMWr6/86FBOOcMLSbtQH9IzPWnvr0v6tpuQmHzb2uvCyGDf7s
COhURtal4VxWNAHP5oGQ5NVcKDxXvnCeWtyc/sO9dqYIgPHMjDPemZw6vRqIlgT91uUUp71Kd/mf
bFGludrieUwZ97kvZvqCfNyiKFZoSivp/lH+Kiom1/yffJlf4LiHF4crhoOak6B9yP6yAmhuQXHd
x0BxfUeB9xvbp0tD67V08cPo8OjIkop04WsBVFbG33cIGqc9wf0KkCau7W4POgkbAh2ip2kAWh6x
iK9OiO2lWquW/NaDTc7aXpGl48MgdNrhcawZNKlOyKmFqq9rvSUQ5NTS22IcWbVUUUGe4RiJmsNW
c7CINMg76blPcLTK3fxNurOBCcmCN0f07hOxqlXmz6l72adVLJ8wRKLjRg+Hr97KkMvt79TTkDrL
6FrRb+b7OEVZoC64/HFU3v1prwq1l8/T72kUpxUqA658tv4/CDSZIWQs/FBGjLGxXfYQKxt8GZ/P
6Ipx31i2GXDLJSZAFnaLn0EcTPPrchvwUBq9TW4H2ItaDiSTMTY6vnEzrMhVFCfkZ13htfUqFKFh
Rqwnq6UGO68B9mLRUOS3axF6GfiCqYBaFh4PtHitb4ltPhiTkAR4AMf6puwI6oGiggfkixeXavNI
OIXEwism1CaJK3rfJ7s2STezSS2LY4/gmQS1xLFE/g1/3Hq2gSMV0wRT1u2LPp2FaDQFSTrk3Jj+
UnxMESSfrOKQ7UDWUb8n/JQvMIa6DLzIasZ8NaTDzHrYOIrfPLAfLAqxSfpOrpBQNMmTiMe4vdCy
slGTQKhdlq5h4cHDlipKayxicS5Gs1jhgMbCQ2e+1Y+s/jLICa6NG2b4Qmewk4FQVtRwtfR1GveS
niuUzExQrabPGbNHB44s55Qk98yQEhI9TlkU5PeCLELSXnd8FnQ5TslCWQvwIWznbLTpHYgJCTvq
p+lS5A7GCiGiifEC7lPr9900wfYJIN6Aa+bzjAC/FZdUepuglPyubdHdQhMC1O4GjUaTMC9CVbqk
j7gzb7718Dz9qjlJD0WMyao79g8UzsUedHDvlXcm3elftBG0KIEkEuwiuBmvn9m35n95u8KwUZOK
UsdWZAamlgHm85vvFo79B9f4dVPB5mdM7eSnIh2kjH6mx7h9clwQAV/RtlU3rrWByb/ObiigXuRU
9lk3Y592tgznwc6hszP1CscLQkCqjmzjH9gwL/BuzAQE3FM5TZsAWRBa/qrynJPCWIwoBclTRuAl
eqmC829a6X4JHqPr4aB0GlK0GHXry+JhrXZid6u3MosZUhA6Eq2y0oQ1jHsl0zFWnipEwl30KlN7
r1usskn3Od3nuBYr1Iad/u4AwktLYrTDQa0rb2SEC2/4Tkr5/JqnVZ6mM4O5/Hoh5HQLlxzdQCQF
lj5a+MhKTSR8T46/qNrUzQjcfQf+2dV5QuuK7qt3j9nf+893Yk/5tg+sZOoaBZirbzKm5HyWc8Uk
4vgJo7rtNorO5+0qosI7z7vgbRDuWxPGrnKFsd5YTr1fFi6C/tErMHGZgww+txj0EczOZlyAkdWZ
7cvY0HzoxwVl6mbWUmqq1jTjvZ2Z+KyjNYVHSy9Jwm8uudRUd5rq579259upotcUvmGy8whe+7LU
7hlVCR2V3uyyntsLcVx8I0ISn+mTryHfn4Fdd1d4U1VBxkZ9+FXy8bFnbr6hEe30LeJCyGuoWhnw
Q1eSzXH1FPZgj329b/YOAfXEywMdQfIeeTrBHRTRV3CxTzwia4m4pv8Q0SAedNCe5OdEFM4EhEC3
rndmtbWN5DgmCYOksA84WyFkGhBBkD5PLkKnvji1Ue3/GcjP97EKnvtjOeDvyqmsxINa6ekl/BCN
aH0/85yj3fQC15KshuaAd9RpPM7rMisABnf0XRvxQ8PBw+skLJpIIiML+BUDz1qEtWCf5/l0ldQU
pOU2mrjbxmWa5txhrZZyyRDfgb/w4/VAktzLkswCWB91fHzhrruN8cn8CqEcjzx/A3HYGJrwVGHp
eUj+jLi8FOfh3RwQpgtyUUQqhNztn3htjOoveod8UAT3flNsqyo05CS1aPewT5N9EJ2pVLtBJ3gP
/3JlDtwzP0EpQWURR2U6+j6IHWslzL9LOve7+bJosOzEUWSuCW5Rro8IflfwvANAhOtB7xNxqt0G
OqHlDXsJO+ttLjLx+Z96aTtA+Ds/ig1LR8bWadfmTrHEvxZU5IbiPmiifR7BMx3cgxG13YpJ7pP/
NT0ZaS+pDO+w2gJ58E6EuhVuBO2OyygwcHrCbUl15vbx+bUIdTzhmmmhFFbMNS/0khmMtUA1TS9S
RJc8gMy1FsMQymUWKV3MY0cogVDXAKKuV6Qblyk3/Mt6roswzQFYrgo7wEVIa8KssyRd4B5TEHGQ
YtMRa+W2eZS2srVdyr9u+2Uq6/S920JPgEDsFUAqmPUSrUPewq4XzTNjurQoC5ms4WbwqVjB/NjL
Z81rmdkaczk7un5SPJjLoPkES2KpN6Tl3d2zbCtv+88qRPE7IJjtCWRqr+6xPtLqgVTnx3N1eqCA
UHh8RVZmqI9Iz5h8BDCTGH9nakBJazRrArxEBq16BKpLavuT1+E3Q+m4BboN4SC2aS+qCGIXUNHX
NWKokdUpnoGRrORjEpaVeCI6qicYEYuoJlv06mzwmxagjEnOYhxnucQZTUHtHEwGJ3Keb5wFHASS
1cs0BHFjGgKkPBIKS/6c35hzke4AT0V9uwLw53quLHR0brObZ8Hv+9f9bxj/t3fdWwJC128/gx86
3SIBNkNYyanZNMmq5tXXeITeeHdD0CL4rZyZB5Ma13GrETOZwx78io+SY4d9rRkPnfyGjqPEnH8y
mLtGYz0gZZiaLeCvHV1/UdJXBomyB2qlNExTDR86U0m9b4vWezSub/q1XFxmT/Ucc5JZh91+IwE8
6tFy1F5XOarfB1d/kZk0Nr15DX8PzvkHOQ+uPV3dO8M0csGpD/d5Joq0G1ZmizzW2sCGddpxCaKe
4yGVqYbejiIg6/G62vUvREFtXrgAm38WSWhIsv6hG0y2cPhmzwoqGmmIr+PSPlYI2QCUd3RgWuwp
XxX0fFwwX48P+v6extG+Nzo+em45aDm6tDeETd3s+r/4S6uGYbpnwVAVuStvjKcwOJ2RmeoSjKoS
QzEutxpngfRXyeJL0AddUsvxsD4E0C9UFWv9pqSqrarg9DvL4i4moQgFAGmhPosOBtP2nWT7sYTL
jq7OrWPXW9UO8WQ2kYN9L5OtCvEgkIQRBCIVtruO1pCfy59PISFgG9C4wE4lYlYShOYpHUyApRXD
OmcJC7SEW/8olsb0vysBf087skjOJEls7WZz8ITQ2tGbwq2CzYv4aUPQBN6yHz5xQEkP7Xpn4Pk3
jKmGTvgjo9HBMUzjcdEvdZlJyxIaakYjd583e3lsKVjePMFqxSOUp6Kuo7GOUapY+7cdOYhthqtp
3Fgim0Zi+k6dbs4UaSSQssJvtQPNFFRerdkrYrPy+2BJE5YAVFqCKZ5EydrwZB0iVFVVvp6Oovt4
ObJNPB8KATsHl4YsIKO12xcY1wL6O2ux5dFW85dkUORS+uxM0hOoiRVakCLM4SR6hIravHBBEEoX
GblQY40OlvEXpvRTULW2hzoa1QJwhOtCOHbuX9OW2te1+T5b0BvU7Tm4k9JsVvVIyGAmz52MSKje
D/Em0vjTgPlWyV2Cun8q9kr9hIGJdeFy0O2mbQpEFdalRRLBEuuowgQ3z4ex6dpwnLg/pvImojr7
vUxa3M6hVabGU6ij8d0w/aTxveQoLNng1c4TbkUPbV+Z0C8gKAY09AtEElb/gAeETFOOy+8PgqXb
quwJE1IgpKU2r6xMcy+HziEx2+qYycQEt00g0I5GT/y3p4rLL67S3V9zUuM4YbQgbGWqXVJrA1lN
vTqEX53E6hNuI4WupU9Wpl5Uu3Ji50t2rVRSNL6MkIIBSnNF0hJ4t+s4SzIk6eRDrOAZc95l3d/C
yUVCNVm9f1kYzi2yOxz+kT+KqPJe3vHvKWXV2pjSa+sO/DaFlr/+fkyi2eZwNLevkvGPTWJ3RAn6
sKb+yer9Erkg0s+M/qnwQ0xkHIF2uYydIf8BPcErk5zW0KI2QrXHOgFrIwoxEj5RakSbjwDyYZYd
Xy33EKgfk1ALfSOjBEaG88XKtzn41m7AG5NekkquEUdrSku7kD2+gQr0a1IJq9zJ2YXEdZAwE2yq
Pb3bgPYoYmsbAbrzaX4mSNRB77HIycJnhP9/zuhuoBybLlYrewNGJwcJue7+QfiWuNBUFPbm35Il
Ul0hlp6qfuk+lztBHChxLKVeTEzei5hSl1muas/5sAwaBxlVrfI8IYIWWfDbFtBATwUH0/dODr76
v4RrOgJVdK3WoG2/1riTXAt+K8H+W0QL+E5ubT9xsBz3aj1pHlMSPVGbHwLmcFUYaouxNLf/Creq
OmA49z8Vome5zgCweR0zboNkgDAQV+uIYQZEo01asJx2cUmxOjyTCQmpg6yzQps9lVmv/qOd/i2m
OJZcFgMRAxGc415vXl1Kz8rkm1mGodghQW/4gA6cdM+/duGT43I9ij+dxccWwehURq+6MaFfZBid
OmZDQF4u4lBn6E1COGseAVTjOHnrhFezi6Va+nnmCBu1KQUli01dVa3RdMvVHKrtJ4bn4wsocqYJ
C/BHbsb056jc1XwdEwEPz/Rg4auTc9OYq+zk19vMCMzEvdQpIZ7VwSrym/cs6TROdGjP4a1iQoB5
YhzP8B13PNGsWfgX/9juQgRI8mgQMI1vmF0ISxtc6o7tojYLiWouNlkiqOMYuhL7GM48rCaCbaWd
DGa/bHGaynrls27z5+R7ZkAt0QZjb+hGsVZadLYLLbykcUiSaSVoNFjhvoTqCmfEeXHQuiqDOcMS
XXaEV2DVnkIqUjw210M6RwC6CqZG/RkOQgzW8ooBqJ8NWyKlZa70qtSYF0E1wNRK/3ETMsimhFM9
dFiqNz1vznA5bwlvg7jYD9Ir2uEGqnd3rc6cV6P4uoS7/DW6VS81q9NB/fQ4XyqRdsdWfIItLSYt
XMdsS2VKLIvMJqCvtPd2uaQV3RFnzUEh922uQz1wpWaIHCQ0ygxboWYhscs4AOId0+uYRHKnjMvs
oawKaXwNPlzaFq2LHWQy6GAyGYJDyMljUMfisx/esek+mGB6O0ebmwYs6w0fZG/BM1MY7mk65tGJ
QXkc+HON7sInXDPFIzSengtAVTsCb+XVxKtPTGVTsXYwTo6fr4ZAzurzhCjSsoRLYQ4+XEhejWeq
Z5NGudvRkB1uacmxD/C3X7/quqREfAYe6LHC2hsKxu3TM4N/3tOYuK0K7zB3576OCK9bj1j/Tzso
ZUBUcCUsqL44lZneSGLfoz9s2jd9rbicEeAeZuwwG8gdtjEadkqdAW0jifWw852LI96AxVpEMfyY
cbTAg+V5QbWSzdPbMWheMr828ptiSjEkQsHOwbXKQnT+mVUKk4UZkqN8MiRL2Qf3GtT8YAYMBxz8
2JPwqooarxd1YR+ZroIhRtxp+THweUrku0Aqix4gReFXd0FRI1uU17dztGnu34wOtW6ZkFGozsar
4VFMz+/03GXvCpb/BDXMDvjR+6nXO7YuMCKFKi183idpXQ6+OTFRhwDWFqnuVz8vBXM2ZJkcdROp
mSkUKi9fevPRPHd8XcO4QSbIhApjksnx983qcimGNVHZ/YkRwBn4RwKiwa0kPvi6o7cv2juT9UKG
8yqLKjTYfUWcVS2zimUiPgZahuc9OUhagZQhQSV6kcieyjazxKMZjE6Abc5YD5hQU4NnphdJSte7
Dz9CQvc35L7655abnXvjQP7skRMpxUAyMswfcgudHs/Mx5m/tKqv4wqCPcbtf/qEqcLcbya9WIRy
NDFpari/kpBqvj8zFrMobTn9fVtl2cHp1fC5/sXehiCKxW4opXY7sEqdY9hkI5usqJcnkysNhdS3
s+TmBqXQ/nNcAo8Wh4kdR6UnUpZRyc+I60m3mVKE4GkaKW13FT4BEfCs+8PYIR403XKFOu6R9V5h
3zhlx4I3leFxAn/6J+ga3QfHrIARI6S7coXECbv2ShmaIME4Khuo4m6u+IYonZQGzfXPsNCR7ntg
ONEOZod6HCA1IWB3ift7G3lI5m+sZ93wQnhVdm++hLFA+F8eLfIkVER7+knVWb202R2BBErXraSW
X+KDLIuUqFiA1vzmZuQXZech9ErOPMnnKJnsEeboTeXJpxkEshHqVCwmITKCqLDMueCM2pxir8U8
afFzl3mWKzCxNSbVcoO862sxG0kTQTP/76CKPD6idtQ8faWyI/mYeZ0w/X+YEhICHrOX2IR38Qw+
gFe9HCDaMpf54XcAmru6ewQ9cWbumWzA/uqcyz9ArGyFoAIZEZrdaURpLkqwecK5bK0UDtc0ofZm
1U7DV6F+4ljMZJeyTElTQtYJ+4c2J8bOjc6/B3CBPrOPa4E/c/bTx1FC458/IlhxG6tOJPTbjmxb
GLWXUg6/xa46JLHpbvbI4iguBnEEipQShiwJOzmmRJ2y3JdI88p0fe8jMeB5/rTyFeeW0seePSss
DO1rklL1rpUmekFZyCzEbAMkXTYU7JbGrpg1oSAgqIqZbJOoNEnJhBRt+b9FL4byq9XFvxFawbve
Eh0iaUil4WslGegjiR71hh7ZdM+4tDiSE+3EYlHjJ0XfCf+NZUcAyEAk08gAhRVjZgLrGekCE9Bk
QQ3i21t9ihy1p3US3JahuSf4K4r94s2whg8jTjkb9PkvDRUigKKOvCics9rBNoB/HgmGsVlxDHgc
40w8mwKJsrn+WNXoxwLTTPOFWdirwz6Vm880KByZ7i0hHVaDtOWvnCgjkWPa4l9F8pKRDswfVUZP
VQvoPI+Kp/2+Ttktq66fWhQ3R5KWjoZIykbtkioFTscMp4u0HQ2OV2QShsTZeiyFijIlEISU4iEo
NIeLSsUY2w/+e8pVMKdQnYw8TwM3nYYplkqstVK4V0JcZwlqI1NWfyAxNS7qUM1fBGrdziO+x64y
XFv71dqcusKMO0S1DX/cpG3CYHwrDx3yTftkx2Z1iTPHxhPN9Kyn1NFX0Sa9b8lY7eepR4oBVIpe
Lw3GDA36YFK1o4gq0QgvLU/8EOeJHIgxNoqYwhzAQ9eZzPkoFDp29lb05oB2WagPJ3SHv59w9NcO
24h+xPDJk6WwD2kNCALMDbL7VkY+DYlYHkjQt9MkJVQMibTHbJZ5w5nXY86JNlPBzfjbxZ6guwgd
UL7dM4o+qZ6z7WrdBHg+lgu0Cn+XRME7TVpB98p5rM42N+g6ta6Hyy4JkHCbVl4YJg4ELV8AIEt2
TqoTh4R9JjpSydBREpQpkilGk9V1zkOklvN8z/6ou+7TB7R8miUbIULLrCDDP6rTFww68+B+DEGW
+rvZNK/ftbzetPC9+mwF/PfcFXOdZMwfEAMUPZUr7bG8QYs0Lq6CSZilOvpKUnQStRpFm3QNk5x+
G0O4oUcgcwoaDkBpWWUYZFuwfXsMscILA8BvlE4blBw+JPMhqij3V5rS5Nte8K/3q9o+UkJWNVM1
y+B9J87SFccuv0ohV7RdaiVMoAxE/QVAU0fXKKgq4f3i+h2h4aAk1x8ZIO/TqX6Fc6EEeQ8iCjcH
rG+yFhSnNNu/53RGMj+HzpklfunOcK4mSrkiK6BnZvzMG2z/ezsfRIMoDKshPM5E0Pq1GNJB+kdA
Pym3nFAJNPFXI4XWr3puj1zHrhEn4ViEmbnoaz0tCiIWnDskZCIlscrPCsDveDF05AYNkutcIjSU
dx6mrea/GsrvfAyDLRHJnfimcxKIGypR/i5IdEbAjUh/jJSM83ngp/cyf22QDszUp/ti1/qaTrKr
P/+RYqZboad98/HGTEm14zT4cTaJCo0jFRXPbuWuZjf+MQ2Y5ua+YpNc6cWlHLDEdapj3po/J3A0
2SPGlDU/7uEVs6NL9+OI9JDZ+Z8yHtw0zi9LFPxmCEechBW0etMfZhvQIH0rKtgwI00vTFBkzQz7
f0DyZiPdhVi95kJH3mxDGaA0gsRhkHddse4ASYMAc/8pxGwjzjbowU46woICPgOc/vntvQJjwfGV
dJZE1Jg26KSRdGEzm82l9cL7SPajU/hJiDAAkWZspTpBOxoJMPQI7GpYAqQ46VYbdOBPO73eRL+i
lyNGWPRU5jKEVS6f49KSxiGu5sG0tKpuAoh24X0qNT0qGTBOBWmj/x1uSuxoDiAcmniEPDmyvITW
UQ8TIc0rCNJsqrX/M1qdsIW744/yI8q0O+mk94aHxhrKAY/KIiB3KldjVOoi/43eGfHQ4zAUnfa3
RSxtRG5llAG7VTOuuLm98GeU8AkAUyGyHD8yVtBjS69CqjD3htOSgPF2bWnrszebs3MUK4EEDiOk
jdzT9mG3cyWN3wGCpq/62vxuFc3eBMdN/fXffySsihNGowawwl1bpt+F4ORbpvvGhHMgJFwU0mRU
mb1lwMyf2VnlABTzXpaPMUtjFUWNLNKFxNciwaV5Nh4M+LeuavGTZLUJgy8NcyeaDPG5luL6DwfW
8zA/hSZ1FMb7jL/DKrf9y1YW0RXIEyGeWezs6TqcXopa2ncTAuk2ExcSeFtC924sWG1y12/M7bKT
Zt8N42YadeYHgCMUG5aJhuP4QGe7dwI0vrfl3OJuycwGJ3tD/E//6mLgP6yKHjE2IBmtLPz2xznj
8PDxrwJLITs2WfOfM/A1QPl1IxJbRvc7oppLeot4UEStVr8R4HjyIoKAFdKgTc+ysBSQwJTKQvF2
1yL8HyCtlDNm/jUjCJwLZT+IeVd3kSTq/CMHY0cWzC9IAUQVruL1d/dqFLvKTeq4IfQZi5Vsst5k
v8tEReKFM2g252Fo51IKqm4oO02QA/LPuwpw+aHYbUiP4cnLwHott6G23CTo/s3ajwI3PXp41VXD
wO0HBiJ1wr6a7C6snJemUOJyw1FbReVu7PISyfbYAw6bl946uAB0xbSZZ26XvEoAsUew3G+H7Jql
voET0/+LolfuYwB+39istR8lUfzMlsw7SHmK5YQTlgDYORzq2kcoA+Yy4C5p3e5QOpTqrJwQK9CI
bYCRDwEhnCh6yky5djXW7S6JHQinIOM+zMxplJ3yOrET5C1IzRfYn+gOz1qvBinhtrGabC2CIfWM
c3O3Xa+k4khcJdTxVURbDECRzpu93xTuLNlk2+N6wsE63v6lNFoSkZMRVUEQSKSbFUmYqDoFau4H
3MZFORgS180VcbLoFtzsdKGeQpjhfnP0jzdV2FflL1vUG/xRW7YZAQUPijOk8Wm/GrLDQergneH6
MVd/Ct4MohNB/Km9TZfLo+tFi4xK/29qLwAXTbz01VVkyrrOZVNsvJnyeEkkdmVT1TCjOmUHf/ca
fy0Jxl1tj+FwefSOiRNlrvw++kv8IN+5fOZw6ysBcRT4ATuF4tLLjyYABFc7fe2IExmvHVws25LR
CbqtTF6oDd8/qnuESrs9+N3oActQOsZtS5MLd1iSDsBB5j7ccD70M2AdxDiqnHcPAkk0F3y5wGCu
ByClrnKgGd4Rc1OKCZJSh0LbrNKWZ/qIznw5U/0yLV+1S4d2Y6Ld3IPLIeo5vNOoHKQxBvGbZDmd
h6IwUiWylJfTDInBM+NiCuVKxhgo18ThXNPZPBzNXoTloacClCHQh/SmuKN6M8p9QWntUweVJd+B
PqfxaB2wRBvHaNHaXKMdw6Ay1B6HvyWWewdIOJEGJMoLGzKXbSNIi12CX5blGGMlX5LcIw34YV2e
UPln+iGPtYx03KHx0q968zb/9Q8f9gh6ga/kGb8UpSh9HQihlhagiWsT+yS/DF2HfMofFUUIqP28
Hep6oRsjdwP/Dpx9mrpcKWPzSWu0oQHGyYU7P0mpsWNC+H42CdpofXf/RBNsiEHWaISvtCmpRX7h
zBrfIKLQK8Qc+nPL7gt+XJUQmgU53DdnjZaaQ4ZJ1k4h/nlBDfSJfV1GLAJcjH1HIs+eDX3WIEeK
77jR8p7rFEHGuGwAa2U8/Keplk+Utefeu77yYc/ruedVwfD+lAOtvZcd++Zco3Qd5ATvGtgjDcBi
gdt2VGBFSmONVHg0CmwZnCl7T/K9meV2PlK/j+m59sThFodR9vj/3t9oziYj6+KVLTtFkXjPWsP+
kQczTz2rNTpt1GcVcUxCnCFx/n0RsfR48C+Uc+gE2j54VB1aY/hUq3DBuIm96oOo2gv9EoiVMgBm
w5Pkpyu2P1jzCNbN+Ph0pLXTnkejvy4vsDvD43i6NxX/yUWH1rYcjruZEeL5WrwCqDTy4wqXvOnn
H6rXBzDo9hTMdUQlPjaIbhgBxf3nLArz+NXp8qM/guG0OQFpHwmLuZYM41PrIyrrNSN/fijC9ucx
IImlr2MsfZ2lauPLa9rM3erfpV7LHw/Xzv/M1uyDCfUjvoW6DF+tZoIzwLSG/njtgf7oXo+MdazW
5H2KFysoOnukoPwfpkBebPOSVLjDA1oBx6hN4+8ZeP79a+w8PkbF8XwBu9EK4eJ/+OTBUdDe2bsh
xjjc68lzXxTZ7XC1Z/t/HZHucAnB/UKcK8ofmen0V+McHFdt911n9PGEnzWZ8d+QlPFFfV0ciVuk
xkfYrj7K2sJ6ehGDees/aPXcB7PrY93TmVwpRPshh4GGR1aY0XiI0ebsejXVH9SNdu1xU1UGHxb7
hzcq2M90Dt+B1eaHKNLKIebBMkluaEwWFvi8j+/eC2bZKv7aYnmEMPwXdLjIB41uZPF1MMMPhp3T
JJtcpZ5feqmlIq+jfJmZIH0+kbPP2G/4qd1bBbqb0mSc5WzQcmEvGDxwbT4Yc5xNBujNMupCRBuY
bN0JieHyCdElU59bWWK4ql4k4b4xMokEY1r7uF0HHwnaSxGxoQG8MSsx31N6pIo4vmxuKx7vJNpO
ehdcQkoBG8OQKOQwHeiGqC+WeXhO3MUxAzxVsxzzPXxTjtOqGCLN+t9E4cxmvOTJk9bQpY2LhjC9
oJoKClOZYG4JihWv70iOAmBlPdsrPbQr7+PjHePnS4OW7vxNQmCm9wJJidUBJSWBLtjR2dbjLCsL
xMjKc5KJlTUzFvBOc7zGiCBwipBrRnvyVfrcgKXsMpN1wNyDhIn+WeMRsT2Uwblfou2wnXNGh2lh
xByc9p3FsjPSHg1IQoiAacY3f1OPv35vVkKhLQrkPqbmk+0KqWb1E4h5le46RtGAG6/akoNArvSc
9ZCJs8IEtFt5zm2DWw0gSVCSeq90cXWFuux2x61PpIl9g6RhQlliFfhYvWypAhEuH/CRrKSGpTd9
V4ULOyGaUbbuLAxLOpm75ahrAS+TU0H0NPNulcfeb10NY8Md0yXtYMtiffxpXP55Phh7dvhqKJdQ
wiK3oNX3YPvIL+ty8TdhJJ6n5YYnGhGvvtCm4tvMuyeSbEqhpo49oipVx3IYeITBGsB9HiwrL6WU
GqrGIB+5+GPDPAe0HcaE4+kducmOH6wOH36t7BPT6sqDWu5uVYs+RBSlPQ3UFYHB/V9O4Y4KzVRp
N/3P4m5+4zWnpa5ynU0Em7eskMoggP3NIl9Ie5/lWwwn3VL6jO1r+Kfjx+IOcrgDyNIrVa4h1Sow
EIldldpS8HyePe2wI1wVu744QZ/Iq01mcPIW1jxT7wex1T+DSpckwjB6ntTeKdC4KqA3jeJ57PH7
KGlfo3Dg18jeyh/3cndqRe/6KNsRkcQLh1CnVQ26C9TmExkHSf8hI/YgktqBfbHDREbxILac+Up9
QIVfB99td1QI8OKlEhv0oamhVIRmor9Ecm5VinYtcn8nOJcCa9YMoyrv6fMy3ZofRPZV37oIyG43
NgRgaMLRlKs6id4TMvZ770MpYL4XXVn/2lFecGjL0N/UKuLEfaXOqKKwAm1HPiqUWhjqiVyBfsTL
zHIHaEu8zMcvNLO04/8RmRZ5bc/vWw81Ct+Fudl1FEtqKASDBdfxpLc4ZlIo4GgW3b86Q1GI5zXy
v9oq+qwgpMpq2V7Jmy+H9KPoKk/D/MF+psLKNNyPXWBByQg3XD4AfFmU9ucpgEOSA5hW6nWuvw3G
fDMRobGxJa3ZSLBdUWq2/70D7She5kKNn1HTGaCOsDYRGJKCU2Ks7OKvHkdES0wuRQafppFj43mi
ela65/IirWwjnfrOoG2BtSoPzoJu92RSB+yxZQEMXv6X0EbPl73cjUKtVzZoIMEie7IGM6cWlX24
wzRg88Bk+hTBhqyUUPGhtRBJIlbjskxcn5rZr1fEBVbe2bI6+VuVeXi0SNo5H1q0OLPdg5lwVf4T
iYGnJDkyFCbAxjKyVJZhZo00Wx1mz2+hrWGGLbdih9W1yR8rY9BCoZXOkrgYLQxaxikwgUjdtbU0
M+riZslwsU/sWE5NH+jFVr1xjRrN+sbEpHKxP0EIqZqsYsUSIKddlb8LInDdEKEkt+3bgTF5rqdW
KzKSd4uCmw8C6n+D9T77yZhnmu8y88WcPWv4TfsouMC0e76ibmr+4X6G41nn903zq8rhUfvOCsyi
KyoZCq+12xZPhgwgtmi4l14yTML7cs/jMrHUtk+fUlVKNWTkmPjMj9eXjkFy86tiSg2sj7vbpdIn
2SZahmklPY719ubfnz0c5Fq6rSR6QCrVI+VAxEWLXp0WLm5W+yq/5MPrZOZ+0PwCyGFAMhz13apc
qQ27B3d2ikTYee2xEdgMpzlETJ6wtg+/EYPwQwaOuADWftIbLB0pr/HVdb3ksJdihbFl22N4ppRM
ygxGoGiI4aItOmmgN+JKhUWqra3+gh9fl40KsLtQwMndzlRoUgQ12n3Itt3bbKpz3cba+savT603
9A0PPRQzWivhaBOU6i+tqtIcMvwg3kAsPcVA+3PD3Wuk9QaUGrboJLaN/9ttDzABMjQZndGSLJl/
F0ueHZXV8tXchTf8zIk6NBa5OCdj0wwXpSNCzg1kkIabzsLtmmkbUkM6ej6mB9IWSmiZqqkaE/5H
yvO5uMhbOupuZrmrp73HSca3IhYah+UArHEWwTM7l8Q1DNW9q3Dg5AxQRMZyAv+mw0InvmdYT/NA
vY2Bbxapg51YVZrbLG8sm+pyZJEj6rEn0ajC72v/GqBa5N7mkDO9TB1af5nRH8CvcfA1m2/Q1l0j
7JtTsNoMSAFrOM41STrvSyaUeJXhbAc7eG/3sgopTrIjRpdRr1L0+5UUKtkfNUCgEuYbhcVOqH/Q
Zs5R5ac62aOhvqN4SWq/duqEThSjhepSITHTRW7g2Z6f9PmJZu2lRDH4ZtPdOEQEwdmwoxt0FirI
H4/ZyaX0Of+3OLdKRmt34jAmAxjt6f9l0F+80mRn6Znn97fb5WKpH+IUk6fA1aFdjNO8Lih6jDCe
8YINPTm1cVCaY/0xn07s+H4DQIr69PqW+tYqzawRI+dV8oseZ7TeKgx8ONUPjv17zURGoCcDtK3T
QWFLnE/zo6hP0Yft5nA+xX+WAVTTBo4iTr29JT2gE6cPYqWJ/MzX6L8cPKEeYCt01uUE/JMXYrSz
6pORNqJEWJWt3iDI7TCLZJzX30bCQEcEHiCwVzrVIJnq8UWLH2+U/lbaHYQ4YGf2WIVp0i7Q9Qoc
QublUzGNfXd84Mf7cwt3Xd0mwRn9xajv/qMnZ85sDXOguNRoo/SutTzOyma7DimKxALZQURWrM9Q
BO5XqvrfPhzDs10wkugJ2u3kAhrCRxDP9KLlcyIqwoCVuJsyU8qPLMSHjm3yUr7s3siv7upzeVpr
F8LwiQbB9N5u8JhOwFZEKrAqlk8LjcdbvpIq25xT1dP40NtPqCeW39H0QiZBCzO+uoZZ4vLhBP36
DO0E+vgQ6ysLm8MeA+/B7qgSRbWXfujvd8QSR/+d63+WCuwII16DgvF6VAzAmRX/MPD4is7XiYIJ
+JSgq5aXJVhphUlpbU88LyuKE3R6gRG3B4JA1EaizwbrOPPfjnapQTyAg25tAYIE277sUctUo5hr
Pfnd0EbuMj4YxfVs66BWiV1F8wuH5kdNm81kupHdTxRlx+WdSjQon2mjP6/qzSfVT+7wUa5q4pMs
qM81LxpqSVHPsXbvm6mKgXa4KixEINPaRmQoEtYCnu9kWqKoLKp158EwYh2t/StVyRi+uoTFM5zk
wchWnBd8O8jybOUffoEHyV+3LbVlZ6KYI3M8vJWfclndgU4/vJfidvf84u7tJzvRVCnxWebAuv6M
dLsZRXo50LrrbobHvtLcAX+aLWXuh/Hoy0wxG9nxsUI1RpCoMnuX4L97oIbFUqh6j34kTfzc/5M9
gbuBcA4mh0ygkuXElZCNdBZRyt9yYOJS8W0Lk9LPiWD8VjtNMaaoNoux9v4NJ+zzsM8XPKbDIH3l
O6smW5G60+JTJklLAWKgRq5Yiut3KJBAxAVWW/v9Fz03ZF0Y83WEh9QuozFkxMr8MwI6T0t3YvwY
c1Ldyrw2M7/NbxM/V2Qc1Qm0QE9kniYyQ54CDi4MyI9LTzCfLPuFXnxE1FCZyh4bIvKGeM6i7S6K
lML30YVUi6OsKvn5cKtGU9LRkLmbikYjPWvLk6laUikvopnyRj3EYxMCzHLccrplzTCiZCgot+V6
/+3LC3lHT5LD8zSa5ZTxIp2k5+p3kvEpIsScUMrrR2oaWtr+t47BsZBv2xOD1DdyFpMLZy5of9G0
0O6diR1M8NFJax8unCd15/8e9732pQvgibwWchxwB0aNVWUWzDNKr/ruueJ/sz5jpXFKO7rCTPdl
wGR1sJf/mscukmse2dbzAFDV9z8J07MLF/pv4DQssDEqFFskF7LOaUKfJTyuovG7KlRnPDg1pfTW
gu+FAxI8e4SRAZix8Uzb8xBrouv2UszrG7HuInfqTQw5wF/bL+g8lmnPz1Pj6LDXNR22R/2zPcIf
fuOReavAl+MB4hW7t7NkojYMoJUhpqEnaktr/QSjMYyfOYTzjXMmxCjaLLwHao3vZ5v4ZzlVSba4
sT55MvLfei6F/ka3s5RuDA5yiZ7pvuSVb3/k5Avckslxd4qy9ykM/RbX+m90z1d2o0eZFnYaaoFk
iCYZTEDWyHPvQkXjrffcyq8rGvaWbQr4tZqHIuUldwSm0QM9v3c5eHM35U7a7oij/XK1c7T9crds
bXlJaWyuoSu0IIdPbexgmYsW4rLL+EWtBLBHnpczd1JzKLXmMrrmDtzsV3r62f1OaeCnBlcdMt+F
vviyu7+0oVXd9WTENBs65orI13D+37TvsGMeO1TQ2fnVPchr2wzHXT5/14vQvdMxe4dAxElKvvr1
ry8msye1NJjQ4vL9n2KFHZyOhWV53ITrGcyDEjWsFgmx4glD9p4/hlSSmMgNLxD4gu7APks6NYgz
JndDV9qqbQH2kZJ79iiu1CQV8jRLYtONYKWUcoC4E8M8TlKTprhSZC2y3FXVRAnbpFPtKKzx31ai
qANB8zdIMwzFA32qtAflX4rObrIqMQlAGy2Klvv9bocNjXZATNmPoMup2FaC1jEdAmLo1Z0wP8ss
9MLs+8tabWWYMQxonvS7RWwCw9NYEJasrP2UeaU5x0vJtbhY6+BLSWPvKf10ceLXyl2Nlo9j5fmP
MkzU9JffaRzUtb4TMNJ0sBKpMrk0KU0yl0uReHYkhyuFXHZX+4fT3VDtxRb2Ha4aCM+9L5V1e/v2
evg+MPE7A8VDMOz3r4h9N3FYMJJjYlK5zc+mKucMvjj2Qlu7toHvkd6WR9jUoROdQQXN233/JAW7
dHcY+Km+5ENRREpJlTC4pt8mBg1d6mfooKGDNnaVjQ2ZOjzU3S7l0uZHiHh+S8sL8o8lnqVybgxy
8uxcb8M4M6CwpK5Fz5Q8V5JHk8zjnkQ/LJLAGMEXpE+BvSM8/BVpEYXFBDxnZFfjG7eUJ8lnAvnR
OtMTQsw0p6I+FhZFo7o1dLL0VH+5mGh2ITEQ6AJ4v4XaZo2E2WNmNDWR1nsfPxzwH/cxg2lUQy1z
CiUU0E1gmRshaiOz5vmOW5MQflA8swIr7CjpLEaWFIiBywXPCw6u6aeL39u8O/7962CMe8G6usn1
VKeFLH0vTzR1aiG65q1OWy+qbR0YIaYGtiiFG5O2KNgoXDAQZ2DqMOUwvQj7vcOXoMh/mKgJNNHe
vOMG2OK0ge4KMqeGBd2lQE1YH3YN1z1tO71+kh4JxhgLG8tyiyu44OlGwCgEyhpQGpkV3wcb0IbS
oZnPfgWFhX0H84FOtLhT4NTJuhsrDwg33VmvB6zVcaJ/CE/srgeo2EwZcMjQSHr3uDmecUnF57pH
8KGUjUhct9V4dT3OL4I5DYF5LDhyhnNHhx3blLq+7CfonzOa6PSi1mD5jbyE8gWZqUUvZTN856M+
Us57Ry3KHcHo3wD01QAIyqUvj6fC0y++W7HvQvUuXo+DLP/9C144aHSGfvc3ROM/+xprkohmbPaW
K0lr0GlKO62KDjczewlwKj/yKkybdgFR7TEhzZvmjhdDEOChHw7ISSSCOim3UB1FxP8+0adgRxB+
7omnYDwHaO7N2AgYvhB5XWPCIWxyxAQmubRwL12OfrvXIv5j5LOZnbrTkfuZFVl7C3DD8WjD4APJ
RUXcwT51N0lI0c9Jf5MMUQ/92Oj1EpBbopcaRhyo1/m4812v7tQKVfwAKDErqRnrco91ZOwsW7zy
de3yhr6W4AQpojcNPhQTWccp6kyjceLpVl6XSQjwXPc46/1JZwZc2P0l6Q3EXYDidmfYDKKI5WBP
LgeQsoTNoXvnkEhNW4pDTRYR/EG/fAKJNed2bLUI+YWm47KKy5dt9OQ/+C9aVZhU8eytzbI2oxnM
kUc6nKzvR+1kbuaBJxknaSjeWf93R4zlAkNdX6x6hyeTGGx9tklR26InPKKvwPdnVkMxvasmRYQF
+Agm4NEeuYi7Isqel66o8QG5GfnyVh7r1oLhkWncJxh5W1T+EXsJW4DlK4pWjobo+b8h5V4qbHbO
Wi75ik6ysBlGMiqnCjrMr5XsikfjWDZUlh1/6mp6jfF29PK54cUbqP3K8JV+8zoxwX5vPhri1RfF
XJ4vPB/4oslSyzD69eOjI4+pgmOl683ecSgV1l5YHnuupypMdEAMjHkNshk5QO/Sgwq+aQQ6zRdB
RTymzzq5Mz41LZPLifAsoU4UUwBztGlrseWiFXey9pmFAOYwYRUz39PgAg+LXeL4+U7Q7LjbS0e4
FdjdQaMckeDYYKUaqs1wIr2MmSxCSNqluCt8ud+uOGoR3xEJVpyyv9uZ8Bj/WEWhd+HiER9P/rpa
alBW7HVbf4XnMC8TTAwIdq825iDtPFtPP6fblaiCjBaEtOfvdGnsxTQUtvKg4p3P5J0ESWvwEnIs
0TWxzXol1TI60PJSpY2cB9s6w2TFBdBFG1e2Gr/SmiR7JIREVh2JXz+VnN0eNrM8LpEh2p2VioAX
wEcCniiWxJnLPf2JM8BKRkpQL8Jpm3PhDHt/M/X7sc+GC0HVsWtaM7LAvIq/KyLtsQH2ywLkRDvv
w+bhqe2FlIwfJWDR1klzOYy5RBzHDzgSuoET1SytXBmI4ZK72RzmxwEyXMa4m1dZafn14kqdnaCR
zlmNOjJcik0mI8CIfxLID9zaWAMdBTloBdfyrjLC0D5y0BGJ/BleLoLdwHP+VMDBxSul6/loWoRE
WuW77BAIAuxuSCuBksSxHSIUABrhN1WpwQ1OG0SjHugBAVOx/FDGKCRhkqUjPPB9rylDgm22lP3o
gQRC1TjQRfZaahjhXYsoFZ6XJmWmJiEBlwSBil1Ne+aDvZyzxjehd7GUZDTnTMB4noxpJhNzo7GS
TKzKssDPQSlEauivA+rp6ySzyV5nKwZOUONoiDyYN0Zq1YUUqSRWyomt4xi9gq1O7rFhz8/wBkfh
9GNvSjLmxsnX4Ua58yg+Oj+J1o1ielpRk2uLb/Uc40qQlhG5X0WgsdQy9+OXGXD4rLbW9P9FTEFu
Rf1u077Ba2SSjJ22j1rqH8tH+ue98Oni2YVQenQc48kQ98VwpJaSu2naA7SkJLdkFxAlgISljSrb
NE3sobleNol2JCZWd0KDAnT6wbSlBQyNwRRbimy1j8IvqgaddqM7seZrGBJXJvHwIqZkEi9Q0Bh2
ESV/FRTaUg/kzaHCSKwZzvzH5A+uOPqSzN9qC35t+h3ZwgbkNjG2mGowCdx7RvV2/XSDqhuFdRVs
ewpTVW+Aw9cWl2bych8Zcs2WCbiIflG0Lfj0yhpoMcHKhwr+5sm2pOiliRfrrNhwKRIAYyamksk1
Dvvm5DVFg3FP8DNN8U9K3xYKZg4v9+wkwsPxdQu6rtys1/UEmNbLDVrxTP+uVtrcF6a3aGENatZL
gxUYj/XpmC/AVYEgmrOzd7SxUXJf/Nucj+XJtQf8iEKmIXDDegdCrfRUOxFh+gfKmX7EmFSmLVJC
bMK4wA5wa8su5QfkwBNxolPSLaaLHiJFBpX69VjBkspkGyDsUnBXJoT5RovOMSzX56KybPcfHD5l
zOewqj0laQk9FtJ31HOmsWHjRb7k+1HEBlwpPaBT9+f/qabVT0ksTM/iAj28lUVBGsxgwQaVX5YN
ml6HchxtD1yapyKv3IYgLNQibCzsekaiAdp2r3e6FlqO1aS4XIlCGNxYaByEsA4suraqIrL7fo/1
QUxKVN76ftHDJ/ZR1GAeJ6fuh53ty5JpAR2/iC957m3MVBdiDDStBU2GEvSAeXNgHw547soXDLvk
8E19DdasbFKxtqp0hPxe1cAWUWinY838lTJ4dnA6/y8uQVCUUyaUruPM1eESGNkfh7uKGyEuihdZ
Hmx88E2yqFmssru3VMrcOgsHm/9fqHqhJHJzxJgQYXho1g4Ywr0Wk9sD6pUX9IeYxykyn8bcuGN5
4NXm4Whrg0r0xzU3K/rUbgocINgwyLx/IZUJ/GWJZ2CwXaQT+lc7p8fR/JdfLSm1/jbFOibnOno8
+LkTlyXlMeiuBtqIXbbXgpwWwZO9okNzO1Db+sacpPLSq0ODPImUHEZ7ASgmBILDdEud0OvogNiA
JaPMQc8fIpwXUY5ZLuZAyp7/srOgb+eGxKdF3B5NHjcObU7NK7eHXAzLwf8DjHwIOOedcaYWEAIi
tutu9eJ3mUxsUZm0yElrKc9bKv7RVpwcam9R6G2eHGLiQBINGPB2r6cM9s2Pj+ekYWT9zHR+zcNO
2yZLPXv99vmarGsvLG+9Pvf/U+O8R4+WWlGXfpWnqql6xbfKk7tyKO1FaEvijFuuejRhYico28Nr
qG28yIwke/3lNajIV9swcR1iFo8mevnzFnkTlDQGCuQI1J8oJwvDobZsu/SsdUaApgnvYgj8dAXJ
mRpXx/aPv6zDx0aDkt1tlivAq9WYi9Kz2b4oRaC4sBGIiHYKJwbpT7Nc7W0lmYxf9UDiS21RlTC2
0V2rxy2xe2K+wGIVhmvUR4xFVAfcYWBflN7v3ODL2DljhYFwdSGnQMXaGFNH4w5Jc8swee6/S6NW
XAFugeXMmRxTqMfzJ4xsCXcImTzRD+Hofn0+2r17iMCAsSpESnbn7YDAhukA7hFWo5irGCJdzrtB
yM+vApiT8dKc0FMjrD33xf6hNPkxXpmZNwoj2AaW3BMuXqKhcGUVHnQvGh+p5VJyTKFIsUwBzyOw
mTL5X7IagVTkii6dnWh87+32SrIkLBXiNYxdWEhH5G/E8TXWBcB3+Y8YDhUNAWBj7OIdHPxisV5E
vqMt1epdO44f0I5tVMOdd9sKotX8I1Ifp7QoNptpqWUCU1SIzzgp0cfW52zwDbMjEP8i1Lgawxbm
b1DAeAE0q3B8hPXWAJNBtEKEi8icOHITC9bWM6fL7rPiguOgzYjVjr33dpcz4iRrEE81d0FTtsSh
2n/p+Z0yB9xVm7Y4cr9/Ld0OFhtfglTmtiGrW+PGlYbUzxRGT9QZwbI5D3kOj8QuN0zU8ZpYk1+F
T1IXD0UlmT0Bpn7ugTvfY3X9IsEYYgvVS/x5XFbWbaOyiSrl3bKaaol6tNsYKeXE25BygkYfSzL0
7UZorkN00/+H2PxTo2v08ig7D2iSvN/vdCcH+MYQUtQ4s/h2rQHo7bsbm0S814ohwR1Zlcvsy61V
nY+JTz1QRKB07j5JDnjFzWnAYZIvQ/lbr1YskrFMkDm9VdlqJe0QAgwTQJGqXyIIt9DA3ChRIsRz
lHg1kijsDl2B3uVw7RMC3vyYffXnOjQszcuGX4jC1iK9mn8KtlzGAlz+U1SWB1njHw6vB/hM1iW5
fu75cniaDDGHmYjZdbH587BgNe9MK0P+e5r94EcpKgq9bUKrgpHS13zMnKCArem2iFbpeOO1uZ2/
CO9XsGqQJVmkJFO4TDGAfVnryWKVxu0NUnXC7/fKa2Z4FQoB90m1oelPhVlBUnVHpgruJy0I8916
8Vu5/gQlc7HuXSvLsjkpKoWzVjgyXpr+O1WoVnEae8E2NNE2cGJ2DldEicP0ZecGeJzwYWRaOAqp
MODke13yPL03UkHvj673veeBwewmpWwb6u/YVTZhLtgQP0Gvz1HVna8c6TxAl8U3mnCC+utkqZJc
01CAL2nRF6oiuuDBFXj3qYoJ2qXTbPVQOGwrawEqCZpm5crLfwD4emrTZz6qlxWteQ/TptO/5FVH
nkLLYty4BCXy88x90Zl54wdrNJN7a6Gy8iklUy6qet8PhQ3chANEIKMCMal8wG1SePkeBKvq0IO+
cRYcKDCfi++GQO5Z2WDyFQSyhzmzA/t4Yfjq18NxpVgHeAkRkP/THDKGbxv84nqnm5lctWwTdJYg
GNYmVdtFPXckmBT8/YwufPzS5jkIRE45+kzOcvrk7a4OTRVi8/DUJQE+PqBe8VfrIQxWjGLmCrPC
6Xz0inLpisBwcQqqN0ZIR+POaK8Lya6woedxw6uA5ipJn7ZuvHVm9qOYTd1kAX0ty/0arxkA/2R+
p/zySHaC7CTd7wci29meYQKrotUyADVjC7AoFnTlxuuMV5PYRTYOobVIhGhuB7qPTHTc2VwpR4+m
C/NN/Uk5Ro/9RTOhvJMhHJcMfX+1XvyXmC36tgpnYYQsE9mMkPa/qTVequRUnR3iNkWNHJuocLSf
uxniaO8ML6nySjdc4qOSG2OZS/TzQz6+x4hsUCcNcSnwZYbTV2Eg/FXRdAZAFKkDzd3ffP6YrmkB
qcFHxSKI9BkT5sdgKra75kc6eS8yUHazwbWV3kJU5uyOZpCmR5RFYF17oBREZs58CB8spcrMvMxS
R/Fvwyhz5HzdGQSnZ7Ren8fEOGSRyLtbgDGTxHJTJSvJl9wofdpVkVv9EpiHpwnPUbm0n7X60TyV
YYMGJkkUlUlz5Q+yS9HJIBg9fFJuVLTPF9kPolphzFOjSJ+wXnA6yM87vw+evyRAL5mVdzmCSOtp
MgcyNqpNC7AZIN/H88QiZEc/2eM7yZfZdeqMC1R4ie7J9TD7NiBUAl6SF67Pzjo7I0AhqUs25dit
UOy+EebSCMpuFepPJQyRPiyZ1G474ytRYtNq36q38vUuQsvhf9+ZyXcY/sD8cebfn9EWcBeD10m4
5Ixt0ULwoQSD7Ydzu7tRyfPBmeOz2mWm0Gx0CVbZo8gIoW3g6AzdEIxgvP66pZ4euW2g/okZIuFI
Uo3Kxp+Ebw1J732deQdPSxNbdvyijqUe1LuNZaIjiEhWUoMsaKabDWNyHuj5U4WV9KPfG5Xrtx96
0Int8ffesxQNqrwY9te2/+v1d15wJqvlbVlJ67Hq5yYGG0V+n3YQwdDPoa68SmJcHAlyIKuegew7
NvJwLqZCZ2CPNTtz6Izvb2OsUM42p9vnIZSkde67aFlj/nqHs+vdwGUuYGQG4GDzePVuIb3Pakrp
Rlz9eGh24XkpjsG3kxFrnnv+UvemDwZEJ33du/DKfzvs3tqzZjIPeAj5HnoEDTmmE5+hAXAjxyIL
7T2emOwtmrZxPaFdHBh23N2/jK3dFqmMayGDWN26vYWKkPGsn7oezDA6S4Q7eeOXF4kqoVq0pXfL
QU5Adusq3EwM6YDDksnvR1rlWI1dNCKbwqPj3SV4H86c3699TNUnf8GkNir92ZtUq/f6GF9lMEh/
Ns+KdE+Ebgc5aV0e6pPq2MA4CBw56BUg+uQTdideYyNtodlX88dR7TFLywa+KaLL87KyNW/fWBeu
uVW2WD+qkdkhZja6FPWnLtJ43grkC05/NOlr1QEFny2Rm+tn/SmJ06yJs1uBXHG8wevaLaK4iUIa
YCYrq2FWeCo7rp1l2zYwr//4djIkj3z1XXYLI80To5D7oK31waRAbBSERwwvIwxgm08z/RP3FGNa
iwe5J8ekwxbk/34pI3mSa+3ahwakGUiR6h4X3FMhPQd85ygRi9OkiAfoTIgb7nowH3pK9SeuaqXu
S1fcKZxzP3P5DKuCAkuYGIhRNpGKTGFLLD7GjgB7KpxqyAxHZQymAe/ABjDeN9UCfdBydI+dF4BN
cQ9XwwTZJ99EyjfH5BtwEzTokPIFsDCJb/krnqGE/TatH7NlxJOFuMvd6GQkzAWPippMXYAq9BeS
3GIedrMPE5fXwmi6WRlg/GjlZcnE/dyzpfkbT4O1GPYQvTWBBCmyTOVoS5ZkNa9HD/fosyoPUAJC
Cr/rDukFIVfBqNM27TpuptGQK4czsUHoG6eQMZPKp32H0Qg81AAobGUM13v3MkF1ngT+gwFq0RJw
7NkTR2ZjHPZ1FrH4dLr0dG3Z5jxxwwIvro5WB7ef1Ji97E/V99FDXj6hr8SH44fIcW3k3DTH+X6g
I/Y4fSrO+Kj6whXVwGGGodcYCFru3DK9K/iUnQHmaUqDDNqfysil7gdtEbBWYpx5b3RVAZbelzD1
tpE76BDnrjqnICXwCZf8U5/quj3ZULUlgI2LgKkN+dYOgWqSAGx+LTDMAhxWxBEIdnb6dKIp0rfN
Gp2NNgjA8d3GaWvieC951qLblT+AN9cAALL0Dzd0oxILqoiVc99kKy/elOBUWvMnUeJ3ERKA7X7l
eDxkKpgYUyw12shfsJH0idqmCtxTFIY5gsccwmSotyHb4Wj70WOPlbtwIZ7WdVoaWSC4DrwL5oNt
EWP0CkurqFlLvmnDHSy8XBvHnuwBXgQyJZMKWg0udB/RyepMA3538oS7YgptVpWbFD+huNXKMEcx
zFxYLZGQTKfRGFGBeTmLcf1CyQYsD2RPA1swqBjafv5aKb5rUgsEfr8NIMvHysrFY4JDrQ/W8Unj
7tjD2xUOoP6ICSKNHhGtideO5uv1A6SeQB3xG0xKvTPwxq8JHHxL9yn57kXla3ZPn/Qqe1xBLM9m
uKq4VB2y4EHIxTKmOviz40kjkh7hVI0OlJuuWP9UR3g0JqcHGLPcqLB9q2kF8k/ZYFFibXn+Q23a
A+EbN/zi/9RYUwKVzEQcb/uWA1cEzEy9BcS+lonqWm2JoLaqMFG5Gt0q2jIei7yPkmsg/q9bTBRI
urqN8veC4+rxqOxQVhVReA1iETDAq+CiSA8NOmupFOzah9sAXLaqb73BUdS7G93wtCEChvkTWNdI
Z3jYUcRoA4h82eygCD3Ysj76zQiZtaOYDSv+tMcYIyOBmeGb3FLJtA4Mvncw6BcPFL6qrCHC1+LP
70z9qV+2HFxFf5zFsbrZNAHxTX7/JeyjMyPykA8txhqkiujeBErUsGPBJbKEhofdTCMw8k3pWuem
HhKlirNjFpirA13ce9mUWa+E/zncj/VRkdNMDH1/WgPmZdr3bsGeXTi4cxTRHgbLMgqa7ssdUPkF
d3Rn6nssSysfJoB6FN403gKDNL38/8Beic5CviEF2gvDxQOvK5cdEgZy3CiD+fts0oMeMeBGagRh
CLrg27PP7lXCZ1QSEhGy1oQQm1s5i3Aa6RU+Ij9xmutxjd0gxUVBuBt4Xn/doKfe9PnqmD703KLd
8aoxBRnSIQlf2iOsTAjTEHscUGAtNtSUeO59g6bHxyJ5/oK3qSCujELK6Q66ZW0BQIpQmpLV6Kzr
HAjH4fTGkoRMjK58IVa2EJlG5F8WLu7LevKOLoO3CMN8xdOWVYZ1GkwLalIDH1XRjxGMwqkxJGF5
mszsR/weAh1Fgr6Av8vfw+2p5/2FuXhvNgq8Pu4A5ijrap6JB9xHbSNk6N9tqJXM4CSRoHZ9qJX6
B+HYYoe4HabFImDkg6Yc0UX0C5In6YK8LPyE1+lHNEN9/sq41idrJh/s1JQewGGQG+sy09moZeNI
42B3AYOVrtmc1frUFcbEKyAbbj2fxtamzs8rk/jcYZljtb41Fzp8u4keucXWRWWsnKH8fOSbWPYX
lT6AoEDI7utLpPAPpixo8mByxVd+9Kz2qmo2240S83yy5mFte3w4JsQp42EuxQGziV/ZCT8C8UCw
YbkN7lUjJGWIl+Dy3TVttYsBRPYgLZ4GE0y34kcZKDys3vsVoCiOfas7jK9TyZX6H+G4gFTyssKT
0X/Q3VKJhNumPERIoj7OqX05kyKgmvvoae9QfncvvdNWZzTA+WFXY+kGjApGiljxfNYeZjAv9Wk3
pr7YwbJXJJNBmORti9hRWgdk5jVqtipE84VitCcCYjavZrXPyPCQnR5D0wVXv3AyZCY7QIoD4FYc
H8amdpKmPn2ErRCxrQvJ+FgOgBmXG9vh874iEIkIzx9etbN8vIj7z1yHJyU5MHzjmY5Ttwxa4F3q
G2rPDhYDFg+AoKt0V9chr9H8+LByadkBWe1b5UhLLj8C5LqjdmcoFE3ED0UMTlJJoBwmOMwJbjsP
L6WY8SEcFSNCZuQYxCLseVtVRrRiYF9LaZouCnWQzFC1wrT5vETT/HGCYZjqqkZ/0HTFO8Fdkmt7
JVdKQuxD5vh0DGLOqDe6IvRS+ymwGYedq252eAjJqSFK91e3EE3mWyIVK+8AD/Kt+cfCkj59QRl3
i28QNacByNqOBqZ2vURsWGMzZx+c89TBPdqdlzlbTieCnBlhBbVXVZVBsbk6f9Jf0IhLhjwtb8xH
Yx5J4HGzOoozuJJcF1q1OM8m2RTzepx+TEeZy8ghGnd8+xol0LljAqYpLXb/ujB+8te40xGsdtBd
aSYTioqq2UipZbMdK84+5y/hXJUClG1/Dk0eQh74ki9rxflwcicnpPWPVlEUJ821S/hbp1lFk7vs
UxENP3tRYbbwHkQ5JO1deIMYv9YRTZLwTQ4eu07sDZCmhBqeDZg+ieYoLvnRtCXT1hWSKXCc8LkI
X84lGPlhNiesRF1qL9Eg1hWeUBsiUHyMY1+gNe0EljNRdLSelDTwBnoqAoum9Z91xGJv4nLSTEUc
XtjocwNv5+vx6LC+SIojbOdJqdjEyj8tivXz3aD5BAH4Wp8NNMNQeVTBOX08TRRuRHgQx270myAB
1zNJB6TtpQ8dTLSl+CWI1CFAK0z7qam1uHP+j52+drNHrTy7UQLXZFXAML0d7AzEv14G5mhUqBN1
cnZElVJy17XyemJ3IpLIgxB5pem5Ot/grOzdkjOZPQiONYjG+ucp+l1Xhf5NPgxaelrPTON2ggdS
HZSfIG3dS4UwQURFpeq9TOkojDUjsYoORWz/+DoOyOZDKaeWetOOJ2pIQLhoA41dSGOa5czvJdPv
3h0EbTVB37c4k47jwkzKd7cYlmvBJYWhwz97jY/6mCKzZYEqWAc3RT3fc65BjiQvWstICHYvLu4v
pVmZNSLr9muNrYKzop7ITn7A3SRn/vNdD5untX8HGUeA9LcYgZf2m550zQHw5vKdRtbKajigRuVM
5x7h8EAsokgWld5FJrgNeArHXncWxNvJToFI8TV8aPF+SUKjPq5+7mUGASquCqHQ/dQ8o4etzW/Y
OvmL9jO2tdISaOPUiQTwSA1ykfvvwvs+ksBc1WuRSDV0C2IsiwKFHZ/uehTgh9XxueTOvLCBsIMa
IY8imdG9+xX8Z8vEmeAIXwrMbPWdaRQgmkfA6JVxyJ2uTuzPKnHZEDgJSryiyqJS+umbhPgveSw4
o+oszBwKEqVeusQVvH74BtEBVCmRkidS/0yblIE7a3dFZiUSwmGq1V/I/5jB4ESS2cbSuZbnBrgk
tL9hj+Gh1DscYi9DhcEpua+kRTRiPBz50WJHrrwdJkbODh79vcs/VpUdW0ih2aiq6rtAKCLpcn5y
fLmX+axc42dDDmj6SNoBjyvhQLOiUzHq0yjhG/KF5K3ATWVsxpNXODc+kcmPv/8J8D/ZdboQcJpX
7YrB766q0wAKMG8OcpyhQ2qLoe4yRwKKDsdhRpG5M26zz63uKtS1zi+Bmyr8XvlMK4+7ltpBDgPN
RCU39NkR3eIKaWgYCndtipgaiRV6SjyPc/3uFKpVHqsGvXOw23IOsDUGLFwlI6gX1IGTYHZ+uJjD
Cy3Z1DQRvfERiKHwzYWlmBcYO43QqB3lbFTme12D1Z+mvRxdoApbepAWBPbaMAvoH5oKrxvaJ86p
iY1MOOCDZbe1pCg/p9e7oq1p0rZTGrfPHymJbTZyaAddJOHFRFDT+yexZrIJoyTjwgtcFbzSX5DS
Hs/adGXf5CjiwEyb9YRnG2Fqap2/M4ZPFvHOlOYEhdLYKKvBqFbz/pHUUsti40Jjd1wYoc2+zL1o
4HPy7KWV7GLvTlazMWcsEgNS+Sf2Wbk7tuaNPPiEVxIfhDVLYBRyuwVPgs/2nU8dmknhZ+50+v0D
B9x2B6aeQec5v5GyoncLgVIswGt/xzSPQ5GJdB2+Q7GfoXRPJFYCnENVbWNs3zYZb9v6I8nhlcF2
tF4hjUnlPD6OL5r5KONNdrPcnbS0c6g2L/UG8DUK5aBkzAK4+2FEOXCBueuBnZy7glrCboUKAsVW
+2QaIAOr3q/MQcQKTQJiIBvEn1JC921chq3knPc/IFHQgkTdi+vTkTmDk/x15huk9Wu9GNFnz2KR
2nFHg2hTElongjIUSA29vLdE9xA3gtqNlpMf+fKVlNNN7Ohf8onXAX87/LSnY+/66cy2KpDA1M07
mEO4DZY71UGBJgYI8zKxmWOknv9X/A8CqL7ANizIGzVWOjDou5BKOl5hRtw+Fib+BenxNRPbuXij
R/Vi0doiwKY/sRqCVH2rMOrNl6qtrJ32qQZNjD6XQdCbo7c2klCqyChdVMxO1WiKAJwINID6tO79
zJhzIYMEeGzQoJZOkmJ0Qhfeqax14dLS+Nru/wCIQBX+LB2ROTZPKvApJIQPzVl/G5LVQxO+Zncg
oX0xbJpCZP9QiApVkPnZS38w81qxSyabNTqyQXcEz7VcTf4jmiTye4ATJZVb3C+epQhEX9ebJMIk
CCWI6ZdoPS30zeB6FhnvBexfhGT1kW+LVf+EuqYR2qne7s6j5Z8ih0mbDH4iddkHkEKrQpoD1q47
2Gqjl3DY8iS0vcYTnecfvhxi5J/Z9UttNukKde6dLBvWCJBzMq4de9/32fBBMctT2qHUSZBG4uwi
WDNkXrud96v7iy38zYn+0mtRVVjTakK25gMCvSYo0LcOny4P46dBcnWa0dNIf2cBOK2mwScjgyvz
FJLTDQdYDbu39nRSkYsgJVLl3vXlyXyZzrpmUztrOYmgEyNMv9WO97hCWI2Q60N7kpOuvIe6mxX0
oTE4bkWuNmyRVKzQt+0vZwMZX96U7LSR2n3HbJTK5gRjNIqV5b3DyDNUdtKqnlqOQTZ+pDEm1ubD
NDpMIs3fJM3jaUg9b+4WegZZHkZfqkh8UC83oPXxpvouNsUeHEt152UdbhdNK7DK5fTxK447a6O2
8s7BtIIAAWP1h9yms5pgbfIF03cmt0c9bgatt/1sk6dVvRvfbzJ6cUiaoPk4iMrtNSmK+RLjYm05
ner1Il/B5IYqeKmeOtMHIFssUtX3GlbJ7Z2esOALpLWcIbm3BGLv/p4iDTHthDLGezl+7zyUw15e
8v5kiIU1LvlpYvwTSpQT/qi9D/To8ELtK88n96QjgnVc/vuwTJb6J7aL0+m88XMl+V7cueHwANb+
F8USZgVbfoXFovKPAUZWA8O/TIpCgIr34gj77MfUHuYvL/iHQsYomluv742gMyMoTTRKOkHJfkCE
H/KciL4dESMCS4S8gkDlfZPXwher6hgJcTGTejmJ+W+sPJcEjGyYBHM0DvVaGCahr0m0CrevGjBA
wFjEPKrTFIGQWmUFG6psIrSeIqO85HSmyOdm180DSVMWaKDP9CBmiGbzF4Qr1VSLC+6DYwIJiv8Y
WwZG/nYK25i/DYeq8b6XPfaFAIpx++TcsF8PwXyR9X/Vu7wWzMBhj08LbeWA57+Kpt0FFPEH+sWW
vjTOC4d6EWj1cayo+etydTmQukwLppZ7NZiNv//O0YPZNV2sJkPGySpSWLHyq4x5E9Xp8/TTWw4l
WhTcNke+zlt7DIwlASq2Htk37XZjDZq7ww8ef3j3S2VPnRUPw8o2ZpMbfiYtR7lye01TCG8f30O0
ECZ4wlkuvcSuuFFSIB8J9kMG3jR7/qs4YKEmKnlundY4eqTu/s3sJm2axC3rYSxONxwKfnMFQNuu
hVEmgnhXIum5jjshBRShpGgL15SBTZtWDrP/5r1c08zaIiNe1QZheZmKFRxXcn2ep5T4SoH0hVR5
OThmfCRUhHZsfcSA4xHffvZvpQXWrC5gR33yMvaIDrD85eQpm8wKCU4QMiWRVJfjl47PH8SDQkOf
3nj8LlaONmC6rv4hwhksnMHuCpyruTNU7q5br/HT+gzK1r+QvTrxuJ4eOa4KbkSTwbCqb+Ny0Rgm
UeCX+9zRfGwqmtqp/po8lpi/FGbc8WuhMO5uAg5WDsn5M4qwXM7UKMA10GJAY07PADZXeI7SSK8F
QhYg1GeWjZV7Whq2pBKvQDnLBZZtXvOF2xFS7F3mi5u/62tHHBP56eAUJwIWiVSnxh0gsVZB2g89
4apx5yw2Ng6RJqGCLINd7O011NIgh69yLK30Mf2loEMrbEdcMoFly2ePLaa54uDFZotECMa+3kcb
rvMG1HtRKIjhBWmqrmUy8SjZfKhcYDMw5SVHXAfFCxM7lhQBGLJSco1lujjCy4uXN3hpE1aPgtkq
QinlIwV+dOX7EiOrj8i7Y/KxM15lG7S2uLTXiaV6Y6/SaH1HxgDz2jVfOvdp2MOnfGpZH1xHaJEd
Pj77rgqXKO8E+tLZ0DLPk4HF0qN++nhehsSjH1ysnaXz63qJ1LSoKN4uTLaQP1OHDTf5auDZNT9d
VUaIkCcZq+3cJbTxWi5f5OSOOejna5EstoBnQSEUx4x6i9rz0iGmkvTOSfVGMiIuLhTqsfAzBfax
hp02TNxsOB0pnLOshLYaNu93M+UPQHSOA2v2v3lV28EKl3I/jEwbN0jm2raHreNx36dMkmt88tl1
q037QOyfz/KzQYzBJfA8HH9IJisVFYeaGaQsbteyh9DTC0MI3Rm/Sj4STYtCNz4fu4C0ZR3vfwr1
ar7JEsIV/R3tq2qb3Bvlq/9xwYHpR70yMgBMl1J//KRCTsfa9RNXwFT2XPICxVS27WMgAN7gvdef
KfjSe/895s7aonZHCQJcaE7N35cMjWTBUsw/9zH3kbmeSgRG6fbI8ofnH8Nskj3X4k+r0s7PhV3W
J+MNdxhx9VqJnQJvOPAT82MasvgcdxipnixBih//G7vSVIT6AtCtaGMBy/TX7SWG/xA8esupkiOf
g8V8ryu+DHKmK7z0jagtXL1WnhDy/jLQ3acM9aec5KlB/0NcIk8u/ISpPb00i36xHoU7LZ0N5lrm
PMUiy10g3QXvngKpyVHeC2Vk/6nze8cykkcU4cCdkBqaj7YOz5ggSWOuu1tkGQu7H0TC2aCGopBc
yKt/Ayy98Uo2HtLAv4w3KobheEHAxvXQFtSShEcUAOvpNEMdaUpmA0iQvO7fS+TBoBm5tp+hA5IB
9YibKAUvzsrVe9L/XWe6ZWDOO0TqjbrkKGIfmI7bQ4SYitIwaUz0WMjw5upnlTcQRXppARjlxRuY
eF5ZhFV4eomOWEQypFhfzkILvBSnAU4B0aYqWmboNoPRw8PpQihHEps0ZaE8T4XFHEZjDVzqandf
Z+SffpGeeGZHiv//lpqnnN8HAyqHHmmpUFz+5mtJ8JM+xK9mM6k9kb+4NJkhKtAPDqTo4LXy+1FJ
uNnH7oY8hLo1wXl9ZHhDNI4ubwMN0XVj74KtQBfekVOsKtkxLVgjev2/CXWz/2gOT8+qY+VHdc8r
BL0tMxspaJ0DCdsRWdPY/RnPmOkGw1bboNe41kstBJhEqE6Ou0d5Iv8g9UbEVQWKfURMhMZE5RO4
LYtdj61IooGiOVK6qOHeUfff0hK7wwhOg+CCn13nfyRjvqN0W69vxt6ooQ2p/i7uxNGQDrafp7iY
PCKtcnLRGf9WII2JwO+Eii+VIou5+CgcRRP8mofpyeRWjQQ35YCSvCb4uzMSB7ahltJSVOOsJOy+
362uxyvn69HgzKXNLopUkRU1D3wPcUCCRZvD9r9cNrO0NmglVLXbzpIxahzVaqiraZvD6FIvcCZO
iiNCboUg9amBkwMYBvahxE73pVEFQ8za1GIx7AhORoKGnyo9+bwmtPZhyTEvgV1p5mRdiyJkwjlp
PNmcuj7HoD3uArEtBg2E5HHhwqYhSj1YoNvLPcl3xwDetKD4gkAS4LmLqJ4yNEiWkK9xAXHtNegz
IWyY0Lw6cDrQQmZpVu7KYKvj8xg7R3itlV9gKnkGnctA7GFiRwgU49deylBtx7oP8ePvxy1LRkCG
zrm0dJBE7E6nJAQZEwyqorYilIQ2XtCE8H4pZVvvG1x6pQYBzE0WlI2n3qfBecFFvZ/hq2sM6TAS
6BaE6N+uQqfTaYY5OgmtC9KH5Zs3CXnDJ+C5one0v+VxsYfxnPoEezkcNmIRQWXv6lTmdloOD2vw
5LxgvioxERgVFeo3uwEhJxaNvLLLh3VxqbytW/f2QAniRRGKrO0AMfRHoR8TXHUxWl1O9WtmQomY
a7ywn3j9wUHcGDFXk5Wr18uZMmsaLRyrCVqfz3Ae5fVndNpECeeSe/Q781nF9OrYnxRXnB113hx/
S84+yMntF7okIRRnfoy+8R2TI3j7nqfX23RcvX2fLzhRTUgmdwLs7JAxsSiDApmm/k/SvE/xPxHf
JX1dIDO+NQLqfcB2/lne3gglHkVzxHgvcvPH0oOebz0lc/u009DKN8zLprKZRrjVqm91AyoNhOl2
maA4YoJ7IMt/buFccqIsGrs7Ztc4OYI8DbRmwFKaDk2uLiwfCHLUU87dnlcttuSLxa2N/k66pPeh
Hate2soil2d41g5cjpTMvzk+dN2wgO3w0s1cp+504o0ZeYiLjF0HtkCDjIr3uLt4ozRVxbmp2DpG
zuS+1OJfoEg6qVRpje7mGlm8e0LnLzywOfWJMa4YmRPcVWN+LyoNdAOLg2FYTUp4T9eeSeEONO3+
l6ymsZfCcdCTfYFmproHZb3rm/yJPHnALCJCA7yif8niuuZXIyTjtZrOPhuww9K0f5OJ6Wl/GLfd
k7ZexvAyZM96XhBm8R6EvByRS4KaIkSYonJk2eDORBWcW4033/30nNtsjddko6+TmqBjdi09Carl
f4K7DZXXF7CCEnZEItOwmoZZrABnrgEArhC/4Qg0Ft3NgKSXs6FbbaJ4RouyJeduS2sDntwfgnPl
ht9vGGwIJRGdol/F7R5hkNK4Xxb08ELPSOexwe4nLeDyL2Badc4ts6a5pLpDpFhHcXOa/M++v7pe
buu5aMtNbLr59j70Ag2ifSd695SnsMpmqVx2EIJ0bdLRZC8Xcxvuxr3HfxnjpLFqXnFgI8hktbFa
81vAbyUtMC1w9xtobsw+J2KRbOoGFIL7Z8nKQdxMEic2weNkXg65p6ijbKJgefawE6m7tnVMCBV8
rH5DAhlP44Jqx6G596VgKKDDO3MbH+pyiAeGnpkRpK6SmQPAKmhTG8+Q72i/Pzz7uCLwj91aLI8y
Zga9eKYYxKpI+ej8OybGSrYcXFeaxbpeMcjA+A+YQm1VS5EUkJSX3nW9xiikcNRBlTLkYkuNT01q
Vuf41Tl189alLxiFhE/wCU8z7n1taq08YgtW8PsB+/Sp4lxPiEX0JSMmyr43r+sW7LgV7avdUjmz
KICfgNJN905EFHOnut66al0cMn6d+FjZ9IjJJHSZlgVxZ1/Xay8Vv3Jqdc6akw4QBpMdw2CF0SPL
vXBEZy5X0wqf6edscOf0jn6mpdvhmIZn1O1JlAtldN7pnDfVGO4KSDzdUoDqRbNdGF3O9fj5mYxA
mbwuAKLENN4zlP/7U21sKpO8v1I2+f3DUD4lczDB9ekC6hH9qSokbh2K8UmF/1kLhDDRZTu5o2nm
/l9Tic9aZ95CiqQDnlBBq3X9J23s4Mgf7ZeJ7M7vxuEh797sk43zQpQrqTIlRnPq1n7bPfDmRIUF
2rj4QkEusKWwwKHzmHUN+SP6cCEZX3m1ieHNG/RQb4YBhbojFj42eAiAxXjpK4Tgd7MJzg9bqr8d
f2yFq938Wipi93+iNUB0WP7Zvd29LUTxnYEu/YRFkTBpq8bC0GVCNmARJDatJEYxVHhGE/LBdIy8
5Y3iGXdPT/gGKDEry7y1Yms+G7Kr5fkEm7boHAezvANYDDoNDx+w0JLjc/K91qmz4KH79C8OIgLS
fY3OrlTSsnggpY3g2LnS65WZr5i2FzLtTVgcxcDx4iS1IUjic9rk9UztcyUTRDzuDePlJztINs5t
gT7+kqjD5Y8TvBk9p3jpLgZi69sFqcZB/Qj8Bi4Hau3T8gFu2DW8jB62uokN2qxuxv9E9DllpmTH
teQsSg1Aiox7FO/C6Msmta50fHSJOGk/LUEmRxTRIzcckQA4N+Iafl/4wxWk6wI3UwIJlHGkLuCt
0YTPyALZehaDQS5UmtizoWHF6bRjuU0qVNMgMX2H3JJqEB3UB5nvbZ9ne9TINADCCULD3PRpBtYk
fI0UsbftGZAcaCRyozL1CFmvcX8H8okVsubrjYhWuDKpsXTHq8r5SEs4GXWXss6ILimqFB66kGRM
2oDJYawA1Odfo4iGp2QQRomjciKQJtvzrqQwwj+HruCh5czYKCJyF7dOCFDI8Q/RHAAACmKRPGyG
Cp8tcgWMyA89c9VdmObaT33E0l0zePSuPlpKB/V1dMiTpl4C++zzr9+ofM+2uM7TAPkaE4HDLqrH
Wg67wCrPTO7ImFD7rb2mTd0o4XWlba0Xg+mn/HQzZD2BxueXXHApAK8JWJBUWIN8GtFAruEfxUug
/46m4m2rD8hc6vgnLz30bTQ3pOMYkKHK5svKM3OnTHI4SCGlOJxjJrUJb7vKlSPFCJ3m9r15AQUl
lSEnIMbRYGsMXFfPKbcA/KQ9lZAFZKiv519VTSZuOYi980NTf8UfdZX/1wPL6oLjJU4hxq1iAz/I
zfWV+yqLwyIbYlltODB2mx/AQ39MaAV5r/UVUHVw+V3WQrX/l3lZPmQUl4gdyDvk9o0Epf5T2WVI
6yqZlMMQGfsguzOlIeB0V0gB8WWIK6gwTXvHNqEI999F4yFgypsqYgoJwmCfQKaMH6237MvCyKGo
mJONMQTVi3vfGn7+uW2FGQKG0YWWxu7gkCpMQazpKOj3x/NsUsbp3SICkbHdA7rC0W1HROqsMtNR
O3Pf4x69zUnsvDMk6HvprIOqkCfMfCnqp5d7y4t6Ctnei3A1O0uKcqdQxcMa3Ixf95M+K8p9Hx5q
UnKLgf92tBCJ1ZKx5IXxTNa4Q2BZMNqjObTCMxaKIbruWRfg+4/YkoGyrkbRkUuHa40Ixpyin2I5
9MAWTVyts0+N3jE89KQKQ3WZSOF2Enc6vlbxHVQRtgMzg3zVv8hmMVXcYEOksXSTi29oAN7c8QzE
9qc5W7sOC6vvh71m9+CiWBQE+rOLuPH+mdhj8Fr7h6nSpnTnQutC6FENjmTWU7n+6WK+fUO34voa
Qh/bO+q1VZs54oLy5SF4bzzyywUkYqIdzAHxaUMbPP/kr5QbXsNM+991no2fA457LOEN65WITTOZ
RCTrOeIpl6gK0xAmpGv0nzBClZRH19Zp+72GEzlWbW8PyvkWU+4ORaNb0iVPKYbHr7TSwCQl/wFi
14aM2PN0HERn+lDBVLDxCQOBrEPRh83NnH06Fiyvin53NMtpwnq2QIJXub9RORnEi7jyR/ZDeX+r
z2suqLX/LEbx/C0RZarfDnKiFqMX12PelJ1O9LOcD1oSRtPxBK4uQmcwsCjp6JdAsl0ZzCNZr6cy
8WaOZaqrbdWiH91OJ5LIsz7SFRlSKt2GXJTYiF3zBQ0kzHS3wqSnPt2TnhPKtGGK6yHUXJh8x8z+
bYs7mjZqDDp3ZiD4v/PExj9mOcsqqGReb21zkDeY8oyCHiftZ1IHZC7gJ34mwZnqPeZEShb9qEw/
Jbf8E9PJKVhAPbaQE3kQj+2IsPfF8krCLbDI9WNhF+9c3lO2xHb4wUNZQiSp/n2E3C2dJG6hMLOr
DotSEgkL7jfgOVUtH+2CxcStD7rTpaVJcK+dBz3stz00EWQVSnANwQq47mvpumeWm52UsiVCOIP/
CybkQFCXm9SS+OhZrytE3/kMwkFn0Iqh22b4b7ItNWiCWrh+ynbbYzDhiJg0fqUleiOzd5ltMB+X
emfWkI44TtjlZ2eoJSAxzJzsVw4jnpekwCdiGb8N+JmBa7N4nE8QvLX3KLY79AbDnlmIn52hg3iz
exxLbj5p1VoyEpZTXxl2uYcWSLJBPbD8XGvdov5Bpd2yRx6AkHoiSIWScYG+kwt0foJoNhqgyTk7
wLXRZFjjRenuLEDAEt1w8cuQ092UpB9crElGG/ArMU02Oww0w8k6lxnjVKQQcwfMvJwNFLXnRJVI
q7bBm7/0An4DsnKlPadaZi6wnc8hHk7E983Fendj0iZDKeDNqocxKFZQszbuh9dVMp7yTUTR+lQ+
XqmtBvIQlSNbR19m1mcvQ5+vgo9DXRqycTxyai57Ajh0z1Ku6AwguwSTe3UGVuEzpODrrVBR5MIy
28/ejc/hF43dFzuPuI/tx+72R0qoIU1AmQXzhN9F0z1X6cxK/FNLJIYX2HuI2IGb+lNrPyZEeTP7
Oxke9tqsDPXgokrAwjNoXjbj/jjbjME8UXAwZOO8SKxDDhGF55dS7bvrXKvUS/QR6lygkxdKn+eP
Vq6V1hXZMvEldvyDEu8T/b1gZihdwo+VxysW0Z4pb+YXFVgLErJtqmgLMuKx5XxfyoqKEpcbBRQ1
hDiQKYgrJgfAhEBVj/PBJ6GW/LuNQ6Hx1dn2eU/wsaoV2zGujRlDqqGKGS+KdJdbv0LGP104nwqY
hMTRA3HVNXOIn2oPtjnEZVCyUm9CImF+NQZx6shWu6+QVPrdKsO6Has511Ws43khvSvnI7CzAxcn
+ZMnV0queBr7RDYaT58pJh0EGlB+E+hVFz95e1ukd3CQvZvRTITnA/vpmUIj5jaK6HKxyzBGtyNr
R1dk0nucbr9lZSUvWnCqtQjx65ewvtZ8EGRy2snmkwgPcL6YZ3lnLS++FsngYy5QnB9o21l5Sm66
mvj5bmm0U3/2MErYkoq5QF1o7BnUe+7q2VBdZVfJ865K0MsQBcNptBRDJpod8RhBGRfSt2kasyeI
CMSNk669XZdpB3ZiSEzYPPWswAsJUwktJSM9zHnnvdyBYLDbBO5+04Gl0UoDkLCWzkPyNqDOS594
Tlv/Ir8Xfel2KiMNR0MR2shpIxpoMG7eyAxctTsHk4jSAvpYyAWpzk+vH1rUix2cK7aTO2p0sHu3
YfA8sF0NdOlnibYzb5oE2wpLSaXulxNCBVI3aiorV90j3iq/IMQ+a0CyvrJ4nJxjJhenep35FxX7
yAvP6Work3QjN/2o+Fp0ZUK4H0RSWTcL7Et5GYfGZTqzPTgm/1bqBpKbUABgZPijAaz/KyBbcdpy
Gx8ygocD/rRlzTpV1gKkUhI4uJsUGgDvQ93A56zpc76Fb7plXs+wO2+MsmDJ3xjK2KQYqxdMFgZm
k8APcjz1aIwLDziGCSaxzpmfaGz3kL03+e0aBvr+ru4As9VJ03gO1q0dbOTlANXxQyLqYBh4XjiK
j7mJvs1IA3eb4qc6x1jM5D+2KuQO3iqnS3uS0anRJfzfK7MJklHf2IIvwxrAzubo4ZQtSnSmkWpr
GG2yWO0dXTY3/+/6lEpJkaJyM26zxBu962POIIua1FJynD38c+4zdE7nDiqzbKoSptTtkNdLZD7j
7PHYYZKtS7ivGf8b49dA3XEotxAdQVw5L19JMfgfk75Au0I1QaiZnEcx5fXNNXSispYJWRI8DDKF
0rUF3u4a3tZwNQ5o0MK8GKUC4t8Ab46SGLZGsQ+wFc+wdtaLafbJLuINBxPKAY5U4quRugAA8WZU
+7B6mp4nTPsHyS9vziBGb9jpuDnNmccONEfLANXiN6hHzFjTgjw1TjPlor7jxwK4Em07H8H9kmu9
chDmjgzkiMVO6ASCB60iqX7tQpP9uqnj+QhOdPT8WgHjcgH3Mk2RwG8qISmHwxQkXvul2/JWTzOz
NX8pwWjxK2U7zegP1AJ73O0VdC/utvvl1Aiv+IMze+3e8AUHyJ2zIpqNvg6BsH5r7CpV7ZImzQwG
a4i4twf7gtx2uaDNiJ6NrbfUvjPo4F8S0vi/6HW5oM7BGMrQg0SANl5ABXy5n2kbPyE9IUiAAaQZ
90Y5qFoWvoSHVn1CbhDXl5R45AvX/m/4IlmJmlvPv3iHkk3OjXWRR0ds0HMRIo/zcpLs54ZYUUg4
GsQbPsu5ML5mXpg22fSv4h5vrkF+7f7rH4DboCxMEjC9oqHL71Ww2OxsG+gXpgL3yYhxcUEazg3n
daQVZde8Ccm4tTUhAI+VM1oAJFDlh761b9EoG4aTYBRk1UlFduXQatmCkIK3xJEkPUtu+ug3guHh
hYsxnZikHUya7bQza1NCP84Q9eGKsJdFec3hZ6uxM8L7ZPjFuJcZnFJFFrf/uucaxafOzsfjFpLI
U0NLKbor5HZQCMxQyJq5jkW2pliyoahCio08vICZEhVLVEHCObEZOghz6T9WYYBWwFGgmYhwSbAF
dnRo9i9QXzUpWGQXVBm5apYeQWHSL+E+dyE6wjLEZuBZ5SUojbhGhxw3fNAo9BB8X4FQn3r7gc2h
y0CsJl0LFxphMWdLdWnh+XGWj0knyAAQoRv/X0tKj/iQI2mGzBIq1DLcNk72tkkhqCIql468dtML
mX+T4zf2owKxawsbHRy+hqFxrcwXNTla+GvAtAadOD+3JfFVPSbf4BgWVGVyIpIZjemumBzMdO11
y129+F/oI6YCpLnDfRF5ILDWVtKkrO2P1nc2aFYtB9y//nEg5hkUYsEinZOpSEeqt15Mh4iEiKAM
sw/vFL5t1ff6g5WjmEU5JhB/+ESSf5CRcqXq7SJyBQbN6zpcOrnVjajjHqa9IL3JrgoYyTSsgbCb
9Mj2ANQD8SNZ4YB4tS7U/lya5Gqe6s2PdnUM0ZaRtSoEOUUafLHD/dz57Q70HCDEOejjvrbTUb+i
EBu5vIHfJ+wXQW2T431DusoMqxr7ukZN1eO9lz4yE6x8KGENBUaiRSPI226/gI5IuONk9yYn0yKg
RFTqhpbvw/cWsT1JK3r8EAQ2EU6DbgQ23qWo/I1NNpYZAukOsdb19oty1DwsO+ORCRsTbkK/pI4K
v4Tq2meATvhE/AjHehxxC2cEBKZrzsjKh4N/N5mwMZ5ow4q2EtGHA0ONWVqXHUnPySgXuLYbBg09
NgpsDrP62+nlFWb+ItVhDTr6cxZyvpVJ9/WG3XNXVFGTPpaV0htT3VjNEnhT/qwsh12Q95mDnKmd
qMusZ2iIBCLRkCmUlapeowvlMXq20IkvxYDeP1Rza9ULNdEKu60F/kyESNfQXSfF5tl3XMdMgfq5
XhkAup8SG/UslX3TUJxw2GnWr8BIPR9eetZPJvS4PaE694sN4vxX7Og3t7ViwFqmll0DTiEcQjQ3
oOXQxZ368DsamlepsbqFdKSgg20pZuIFcP3Yx7a7w16NdQi7XqSkds+IcHeqjd5eirbZ9d4iJnpS
ly2PdbMsocPJxeREHhFAn7OdPP3SXTrUaBcX0qLsNTd1y78YETOk2B03MH7kzros0DgDGHJ+W/fH
Ylsi+h/Tl7qSA+1LOApUXssu8O2PKAyae1meSwjjRLp4ciPsrUDNeuPjpiVhqw78toPbfKUzQKLo
zzW81hXC5GDrresmReRcjciN2dnFswcVYaSImfhKyibZn1eU+dgyRnJ20eykDdarhpUECevFG/M6
wr6XzECzVTWByDK0VeKS6r9Xg9WrBUFFFJK/ySvTpeSz6c5Jn90JZ5M/DJv5uoPa4Ex9xyxLJAGe
wL8M8+mkGm/joPaHdOg0g21hkpkREc06rbnbybawHHD1D1rvUjj+dE8ExEOzt1mqntPx6/n4yWSc
v2uNh3wkTVkmbq2kLM45Sa4jj7BYEKjVntIJ6Gu5F2FFTLJjxLFqc6VPoD2kUeMF1UYd5dipVEF7
Vi7U2pN07ONcv5Ea5H3dMAyv8k+hsPQUpGKr637b57URNuUKpV6/J9QFFB6i2TKk1OOXs56jWyeO
+LP1o4ia2HuPv4zi1sWvHyp0piPgleRBs82EI/RB5Bs1lR8zZ4U3B6MZm4fLufATQGWW0dAZq2Ul
81g1lFAJJyOaV1zq7bAENJmfoGmpHLDMB1vFH9l7O8N+EQDNdvBurCb2ionyDhoXneEkh1QmevVs
O7UX4aavSi+pzSzRFqQZUdNK0bvJv4kt4Rps4cr8OJuJrTZUHId7tzyA9D91AaErK7hCyUpvuH+C
UInDRHKndpvfF700hOuoPWF8Ut3Qx6gjinXWQhAdRtwnQykC52tSwY9KqExyDjkMMgmNTqus2Q2t
dfwKofF/SGPI9a+mEnWH6I8+9h2j/qhIEKRciFNhB6Wn+B+hWO9b4VpwCRsFGJBrY5oLha98/N1C
OfLOdusdZOkv4pw5fIEI09bIxesiekfKySM2dT+RIZ8hHvRS0eOdQrfWk3ma24pFnIBpreUVdnsh
D5/CRVTVMD/c59HExfm9S7E6MghxAqk6977hKLafC60FlszPuODHdDws0KSRK1oa3LhqpCMBrnEP
REsE8TSEYZG+cMElaXL04RkN+tz+svGaxwlpgYmcjiseqjB7I4oQNwZndWM5NNbLyu63f9FiBcRO
Sd0Pq3RkU9ZqqO1JybyRVPrjDQ84f6nyFT8KK5xgH2u0lqMaBNMmvNjOk5wd6g0PZaDYs8KrLmDE
w4PPhC/vi6pnFQlU9jfJ+HeGaXdkAjjuVPRf4nq6XwyPxQ7JbttjvQe31aAkGA1k3m3EOq+WaslN
i9q+JtnCZwxVwtRr08u81qiNN34cQKSlWRIU15E/qsYo0HadKC6NtU+Y/fi+/uivCs569ELgPDlY
pIIlFDFlhTkGgT+zB92N706z37+N36e9v/6qKgzhGZAEyg8ii8zX+bd5qB3q8rC6IqK4WZXAH99h
VRafQM+Z8ot8YpWl3KW9Y1zzmEyFX49HS463BZlk8NaTOMcFtoGGpFbgTYYUp43v4FfGYRaer/y1
fWVlHhnTG5Cc3BRG9lyKqjor+BXGV6O4htMgNETjZFnVLRnYhie9OhBas2t9TWByhzXak6KtTKwB
/ZzdGi+uONtVTsMKNX/XNmJprwhSOKla2m5liGJsg9i4cxjTHNsUUlxbWMzgjW5omGlPRQY7SzPS
HcHI1diZncCYVPKo8AkYi6jOaifJIHtuJylrUBhjtUQK8UNs8DomlbttuMPJrTavbY4Vn+09ebmu
cY6tm7aky6E0w8+Hk8Lv1SkGCQq+RP6DnD5XRvRczXiIir/cpmnUUkjxlbW/tgxFbeX5TVRAlqZx
C3IiwHhS1dl/IZEqiYg9J5OHO0dTS9lN2ZThgImPK5aHGO3rCHfxXYA0refMTGqJZe9Fv3x+Te+E
2pAAxGHPD7sJsbubc/Jwlt+CFkUDeH5ad2/zQa+73FLhmHedqrJkeLbbqRv2pPlquzv5JnYuxzGI
wH+9OBDbzqMQsY7bKy/42xXIfCzxqzgsTRPKVRzC46br5kgo/GzzBMNY4UCCUzPPevnmT6OFYwfo
k7+g+NRbIGPctso/syqwJyIJO7mHWnGwOdGBpEe2nLKj8yJZHOThBJNrHEofH74HTwrLuZ3qc+76
jsfwY8M98rAKwccts3VcTy5RRuznB7QTPwZQNKNSGHtLIDyqbABGoTWSoNWQ/mwT4Olg94p1gpO7
sqdDcMYEFVf5/ABaMQ8sqOoIDhh4VClSRhfn/QEPsiO9krnKDQhJKZmsp4QCjvq7OTrZfmyrTn2c
FtTvDORgpIDgzR/i7xESvvZRK5Bc9Ulzb0ZZ8bxq1ot0UALGY8kbZ7Z90HnYlMwXyP1r73A62XMw
dDRQxmbsk3aeJltaL0nEtuSf1ACEq5x1AEHJM6daJXQgI5gkibiYsjcOxMa7QmJeItDPzyd41MyW
Iyi9dXyDpwtVuMJSTNg7jLJflN8Vgh4+kBB46fsunYrYhaPoMGooWJ9Qb+WrvGEs5gC3XbmKjuVV
pII4dJq6dE1tnuS3Hzspn76o8tMgOkH13ga97+BCq0/ReTm+vUYcH76zXNr9Be+SxFMmCaaY4K9M
PpMh5tAeO7WOJzBldVo8vv3jVzS+AQSGSAQZKskcQGxbDsyxtPxFYsATyr6uY02jN2TLwxrJBKBX
hkxkuoH77/ufp4oYghi5SROFLaNC14B0xcgBoP7mshZb+iWtBbS9EPioJAljWCWcAUNlZQIgzTjW
9J3k+Fc8pfFYemaWJpTqIDvvf+6TXflapLZ6Fm2Qumho6WiT5nh2Ds3GSVvK+G1gLNRdwY5BjQWP
F3mj4aLLEqdCWprmb8RKpOnbuVkFxgU6Zzy4DDPp4F2EplEVJ/ggvOlZCSFlsxZTlMG0X4pT3jxS
+b6yMRTBPRWCZbUa0aceI7qDm01Z3R8tdfmuE20jTSfqpzf6CQemPX7r9h78XUxnqGtRxDd56RzO
Jzyhg/80R5pRWwk957EPa5umPHEWHApN2sQhH49qDgmfKjaef0EZH3dcty35SypUq/6wBhYVcJ3P
3u0vVai+3pUJMTxflYvLBRQMDYG39m/DQX6Wjh9Q5pzdcHVEhx5/DUSol0jBkLq7MN1LDJlCaEt0
Db0ce40+MQc0aBI8SUn6HvKbvm0/8l9qp9NI4m//NBVCXWq83PR4Be4rYA6z8vovK3H3+7+R9pm9
HQWePglpsQluUCATbblEfrIz506EU/PXos64EmPLBCoR2TIx2nob4XohauVxtrhi/YRw1j/02z3I
Dzu3iQau6VoyfdHlZfR5feoCsyMdrmAZwkGv8C39jrAwSNg+aYRlFf1pEvQB4BPlyckOfgiKUtnW
/mHdwF4d/AmRa0PuS7WHCJUOdJ7UZTEaSwE+evrhqVB2REzK0UAl1qqi9EnIJqDPtxVcEBkMFpuo
hssOjhnf4Ldb6xpyZpRPzy8jof12L7PfM0EbvWKepzBmJLhAVXUKClRUD2kv9NjnQ/+++9sZtkbo
YDQPUH5Nbh/llRw57GtuWB0QHmUNxr8vBYA7PJgDZC29/tI+HxTpraY824eHKmlIAeuJqzozl05N
lMFOCPxW5sNOswzf3kceZySWCJWvKUIT6slZVFPwiwJtJzClvrijgvomipAZMkOwkcWkgGO58u6u
y/OIbMupJxW6867b1BajahRdmY50kJNMiG8dbTVDqQCac1Lnrqf/oZbP2fP1oDClfRL5UwULU0CC
PxQ0Iu8aXUBawlqqf+7LD1K3jn8tdXAewpIyHyiL2jT4/yJQqCQtYEw8yS4klupmsIssoB3cyDrV
mCRZ/xYUPzZ5W72WBPkWQCIpC/zhNx9dAkNM32Wr8kftM0mQGVyCk20Lpd75UXl1JjZzghOwXsdb
8yEIhw2CFLsHjhuDE8qtncfEN7IgptiSG7E/FlrsZNI9pO5Fg3R8jsD4R2oHfSi07Q2C/0irTFAB
iNpAaUYnHHlp2nNU0d2PgBbwLN2j/4vXb8OQ4KhaB7RRN7HTxzVU6mzUKR0eeF8LMDC436XgEJmR
yVAaykXR0DiqUL4DUB76lAWIr4xKtg/eFrwtWCgFjS3PwCrhnzs1vas40aMSF0Oe3AIHVQ32tfA3
8RSRNvvJ45Vc5tPCwhMYmETHy2ONHfsv43juCXliO2WG/I1fhpX3m04jABC726v5BEaCJwu0cMMe
Q6+GMb0D5kXbiffM8Kgic8f0Hi02Q0ZpR6xnp+vQGdxvCJw/tQadqzbPv0uil+RYtvky7AMu94nA
F3LxYQaYV+iRujduP0eFc+agyBS6yfUuPF18e7XX2sJql+GHAuYWoLeKOfUvKyU5BoOHD13hXjXo
svNZXSIE9FI95FM3tVhyJdCCdEes/RXGl+NOZ+Yb00mkOB4Uzy0aKVGooaKJ/jeU33/hCE8w7E3k
hmhK43cyUxo6VrSfIH8CiDPibXSRNuc5YH8bLiN7XCILVT0QdLhY9VICgomdjNEaQ4wJPFEYSz9+
KfVnql2Pla4FUdTvpHTKaihwcbfNUEUMGxyFch28rQoE+ShuCHguDpo76y8/EyxWQaPXr73boLfN
9f0C6bF7oSl8SJxuNl5rJ8leLA7U8CGPQrN4/3E0JP9LNizd8rNssuwv0dGMZOfB9Ko4JrZj9u1D
e62DeQFUO6NifJ7C1tD6wDgCIMwC9BvuG0YXfBKUIJ+GAq4JInu4nnsXwKXavW1M96qx8a3IsFl5
M2jWxioToIADXHtA4uhg2wpt3hFey2P23/LLYqMk4nydun4kSgNAM5UBm+wzDtmvTTsRCGmBzDps
CKArTi0en0jlOlJGDpAYGulVHJ/jxgt+OtrCds/G/fB8gwGUXTh8BupMup817yWAycw2bxMWNYtV
tXf2IYKrckfuFQyOc7iQZrBiIBvwkn/WP8HunUQwmNUnkYLtQemvsagmjW9GCgnXkbz1NZ2orkUb
imElfw+QgfGG88Erlev/5Qo0NbFuHdvoioR6nLhGz3+A1aur2qRjxZGqfRhZoO/+4BYyovz6CF80
mMD+lLFhC2TfL6KqxOmEjHCy9otbNzdPz263WkMPTqNFeljfvrzZRlNSBhxo1Kh4+PzTziXlapBV
fqTetcxVH9iGFIwIkcO7d2lEmol3CHyggblQY+GQaaSe2fc6WSv14H0m/K51qzU6ysf8VB8hG7Mn
NsZbw2x4hNEHtDgyB1yczVvcSX0rS6S02kOnJyZBsYAcOqU8sJxEkuV+8ikR/0v2uA9JxSwL3Wf5
o6S3g5Lmp+Nrb0eSyF5Kv0uCpcnAmsll2yHGCOUA8llUR4iz7QlySbiUaG6iDa6qMbvlyc9zwKdK
cjAb2Z24/hAHJ2i9MU5VAs/82D1oNaAxyUuGjOaMU7dbWxDGd81RNrEqRIsN/toz2TbsRJJkhmT7
vhnQuhCe8HnHl3VqR6kfjfy2HgEMefNJCleHX3mgC7yPJ7Bl0ApjvBWTRC2sLRxs5MjC+2rQDOtY
zInI0gSUr1Dj52665rWYzrKWJGeHEImTzurRIg/hxnpVucUf7gg9elcNSEeXBS2j2jyZ8RiFRxpo
UYTCpBBsRAkPFSLHpcUxvDYlib4yRsG5xMd8k94u1KdQ/NDEfCTXNME946LGuiqDnGUbMWMl+jqB
pTwHfS7rlXo7FrWqGtLQ9maeSSdOoiwsRxBYgKfXD6pdtM5cVnD3J9chdSOpIZl7067Fev4MHtJQ
fdXsHy5n8mWioMdxdhPo0BZ0fKvkkMiAzZWU3DqewXsGW5SfDJVsaUvDuwPrInPb9ZkKPIczuVWy
KmyXSrm/3kFWQToIV8iemTie0sZNaWOdpZAzyTKCW/kO+WddlDMO8HfKS2KN3WBzfxEm+34pZ5Uf
TIupcaOGUAkdizFhIaw90mUn1DoWTcr/LPyA9Q3h/coHVsqSnqoH9mvmWNaO7Z0p3rxxvp/P8bJB
Mmw76fwifhH1s0lUtfoEuRoMVCGrOPPFX7eTAyuTD4y/NTKSySJnT67me5uegPj0aJtxI9yXoahu
yGMq/z4p45/SYBBTWrpPkMkqxzj8iJTSvQxPrN2nYzrJx2mAS6sT3qabx33JgLN4kheuJcS5NdX7
6utXSyAf0KHq2tHUKP0k6m5LDiq5Eb19AI8Ge7IiKAde82ytSQdSbLAJiQsmW07OKIFJFFq/9i/H
9Qv3i4bRjs8sQbFULdCbDD/MIfbB4zF5me1wgB9c73kRYMK/iGxHsSTqHcHw6COdOfLYVDbJu7QA
vRQK/+xax5oWvJc6Ka+UVgyEp4GF8ZxywbPl2MMSzYVPHlXp2+JoZhBrzbHpGdzJa0k5lkkWzxlc
7GbtTEdougsEWohYXvD0VEPzRXskPO76eMB7g4quUCMzDlKHvmUfYzTOV09xYgxjpjvbn8y7JqB8
WbPrR+rKdJWyQ52GOQFLJJ0tcfn8+35g7yroCalq4ioqY5u4/8wOlXVOuoBE6kCOXhytlprlsI2J
j8N72vcpSdAM3WLwbUFnFV5AppZPDWStO3W4NtBKcZqY8t0r52urCAVkDFxWU3av3i4BBDT88Jxm
2FVp2B9XkPknq5/I91j5Mq1nfF8DW1cWSm4YeO6CMsx4B5wEOZgeEo3XWQgnZwb3l0+h2NuA99EZ
AS/DPrRgv9uJJMFsiPmtXH9bQOFyWRilAm98arl+TPX1xg5pvER5uFA5HIgD1lwHfgEL8NYMaOqw
u79i4l4Osp+lEYWx5aGbws25UWEDj3UNCfJZIC1FJA54c7UDDZAwQuggenJ0Vfso9M+EHw+8uZIQ
rPKaZdPzFnH7YNreVapKoRdSe1XASXLATrXsOsPj1AgcUOGeEG6Iytdb2ZZKmITkHEorvhjRkz/W
DJ0h2MQ0KGpcpj3iojlJOpP1h/gMJfx8+iVhFBuMLbjh7us1mu+CoiFzytAyaC0gj0ak4+ffJidO
kPlJm8wWEe8oDqhngiB91z2euFh/3z3ADlcLLbjWg3bpG+aFoVQWucttkd280jApR/S99n7qpcXe
uksBRtY1vHAaoYvanFQM1h5+riL6f7/wBohXcvLyeddqeNwy5HbQpd0Bat1OJpVgJNTMGN84wNap
iq89gEo4+0Bs2UEVCpEjoQMeZNkpVL56HB68PmqqaC2o0m6KJYPO8OXwUeINiUuKYnjOsIKxydc+
PXxb0aUqd2NLGU6dQLkP4+g7k14EGgRky17WjELOss+Jh4HSCwKOfGZ2h+yYZY8jBRg+iaUWqrgf
q0loP6OGb2uTqMK9aIaYuRREnGJwT1p5RKCGhQLQ9b6xkDEUsV8oybWbijCpnJ/KB7H3g5ItdBbi
Jc8B6J+h9CF0KfJ07IYG6OTRAkiALZ7C/wl1/tHTrJShpUhbY/dUHVTbbkGcZZfRrDX+BzKd8F3m
PaNW8nKmHrr5ExKjk3SbRDspFaCS9IVRxBrkb/4zrRi3d7SRL+UXhE7g19kmSRr79fzXnommam7q
2rl34h/FspZBobzdSWyZPKJifJY4wnxP5iHMTRTY02WOj2uBqtHVu15gSG5Wb+a+hCn37mwM3eBw
U/DtP+6OmeRJgQmN1TulVbOvaQnu7VrnJfm4dWd4eCE6KDAdmTzFM17A6+nCF0fZ6ucnH6UAS7Wh
d1gFvraJU7dMdKkrwtaWAz1RpPkJZuwlMV34XDI1cubbiymbtyj8UOcxupywXzdXqOaL/aNPWdLD
r03xXjYvv0T/8SSpUuvcYj7XmLpajIdQ6B4BLnu64Qur1NorcyK+wveSpxJhdXiDnrYctSQrxZdK
xZnovKsjYDfSq+WpizASuuwi1LYM5aibW7pAT1Y2Sc8XqaKSpcYrruxSC6PMShwhulqdwKqgbqcB
3bcnIqN2wXERRjYUlq65Ggki/N7JEkGVAoGftFwZetDULnmD3mXclu0X+PBXQBDaVK0NV676CnQp
wbvyy31yympzxekN4qbWv+8n67dhGuOMEp2cpkDJy8EkwOuUyWFw0V0cI2qW9NKLfsZVgPSqUk8n
VLspEz6rzfGqe4zvpuE6dfuGD/Vb+mavvK8+mVDszuVnQWYm15q2BO3buugisgOWJTkpgI7q5Cre
ml5SGunbho4VZ4UOvLFd6wIYFDh/sUkcKSnqpcZYCOLNLLe6EIIVRLmhXEEjStMYdIOqMdl541a8
jfev+iY1n5xYu4EQeGGEQz9kJ5L0QBXUbeV9rR+JvieB/cT3AwREpRzftZa7e+2+dwSNnQGr4RPz
dkX1EIgJ+KoSm1zv0oJuuSckiGOEelPBPWWCbA4qesL16M7nsVbGTKl5DVhKpJsKgJQlLP4cAGgS
VxSEuIpYm3nisX7a8rRfvqnEmPA+ubjxkRhI6axO32wfk4q1sVGvdNNuJnUotnxh/DJt++LWCAMx
ZkxOAeNdHs4cuRk4WYNlJ6jUoQ0oe4QcrxyYxQ0MocezcA6nrKWM2xSm0QThXo9aauBYGILPkj7Y
y3gHwIJQLTWFvvU2cJeb96SSYLn8nnyVjA/Nnne7JB6HnulE2SrZRhQ1rxZK2fDMI7CwaNFePzag
W6kH4xV2HcXJ0zYOYKRxA0ibwjK3CAq4437M/jH3ogj/I87BYvPBtfVz/mJL1eysUjMQ8eHM1cYi
sgM1IgJrAcbmk9VKFE+Wjq6fFla3Hfr9zcCvhobo8SuLRZvUcKAkPeEbMO8iVg4CLF0g6P0L8yvV
oT7c5Prjvui+xnwRnaq5FbJq2f4YJgGVqzIr2kgr4QZBSKkWWUVyMjrNuynFwnRNR7CknI5bPYai
JB83g/jq9CEubL2J8BnSef6dqSNMiSHiApNRHd1ay1aZidS8WiQCOZy6A10zwZTqk8j/dcjsRbhL
+lm8z0Z2YrWIYFxBPrazEu+S/6iEwzLPWHlGiqjQ/u7BhEkbDuUf+zXfVLeuBFeRtAo3ktEY7vcm
WTHCF8V0faistU1zi4L2ckHJB6Vuo/Wy0ubbhfwcQOmeub+hXfW17vfXzfTlZYtG6RxPe8Uo3HzR
b/lKJt+Ie0sTYHBxWOEVRUv+HS4DlxcX1/z+nX9jM2d7aOmwLpy70eaqeX/ONI3YqGO3JtUNq2eB
QzUof3MLpz4/aDsM45++ERdy4zQ96D6kfUjmHBrrj8FjSwi3569Vzv9j28UgWug0bF909BYpPoDL
HuUVnIFTR5JN6fJwlF68R794j1PGvEs2wFXPCV4rliHyyUhu88MBAmYJzHdDlgBrccGjJoKU97MU
aho9u4JJy/t+GKafMnLr/fW3tJp4bwg6uzkYxffX12oKD54vAnggai5oMVE3FXdfvWCAjdOF4QeH
Dk94Uzp3gSfFbinxNS+xFKOzyyOpObRVtw8FjEHTZgJHu30yufm1oiXrht/vhNxe+96xuAgKVMkY
NczJZ9xHoJY3yaRj2ODE/rf/ceQRZO7Tb24gqV6uE+yCdJ2k0VKm9h9etftr09BCiJh0ZVfQTJmn
IteN+RtXWADPyt+ftfgc5n8lmWzfJZT4xcfSman93KWe05Kz76AnVz99V02UqgfFc1BLo/ymrI2I
tWdABxV7qfftwex6tL5TexS9KBUfRdDTuUrRZK0huGdnDsdmweenqCiwG/BVVNtWDnt6RxBVGi62
Fs1Cvz0kkHVzFkSApzJFILDWum16YiQyr38rugEf7lkRLF8rtGpbwZqADhP5V33wdhjncDAIstTw
UQL53OyZdWpzqzxBadaCAxtAs7OJYhRCqWtT66c911GuyG0rGjqgERlPC+xlHqPAqSsMaEM7i1SR
vKr+l1RmYLk+Yq4s4WZ57M5PQVYs2oBLZRzLmxVSTSznR5il0L5fWPDZFj6jUJk0qKJNmRiEr4Lc
xFmUzkAl4xzJDj3LO/VPxNZGm0UfSfcCObyLqjwPVBFMNpvU1OBFdZooj4wlkEeyi9d6FMmP5xLl
coL3SiBs+WXbKDh86srD/xONuSl8KhZCtRYEUeVrjjyXkYD5weVSPCAbV09j/fO9fCjV3ojosvNI
tw52D7gDOIHwQyDKmAvWZy6SsmuinQSXsxsKrNkh+VfX4Gmllg+J50AmG2cZ2nhUWXo9TBjUzCsR
K3yVPwylsZG0rgNBtq5PnwzqNydZpQMVCUKHrUABJy7yE9HLduVrmk7AeE0i6zXWuuBG3NqxURKk
IPVIQxxoJFFFtoZncgB0Pp+I5dfY7XYPGaf/fdYjU9xTOEeipd6NQyHBpy4hM5S7fTB8WDXKqFNp
1PCH6NBCEtUiXRVgZlBZNS7oiEMX21GMTuOgORgDxd7zf1B4n8uAH19seq2/QffFmA5usSVzLNqz
XBDwBI9737ffG6jqXxdA1nCYT+hwMK1WpldersxQp63LhfyHnicofpct6bcuLC3uRjlk+8f9oFMs
IBynI5r3I+f/L69Z5HnkBLVoSdFMTJo2F5A3sg6/YPdzsPSDjuVv83iPd22cHXeg+79krMdXHKDo
q4ZFxNQZkC5hV/6CLQ0qga+yDj6WWOUvqiC271ImBFZL5ndahsEetfCrdkhUwJAXLg2kuFYYmYXC
64wwS1p7xTP/zCV9WRx1nDahUHhppHSEApS1Dd1i2zAGWlMHlKJeKT/X2u+iUX15AyaCca7Uuikg
s1HQXSy9wcITBO3mkNotYNOWUQhqwh+P9/Ab39A84qxyQxvHmoh7PixjQ1Kzb4U3RQBMfWKRMie1
afKB4myCk0A6NBULQ+CpMZ207eC1XXADqNbWVHecNQDVT7Mre1Sd1RwX7KQ2Kki+E8d2WxHsWR7H
r8wOTsXxAA79cLO/4CSXEPacP4sKv9B9QXShwViZe+VN9c6TfLjLbZ0l2a2kC8tHuqRUbryqe08T
k3Gx5MQ2fH49vWnhr9lwhjZb8XaXak/Kda7otn2g9dTCmjVJNf9IP4Sqp/bN0qft2BwwQv2cH0vQ
9X0Gt6/rBmrOZpkWYrpdcSmvAnRoJYX/yS6zPlgL/i85fkZV3GxmNK+gdIQ+Umi+KcwHfGSr748E
Ar6fxfcZdexK/VJiz2Zvj1UfzR1v2uAWfigVMfFRMuYjPirWovD7Qx7mOFMecBUKce02PEoUZyYu
c1vuNKKOe6D7hGRoQDwY97F9xOEJDMdl/RRg1MJZ1LbxcMeh7fvEJcHVmVyUNLcuApZi/563gvDg
DyXcqupNhyPKfNhB0bymuJSF1xndYiVDuvp+0zGAHaaKCX13+hotRMwKG0gM/iWm2WSG9zEs/iiS
kY+g7wHj+UP2vK/XML5ZEDLS/qacp1PjUDpWLQahzYb2b9ToP4W7rMy2RR4hBRzU6ehUaC5atdtR
SycSggfOaSW9Cax9NXoMzn8eNFL11wyfBdC0YdWXmxGO9vjs8s9uaqeFMAv/u/hYdVUZ9nngwStt
FEtVbuOe23JOOW0Vy+M1/Tnjs9onQhJlku1nesUXL7TbCYFfM+8uuhvjU5otpYyLpACNq6w3Tdo1
+kwarveO0kT+FZwNEkjz9HAEjoFCNC6kIgB8FO+X9NJikjT1lgPBdlDe3iSjmF1CIvdiJhYK1Sdx
9sBLxDD0k3c0Nv7Joy0hnYnEaYWMeXehB8+vrZpVaHI5j5X+MoR5jkGn0tiNTjKrFe7QSAx7DIxa
VrsRkQJ17E7++BttqKhbVcTV/c6cHNYXVbvl9CavhxWcKdKgUlYY0QkfCXXEvJWdaQhhSBBlu99o
zp4X/I6r++3iWFShcQdlWXshcKpysDEN1w5yVgikrQ6r15bxaxoPUjHRWIQbTt6+8otBfpk7ov80
FPWgrq2LRPrQpEiNBvWswNxRIiRHqxU2Op0agflui2JvZvuAYTWsf2pW1dyKMive6JRploU9bzgu
7QfVNpGLJpbFTFjFSpMVd0eaYXpuwYrjSOx1ay16UkJufXJcDok/Q8jd7OlswvU4jllVrAoT1ND9
4uiGl06OE4Z9rw1TkaIXPYMJySpFyVIuIaeRMXiGAwiiJDBl0aoU1yBRws9VKdViVvEvjCqflAhf
0IEIniH+tnDq+1vqRbVZPm87te8cf+2Xhrz7IXFXikzkq3ug+BsPaBGfOrzvRFYswAH5vTk+6CLp
bRCtbMBy4bcPhjWCGA4mox6c2gXCblYixGXyIf3PjoJbEht14kFsc99Fpa9mYJrvoI/3fizgkpAm
j0S9+vGYN2TOTUWmst7eHl7xaemjvNCCca0Ca6jAeVbx/0pFlS3+8PYvri4miK+2o+I0VtCRwA5c
VY70THZKqPUFHS7h+XlPtQ8pLeuvULkUr/fnxLcAinXLTnpQLimMoPypZg9lIG6ea9NemDUCJQ7j
Ugq8U6eGp5HgfuKdZ3W3P+qIY1ronCQYza2UCyR7PD8MkSNQGa8TQwyaLFNc7MTHKQoUimFgi9+4
jTF5dKnwxlCact7xAjXqm/E2QtqqeQqwc5UDCYZfoNO5Ndkk5BOg80h3g00jzH02EQ/TUoj886u9
PJIlBNT17XjxanfEiaxqnIG9PFoeHfwwFrSbhvlqeCzguKGsWwyH/M79XzE6spymoQiabLXOg0Z3
XgGMxQCv4vOeYACKiNu6DMWL7YQT6WWPm/NWN8IXcxe8rir2YCEjmA2o6rhbnOt1DAouyW7AejKt
KU7+3Bdr+jikcZor81+AJNCOzovaMp/veRMV5mhiO7DL6jccqkljhkhds1SbZXdxYImEBqhM1pCs
cFcc4B70O97PuyxGf6KVjSecCd08DHyzyhDdC3c3NLKWIk5o3JTqQYRpycL8H8mhzfYYXapMOJiS
uinojvkc61v6Sk1p7zHPSUmWMq6u1UdgbLtooMNZvAy6w0GfINzLe/E9q3sQe5PBaDdTq1PsUnH+
KYChQVAMB+64otZlrF9J8EaD5sZUTpXtAWaWy8CvZTXJfC1p8ewbfoIQ9EmMViEXtzHlAQqskuaO
puffJzm2byq/zvgwtuVDxzHiu0d9K6l8I+M3YMA7HoAfj1W9SMROJHJVw65Rr0MEitZNwR1Ybfs5
wJaXm1xVoygy4SylSBMMqqaZNPdms762I0A6DiAfJNiFa2yOHdRTu+806lqI91KQ+j8mMrLDZYEQ
Ar82swIfLWsWDdN8KOdUuB0qckHyZitngj+XZiujM4Gsz5+9K8Z4rY2FBnPfWEg+jciwP00mNVEn
+3t17PpYs18iuj4ADCMti2CV/8J8XMrdjEMC7VBKXk7TEBKwbh4Ck2NNuG2CukxrH2ss49psYx+B
RY4JQnb1mZUiTSdXyZHCTeksu4tNESz0NC7iViJ0Dzkv9EykpmdPN/m8kJv8aYx4oQrpgx0okmCf
QtdbLse1CJGucNQCeiRdqAeqaY6s5idoLGU6Gupztq7PX7SZnXn1iiFyGMPJiP/LwZB3DXjBBXBG
KHM8AuYsEz+rf22DJ+/323hdtkVFDYuU74GEzaPSr4E7I8hbDDgzEmqn2HdhvfBUyNPkjWTDsBHJ
s9C1tYlqf56UzXhLKiEUSIH7i/+B6D0UZjxftaX5QyZgpNOiAnf8jaBWOi0TTWUOEuBjCJTu4rb2
Vkl/vHPeXO93OJQU1PEdGqheNqRTl/LrYxUcledtDxkSQGYBlcYrGN8M1L/ULqX1aOuycsQMBHal
3+nxDe+JXnXWobEDZx5TeOyi6Ifj8R5lTVq0RJXHvRfOBJv7l+fMwv964BJyGdM8+1OHkOE4SG1I
PX5YYtrYDxux3TtBifyBDPisYjXyGDOPCmHUTV12kDix1a/HyiN60oRIu++7gBpDL9qSdOuewaqF
IZ0ywWeCvOJrIhUADZU36cvSN7p6ygncgVJoX+eu59X+RL5mx2C6LoDj8XdeZGLWoBBATIfmi3Kv
kViW8CkwuTMyEwZC4NdRMSFMPjcMd1hu22U/M6OfXM4P2xXOdiZSTgAhQspOqqsBJynvcp/MIrsn
tIyKIqxbun0J/lemunrFBqwuWkRBWZv7zleSnqavE0zfR1aZaoHwbOuAU8EhG64RLyET3WZVRSRp
vOFVTwBXGENf3tmD6UtfYEkvoGKzWaoXd6MjPAtzIiIMYPlhIO1/8P2+06f1fOgdjqYaQ6MckNBy
G5auUXq/9AGbvGwApeVJaRGuc7VGE8YLbl5YSbkAVwWnyP80D74NiWM6iU4KxTOcyxGue9z6N2Ha
FRzIhJjlslv+hBWRaNPgKTSX18V1g2v5X1QGSdu/vQUZR1Vk9HU5m79ViPqWVbqf15jRdE4HRRZX
Y/LG4M7p0VuSFR5pzUDYKuPpaPsNjizKEnFi1sE6jdzqswir0YQrL9VMiROorG6MmnrHjBHQ10gu
k1z4a9jrrtyQzl+7SaFjllmphfMEFKP7u/7NthnJO9nEz0sw3VIz7TIHsaoKjWW+VYs70hGRTlOf
vsacJLuVHGQf4Dz3v8c/II+3e5dPVulGMqeQlVrIA/XZb+YfyX7zorXjSM2hDE+xJOnFSAQXpzsr
WGZu+ja/tBYKIEbbTeNrc6zloE0qFAF5XqRMNsMnnVYRcwy4HaV4Y7f6uCalo+MJ0OMQffPKtc+U
dhB7xTD1iF8AFjqeyV9KPHM8KeU5C5FYzGOJsgHQv3gZalRLq/t/w4ys9i2lPBQOdjGzYR95aLEZ
X2hSHqVpog5D+cnPHDHdrDF931DQFwEX1PGOiwDGEU1lYOnGYqCUzNRJdqbGyX4CZvKZIv4FNXTI
AbInVDh9DfFOadmoUC4dzewHPddgPFBAkMkYwbwYsERLJYyi8o6FaGn0SKk0hggikHDJXnYBt/S1
28VMRDeGAzbB96ulFVcsewil0ZSoNYXA0uq3WbRVA1ApyYzC/R9ibLlHMKynVLyhI4FhIpNcI+1e
JTnSQdI9KolrpcOMLXZMLldBk81AqPESR00atYlK939J20M2FBoEhzm3fa5sj+NPBweTOXCqIxC9
h9WEbOS1mZhgqm6+K8P7dft5eAqbpyccjsNXmKyeJVgsIrfL4ZbBqTYuE+iYtqNBDzAbKfSvSln/
GAwO/yZx8rkHUFWGw8DBx+0LpOW6eDb48qsAtFfreouSsUTjUzLcDlGn82zkYpuAA20rPRe11yKZ
ADEkb/77JgJaS1ITtm2yFYqUtF2sdFYcCdq40lZYILso31+7Xz9C+e3OO8SW6KTY/2dMB606VymS
XMJo3UZQui3HUJPCOw3iAz3Z6mLUVt7BRRC+DOwx2fAorVIf4frWtcMZ6r9YT75jBBzmARidwNhx
aC/8hKX3SWxfB9zJn/xcTmXUiSXnxf6cM77PEvJC5SBmHI+hxPPexYOWui4dVHoihuas7v74b6zK
63ZbkJENCWijS46YvCqhM7lKQs8OruXrlF7MO83lGJIUlT2qaTcj+oofb3W0woOVspN2vNB25ls4
YAq/5ZKiHVLgiGQvnIRWcBLzmk/VLAkmk7Md8UBFgPkX8YgoxsAfKEKyFoNFvX+xBPdxBq/Sm70U
9ZdibwQ8y38OkeIrcDYSpXz/HsFshUep/6UXVvc/WMSuFJKxQjcegP9lUJ25YRmv2NxCeaY/1IaU
6Kx+EB+wrUFLAxsoHhi+gOCuXvejFSxu1ySnx8HKwYA4R4W1lY1viR2M8PuChlC2nF33ZVHXJ2nQ
DxarSQnqlpDvrVKLkU2no5WIDQVmbynt8DSAEWqJngB5ZQVFTPDbPjf3OOZnWb+g4ylAEOal1IXh
r+ahBktvSdSsEAC2ipxUYh5vhu1j+0r6OxU9kBmqYhZBF/s74/sJsAtGTaDVGape1/a59ZypC1nQ
a4D88MU3fMEgDrq0KgimV80qiyoAPyZCyhwNF3cNSAwyqR+CsVMcIkkiGwcGPnCdGLVm2FusRjW8
B2vMSrX2MX5TTJqpjhQcfRdfv5pu/zQAEnVSxZzlxA9KkeurwNCXlZH9NrHf483tKikgz82uYpcr
zmAqP173dzzYrKulO4X433vMGW3EBZkHDoF3OL2nH23aJzfyF7QGWCQPpQQEUdhsxg1x+qA6dwQV
m3+P/8NlNIJxzxtijOTfeJfd+nyUfR2ZCFanVjxzJSKuzL+Ct1zfEIR3ffngBmiuSyRUbU5bYQRz
IA/4fNLcSS7HcLapT68DmS3fX7pLI1HUuNDBJgz+k6VTYN+0acyYZ3FWskY2A3HpNtvN/2zik8zT
sOrrenvlS2J8NoyzpLHEbSeF0JF8jYJMPOCobq6j7D0IoLbYOiibljzBYuatKndGDJDPB+++UTuJ
y+GSDRe6P2f7DIAVe78um4Zer6v4q/qudlM3gSdq/mVXxUU5msmjvaXmA2o46Ez9uyFccZOrHDEQ
EFaFOh9cJI/8L09LsH3BU9gnTzzpe3Y0D1hpP5YfrRGI1pLdw4yzXFKfnHEyE9cOT3hWlmMxFLSP
6xo2+MkB2vhVC+Tq5fOO/otnFzBncr+pwQBjXDvLwEm22FtdlQ+qH3fsTIW0UMYVEV/bXwN0NUg+
FSe0yQ9TfVRbenHnro4OIizPQz66l6HvZtj5Kj+I+IFtpTmMpGCf4mY87j5pHG03Sn1c5cys+ugh
16d1BadISCfGGGHOfOn0lIAzL68iqa4mvxE6ls0GYHe4/ymZ6liKE8x/37jip2+IovIQmiabDtyC
3Ru1E7nU+eBK01YnsUxKHmKZPfvQpMmGtfN+aQPq5woabaJk7J5Q/eb4kUFczyux1u10U8fT2dG8
Nqkd2o5wN4oHfeq9lwBjgFOnh9+ei0Z3z9Rqw3zd4uMZSC7FAqht4ztzl/ELMdIuBxTSJ9jiUASe
w1WnYXBc9X+EZybEnUwa4ZaMczdCqWfvQOR2HPnAf9Zzt/8zyXW3QfJXBNDHqr5zLsh+fAoHi5aL
6exI9KLDetduu+CAaCC8xj1IDKZdu/QDqxB7yed6jOSiTVIUUer17bE5JwtDElWwpM9LRXFkNhj0
WY+RE2IYkH/QIwHi2zRrX8hL7ief0FH4m+MaJVXMltKIxM+Jof3IX4tyryjg8pyFE1QDmXQXeGij
Ns7vatC0noLvq91xL+pEOCRIUkyrmh9gw6r0w5p5h+dwmMahv9DNDj3zP8ZvLIo86jhKtpKvPKd7
09EPCG2ELXFpqIZx52sT7yKI31aeHcPZLyR5qUbSpdIuHnA68X0PpQi8Wj8jdJlbGOsMNHRITdCv
TOqyiBxfRy2Msv8F7uVyRG3FMzIxYkUfM50hLEsa5U3kiD31pXL3RwXJ4aTV7UjagZAg31hB3Ild
R8u2GEXmePCvaPYJUQKS/PSFf9n6gu3Y3Xx1yhQ+WqU780l2MklO608HvMmeqIIF2ba1ZZlgW5F6
6R4EZGB3JzF3PFttbqEwzjArAreaUVIh53RvKsJKyai1S/UWH8DXNw0RFueEO5h8DC8ScLyX5xgr
6pn8IOo8TWqxOLL7OffYMIBTgvllZ5enpdzNAvXuHM95eW0sUOnyMI9wR86+m1mH1W9Z2CF7ccOM
4jmjwPE2pgnO/oPnZlFUNt5OcMMSlscStgTIBc7vCbu8QHX7Kn6fqcYD1yqzNfoJ9k/68jmPJ9JF
ubiorVUxDc4NFYkQYg1XMoBTYrJgxUuwUc4eHkK/A9uYzvRrTYKo2N3lLWdpGoD7/nuM+8PvrlUq
sVeDz/ivIMG61J+DruIquOqTOB57hODWG3k/dZ7Z8jqmK1q7Vf0zuRkRoL7T1ArTKz5ApG/i6kx5
yPDD5MnVi7RXgoa54lfAtWbAOuD8AjKX+bfr0bGB4MR/YitnTd/oKVoVY5og3Y3tP5ClO+krsB0U
VEqZuFcS71qdCihUmMh9V1qg0cCxims1ouFLb193uyUr+ZwIP1UdQvF9gYh1nOKlI1a4vzNAG7c1
q2CM2NyTi3vRy/j5k1lL8ASWqIOZnvMXadqZkHnPs79OEOeBsy+e2QlQ7BjWBLZD+1Zou8o39J2D
ZS01idcS5wxp/OVmHgemnovw/1EDeStzjU/3yDdY66DwuC9JFHJ5Rilu4GT3Wpurm9USlRh0PYw8
4W8Lwuy9mAq1r864Emp9QafoOdRLyxMd+SCwFuHpe44o4PEyUziPk/E1qx+rPh4mkNq/j2K3HM9e
ygkO6e2oZi3tC4WL/Glnf6H4MzdSKBKc2LGEOhLAH5Qp6owSMMiWxn3qmXDtVKiJVhGF2okvP6jD
iv8JIE/cLYY+E/ke4P8OJpFkzQ5XLdiptkBoEi+IVo4PcU8GFCk052KfUWriliMWlS64tYPVuXc4
btUSo8QEuJseZYBdeJfVxyf041ZjjpPqXooo0UbIpb5DwAeRxwkjI+WG2b5dsvdNaHdQxCYY8AT+
jdKfhVWgS/F/mRYSjGN+Ii90ZU1loCr206UmQaiBYcuJ4G28kqNU84ZSMMfeI2Ha5kdJwt+29u2U
zQwiGh06Lqjjt1CmwbAVkwNib4NM1JI7VfUGxE3ze4TBXvScJaSVNM3nhGM7uTtr+jFhiPUYCoUg
OhqgqJxoWbFyh4dojGcgIh39AZOE0QL4cNdkBjvmCMFCh/ODXqVJMTZmj0w28BhmYRSufA3Z8x4t
X82anIQeAm9K9361F75Auxyqyhuy50tor6mU5FzVLJ0P2E8EdRWIP2Q28Awkai1hFUbzfSMaRWMh
/9Rl5ajLhoBwPBPGOXd+66Bkyk7KAlWlYwORkCNaPZ7N7Nwv2KWsLv4wvWP+NRY/7iB7/wHS2BzW
0I8n8H/LTzomvpGhndanUlOo1fzPEwsCxyhKiv1fNPVjGPRWy1DQmzfh677UuIV60+b1Yq1QNhd+
A4aK52YMVBNVQDbA6AcQ7UPWJOcWdL4sIRy8WQaAFGpQarZRII5rNoegkDyW/5uRgxFuBLamNHfg
yys0iN646sR2VHZjqnXef7iH41VfcqxrFT/COlqZWD3URI10w2efrp2fa9MOq+c31i4nabNAqn0E
AsLk8MglKsUVvrBe9HwiKgS6hJUkHU7FQxjVd6axw50GHDzKflbxvA79pxL+8c4xpw0OHPeTZjJt
lc/M1EgKXMMFlWPqKadxQgsPRk1sf/56YXa8q+JLUtLxi1TqYPoLhngVy0cLAz2jWU/7ia6KMQis
9I/gNrcDj0i/cS2zckfavnxdCQFnqAkodHS/K4JnWWvrWeZkR3yzrzlRVWVayVG+2yjY+qjjfHJ1
liwtLB1gyzoyRjmyahRv91hFAQ2FNW7fixjrnpUWqiUJ50GuNJ0UHQSPdwuDgx+/1qPF7tRDniY0
cFWTppHFTsYu3C0XfOiW7kPQuDzNgHvr3znndPrj902II2f7H8z6sxvsy4goC8VwfbBGgC2ZZXVI
gs0R8bhss40ZS8TOpQu1s25uAqOAMShokL4SzDu0CfYihXOcYunTloX4OdDtCWqyNrg5gC1KOkXZ
jMImIMxrpamHFmk19lG5ujK5+XhoATjBO09Ba4ryH9M27mPOputQ4FQaLnR1EqTOJIB4Ac6UudIZ
YrkDMHwazJYGIISjn4d51xC6d85H4YwXjMsDgUgPuBaq/6zL0J8XNrCD004rxZSIfs60JgJnO6nk
ew5oTCycQydceRErbNJMhk83DNTZcJL7tRBe0yTCdBp+ARYgOVKiobd2XrBAuqCwidvCwqAJJ0+2
DbIr8umW4LlGDVFjCw195ionMjuVc3p7CewrE6bPGjrAo7uTmjdhS4n80XH4EYz57NqWSLPksJxi
zKZEQego5efST8JJNksgIGqOnMIc1gtjmJO+51dq70sQRh/iXMwanLQJx1wdZ2S8ZLx/1oJCJ8CC
3thQQg/0wUWDzVgM4Wjp51wbYZyh0E70b62kbBtQKVfs2quYDOvDajg+Xh6l54BnC5oWBteK6xLr
hFPnMyFu5beCDYvxFz8nA4TVoqR7u1EwW83PgAp7Gpwby8Y8Dk6CH9ayO37Il4TElcSSwQgZh/s0
Qxe6wK/1hx/PNEPXIpr9wUEQ6tzm7Gh2KWGFCi4LnV3HgoU3DJILLPrd0/8oP15KxkFJ4mFIzhaO
MiXEz6BLLpQvkQD5Zvk5O2UwQt1I1K6KHDgI2RYuiXjdXAr+guayI2RcwOECpmXqIHd903xtN5M5
MQRqLaiWPKofYXrlAnmGOnOykrERifgNKEeStUtFp92Pu8lqAcN8XLdeQfwFB4fEOkhcJLfXo/q6
/yZlU60KSaqbO5AcQpeqkRk2AAv0YHthIUFNAmcMh4ZK9c+ou5CcmIT3g9xBNVrBy5qBACa008HB
ndFG4zMYNf55I/JYjH3qKqaH/bGO8bPXG11x9X0uea70k/yAQXkHKvOUYOgln7HQnv+ooaPPUE10
Up9q8PzbSJ2a46YJeOHxdHZhzs2VmlALkymXe0qYVpqBojS0GWci9WBGpiMwGVhRJxZK5qH9kCFe
U46tYpbs+eB+47hE43BT26GAANsit6+hg2/N7tlvxZR1Mxn3NAKTAnJk1Rw6dhEOymVrH3H/sPtv
+IGViMVEtOtHVnLNh/1mDIVp7O6NWdVeFKlIA5agBsTbLm84F1NQ6cJeUfLcOZwS8jzgqhKDcpXW
5R0RapE9nb8+X5oOeePEx6WY2c3/zq4nXMZMV5plYpx4dJUekfgzkiOWEzfuhOlwg3l6f9XD36Wh
0CwFqJYeDQHEJkMrEP2ngAWsZsf4EvLNVQFQHHvhAi8+JUc1kJB94yz2zjtj5gF2rDfj+Vciw+cl
vu4XR41zko7yk8xq2r5CRAYgKMjZZgDLI6fAN37aJpOR570675h4PTe5WzBKxVtDmi/a0Fil1LTd
MA1xKXv1Vsn/JKS8cFOlZSpcvu8Jv/geN12GVYhTFW2GGNfaer41QROPpaDV+eU9lKzIQRWikUu8
nW6224v5foM9VkYgmaTKKBRFc1YpjBgj2Ls/hMUz9xvW5QpZ9Z2uzoPXLcpww3EeAu0EOfiL7Xik
PIp8t165OBIV7gnDpfbybrwddZyPlhf9b2yw2ScnuIldYocYohV6CTCwGUkZf032s/ubfDkG3CWP
U/DqE50Y/cgUEbI9V3DMi3DcTfn+tXHPQnCczlP0hhJnNrbGSix9wYHhpHsYNVyFyx/He5PUDe98
XK4IYAM/qwIWY5j9X3MVOzGVjvLPflHQC0XpufO41lWrxr3JO2TNZPIoWZx+LUmuZJajQqWjaVH9
SabZJ5Uoi353tuNgdyv6eBtYkSqSPn6hmts4SpQYf8iojrcpAmzrJHxamxqBeZr1cCvrVh3pgMCk
NkVH75ulR45p7VrM8OAk8ToeY7xzr5rDj2CfWelqE+QgPIfZVCQGdyS802k6n7Y99Fz0TGNZur4a
LEXT5bYcxs4lOXfhRcJN0eqzmI/ThDQMFTrpV9xVcXOecCzIpqDdvfKzxmUHUKMptLzyJ4kaNs2u
gxboDbocjxMJ8Ypx3hNT/itzVXmHEnsfEwQeSoQtLNeBFWP3Q4wkpFk+NKFQMU3eu1ZUPQdPLfpY
gHnl+DVeW+ErhqwUE0CQBmWKUfZ8kbWjXcPh42rJG4R525FUqaCZbBA4XOq+i01s07/sR2YlNjxv
5HeXnBa1W9XFcc8ro1H4kF3Hk0j7hYM8JcDa0MN2PrGEfegqo4J2UOGQdJN/2IQpa2ZCbnsF+kFV
9MT4+mp847QRT425Z0zt7c3W32IRGNkOzgRIMvW4tqSDwkEzUP3gIrePmVSBEYAvRF1oOQf3vUSr
9AbOK9vL94siJ4q7Bn9NvnyP/Kv1aPHMc43lHbtG6UwS1tGvG131UIBsVsI6tx4J0tiTNtGvvaQr
DyWCM7hG1UEs9iEoWrTwn14coYG2souQvXtPmWRNJpHdNAvXgxmqJfCVuPY25jrO0jxR2iSXzhXZ
R1rgefkpkYXtA7cZhzGNxbNF4XatilgZcRIE0SS2kApJ+D+0I1EYua0d2ypk7ohdBaTCdHOE13qS
kQ+xNXPU79rJW3XXqKL9pfe4IVs0eSAeCNeVGdkfr0uTX8z9vDwUJk29k+JmhjBtbHd3I5NFKmyZ
AGaRXwKJPhDTzN/gAlpUUjBml2erimqNbrGddvkkCaFylQoSa4b6cZk5RFSBmWbjSN9WWQGz+tCP
R/itpil2wdAv2USX4q2CY3pqZYdg11nRgtw0YT432Ukdh4advgToIQFBC3JX4nB1lVDVERE0PuUc
3Vho2LKsgWMhssHzLBKkFHFs/3kpcTwtxnpDBE2sFnGBgjB3eBlmx+qILO8JdjPUYQ4qvpuTayW5
qlxWf4l10JHK5OfoBixDLLriqE3bWE65m8w0geQ0USeV9sm8YIonOR/nYB4jGIAeMMdJmvl01Mhy
BGeqU6SiMV9prts33K7oMACYEi79gVnskqiweqUEsOVDdIuOCDjXqq+hjC9S11NRMxp3Y4nzxuzp
6YRcYSgSZom8KARNnu9zkdOSyWHE4jhYehLOxx8qEme3SSKjI/1FuQvfMOOEyewPVj2E9IKGT73P
S+J/iohHuWuk7cKlr7BbNejIgTkB+W9nXNewB5kQIiVtefmvqijJCLh+ezbF862lXf5RPCQF6fmu
JInym+zjO5WCU0ZMjYqbdIxXa9h5ZL3EYlZYdDYmAuzfh2y35yr38XY42NfUFj35/l34mbdjOyoJ
02fUX3QFDIM6grZBhlHs90muYZFKRMa7L2KrmjmbeilaUVaHh8twnUmO0ehfgJQBQHrS+vQT9K3q
AYyd/EmbpZDUJG9pgq51wltoXRD5TkTSzcIx6kXDBOVmohdMHmA8h5NizpF19QKjbGNHavySr3jh
fV8ahO/ThA0fQoSY1gf/Xz2fr16JiM6RtVClfyp6XXCpQbXwrtOw6R7dkEmKdbgh/uAPGzyPRtVH
mnUg2vFNkxnMFPeci8+MJJGvlELa/EVYO/FmrmTRTeYy8Chcak/X/gvjQSKkYScbnqzCyiszRENf
sNkntAqxBN+Hto6OP/3fToRI3VDHcgpKBQqHKwqGLj0KaTLue8IStnQvIZdngX2cPK7EkxbjpT1T
y1WjXKkqK/D03x+SvdYkoB6tlngR1t0+UeB3l9Df3IgDGo2rqyaYnT1jun1skRlEATCxHjnP4zUD
WgrvEF9yK8M75p0V4izNEk1JENFrYSgBHi2MHY/KUQuTxddizRz6lajeRdc5VMmMt3eJsnrR4cj/
cpcnB4SENBIFbNn6sKid7wPub7JHv0rxNtx7TNZwE5svnuko5I6D1lcidf1k40YZ9aW4+3IHHZzq
malcWKU/3aZa/uS9g95D3ZdYU+S2U1qXdwsqIhI0+6r/zHwtDGsdgebytGdezwsySgI7DHT2r7Ki
3ZOrSuAO69jnFQZkIZx16EgXSW/uVvpRL+h54Lomg0EekcHKJdeTQDAv3gIb5N8m9wuuPYXSi4WT
yV0Tc7P5JafQDprhyPiJC2qxU9ACkB0BMl/Lju+PGnoxZghR8wkWLYtZv6Nj0uQKl3itgXG1jpRJ
5B3z0cKH4nwdvwH19ZwoahMIh37DXYyzDq9bubcHNycXkD1e21/8zl+ubEJdXZQ8FcbF6MMuh2OL
EzvtZUpfiqhbWxpv5K5cpdI+jGp93jWdnMiX8dSW2/jVyGq1xntYct61M+E8GlpNu9/lMumnQMit
1Iw0KQzlXIcrM8U1j7ZNKbTh9YrDvHXM6b4zNQYHKwVdS1ptyzp5cHT5umT1peUmSPo1FeznfWL6
+Uw+H38QrQPRpSAKGVnamnpQNJ0B4bKBv94ROv4fd3/S3Lg6X4BtyjVPfR/ljKF1gSHFaAJefKPy
/l4Sn8p0ZXeW5gJXotZ7DMBuPFGcVEwcaen7tirsXpjRlcML/PDiuYo2Mc2gN5vdnvecpy6b8odh
U0TenaTB8oCS0wsiUWOR1dncWObt2tFuJU7tIRPBoiRAUrFoaZWv7BltlG6c0XvCNfrU8pP1CjIZ
yQq3d/k0FlNOM9tb76Ua6wmvwZTFwP7xlVPG0YF60MfIGHtiUz9d48QQgKmR6GNdpOCsdypykwkO
2sE07eQ5lEMXWmaiIOZhbl/s2OXxOwKDhNviL2K7poVNHEPwUokPa0tC966i6hNicI8LJmwz5zcM
NtFimIhQPkAWHClabpqKTXOGENIAh7wyLWPC0SCpsKr1XW8WnmeqBbvDGAlnXRjK7vHD24Ra4nNZ
VBCUgvbyubgx8iuk09LkYhneYe0rHy+uULF1Zcsplg27QxQ3rGqO+VNixOnITc25dgsu/PXd50lT
0ZBBQTMToK3qM1RlG27b7YZ4bvzICM/3ol8ir5XGh+clGMdJBSErfKaAb30cVyYgck2O2dinctzX
tbkGdK1tXULdHBKMlrjiFUREjTDue03RJXY75YD5IbSiyPlJ2hGAgudvyoAptytLwEhSDMt3tVmT
+7AP7jVa1aKUXtfhFl/CN7KhMkMHFoJ9HdLNWzdqeUHAJQ+tl4jM1p7yOGpEXDSSBQB/g3HIe+lR
WpVB5xN1QKp5TzEimxsG/AGWE6i3c4IXyzJMxsCz+HZG+e/J/KLijk0H9jt1lSgYAUPLHfQk9zPK
SVDItu6kiVJELIeoIPmMG+ZrY5qvRweNKVEJH1IYhRrMqAtvYLSu8/awRx20rzY6CE9sW4YLECmf
mz0TUtE7DVPjS9hQOyuSMFSUuevk15/kSZLWNVSEBw9buSTL53uq0792fxOb4J0VPhZiKuHVW8g3
fSU8/x3wgH5X1qqEAVo2gsVcFryJUKPs/yZHB55kkJzQ8qeFmRAmYXx3XFbKhObp2Kv/xF/k20aV
BLrZ2imkyBAMI2QXByjy2JXnDO7MGPBeah6dvHEJVj7ZF5n0D+Yk8TrUplNrJrkWnlLNMj5GPdQi
Ids2XJxet1NXHT1qdapov82lGJAA3mZGBk8uDVC7qVnzxGcIB74cZEODcO89PPNhc9ip2x2Yg9eJ
OWys3fOtjvW5xyl1pdI9pKcQL4hBNjyOfb0Kn/zwqMheSWKvNR0g3qHTWDrB+Gfc7fmq9DIre7vA
QelXtL8Vr7v4E2R72LxVi0tFL0QP2y0wEGiFlGOJiuU1HOepD/BSdmVRpktrdqrkRN6geUGK0B3s
CQr34k3d2dWbZMd3Ea1RnQq6Lhd9z7CaTJsTlxVqdeCkjZhxZYvHuP/ma/jn1uwudOyozCU/RW/j
BN0pfjdNkeqDg2gjmnWNwTcIU/cUlI0/6RQAuSCO7cUdK+V0KndkzIOeiT8l/6CtShKhhcUA83Xh
3AXRA8c41GTeHyUwOWaRqwBhhw/oPB/xYkSrPInyepS2o40Yy9Ca5rStGxj1NeFDL8ULS5coZXva
E/UAO+Rx2W/LQczutZAQ9uhMXrXuyVedAbN87WA69nINXtxLOXTOy11nXAjMSgmSNngUxzKDLmvM
PPhfaoG/8y1ZSa3JOGBDEIwntZtrcBAk7SZcfb+J4/hK5nxu/HYRY38FW1vXtI9qYHWJCDOrBGUU
G36iymA79d/AvKq0uvzpCDLHv0d6pNCUtLILTNFCpe1SokYnRK9yFAOYI8rZ1vehpGngFafEHSd+
IefRpvtFYyg6ii2OYL4VTgqEQ5sjlqWHkSWG2uJga1VH+nhQk24MolvTqvlHhHw0Vf97wc4XcU/O
KVSOKJ/Ry19spFZ0Xlz76NsEFh4ynIMiAX10WETAXEbjB82pYH8n0NpyWG9RJ5gugGIOC7yx1TQ1
4VlhMcziwSMg/eki95FZEVD2NNYCl0i0Hh/jyGDvFQARYkpvfg6SysdaAfGEXGgAUt3caNqnvRJF
FNYRVpE8a4pjm2oExESrQWmPdp/K2muwm0ooXAFVhtJ0k2rMIwtKEc65gRRx1kXmqVjbRRPWkDg9
rm+EJlFcksw1AzuxoMqbu2onilAAvECazTt//TONCQqzJt70KsBKuz62EQ7/L0Wf0w1h0Z3bgzMG
Bck88/sxqtSxGy/moFP6gRAh3xDbPudzSedU9MO0DacguOq+IVEUq5Tm2b0DdrpcpO7XNuxuUEDw
bI9/EfpB75GSOt7RexkRtApH8fvmry4FwpaunS5EDS4Mn/Zmj3bCjsbuMzzfFIE7dfrfq+8Fa82G
rOZHc4zlzYF7vNwuSewwChmb9V6QMdJ2+sIcjmsx0lGuHSFDSXllZaF7Lu6Y3o+TCa34e84e+wLH
galZiXISN6xFi89f40ppLwCiRuw2Jhq47Fw67FtO4AGLLVWc+JFtqztItY5T6ccSW5GtVNeNbetJ
ZOTWTGLUeBlW/TGHULtf5CegHujabj8px3gaJpd5tf37Kvr0fZUiVkUnRH4eqZhQJWsWZ6N+YYT8
77lsCQkrWDwzfxscn0K/GXw45z/vKp4VSfczJD8LvK4U5xC4Czpr+lxZ2XqbVbs+V0/gPZwNijuK
r2c6xoDqYQsoKbheagZOcwf3jsKrTFTJ0Llguwrnn+IPuYtbRVwF7hi21is/0TdE8PREgXFgHCpz
80LVMm+DIO7wO7wkqliWwmof2KcHVOkl4UFy1J4gPvEvpUwYex5Vmw2r7FrzjLnVe6ke/gxMU73o
zNkuut+cPwPcU94dhk5ELsMnmiclRwHr0jxNnb+MrJV2YM6yaOWNUQ5Y3ftu3QGULlM5Z9Rj5y2Y
UUUoWjVSg+IiSIBNGOd3l83e2/+mrIx6zCrazxMrsxOuPcSeSDH5/YxeA6ZEEGzpAfmUAmsRbbTF
zCrvbHvfiDZ6bZDZSVhqfHofVWBJtZK517Zv330wgMCQd4/rqBxdPJiujDrrWcY5w7eJJHUMWrbf
iUVc1rngwUQhozhMqXes6VghBb8SDvgB3Sar6PNRrH6nM60jd3xPmHA/OQIipgpwBEehiXPL/l8U
YOGulv0k4ad7nlBLo20o04+51XfJqe3fMFuPLxAa9hm5c9jJIERKfejF/4mmhyUyI2ybjCIvMHr1
ZssmZ/HoDL9+R7OOovxj8A1Be6T2tvD8B1xW++HDvbBkgyevM0vbPv3DZm39F/z8x9C73cbgeNL2
USmUEu1imeVh/rGPxXCAuDlOKMnVKMi/YyG2OGJWUdJb6ZJg/lyNr0noYbO92zdVfbpTEWBji3oa
H7CO4pd4okMRXQwNxNr5HyDjccrKbJLvRYEB5vJMLEgvpt3H+CKP1kyfgBa/iH3UzaT9f8Z3Q+Ye
Z9FUbAvucYbsqftGDvoMLjHPtdQ6ND/GbgtvjZw1DaJWH7eRVj8vP8D3lhufeVwQ+bxSMLheCShT
Y7x5gtGB/ZpNvkUw4b9zNWXDHuSQRm2NJOHMAO8Ek1S34FdSob2N+NksF7X/6BbU6WpsXzLXlYdc
CGsiv2ZKgHRO01XCPmQsyyu6D2GliAzCkTXpY28HmGbUQ2PuF8xMC4gBEW55+xQeIwxGEt4jXOLf
x+XppTextgzyIpIdRCMiGpe8JUfjrWPnBr4JWkmZl71XsvE8/TFZwMRUN68pD5j8IMminVZ3N366
Dvhgp/8GIaQjuJWnOmxrA4dGsCCYCsbZxYwgSS3YK1T/m8PtCWEdi0WzoJdHTP8IJ0T749S9yswi
3GEoidw5GebgWjfj8ENwvyC5p7u2vOLJMUdOvMHINbMXBYBu3HhwFW6MSnCgEmaNB1aFgGqWBZFt
sQlY7Sg478rInqmlRLtvl7019OI5QmejvvQFtv7TAsa0EpDO7zRdX6ubZMD94Bn2qbaWnERQF3IR
dUfjOPRU7za1jE8OhUz4BVVsuTloa069O5iBQGFZ30os/hcadV6vAcoOGlWhBqXvNRkygRSL/m3V
Vu+VMjGCV2MHz3KOg+NfRQGswTG4qMZkhjpA1hXpWKP0Kl//UknI2TwoWv8c7rhWE01lGm2N4x/k
ecYdLfMDq/pOpdZxMAf2b2un9aJI04gKigsuUFfop9Ndg0E+e0AL7L6vm4rgsnqzMe8gxx1YQRAy
Dlt9UOFM8/9LCN+tqXN80H/CHzWStOnwWPUttj1X0pt8yis7kJk+rRyIaKlweX6YG/MNWMulht0H
AfR8JKGMy3fGKiYv1OyT5rXWWGvs7RbvS7q7OZvRwZaDLqXqvPh6pJjt8kDV53lvOzxnoXvOmnhu
TpMaHoLIPz9bLEatmmnP8n/kvkMHUpg5rM3Do/4/rtQxt4YI2IlZp9+k+CVMRWkFrJOhDjIH/U/W
gW5Nu84GDujyysAG/7vhksHikCyUmWxAwpedDTie8r54P5VesbIlV1OWhC6vpxTD5tbV2XDF81nX
fS3zAYj9RZjliPyYfjl7f0mQd5Pf3ZElsWopof1DiBd2ScJnaG0ZI/C4VsUHz2GBlPR+RAStbSHd
MqGRWX8mj6fOsyh83LaYiXbNFt+FdJlMCaV+rHmLMCWM6YLgtqIi0FhozjUK4UpBlwRU3GEYIjtV
MqxKv9umG7o9npFhaeMynI/BtnPv1vdDWQwSqBKbzdLkl1UkNJuPG5xT/LYPherWKgmGA91xxKoB
ysVCocoEPBVQsuRTkj2rG6ksvPB/rSClHkky5abseDiit9gzuE8wFDbrmhSk6tzclUTX/3OXvVuT
4+xX0hpX5k38hvwNJuQ1Lq0Y+hM39rylGx2FU7cD6jfHjbu8nwDWuv5m8pQcGCqRqBi2zddZB1nv
DHsm+nWaw2NVgZRj9jukWOx+05N1KElDTiAGt0PJfYVC71Pnt2Hg99W9dn8S3CXHfnhnuXc34q8Z
Gj17jsDCXmZV9IEgcOPUup18jY5n/KgKcC0qfqpxMAGp1mKjnpQx2hKi5aGETTGk6G7MYR4hEFjn
oOKbTYlYPiMpeNNhNSe85/AfF4c82B2tR8Oui1njMF0s8uJnTRUe+CaaBdvOxu9ianfB9qzNVSkS
+/+xTF97PbMqGko5C8+I5hA/sZO1hLPaR0TxECY20Q8fefV2t856IfxJgYk2c+xFN07qYhzwEgXl
plzMoh+eLK7bquErcBb5oVM0WEeRKIq3EWEaPfRXwqIf7n6L1gjNmiwB2maSlDAA6KxYYGT0BrRc
ajBaE+e653FV2mqIXE+kyJ79M1T1u90/WWqHosvCwhbdobuCvXlU2tEnMTcvAP2VhL6z6Q1YGS1A
ExSFBkxbHtgUKEXMS+hmj7Jm9l5bejy6ZtfMYvG1l+Qt1dg5QDOpN5r5cjgPeuw18ndWFKrqpiLL
chMxaFe6Mw1od5Hx3rkkk1Ouqv99p1m51WtpegYgheNZHls8FFaKnpmJB2RazNOkztO+4gHF6Nj0
PJTbCmSWO5mV8FJQDM6HAsnn1ahEsIUhQPGI9DqxuUR0yq9vkWzdOpDJN6b6lYeBf5kZz2V83WDS
EPs/RFmD/ewnHja95y2fRHo82j0X+bxHyvCYBXnOiYuHjkHiMvVTXU1uVTtjzVbj+vjStMzN+6v1
VADIshGETMhZ5WaVekAq0sfgTc7wCcwimivDl18irwz/9lHsG4crZgmmCB5aWkaFUIWcQ28U7f6k
9t0iGt/OSs2KyUcVDxrnSglRWfAluAMRop/FKFDMGXHYJVloL5Zh3V/h4OSf6R/PU3VH3IAoNQe/
/iasigl9YgFWViBbdbhk2Fqi0iK5ZJa9y2sKIFMGnoaJQvPdO+gMkjWav9Cl5E4R0Ztn5OuzN3vU
lbPd5VFL6naoBIsR9u/gbaefKzXtvw69YCciDM0zY3+C+eZg8H0c8OsjlMITO42PzD9IFM7p+b3F
tPBDoDmwgjmv5TapvwrKn3AORmr++JlTrJcUV2VTS9wXUIFjfrT9DILCaPJpW+rn8ffJXekCUnk7
6mVbhHUXF4XlIzgRruWv+gvmx+XRopfqEdC7DxwEgyDNdyL2wSrQn6ZYriHMeS6eFdg02Ss3hB21
g6HRk9olsnhhhHsfxb5ShzVELj2nRXePHMeG2m6BmzYsFnrfyjEMJYMq3EDqukZDhKhBHJpbVru9
j+E2z3ODfUq8ruhrBjPJTFAqJQ4UzDbGonI0jzOXDi2NRJK/EbABeI+PhSEXwzpK/V7B/WkRtYpk
2rs/4zQNtADc2m3XbS+uBxce9xJ41MeOvs4MEWoxtsWtZOJOAioeIwx1BXA/4T1j+F0B9oVl9swd
Ecn8ZtReAXy5gbg5oodqlKODGOktfxYgOv89yk7HUS5bOETiaoKFwyQiNRIP51OwynOy1HxxAJvv
GY7/zWQnL/5hEdsoTOCvpwI+fGz8N4uhT104egaGxm8VNTwcNgtr+QtGRlR9e/ZXlBHgg1DJulgR
tLofmwz9nTcK71HEqK9dMJvHXO/Gh3bM5Z1006hl9sUgS/dSdf0pWwpgM8M8Fni3eW+d2dUQmcgu
Cg62SHEd7szCHjqszRbnHzGb93M904usWahUP2hivWivG02vfJaDsJesjauCj+oZZW2o8Cw55DCE
u1OuWfNLB8wYUAAbjS+qvrZS8vBF8BEGUBJW9b8yCzteZ/ldkXFq1Ql+K+2xhbsvxAQWJ5PSQpwt
kLSOtj/oeGCbNpoEN1Fj+fMPaLgIudgr+ZfyV3G87SUUtu05I+T8yPs/1tbQGqX8qqIqPTc1UKO3
7AjSXL6sTyDRkdIv5h0fpIim5cGl8N6PsAhvhMu8cYpYuAhlbzwSXYzqn988Eeqxv3/nxulLy6Tg
48HIXXqrBNiS3h+MPkvktm/WE/84j/3/bQ8Y6iyaRa6NHqiTIHVXCj8yJtvcEOw90r0C1yl4MKvS
nUMlWPe6i6rHLi4zvxPBc8heCfZvVr6prbLpnC7Ru3ufpdPA8H1MJShaulaEEYsOsCQX847pyO2x
JlbY2QP8IppyKXlLXun1DegPIimm5qdHB6FW9ymgoWsbWA+VVBnkiOAGE17oddM7+WPHUQl7AA88
QGm2mcw/WwZt2kJVJ8BSWZc2GDByWU7wYEZJ2HwHDlWBJUPNdN6DqcS1PtY3CRJozy8xYjh4B9Wo
VTeOOE65TlXUfkAc0s9aTWhPRz93hcb2X3noz2sxVbetcgVhINCieHgBb7WtBxTBgu+NzDMKr1qP
Rk6bC40Ql5/r5rAIwUtgLZlBNLmuzQVR3vf5bvvkj6+O5pgT+zCwZCKfAzp5VJQ66nxxdHrmq7B7
1g/EkMLVbZP/cu+AX0B0MzCp3JJpNzmsTMPExtptl7ZzNMANef8sREQjH6sgybcMQOVv5vmqVs9h
qKDu5FbNKV5Pf/g14kHe8DvwSwQlgBOtdEkTxWYutWaG3L9JiGT5NdqTJHzCqAyxilBwJB8Ab7rl
3G1dYuNaemU1Qe3NPfrU1TRHBhjoz3xVSAjaUwQFrR53E929D+rQU4ETP0mpPa+znUMNlfSHWKYz
L/KUULiUFUhy1z0OfiSHtXFH1kthQAw4AFncP2/j5QYNpuunJIo7LeDjGEu9h9hEAzpd1f3vc/aX
It3KnfPHnOxFDCV0Z18YNZFmezDby1NRPHeY3YtrSxbc/hqN7Ri6KBrfqitwE6iYpxeAL2OuSdxW
ThfakPVrI01fHaZsHX5n82/GyPiiu5kkFlRVs8+MCpH7dujNf7acp63MgwWXfQlhFjr31ABK+B7n
kpgq0XkP59x9WXnmQwt5gCh7qgWaV5sCSCvDV2hh4FUhxIl0++VfG1Wvkp9IUbZgB/f0bHlcNwE5
idBZAsq67vrtBcVFYxqS9r5JShdp4IhLWQOjTcQfrQ/PQopKkGE3Kiwwb+rmb7AmsKtUZoUnpWEJ
nyTob7UTvwxllMx6js9vd7Knr5QW/wmj6llZFj7dcTuRWfHKT5osO8BrXT5vSAFwpgFvFFrbG6oU
ha/IrE19iFaEGsjZ/l0+/BJisobHk2Rz18UrGEpMQgqYwJzSt3YNj/6GlL+EU0SQ6J1b0yMzqMhk
Ki+HUEblC4c1kHpXznOzDWPw6lWpowAB+rVw7M+eTjuuhNxcLA1TOHpYG7/M+vGl6ZIg81flaCbs
Ok/GE/yRx6m9Zkrx05XQIFZg5H0RQ91iZBlPiSYC2+0fEtx76VMOx4Jhq637OcYwTXa3EfBtHLfv
Ov5Pwe/h/BBS8t4o+i5GTVgwOmxOPzp5x0zyikXGoPIb+qjVCUOSGMHqIhq7frHrnY78bKzwkrkl
FwY1RlFd7U0szgkFHTvjlp/2D7Zc6AMq1br5q+vfljvfpZRFr5pkFF1ltwgj64AD+w89zzBrInoK
ErX30GRM/5bQLqkVPOKs/IN3odSUYWE3LnSA2EFXuoOUmGz5rK9WoVVZAeJHHt0nRS/94GojO6Zz
Dxs6iybKoIlxfFypwduhegIf+KOoquAj69CTtoj2pnU3C/FFlOTOUCb6j0DveBtOLevYtpw6km/W
lqYdOgObl3d6+et1O1WiEMnbyTsHQ8oBUipKSjr64vSNkQkKuqmPkOSlmIaUO0vFT9PA5DtqPlbX
1359inrLLDyW85QT4UCEILtSGZ4U/TSHL43EsT2d+M8yrqdd4uuNiRBd8BUWvrsJTghGmu8DYaxD
ODrMWpL9sHCdBBLX9Jj8pEAdqvJFMcwKVr1ltd1ZtRieFuZItvmrzpGeQkKtP05CKwbLgIU3xSkv
Xv3jK3+b8FbNj7W2W5hNGMl7K3mSQ/0az/9fwXqksKcuAqxjK96xvZGCrViCsbT9YW6SAay3/lOT
eStfuejkqv1jSXCz3il2jLwNFSh6FkYe6THBn3DIE/aJuSjOeXv5MzYk030lZ902KTrgVI7kr0cT
vA4N5OMBGW70gZ6eK7wHlRr3YKscXEWGY1zAcJZmB5uGKXFA2zKkR9F+VXWkcfElK7uBilg15GxR
rnIODoGgJSeqJaJ6unL0tK/Z/qsjfDipbzkb/x9ABonXMB7hJPjTidUiRxUB+Zkmml1Wt9nu2/xG
7X5MGLVGYGB/ix8DgAUr4qXYGoPJmTUIaRsri0iq6L/UPSD2zGBZOH/4fD53zcdWusr1fsw3wwdX
sihec1oRJIpQ4LoAlYvl44KIjd1+otTQeZdg75fO+0NYbwZh9EOXJjan7XYxD8LHkCRgGk2/jaC6
vmEwdYK8a6dpo9iwVf8naw7sgmTIKn46ERwy/aoRWKZop/L0tyRsCg2r16iJkqm8rPXLg7CWlos2
Va/yVDYjHalgA28kgzEThtqNG+XooeO0waCA34KVvy3b7R6e9iV21eoNFj+E+9Uc4HpoqhSu/Fn2
QzTZF2EeEGsZJ+KQooY6lq6GLzH15pjkPVROvjzGEZ0jLXO1rooBlwN7dQSLgVh+alR5rqguYeSp
a/1XQH0vRCrfF3blcbTwwx9X08y3PAQEC0//tvtf45ipH028e37uIsOHH6fr3qrUULtOVDGlYx5f
55rVcUN9febPy++iw7+819fxElyZ0p1JR0R2EsEB/QOd3ed67v4JPSld6CkqZnOcPQQpRA2t1qI3
f79QKcx7GVXx4UnR7HKt8lCsAGjlpGHMfNeFdYTl+lyT1vEPxZ+AoEaMkLN0DY97zyyeYBOPjRkX
MDMLADU3gGY0BNOWblPfQe3/BIrwIS4atNVFax+5UZXQ3L7nMDutFDQl6DUsPJ+fEM8FItdFLqC9
+dmqak+Z/P7tBgTLFRow04UdtoBfZc++S11K78w+/B6m0mzEhUkGideHLs/0JgW46Z5ezAee140U
PbhecKNEMqSM8T5h+jmXT70x2vjJLrDWUWCDVV3a6jcm4YbPM7HG6ooxOiD/FUgULze4JbuB3JgP
KfDugW7Gqlr4Gh+JfjBpCCWL9Ll9Pmw3F4016M2JuIbY/AQI6WsomAyWRdQ/Nr/sXYHpAsL1TFxP
UQoqgFmtayZKPC2O8Tk1KWd729CYi8dHKpZ0jfcAa5biiY79w88anEG4mmH/iTtgiU1gw+TC9QGS
xKf30pmLfhPAOMQtu+ZfN6dmcobEA43zbXpOk2gh26hYcSyU7owdca9Pn9UQ64lktyA0lYRCUN2q
80lMlVP5RxM4KFgpod+Rcl9fqrZP60I9F7vWotvEb4nZwbLiGObFQ8DpIcLupGNg9KTynZGglN8F
5mUocXUCsfbKrchJ1/653kVJH40tK62nX/ICi4HqD0vrZLWlKGAFTxmhNdxI5kMD8iuC5WmED/b0
fxRQQTfiOaNwZxkE48m3AbngTnYudtwr51ql03OoLcRBH9oR7nCtm76aU5geltL0DVrgfidhP4kP
nY3EFc542nVPbEpRHbfwbDkGAbMpZtNk/OJv4j/dmwBDD8WBmkYzv4JwmKHTh6kQg8QXSBejTjTu
FO1vN+b+pTggOC2UVkUKeBSs5atppAtc9r2xbXT+zaP5UhI4olRJ1iPiHkzV4fWrMqQ3uzG3LL9D
QbLEZjPyu7ywKqL/bX7IDXlb8Sh4/tOJGZL0r4LileGBktVPRUvQ+VGQlsMB4Hy2ywGPL6jiOvJu
gfygnG5mEnyHfSV4qACl7fnUJqZFd1TN0DAST0mVDvgWa6iu2Y7w18tQLt5z+RLUSDY0qb0mEG1a
I+O+GCFUtorC/uB+4VNjpT3rkqZjx5aE6n6X4hjRziJiMX/37v/RlfpHJphvwv9WhLp7Sl9pfq0l
PXY5ApO6SOSu9oUn9Gmxpo5YcTW1HdvqK1iDiVI8s8xVkQAoBYhDJexXnE2Eb9hGabevY/+kazqx
p9Fw7sOvdHcxo+NZloy8FSe3Z0Yc676bcQ6GwfI6WofI5jyGoLM4sNxrCUJopV9IM1ebC3qCf/4n
wOALx7Qsrc3e64FcqxudYUNUlf8QjTx+F7bcK5muL3KgfIfkRo+dkBn+K1NkPVMZNydN2hPC18xm
zUT9KOcMC1D6OeIAr/4GFUxTraLhZMjwgSUVtSv9vRTOKBYlG8GRZwOzEfF+9uPlDa86jkLuHkV8
qMMCtxoq7vSjZGeJspS4IqavQe0nfZ1sEgA3hdh5a2qhWqNUmCvWqy6dK9ZJb1q8btStrXUzSQHx
BBGpnrwkmTlNkHnqFdnVJ272W5iHp5A6TEPbUMEEbxdT7HY8bKVQHgGEJ91zJ7q2xDeD2fa87tD3
8Pb55c7qwuESlb12B7f7qy3lZpNHKNh++md8NbVEdrqHgC/oo7fk/9hFKOmBPs1bML1+pOMRiHAJ
2/CFB4QC+8TzWEBE3z3WrH094C/B4eC2hJeZ/R76Q5EkzkZh2DTnnctk202jDK2rOHHHG7hC63uJ
+i4DbL5yGjcQUR6crYEC81aAXSlrEI84u/TPJ0ovUvbgGqPLef5hXQrQSeksF937P8PQWIjq3zr0
MGp/jRRZlqceKLodpeAH0gtqzVUa6ZosiYWLL+p8KjG9Q5SUNYkrkwDT+iV29TMHu3Qs7KRPKn2S
/aKmjax4pK0w0DMMPwXUT67+Bb3IzBsMcjO2g2tqZHvOJKJrdilrfL3/qLhAaYD0KLGCqu1QXEBS
5zHrgURv1XL5jK3VJagG7tJ8+edWnAmISD5iwmM61siIvVPwdLacidKRtgWy1HQGGIl0O6VaCqFW
fPGW+t7ze9hmmOacdD+rmWq6b8nRk4WHCCxDd7Tefe0e3IZB9XIWDIIM7pvy8aLPeUnt7I5GQq2U
fX70qLrtHR6UiQeTqjCNtaqH9v0CfLBENHnJJFh5vCtbFF1JHt4PWQz7tDkTZ0z5t5zxSiPVTOMi
Pg8DwsKyu8NrNfmMek9mJyc177uCCcHlST7vg+dYcrUQRkOj17cUAzQDcA6EbrT5gxWMBkQxZ9Wf
ufdi9IqlLroGamiMeIVhJyhaLLETDr5zsANaGp3YuZnODesiWqMTxDFjTPyrZGs/RX9H0M/DuzfT
ZMOcjHOp8q2EsYMGSiKRogcxYsvRjkAdz9ezO+iR+OJhfT8vSQLiIkY3Mo9rOvZWhTLfgAz9HY7f
J18RrYqck39i7McHq2MrHs7Nbma4zbagYY64DfeyNcMZ12RNBVuO/mgtQD2aZDA78fEOMBRyCH1l
g+OH0aAdUnuC4N4QY3lI5lu+6CzHBT1vyDkLGGv0xAGA6sVci8cw0md9qFwNfIqSLKS6oGCofhmn
Du3+AGFRJADwj3QMojWf14C2XCeLG8VPIgFEZLs269saNUPMOwYZC2XxuOumXU5a2y0xhEorbOOf
rHyHU4zPRqt0H7u9ezRS26TieiubvhRswfZpcRxUZyfwQvg1WvOlFF8bKmUJ1iU5zdv+lpNr7QYe
KCLLDZB0GgjVIXgQCq5Y1O1TNklGrowoua8pxMatEZV8h7yFQuBqT3xGOBSD+i2u6HPig1rw9QHQ
aOW1YUtZ8F290ECg3P/MywCBwFo7cnYAPNSYuUQR80H8p3b17GC6cjiL4kP4EFziy0i+OG8GnA2Z
+tGXqDR726ecxb1hijp2nlN5WbXBA4Br5gLIQNk5JoUANYyI0TFKajUN8anL0YJDkXQPyeP7JO7Z
c+JhQrh/ookbm3QPXmIK896VS31NnUvmPl6KYtYMy9nA4Nd6nnerXHgkpizHTZgkCZ5ToOuzzb5O
jZsYLaU9mtVvKKaeJZ7YO6tsiGsGfDGcfj5Hkfzw3lbZ5L0+A/sf1APCLpmwtjL4qhlNfR1kwK4h
Zx4lRQ0TqDWr7QMyLeNTXWdmugScgks0bjhX8rp4FWYBjXmhJFaf08kQHkW1OFQve0D8wukxlEWu
kW5N3V8lN9DMReJDhR/pgYpsj8HrcPRD6EVK0OeLjqv3kVRHuEr4QDCcFVtzTgqVfnbpeiTAVNla
5SxFSlQSewY1krLnnInkP6BcoSiK4+O6toFPxGIQOkqeagHr2QCc133ATKpHYGh8Cj/7ZgmkPQ1q
VMYQCFTzyZRyhA50mD/wRLm8vsTBeuLlmg2BIsFlb5mCCY1K46nu4/nIWDoUxnPOrSCna0H3Oyvf
+9W/D0up/RdjfcCa3iceO6N1ZWua5uWuIbmwtxL8p81FaUqRJ7MrhmNwHnhCOYhT9YS3vyhFRWdo
Ht0Hq0b2flppUyAv2wpVgyO7Pn2n6tOdUjw7i7NXXVfgE7PnhumF3d8jbT0any/wfSsWvGWutysy
zRNa3v2PthUiey8Gs73n+Oww7VWqe2cl5PFnHXb9TpI86jDJlBiBJwzU0clHYxn2tOpkwOoiDFuV
WvVhYTGDK79CKEXVxgpC+Uxhe+P0cwcHr0z+/qrtGcGE1+qhhoC2QO/tkLpic2yZj33ExzZeaeLm
2pem0D22P4Nzj4Mb+9oGqQxa0jifMN7IMa+qdLV5PuSfpV7QzWfLOClGon22vtWXt+Ym2SKQBtd5
GlfLEZHwRhVeP2RDCG89M36MCinjBJvwb7E9xXNiBmQdJ+nZWI5R3tIEOV5+mjGcOIPDw4W5qIjl
Ee76pE979I4j5vJadDPT1N7tCOA4FnDoNUFUpi8MFq5j+O9UlHZENo2XRWh4SIAqoauMlJtFe6dB
Z8l1m/aUpjr+//yxGM4dTUCYOcwPGG4U+r+lziVQzKXp+cmfJXR1nsRrR5Lf5t8tSNgQfb/aF+86
hlbXzih2PFujf4g9DBvpS0pUufACCq6q/L7iUZyKBJ1UYTMJ5XGwHiJei+22JCa34MdcfbC1DSa1
fhABDCiqKNia2fnCsfoB1ch4etH9SVes/QhaZ4HzrDmE44kvDz6ChfySLUnF5jzUZSoxw25k+L5I
p70eIRYP14S0S/CtJJqPSEURen3WEvqyJqLeXw/gFYhvqou+U1bDZjpDG2gj5MY9W2OS4MYfIjra
WuSCFPYo8+BwliTtmPgxst2YearOn75K3h17dNItsDKa4fmdvRQB4jpladikxQ3+nt1QKYG9U6LM
HSs6JO8yeFmCSKtEzyZaiCebFd+PCF0pfo9WURqHlHT6pf+A/uWjsDuDPyxilRB3jm6OCy+kG1ef
N1UxZWj4f9PJwSvd5wq3QTBHSfbVM5HUqdsNITlBfZkcHejcMgPRnehzgAKnSlrGzKrcXNn2Q0vr
kSCs2ALY7liprjTxXxYa92y/CRVcMpvEXnpaotNHhSDvIqbZeYldDXObmzgLNXTiULVcVp1avei9
ftHy5idj0hSVHayJbSCRTMvdQmsgBW11Idl6OrxjqYFCcn0WGFup04yqtgMzVPXhdHxZkNPYGWSR
S359zPbiQ1KX1zwW3Oh6F+OI6B1eIGWBDGYNqyxVeqY33AVvdAvHicCpfBXVET7F9aDBsQUSMLYH
ijaPTdnouo5sH+VmrAC5HPyZ3NLU7ePLQfbM5D5IKnh36N/gtCrQ1dybAftTgqicCZuEfPh9pr+Z
YxnP4DZ5d9KGbVTNrPw7oQ1Wi6yFmqhT9Z819DmdNrMShbag77rSdB2PgmW42d9FB+yb763UBkPc
p+ssRT74gj3RQjwJ/BDOZVlXI7+WNGp3CkV7jpInpniyYhhUTDnS2whIGyZ72xUGowuNs1VAXyEi
PGdm97Ry/BSaMrRCs6ClUexRJgN+Hu0PYdfCntK1GydwnX/WuSdLRDBWSLbJSac/hYj1xCWOb/tX
4JLFlGNFE5fhckWhanvSX/DZ2A0OAciLfh3CYnSOWvHffXtkGzgSrXQ4HjfBECfjBNLQIX9r3uPq
OU/f8poo+Y8ujmsKqHWQc1TUZzFJBDMINjjBdmm0fnfQqtqQBUS2ykqrMmwdK/0pqksIj9BNWnE/
V4g1JiK5mQapuUm765E7za4gIVegGKne99xrdF5a6srNr7V7ufgeTwpU8Ud/NhHB765EpympST8P
Aa+EDqsZ+eFPMGhEteXJS8U85pTjQX1/MEH2Fm9XY1EKwlmr47BBRc+yT7NUEOiEL+OXeAQyOCTA
f8071WVvfX/nJfpXcyxnfIdx9ehnj1JW6nVK1LLBgE7WP883AEoRMC/NpwZwos1ooXA18nJqOyNO
IvHKoCAD5K3PXxCnZdZXL4mYpzb7yrJoqczO+NRtDB8m3YgW5wsi3OGzWYnUEb5TuPQdPFpeRCZW
1msfYAM2zIG95WOahi0Ukq1El8AhXbNXqKv/9YFibIuIAC+AAAtvZ/wNoq9PW++6qQS+CCt/S3Eq
MrH+fKwQlZ74ee3KnzD541a3bWWGM3igX26ziq07gx3u0TWI+nEEEXbUMu1ZINr+wybrstGxizlw
FA05FN76MWtBW/MwdaCCsFEKBeu8doWs/eTfMX/w4deY3De4CmRGozmX1jixvucTT51PuWfbjMZX
nK12PzfXpIU/mw3r4+lx7Sm/UWbI6mMxOCz6zgMcy2bM9GDl6CJW6fzXkVQZpKB8y055MWtfmdd5
4hcltmR9g2o74DrElKGIObuDXZ8Dwgr7PjYnIAstWVQbI4E8u3ZK1/LQm4vD8i2HK7MtM8GrDjg4
oBsL+3c3zWPyW5l/NipvQE0w6Dx5H+XVjQe5wJB7EkzT/3kSreLKLj76utHnTGJsTiXzVvE5a+Eo
pCsI1wVh/EwXQEBpScyPup5YEnhLcra+ptKHj1/CgXb5ooUCo9ZB1vljF+F2L5APDHHKdq3A8ArK
el1jtQSOh+GN+EEJL67F8KVjjJwUZkyAA7QzJz/VhLcG/rZmLzaaDvfWha2t4HFDXj+fEFZkWwUU
KQTMXVvpdv6BwZmT6Auy1GsMaz1ny5dSOK3EE+RimnqXn8mkHlI4gQkcVMSXMx3fdgz5IUnYoV0s
iz1XuWrRJK0Pty3CdaP8a3owo6fsTIZYZCIszMGz8BVOnN77bn8tBqxCfii8xH+qsqF0CxkXEQOm
cKTP2HFsJWQpKepZbenWwBhd9w6WBVwubgy4z61idhWhvC0qhlyn7XKCOWd6LzAYBqz6WxWj4hwL
PsxUSGYW51yV1wVebtjPGtDQSZYntTkoXwSfBve8WiKtD4utaM+hloB5afQjYF1ufbPXt5me0gj0
H7DDwbLK5BYlO7IlqVD514zHpc3C/raBiAG3ShnwvgfCcA1xxHlzzxbmPS+70fd8xT+fW3yaP2T/
M0HLKRVu0e6SkO1+TUTYG/MAKAHO9jcLaHOcYmM7CEMwE04nYw1gqMf6F+RENiO+eT5ZWnQaRZVt
J0il55TulgqcObo++jgvStfeIxEBTK4M3rG61g/YZOZ7Uuu7ANQgw94q5nqR2fpjufRUQNqTRtdO
I4BFjVtvbAfX+CtrVJdBvAfpRtwcF+YmAoyZY07DvBr1I75tSMjcKCJevyoLJO+aHGXSJQ1LzZbD
1OGepjL+3yKhciaxwNCzWVkN3MJAV9OfKc5eTaGsvZRBxwATemMYqtWC7DxySEnbFenRCoDtaTyQ
Ll5OzIQfB8XSSuOXjkCg0ZpECbvF2Ugm8QqfVTUZzBncGKuYMP0dhZeX0Q64Vadr62iZLUb+JdNe
yjv8qPN6OoG07r+fzlA7Q5/c/f666klzW7MWQ8u7FHE6eIvSZtrwOn4UONEJubLRcjNfKAU7TXr1
hQP/rt0yGCZeuNquFeXoliewNJogIeWoU/+8HE1JaKPryup0A3sjuYGO2LdQ3HjBG0yg1DWNYCJa
FX30HZFFtYmGL3BNxB1TGBDQcOfFeJN3U7R2gKmo68XKFSkda7EHiqiNgQO24aG6zsjQ1OUNm5wV
W/m5WnAQ6qRZbdyiRvbOacfoQtlSJzMyI+Ag7a6M3JCJj/zVUIyr2QD9hzbrBMGS+ADjRdj3KL4K
bwCZjMIyfEG97M+hsOPjYOJimTZr3N7zaD4buq7ILxaDrLTEHqktFeHK+R6vM8pikMojv2W/FuMx
6NjGjrYrNj8A6jQFA0tTxWVReyhdb2mOykOjksi5rhZ1ozwlvXZ80fHITJOLkR5NJ76fjkfwB6KE
RXdbtppbbCcesoIn4WtGhWDrnvENae1ifc6Y6XIXgHmID9mwsQRvR+1+zgjO7KFGgF0UfnZTmpXe
aZKH5elTph8RO+nMhkMit181nSYqMRk73A+/O+F6q0YU1SdriUr9BFSkCM0tHrDVUZwPjD7ImkSc
9UhnvIgKGg/Qx6afGvhuiCVd7R+o8FDyBJGtX9W39vagmdjWcnXEIorCC3ON4kSQChkE/wafQMAS
Bkpzf3Mep3ItcjZ4hVt9MZIyrBl6aVY9YqOMtNADiaDR/EghU33GHybUbZFT2dkzHcz8yO+9ZLh6
abihUwL5bRBiVFrmkZm/Wxfqa+Kd3WL2kAX4lJa+M5CP0W1YhJJY0G/mTaqkl43R5785uRqcgKNK
bSpUKi8T2N3FAamSK4aBK5pYl/nG8LvapmCmPJmfxhDoN3jwjyqSc/gDc5tZXmOf1M91UFIHB864
NpfxbQ95UmUfBYF0Awyd6s/TNP8L83zjJH+9hjZ2E8YCzwNvdZjlvsc4xULDd0ZSBvHikX/eV5KQ
1OpfpyjFf1FL+9k7wmGkHmz3Yzyx/QBmBMPJlLYQCXTxI1+7cjptHlmk7OAn+5yNP1udSzWiGdrL
rhyU0XTuEkwCIrJ1JHeoEcPfEYYv5vzVEpgGhC8DUlUxC0j7dw6rb0c+M6fVNUkNpsjNGKwwuM0x
rLSjNlLOrVoZ5h5EufJT7zEZraef/9Dxr++s58FHefRphtK84eSZS60Li56HcABHh+ngEGwh+DrA
7ymBpFxShrF/2PAAeKZpDet4VHxbpSAC23RGkHwslKCiUAqZdWQAhP4QQo+mEEhojISOyvc2I2bs
o0Do8MsDY6FrxHkkbgtD3tUUprDfdgv0nqlFPx1Oe5TRdjgI9K800ihMFRbXh7BcsqVFKoxscrlW
mnp+MrsT59tHR9rZjx1cjxFvUYopPbPTsoJiFM2KtfVfX+N/jbfyVcgqy/Z16+wKHLFT+75QSUGv
ro5wYJJGevohPtD86S/6cN/rUYnAkl+3iR8idLIQKHhoIWydcWN5SOZvuvEbfz0/1viy4gXRx0HF
cX8SxGxfAErXpV1LyuWZQgwzL+GXCg9Pa2Pa6BrbkDir3BLJ2XD2vfshFvc2gJaiHA9B2ck1F/Zx
pINgucK7eorhjlSMEU1PImcD9tAF80+fbCBOUTF86j2yShw3NLVYTASVfw5Hs24zAabze2pSdKlA
S/cGmAYD8DZv8tSyH+hwSU0aAiE3D2a+3x/GbDxcB5XnpBt/3aZ9yLiFrbyqvEj1kSp2JKvUmkYQ
YwuLwg7VPQg7g0jSpxdIbnE72Cet0L28U5P+rxVJCxXHw0mlhONJrIfBOw4f8YmI/rLX8+CJlJnV
IfVr/XN77XV2R6lbx8VkkAFukIcL26QEXUQijAhoaCL24PRNQIww3iLepSy4TiLDp/wmtRsL2hNT
e7Ax3/F0lWSbzw4U+lovmWcoMF5WVmXDvkjYLw3LFlVyktTcmRkfU330TKXiEQYKEEq83T23krjy
3ygvw4mO5x0g+vcJWOf8p9biMcd4rVaXOggGv/aYRVcWNylOGcBu9k7ZJiWHbYojDqbvGaPCHVIj
tz9/UPpl/Yu1XBbl2EFLsNeG3N56bhVCbaYCeP0B9t8EJyCB2UimYAdmYXEOC0HhKKdhGxDWfb8B
/7N8Byvlkx2P9NWZ8RiMBnC/xY6Z9qoeZ2ICmhnXSLYjKA8BwwC15l864fK7j4rnB0opSk50poFz
GrRGtJtDoOC8/j19utS9EnunnOPe18OsBPeslkBXJJamB4pvvVPwO8P2G+YGCpc5xGcIFOYOqtMP
P5Yi/99gBdKk1CVGxP65zGqKCuZNoos/Tqyc8VqkLC30HFDs55m7zmYSROSmAFqDk69q6mLq820F
/m0UWL2975HvxFKojGxGb1REuirROKaNZfJO4gMVU1N8lIC+fR9FRp8i0pcl95spjd8essRXPOSJ
4xmTGXeew5OC3C/xROWD38vetjcqtyEoTNS8wRrgg7CQv1beaZ1SAwJasEt80Er0sphUxaTi/rUb
7OWAI9lOZLxQpCHZXAd/FeQ/Et4r2oAYbqazEuIm0QDLt0QvckROGwn38UiECyVmdr/LQMQp3ZdK
Op/MTwpkZOr9YdxqRisLv0AZCUZNNuWJEi0ajTWI2muINYJrY03AhefhvZSfhUIxoijAgryPdYUi
/sT0l77/bKXL1JtWrwAJkh3s0VS/Ri0ZRQYD2MBgektNU+l1+1/VTU+Z9AD2g/oAEalh3kElcUQb
5VbYOicKx6rohet3dmeFBmsz3QX53ANm6FqKg/B3S9z35apt3kbov59fY1y/s3qhjcAq+XuLOReX
9ZHg8cUXmedKjkejNTUrV4OYSju8Yh/hMXzf88xauco92/hL1nODXmwyPi4wDQLO14RCMmjjDs8z
GFTLIsoWz34wE0epEVbDNY2hurIWj1ThA+jF2uo5njhy1fUIAnw0TFC19n/QTjgQZMCcU7oo/VYB
wJWn1FU1tSOQXtzE5ULj4YELn+O5LInBH6L0QGHqP8gYRA3tZ9Jmotz6bES1i0XTroezgSXENVDS
9jVMgkzpj+KTBnxtE6q1PnHyopkQipyHrNgzU/EYya7Mhyhh0MZG9phRpAg8iHSYPSu38egXwaOF
os9IiC0/pVPbPCfwISkpgDCFNXuF3/Lm8hG/2IJOq5+3lJmK54yRwLCASyH3Q+cP6xz17aNky3Hd
Z0otPJxfySdCr2eVZ/d+e12J0EzXbOknhqCjXi38xmB1UpCzztB/AJ8x+2EXTe1jeskl90BmCInQ
obfPv8f2qivseuu0CaL3pl+3tKYFOur/pw2b6EidblMf+wf80whjWKAmArxQPLG/zmWOsmg6jIRl
TKROuy4tKX5aZ9JoctCKX7UJL7qe8oKUw3IVHsE8o60Br9NjNLIJytbF7pGn9Cif6x/33CpZoa1c
1WccnzvyrTDK21c6x259JV2rTjrd3Bln+qFQx0VEtiY3ORZUugmPRmU1OBPQcQE2dKdUJmWEuKmi
mLuLiqrEu7pwGaq6B2fDJ7xsCO1Idx6emt0jYQMYpHxmMEXRvIQZyI5kg2a3nuz4KaKao+ndt+TY
JkH+vRUO9n7gXxTPtmHSu308pHvH528J0MEsvCCU3bTeXmUAEH7uVsOMgUeeqAq7SPWVfsAqnZh4
JgtriXU9M3cxHeHTOeNjTdH81eX5mHMuBuTzVdVjbq7EJOQazWMRRAzvTm6Ib/VF7ZQPp4L+FZeU
fMZYPfF9llUXU50lqtJm+W1hoYrnRkiYQWTWhwTcOve33WtuT5SOYNySwNpcG9WvwGIlJJu3D7/G
kAvWkNVffFhkvIlymz1cEKSy1bbOURoybsMxH9V8FWkz2J+ct2pIEJtML/Z5tH9U/KJ223PnMV+g
4At5RqGBQO1ikHC/KIdw25PNHOXpTXPbQlfLGpHqT1LRAp/hQts6I5dBuwZ6o5+tdKWU0tGinwhT
BbGl1tfxL6XbgMxKVn68tdp1rTOr14Nm+qEYkPL1pZflDZN1iqVbk4eNT6wGj0U+DlHuBaKK5vLs
A4BjX3JaXsa2NR2YRcRuod5RAYlj6RtxkGRTqki99deY7QanbHTZ1jPIg7cNE7kTz02QsizI8nLk
KSBusMH6UGk946b+mGZcWyl0cAd3Yeju/qaheBe0+/vfFMcGChUx4WE5EHQ+EPyjxyaL0s0zgywj
GXGeZX6JeRU9pTnlnnvCq0O8flkDNk3+tn3fq1HMqg9hhugWSVxAlaVOkdCUvTpo5eQ+EfIBLXDn
7pWpKkh02vCrkZcMs0Es4yBZtNaErP7E6Vn0m2HL3SYhY1Pj2WGEI1O2mh9Q3sqz3mY+Ldv5l9J2
aYZko8YA3sVFG4RR+yceBGG2o7C0g62PJrogum6S91vJ42KPwBN/nMKDfbfVkNvaV//6KBaNV+L6
mUDgMbCtF1ORMp3VRwPB5WJBlZR8+petTVjkEu1woor4b6735q3N1aogNLDYtEs9DQvwQcQ1S8oN
JkT0c4qq5BVzAI3P43sLw6prccNHm8rSIIPzf0c51/8AAz3BlI2E3OIDB3vFgQbZkd99hAl/oWmx
mUHxKPzjUpp/KiNJqj4mVmlZOl41R1IrBlainHyz+7VnwmMFBuTeLH/RHHYXEtfZ79r8+C2x34xR
kfeKTbyj6ww2EVL3AguIfwKA1KG0HtI2fjfLdBGkmcEVdBzEaJGsJWczrB74g1cm9YwUOw/gn+kU
Y0EVO99+SaCFmHhdeXTeEwo2iUAMU2EWR+WmL2BFYfLsh/qqUGO9OKhv2/DjmcxceWC4dApuZ7Cc
WoRSZi79rV/bhoUeHLk7dSY+xUfxjciMatuVn1ArDYMym69AAflY7YMnWD4lP6sb7LOEIbwgdphy
gxXoWedwA5lQCljkLJIOSMB/I3h+stDHLg0L8lweaXHdShmlwn/1rh9wijhMUOMtjpEez8UNLJAU
fBfYaaSBYhPJllbTOxeF3mccCG/UGuWod1Ifbq9ELWSjZqs3lq5luRv9VX/UP4meuEF1qg72D07h
gGkOR8IM1Hv3jRVfLOUKKNRbzo1f7Fhr+J0mrfHj1vAPPwhwweAvzBm8iZyJVH7M1uADTP8bF8k3
JJG5CuF+HPNg4LTmYYVZgOh/QhmKiqbKazWLnU3IFLqVG8MTsvNyqaw0fDJrHi3Uv9RX4TzDtI2N
lA+nft5kTvX/LvfXsgT8GymTajQt6YiZDtJORlYIMXPj9jMn2Xd9Jw9m75IhYe4N6hCCPMHp0BNC
/yC/m4xrI3S/QbQLuJ9+8gK6B/JmGIZAFEIVLBo4m7Sew0ChRDdO6dEn4vZ/wSex/XUbDDD5yeDe
tmKsTHAvO9bKmboU2NRK/0LAHe7sHYsBXZf2dyiMV+vs94cgvSi2dx7HQJqCPRA2whqCZKJkaClH
PmkZE29aVlUrcNZ/wVtrzNYCLRV+nhOfy2iBwfRWq2jViunen5U/IYkLXJ/c+CirN+azrRBIgMUi
Nq7OXDwpMe2EFWlMCr8iGOgBeA/r44Fp6IaZpcWpxFZRLRIZbZObMBDH/hQpUiDcy/Pf8T71sChm
s1V6FRNJLcCpi9xvuLjSs/LCQkCzpUmecT9TDnig7hnquiYnZJODjq7BQUBZVsLCwfoe+neNxkDk
afBvTKpmoscUGrzSU6Zhtd1FmmDIE5n33LvvVAG2sa9Gb4ifzLzzv7k9I8f5i2qk7jBIUDUQBMwx
ozfZyRJf3SR4bH4gSs0XhTFlD9EAM8ZzeeH2+usexVd9qPyTOPY8FURy10kSN79Uo5dyiSA1BuOY
YPB4QtfV5gfg2BuMQ+N94sF7VcifAB5CB/HzFapiV34dY6ACkbttHxNPOpu7gG2EarAgp1HVko4J
5Xqm0cBoNX+DNL82bmFeZIIpGf32CTlpYoewNUyKOzNvkOm115Bpg60cljKCkvbH3GrEo76LZ2cg
VY/rPWn9hUvdcYNbD5i2RHzHS8QqGWsS2DXL0HJefrgOldgXpKInt77P2GQgNzXykLSiQ72oiLDy
q3zkMZ3TiePP0UXWRD2C+hh04ddvVLcjmFr2AXmYYEhpJlBqCtlb3tB5QBTeocCGymxhyVDZMMMy
FW3AjkJ6kocw6h6LcvcaCOXkSHZryRqUSS7emNHY8exV1MXqVfBbhbCRFpK9cCFbBUKy8xPERDV3
vPtXV9xQ9aJ5Ro1JouABIE9nSL6s03/L8CODSRJV1X+Fsbd0fAVINJU1XpLRSupNelIKaQhlf0+n
BAs0aeoGzgpYLOTRB7DdM8Vj7zC5DiOGlrk7MtoaYpGJ7bhlMg6jKWVCyYkzfCVZlJlvyrpxhNnL
FLNCQ+NTAtOTx+tP9psIki6CNzRTM263pcsSW1H24ad+fHQtALXe0rjfk9PXAxNahI4knI0XIS50
MzT7MF3L+xqZvNUQKnBit5ntP9PJjGOzIxsaIZiy9lokqQf2M7HYjyuawBHEKft/B2Yz+MafRAZj
ESzKDMlsElasLoDo7LU7Nz/HyugOc7W5R+T1ErG/gqMaA9h6k7ZKHVHrHk+otV4H4aySHiyYg1VI
8n9N799uW5RgWZ7V6BdiJ2IdPep7HJOGvtp4F7uQJHoKCNBfhjgew6bMKpZajq/rnHs28yhmXNLY
Yc5mfoZeMwqM9yqrby6bH2G9B/jN8mN7AJcFUC5259tQlH/9TXDv1h/8RiMSkQauzZ69XKuglo+x
q1opttF0PFyMOPv+7RNOIlfz9Hk04MlzO864FrXUAQJ+eMtTf4iQ93euPW73jPSUXwsgrKKtSyIP
R9psf6ljEqgHhOwni0nikAv20AaPGX/736YhUjNB6GqQ8BgUX3W5b6VZ9Mya1I4TDkEkyBd16t/7
TvSSUlGRlE2/EVtOzv/i0x/5xC7iWkF/iKYy/TMrQWL8dy288Jlrhyxb8LX6qMYpOAVlowqBZd1g
yTZ/9XEpnb/isQ1Nc6UL4zki32OfRbzjzvnX3v/on/7p69g68tTGBy3Rhqz5Q4vWfpbfDfDhoX0X
JZAaUUVOq4j5A1Vbd7YjFiU7IbBktjAX3SjpavakGKMDDuJr2wxcLk9TjPOnKd5nnVH5kE2GKqNe
3bQKS/fJgclKH3nxSGXBv4p3d21Fz7Xc4rWSgXv43f+Ui1g3QDsmRKW5AvxeJ8sIP22WhhmdIUyp
taV6teFhvkivGQphq8Er2Ky+wbo/tJ2s6PHI0/jY93V+lOja2HkC4b6Jd0I2FAI7QQ2XLJSSorUm
V+qPI2+oycjAA7uXquXBs0lYIVogbCuqRB6Oq4bL9i/GE0CTeFlrGHL4OI4lItcOpjNVnxQfEvgS
iuymyclV+3CXzpiUEZ039C1NgCmmIUVrTQIv0uAL3uuQSPXOoXJTOw8lMwSzd2RfQGPA5e75N5qe
Q02pvrXS7k/t6E2f+cxP27o7Jl4dbgVGy+vpej261vun65gZEwhn9PLI3/y6xP69aNHkfEA+GtT1
v8ejxrwUl1wTTlVOIVgBAdCB7xNrg0jFlTjk2RCpBnZrDSeANF0xtT0NqGiGDNPSDIwBkNtCTkJ2
0Ant/w7/Hu0jZSoo5iMnbzsPY9E2iHetKPOfFhBt74ZN5p/l0gZ2mezwpB7RxvpvEYHpXGQvKWcq
BR+wpMZxFq+FnqgRDGaJYwcw56j1vWIx2jb8KD64V8aq2zSeIk/dan/Okiv1ZgzgNWr1PBmnspON
xeQE3wQueelZlI8kn/C1B+v50qWsX6k20nHer03Bm5UzbPVeXWlNNPc/JVl0RLqmY2zytyct1YXu
96kKABu7JqZFWOX4O0OVEYUpmLBMLcHIRWsW5rJ8BIQWf4XrdZJcN2zlVdfgJMxeTrsZvxrQ+Sd2
Y6lonFD6l8UxSIBKxfFornEjX8MOcemZFvcf9aXtEzkYa5CUlsbOQsj3Js8W9lCgPRPNU3DSHtFT
dCVbjzgX4B4DLNoQjODq/V2yDJoWyIma9DpR3zDhsoacMOI+7fqI3UTTlyAv85DJt0Cr4GFQ1zmh
b3jxJrjKfEdt8bvhK24BXBhs4N4OoQdBAa8Cdn/8dCk0nH44Y5HB1AqApndAzQPqmsRXEo2QQ0uk
dG0EhegKl86FKRBr3oI51Ab4zXu88khoXHw/A/MeerczwFUfHR4dRYZsIl5Jzm3MF7iZ6a0hJ+ee
gER4XF5c5FOlcxgTho4zQtozDIMgqHkVZHpoa8VTKMGguItjuRVxkU5W5jFMc/yNBG2I9IImlGsd
5BDUOz5A/6GGqApXEa38977Rb1IDFOdTnDsBwfXLHn1IPPmvw786bP1atnBiOn6iz38b0m7cbtVM
LqxqQvnApoAry01JH7cQmFDpSGBPC5RqSjbJPadPlysWRsf7ySwsWAPUN+a6kPwX+3MvgyIIXQGG
KN09NKsGk6afAqk5i3CvVsDURh71yVj2caUl3e+lV0NkPTW8kxLEGUdo76TpluO6c+wYUoLW9xFx
RWTOlRsrcetvpP8VQJtMCGDhF+cz5izi35Xetm/fH8ykaoQC4pmcAtUuW8aCHZYtxrl2PYmv0xx7
sgcCQ+A75COLgdaGqUSvkrikKzYzGxV/v1SeXGg19z/UGBj3+a0+rH1HFl4cjxndCNrH24VYU0Uw
7iOyAgEt9VieKdsEVpHDPVIMuQU41ZzwbnLqi+gTDoqTupOMGk7ZM7ZMAALKWwrzst51dyW73uR1
feK7WOYX9ts976NQfnMWWjfwc6cLhHf2h6yFc4a3yXptIy2dmYi+tVVuhJooBMfGqVwkc8Eg7ZLZ
GNcFZszMZ5dQq9Jzl/tibnFx9zRgHQtfDaStsWDZ5dB+/cr9LsuQgm49or/vesq8kDGx/uOk+ar6
9TNVq8E9QcRGd+ISzOR4s8BljS0CakpllSjHa1hv0IYdyknhWeHmfRQz0j71+EpdBvkg9ZAtMArd
fRIiEFruT9fWOTYD/cKIsYnyQHHGKpa2ixZo7e8On9ebj+kMIfJRPuEZLvzWy2GmP0mK9R0Zkhev
3r9PEWzWdZd3fyrHmy/NKEB88H7z6Ok1pChkQHcZMLqxoQ5mOrgc14G+uAoMhrUrM9Fu6EqzcshQ
wAjOrM3TtS1YNH8cobBh7lupW6o3eyCLwHOsm3+9IqlyWASQ2Ak7B1no8CXrbgmFWEyEfsjsxdZP
WV2tIE/M3iIc9NVSImuPw6+WGCbisT7vXlB4piDqBXVg3rRiHUq6prDMKY3gb/mndx4XGHeg7Kli
4tuO59HFl08aa+lPuT6tbfz1koPWigQLAdpO0Jy0MaRgzeywcE4zILEthLoeWlLcWPjmaCZBck65
wi38yJo7wOa57SvJtCcCo/w1F4Rjep0fBud6AEZ8EChVAOR1yM+0/Q5Se6il+dJQPSj2z1Gq9P0J
Z7YZBxc0j8pKOdQaPTDUfyTDiZJarjwxIUwzZnr9LNc74GUOoxaSPUHQnKCW67Y9Sqp4YIysUfuB
yXPi9X/q+lzgjoh4uY6hzojapaD5VYv1Yn/a/CS/EhWGGTa+n4hugeMSDW8xAFmxm7nPeiIKWjIj
cOQswqQZKn32HZtinijhQpeofNDsKiB5lGtdjavuwuOTpZqxZ72JbYhEuU/JvSu3Aay89bhZZSCu
BpaFVVTs1N57p4PvfeAtnahiLvOHMFQvPAthOAkFxFNpuASEF3SO8zZv14b6R02WZmlHWc+OYhq9
mlo81a9itXcD1e4UXOYln4HWxPK68OCGDoxHZYzr1mRfxk/nbaRt0AFnXo5tufziLZE+pmqeUO2G
zyoNyHvRPKoAYg5LCfWJJYkEhZC39CyWL7workvLXMglH2gB6Mg/XrswhCGBmUa1Xki7bdBjyT99
xHEarF9lMI/0u3SUgeylE3V60MUjnhOaAuVj9unX240A5vC6hr7jMIKsBxDzzepJwjdkDzsLeJ79
h0rtVGDhdSe0N+Qq56E2PkT6cN5XW9yQXxmOyhndNOiQXlrSAItCHMWkWHIyjWQ3Zvf0ho7AyWwX
T/5eDMeG8Uq+ybjw+k8M1VBgFMxdLHG8O3PYs3FRGjFooPoQrDXFaLBo/LFWWeFsQ0cENnRAqq+V
jDiq/xjgsLvzN3v1XhLA9TJ6VD05iaLk2zdDBYK2DZCOgjoVUK2YgSYxgJvGXYBqxAu62Skmn5+C
pIkrMAXi82r/Z12grrN564D1KVP4q01huf1JeV8LZCiUIdYXgOXWRNW2URD3ny2czdXSY8KiNATE
aPhiUJak4XHFp3HXU32MRyDmaqwdtqVMJni599qGeHS+SKE9v/6YBcWnHehko5za6LqeNUWgJ3iN
TXiWk000+ajG4jak2vu2HTnFdAMXwKtrlTIBG1twO9vFFewTZscCvTl1R56ZY+o0hDKGsFbjpkHb
0lMOLiR+mtRci5+vg5/IAY/M80RXF2YGM/kMpUytbGUcj4ibZmko/+Pha9vEpvVNhf4Yf1Bx4YS+
mQBQ3xD0PQnVH3HHYE+yX0IazY9LsiMuUzbQ5QfH+rKnQhGua1BJKl1eHfdT2mkxlcCzZFGstYZb
Wtei+HU4G4vuVy3QryCrc0MU+83AEu3tagqiMWTSUb/peAqzLQp5q7Sf7DKqk9fz8klGyx/s600V
4lYTFADUJAy5SU2ZxeU1+KKeqAtcJ10+1jyHl8LHkFIhPS+JEXOLwC8hQqqJU1Bys1c2j51jiOnS
FIJCOyV+VI7tFLjMLIbTLwbVs4Qbg3zfGkV893HKWtUhRBKmEZ4VZSav0t9pL+zPsI9rRJ9j6LXK
zhMmKC2yJ4wniA/WWhtfBwzPc/PblQEiSVu/GpfLWfEpjG48w/TFN0PWwaI5V1OZhntI03QLujZy
s3QaxVWaQI+8ObFrfiQazTY1pNulYoqUWpBkFRl7KC2rZJe5FOtth78PAr/TSvzuiZDgMTxlFp/O
Ur1Fr3mOoC1a0mCYVw2FcPhv/idKcRcOzslHzk+q7imI/IFauDvsFYoBNCTdpWX2dTs2mtQw2pED
JALzuQb3sJTplSgmAyeRAgn7sm3ch7YZmCzWJlim1/zbMH7utWYXKFxBRs0xC+33weLPF1AmpfKl
AU0v3kCtfe/gIAeqctM9aIcvE3M7n96lcClvTqBqiVynOjKT0p/HObz7qoZbDhgVrRTLlvMbol0a
5FPkAQoZMrLWIvgT7q3pAQm56QqrwvPpHS23xVZUYTFlYBjyKRBYNwrrQGXWhs3Z+xv2xlPJwoN3
I/dVyv3ZVf9McGZ402QGNMkQCquUGHr/Gn/cpsNnHnIcA56ukMD78KbxHPGFaJHbHoZMpfOfRzOt
cPlEKDmjnlJwoe8yDtJolQ+KEs7ujqbt8hvWlLCLHTZZeKXNkPpPywcyTVgGvkXXs2GDWvrFOEaQ
Qc02JXZCME/dpNVgwq1uzrweHl5AI1MzujKixk0Kw4x419c32O+8JMnACG1dgxAgldoC880cLvIW
tIyeFP7W3QSOaLc4Wi9ZI9DbdSylOW9d8/UbD6X4vNzyZYpzzEq/1CUn2j5ZVr0TAYJCNcBh4fT8
Xd2kP+MjN3WYB+t5ABT2RZDM6TFKBU1Rejj4VxV+vQe736PsXm1C4eJU+AoyvSl7TWwB60sQaXZu
uLuZOIUsS9wT2qMTlmZ5T6ejVdCapKDScedAgxIuYUGXvCvrUQJRFBX0yHo0u+hRowVOOARmwtm6
Aojhotm6I59GZdVDKcaNlqoOp9cl5oUrzk8iamtFI+j2IRbnYiPDdQa59//cSgAxge5fD7VLMe3q
iTv4D85kakd6puLuoNguhxxQw/R4CSrFpVVAXMFciULnnhi3g+MhQG93/9aIoGn620gbCUU5cAcx
KGJ5I6X4yuWJARvM88IYnUfe0LflbijBvugAyou1Nwbfr6fn3fo8ZDunyBGmyHvcHWi+TKXnRYWH
L6KC1qG5pQ91dvJgYfIWf8hYi/cU47volRAkFmmLAWtB9J0gJFHQEMWk94/qiszKnkwBH3mQCrPo
UbHNoIuq8+ADmzD1zbjWSnDbNzY6w6jR0ZL4T00lRPP8Uw5K9i3W3GIiwnGdwupnOjTa6wnITRMe
JJIZXjXipDtMymxn0SLS5eVTPXHZSXfUgqzboM2BcadpqVru+6eKeURwU5cgrNvksVstmI1SUIhn
CILL8Cg1d/Y5PNYF4Wt9l5a3DlqIp1quBiZ5Kz1yIuEK/WZx6xbdkDIl3P9c5hB8FY886TrLH4ji
WpWX/C5j7COSycLRTvY7i7LvB2T2o5KvaL9qoX9dVtnfeoF/aF6+4uRZIvigvibD5+Wwr/ayhneI
x1QCyWNHki0PPpdTKqYmT820pt/hno2vOpqA1Mok4eP7e2txFuegN4yuzs18/U3cxaLR+PmFPGd4
Z5Rgi4b63qUSLOm0SkKSs2WTbPUjT0qseJvO5tcVEzGFpLBLUIQK0C4LoQBvdTbkq3LlPgaqYdka
DlQbA4NMAo4nnSrrzS5d7r5oYMcyQTf+0ZPNQtiCz98hlEYI2ZPYtepJ17LbhECeHG/d8Jzt7MbF
5/PxVGIe52Mq8yhoEXPWsjz0nqrIIQXIjfvTVU2BtwcwZNNawHtNsYPfXu9IBqNCG393zzmiul0y
G0/HJTaWz3GXBZpUVD+UK5qZ0RgNe37s7xTWsQcNtPZfLurvWh+s59bZBNxd2qIj96XBjb4w16nv
GOWSfsX46lYrIhU65LTzIkS3cu+ClTOz7tFYQKqGfrRBJ6AbpEdFjs67Nsp3U6x0wgs9e1QAEoOr
tHSQKr6W58tigWAmeXSBObYufxGPi7o7pLTexsZIzGtLIxF8TdQ/XwBTWj94fUugw/gYRZDGEWGK
jQfwdmmgVsPwGqr5KvO8bTCkol/3ilYRktrJs36PzQ/DNtnITlTuRYZ4DnL4jp2XlGR3zVEtKfD1
hfwzsQ1dKeE/nPOvzPL89XIOA5MJAtsJqfPOlY6YcMwZXThO7dZlWIzdpIAVj3gSnkboXmMq8N8B
m7vGFkyxjKLWnwWQ4QkBwEIornZUWD4pp+RYqExVMpf2Dl3LbJLeF3lbgUbkloverclvfTKY8nfF
fDOm2VErR4sG2werQLP6e3LD/TIYNP7Ohl33LNRR4roojTRD82Lugqs0UK0xmGOjlqrLfsrh0ZlS
hkCW+P4Jq2bUk8kGw2bxGaqPVr+NOZe3q+oRlrnFymjFGOj8cl7oqaf3Avi0CLHQQAy3g87wfZbU
oZA6cnoOMr2CE4D1opDHnq+oBHKTk9INx1qHk7p4wdBztIjyF5lffwiKaJQMPJWc83OToldxSWZE
L02qho/OJzP4Wv5os1nlKgFNYyGgTH8SYfe7lLbtd/iQs2V7+rcW5vs5Qgamkc+XBTGKtLpyrBsN
7+Und1UT9X7UDX7myjf4EJjPbNv333CQj1CfzC5fS5Af2jN55uJJuxokLIWMBB+9P+nBbuSaiWAd
AOM+bJrkp18lTHgpQXpdwoIeUl6EXal68qkExTbX5WEMfxFEwpYG88Qys8P5BPjsWNcAe/DMi+AO
flcPUZBQHU5EKtaC1YO8By33l8VEdetaQ8ZpCMU4SfY0sgO5NE6QuLGLT1EN8DDJL/NpVG9nxtaO
tFUt2ZK6ZUCyGmmj4Mm7phOw4VwDymoFer9HmNbHtv7mUJfVURCpcCRX9oEz8mDA9fPURPdDBEO0
XHsyP/xGa0rVUaxxu/cMVfMfjBNIHHAIoBOWCZAuaVIGh5xnQg4Qesc/qwNCfwmfxFXsxoQLmVnt
WN4umr4zF+zo7kwlrLYGWzhaJeI/6mYkPXmEdfY1t7+XP4VYtvyzdj+W/hF7SgkwPcKGdapmImHN
6M+nqk7NLED7X+0bas4bDINHRkNA8sSVl8Sh0lt0B9l06krZHMInBy97p+A16P7p/Pav/IDGmFLh
Wt3pve9XiA4n/XdCUYUpJ0Q228gTy/5gMGKO1NNPEXe2cYh0brwgxnljhoDrcFHYf05o48iK35Gm
0I9yZcMA670XpbK+ORxlZafPOqweevFXHmr3CGxYxhst7ipMaI/fNBSDdoa3AFgtDzz1/g1kNMKZ
bDGqN4NtTdqbFotF3Fnk8J6p3fb8K7J4ZOQbNH7armVxmO/oufMhnPxqNdxEVBX5jKaCKGXjxDrY
ZAU/PHUP7/AcCTyr81BRQZlNMd98n+6uEIdRpzv1j3uZDssD8uvoNnNJt8TYeNTv8JjED1oewsBl
bqBUiQ0IyWBf/wSRSBHQDExQlrx9s69YX5yHCzDT1jCFZn3RddV5plKzHCZcb1UtrxnJgFIcvQ9U
c8wXXFvtPZUyRgiAoRvCgzgDxSWcRtJv8ulbUdXWuaK8ZZtk85a2QolvC5Y+zQu53L7pNe6V5w9O
SiCydSDz/ppE9sAwSB4w2PA+eKxHVB9kOnuOIZGFcef+WjLS+DKJkM5V4hOtAILmDsQVzvut9cNA
0Sn29B78HFG6m86n6YSr/R1mI/1oVqBGG9drJmL5RuKCNn629w5hgjNYIBpW7Bu3qz/Nxo+we77t
5LzAsRPgv3Lc3ZNTbrY8qzJlds18yQAv3CXbkA8+EaJQFUNpgSN+vUfGCo17wfbHcrAZpaUGAuMF
qY9KHyqpedsPdlunju97l3MsiUbh3tUikwVDHT8XKfYZBIuJx6FjwqCwZzy032IeEqtQTtF1/3mg
XKbJ39+U7O8C/TWrSPLBmCfn91GhWjFOfeGROHp5C+Fc3Z04Fi+LfdV4J99rk2jHNcu/l0J2GPdA
FR3vb6vfRcmd8E1+S0fQSu7E+auxlwaFJB76THrJOYRL8z+w5kVE5ArHervlpZQRp4TN5QRhRzKT
pyYoiEXlS4o/KyZOECSJWBLs78/XjJLWuNpU6GtWSdwOZx4YzUuRA1lU5VTz1oS3EevpRIT98Q90
4U2pBq3VWvBok3wA/QkK9Nt1Si4zRbD776nZgaQb+pHSEEKPV8ni0f1WjnGYTDZqqZicdp7A8i+E
3wpoku597y2di41dla9OQNVXwLruwdHg+tQLKOa6qKHMDhKhyGVYC6hnUjlKLSvlaMMTEw2LspAp
w9Xz+LMu/Dh0mI4PHJfWnM4XblaaAkKCs9oafI3UCSYNTEAaDEG2QyjLvKFkZyV/9TnEGdnC8bDX
viXVtubuk1QXKG16bS9xr7D8dGxEUiosjqz5IMFB094uT6L9pWO0DQvchHC7r5v5AHITnhug/sL+
+z1q1EUtJJ+wryvA34MWwMts6YYLX9evJZVXxLCst0gaG3oVj6X0PrjPXUuqiMK0zkyme52eOGIG
UvrK3mVlFcc1gBN2vfP8KyrDhjh47Ivi8GTJe77cUxNZ7QMCTKTOjZhof34KDag9ZluTTvQ9tBJ3
XPj6E5JPFr/IdbMU7Sj8r0UEeh1u+FLdbXONu67WKa9OWU8TIeY5r33iwCbSgLkzEMsLQXyh7Exy
VcNBuvMtARlqFpelbEgZdNHWcOPLgnrptcm/Gg7o5OSwyv0tTnb1AAt8gG46LMF2grnSuQH6Rnvm
o/rrGqgp5hGRX5+TxallveZbc+5gck6WJ1+NPSHu5FtYFLyvjnBU5b7cYlhaIoyLSKw+R27R6/+F
rkVEK9Ta5cXu0NoFk3YELqQAZjmrRfYuzOe4KXU1O1IPigHxffLH2jmT0K+5BnULQWmCLRsKurJT
XXgN7dUSlGAw7+bX0CUxyoXix4AyCsjenB7C+3FmVp9AQT+A6MQPJ6TmUHK+lwFOfcrQvQcgncLo
AKoifYOHlQ5PPHcTGRkCtBKMJiO6YNUxizP1+przyclAjIlk0IJ5PpZiYnq2GCSV2g1WCXFEFKPd
2FbYZLbzTsNQZhYQ48ibqcagbojfL+dcNBDK26x5LGBHipaxKnxMEk1TPQZA
`protect end_protected
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/zynq_design_1_axi_gpio_0_0_sim_netlist.vhdl | 1 | 51912 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/zynq_design_1_axi_gpio_0_0_sim_netlist.vhdl
-- Design : zynq_design_1_axi_gpio_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_GPIO_Core is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_GPIO_Core : entity is "GPIO_Core";
end zynq_design_1_axi_gpio_0_0_GPIO_Core;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(7 downto 0) <= \^gpio_io_o\(7 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(7),
Q => D(7),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(6),
Q => D(6),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(5),
Q => D(5),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(4),
Q => D(4),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(3),
Q => D(3),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(2),
Q => D(2),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(1),
Q => D(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(0),
Q => D(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => \^gpio_io_o\(7),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => \^gpio_io_o\(6),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => \^gpio_io_o\(5),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => \^gpio_io_o\(4),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => \^gpio_io_o\(3),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => \^gpio_io_o\(2),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => \^gpio_io_o\(1),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => \^gpio_io_o\(0),
R => SS(0)
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => gpio_io_t(7),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => gpio_io_t(6),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => gpio_io_t(5),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => gpio_io_t(4),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => gpio_io_t(3),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => gpio_io_t(2),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => gpio_io_t(1),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
rst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
start2_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_address_decoder : entity is "address_decoder";
end zynq_design_1_axi_gpio_0_0_address_decoder;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2_reg,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAABAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(1),
I2 => bus2ip_rnw_i_reg,
I3 => Q(0),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => E(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(15),
O => D(7)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(14),
O => D(6)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(13),
O => D(5)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(12),
O => D(4)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(11),
O => D(3)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(10),
O => D(2)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(9),
O => D(1)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(8),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(0),
I2 => Q(1),
I3 => bus2ip_rnw_i_reg,
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => \Not_Dual.gpio_OE_reg[0]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_slave_attachment : entity is "slave_attachment";
end zynq_design_1_axi_gpio_0_0_slave_attachment;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\;
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.zynq_design_1_axi_gpio_0_0_address_decoder
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(2) => bus2ip_addr(0),
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => \^s_axi_wready\,
start2_reg => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_data_out_reg[0]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[7]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(4),
Q => s_axi_rdata(4),
R => \^sr\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(5),
Q => s_axi_rdata(5),
R => \^sr\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(6),
Q => s_axi_rdata(6),
R => \^sr\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(7),
Q => s_axi_rdata(7),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end zynq_design_1_axi_gpio_0_0_axi_lite_ipif;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.zynq_design_1_axi_gpio_0_0_slave_attachment
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(7 downto 0) => Q(7 downto 0),
SR => bus2ip_reset,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of zynq_design_1_axi_gpio_0_0_axi_gpio : entity is "LOGICORE";
end zynq_design_1_axi_gpio_0_0_axi_gpio;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 7 );
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_core_1_n_19 : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.zynq_design_1_axi_gpio_0_0_axi_lite_ipif
port map (
D(7) => DBus_Reg(0),
D(6) => DBus_Reg(1),
D(5) => DBus_Reg(2),
D(4) => DBus_Reg(3),
D(3) => DBus_Reg(4),
D(2) => DBus_Reg(5),
D(1) => DBus_Reg(6),
D(0) => DBus_Reg(7),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_17,
\Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7,
Q(7) => ip2bus_data_i_D1(24),
Q(6) => ip2bus_data_i_D1(25),
Q(5) => ip2bus_data_i_D1(26),
Q(4) => ip2bus_data_i_D1(27),
Q(3) => ip2bus_data_i_D1(28),
Q(2) => ip2bus_data_i_D1(29),
Q(1) => ip2bus_data_i_D1(30),
Q(0) => ip2bus_data_i_D1(31),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 8) => s_axi_wdata(31 downto 24),
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.zynq_design_1_axi_gpio_0_0_GPIO_Core
port map (
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7) => DBus_Reg(0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6) => DBus_Reg(1),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5) => DBus_Reg(2),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(3),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(4),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(5),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(6),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(7),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_17,
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_19,
rst_reg(0) => AXI_LITE_IPIF_I_n_7,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_19,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_axi_gpio_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_axi_gpio_0_0 : entity is "zynq_design_1_axi_gpio_0_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_gpio_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zynq_design_1_axi_gpio_0_0 : entity is "axi_gpio,Vivado 2017.2";
end zynq_design_1_axi_gpio_0_0;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_0 is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.zynq_design_1_axi_gpio_0_0_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(7 downto 0) => B"00000000",
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(7 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_led_controller_0_0/ip_design_led_controller_0_0_sim_netlist.vhdl | 1 | 66664 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:28 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_led_controller_0_0/ip_design_led_controller_0_0_sim_netlist.vhdl
-- Design : ip_design_led_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI : entity is "led_controller_v1_0_S00_AXI";
end ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI;
architecture STRUCTURE of ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI is
signal \^leds_out\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal aw_en_i_1_n_0 : STD_LOGIC;
signal aw_en_reg_n_0 : STD_LOGIC;
signal axi_araddr : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \axi_araddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_araddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_arready_i_1_n_0 : STD_LOGIC;
signal \axi_awaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_awaddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_awready0 : STD_LOGIC;
signal axi_bvalid_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_i_1_n_0 : STD_LOGIC;
signal axi_wready0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 7 );
signal reg_data_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s00_axi_bvalid\ : STD_LOGIC;
signal \^s00_axi_rvalid\ : STD_LOGIC;
signal slv_reg0 : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \slv_reg0[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg1[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg2[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg3[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[7]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg_rden__0\ : STD_LOGIC;
signal \slv_reg_wren__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axi_araddr[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_arready_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_wready_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \slv_reg0[7]_i_3\ : label is "soft_lutpair0";
begin
LEDs_out(7 downto 0) <= \^leds_out\(7 downto 0);
S_AXI_ARREADY <= \^s_axi_arready\;
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_WREADY <= \^s_axi_wready\;
s00_axi_bvalid <= \^s00_axi_bvalid\;
s00_axi_rvalid <= \^s00_axi_rvalid\;
aw_en_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFC4CCC4CCC4CC"
)
port map (
I0 => s00_axi_wvalid,
I1 => aw_en_reg_n_0,
I2 => \^s_axi_awready\,
I3 => s00_axi_awvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => aw_en_i_1_n_0
);
aw_en_reg: unisim.vcomponents.FDSE
port map (
C => s00_axi_aclk,
CE => '1',
D => aw_en_i_1_n_0,
Q => aw_en_reg_n_0,
S => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(0),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(2),
O => \axi_araddr[2]_i_1_n_0\
);
\axi_araddr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(1),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(3),
O => \axi_araddr[3]_i_1_n_0\
);
\axi_araddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[2]_i_1_n_0\,
Q => axi_araddr(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[3]_i_1_n_0\,
Q => axi_araddr(3),
R => \slv_reg0[7]_i_1_n_0\
);
axi_arready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s00_axi_arvalid,
I1 => \^s_axi_arready\,
O => axi_arready_i_1_n_0
);
axi_arready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_arready_i_1_n_0,
Q => \^s_axi_arready\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(0),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(0),
O => \axi_awaddr[2]_i_1_n_0\
);
\axi_awaddr[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(1),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(1),
O => \axi_awaddr[3]_i_1_n_0\
);
\axi_awaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[2]_i_1_n_0\,
Q => p_0_in(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[3]_i_1_n_0\,
Q => p_0_in(1),
R => \slv_reg0[7]_i_1_n_0\
);
axi_awready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => s00_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => aw_en_reg_n_0,
I3 => s00_axi_wvalid,
O => axi_awready0
);
axi_awready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_awready0,
Q => \^s_axi_awready\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_bvalid_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF80008000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => axi_bvalid_i_1_n_0
);
axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_bvalid_i_1_n_0,
Q => \^s00_axi_bvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(0),
I1 => \^leds_out\(0),
I2 => slv_reg3(0),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(0),
O => reg_data_out(0)
);
\axi_rdata[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(10),
I1 => slv_reg0(10),
I2 => slv_reg3(10),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(10),
O => reg_data_out(10)
);
\axi_rdata[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(11),
I1 => slv_reg0(11),
I2 => slv_reg3(11),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(11),
O => reg_data_out(11)
);
\axi_rdata[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(12),
I1 => slv_reg0(12),
I2 => slv_reg3(12),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(12),
O => reg_data_out(12)
);
\axi_rdata[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(13),
I1 => slv_reg0(13),
I2 => slv_reg3(13),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(13),
O => reg_data_out(13)
);
\axi_rdata[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(14),
I1 => slv_reg0(14),
I2 => slv_reg3(14),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(14),
O => reg_data_out(14)
);
\axi_rdata[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(15),
I1 => slv_reg0(15),
I2 => slv_reg3(15),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(15),
O => reg_data_out(15)
);
\axi_rdata[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(16),
I1 => slv_reg0(16),
I2 => slv_reg3(16),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(16),
O => reg_data_out(16)
);
\axi_rdata[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(17),
I1 => slv_reg0(17),
I2 => slv_reg3(17),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(17),
O => reg_data_out(17)
);
\axi_rdata[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(18),
I1 => slv_reg0(18),
I2 => slv_reg3(18),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(18),
O => reg_data_out(18)
);
\axi_rdata[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(19),
I1 => slv_reg0(19),
I2 => slv_reg3(19),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(19),
O => reg_data_out(19)
);
\axi_rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(1),
I1 => \^leds_out\(1),
I2 => slv_reg3(1),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(1),
O => reg_data_out(1)
);
\axi_rdata[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(20),
I1 => slv_reg0(20),
I2 => slv_reg3(20),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(20),
O => reg_data_out(20)
);
\axi_rdata[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(21),
I1 => slv_reg0(21),
I2 => slv_reg3(21),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(21),
O => reg_data_out(21)
);
\axi_rdata[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(22),
I1 => slv_reg0(22),
I2 => slv_reg3(22),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(22),
O => reg_data_out(22)
);
\axi_rdata[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(23),
I1 => slv_reg0(23),
I2 => slv_reg3(23),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(23),
O => reg_data_out(23)
);
\axi_rdata[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(24),
I1 => slv_reg0(24),
I2 => slv_reg3(24),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(24),
O => reg_data_out(24)
);
\axi_rdata[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(25),
I1 => slv_reg0(25),
I2 => slv_reg3(25),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(25),
O => reg_data_out(25)
);
\axi_rdata[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(26),
I1 => slv_reg0(26),
I2 => slv_reg3(26),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(26),
O => reg_data_out(26)
);
\axi_rdata[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(27),
I1 => slv_reg0(27),
I2 => slv_reg3(27),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(27),
O => reg_data_out(27)
);
\axi_rdata[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(28),
I1 => slv_reg0(28),
I2 => slv_reg3(28),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(28),
O => reg_data_out(28)
);
\axi_rdata[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(29),
I1 => slv_reg0(29),
I2 => slv_reg3(29),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(29),
O => reg_data_out(29)
);
\axi_rdata[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(2),
I1 => \^leds_out\(2),
I2 => slv_reg3(2),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(2),
O => reg_data_out(2)
);
\axi_rdata[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(30),
I1 => slv_reg0(30),
I2 => slv_reg3(30),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(30),
O => reg_data_out(30)
);
\axi_rdata[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(31),
I1 => slv_reg0(31),
I2 => slv_reg3(31),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(31),
O => reg_data_out(31)
);
\axi_rdata[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(3),
I1 => \^leds_out\(3),
I2 => slv_reg3(3),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(3),
O => reg_data_out(3)
);
\axi_rdata[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(4),
I1 => \^leds_out\(4),
I2 => slv_reg3(4),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(4),
O => reg_data_out(4)
);
\axi_rdata[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(5),
I1 => \^leds_out\(5),
I2 => slv_reg3(5),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(5),
O => reg_data_out(5)
);
\axi_rdata[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(6),
I1 => \^leds_out\(6),
I2 => slv_reg3(6),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(6),
O => reg_data_out(6)
);
\axi_rdata[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(7),
I1 => \^leds_out\(7),
I2 => slv_reg3(7),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(7),
O => reg_data_out(7)
);
\axi_rdata[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(8),
I1 => slv_reg0(8),
I2 => slv_reg3(8),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(8),
O => reg_data_out(8)
);
\axi_rdata[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(9),
I1 => slv_reg0(9),
I2 => slv_reg3(9),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(9),
O => reg_data_out(9)
);
\axi_rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(0),
Q => s00_axi_rdata(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(10),
Q => s00_axi_rdata(10),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(11),
Q => s00_axi_rdata(11),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(12),
Q => s00_axi_rdata(12),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(13),
Q => s00_axi_rdata(13),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(14),
Q => s00_axi_rdata(14),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(15),
Q => s00_axi_rdata(15),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(16),
Q => s00_axi_rdata(16),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(17),
Q => s00_axi_rdata(17),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(18),
Q => s00_axi_rdata(18),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(19),
Q => s00_axi_rdata(19),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(1),
Q => s00_axi_rdata(1),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(20),
Q => s00_axi_rdata(20),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(21),
Q => s00_axi_rdata(21),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(22),
Q => s00_axi_rdata(22),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(23),
Q => s00_axi_rdata(23),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(24),
Q => s00_axi_rdata(24),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(25),
Q => s00_axi_rdata(25),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(26),
Q => s00_axi_rdata(26),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(27),
Q => s00_axi_rdata(27),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(28),
Q => s00_axi_rdata(28),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(29),
Q => s00_axi_rdata(29),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(2),
Q => s00_axi_rdata(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(30),
Q => s00_axi_rdata(30),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(31),
Q => s00_axi_rdata(31),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(3),
Q => s00_axi_rdata(3),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(4),
Q => s00_axi_rdata(4),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(5),
Q => s00_axi_rdata(5),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(6),
Q => s00_axi_rdata(6),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(7),
Q => s00_axi_rdata(7),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(8),
Q => s00_axi_rdata(8),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(9),
Q => s00_axi_rdata(9),
R => \slv_reg0[7]_i_1_n_0\
);
axi_rvalid_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"08F8"
)
port map (
I0 => \^s_axi_arready\,
I1 => s00_axi_arvalid,
I2 => \^s00_axi_rvalid\,
I3 => s00_axi_rready,
O => axi_rvalid_i_1_n_0
);
axi_rvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_rvalid_i_1_n_0,
Q => \^s00_axi_rvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_wready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \^s_axi_wready\,
I1 => s00_axi_wvalid,
I2 => s00_axi_awvalid,
I3 => aw_en_reg_n_0,
O => axi_wready0
);
axi_wready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_wready0,
Q => \^s_axi_wready\,
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(1),
O => p_1_in(15)
);
\slv_reg0[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(2),
O => p_1_in(23)
);
\slv_reg0[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(3),
O => p_1_in(31)
);
\slv_reg0[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s00_axi_aresetn,
O => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(0),
O => p_1_in(7)
);
\slv_reg0[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
O => \slv_reg_wren__0\
);
\slv_reg0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(0),
Q => \^leds_out\(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(10),
Q => slv_reg0(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(11),
Q => slv_reg0(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(12),
Q => slv_reg0(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(13),
Q => slv_reg0(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(14),
Q => slv_reg0(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(15),
Q => slv_reg0(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(16),
Q => slv_reg0(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(17),
Q => slv_reg0(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(18),
Q => slv_reg0(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(19),
Q => slv_reg0(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(1),
Q => \^leds_out\(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(20),
Q => slv_reg0(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(21),
Q => slv_reg0(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(22),
Q => slv_reg0(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(23),
Q => slv_reg0(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(24),
Q => slv_reg0(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(25),
Q => slv_reg0(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(26),
Q => slv_reg0(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(27),
Q => slv_reg0(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(28),
Q => slv_reg0(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(29),
Q => slv_reg0(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(2),
Q => \^leds_out\(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(30),
Q => slv_reg0(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(31),
Q => slv_reg0(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(3),
Q => \^leds_out\(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(4),
Q => \^leds_out\(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(5),
Q => \^leds_out\(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(6),
Q => \^leds_out\(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(7),
Q => \^leds_out\(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(8),
Q => slv_reg0(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(9),
Q => slv_reg0(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg1[15]_i_1_n_0\
);
\slv_reg1[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg1[23]_i_1_n_0\
);
\slv_reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg1[31]_i_1_n_0\
);
\slv_reg1[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg1[7]_i_1_n_0\
);
\slv_reg1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg1(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg1(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg1(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg1(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg1(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg1(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg1(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg1(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg1(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg1(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg1(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg1(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg1(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg1(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg1(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg1(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg1(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg1(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg1(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg1(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg1(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg1(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg1(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg1(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg1(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg1(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg1(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg1(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg1(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg1(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg1(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg1(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg2[15]_i_1_n_0\
);
\slv_reg2[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg2[23]_i_1_n_0\
);
\slv_reg2[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg2[31]_i_1_n_0\
);
\slv_reg2[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg2[7]_i_1_n_0\
);
\slv_reg2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg2(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg2(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg2(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg2(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg2(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg2(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg2(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg2(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg2(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg2(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg2(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg2(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg2(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg2(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg2(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg2(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg2(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg2(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg2(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg2(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg2(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg2(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg2(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg2(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg2(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg2(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg2(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg2(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg2(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg2(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg2(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg2(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(1),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[15]_i_1_n_0\
);
\slv_reg3[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(2),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[23]_i_1_n_0\
);
\slv_reg3[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(3),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[31]_i_1_n_0\
);
\slv_reg3[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(0),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[7]_i_1_n_0\
);
\slv_reg3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg3(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg3(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg3(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg3(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg3(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg3(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg3(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg3(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg3(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg3(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg3(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg3(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg3(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg3(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg3(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg3(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg3(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg3(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg3(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg3(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg3(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg3(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg3(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg3(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg3(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg3(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg3(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg3(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg3(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg3(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg3(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg3(9),
R => \slv_reg0[7]_i_1_n_0\
);
slv_reg_rden: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^s00_axi_rvalid\,
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
O => \slv_reg_rden__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_led_controller_0_0_led_controller_v1_0 is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_led_controller_0_0_led_controller_v1_0 : entity is "led_controller_v1_0";
end ip_design_led_controller_0_0_led_controller_v1_0;
architecture STRUCTURE of ip_design_led_controller_0_0_led_controller_v1_0 is
begin
led_controller_v1_0_S00_AXI_inst: entity work.ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WREADY => S_AXI_WREADY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(1 downto 0),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(1 downto 0),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_led_controller_0_0 is
port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ip_design_led_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ip_design_led_controller_0_0 : entity is "ip_design_led_controller_0_0,led_controller_v1_0,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of ip_design_led_controller_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of ip_design_led_controller_0_0 : entity is "led_controller_v1_0,Vivado 2017.3";
end ip_design_led_controller_0_0;
architecture STRUCTURE of ip_design_led_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of s00_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of s00_axi_aclk : signal is "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of s00_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
attribute X_INTERFACE_PARAMETER of s00_axi_aresetn : signal is "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of s00_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of s00_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of s00_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of s00_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of s00_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of s00_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of s00_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s00_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s00_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of s00_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of s00_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
attribute X_INTERFACE_INFO of s00_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s00_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s00_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of s00_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of s00_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of s00_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of s00_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of s00_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of s00_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
begin
s00_axi_bresp(1) <= \<const0>\;
s00_axi_bresp(0) <= \<const0>\;
s00_axi_rresp(1) <= \<const0>\;
s00_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst: entity work.ip_design_led_controller_0_0_led_controller_v1_0
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => s00_axi_arready,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WREADY => s00_axi_wready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(3 downto 2),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(3 downto 2),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 16 | 142619 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
DFZ5WgRqjFT9lVyqK6nQpKgB80akrPBjimQzluHFLikgdYrj5bwA2ssN1ElOIV9nrvuu87ubKZBv
lnRe0OSrzA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kC0FQeS1WxNdMHZ6za9mILmkUWaq/YvbftmdmD/YvkxE9qXCzuQ4X/Kcd+x95IK0oLwYQ53mcHtv
EJQQ2fhu6R3T476x8WBoOkJkm/HOADjkpZm+Zg3MJSjn5sPtCsF4Z2/wkUlCmeZLLxI5OsYtWFyN
04svrx7Wq6Y6eU+BZBw=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xI46Pccjo8ThDecbCfZ+2ohSnYQOsnWr2St3oXXHpvwFg0Nu1rUBEPSQt4jcO/raYF0ZQvMZFiHg
KSyOn4d3AwPjS3FPjL+Ky0GBJMLNsYWxYDXZrfSova1B+0HzhVtGQ8xMO0ZRkqPilj00dH5Hg4rE
JlpIxyXjyhpSAWu96sw=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bFmZshi0sqkN643qM6zE1i27VisWSU5eY/nwaA2zsxUk3CqZcruFM4aqqI7SbeQ2eR59k2dkeUTC
m4raP91MF7BThgpZc4IkoR8C7KjDTBjNC9NjnSaEn9In4SiO+V3mvFEDMaW8s5fXjZ3hyBENWPaY
9YovoxnXbpPQ5325vf6Yevh9YCoyIasfp0RqxFxjNHdXJhHsp010HvJMvimpw2f5pdp1k55zFvXH
pitA/aB/99CW3J+QubemecW/ILdb7msBsNy0/qeyv4b9K8OPKLNSzredgiYa4fGbHzgphZqw1/a0
AtorqDnV6AITy6RHzZAUsvSRnUvt32AY3w8gQQ==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GT3YnJzupabpLi+SPy7VFa7UWjQwy7qFFlY58l/uq4gMFprj7TNyCu1vqVseo2VwzEizHzNcK7kH
1GqtX3RH+CceHQiYgdfMZldAK8gWy8GAkdwVj7zmpoUaIt5wYYMP3SDiidy/J3PDwAEN5imFQH5Z
xm8DPpTl//MGSwXokSPmpszqyH1WYwp8K/1j1JkB7HsIBpkoWthkUZZanmOf7weEx5wMxJkQpLz6
VPQXudw3YQYkb0Sy4QvLsAhlnfKh1Vq8HzScK7btRBJvs41joO9hm9fSDvjrFzJ+V2KNNEL4J2Pe
TT3vkjsziFz9KOQXBiVLM0jyNcQUSQjZy4pC4A==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Y6LshsPD1xF3TdW5KuFKeeUs/lgXWIJ7Je8GJUjsQs+U2qvOsyNMAInwIkk16UW3gxJ5JaFc4m10
mmnHCs3YIOr3JumCuS1jJogRkVTqPd2+o+j8FypFulSA7owquJjLTt5jm6RkpIqqdTzK0bv27ruA
/K5EPDB8CYmS5HhFZgaGGk6Ka0Ip5SB7ivzUfwsRLUw1Z+K3Epp0FNgWB2SoQOWMDTdpQa71cXsd
2OsgR12rpRLx16Ula1xC2MWeKR16MAnz2wagfpVIn/dCyIGHHVYBDYUrii40EP70ddOLlwG5SErt
jE/m+WDVJygvfcEun3Ys/e1u+V1AzDx+vNxUFw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103440)
`protect data_block
Uus/h2WhOYqYiBovodvY4reCVXdj8MkqJvk6OurfbPvYT8DjZZLZwSk9W1al8HkKHKI2YzvPoyk7
E0tqf5G5zjBbkC8OGD+gVyXjkqFP/vLWRONyn6sm3AuwYk6xcbp58eDCZF2LuE89NJkJ8WDRicXc
gUYTemHpUc38CpP6K6UysTDE8mrp1IdYLKkerSP5Emlj1x59fU/ngWGe0NF3XacyWvEPgglCx5f2
IZfC4qqhoWIcVz/FGZsO3mJwwqdLUZkE70ZS+eGs9DqgsuKlhIPkGBdq8zc6BQ87msO0MYY2tMSf
pE7VWKWn/UWZbmNENbD+DeLiIEVMiejsPL6lsYq5JNCuuJK9c1B5haoJZslLjosTnIfSZYT0iugL
L9z8HvHQle7srZ5mTEzOTPOE8EVXAt98A0UFSKf/5wlwxxn9vBN8PZuXQ6EDQXHhJXUY1O34XmzH
LwptSFTndPI8KSPwfnUvwHn2VgkI6sLq5KgWS9Gne56fpKrb5ZgBaoWi/JJ/yuGzHNHaIeLlhU74
3OATXl12Hr+A+CRzry4eGSPqsLJOqGAD6QjkZKDYaZcd/rMseK8KA/tO2hx9zhu1BMyjTUUDDgVQ
eU4ltoPS8HZWnPEqp9HY4YGmKXFLX5/L/Ppt8BWLpMvoVTI8twbzoGqXAubZQP8DbjM3QPF0v3nw
VVUIybmVZstWuqC7Rvizbj/9jCMogs8bE91jySiFacV8eF/NA14h3+bZ283JHbDxFZolIINws1Sr
e1qncd3n59ARJqGCAcN6Ahqmgrmmuu47RRrGJ2Rt88/ynRAO8jmK3XO5eZUztwJPIL0YPZAT8QuN
YPOGlG2Lg/ZF//T7quK39ASUxz+zXyr/hwi/nQXAqiVyjjBRWV0tvw1YKKYVOxPn5Y7/OLjAtcZN
vyxlsbsWO8bAcOmDpHJnM6dQ8uKFLd3bRH8fIAtrLXJDlbhX4SaQt6wrl/FoMuNI7PzaXDP/hY34
BohHDE4BOBXEtgxk0gJ8jO/TqVLbaury8WW42i3Rp59DMfJReVQ1qb7OE4VRRStddioyqkmb/0Oa
ZQ3X5oQhg7Q+L9j40rsUShBrYc5MqFRO/SV7n4Ely6/iuuTePvhJWHeonFhTQ1TAQnhH9UZ/skYT
/4sypJr6wQOdKlAbEvu2uZrKJvhZFQ+V/7awKxtpzjKqDCJz7YvQkJdySCvXVBBujceVzxldb4IK
THKFJAeU/VOaBnvwELlo8ORUE3zGQeh2EBCDkdhbLjYFmzkT7ojfVLctgkfEDHAHzKeZvOr9loe/
thQ9Lah2wLNOk9DAjXf4PtEAHUFRERZzv8svk6gI2u/7L7Nj7Nv5aC3tqNBbVV5XKNtqNqz61OC/
NPI/HfVrCu2Q9av+X3PWM/pT0ioE+l/JzyOkUD6/xFpp22KidpoRJKCMyYR6lz9j0ZAG4ntze0/W
pP0/t4u3ymhWUlylDxZ1KOIPC9GVPh3ezg+T6Z9JmIGVOSqgvT++CClff9LReADg7IvL0hdEFKxU
AOQ1V2PPNbTLt8QGDwU7ozs+AomGTpFDCeWRkDgHXLVvDw8XSTkFy1SqZ/KUw18XXs8pg9q+PMNV
kGQATXfTY55cXvp9+1Z+RwqNob0RGyCf1iSRt9p/+aNO8KMdDi/ao8WhLcrEIfaUydmfJ6Oja4l/
I6y52k3KdLBbd2FXynYAsaEelv6UmNCHO2QIIRdFzicYCGAQ11tBt26zzQvIdP4piJoESBoChq0U
cEhTPHxPuHkp/Zxb/v1gSCxj4MGj1kj+8FH2I5KyTwf6IwY/1+koepfup2Mp81mG2hbs3Vy5VF9C
zf1FboUnK5OGxM61dFt+Qx9feJ8Q1Q6BVHr3HOhGdoFQd1ZGXP4nEYTWKWmIJSCNbEPXqrJlPSp5
twYKdYHHSwr55mLQG7+f3mmpHdvjMKC5RkjZV6LRzGXvlvd+/fO4nipIqiiF2IzCDXaX3Vl3KlQz
z4A2/dVOqGXPEW3RkRX44DVgy+IhvBjcVeB8PBKoW23Y/osQEh17gUntzr/feDtzlXFp8XRUPgfu
ApcuoYHR52iAghfiOeTk5cr+KlNRF1d6LXPvxwrUy8loF9fnc9lkvsgvB+hPnUzrSBgFGcWKQA7O
XDu/XnRtUBSFwMQEnzxmNtHIEnnRjgeOq5oXMYgoX40pAqdMW+4wBxTi404mP3xCgLs+sq6w1tC7
JIeDzOmx2ognzEzLOltrpiqSU2GQVYNpCJfY+o38kc0ivz6RNPYOIFCOdE7o2Mw4TNm6uSJVYZoj
9HVE97cM7qMjsvoJYH6hkgrPxRBdT+AUFKjsb7NCx4CByB5PVlQuRbmIfu0dl4M25YVkW7pdT75Q
faejNVZ0MzICCSQs+A1JKHH9g3UpkSHMtdnc2e55n5KL085HkLb2rceex9LyRwG3+exmvBI5sxED
PCzJLP/5+jq9XSxaK3hzA86ZGFs+yJCag3CogAwnw4D98r6zyOEqRPK+JQKFbcvZRddm9V8gdEwJ
/Eu36BtReNrLlHtsBUff6yANfHb3HDJ/Suzr6qyU9gIzmblUTScrMnGTNlIEGD0SSlS53slnvG39
4QN58K0f1Fr6KcxoK2hPbGmKgO8MsTjDgUAO1hQ6vnG58p4bkt9stx+B+A2A0L0fxziX/kHqoxxV
6hbKUqCDnT27Wz4MV/gCxXnE1Z7SJrM3Jm/+bhmVOPb78cDPZx8vLIwdv6YPUPP/lTNz20NT1wrd
+eWgxOAq6RCr/raimIopvhVSbcT6e02UZYNIXg07nPEnk3PhbyCdIcrhwZ9Jvdq4mK1P/wOOkrNf
PIeC2L3o9+7WqP4aZtUkS9oqAbOzbREuB+1201zxf+sUzoL86yoOioBF5h3rv37BsWtw0Ufdu0Ks
Bo8JTLtD3ZZ8Qox/dLGc4bwUoSYjF071etQh/DDJ7GZMphnD2ne5Sr4HRW7uFZqyiFP/ug6Kp5Kh
e3/5Lbd61dad55C1SRZrJARaCqV4aOlfuYvVB4xlBHyd422xstno6u1bhdCuNQBu52FHxwO6IN0a
2106ywYHu3fzx1GuyjI5/Ya0YqBS93Ut4clNmPjNeGAW75JD9BjrX5y7AXz9RswIiUHdSv3ec525
8a1dKXTl98DAZXyAfNGoQd3ULV2EAofa83NM9CxoydHA8m3Ry3WOr68IPwtaWKAHkzIdenTihM/j
/qH32nD/25i1HK2qlvVL8a1rogua/UL4UL+A/Z95uBVEdEDSmv0EA13v4Rz25ruCzduSFSfR+W/3
uPNmnpm1lDmCt7NnqACA+XsjHI80vWaH8guhN42Ega/iRezkNoUupiMfEeD3CZ+BU5tB8htxPuzO
Hafagc/L9sVC/62loWVFu8vOVpyRSscNwOwfsQCz1ztdJ5mBC43fDn0y9NXegH369JcXY6x4QMsb
3Hlq1GUAcwtpwqPoq2BtTtfI1fjsAGdm5gDIfCyoUIUmCquotjUFBw+G/cRVoZBSSy0XTZqm+ZtT
hFvVsCqR0/4seLSyc8Etm7qDdDVVeO88jpBIDCFvn/OnkJOr2HO7Fz04Ur8HyxvXhKQeaPSQJ/mt
tVYQZM6Az112g0Kcspm7UoY8fSNNqebsnHkWaQ0yRt0+iKl0Ier8WKpxx5URJVbI2/LJqM0Z1gvW
IhhppcCxnkX6LAJSuER7U4RYXOWSWxLOfjwp2fi2Zo/RV397AxfIPV/R5DasTPWRNP1CK54XDlbm
fQGb6wvB0LrvNsavQlL1FJ6tcBo2Pyrs/6g1Uu2MMPIuD+x6j7kuPP7lBfqj+9SN3LXwltxqf96O
ehz68S9xPkHyuo17u0BS5h7Wquxo0s2M2G5f8Vec5H/vIapxCq2B0ARYtuMlWdpPFp0DKCu+2ShK
nLJWPLzTOzb+CFNiOpsOnm+efHcNbxeCaDx8N7qzskHvUAiyfwDc+UNYlYOksXHc431jUGCrOHfP
2ReJWWSrW08uUSq9IxU3Inw4F23b4uX3ouXK7Y7VeelFY6UnkauhR8fOzSmmG8PmzBIGma4nh8M4
S3Oscge+T2udMuK8qW7xOqFhswGx4gm9zEQYO1nEP2bDf5gvKVpIupE1O68ZHEeZb1IWLH1LMHSr
7bCgixtATHLhM8VLT9Dj+rQQeq5UjisBbi+ZqZhThIqlw/1TpK9RDV1S9XPSN3YzMeiHmieLJ1rE
w3F6uTscgXDnosoZ4yurWC9ZtXhs+tc0uulRjdcgFULhkc9yRJzNUexhWV8lMYNFUntN8GRLTqKH
k908zpCHcANqjEq/g7OGtj8Qcg/abDa139MoWZCXB89eOixZy0sgbGangSywSqjyvmeT7Oq9ZBDE
CMPg6F2g/CxyLNq2XXQGQQ/Ar9m0EmxWz6eXg4hLyRIsnbZfzgioEdmUxaX2ld5Su+/zRp7AgKRV
9rQB3+kByZwxQq0JWOlr+eKCkefNdFT85hMxBv/RK4D+N6jIt43vaZd21E4TMOjaDYS8zBQKDGr3
7xmZ6LDQGOW66S/M2x1AV+XiqSXQ3JPkD0Ml6+aFXWtEPsbYdcstdW4pYfVoaQxIAnVGA4lNPBQl
3+BEbzU41S5yAE3u7zWPM6ilJzoLHfRQQodFRUc97znxrDwQDaYu3y6J/811OuLN3eXCHDzIUf5j
ZEFi2+U1L8jALHh/8OM7vw3BCGYFX9bPKtyiQSTzYBRC9CJuhLHe/+1ArDNgGA8pLbeRkuPy9n7D
SLyV/QGTA6c5ZLnMVr/ZacyEmyNTkXnEtILwrOCDv/mmS+RWoM2WdxMXLTdT05ZUrzyftHXTT2Xo
SB6jaIgWTdtyNFnbKUx5i1TpFG4FIbZDNh0mWlH9Lrp9Sv+RqMqPkcaZLYLqyP4KorntXXS8lBfc
t5V/aCVAh0VRcLElm/t0/8jC2zRz+1tso4zq5XOtbfIFT/eyo2xWm9kPuxFNR0KrULsWZ9ISVJTT
eWeSIsivY3DMEHbPHEWuiqpR5NyuvrD/80fn+QigH/HPVxeKsDnvWi+I9bwvUSIjTEL15U4hdizM
jUwLp5rLd0ayxdWsYOREt2XWOTmFZH4Gl9ycxbM8bX+F39DfN4mC3wuK0VL9rdj9/vdKKMpCPKZc
WNGAch12/MJ92oTbZCt8UNjWF/0LAFr2JVuscg3y1V/bWG8Og9uAcsXCtX2ZBkHWyNI5p29CONsO
VA7J2WKABj7aUbBXbWuMayBzpidw+/r760GGut/ualHp0+k50YeUO0wbqe+cE5GRu4ted/nTFlew
1Vx1OCrqEaKjJ+r7WlYMNoxtIP+cHRTJNtQ8JpF2Sali7tppYdACx1lSHDV66XZWXUp9uHketmCq
fCH8woZh+fw8tbn+swozrGKAs4Ob8nfYMVLM0cb9vQCMp6wEeGC6O2vPaakZEW4AG0/2vnxT9MTr
BUWpniOwGZMpVyE5XhEgwHevmB40F5L6MnGJuhf9dzLuOvB5amnnV2Ri8w3p9s6nkNhu3j1AEctS
QH6DXryMkpKNAQOctkaTRTAqTEBaplUG6d5u0TgPertpibSxFZ6dgpwO6XD4iDwTqCuQx+ikafAl
9elTSMXXPKb3DabYEQKfReyv7TLJLKWuTccsc+4daBU3d67WsnX/wyj3DvQucZF9qn2Uo3yZwgvb
dzc/leTWVTqbMMNoV7fXDYP6YD2Yv+F9+XoSHR5O997rKnGFDHA6FdEC8bZDuvzSu768836JsYuY
p6KEOZb1UViOD5BENorNlOstDIYK5VBMwzmH/fynGVLHsRPkxxeHGzTxHT6ikh/ttPm0+yJpaY8s
9gAuoU1tuDWUhwnyGFc2PhBz+I+m8U6IZY5VfCN3rBv61eIgW4sUYOK+0yZtPmIq/OAZFDdwi3YN
VegFxwQnaHPrAvH/9+BKn5qipfqFHwpj4FzOnGagUCUFCb5ComDeSgMlx6kB+/XzqAtzamexxONv
FwGa3r4apzFzF1Enn5sXAkvcBZg/nIKnVFH47jBp/kIG79FzEZH0v61F8Q99WdRWWPMZlaY4YpuT
z8lLPKa5apa2eMfhC97OvDPww4e/BCTDbZKUbTgsK2mJDXkpzDXMsEVIqTkzI7ecoSiJw2VdYMZq
akJv7Zg3UpOX+T28PHdEzYFkU469AtADY0hlNdGQgapcUyKPxtjccvTNvCSIdylh1vU1zKvkShin
pluNe/pDcnXJFlCZDcvXxGTbAqEQQ5GfJfOi2Bjk7XCsX8JFmt3HD1YLv3EZkONQxXCHcXajPnoc
1IxPHyRnBytmbuPp+WyVbVr3cdnk3CtvCDRpmZB/6HZriNGXFrQ2x6tAc50POyIukcAuMf25QkML
FmHWkWxSItD1sibPEQJlUCofuwhMP0AV6w9g5uqDIjal2Z8mMAApJU7zk+T6aiTTgBKGkGQKVYOY
zwsPWmGtfkFDBL0odu0Jj89CQtcjdIPbidRQtgTzNEx6u1ARWCfA3XBaylm0JUNwv54WLU9URIwO
M0Undn/NLcISyMCY8PKHyxWKp2h7QSRaR3IGv/tXG6NWk50l3NvIHeQlLFN/92OC7mvu/G5e+owq
p8b9GnV4xOWAEYMiLZKkcfD0btGgjLJGgHm+M+J3pAGVZYA6Di+VCM1xWp8b0MFMyIRejeVIYlsX
ZgrA3gYrWHGXfLif0XZ25laddyGY2QeKVMdpclVX3LCE9uG2zMazrw4y3vwl00vAzRO0QgF5xP7E
G7/Cq122a142mu8gmKM81AFWRoYwmfYSaZE1CkZPsCEBLjw+vRMftXyt+kXnTFlXebUlksW//ENj
eLB4OaG4Vv6DmFqPjdUjydTIja5mz1Tx3jFHeXAHWvnUHcSh2kDak2e2pCwVOEIsPw7/pwPBHWlu
mCgHRryejG18Zb57Khn0bBWIS0qvURN6zG2mf6K1v8mZiT2/K0X1v36C9czsyqvhn0TiM++aMsvM
TkmmtXe35UjJfRrAFXYd/Kh7GNrqzYe5Kezq44O3f3g54XX+tU0jkdAb0a/J6cerfyDJhkh8rk8/
mdHMOP+MnYYxmPPBBSaBzUJ3ApGIHykXoH0+K1hxp9I1Zf5DbDlIHkkn8HZtbYPHhAOdvfziXC1f
y5cNW2dWoUdmBwmser48CyWa34YbABQVDKxi9s3WnmCKf73lplktMTqvz5cES4IWry9JuQX4cYD7
w67GQ20+gEsjnASybFQwX/6d7azgr9ef97xBSNkSR8v5Kxj/UpI3rPQC3yr8okPuDZSPn1j+HejW
T5HR8J0I6ayxU7rqmANkZ6bbMLxRb0wv6Kdp3EgI/SnrNabAvwVLLkXdAri8JcMg7eDVkPcSfZh2
fCvvWThvGto/ODNnQVkGr4YFeV4MWvvXsZmdOBXEmzbDOMAJ7sMVuZXnCLYcqK8bp3hTusxrInnK
ODXQdlUi+KNXmvHsx5kkIYL/bAUzDRhPJzCJT23pUMiZuL/qppez0fW8MvZrQnAT8j28Qd4cR1eE
Pf4SrIX3kP8czqyKW6C7gV+7lFa4SIGFqkpDPigQKA7KJqW3FR6RSVTa6N0TItPb2698ML3hvRJA
yWFvbCRcHUhywleQhLL5eaDxNwG5QRLmcY0rGYsFWMxyL/gksQ6hQFKlUiUnKIHL25d5hnanKbeJ
r30jyB1UuyUmB1j43cdFvhIbyVr8unc4jvFJ7QHTUMZSux7yLVeBYmta01Fa9ee5xcTtJSkZUbdl
UOePiUvHrGXHKxW5zKoIlZR1+dUL3nj5jIR6CE3Vb2/RMqjqgVGiwYESCGuLGLhKxub6APP3sw7v
yEPVCRwmcR0oHT81LX1x79rht50ThzHPfmpTVC7UsRYuVLwWNP2TgNd9Jmr8/VdJ+qRfutJgoz+N
9KooP5bqH3QXgsRTNBpdRlNxEY62iO+B4Plm+PXUey6pJrWrbM23s8t14sYmvRE15yi+ZrqsUnbW
VAukmV6rNx0pDakcjAmTle/sGA1D8MFOeVVWOme6RhT4R8XeXCzxNSrqjOB+fs+7Aolz3xPAoPc5
GvNWHA4HuGBzsdPZ2tori2R2NZ5FFiWznPsQfVvYVj/F2K6W+3sAJxrt/U3vjo8kYPgKDe+s3VRP
17KCHKcpFT4OHnvLZkN9lW3tYbjClhrvgpPmmlV8cRpWLHWPcNOOuQbNteU164E2L4KM1vlpEtsn
kg5u390k59DL6HGF/pqX3nhT4+X/BQXwv8C19xUkO7W3byP+RnEy2ykyda6btjNBs+EyIwn0suxl
GQ+O+lz6fMEe1vFc4a2GFo7i3JLq8/Cu8GjIzyvSKJeWXwqR9H1ktkvS07vH8gaTriN3UlPGr1a2
qWyUs4J8uUw0wV/lmm6j7/5Rrh98D0OFgHRaWoJMoyRxr2W8hwiCgn2n1PmUBnsbYcfgztNllTha
xg4TsNETCI5CMvnj0G9MCdgMwyUr53Ttsow5IJXwJJhv+N5ZmZL4EI3Cvwg704/ghjvnntDZPvzu
T1gW+IX7ZFwTbXwReHDXpRknXA4AzML6up4KyOA6dk/xKFXbzgPyGOng/y52eSfFOndDfriU2dV9
CGRXICeFiHIrdaM0iqYlFbPNpIgciVnkwQMV1DWOEH5oJmzZo+ZYzjtYgT7ChrpV0tbGYcyIaMAZ
hIfRMTd6py5WyivYN9Xf14mIINzO2EhM8qHu6AKZTD5WNwLE6bCndTmYho6ewHYachiqQAOzlXuL
i2U9H01fjpjafD0FqJvZvMzVL0vreOvyPupTwj55oZMCksIF0RaneVMQj0NiAyvY78NNWEl0bU4R
9svWGDkdG/CXCqBnIDPS7kj88gijT8lOmVe5FmjykCXjXKBglA+3glZhFm9nWNoV0FdiH0d45vau
ut9Qj5bgRA5fhPNif+2/QH9vxz7q8CmqBPoX0Ixvq/xxvlAVo8zKrucFMpqXKWdeDr6s+A84f3IO
3ohh8vyQJjeNfEJTQeHnFp+6eOpmkqGQJn6cdYechFd30lnATMQr93BK/f/KJ9qfjJRpV4Hj7gCt
1p3zSWOP2JXxgzZhDtX4DIRNLN99Hg38e4uLr3iA4bKy0PfE7TijDI9iw1aO+deKnfrSFtrKuP/K
MJk6FqbQ++7fGIHxWZ5rzJnmKsFkRgbVPMZwM16D/Pui7b+iZHBTCrun0ekwjItODyVHxZebkrvU
FZjdzSZieiFnkoAl4N0TQ0MQ4Z++qqMNiao/SskvxaYt6CSgkKkujNXRVzdemh+AAlrMzbcMU/TM
P+rRGVYHqVhzVldcXZHj2wm3e5wZAMv6A5NCedZmkIu7YnH/2KhtSXOe8H7r9gKWUKPAg4fifle/
ICYTWi3eLV4NIXianAzX25AAVo16EffSCUaf6KU5EiJy74IU5esMzTS1YNdByT17ShI126y7kewx
Z2p40P0/c7SuX2H0IpyXD7UV44hZqt7NFBhPpyP5wIOCipqlUG/pKZ5T5aieYAinliwmDM1rIchg
OoishVCcTGE9LZDCF5VtOC4+5snEl2JImH3zH8LTHjhM9+17kAuit6uNaF9/vppwFVIRibtXaspn
r8jaR2ZZqW/dsLOOOnb1CDgj9kzH4QPKXCyprVh0NW/u7lBs13D8DoaTYn3CZzrEqdqx8/opIRl+
MkXmAjaGj6oBo0Ky1DxlRxq5Hg1Gn7kdSCgD7/hj9fD9obL0LD+fP8KzdBqej+0Y0XExFzgPSOVl
DT2y804KrE7por3bYI/cU2x73czEESsTOhUkdBEsOxyQ6o0RQ371ChPV+fPU+4bLPheU9bxG5nzU
LcuyT/pTiX7DhrcQvmRR19CHsUxlQT/v0/G0Zy5q72OkEqXC6pmFVWvebFdT7BhN2244txQS9FbK
aYZuqhgJzdtfwaEgE0G5BaDM9xDWxdZiTEddwMZJTOlZKpnIVE6cxeLUObD/QqR9aBc36i1jWolX
PMSczey3h5zgyR+/9bEuebLeAqh03cjRj6NYh3EZS/KyPjuQ2G43vphEstWN+cRW+knikiHLyCuX
WN6ai92A0x58BJPyeST4IZIzraPDdxbmmd1BRORk+jYD1bv0qagmqf6Xyc73opXGDSoq9WeOXfEm
+ALEl6i//dgc4P9bF4j7lhVpdBHXEgueiVDusPZIgkdCYwiUNY+o1vi2sftSdK6RTIWfYDZGYQFq
5j/Iwmg/wlB06rrAn6Fy500Y8cJULLYtLDek73NalQQbSJSCwLWAJ+oJH7IHz5L59rHnELyHDGbb
/4T5JvjEXezHDJCkHZXbBactmHod7nawmzrXhBe3wxLQYl+NQCvaMae+1a0OLwmVrY6OlhloO4c+
Qs2ptsuaDYvznEwoIqNEAFdByHctFXZBRuY/VljbQIV1MMFFszjhMRmsLMAuFY1UtQ1cmDVh88wc
B6XugWuSvEUUAYQ0NRDbGbE2baazyAoxTqkuYjGKlwcYvmJrkLg7NrqGO6RHcGh4lU8DIt0Qo77y
Nb922+6VFBQvCacdKsYoOhen6CgFV/P1YChzYVb/TVLMOJaYjQlIbF160Au8Jayf90a1O8m7hLzH
DXINTt/AnkJjZf3Xc7nBPbMU+sJHUWzKZlmlJJfB3kdBL8KfVyDpalYBruPeC2TSWx/whT58KP5V
BWZQtK6hzHzD++Y73+BYTWizYdRwaz+Nr3+dXO5M4K9UD+F1Z7ABsH2mmtI15xdUxyaqE4w8aljx
oO76dR770qssbIpTKHRXgLnvqFl1aGTSbqoQdy6MleelyDUURSw3y35XCZPLybNRz0McYlnIzKWj
d1HFQnVgTPJsLE4OkZp0cIKVeJqqoYFM583sD6QIqQGqodYxZHExXG3fewamigR3Dcc1cTBO78l9
VM8jg3tHi0WJk3I43HB9da2vYyVrj6G3y8/WTs2h+RGJ8eRYa0ewiJ7VwZXSZF8V9QKjD2VFaT0w
u2YUfLZdWmal3+hN1RmFlzgQLwxDITvBZijcJ48MLsUTdybtOBx2JvAgLOyUeVWm65iKg0daG96K
i6MOyQ9AonaUf4kOt7EzJGuiH5SYtkQYzEvGN5vqfSA58cHJOf3LdyQ5HkWlVbFQmiEKuotZzRhv
u9y/+NBB1+0s1SOAdBLUb8D4Z6Tbrl6K0uSJY92pAi6dhs5DnVCXpY11C7xHrElWZZnfHU/TJUit
Vshv+yQYgbn+a4TGOvvi4rssBqbqvCOdnCZOExpsj2n3379gqYxnYMwKlf0bkSAksDt+tf7NxgYD
dIyqOaNQS9Jglpt2bxrJMHFsnJTEwIkwHaSAK/v0WjKKuaccykIsvNoKtKJ+Ag85zmF/Vo3D7Q2k
nbbPoIZvQO1l8tEGA3FUNJB0xvkKNfokoViFKssOqmFKPgPWf1zufGXBNuGZykoK2C4gH7d9jqvx
60Qay3gvF1oxk0lJSsr8l4q97FEcq2lHel8URGRy/7EM1cBgBeJcPdURDabbqboUDeKEBLqxZkGQ
cH/ehOaOR1o6Um8SuLSworyVXttDYsGPs73IJsMUMP0PqlYB8ofURRjvL56UWi5abmPtWr4FGn+F
u48qM5JnUsakruadzqL28S789mbKQ0J3DEAgTYhjqgckL0DQdXd74es5uPRvCiBCdeoUqTkaMt/I
n14vG4tzhPrIK5CDNBykvdCxDFbOYm/HZRTMNEVFf6Pl38yjNBW7XoWD8t2YVUA9cDAXtPegCrRb
lnXNa3b+wh2bIfQyH0YB/mYsf3t++7Yk51fNJ27x+T3N8GC1bto9KFyzbJDZf+2effqWSGT3jpln
tOu95YuU9rSZycX1/CEOjHK4u9qcP+rgLqcha5FfrTncW0363+ghhFndVhj5ZH3sJFBBMQ8RS7KX
JuuUROat83z01Pl4TfwHUB/sSXGWFrAP4fwODYYcRUd9SpdzLuxdFUOcEy3EPApzyKIfKzNM50f9
2eDCaaEKN6yTG4SSAgyyRzwoqn5cBX75gWg5r6yauuaDe8ZrlRV3aBn1FW4WbFeVnhRk/QIfLH0y
zMuH5XVfoQmuc+YLTjJDiD5JICtxxMkOrJ37EeMHQvwQWrNejZ8tMZfHE3DAIx8skAKQU+GMQR75
wwxkGXWpZorqDwM1m/JBBeh4PQNPo6yPlGPspvM8J1pdL4MF6LML9/LlhO3V54saVeVvSs4M3nBs
V1YzTso+CVCJ9xjXoTObuUPUc+KyjqQIKCECe9332EHHitS6XxvNp6sm9v5FjyPmZgwaTgDEmMld
P4MKIQlNIxXxscXA8/bmkzohgQBOMYxwJIE/ELFT2+qD+bYFv9NJrFXdH5zDYY5WS3SHKbFC/ckh
gs4BUXiXHaVasXKKvLhxykK+OB+ICdUANp6OKyo5Xn9WAiliBB9V55CYJv1YfP4No4q6YpxPxaVY
rS6Ud/BbCIqp4rIrAiGhcxc3/DXkEB2YzZiTbmq+npR1HdFdtq38TcX+bL1z2nPao5eb+Rx5LPym
Py6Hz5GLXBLBCtQaVFT5a4mgcbqVXWGV/cRMYjAI3lAUcFj/84t8gko/eG3qDFL55rHF3D3dzEjH
M7u3fSe7R0MuRPC6Bep6F1m+ozy1e+3H631J+VqTk2v0BPrCrUTqVi16CwNWTm5tuwRCH9nE8tew
grHOhKHKG7ZVeVJymRF5HUXwLdzSH3Kmk3L/Rab2RxLIaBo7XoB5Mcl6lsbHIV0TtTrOgtSyqx88
z54VmFcbjJRhYLF6sYH4lcCsRi3f8RAC+BAZJnUCB7B1lQro4pHlskR49QJeJrSb+9H0kdCZP8+g
tNBLdOHE1azp3Ea4cHiwFbfAlz9kWWyPYZcug9jSTLH9FBVyQav6pvPwOkDUvjLKurBuP+j8pc6c
jUy4pbuhH3n7T2qWMi97KgyqsPZ+m5rAEQ4N5wM5u5dM6PHMYXblQ4VBd9+eNNRViohbeRgku8sT
v6jpD/UAGpELcBzFt5ItVB11n0ePht2671WCZUaZsaCk1s+MDXsk4rzNKgE+/MovKBjtQSab7CIQ
tZDmyi/Isx7gAz8ZZMjqN2kmj3GRtPH8cp4WnwOCgfVAOtFHUTFX45Qoz6QhtueK7iQUVzPtP1jG
6Dr+su+bA2h4qY4pC87SQ6mXa/cldb/c7U4yPCHDRXZLY6+/vZpq5y2PeaokLpuGWOSDKOZR/3rx
G97jozjfHNpwcDP5O9Rbj2QWNaK0XWTjxRzkZylA/KVrxI/HNdW7mLK8Edv27UoNAYRkmgwGNKC9
Q+/Zz14Ytn7esb0gryTxv4ln38Et34dZ2g1fnUE6xE4n57/4DH0kMTdpTIoyB+QqZan9wnfe/37m
AXKCSMO/CUaW5l49fwikcrLnSwTFunZ3z28bQrKat5Cf/P8MbocUiHD9kc8I64eu3ttzk0gjg4Ct
LyBl2+e8if7PK6xyryAbewq1np68MvaonEaUBUzxxP48iSdbKGbtDoJxcfHiyeRDhSyBh4mOFF2D
8bRncIk/Qq+lCtaz/OiAkuA1JeGNh73SV2AOI3SmVKRqIlmZQe6bSK53ePSJSYaOfX1nplMWv8fm
AIVyspEP/xM4Y6hgTz83/l7z5XXfvXEb8M+xqEZyoDlZgAxpy3IeHFQnLerewar/9ZI4SvQegdo0
DsjQI3DKkO2LJFy5xks5s03uinSWIGZ1l+col/wv+l5vQcH9p7XyDSVjNw3faI+PJI0Mz+D9nc+v
A6rs73sdJFtz/r8vpTXYSFobRtGyUBZ/o2hgTult57WClqGEVDP5o1KLQKR4Hn7S/Ftc1N1jKaY9
Zk3g0n+PauKqoA75Js1HsZoINUs12L48GPnfYk9URrMdkSyvhq6KZMweqnF+xP1OuCtlgYDnGyWs
dEqhz8HjaakBPUcZZXRdJm472DnTOgB124E5v4k8MI4Lddskum+Odne63QLoiRTdwE5dV4cTs13d
/ntLD6jrjfYH0wikSmv57NzQBplAxW+RbrlWdfZWlCn4dptpArzLm1ME14AtVS7Mf0INI832vUxc
LoAuxDx0gW6EMuLlSf/6wqY01sXRu2xWfmcsn8fQWjeIRbSL5IzXZ0anNoVSIUwnYcKgOtB/xoqO
ZQkMMyZVA4NH+vo6HlBaeqfKP3WHq4KMD0cH2MdkSaz5oJQadXQD8uLi/pr78CdK6VDuEMValdjH
LbsunhKCqfasQiQ/iC6pAVGl8JBMFdVdYWpo4pFfdgvEh25hlKvSJ5Wo/5z5kiB4vualXr74vr94
Y/qbh6jbjWbpCkt0kFyB/5p+4lrBlI5PUce+Rxxjuhslky9USWWM6dbXaS4PcJCJ60uUvXAfTNAV
2fIbL2Yv4mjEjKR77CXI7fsByhTcyLKwlGH5UDIziT6vHKxPdH/ejrbrfG4f5foz+LiRdCFmNA7L
Jm4HbBvAyb8Jk1+jnz7MVGndmb0Ky8r6wEYNmka4aEBOOXAwcNTq1Ao7ljxpvko+rpzqJgcbm0rv
4L22zkN+8Je3ZMLWLgj3+e3uhWkkmjtqb+sMvjMq7zTPCm1425GIMvP/czpIzZl/kPDOkceMKT4O
3uh+GxzKOq6CID+QtTVjMnBxkYAYzpocF8sFsHMqXQpUqNnzm75CrD9aR8zlWtAAd66LfiSpK4JK
Lgbn++bo6kYiVWeYMG8WD/dDsF4ac5KDAfhIioHqPvwZM6dG6Kxs+dd8AHXOvQPdQktTh+ownlJc
gsJDlLFokKTixdCtBODXCDajifl748vH5xMAGW8/uOsTiwHkZF79r3pNQWKJMQkA+lou7Vx6X1w/
Jsj9cxRysO0MNBsuJRO7Hamu6RmoR8v/qMSngsJqf/5PtRSVo3j0V+84c1NKbaWj73QBdS1++vhj
Td9A9zrBPdKjttdlU3tFSg1xzoCT0iotxUZvS6awxcGC9JtmxLe3aQ/0VHB4qlCnB5LqgvRKBBul
7/fBZrBwHqyB5aVKL8qqa3+1JtdkHb8//x0EwKTbRh3edfEHpw1jGSvDJZU8jA01v5M5DxjuglYQ
5D8D/pgW9W0lpDJXOFgzuUH2U6k/kgwYRmCx4o+MLMKy+4Idya8KVc6qwYSOpHEyDTP3mXcQN6Kn
aQs+NsJNTMtUhxe0LXUrWi5YYK4enJnESBu3DSE/SHsh8uykSCj1E1h5d0ywfaW7KmOGtZwHhilB
EKjEBJ8qBp978sCw3YryCcfIB+BMVVGKWdZQ+7bq932D8SYQzpxiqhlL9hK5iP8+s5T2QrqO33vs
r54UcQ+ke4Hp6k+FH2iag3s8rxhfNyarCQj0i8swBozmKn4Qlg+jc1rI+8LxI9CXU6mseGlB3gbT
AUhovUrKyjd2Mdao/o9xqR1jWjepH3mc+DrNkK4mCWhzM7t40Si3WlXeDYaQJJlXH9HoaMzSyxSL
4xjFitn/Rr0zONeJRxdYRk63qr+t9rWXFH8xCGCVhmi7CDZv5NAMFaIJL6MrRMQAX1MKMj4OiBkc
iBAzbiOF6yKhzFm/VEJAqaII1JlJ65VI+0+zvHqz8UnIGKr/OKcPc17qePZ6vX2vOQL2ILrpDQ1I
mceAfhiRfhJsOlzNJI1WU2pDg2it+bYR/fa1sylXAcmoHY+kPuyqyRPUMy8xi4sT2Kz2haencEtu
fw+itzOcRwUV8xDs9d1KVbx+rusvD3ffna+yfc4l/6zJ0ebWsijhxEWc7zTSne1UqN9sD7rL0yRP
Jw115CgBFTVhTAZQuYiJ/5n/3lFtMKUJRnBXT/VkhWcPBVnuPA4mPoA6LFwh4HS9kSUr/ADnT2fG
O0gQyGBqjuK8kGvXeHquvufij1QmRGj9yaxUvho6SQfWwUinwegKW5cGA2U/hLhkU8rmaGBUne/4
loWNVcbGZRVBJGAYLXVGLAInRrA2WVn7lNOUkSQHmUsEMuOVEhFUWR4vCWJHPWN0/Q/koWRNT2BX
2ZLh9TQVNTFeI0FkwlhJQv6bXMnb2i/dY4luShH+u1VIZ0CZ1w7cntf6wJIkQZ6ehfFrk8GU6gYw
S5w7oeXouamvXcPtp3x49HonZmh8cy10sc6Utk0DpYiAWWmd0/rAkj8b+DdHqx9XxAajqWjJmgwT
EVmuatDpo7TL2ita1wOWwMaDX9ID8za+2jrPybt6AYCRvAA4q1vxzhQWlJLtwBNm1hyDNChE49Z3
avW0pG51ISZ0rPFBdVogoXjYjKCesOxCDRqEynhRU/28wiU09UV9HcSTu8HMCyh+UcthrFp0Ef+/
2j762GThZ+OrD5bj9+GjQqU0uP7ULQlWNoQV0STMF2eqkxXvf0SzFzrDJlJpHuKCRX7oQ7OBhYsN
GMMVZxyo2rtlP4odoLjGaDqdOCKbu4L++dg6rv8tbc6ZsWvPuZgLe7C4f4f2vohI6yT2CzSDSsh7
tJbID/ZeA8qdp1+0gpHF9TFFv0CMEV8IyzsUhi7UzLJLw+myCsLXk8hukC9DY/QiIsmbxJ08CY/1
GPKKhOZOZyE8ErOnpuwfEyyqDmdz4KdNW0RP2+6LGIlgQFh3HL5XJ99pA/HAh2kg1ZDaocGUjtv5
WVKH2k7Ueqeb2pjy2ebW+FDNdlsKnkOdF7EK0e2ODQrAA7E4Pz9ZL6Bp0tX6TTGFbUbfZoRAGANA
NFZCuAHj4WUEjrhEmbUxP4C4T+22vndl7Rqh2weTM4QJbhP2vnstGmrxB35lFmnGO3bIxggX4+qv
pPos22sGRNRHz/mbPXKc4qw0Z5ATwSf1bY7AxFnxyWSNCfY/0UWLIiMqtD9eJTUVh7eA3roThg78
J/t00JBq6BIbGCnk4OgM3N5m7niGAM8v1AedongENZfqJLVi4d4YkHiYWDL/DZKC5W6Pbo7k9pa6
gxx2hT6tvV6nz+3yRe7tM1OcY08kyQ3BgUAQYlKLuSUClH7mtpMPb5b9RSsvKrPlcmqQBI2+EAPq
VGiGYp2W06uZoHxogsfoAa/4eRUVPPOWyKb2tyfnwtw5wxAVQSlAOnCxA6ifXadg7ZR+9JWYyoAy
MCMDMugBKMjVwnRhnU8PtoT/RJNKct8ocCEXehcTleKHPbCwnvkPlV/Lz5Td0iD1S9NTr5Ucvi0A
z8klNgDfr/xYGWWfLZXysq4b/Qq1aArN6ou33xVtQhv5Yk6ofhOoooP/m5iQsnG26PraoOlM6pal
dDQWUrFEpX4WKDZqHYIhZR5wlxmhUGeRF5P2TeWa5njfVc7GLk2DsigMNIRLnQ/FSgXiHiCKe5p6
46R5gpEqaHPxlVrPGzZMTGx2dhr1bsTNDhSu0Tt54hPUhBRfe6J5rfPHyTi6jEwOvLE50XEqm0Xs
BsYW1PP+PZIA3P3pcq4NGBXd2X+pzxEkb5qroVgJgJux6ewJuM4qTO5uK1l2MytWVdaYR47GYYrL
VUBuj3xZwPWVhEE9iTFxw13GldcOnWd5IK2m+5t927PWnvhZuzsFlkjqJZznXCnWU675S2GrswxZ
+InYl2eIX0/52uS8RJifXvQ/3cypem2D8ml27gXrRLf6jKMEmyWjPXFpdw7wRs2EbqKjTc8/ey5o
aFbqqOu+j9eXvXUBDV9slwrRpxCf4LIiJEnNyY7R8loBvDO0Ie6WnHaFnA7ZCmuWmD23xxYqLzfY
eechOVHonx089aU41vawtxQCr3iVZ8AvNohvjUME0h/kWiT00+0kKXh3DOhwof0XAQ5rkHFYF6Jq
FXvFQFMEHJPg4QsycCbUSqVtMab5AFyqLkNThakmM/H94johAEhekMWO4HDwNYhZcMsr6qhiYZTT
qn0SERK7cf8t4THp1rqMnR9dj+Oh6gm+7mIeCp9qSWr0L1o2JKqIAe+EUD//LLGPHva66otyGQnT
/rPvrz3mYXVVCJeha2eNF94zP+4rasZhSjoJXM6Im+aYLJOS7tzo6P3SnBN4vOK0US+R5ry/pCU9
bCKZXP/kRSGcHOuKI1be+3/KmbV2E3goZgjqEU5sPuuawmOQ/l2U+s0XiciJDdW8Nff7kNDlDOVP
x5IyywmJQD6tu7Y7U1WkAsu3Q0U++srAfMBcUWWdfNetQJs986i4wE8vGSF46Jxh9+hDaYomXnD+
DXlYc6tDBUokQvDpPqublk8CIyLIwrW40xuEUKcwfS1d9CzlAAfO5mtCePsNmr+HlzJaHH/f4ZpW
je48GEgS5KOFP5x5BwKcwL48zB0OeL8nJ+qLyD5yP6agMyns0r/sZIRua8MyIHzOt73Nz3OUE+or
TxdAmnghJDo0rUN9bdwyfrMoaTk8FN0WCcjDusuOfXM4JV6Nhme0a8rd/W/jEi8XEGnjBsFtv2t/
m8073KkDtg+hOWD4Hfn8bWe2x+bp8FbYTzrqe9W/ScWso/cDgfShd8nLAdeXH3Vcto2lljxs+xu3
swP3UwnZeRWXDxiNqPVyjoDuAtRc++D+Xd9Yz9DNBIl71H4RS9UrrcLM8qBAHEaRe5+Ui+wV8EBY
HQMGGhCS3564ZuQXRjuApCPkdIv8m/NBowrCNpOzjOvUNEJ4TeG/zR+9p5J0q0t15v2X1E5bBkpu
EGoYSVV0G2AjdvqOLxs83FwJoEVdSPFEAIjVxZs/ZqCPKnSDTeVv7/rvk7PgnfNMwEONtOuDxDsH
XE0uQ69ABlmAkRsSqpUebGjpsFeyDUqHTmc0VXkMFUKoFwR5u5/ERP3aY7rpAVJ47lqAU2oPO2k2
m9RNo5jvVkZMJRVlKtcGHIqrMrez9TCaqcfLo8g6KzItmEhOA94z33ashyKfe2dHVnKZ0ceGiBsJ
HC1blI9MJZ8HtVCgK06dFkFg1OR1meE40AWqFxFATq5bU6Rbq0jmRHI01Ks3MHLiGxwV5RSKSzPR
XCwWtGUjDphxWrHn0+ZF4W/erjn5rzHdOavCuMQWbpuP7zngzFDSiL4aMVPi58T3P+e8ACBZ+XLL
DEPbabjsXg6yEqyKO8wpzZF3Uru+Z3WjUbACVRr43q/oTEcgs5FbpawwVSvfL43JntPnWC/LU/ZY
znAzejqZIVJyiVy04mmBkqH5i5+hSmJfCbT9FmqZ0VMNFxnXGjqFvsk37Ax+cZ30zm4NtvcCT4U9
ZKFDyLqpV01aNV/0NsuNRxpHCoM5FkYdT/gYsKMlrPdA1HJ0m3mqcgQJl8AnqQMsDEHYX5bVROkG
HpLW1aJYQphQhRzfeL06Vb28BRkJRIcQx3/tuQoVmlvKK6A5fg4g0VLL45jdllnFurEFZeqaAvuc
W4Uc+GPQxIa9bI5ebz1Mp4lipd/meQC+b1Z1c0TyRvpywqFlNK64/DdFfwENnBw5g01q3XLBu3/u
G959Dlq6ocAIVdwJ4oGHhDkCs0HJL+s1uvZptEFCk7Rk4Y/YWE3OOfJS4TruOFXh6cn8ImYCerNC
k5QzS8EHjplVSoQuUf5fo7lZxvcHfc6YwR9WIxZh3BA0Vmsk3CCLwGyQlF0cWL+wgFyePB3XU90d
MZrLFBxb/EA/LR5aKVPy3wZOxFahaAqVpirbFMs3JPPQXZ2mZXe8yRAJBWETWxpXyH2u4wMT9HtF
whkn2pko7z2g0iMShLh40Qz98Mu0gV3Gogpwu8T2xrq401ESs8fNkoUZzdRWM9sNZiONbQ4iFRs1
SI6ZgxVrFvKYbfIgF3B1JjgdMXi1U+5w9Bqm6stcaLJd+drwIVRRLokBMVIFkGRxdRE34utR+gw8
Rxi+87LXv4R/LHOyh6IQ2dv6Lyhf0V2VyPI7bETUJGlV7CDR/tziA9crrY5KW5GCr1C3o2GA3QD7
1gGostP0Ij4M0tiy5qvnToWxDJyQ/4/JCwmSrDv2WIiXHVEtw6A860gBv0+jmoCouXqavkAcsWDd
C1DMVaILGBpdfIWLUujOyzqhTVczHBJmeCUAaa9P271FWFdn8TqMPZw7rgYyAwtbiTlXY2lOrZ0q
uR1oq1i7ClIQtWRZDIBPfKrw65oajIU3qdgffrQZ1Of/7hzfe1oyMxgeu8xR6ICBDsGGIHHyYqAN
gUS9LpVWtUX8YjCdczc6cj1624YNkz2F8zuAdj5QtZgSWYspv9U1/KU+ARm3VKdzlmSyuV1N7/0B
9DBJbuXO4nFBNkwXxyc3DZzL/gpVkcJZD3IScrj8WjjQ2FTIX8u3lo5sF9UvwwU1qS2nay59DUGr
y4rDn5O4ZZSJXR2GFzU6GqWUjCkHBzhCUC8VOuCFnMU8DHfJ94DoMSIBDuZYF0QPeiPhJ0urDxJ8
vIxP62kQSqDUJ05o7jAYNI6fZLeDDcVPY6/qp/+LQ1FDwTbXIwXk+U9xAVt9a7ODOx0mPCfMiGG/
3lJivrwaAC7pKGDDgMseASvMRtEUgs3FBBih/pL1z1rQI/5nsrThqURetsrgjVWZ/hYbvNvy9uXR
6+gpxJbtslUyK6uMlv519ei99TJ3sOxxNSCJc7/6LK+LaI95CYD1Q6mQROH3zBgASx3df9dTPzwl
gb5P81iw+TjH7/HkTEO1bbYIM/C77S06AzVT4lra7/bm1gm79bHH9+udMJ1Yw52it5XpuZeXMyPT
MnYY37rhZoUfeCpjnw7aJ3D1CiH8qK/RNm+nhO+XpuRjCsZ/K7dj11L7YeFxpbCI2Y198/GNp53R
QTwRr4Zd6Re6e/k7hRFsZu30QFfmg2w/Pbbl0ipGS7g5wRlWHP2rwCOuMj/G5iF3T4h0uDwg27yv
ubI4Hkow+0wphoBF8gMbd9dhdYkWkG9VelOnLtZm+ZxmWgjI2jOVp9N80hWnEGncuzOtbZJcoQHG
CoLxtCJ1TnurywxmNv976mSWVbCXqk6+DeoVdvaxsMyR2/7ZyXIAkbKM+VCBeBg6z8c/8wmiH9/C
MvNrdWBOVC/dRZi4K92EEqGTuomPchPHe15BvDVIwlkrDgQrVL9iPCOoJZxFi2MAMx6KdcG/Gobg
OBB0Vs0RsLMDWb9yRt4mRPoHvn9/DzK6ZxuMF5N0+bVLbuir4BPL9tsiOi/sLzMPKVq0UYa2Hwtj
7RvQLZfXDiLchTtuv9ZAALVyZNhTXQxrxcL/qkORn7T5Sm69+DjnMInPphoXxhXBC3VgTaJ/DpIm
gEOdOib/n7fOi40b3AbcjwSO4INVyIE1JhoDn1zgeVrBUZR3Fu05LA1Ee/QoFQDOWP0N7Gaw68xQ
UMrdie0XN6VJCuUyYf725qhTlUWSS4zO77ZslBvktav8eBCcRpFxE+YjyqzdVocyYIh9M5CRYfK0
0NT6qFUQ0AbJrfvvOw3XlDGSf3Hw6H08C2ZhV4vGCKUnu/cvmsRXBMxpFDsDT1LbJgXPPDOTNFeS
Iik4G87Kr5lieC2JIvDxaQcClpHN0rjyeZKizBr6bUj7dWQWRjSNWfYeUg/Au6tKqYGkti43rD5M
IRKlcwbvEmNXg2zMP97OA5c7KoU/qZsKzGFDiQiq1vu64nYB0OialODAIfZWlyHNw1kVYgvRF5IC
JVnISg04vKb1iCdmTtvUEMdFdlDDVZSSeoxgZ6LkdIsZP5DLEoumNPSg6gLcg+YWOmkpdSiG95Fw
NeehhjC/14RT01QIWEz7WQyVl3NiWvMJ4KQDg7DPgc495mV0Z4tXzP01UI00Ejt6woOkfXAhKasa
+6NHm1e0eQU1JveMt6IQXZbZ7UWZDb+R9vnM2eCAmqvVrDUu+RcvDmb/n0i4hMusBD0SMqkMF6aP
IK8z0RsicDHe+P5sujfxGRwjDPfVWPIeYOq0ODvJIm2LtTrN2APEfso/9DF5UZ+iZJXhvEHpviO1
CrLHfCsssIGQNtu32hUE7G642dyYsT+GJ3lHPbdeIjelp+z6AnVG2oXuSs5LnCjvc33aKN5N+qUN
Vq+4iKpLubed4ZJvqJTlXsuViSwYgWVvjHqvM61KhmCZc02A1qRs+NxORZWPCtXZ2HX9h0ABcaYb
0axoWNVfb8XHn6kdecpHSW14PzUpox3+HTuo9cAOgrp5u3Qj/aM7y6gRODXiSD/Ua3rJmglaiXSF
j4yVHd6VePrlc0rsfNMVXuMrKkEm7lasW3W04pQ2Ou1gs3koAhB3eIBUN0Okiv2fw6oVtJnMA4nn
3oldm6YtDS5K5NQwyMxvmS12nmr6GglUW8HYEUmFZo9IImyVzEjAFt08qZYIMEXiF/TGZB+ALsg1
0QU60e0o+LdJeknuEURd53VL5G2iT1duYlTpqDMuiB5xaNwdpYwkscL0Y40KQ2RGWtHVux8pn/OA
aD8YZWRN/81unan83LAJJHa5kmO7MUJ5LdjEd4wEG2zfYztOuBk2LkgHGD8kgAlUCRYh+0NjXtZC
yqa0BtItAT1TQ0KkhvNwkBBYDterln69Un4JlPNg/Zo+roXOwLfgkS9CSpLQrb1yE3yUH+jivr9q
T0088mt9N9wKIyT7gCaDjLtVQuJAK61D9QUDN734i/ksnb63iGzkYbHlw4Pr9rhylyThg8WmwwRS
8kyL9iogL2P3AO+NWs+aQuKNyiFPkDure+Uoxdmb7CnB5swnOQ8j8G6DrzdWP2mKNCEYeI/9csct
6PLxatatFcb0fFcVCX1Yjit61FykgEpGL8vYU16MY+9MbTu8S4NjRzutoTGUuYCkQNYk2+XBl1AS
B9u+JCv7TJCc0r4CpkMWyJczvg08ArusGemJozB1BtyataqF9aBfDMIfIzUs3jvW9G+Ruy5K7VgG
Cn0A9LrKb22Jg1JvMD0F18nYFByTJyD9Y4cnycDLKoo6VXpi5eRhkYwLZXBVFrmsDkQsE2mtEhWi
bCTpCY2dAVFyyvqLVrMTlfWK2oruJWXGGhIJQ9ehvEcdySnWqNsUgIXkVZO/DReeFENJrsh6krOn
KOt05E2N/385ZzlYpGuPhlYHL/sIwnxqoJRX1k5bcJtq9UvVKPBU1IEuSDXNDYArJ9mPPe4nu0EB
aeyJKV/QmwuRnyMICztSX86/Qh2sfY1NBpf5ZcpnTJ4feQ61nE2dmbP4cSYBWjHalc+/G1BBSHwx
Wx6Ibrh/MK2Up5ZvvFLdFALZrnGLWlT5LZeKgkYS1Upi5Q6uy/Auxb0TFF/whrR6w3MfzTpMrKY0
hJr49BCPzt4pcYDnlCieGQdYIHVEWrpQEUSAfQ3ZQCZpX5hj0v3FYtj4VlwtWEr/wnnsHblNMO/Q
9eley7Rth8Dur7+bOVajAHppdvFD4zciyEg7xI8HjbiP/eJE54VNecyseykh3/k0T3pDRfm3VKE1
crYeziTD9s2bqlybMgtNVhjg924Z102I9/ZAzsuY8DeI7Cbt+KZ91xBUSivCAgxil412fbhr2Ifa
EMQonW7ivixuQLvhYh/cK33Rm6RVTM5+GUGNZJnvJPPvNhQXu2nhlmesuuMAcfIfzDTvZvAKSjox
SBIGVHzEdfgb+7bMGGucVfHUlW4IdD5vATV2BSzx/mLKYrqdsi4XZkz7SykTfatvE3KW45IgKOIr
y3+e7ZBbrmAZgMgfveD/v8RFV2EUKvkwi83bIt+gq8GViRNOZhgqhkHGjd5fc1x5NDRrifIv9D2U
jirdGY5ZpPyn7DlQXc+v/bXOM67jzVbuSC4D71e/YrQ4oSPMu1AxhDi+nbfb1aJxFRDyb+X4dowk
COiv2iMemKL2+bI3IJW+DRuViDVe0oenXL8y1OJtxkv4FxIHKWYKoJmRQwByWfO+WWH22xL5CAin
2Ob7R/TFkCivylRYi5tmwn7AzsOZaemRd3IW05ud6CVNM9sZfmZ1Lc4om/btxYIWTI8AQdoEYjaP
0nz1OCG++b2iI/PDT6zLj+L/z/UVFovNNGFUaSoJtHGGpu+hKCXeu0gy7KZE3x9C7tUbhYcfNmVq
hyQVkkPTziOU/d7VtdKlQld/HksWWP0yUqFIxDLlZVNtLBoKaL6gkZhkjBpUlLkgClUHUdjIdPy8
oLub4O0UwOdBkXwKnUNPrjWNIjkpFsAzeu5+Pmk3uq/Ukz5C1yLExlLw9Wroe5vyCODOrRXItGyB
Bhh1zB60T81kxdNh04Nzwlxn82889nKEWqUgfvcjsDPQCY2ye/sfbWZke3u/Eb55BdUArzgGFipq
c6gBxdtR7++W2vKeHqGjEbgUDT5g9rzR1ydC7QWEpuYLcW6ls+9TC5haC9uouEMu55GXVuKIdFdK
ZR5mOhh8p+C5JTEaZNa0X25ketfK+ADh/2WIllSlnqcHO89YcsCYXX663RMXmTfxeSVOSLEYeWxf
IVYp/jGf5T4tGP11Vew15ghU9bekBuQqAD81JDTP1Cpo5Q2K9vYwipqRMsFUjhLlcR85id4lB23n
YbAJ4MsVg+anfpKmsyXQBfkbFjk2xD0orFpnreBD1Vsa/v+frnpyTqMgztulffhRO0oFsJPH/8KL
0qdhjj5D1BirwnuOZ0f2lWtEkSIY/SiFi1BuhgBKgUPuifcdInEXJ0kHZzEgKEAQJ6NRxBEZcuvT
r8zUuZAqpA5BumlP+pVdmIQFL0aCRcS/uQ2QpevV5OY5KbZWrmkWTGabpNA5KEWOT6A8pAma3B6U
1MmQQzC3Ai1ef0HAXHUbrvdqTXQFf9wkRNcS0l1dtzgE3KsAotMkU3IwtGyC9Bk406+IFQAR8N27
mvdc2GtkTP8VvjLbRhKKd1+YoUt7dhdL/8QLV4GdboXEg8u5yrFkV5HicAiqQjrsydg34+Y+D22o
7cJGPqEXaIR5B4BKFsrjoR7cqJpy+Gc9MVYHEo678FPXQIhDxkj5yHMPYNCYJT5Kl71AN67k/rRj
30R5fRUkQX1t4T1jRfRxLOWyG6av850YyhafbD++UUmYnprfFEfQv3Bx5ldEel++TMikmwVxGeNp
4/IJj4niTg5n34tm0RRZY94ldOnTDbMD6rglUQqNpiYs0WvkOUOSS8EkQzg8EItK0IgdvSK0QX+8
Po1LPOJlAVrUSlkzXYCwVJFzMm3n/qJkqI9Jnk37PzJGtFKdDc2X3VuhGmlvqUPn/RAVXBfFJGa/
bO7oSwmPbvJBT53HkwRiwgMiyW5m+gfhLRAfge+W9akG35Kg0y5u8O0esTc+COCn1M68b9O6jH9l
V6EYLAYMuBcEfkZ4cPweBeOtOZnRSy/D90jsJ6GBF3i0Lj8ps04lrLi4QkTFkrQZQBgGu0qP8lfJ
xR6oHzIVd1UGcNtn3CDcLUmUIg1Qp7KPg98yi+9dmNG5auyr4GUXBSMpHbEcNoSetvbTzMrU9ZJ/
houi+b8g9YmrK+yCuTxaiebBrxgn4TWhyEqj6yKsUmp2DE1wAnYKdyfLmNndsANmZ2CgOqU7Khyu
Mye5Z6R49/qjNIQ+ROgdoJjD5a9jwRCOBuKqaEPyGkM0WQWfznEhCfjzx9CEiz9qhhjTnjYeKQjp
OczaKNI88kqcVwy9mT/H1P99b7ZvaMUiEAT5RWiJWvm17m5D6G8de+9gNiwddUuF0fz8/0Xf1wD4
C3HW5EJ7IXoo1yg+8/e4iyarG0boHzSlNd8sn4xaaWHT+ovwceg+D1nyYm6tMbsWt3C+jxiizzcs
ab3kDk2F73fcly3DweWYQ2dVKyq5Ho8X9jIBXSCIPV11b3PETmWAl2y8ZyMD+ppSrwu471Neb6Ta
JVzx0FA7MZi1kvsDckYfHyoF7ER0TBV9cUO9HCPvcmQT+B7R2BtGNITl+joA5UE6P6yczqKfSWgS
tM9OUui0B50c/jUwW/BYdn6K6RMvDtaDlrG/Tq3gO2rfaU7pJUPphiaPx8z5owgwhoruA8ci5oUn
su9jcydXSfwaHAPpNos0U9JBc4TtpoumCW2ivuoa0Z+rm/LZGRJ9nPmu9CEl/GC5PPR/U3vuWevY
ylCteqXNVgncszLoMweaEd+Va/l5vMBCHSzzZJe7DQqQRutd01myVsGVQlHufOM3dem1m+3/+yuh
dElmoBo05v7PZN3Z7r3r0xXjK7avK6TWSYw+Bg6z1NWM3FvzNVyK6mhypXVyUdi+sA/9fwfO03FE
yi1P8K2HHdWjcxum1BiRmBuETLNK3nfvMJ00raEqzHZvrHJrzyXjwrotjmmF9tcIOvt5xnglfA1G
reT4M0RHCUu7Z3hX4xofpDrHnu04iMRqRcp+oPGq14Th88MvS4Rg9FJHGK5fRiwNNPTjodqzWjhD
pU9m6+V9/xvJ8e6NvvS+opQ71R5NwNV4VtXlyvEsJ4cOJce+9CYH9IQjzooFUyEgCxYrkMeQRvzY
uYPk/L7pIJAz+ippotu9se9TWrbFFFcyHEnZrOm9zAFls6NcM1+v6XcO3d7A0YrZUZ9Os9+ayt4g
bao9gglZzyBqlBBabWUqF8UfFSZPosDNyJWGSwKRdH2tfb8qloIQF6N8Q/Dzo1odebFlJx7OE97U
lyKaHa15E89191OSuwYAi4gzKHkPJ0g7aLeMvgJZ0zS9xJWVFkvvv8O5D2ZVuzQP7eR/faWYa9Nn
Jb8a37nRKDievWTBsVala8YhhhGh+7FT0lepzauq0lxEPuJpPjWokpcmXIxWLCiIaeeklCCkyHLI
kr5HRaRcBHj/hPfySeif5lMCMl/fjoh3NrWZ/6gQ7PSGWTqUmWp3V5JP6yqirXpbY06LV4ksmWZ+
omeqL0DIk65MG6s8VEez0/Ez2cOzgQc0qgC5n6xa8C2AHRNha15CE44mDbkcu/SgRl5SPpUFcg5o
aZ9u/1pp7k6pfx2xCtALX40EFvZBWTIFVQM/3wNBgqsr2V3XfexaQdqILFjYex9ks5diFz0ANiRC
Ma6qvTiQjgu4niVZA5f8RQ45eYLvuviV8iXz0BZHFAt4J6l1++c7PDYKmObAjiUrqE3PHeR0oeej
SdJKWuJlV0MDimC84WxIV+J8TWTzpaGl15dObXb0QLuDIdxVbdyWZT2PkbjksQerXyxsMkv2t/2I
l4iKJ35h1jzuvD2NrohqvC0csYXmbJLgCCyus3u9SZk77LD18HFfOw1CWw13CWStAUH4Bm5PNCVk
sXM4+nz875mWnf1luX8ruVupnh9PQe5r5xLz6lrmI6ZhUHTInA51oY4KJAUHQW77oSHmPw8+rOjZ
Q0xde3tYfc7RsbY93Q1ZcBT+f6lHQubHJYSu1Z4PBbfa6ZBNVJmwY4LaSUl+YracRRynzPVNBZcj
P3+6maUTOdN48Z+HTnvqATE4zfc53Q8Y7Uys0L8jyiNNPmpG6htgMwQMXRbfhY0VG27ji/K1lZdS
G4OtbH8ZnnB1NoK+xqL0VUFDfN7gFgE9nBBRtoq4bscEXifNzVq+Iu+5GqlwAWF6f4Ad0/ovA11F
Ij4dgkKvJrza64w+gim42qmopgTSM+XXjwG8eYtVH10X9XK3KtNToGynN3n6q6JqDyLGLFw9Hc9A
KtC60vf1shAtTLIjd0FCurON1strR4Dkt3O8IR7gjd+5GJTnwYvsT/vm9yLMsioin8WR91CenvWa
c+JGQTL2O+yjYVg+Wah/qCnF8bb9tdYoh8XJM2l7quy8LmmKAdV7mgcMFnB7u8KubKs7TI2nTg0J
b7i+LCTZPZzHOf/bIMYRqwVeOWf3Uh/beRIWPvnmmH+XBYGGGAeZRtCpf7wemXo43UphXFdu3JtM
ANs0iANswv96TDZGjMOBny6a/w3VPh9VM361OBT2BuAMrIzgwzdB7CzC6BW3lvAa8AxD2St8d/nC
LXBnWo3M898mgLdk5HPQv6VSio6bNI3hqn8bZqKXpm80WEL+CGuTkXNoZCPk2NzmwTcAc2jotZNU
bJfF0Tu4DB22JPeF9iXF4aaO0mv/OueZtAtRhx+R8AXCOz9w9mb6UgqUP4INpkweqIDvkutIMphL
8mEEcZ5kXqQgwSad1A1cWfDqrfTMlKYAJ0HLUic0BC1KmLOjTx5k6pFh9lZxEmWN6W3wIwDUmbg+
AlRiZL/63yI4faFoaEAu1ZY2NJO5nzBA2nsaXWoJEAC+tcg6ui4NzEe/TFt+yedOxV5PR9wettJZ
RU93UMHvdYg0wgqT6soviHp9Kb+ywNaUZbGN2tBlzeoWs9zyiektoJfk0GC+jRseE8ShIOuSF8fF
tlhSsvGgYKaq7o5cD+uP3c4uuODFAFbUw8YXXYfcl3TSI89SWoKIJDl5KZqbd8G+wXbcb5mZUS95
3ZJIQsLrj2fX/0ergaH/JdtDWE86KZksnQQmylkXNA7jvjnwEFVtOGxU/ZJGhd1T8TnH1UcgDaiS
sEGlmYiHo38L/G70/eSTH6K1urfmkWyy9Rv81vSObB8TCbwbXDPq42njDQkYcAm+6sIhbMTgEyF/
YKjX0unBH4wjLKIOaHGhaPA5y100VJZsWbdfdeKV2UfG9e/yccYE9GDdPTLBydJy7EG5haBvA619
gGwesx3XxDEyrxBw/PuW/XIuoSn7lYzK45fNaO44wrlprdvPc3T/PlQ0mAzHZhhAFXDjoyJMe7Z2
06ZZ6ZaMt65lBjlsk+rFvDBtL1KfHepYBwuKNcJ5ifknV1AFmAbq4S50aHen13Pi8fBDowK+Xkv+
VXcKso4Cq/CZOaUihwRQAGTF3pri841SkhtHbDN9Hgx05ciuZmBoAe48Qou0DadgVZSP1hWKYoS4
RUrO2VrgqFyVYglO0Z3NNAb8f3nFPcRbpgKH86Ua2z9Xor5RtL1vhlSyF5UbZ4oSCzXhtCFXkaCG
+vKL2bYxLTm7FDf8g+/KGOCF7bmZ0DvvG3qG5NWuZoH9XWht0+HlfttxOtzgoc5gFEOlVSrpEYvc
5Jjg1jsYZ+BCfFWpzxsF8OY1FNDKJE81Qo+0fKeCj3QJDdCsFm0uQLAMa7CgVxdhmziXQdLcqwjd
/96FzucIXfNToOkn+ONGzVNyWlYUwjVrQP/tkMnhaTIrRUG8rB5uIshmBESfeCLP6knc9TXOHFrk
k/AuKEH8tEX0AJq8fgvyhQSLGkgN6Yx1WpfMap3GEgkuD1idAOGN4Kx6Deww/Xn/qr+UPKL8l4Xy
U1reiQTbwY6iQpW875sLiG+Ps61bzyFn1eyol6Mn9q5vWW4UFlQ29k8t/38jH2/upwxj+HXM9baO
1w4WFdIK+CTPvoF63fovLHa38ihC95GH7nPEsTMwWFevD8lDAAN8YsmrWYhdv3OwdQBL+/Vnh0sf
+HGClqJtoEJZMKvZ3dxbUpNM4wzP0uMs3DQA0/jl4bk/ehjuJEFSYclS4EISRM6oQszPec/ZsJ8P
gOTh3zUdS/LBgelJ2mRs2hA1GY72O9OdhCqPeLpGsTOgtxNSedAHLBbr/GhV4zz92kMSXOwUjol/
uE1SdKkDPXCjBd5tMbvbwI6u/f/05xQVj6zWBMdplxCnBSNh067xAEduHIxNnWoiMViXeKyGHnDE
o1GSZoccFJ07/pyMgwT8A30AEHubD5s+3IE0Wn0iCWuYzy/q6uncIB+x8l7yvoRu+BQTUCt8PaT5
p+itFTbb9nTcMODgR0qM0zEmjzGuFFDC6xqLuCutGT61bejBFqEfpl4SSwx/AIne381g4zp0cfQ+
gPvqt/Xe9ooSxmBpqg4cNgcxKLgo35FoMEyqoLw37o8+fPxV1MhNmHu8zf474figNo8tlpOH7c4A
RhmHYgmZV3XibnOkUQt3ADztUhHLrZkjQKCyEQej72KCViPSvXkoAfK+Yxc4cnriL9ZWdSxBMaP0
Z73R8d6JdZGbE4RYNWXLGsNBOXCfbSdjsLJXYW6ziuUsSYdI/nUQIfX2+m/2JI0pPFa8c5CrBqpc
wAMOBuTVVLBdMTbdmlz2rYnohrzMzlB+qw4nMyTAsj4SJ5d0/APb23q2ROJpKn9VNeJzfut+EsQO
aRnBmYaerF/jzXUPgCyCIc+XibwvjalDjuzO2WWHa0qduDLMRuGkM+FUlixoB3S5ZQO80vIz3ScR
+EN/yTcyOQKJk6r1Jtsea66nZwqWYxUozDk075gmwDxo7HpAlEeVTfNAVu78QGt3sU0sRvDIt6gG
XuaH1ckw50wPK3XOp2REwY2hU/yJQ3jaR+ty7pdUUBRUqhGnwljRoW85ywnahyNLUX9/22JNCKDb
CEsNuyYbE5S1MPz9oe/1zD9r3aHfbBHv+j8G66HkWNC93VO2fsVoim7db1WzOpadfpM2ysyje/OM
/nyTDgvaBqhT5OuXSOqX2/MFhxXvdGnM+W4rjmhPEN3xXfTOnv2eS75i2RXHhtvTU1R0J0P4p2cb
EAY/ynKVGXiCQKfzurW5mbqWeZzzc+8k85Yj1hGgqY0eVq1URe2o7xfQpUgk4krsa7NkRfddJp8v
Y7J0ju5B1dQViz3r/lkGAe4wmTPfOWe1Vow31NHAtNaX2JdeFY/Q9d55ubvcGPAilrz7YBc9W58H
IHQSPATOWhM7Fp7TNW5+0m+V1BmZSQkXTImDEOol2O+f5rXJ3R2f0tadlDqCTU1G/oQSo+SPN6uP
F6aWHNMvhmD48SGSJr+qAxxqqlwtMk5SZupAkXO6XTw9PX2cQirwpmjwfXRlkjhFuirekeucMuPL
OLqHEkoQrxDHBf3zhaASFY1Ji31F6oUaeG2IKzJQveriIh4TIFY8mFYai+8Z/qGw5mC0lYumBJUs
F55SrbHP1bSmY8LkSE0vDmAG/Sz/rpMLk5KNxmMN70pcoQJZfEh8adMeDLjbv+0rFUATzY0B6Tl8
9DDW3hm27rKZJfrUdlCR00Xp7HJyWHvvkzV/57e7SFXV3p2lohDHqVmjg5CNvEr+/Ns0IZ9bhdbB
z2JE65aidHrELwP/Jeynkkbb8vUkYYMTTpD2P+0NUCHfFnYHRs1jh26Oyw5sorWsXk8TdXXUSLfp
w6jDIGIubqJGRrbiWU1Fz4a5ic39J0eqygM0HFN8GxYbxWdQZdIbtoTfVanrB5o9YIRyRrDzGmyi
//iUeQO9DShqZfgsO4sCUQCTc+Pn9CDtJlce4T6DynKFiy+vy/skkoYMjuFNeCPD5El/45KAuRiu
BC9kcO2rHvxD4tf5nQPpd1LLfiSdoj4d+6EoFawYnzUZ+mTqE2Z+G1P4oXVsyRzOAZty+40f9ken
pvjIw2FUIfXfuNGowRUSmNVwqb+J3a2K/WnhbSD5yG3WvRh3Z7GPCZx5BbA1Cw3OAl5VIxLCmYU1
hRgTmCiM8v6Vwp8w9XW8j53T/wUp4wKYbgREcVJEc4Xg40HUUNsm1FAAh+LLibNSD25u1sQCQ3GK
UIRgK7VLaFAQncUN3i17+3ZB2ilMp27RY7w29pY2gCcJma0dgFU/1bVHtG8cV9YTrjOr+mG8p1R3
mTXL0hk6oabBX1BOKgYf2aC5aOnK7m6rmFC21fDOBpjXy1NCMvinxY3iTpT1sHGnBU7jwRK9VJy3
B6708HO6gfgmhQIOE915rqcpsGdMfo3v6PsiN1pESCbr1F819eMKfYfq7qDc+exxYp980S3Ao8SQ
ruTXpYhIFwgmCi98HS1oZZHN9ZEAfyYIcWUin827Cgn7CyUXmbeEbJmDDA6SMW+yCjU64jaBV1SJ
NHyVdfzt2pbTVrZMLxOEQ0JzQSPzWnux9VF3XsRPmqbMhYafN+5t080P7Glu8QZN3pJN5JI0nku9
6FgD7fMb3WOKb9IEJxFAcBnuXbs6IZ3j2I9vsZENyF1oHezEQ8Hi9MXolWDcnbPJ3iLJjc13zJ93
Hq8iVRgxVBpjtFUeziDzcRm6V45GXJn5ora4wsI+m5Z8KMhU3e7Xo+IknIWVKQN+y4rDKkUGHY6t
igErrVEQHAYaAa7VAdP4yYRSUpnF2YmBg9639OmhhnZdT/V8fn9o8wyRtGjS4MC4cxPb8O0lG7eF
ZKVMiIIglWvFes2gEViRGmEaXZbd3koTqd0DMz0t6YImF4O53uJI1nHSu4TUQlzrl11ju1sJQnYE
HTKfxvREA9WaKJfsqq6ojAqwJJOSyMcIRDr2RL0HsTqJTpDWub2QtfZ/7JADXne4YZOK8yAymR9l
zSNwl1IT79fgo1ux4TNtBZxYuc9kiGDkc3UbOmqpQqm5FZCBY4gPvPEOJhUTvkp18y1/7DWZ3BQn
6QjHS3+ZGD1EVVrjeaZYQN3ru+mmzCKHtRJu6yt6KKCEOfm2za4PxGaXggzZcFg9kkVqPoF+g5Um
r0o5K0lZFrLKmQG3WJFKJgtb2McUT2crc4WhhRO7foLBZEkTfBFRtN92HPb+q/hFBVoSTdgzPC2S
S/ce3EGmp/ZNNoNDE9Sidk8/ITdFUg1xIP0yX3CBapgijC/39gJ6/0sb0O5nt3U2zjFeF7AhTZT3
cTWXPvsb3DdPqZdbn+C+LANx68ogZXnnisINRJHTTuzq64sgHmaLEW5n+mj5RD5uW9M1uaaW5jL8
LT0QWdKbi8i8w7/y9FQdxlKFLYoiEHJ6X/TaaGff3GoNZiWH3hOMlUhKh4Gu4JNdlXcAiCITceEp
ND2I+L2VGn2R3bPI4vPqaeMy6NmHtPhunh4Ibx8pXYfz48mWR+KKNzmLzYVPQ7D9uaF+G7SUJBbL
G1CsBkSlOBuL+XJa9Skq6NdRzjwepxtamdkWEdg5Fdf61PZSKwbvSimnE8J9Lf7CIeub2WDtY+Sd
TZaZgC/+Aq9KP8gdZ3DM4FHQSIOOMG9w5JBcbwEXLXUx4KrQ6VkpFOYPFT48a/XGuywe8Zc8TaDb
m5gtT4l7FBPsUvd1TyVpr3svCWEkhwCbK+Zq73UF4xJMLnlLzkHh94AsKYDiLS106kpMOHKiEG08
ds1S7HsAXpeGXcHHPAtmRO3T9fOi1M3xff2hDuyxY6Vr+/t3zmLzyL4XG6z8jMTPjSwNM8Y9hGVg
7R+hciOOSZmWJ81hDXmnWaA0CZO/3Sco4cq6ovIRjExqz31cA2Sdrqo8X/Vo84T0skwKkAQ64l0G
kv6vDgV1LXPohmml4e/nzLZkVwvxOQtVQDfZZXJKsBYaCqrLBUoCVMpmRR7lRvwCc5Hqx1YD4BLj
UNdn12fgXRLxXfwxQYfKTvZYcn8tn8BNT9I7hIPLeTenML0bQDxJwFbJ2xJW284Bklufuk7u/yt9
w+Hio7tnBUe2tuWvSfe+tW5JO5J9wTPrcjtuG4UqJcjKbb8iBbqtSbJ82qPyuVHonaeaP+HVCjuL
Iey8DUY8Ugwl0UkxBZAt2y6eif5u6wss2JI4+YdvKgQzYxQ7U69JWGJPrAnzXUPKSO3S4ei3QnrM
yly/Al14tBccwCBMPswu0sWCI52iVaGHF8GAmwZvYvdYqxh2aZY+V3ERrnnI9TpfGCkBGspNjfy8
VELtOueM155ryHoDtZrUnGVaicH4DHuXUSp+GwcUTcTHU1+XoozfL9XktTSrcrk9kf+hYIri6wz1
2qbxIPvF63aidY7av6IzoFmn1XMN9rqkVc0rwYzmVwu1/4Sf5AXZCTELN2xbjjpyolX8+8qZxSu3
Lmz0u59NZO07ofvhmp5GwJ4WTu3pKAqc1T1I4rBOXknHcKfV061Dmfk7AuVfC2gjkNWP9ms+PVHI
eWQPAN2CoFieIxa1fguDyA+kqfINcl4vBHTY8XL5c2OVeYoUdzMWxY6pszWLGwG+FHEGyEjdRNLQ
8AuQaCJewVruPuhVkv3KAhi3mu1oYJAtxD8rS1YOBe2m4iUBM9r2sDmlVdmGItK9+pLvIMYaxwbs
3jenRj169XaVssTAh/JoQ/Mg2lEIGCws/2lbSh6x+tV8gTYTQklDe1FXy+HeHWfQizZLfHeHFi/D
n4YXz7j6bHGNcYVpQSH0eViAiC06+WjFc/QCDZnAPtUDMUASvnh/XC80F1rEHa23bo0r4bCcrwgB
xpxYqV3opmhLj6eOOxviqQreUMd1EgqQe8IqHfMs2w9IRZk1RZhFdLrjzM7J6VIKviR30LH0CIv4
vITXqOHR2WZO+kB+1VXeRIOVb1wxKEEMyAozBsci9J9I5ktEKTkayzgahRkvQKSrG3WKAilLxEJD
nF86JM/+L7joi8qZsfubghasEq4iHSk57O16rhweWdba7bcxOSNLnKgT4f78ont+T2tnX0ywuQq8
Qv018o3575DTqYpAtxCgY1KicOwidyKKJ9TSEwqdzEZPWAPqsyPixe6kpnm+V7KT3UO+eXtg/szu
h+CVcutxP0gz4tTF5hMEHNF0Yfm9P77K6xQm/3/swSSpqr9Uy3dvm6dHv0+g4evrEFIP+TJCB6h6
0eelg+zKUauOHtKgcSX8YWHXo1kt8UHo6ZrWJQXNi9PHjudSlBsa8RYX/pp5plyeGAG1ZAkD13ne
1ej4pcgVMFe4ESXOk3DG4LfhgiuMKHSGO3g4H91AHJS9G7feBexNW8tZD6L7P/quRVjxgM7ZICY1
YkeulsxrfRGpwf0bZXX/1YXdIHCytF3ix6QLkpCSUOYfJ1BTtgvtIfw1KEvMRwutMrXPqP5WZhyQ
5+m5h0KUmD2x6xGAZ3NyNl9Uzfu4neYwqo61aqwFEh/SeXhOXT6vaEVctluSX8fDXv1Qoq/VYfDz
3r/g9UkY3fGFHIn02827MCAtWswU+cROGb3XJBjQhAGs7saXVWvNso1fykOIEavRVl+fS0Rjzst8
+g0Gvz+489FsUsBevowQ1MPLYjvfm3DWcJ6Vk9BEn7DjNjXGSO+BenMfsmDfVhjjcgKoUB/g+jSW
mCrh6HCwi2ZBwfhvKYaOYOhTNYxJrss7Bf1T5xQvLV3C7gp2kWftwZ73VR3F+VZzNE0AU7skPzH5
mXQz0lZAJwx6GITPzfhJVyZbEKcQwTmchrpheYJ2Azcs9FjjevCpP3sIaai/QrLrb9HqfTLDLGs2
Tzedx4tnzlmKefNaPz6J98Ss+3/leX+l+cLgxn0hL8PPhshU1TPEmDEbNl6Zil8oNlOKDB4eLYKP
vXD1hICm1n6J9PnRDcAkSJK1X5U+SV0FAPRM0AixQ5qO/B5fSZLb1knSOXb6mhHUjpIUGR9s6OWE
jcBkYhD3mrR65cc9+jJS05Oj6gvDW0G3Usj0+oqh8UqHa6ygLhbEPz28soHXXwMOaPQqSlITil5q
ehSsqAee3jWzT2jrvO+7uOTtbqxyyfCHpqbNFyIi2AFCmpbn+irJ9m2SrgdLc7jKB0suVXmBNgTi
TYA3aoFANOZ+TnLY4weuGtkFRc1YDKa9vZdZdT18U05gov4kfNV7TIH0MRvhLZYaBHD6qvqkGx0p
e9VkBa5pg4030PiheARV8f/0J6hHHQamugwnX6C1kZHq8JI47deiYJRt0JugkkNEWC8AxH+MDNhG
JU+m3XjhyrFFes+6JYDKglmh0WfoBXBfJlyna2W7uBBChfda/5CcPSiMXZFhfk3nehsAKKR4zlAF
4xJmfuOouaL2LjUBWDR2ZpVFQ1b3eh1pLUoTGKyd0UGO8+RnEHZnUOCZw5Z6+jRZZGmRL933WcVg
EJNqYfyr2K5ly6qTgx5osy2b6HLwSYgbI314hwx77LHh98dg0pTFH05JTk2lEZ61OWaZWGL/tNFX
IBqCEXs2BAnVbJfl27h1wiXZ36ryYtwX8CHQWt3dUTfks0hTrOKRbkhYQrF7C1xHlAvO9ode490B
nZ10nphHwIltToV51/yGUEPmwzCAXsW6wU+Th3xce7OB3cFoFtqu7uDJN75y0NIYaNSl3ZVu1TsQ
/vCpUpyFnctrJfdlscmvBL8m5QYKRnpsCw0voVK3WFYe1qfzy6biHgNeecmSpyRannjgyxidUkr3
YuhmLfTlD7c33pa/si4Rbnmq3R6NvRailaIaLa975NWqrk/PX1v+ixbnhVwFpzooFEl9A5h8kzkG
dS/XLYO+JWXZ8/busxjPUu62xF1OlYwcEkDbeiYjBFkciGijgGDa9VPNcbjuK0tvomLhaXOAcd9a
WXOJE8X1J6uCxu7g3B+OZnuCfDKEXi9MGzPOV1XE6A/WG1pJ9PS3nuZLJQI/Cw0ko1M6jC038jA8
6+Rfx2nMvmr6Drh/+TAOSoW/zo6OYRDybepKxtwDCPjSldUBcSLjbDB8xuUeakmUt51WDkqnEeOO
yRbgbNJybNKtDou42LUP46aUIq2MvOaMk1nUcZbJ8siTdO+5OA7fZDGKCQD4hAC3gxANiZME/i05
0fCHZYuGnCQC2rk+sp4fphkEOITnWdJsSNpnDPVhg0wfCfUZ2ZiuVmGbrQ50z6pIzB0YA3CU3Re8
Px1fy56S1DIU95nfiIdl0BUN5Lff8WtOekBVHHQL+JGd79LQx6IalQeW+o9xvNlWl4spVb1iyuqc
ySJsA8ri4RfSIPwvf6ubeQRe/cpjC1nkFEYV6BlPZl5aeWJIM/iRg9u5DypMd5lppwLs6UuNiuH1
x0RI3iDG5/tUN8a8tizTxnEctBEwxuVErOlYtEgR5mDyh1T1Fk2gsaYgOL5fpOXaj2LwBbKKZa2y
o7KlsgdGtxxco8Uh3eLmsU1e6LkHdcpYFiIUp77H+bujseA7AYI8x9M8V4JJCP6Vwv90c2W4sPWF
f587qkfgWstg0o7jWRiHGIhIL+FzxbOlnXNuF58tIrbPv6p6OGz3unypCbHGlkGlwLSoNcdd8TUC
IuVRwrK5bZVGxaz5+1o16U4fieuGrOM59JCGosKYlAZKUl+AlS5Q1SFhsQoB+oaQfdgnMYwkr4RG
bkfHiE67rszUwAObuyWsECRczH1A25Ud4XHdJXfE5y2b8GVzPBhfaoD/AfS9qPyrZssWIPtkL8ev
cSKzjLn8g86WQ+LxJ0FEu43cETQjA4omZE0ptffwvsJJhYp1AAlCFbtR1oCk2oEbVXALYkDosWHP
RxdJOKIVo/xQOMe/+caqF44yNojmhzN7WpJz6WpdDqWwPcc0wIicG0MzYsA0vHXn6FU4rzXJeUwk
QB/QOarVQuVlvrjHDJ3nu8Sbcp4vQIfXaeSoVvzO+/uphybyP3mRMKFMe4M1ZJ5JdMgtEKSNO6jl
qLTPQBzGcrHVPdmCi1miGWsPh4Sp9YJX3+veut0pkFXxMzsE4W9WvrIasXjkoUsK9wyueoL8gcOy
uF4YqXwX6Aljp9028OGXRW5hJas6JU+d6Lrsmd+AZ19jHFpcR2RhPbTC60fvApyxiodF9xfHONGD
pRQdJC0tnYdx0YQJpggRzZjc/wg/LdhcN4spiuhFqx5wV1PvCW8rKAcJJ2/0PC7/UWqltlSky+Uk
Me4ckAYVFW282wo30aPd/RYyv0UnpaCgtP0+sq5YBaIf/IjGSS8fEE6sEXQnamF8e5M8ZoqvDrAg
28RtXXK1PHsvcGQSPWtURtqjSldCfrTVjHby2Cg3DTFYDorAVMk1LkTgfOBAM5uDb+VNDDb3zsim
wYBuSY5LqLxXJS1IHWyJNcVHZLoyngLoP/9Fbdh4LxUjKHoHDrcgjhgwVofIH+2mfqKoq+nMqfdw
YzpaPMBfZ2wb8yXhUAZDlJEFge8rgdSz2lcgqN6onK5dxhDVuck9C0qN5jSWwZ2E0AzwnuzdlTf2
XpjaDJD3viVB62h4m0z5D5g1qSqqGhC4lzd07DOZOpYf1wWyPyIBDXa3Tz5PducQ6l3a9v0oj9UG
RcTDQwnbd92oCutnkMb2xlexBWmqaa/H/A/oOl5OycEUIpG/K8gQPbgUY5UIaM8LSTSn5c5c9Y5m
bpLVAcQ5nLfGCKeqqHP2WjZYU/gQCWdFBm7IZT63+3N4MM5ZLc9h7VgQihtBbaEqDSaBXaUusJRw
1Wu+eB0sMaGHu260MCBDe5OvML6KtoiYVj/lLMclfR3CcuI8rDnixE7+6E9uN1Dwfm9bpz1gLCpI
h/Ul7GDYuwpG7/kFvy6FtgDdQvLo4RyYLn8KTKkO23WNsVkVoJApeOVgjK4/KC2GRlIzVQ0kg9j+
wFbymyP8hUem2m/JOjxY3J9SHOPvdJdFbL4k/SzwQ/lPwawN2ozr5HRnEWhaAocUHT6uLfZk68w/
xvWv7U+bQV6Lv65Fuyy2UAxqHd/gqtgWGfe7Rgivd+CvUQo+zkYkgOgTNuLDZOJIiXh4P8W4bku1
w/aZU3VQHYdIMPPr9WUomwsKT1nq2L5Grms4nu1tZZALlX0Qg0EIOBNc6fqAH5Mz6uavrktJGaT9
J8cf+wpY1Urg5g15JeA6eRoG4LGOFhFLDJU7uq0CMm9KhlgNIKN1LJ22M/tpZk9uVZD5CSmutMp4
K3AW2wrlH9abcqC/XJNH6qrd5gbHN+m+MmlLv1xFSCSUUNVte/s416A4uqbeqh0XkLNQXyfWJdUU
XterRmFLS8+W7grx/NYRZLZ0RxiLO/AdmRWfh9F+rduVXGdjxF41F3jehKYLO/trOhKecsngXWew
FBp/aFFuPTL7/ZW9UaUBqANG5W8gAZbkouIxDAuE39T/HWQBsMwanLiVZV88EzJ7W4Qh1sUDmCfH
3HAaA71ajwmVr3HJx13FE8Q0PSRLytK1FhQkf8H3GS/U2V+NbF3AxbezDkycJhTQSRuJszD0uYTi
zVX3UwrYWrBerol0BvhDDrJrSHaoGRGq6XZ6+dMXA0lLDdvPuysiKbTB9CSFDqRco1qffSL6HU+W
nrkpGkA2YTU4X/Xqf7xg7FHlUlUgp9ck94UgY/5iPafa/QlQ0CkZEX4U67fneXk+VxCpOaf5Bbyj
/rqUcvrQK51hQ3uwV7m/7Qn0Cx7N64ZZgrX5cD2i8Q5EDFA8T7sFz1X5HMSTE6v/a1AP147xQhNy
xJAU7ldVrvpt/ROE7Wtxk5MQtlxUjBdCEdkBfOv3C+h5Klnz/B220KArK0jiIWKrlM/aA21gOuqP
2XRn3nVKauciw7qCHQmawsgYqEfvKtzUSBY+ktPcaQ4bAZwfoS1PGJGiddn3qp9ped1KxDm0ufjy
gFaBzr3jat6C+StvIDG6nhs3y1ocNfFaUjUt7PdSgb0oasgDfmit5Os9L1g94i98VcJYPAPVRsq5
C2FZ+ZJapm+1FOuWN4G8Bb4tXFSB5KqiEHup9vWwO26Dlw1RfQoHG36Xe+AZnsgFU7K3wBWRXfRk
eEPnvGqBDI/4WWnU5PkR99+uTuzeH4pLLVU9PrMZICWX1X+zv3+h8Y8cBpPZHv0d7+rQngByCiyj
zJI2wccdor9Md/jEFND6nwZuVbCTeZoyRncvWZU2c8VZol2zpCe7kjXm5UV152u0g3015B2lQJwL
G6ltW/awWV57wVmZ+s9aLD7OE1dIHlK8aTRy7VGnLLK0sNcve89YqrUsPGIhpIAigxmRTPsOL137
170GFRS/lSB946iN8RFd3RHcOhgVIIjxDhtgnmURgeA1DbBUFiOt7AglyHfY897q1Zy5lT/ithcj
BNVIYkC8Is38iuhc9p/eobiCbsnSU//yF5FiU8ev52WHdg5J852GX1r/u5BrYGXQefRDtVUOxsHa
7zqKHAvB12Jb59Gl/rqlNba0ykiJb5F4Bi+1HuGDQsp4278b6VXoA0NvGEZWpDmXLIyso61sSbRa
E1Zl5J8W4akME5olh6HXpT7YSuBeMHnIy1MQWADk02tk8O7DHVgfMHcuBwyQOocZXzpdt0qc9iT9
vigvBZTSXf+pxCqHqR/BUJTRp7TS0iIc69opLf3ZiKj12ymQ4pRwWQR1h3rJZXAECYPP4iIK27E/
yL+pBwL4A8va2v6GOmmpriJOj/V4XFfB7UckV4FAH+Sfxe/9OTyJI/ttVfYn05RfYTTibpGA86es
5MKAgmWWh4FK72Nb3xolJ+dk+82E4X4wyFb1+0kZNaQLdtxikUIalC2G1cuyqW1Hf90ko72qsZza
bpvdOkdgbi+pnDerz7f8c+GOS/bWBpIsnF5EJ6pwfY0Y0YStI/Ozsit/bsBolaZxjHwZfq7bY+wZ
Rrbthm8LlHlXVQ+fhHR8lrPMKwCqTqRcS726yKz7qe+FyEq57dut8YY+aAz8FIFdSTjY9IOfhq2D
aPmWoM+2aTfiQkbi01SnSxd2cm+ac4VjJrlf0Cr+s+A7XXTBiltFj4+EGEPfhy1/4Up7hF2UjSd6
eVtA6OaL5h4RMQ+fk45it1RVQxd4DCPZX6m6NuQm329JlwzuDgOnpcC5uxJZUbnOFFowsvfcOqTY
yeod+O/0vO/ShWmt2sSs7+lR2kgYI8AJDK1dj3vhH7s2b20r1U8Rsp6C6TH+IJGOR+nb3S+tKLmJ
N8haWZcbPQNKu9ZakJ4Tvbf8L9f2wiVkIPvWvUiJyd4FEcgYYj6KDRfy+d5cYsoV+OCeXW01GxLV
4FYSMluo+WXZspQNB+P149yAM3FeSceutVHTPrF5OB/XWiNxjMSAgAgaz41bApE2pogajcGtNUtJ
CM4oF2A2MuWOoq+fOD7begKdSjdM3dL17jVGcOOmUFjM3xwOXFZM19R7AkCnjxmr3jbjFsKzeO/N
e8/79/3pPuYv9ALKnmGvWd1OW8TFgUc+21DLFCMZ4HdDzqJW/U/Hjl7Xj2Z9rTk1plfLP2L7S5nS
tbpX+Jw8Q80dGuPnHJBbWoA/8dvn7un/wf6zWl4dpj6mMTsoGhSGty905vyWvygNvXTsNNTfQDm0
vUj8lH4O1ClB9ghEKfjdIKewZbpo5rSCzZFET3vsYd6Zo3WYkDYDTMeZyxwTsXszrTIvC9tMfm7L
C4suJMNO8DctCipHGYOICFwKkadmny29LhsCzdxhhEgsMBwUcxT0iS9P69XZG5nCTYVo8J7K5jKd
w+9Zyvf51BqFhM5Ry+2j/8yRBprELSLb6jBOP1oxzpfyzA9Je5n5ShrwIgQan5f02IzXaNCMv/f1
ADpI8Wms3tGzQcy1PJac4DWr0EQjOm3NNXGOY15BCdNim6EIt4BexCll84zdv33YIYSlAGqsx6T1
nq5Ogto8Uw4Jor5jPo8Nr5XPm+zu30baTO2NzSCEBqOd+MvDT6l/VfUae95R99ikhtWl3NgAtAxe
CE3lYa9YrZZMtmvjQ9WppMPS1IDI+ACPhU/5CpO77P/1UxfEdxUZu1Y9c7fZuM0Ngw46FHRRoUH4
rUN2ycBbhsRquEs8afgmet1VnsiuPZ25AYSSZmxsxAy2LlE2QwiKIzEuiTiqROCp/IKy7fdWLTlh
QW4V0G+61oDG4o2c0u5IZYL7mJBeTVPc/4B0BtsB5H7yV0bGgtbCmn4oTizgFYIfbUb7rILbuc+9
AonaSdvi7oWmZf7psFT+xAQtSPTl8K78IjnIOz2mQyT4QxwlFCgotug+W8eg6hygH9PTpbfcibPy
r7hK+FDxNk2ft1NL2QnqBmeQxL6BKsuMsXMC+MBBlep/QyGQkETJPw+o4IkfGXbsm7vrlA9mE6Zh
4pt9U4pHnG+Iu+9LLhVzv9M3G5R6OMwk5I69i1zyRQkoODpIdQV3K9W03NnBoTRH32nsZmIOkAUA
SxfO+cpmqo0/882pVVYhNwo4RHIlHZOOgkAjNw9Yjt1/wwA3zAH881R2jZmg42M5lfPOhp8pZrkL
3jirEfk/RgIPiSOMJ38x3vszxjAUo4W/vKnb+q9gnh2CUZP6YGMOLZMzAQZMPrOqn/Ks8ZnM1tAg
yGlfr4hJG2vVYMYWFe7Cy0nLk2HrV9gtgZi5vICXqmxkCJIH5dHpQDLqY54uyIWa+NVZ4wPZzkOX
8vKxlz8H8ifNxCev3m/XHNMUIs1QgGrdKFtwgCciyokU4g1urdBnqoVGjM+5rYf4KCCmVwNqHzoa
cxfZawkaR2v8Y+qWlws8gbg/B0+2VOYyorKfHJl4Ofdpia4dpdIybOeggSv9YqaH+fITbIoOWkr7
AC7FLwcOXqgl3b6xIAvJbJo4fnf8DgxDxESZJht9paLTkKhcqfUs900KK/3K11NhUqDVCfXdc1ek
26Fab7wPtbalU79GnQ8FSQDXtjZay8s9VHYLrTQI5cGfn10lDQy5qHk+2UKfjRPHgiM/C1wRLH1M
CdlsewOTPJ8BjO488kXcXdJrQpX9oNgEAKyUdv7vn7xapueYd/Aq26GRzlwmRLpo8jrcNl96fzpT
kLzNWyC5BJ+GLd1hI5IyzsaAXXZuPiGk20XzvLff25eofLngCIZ4K0EJd6Piwsku0lx1YnqDOBO8
RU8/vXgrlb/8LBhLuVXwNS5B++0qxPMTKW11ZMz5TF7Tf+mhcCqnu0Xi8dLKE9No1MLsThI7NLR2
8iT4OIQC0O+8I017QswaOddD+nikycAHqj6QUCllHtAiCu9D+v0TRDNKr4VnGJ/92ijJjDgnKmC3
IBfdVytu/IKKaNwY6hN3MPT/xi2U8ih/kCD4XKPOtgfEM0r/T8MaqneghX5LUB8YsBM5KaRfyDga
EBrkPYY7QaYlkzlYfs78AIPgtlYpnIDC35AEp5pBDIec08nwnXp5C9gBtamVFOMZsrL858HnACyH
MZiLZ9AiNGncBgQFo+msau7vvgbq/Hiny9/83kJDLi6IE66N2kuzj4gi3w/f9LAdmEVCtK8e/NKu
hY7gIhhYqUdcqJezPbLO9vjyR2D++LblVVUZbIspnGJ65RHv21dmIiIbhQJ43KZUK/A96zxfB1wP
y+CCWl1toibT6lQkoB/y3nl1l7HWzzGv5zj0hXsubWRJKTvE9vKWlC31WwrYJ0HByRvcNoFVoO3W
uQBmarOLqjYUEek84JpXv31Ze0cfpXRQtdkPz2qJdmbhQZVK11mnYGr7SKznYOBwOthRLfsuNw+Y
mkGi8W5SbX1WFbuk1I79bCJu7m51VtMbbBCTBHqDNtKOVaYl0SCKQz3LkXQwSYrkMR3KRqj4TgkG
nuny4/libJYxPsJPvljjgeIM9An9QhyohUgJODd7XKkH1T25mG21T3UNEWx9Qe1JGVHndUbBPIHc
ByDWReYxVqw/ofWitRiW+Ayh9V+IOfYg8lLteyk42cC2gVUYRN0NhWHyHPI6gFgnaOk7N68x+ncM
thvSw4rmkbj1d6klXLurY5/k+kMDFYO+9MrtcTF5a2Gi26MD13hnJ2RDPTin4LfX8g20RwnwRu/M
unN7B9NrCP0LGpTr9IItFakFHzdwF8ZRMEebSN2kMoSIQHFqxoddxP4YdqA73a2sGDPVPfIxgrcv
J/w1Jcu1GY+tu1qQB6jGY9L791yTyLXpJ1kKuuqIeT+ygZQCcQ4Clil/jPCG3xN1y6e0gK/hX7jV
Mroh35fP2NmxO7Efzeyc8xyEPo9rMmRSYFZYyHNMdaQtKwHBwqfYjWOWDJpwiR5jA93AMT8ffKaH
S/BpS/ZfRCNVcN9C3InUxMPZN4roC0zBHC8h0GDFsQmIj/ZvTNRS4xHkA17y45ZWalGpmlIVKJM7
LKZV4mkc0fuRXuwplZnAfZgunHNGj/WH9AHIffpx74L2eb8T2QDvn2TpdDZN6egfvkyuDpXP3uaa
fP+sCvgXxvAZB/pQrdhckTI67kG/pYGOw4wWuV6LzJ0Lo+y2d09oQqUVKTF5+eLmMuu1O34+SHYM
9WdkSy/LRHBJxozH2MHXQ/6CbzbXH2I9ggHthObUmqJ65roQSxZf3+fD65LN7ZCOldPRsDXZBHEy
/uaWYkk758/5L1rNNz1XWEnmpO7ogYGbeRyqvYi4C/s4cFZIORBcFEhKgS478OyMQNKnjiA/h4h0
/T7Z0crM4QSVN8d9lA7BF0GEx39rKyDEsDzQ5QBo07QK2QbtWYtSUoctkTRbFbCg9/hQHRCVPQiO
Lu6gmKLatDFg69GhFVXzpv2FApWo45Q8UMvoka6jf0SAoNboC2LVKGcyd6SA8o9rUKWNPnZrj+rT
ykoglUUhHk5vC1mrXGMaiOU0y5bRfd0wvjI4lqdzs26z6+c9fTaqHCHljUkw5rFzQABus0FSi0pY
LCqMbi7UJyCtj/0mtk3cChIJQRYm7kgeUZmu9fei6Sp6DGCSH0G91RG6gIp4yqM1+RP54ChStLUi
djLrDAjWku8W1zft8N4XwtFLYTxzK+D8810NCBC+xw1mnTdsMwYqXrF5ySEVDD9RnUVGmzeRI6p9
xzjMZlz8pF5LeZJEaEE8K0yHdpSdt9izOSAEUbnUNQhEjPsf5KTGsl8QnYjnSwKBjoTMmgtwWS/1
YREmMk56Dl2HzF0hod7NLmOdsmmRWwlORc33TZv7bCcut6PYPSDN1wF/3njovfUIaPHWqIBgbi94
JZJKW11cH19OvSGHgfogYjH2Z9nRu5vbd5pvogaCDAyQ5IWpRX3fodkBOU983uRpZF8uNMlRr77p
2gqFOENOloAdSi5iavaVJCRQKYsIZSspjqIn3K9w31d3H1DWYnI9v+rn+EuquDVNX5+N/YexfOta
+phoKrlPGGJSTDkMSJBnCxQ9icB6Mj/G3KtNeo9SPBwsvlCDbSjvlixpUVNoGunuHQaTISnaxqBO
fz1O6lwA52O8xbet4F1fPbSHQabf8h43hFnu7vuDGjwXvCI0fBQKUYKm6qdOELhLRL3FIvWdA8hI
X4PerGKHUuIzup/fE8od+pAzZTluBI0t1wfSX8RgLbHKlfp2NxrsmSwI5uEuqnsgsoYsXGa+2G9t
Z/XAYMdMX0oUQSgXy/+bHX65I856pevzkmEzjx+g+LFPuXYDyhQ9Uy19G7SKMlhdt+MhQxB6HGFd
SBCU+v+xbLE2b56PpzZsa0wHwIfTauxblYQCmqFze5MGFQC8OfL4ZtDVTYHw+5z9/MosPnTJ7oQx
JI7mvIeO5cSNuCpeWnR9GAs+6v5gzdMPTuLICmER3TYZ37MA4r5WDOsf+81B2+B0pwrFDCHygkAK
9cTL3AO6tEcwIAQtfonlBCtyOddresa8Zidw8Y8XENia/TfBdVhWvrOwfFxbzsNEIOqF3YHB80px
Kt2YinX35ptmdpFok3J9UQFzOGvb5OYyaGuvnAsxG+yFgwbUiVLHZ9iyrgnJ/KjQrxKDh0MzG8Wb
L00BLyOiF/wQiNPzmq65ue5iG/CEgTIH36nXASBBSofM6a8tZQ1gfGG05V+ZCBRQDRhpMjrogPAa
vEEyU20ddHjWxIGlA9PXbTyuW78+H54d4sdmmnDGxcHL86Zod5/YcaNrgNo9rFj4vtM95LlE9X/y
T2/3353gUCtLD2YhEKYyEjokUmBNqgJU+ki47ZyR+mXFrHGIIiJNJfG9+10rAoR5TUspjx+zIoo6
sROpWhECGRTtAAndhMuibeyvaViCXHiloVVXIIoHEtIdnlX1kcLMG0FfjTo1x1T+DK5q6A8hEtTh
+HR8QNjhRO3DL4gSwhE3Q6JUkhvJqxOzLEjQVU07Fk0NUvvIEDvyW+CavQQRVK+zZ9LIF6xbN9yi
qhjBcKH4FsorUtIm7hRKUiwVztst5hA8kZlmp1msDtMbnWE8KEE1q2hdxaaRyeaNZhzGmzP+Eu78
sENn7OP32UgJBbraj20oMXozMgff1oprqlroo+HCViFKpYJPotAYmPORUxdGr3NA1N0bOHxAuLvA
wRvLuS8VOzXMta6W3yqXnvFe7m2CpFlVs0/W8741D8dV7OBFQ8FfoBJJjih1vm3WDuD+21IcwUjJ
kAwi0wrNM+IdULN5x+5vj3GYrs9sJvpe5j/IvA4eHk6Hg2QVuxSW8buXi3H1dEkdmyMIMBJcMkAJ
sljT9rdnLKz9oLjo2dYvUHQLKD+l7b2dmtUO3JKVJR134V7/YpZtFwnnTMiXtLEiLD79b8+f1Ce7
LwWUbSeOtKilckDgNuxeRY/cpiqFawGwvISASHafFIizTxrqZAI2nAIJrYUz36wE2eJRkBz5AnVs
BKwTZfRmFr2VNnRSqzN3wK4keFGCFlMD1sBrKLfbumU98kbUoP/k+wgeSc9Xr75olkOxaDzFVumH
XUff3Y43DJLknASr/UxdD8MjaMMz14ChL2ZMmdVsEKkifqxHy2tFnNFW+6+NTT51fHTMU73//iC1
TAvqowmFS1MIzQrUAlX5NdSZtp7t0+vwdXGLL+Q9IvWRQ60njSIDo7CUq/E6eOzpqEeNX6Zwat0I
XIW6eKW+8DXBeVJDPsOxznGH9N1FucGF+qliDkckfK2DsC6/A5lZfDuCC/78FMTWj3A585HQag3A
MFU6Mj6o2VjkZQE2NRU5uHq+Hqgbx4ZPYRpDl67oEAmZXcCtBPmXJz25Q7nk4Vcm5TC42rhdF7av
++c32WjnGeucNgMqCM97UJqo63/rq1lGm06u/F4jAJvhYoxkORRfoDD7p2mBlJl9DRWNTm23cglC
Iow49rnPJG1QQMdBNE5F3cdi69KbnDWCFz6nnBoOmA7Sr6opeB+iluI9YOOUmI5GE/Q4iN+WyWwk
b/kiG6mYHWEIa4A+Zi1ugiW3khc8jA3SW4L6yGTegkQKc0jqTYeXo/GogPUtOUKyzRDPfy69AUSd
cHQPrMFqDPOgj8RdVRwsTvAdnmW1JXFq7yu1B83BCgIXanBcPZ8QgNnG77mOoJBEqErgLM2GnsmO
xsalWTBWEofK+kV8RwYGSpepKg1/TVyegAUEAdYewuw2ul2glUJTPzYP1A4yQFlmisyAAgKdwuYu
KPmaizx1L29cr0+oK3sYeE9V/6mtHslnqxG6IBNxanej5REXsb1IpYE6lAwB4qP/Q0Z7jZVoRQiI
A0dSeNKSZKcPUKe4EETyKr0l+KrNXvVjMRpKNnW33H9dUiNNueSHRqmhlFIlyq42nnR0kWaMjmVU
eefFO5tD1EiWpUf0ZLHJtDAwD/SU+WbI2KSFedFGsHOkIUIckD5Lm/2PVOQvGXWTcm9Yi5IKUFJu
GQAWMR42deE8clgwfMM087/+k3kJSoZJCyh8pA7gODoZkeQyCuiGV6yiEfHKUnCOnP5LsPMj+h+Y
YvaNvOrtQrPb9AAmw/mDi9tQuYC933CCxg8sXpN1XzYXw7B8VzpvurDk6cd12Fznl+iFoxg803TA
1XElC7ri5/oj0HMMYt78HzrD9CQXr9Lx5G3i/ICDlQfNRiUmyY7q8q300mZgpCyyGZk7SU908dRa
qHhEeThRBl6E/2O6ap1cP/sXSLFtw55nI5J8sabYB5w8nzLiojjc5kBxGaIhqaas7/DEa4ZOhivZ
/E/aSsQPzHr4Y5zHJxB/D4YLJHENqMCbGb69LT0VBaLqs7UynrCzLoYx2ohEr6FPq54HR2KkTfBL
aEGDyt9v0YICpR+SK0zoB2nvdoJUY6YV/x32SjAyhbC8elOJ/UDfBTxddsJurZzSQQFH1V+oxmd7
rcBfePMhVt9HaU1zlunZKaRnGBabfMQXsEQUDZNjFH/53fnQX5vm0+ieP9tb6PAx2fW0C4wjJ4z8
sywhVGyPEXEUQmvX7Z+e6m+wFybU8u1WwidvUbdudZrEyB2eMhYwodphIescGxrvAk9PDgf6ZD7R
tREBBZ8I4AbhWYASBiKFwq7suf7E3YSnC69fsFcGpH2rHacwnFQ94HXmrie6Cf0bAgyRThhvoVH+
YVX2JTB2J73tNRnW9FaMUyEW2UyhGItCTVGToerFKblZ1PHtAw0bfTuIp/bL1oUeqYsB3acH4Qcl
tR0bvBGy9vwPR/BNaL+NW0dFwuWxRFF0W6v2BAxXiJT4rgDfh9PpS6vARFxI0A3l0efJyjDrFXQh
c/Gf3sI264c3tRDfmmwN9c2eejla2YPt1diNQ76WGWxhkTOhPrLvYhC485BLlVZrP1nNx4tTAvlO
54BUe8DnaKi0zcfyoQXoA8etVZOaL0ioY59myzCnw3vOonQKzTFXfYrClo/hZyKWiGMmuOg8Kvk0
JXzRK8EVwAWOfdMizIJxGYLjjXOW8fTKVyiXHV0zQqPTnXU99TAWSmkeATIu783M3Dj/xPqR6P7f
XQ1GSExVRa2eVpv0Z0erHZT/HJSpjRJnhghF4fio5V2tVzGvSr1a+kHtb5PjdLwnlYdqjtKx3Cih
4luAPztWucmiDmapaYHCuRK7x7CoOw3r29cmJXCLJ7YfzO79YcmCTQNygE8kM+IT1WcimmtPoPW5
5/4FQvT2dCzYTZ00l5ACXSyPKI4t0VhV4GHunjFaER64mdbMuHka1pzHljBPfA29Ir7WWJlTtAZO
Jbgt/AQyMMbXQUaJwNS1Jvg5SjQcAP3qEC2g3vPvXENek8net2uIOJTn9V2IIGZUKk7T1PzQqZkk
P4C/UaboL0hBIZV5P4aBrT267wIARqwH3PLbouO11b4TwPYiUcQS2igzbOFkYzewwS5QZaHzLlxF
wseJIbxWwgVBhERk1iF08rn7smVjTHxr3w8siR37FYb3N6TCFKFlBSTn3MfDYsFIS072Q69vpJCL
kRxbKsvd7AS3ng/eVLY3Z8z9Av3xz9zT+ixF4bP+Ua9eTmDHgjiXFOJX2Xle3LuDjQ73ZQ65AsoG
ttNzc6CzYKc/G7USVvciBCKgtItYsslC9UnyNonee347lTBmraFi13mv5/F7enmH7tnOpLJCtZ7h
zmTgMVxKpUI64BC2P+sb/A7Drk4/D5tRMolCRnPhDwPy0WdaKlEy+7EkS+goKMzKMfZ6qTkdfwzg
Gl2TJtIEFn2XZs2P93Qb1RrEfsKf7Idpw5KiHjnwYQYEWlkcywYaXyO9+qk62ibAZrB/6IExhz1R
FrmlCIotb3FAmE5O8LXqOflEggKyGkN9RnQdJW0HIgZj/hFLU9GPgOPJ0GeQK24t6x/zDGwc6weQ
/U3Eany0FGqRjGek5lAqL+gnQT2JDWLd3mgion+1mD6HwV2bJRALKsuiUMkTwH2bMU6jDR/nikel
Co+rF5p3/ypGl26+lRjlho1yHY7xQmKrfR1cuIg4N76jf1g9maZLlUPZoUk0TXy8mukovMjvfhjU
TAU3NJlwZZnYJDbsaB4rn02b3FGqRvajPwSg1IFXjI7jg8J8ZiwSG3FC9bW3stE0wf1p5Z4cjuH2
yyLoavZ78mx2qTiMzGqxMkuNVTFrxHkLzBV8xj2AYgc+CnFC8+barb1sN68FKGJbpUowxmlHVcd1
T4sWSZPeBRYEEqigBg9mgluUBkw+iy0M+/Lv0lwLGmAP+A9lA/Wyw47Xyg2KCUPiu64h40ffNc8g
VMr0NmaKlM0cdTJDr0Nxwm6XYrE9si8/KRQrh8OyLu9CdAvNB3YJG3XkYkLInsOKK+LcmybjfG52
sp4j9apLOJMXpdQWrkqn5hixm0vhdJNGb/MsN9m5VA6wd8spf5dQ8pSihFGlEXRkg/N5YdsxIH11
83NChn0dlQTHOkqWJDisA5BlMVJ5/spFTclw69pzrUugMJzC0H/OPZpPnR98rRzl/BMJvUNzVAqK
qDbOctzF/4fqYrr6hEBkA7tBodmCMEesSoERwc+dUixU1yJPijui9S0At+pB5B1e60nEcYqIbtte
zmZ1QDZ/y41k8U9Bkm+oLoLopXPP6bVRTVKhn5bqsBd4VDNaGsZGXvqnwdBQvmwg8IJDwj7+Dt3a
kTvgQ1K/gmcLlES2le3GZg2aXrZJMWbkpCJrEki3SQG5FeZzkRjCwDhap0t+DMd1ewK8tGjFwubE
5h2dumz1KvRgs+IE/aMRJQCnXHQV0QnACgs9jj4vewAZsHX8lUknljlX7cZSY7SMKFLDpU1CblGQ
fcgF+dUSss5NUOD9NjqhZPJWaktL9bZy721pOKDIqwhjYE3ikFYwdvsXdD4oFB9D4esp50Or1/n2
McKlqiAjo0fJBfktfeqo7tXwQZ6zDQ4O/bEiwcic9VWusaZNr9QWpX9lXw2HxeQLuMZ45MoLmTvc
bqMBHNbxcT/FTu519DnKDAahgucMkmjG+CJ/ksRuDTWN5G1QK/2HblecOodtb4a0s9WMA41qZrRZ
ADEm45YvGUG3+mJZosn/EXOSLK8F32x8xcepf6fyap/JC6dWeaVBfDmRfCu97+FgXfewi0cL+pJv
hVgJ95lShr+L+0Eg8DZcqbdyvT1hRPyh1GwDCdvwMSRWjLSiUNwovFxcs4B3rIaUXGMHLl2rRGsA
cOHtfih5GljYfoa+b8FlWgJhfuNugyU+w5SpkZUI52k1xNoBiTvLDVAnv7rn5BztTUuyKw2iy71U
YOwZ0lWGvLb6rnC0V8bKdVOCuGpkstweDtB19aMCXIC248mYVUBkKm9kcHy0SnfYxHpeW+5WH/CH
RuPRcX58Xx4T5G4jHdfJg3ts3qGDp1Yw1fCuIlMmslM+7w+X05UIuIaFShD9bQPMgTss5TAMMqdN
la8viN6tFuLzE3WaoUuH10Mwm7kY8S7vXcHEbd76SKWKPvNZv3+d9Fzu2YgAUcIwgod1tABxcZ++
6OSV/wr4g21dODRPraHQgUhGG3ZQWEjhPgMBChdSGlR0yo1r097QXZwe1Gm6kvPxyLqzDdoc/bMH
/Beh4VoFIUGDtfePbv46l2i1Zqm1tj0HbWxl570MvoEOKWE9EoVhv9AV4+XC01Bxd8IuZJ7bftz6
lX1QThjBy8vGfALZpCLwrrzmpqpvBwssjWlG5dGCIzoCRJ/iDJwkjO7b7k9Ghizrc8K7sReu239I
4zXyAXRqNMjcgs9WewpRs2747ftDB+QRHIyGH2S1kIUvBcLHGcQBEKraKTNR0x/0CVgn6W6PciGx
4OEZ4an/Yj0eB1WBzJb/Y2Z9lZ+l9UQF60P23ylIwQM00SwssdoqxRIZSGc2EEhoC1k/FShp68yU
BfuaGU9Eid8QJo7Le1cw1xAYf4b+/wnKWJrl5rExqZQjNUcVgmvjCdnN2etrlXcir1mCAyknoBKV
F0+VbncXUrllkLjWCzs6F7Zor5mCBothpdg+4S7D0eW8jnTe3JMEsJUFrxXxyaoJ6PVKwZKV+Klt
5k7L5RDTTo/3AQpjW2CvDEjexyI+tyNASIK0DJctoKtS+gWeVDUKicubYlm/SUhHq2TX1O+aZxNQ
uRlxD1MFkXRxYgBkUrYiI8IyyTWcTFiZhSsBQfj79jIKgpXLOQS2WjpYoV7/qWWT22cRPsPT8PjA
VGX2bp3lFG18bNUgzc47lEPSMJL9SE55PgxADul+SX2u+gHr8Zn4DG/HMSeBRGKZ9zNoUb0vOGPs
MEYS+mqrf5WQSb/Zb31Ak0ZBNRq/7YS8zw9bO4LxB+Nv9/MjlpfV/2+NZDrIaeOLWdINPOuIpakV
kKwReU5Bb2bbtp5qigH4RzqKga49LbHTDbZDc7nvz5mhKV16qjqhuNxv8YAGmiw7C5/j8EIyjexK
lp3UAHKu4nfSgwbEMVmlZWa4Ybw64urWuHOKMMwq8Nd4RvflnUQNQKtc6U0xkruSVXRNS5huIHDc
jCmuL66mLdttZfEu76ohKYt/YfJsS7kE+cOUURxC00Irts66H58wPV5ri70q+Y4EUtjF4BmqrL2q
WJVo4OFCsecL7DWZj+9emstp/PP/xWvnrWCEfdCyCgLhIOMOfJb/MIlfWOeXxtU5kZDMt7PuZm8c
TBJD1L5Fup3q92iZGhbo29O67pya75X3/ZAFyK1Iv+CHLjJQv0YWzPMlo6ET3OU4hBKclSt5XabQ
uIgGZ0uLdBmsnsz3fRa9rRhNUvrF/dD6HCM/BDPUYKzElQsKX1fElXtSQN47IYjDF+W133LmTm8k
o3jqHEIV3EYJLlO3T5n2iXjUXOMQTQlvJpX75BIZvDrvDcTYRkU96wkH5IZPDNnR95P62+MQN35H
Ku0A0r1UuK3iJAePuj8v38oZwS3hr2MLoEZ9bPkTz0VsI92xCGOXFJbIHBG+8z/UafNN8dRsZRnv
qPJfr4ksKWPaOnPQpRMBZJ6REvfjUaeeLAytXkZ/0BsXVvSpp/nwsoDJ7STIGWQuNs/1Q7jHfdup
YYDeWYPT6kBcGXPcd6bz1bzH94jFFKlzgBG9TcXozgCX5oF6HBgMgy8vp2VhNutRukWIYoOuCfzd
8oW1B9OVucRI7R7UzmV6J/G59r8xT5sttu/Du2dEym3HdVpfwzDFIK9RvVRcMCdjCm30uqEnn4ki
I+XzSh0+We13WyRjP4K4MvNnXidUNdGb4fAX69B80W7cb81W++bOlvvq2MZafps7zNF7yVq86Tyt
90BQ8EY3CnFBImBuy9/wwfOpOGlntFvbyf5ByAH8lTEFzc/DhSBz2sk03l4BiosqIY63gCXSegkV
jNGeUnLMQHYx8jgsRV28YSdGtRDGqYnP7m8MfWr+ZmmgGxPhutD5JVjY6VvTg9lr8r+zwjF25hv9
2QeJTyUutCoY/4gA0Lgjl0YnaF6o4L0Mt/Zk69ZCsG8nBl83KqCCi9Xrf+PD9W/GqrrhWMnoGNYz
HyOuE2ZZ4DBRdBbzCwfx9B4UBorSS5oGsVXMoaCjXQaFdZU1p4JaVGevzKakridCFCLJTI1CQECY
K3NB/N5rCZQnz4ldP5zUFPRUd7w6z3aFEV/EPuHqGP2RihhNF07wAOvfJhj1mWwl9j/aGrnb0+0X
pwVrCoeyu/FpfNWrpP6Nkun8Cs/ecBznMXmqh/CvZ8d2z1cY+Mnet8ECmL9wksWd+VNzovoWQTTU
wi1MIbsLu6AJ1qULUQXdN6oxvAVARKmVloGqhsMBIqyGUtKlmJxARqeck3JTbetOkUXOi/VRcaqx
zvPDuJyvVfzWM8gL1uRA4lQXepoml2Y+RDN6Aahr0RaqFRhdakvxSJ6PEGuJGUZFE9jOnp3wBDBT
iI8UU7d1bNgAnyOYufsqymkMvBKM2hLknXhyLr66w1QqB0tjhx70YCBWZwmLcHAi8xFrU3Ugk3zd
SlWY1vLT52oNmwi7b2DV8cqZPyV7oeuomrqanjl+p0j3WzIXWNJvRRa84jQL/8vNC9pWbM9KSyRk
Drggzmr3aF/Fupy+QzhMQaXkTxocmpuhIif3sQua747uIuSV39Ok/s9arr/siZUTyuBy13XsNYSU
tkTIIfGi9m0E7wthYN1OCVzQMeqO4AvySI+qkAuQtO1ZHdVEzUVuFwW72nXMcdWIi3B9TPBrc62C
gMBasL0AMwofFl12X2gWqSu8uzpJbvpsHryScMhDtZEfEFrXgWAAFk/7IsqlInRFB4zi1H06D0A9
9TTS1V9zD1WiGiZujN8HY4dQDbNGIJQqn/HxIzw+bjwFQDK1yHN2zbHbxvxpz0ETDSX+/c7itKNQ
e1KNgpEv7o/OBsnTxCcYtmzAcgksD1iFTAB9vx1pHOwQK/+RXZ+qiDm+A5YFYTDYUSqc4tAy7Ff8
dHfkG3WLu4idi61y6R67VLKTsVE74ICWiYRhZSIR66/eD894nrBs62SVwDb4wRQFWxa+KFprmnpR
dEHTmKRO5p2Ejbs7niirjnkePRH70tnKYmky9eZMnTmSEFdZZ0q1DcI4IIzKA/HH0fgFdNZkjUx0
BCfJymumFq4VaQOeTesvV0My7g/C5I1GNcIzVsvCFunwLyrUlIF1kr39lzD8rGyQXQoRDe3mFi1Q
EgyGwrIRubx7BCVV/xar8/sopflWf38YO/staFwRNGL+v/nmf6x6FxvxPxoRHQMLmFEBBqTFMPT2
C5UOF2eaQLvKtmRXz56tsbxFlF3A2lW6hIwmiRnsdK8TPqbPTrWVzaZ5+FIj6fdl5f4mbnmbs1dn
woN/oK2vsNsg6q+VIoem+nzrBhPu2O+GeONUpoaEFixpXN9cp2kGdqhsTkPS4ncD4qHDbmc2N7/D
5HTtouaVRpyWLvLpu2EIYqAyvvRPDBm92d0CaI3hhstdfAQA29SFW4QP7HGxDaXm7Sv1C2tVgy7R
I5kCAZCIz4ozVTExT8xb/Ul7veqrXuRLidMh6SeD/X9QKgS22LRI94ad+mEQyDikEEbGVSZPZFfr
fe1ci8n1azZk7j90iSKOUp7gNdiFIUvUb2MUZpkhm/DVWXT2hpqPIQMWPh5ecP42Jpy6wmDukrm/
dyRG15T9EQIcerYn0v/Mf/no5eLkkjoDNXkiOCJB2giKn/BZo9fKfGVhC7HWrms+uvYvpXcl8yXF
8nkk+1Q6gfgkwiXSdeiHe2Zjt8re6nBGN1JnhFOJHAPedyjB0tRG0ehHwnU+KSFGRTH7onxa4oBo
iZy7mpn4XivqCITRW1kM1LQz2QjY6D9J5jXolZApkgcpXQSmq6UqG/j+ACgeDRC2kIsnDrdiCG9C
DSxNRQUdtNy3EoqVXsVngmPgZcIlZOQbDgkDcuMPqaul5ymqFTKkZ2Y2JELJQAAOs9eOy14SOlpo
OeXKRvydBzKIWQ88896jA/yreF7AmmINRwGGOPG8hNE4vYnH/uNH5xvsN9bBUEgfGJfuKVX95Yz8
ERF1ReaHc5B+7dKVjAbxNvE9zK7689QbhhPxqbmeKSTwlsJIqzQ9A/K1zmVtIjlaSWeDU/w31cJP
Ubrm2zuA694f9b02+GpNKfAWIYTgGadV9XReYrk7fAYgfSGip+HXnuzOG2FDpNGituXppICi+oRp
TUMVnqs9JKMO2cABxSbGhUtJ7tP/jNeZdz1skLK2DneHIwbcers/9u9IURFjWzqJJNBwGw6Zbb7i
kvgOfl5+RKc3H9QQz4OBUkUAr+NlkI5Sd9WHM55j/f7dFP1h493Pfzru7s6mql+wWb7ka1RlH4Jb
+9x4P0049ZgfzP/tIT90n1fS1OzFrkahg843gGx2vPwSvIUg0NI3MviVhjmnbluKY0EChPZEO5gj
1KfCNWep2Mi+SjyRnLPklH5sdlJZhvZGYVUxXoSVrrw+k1XGfRp5YpC+uYBMz3ltnl7wLAvjPqf3
lVaAbaqu2PGiwYRUaeKuo95gPVGPlNuCQlhzprTf2LNwuPK094IQQPa35sQZdWZZoKzT4L2OU/UN
C43PgyNW9DHTNseW98l5Eyg0xxl26YDmSsPnr3omb7fu61/J1zxla7kZXcl2f4AtygbKEomc8jwu
VQL8mat1f0sxWm5uLtvsMFKIjt3jqNj3P24Ma0wwIqshOgA6d3ufZy1nwYtyXwhRj/+UXGxCa7NE
5iZCPN7NpBTIDbRJsUXoxoTjo9wMhNQ/jqOBkDI5GaxKZ1RnxJIOoPeDlpHPqALp2eYp4TYCkDq8
HfdXNi235/pnprRZVott2xMyaSFx5UaZ9HXctCS8BjNHWrbjQHh3lyPIDtZTTtfrYwNP2/YE4KAj
IurnLwQOaUuJCu7VFD1ELGFgT1GWEnSlE2RzxWtpCDC1Pzm34dNZb4TO0L7XaNRjqIPdmKDl92IW
SE5oln8fGJikhtx7gGW0VCdIdqUPe6att0tNmOuZo/dyUaxnV0P9GAZn5jOXHTDJtpk8udSTBtaM
EQmwdFzSspkPTFTkvHgC8LSIq5vVaKQfXrbBBgPPUtc0mgHIZzGPzYIqNmVGWSC2W9SFtXgSF1G6
Ec9j2uqT+Rtca4NMKq1PZyg/4O0esVpV+BNf89r/6n3vxea3L5mgWgwHVDHYSMfqAJPnvs114J8m
wXIa6990zpxrCsBQXE7E9VT+sKmtFxgTCuzG+TZ0B4eNd+roowSiBOVUa5UBHeNRwnec9AejsEJB
IsRmhNcAz72iqFNjHmJJIljeEfqqAIfuTg0QxmCfE5/hkEOmhkxyPfmwwlusvaVGGJ0pQt2shwgv
pRhjlgUi1TRA0Zk+ualzo0SEhKH8y6SGRTVtKuUza/p9carFS9MqC1EOHncdBf6ZupVanyLKs8va
Sx/jROdCw+3+zceD+w2icIT16IdxVb075qKEyIqEORUqcbz/GdPNQ1wOtiUpdMKr1Q2CjmO/EHlV
2cFy7YHvYu/8sk05tdimq+S8XHZ+9UPl6fT0/Yw7zh1kgH3N75KvEZY8uEkI9XOPTZpIVnPw/kjh
32xNB0jq+z3CVC7fd3ksj04IfFFz3fAGz0L2XxMXEKCpwy1mKrAQSZolHohCTjUPloXvXQ3BRmwe
L149LYGfibYx3eqhlGwFGod6BAYCBETtuO985h9etoYKiU1QJbidvBbXDszXYcmlhVdct6goGotr
mQphB9UiLHwLRavMCjt2bll1ytQzsiJnHsd0uX3JzKB1qCe3gCO7W46FeMhNxSKfoNsBiC78u02E
NV+8YG+VihTHafIYkORy2M0A2MZqCRrYqeflqU7qwsc5NSX/10alsgbpbJ5yigJHopNs3esTlhL6
SqcMqNC+VipFUtvWztyXA0dsfk3xCd8onZlVhox8efrB6QERleiKM/OgCjsvoiKVSkNFDdUWCTIw
oRlnS86dsZfVBCTl/nDNL2UzntdawiMpBi+rnbQyPMFAUbVSuPyO4i6kBdWBOQ+bhkEBSiKP/qhb
Wh6RiNLBNgmYK4pjCqnz2l3el6U0SNd3YWjkU0GhVHI/Zm2FXVklOttTKw0/AlMK0UqvC7p/nngp
sCM+ttHBGwwO3wkPEAllyHggKqhUes0n61Vu3eBsKhfoSS9rcq3Zo2wM1f/1OW8SX2t+yRtGonZU
/+6pqUhQQPw90q52T4qwRcN0aihEQ/o8/DNoxr9BgbUDIzS0qsy7tEWSn+AZ844F96byLeeZ2kGe
aB/JI7IUWVsftGIs8z4P/8XqVy9WaH725UMmJ2m+382s80632WwTZptYJINbMAsEnG2feGqUFvcM
rvAeBVMN7tFnYn4ZDyrZxYgpQgt//02iOd/iWyq/HUvqA5NdhP64j63OTh54VK4G1PSrQX1wDPTZ
AkELIyUgUa6IgCdGxA/zSuK82a/2KzaKYQfBY4oMBQSHGvzLDhYJO9a3CV8YXmMBhQiGruR3fNTK
273hVDjIDcNRK4yjX/+Db9goTzoZESuL05QNuvD6t3Bk16mtrBErVEt3wjEgoaScd+fqvYOkmaGd
xumgWD9WVTJQVQqjRfSFkDxRU5Jjfj+2Qz20PTCJ96GSoxMpilIo/RH+lhihT67/5DZJUDL6jDrC
xYig1yOW9q8CUkIMlrJSWrjxge2MHj1KBVj+l8MUQM2v8zlHVr4zo6mH8AwVwsGt5N8JJUe+CAfd
/vG38ZZlTGpyl04czNyvh51mg/zwM1CX5X2Q01je/aJUdsXlr8URt11fspJkAad/kqEjTjssPj9S
Q8TXKu3O2Rm8MYi5Vs5+jvGu5DagPmAautcqX23z6quWBdwOMkIRj9prfVzLzL2SyToZRK9uXqdZ
pYfTdn+axmkCZ8PvhXdScNP3hWrFwNGNg8YFulnNrPbLnS2cHf3T6SinPlCmheE9LgzaNq+Q0hnW
VqQRq4a+PKejSJQxrFgoZziiVnoXlTBuC6L7aOVVBU77KCIOYbzF2fgLlpilCQ1yTnJslUI6xirU
y8FzDA+rQOgzYsqgOb0pFHCImlkZN/u9Nmnqv/wynHM//CXd3KrYskPdmpCjG2JPD1sVciBqCoEg
fl+9Rduw8AboW8eeJzAW2affxj+bsTtX7BnMf1ByFscQIYeZHEDklpFNtNZzykYwfyL5mDU/1jKT
cYGdaWfKnCIjkMbcJq7GPnH18oHxCTvpRFT4ycClkN5e1Aq25e3daHvayPphblP05tHOqEEO8Tg6
XjJNEvfDGofYl+2d087W+AL3BMgNhZY4c8os+3wvlvfmg5HgUucUrHgDX0AE7BoG7OXv3yTP10Wp
i8mTxLmbeVrloKnqGDkum4FOWovW93GqZJT+rqwR6wHOxIzIThwfW0L0+nrcA1QiiS6AV/UTe/8k
xhusZGbm2uoQ85fh/v5x6BoL91HdqfU+EYDH8wB+zroi9dVUOgiSNHmJ9x/rASnZ3PCo8FAzmw0O
gU9fJ8IXs43uWouSEPTFB5JHOV60ImhizGMS0O0C9q1y2fdS+cn+X8rRP+/yH0X+fbhf8CPdTTsT
Y0Znz6a5+9o6HrnsAsS0UnAmHVankAImeNiLiHwWXvRmrI4g8DmP5TgHUEFHW4GlGz7WWO272Xcr
lF54VIKIOlVylh8LaiPY45akUoad594Xn5UnahazyNmzQD5qPQ8ICmXVu5/8hgicVgwWaW59LWIo
UyBhhtDQ/u2NrnNtoVBDtuuEok2g3AyNX9hsdlFE75bqMkhpkH61Cs/TsW+rFLtAJilcuNCrdnxE
p5ubHGoiF4VSC4BLTft87TuLlYzOuHeRnRAyWFlDAVXXv7TypYSjTkhuG6UgNged2sSmwjA2XJ7a
trPReJwImTKCDntTLMy6lIQgTMrxQywTCFNYINnS8ooZnx9uQmAgillR5r8KHUaVgJkS+pGOEXVL
gpZ6AGWY5kYJKmAkNPoLgh9gBxHNYEJKzIEFxcyBaNsKhzZuWtIrrDXTWHdQWMZzUxD/ogOLi5vJ
FFik838JLkltckn1QzvxzOixzVyAa4VaVxX0qrPArLmhcDAmRUYyYBqkej4bkAzFDu1+gcvLGVOb
QiIMksN2NAfqqECVE4OCcAvMkmNqYUCKFIwQvOJpBc0nXxDvewTEGOUti5phfsK7HAn7nB4pkeun
h8RYU5zexHPPQcu/pHz2Ozq2q17BnO9BXujylfMKUKDn4PU4wPm4RH3nP9IjLV/eCSL6Cn8tNhmP
fzzZpCHjb6S4byxE5fQgpR3o9x68aJX1XAZRXo9DK1VodANEFBp2PGtKjC5hoSxBE7pP8QTnoPMn
D35HQpyas08/xyITBNuc0XUcfae2Mr7gwLJyaKNEzdz3hzYu3+sYvyfn7t51OEuYc/vcmikNleGa
FD18MKL6tEzsKIMK3JLnH/cIdhUiVaU+xNy076cikaGDehCvaY/8YVzl01Q9Yc5a/fqyyMtUaIoO
uiBYZj1nUiJKzyRnur4h713+1rMDi9kN9x4rhIKjz1AYEhbdhCf7i/u/mydIgqf+9HWtxBPi4ig3
t5/5yO9iIzU41zHBayZrcHidBquUEf78E9Khsb4/Z3xfxJNgvghKCzeCOEFUPWFeRMRhdzw7ls/r
zx2wUu3XjKBpdkFhbLrt8HMU2q1WUgEwr1W4gee6cSj9hb+tNelUV9Rm96M0RtzWkaaDdjIOO9J7
z9EkzhR8oRwcxwam+eKuww7VVBOmuldmNWcNYo29vJtDMcsIw3wocXOIwq7OKjwMdWerQeCvPUze
4U8Lqu1I6ho9WLxEhfnoDyjW6AwD+xoWgOFuaBksFHNUNFiADJQLMDQjfq51llyICqJBKBq3Dz3P
uQVFBz01wLohHqJEe7J2xmu1R7ts/IIj32vNnhWMc8Bd5DlV6/Vt57kyjrNG2nu6BNQ4ycn8fI+S
DWz8Wu4viQEJMZAS4dXTFhMuybcqxL9QmR1J9+t88n41Fd6yxSDoLxDwd/NdFQwlWcl4dU0cPZgg
nGBRtw71xwc1vknb8jH6kM1zvOffn3Ivlz3/lwu0X6Pjxnqn3S4WXtdPL+NCwioyWFWGy2kGDQ24
1q3cOoUF4ldC2YRPOJmTjIRAz3OpmxCiu/MQTg1xs3Z3jMEOqkoRvSL7H4wRckkoJpPJE7wjkatw
IQBf5BkqPBEqLoVaSOk5ABNxUUyb8it7JgO/tYFGM86KmNzGH036zC7h1NOdD2KZXJrDtpl+4lqc
g9oFN4My90ja62gU2VzRe5g+ij5bCBDLczXvz+NOf3yg2rtVD739IMxLx7KLEpgeGSPCzXv1OJ5O
onyXt/y3j4MvgMHgGaqod41HI4YPSanP53vEOMebgxmSYdKr1ittcH38DOFGBIe++Wly2PDcuCgv
TO29F3BVb/BNQ5eNOCHIRsaj/xAgHOAIIIgQD0la7SfqLOn1ifY0K3m56OZTutpTUdukew89cBeO
KzZHQp6wS5gZshBqbF3D6QlXOEtqxNHa19TvaplzELkcAlBcQNT/j9nBGMxmhZQa6ioViUaAGwTm
1pOIn9QmYT5lkMEkvqvwgpAjjwPhuBCUoMDnjgAs10+ARbj9BCTzXQM4uFaSfweUJF5G5HjI7GDh
MQu3cWvrU2GLJhz2PnGalWrt/i0ZsSbMYYUennLNtOBoRkvL03lTWJ0wd1UglEA6q/MxnV/lbzKA
hq8ali0RfDyWID1wZlgA3dCVLdC3DiWx4CXbmtsPNeC34Vk3G0HkD3JOva63ypXBXZmYUDHIAv7N
VX7UOTZ7fU32/NPcoUCn0mVOod+I7/cNnV9ayZ0z6t5qMei3P5utD6FuMXtkxsenz/BFlUZTal3T
lctSXsIly0ftkQlrq98pNQvGJ3zkcxJwISkOHPTPPx+t/YIKcvf8rEjRdfKVqSYIm07vPQZMol1a
ozybr4ZHeZGQyuZ/WuxcrV9GBQwtsqc7zwcKpK43YlyMUoeHUgpXcH73OEyOExOzTxDCeAvqw9ex
ypIFTLGwl9Pedd29peuuhUOuX3nHuWlbuFeCtKZ7S8/yDUqBqx6oG808vhigaUD2Kd3P+DJn1lL8
vN7sBBsIk0Wb9SOoxgxNWp4lFVuqo7RHBnNawh0BkKdcJYQAOvNRIZvrR2XYefTs/+VEt5BtrmV7
wKEEfnK5MvViLGWCAi/Sn4qKdi/4ZEMD/gzBwp/a094kb07IfDa9i7c6xA6GEiUvwilYuBxLnEQu
rBXX8Z6iiFH2YT1/KMZNW/8QhJH7KB/MbwdpBJNiof6uiMg+3bhy30XMMFAMHBvjKmzxCNOTb5sJ
Ehpq+DkJmF/pzkmj+QGTsXmjE4IkBCLcNVtlTWw2UvlJdL9wUu4a4rCmKRBfdyUzpY+hJgBsr+zw
xQ9r41qcyQ4Pl5jOo/w8+RVP5O1RBHiyqsHgk7dbeTBHawqfDbItBFsBjkzn0TFooyNnRbamBecH
wrVEnW/40r9mmomYj4AAa2Tnm7wOSP5IiY7j0v2AdgcDzLSqzP1uV/5fuAggGlzqEiPbJUruCVu8
UqbGxgk8btMSRccGvnRQfI85SvQ8hnvGCzCMRjW97TYQWYqmsSbvVwuBrwlcvc8b4ZRIqqpumqN+
Q+6y0J+HJvQFXZEAWHWx7GwA+PBAAwAQumD7mtYj0iV+rZ+M41rOSDxIhY4WKxMn4YABIPJ2/syx
GgLGlwo7dixTMDQg173c9yKF9mZ6Oz2rxpWdIZEWWYmQlfpJbDBhtudPQOzLBRH4NqrwcBoqmXsg
Dg7Q5uyoz+dW3PKCHe/qQNfWip9ITGcKXXsFmuCXhDlplqSjcGXnGql/It3+55IOZalU11DNQmjZ
9UZ0JF10ENoJHSFCszugTg+TfgHAiWP2B5mmyhfJ4WC3ocHTuF+xINeXweezRD0+HlVyJDgFOsQ+
q2Wc2w9OFc24DWG9q2ekmIZoeDQ2jR6AKLvcOhRuEv/0kOh80vYpj7XGeoqM+bRmvJEGkRdP0ZA8
Tpk3SNPZ5Eb/opp9drq9NCSDrej6UJlSw87q74uMZHZzgQdgLxFQrEwriDgwhNYAjxcd+V3y78eW
xr0ibOQXqoQvUd1vRSrlEBEP2Gg2GBFnfWuNrVe42/Wkr9Cp+/e/Uybnh80kX4LSIbGt0HeoouoN
HuZ8WL+88RWzc4dCKiLFXVh7Tdtkcy5fPmemHdfwzLi5UBwZmdotyikJ9uxohBAuV0S7w4oqOj4j
FQMVHpfR55yM59fe8QZk0anb6O3Xy9OC7nPR2sY5XTWYXZvKnaNFE6Z7coS41xUxBkXxjo7aoaEV
9ZBB7WyMOdl1LbW6IjJPA2iN8RRm+nshLMdko9osr+vPM8EV+uFod+w9/skITgeorIoayqhDqoYW
Rpodjr7N+gLcFTbz0KlLNobijwjPTsKpuzQ2B3PqZvY8UO2Y4/Pz28eLFQFIBKSElckZ3uvmcNWy
i0Rl2eKI2ZwH3OClfzdv6a/F1Kclz3+njBl4OdeWhiG79crsNiBEY4l0D+Jf8KtBMIwyl8dp8Mpj
wzk44e0Kz8y9n5xptdq7r8SKuQKdmA0M/pMFBj1E9lj0TE+Z6v9omRKixtpWW4UcihrPvbxeRtjg
Kk1L2da6SRv1ajSAIwXq37b5IAvLxfVfSsLo1wlh99gItZV7HgA7+eEieQYLv9zzPJek9fgVqFzi
R51gQJNTaxqqqANbNNLknoDRKyywrCVPdWxcCKsCi4I0ivCbk8uZFFKRW/BhE4wjZ6yMhK+Qlnrt
Wo5xblCsYTeDwdDIJTE49uhmxohUjbb8PE8FvAz0LbVWr7do+5ygBOAxFJWYlJUBBLX23oYuj1ze
oasBO0sdvafrOssmyNbeFB/G9jJl+pNL0n/sGg4K8WMD7JdAesfsmqLsyjFGSdElAYxeHSMMLvyO
BZEUR2gFF4FlINAYAT8DFkeFIJAtl5jEsZUkww+8biiyEfjwoIoCe47MX/mi9TPcTOa6mdCB7WGK
SEYdeci3P89j1+V3OAxgMRhnZ50IsuZ6ZqnYX1iTn/WLNj5/bqalQM8GHszGvt/h0QMo2cPjNglw
BO7RNvb5RlZBsBssp95PKPRFgInILiJmSJgSo5rt/jiitAGvaxku0mBrHJuLb8WE6IvqD+iUurFh
iV+Ifo9qgkAOzF2n41OapS8So2EPsia4lBW7x3E0vXXJDrUdXs1GySqZjlJ4pmYA6gYCg3CiVHtx
IPz+WCG6JwAF5Hu2BIoG33i/ionRxKFBsmA0Hl7P99QiRZ+AlFk3q7omTN5VzYSsuZcApLpZbG+I
2W3BEGzF7J2BDGYVDfMm/kgPtrXotRZ8DJCNJXf8iYhsyDpF5TyGyAl+o/rKFOJJ4RIyy3SzL0qV
fty3+n4wC6TxyyVpZoJrKO1ekF9QJEKOe+0TAHQLMDbyWW1/tN9+wASV/4Ul1zHa0n634cUQGDx0
jNdOYwuHOQA215zQY/RofuF0YrJoAqtcXyWghGjiXB3fLB+KDC1VJhITV0uZhu+l3a9SygPgm1ub
AY9GCOtLC3aCaECfbNwQVfGN1JRKn9f7je5Ax+WDnpUdFWZp/Xu2AOtE0X1Wj8QYz+8rb6QKGoC+
p8evnRoOSbs+Vj+xAmavsRfT16JLJOgXTawQw1g025jfq/U/+Bvk7J0Z+FxBk6SfTd56EezD7g0z
p/6qzGZdnDKsNMX81WnCXi13n8WvY3FYMpXtd1R789eipnXGELOchhLJF5jIJwDRRubSZYjL80wI
+l2G3ip9ncB3fakZCP5Jjm8dm3YMd5pi9M5KPGiUhiHnMGUny34LVctw0m2Ottku58omvtsfucg7
6EDx6rvQDTYo1JtMWjXvKcl4OfN8d0ytUYuBZTq3tQggeop8QXu0ESpgEvX1Vy+PZrfuAH1LXYaM
om9TJPWNQI1UMUO9L1+vInm/emkUjerVFJnTgocR2tDkfruMQDFMnhgc5u9s4aMnlV9DgpkZZOH1
cX1yPNe5bf84khLfS33vrW609gOD9xBy9JwUGytJ0tOUz/jVgXk1NFW8IkGKTLmSqVirjUT25Cxt
+XW2E7SU3gICJlKKKuPENLt7thD1agtisBw5H9K5bwIzVRAwBirr1alwoO4IsMS9yNidr0mKIa3f
tsdZOVzAVSI7GVlMXFp9XaheC/4B2AXX+6Gk44OZ906z3UgpCBFvkEIASKW2u/r12PxweindT3P3
RTZ60Cg+jWbGG4D+7WZC+Rj8AjVFMRaDQDTIyOMO2OC+umY0+aUe9cZgXf6YQduT7B0H7iHK79bM
/J0I2q3bStAD2At/3MkV+MVSsMgC16nsLF8PbBGoVhFw7FHfkwZkCsDHvLtwGqAxNzRObemaI64b
TDZaLeP6q89bAe6N5C7f7AGo0cmeqQfbedriwLm591150rZbI5TJquvhSB7Xu8YSXniHGIjhiwzJ
KNmyzS9wfyT8IgyEYSzjoVUP0KR2JQo5XSFqu2+S0KE0jZuc5P+l7wDuI3H1kZM57SHd1Zlfx+qU
f25HAe9ABzMJ6e5mTkBowts6FIkC1qp9yln7rLSSGun+Ev1BeO+bSSxjw1R71Gc4hAsZA8xPYKe2
DuU5prA+iJpt9PrIpsN11Zy0Zy6xLJ71v3CO0iAaDjatjfs5yqvMX32wsCMzwh/si1O3dp469S2i
XqMEXOZW+SOkvERFpqtbDqmFT7wFMrVsLhzuvOoOYV7URYlfphXlPgrWHQzKqbvEpxJnFgxN2pmi
WJGZ3uvKVvunJYPFf8c5zH6w8w+B05zCgxRTwuCwNrES9H5Lb7gPnSmZc5EdLFCfw6kvqBwyITxO
CpsKo+o0mFOi1zyVObDRUkypjR2Y1hY7THPTV0lyins8r5ofvbxqjqpDyGIxXqQ0m4fjgoXIO+mv
R5cHlsBlJ0u+KwGYtfsLeSvuVD12m00skrrtSbcVIw0pP7VzYGqRGV+5xDDeMFUdAZpw3XjRtT25
NR6mUvEC/1Fyw6VKx4F+JCRN1MpaVkkKdPe1g4ta2Us6/oEIIHaHhAJAsJ+7Z36Nlj37hvYJ4aGN
wDBr1pPonHw8asYwQWmFb0LExX/j7MnaTAZAl2LsbCSA1R7iB7x7xDmBfWwp6GX1Q7hWPJrYW6pG
Mj/X3l6dvTfGvcrbrhAB/Bs8XaIwj88Em/QTkgDwwY7p6XwyaMUkJQpHJx25QCOOSp8muoLV7XWS
TFW3tQbrtmtcZygKFhDfsizCt+yzU5Lijk25tqCrTr61oq55T5y7mqsU4jjpkofTtqrSQqjhXw2/
r2ssrwT9xT4mNs4xEDWBmwl92h7V/4A3XkyjflvLF2GS6nqLH0VUnHAQAv7mRbCCZL3+YgDQ2OmA
BJCSLsWhS0glTzCrEtGUTbKS0J6IHOHMAgfPX+J2BKKUkKre1I+1ppzhme/oyrTBjbwTmgLlZmET
6c8KX2vKmKEwnYhiKGfJhZvjAVGge1nvdhUXPCfVSQtQNI70ryAUx6B8YDFNlsCk+lFALCg7U5/2
BI//KacD6DpY7eqmP0RBXMDaGFrrZCqLYafdVNv6dViReiVHYMiFwPx4jDNRq1Rn4hJ2bPiWPJpP
n6dQ0XaR9ugF0mrS2wrRTEm2j70KVyzBRc1UTfMIoe67BuifE8uzKckz8y2smjA4UQAIrP4TlZ4Y
0LwQ1hOZ+ndSmwZTPzLLid5KE5IybLN+WVKbwvWo7m3Ewi7It/gTdh5zdGVjfRHdFIOTcmibe7YE
PjhuTW1em5vlP6f0Ty4HilETdNXzPNGdJOdfs4MeydLnxn19hir9tsuekIY35XBfC9FEPjPTChgH
O4Th9nRJEsKuGUJ+eDxJ8fVa82np/K2x+Dxdn9CdKXDuP+JSsf+73leXuixzG6kFKqhqTBuWnmgB
aWdN873/c/lwGvZjcw5hbQlFgTckjA030sB0lXVGhyFDQpys0lxwYlU5LQI+f8lJPoVwB69gHUEN
WU+6YtkCjdzrtjfdNOibEELGBd7030+L8kx/8TY+P8WlUEyGPAynkA0bp1iVZeN90KFGzLQbNILj
CW31Li8oIWx9CMdTT62u7ysIedOuzkZmxlFtThxM4su3V9eZ8HBp872dQkDMZIPHo7muQ8GeJRoV
u6gqw2K/0PofAFFS2yRGqe0cQ6JfKx1vpNkyXU/yVZ1++6g8iDCyzmbwEkA3JuEo4/TnLVWJotsJ
kZG0ND2AKg9+uqOsYO3C+XgOHCbGCeHUgZqGBtPFtivaCgjDnPDJ63vMGOGib+RjwMNHyVVe2s8z
7LDQxN6UuEIcYBAuWIajupLdcLKzto7IZdrKhlTGKJBKKw2OFA2H5isItUJ66tDvuVavap73Qpvs
tCmIr0iVgKpKbOxpiAUIIR/mtCXdFaMhTCwytVv9qO+SBPsCsWGa9Vm0UYqWx3BZrxKbOrNet1Hs
DZJ7HD4DRKjF6wB+mB/bsYvnp/f7/6huJ6FmhKAUkb8Kz69W/jenkMkE7PKcIIQw4gxeZ+pS29XZ
wGpR49o3oLngFGVboR40njL8mshf8XkuiGpoaVMUSCMcsP1n0BAZxMzOIuxOEOZS+BvSdoogeKqW
E0N4d4VshvSmP62RoCV1e3RlBWcShCpDVvFM5g0lWBy5tyQkDBY0bzvyuGaYh/aIF537zRAAJyX2
3a9tCjVTB+4RsxVkomRqnUYwsPvmWEKmWRAq8rWf46YE0jRGPskAr526fyQmkONJeNH7xNqNFzr5
pULhfH1evCg2vB1SOUtB2nDndsH9Zx8pYUb8Ny02AwbhijSmPyPlYU98drKGV/TMXODKgTRA/3tl
isGhY7jJo537qiZgF9jn1xRs2e/DSn6YalnbhajqSIxOEMZ0Ji4d+oyvLLS+DianGsLs8b2brmXT
UheFhifGdfPBdmwS7pCTcu2f6sv7rWHgWFw/I4mpaU3DueoL9kfSazrTY6p3iGjVJ7Fg8KZ1Lnyr
LIFV9VKbS0TJzFsY71QVOWmrdBVzJr+D+01LH21kqR/pzOFHeFZ3wuGuvmQsF8xBDSSx9jlGGjY7
kdRORRWPJLdA7RXxXchLO7t0XFOhHEsIdTOHbOFLcV1pZ/0G11UYqz7guDDM+9ZNvj0kaenO2Zqy
GVsDA+8pJd3ydn41UV3vvrcMZ1akYnLsuxGXX9rkq5lMlIjCqIIGCIvPt7o20z4B46dyvDyfffPM
BwT5atQ8yOR8O5GXWfqvmNfWvP2cICAVnOeqrparpmiPdl2HdyJtieVywTF6wmkeXCyuYXKH9XYe
8GCKVtw5YDaElXeQSQE0abtKEeodgViReF26uHtfSvr8xthoSL9vEcNzaseu/xknlW7QG1Cnylsl
V2hsZPvBK5smofOdgkBp16Xn/+1nrB+LtYol+bcyo4qmFk2cQMZKw03SB5GjCvTIku7BeWqgh7f9
8UeuxbXCi5Q+tZSBfIkx6Mt46AI0jTZsjD2JfeLPW+FwFOWLkMSEsQnzFS4lIwRj3qMyV1fJkW5d
bprTufWTVqMebaSgupN5iREyn6li6Hmooq07HQtA0P4Hw5OKpCuBKcMCUgQ3jjMKxq8BDWEYd2eO
82gzLDoGb3kdxcK2aCxs1VUzkrOv78L/en1fA+8eXJ+XtQ8CJPMVcBYp3yC/CK1HUOR+WJGKK0cZ
7z1OnnrTVdLAbjoxvDdYOhGMNkjO/X6k/5SpzdvNSUX5ueg8WrgZwmKbgGAQIdrRxGUHwpStDJfr
kXZdn174mowh5fH6fiq8Ga5Iy+deZuNyx/Ij32Ww3ZY7NLmmpxDLRp7Zmq012yPDMKwQ6Wshrgr/
L3dNiDQ24AfsLbZtxkxb2n2VG8d1GccezRZHh6giLu34n0o8olwuY4iw9EyQOvixpZEEB0ryot84
berMavrRkCvm0vmUXAz8vi9SnOKizF77v1eWq5KPMXYjnVC35T56QYMGkwtmEEd6rI5mM3gRUtoH
nkOoDs+KKx1C229M+jR8CLP4A56u3P0QZGmlrIYygxc20GtjjYAvajTU2RH3DCVHeFaSGXt/XczN
+6xHQ7ateN/P3Hh///HLnlAenk33H4O5PrxjsIUV7yHN9gsUvQlyjEXeHwvIErUK1WrSsysQhzv6
khkuntJfb8Bu5iA6feotsvVuWk3KOxDI8HoRsW3J0a2LYEbVmOmHyuT183XmdHhSwjl4F79LeK7P
TWjI4TKREVY1gfabAN5VG9rtla6KZMN3SLz4ufgOUHyYFZEaDEkkLz9HZQg46fnULRcKp0xtF6xS
IGrgBktTJdr4X/GxDYWwCy2jKz7m2419x9tKAx/rH16SjveW/9pSg+GudluTbOnPmgijtl/5mKMI
57YS9GKrrxvtmVBjlxlmHn7iMvZ8uXwBmSqPmnh6QxhnJaCDy3IGpOEIQ9YRhHR5CyxgnjikYgHk
F5huZdqVf7yoBwEZ5CXUco763kYLe2G0xt680e55Rr2rVl4Wxr7e/lEMr+Kac6kBVyZ3rXOKlu8Q
SHz93xmC+QIuPmSGmLo/Y6H4TGcM8Tq8yRtr5TILCu1yE1yYg3K5F2tNjZrzbTBWBViMddnddO6v
mfFBl/OAffVs2YIkBQcCan5lX24dPoWQApGst3kAaW9imvzshGSva+2liMC499vuADOssjjSJhKU
C9yefDk8QhZRATzCiVveUTmwTNfec19eI29nkbC5tpHATiwwHD2C9JxMg9ICKmYtk50CZEOeQWwo
i//B82Vd90mk3rdOsyFPR5zC4gHeW4vLZzh4wgpa8C3+JSJX80SfYQWcrJJqhsHkWkNojFmpgJib
SAL4fcfD7wOUWZSgGqDKfh9iqsYFzfGykpbGzebp1eE3CJPno25Noxgje3dkkyWQbp0pLCXh9Ywa
tPDgJMexE14Vg+iw8qP0MZon+J/U2EOvRH14rVl068AOewK6LKKVyVXKt6evRfXyK4cqY2Wad6e8
jwNaynxE3nOnJR6qGjZrpow7+MLEa9jp5jazsOjreR8t/ABc0fP/PNqha3yfGW/I0Y1p+JW8E/Rm
VBUrOQSUFkZh7bcVqCOPdSo8IIGgqj6feyRxxOJy6Xy6c9VAbMjnlSZL4BHPj1A1l5GyN05wWpTr
ypnFyh1VnvUm26tQd9zoH/YRCFDT/N5g/AUmcyEM5LNqRtbUfZP/ZdN+wlxkZgxSD8p7Q2Kr16pc
5l14tuVMWecHdSKK3kVZkdq+1JfGNSGaTeWUMkD4XRD8JKa+pINXV77Edit6N1zOftWpoiyCRTbZ
sffri/PS62Snk76M3Bgn+krFOJ1aisXcCYrrEdH/3UUeKKfKF8RTjY9eM9PHRGwEPfRZIIGq0BxT
0vDk+rPKhq1aKKWHTlQ8FvC+BK9I3nhRa0JI5iFYo+5Lpj0DaLU3xIa7uAHa/SVPCaARuqGTm01k
3ntFqx4gl/qAQ5lAm1MgRROXT9CpKUIGfRzkVTR5yxVaNR7lkfNbjXFXu3UnbZ9msTFOh9JlwtjC
/y/K8hbRT6K8XaWvgjJxqF6TBnxnOpnMFFWiQj3cGKFJWTHi6h8HZkXpEPN1rhJibkcuR0VN5vWN
53ZNGoRQt9E3E0x6yzZHEWxIPbrQgkYSwWeABMPfNQbEEG3+DryU+DHFfTBjux9nKZoJSz22HCIV
ZfjS4Mghco80O3JQPpohEmLI2IOEX1b90er+kHt+jtV/UbT0sRYN+54Hezy6/M9bbA/l6Fos+UA2
UGEHMnMoL270l2i0riYPwlFBpW0rJ/xxBKzdzmGxFtYzJDGRYhnNic4oBOdDmqWQ//d+lhiXMklm
Zb2XeGOOZUUUBjs82v4E1qzs0fw/0jLhpbB2oIeWraRrwRDUga+u7Jlomg50wqK02XTpfzuu7+A1
bPFhStp1b9gk60f8ogyYH8ZpI+vC7j62izzVEyvbLjkhjS/w/S8H2eZB7bTY6Z9SeR5Bke0jmPL8
Z7Th5KMnI4c/pOT3OgqYYThHZOWHRyFbVwIVSQNkLeWMhToI7/hfp4GAJkW+iqqMoahUIEIDf11Y
Q6NbtBBznwvyuTt9SPnsL8dgaSdDBGCIPxeuTpdEmf23oV5uHtHvZK1T2FnKfrqLOSzkWu8JJsXR
kxP/zhAjcsdyASagRBXwpIbnrnptJd9Q59EGF34iz2bqyKegH5Qh27+oedgHKLIunzl17RMyZFfl
kTdDxR/itpzn3q4AlUqF+gniJ6BtxDIWWUm1GBtBfMfXqv6S3SwUeTA3mXwJRhq69En9a6MNm4V9
FPk+hXv1hqOaG0O7Wq6vqjGfzou3Vkic1MaAbkhDyRuI1EZ4lILnVLZCIW2/Elj70X55ixc7BY49
Ek/sIVWE3+xEUblhy5rOCxg9uUN8h3LwbTKDQElY/SonAtZQhzYypkfXWWdE/w0/64B3vPZJoltY
t3eGH905u3XyVSfwy6TZ1z762hdy/Iih0rn+N1nXsgGP1cesJ5akX1twdvoC5Mq6uLIq7L39SVa1
0ZXnQ5NxZQwr5+kWu5dq8hEOlP8jU6YLgn+yz5Nmm01HzUs+lUkXzp5nYKsssG1/1YXeEdcvmzNi
5u++p4bbO7E81PHqShKQ+qDiQMmJLy0c5XDWhSH9r+H7lhjOe+Tzb4Ly1C0DOnn8eq28tdZmTMvb
TvuK4Qk18Lj6snMjkQjcOGqelmemRBX/gHyLExhDizIGWX1U+/YMbOrSIpL0cWQzRtmkTAfSQXtW
y8Ny87w2aOqfF6H2ll7jHmNOumSdSpN/umVb5ML8Afu1H1CfQn1KXoRwqhHsyYzciRbbv3noxV1+
dfj/S/Yo9Iqq1nyo2mFpkVyNCHHHgwzbDFfyhEEZq1fsBwvxSxJyHYem0f2cZHDgiKoq7znaJzHL
v15QUNbcyuOHs2LvH5D/N4VfFKt/vyCzAxuEfGQIakv3hZgZ1YKXIfigwAUkysahVXFqblBjBd8V
ZpJW0U6pTCxC1saHXVcwAYOv1SrnYEYtC2dnDvbRuqAwljtzlj9O2H7nMgIyMCwz6uomgmp7+h7V
xAAmuLaI+SMWNZxIW60bIO73TYGk6ZDZi90U+GFzyS9jD4f4+iCphaqu2KDXhlG0MocFY1KxsS2T
kKGfz83XUPoqtDo/DZxI5yMTapfIltDUrOhwTKizEov17vcZZKQVKlDdxptRs3flEOSp988rcgmx
kqgKAsh3DDaWfiz6u6/ysOs9edk55SO0NspA0jO/hRaLXY5GRIJS30zQUrBjin4ECgOIw7w3paSk
4IzgRb49V2ia3nZ2/BfU+NtGQ7x5MIuzHdrnkbJx5KHYpV1tlXI4kzlZU2M2tUt47tdR1ImYDpzp
e/vB0WtrwFtInSZNDYKBMEABDnkis61kKs1A0KAwyGV7t5xCkW3QB2vvhcK8rg4gBQ5/GjqzLHfr
XhhbRoR6q17eZNAG4W73wLUnI6WTqPEtY5iD8+e+M5c0BZO1jSbErawU1Pnc8FeoY41oC8lJZleG
sTTcM5fGOcEGfOfEnBfjzTQL+HMusyUlG/7933UVhW6RSNL5B3CWq+4BJQNS8z9TP9cRVEJ29QS2
MZy7Sguem/mqxFob4usGaLpyauZAYPnEA6DZsxtGLtAL5EsRMYH+0lOEK2gxsn0vIWKrdDsxw8Rk
DRMXoapKyqildMIP1lmwpWlKWI2tYbW0MDm/BQugYeUtb37okzAjjQEa4XXZ7CVdP3RFpjDltVs+
XIO18z4PXvv64fV6KxA4OU+OUUoGQ2Lk7WsBiAao/rTe0p98riGq90e3+o8caO1NU1ygGjaLrp5n
wj8nz/6jpgmtUprctAjBQLncEZzpO2rmdIPJ+jeLj5RH8f/6v3Eafwfw2i43L9NL4BVeSF1MRLMm
WWA0PVkmBm5MJF5ruWanhZ3Ksopwu4/DYUmbD2sQhGKV5nTAS49V4Dw42/VIsylB3DzUbdTg4cER
kSdZx53DD4XhseBR1eyeNVCwpP6xXd9DugOn2ImLU99mUOakBvDxbwPWcdtwgIUFfFQlxbsPj+WR
vL/GvlabQ3N0Bs6WHTmRb+P49/Mh4CYwyjxJimay7rXnipzCl6Ckp9OFVrYN4br18x0B08ox4dpx
SkZuvjMuEvVnOEZOVRjD9t2ZK9G+gMp1J6PgNBrwAW+EGs/mq7buPMH1cSWNxy2vol+a8Cu8HaC0
AYy7VUP98Z1CTg3ymUCm8+nz8zbk7XSmjBVZwATSwH9j081Krc28eDjPXri/+bGhNC8ymKmXscWz
Qp6d0QRQaigwtofQUqZlBYaEYaDG0A5IYzkPGYOPmTk8MksypuY0iL0cZmR79Y5SbciMBhE+kQYZ
313Q+OHowJ+slIdx8+vz4gFihBKkUnM9WLFZJSIapO/rygpoVBlM0J2ubvlIkAiIPClDf891vN8D
+7qTS7g/4HUPc2q+/SaDEd/8D4h/8u5Hgf4WvM10Z2aSwpph8TwKP/Hh5aAWZ0+BkwwZgweG40qn
8t2e3J3jxeZUiDzMLxhwK1GwcBReOECcRizqfj+1IxlhUNEn7+UepuxHgxbWwyksnyE21bFu5p/Y
MPyBvbdAWc6CgTvVAbEDdGDFV0NPQyf/oLY+IU82ACklC04hJZGPEB+BLFvAseNbKUERi4adyGvh
zXcs9j0nHLz7pV/LBzhooQkKY++moNehTPjC2/RvE6w364rl+EqNh5AfcjQmIVMtqmvXB+W0O1Ve
+6MpklXOSRnyud4Y3nYzix2yG9V+cD4mB3Cy37qg0dLAJf9grU4wNBG9Ww7osB+rhvMD9kv7WEWI
xzYDU15t6Cq7uHFv7BoWDJPh9pXF3WzWHr97YWZ2kUwfCk8KtPGSZsVtSrDU+FwlEgTzrsi/biA5
Sq0HIv4T7vbNNZYtOsC7QlRTOK395/M8bk91pJFqjZjB6eWXnI3ucjSyERgKxpCXL7kECzSOVD9P
sU4z6kUB9h2tPQFHgFRxjeU1cbFSiqEWPLLjzqgyp5U2rCbgl4QY9ymETA6+evV5gBWalTINCQ01
SlaqZ58qoDGsq5UBtxleXBQzO8VWR6LiTeafaQRpDp1vUYYkTfwVwb1daKnL+VIAtymdPZDgRPla
hHmWZqq1KEMEsrGzodw2cvXXt0jR2C0cFQErKCu2NhWgNbvQHImxx4GitOeRRufQhmXyxTSkSrKs
S62ofVwEjLBIm1bZUPXrUnSPm9hwBhg14zj2uqdi7WZp/zIi5tAKXmJK4tf2DLiFF9yXY+SGQx1O
4WrzvvolsMT9UffNdRyRXwlfJOTruJ+X1DKT4l3QIfJk15HHZqekTNYStWeBbe5FTs24OHRN/8s9
i7aAxNeyr0MSuzKW5ccqqAIYygCrQlVzcAe2HovEKQOyDWmY7d2wplfJsBtbXZnBujVYeJE0snwd
FcrNGo7pw+qLhtozOZw493rR06e3g6Uvaiis0Y616KBQG1pZ/KL1J2z5vhmSarke0HJMpnJ28Frv
VaQL973/A+6JLbre7qdkhb+OrvFxxJFTTRnadyumDVIr6DHfUIiUiXu318pZA/Q9NuP8BR/UbJly
hUpse5P0VXCmrdvTbEeuz4Xfx8H9eTD6iGA0CN9dHAO8D2RbbaTI/YvFHRHcOqORnGpcojICrOGz
vSe0woKIxYU6GRv7SFn1d+oIgtvifZYaoFA73IdzlaHvnRl0upz3rTxZv3I2J+fz4d2oqEfVp6SC
u+nC74RUjKcd+ihen5BtRKFw9jr3LDiTHmYMWoxJLJt8qMOk46i0hrW32q/Cn6r1OsuWXiqhyIvb
urSqDSZR1afWewZwyDirU6OU3o8Q2VAZCTzPKrNgpNps9ItEH3uU6qiTbJmf3A8E1Pc4cacxCPs1
hb+ngCqwdtp0mdf4EG9Qum/IBudQf1Dcfv6YQ+0wuInY6YhM76m2it22jsINQiMtfk6weU3aoFAI
zJQcd65zp9zQ4eQZ/MjNjjNT+6knd4kSzr9fiRSLbCD3uXKvRQpLDNJuhPecn9mo0RnYBbYc9chK
t2cHC7KU75TbQh6gj0MtXEP8wgrIxawkVCqay5H9/EcWzOzL4R0NyoE1boC4jH83JuHakNTJU/hx
GTXs8MH/5giQx6xLJpn6lceOZ61VST4rqhv3j6MdAV1yYAsSWyy/EQbxErLPTr8V28V37EgAbiOf
clT/A5ul881776cA5ZH8zJUwgtuzz3YcZ0vdzHm6H/f/Av8OxOcf7NArfAMI6cTTPE72rpR766Ii
knVR+VBVK65m6PHhvWwpgyaP9Gcs2CSP6aDF4ghzD9Juou0dsg0jU7LRuBCcuSTrzJ/83p6b5NCz
4ygE4FsCVexW4asyjRGzvMptzbgXFfI2VTKP1vZO8df/uNgMedbK0/kEM6mHv18zs00MCKSYBEyc
7H3ctq4jAxawhbRa7GcxA6RQYxDW4U0W5IBfXm3LFMs3o8CAmbPG6Jbf06NsNIuRUL5sVcxfrvhG
otLyepneKQ4rkv1yUD6i23TM223dvisF2PJW4IJ2MAa4DCQp4xjJOPaz761UTu4YFsVM1hpRBO2k
8d1e1uCMax2bqRGur/ecH1Q1hrfCqCohKhHUCfepU8DhLN/Kc+U4ffWgdGt+0fzw9AV8H43T4z2D
ruoT+095zbb8ERFozdU2V34CY7cukFbK2hBbJHUM6QAhgKdPR54PDsYPhK6Kp0QetOv6k8l2lFHg
mbY/ZUdi97LToW8UulqB83Pzh3PcoFRnNph/TCCtczVtrFrUxojV2Co1oetXdN6TG2ZdsWvAJPZV
2BOuum9eD0cr28uy/nFDQ4+lmvJbek8yNpDT0Xatt4njYsbayZfbTyh8G2tUnYFEASg7mpH1PlD+
G7cJJy2cLM8Oe84H4Ue8odYuFOM0UEVXJPjes2+dHs09OONEBP9let8cDpeO2F+Nsr5WgD27sYI+
qaHZfXQzXAVjPtqA/k5flKLsmHHsru8pjT+F4yY3dpb6gg6hdFbm6DT2Lee2OlZvAaFHpmCwaJE9
K+tF2N7bDSO6NZ/5OOsBpnpOtG7/5ZA4yduVYbQ82XhK/6EhFDzugu8rtUApqeCiErIShP7S99sf
9kWDYk7KtPduZPDssiOqUTE5JjYhinSYo1MbHF49JIAIUJEsXqm1Rn7UyHu8Ex5YlKfJ06Kv3DUj
ClO040sIr93h9hJ9iYCn6/hsNzJgWb2oY8EtoapqMKGV59b9wgkHO1MMGHC7uORCIVMypB5pNN1r
qg7YIa1koIt6XtbiYlGuvYF88srLDacDyWBGWlmZ0hynw9I5EFqyocghkAAC0JlpJwue9vhxO57/
r2lK70ILvjMmIwpy6DI1kXO2YkDKbVeKr7MEMpFnIMJIpmhKlo6neOvsGScoIh4Bl0opYtLx9y4Y
XbXJs+9/EIS4zmESh45oheE/tnCyhZm9xqkQfOFhJJvYd4zChlwgi92nTy1niy6htPVrdPFv+iNX
4cPj3RgQxh5Pxikfidv2ImOlqUlGTmLqIXeoNbl3hPO8cb71y4ged09VgJ08AEJW4xI54FL8U6Oe
xk//1kb2Cy8LlI4qINm80Cuai/NRrDPYetxWRTQ4Kq6qQBOeuKvc8lkcnfbJhYfT6HKQ22pBHo2+
S6hYKNHvSevEyzDIZYFUE0b2LJzcHXhxK4RJY4AfsCYTxkug3t4NJ86DKDreMoUVSRepiv1sDiUe
GaC2Vtd2Daol6HaNUM5SCOMR11jcn8AqlCvMitJu1JJDyum1g+BTUNgJD968HKA6GWM13tXsFDDK
wAGGGF1Lh1wSgljbt3AL1LHOSrhRh+EJyfG8w0Ec1xxu9vhggYODyV3eDTuUTqAvjyHIQZ7/jWKe
73FUKHsqaX4pC+bcvXkDL5rU2gbx9EdL/QYJq8BpvzK59ukMt+W7Yf2MJaCI4Z+Lst5cWmZZApZC
e84hY3DfT5yQjAR7w/+a/uxsr7g3YlFEXO4GNeM5c687MwvP+Uzs69nbwSOLQVTOG+fEj6P+aTfU
k5oWF0zKuJj9Al9zIKG0+7zD3BtFayVNDdVazGX14XvXq4IKSnx2BE6y9grYbl8pASZPyf7TZdfk
3JjAJ14CrxIAwfH7yyRMyhxkl9Qi5x7P5whECv9vj25HIceTqbHFKylcLy5YZfdlwlpCOx7KSxq7
6LHm/aEMg+2RoCFDE5Gwmm+3oXwbQitkpXy6zMHSInxxjeg902Z5dFsRLuDrzuKEwM6KWypcUnrh
phT3jXDfDtAKoflNw/5KzoKqg9uMPAaDeV4s9pHEAkHnGBv0m51sWqIUrsH18vmC5t/I8LKmuQ8N
8+AhY3AXzxNtUESiBoVCmQiFdOjl+Frj36KCFOekdema3V8pl//EHNYSMCEr7EJ4p3HcJNkyUzRq
JHd/ncy5f8j9OabPIfEb9KER4z4a2OnkuVnjqtFCm5O6wCs5/VeqVDfaYkPp8YaXs+jn6IopvDJl
NehwW7DpgAhEBikudkiTZ5nQS3KS/i/isF+qZF03YeAIwwIXhUtJXBrbNJOFyqMjjg4FHUV+aEB6
iGddoIi9ur/eMj0kwk96z6h567KnwEIS9SaQXVFKBxkh064r1cO6LqI7mB2ty7E3oPg9HGnMm/q+
lRK3PHYsPioWqaPEQckgDNsRWGaysFKR3M7oxSUQ/CBa3Mafs7cUkkiSeVBr+ECUoe0Kcb+9xkAJ
SivrmlIzIOdsqsWKec5t69orVA+jBmgg9wHit0OJTS9SyUr8joeWk5pZnCesKfDPuWBg4d9YhuP0
VwZPRkfSl3OeW792nP5XDt21aTF+AhgrlEuNJf1BRgxLpFqJwO9WKMDsBKQ1Ri2+5TalLVBFiW+p
XMAchW2Rsw9knfxnKAonKOcmtvDMAqUBnlbGOJ/Mt1ejWHSLnZNF6Gr640721m0Nw1k5Saf8rVVF
DnTQBpwfOlaZKNnPE2l3Q5ILNbNtKLNioZmMZSCWpI35aRZP2BHQFJK5EPBFBtE9qvLTuMxb9Tgz
LH2DreqtjqYhylp7Fy4RiYjdP+OpJGsPmJJpfP0StgsQqDfshaeM0iAhdPVB51grt6S7/kzJa1z2
F08a4tiCG2Zz5M2csY/3IoH4ezW3PmZUQzyYPXWyYlIxwgfBO3lmKy5aCO4abPcbyWygch9HDbMF
gwLi+X8e0JIWW02wFROuKIveZNOYWcBOO3QFuT/rDixIesIbgtUPEy+RXmbVVZdlnqJEqxYlzXjk
X3pLtGuTCy6XjKWKiaOYNskFAsBO/vSxZNBn+yNldQ/wkr8iNeb9aCpApEjI8OMTOafaYhZcMHUu
HmaMoATvX6cjB4a7kuhoCea8fc7olu+IRTw2vQNuFwB39+NhBZSiDPED/e78bS0eg75gPpOY8Ni4
31tae/UNxTuxSQIHh9oonmSDSFlICqEk6SL/VcYnse5AnkTHgvprO3m1RRKCzkCBQf/xMUafaJRQ
8COd1ZYGcA06lhA6xYmfRZbwIJ49jXfvfmTllI7rylP1Q5Rq1IMkKkYp1mE3i0PNG2I+POm4UQ3z
hNlL6B78bzr/A/youcv4KRSAepfY3mw7bJoKFRrDVcJqmoirsnCFRPAglxnCCZJ4m0TJQ9VR8Ofx
1lX05+gcI5ZKR+zuUryvFVaQzM6XMkYjtIUYSBBZrP8C7nZgrgzNMs7jdWctjhFCNDSI4Dftp6Ii
y7x7aXTwfS+WoDyEd+0A2K39WOgJw5LRYwOM2okrRQVs7mI8fat8SEOn7UdfUVMnU24BMXMQzCcu
rncZmKFo4T5L1NP9k3JD3uD35vMOn7Q4nNFUWVU+WKHga4Ifb3uEAUDMcXaKCtYXO0iH/idzbMOB
WLyTr/60psheXkqVBvlILkknjbAtJIYmruMPpUF/iGzv0F+RLWYxW2r8e1NG2VMkSswkw53BTcqf
VXCdMNJot9ZruariseFvH4FQP84ye4lkUPQsnP1pYpQX1XxenyOBwEHAUdVoyb8hTpOx6LvLO8Zj
WREzweSvbhFoOzj18cbh/otoe2/7zmVnkNe3kHk9Y657pUDwwUfg71X3y/73F+zuCNl1JEO4oCtP
f4LMi0iZ2jukoW1sNH9jEVjMayV1foE9xa24RG7a2g/eerxL6V7lLhOekOJtdP0MU2hN7IQFwe6r
UwspAsYmd9BeOdXfJkJ45eqSoU/hh3fas8a3fzUj7OnBmOO9ACQUX7E/cTokG7J0QNaonPLDBDNv
gAPXT3ebzVsIGSlIRwn88EpOTtTkpBVx6h4OjaixvhRzarAZ9FJ30FPgc9LOX7LXF+zzLJoOWpSW
bn3LffoY4cqJlRzhkkLu/Gae+VZhyW5rnbd8yzEDLKyZ0JZkaVBKcdG9bdJeAExRRUhT9jnt/61O
3xWZLd+g2UElVGizRBJyziECwuV2/yi5OFVSZ/xYvd7BXxy8Gs8ffe2AQOKqMKzj44kj19AGlEEX
4ijWLqXE/ULkvTx++1pD/79SC693RGZ+3RmNY1d9aLjYdMuFX2FFNCsJuP4wLvVYHETEk29ASzz9
34VgoscUWtE7ASmFXLQ7Ma8NAo714HjjfSKdFzCwO0JPH6PSJQysaD3FuMv74RQDvPEK3wMiL7wX
1XfeEN04/UcZjv5yWUewzEp9AM3KBuEnRZCUKhtlibJRNg88gPAR8vyU7JpCAEMjAZnBTYu3MYu3
dc/MkWgDJrBtkFHq7+CMgn6BUOdM1rQdmbWFVcggcGwyztCsdkAq5zkpHJHe9qJZewP+9KeeHuc1
GGn7yucBUp4kLfq8+6jQv3UWlhXEgMg+575CSNQHK6CybyHsX60KaFesoTYJWggU5bcjQ56B0cJh
yWiF9agQDQcxO7ZVA2CoJ8vS9VEIIb2u/l9hOa31euBi/8MDcaiHLNAek6Hq8SSkh9jyPXPcRNAu
8NyZ7banrY/2yVnexmUSNEyqRG8wyZx8VMFh7cJ7DPdKuZTr2xRxYvYEMOURuMSZjGvXF6HLLHZI
GFq4QSOTtsZAva3sz2Td/O/xQy12GnJc17dK1SYsQrK46GePu8USjxfOWo6c+bXS7p4M4bRwFx8K
JNfL1mIGW0gnlNeJSTmeVfLTIEWPqCIKiKZ58nzE8BweQSpLAqN7jQMC584aJq8fd9Qa3fdZsaAR
H8upTYtJi0UBEpJlEtZWg6VtZU5PGP1ScUzeM7ksue3Sdk431K965dk2wJ8jRtk59ekudF9MoMHT
cLqO9IHTDAtcFKQuEoPIp1Vi5mcgx4mTVGbe2+YJ99yj0zY2H2o9oMGrE+dr1ul2mm9FakHd0jIj
pD/N5XS9Jgu95mbn0v57Wp3PyI0jQ1bfXNWI7bGHDzpnyhjVex609CKEvayjEhB6p+BWLgDrN/Rz
vnQnphLDS5EITii6uBED8nheWoxHpLDtZBi5Zs8bsqiNeOXO3Kqnr66IpL3rN8A2FXPqNJCBKVA4
igtsTZpXGpYIraGa2RtZHPYY6tZtNpnxwdtnsoV0Te9b4JEE+rGvWGYBpbEREB0yQ840OzQqrc8V
ONCItevfBLoVNz7BWzVZQiY2CWprFrLvPbS7h0cVpxBE6LwMXgP+kmqyFf1sYtykHCu6zHwZI/NG
zvmncmKvD2STcq5l4kAQ8Bd05g4S2oignxNyOuCdZ/rPejdFc3PRonAd4qmyBT265yBVgF7EC74B
69XaJaKgA936CWu/jJTnFYAOq8Z7kWx9f61H6Wb7S/NoW6ef7kpH7Fe7e3jZmTnEdJadZK8yK2TD
h79ehAwDJTtKmKivIKsw6SLf2iM6Lh7iP0wWpOXKckGJkaSsO9c0/s6kGXPvGx5IHKnfnjSsKWR+
Wxv4N7bOWslu6ykP8xrtHQZoi4EGtql6Rreb0abRHb1gCvH4njIj6IJhT7VRInsr7iMUkCKEw389
Vtiwm5V+YLcCnvXhu0eFzUBq4WhM6IRvZcLEGg31dP33nR+Hm0sBpn45BAutKlp2uSlLozYF69O8
2sc1dSvTvfXStRTXMPbZ5IB7YLDAUGgOhyTXIMHOws2ui1qhdHmwbfLaIMviX9DA18TCcUmamrql
snf1QF2b+2MJf9sJBVEtVQPqcwUFWQCHGUOwS+AcAwa+RQvXm/C/P2kkEqiK6Eym1S41TG3Yhe4a
2Bz5p6h/5SuqnX0LuQs6XG0fYV+bWWt3ClN4i3QL1Z1A1MtkdMbaM/SkwnXJ8NrzuJxJVxcylmFZ
nhaAq6OiKNM6UrzuFQPsTJ4YDpNC47XA7PXrPxxhNTcvaipe1KzKG5JYwce4HX1NUGFTpM6gefcR
Mm0Q0x2yMlXbProq7cSyICLxZL/UXFD2qiMsoZ8K7U+P2XHKqsa3GUS1ID55PzeEO1CjwT8dxpDu
Q4jevRMyaqbbEqMcL+bfaWscBgPBfIHDewV9iyXA8jmtGq7d77nD3XQOxWLzOQdMax4fqhLPcmAk
AqlP7uOiAwa91ChTCGVxGz01xENtSddg6RCeUgjGgGnXCMYBBRZLtkQrjU2DxsbYYPWQPH03ztGE
dg9AydD32tJlA1/upNlOA01+K2/zzicTpa+5fdBLsuEsDVMddSy5SjrDNKE9+xYLDINzxy+Wfth3
EduDdNEVIE4unDEnndxYMO0UhTthVzLve6DBx9Im7aZ9IDNE22e3d4VtJYFfAzLN4SKJ3kuxsZN6
1h5zSvKFkoS/jkqr65NCf96S9O32PiDfmXFsPnUU8MLKX2Mar8EDaXOFWiunWenY2VdTvSbTrO4X
isvwP2KwWECF9mkW3cS7AhBEWEHdmPKPd5ZW9rAWT41x82ytFo5sLdTqZFWRBvKwSsTLbwk3GGlV
kqgQrk5GS9LqfdV3oT11U3e/9FwcB5ZPgnC2edWt9oG38oBjCGzhcmb1P6BaJFjUMAqEs3npWrsN
obA4+bBsh7GtELXHdEBK/9unrXtIEIy7y60Oi5zpk9yDy9oBfM4jtskrZFDDtvehSrffsWw0vFR7
ju/r8bGznwJ5kxuDH55SRI0bwszuN20ZPkqo8Fe1y3020+ulCFsRFO/2lB5DOWOjtqoMyfohY3YZ
gFAtC8/2fsqYBW0oa4Dp0iy8AfJV2nAmGCIzNzOvq5ZslM5yeZJ6F12cMcvoDPS6oXcZZ7AFhJEs
L/bOKnE213lgVCoN+XgK1chrY7ThD/Ip4nW1iblTUilZDuRjdrUhoRoNvkplCvR62tI4pYqw2LQ+
JYsP7qX4VoZ6VWHK3BObRbtcGO3K937i1NXxD4p47TSxIUj2EEBGpfoKu3+UPJ3ehzJYlSn1AXUb
Ywi0S98FYq0NbHk8WDcLcuzZqDJ925Yd5bpSB+JfE17WXtEcnZBg3OH5Tv8nbsVjP0DCzM6Z7Gee
yTNzp3EnTpmwIKgOtsaAjbTsjsSajw8G5VJjX2ARVjlmYfOFXTF1pJXODcoW8X8kHfxEejIzIKV5
BZhGO57zZhNV6/IHiEcHgw7k4BvQKtTHOuZh2HTDefit9ogYTiXl3QF/AHVdSruGw6sH4WIUvT+C
sIKwxs5rQIdWVGh59QV4H/wEQrYFFdC/8rXG/UVVPO7yX6R95vsxf0OwCLZnVFJGNnGQ12LBxHxu
ibUu2oz22zj4vn00GDsgkcLrO48jX5Iv8kvs4w2dWd7qcoOOok5tPtK7G1Bo7iWAx1Y7ay4mSnOu
r1PRlU8wD5gSmnyR/uAf1b4pZI73wDWEj3TRK8+zXAF/84Tynbkt1ydZymiQY5beooJbKwClBJBs
ZpdQ0SbDZ3WY0xO+ZsGfZzgcX/PcZLzFRVq07orqJXsIBi6py7gEVJ/ApgCI0ykNnDB+SmptxKeA
9bg6wSpAm2BMS0jn8PTGiyObOpMMztx+RZoV/EcnsRHxj1vbe0vNsT3iGdhSZE6j1ahathFTAkJw
QuqMypPFnSJ1PzHH/YNJuKflN1SbQk2bFoudIceOeNlJ8Q7MjbhyrJMw+U2L7obcMtSRWuJB/t9f
qtkArHNQ4pUEtdbuEWIJMRv+7XtZtezrDB4C1d4t1bAulJ+IkLy1Cn6anJ/QFLQ6O7p0gEvX2dYm
ZJTF1B+3PUBXVgmJTpwek2Do1iBJu4LNW8fGf8wtS6hckObWZ1euz/rIVl/oNUab6PS4f6aKL2VJ
v6ux0k6HjRVd/m4gbSQveswAWMkMgX9LwxRDNeagZpq0F34dKDXHSWgBjBCeFcZ8KoTWdCUXCOFt
e740K91IcnH/XvmHjVjAQC7DWsNzKZ6rdlK/V8/m2ZsCYeRFIJGsXeffLqfG6UyEpZfUytUUunA8
B552/976SPZpdCOpXcrkRZmGd8NznN3bY1K+SArCs/2Scgu5B/0lVf4Vw4iccudrfpROnCKZ5EdT
WN+UhabUyMQm7vjabBtGM6usiWZTnX+AOnoyX5IOpffhv+fRMg9co+oOySJzD1QIeov9Jesz5rW/
/NSJHkCJcRpH05ofdp4K9bCyVS1rJJxqGh5Tf60sZ463oc1e04pjV7Q7lVcumJCdHXhiet8uv6nq
0nFX8JB0WxxoAoWi6wK5dnu1k6BIKm+PCTsZqzpB4M4FFBv6ZFkqiWcuwM2cJoe9MFoj/Y5FDcUy
DZiccNsX6eRXFVlQDIS8s+5lPO95UMqBvZl5cL9yo4je3j/+RIO+xh3MjYa157+V8Qno4ewwbgzv
hhM6YB/arbJp4aGBYRUU6dizdbUJH0Bb5FgQ0nYbMTTFRyoNKjnXG20kCvO5XpVgI7ksvlIodlsj
scYTE4THDqt9JWfGlZBLd6/Pdnh51bM1NewFgaqVGkG5xSwb/XBhaQ7RvcisICXC7U8gTgqDx7pb
uFsTtQX6oe0eCKeMP/MpbemcX1erLD03mtzAwbaVaBiVycqwQV//LvK5KF6pDJbzw+Zk1ilhcru2
BvF5n7meaS70ihKl4Q9nSr8jh54JouiR2hZGoQ75Xq4Y4/F/uwYoiLnpowDpEY3rESgktvOJDYGJ
vQSf0nBOZUPa9z48Y9MmKWJdWL3ypeQRphYJ10XfM5c1Akh/BpSdLRi+6xZv2ye+ZNBETz4lIsUM
QAzLywa96w3W9V8ADUzvZekLICPj2ZR44EFxUkPJtvyYVQkqsYekhNa46r5ONBPgRCrwuYMAcgTf
+R7q1ppmrBrsJ+6pccg4B1MzvAVJHiwjrrvd8rOcF1A7WR7afEoyF7RexmD+6qKtGG5QJVpEHdRT
aPZVSg71YtpdZAJ5tsVKYcl5wZaSs9L/N+d/6HMAwMxPCrfyQ+41DRQUoPFmwtQZwcz+6gBhelFq
bZStuTwPm8Me5WJRBl9RO8CyqHnRkI1gwf1ia7NhGtqpoCW0y5vGb4WniDw6SQjaY5Agwem/yYOm
iR3Ylqt4VuLGsLEtel2yb7FYZpYlCtz3U8nO2c6QZlaDBuxFzFjZM1z/VCJqSI5itsFwZtSRYAwV
HgGKqiruRjJskuKUSzlO+pGqk0DlsGxESFHPW7rZbAgwArD56ePaBG4JQRlehJskFDI+CmHvGOSv
8kIicULP66nWv2Lj8B6tK5GlO82ha1925pcXhakBjz5bLKiJjbjlTH2WiewEyJKbESvNoQY5Xq0R
s50QKb5OT4dpDXAi/02RoEl3wNPM+Qaqyk0G1KA3525gaGNakc0Sx3G5bIv0yJlcfqVeWEDdy9Jk
U31hk42EKUTDG9wkK61uX0VR1bJbbJn4AeD/i8wimF8eQkQ5hTqeYYMWBw3RMpKZSJSgrvemyBmB
A2feSkcQCwp3CQ5ZnDrfeKxpiTYKVeMMLuCFqSyH0L0H04CZ0mOCNOy79fbuDqtomtqdARo9UE0h
HSqkzcAvPnZJXGnECmRicUjqDXKZ0nxQGPM4+3WDXuEr/hc7mPHC7h+6QzLKedRY9FpiPQFKEExK
0oxBp3+e8UW/VFuRMiaazGHMWenC7u3Ao/0vQgdakiGlND8YVzSS9DR3q/exIwqBjqZIcTU5jhpT
BkaI7/BSi+VvIo7hnR1MLHTb5PuoLTYOdrOw0XFlJ2eGW+bxcWBbDsQfgzxKO2VMJT1heOVKOmb4
cbMc9IURPpLJLWD+MjYVosv5NMn/i93g3IwXXvgIFCNgHBBZHt7Qfneyzca0VPwO5lE5kK8bb4Kd
eUSykOZMwgxFRZTUVM6lJ4tOf7IHcLJNpE9s4Buz2cvF0ET7WfdKTY317OFQFqyItyatcKxWKv5F
xoIKQkmVz9UAj3V55AVqaI887yUfgT/BQXtnVD2CTlTToqC+2esvK6Xs58nsgIIYPB9++iEFjaMZ
dG0Teoll+dBRQAchAbr5mhFv706pfj0LoaQvkyKMu959u6z3shLe6irwM27mpgyap9r7T0JbABPW
vJ7dxdnEDd/YnetG3tVB+28DOCxHIPBwsVAK8k1se6TngfOGwLRfcz5S3itD+euCQ5LKIM3K3w+I
hn5yysiT1Q/X5Pt4TwBFpzHFYB4HdbtNdPKtehenESZPYSGTv1QlWSXhKK7faY+VimyMY64S/1My
wpDwQk/3jc0q3AAgSwOTEJkk287sEfyYsWIqpYzgMIFFF5lTKHUxePv+fGO8ikQVuI3p7JzV/K9V
8hNFW2VbQDTMt7ze8N8WureLsmExFNwElwz9urRR3N7PKao+LAAaJiSRDdx5KwIhrYdxNMavWd1s
7zsfmrNhn1EBbgYCxf7IkZfOEgs4Xt3AT+eJdwMSwTRQrJW1uPqZMXWT/yywvkYC842Ux8jzuE5q
DXKXOIPoTChXttJ4qoHwLscT5c6Yu5zO4npOGcYEU3fTTx18BsUVRtAi10DgAx+MnhRhfH9fRvHc
cT2Hj52xtFvtE05i7XP9PkgAIngEBEts+Z5toziILTTB/S9DHwy44eexDGc8n3RoJPti2oHe82NV
PKFbtFvifK3ZuSFKdsxdSJlS0rJrTFOFU1Zscq6pwwQEhRSoGjIOVRQGLDXSHx2QC7g/yYWatxw/
Js0qOruuZ6lSo/dUAKqR8p6TncXxIWAyyujC9Nz0xg2DmOTYarItRbjabjfZu1TJ1uyfA/jnXEA0
P80xgJiQQw5AsxpMrsG0/m7fXipxEVX6ivilbwdkLW3CiWdOpL3YoS0LOJzJpk11k37YRRiJvnmi
ZHIkrh1kJsTcPVVjkMMhvceozDqGH22UXkXsc8xGgGHprOdjyNtpUQMVHz7xO6RRTPLI9Tm0AJ8I
GJAO6tYHUFme4YcqzMY1b7ysrP6H+4enCzw5pztkPk9Ak+zzIrAYk28/buQXZpLZ77jYeKePLiW5
zdOSPHPtuNpYOKZVTa1OILFVXZmUrlNFskjPgljVK7xMJnVl2++WIS07IF5yAAIXdeJT/O9d8COE
sn8SBpUyCDpT2yl5mxtxsckkinT9rMH4eWUmXiAOpLKVHiY9qmjDYxpHwOLlKuQxvHDUHnaW9d7J
C/SXrBHY7PIyklFSbNsb0Vg4/LziFTcUhz4q3xYNJZ5SR+Mc+s8yqWSSftityAa1cZN3/Clu5muc
/UdcsAlg8SVrds38tCm+U3ILFoLejvzpDUx/KOQvH8dgSy66faRixKoqWvvr6dwhynPDGqlFoPxp
lIhtjCgonvsmySHWnZjpKJv3ogKTwWim1+Je6LMdl/MsJoVJrbd26ZKvB4sK6OsejEDdcXeHYxk2
f1Bh/fiXY6fs3gYp9q41UEKh/YaXxRcLYZW7vvDQa6zWLoo4EE57o7hMvuiH2Np+2lAmhmCNq8/T
GokNT1Q8dx4gYYdWufERMbPEGX+dCXmi5wrD73/dlkd9vzl9hu18dXkvsPnGfiJ10es+SRhzJiVu
vyC8BSG9oYzQmOhg6kLU5KQD0jox7em5lS5/sLsf+CszrTnpMCdYRllDN7PLhCZSgezCiq1tKtZD
Kwdqjbsr6T+pLeVQ3HIWfWbXydAkmq7Kgu8e5TOfBq37mik3ax4mV3q+7PxXWPF7UjgYxTo8OPhe
6dlGRkure19LRYO2RpU/XgpcaQssKFpddWp/9Y83kAmHcM3JyiBvtotomXRGs5NHsVORcQGpZq3F
ukTpKQTogQKurQY1P/fq5tW5TZ+Rif+MqjErAYULzkQXZlJsK0v8AgDY12vTNmMstdxvQUpxvgu9
dLkea0K+k/w0vGktB5LnMOCfg5Tdw/mxxZPlAOBJfL29IDzz87itoctS/QUx7NrsPDX08N1aiKXI
Chttviq5bXG3Q8pGc6bl0FgVPcea39fqQIE1dXL9UKOD7F1X67TYx7Xj9rDht9eFsm/xoRNJdEK2
qUzrNsg/PE/qbR37frvBZb+34MWmg7v60kQjUz2H+fk3mzKApQOBCu64KUOoBEP+SEBAuNnYHT9A
BtoKlSIBIUkc9vxIlyaOuxMITy358qkuHaV13nUBzoPMb5AFc6l3W1AtiF0EMXRejeHUOCMZLOeI
1sGJqpryVhQSaBMX3koroj9rmARKm7LECyM//kSARvLAfk3F40fZZp/AL81UUlehDskqai/Xv63C
DAZDxdTLTpYz8vj9AJanKWf4XulPS10srOO2vpAZRqr0OgJ9CovIgF+DYLPqiG4+FL0QA/88aBkT
sKqfIuEH/I8AbY3tJ17RXKT2gh3pvaVWl55iMpv65kzya/5RZ9w+ms7tsPUXWQwSHcrd+K3Dh8LM
klf3VcK85758fBBUgnyAuf469npv/5he7spzQRD1xYCO4oVjFcm+cks7eMnUbVigDVkds/BRMp02
ogjT8GgxVhw9XNAMtbbf3fYikJqP4LiRG3xMii68NxZa4RRQ8KsIjdO01yH7bH6+7BVFmkRC0v37
8aASak9T05qUkvD7dqxLhenZlzN5dsSVf19z1Czp/N2sqNc8pPIktiRLuWfFIkkK+YKgglBsiN+6
lYkXuNFXP7oRNN7XVocGrafuxDqiZN9EGfQpZGvimY3CTKmXMyG+2rT5YFUNKJ1eGgO18INH7rIn
kMk/35jcyPkgq8/sNExo4peYpovpr4iCkeMA+zd75UnGzTiJXweYtnRjJPWxtWsqecwBmj2V0TC2
fS2vgXCFGoEeMYmQ9TFUczf7/uWn2aCM1tEzDnw4Bx/rOkCzA7B2FI21m3QljLH3L+wakWaTrqyH
huIy52QAW3SgtYNfFBgSTgL9YTYt71rL6/r+FL+6b/5eWU/aVr/Nk9FBPdx3gpnYB3w7AZ0pZDd8
czl5Kj/M0Cxwsqp9eGXKdx4EiGEfT7Uu8fHFZgJsCYJr1BIB9EhzkoD+PO+t80BLkbmWUxL57UBA
MaV8XoCLfl3h8awdsCFqpM4R9hi+UIwESIEVShL1avajPdVh2LeIn6n4ZMWtYMUvDmNUadtxt0vD
a8bbmRnObQzHFfg+6Pnj1r8a4rQOAZLmmUFxR2AEzaGLK33PaAshcnczRDRDGfzJnGIEG0oTp7nG
v3GavJK7n11cZKxekogKaCB5u2EwMCMhp9CIIYAsKKrU2KKVj5iPdMRmWtOLigKSbXBmnnlOZQSm
PycWgZ/z9BGF6qE+c/xh7YppbOqJvJ0PcF9coKZjn9RaA06IBNZ/SyvtPehRiuwFMoFtsEAsTod6
wdNc3E7m4vbyCkWCtMyuB4L+kivAF9tSY0B4Oirwm3DbqA0OYzJBn6sTOPrrGM/byNNMdWGiza24
vVc7QOXrGIrQY4bou+iNDf6oNS/RKa3Y7ZBnvT3+fwKhtI2y7SX2g7X7HKb3XXdawlAfyNme9DsA
OvBvNMeWhn6zNNuz83LGxvvEs7Ns+x7nVGzhUzDXquH4sZsoCPb751RBWInGuqBW+1U3IS1qVia1
f7cx1xFmElZkHTsheSOFhv9sRa2jJAmOBC5BGvD+eD8HbGTycjzBNKz/aiDMOeleOkhDNjoFVnOv
C7PPMGZhAbPZrkR9kDI/Zx4MN0KQrF3cp+a6V6RUvbNJzlW86lMjVxXb8DIqV5W+NFIQ8FsYOYVG
C08xiSlC/acleTI0yGjAnC6zrGuklCZ0tbryv2rpSRJanVmVFoqohSI5ajbkNcRis+ZsVU7NHnvg
h+/PrRAnlGKtg8Fb37i17gW9aq9D5FcQGMEjUfH85jb7NzV9K8PhPpqbXXkrjuhq3VCr1GCtyh8S
PZO596Xcvtc0B5tzDIcPRcWPcOro/w0OsxppPDW9kUWK2N0zSvxcaGrUn54cJKUGzt3IxsbB8Xy2
N8ziuSny+HAMzmA9/nrkJSLgPV8Iqf1BQqb+iRdbdZNz1ouy5yB69MzpCLOq0OpCeZUYDKMQ9Ur4
t3Hy77m1Syr6wy2+t2OllN5ePRGW8f5gJwn8oeKMH/4tU/FHZFc6BFtp4PCrD/pBQdSpBoBYvlOS
lSTyI/bdNcaynrTqz8XRNk6MWrPkWIBrykjK4Nm0sXOSxsq/H4nuTe0SXhr3nyvTDYT2HpAA9t1E
LNhzYbe+MjyRhURkHFG238erglIevS4EClyNYlafsJbiUG7/wvLKAWJvcIDgLcb3yGvc/yBKSLfm
zkd1kF/LMicl6QMKGTE6MJV8u+8kcFQ1pib/WMjl8abxWINxl9YbTaZl9bdVBSoc3zKTkV5yVFLD
i7MvOiApjseqMM9hs8nIIIRYSRfIgX3ibgwq7bfQ1oO5y6cxhfmfSar6ywit2kMt+brQoe0Su4U3
iW3vxbvDv59QKKtqyB/ikKGp1e4wBKlY88+3DRrGf5V8lAeQ9/sP29sgIe9bAv1tkmwEJnqXot89
cXoja/tooHMKtQ1fBavobk68qTrEuzRqaQj5eOn6n6VCLUyNfcYBiW0e2Fky1aI5T8x6PKZQtT1o
ooPg//H1ocrRQtRKDYLY/svw2gm6zSGL+jMTxu0sZhRBRROXhcT09AueLNup4oXUSsxZnz9rg2vp
R7Hjq7EbL8m1WHsRUfw28SRpWA6zYBNe6P+VNOdmyQPQSbTC5QdjzIudL6CRD99htMZNzAp7r3yw
OFoeJ0pg47wytdsG3CT7mDA4te3NWV4QokJZai45L6Rx6eXWdL4nfR+0TyaMndZtZsiqMVOLYUFW
trMhjz5ciKQSu+Ug5xdAwCeo0rKgj9xod9YOZ7/7eBvC4MorxT3MBjLLAD5ZUUmsa5PW3YXzoUcN
Xp9HdTTtpzOFCP0ag/pGwpM7StpX6GoFshpxFXWHu/agmQVq5d8iymSTyBPedecgAw+UCvLmzWGN
91Pc1xvVOz6FY1TkocuzRKPz4rynG448WeQjOgaK9bVBjov1HHNQwQT08LzMP1ZpWN3RVmFAEq+A
ObNfZQX3WDBUGIIg8YQFRLgD8LRVefS94nLkO6tKFFRAucL/p1hM7OF2yU8cev3eubuKadgJQJl3
OfOPkK/ZNfeO0Ge5v222Q7HOOmLNw7kl8BejRMtB1h09GAMZcNwwpb63Sz598E/n+v3HedQkNQaC
qu7i0VJe1i7iZrhhIbr1iT0raBMZUhUfhoVeXyKSVwBEEwNITbx7Ru/iunMRLrSrnij265hTrMnk
NTmfnFTXMMBlRHKdtFtpMO4muDouDeyqWBDvAegSC2A7duMrt33l6NssF/Qm46RPMPT16ctrELF6
Np9bBdLDdQK0HdP08DzvNwi9a8LhOBkCZO7hwn+qgPGIXxc5wWKLwaeINvpyhqx3GqQc6e6ar1iU
1Bbfs26BsN0Djs55agMSUhcsbXgnRRlIbSDl8Fij29uYhMcAe4wLjrNOEgqjxF1EL9Zh7p24bNNL
HK435kR3THCjyIRIc8dqlKGMSSgu1YokFj7QZZyKBy/0NRhTU/JWfUpW2DUFBAXT5LCRrccbJVtg
UvCvW1h6s4Nzs9A+RQarnzb4jJkqSTqWvXIJD//czrTR0s3+rPl2SjkJSvi7OtL8rtRBy04ND3YF
ekXcLHwWswtsTo983vKhKl3/nMfq60kYJpPyxl8OfVIvGcryXe7FWlgWSrOdpgtVxfXfvIi0Lw2w
LavvN60B9Uh7Sw9FPYF9z8mxmGTVG4Agj1WrEQ2MPqAM1ilxFLX39T3VStG1hfULtDasBLDXZiMZ
z8AztkwOAXLE1UV6Y0UsfLLQaHCbtmS5wSrYE6SUOL3yarBonJtfGuDdScVakK8CGyeSGkfUc9wa
+GI186N/6/QHXksMLjlBMC5bgWmymsOhaqYefQTAtf1eIAiYtBOaJ550cf4q1qd2mDNHLo1FI11D
GdXqdBiyqWnq3yrjUntQlFi39acM6qWPkr+rxbw+mUuvfmRuCh5tQrlhmRvZzNPVyF1czGxDV8pF
t2aZy7oaK6088T1f5GD0pUdUXRMKAFIbKkMYyffT+UrRy0rz3Cgv6BuhOQxUzg2Qkl+Bbl/cfXXy
GPTmPR2Mo270b8fOqpD6766NlIU425d5XaRqShDk18Mj3du4MeWShrysIwdqaNGEE+LKoKoO4U1v
V5zLkSLYGhWQHXhlvIQ7sZIw1Iqb9gLAmbsDe6UgYU1DeC/q60cFYJomz8L6xxJidyhvMI6vlHsr
Ij8aiPBpuhWZaBeVkSFT6cIgyh4whQ3p6SkwnUXZnpRKWmnM+QJD+7TrkbdNPuEz1tYs9Oo9aFZa
hSd/6vitDPxkRbGhztHETvQKkahQz8+QJXb51ZYNAUznXyzMHyymQvnAEcMktjv9ZqMeldpk1utN
ul7RylbQmsQaZxSL6woZD8+hGthAp4CN3KigyEhwvkj4gPySBt/FzNWPJHf2XAQiI2fpLsVios2V
ycWSqOv/8csR3p5F/WtuN6PR29/JwxKQAbmiAsF5pB7sjtjU06BRVGfNlnxXlIZ5D0mYuwlvTjrN
4ZnQNT5jjhw/hiJkZC6nzEgBvFX7aYI900Zuz+J4WVszPaIiSHMPGCd4ct3P2MIs7WgGXN7O7cPX
BTYvvvsjySNWh+T3zeu1nBq3IQ9dpe7B51XYXH9f/oR0N6K94RQ8HITfVeYqS9UBjy3CiM91uCVh
XCFe9IkF2GVR9qc/4cpgCjC49kgaD6jp+YPdaU3rsyhulBFtZ26rClb3esatTTfj+g5cusMs08EY
3Iea82lPahpKr/9Ut2EY69ZGEw4XwtN9hHihqjO4yVy1tCCVTBMLlD5Tx1nPW8IFbdpb5JDmUuCF
ml1g1zchPqyxMUK9NOGUMRmMzi00WmmEV6BKjHnRXL75c372n+iIY7KA9vynfRXtEGAryL2b8YeT
XoZDcnv+tF+9oA00fe2I4ipMglwdq4lmbTtCzsoMrVxAKkrYW4pxP/FFxd4ycfZwP/nhImgFOCPJ
JtAWty9F3J93KBtrnXAxvrsJaiRVvEgH/aQi9lLfiutRl6EnlsUH2YRuVqmd+VWjC4tUNr4j+yl3
yRWhcR9b5Xl/C3DnQ4l34FwoDoup+ZUwSokpMetu3m1hF3rgPK/VfseW8pvTFLg7of4wECoH4XZr
KJZsXzy5xWI+uLBQm8yXDPmsm2nWlBkdxt+CXQ00lLAkPi6rV8j0acEdbLoaWf+GKEc48rMstTKw
1y4/9BeQm3Y29XU3H9mdEoqyeAexzNzi/cUHvipOk8rEYkWk0i4ZolPiyXq0veTU1Tqoa3rqMqZD
/sfoPVemBmvwGotf+NLjTCJBSSakxNGMgJAZy5CAWyvcvpZoV+TGW0k1rdAYGzdt1IkGXj6VLTdA
h4R6dr2VwVOSJiIqy6HxCvHWYLaCy3mvIvfP24CrQGOFTt/ebL1Icad2UdxBmciONofsE5FG3Dbw
nHq3Fiaf0JI2eg/3IA/AX8ylYcOjLA+zXQmxtc0cz3HeS3hNs7NXfQX4/92Fd5nrpXWffFVea49c
8Frpe0sXk+U11p1OEqbNME8nk537c9+a8LbU9J3rK6N2DyrjtSi/UN15yIM4gU8bPZO1SwfyquLI
3JcBMrqwhweMBwb4sRb122dRW8AyryameGPJp3Y37PDsg4ThEILvQJMFD3gRe/tUDGFOovWMBv6+
KfBHfsPxtukjEglB0UYoaKYbCX25IZVzAACiAzaZZoi6msElwT14ACToeialU5bP+wSHppxwOf/b
bAUwwpZTL6NuNJX34WgzQTc7fPAr4UIma1NK2n884ezqIV971rzb3N3t7w/pzqlMUXAZY83aokqq
9AMcSAWzYIm+mFjS9XOD5Ag6bNW9O2kHymlFyN90MDG70Jmwq68oyYi0u0438dbMlWDlODQry8ft
IJ51/8k4g7TfEqWcp8ZjpvdY3/e/PzjYVdXWUUkx1+ZvtU7QNp1Y2XnBeelOvLe23QUJSvT82o9n
P4c/pbzMxDasA1WA9J3XS83MXa4YI6LSx99TZjzQzU4HuIGetUcMWm9GtxZQPcV2kQ60CWTcW8M7
M7z1uy8w6mp49SvXQSZCf8eWFaqNaG/iq3e15nq4ZM3osgPVEHIDPGo6tDI+7SRS8ukauoPj3nfJ
fZQ14wL8ixmXAw2r2WGKfJPwKJI/u/XOVD+E5d17nzAERjhYvNioEOEGLxqVuu0F5YNq8cAgdSIZ
UMN2jMGqBx3pNHntIGkV3wvzrRZGOaqNs6IeH+fdKvIvhBb9bxmw3mg2hTUSdo4W48CoLhQ9wDX5
8jtARkyP8aQO/q2epCn4T3yOWElW0VsI6FpRmqI82+NRxapCa7UN57V6P/jGNb50AAOiNo8uJJrS
d2qKg/m1VtmRN4RIVFq9ckzI/2lAcd+oEvfuhFrVnSMdHE9ULXg+QjqCXvrWTwViDbxYWh7+Ytyt
UocPaZx/kCo9hh1UCcajWnOe0JObi9Y3PIAowG52Ld6gpmYOKHYbA9zvs4e6iIHkuh/9ne74ZSvB
tldvUc5uA8xscKCsdKjBynZwLe7AyrGVpPzV58sqEkKm0pNZzdMITRFmMvCvvtSenxKqVqmUeCvj
wYKY1bPtPs2ux0KbGYGVMv12C3bRhBiVYPRKEUX1D6bIjsMGdgqJnTeTW+c0NBtBremwJVoj/pwe
6GQ7n7DUXmoHp8cy5SKOrMCBNsBK84O9yH9V3e58O/sK6Yzha5OupEwxpTBtFu7L53A3eSS5zyjP
xca8gaByE5/HbFMdMwAbHK78T7hgbQKjRqOKoWS0qn9JrvPJYiUNJLCyhiHBYuyI059ePCMyDxJI
UbX/u5IXlfWOiGjjL1ExGStaWlbikaOKQcMiQglCvOxs9wbL44BrbXcqA44uv4GZLaKc7rCwofW8
nIh5A8tdtW6ZlV+Be4mthH6zxf1MHP8TFpyq0iPGjXRd10czkIdSgCDcWg9+LVuihSiXQZ5tuuYr
/knJEVp97+uMqJhd9ZZLjRiw9yXqaMroImwSvu0y/ugDi9SK7BwLls4Hfsp0i485WKy6rVb4zZQq
XxwzlRnYvZ7AD74IGHeNc2HOft3phj18uYEQROFKjJ5Bd69FmGjQfFtF7TmvVPC7BUhkVfou8On1
hxwbvfv/Wv4RK8QqUqBRYJaQ1qzXplDo1smj9ZgacordnZiUDGDqCf5sAOizeAIguc/jHDcZTMci
JpfKHz9fgnnUyt2J4zE4o9aniGItRgTNOwUQx1x50HhgeXxwkSf5HNJ0WxZ4nO+wtuZV9+oHansc
/+ASbVJNW0nuoabvB8wyxu513nsiQMlg5oFdpaB24lJ/QCt/tL/P+9hDGcJz9iUDUQ8vc/m6svSh
D81KoBl1ZnxTamTngrSa/QbR8zUJXeoXF5ixGLbhyE1m/lKm59coHzo98QKhfO+c9K34B0phajgm
RD4Xhq6TA9SgHDFChzyHtFzRhG+wmy6rMghM2Z/ahJ06y7OW7JofUpD3FJrhE8FvKFlg1H9udHds
jJVmQUOS2i3U0ulsxBR6KphcwXS4/3M6NZtK1qBDYMnJUK3DROV1MXz4HeUuuvzxfor23bQvXnHL
EhpafQ2PDG0lUigu3AMgnERTOo79aY3spGB9G37L15L9bnRujaeWpnxVCEYU1EadZuK7n54uGdOI
qX2j2ViXPJOlFTYnFNgemxjsoSE563xqWTEUwksO0oXSTPfuC/lM2pZ0ieK8/C53H2pZiSwK8jsu
KdaLkHHjevmhmiyeoAKMVeqrFyZ5FRYaSs6j08oXo7L048cjy47w52svfk+cEgLoM4D+hcZDplH3
uiLUCXC9XMe1NTeZkBSHbHrweHhIz0QfFwU31IYDJwo9y70/bvFJI48CDCI5krn44X3Sr3hcgpZq
AHoBOgwR+bp1TZUG0a4JYYEfOEoTJ/NgiKFqzU8404ex74KDgec36GO0vlRKem24BP1S6zOh+Amh
yc2PbLsmddB36xXryeraA+8b882Mf/Pg/+yOT6UU9O0DdtzIlM1k7hMlBgg7qsON8X+5FUGoiqzU
5NRDxr/1nphXJnm4Soy5oeLgmFo+q9E5ZoVyWvg7vSfPaQSIIafo7nRKfyiM9sOJbpP5sPR0Xd6U
yxHGf9XWm4LcK1wuSPDj3u7NpSHie3lXIOYM1U6XVDGxkDgInBvqQgX8q2UwkgLqDb+eN/Dj39sa
OqWOpGgY+wSZilnPQziBi8HtiQ8Q3eOwuDE0iOV/aE1VvHNUTsn2dR58Zd+cccm6CcAINpx/0QlZ
RGB0WT8t7tLKMDG/HNeAs+UYVlJqyl1p1NS1HBDymG3GQIvnhy2hnY6OCxoRMS4HbBHPXiIUsqYX
CavTiLUJUROYBEptuRyeDddHOuwA2GQ6XTI/VYX+Yy52g/VrSOurXznhcIubOhwH/nv8Tte5TTy/
ekRwUt97OEdvm8AkbC5L4HyKJSxdRE9uqfUSZiccQo5HhxgakmIrcgJuN9rSsfpgeaccWs0phaen
TNm3tbKGHg/aBzyYWmUlzYUt7vzChaNIq23bpURCX1AFwYCr2UxlicfwlRHa4+o6S8oTguN8Y7VD
AayXvI5xw+0R8b1t7XwfZrOC0Ixd+The3+eq1hxRrUIp5CDGJiWGvQueXck08pF6F7WtTIUSd/HH
FfH2WLLTE6oOn7Nsj2yUvK4kAyXIi4caeeI8eGI+/zYrtALJcRQBzHigxDlP476szaB3u2YHz95N
rZB0NsA0VF3nqR7ZzbZ10KPdO9/05hrPzjiJvXGy8q3hWNHMEnJh655Zq8tZ9JewBYgBB7Vy5A7j
IGMZnVCGigrY5BWso5i4TEY/EXYHG0kxKchBNyofblToPSimPacJJMahjjj6wr2TbOojXB5jIVJG
98rTLg0KRJLPUjNcWfFw2rJQNJiieBwfp5EPS39d6aURTVtJ94KDM1QqIXrAUHU+ngX+m7lLBwaF
VE0A7xoaF0r3q+fn7nrcOmQvf4qqXPpI2BKyG0nmNjmkmeCfGb5r9pTQMD65wV5zHInzllQdDHZj
P0K6zlNvG6u6xNVcZTwSGv5zEhJKq992S6IpESo3/DlcU2nm2TWo5uDsL7dG72aOUESBYi7tCEX6
20a0g3nig+HxNpcoPbpoL79y5/B5C88pkVblW1QfL7s9d85zT6b9ETXE8mcokRROhbgyYz/TKW1F
vnPt2bfXhjOxaomHAt1WmI+RWAgYecsdTlKd3/BO/3ar1Pdf9Dig3zCHtbdNyyQoFMxffLTZUzKP
J3p5JV+jQWLcx191mLieGD9Gllmqk7COiscKYjl9bfbQEhrhlvNwB+WpUVZCVqBKV2hQsIPYdH6k
l4dJMWkk0Fvnzh5sw43Tsw33TOn8qYD3dX9CB8UUNb4At/IFMKYhCohzuZ7nMzyDgHtXtkRPm2mP
GZ9uoxhAXMcQutvCJkRUWqt5eBc20U+KA6HrhW+aOpExHqtRAlOvXiCiMl2cunWUqnn/BdsjxDxc
phgIvdKSAyACmiuobUbR8LF69QpI/lprSXbRGVxXPxCwq7xT20lEKXGrzMisWM3zk8GwcBr4Ms7L
q0thvKQcdgyAKwxZmfUr08+1Ub+589wlyZ7j95Xm6325hMEvYmHmfFKCJPHeuGVXqme2KyUexSmI
gV3c/DJd31c3zAJVCTdEh4Juf/KKbw+QaygLSlDCDUS4s356LxpFu9NK9PdcMepmOCkA3Cfv9HSP
uNUDY9ycyUMAhEQ0YC+EAkzBU+xNiFVTffLRrDr6zEME6WYKl4oHv0V6PN6nEdLdn60iouhG2GQC
vMQJqeGfUSzp4F/QtUIyC6iIFngw0ZBxrmzk1KX+H4rk3dqCB4KoIes7iUBAEahKg989LueA4lPK
gnDun1KDr/cLZODK8WJMpsaHtBnxtvKjJa8EPEu303Qhu3RQQHjpeMSqHY8j333EbMaWF4fF/LCN
3OKo36Vrd0OxzQRRRuN4zJfNtrwIGOJIqewBwMvbszSr3gvEl2pddETMNFKlysh+qnNRVkEUKwrf
OyGvY7oZMQ5YXG7T2qpYNPYLvgSQO176BodiIYptLuZLZVC/kCcJn5xoX7U1EEeXTmZOgYNTnkjy
LxmmfAghuwt0671J6VtFH2eXp3Tfk/+SchD0tq9UoudIPa9m/3jae42WTrOs4Vo4Eqzj+2w72+xX
Lmb6epgpx7HQ42TYaocto4EvJMAl20Yij1HafY6aI2jGfx6Pic1f4ZmWS4woP/z+vPciBsrh/fJ7
Qhd8/5TMmXcfZPZahZoTk2fjsEzoUN2bE35qJWHi07JyhZCsIkhOxQOO50XeT9p0Nfkiq4uF9nSu
N4dSGA4tTwdE+9zPcPFlzJVFMg7GXdjsEtM1gXtMBKnthA3cbtVfQ1Xge+GkOHIwvV+sfFbXJw2L
yId3Osa0xyfeZs7hJGQIceyiBaa6/wDci57IkbYGU90vsoq2pq/Nefaatqj6e2fdxevq/SYejpuW
CvlbjeKrBpn+a4R1duc4723GhYmUMoE0Q6UCpY2uMvJDiSABa7QlpapMg1HTzgbWPD437aDSoFHl
/umOXQAG0UgoJxNKJJERhhjRrIgTswNCpTRiG9ahJvB62NPjzjdEthPmAcu89s8EHGBvJkUg1A4T
4ym7VyOWDwzu+hS9dRPsz7ivIBlnsuVh2EMtOlJxD0GkIzzEGrjIG2jTgXpMsFetTVdxy8oXFa8c
eLyIMGMg0/tv0Jhg0onkKN5GIhkFcQAnjB5t6Ya6DK3sL3ghfOwFGl7Cbjn1KFVgT20Fk/gnMh+5
C6kVeJSPNCbEPpl8laEOc7b+8rBaagYrEawwI6fsun2BjUXYNqXohVXHUJGcPw6dUdWAe96PzhoY
zQx92t9c0P63S08hQx2+p+uFB4m+VDsY12BNdYL4khd+ye4arh2QJdj3YLnBFsEr8URCGhCZwGzT
4GICxnTLxI94Bszru9xFwrXztf5wDVF8A53cAG7K47u0iDtzb7htLo7H5YT3p9y5RKgooDutXem6
g8WmiQdvksHIZYy3ZF+vOFWV537jM6SLgdgGykXvmK6hvscviZsfuYxljhW0J0n1qKsVVyfwxApO
sR9/AVmd3tModg9UQfYk32MMO2GpT3/zgO3pxQricMr5m+1IbnEEuTl939RoxG0vTtomHL2IkK/f
UgfIaHviRqawN+E9xzgQyEq8GsphGv0SS3uZtEGac47Nx7BubsBPF+x/KdnXieREYH24QxQVWrGq
jR50W+AlQV2jlPw+iyiKylrVCy6WlOJi04Vapy0/8151t8e7PNb7Zx2Kq+IZZnORgepO0dzaR2bl
WKrPrVJAX4wCSVHW4L387h5ihlwUKA/c1Phdhg1GXYozRWTP2QbI1bz4e6fgKegETR4bpBGIEXs+
WzLHfyPo1fKL04lrvAp2m7wCrxuLffs9rdIyEPMk84iB+GTgVGCCIb4Ysjlzzgt11g2c7nZyA4Ai
Da6eTdxRTr2oRMjTHFy7D9/SJNAhqoS4e1TV+FRV1m1MKDJk37ritcuvu+Sdoxo2iIhzwKM0E98R
xxBvYrXV504wQwTj5fzSnt6uyh3EbiV3ZUUp8aHYiu43mdcXMnBDyuZVfKxbAklImTFNWOzF7RrS
Kqq88zeBJZj9Sm53+LDKXHW/6807QPDLK9MfuWjHu35B5o2dRV7E2mrSImOdifX0laT/bxB6cOke
AI9wvwXRRDY552qIy4XkcnFZ9qaMeKAwGM5Vbn6pecypyMmdYn631nVoffq4HMO3+2rt8+vRa7SV
wjvGvhvHRPhh7QGLzGgtZ81rkYYZ47ouZ5sVMI4Byso4m+3+2JgwRCVAGxtoZ9Ct8yDFpkXqwyTy
Necpvm03jbatcgII5A60t4XuihtydJZ62cDdgNYmBCNEmHKS+HZn2fpYECK/5Mhb0XdTH6PHTasa
Invm24FMnHBZEjBcm+gikJotcnlskRp+jafIrb6D5NVaqvqJXXXNKHiRh9mkw0xs67am7VbeBfzS
mnlu0zjSUIOxbqjndOFQfzXlZVWg7p3z+6KlHeQEvBy6sqS4MA5iU3cOIm247oE+0JvUGwyFfOPl
s41ik9MCKcYW3fi5S5FR5Tlh+CResoTtH6lnWzaIY4dPGH1bjj+p/ZSjnh08p7Y2kLHiceQgMCzC
kGGD9aAa6OC+xZVwbdwTX1nSrHrsJvzSDa4xEksTpJ/pY/qbM2bk8vxvq2PWLycM7E4G0n+V1jMg
b1Zf08e0GbTCHcnxZkCjr4jGHqTq3Jfbr2AK2cVIRsecHA54HR6dQdlD2WWu05kob/LD5MDbswhN
ra0WssNZmPuofzG59fN0+SyKr9IEaLXI8pm4wb0zyydh/TDthH/LaFH+MkWhpkQ6XBpYqG3L4n6R
ASO8NFe/f2RjZqVyacFagdjNGUrWDxcqQki91dOswlZVgHJP+ex8+Whnl9Jn1giB+DcUTEEeSuFs
gwGxeQan/LAzmhXlXH3HPkdqbsS6r4bvKJthqm/Q7Va/m+/Bg+O8Valn1NL6uPfmbyLYit4xZHtv
vMgs3TUbyKFm85kp0WhhihpDymlGQcGeY6BEoIRKCukFa4fMxaYSjxVhEe8cEijWf/xnzNfTGblR
EDDNh9CqikH6nI/CWv9qbMqDdl1FtyUXawJHLDoavLfbZZYUDrdzPhdyE5Y81dOsxu4tcerSdZzC
OL/NY4B03yIDe7h4TkqV/9jNKVSl8388GLTNSrooBuh/7135szBJOHF0HjQL37eLBveqB+uTvD/A
jxbpZQfUAq1tdCFnOgptOBzg0qX7FHXT6jeUxF/5Q3YbGyeOG8+OEXxgmOQja4EjeGgtT+8qOcPS
jHpMHhU7nkz/svNVCR1lfB/y7lBROP1i0r/iUum9R0z7zpM0jhr1/RvtewzRPhH0+UbKIMJvJpGr
fN8FaqFaOlmyNpN8ZFfNwoRaFfpp3AxJqK4+XyEX/uznrbF6ADwO0Mgivu9ObWBVQGazh7/BI1Qt
RMoQqWplu7vEsj7Z/jSfXjnaxgzJG9Za5F0H+NOupeMuTIIL3aoR204TVNOiEcqLS6nFUBU9hxKu
6IJV7vmmWnsPtW0LoGZK7D8T/oqRUlsf8q8UjACK0RlE5taFxPD/+2ORAGsu1HeXngLwgf6lEHCO
da3OTscCBx8fuo22rAzGDylHr/b+3t+/bL/0Ln4dfw6zcWyumCf0rc/+5K/SAe2sQZHbKffVvOv6
O80+CfV7RhVfrh4hy3+0o63Q7jmg2dEAPXd7g/6L0wCWDeW7cxI0EaoRP1s6JpVd44MAUNA5OwWn
Zjgz+H587Qp/3qX6hi07QlDK8o/Wfap5F4+QifxJi/EG4FHVPlfBRHhoYTldkOaLgIDzU0yooG3t
aBODsQgwYgGcqriCi6HB/lPFLcS57mV3ZfOV2F44Gnm4x/onWee6xP0BdUjZ1e1946M3SAS9R3Vn
iI6vjiDDiF16olLi0c5g0Iv8jH+RALXMgKHGgJwe1gU0E6VrGCcyISkozZPspCMDJBSHiEwA9H3h
BO6gS2n2Om1RuD9ePO/0w5NCsnJBC7tAhzXa41nllTQtm+qQM0R5QfAKgkYTmZO2T2+V9RoKiWn/
qExFI74SIvmYLrRCax1d19UAHF5DozLkrSykj9Ns3XwtiTodIL5QLIlhzWOo9TVEeXEM43Q5SUH1
Qv85x1aPQle1sLU6N3b2Eh+DVN9xL3O5v70l+K9X8eRkNgtut1XDQe9yrWKe7hX70pYlFg9iIEVD
lERoOW4KcTVaEN5/HxxPQWBWr9jkgC5/uvqjN1HLz7iwo102iy011rPZv3UvjZvbZMXPnaiS4yFR
bOBNIpo6XzGMz7EuPTAcdEGbiaaGmJDVQmua28JdWe9Z6svA2A99n0OrARMhXsfb5If5PQ+3btWa
c3U8W8kop97wu8WL6k1qSQqYCaMmbjebqXTSLwE2vSkWQdeMNF9+lKYacoDrz8fu1xxp2pApBz9T
sNXELgp1sZWLbKxAkrQfwmdBvHzHLnEpaoBrrzTnJr/LoUlcscX7GgD85TT+ECST6pqceUwBP15G
2kuZCQ+O11m/8lhlKNAmUHz5CNAEww8XDavZo6hdS1cPBTaajTAVQbonluG5Cz2mb/s6F231N9nY
k7gRsxNfrXQXhn6rDcllPuDSYnPWYST3wu0cFGMrklzFfZ2qfWOq/eCDwdXb5RX3F83C3H1KSxOm
wV7r6aD5r1eR8fNAmCLBb3MIvwT0ob8nH69rkItnyxeNhcfTu0HvNa88XlFE4rzcb3Sjs9ZVMU63
SQdbiPZvqEcmVHBjgDT4Sw4jNpYjRtK0xcG43mRO0FzbgN5vPrxYK4YUK3UtkTdsCN/jMXy+5BZC
BxScR8fd6XQJ/cOKejFc1J+dtg344FYEog3ZjZ+iAz/Tc7oZwryCsMnogDad4PkUPpuGgeIaFuvB
fEIIQBGUNhvEpMu76GENLV1WmISOkv7M2hl2ij35r2WYMoHFpsJ/pBIhQqNQv4r/DSeYM0AyhmTH
5ujnI8psI03hBYSQE+Ny2Pd6hiPL1pN5ZfWz8cpYRatZWvLPSRM/xLMs5Q2M+K7OIpoeqE6G45IG
rpvhGTYDtSHxbdaEKlbHWIkvlV73EenPu6hvbImtxLCHrcYeupGU9o2CUTQ4cSqEMIg97qbvVGmM
d1MnjY63QzbjzrruEm8veHKWVc0rSt4P1QUKUzuvUnsuQuRHBi0hYuU43Oe9Hmozf4JCpAgumfLG
DwOoHP332291iDTVSUay+UYUdvuZnnK8xc9+RcBuBirlC2o/b2naNb2R2cidSdmhDxJ4rEdLGS5T
Qffo5WExztGmKm0qr4nXwgVbbMl3MkbkCagKihP7hedXo8/m43h/QeQBJe9lWWfB3ZTLt3sTy6xE
IX7hw7QeanP+fT7HwW2sUXUfzhI0ILMl+1P0OZc7xogPeNGMi4OlULcOcr/8w88vyMagqY6sALGx
QgcGoFW2VFV3itwEENkxo2CbPfUqWUUPk3c0lq73iWmqkumbDm0NrQx6ReqRCyran4xOmfvzAOS6
zyP2bKqZh7p6pLZHXvcFg37MlswSJJmKgMAz0IpTzE62yx5YmTT4EVJ1Bu8I3o22Eufa1DG14bXT
ehQy80iv8NVXykvEMvdikedV0PFacCitDpbMG32bKIXfDlRSAloLhh7owhd3Dvcb1yqi9h5ZAXbA
FpBVutvzkMTUZxlZFrO5HTW01FFLt94b3riOkLQ0+E82ihmi0GwqFFb5Yj+qX6HoN8LZnjrIrEp0
yCJANIWPv09hLQX1kgwAEUCRJ5WNx4v8qJtxyu+DdTWE5XRi8ZcEyNxqTDfRlIwBc5YXQAjogddn
PtQ1Haq/K0bjAS6jDMvBKicXDJBgp/GaCz8Pd1PsRYNKO+mm5I1uT9pQNCVxc0gEhXuiD3bzZ+30
OtN3aSnVezuAXnLvJOvhugLZDSDuZ6DXmycrH7hK5jCaLJksXlYkfJrZDixhlJfZQcl9O1ggTiY8
Vc+1BHjAoLhO8/WEF2NVWzAbPtRjGLY5obrpgZ8VDBHUyBA+8K6lq/KXq0zv2u0MQAtlJZesv5No
jigmDlKl5jQbW9Qe3B0X4ePT5sGiqYxBq+GaMtNf39XS7ZVbLALkOMQ63MY1CQYxBmVxqSSEUJJ3
jIIKDvrJCvgAHqvHBR10AB0cXpj/5ovY6kKALruH/w/Z8QcSJhU968cc5ZUzzHVq8zqmGWWE5BPM
mDK0k2xHcdDB57ElqudmeitzenAHpJVyoggq4Tdckad5DeEJTHN/mrK2Q7ge+ZuG4SYr7Ngf1YCZ
1ZycwxQilQlqCLhDlx7lrUTUcv93lQmMEzYeUf61r99ib4Fwo/wg6mj560PFqK+uP2MEHoXFnOVH
jWTIXBkwRIwI/E+eEen+uppHJ2JK3tNGapaoFHkHXJwbJiUBoGR1ncnB2mdJ49sqkKtpE7bupSFU
5oKTR+oD7xnJoO3pLe2N+/iOBF60r0LoM/u7oQ1wBGpxx86T+ipGWIYdwcUMu+z9r+jzMcfWILoT
H7MagFpJtn8DHzWawIEUwuB2XJoPwJpF1XvVKFUTbN3o61kQxXgbzO1UzDkND37LtA0ljxafbrcY
dyYiB2aR0/2t8gY6tU/u+wsWY0dEH62LeGJ4ODmHcSbfTgUKEqAdXBy1bUvcLc2qPYgkm3hWn5kE
Dk+jNOz4ijySiWSAoCl/uNzwj3FzWpO0F3ZJ0dGg4Uxf2ITcGTlzpe9KNnp/TkRYjZML5r/jYZkt
PEBna7rIdJ3Wv/PABP6QGwopYLn4NeP14GE7BwCG3KpKp4mHtFQ2CgX4wcOLMEFyUTDU5Q5FgdO6
5/VecEyQ4jySHfJk7c5XN7g47FSLpNNbYjFSlADZZcIQsb06hbFMtSMCwHnRw4WcR722llEt1gGh
GzeRaOPUoU5clJVXI94MQBraT9UrKTSRWdJwYriAfW6A9N5+fm1TxHbSpn/o/lPVxCTSKejKwG4k
VqwMbU28sqmnsoYw3A8MLW0+VXN5CWq2fauW7i19GxCrlASu9wsXm9bXf6b3CKxwsn/KTTESJte3
BmGdjdlf8fhkqMPbYw8s4WUG3avrw3Szt5hWO+oqCqQ8rbI5qpOgiQKq2HTQGvU4O59VC3Hyf2uG
EHqy3L27oeC6CG+SoGYisjFqG5ZLpmgHLvUTdxrGIar3KXOh4xQvkbGa1uOBOIjmARKbdcGPxnLg
WcQa3zuvV9IB0PI8j3oSYwpAKDY17/G0mvJVrUZigPFK2aMfKgFkyLpfWIu2P/J3uVQkQlyXshbB
BLI6PQwzPW3817EEc+9RdXftCHerP6gTKJtG30aXjdqxwOsDiKIeMJw2UO7Ht+1f5938kQH+TU0K
I+g9wZhAg3vXcPnAf5mfzBC8FWBR5VmZ41jgSrM6Zx+hIdp/D1z/BXedXFVEElEnTjvAt5sh0O4o
q7HYcyej5eyNA+UDRhgzBoEA6teVTBTNoGpzbvYAOPugBEpZrHEiOa0PoALPgWi04k36yq5cabRP
RNJJOy1WKHktGb6uzm66dLkuzIbevgZyWV9usi9UGOqduwwbF8xxiCsR8/bSlmAmlI+oXRdQ6iEi
2LG7MT9rdGZp+JtC3fYPPebkUKwIPuN4bDVB8r+UZ3L7F6y5a9+cto6upCoBAh/72Oq21QkVxaHC
WUoDctKBn4mf8EYy8Ypn3v/h0Im5cycU17UokwurGqCKzLZXqCywx1GOi3AsSWA9YU9TIgAyEoU9
Ey7u9qf88v23zeanJo2CbURB4tshhmjPjfdLfclczhKPhvVlxpmGUKlHCm96EWVlnaSjMgrwuywT
YHHOMLxn0ytwzV3GJomnzHYtYGQzelLVXJFeK649NMpmukuAndiNyMaVQesIvUOuNEnoCeN6bf5x
jWyppwsQIwP394F4Gc06UXNAX1bt5MX0n7DejLoUJ567HFZoIPYGkxrGZyDt83vwzgvo83y+4D6/
+DkbM2YVm5SFne9+QrpAerwI8en5NwEuW5KCakmPKgt/k5/pu3INUDgGl4Bms7qxLc2UhJOoyOFk
tqxX0A9Y4l0eyfr3iJaKvJrdD8UITYDZFOGfJe//wbvJrw7mDlIMd9O8ETc40RI9mg+NVAqoaU6/
i7v/bGHlaqSBU8Jp/aLJdZzvnGxTzeXkdjDSi9OX4pP7HHILw4de4A460VuqBEQuGy6o1Rjc/VuG
BP6fKEdHNMKUfEuknqxayiSquLzjrx6aS4jAgovalq1g+G4ZpeZB3aiqtUHVmDXOFNWh4PS9a4BX
IBORuwBGL3O9/HNhzYn8dcNkfBXnkFfpTHB154UqCtXz/4x62zmkDkm6iyQCpZlaMzYS74Gs6q2S
TlD4AvOU74NUleoxfAFw5oTS4Qeq6k+Go03FGcKPdOIYLTfkFpDvhEsI2ybwd5TMxhSskU5cmRhh
5ZpFr4U/L3in3Zn2Si/XChuWQVsVVOYV52TvDLJXJZBs9oAuC6S4Mfz8ymqJDHXL9BeUQoDAsrMm
RWcj/37h2n8AFj27p/e7+4TqZlt37+dCEJ2n6kPGEiys2500xdNc8bWTRuQC1boMTP4Xjo5tnWCc
1y5keY0s3rmm7sWC4O7qknBVx31spQrPu5W/crVHutYUEssXCsCLfgI9EM7u/q4IIV2j/LAo16o8
iK2BVhds1V7ijApjIx/HYCNJeGBl3qZt16qs6qhRJRlWaB6TxL/KpAguFCpj0ZH9W/qWlVuJ8Ljo
8BvUmsa5XtDp5fRQhFfRE2WVtRvHh1GJo6kMR0XowCeqmWZWDJSWEztBEaI0eTNY2b7y58WJo7ot
5+LWGGepoJ3k2tdGQRAWMaCYbQUXC18dOMkI8123qHfzcc7VaixBjDQcdgsKQjNsy7xbVN0Vh9DY
5Liv5/HY1l3MCFFAFhxtYO+gQeLnQSXb9BBYo4P7TdhzG2Ocgu8jwne5e+qJPJMK45bSH1Xi3aJK
KgrSN/ggMRQYkBqc+ckeWaG9B+pMVZFwKfE0S6idhqkljrBN4Lajalwzjlbsv/mfI7LV0lZxlQ87
y2au8npDkZZVzU9tdLm8CqWyI67JuPXfdnYBO5VUm8FN1+oTEQFJJ2TSgq5DviMK8/B+WI1dKdXw
iXgvYPU9fnMZln2v9ycLZ9dyl6cFBCGp6KkhK4NpRxiYvFfgp/wHqv8PHpset/hFCtJ3GXllXrmk
fbz/7eiKDo2cFaxxDNceMI6eyqqyrvLT0QI7jmpHmbD9oOsW0W0rY6sXzDrZ59sDyw+sxj7QVn18
n0MabaSIcL0iXzE0bUZ2rr1WksvPJCjH2p1ydBEOLabmwiY1kCEwhgIF+NZzgbVEe7BOTmTP7SY1
MSSk+b4SVDakb7nTLY9KZDOub1HRPH+JGb/xJNm8Gbxj17c2vsZZl0YgIeKDpxRlRMDTs5J9oOWT
bWYk6qC8pOPmwF6r/uZ93pMgMsSQzzNz/eH6D4vWp/LMi7B8ceXclHlonvaBKSyZ8NCJ5RdLScbX
v/ZvqvUNIg68DNRXYTxiwCbzKJqYgfSn9HOYhL2wTpJd6/v8Wd/aX9c7uFPCVMh/ORIaeybfjz9n
7Hq/+VAqonFb7G8SE+s0JSGWUMecy2sj5r+2VVu2QDtKx95pUf2wUA2vZWN1FC9AiFCAwnT/TRJ3
9aOuGOeXRvhForhVEtH0xerxowt7qwuPJh1Z5FfogSKf/YhSVRcB923R1qHKmRRvksZKZ35vgj1X
DI+QrYDpkix2sFKbIqZV0u4I7rS4PCOyxdsAz9g4cVsjwk2Eq3qxcKc6d9dpSBy9VZ9kxHrRNXxW
FRYJBEKG0voGlaNe2AwxcKVBEJYCCZktUNwcGilaZFOi9Y7LQn7wMaw7h6CZgAw9eL8UVFMGoKzZ
fV3svfhmoqBHcziN0nMkOK2cRhtWH1gamUZ5cFoN6wgMUUc0bpMTi12UVqW7c5U5Ml2HZ7HkcInZ
O4poWE6BE+U9C7JPtFh2bc2kyCb0wTlOfmHJrtl0SK7K1SAOIaOQINbAFPnWAsVaWMtIX8zx17yy
82EBJl38UVHr8705pA6/NEqKmCPmg/Y3UxJ/g0Aos/WI6lImCPmSuEhfuPA17NG2cdBl8D2PxSMq
1LSMMj4DbQz/dGVns87LjMb90Q0JoakTzwRQi/nqRde4mYoB9Ug+tZAZWuaANcKehbEq0iU/eSM6
q1vGFSn8qUrlgedYpm25ZpKa/n/mPt1YKn0B59D9O1sHAXR8p/50Jjqrr+qfRfKgMhQXKeGrTxzs
sp9rTKQ2cjU9G3+4hsQG++MIwo010+3FZc8pYRM36ztmawF3XTHPDYCL5wrUFiw+r6usut9RujoS
pYzlUcLmTuZ9drORnW+WZjS3du0Xd4rUdDaqY0Jyer03clcqUt+DfxwAdEZwxSo2wg7U0yrl4Pcq
jnGMUdjeP1hq36fLK4s/kXZRUa4Rb+cE38AQtvYnxEDcB7Kcieb6YM31j0AYgzIEd2r4FpnKD5d+
ouOtApajsRJZiWc4/LDbDk1J0OYUzAxCbc9X87wEXRh8Vm6NLNsn4bLVkEcIeqYGpcj6XtkrhTM6
Bqoqt28oYuHeA37NMaULkKhG0deQcsqTOHVUadrvVLLbfGenzaKrkO0toIOu4KgU6YcIt8J0+aiO
RiaxT6fhPsuMM0UMUTQX9rBaKs+QmVJlaGGwFFXbNleOJNCXfoCGZYZzwBq25+607Xudm3IFCIP7
q/VNT8jt4K+YEs233EVEE0w0ClTE56l4tsR0i+scqF49Jz3KWLNEcLhl527Uz9fio/yU7JfBwmOb
BAGlsWrgMk8NxnXXIq5UsfER9/TCokGn/HnKRe8549lHb4hifk5TyNBFby25hMCtAvEexd/pOec+
wTYj5FEbYZ93uDRg6aVUTGX5agwEtmVvkvORXlazkrSz9p5+ux1tY+BGUbRnCZ6lKC/q82hC0W+X
bZnnwqCsyHfr1GIH7zFr00zRHDQAKRAvdO7MT58uo6nfL0K9VBZYdXsoGjib4u/k0+/AdJ97CLHw
hquMnrkqoZjbPRg/QAEL7F7vFz0obz1BVMFukMqsSr+//4cyGoA8zebihWNa7Z/3IKkcFwKQkj/x
gmx63jdKvlZEs4gYURwQBCFZLbTWavQ/BWuSyfBgdFnwqlT1xjaS92kLKyOY3pm4EbnEUJAapyHg
XeF+dP5Buu8feG5kHqkI89LpI85hQ72WaW4X+orvclrh7C/dlvlj0EvULrYSqxY7GkuIP8ijinHp
rA/fMYybdjLqWyJgk5Be2g6qFe2SdXqCcigsM8WzkAGY6wUi7PXIlWnlgL3rDayKaBOnT390eQoP
Vtj+/s+quczWTx2FZH6nurEkN39nEPPkjBSOo4fvlHjgM32cqAA0A53hJ3dDL/HVjnGnJT4u0wEH
qng+vINXADPyT9k5hAWnUN1fSZvzY7X1OACr/sB63wleW9Z/7djky+nUvIfArYyY1JsXugOZDfHe
FZbQMI7qdG1hpfbvslRm1ecy+bNixCSFsfD0q6FzJcseFGMZbA1x3+ywuWZFA5iMfALcprHXpZAS
HJQXYczteucMZp8D/erdMWSJeetdkD94HYzdE3gNFMzKXmenKFRCciDEDyRglvPhXM/vicKR5jWX
9apKrk/wCH+SxY6X1AJI/ObKAS4IUG0QVsaZumsijnIMxFI1zecwEaKE4phOhs0FF1lSpv1Wem34
Bfj43AVtp1E8tdFKpZh8MHXn7Wdvsj3B4u6+ZUjYsp3tXMgu5LxCMaUDeVv4GqPNDxml62anrmIY
oulS0/7HSFUniAMzc+/lqjyg9aixxd2M72/YIdBV55BOevGRJtpiMEHu8hmoYb7wM0KvTkKmbcSO
FRnpRKdZAEX+VLZFS1HvriRwfEAjLRqJkK9JqEb3cSadSuBYb5haxcIQp5iI+462FB4IEazNAhTf
6B8JZYtvKiUwiR3Wa98cK6GtQocAb2EagKZVRqKkRKu0BqG1UOU2J0MX0JWFK53tg2G0fR2DCKB+
3outIQP740E4ypKOBE3UJvIW8EH5DtkMrOGOqqGfRv1oV1wAPWBIMLqDHQTIvJTpYSEeL6ikGs7Z
AgMHJ6qlxfKFHAMWip6cYE8/gEDP9EKwL2pLfziVJYwUuxGaPGSNxH+25zofDJq+rxVu9lcDNRXV
FSgP/qkR4cMTAf40UjDUS4emiH5iQWeQn027Wf78CPazWhLj4wDMMfplLuRk1tZQyft36YIazNkL
glk4FJiXPvq3RBCRhPyAy832p9YIvuuBibLBaFyrvuU+E4HuQbAvkXH3TOldZSNPO1i0ZPOBWaP5
4qHSx/Un+o7LRkjA8gPHd7LnuGyQypoqhK0f/heNpD9tF3HQ6hdErJ5+QXYAn3iHI+0LVamlOe2q
YYqiqAw0VVV9rPbNMutpAEeoX+FwcFhlGbMRTo2Ll8p4THo4bS1fCbp/Chd8OOtvvllTI8zMP/4R
S8zQXim7cOh20Etufiu0uekQcsCCp5QxJNXlV2o2ApF2USP5zjt2azjtUL8bkSkFNzikz10mlQz9
bYYrpmJ9JB9kyCsa/VG2rgRMpc9nVmVMO6t+LKKHjh+rCWh138y3e3h56nsy8GfIGLO9DG0BOLIA
xpumPeLTlc1rKn0x1T9kVA/Ijw3w4mUYNqfALx9L27lStAxlQeISReE+jQ0VTs/1m7SeQzJGU5O/
Fxj2+LtrAaZEfFtnj9z4b7FEhDH0mBzJmy0X0b4328/uEFavv+WUPfD3HbI+riMr8Yguasr+TLXQ
PW2j5bVWwkx4TUq02P/sEmrI/STuXqFrmTosgrPVOMrHdZxsa48UyXEbzkYEJtUqZovDdXn9iJeS
GihZ6NweLNXGZRpw2zF6dmdUsN6T1S6Pa899gIM8Vl7LhsIAL2r/akufKL+ykYBMV3WcYY8uAR2U
GWLDXt+djayLHDH3dmWQJ11CgkEMNM67aPluoG/M7jxWnUu47n+fn1Q+9Fd7dtKew/f19M4txjLg
ycKhs2NEsyVn3Pw6lDsv2CxkON/CQ5k3mfQn6lUqLDqNA4/RZs9667lSJv3UpIJ1QtUYKxYhSSbl
jR3kl04uL7zt/qqOXbfhg+y5/QkGCU/nuDqnp3HWJ/AQo9rPuEQdJ7kFERZFpcvUzrfgiku7Vtv0
3wUni3ae/nOH6UU1k+n80nPPTlZlz13Y/X4DxGBWsMLKP52jXqLnoTEYCprNfiGzy+ORXEhYYPhL
WiqIAhViKzqIb2hDQifi7lmwRlCrwUKciDqQC7b6YV5GBADO9m8udv1Sg+5pgYM56pRg6L587TYe
SiKV9wZDiMAwXZ4OKl1YCTl6gaiIOmOiWFgVpkKaYWkS/vl9GXHTpLVhh4A6cpGhfnBRDDfwqf4O
MpD4nohzJ/6Y7g0GVnkIwBdLeuIJgwTf6xCFulBLQ9KOfnup4OGppLs+8hBT5pJcNtIFDIEiU21x
1bbQGe0d5cL9FS4nXG5OzHEYWicl+iB007zPyqI/SurmRjJrU83Im0pEqjl5S6TA6h+M/Wqk1rJR
B2xsni1ITTW9SYS5M/sondskpU8+fhql5V+umbBCFJiaTCiURvlg+oz3+S5sb/ZiGrOu1YYzpKNB
CZeFLijuvUbpN2R2umv+ZAqkIYd/eucXwF+hwob+0qLLIMGmGFkHwpX9BUXUUb29u4+5Y7pNMokC
lhfLwv343TURSx8X/19Kc+gF206GLxGIcqlw7Wn6HK42zKN98mRZTMiZh4ISIWEUum6FYLIFOvEG
W/PAwqVHidqDBQuTMWFw2nWqGFNHzrxgyRbNLYjJIQiHxxlZG1xGgfmr1zyt3p9mItp/zvzXuxiC
1qNqJGzYwa4JlyymT23zIe/JcBo4ESmYHsAR4Y4ZC1aPmoR7D0OYsDKunviNrMI8tL5E6W+3yAfX
KlCAZCHxIStx6yIakbjE4qTxLuJdQS3iC1EPpIkh+ZQwLcbOiBuPrUc5NoYlFpvuZrmhBaulTAFD
Kzn/6IlXKtF73n+G/1t7YaLXWvC0qQjruNbZRoq5fyh0IyGnTzxuiZj43pJCWNoro0xjLLqCG2lR
9BWOVzb6XVVlw3JJQ+ob615UizsfIyqlCJQiXC9viKjHGcpsSWvGCzEVoYB+J0JTjbbxvQEG6jwZ
VIO9Yc505g1qn/Nn2o9e3J1lTgJgmq7p5VvfooonP7KTNQSGeVOVE7wxeXMxwn3BCXRHVTmU0MnP
ZuchhMlpG3NUIIQC8o35YKXo3wHuIn3xYCOnMKqXh/UBkKItJ46lOaK91x7Fnms4RepFOxopQEOE
JLAVVevPHs3oz5ltpCMsIvtQI7vE1nf2mPWL8sdG2sAy99ihSt3dTpvUIZAgbwih91qmnqsRUDxV
I0y9fWTIWjZ2SCCuUsdDD1SoPl4s6eTGxncIGQLQHdBYCJ8yh2C8e2cuUaTbAVPmlW3UTqLwzMtZ
MtlR3KS4++tn/AUlOhDQ+0WRqYzn7aUp/tyXv4zXo2B9UN657wvl0DGpaZOmRKF1JmeR2NR5+ztV
XTSsyw9HfM/SG/qEEawIfT0wK4eI1YflPmrT4aKcUH2Z0Oax1i6tLyUQ0Fu653znSADF0p5B6x5m
GkG9KmBJv14kGbCbk0fioa+6+0EZ/ulTSIcI7GFlWGD9ifMNXzv8wOBTsrlZGQZblkDNYi5fKau4
BP/L2xsW3hMc36+SJ8UdoiDuPH/bntUO0ex+q05lgo/lgUTXhgG7vNM6nCW89DTGGNZM6Yt/eIoi
KgRnuzyB4S/foCaQfeXFBaLIKBWZcQTGtoxZuKJwkmaVlUf0CbXAOafByOnlv0jNJAskEokfZb4v
6igFXVFZpB/cEZsa2kNzz90qjKH+4prk4eEJckpMuBU6eMaR1Dg658/JuLf2g3Q5OE/iO7HEJPYn
Oaf0nXqTR/81qjnHDFdkWzrVK5XHhNAhWLoPFWsEqkneWIMyhm7791sXqoA+lKhEeszRcabYxVZX
o7qVupM9J6VtA+0chQLq1BqliJn+lE7yk0akXTrf+s+KhxAcipAQEnDQgSLBtQWKzb6wT55ZyzhN
O5m2yJefk9lb6lq/6WHh2oTu65pkI5qMLwPc30+UOeysuMjjcTyVqqm/lgsq1UhoyhA1SKgsIoUr
J6q+sBiVAolIcl7a/xD81cayYgZkdAG2MMzsWoVnqK7HLQ7nix+g0ILw1d/UeUPmGBQqNnry2nF3
7GiIS3u5mtXoY1leeGU8VI7Lp+XLZXj4Zn8q/dFDrFBlwAQnGK7UCGVYzf9qeWSBZDx3JrAt9m7H
9k0U0G8ObSSP6bDOXd7rGFopvmQAMlGntXFtLbd3XBe+QJPwyvrngb6MRUFHFX5O0MG7XjcZMEuL
2ljIBcwkBRGYZ3c6fyGFmNl9zYkEdNgfZNLvcEQnN2mJ1G9fT9+50MEIpBMq/8J6+6MfrlsTixaH
lPGe49r4zjsuqDD96BRPkNV6gPmDq2b36cnC0Ndkjx3B/R36iAnRCvXekF+NetxkSzGE5LmtV5Au
NuEw/T9Mht/VfXvL6hzW1ZzPX8JL2/7GL7YnNhY6GyhkhUzg21YZCwP+Mp+vD+PDcBcJ6WVEi4iX
cuWU3ApSHctiQAJPNAs9eDmQG64G2wcxx/hwoqwm8lnsEnXtESgFaToRc/4ahRxowMxrVUJOtSZX
8tzxP34UV5aRR6OHiTIKRv8+nnHkWo6SeNtGhC8QCvsVyZSIGs7dMYdKUYnTWR+tn2WPYfcI39go
IHega+O2fn1sROrAQ1OYc4Djz9SJKAsATTH0wRWHY5ejuJbFefe7W/3/82pGSdCyFxSkNjQaXgHP
ZHeyRp3Pxj2wWaPU6fk5JAEgWXufE2N3hgxlF5fSSXaSFlqyX8XMDih3Ze5l7CynD00Ma1Fxbzid
vJL2FaAVIdATRi/wBvjb7eT/IEIBJUl5+AhVYArBaZHIDMczsZej8lZBPN5DxpZN3IqLJPTcBg0j
J7PBhpiPWr/Df2sMQjthgaXfuMDf1LWnjHoRRJ+HsUjAxpyR6+wahen7cpBbKTm30woaLqpHhoko
quWs/sBg4Hpa/9bTPufsDRw27zr7f3OOIIAdcyAgH8x191Ux9+1qhu3StPyqlXiDDgN08m5edDz2
REZA03beZDYAtGAecx9M4yx9zZWQ7zU6qchLt/pkgBp3rQryFBPfQ5Y1elBQt1IvlQLyT4XLf0+5
tRzxoEMkvr9pgqHgSu9+dTYyQ3zDbS9ASCAfTbPtAzN//z7XabhS243YNpSC2n43JV9A+Nik0YPB
GNYXw78kCnIBuqDscdGYhhHbB4mTRYvtWjErLzzGGYSlNcCxnS+OcygNUga1Q4x108htejfb8AoT
7ADaxI8NH83QA8HaxO9lFSHhViFDSzHr+FD5Uo+jTlyQRrCo4o7/H49IhK+D+jdaZaIFE2NutVcT
yJjvxFIQIET6+6rjqhhviuW2LPpIaVCipzEl8aaIvbKZZ+UUKH5QUIM4gF2bxpxeWxOdpWGjCoPQ
atZCmb9a0ayGk/M44PdFG5giRn2rA5zcovSGHGAAt5kaJu1D6IDDlq7yz5i1b+q7djLO/7cHIV7r
My44GkllyKwUme/asD8pXyKDj2uFTY9ruCDaKz/qjU1NEZfAsJsMP7kJfHALmZPQvm1eTLTWWiMR
vHKUQwhvvmTNPYatysrx2njRYc/fFXg5btiB1Te2LJHr93OoQRtWtJSlbtqoNxO//ux4Y7xhp35L
waZPasntoHEHlxLqqZug5pooCOY1F5cqltL947F0llr4PqnDyaTeuwW0KnLm6U9J1UVPT/WanwVK
/UpyapjPbDtkYHdBCeFSrgRZMWd7CGkwf4Odon2/flxGdLn9d2q+edkb2exQd6aTok3Omhx8/QND
QcLxjHEq+dGbI/ffCJhet/5CUzrjW3sIvvR9y8pR5pSzvW/suxoPQLw1SC1ae98YeZSCWqurvbPR
3p5PP4gjmzv4mxnvPO8RG6YzonhJduAleO7HVJTG8odXqG1GkW/4BGYFjWlbOuHIEmBaZRHiBGAc
ovGcICGibbrc3FNKPf0nnp4UgRFTqKcN8IHs+65L8MbyQQxKWlRziQuLb6eOjC+zqhZ7W8yVcDR3
UN0YvkEpzDrz5gUpspXh+pUlW7L0XUF8Trr/8jlo7Q+zZYC1W/YhqN5nD6oxZd2m6Vb7jbzdoWek
sdNodzECR5mRN2kTDksZC6Tf0BVjsVdZ0qiIl2qsxm0yjUPrHAsLEkH1v8BKWsA745L5PNjcSJJA
Asv/piYMPCQlOp/epAdAMdTOy0454xknTFho+AwfpAoLNq6R4oFlGJ3r1Ypv4Lde2KtOknmYFhte
+Fz71NKGbwu95xQw4KybF1ylN6v7ECFPxBmyF3BUoZC73OMolSyql5M6QI5De7aVGDLcdqDlirUi
n0CugRAl+gdxcy9eOVZRKuYCcJSNrA7+dAV4MOCJ49VMu7dawQyHXuGob04FHEXRSp81iw4LNE37
fVrXv8GEZkpw6CZYfPrzAtV1qo6evy/qqpaiZA7SNnrO30kgCI9wrCd31B+aLRX9VeyxN+b8WoTD
MhmgzjxyNF1namDE3bUhOVg7cMEDBNic672kGOv2mYp/j1pzmofTWYP+wS7rmO2Ipv+TEN1l6yuw
nmOyR9UwIdlMFbTfMNKsxz3y2/gCwP+lrwmM4/q2r51d/8u9uAHhqa8q6N49SNpRdbtUYrB2UCfN
7hHDgKnwGrcWhn8BXj84uz3iXvu55pVDI079AXBfGISZchYCpCJHw7V2NywpRLRc81T2eMQfIgni
pUBmgxKE26VOJydvMSDc3rLfmQTQ0ZZRcxqjrjLQM8jqZ9MVoUg3YwFXY9KaZaDLgeGCFxzN30dt
ZLpo+144oeX0K4MOHTR9eHroikCECkFqWyRrqKB9JTVVd/NF0eNRJJBvEh7GxSiaCaEesIgVW2C8
PtC6vW/VRDKuNW9mtwSaXy2fuFkzD88lC8aQ4YNo107DQUvvvasp48FbJlvmT55QFOiZRRVySJnQ
vJkdyeeIyMNMA2mYoa9YsH00n0v1EVq7pn1KKUfUCZP5/hOy4Zq+jtz57PBfIQfZUKBqx6dVyBBP
g4h/pzpGeNRA/5McV6wr7D7tDfpBiKPZRtHlq4oO7Nzepr6BsgQ2u950D3Rv3YseByfFXp7xYAou
uAVQDWQlrjzrN/JAuZJM9cnaL3njPRHWQIpHG2DQUcMbxD5kA/Bejg6FgBgKY9uGozKxX5owS2zX
EEYR2J5H+mRnGWk3GVx50s2qqIIWJOKujA1yUNe6XSB4VoAsPC9EM7PAOEBcCT39uCl52XKxEz3y
3N+dCCHZfHCE2kFgcY1ooKU2uSNynU78feDGezvP8epXAqzzNVRck9j8OX/kjCZdqvYb/0PG/xC4
xnYtaYax8TSj5NrJROtxlRNf/O+RpbpkE7iX0kGPW+7dTZc9jhlhnI27XWpvn9AVK/fMsMUvVnyy
5r6YlWiDiK8zM2+uZ27a28OLZRtFKZl1dAnjKqKGMOt5x2ZrCIgE+PIH8QvwMpHdBMloSG8LIQih
/i4HIZm94VGoABqh0SVJY9jq2bDzr7M2M2JZDTnPVpEL1Xj2X+YgnxkGCHuxAOi7I/q4/jJW+mn1
FnOsYRoabcA1H2RvwZF0DCbTRk8CAtnYuhhFy3ILpbNMhCSuHIqN7kiCKmb2d3cMHuZ2ptdgpFC9
4diQRuP64evwxFOVtCfiO1i8hk8XmtQogKfLpZmywdl8FlPRJEZlYqhfgLPqZ7Ssy4AQKMEFHsFa
VqkRxdCW3a027We67RdGBn6vp6aUYZNrTQxKPnc7MFqk9X9steUAXDiTyI4A6CTgbESvjd1mI4vG
UXn2EDOTsH+oCfScowEsT5WpXZ9nCrsKpdUJWh6+qiEC264HIGwjs2tP+R1kmAwCyV7Tk2LwJgz8
w394X4SwMISM8nJiby2gc3MtFBTcsp1aEwwFib1l1poyhLQpj5ckDESZI/Rx+uWjdv7PrXD+D/wx
kBhOaiiabn6yc++ZDv5/gaFDWYjgnZWszlJdsm8lIaqkaOFhRyrZzkD5fDEgcnbyIQEjibCxFCut
j0DDTiuqvQPFVXC85X5qFmwrA33oFr9djJPziXQFV6c5d6d/GjJJYvErefNFdTlVOrS0jjEWDldu
fKOXVV5lGp2c09xcg42ojts4v4/KXNCRLW/6ulgZMloYpxKfm9ATIMuIRf9xdeDnp2c6t2AMFafe
cBqNGi3La6l3uOZJlCxWGxcjkGRNEuqljQns5n4j/6qso3qqO/pZ5NLUxielMX9QVmXIDmAp1EdO
T9/11t4XJidhua4X3JYtA9Oe6lhFFCb7QCtdqODvXMToLB4+zNcD8jEDWwT7N0/Feem79T5qCWiR
wGRm2C1kXsp5N8oXHwVdyyEGdK3+8odm90sLYPFQqSQ7xD2NvWAW8EueKCWf95tfAhGrFN0oO8aZ
jlN9CDy/ercGmrwJEmXmGbC3NKcXVAoghFJxn6NqsshB+IiyebSPtcd/sg/TOiZcintwhLXuOC7K
kDWPg2549FrwfiMsl1fSXy2+8Fm6je8gmNvIXJPxSLaxY8ec8O4TjmpXwCobpfGzEZozAsYDV/zE
Y7QZ6PZBB6dKNJtTZkagb35axawLsvzXx2AQvO1OH704MJMLJ7m53qhuE1o/u9IwtTjyPTOszKvi
yKTl2vZ7/XONwL+5izFM7GksRyrKV6hcfub50wO7CkKMeup4Y9vSHzbAE+uPjx+GWkOYVR+6afD9
lEMR6qAVw5RQDEHqjRzvOQbRjuoMfe26grBkUIgVv7NnPHxoeGl/hLUC7CEQAx8ktZHf2/rVOnhd
To2srovmRkyE2VcKCY2BdNwOFc27xvhYzTIhKboKO2YI0hIiVz55A4PpwE94tIXrhyRb+YCGriZb
jjefKsu1XMJ13oFCB6hjBXiun7RYP03Ny7RnUE6HtIVX9wGM2apSiCiEHT5D5XfoG/k+UrHgipvX
eIZHyeNGP3eNc/z2U84V4RB6RQ76QW/B6/Z9C/lcizqIMQ7XnIoirGHsaCLcPlhnPNYeHGsLDDUP
rjcsC6skEv/BDoEoNtR0qJg1HkgzTmqTRHd+aQuLwjDr63ubMR02XBjcPKou5rksmi7imC11fR7W
1ym39ObYJFDo0t9GncIPYtXvGiYyeHnNnS4/srYGOrC5PTRhOkUGbC+qon766L2WbGgOlisZuyDe
tpQ6Z1Xx8ayXFHj1Onl5fx/h0LEU864yLNCva0T/7403lO1xMjCW/gwFNnQoL2O6kl6a6eAoB85K
mB6ocU9cW2rbidwDTHP2zYxmFNIIh4p4FiB8Jf9I5dxkwkqtEiIKkgXd10XjrEoImBnCmRtPDRJL
P8TQcZB9G0eKEXV+sMVd3vwhwbBav2uG6yyUOBZT3lhXvHfbLQapzK0jItw+v6qLmIFxHTOEMzBn
HqeTD/QrCKDxGDtdUeVjxaMxJN3/PPxzfcA/V9gJ3lUIczLYbOV+ITDsyyxdUsTmzIpTWaCjsx5A
eg8/bBk+LlUtAgL5lxB79kqFlHUoKXnfNYmtxMnUxdLAnLoOdmp1puwQBTXTknbWlCKojbp/qB53
vMG8zOXhmA7hHqU+hsiEEu8tgy0AG4ea2z7pToF4p688s4FfQqjfwttZj/ak/0J9yPmL3eoNS0bs
YZyjNw/GBDxYKhMUe6f3Ymsphw68xzQCGcZlAklkbJ4jBGPMG2i+19R2DXaa0QEOCLo/XPcQQqux
DtCWCvX5p6+61EK9fTm+qjwq9OMV9pwNuFGH9Yh0RNDiGuTt2f0BeATLJeu56NkgkKlmJhrMOg0f
redwp2Ji1WwQCvhApyAesDzTwqUJk/XE0BN0ciNSCTG+ns12+SMkKA1bpvW+gYh8s+sA7ihGbjps
2ytgMGYhAxsPYxfW2YjOX0sS+is/6H6T1babEVNl7PSlBbyi39AR6oERbOl6Kjlvef50bp1Vb/k0
CRGIuKeIS5sEoEW5EBosH9aai0MW3xyci/TY3EPRMPCCHzdcltALyHEDhkZLzrhRtEV8jIkQ5pbZ
fRv8eBoF83j7l1L1S4UBMb1qhClxM9cPi8tHfdXxTiCnBzzgZx1ailEfyp7ONaHMUdvgKS1lqDMo
TECJoe9m30bAAxJoqjX63Bk+t8K4/lQAmpBbBMkBJzl14ixWiDsa+vbjEQM4KqzwVjEge/dHpVOx
AbpJ7fAwOY80klv4pO0CJtkoHjqFeLI1dNaPdJ6WRBEcn1Z26OkXozMjtsU8KI2Oq0Ph4zJj9S9u
Fwa9pDwnhKj/O7cTRT1wx44umqw+9nk7Wl7bLJEsvXSod5I9zwUz39wjK4dCipNgIIEghd9/YrBJ
1zLuewTlXNEyG3knQ7SHAryi4R3SmGUKR1W/+MiY0BhisUf6X4MW7sYW6WaIP4d+cnKFSsqBaXKW
9Czx54yhRdpoQSpBQCpoejjP3Sqgg4KGuZknP2s4+QTgbU7V+PFQQvnRBQDehB5vo0ML/7kdIeTA
YrG8N/RSxIkA88wvtmaIKwYTVZJhiXm0AKIl+uuTTQ9digSB1PAKA9DQ3Ja9dCsLnnXazsChRVDM
5A36e4oHaHHudBywIbjwhIW1jApvaHGcw6ZossJHll/SRJOsVK392siACo7XdR4lZRKUmBqMpArL
1epQIIa+PG9hqz8FUldgCdNagOOknIdeYNrKx4puFV0aUyvxCV3FfhBhwyeCaZVWax10tj3iaw62
V9wN512Sc90oVX+q37dcORsM3Dj28xQjkBPzw/rsKl/ZFQg43o5NX7pZyBIpQlX+sbjIvWlcPG54
+I/qH1eZMlLh6of6XIDVwDOuruybmLSJbGSAGUIsvvB0iKW4vLwzruIkNrgU+kqAoyRBCM839YRq
p6ozNjzmeQMYvKKgrfYbybyUwTb6jb3Jk61W/Jyh0l/iRKVf++datNfkPU5O7f0Z56TvDUbOa9g8
525lwxKbtKIrxNmwKLinLdrmymKSSi0n3uRCQobRm0TlLKjiGbf/V/yr2DJb1X94xTiMFx1ATL5H
pvu2pUkfssGcgDOM7BdpErNkuX4e7dJWzqe6LflO9DgX3TqTZmbFw2VE4EJkR7c2lwcDFjV2BnyJ
xqH9q/6Samg1qvJpXWhu/XjOaHc6WpnKIPaSk64Sgu+fqGGmKiV9JMLNvTykANY6xQ1nF/CC80pk
F3aOiE/oCgSOJ7c3gfuTUQ2Thw/xpz7ZlzpG+rhZSs7OFXHfVLk9wt9M+9cuxuudiyTU+7aZw7V/
yrKq47FpQ0WlsFmFNCu/acafket8IdySOC76701vKIOsaoTLmDRABWPu5jHmykSk1Dms/eIM2vOa
HTA2ZHOYAD3pDhuUCCwe0R3PzUIRCMRx9Wojvjig+diXg6/1wSA7N+DSkGnxPmn1oyFfbk9HmT4T
oQvRu2Elsz5fDQMj5sD8KRIbebeWPYQznuoX3scA1aY9twCY54K0rjVjAgC0AB9zwKkqWmenFzG7
5nIpVSdJnxa02CsyHMU3PGI9mBYnEc7gnLxv2Y+QEbyPWhcynTGibKxSVJKX1eMbDS6ChE6nALxs
0+eWHl12m9FgWCvIal8vqaDsyERb83mJlwTnfuKRZrVfCg4ziEtf5nyZb83KrkvqbgiEr/x7b1bm
noHrzc9nX/vP56U/Xiui8fMZFsh0rckg0iFcK178WFbrYZiGPLJnYigVYjk0Qm9P5uDZCJOgAmWZ
e/KBwGmISDtKbgL6FikQ8CGpSiH3XOVC2Rx5E0CE4+drYWqlQwbSnAMJyk8ITWvbEfOPDATIscyx
UMWI/AO92HTD4GKXMkNXD1wnGcYFOKiWduIw/v6nTl6eehMDkxiSyfwcvYfOhgYSi2R0cvTmVTVt
wepo61DIf3UoUdLf8XFOPiiKHH0eRRF0JxmBe0ozFaMJsnICYei9g8mKM+pg11ILoJCUM2o3ZduA
ReCLIt2J+gNKKbZELvRURHLk/+wyHGRwMXBLnJTEJqZn/vHPqMr+ccRaMkAHFBK872iWyTJ6plMb
DXppF3ppFR8n7EsOID5Mkyv5N9AsJnPfPQ0TIWPo9ncq1MKqAsLMTfJHSVeGFDSdBK7oZlDxIWm7
7O7Q/booR7rFEfd9Pr5nHz/oXREB1gEKZmqViU7aI8Nhh3OV9/ede3hS37e/H4d8pbCqINw/bmjd
C2q+4FYjaNLpLj+qtK1d0lIZp4nvvjwGp8VLvKq7iuDgbv5m6FzLi09qCpYyQy1OKZ480E3zKoZL
Vf0wnlaIQLj40uIgozp776/372DOX6+knxd6XAk3x1kosHeFXHtBivjvEMYUX6J+Ql6r9UNEWhY6
Jdwjy7+4IylH1DbRLrrM9xbPZg8eQBeOWOkdmknn0QlkByXpFtaSaovgat2BP2r6kBd/2+qrpnFF
9rljpi/A+tRotomF+OkM5goY2AKvXjj/SNKgKnBjS40R85B0OEmTE+YjzjzUUMBy+ckwy1qdniTf
GQNKCuCqHbyzoVg2y0H3KRdR3Adt2SigkOw3WyY8UpWsGynnWb3jqVB5OGedpredLxlr/InoCDOO
Ev5w+ccQe7DntI+iO07m24p1qxPhGv0ZlO3AsOYMk+QUfVgmY297HDVeNQDhBfp/PWsxsW3ignPE
sI+ZTf4/SWxqp6lmkT9ioGx/rBsidoXVwRPPxKEoE/cgqb28gxnckMQOMLgjL5OgGZtLNUWX8Q7C
mKHOJRQ0uErcWXfKcrIOG4occAmcZvlTNETt3gKvcCt3LwQQyxgwGN7JBhkdJmAo2G9oAMkbYkjW
8opMPe5kLvkqa7Zj6Z27oElG2d7d4J8UGytapYc0v3nm4WmejtaAv07x3juRZoxxbvdFiAxVMm7H
h4+UdgSM8T7p8+hUH6tjDbi47AJDQvBus+N0CbV3/ZciDDtNca8D7x+PgqMdTWc+QSrvh4xx+itM
AxFQ9Tz2OWepgmPEJjGBfHLYEfp057KDiB1yMYo1zwCPysY0PMKufXqNUjtHLKVM1KPvbCiUuwJ5
CecJyZ6ti+bsjD9LFcFh0nLz5BF3UVtuKHR0sivHkD6GK1sICUP4MraEZJCbGQlG/0QjkkrgnFiI
NIEIqQWbDmWQ12qkacUMiZxMBdpuonMe+8iUpz4whyRePBK7wvJettX1K80UsPUKr1+8No9TPP1W
F+DoNaqmNh3cx2EgErtnbwqX/U6VqZNRPKWZiEWxc2y1K1E1NNohEoFSDrXB6yudaGqzh5dXO9TK
jrXMAfhXrAiUf8WH0LuBG60JMZw4OwSur1VBuf3gNwy1KLyakNWMrdgZ9xTG9GrHk1kdvJ864LNu
FdGz97B0IyBVgvqwnfPKgXhGLOU6nhgCIHFDZihzZkWWoL1TSkHqT/hU3lgeQq1iQE/wKnK1m+d1
htIjZiNKB80vkf571XkfUret2z76SQKs4QfJTfuiA+UzJETwZmsZkE0Ri1lgWiTAWWWcOndp/OBu
s1SUgib2yDRAX6Cw1CDtyhcJWXgfzCHGs/N6qa1cAjkj0bjqkVfpFERYjXT+gBI9b5DayOmMGe1L
2IrAbQeHuLexW3A6XWN5drpAcp3joFegJ5EMbRJxGkgcN/BuLtfK4cHzJFBK0xPGKA303DHxxlHS
t1jZizyM/TswdNAb33Lb34NaSI/+C38TYqvg7mYAYNWDQ2oU5VsrzjuTKSx/iwllWOjJ35apf2fx
mD5zjQXm6H2vC/sSh1zcTIujx3FOTG/dl3MQMr3PZJKroBbmPRN/zOFvg44mqqYaO+IZ18yxFcNO
X/reU17VaLNelJDYVDP6/gNwqruGgWToPj6t0rXQ0jBtnbiCgeI+MMwGbwFXY6C62N1zs8RLhdSU
X6P4DUV7pObaEQkgPn+2twaFb90hepbKH1/RkrB7rPhU4XXt0IZTMDXQmrA3tUnU1Szll9HzdwcQ
MwcaBYN17GftctkCmug3jfbIi1VRpoPvCeuDWE4yDfsmmpb5HaXUHt6u4qGFfdCO6BBLETZTYGgu
O8IWGR9YZb8wn3SMOp1en5kJHukKry39MLrG4J8QDuKTpa0lmRGL71Iwsfc4pfT+ydwsA88O1242
qcN042YkH58fFSkC/NY422npvNoFASk0xH1URf+JMbyWI7OmZAE1VxYw0AggKPD+cSI+o56dYmQW
tlThrdNTQ4ovLqmWKmVOkBK62PhZOXODaSIgIrpUkrxvJHlZJyfDgF+hkrFzRQ+sL7jStiKVWHLW
rBeGOysPejRVdtjRVlSZL7pNB1RfUiubyNyStGMdRrT/MoN+Jq4ra5HGgb8msyB3NhY8cCJDKCIu
pmcITkNGL+tnUOfUwXhjLQkUPTx5S06xcs3GX/Xqwko2JbPdZSQt2S7Hey/goTUze0nbEoWmN61y
+ZqKSIvJddzAXPXlmfPhkK12AFWsyRFzH+etL8r86UXfNXab8+mwfuT87zAbCWZnDMZtwi/sKIha
RsCKKFunqII97a65j4t1AD25fCYeMOGfJe3FWD03fGee0t9otNbX3GSG9SPET622PpA/AKdWCDNV
T6gTAwpNSjBxZTQuAQgPhTUuwynFgCSfrv6H8/jsg4+YMQyPHEijF19XpsUA948PWxPsmxNlScRV
S7GFYEkD32JMDjjZMSff5Kn+7EjhvsCRz3SoV7sxo62eRPfoU52vqY1FLON0kTME7qL2t6kI/lK7
3bUcXthFpChi4L5/OvoMbdK1L+3C2z43mflS51a+4yA3ZWLuL1whpoOzamMZU6czavo1xDgsVXep
v+h/9qAXnJSvMPI16y7CySUEwENv87pIBCzCS6onUO7ecK7rdssLG9jba6aucGHYEjVOi2AjUDH/
rKyoW0eWlsEVTshx5VTCVcyxHlQkVcsGaT4CYehStgXGKK2jG1RXvSZ2jPlITxAu9tL84IMnLMhE
iqE5x+ARJDp4slM4JV/gsD3EV5DVCHR/k/HrnAkx3tWJ3qpZb5b1Ot4/O53juMfnu+tXqawoDY/f
u0LJxcT+voo/UfrieIjDRPcdkap5toiSZ2v6mDs02GErRBYP4uXkVyMDXtzykwWUvlgNhqwkIDTc
500iHdz3r6oE/3f84Na2ZYNNku0Ods3LaedtpIcvqFynPED/HMYeIaZ+zDydK0F3BTl0x8mhmrVc
qyhb+GBzY2stiJccYcwOYzG9qrESpqbY4HFre6H5Uc7nf02tnjwAsw3zCpCA+6swt/h5zqxm4IDL
M+bnMPVPrwbNWjldCyYgHHsCs/11WyPm32wTXqazrObILgLCT2GEyquWj8CtUqfzzZDBk9pXp9IO
uGvD6wUgPkZeIZje6G/SD0aNeNbOI4iZHtn3Wr0zmlgPWwCkdVyDLPF+VWlTp77IK94Bu64KRnrK
xZdnJYG7sRo7yBSdTmsd3Nu0JuPXo+W6Vijf8pfCThZtkIYXvxlFoj/U0sYp+3DlXC/DCffRFtHy
HMFVvdycWeQQG2u5pryrT6f1xTMs8HruJu9IaHegh740WS2QNBDxyxilYh4Se3Dl4lOsykuC5wBy
CZDwWssJx+ehYnI+xDjfegmA5uZ+9RU8iEVbZP5u8KN4BzQBj3+xZpSvdAGWbkmStkoWD/8jKXYV
IQhypGGxmZx/A/OZm/nO/vWjtLDAc6OdQ+sPHfIXu5uTqcZk+G/eB4ST8M6nJhX3utASKJm2JbN6
dTx6yFiD11MYh1G2wQTKfB1MTTVEtum6uWY/2L9cckN6ovEANHjSSSCd054x9a9cvSejm/nGpbka
dfUDZ8bNgtKxhfCTqGncmABZUE8bU4E9FJMV1rfVE/BDjnevK4hQVfZETvl+7dcn/P9n6YfH5mWi
/vA04CkGTOFT1QFh+hlW93xOBDBbDD0gs5tEc0S+0SDRc2YTcatf9Mli3ZcLgABq+o4sF2kpq6DU
rQ1HNUNZUWU9m3Eg2wy1RG8lv9tyLo5Ky+VDi1UgvMICj3AM15ntSf4kqIjCIxuP57cuyq//9OlJ
p32aY0a0YH8uFpzTgKCDQb/18xMrYJdUTmtjFZBed7EnUswtEU/dO2rHfpeFbV0EDpMHuTB4d46y
N5ado+WtnJdL1KAoUZbJIVBWkqhK8/Krc8/rCitumyue5PCylapXV8IRUdM0f0vebnwJbow+TfPi
WlQ/X8TGfNbBSZGa1acHzZ5NRA2bxlcidFgIJZ50x38h92m7WuztGZxz7sr4KCUWxgmqUrUXx/vg
XDcBN00TQdDYuPGIw6Awxy0nXmIkmAeZ4T2c7v0JuUo9zZ9nCIYWTiPsYgB4wFU0WSbpmskS5lhL
N61XYYpYhx8Yyu52GVOkphLcy4J+NE3Anz+WZOXQGXdTlPr1FTF7ftK/rS/2aL4xo0liV/ldUSi+
iXpDo9T/c8viY3oMkZ8zd0Kco1EKS4tDbVPcD/Q2ZVAUz6tt2rxv1pRWo6m3wgRnh0wBkLONUrEZ
rNfZzRsCBXtX0eTfrlSWDU5i7vt3Ivvwb39ABYY5LJIv9q29bzsn2jyMGDIG1dI5Nl8z0mz255lb
M9ge2tFC1u8pIqj5tM0GCLBzMTWVo/kN3C/pRkDkmf/eXaXy8+ccL7D1h9Iz7F6PMZo2S0L4rXoO
RMOfBkA9/M3k1eZvOieMIBnkyoZO0W36gwmLLbWRt9wwl8rAKjjN2vPrrxNv5NDJoY3FYBppswuK
+9/u02x8ATH0MrvbA40D+goUKA5+bQv8+kLPRIHR5t4fCEHMCNFawuRa/gTMr9Ogl1K+a4s+1K4u
+RnN9TrDgtiypYJbPaN8gCvT7TLIZw4V7MrLpTKp6dcC8jziQNtAEkpK5T7YI8yZbLXVd+tltepw
DuOeeflnt5LpJb5dzR2372827b4lsLJEirVsront02O5ZwjLDxMwDjTCFPH3dmNvx8q5LCDhPH8O
ZRitGIpiJcqty0mRndRKdmWb0Jws7oTFlsMheONfBhIBTAa/sgMOAdLXNn2zeiJYs1qPP7tJ+6Yi
/zM0bbo3TfAyHSgjIBiba6dsfQdQDWEfm1eqaLMPr7aAVYci9ygbcLhMskLiDgmlVNbWpQXKROOg
E7ENQwaCk91ZDJhEQEqW8HQO8EiunoSx8leuhDEcdq/6HUR+2mLwMPdHa1g1lUWp7xdhLaSWULSg
lkNtq74JLhbrmPhpSc4fhXpK1B6354gF7AaISnVRF9MOnzvyNph4OZE/jlgktb04UnTT7ylAPFhF
zVnh1kqeND5IrIyZ1JuAyYMU0m8zVm/1ogH7/Kd86bScMGsKHFLgy0Uk05/mHbrFoNEP6T3rdGyn
Z3TyuXLTZ3j2fPlZljulV3kRngGqEdfb/anEqmt+8UlqxG5O+XI3N3jaQZvlK4p0TWHNBhCN5PT2
BQ1M5z4bkttZgfcN4eMQy5lOkefNLDL5G4WSkU3dykwIQM8GSo0qeoNwWQRmYCAa0jpzF4OEKEg/
VMSImE4XJ3firX0wpkzQ8L8cQV3aFL6e5IpMkKD/t+cxSMOCbD7f0kdHd39NWPAfFLgpTnN/QOzT
fPzpdrLA7N6vdsSf99MpjSBOztKsbdYukj0DhXji8+vK02Yema4W2eLS5KRkxM0y11irJX5FRkFR
b9kuS0Cp/WDdO5LmtdCrqvQGfBLij1N1+nBHR0wjmzKDOllOMYKvZX/z+vQA+SVwnIii/THCDgyU
h+os/I8X0svvxZxbMhlX9NWG5T2ZzA6aE4pX2TBfGNwCcmEg2Hde3PeKaSeukzRhqGUrfV/1P4ZS
yvbB8HXhyT+kRInQU0KH+ekyB7bFFg4ULYtbFp9gT4a7T+q7l2oehVuBj4NpPdqnrdhORtyjTcon
v6c+jOlAyGfpjqRn9xzls4dZIZSfq/b4LQy7hBQ2Dc2WVs6VwwRS+cXbmwA8aY8NHVJvS5XZbrly
fSFngIhAYtncTDA6kIuOqq5H8h6GVL/MF5yTN1XaGR/aAs1mdtncK2AZcZPH7arMSOm/mD5bMOaJ
+evbAjQEExHoqlULrugN95CpN5EDhp5CsTrKDOkjFBxjbISxgj3aLfvueAqzXsZcqRTPFPNeTbkE
PvFBh2AJ1rTVh/5UjXhviKSvz3RifzjZItp6Lg3icdFMCYQjgF9fXI25QH5srkPOJ6L1f5jW2uwU
rR2wiui4cW7evb4YRqIkfPXqMdddk0VictT1EK8jLp/tBsNm0AEMT2UFS0/vQ9mJaFNzJtfYESRH
wwRhYjzTwpBUNy7j+LWlevRg26oHM2D9eLBtXq3bYsqvlEnhYkChWihPJtsvp5QPIJfgEPSPjask
9RN5Eayz0KEYWHg1wvnigEyEahJivqNLD0O3PsqSELvLuZPuKAl4ZY5vSxlrmVURVZJ++kBkQjwa
TJsXVxGbRWq6LESKF9k3ad35+y+moXzgUXc0EdE8ATqfztg4i88S/AT0G5coiHjgGTsTqF8wvK/M
TgR21M/EoPL4QB5rXLrigcMxSwSZYAh0P6Bt73bOz29Jio4LLYsOkrOTk8aI3oz2tDu7Jag9Rr4x
37ahuoIzt51xk4RRBVbNSUhTd91BlNKfDPWW+eHmOoFyzNuSrde4rhuRlMIZ392LOIvYlXq97Fy1
+ahxd+AiZgZKQTTagppDdoJ+aTgTPRJSx/UIXi1NA5SPIw6ZPnsum1XThh/63hVXSu7WrmSP7MKd
ftmiKjjYQ2YDOz1g9a8wrCc5C2DvvIMemd4vZqVF6vjihyxCs08ClO7h+xy4R/hW/jW/dl+hCFQN
Sh2zW1CdsTvgeVSVjRX1rJHomqRojfom8j89l5kVIg/5O+Yha8Nyg4Tg5bHxADIcHL4z3w/9Lr81
u22GZ2n9CThIt97AkCMOWoEZjioLg5QFey22Iajj3Q0YFj03Q8gJ1HKgcvb+404v9qa79QLqpqdV
L8B+5YyA/uSD81pOpWyf4MX3KHanyZRGyuTdzd99WuDI7TjO0hhYtj023kkYX6IvSVJMjZzw4AV7
F4KgXMJHGJi2iMk8vTvU5hU32l4Yj+LeHY2Mk0ovtLEGUb3h9FyAh6uRh4vrNr+gJWBniXfDqQDe
3aXqxaNF2oaqBRyduXv+VJU6PPqXvLIvY/wXQ0gNdWnYp28814F8cuCsbWoflBmuz8G18AUGL4s9
BBOKiMPJbHF+RFeVYJbT4HcaHViR8ZVUj4DUP+kfl4KYJL0q5MYQrSyLy0tHIKnRSMpW7kJbr9xy
GllmaEUqAlkst3+178X8be4jyqSozHPm09Gsu8R1nu6T7daeNtMSnTGWnnVj2uMPF/STcXatwziF
FGkwGO8aa4+BQpwagvKJA/n3aM0TE5DvlE3E9x8No+fAZrq3OK5g88rVnBye7nww0RUmISGpxk70
t9th8JxUfsB21gU3elyP1KyMW3gu87tH/pAEjsqedSNPu4gC2z/QqU45aDuaUfPYjUunw5ouHOTC
Et5+GinI5WkK+8mfFNJFBpiTbTbNBYYpCFsimmvVf1jyvVEZbCcwvNfnsiAaO/aH7opMQoHCWYYe
cC40ip10UqW37Kw+54LnAxHZiFZN3OgtYPA+TGR3+d0szK14YI4CZaccadO94UaRzoUCeP2JUFJ5
9SkdxR4jZTsglD1Ls5kcfa5rkb+UybM9r59mJYafhpGZJ0GQTOmHmwHSr5MMqyQ3GdT0udku1rvk
1dlzp/yK7Be91VbOxONOhK6NLp2T9hIhqjtEAHMLGO/kgnEn2ICL51C2S0KnCKUqW5IVfFu+Aq0P
/HIL34srOHcwQIZ81zyADXIIBzPz9CdUTDl/KTd/ByewH1MiP2trG4bqQQ4EmQchYyGs1A4shOul
1XR10/tkpEXMWf2PKRCBfndL/kGbeMLHrvRH7in9WWtfDRMLEcEWlOWUBMiVvt6HqLthIwNTFdM6
0EjB/raQm44AFpoGKnX5DqZTTMqX7tqaAmySxjxzhNaeHBSCvSvhtaYDb5/3burG2dl8ZilH+NB5
meDWbe6g6NgG5kBK16pLZGlxfDdnpm2isoH9TqXIjudDtNVQsspAgZh3A1hgasTzzxcRajSdWWMT
3MggwK3/jeJsUFaoJVQXfraDmq8tCmfi1bQdj8sJafa0QlhGnEYKIvPeDKGK6rwCt6hbdjKiACJK
CbAFtqQtUWaj23voBw/fzkq3nu1C9RcHe1FHUrDmcZqLb7t259bWg9V94SQ1ID/Hsnwv64ihdNbj
qHWsKUuYMpcZEPhJt8jIOYfX83MrKr5UiNgb3u5ZV8k8fEw0Am+MsDX+K1KogaetBwkmCZDunKmx
n7Dk+fcPtH+FhZKQTpz1lQCOJAv+pI7kT8Vw2LqIbD8jdZF589i7aUh8UQSY1BPGm+9LJLcIgi1c
H3VQAAjopldmN3o/sO/mlvcVPQ10ibd+VZyCjfsF9pNU+f8709PcIYpNRAuBxC4tsmcWAchoFRdg
6sHugGclIiE/Gptt3xs5JVciaXT3YQNRcgOx0WtGjKl7AhDBW1yHtdceoosrjPtYfuSt9kcS7Pbo
jfFFe/BwUeWiPxO8GjTEQ66ep8KWBy/QCIxNLboAfYopxpegQAfBRVsm4qJMtSmfZCMEi1wL5iHX
MnNjPR+9HKE6g6ccKSvB7knnu5YIN0Zz5ju30DMTQhPTW3fF9gJkh+0wfG5mC1MYSVjzAuICtN8A
C3DUJmcp0rxJu+fcM+sxTNzobQnftQyjc2wlwiOXicc2FWYFlB4as5z7WdCsiWQAinGuIxVYcOai
nLh9fCabveFgkJAqAJS2IFmxg0QJmBm4Hw/V+55kC456do0PueFvkkQwptX6KbGLKLi2JWhYDSN+
aqlceA3xfop9N8O+P3Xc1rFKePdisl5l5XHQ0r/IHE5m2rHVRi5M0KEnRHE4K0gWcqkNFamip0ID
ohGGsNOFwXs0cs4ZgEGMsU3EngCbVYHOh7MfgstyRzrnuq1vHT/ZnGetu/6JlJn9pdFYyqnMTVO7
HrCWnwcyXVSIV6guGHiKngVl8IOgucPQUwlqiqw0fMirmelIGyO0nQgWGCGerXC7EjMd9Iq9mf0y
W8bL89QDE5AWj+wzwpd4LC2wayT33P5/EDBTRggCMlMJvrJFiJObfZ1VgMWQCdgp5WkxZuzpIN9Z
qAe5FjAZK2dzXfhHCaospzVzCZkn6oIgGiTOtecW6PFHEpYQ/t5fdWUsJwDm0+xNdzyGqNToS35h
1DdRy9YCUybitmIRkLS2jcjh3UbE9s1ESp9yJLPkbFUXFyPdNkgQBGhXMq5LA+vYC8ywb1Gata9g
1Esdf2pETQtAq8J1Ube8Ea0gAo/0F4P+XHYitssxa5wZBNjYt83w+hNrBNGqWiDEEDDElM5P9RNM
Nqs4PLDI7SigvdDFrcfUUo7n0rKifPNREg9dWM6ALnWznWzZq0IWScHm62bds01YIrC5hhMosuf+
StWPrnaXSrkWDBxnyQXxgK8sAr8cB/euv8DOm++S7+DCAYK7tMm+CgM/WICwfbjZVMccJAispSZM
nnJD9tYqw4fpLahRKeQmJ1zUad3l+onWlg6E1JxyNaFGqbNv1jeJXfpiq3fzo+/H3ws9PF/stt4K
td8eY1x0cukLIM1lDqrLrGnwE0sIbVTdNEVo2X6uGoEGR9xvp7FoHpWAo9r3pGKuytPGwFVuIv9a
e2EMI97s7PnqS4ubhU/LipvU6Tmv+ylzp9STP1iBSb93FEKJ3xMW45X1+3+HrC3cGpYuiklq/xb/
Nf9CzFh+B5s0pRSunVNrcwIsOxmV6bah+532LycEV6+nNkjHoyvST5i4Iyr2bDMUPPmZT/m+Bs5K
2dh8lPhx3X/jVlW6TzgEx/mwdAyvQ95L0hu9kqj2MEFYn83k0aDubcMRQXRJnAK3hwb3fc2+7L0Y
GB3yV5tOkTmCaKvm0mgD9b+t7ZsLm4AfP9L2kEcyWp97HKHrFpbvTS4UzfEHAjWggSl0/5japsWs
3rn4PpQ5SANeDgBTZqaXdbVjsVMq8XtaSztI2Tlpc6UFyeQyLmiIi/MAxXBoYY4ZLWef7bFfpKIT
d/8yhrC22xrRaG4smMc81z/khkgkWlxmWZFNmdafOROnWoZd0aXiWWzrLEq1OJxTAKRKsrAQ4ZdZ
GzdeJgqOlYHGlOE3XOfR8D3ky3HvH/tBNbQakqDUCvO5RJLG+JAdjInsZ5Z7BDiNwnhPsHzqbk5B
nks+h5pBxiVviDGxAW5WVtH2hnHKUspTS61LyloxzLxLJgOfdU6YdpKwkyDUq7psgHP4cRjIkES2
WTsQLcufJZJQ8IdlInqTmiHzcIDw1LhHzcq1sA6bDwFquIjh3HlCDy6kAmbRWJAOzOutdOalnFpZ
qd3PJMsNn7AVN6DN4xRoOGg0AnaY6JxnNA4/Gs/rHIM+bXhDivzOmjXPSxiR1iS/BxQx2Kp0W2LH
qRQybytqN6W9CHp8BQEsZRggFasH4blKMa88X4VWZchjMHh12KBDYRouLBP+92McnwqqWM7Hap3s
EyxHYqlav+CISA6hWrmCWU5s+Xi3s1ZUxmBVKVuNQMoIqe8SV1+dmtkb+Sm7LDZV6zz+jzez/idT
JqApAuIB1Rm308o3cmKjfOaLXLURYum2GDoEAJoWJgeNt8bQyqAVDXZ5WYfxCQg09ZndKLCOtxRo
HqY6Cib4xfJ+wNNUgHSlymF1mch8RismgLKyidHZGypICjx1+9/R1R/pPUc3XI9A2a/d56gq8W1o
+aqCVejI8TN8oIcW9WJmti29cXO/Jp6msDCEeHhKzgAl++3/sufUaK+ANcSseajKcn2i/67vFdF0
xrC1hJnEy7r8QynRM4boln4ziKR7p4kRxNokLetaeATSB/g6HfEvLptDq+5igXqzydQasxZ15TjK
fGniXKRcxl84NU7w0JHoYcETJffzI2QC5u1JAegs3VjtUZWYQXSnGr0p9w0y6I0eOlY5TvD2N0RB
+9/gwmrceWbTCaOORzkzFEzid72nIZXCokFE1J7OXlZio3uemw8KjOOn/gf+02RQ/Sio09+BL1mm
hwhfoFL5rJGRZuQ+b1l4jaXhACp4ZKZzC7j9Zs1a6x87EP4fwBYGYu4q/urOoPGjz+7jRlMEIXbM
E4HB6ewzhApmzo9L71t+XTpKhKs4IT69Usy45ZfjSykdsnHrZaVWgLSAenbwtCJec0V4DNZTUgrU
UH6B37bBp/b5/lR+yirUpq8gq3rDhXnzsJzhl7ImWf9mFb3HfD3yquHgZI8RzmPDyw0cd5QIgar0
LxiCqf5TSpuXR4wzZTz4/CPyW0f0lgul3LaYwYKgIMt0bOhCyxLfbu3r+Aunghyp6VKQHomIYkH8
Gnp0tphSDaEz22ou5qvzJ/o2Z3Fu3Dar/vmfmhpNQvOTw715WTjUOr0Vvze0Ows57cMJ2GXOi/ni
ztRXgaLo6vRLz/I680pHGNrqQUGwf2faSYJrI+Is7DyhHGqfYKn+1DEl+GOAZ4y/10HKLrQ6GUG3
xrYmTBTw5FTQ7tGoWzyanDM8Hc7O+O0dKCNeWanp9/WHl/cxVdrSIOG0wZ8ohE31coTsWefTG6rx
tqs/XwHSoRjw8M2XPIu0fOBGgl/uKxavvNaTyH7KGpnhbgq2smvOWKP+JEc3gEWGxaUNYaXFL88N
ojsmkgrS8Bnph6VssD5znJZxgItwwHqzjLBQ6HslE2bB0bNoXWX12qAyT/pGvMs6mk6a7WFsUtx9
Jr1lJXX8Cw3cIlfHIjQBctt9PFjU+caJz1uNN2iAc7WwokBb73P7cQGgEE6BZh5ltJtAPUWfChtZ
z9co5c8USRzlKh0649klmKxOykFF762iYuvafKWpKNdWQ/UBDtYl4GtIv7v/xVmUZrcNxV6+DHGH
fUC+75O+MSkkwJD1M6jGGdM18gxqKFR7YaQRVA6cK+kBLc7lXAJcu0CehR55b7tgdxPbpZMGt06F
H/aypsSAFonn2MRbn9kNueQgw3dVo35FtPH1xJbc5JB1Ldig/a4d+yXj6kHliHSLlhtl+I5SyIV6
9NNXHOC3B1CoVbZ2xkgykRA42qX3dSwVdVUotrgDZNb/p3vCsKaQ+h1Gqx0DhflvlRhjIoAa5gea
YfBy8J84xNAfSnVbpAQKE/9k5BPDQrXx65e8InKUj2b3rAS8o0rZ64cq1eVyi7aOI7s5yjTPd9k5
sbsxmJqShf0RSlJcFyr7HL4fz7B3fPXip7mBmGwbDqAXcfZTNBtwZtfOw5Lxlvz207bGBfis74zq
sQnGoONkY6w7IygvENV71UyJxSLQ2Dgm5GE8uhFM11gW+zYbUfe5LauSPQsOcfxahIJySLJ4k2zP
Br87WnizJ8yGbgJlgxn33ikVc9r8lSyRa90rYjExr4BhAlsxtw29vVDXdcKjai0IXJ2D+EF9AWNY
Cq9aKTySrwTkkv+D8cUrdm6wFLoS6Pi61WmeChMY5DEOYO3pCkkBMwEMTDIodlL2W6piTFYtsCIx
j/eI/s7tJeJvPNqkiMXk598Oe8Py3akihVm7Smc7VJM8uCvx6jBKX6YqHrka7rm2bJsmqlsMp502
a0Z1CWyCP8/PAv7ynABEHDeP390gWU3OOvCWsK1pRWVxpBod3VXh4kE2Z/HPpzx5EGJJOIv2rf4D
hJwwuCLQpzl0Csipzkg4Fh+RNBT0UzJJMmKcDEe5rpWAxY/n6Otmu6vTY/JJ3zmtS3oDTXzqrRnj
VtoZZx6ZBauLdpRS+dFHf2YeDyy2AAj+0pPQkviKI0zgdAJxExXYWno/egivgBQm0qCtwMDlICpy
u3iEwnE9/Ad7/1s0NTOeSz0fc6wp+Gq9fb0Y0B4W2bind2BuBNQJHL8cspj32IAfWImUODLftXw0
GhMF+iog3YAdSQrFWT4B2n+0gH3dcVNKDpfEFbLLXMAqSm8ud/sLJZz2+3PJlhAgFvGDZuJ5YzBZ
QfeGzdefAYYIbNUtqqwLxU3pPxt3Db0LOKQfj1nVeX7H1afii+bM7PeERBErXEnJnOHFtX//GT70
TNLcpHJbKXQGxdVXbzon/S7FyHsDxiaXvil2veZiIoTtVir2ib3pzjX2X4/Df9zP9Zcq+brt+aFw
ma8TZkg/e7CQj/rVY8Mj3uolmU81u4LGS3hsluY8/lilXPShypkcb9RUVmAfVc86e/2rwEFCR57X
RB/kwHzy2QTSdAIEz2tBBMCcyGpz2Q7ceCPA/RFE7sfJdxMJYEL9nneggmEFq9tsIRPeQJvhPKcj
2GOrg24KMywZqRMD50z9MPIT8wKA9HCy3FSPNzLTKLVLOKOTIuY9PX0eOEVTgQG6YlSQGtH3wRA9
0xEVtE6Zu0Runao2q0wrArJszXbcePo7ULfG1ksoa32/grSENZfFQZR+NV52V+kj0QAKYlFql/tf
480X26uYC3tXenAjc3JZ+g0kz9GaVDspFqQRhZgHLrH1dJbo2Tq1yZfFIMWaFNOfnJy0Qs1QRkUg
tjcI1xYXAoCgJrhBbTmZ0cPh82JwQ52v060CuHeiV4ngI6vM6WT3nVpdaujw6skYtT5HcrE12mvC
Ft9HEn+dLrIQCEcrP2Qp/7DdwnPrwBgAt4CmvFaR5r4Ucbtw0PN43Wgs7fL6vRgCrwXZscjcdwhl
dMx5tKGS6EWMMrZzRpmkR6u8ku5BriDXcCCpgNOOkm8WBzsPnlGS31LiAwp8qCqZa/YbHVmhf6lR
GaWFjqm8hreRMDQj90p9SS+gtzi65+y9rgdsBvzPlfF4AyFwAsR7QKBDTzGplMoANbLaI4LBQUzf
tISIYvUUDYgEdBmF/GoC7zydyH8y+ye1AB2yTdNFEZbIRP7QnUNwZbeA8ZwWELXReEpDhvj8SHJo
VwHIIQ7id8wKzF6RN8//lf+KUbdKvS5yw+nRY9MGuljm83FytmfD1D2bk85qyeJQrRLwQu7E2qWT
GmStaOWQqT7FOpz0EomUAIRkSvrB64FplyDAjy/hM+gdoX5D7iJv/lvfhwlhusEYYMBcc1B6+x49
mSpUCbDrW/T5IoUVnJMbghhAs8GhuDBzje3VOnXB6r2MWlw/buWzhNBoWA91PSfxMqYtgLpyu6oo
CUYxRUhQTNd1fOLEl1kn1Bn3C1RDRM2y/YgtrOuAnxxAOU+8FIqmUl8hoPGDq34es8qKCeDfnX6k
FW5cjrmAAVXN6AgFwD5Nsfr9mv3vz616r9v5YjdprucG5iFzL/xDD1oa6ZUKslWpdhuaVWXMrA0F
NEAsqhOKfZ+v2BewK8KOOntMKGDfrKkTxvAJ6kyVFmZXPGfjHt0n3xDZAngObBWSktTnIwwpVWsr
K/fIUFz2lOginUmj04XVlKKSFwIi1RngvTNjPqUna6ERPmzZVYCq4luYuBS4VazuenjCEmOIMzqr
PGEjWdqItieAIH9TW+Qez6/93GNIq/wEAgiwWNgRnI1OlnXt4U14XLN+mey/P/+0tWSTJ4G25OZb
BT13DuF07mtyDAaENBiImbv3oPsZ+CQlP08rKZv6Fst6GcimmY+zuTlgzVrX3YPMjnMXjp4FMJS9
c4XI97xeykCXiDSYfC5+O3pyWvocp/M2ZxRxniawH4DLWogL/VYaHlv8bPKS3ftloF6j/rup/JKc
UdY38jRB0ET9IEhq0ItUYP9K1yGm8A7dhRLSOWcb1uv4FD4a1vB4JxdLm3NpXqdL2BByxHDDQt8u
sbrqnHJn3V/U15ETg4ufJzag1S4VStOuS1D2Ey913jqgiTzXejN+KQFgQyn8ftUhYBQmrCJP0zct
Dqh3Ga6UD6HWik2lIKrwmDhepRYOL6GQSbOXrOaq5/lSxbYDmxhK6jxjsiC1h3FB7vHtHizvLdoV
qKI97P8BnFzgnLJaXiBee/Cwp9GI5ymbbZNqzQwrOILqpu9pmyRL/HRcHp3gm3ELnx8knHW9CWwF
PrdaGZer7iVqpgjy/TM+TrCNJfEmzUGRx3zgzPx5rPGjkwghXGuDjPYKrwKlkC2GYIqxpTt03eB9
bV6JS37/nOHhJUmPLB0oCFBmM7ZqXpt1Tc8NS64UAGHcQebSzS6Ympm3pOGksdWpU7katPNanKue
zT6NFSkadigg3TusZ/XYXM0O7B5c2x1aLQHUQps0Kg8vihxbcnXeztnsO8AA8Vr1cxYMmjO/3bWq
gdx+P9CcR5XgbuxL7LScjzFWBcb0Y+8BDLyps43nPCGSR+OtWZ0QR/b05F6W+zsgjBgb8PZLw84J
mOhnSIjyQDuylz0ZAiQFJKqeOv8Yo/HKFbqqBz6gU5aBjwu0CJ9h0nnUiJzDPdAk0yfrDucPhsEI
C7bYBoX6hTvrzAS849pHiHlMP1tbIHjNXUyBFXA82VzYmV0awxN+YZGNxecnY/bqSFkXdBtqcTYi
XRYvepmeEvngMG8inaboWjV0yA7chnWIRjl4xT6mjJOne3tmcEOoq3wQhQPf/945s26xaqOvEkcp
Zemg7cV2oGDYJZZ0Bk4vB8dsUTi8bWgrdDL2arKvQNOd6BddemCPrcbtKB2wby3eC3+3/H+UOI97
W2+B1zMUpVOGOMY1SGq8oNpSD1ckJ/4QZp+/6OEr0nB2/JuOOkm+qhU3OKHrcnEupI3/ux6aVaki
OQ67Iwg4GTAJ0XhRYUbKbnc/qCnx55P54f++5weXc6BwmDI5n7I6lSb9eu6Ta6FXoL61s+me+hPe
d3+DVL+DOcAo5E9MrBzi+P9AQvjzHNb45W5fXmmb64nJyszIvnhcCwmTXE6sguYdKAGDeLGp9bA7
NZQyjVjt4wk6OBK92+RbB01FPDGJSDZQJcr9OXsnH4/w+VgEonCHy0lHKHia5gdWETNfa35Ygmip
cu1Lu26ExgJEqvwvrzEsaxM64s92nP31fu41HgBsInaKeBAcmx95WPe9zFuTNzDfKRHi/bkvyi9F
5UlO8wh8lBJNQqQp51+oWlisY7hMYU9vdWLXJ5KPIPfrnK9zeRaqOoss9UfttBGcPUdom+sKGa9x
rElgsxE1qdiBMasI+ooCriUe0KiCaUVJNVmMSaYc0SXSUuGW1iXiSYjlr4GridLNGGXpS5SXokKI
i8lu6u1Ay87D7jvX83r4lWs06FxP5XEOeXVA7f+cY5SGmmK4G5jh3aBeuHpx3VsnW6qj8100cqHI
1HcCmOZURjHRaylCnOUb1r7VfYxMTOlt5Ryd1ulDrPWQQAenV0Lf0tNMeidJrvW3JivJuqyd+SuA
l+4WEbt5JKirMW5G3vR+z+NIaLaQVM43t7OCm3UiE8pDRPUid4SuQL9TlUsQl2Tx46aUTcE9sznL
VAZn0+P/04gGxvbf/i250+TGMkcCtmH40C4vQ0YEw9oDmUuRp4te5BMsoy9ssV/hlsGtffNdJkdM
lZvFZD87Eqh2MfYXRuh0Ys8mxR1NFM8UoQ6Ae9BYicBnrl3GfVlYQGU0yZek5oh0OIO8Veu7yZNT
yMX1CkCxPffgw0jP8toKIibqTszuxrYbzjwFIgcW5Te5r2PbqPFkCh303T3QBfXw5FAGJikBcKsS
DWPmhEoJDEBNw/Ysd4ItEIBogeNKq4C7LR5t6tw60LnX6KyhPJcxhP6U6Aagw5b5fPkeEX1seUob
GJdx6bDQlBahYYiJZ/GRS6kg1CxhHB+Bw8F6ZqRRZ7aDhB0wWdljHshx67zoXVFNRXs/nZ7GYh29
9RwxOweIfCQxiLw0byTIAPEXtEv/AEgqjQps+UuF0IoHlI01m2ITpXTTX+i4dx2jIq6GPjtRMI5W
DCVGN6yVHJpged5B1YkuIAswi5QYxogf+6yMvw47jWxbIrvoptNi7IhVl/+7EOcQrrM4Lrsd6Yg2
aYYqAHJF8QiT7Y56m2eLQ8ivRUypy+zJtqGEvSXT3FU4ryW+kLVpWJxoxkpkTXSZbrTaT/rrJ/CQ
xt5HLq0QikjLdy3jRQzfqmXQdXOVLfp/528L4M3ahy4zYyLlycqZNgzt25RhEsWRwP5asOsRSio0
Le+1KtPDSThXUvlcKT9zIdaj9mTR0MqTCopUaaUnifS/a/f986SFQ/586SAa7FMVDZIAQ0pRAJBm
ZO8DqZdiyh9cQErJgBmKki9PHUmgRjoeFqGOftTujhkjBnxzb15k4PJ8QyUUcA2oWwzppRoYm3Nz
43YvrOXIlk3dd9SEBqeLG/buEk/fKR9zPzLosnKr2ezmjP/Oco0ZzzSGk4n2rO62S2k1QHbfiPta
9yktQ+54oGCJf7DoRlYHdUefoqw/xCI+YjrLdiOVzWK8kbQQ+J24k2PqBkhb31rrzya0LDqH/NMt
R/YtDtSO6qEHg/W92Rza1fnlFBqy2rdV0tXmapbuXZPYAXF3dLIlZMwpBaOvxfs0f1ZXZAleksTY
5LlwuZnPZznsGA9HuDKU0KWZzHA+cjabuwpu1XRq1SEs5xOiCleL9K95pdsyl+T/dSlFvTQ+0J3K
y4sf3l843cHoam4PJpTO8DHx7nYhf7PttlB9H5hS4cB+AxCQe47u4tEqrUPYklszC03Dh5lgqkI/
kQ+uFqbJqpzEPM+LH/LjTggbtQWtAkbMq4SVy6ccrQ+d0zcwScorRQuE+4WUoPqZl/7/QQdi/XRY
4Df2SP+ncKrMOyppWrh9snviL6H0Oqjmf+fIb/vvwmRqR7TuAiPNzKeVGeYvXauLCcXjltd1GAc9
X5GQp9BxRKz0HgFxyNJxC7NFCsGKc4uazrzb/iv1jt8nszgTHk4GXC3mK8ejPf5VBWYm50VI/xz4
pRGFoHhgWL/4veiVnpba9KvqGo8+GIwfgDG2Nltg0EEJj9etMmHxm5mkVP7lrddL1AzbRpU9Sbsh
0qQU2EMGYkV2L028MM3h99RzDgTyOXETD7hmAbnZaFLRmudQTWKTn1tXE674B/MV864rSnl2qtL1
nt3o30X5QQ35Q64p8NqXVr2OhX40sfOXwTq8ymCdsjNF3+ooxM3rrq4TN3lqp9cqEtH7TOs2Vr9I
EriVEy5sIxB6M+pdhZAUr6O265RkJnOrNnXmMC58pC8PRG2S8WnCNtlB45hqAJAxwrppp/QiiZ/t
23L+dDB/sP9S2iZKF1n8YV9v3ASkdRZGpng1x3I+DonHltwffWjuzZHTwJ0BP5eVS0m/gi+Kr0QT
00ZvYe9E+vbqtXJ8bzFbasGDUPyvHGfgwXyvCARXsX02vhk16rlhRH8hxA47ZcSb2bY6zVffy5GQ
jteZcAub151Ay/60xyE1Bx0bTYO57jPAcPh+HXbhp4vHXf2H9GjXfRAwkfMwJkw8GcgKusNloFH9
68O4uC3RkT6iZX/FL9rizbmO7Qu8YeZm0Fq6FbDS1q3U8PDnQY7omeX85eTXd/VBYO0YjrHP1zwJ
gI3547P5SQbI66EUdvI6uYqtNre+bVXxbXd0vTp3mHjTkXrVS3XrEEZd/xcFvxEy4wxGNTv7S2dh
Hr2GBvTbG//M4e0ldN8PA+KtJQ2v4tqPu0ylgWu0dLFDjwfl4kKbtuUwxg0jKeVuxHJ4nv8Xti2w
Lbu8MCqps8XYN9+8RxUxrusz1cB0l+iLo+1fJehshMnQBR41zTRIPEU7CJYNyVQrAWl0a05Fh63r
RwXG5YyHXQBupi6oFSrAq3VMzCDclwLAYuUDjFuKFdwQW3Mtyx+wa8nQdisxhozA9g/SNobD2Hfp
xgclhuX4dJ1k2Wo5BHVXBQgeWTikS4ZntKigsRgKQA2Ck7XFHu9a1vcDO9Ii6spUx+ar+YtmfZ2k
FJSNDLXir6a2wUegy1yyyYJgW8HEuqnyo9TInRSrxk6hvF+D3vZ+plvVwmR8GpHNCxvaVvEIITT6
1REWfUko8RlwS+GIIgCEHxyMtq7ENGhaqbFqvbN0eKbtwn+AIaytUQ000+ncrk6AWWqc0ERXFrxl
1MvgR3LFsJBn6qmb1bXq/Q9HMN6UIpT2CZ65vnii3Og949XH0YCXYcE27jIUJsOjYRnpee5rvfLs
jO6TGBegb7Efb4oloEzLLnIWUQTtGBiTPkYdbJo7OM+hRRFKB+c0Z6E3brv3Vsc6g6inb5pGbyt+
eBJxyAHrjatCY+WYG2yn89hGPGQIKOS249c1uexbJqbjwWzoBvrTnCIOzMMwZLcIqlbNkYEKMyyH
SUQ5+JulFW+ugKvyoXfkqSnoUyWthH4cMtqduJ88wmyMtLzEpAzXkYESkfdXmoJmXwghSvP/ypMM
S+iBD8A5Rt7vCQNrsHC9+68tKGEp4yn6pWc8/JFY5099s4wQOq4pxNitOWO2CWaVWzX3OA8yKx9q
KEJ0XBeUI/YFb8VYRdsuT+pq+QDtr/uax9LtMCTYnwn/bltuNFyIFz2JjQ3M59YUgAPl61wVCTKz
Q8z3tjmoKXyaPfuLSBQC3eC/i5yvu261/KSEtPaeJATVdrARmuNbEV73nA2EIKAJF3Wz8Hdt3BMf
ymjhY9G1j1kY9x3NcboLKpPatLzEzUuBHfHC5AY6AxJZGXBGM+SaEWmcgeG2qZK+5cm4WDoKatE2
+wQGKKqKpwZD5RRqRu6syWL8sRGjM5WVX27MuCYJs1e3kR6PuGLhjHvz8Ceia7chTOvH/4qsqMKU
OBfTic1H2KjyDYlhBnIUoWleIBPJlORYFZUu6luZiCvUsOgXWCrmuJp7P3Vpb+ulwmIjGfkQlyWx
bmCW3QxXVIIC8dfJ7aa1DK/MtIl+kOZ299rcdX+DB18NrLdC7Fbwz+dBbftPSlwdIR8SGXAGGN0F
NcN5JnYYXzAA1/+19mTgW5IYaWld5Sdt72JgV4GuhyZPXYDBKsxB4c2PPMWiEAVEhbGV+23hSOTp
/YlmaMUOl0l/yruGXyEm0UVPAV0r+KGVh17dP61dEBorPKHXJXmv6ILNySKiawnvtY2W2w24sNx1
rPOLq6ZOdAOn2z16bXjzU2eHZmWYetTBya0XyINAw89l/J9t1WuLLkiiqOfKQAIVzX7syseAP6OZ
dMRcEND1NvflcxKIMYRDv/H0Y1CrV5JPlkobD5hVKSFgK3Oh351q+qxCIdXny5ATu4K7nbwJlPX6
D9kcq/gLjTr+d6VBAvy998WN4iyO48mpz01mYrZGtM73qQT63VNW2ViKwN05Tea84r2/yZVN8BBq
GGAAzUOaMhk8lOSd6qx+D4O8xk4dXUMJnnZpclYnDLDfe/2aLBrAl/8juxCbsWlFSlZZik8+VXGT
yHV0d8GrXKcxwKGWmS+HKHPoxvpDGGS8W6tl+6cso3vaHdDoPkh6Lf6TzZ1180NPOs6YF4QsMmy/
Zj1hUA3e2j8y0UkujiTIrHXIHxjUKoDsijEICmV+awLlg/z5Qo+mZBUCPRnOBwlViGRKu/4wGHyt
nbG3XxK6mO5UMYe579mvRuKva9qh96GAeUJE8C6ANq5ruibzTrXBiXGF3O9VcxcFswNsvqMJNS5u
ERpbdJWg+KQauB08yiU/jxWD2jcz3RAHzRDNbPpkAHURzX9ljnPHFWmJieDM7mLI6N2MPAVgu0mb
nmDS0e6YWjxnqwo8WUDCpY7SYbImtr0zSdMgFufFi6QC/WdkLt0CCkRryVRk5WL6AKT5nTWRDjW2
NhcvBenq+GgSlbEHiJwX+e8pBcPJIO/FV6xBVF+qSCnMgyCawEvYEW3D492PLu44gA4aWh0xcmd5
mORXYKmNgBzrMptaWpD/PLQ8eOQ23oq5/ncac9bJaOUqN6g+TdsXwyr5dDN51d0mJNsOj6auvVLz
+dJR9X+hGYg2bWdpthLXUZ+yDe0TX7m6nQpwNl+9EBGnZeFgZiuOCpb2
`protect end_protected
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-3/src/DELAR.vhd | 1 | 380 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DELAR is port(
D : in std_logic;
E : in std_logic;
CLR : in std_logic;
Q : out std_logic
);
end DELAR;
architecture behavior of DELAR is
signal S : std_logic;
begin
Main : process (D, E, CLR)
begin
if(CLR = '1') then
S <= '0';
elsif(E='1') then
S <= D;
end if;
end process;
Q <= S;
end behavior;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/213bdb6c5f83bd6a/zqynq_lab_1_design_processing_system7_0_0_sim_netlist.vhdl | 1 | 197463 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:29:07 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 2) => B"00000000000000",
IRQF2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/ip/hdl/vhdl/convolve_kernel_fbkb.vhd | 4 | 3597 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
signal ce_r : std_logic;
signal dout_i : std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_r : std_logic_vector(dout_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce_r;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout_i <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
ce_r <= ce;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
if ce_r = '1' then
dout_r <= dout_i;
end if;
end if;
end process;
dout <= dout_i when ce_r = '1' else dout_r;
end architecture;
| mit |
dsaves/dsaves-hdl | primitives/lut6.vhd | 1 | 2095 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library ieee, dsaves;
use ieee.std_logic_1164.all;
entity LUT6 is
port(
clk : in std_logic;
rst : in std_logic;
d : in std_logic_vector(63 downto 0);
wen : in std_logic;
s : in std_logic_vector(5 downto 0);
o : out std_logic
);
end entity;
architecture POS_EDGE of LUT6 is
begin
LUT6 : entity dsaves.LUT(POS_EDGE)
generic map(
N => 6
)
port map(
clk => clk,
rst => rst,
d => d,
wen => wen,
s => s,
o => o
);
end architecture;
architecture NEG_EDGE of LUT6 is
begin
LUT6 : entity dsaves.LUT(NEG_EDGE)
generic map(
N => 6
)
port map(
clk => clk,
rst => rst,
d => d,
wen => wen,
s => s,
o => o
);
end architecture;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/38a92fb39758d0fa/ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 35666 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:12 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : ip_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd | 7 | 292628 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eHs/om3xPkUfmVFNG7b1cVOVTl5/zWBv7dDxBpXdc6lzIY2kc0i4cx8WYU6sLNhiNItV5rr8X2G6
Dny8em57zg==
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
dP49a3Viez4NUFgWEXGRyCk7t3SjpYHk/q3B7eDsU9d12tlhLycjqeWvHMh+k5RTtyYKh9E/ymIG
KUP+SlaPwO/1kX8QmbbI4k+xm7VQssjdFd2UHx5AmUK7mvk8gvdJxcY6qJuqE+yYCrmDtNA03VVu
ARH+d7nWl6xURSTVAYM=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mr74QSDTeWdPfHu1bzol60RsOEk53Rnw/4M4ELSoQWtadbwFuyjJF7OKx8W/NdG7CFKfrGASrSSf
WlOlfD5MHMx0pBBiYLXlwTX5eKx7+HZp0t9BzzVmmsayRZJmkSugdtjvMnBbFKTTSRDAe90qIFGI
6LaI2wHx7vUHhY0VcZRUR6VpjFOwsflupuduxqssjzvc0GJyoyNvtgPTn/ID+Y62LL024wypYRJB
IipkkP4lh3IMecNn/98+v8CB+raMHiCtPp0cd2XEoNu+4J0cBvrstoZDLGkbkAmwPoOO+zwAGWHY
8xuF+qBTl38m5XaMK3lbMRGbtjdm7UHnGJrplw==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cEjr6notZbLdAYAE1XbFJAgk3so9IDljbHTAhkEXmnw3M5JRoI6xoGe1zlxwriBwmEk7pZnmYRDX
uXhPr+Mzln4B3hbxmVB5vU9PlvRjw6tzIWcL5GitDnIoNqQWD27l2oXHkunAvDMk5g73SWjNMWJJ
FA+uB45zggPljRXLnl7SS7eF4/83c7xioQqaBpORv0spqopzaYG2PATsC22X06uHiLUXtuCVkOwK
wQn9+PuWfWVdqRmzOV1M5UhMkvp5iV10bl5n7uiIiN1yvQqdK9vsQNBWNmWKdN7UbTjOhXucixp8
u1B+96/UGfXNJh/x3kgwQVNsKVi+opi5OZXaRg==
`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I8+mu2CbVLXutGgaMNQD9DGjMJv4c0v9qZILhEilQ9HTbJRqFoVByJkgds6mI/TF/Y0bGQug4vGw
GqwhVIscoaR1+kryxc1ljUXXDXNubIXfGJa23EiT+ak1RJDzrEm2dQ0KocJceZwDxopTpfbqcB7o
urW6EL7oR4e/nWnGyB1tF9Ypmbf+Efckoo09mBL1wGDkIYbJqhVESuRmQI/bU+FN/5uaUksxu9FY
+TxHvhglPD6Ewz7k6g4PMN4CMbK/EpH5fzo9xw8gcQNJ36peauyx2mLd6NpzT2+tff05ue5SJ4ZS
uY4uBy+kqcLpLOE51kKPqtoiqoW05/FHR0I51g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hdErpuE+aFYhmDALn2n1eoWLnSWfzwddsYm1f5/yY2XOROKguIGuhkuaSdwAEbYiz9n6cQScsoni
RVSOgBu9L/yOcnfVBHOo/CJgtiBTHcyZtiXSa3Ivg83tNWL9RVGhbFndiCptsXxjwkUT7fN2ZzRo
NeGK2S/56bG6drPj01M=
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lzznQwfo1Y7Yv0/FtDUcD4s0mxkRmvZuVV57EnYiTJSxJedqfnpT9o4U5RyiBzkqofr+73Q4vA6a
FYMuI8cvIQoKqoNrIss18C6EWgiBKVR7cC9GQMcGXOKwIsNZwO1Rq8eY0oHhKVhH3YkjI3LP8epL
dhOanJqF1fJxfjfkbykjQ/CavS/XimJD+Tv2BP6U/qmNvUIROuLHbBAw8gCQyGjSDb5iXjnWHbGx
PZ3b28lQA5r8FaVLnL51QYcUO1Ss4vnVJvd7gb5Dldj/kWalvvDhi8qoLp9fLuAAknzKbAPwy7wu
BNhCEw5ZyPIzCYjlbM+GLwchrHqj2vmbSA+Sog==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214080)
`protect data_block
Lq4qz/nOZTL4mcbkxz28ab8WK245C/BkwKB2IMKAfTiErKdITTSB6wh5cv7xsVygEWvewTlTpLyY
vi0FlNrXhX80pLYnk4s5lCwH/9OvblU0BE4XEVcCo5+Sw2x7ab7oN2H693HpBnN7nB5IkLl0UD3H
kUkUAikAMnqvB96yMIl8dd6Ft0wxoxPwI5zzI906u7aehzN+jLiQeBp5xK5cHla21KMXfIRVg92B
h1/gE1L2ftrkcL3iuJ8NoLUfdqQj0ubYBz82D6BsbrWqLWtkK6mJNto8lPtzo+KxP0WLuiJuRQGN
XTyH37Vzds6+xWfFvC0xZlbvutMWQwC8LvBRWgI8zouUHSIKIcc0cKTwtb9QUnfZ90XaY9THQz/N
SZpNetPqqDYxkQZu1LhrXxoYtmh6HElYg2YYAsZvQHVO+A7JdQpUZy4C5Y+33xC1BXsJejjzi70c
t1rS9bMa0rjDxjK3NJF/A1w3Nc/UDSsafMv3xr0huFAoyc+J64KXV0LQwQrF4wKYOzoNP02CHhwd
a3PP8RG1NSxUglWpCCeAQzrr2PBl95ndtAOmrbyYF/WEeFXWefH4WPUXyzGHuZG2JC6MTp1Nkk0r
qe1WCVCzYR/4FXkZ+vopLlwbNJSdsK27lm8pG/QTRQcUkXamYw10cNAp4BBntiKwA2LavXTTTKGt
3JHW0kIDJqHoNbFdYJtftd16qg9dNnSdV0VGgFwj/seLyPMcc6wV4+NUtgfQ9Ev4ifmlfp6idgsJ
MdnQXDH+AIX3YQaz4EFkU1ltoyBrc7WJ/hLHQPIFz7qN+p4M4t/aSlzvFz6eTtUwBnbk0Lp2M0fq
OI79gVKLzB3BnpGTweyuQYUv5quoxagYDllV4NzAY/Zv6vT6xB+KUwlW0XjsqD8evAWoOx8jw55F
IUb8+aV5ktUCKI32HFiS5i9U5MdysapNd2B3PRjDrcfh3BGseGUbrQAgiurNxyiRtUqCSy6PYYoT
AaqsjnFDfvQGzOukGKBQgV5RJNdxHTQYXinVxLpYmhuiAj1K1Kde++GwA3Mgg5L675ibTLiOop+C
TjtWggt3IC30luBJppqzQigMV19llwJK6M1lMFPpbUuWnVH1yw8Q4RXcv18yiKdg1TlHOukIyKm2
DKD+RGlqYsb4XbN0v/YBRNcUk6HRYEukEn2jYArmvN8e5ggvcr5wikQIyEDyX5Byh4ryFWS2I+O8
aPuEp7ny9OYGKZQBKGU9oPenWlVtDKcx/SBz3uanJSVJ1rECSy2kzhTdqG92AAsMv/z69mx/Lb+e
bnptvkMDTQHXu3XuMbxVF6eA397NrIyzvJ24bX+nziD7hEdXYUs02wQMC27yo3pPNE0XL4v0ZXBC
j1rR2dQsh0/RKQwSLCgz7dQ11FHcQbI2Y8K6rdpqhmtM/mEhAYa4d2Z++dsNngFlv4I77zTAmiqI
QQnaHjRooseukl+SV26wFuEDZ7wpIKyuj2mi5rVu9vrvlstOSeFZvp8tIam9/GxljkcRpRL6IASO
Hx22ERG97Z909YjThpMbsaK4mLUPBr7L6oU6oBg5EF6Y547lLI7NMFNJ8pU12Q/dWOAOOdnYtisd
FBDhsfcjhGfEniVdRmSXHZu6EdbtTyP+WvHvreZq4StEeCdgSmDF57P2EbQMLNoMSrIQHDuA2r5D
KVGrOp3Lq2eFxS8/oA6oZ79XL3oKXhQh6SocXD4fpWY+pSWUCbJkFMCsxdEl5QPsinr5zgeuB2vi
Pg3UWYkI5nukf/NL6zjeOLKMBsqmvC9+8EZzREGsqX5cypD1p7faaxHA5L0Dv3/MVESK0hgvXo/O
yn28a/ECi2qxDre7IYLFPMdedMUsTq8tnt46wb0pZl+dbhUL6GafDWKqr2p9K/lAcICWxwNzkcj7
MxB2+GYVm3FF4Om28gNFD+sEZh/1yt2W54opj/gEs+4RdypVI5ZxJSBRKq+lIPXNk1Z5Rlw/h6UY
IbCnep72ozR9IZZqIg3cYh2mMsHel43Frul6wWeM1DAxKMacMj3YK824Qo/HZaTss/gGvkOMX7sV
f21iTdG77JkEK+upUeB0Vs/dyGZhbr5JiLfCdnhfn7lMDRwuytU0E/NOy5H8l3b7fSOlg0dqUSuJ
UhXGk4JeKlBG7COEhPCU2WqXjnC/0NT18jr1G6R/Qd1pbriUm7k/J+y2ql9pr/wNB+gIJL1mFfGu
oY2j813n/DYEr0R8P2Yd9vQOWCeKUPJPD0ASWGeEWmCQssmEsbwOuP+u/5mifcJ55vZ7r1uJbQI+
kPkCIykXJ8pmzCfFTyISHIkmYFxC+YpdrMkFulCmxCkYF+Rq88/AHtpP2ACD/6svY+60X2/T4C49
wbogCLiJ+LDgBpT3r8t6004sZYL9IxkS+rEqKrYWYrTA2r+xvDp0wlCqv3QX9idY5NbKkryRx7ns
SJAOPgXzNGBocZJY4rMfIiI0qPMHrz/c99OUpCRGFnwUH8+vLDL+R655Ang0GOGweIOafKK4AF3K
C4HkSmdP4lKzTpTK4kA5ZwieWzN9oeiSakGloCa0eAwsO4TIsJTgGkHqKaNIHfIQJh/JUM6cg/oi
rUrJawn2xHe7D+E8EENllZmVsmlDxPSUZRVVq1vvqBT+sl6xceG3ZJgeJ7M4ol/v/9YFMZEkwpkv
DlkC/svAsuScj23ekrlLUBS63irTiQ7sdA77sJ/bOb4iDZ9S3F/Tq9O8piocWd3YZq4yQ6QxXy4W
ZvdetPiyF/Z6QYaWbOgctMvZcFQg3dwHZ6sS3ZGm2xPoSGuudrTE9tmbdmQG9+K3HuAkuK6QKci9
rFJpmqA0uccyV3nfCXFN7GvcAPqTiI+wQqz0B4bC2oLq/Zm7RXfSWWwwXTah2NsDwG3mk+cDp3aT
ayUHmDtU1Sd+OfuAU1KS82YHUbmQsH+el3hD8P8XHO1f6tlvwa1grwd5++sn03r1HGdB2C6iLYmG
7BWSc0zyk1YhdjKkRe09kcMFYRR9bJ7+ezPldxwMDEdBg0OXUKIiTSqX3PuZa0qjoBifAcMrztRq
Id0uNOXGrjJ3nV2PtGtdE4XhFYxXtKLDOzoOIy+yJfDoyXskbN0QOBtyayFj/NiUiEflbssNQL6u
EkRSmPYMGR2gBXHEJUFICgnG4AL+K1rGf5cXGh8+rBau4bxBMfKxnXWdUZvK0FvFHP+c3i3WAbqk
D9XT0SWIod4ewbPdwxWMGieeOYOzL4SVFy/VraXGa2hzas+U3t/s4wh0XFmdbQ2y8AuYUY+jRMhs
YOORHhsTCfAe8JrSgAe02fZg9TPXsbKBymiDvr6IxPvg6/U01vI1nerDpGDapCK6oucVKJg9A6xz
d23gjJb+bFw3SPsjoh8Lv3x9FvUPY8VTs6KLqZ22ebRFe3kX4d3sqNr7/5L1Z4YEX5+7EupUvZK1
NIiQQMvNhXlArQPXErk6aKPKl8LvIWuk4cigE4S6DfSX96nbg4qSvI9jrvkU6jR7jiYOh/ELzIaL
++6cuexrOnWVIPyXhtfMzLYvO+ZvOZFR03Sf5UzCNH/0vk4Ak4P6itozMEJ7wlPy+ug9QEI3T0eM
R9PmJVypi8fD3F4Rl+oaWQCjf5yK6/xlf3qVpY6ubABzHED90tIj/ujMPXYvBJjbsJjxQwjewHtc
N76iJkg+P0P5UGBLPZ94ENwT8JN/aSNmsIIcu2xBtUhhhCXijG0FCy1KTkvkdhyQrFVPRLdXHjX/
/nipM8UUfD95puRLqM5j6cUTCYi+XgEDn4UuxTCNu8azMU21q2P9kUg1B9SztC+DTFAXtq6Y1/hS
9WAAzm0x7Ei/m54DHVo3ewBsSl4ew+sK+k27RP0rLwB480l4ANzH4X3JaBanW78mItczqU/FCdVj
eE4vrCE75u7Zz7GJYQJPZiJX0DUudA6FYjg2PFy0ScnJX8DLqKnVZW3HrTlvQTFFA16ovmSYgmtZ
tV5Ogo26isAP/GOIcjsglxEwImTFcqeANqbQ1HEa6xkkIBJVJVKZCZkogCsfCStV77Y56Q3m+qbO
LnmBetBt/PWAjzVn5Bl76IyM8pWeLNpAwwrFPCzfYwhgVC/u7RKFT3W3bBeW0XK7o9iGCwr+IvQs
kuGQrt47f8WRZnzrgCaI3EATxmxy8k1xwa5BS+c8il27B+EYxa3i1UkeLPGBA/4O3TkfW3AbmDgp
Zu/3SPFtGgBU4UQOJlWP42l8lrAtWgkLqnpJTJyzUKax/c6jIzHs9GVmuYWcW2Qca4eBxhDJA02s
boSoGNmihvs10GKz04BTdI87JeJwDILRUyeTCZTVA0EoDkizwK3Y9w2lZRNBSxAt+5cZls1dXuTM
nZYfpEfDWLgoNwdTP0vCvUOUZLE1sSUya2wzADKY5wRguPIPV8YanCkBIPB6pTil/I2rbkoB7fK9
0yc89b8+9JrMTfbUmmdOvLnwLUgAWXrS49PBQoLnn9QdB9zHg8WMdJUwHMlGBLTcdFpqBzP+XnS3
pCdMenG8b7DNjvfIoKMyRaDSj18rNpz6PisPoyssQaIkrxg0vDaCjOS2aXwhu/S7Pl40UgSyvw4U
oDK9fEpAKUjZgZ/5llLr1J1/KKpTURmyKMIB1opy5pvfLrs0cW80JHCXx/1N9APXy6g68toPqbys
6+qyXDMiIObLCpCD77WEjSXpLbpCVJwv3RODEeXy5LpDWeJzH3u6myUA/hHNEPdYxM/PFk/gMHqF
nfPLhTMz6FC4zJV6lq7Q9c/MtK/RkCvS7MKCNme1mOZvvTvWwLpjOnLMdLAU/XPkH4jVSUwq21MP
VPlgRShv6P/xmzKicj/WpfAoyfsxflaOBDPwQQ7v9/sSonYXbItzZy00mxsKySkClWIxdzD2Kv8o
4kna0d4Z9QgLExuwtelom0OybfrTumeAcW0Ra5eaG6uAqEXiJWCjoVDe55XRmo/PkbICRHauW8V/
eBnSXJHLb67UnIY/YdTW343GWuFkYW/LHdkdVIkIkuEAKTjWxWCxBDvbsROrcSx9e5Xf7tajcfUF
liQ81OZfr8D/Q//dOKVctDkXJkwgBDJ1xjjeOn6ptVEe4gL5IEh+1YbBuKNpb+TKAYHiYdMDFl2r
usIr/TcB/0Y2QtDhB2hZYDjAieebWuDDF7RM7fg0WNS5NfMdunHHAfBsDmNsb62xwMiNBGU7PUC3
qyAkF0UO5dreTC9lsTUpmvCfrLMhGy0HP1Lh0MWJY4WzvhnQZFFsS4ulgGBhByscFGu3zhQ47asj
x6n6ynQ11pwYE84gxjHZG566sPFZeXQ5pn942VkxshDT3H+4XYlG78Wrb/p/8Np+GNIsINtz4aur
hHVNdSJ2tjWMEPqT/F22X113zfJbzTBQt7buGtcou2ajxBW5lXcrIv2DD/uPbyxINX0HNJtV/GRQ
rP6H2l6dKDgt/1GF8T1LYZk2m4Kb3JmXPf+5BYXkltHGnNQPleDXAYBy2tky/w43Vfjjgp+NAeFC
p2cO3mmlxyUCZ+ciZqAt2USUGitSpKpoGp0JMUSDeIi/QG1Phw00xc+U95tcSNpIuZ5aB0l7RzpG
ILAKSDD8FmudEueGsk9KL1HuWzs4MBbTyqRzN0KSeC5PJd46fmcgJESamHsc6tVWkruBSVm5pg93
527rHTEBrWHMjHaVN72z2B6aj1PoH8Lv/HAOBpOf+792UrDVZmereyeWLUyqjjKTclV1nXNhwI/C
/BuD/9FFkvukX+0w2rpZnjWgtslkLafYUFFxBeZ+xNBBj3WLPcUrWHvVKeko7ThYnefB6O4paoDZ
1+N+EbQcHutwJa8lEdXqhoLgXT1NqAOAWV1G611+3xWYOd31iLbJy2G3zkJajd5HMhoG+J09Glt4
32jfRPuLqOC3u9PVpHAHGwFmLPxEHTocqNcb8jrXhHrafQ9xIQPx4VeG653wScm6q61AozJJti86
jA5J3UEEHGw9vAPaLfTe3/La6dD0V4v6u+Heek/0sSF4Jw3bvZ/kp1r5tMc/WYFxyjku60NpV1mD
G1/x0icHXS4ThKNuh58XG5ivChNFHpoKp28zgNC08Sg1PpmicjaYQKwP9cmXqagCj41BvfgDreEm
RX8EcDYczNli0bwNqFCagNrMiXnCPbctJD4NmSDbZZ5JaLjxWMWsz6j/4HbkCHGjMOobj95MBOtE
KmYlq0jsey4LdjwfGsVPL08hYJCniYDT7km7hE3WVgOIV3DCNeI6NMJGoaTETusiftLuOQ8/lQLn
Mh350tjgEn36K7F3uSnOIU+vzh2sLgdzTFEi374Bn9ySbErsBvVn//xUD7DRK07eugI+n8sB9vjm
oLE/VdnCZ5JedKJXqPt80EKuAQfOSirfM845Vt8DElK1+UQYoUrcuc0qFW/N9MbDToeieqj2plBp
MRmfviln4oLt17VD/YcTzVy0d4RL4+mfJF4TP8a+Fj8RD4OArG9JSXzH5PMkFwT5SkLkvjPqgavl
0yZKsts/pfH0Whrq15xya7rDY99hbXV8LJj6nFqrOQQMwc55aAGXGMb4/XO+REOc7rqCT4xvLdgJ
z/sYMARK77ywJG0A/yF/01G79Gt43dP5Ke3d3sdoA46j8N63zqj8iBSBNU4coQmdzEzGqiMXZb4h
g+gB3aVSlTHKP4a2SD/z2hjYhyMTTd8HmNPGDCFfefImFQ5abW8J4F3kQeiBSJMfzxyg7HZeFJqm
/knvNi3ag1igrDsBRt7TaMpR5jym9EtzDsb1Vp9dBFHqWD1IKWLFJQB9b3hrIofjYeuQwofjryWs
ZYEnAzuhI0F2IHzkONtld1ARVTlFOlp0M4qwxG8KmL86La2xKEjfbutI98K/wh2md+p74WHueajR
IFvsC6bc++mf+OeFMo5zHryS0P0BFW/+5CrbEf/BAb5fDEc/VfWOaDb/EfbRznI9tcdyV3SW/7wT
p63af28bhlLis4BYJa0FsLJJ4BEyIrc6ismSOtALroTrfJlYOdILWo+38Ro5R1vncj5wx2v/2Euy
o1FTKIG4FCR0MV2pL7vI1smorc8mv7A4urTrBY3HPQDq6rKHBC8Qg2+O/ydFLFdfhOvHNrequ4C3
SsiRhXFuTcrSnyN5nvudwrAYqptsxl4/w6rqitIc8al48v4fW9xirl+EcExi8A31g3SeL7reKQHo
tqKcXHG2+zSUfzKSiMhH8TXa2wSqm7/uORSkc/m4wY3s6XuyLkOsCLvV29HtAVX2fevpagyaFG0M
MUSiITPIBu8IU6p0QfOm+Q89KYH4pIQrEePPbWouSwv/R+2F152uEpiz+DRZuda8qzkfuFUPJID3
tsZewTGVXc/wJ0BJWLVOgla/UNU2e/qGGXXjGGvEX/BuRto+aw8DcN961MFUMpe3YO0SKPUTUG9T
0BjRV2YCadElyCH/wBBP/r4hriKt3IuJXcmi1pIUx5UfE6X1psSKBfI/ovTBFB92Cg4UnNCLxiWb
s/ydsoQa9FS5rWhf3/YR+esgQmZqrIm/zRieXDe9vllN7YBGHJTXRDdbnnCZhPHL1saGE5kAmWcL
dUzQcyuRkGtCQo5Cjz2Xqst7FWMxfzv+5v274FrE2PekbDBSzqcs5Qe2EDhfi/WJEvuZjHa7bP5Q
DRN9ZG9mz51uWU7WBAIIyNWnTAy/eBI329eowQdCQ0SCsSz3EVzDAeOL9KcOe1c8Az/SvLRJFhTe
KnongaXoWcngcFCRcoHkLCqJ+2Mzskd7IY4wx+QZgWegZwAAc1ieMQaR4b04eVQB2oFI1LhhJxOv
vEyLBGUBvV4gFqBsjriB25/6P4buKTX2hcapen0uaUlwM4MM5TFtw5HMneV43cxR1WKy6wGP5oZO
ueuqSLrDbatSi8C4HbYDmwuU6ujcpDZ/tSiYo9D07C9U1ucLyGtQyO7GzNG2BH7yT0Rhk+Go4cPI
CPwTnOEAYluOr2Z9ELnQL9gnviQ4fT4ykyhFljiHUGJtpZ39IF5mj9V38BrGCv/AfxVPhBHYX8N5
wMZxQvLIU+hs989wwDkQe48SeC8RKosntwFOfUmHlUPMUScmMdsII+SHrQAfR7b5Ey2I9uQjJmnm
Jm7Bwx5GeHEPV7fGfpu4INbaP2L9N6v+6xrwcvtgIT0H/C5+EgmRfLl861LUB3lNbECyNKZIT1Sl
rw6xa7O+SsUsSq88njvwrQklYp+IS6h8rzGPm8kFJ1jpJvPhSU8sOjIjl/UdchiH73UUTIVnOwHB
muijUlCxbaIZIN32+hH14a51w3NkEx20MI4vIofAgI0Gz8AdD96SU2jFyeLgmbkgIt/aV05JzKnG
aNWpfnCrcag1RsuToxQ3cfGFoXBcX5keluVjP7yE4cLXXbH1P19jr8YVVpl+5+GOS9OMI/uNwflf
ueRGXjc6TuYeG1i25YJ0Dc8jionRdVLfYeEVEMXY9KCBupaX2xrOqAK+WJ1fQjJE7jOkN2k78Lkt
fLK28H21oeNkginqHMQoeUdD/C1Ot0Sy3qk72RK4YiS77EuUTLM2qhtGzD/JkriDCfWsq1vv1fHn
cNIBBwcvXkpPs1BBxa3JZ5EBgH0rwxFDeOee34AUT1xcMLz1Wko6V/z8OcVXJkpezUjBTklwI7iQ
O4dDyBNwgoYgmwwt3qNXIa/WYC75dQv1MgtI0ZHw+GUzkP0OGiwVEG34ehX2O8Ehak6W5eUooIHv
88V9BPU5SBC0utiCvDbaOEMRqfXXclwKyAexzDKdP7vwXb3k/g+VrGfMs0hSow36rskPTmqIz9Ha
urzYyKd4aR7FT5UxOcWGDA2i64gLC5/xrpt9XMzIHjvkhDaHLPSwaewTl2p2Z5UTIDnAnkYxa/4y
2t+O3bF01KTsNiSY2cANV91fq2SHp00jtrIRx8jG+JEqSWTngzFLsg04ll0G/CyG5XNANIe0BXr2
h1gp9fW0IVhYPt7TAcqcme+oX7ZhjgBov3CyfZidWQ9bqsiSD/46ZkQWX7+j7XR8670eNPVuC3m9
g7vrIaFa2qM9UZPpPvZt17cziwx4cAz+A19CbsW06u/ujQNkDQxvce4/Fkgk3dHLswb1jqfcdNOJ
4g7ndSjqrQ2kXHtsYy0IbXK2HWf/UKigze4vXv0rzilOE3gLgdwivv8bZ2LqKZcqe9qgUnPcQwHW
SA06HpFEDpq+MeJHohjUp+pbVA2vTttoGwfLPmLfnl5f0h7UPFhe2dQ+7IdoMwVi5HUVvgndhyFK
J4nYfEX1Jw6jjHKyS47yaxTL8jmgS7zVejA13w1NvMBcoH7lNTnRH+eKL+WXcj6q/opj39Qk3U4g
vLWrtYsweKY8EfofOwSN/XztJWAroP2aK7+/OUwZS79WRXsKnZjRKCXh+jHpuSzaanEeSKplqjIg
Qa64w6lB05DVSRmLffVR3vI6feNjOHMss8itTmx80MhU/opD/QaOEBvEvQB0NECRSc6GOt4PoZej
603vUVww1P09Yo+1pLZxXfE1pyxG7shm3IbljuvOYjrHXsQkyuIe0PHyOJSYHBki4k9g6N+9Z4sz
+9aqKP5Es0MBixvZ+YyhEfhZTC5C9tJsmxrZpZ95Opf3HvNU3dSotaR/KSQApeOWRmHXBfpYgfW/
a1NjbEB553DbHREHXy3gTmO1ACSKNpqlviZlJDRH2edRIxTJdv0ETuUlh2A1XPKhEmaGudtxPhab
QcavGnfVdCLjQu5Y6IeuCmFscdvGKeiyOhdIyFgkbOVealZHz7GvLimFr4uoHvn5d3MFdjroyE1I
Q1pWpSZYZL+MBTYs9YDgMs0JueQ7dbdlz3DqS1Pyd5JrJ/u18oME83GD479F103jPx4pwUgp+pYo
vx3NFuC0kUDRMZvB2fYW07x1J/N3f3uUXnnysK6V3id0J9mKGDCxr43x/Swc/usBgg+OmdoO1iqW
uaBXTbSFyyospauBNLFw8l0Oj9WzCRNcDlUswvmRVoDR7aSRIcI+pS4wxnVPxbg+bH9YgF3xlSIh
sy+rubBJwfq4v3ULqLcD7UJm3HgM1R0V6tPhE3+HGsMRc7yVKtJiq/hS4EbWqaWFb8IbQ/hbU7RT
aemS0wrfzDjLR0FEkASJeGXW4ujM1nieuoNH/pHKigbRNXWRTsV4NPrkP3mc08dbpHz7nulhtDMT
9fIHwHZxOGkKDEuCkyoitOnXarnOJOnf8Hw9dSr3M4tisLnZIrlxU81tWpjYtukzcp8WqqzABt2Z
24APTA6H2HhUbcqFIWAOjAxtrGqVMXWvDy5oEBEVCja6xk5oni4BlDgTUyAeLQERFcM5FEnQ0g70
fiqJAwHgugif87wTAuJueS5h1BH/KUE+j553wSRBM/vZP4jYaYnDr9eH+JQcxKBmfYbbGSLKK4+a
ahp3yaSOmUuLwA88yOukxuskq5xluPKDiV6rNdOIN5hstpnl++MQIHUvpuGdN31c+VczgjUcO78D
wfCX8s/FknOxMBqX78XT8bys+Q6VQxdRaR99Lke3l2DENVJjcR0ABZHDNtoR3uBbrYnkkiYYfw38
e/4SEpbAdMLn8mRzrz/4yagW6+dlZiNj2cKomukmCJTTxtcyL9pFoeYflDTKdUq1O2E3CV7rD3J3
91GINZ8+orGj+8yj3KfDq2BB/19vQMp/NCarXwIu07d8mZaisSA3t0ApLJ+hruoPnUc78P/yWiTG
2DLYx19SB0A6DPRmhMpM6zcUcY/1WM9tNU7EEBH4ypv2TQMBCqO1dSfZcbiBsd8/WwlPyXP5gvsB
F67dr3DLptOSUy/gr4j/gji+L4rg+fTXCbKIyM5YIMq0pSLriAynXGZK3921E++sXU0o9JB+lH2d
5ZXWZSo8rQu16uX9yS4xAZtkTTKtE4/sNho6/HH00FPLoNJRn1wjJcdpdW5FEKVm835kFQVG+FvM
DQr35+UadderIZaeCuP0e263o2MqYpbvxkNcW6nVWj9Gb6I3W5cmltXfEhBB0r6L4kEuqmAQBnc3
m3BSXHBO5XCU/imiF49gFjytBEp1PMoCrV26s2KEuhFpVRmj6K4HX28Y6DfzktYdFKI4DDYJjjFd
EnunNnWV0W+Z+XhIHdBT7b65V1l2nZg947tpcnt/8Y2eHsk6W/qL+9QFEYNFwImYnAth1FWpMyj3
TOCAB2ydrvZkzwmNI1E6mqQnnA8vS6OEBR5yyUD40pu4O2hhuopl8rZdVPGTgfyvsd7SR9C5TduR
M0RQv6TO7dK0cxx9H9BrfvV2V2QxblO+7YvQAAZCTPiyl60KW+NbnE3ddM7L2/cj1fKOyN1C1Q5B
DvS8WwRugtj6uOzkDtuNEXNxiJ9uRx9hbkJ1CqAGGsqgVlfxN1Mfy5lqvT2K/QveF9m0HYm9665I
eWzVO6+b2K6SikZSSIV92voiHwMF0/xgRpqm8Orr+AByuV2mPEwB6b7Y/ycVCptYksUESclEotM9
j0WMV/Uwv0kmflqsWGRv8gnNUFSMD0Q14I1b3Z/HFu5++H3+uymQ5j7Dj/ChRN9Wyzbqs/O0sb4E
WTZEJ3WOkoimN1DYls7CQorbCGBcTj4iRobUN6jMQOKDIU/ootacjAu8Rx/DIQzFLw7CLttoD9Ng
gToGrJ6wN4RFtx8CKheXSNtypqor8OeGnH0X9i1/apUXOXMAe/V2WwmoeDnTnijXjFnmWehJdQF3
4O4KedBJQCw+NImuzTPrRaYMhh4NujKpOwhXe423V0X7i08yowDYJKQ3y/RQeKywUs6lFa2vWGaJ
yy7A5mJ4oceJM4ZeeVRmV8HT4409585Quock5jWyM82juMxxeg88SjcReoEki9gMSnB+I4vvlSpE
uX5nmFbsmpWE7XHiH1dNcmrBiZy1f3A1V6eHkL/FLZjJZ+ezs6grpY2AXCgRSAljHPCpV8QX1G4N
qj5rjcn45/49T1oteQVMMwX/KuEoVWHU8rdLhZALwFI6NjXr5aPC6DOp7xqRFs1wYo1JoWWUztH/
oWZhka0ZzSr1Txqzyu5iFOp548w9tJwBZrtmdUjtOk9pSPZAoLYThC8jzDy6afAmSttNdaC75QKB
dszc+zkeIlJiJ31WebExyFdvt3fnNJ4w/wORiBM7UY4yPan3I8qpO4gaW+TmceT2RVf7Akg6qzbl
DZ4QEWDjCWinVneVlKrMg7lXLUUACXnq+bZh6M6w5B0kEvSIqMU7M4tcr1SxZA4slTv61yrXEwzf
1LD9iPiQP8RP2howhzwi0nfZPEBn89kS3Yt0KcTMDdXWE7L7stB6vv46cnORVZD9L8NjbLJHGkaW
TUwBngr8jGDIT+Fr/dkFUn1ewzAzmReGsNJd7mtkKC1uxJIyXa856LEJTNnOvc86zMjcBN0Pwq69
1iYdiSAG0K7l7WEcQGHc7XLKxAKwzTqaPJ38CEp5ZcPROgsuYqo2bzkW1vzHd7Fxkadh44j60B1t
dq3ob38H+CaDWJI2JSoeg/PEw7FYXaNf+twRNEt2McTcrWsoiXEvaGS05NW49FdabzuH8lUO1E+v
DVo6cehJdosZcFrvtIs8W2vB3AtFaaDuWGyBZc6hjheWHwTD/rq3XoVLdcX5NEJglC8ZVmx2citr
+GQNwj31o5elxEGTFVqi26mfjfubVKCvY2a1rzTRy2j8fHGsfl64988Pvo93qMzcrVqP7PJjus0/
wrJii5cXOm7PpdNXYiknSkeq5FQCKdiTT6wiPs8Jg4nlj10c0073SH7FGzfU+waDG823JHysUQSP
zf9nHm9gLO3LnmFMk1FEvOJ/jPFy72019n9HmGbtoBkLY/LxniZCZtVICRczi+BMQVPTD9NTv4dY
Bel0BuSBdhqy5ABQN+yFBAY+fdpJ0L9RFkSoTXUo2DgIdJG0HivY0/jLp178hbCflbChccp5YTIQ
KP/xbSmPgqPhuPw6Naf+dndl3RKznsYF5SmZqyg0CEIDopI2U0paPx1oFbzRI5/SVPJKd5Ilwsos
GoQEYFMcV9HcqxXnfOh5zvCrO+2gLykcJ/q2Bad+kQuFifkjOBFuvVBgf7r7aHVf1vnu7pLiQJ0V
rug0XjKbvUj8uac+AR0OnH1T9esXT7YL4IVth3fafbKUvuAidE4coQIk68hj9VYaVt1ELvUl2jHM
1rA0fh+6FtB2NA2mrF65CHiRd9hn0sVuAAAtwi7fcvNt5KSOl1QKJ2iBG8FMgVCPJjvYopRXeVra
VT4zZ2E3vVoCrRbl3cerAzJb6kS68pSpYpdzpOqELuaBXOZC/JhBs6CZ6UGm3Idr0RB6llGgPcvM
1BufaPbSdf393tODyJIvLqCx3jSQEhWYlyg9fAanRmERFnsPJODzDW7CnCpM/pROXp1PjwMuVwgh
4bSEVnWcSmob1ubfsOWtUnuq6UeVMCryEK1EyiJJ+JKNKEALjTrua7+WlaVN399yFySvq0dxQdIy
XxWhGysci2I2LZzhxU5BFtbDVBRnf3djcKYqoFbo3ZeGW55qCXsr6GLJc+HZCmEteUTuCvFum62T
fpaGnvT8JHKfkUQgNxqyRg96SmcHSIAHMjKUPXsjrRdaMF93OUrubA4eSq2LpidSGOZ941o0dwfM
yEexhBs9tZbtFzE4b4UaJ8HqNMQdYe7bLibLp3dcEQdcSwwttmJOUEaqJOl9xWokgk3dcHBy9h9q
sUPRze5QVm0dWUrSk01MR3It/e8gJPKGbEopiuh40vPZTbY+mCmkYZqyRHZMRmdV9Q8Km3Kufvw4
tz4wO0kCANFN7KjoNJiHoN7cS8cQ0ceThiTwvTib0X77yyx8MnDMg37OOSZS/x5SJWirJtFhaq1E
4xmYBIeWOov04ESAX4AL4f60VpviRW9IvjSYJGmk5d2sG02nPVLAYo4r6y/G8dcLgtPQJqJMT2GX
XSESvsCAzgvTkXH8VdZEMZ9gWy5OnvIPNsWrEwXkI1zz0ZOQkFJcIpvEkpQMqLZ16m8Dndka7l67
EyoiELbsTPn7qIY0mmSBoRjwEOM98jNjvwO3C0Cyo0c21lF85x9lx1cZGyXLronymodLU5uLk709
U4n/VL+M9NZ+y3c+uD4KdtbmHy8OL5XQmhSg4wXhzM2yU2MpgJChyzok2r9UTcYva0edHIu3qcDK
JwIuHIxX0gZ/PFGB4Zn65AJSpYMtfwh4PExrZ4+qYjQT8oMUTMvHSdfLUfH2MVdQHW24e8VJr20P
DiSoxPt4V2jrlHEdMHx7h1wR0bcpqUXbw6MxwCFDw2VnZ8pFHIfrycsU8n+ODZWxCphHZ61OhalQ
/36Y1YdzD9nOKSdxmvmN/vPQ+fVnpyu4twa1XjtwvH/4Vc4DhGZi1Ez3CtCwdMRnz3XNe2gjrXDK
GD45iJmtss8uw1xwNsYDksFWeOgJIL+FrqKRQ6R2pumaEK2uaquu0ch8y9jcnW4pS3wqmlvF+Pj5
dkwXtKnUJXGPQnLMo2cltNEEdqQv7zItjD6hBbtnfGaov0mW2Ep47kW+wMx8FIzMXFKGLFX3fb5f
FOgBR+PkjYsr/hXj6PezKsvv6emyjXbVf2g6wibBcQ5OovpJ9zBOt21nbsuIpsX5vtHQFm7aD9fC
KIMzC2pXMRQNehlTZy81JVsoq14TmiuMmN6WAq5zlJ3TSHtxXqi0sqqhh0xGqYJHCr/HAPiSCnAI
WvTY9/t8rtmugDmmXQy/iNDt8RwWTUe0WANB687f2300qAidLkNDfkLxH+AVmA3a91KDO8YjTyUO
94cNf+RHB9E2sKHRqTKDHhdJh571TOTyo4ezP8qjRW1hyhx/y94825CDjonbCbEQSi0EH5BQKRJx
K93sMbu1xzy1tLqvs7mJz2Q3mVX3EG1vm8gzsnRUwF1P5tMDYL6p2cq50mOb5Ni9Gv1oBwbc+XND
s5KQiLs94sgHvaPuLx8ZHHvUsDZbb8E2Y/BF71WLrO46zBXGkhPeV76JvkpLI2Aup4p0GPf06xvo
emvy8zhRUulrjILkQrONEBM5+IXtGEgcrDizai/o0G8vq/pkzobSHnvrjy/i5yUh0A6ZrWkJxIJH
xa0kl4Hqt04IaFg/XI2535cnIxJMMvfj9irILwoTi20DYtOlGwFRIRzD8Wv/MEyCc1jdmF8k3EzC
6e0Ix5lufp47UiwYV/vHkY2G4YSuSAzPm6+HGiPcM6fM9KAMsyW0PM+tybaRTO5qaM8LzpdfONMe
Je7DjP9/ZR1+OeKIkOYa4lLY1WwWvCPAlU78Yril1+sX3h7rHuHfkOm5FBZQTU2Sumbyj874aT07
1MhBWkJYZIZnXbzXhllO0ns0EIfW+rC+AQsMkUs7CkYeLR9+ys4UPrJG95DrtoNImn2sKtaqTtGr
Ebs9fBlgkT1PPoljKjU9lCn7yN0Ac3O7fXq/Kj+l3V0ubq1yXJgL9ACtslMuzk96ds0fT3tt2om7
HGsorx5p1wTeTHse3ZXJ7IynDPf14elWRqSPHEceVj7ctJf/X8uqKSy1+0BYfJWtuZq+xPv1txYC
HYLCwKJBLqjgjjZ8SCeqvZYyjI3yUA+xXo1A/DimBuh0YXsYTAVhmWVRRvmlAdXueWP/SNcxqeeS
lwsorqMe7POqi49FUG7N9HV8UqjukA2nbiGwWK6ql3d4kYEN1nkpaPuIWLHzvDEs8FIk6+BJ54q/
FMDOBT8cDUcG/mCGFSzn78JGs/nDKnue9ByRmSZqKTFZd+Cv45UvUo2jcHzHpzxs3zF/PSN6vovF
6WGX0bwBD0wAxuMAabVgCiAi2e1mRX271oSCFYmrq8wN8iR4BW51gDNz4bosvHezwoZWCBCyw997
uAQ7tLDFWgJLuLDk6DEOe8kljlexjoZ1xwar6QeS8D3hB8CraxFvqxsUMHlTFllTlU3ZQCHv3t1b
1SrkL2pf0ohIyNJvHkhsAqIWtPPlZCykCDviO+GWjGFAq/f1/8tUblz15MBZ16DK++DJ0qi0woa5
2F+seZlc5u8SjQTWURE0/jnG1NgYOqsX7BndRWSIfnWs2QrSnJBFYL5dox/LZHEtrl/Afjan0PWh
1HSm1t+PcHu9UU5Tn4CaprQEEgciYy35Iq+pjqGvDgyQM5Ry2lkpSvIM4jWv588EPBJ5aFbYZwJu
flUqMqB5J3rNEr9KWlKERBzS4bm2GP/G0wRu0rikcDXif1REw7VRDGRrVDfVdyUxS4iJ10U6YEFx
/mFFyNUxHSttaUnV3q5grMF7cmVai/w1+xhwpkgbIr1dGuo27WR6sHz+zDWoddybjN6o9W5BM341
HjHTWeyRYiUyMYctB++CiFZbjJGVA+m980z4QDpkMp+V4+XfMXekAJuj6UzuyYDE6fSsEXYWiCsp
wo/M917KezbKbA/ARI5vYwe1f/3TFWA+fALPu5M2nVSp5H4JO/QC70zGSsk3K6LnPBfhsR2/RJSU
PVTsV7Y2d4Oq2BvzPOT4PZi36W/APu9nSaRAIcD4n6AT3Bu7LuQ+s5HcgKT6NFvBnTrVwG8x4Wjs
czctBLxEiGJLjAadxqQiIkHXDTBoJCx3Qy9EhD00dGPi5fxMjUuNbvZZtX0YOTbboEZMwucvKjAD
L2C3/Id6YdtfVZuolwh+PEewzKa6n4E89pGMwdltCuSJXk8DxuBHIWB8I+0Q40fcfeODkDzJDW3t
XHOs05WwwR1300IeICoHmbOx70MzQl2m/8Ede889NgIah0bTPmesN/PMnX0LrpuKJLn6nFeRxo+b
3fPkrrJSejp2z9JaDnqt+bgaPP/p+egl2bvs46ek/OzU+49+vvzxkhVPoYxMKYK042MsMNwva1ng
VnvePSoewV9PVG4uZiYH/sfW8LfWjLmhg4Od+wkMhcpLbuDnJtDUMcxXOGkSM+AexWrYVj8fNFen
weR082PV5ySgB3t8i8ps1x2F6T2OXWQdv1q7JiMjkb94jJdV0aVhgxfZVbDYtVbG9xQNPO2Rx0y+
8eGpyhuyVy0VJi6UBVSn+2HiO1vGonyhp1WcCR17I2KeV5SHyXp+zHMPB+XHClBVZGQrQbeGuFEG
GmHTUXBilvfNsTXqHueLPzwTG7gHvGJvv2NIcBDeSgxrE0MTJif6KDOXymcE19W4y6p4o6dBWZtg
D4n7NQW7++YxEvCgr21ys4cTwK4eQcn+jiPLd1solZuciNQUPTZ2Uo1mx30GMM5POXvvYb+xp07U
r/c6vrD/h2n2fbA9qVnaK+ZPBpYMBuAS5zeoGee8Ou0ojwHHfPJ79V2LOwkAbS3L/9rO6xb33i4n
/oCAFbueczh9qcJ8C+qLCUA7YEtcYFwLD9xK/4FC0PTAzXtDfgQWczT2HMJ/yVrwpuYp7YTS+X9k
dhYovyR6pLe+yRh+t2l8OwsYxe9jwz4w29Epi2C/RbQwRsW7YR9YfHfyZfiVPRfnRD/v1V3pHM0u
2vRhgJ2nbbdsN+8cJZjMrijPkDruHNFm9ZPnT7KiJz2PyLImDWJwgpo/q92UWb7pOH6Be7hz6RCK
blMz4XGPeFgSpSWKUULIJAaGbjb1DinISLVp/QkrdXYD/yXUmEC9lKEL2+qut8KlaNw3jjb/jdwQ
JKyKXkqh8V/q/IJcsI7fPNoCZFGFNOI5B/iasyv9eDR5vZzu3yN3kICUfsgaluWKSL7ergr9rLcM
VzDU0ehD4jzkvj7LrjEQXescwwA30ZyyJJ31ysg2pahBMDpL9l9+uwQr5/xoubADw1MjpWr+mRqi
kPlXAM4QT/DluhuzZuYxHn/T6sSZwFhEFOwD5rDsc3JmqJYYTgxj20RCcTwu6Eob9o36F4CTS9QD
3JI3sYHex8acayXDHNNd/xrwYuWQAFofaHUuE1QHsSDKSiglFgQPX4tyy5sCXcCdUW6zNAPRDKdd
sgOiMtLdvUW0koeZzyPH666m+TD2lX8ShsnyIxWvLYkXQmCCwkquUwsNAE9oUamEAPi0AfMkRNLu
YigsNxJqG1WFXrclLih2XVuod4+Hmb2Cyvx0B8nI6CNkGQxUM1hQ/lV8XAGI5Lqg/0Fjw17p94D2
HJJtHMVVso38PB2AeB/4PVnFGUMi9v6zo3Bz1F2k7q5dUSXsnWiGRIwFC6rfKVD+eTUkENnT3+9o
aw9g0gtLFSfMSp8TXy0isl9vl2e8Ze2DCgfO7NmHbkLlXmESh1tcSocT0Q//Jm3wCBZ0LVdK7R1K
AbBv529H5jlkQvtC3xVRJ0NOP+7t2qA1pLDi9kxo/w3H7gFRJHeTEAeTHjqImQB/gKX1E5rBUFIM
ke9+BSX7U9hwg9uXJ1YhXC33g6DUzR8sM/uLGYbD2ZjrRDXcb8vEnTFqkNR73AAQRnlubQDJq2hs
MqQwG/TP8A9aJ5ElTyL0qpNMf4Z5zy7ITVxPeHYdOs5v2JQgR3+zXJgh9UGTX4IE97oNlKsXEWT6
xmdNdy/DNOUGUwP9VI2KwTq/lGNP71Jv2ZZbGqXbu673kqgpf1SxOoHGSX7mwqKzTejIzlKAHvRX
xBpSoN6sOxwbf9gIBG+4/SThh9+6Vl9d7hguZ07k13Sn6Q4uVshOdp7A10q8iIdDJPQlUCrca9l6
GsHVwAhTr9UyLKMHRZxALNJxksozFTDoHVirrKBddncPE9TUnHJpGEWhtKnwcOYWLy0rfjQWn9ig
f+BaWcJDcECfV0iIWkTS0/ZsuQLnAyFs7klHlJduByMXjLumZD/JOEhg+7F9qUk4Umq3XULz131i
aawFSn4rCn3i+J6QbZwGHWJsLWFhZk/VquEYnEEwwAkc896LUOguITpXDuvrd7Yv1kXUCFQ5TiaC
DbcGOTa4xUBsPY9V2hfG07GUP+tnDdhxol6XIIK11t44ZC361PCVzDMjLF9NAS9uI5ZrTTYPHl1+
KclgTHKFAbBXMrQ88UygmaoDvN5jgcd2JpO7t4LpPdHaitjonojVDMcfCKrWSGv1nYMxQXm+RisD
7eH0J8k9U6YVpBl3solKDEnYpziJEUnWFYwPndMgyf7oecY2DlsvusaBFdna1KbC/FWfWQ1Ek606
EuaVV6d2UTapTh2Qiltuq+w5Zaa/z2kl4/G89FB+kzzs/gc+kwfALWyLGBbpnQd81PQ7UVGZnZ4e
upTwCtCR4+7Xq3vHsmkx0y/hUDVqDIg0I3a/oXiwBwyy69v/8sOrHOXoOfpCoPl+0+VbtNEsfoCW
tElNwH62jTgatoltLNdas+XJ+qctvAk5cKI37KI4jqjigJyanfIdt/A6wBMnqUU0lLw4IYeYWFn1
TUmO5Dm/79JASqtp4TdvJUFPaQ9wSoT5GVoSaDNnl9veQyCovwRkur/f15956JaPjGrJG/RBf8dj
PwFObHZx2BRkGghtHz6h57CuzjaySCmJkChYFxp4A3HFn3Bu61uBWAdCeAUyGYs4FEbcmn0U3hz5
niBn2tY++HC9ErLVwqZM5kJlpOI7dewMsB54CwYml//Va2zC7aSmItEu4u2gd+t4ZV71ugFhyh5E
Zrmd4bH0Bbmh+FvM/Si1ATOrnk7ptNBuKjVlHopPIyJhWXgpFsK3sRo2FIer5dM9jRKyBJOgWllw
D/XNPX6JNmvLV/7b6prA1gCbbnNfb1BxGS++T7jGL5MnUNDcFUK6pyr32EmWscwX674rXcKJRCyC
0cb+4HMHgi7Gz7f107D5PaHdG19zCbGT/QrgNRPBJXYgnow6+zVw47K8vSqqDcF3ox43v8lAKuif
/qrExdPT2FVx78fUJAiaHT0hACziyWCkGDo9wuxfFXgWeBB3w8EWKB4tFqQP2/QIx4Fxv4n6i4sv
LINpTR5e5QAQRhWGsSzh6LRXA8NlhNUcC2zvytuFk1lJnLvDIGPAeRiV/ykhjSl2d32c97Gy6KL9
i/9jC8tAx5l0G/pD/II9t+5B2jBrULr9uBXUaOhIJVOPK22WR6HHQ7m+TGqKZKOy2SmJA2T5CeTV
LgXwf6wiUohGg9ER+Cf3eDKoyaQhgQGEat1ZJLcKJ9OJK+elvYZ2MIegMOoTcHvoFJOkVGcwvt4m
iIx2IDkGzOONIoEDbuTHijdb3s+Jc2ifTwJRWzV891RDqHd13RO+1QzvnFcv9qVuAzNSRMj45f6l
gL4GrSe2DNw3vqbuunA3O93ZMsUkAEMthX1eBr5GRt+O3mjHwzaJK9l/4fSs7kOy78IM6ayVg3Q4
BMOdsnaRELx1x8NVAuAPUaor8hfqADW6wB8bUPQf3Cn4bgEiurAKkPg6aY7BqHwsQ/5e2y5hqmw4
iAu+uE7OOWh5OuTm47v4rMPG4TmWk9NYEMmd1e3AYwsX+ibhXeH3EEaTAXtNRslJ/nY+Cl8G/sLi
IUOhmw1vWqDxFa8MCyIU0/wkK7Ry7mSp4o3TMGs89J5h2cYX9PmJjhifvNV9zkHiGuH3xwJdilAj
77K2BdMQ3k3BRbVzj8svNxWdx8XL3Ytuaczw1DUYZe87teEoM8tzWd0GMDwyKV0MJYBibKrtGK7w
Ew3C98ydu/mHlUW3sNcFgZSmu9S8PSxspKe9VTfD1MLZOb/FNHRAZXxT9wfJ0O/3jxAJsH6jfr+6
BaE0T4nPKeY+HR61g/qfQQgwk4Xx/WCewbSG80FjLSbocwYiuLuhAnFROnc7laxqGyGUD/dLGmpi
GvLX3uHubHdlIOwU6UE91rT2KGRySbiewfCmWFAMc3gCFo4RrweGFtp58wBKhL1BRG8QHOS8EomE
Tjm09SYpZHsqZOPYNToTV7b298kcv3aXaZDcg/zC76KtP16hJrYx/W1A5XeZDZU4xBLOcpXIho8s
BQ2PyF639p3fqzujL5BnDfu22mxqQLuBjoxMLhXb1u68wM078g98MedeX2fg3Dwlkl0ICU4HEvQy
C9IhjFds/UePY2NHB9Zz6Fk0FsVjebQb2cp9/6IlxKXdJ+CgyN08K4EW6mEbduknPDP0Z7K/Sg42
DC4XtZFGnOUFbzmVhhOPBuLsq2WAOBjqjUID8yIHxwshxz6egnXCHs9tIrR7QiO3S6Lfgt2/KXjV
lK52BFMnXfKl0soVh5Y3HYC1l9APqN/7nqrbOif9U5UHM96CJV2HBmQwIX6BJUAt1WQGkVEMHmrV
K+MAX+hFvCiIhSrWR8NS7FzK4EUtfymixofh2+nINFJmEaaT5FxhvNhV34/ePrO7wP16A5I5DfUz
0OdTW+sgCen1KqchMg1hi+rVs281E9HkDaOHWyOjyX0hzRIwFUZ+mPKqW0iKbfJ6oyYzIKVqUh62
kz+bZ4RmMISTP7Ys4hx4tScnzUuw0SMpmC8SIR59zTDZWZYfRROvQJrTlkICi34bu2evccCYA3Qu
F+N+8eZzJwpf2oN2U0yClqn8xdSOHp0piwD2jzPfHQMQCosI2Wo820owqII+CLS6e44lZbll7CaY
lPzTEqx8Gzzfk7dz+yt8zWkkd+gwRzhSleE/dc5rpZENAW9MOa54oK0TIRTi2SW1p/eKzlkk9QZa
NZvg7XrDg9yBvgC11j6EVLHaM8qxMS7ZJHCj/XKyZsx3wy/J16Pnjp2T3IhjRkJD83btxTijelDr
CdK61oNNjIJbkupk9M+vUP8CfGWJo+1B4MowWp0CAHbEzHPsqkBRzgzyQEJaAbZWErD/UQ9Cmc9L
t5KiBalLdAjbRc670BEmMWPZeEyp912/b+HjWLEnHl6x6YuCOusVWIpsTf0laGPwqRIgVjOA92qP
167WfdylxT7gMEM4YgHxeiYIQo2BcgQyo9WRo7I33qwaL4omrad+4s18gzP5aHKnXvj6J858kA0o
QHkLhsHN6tk0RPYm+KEMgNQzhJha4jTW3PssIH59mDIlqTyMoTBki1rp8YvIi0pPhpkESkyMJ8Vw
LEgau1p094FJ/DGWLgWMWpXvdIdtURuc8tkWbCNWaBYPMFbZiA76rDAkRtV30x60p4WQfZjXO1n5
TcK6lXPar2H+N9so8SGWg4it6frxreS40biRja0nFSYmAPlivu6TrSwFTfI9u2zmrVXaMsHIUiJT
8sibIAbZc7sh0uxmkgy1rL1UQjlQyUD80c97QThwhTm2sU5jXr4+juuOhmjIyf/6Jj467GvDTkL/
XR7owY4swUH77moRa3UXsfog898HA5ekjLupSPjmQT/4yO5xVEw5+Ek+c8Z0HsgGjTbWuz9lKWA4
gih8Keu1z94klcVKg2Ry3xVF5DP0XdMfh+JKKlINhugiOnbbJq5p85QR23U1PHz81rlqOIAaUFzO
OOwZRiOupbMr5rBKSTVcdJw+ak4LBklVIZVzpSqPYSOeq95/QTgyVwMptEvBhG1Wfkl/EdhPc2YU
VKr0Y8OOuc70V/ULyCGrYygRngIgjtNK+hQjO018Nqt1++uK6aAfdDF4RhU5X0dMeO0X5J7kzJqR
C79+iqVAjwgJ8mGjw8geq589+fRLJ/23OZyMllPoVKDAg1/L+pDbcV3smPiBs3eEonVu7gg+4nvB
SVI3gEI7ke8vCD1me0fJoq4GF+VYGWcE1HClQBqRFh8nWiMXSW/zUPseSvqdhqvO9ogou4uY/jWe
MS4J5O0WcULsFypfm/0hz0yZq4RfJ6KdzgAOjIygYN1+h7cql7zpFvCYvRRhXlz6yxklOQynZMYJ
Oraym0vo1QQoysso3Sziz0G7WIzsuYy9Jd3RDnjkdkTvAl+Rt+AfeI0YAB83Dqz2jpSSepWreLM6
tKDjCoAAWRMOpGdyRf0rhNdHuykq0x1EjcsI5qiS95J33XHp4PHqt1PxbTez183aUv8WLUTZNe8P
+K+szlsiWbBlfjpQxk8iL7boduvQLUdnXuNZLYE8a/KdFeBXGv+bpt2ZghGgPqTQDb9hsJaktA0I
vDj/lnWxJfWYuNVGDYJbCkKJ3QpjdXeylv1OyLQwK493KOajfqUWgWu27cNWHB5km0pYk3n+4Z9+
LP+XedQ8NrclEK1F38nMiGxedrHUlSAcAhoO7hKBKlYl2tr03KExkbcjlvaYhQPZRjoVeMJY9wO4
Zsj5VpTXW7XlOOo7gHHUrLfMQFDDbhYelGFbawJdE296erK681K+Dk2bkNuRUar5tIRtP1QmsuK2
ee9Y7A7xC3KiP3+0h/s3A+aWSARH2OF7sgX1AFLA+oY4K86TZ3EQ0NH2LcACMS/vD6GA2iirFqCW
YLcO3noXbTfSGfAzSqLfIBKnALbsNYuQMv5utkxtdI80fZ49uHMM99uuXdncmf8jX6HG+eiVzUQ5
WSLNxeP5nOzM6+3IdyFw79ldqb5uR0AjOYhxL9F/PmYf/0Z0JI5ToHsNU5ucyHUFXF/EGU+ZoZ3q
Q4tv7iLOvEvGARMaWnC/BF0QBzRqze3EAX6+o8CuzEO7WuFbz1Z/w/DaoB9xqk5mbG5w0Thx8BF2
tU/svPSET3bRYrwNxulFWFbhK1Uj4GrVBsNS4q1vn+M3wNBd+6srNMtQ8lyp3T6abrYSXtsSrQXg
OEVSPp0yOSTGcVkbW0n3w5SqeHHyJ3vSRW/51c6zkasG1Wc2ulh1CkJNG/e+OrLj0Mt4g7plAO93
m9ydfSfEEUJNotrnzImSbhp5CJkIoR1Ujd5HrpzoijEyUvSD/brESz7VvWd66WlpLpgcPa/b2tKG
/qomQESZL4vGiUCw3gs9AC1Wwqzn8oD1IFGZZGkFoTxxG1S8fvPh62K8PAQc1PxJ9O6KmhVNFsc0
32B9y+gnp/IfpLck+lbtIPy+aFHsm6MyYpqqeQyQxAKbIiDIpdpKBRlQNhMALW3qCl5xbR0si0ka
4zS/DDzo0rPBhC7Ta/4jAftMvaz3Sdpx7CNOHCLwGlauuBIgex8CQJqe6mNuMustf88Jt9YJVJP6
WIzBNxmXR3wbMK9Emia+t3rdKLAhejw3NLy/BlPK+XkrMCj6fFADMlXO6BBR1hDg6cXycu7EijSk
LzZkYwxqAVC82XC7nkXxaKfEin/u1HFRP5CT5+hhrlbOyZdd4X8ZK05zR7DVFEyvyEmSOhUJvYgz
+pcDqYPdP5YuSGNh2080grMfpziWaVdgIWUhfk0dSZdtIsQ1q2xmTZhYR69D916jqkzSO9HasEkt
It2YxeA73C37wpnaLtXzAM1v7LBh5TUn9kwsWkQf8FrZ9i860aK4ms7VMCMa3/WQyHenhnlOlexY
rnPKPakKL5PCh0eXzJ8YdJvqlwpf53QXGH67xdaEs7h72Gx5bG2MB3VTysQq+gMGuVcgHMVKlHk4
P79Wovc95n28B+f3BpqEO31nV5ZLE2y0wBT4qcVZq1vf2bWA/ZkSuIxIZgpOanwCsw5d7mPQVneF
m4WvkV63ayxmCwOwnSU/zzBQ+9Q8Ble1DfHf0qztvuFv4bq/A93gyWfVImj0EGnB7rmWmpzKYmi4
XFML9ZAYme13EyTaCUr67QDVXmNnyxXw4I1Y1hGKyQmKG42EFat0CJwVHo38dz8Qrna+HNeNX1T8
PyLFVkV0rNINmnFmlQN1PE7YVE6VFXoHtmX+q1PnvBeyyxCGiBEYfLZHNd+jlLcvaydyLEsefJso
tWvXvjceN0lQeyyEcc+pRDk0b8FBNjYVY1KC3RwvGArgV4s9t+eMpEPFIafSngaVbIBMPbwAnfHw
29tSofbQedR9a9MSEUrG4y3lnDQrE5lzfl0gybwnCXfThF4V24UWEXtiPnVkNoBsvqJQ+QoG4YbS
msPBiHt/PUyqMjtsZlzFaB1PsB3Q/uDtbtGdbAoy4jqGDF0m7vs8EaABwTBTLGavJRlrboYtml+H
icesUNkEYhJqvUy0zmTPMmJ+8+SaK/f08YCBVfHKyHdZ75mEIxvRLP6m11BQHsJQeHs2JTG+EK72
gtNPgigFfM4YLEAqHI8PXxIc4Hle3dvy359EAwigsmpjw1Hg/e4NIgR46hMb/i2Kp9Jr3baJCme5
PtqIn0MRUrPpp+E/xJ7ZNatA1Xj2+IzRc0aZ5NiI2ng0/1oOvXc5lGwaMwwJv4C2e69hRoVDF3pd
jpseHnwsDWDoKc7TiSUNoU78v/S6Xbd/L4iO4TNl8JAs8MF9kRDSSIRT/umUG4I4adbptZglEnfH
p9JLFHHeL0s2K0Gl2hDOgi71laaCJydNR6VgubpcjNNbAM2MFoQz7HY4727ylYOdfCalgsv0jNYI
adjPzgq2CKgVHtUedMJsv9a3uMoL5VaCbw4W31EnVgCbmNLGB9Q0JjbHWLKiBwg+8RdsWjk/O4RU
Rr8MEQ/z5gDzy/Bm2YWE5QKJRVUevxJ0/9jwH6NnakaoYBst1Goy/ZrDmXhb7B/QUTNg4+UO6Dh+
kNNXO1ez4sR+dTEIKBuoScBmaX81YMGrzh2fPm7Nog9Nt0P08F2PTqp04jfIAlKyFzZfKF0AP49Y
8VksDNZ2ah4cNn0mxR7+tPsZIhO1g4Y8Z1DuDm7ZP6TVvBA4VC3ufgg4s7b3bFovvwCy0J34gBFa
o2ckI5qt/TYssxW6ecKrEzL8xBXbNfA68nGO+oGO8ABvnlhpV3rKzBB5AjBc2jlCu/hyBTp8Wtzw
l6VZ5eM5uhE1yOtKNsn5QtmgsJQXjRzZzV9dR+71fSw3uTO5ls6va2TJhfPPT4vLufuCakiAoutq
YuA58AZxufa8RS/4CsKzd6BdKkZR74ni5N1n67DrDjRkobZ1GU/OLBRC/ZgaTZtUZuXOXrXuy+9S
lFi4fYXmYLab101B0Pp2ANGYp27euMsOCKZCY6CgvVrP65dSplvM4FNEvqE7jeEczRS5bKeut9Af
zly+N6R93+m14wWjiIN683uK5mHuHIVC1/d2E4c8V83wOaIg6XM57T6kSaae9k6UwfdjxBBlZ3p8
9qytJhoe2foDi1BbRrKjyi/tDOuB3g00ibfFkLbWBOR7Imin93LOT6JegT/0mNYTYyZBCF0Sd61Q
uqi48mJt5K5pkjwarN6OErA5kyYVG9FGIhrbUkzjLDGo2gOfQyvlfczfiYnde+rrWgNhHrdMjS78
EVRik376FEgv9n0qd5ukFUwuxV5FqPHyPtpD2Hu1i8xTo7i+z/+Kt/dBP3FK2hXOEfPW5+Xtpccs
zXHnHzuUmoDucYG00l8XMPATOlHwwhki0aVdAd5n+hM0p/Fnv3DbefPTcWLo4hVgwBXGXc6ilzH8
1/V4oHJd1Gi+MKZN4VPNEDpLsj+Xm//to0t1/O9cQZYD6TDNzLgXFgql5oI7ODpcvzKlcwrS00Xv
phSjanmoK4Cned7XCdNEPrXN13XG8+bp2XYnhCxAST0yk+gxJ7ItK4myZhiZ7KQ7U7+LIjaOiN+P
IhFxl+TLjctQrJ8Bt75tUYKnhY+zK88JO+dImUDHMGoePYV2uBTZLZat6OFmV57uIG7PJefXCegu
ULS7kfyNELS5MR0xSXETAbkMQrbgV6gSrwO0m5TtTaYfXMP9hmJPhQjoZ0cWMERNOPmFcx96wKKW
B8864qqM15cHp3AQaHT1bl98MoJGOfa7a0TK/KyYcLiqR5mrciLoEPXQox4td3LeEOYVX7cgtNzA
JBkZEnS7AkOztEiwt22cEtqIZ6lNJ9lnj66Sd8QeBLxYIMgladg0DvJH+VI5rHdl0NHKviA4s54z
UE5dZUMIkzZbHt9tMjN+PYPR9CeqKEQF3JwaTVMNCz80rsmvM794srelIAvx+yMwfVx55WnbcQ01
2Yl3R7amVTGmB1wXYYw6ovtwr/0MriRJq0gyOY9VvU6g8OfoEM+QcES09bGQDKb3c2b7aeGLZrMJ
oO8rwBe6FlVvWYG8qBnjojJk3Da3Q/HHlzijz0OIvxHns1wZzUp7z54Qkf2viAP3NJG9zc+TA6+T
bD3acGqQscvZySzq0PuBckJkwP/TnsKAVCGHQwkgcckkoCXSxfvwTBoppmxuEo6znHwl8tv5dEBW
X/WW6UiaYx8jvQ0Q1FiQzwq4suGpN8iM8TeGf0csDnBd6+7CtWAvFMzrmH3kSIHoDbyn8XbfrTpe
qvgaX0IjlBl8V1QDK+h0AJvEkt0NMJzQp0w6eNb011PbfaUbuWgjwvOXcUH1JUQogGqZl9bdN1Ph
VyLbrdaphNQKdGr4p8sRfDJwxGnj3mas1dLhbQXggEt7aoQfxgHa+cm3xLMKFv14zGzgkEKovxqg
zzrI9kwlpZ3sASctg3L6XkGLvjKevhI3BCevNYC9C3kSBH1NrCQcUBy4ONqHXNwtkYElHIS45Alc
N/8CpKr8gSZnhwWj4WokDged+pEWmug9jSdEto6kmIRlcWWa8T6islueh/fUeCy1gYO8hEOO6DGS
NgiKL4mTxsYVmRAfMwVmyGOBHijc5LsOZVMUVo7ovsVQpxjfIIfPnFYNQdiMqKtHyIpslLbLVRlM
oLj9ynSh4G8eIFqKE7lluvziH2Af+tVOCUa7w6Mw9GbLDkGiRgMK6jzbDVHnfb06epw5JIMNzlBY
4vbNk+JtipwpVi6s8lf374vjfVq9oBYcWPI+H6kbYtPL9yhhq5IqJVc9F7mKho1kgH5jt9gTAWF/
kP3YMIAlRV3vqd2p3I/5qgCz118/8RegkmHZHXV134RgSVCdfCHw6AP1aUfij+x08zVZQTMd5xrz
Ksjn5KfrCWEmX/YRP9+LpVbCuVVqFbJYKw1yFdAuMz8ff9s5iG+pylhwYzhrIeYFY3Rn5F68TZNu
DSb3NuaQOMPvMs6DFg5/qyxEc5OSRrz+wm8n8U+MmjrqU8URDb6ClMESlyyMSsKBknBYSUhqaqWR
qOuyIGoDg39S+RCbghhnTUdW/KTbj5mi8LmzqLpCEJ28NUTf24cDKoYUTX51u16MriyeeMBJQavz
JCWOZzd7/KXPvjCWF4PM78jvCNlOBsL9PKGMKkd1t4l3N1+b7ARRGOgczRPjTrYbtq92524WjC4y
ncdzVuFTM7ZZPtGDtAkusD9TXP+3zvyPCxBtRoql+iDSNfZM+rhUu+YDBiJ+UF5cYeUV4+lNb/GR
TFp40Qp2Y0cxhMvNT+PTe2wRFcbVyLyuU+aYaMhD1b1lq4iY6IPGNhbmjcFT3lT3J3ouBCF8kVn0
PynmGC7GGQVQ9jSl0qWEW8oHGCzLGKjcMkx+sZNa9veWUlLBAFCEz6aolgkYfCq3PXIMiPZCp3aE
ts7/jfMHXFjqY8roznQ2RDdxILsiI1cD6DE3Gxa5pN7RpKeQPdur0syxgPnraTLAhjoApiqhZWI1
A0Splu1I7Dskie6ZNZaJ9wzXaWHqC4acXw+HsVVKMJVUuhTg9mNHMSA3lk6h8cuxBby+zWgPWTzD
JxO441QF++x1e2fetWEAtsyq+eH4cE+CYyUVit9k7iqZZELahASNvih0DVI83fOl+IUDF426rOWt
UxrNImVZGspbonVoiexLH7Yh1Ino4Go7owR3/+SxTanKSOGkfv7l10GwZQDIk0t2uLSmE0vBDxbY
I8ONaHv0SzphLbyMv3z5DMjVmwmgAgvnDwcXhvF+wphBjlcts+mRronG425Gmh8hXfSa3gxFP8Ox
v1ym8P5K2bwX+BuodosUHjzYWw/wponPmgZYeyc5L3JPwQW3+T3vjm9FKo8DSHeM7J9HovpA+UZW
7cjqhit3NpmgUDHZqdIDV0S5t5l6PJG84IGP6JALquwLEtynYd+9C+2NHhb+gTIVwZCI3HQbUuhd
w/8lfcEvepm0h/qQI13cJ1XMGeJIs4oQLC51Yb7G6AJZQcvCjjOLQ0WRw7cl3t1G0sGhN7wr1b0a
qwU8R6be11rlEsggQMDIKR/M4iQcPASCRwaDzZtbnAm9Ako4D9u5JCI8P3YyA/aAAPmgyuf9dw3m
UCiZYAPoRNeYFylxjxJb4RVDuz+Ce/IumePOMvwz0J6YZpYwJHxYGkireHmz59IUttxH7wJ1YIP6
eiG+klR35hwFuTRO62TPLUjMguSYmogfvlD5mBlajP46m6S9hJUgKA7pamgMrxgkwqtnyDgGAlLL
EhoaKsO84bbcvUaKPLdSdz1o7EgQoNeg7Lbj566gs8GB1W6qUG3CgCat4C8t/URloyzzQwS/h6HL
CsV3CZM54m4xqo581FPxR1EWMY7Q/xHTzvgfC1Wo0tA2AERxKJ8Yn+Y1Ab77rQofr8hotgDcV47M
s8SauarhyOY1/++AQgD5gu8Z6u9oWHXhv67pQxhegWgf/yIpTh2bBq4uZrixUUxu6JO6ZLpGmeN7
6W63kQxhQg/weIPLdETdGTqU0Kuo7nGbPQw8/E/v06pTQsb4dBeYkoiM52LWXAu6unzSBrnmvwfX
almJ+W6m6M7rMusQKdDjzzUx5PbN84db0OQsReylMjjzQbbrOWpsG5NzE1dE893hCQbcNoGQ7Od/
74LkLZUfzvXBov6APShtT3+PPQO6JyTRScEGYDTp41agE7xJ46dpvgK1IqztZH9cs1eAHZ53haYx
vtBi+5Dwt9lEl7Mrs9MnHcCIv0SXOu9dLcSgZloNGF1rHP7gVyVXpHI+fHX9ZcMT8mMqpjnXWSTq
ljknBd9H53cWQs+WlkwhnJHtUHtmY0YRE9RL4Ndwq0GWsjvqiWjaPE20W7e+50EoempHEeZ9rXW4
JCFRre7vZOKl6+1Bmf8BN+fgCfan2p7vZTAgoy/V9AU9/qv19Yu09abM7K65JlCxcn4BRDgzBISn
70F221WafshcZaGPLvgWM90bqYbx1M01xX0lVBmCph5q0dfdkcmjPr85CENzfqL1sXxST5oQ75h9
25/mxHg2aGyC5DOfl4iHBwxNu1zkiQBaKccB+OJ5EMIciEk7SfnvWthGuRQXTOTr9g7w5Xuu7AxK
Mp0FHzZwss8hweF03NQ1oi88NPjuZPTpfw0mCgong4YADz1VJVbXPB3zUwvCP1muoX/lKYeNreeG
5N5se1BgxD1BZy9y1wNyDhBK98gmPhdbWiWSvQFeUUXK5L4CLFG0q2K7uqTXkUt6KgwR1rKiFhuj
BZcSIyFKBR37lJVu9NHb6/UtHmrFPbULCSi91ffBApLP6MQiKWYi56NJ000TL/I2JjpqqAfqEhA6
cW/NeaEeql6Q3LYJrUGZt4ogey+fwt/buEnWygIzv3PRIoOTgihBecEbWQdm29mFTAg9LafV42nq
wwRDN7bOtdX7MdzrPfiTGrBKYMdwhd3tCJQDte+HHnDDQUhH2W5L2KOEd7rhwCn94LG+VkDm/n2m
hzJKPb9sRTg7OERPJGHHDMbeXvyKJkwnFsUDE8Lj9NZCPviUh/pzQd7FkFnar13unT1SpFF+fbs+
wIgaotSafV6XUjRBPIsy3Zhl2GofceePN+cyWvEFUv0UQUQgHFGx+CdiJAQcxrg4wm8OmI+9mIFD
v+/V4dw5p5zF9F6m513U/aotjC0niGJDhfU4+8yf82wNlseVUcNsfVkfS3rl5TqyY31L0DxZR997
Y3UE/0NvVlbQwyjmK35+hWnrcHRx6WwdsG01/Khw0VvVQE9maeHpEA0ThK0vtYw32EexUoHzBB50
rcSZVcBqP3nuQigLmImYoZJc4yPlxmWGD8Dp1ew2F+5Z9WiSU0njMO3V/P5I2Twq2dNs4mW/WBuI
Hco2OtpZXYmjHiuurRUbYLJvZWD3tmizB96/ZYzQM56eZLhmxLy5navJeseFGh8gXNVMhBlvsLwt
9KWLrFsYzi3c2jM5F22TtrAmIG0KbQqFUj2j3fOW1BjXj6x/TJwhnWYo7ZIeETkSvWkwJXz6hBRD
GTsjR/sGR85ySylGOP4QurlVihrQosyVRa5VDYTs34VmMg5RJErjNbR+QBr0LBiSb8sfLEkoHztf
yyY3l4G5OpwH+HUfDonHEsX7j4+KCkvRLwaiE2T/4Z1QNpy+Tilhbc7mYJxx8w9rWWdq/RMr8FI4
QJbolRdzVSe+8SWxnSW/ib5wKOPmLAXdXak9SBZKaPVmNJZoAeFiOWSl+0K0aHSaEDJDKkY+q79U
5xrbpHUTI8YmlXP79p9nRj2LkUTQGJpnMbNHuaXnPauHGVD8qT17eRYOWx0e2C6AeJgwqDLWVJi+
A4+cTPUCtOAGIWe6euyDfj7t4MjplzXfzedSX36eHzZGwJCW/AVN9lGr1avCnpnxErgCsXeBEMmS
73icQfRjy2nQ+25vfqOuVKVC80xrmgn5zsl7jtTTjjDu531WLfQ84cqQu9bet1uWK8KjpTrjtc4a
xrYQNtRVFBYTKpOZcx3jeZy8NyhSFCGILXlNMeOceukSkCGmEgNm5XC9wkk+aahEXtCzWdONYL7i
tv/36pEbqKugsE+lMBaIlk/D8nGhoGEnGsGFBCD71Q94jdJilNK9YiwfMzX35dn+QCK12oYAOoA1
UgzZxMVnvnNasiq5moWYWYuF3AmeCQPee8Jdb1TNndLKrCzCUnPR7mtY60yFumVn4fBhRH5HpzK8
Uez6soe/bTg0cMxIkNU+8gCoaNMVXqDixhQbaqmEIi3PQtMd/LAPAHITPns8sflMId9DB1hL5n8W
JHWXQM/CdLT27hHEC1qJtaOPaeMRr0bFFa+3lsLn02e64FoFCNPdlPVwFEU22XfNnzMAQvP7M8Ez
LeXj7rK+GFASoLlJ0udWUGeN3YdRjOScnUkMlANFTHnyffpBSSCNcyCAvI7OTEhT0BNosg06yyoz
Q7VTQfkJMEAmDZ3E6C0DpHhTp2ISGaIaWJQvVBB3MVO+u5RrF8clmklhoeZQtnzfnG7nCM1keadN
dymHfTvI4n4yyz2U66fSVwMvsOkyAGSvSgS+TuHsc0Tdu/j3kArb4+zNX9pa1eTzu9CmzxBUGV3N
DdaDp4cJkwMo0+pKMuXazfy7vYo4ymGXVmxCpUP/lBrpeh5eqbEWs+TIpvs0leXZHI1tOuMviFCr
al4kQgzA/7Zsq5DLZSP80Lxbk1fu7TdKzARHf/BRp7lEvgDHFisgA+16ChD06CwEAnJqfQgIvUtF
GMcPnAX2udihq+XRg2KUACICTjULuG5ooBDsPKE6vIG8AzFMjqHjjUZv0blGYa+rAgTFfkaCEFoI
E/zn1OZnO6Ca7HipwNJioYjnr5THrMXfSETg7boPA6050stClSe2aQyIJ55lKj+X0UxnQsM2es+f
X54S+Zry8dpfscTXzRaNX+1pRChYivbqIm3Poy9ngMdEUZqIUWDoYjm5PHVvezna0k2FqWTFChMm
4SyIeshnA2IUabj1NmcX8ZTfdgSxPs+nzpMjWBAh+jShL+94bFGvfPbWbpt20ZnvgUFUEV1HLLY+
WxTUCoWYoLFXiSYeVl7H3GTS2JFmY+RKBIiUvxuVPpt7Q06i9cmekMuNwxgCN1Wr0ZkF0UJEBrHx
xcAk1vf7ExJnYMC9i5WDJUcDrFfbgkZbhKBiYE3+DDXJTspukyFBYzPRDj5UdgkqMAKF2+S9fKCq
X6aa6v0juRcs28hcTqWC4k0Ib96vgFZgq6F5RwXCluioAf1rLWg8MdDm+Xze1rEAnR22IqqCN/3D
51nMAHZN0xeW2siSY5tBh4B2dqlDJ+VhZlSSUn2V/EFKCKZ8XtUPjCcJmvyvG391o73rudIDCJl3
+hAZ/GExVPgOr3yjbCyCfXNgKW4M6OsjnKVcQwiOGjYzDHzic07wFPY2/Le1XbDEhruZ1okIvpnz
3pSkuRAkinhgyKpxuIc12NjQQPmCZ91LSXZm5tBOoUpZaLFDai0CPpdkpcEai2MQ4u168pu70OXK
2ms1A6NhtM1bvD8y/UwQwmAlbCTdAt3L0xvulO8cxogmlSHrljVMHjcWQy6H2eWFUniKxF0cZotq
CzxyKq66zZ/D7s7lPyq8FO2ccWCgYGiPZSpxm9qN0TRLoNqRuyo08yOWx/+nQUwR88MIKYX+8KSK
l/7m2RYa6KSfPMa8KKc29rysqHIgYj4NXq48130NSE15iYNF7+qGbi6nZyVGRTkeoRuBP9z0WXLd
r6vQoBJgKeW0BqQxSGBKWOkXHwupJhGTFDKjqTTMmwsv25Rkfdf+SBIYq2uJ3LpDLeK4e6uEASfl
6veSQyy9ECp4bpmHUimn465P1dD1DPf2TQK5imx+vq94ZZMC0sQAe5r44uLJD2ikV2U8wdQutVCo
xF7Anus6d5i2lU0oAHTwGzXKONU10mHDodvhoSq6uvvYYrRYQE8bw93UkIutjaL+YgE/e/lPuMiP
+TP/WJidJ0XZMt9ZYkhzdqR0ZK7Q7qTvtr09mYf8HRZd1+8HlsYBvV1KesRTi5v/zxCLFFhAUsQO
CRulCm4d9rx3REpz+WIJIF1wbfQ6lxcYj1AZN9PSghbWyLUC9M7L1Fu0eKn/mAjdOSCXObQL8o+H
LUMh6qHMm4HHGqUu7rnumq/Ly5QTvWXkEzD4qfm/NakGm/XwSaht37boZabn7mcyqEzICtGauOR2
Tn+IphUC3bSPm49Ul0VYatNtU+3gt9ueuqNCDzYHxscRkXD0xB0ajuuUpQZvI0sGKX0Fu2Npf7+t
Ie3WCkl5rek8zPX4RKRCGM1VdETiqSXrwYxZXGxdRaFAnQpLkuHRzmZHZP88GrM8PXZZJkk+4baG
wwr4YGeMaZK+jEj3WGSW+K0TpJ9UOX/xiGGMOAUx5vYxz/QCH8tI+dDRRq9BPG/MsEnQeF87D8fE
DLSThanmhKJylq1oJyDt7Svt6zqiCBauSQM80zgN5fbKg3wL2BsEIGITRmx83t22bMqIyhS9H//U
NJykwgIEKobJ0BSayyUav9RbiHUDXnvC8FWw+wTAL081gKc+1N5a+aT29pPdzdBktXXDhfdizwDy
Ef6sONtZHlOr2lVn5zjhpQ5dz2HKLhUpSybM1JBytOgXuD5opt0WZLixUOFYF8Ps7fY09BQHyQc9
U3dNnlJxDjx8RGgrvx3ClkEXfznwaAISD3tbb9QVbnX/b1ni8obyBoqMbvG0QEP5pfc0RYkAlnIr
Fa1v9IAHAnBb8PrJ8/jzLmNF8M5EBdhEYv3hdn3FsRlLuOsjt/cYAdk7ZlmntVIS3pEy//CUp7Y/
1u+q1PijPthvioPZNd6FTgXtkFA0zS1VL6+SIuml0K3+8H8YD0phWHEcQFyabNYKmJ4dAuiBAqX2
tF2wAWiAlL4CI5+Rmi2/1pE2FvhT7hPdgl8KqxYc/KHgw+wt50vLz74E0DCGI/wETSLz3PmTM2cb
dey4PuKY13yvZ7PB+O/OVOUQasAHDqpYmQgjV0rSZ7CKZFJx0RkjAGE4FWpwTA4K4NlGB+PT9JaV
HwVjUHJpg+tdb9qXcl/Kiy+NdwNX5hMdXZIVf5MVkdfBi49Gx5NSoUootxbUeR3pqS5U7xA51YeI
4K82Z3WtX3eZWngfotKSatUwiWklWGUAi4ait1Cst6t+JNvNfckqF3L+nvJSvZEQqMHtAlhgmiQn
IvjM0OvFadOBeP1GDdiywdcDbM+YEjsTGnYA+uEeG/N/muUxvHlDiAAnW7rMsXeF8XVTXgymjf1U
FOEic0ecN0wA6s6aga6PH2HuDB53wVgEd+YkAZTGzF4OA0vT2XL8swgD5VdCarbEZc0MiLRLv8jJ
aVrs2H3y9qcyDMDNI8IZQTXMK5o6lUdMIbTCJHTSSisABUywLafMc7utzscONqonumP9mYPkS/gy
UphpIokgKy3cUULEqg0mFg9SVB9aSlIm3I7zLgIkSDIiDeC4n10BTPYOqcuGZC3i+EZPikOKLVCw
TEWiqQYrfHjC0PVCO/oY4wmiDA6Lbg5XF25F0DzRW+HjHwT5PSMYYv1zpas+WyZNYoLtiu21OfFJ
D9TSe4a8RycDOC2IZM7bt8ZsUnemo9/ZvOOapXUTYLWLb+O7+fpGW0FspuyTZENPp0uIn89vzzJ9
HmMiC2Nkb42E9gf5kmPJvSXW0M9RTsjCifU+vVaS1ttMGzxWWNUWVcZTXi0DhcXScLIimPu30Xc7
TVbyNbIaF2p6Fvw3UY+0b+JZ4Gk/xzRwwB1U/xHWV2cAKskAAAQVs1sW2yoCEPfhTMjJU9uUiqj4
CfWPB6omV6UzzyzE9PaY+GdP7ExVb3rrmRxK/Wj0XgQxXfZrOYfKOdfRkiM8bKBM4TEAWC/bsWSD
3YtpcI64huqCCmtFcq5HO2sdfXq3GwpSfRCLXuUMoyca8iV1L3nvNwwZ5JkyeY/ekDBKTwCGv1XH
8QrBXgKAXpgIEjmgW+Ub3g+lcg+KhtXFihuV8Vbg6UklhqA+cj+qZ9EV7wTlNPlOs6YoerXn4lbz
VKeGdOlOo3154dp4MXeCBSzucTt1aDkS+xBoPC/KhUixTLThahVdWjRYwRIjIg0itDy9ka+szl/6
3CMOJt/B45I2nB6jCv7oR6jJkLO9BkUjf7okVLTBKjPzzSS30Tgxe/EKttP3cIJAtLG5TwCOYoVe
spHeJKSiSRlukTDrr0S+jn1i1RVNYSAEEZFAIthYXF34rjqL0H6ZPr67XsWbzZwn9/+COsXa051m
ktjj6mO7M+7Qm43BnuDmWvJ2g4uf56mE5oknOOZI4c9Og3ueA2OxRlFv1f3es+zySYcVcJABDgKc
90dep8SmQPgp9QgZyvMlwjkQkq7v4NMRuhzhtG4+RRandJwrabfI6SmcXAUHTHU1I7VhRY1X5T8M
UOqsfEw+2FmWV/ffrYoTVc1fUCRJEfqSRfC9YqSMRiJXD0kMTV87a3ejvlXEHjr6yl9Q7D1A99KO
memJEsOOenJ01MgEVirpbRXrynC+omq7HHZjy4rS+f5vQhIi2SZIQEe+gcAWP6SXGcIMzL+ylOsu
DKKmXuY3vLKQ0T1CjAT6n11rpllv8k5VxlrH2XKcbw2tjjZaKriRyXZISl5+s0zOAto3nbbu+y7b
iIkTZ26gSGi6qG51RCH++IjGwcqf8WyUrIfx0XDYRPQTNpkE1sG+UE9WM283HHU6hzc67DncA4g1
RE6QUyzgOnc/Pt3CGfy0vVkPJ9MCG4yXRk5hsG/fYd/weBHTxXCeEGGgGEFn3Lfhj2Z0PTLvY9mh
En9nUi20ezHpubLXbWXDXEdNRsEWEMd+0nAxOL2ydfFZqrYpBQRPUwo3cn6kelZ8d3iDPkb+EoHc
USKCSdSHHbeTaTFVvJBKxhP5Q3zxVzipFS8/xy1HTHCWEhwRFOXZedK6tXLKxsy3qRA1QPeJS0rY
dazkrzINjDdU54QmKzSu34O6h76EUuoYP9hC4qFo4VvaoQ/rDIll+uHfLR6LK8L2kLFbVmoV6wz9
4zoDTOrdjxRUYN5vzuygndh9vOA3xQWJFpntfWaB/vx1Up5L7dMUAFSBuVzOQNC9SUgtvUAoQkal
bc3qQPCUqtGhpP0/opBRvuXA46hhgUi97nKApUYFMmutE+l/f6UDr7H6jewMJivvekqqluowZ0Ky
pR3lwgACSA5Kx5roLJc7QZPTQfxo8e6k8oN4oGVKjg2roo5kVRMeEpQl0WAMVPz6H4Q2rv7ZUtxY
CtPBYBCwjPrMl6SapxPzZh2XL03c5LAvUSq48hpz/Iwnr1gMElvNbqWGtqGYVfMGTmcB+U1pNB8Z
8Z3Nov8isSGCaDVB1JNENyUhpAu+WqlgPM58zxFxzylbVgSBDPDaTQMlAehGC8mm9itHygb0CLHi
Hx8aMLduH9T1qYnt5bmAMawlI6JDblKz/ZGiZUi8YcfrvlIjxyC6/MFE0vAceTyRaqSCUv+JYRl/
LTATCzKLp7qp2b/LMCOiFWuPOjYIhFTK2xMms6AjLn0Mzc2u6ClvRpZxVqqeMbciKg8gmmD9jMs/
EqBqqnOqBVNm5DbQuF1nIH1fnStUNKL/SFCKaW2PFtsiLWYHIQhmTs4OGi5T+iw7FKSv9tJhXhvR
Ke2QeM8zDJJOIpsSEEAQh91VnamMsPPCCX4xIsBLKBDiFg/f0MQqUzh6+Y91KLf6BuKmu/NX3LY9
ktlLDBlPdoYjzrjvf+zZCjrZ73bc2PS06d+xJlaYAeA/1RyScJAfjovEhO+0MXO6TgpgTQB/betg
Q3IiXdvN96an4DizEqDq8393uMo+cPpgm5Vy5UN1AEKq+AC6sFlDn1nOdjh3YbgRMHtcZUdAfwYw
a0X6MmkDxFARJmaX7pyPPlC/+hZ4wSlpYpkFCdv27CzdIGMhJAzsjyaWSfRCZ8UyD+iVkS0fsI2V
N49MeZybdXZ4n4dBbvQlEkyc+nPWmZZMUmzNEN5BeHNvg3q2J8rrZ0ETFFtIV6Ph/7kPLVAJc7Bt
whaakli9V+UN1j08fh1uCP1NdEtBRScvvNanW2ID6zYK8CPzvk9vbV+OoQRTcrpHhVmfsJg2COKU
UKZNzMXNNMNCPLeldoYaAfwhA+9yOZ2XFQdsoZLRi2JXg4rghdKHpbFDMOR6BagiXIRNFhzZsugH
zzZk4DO/JbEclyCxk33055xoLNpD59JikqsvPJkmtGm/K8fFlJp/Z8HyCk9S5TYjSmuZZgJ1PvvX
1ZVn2x4PjwKije8qUzjhaiDvdf3hoN08Oow4rd4WZlq3sqnhFt81BtBP0imsi8aL08w6/NAHk6Nd
inWrhxKZ3vSgiQhOBwFSFf08V7pw16ACQXBIKMsWgDeSlvQjr4vJX2YyeecslbUhIXTI7o+167zb
wo3rNa7F+R7Hi/r5jxDCxECIa59uZGLW+jJ8HCSs1rAG4s3vnWuto1MVO2+BUxacif73BmHrTC5k
ueCeLnSa1Y0rgWBTKE6hO8frPRgyzo/lFA32H2FVOmo9cRTbJw/aP0M7WEWg2d/qy3aX1VdS2aVj
pAq6PvHk6pkDeTUdqqM2f67dc36oi/2gLPdAnUPBrkAbN1ZZb1y8MpaXrl2slTz+YIYDi4b4ulMQ
ZYOjome24Pj9YJsaavGv1WOpeqtEOW6+KMwjYbSNgaQ8khKPJZp4MUaReO5FomIeCfF+EbUvCsrl
u2A0tTO80Y8xkRH/Gz41brOKFi0Wp8R+GKatloWSrQIOSEzfcvJiGb1MrkVcL1PGhtsKMwNi2MsT
L9aeygCGE5PtYa9fqmhhnUJx1nd/TbuegGxnfolgSqN0hP7qcdQ8SQyguAvzkuoOku35FotWwd8k
HcRGH15eUTiQW0ZF9B2B8DbMxp1RsiGwOBfd7Jc5tsm9oaeomebb+UzuL+b0q6OHc3m+cKnZxAQ4
M7uNxsSRMiTfKDVBSvJ3cgvoGs6OHRRsQfEdCzd/ZnTtWNv0o/sktRGj2Ivqr2i3gPLK4j4oHfSh
dtr1NOnCWzWkdz/voFY9xl2qBPUbA2diKIUq12NXmkH0MtaO+CFtU9jkgNN13XQJyUK8ObLFdEg7
uoCUcWCXqOxCTAk/2/KhKXSPuApSGFAISHJe45v3nwRHvFgyiaaHFWNbEDcnWMaBVMlQNC+yW7MJ
u0wfFYD3e6CsNO64G135XEIf5u5nzQraxBb29eAiwZHBZB+fkce8/RseYJ/ciHtL0KY6BdnRkZsv
s6IaEDLYcBVzxGa9LF3raqyn1xS/ac5Byj46kPcDAY6d2fVcpWI2Ro5B1GRjJka9rxufPbprTrHq
bOc0kJNMcrOgNPtVygtEzciSsk96wKG4U3V3kughj2WQEgT+H/jUhJmL4OAaib1D3vksnOWQXZic
GwhEzyHnDSmxoMZ0LCGQ6jp2Dv7mTK06bjfdFMqagmNvDUw6D4thgY/nu723AseMCj9usXsGP0vQ
Wc6CSgnRD4Xq6lD1xWv42vMCZCJYvBVycZ8SwnteP3RoE1CY5tRVxxfUtCxqIgazxIeS6+MazCdM
ik2AA6mOIFm/O1fAMEx6WlmKvH3rWL3jMxIh6UFvRmoWHKRT+F9fytwHqAlM9tmvksXfNZEtBT39
aFHEQC6Zj2ltSxVR+kwl/n4a86flK26jsc0upf0n5ug/ZkgViDi8MU3PvTuWygMe/WCNxMjbUJt/
Dc5ETDW/6sugINETwC7LCToYDvXaH8zKL/zvd4pcAw1Gq9g5SRbo/SSd1EJuIcIrQn3/gJLO6dGM
FehVZyRqdCLhIAYt7d1g8dOrWIsMfqbr+ttmY5muveBvCBOp8r9et73CPDW6wWcsCEBJgjqJn84j
eKGNuLXjzWucgzyK6ta83aHvFY6ur2ILTzaVDHMAdfisKIcZBOhP0kmXpn1ccpi9jQgYgCkovW/M
AIJlolU6vSqvKL4gvkbCHjuiwoijAhpVQ28MRorO4cwAXlyf50R2ireRNWPgg2zjp/DEEldng10o
DlzSG4ZJq+Sq4zxz+mxieAilojhLmJQMUGycxAcOBT2V4O7oW2/ftvpDcxPoL2sT8z/S+PD5MvXe
cYNDCBhWDmVTSrz3S03jVip9LufwB2LePQsoHcDVffxtTVhRyZHgwgpOLZ2/L4RU3Rt76idJoiee
3tj9S+ubVqzXUsmIe/ogDBIgahbfJi3oDHTZv7MoXiKonJmYMSl4P9W7mNtlUTsTmGQ7rPh2lui+
7ss2jab527uyrZ0kIf01JqyA2z8mLyDMNI1yQUcwZGckAN3MFkNA4iEpcBq+m/yQf+1sG3LlaB93
6p8If9RQ3qt3pNyEX1H2n3rXy/n4kY6U8KuLS92rXrSlL8VQ/QZQ3sV/hgFppau2HYDBHxdR3lTH
kp1jNd6P0qwhNmaUgG2uQguSKHvsKlT2jRwm49/KRCn6mbC9sDHZnSJJchEMI35u4CtdeVRWz3kk
iDgpB8NeOUJf0roATHV8uOC8EpfnFvro28jIux55uU/aqyyVP3RTTk8iT+8uFCIy/f496YNxnjBx
3sHYFs9u8QVw83aOz5b8MDzM50BBLLBpOrrGMkBW+HheMcvI7grOeZ/Qo1NdXMne+uYandgYN5To
VDr776RJhFybGau4wkfOOAhDk0SPTeAYw7FXijYBly9cg1cgZJUTWiICt7pldk2wxDEQpuN5qMr5
4kvVQY3ZgAoEXN7fRyzmI++ECpo8hepo6Gh8McSDnqysnqDs7DA2WB0Rf0PcbtXv+Fq+Rr1V2feh
TOdo6OAKQFo/QfxpDEBm4xXlzAHu42mpO6tsobqkNyiP+/uuLH/xd9AezAGrWKipDPJL2mMMRaVn
7G0bGMAaZPVno5aAMFKch6/Wh/S7vNRcPm7OFAJwPdldTOE/xjF+7EBGDMKwM6a4CHEaYQE0WY7u
lXlqicfzI83bbIC4WR1IlNZLfJo855KFwQgTUhrsjHrKpCQGSXXJvuUgG+kf0LPgj+vK7Krk1ge5
2jm6dLxL29p02Qoec7BQd9VHWHOGIq/MSStr5fkDmqZ+WI793Jie055+U0P0DGWe43esywx6ZLqP
Cir/QI22Ox9Jla6cxzM8MytlUE90wMBc2kNlje8S1xfW+mIuK/24cLZHDjyjXt8pmUnyq0rkqOJT
8Vprgy+AWXX8snKKIUXAsIpaYJSLtlhrkIgLbWzg+DQriRsXketwbTGoYkhlfwTpTYrlKeDkAS01
lLEd0dsKGJxfHIpz4TJASl5PK8O2wrAzpFpNHeajjLZ+dQubCnO0k3KgLdfk7FblOFtBF1UpuqRX
q0e/QrSNNAsb/GLMBxl2rIR7BMzsEzL4gHxfyT3ky0EqXXzjR1+eB21XzZrVFx5hBR/g9DDIwb8j
3zAT16gj4CrAif20GIpDaZtpBRLpDsfssQOJ6P1m2/cFrHBLftzEhfHq/X9OUSAr5IEj+WzEuZY5
2nBKKRrG1u6YNMjskMNuQkEKur96mwNcQBdU/2W/DJ1hOjyOGR1L1XHX8bs/xw8DuRRWBaL0zJnx
dGBosfBdiFkPvBHLlXIWzHPSHT49fQgQiOAofCZFWfTrEA97T4Vpgm7qAUMrALDDal806vYLMG5B
chW71rDsF+7ld9AZHBP4WMEn9PczFRI0EtDh3QWAsfvmGfwinLj/m7k086ZfORK+g6/PBbURSJq+
LAm/Swptt8D43Od9IHrsxtcQHGY3PO3bUlW6Orv6v6mhFuxyo5pPp1vpAFmZP1Kl3amodseS9xzq
ii0tLqt0ve0kgzaDea77k/AjceDKDVBqVMOJTdT9Yi9onsPj2SeDfsX2OjWF3iZ8D3rGRA0zRgwt
ojC/xKqMzVEVJgUmSLpJAkh3DuCbw+zSuCpKUsB4bARjgC/SsWkE5L8FiZLQTF0Dg6RlvBzBXtbm
H2ikb88ruCKO63iWT7AVmsMnKOrci+xWQRSWeP1D8SDMYt1qqE02uWRph/q25FzPBRYnOuRRKI0v
q/RiZS/a0pjwEsuvk8zRjsBjrsC7+fCUum+Z3HoWdkG2sZQZvVRRyL9bfZHCyshlC5JkQywDNvQo
0isgRrzDz4fxmsbUCnxnMzUeMRp4S8a6iHAHzObyHNJ1WCNyb0ZRkkcB5y/XEkUwWy3VzjY9N9BM
zDFJIBHPonAAzyEFVsXdXr/0/3y41U0ldRiqLt6uH/bFpmQiHfTnFp6wi8gRvlWiZS1teeaeAoix
tfx6z+bZRHTgwW90us0cT0tf9bEUAl2mKvp8PeAt84GMINO70JWR4mqwFYgkL+fhvIi1oS/Qhro+
33V2hfXzvBeL9fuVRPelXCWbJ54hxlhz9h1QObfZowPvBeDrtyus5SReORLGhujZShwL5AmroIXz
RP712+lpOWYsUYjEaAjKj2EGuTSP491/rWw0bGE+it4Dob+hAecOMahsT8fKgI8SefLDWG9z2Rcc
5uiPn9K77QZpnnhNiEbm2+8xHMxw8wmPNWBCZ0DO4MqBDYRDawIwsOS2ftiZL/9A5IDQ8ydJT8vo
XeYAqC8MNp395vG1UBOxp8Lj3ou4QzUrFGie3KfdNS/qDGck/v00YDAekIMasg3vohRcX0lVGfbN
vF6wp4/haNQpNdGLa60EzMdD0E91GpXK2jfD9xuAykU2feWGbCVDzMOzqiGeM0Z9Swbz8nReO7BB
YvV3xjAifULrLFXoIRdgdUi8bt057pd02iVe6NcW3A6XB+JxJxDRKwAXTnmaptAPcKwR02JidWbc
0CgTz/KrCKrJTkojxQSGm1EK0P45km5PNEPuIhKrNmk791uiegkr/Es5wu8eeuik4rf/Dz8idG59
cumoJdMdEWFUezZQoyBopt7UqdxDVCD5lNzdJ72J+RL8ERdvn0BO59e4ESLI/0gK+h8ivzm+8XeW
gUSJ5nvl+ikmd2PUqyrubIlLMpWVKA/2CXjuwxJYhRY7FaAXu9nAQTngboD0Vefz5jWeDehq/6GO
RaoRvw6o43XGGrM1fgt2rVR8ba1pW6HOHdC7eujAC9c5RUY0BC7AaJyed7taZv6+LwVm0m+2ItU1
uhwwWVWyC0OoRtZbD20COWf3T9qRGY68BzubSsjP76wAJ0NRLGxVc0TFUglWLWUutA6Kfe0ssblG
tIFHtJ4aVXH14EfNcTv3h+26WAMnpL0lojZhkItYCUi/VXgpqUJqsgtfYQIKBU0UJPQRfhZLAjPy
Gu46lVQiaAdkF0CFI8p6lJdnJK+3l5z5YPR1nU4HK6V2WLyvaipTSjXJO0uTORdSazzuL77Erbua
HYjcbYx1AfSJt3u0DlF2MDqQMR9ZPh8cpmzYccb1xGPEim5BN335uByPC5QIgC1mXQyn0IuBdjbf
jYclnearsLWWTxfaDJD4la3HIUSyZj7zou0fosDW84KTB7ESGizRha9Z7GTZfdyP9Gs3meyG1Ebi
cFM5AdKfl4MOOKw1sk+EWr6/t+R/bI7i4Hfnj438VJu5FijxIYxBAbPbvBy+zQOFOBP5/4RF7NuV
1g9g+YYC2bPOFG0eULEOyxf94+9HipsuoBGOzXq1EWEPBYpsZ1XpxzqfBlN+2n6lEbLUdXsddzgB
JSio3CniD6iXVr2cNEOux6iKvHzcRwc/0N9qlVuopWlxj4SBsDvObgiZUjG6maZl7rS6xoQAezV7
nW7+J/kH/bmj4lG0RMaQh3x8eZUBdLyHZE/MPNVUtFjeFzalxqJntDgX5d24m0CwVVGfjAt7RNcg
xfskCg2N4l9kVRkFSXVxvjt6tm4AQEE4/7IETjlfOqaYK5TBWHZHVuuYGxzVgzxWHIUFp+R8ZrD6
KdjRlJ7sHIxl8r65wSk8Q9JjHJtnabSMvJhnS41M71pMYiEzGC/ZSWwgnmagy67cbSIGqoYFgsae
E+nn99JRml8XR+eUOfYoeZiaoQQvFYLJuappg2Qwfvz7vxokDS8rO2MSYJCP34ZfNmS6x+oVc03A
RM9vkl/ugEUQNyYjKKHHWvP18cmGFMwqnNJJ/tFd3cpOAx/+H1C7sTLrXNQ5usTIXfR3x4JNsGK1
GCgWjIqaEQhS9gpd412567RuzXJBUWiPXaSVm6ijz0moT+E3/3sncUhhd+4phh55qSXC3GYn3An4
iuJuqrb8cVzcsAT0owjEDj2Az+dff3LEeCh8D+kLWQryeX1gU+QE/t3GQYcNiwMcUWZdzT6NnsdQ
FG1cI1wBVnrTvyoAAc60C8SQr0ZX6lDHCcHrMytq317508/CP8UAQhnkoakMmYdEYJ4LUNhiHBew
z5v78mgWw7Jn2X/X9E8pjvJFhQKBZPae5U19nak0zlYSu7LleIBkFjkZo+C16wyuGNZqJiEz/Brt
EpaN5efysHjKGkxWWzOh701jgu9DgJEcS2fMmQ+CgklzTM/fn/HPY1vOXF/OZSpfLQp9XSu6kktR
TT9Q4nr/YTfRHLGYHtv8G1VytTV3e8KsO2vqdh5NQpV7t2ow60MvygzlqYmn1wqYNlOl1ELYvERM
RllINdh8Qjfya2ltNgwcxBK6br1qA47pLr6+D4lj7zY/KlYBvuZ3r5IB6N2Px6OmFocl+PocRU5F
H6GYshZ88PepWx0tUHBSTFzrhmSCBCtakN3CXVhi9FHtiYBM3sYWVPj079flyIgyXnDjrkBaI0nz
5QoRte+Hzd8JsK23iu4PM3A1jURFi8pEC2erEdXdOEvJDR5jeBzWK6CNW59vXCNJHHgUi+4xEzNv
6EBibAebbT4qpC5BgvruInMkVslyxKjfad0TtALWGB7x3QTLv0vU8GTi34M6zQYfV3AtNMxF5Qj1
fEqRUE61BxCFBpBh2bYIrv3THlUwwnmKhwui9ZqjIeCWdm7+UnUxAfFDqrgDDbyWdIvq53g/NYJT
E6b9+nd2OeKmyIsPJlheKiAagQSvjXhuDwB7Y3PPag57gJbDdqwR1E29YGFiFQzywzb22UOp0YX2
M3r1ZJ0bRxro2LzZM6AGU3P1J3BPVHRcfnWG194+TknxmpjxkVXXLAEvnfQ7LbVl1eqTvhGfNNMg
aDjR+DqR7KKY4z5kCbDaKOiJsao9jE0HXWwGSLwoTttuvrZLRZ0oQ+ModsdZpp7tYby+wkpun0vj
I53DyShy0YKh1SeKJhEyMaHYDdMFBTvEeVxOsLwxbw7JBMmca0iMZPaIqUPYWdpfDf/ZtbfIGxat
ruFEDoZkeHkG9UtP9r9MN8+oJoXQDmgFBADj26Xae0TwtyIm5DiMpBHJAtnWo5wV0ABKV1ogCTdu
9TMYIT8TLCFVXJaHLJ5hbrMuBVH6rxj1esp2zQ/NqY2u57fikba85BBMqBcsEXNVrWfJXCF62syp
qgp/98ZEr1y6FKiB3nbX8kojqRl738ubpD9T1LUx3q5jUp+iUhsqUFo1FCcvpCTAh1Ji9J0xwpOJ
ZOkYFo7VGW1m7u4cHaU3FcQPJrKOqc+GFnSOMIAT7VZbCza6DQH0GnWvd45W4yYQXNwiP5mCivlh
e0I0gzFDxWPOCN2P8SIISd5/xiznPK1KBicTDfyK3tB3JR+RfjFForYmh1Ct4JDR9jG/iq2Yazqz
wuEo8ooDj6bDJcuhZj2WrwKvk6UAR5LQUg6i+8jMul+nmgJEHqsIiZ0i7AHq+Jzpw7ESVku1Qp3m
6uccBHnizm5PCuDWHtBRn+SfqS72yVHffvNWyx3e1P2onrqBl2X26LUG1Q6giapvtMB6+dzPg1oT
pFpFFDMUGhlxa0Y0pcg4swv2130WfgnFGbMLsXFi8HhwkCP2UKrE+lbML0l1R/zLPILrHNHmBwpp
nKTLE6oB0SnP0DS6y5/dENsbCpPzb9Lw25lbRi8QTwwAmxGB0C02F6NbAH6I6L7uBDNINDXy7xZX
W5BX4uk60mcmDqImwS2iMySF1r6+ia5kc83C+/3MhHYgVXZEzybCQYrH/YGcK4Do2S9Fh5zWesmw
QEc9aUco9YL2a0ui6WY5bsw5+x+SCNuQfkQ24yOcB/o/j9an0yjYFOivI7id59xcMf1tJyn0/i4r
MOg/KdpIcIAsiJ5X/u0nrH/omImxt2n0+zPqbAlNu0TVO3YdCMWFknya4blmYM5qv/N6+0DRjhHA
jj1YEMT/swzbsaZG45P8hL8VhjsQisZCd0YY59rbdAb2gPdO6Z/Rxek72eVbwklp/MPdsinpfKKK
E6GICJLfZCJQ1Pto8PRkS/Yt4HhirLTs2b0WeYXUAUfcuj8IA3HmEZaO7JBZ1I8BJcHJxjj0nsPo
iEhoaUhRbsMq0Ez8geuPSzu6m7Z+nLdERYKwrLnQcprgPhzqfkzBBHtFQYvet2XyeXHnNHgGyreC
7edMkMb9mUkWUwKZC1DwuWSyTwCYgY6YOmK5SFOJG73LvK2YJXHSlLgCyBPtu361hwYlPQQW1Ly5
vAchzcoaXF8hYwS1lNez89U6ReiHFs9Lr6U48F8oVfwqNk3EAj12fYxY4XGEDRcGpG17y883qpLX
HFnUqTweoo4oD/fVN2+a5/fxujls1+Clfoya5rcvHU7inIYYE/t8PLW8VvvYBV1zbkqpNadSIyXn
Z1Spbfmfw53V+LREMWR0buOIqTzkaif9QE7MT9O/D4kvph/e9cSdh90zD5zUbojhMA1LzT+wDZ1R
LwG+hIww3x8RYMKg9Ld2geAo0dlsr/WC/mxGtUVDwD7ytpShSksdyouMSQS8AlFTdwUHZITwmNf0
9+hdJiiVN3mtVWqVFgc311yBhvJ+GvnvBC3c6shy/xRpytN/o/4mRTMWYcGERkm4y9i2zO7btHMU
iAo4sktZOw8LZxGI5HdRT43teaEYEZGMvjqFT6/nza4IxLUErYrEd8+PeLsW6P4HTVj4K3ETFscO
x5ZPxRM0R4YrCzKClRR9IIiRLH225n2/Kv74HHA6k2DPQCxlvgPiAGLYqvaUHBvnjmroQ2f3d7xQ
+r2LKymw3mzs/QrzXLfg3FdCwL6oubkZAXcbmvB7UgbNuDLGMSkpdsBOsndDrsI865T3h9uPCyrq
4Bzxat2qEcLfO3q+UvekgQMklCH1ZdxkzDJEAVs4MZXFPhIqdkoDawGqsGPtdR/cFQKRfvT40G5k
2QKziQdXQLB/Fx5cF2QXnLYznYNpwWOU63w8Sv5Iyk1FecTYFZz3AK7ktk0y1iI+J6V1yflfVPMu
tbQgSzvVevmj98P+Mz/b9h+qMwm0uLn6CletMOIOyIZrnd7D6x+nB4t6zfuXcaAM/wi2E5PVgltn
mh68t+KUJ8wN7ekFiUcC2bg44HOApUotuFDT5BFTeXVIq+OlKWkfiY+Y54WmYKTB2dQkY2lgMiAC
8bz53pcqKr1hp/yn/JIUWpHrjclb+rSYF2Imb9yww8spHtm+G1i/kr4Hh9AfZuJcRekHKlX8jE+5
gmAvWXMZ23PCe6p9dKg4llBUXCmBa1hsxOASZloU3FlG6YRaI5QhPtAnyLwc33nxgRFDWGkJBmRg
bZGwjZ/0XEeA1yQD4A1YJpFS0ibgGyoBMyJSd3beiO7zHA+lD44XhNW9L3AEi+tdxtowY3YP0Njt
EOsZ86ORGpUjhkKR0SlfNyKPMMhg4yb11WLgGqvD6HbA0oisi/TAJRrlQEga2J4tAcoHoJ8yvh/6
iv/jKzKR4fL3S6Bc1so8j1CnX2isH1gK91f9GMPT0DWFEwP+Dspvzagk3zSGLrMe60hnUqOsb7Sz
BgsEM83PFKZAOe7uixZf7fWDtcyr3sCK/zDfeoxP7ubYWeDdxCm7LxYXYqNy/sbn+ElZtkPKu9dX
+DNCcg8qLKYA6fUI3SbW4qMwrKdI1xZrpPaGavJPVhdrvwHB99oEeOZ2LypMl2XgmQfG/q88hHph
2AQKNaJ8eBrpcyqDWVZxDDbPPzZ3KlqJxEAnT1Wq0fbLmVHoXUyjwcXTeRrfwKuARMVAeTlczzts
IsSAesudRMAniQ4y5okm2aspw8rmdXScusbrgpH/a8Y/MVF7eq+C/Ae66jCYoSy83qdmUkpv9rN8
1Q4D2bzkSfw1MLKClTAd8PnNG8cv57yYnTtgyN2GEuxU4iLRt3/P4ypwpjv7VelETkcTQGC0eqdY
Jr+/NWvqIfuplGMGzI5goRoz6QhkXL7su3KzEB8G6Vvc5KSufQgxiZGvlDiUZ6IRzpBXwax87r7c
PaEVwvY7iQMyfOcOMKjQtJBnt2vqMUFkJSmxBex6k7nrxW2n5+dq4UXTOSdV6FfKGBaZq0c2DdIw
CXRBjvfQi8CikiUdvH+Urn8/McvWMJZc+TfiQ/7MAmAwrXQWvtrPFWL8ONS5sZ6PVkBToVcPFohY
MQZzbCNb0nB1f4OSxDZoITmWeYhfjZrm7rq7OgRGUV+gMC/ZFSr6wSMy+h2I1iOP4nl4ssfIRSYC
UWxRNXzorjafGDET9D3TcMr06eD2Pb64SZB9Zf8ramQXhifnYcLDe8jHXZE+DPQmcr/ujFXEveju
tw08lUrT7bCbC/YOfFVPHC/SLrQhAvSJGGIeAZGPlukAlgsWft1Hhxfkz48WnpTUk4JxebRneT0G
CKjQnpGo6rOyo3UcylXTSV8lR+ZYfUODz6FDfVw4gC507js12bb9d+sHrQMx3txEmIGYVoOO+710
SRhIglvWv/pv5b2wB8qqc6os4zfJL8CH3VB0tIVLJ10ausfUbvMTjh126R4b/LCzfPsrv1AorvVM
jXO7qkGFsv74NLGmsn+cTabMmy4NgxJnIB0EJsQGQg7BG3JuffORCfJC/vnW10q4+SHbyXMW76pj
AlkHlQmKJTyiQbKBdxLFH789stEksso9WdUk8xf0GF0pfVGTpTrL+x6E+Y9yGX33lhamotOdFqp3
BxftWKkq2TwXc4gZsyKa29aPQxdsBCueGrbVzTLdET8suio0CNf78OwdoRBj2FiB+32/bRJoO4aM
ICDB9e92hDTiLffW/hmnK8h/rpV8gcmztIwPyZCz/9lu1xT0zB03AqXO8OGUU1OkkgdEqZ81kPnV
wL/lzXxZbAk5rVkUDsm7mdXLPeNoVagvN9y8bgSzONrzyvb1jmfghm8O+6FcptYyhV44Xmlc5xkg
sNKYBI64m9CCrrXRzTSDTRNFmjH34TWaLTXcFffwGnAJ7wZuXvCadMJIA7oiy5I9iHPAoOHEeJkj
CpDNcDB2UXPIbphpQAoJGiuwFHxfycGez7aGc8FBATKWJhxBgYpi8wBx9Q7WhTRZNKIkr4KC4SqT
enMVG1Iz/ap/wQg2FalVXXUKvhF5iifEIW7DEjgLYZnopMJoE0onsCj4Nr4T/XlhcZJWzgTHoIGh
thWKV/EZjUOvhonfQP3woSYxXB18k44jbQSd2gBWPaa4xXFqZ09751UBn0Z981E/4nEny3ebYk7g
W7q7tUUgeUyKOX3okwkNfHRzPFcYwDHlSQx5OvXwN4M/VuYlOofXFC2ujdubzA5J4E3qvaaVbiG1
vjyKErCb5UNhlS6cbtYtrBdyIgGfL74Vi9E57sPfL2qFlUQnaC97/dVAn2jtnohSrZcXVTrda7UJ
oDmD7jWvWoAguFJ5NRcLpqkL4WeTDKN6RJ4u2WfMDfM2UmGlVk8VrmzMQkmD9KLrxlLmRQ3ZXsi5
t80R9NnFL+AZoxpjwjbJFFhA2SH9YL6dnFseZMMZE1z+2Bi/Qk4KSfoVZzy/ymbCbgY0Ch+I+mds
vmgBaEbZaBOLK6VDmcw1aiSue8BNCesyouNnmbvOnV9y7+Rrn+CEgB729RgSfK0C+9+rEsXVFZtG
lOhA8hQfMJRsEhm+qdaoLiDaEzqYUnn3F2W/gXTZSEE6HRigsFWjYYPo/sqf6wGSicuXFzSRXxO7
e2aGofURKm8szwedq2tXmbc/BPBEdp/xmrDyXIiE0msz8fw5nxvmkor4MaJiBIKXRbwfzXdX4FNV
k882/eWekL/Nf4D3+Bw3X1OnL4gI63UMMvcgbcHuT8ZZDyz77fsLbY/gJhityHbIYF2Quiuk3qC5
xdHJNiLOjWrUMvia7VTFvro3waGqRNvOhk9T6t9MWI+W+jBE8sWcfka+SyzOQWNnY4zF6EGbmclw
Wmt+FznMVuQIbWQQM+ZpvDIpbAfZKkrH6n//45JWR9OMQ/K1hSMKwsoJiOQ7u7JnbMWQyLtRBYqD
ThMBed8k+zS44qK4fOuW9649CtlgmIiQ3UGitD60GGSsGOUlMsJclOx6mxjKI/QNHL63e7TgMWRM
5j2xt8UtaTTMuZITa02W5SDvtSi5SbtgD4hvf9181gYtyQxkb5J9MIRsjVZBRDbaMXjEv7cKa//o
5CgR3FN45CzCVqDGIxo8qXRP+kjC+WNnBCArgC0KZIm9ldnygf2IhlO92Rsll6cXwi/3hzSvhEdb
QmGip0gk9ue45s8tRK9Bdy+QwGbeXWJ28QY4R9CL7/GWlTXfjsT2qjz0RyCa2xk/rbEDtNH28NSU
nrOZfvBYAgqOUpkGrqgX9/gSLLW87ZhCYaAbLD2QmB95b6xbbwWk3U00cEC6ix3s5012SoQE9O5n
jzs2AChDVfS5bwMhYNNsNhSHPIn2wZDYDW313ZD+6AaOus/nI+6wZ1hm6/L1ywGcDXVqvvGNgftg
iW3ibnhIAPIfc4baxCXkRhDGC5wjJc23BFpv8e5cAfIYIQMZRb5No4+nR7/tb8Quk9SZ0cXfqpLI
p/aNhuJZRQRcudDfgfcJ0Pd/OnTNQhwnbsmjO98fLTLHtAsAinWAHZkx4tz5+Y4CqKK14M0F5DPl
+73fx77PaQOcQO4UAFXIWAJ3Uc3IcdMBzpj8LEHbg9fKI9g+7g9nU8qkHV5I2RoBi0Q1NaylmJnp
574A4eK+IEnZNzfkFZMJPKLqVqZHbAJU2CsYCdHZEBl1ny8zBaMV30n5Jl/cBYXfgx2AtOLLBb0v
MZFFqwyCNQX6IgdCXXArau27GmH3ovlzzWPdnJhrEWcL5WEmJSrXP4v7/p0c6bqbvQXGxJ4C8WJi
E+H/Xm9/hN0b6Z9NZc/lafDtI8Y6Tx2TN4cKkB6WoQ1gyayFK7kQD/1Lak+zMiOaFCojOZ4QIBAB
TEXnF2Gf21AByBau3SkWtno94Lli5+IUivKVdTxcw7hqjvJ2EEiBcxZfOo3Sbuy2EsSL5cm+hkry
sEEV6NdNgMos4r2fvxud8rPItzrndcpg2xP8KDj02A6/zGbvTXRg+TNbQGtNzt39qDHd1j5H8KS0
EDzGIC2uOvV6YtxfU0UDC4X4/eAJCzUx3Iyk2Y79k26Rytc+dLlUsDWlw9OBgzehH9U6gGILJSpx
57O3+akhbzz9toCSEMszjcsTVwdUgsjclWe74IYPY+LLv7sksC7t48ge5FrnmVneGHQFPDxOlcK7
+vQpJaSGscRZHNjlfyA5Jg/e7r1yHq5cRzpw9LbOZxYQw7MEfxVYbcspZZnOhZArSrfMquYOgfUt
/SPK3wuOFGvGcY4omcjjxk7bsQ6Qa6Qed4MjhhFO4jXXPpm8cFNso4pBj5OIvsH/MVKCx3W975UE
qvwBcgZ/xbBiNyV/ffxv7gg081P0RlLLK1vyoDKKeP4RgNuBzzmCZOdYs4YZZUYjjmeWBNNEKJS9
JP+aA/qXyQJN58aIvHevNJkAOxjnbUCUW150QXKC+pQaPlNNN6pGwM4wN5rabPiYFly/J6rb2fGO
yo0qRh6iVASDt3ralhrMvyf6Qd0H4/G9IXFw9e3Ot1TiHz/cSmtcCoyNsTl6fAYRLuN3eqyZPuQx
W2R9dvjeajmqq0S5OChYJJBxMgA7bgRBMz66itFOzJyMhxwNyvJq9JVMlCUj3iw2HzNNCv9vJE78
U4RYPDG9mYyoH70a+s+foQlMJbJZSYvjQftpDXrFJhjh8oo2F0HZz+sgcgURCmmM0dtzIxMOoDDz
3LUNcF6akIJSURCI5mvOHGLQEASbyArknvtJRHye/6HM3/dy/+MUDnx4jDNcrJ9EBVM3Nnd8qxc2
u/MjoaBv0TWHFpGnTTR/1f4kEOfsXLzCaESNnZpbFCky/+Tmr1MQNFB9A1D5dDtu1yL3jj+Q97Fx
ifCFaa6YE/T5j6l2jTx0jwd2kKWL5h50cqOixWtqjn4jRk9NjHzlmu2UoMceNJuKmRhrG03IFOel
TU9XCMHcTpg4NgsnGedHYhAxAnVqlt6rWxesF9S+o6MSInjX5w2jd9FlpL4uuY0xfXSyhTIM/Snp
Xu+S0qZtC6OBfn0gU33Gq5dqVCoyil2W7EZzB5PiEh6WdHFKWFt1QfbeJqf4tEw5G+VntCd7N0zh
u6OBEXof0IIsTSX1tXPm9cN0WkPH+tho18xpS8JfnwXnOHGpn28JsLrVua87sbJDTicaUovNtTU2
czd3iv8RpDjUvwqzkEBhEGK+pbbZ+E5RjITvvyptojL1YEWcRo+J+n4/BN4KOyM8i24RRXachAPM
38GbhOOd4arR1hu3lpta1o/c35MRJHn+xkTXLjD9+ZPlLXhxqcL+9rDZ7iT+FvJTIVX3bel76nHo
EJWPoiVK2unHlUGyjp4Un+SkGgK/fbSI56tg/wAybBA70me83qFvMl3xSwOAZQE0YDP0jAwXOrXo
R7FfFUv6fAUggMqrFPhwdQRbHFcWCpcw4fJZRKj064WcAdHawRitxKylpBNdWT8DszcY1gRETg3F
U3v7CQwbXLvjNmQ+yXIYR4QiMjSowB7cIQ8xgu9/Hq5sN9uIEpOwj2Y36D3bbaD1brAESGZzTdtj
CXNQo9D+Gag7MmmFdaUHO2fm1XK/I7WYYxG+LI0buhSuO72C3tb0E/cDBxd43Gsg05swslwQDWRM
uhZrer1VZ7f0Xo9R57RKUl045fFrHb0sIfcqBteKsanc7k6qS6irU4mWg+hIKC51s7iZHcYg3G0t
s0ZSHJ/efuKqYbeUGp2O2NJwkqZoO4vSCN/SbMTdUaIfMlBdzPELcbh2DPO8q10UoPjltWPzI1Q8
yvC8LPMA8xXqsr4J+IG2sqTDScfgUpxGwUMRLGOTFPcQVjMPSDzcfFMLcNl3La8odxZtC8NTVz6Z
a88h3nyVeLMdp/CVBZRDjUYoEtgIpXJlOVe3YbMt5/QdQ7R525AREZ5xB4767gpEs1ste/gtQzin
c+yP7/TRPeH7p8mlk6qxJFpwUYs920TMy+hj8xap7edq2+VRmErI/5C0Z4veY8i584R/4slpjs8f
R4sH2Irtg6R9UZqu5Ju1seV7jlEzAmxAE5WSO8X2Sovt8GRWxinep8dgYV6DnZbahItwU7psyeqK
YHuW/nKgvULW4pSiwEkt3vNVejL1PTVjIem3AHDm94F4AebzWU9sWnx7eEL3rKT0ZNrMMoxgn63b
OyzzowIWpL1TaXXN9tKIwi0+4+xBlLoolkMbNSmg0Pk8CshKpYed/8Czn5+HS3ROqs7KHWjBCnos
/R1ITEuAV5IIVBkf/Qfw95DALjatxuwmBnikjNzLXD8SnaGVx9ESMy5pOvsgm5eANVWfUgfs65iE
o+Mw0VlbPafIr0PW7KpnY11LPwK6bLPM0NRiS+Ykn/OJYTxCaf15jjJCSqBEx71Leg2lm3kyxHOm
tldye3orihWzKmeLmIXQ9HqEqewTyGbSr5qoL9zdtd9Is2hIMBafkcuTRwxq1U1OPNo9e/nDPG1j
A5ySSO88LBcOMlKpbNXaMeNCuEItTcmhpim7to5VN9zr/qhpGi0SBU+cQrYld//9u6bgxT1XUvm7
OPsAtgX8PdGPeJtmYhzagQAcSsXV85D5K4uClE0LZ54mdtBhX8YjtAVaIXcZPskyxVevOVEL1WLe
ihzg+LzTyMCkZ/D7sLN1v9kgB5ipjXN2A2JnxL07/GM1Uedgs/F2sf/arMv3rV1dIM/lCQIy6DDy
grXEncjKlm2NPvf6pPMP7LPdWr1NbW53ok3Z+LqgHs3rsws7ZVewdvpR8jLDRoHoqeqZK1Gw/up4
1idS8zEnwX6TIqxql2GNf7XcUM6jNsKNyH3jLzz1Omv7ZBagYDozUVMab58tAL40ixVgjjPtw02D
B2dT+QpJPasUBDBQyLmnyedlSwer14s12b8n3rwu+PWlvt+Y8718bNqLNm4TvH8GfWVtUu/17gCI
lUyUIRJZQW/JRXoqrrWHeZRxbrxXoP7tbRjOl0Uj78qvkGQvYtr9tM8272NEUKe6ed0dubGQBT1t
nrdFeGw/BptTSBXH+Ka2ZbPnYMYsciTreRE/BkapsujMIbtg8QNFd/IdF8fetmV4lW0ZZN/mj69N
ijDOvB6kngd3pM6kVV4Cq5tpmfDsJHxdNTT3mlWSJ/TZa+51TGjNmuXUZCfmbdQE4H0Qs7NV//Xs
rm4fHyHDp+FuPCGWZBegp2G/yWM7lvycd/bRqy9UufCOVHTrCZeWalnjaX2DUa0bforK31Tj7bz8
eg9l3L/DkThaAGys1nYm+OZolRJW/rCkxSmGG98/kBzqXXzFPlS6M7ewe5KGV1Cvq1h7zvUAuSIK
P/ADfmxcUyHCZvy/BkfBE8ZbwzyZAfj3RnEzC4RgKwjF0H6x3So9pBpBPPZfpTtsxDlz94+LlL4x
Lpzc833G0E3DUVKb0XTj/nfiZ/s8Eg8PCyBMOiKYQX47z1GlJnB637qmLb4mBdHjsWNHM1Ei3dJp
LijW9SWo5TKgj0ne6kesWEHnrKgs2NDFdnn3j+lQcXTCnrslnZhHfQ9tyJMgmG/7EBtwzN80ou7j
IyExjTWqyhCNhLfceKXOc4qqfa4LQXFd/ed4EA8W9HLBeJafQ5ZUSVr1eD//ihl3Fplpx6nWEOs8
UXXL2VKUWBsD9sb1razFmmMfup9V8pYbCciVvlhs3s75L7u0EZ7HhlPi3hitfnhkrT7q5hcKnhAA
na0sYQsJ9C3KmPODG7QHjpbnrfFacbj/7F/Q0NSVTUV5FVNHd2xKrgbUyEIp+p3PTogXE8pFpYQ2
sFgaQkrQzZ6B6WXVKLfEHo2uky7SVjFwlVriW57UfHCeWadAoctroMk+EsYqK/PcI1VdubhiuBUG
62vA3i6Mkpmg8mhqd4sosIhOVsLPDmJhSWFM7ziwDM9lFAVkldSMLCuazhDUAS6Elc1u7Jbs6e5e
MIMnRPPukuwG6uOcmkf3bWtu+MOPzL7McJFc1dayip3+2EHyh5NCPiwUmnZOTh6x9t0t8LOj8Wv5
NspOAl1rfyRMMum8NCqsrKyMC0qhS9Xpg8Jasnfmu3MT7dgtWJwZTtYKQQTjz3xaaerYgVcbmZki
k80v+ijC7oS4QHOS8V8cC4trpbu8W3JHoKQekdUFC7hfVNwazb335NmTreWrh37GAP4o5wLNi4u0
jFLHOatBcvvlyLPZTWXYFuAFiNHxKnlKBaXSmdonB8OqNM8bHpygI2AQhpdw0qs4PRrJ42siFEJx
f8RjIKqMeD8VmzEdzxFrjXXg2p8WTyK/M+1lysKUaJ5eRZdVeQYgoBD9z/QzFptEceGvpZ4bIjQT
QdVTBENmjAwgj0thB9db+qk5NU6kYLlMLSjN7590QtXtZOA0/MAo8oyb06GimNrIIKOh06cA3IwY
wK/ev2QNIIpS/Nclr9oeiVkg8hXEh7nMRATyiDvBHjl4V8jIuNJuhyzJeL2iQ195YXvK2/aOz3EL
FiuDxaUu5FerYRGXtK2myS2MMVuoIrca//3pUAHieSsmzbbCNx0RH2M11xvA5WogCkXZsi5IENcO
Sc7iNI7Mv/3rUxbeTzVz9ezcV8QnnrcrmFPpxjFHmd5ppUqbOJsS5LE841MoWlKSksfER5zl9qOD
TWY8e0t5TLH+5brLVL9qSPsSdAebPthRtCvYintydpgfYSKHQI4QXq+d/ykP1y77+WRBVoq+IMzB
dqjUwQaXrFkJiUCsHhrfePJja8qQmohy6ZlBgeD/WtlOMuko9tmlGcRGlcQuyvVoE7zs0csTyyTY
PkB2E7LJyfKD2Y2MdIE8iBlCJD8SOdgU5TQ4QN5LfRh85rqcCtwlpvWlY69sH5JT7tDi+sq7hU1C
NaVq1nuwQL68tkYzMTo2T6jj5qFsPOEOWf4A6F/V2YLUgDmEU0RjYZUs7IxLMK3PfIa7A/UFCfRs
uw0HPuqLycoZJsQ9JMRy0N6wgzBkJbSHEnnGf05cQTzcX8Pj0fph3ZLUkFjs1tGZqWzEcqQSimdt
2pL5qOm99ORa6pxEz5khHni3I/2Sud9JQpTA941fIkyojazIdGBSQYlIRKTejGE9WB0gfhRUWBGH
tCjQ50yR5Z5J8wP15huY/p7cm7y4BO7xLd7Sa5tBthGRIey2Z6utIF57Sod4+LfUUuAgD3pc10g6
5cajK1Iq6hL7Dc5+//I6u2IONNgRhSwFGBRwTTDX9dJsz2107gBU9GYJb/+dXu2J7AbeJc9/Danv
FSylYHMkP2zTgO+YILYSuB9FzzbzXQCzQ+zOEqdNdOycie/AnrIqgVZikcuWTgJAwP4uIeK24m8S
dADN9l3jkZQr3qzv/YOXDtFBbENXPHp+q3f0ws82oqGWh1+fXFEdxcQ0SB+psLlTVqsuKgjwvKdt
PIWr8m5QtB+mcinv/Jfz8z0Zk6l/H9GGlMgFgcnlCh3FZYRIm9cSAu/BmyIrlIzGT0GMhz1FI2RO
Fg6WeiKJUlJcucYJ6dfIv8Nrddpg5GAGkro2QK0JIXbYQVAt+tWFx8f6oED4kK2lM8PafdILkW3L
UulAFQU2PCIz6QnZPVQXKRpwWrTOGvmvOelA8clNqcjk+2pLZ6eaL1ry54ZpW/4lnLTtQ27iPr8S
lnN/Vxc2opxRJkUsJHQZPopQia44JqQWtGnk4kGGAJijg3//nvHd6fMUMXx+S3StcwKrTPe/XfIT
M5RhLgeEYALgX4Ws7f3YeKj06FgLiXDzz2Bxx8NTfC57AkobTFWLeqlewmR3AR3taOlmF3ceb758
HIlr6PZ2t1u/livukrBzrgBs8jQ8NHlPdTciN+PIKPUoQpANuRkxxIfy+VOXF8SgHAW78D4UX7Y2
9/cPJsnl4DP/FjufFu2pG4bGI1jDKtOwrSYKcDANRB50IL0g30PbKsNAAk9VeZpuFRB4bgrn4Ef/
vNCnltI+8iGJdTnWZVwrQmWp32CL4jCVnli5j9Ixa65dXspm2rCfIGpcT8iZ9PQVKXEHmN+gUL5t
VTjk5DWpjxtR4AQRMNQK5Kmlumt6EPMUVWe9yfZyUIhOA89D7ur2YHAfkd9ndpvRx2nQAIwtDgug
WSIlyihyqxPpWzhw5qbUSae0/rSU/9xMYIxDzWkcYTYHeEYmou3pKHEDiSGnLBvMe8Dm+BhxKhLD
MW5TvgZgTdOuIcnnFhFIKShR0gbgMMUF/g+qlbZxNiuOhTMP8X4f+XtbVFUWrUjOi/kaenMo5W8r
9QrIiTJKTxu4zlWz7XBC+0C7iqRQubbV7N0FzEekWS6zpwL5CIfsopeCIKSq/hpZOncoiC8OIRDH
1GomrXh8DmVKIyLvrxeqtG+PdsuiPyPPigX6nQIeIq3+3SezT0kNGJOZu4k/PQmGFTUvDEhR3Ewv
I7OFj5AYbiXlETXHOXZX8zfDj4r+FyDAep2Brk2oWSb++45bmnmA99ADro5qDtNRi/Ycml7kREQN
O8lHDTeLLaH35d6gjKqsCU+tuZ9Yv74RwYYeRLgBKiub0KUclzQyThtG36USeDUCH4gt2Z9tFPnl
r/SPuztf/EYkpVwdx4qDT8O9GSvOQj/rLKNJY+ujQYUpdPkqH1216hwWj68ngoVJJzn7vUOwwVKD
j5+iK9VW2UZV9H2RU4yRqDAIhTzGRh6uxKqnh7bGj1BFemtSQgDxT/MYh6t38VLrATCK+Z0R8NN7
hRHyzI2voVTKv6LMnzKIT0o2spm2f4GYUf4JTmuI2ORTKyVrlTpKkUUFwuKpnc6Q0cb9UAeisGvl
kyMUVhjEyJjX6v14aRaJk+CqZc4L7I8FCLMOp4vbXAWUeJ17xs54go5JHUI6C0qQ1DTPKBmGbOhg
jzZaWFSwTxgb3WkSyljMsPXtPWhKY5dF0bfhFHwe5LPgq1J8j9IpdTzdHQCEBdACGbnUTRYfcPEG
rZE3cQjT6sGJV+5+w6fO4YL0/nU0T9qJMWwKZgoGGuiA1TYUdDi8nEM92FuGll95lNK6CG590Ywb
iqooMIN+NBhO3z9Hgog15ZzFR0c6Ut275iESBhTJen+1T0H4zFvRB6M3DKACAjBn/r/pVBDmWKZN
EIf/Ynb1A2H+EyuUfzB06EmmX7uV7PgvTIWJUZUARWktjx0aLNuelB52DUv23hatvCntD9rqHnth
UwYND18rgpyFO0Jf64DTwL+jNmvkuTs0oZm8iRouScYUgOlFEV1uDvW5TS9SlLdiTJcUgXYXX7Ne
ZNIL2q7f8sEh/JIZcgFGyvc3esjokmtV4WRTp5R9BI1saC1CBvUh8lRa4jiIb4bnttWQJSm6+NfS
9so2s8VzLqr8lmImftYN2V8lJMwaFTlr793+rJVDL30ZfclF+Zam4mf/pG4jPXL+9lZtAV67pED1
U0XZ/MNKsM0dYCNiqy4jb+Mn76/Qh703MG+f9hlOlZH17vjkc0Pa3b/jXRmNU8L0g7Y+aDXTfiZE
XVB1IXLa8ZE/ok3ZCAQwXrptbfDKhq2YfU2Fp7WOpf7Tl38M8+fHCUazTK4W3GpXy+imAhsDlpxK
2wqSNgjEHRW+7EPZ+stbfUTAvXSfIIj8n9SwMzxaI0SLcOUmZ7XQ9Q8RRPbgTSVA9WOU/SpqBQ3/
8JPJ9UO7yzoYLY7HYqkFiSHVgWCjDl1bHBe9+nzq9HOUPruPkpM9WwTfrJNBIm8BSRrn5qFXkFCs
NqtY2HMtt5St8pHz282H8ZItkDopv1Be9GtkVZVYAnoa5n5wUdz90M+d5bWarxAhVNbr1/vHFkoT
boKrUQ776+s+fdGUwhR88YPWQAZAgrUazOXhYhsgIr62iUc7C1ab7Rg7A+cyH4h9f1uF4O+TpVD4
wEosIQgW0MWcadJhc+bhaxs4WHoET1qWHo9umJsZ+HKdMazcRg+C8D42N075xCxBop/v9EcJvaT1
p3wmJ+x1tumiyp7qHZ0swLtE7QVmzqU1DDDUUiN63Xu0WfJ1/3++DkBzmUaJ2JmloJfEqg+/IRQW
oAaBUBm9XnVuFVoWqxpXlwgow66KHSykUGC/q/Bhh9/90yhl+nKliptra321tyce/Dg18a4PfTg5
tX14SNNMGl5mKa8IBrKZNhOk2McYXAPJJ7rQJcwyTOx7oyBzXW6Rnd2KhgdoXg2GLM2gkvvp+/H3
7NGgdSY//zLfnC83RNTUnwWX9ArWp+0PXMhgk5cXCbPKgBi485r6Q0JLKA3xZ2rkTgCuYc1h40dr
XKMUZBI5+ekOmLYcOTiXGefdjrJruZiwa84GMXs8N9LBbH1ExjwHGdv15cy9ILOHg4tCo+AJ5+JM
QcJfonLAZWoUOTBigwj572FXghUeEUmsenTXPQZfIxSZ1IgOXOodS7IgoPvBU0Nn3Tn4/v78BkfS
zinx3Wfhdbw0qwhPYvNB83pY1koivltL6oM+/iCX0gqKT6y8KPMTBrNs+f9EOOL241FWznIZ3FGr
cCqIQiGjZ5lzTGjhfecOh9mqA+OacwldtaRVb6ottrqQQ6C6XX0YgAhrRuimwbcNv2T0NiWdiXFT
EbVimQYrBcl792L4dwDHUM8PEhNRafFRnhzJDrA5p5m18NqLADElI27nbRH8qgG9oeFjcIj8wuzX
Vi1yRMkOWSto7fg11hDKZYI6IUih+adAzl7P2JcgxcUYlzxspsCqDGVUmRwtjnTEju3PiLv/D9TQ
5xYt2bUxXLvC3Vw/U4aUL6W2chfhcq957meVjnb81J90TN5jEBycI/BsJY64ZerJ07o+SV5XdJ7e
VHwhfnxUJSrDSRGdIVyFcKZabpDtx1rHDruVfSoBQqsKtb8kT8Bsb6jtoOgfX4XX6ZCtPV/v/QC0
k7Af1YOKn44PSXoaQho6KTQVeJVbN+ycAlqN6WAfSk52zIQkuxM8TCSrjt1UA8AUIwV5++QnhD+T
x7/gHRYNkU7na3h8XT6I4r8h+X2o+oj+ERccCUB9F9Q/eHyy6gtJVXPErzAxgDtHRELkmVgkNqQ2
QaDVZbr5V9INTnvf3/UOvcG/Yk9jFFnxAhd76udRwMX9Odo7LVCzyyX1OIqhjp2o5vpeyfpISka9
kJ6Ib/wGdca6xffjdd5bwuMh3Cn1NvS8tZJnSXZWWFLVFah0Ll9u05r85vIp3B79V7wuXo4EkQp7
tGWfIcjM7V5ZbOZSX/bU1JrWN7GasW7UUWi3q9m1h1QIoZfHglyEO3SutzxhdMq9H+58Kn1Z7+T3
teZ+tu7q6qzBS9e+zrdCZolM+tPcLw+mS2gUM3h37TDW7AwJiXpAEWOaaBDEAZuXmPajBpFhQqMY
bElCp9LzvR/JiKocKCH+3ZvaqjkWqXLxikz0mMoSAPt4N3WO8eUN19BZuzaZhHjUevgDXHEYnvvB
1I67rbhL2Z8X9dja3NNoa3wt/qS97BKdg1sFK/Ryzk6ecsiOpRRQIRGJ2FY8LF4wJ+OxnT/Cowrh
oh5JF1jKC9n2ZCH4FqJrOmTBDpCm5yHtjWeXkWFaSj8ipCYGyJR97bHNVnbFglPTR5pglPZI2kvA
wPzjqm8un2l1pBmc3Xu3Lpz+oXjliks4bHtojKUXEcULpYX56RXmvkH7s0Fct/SwXddelXP31/nW
I3d2KDGG9wjdFYGrhbvEhxA0tTCij3no5XJ3I9R2yO8pmambeNnnBgDJQXWZMhl8QNcKdPNQK6ST
t+HNi6AjSf+FRJ2JpkXmgnscXZsXkFCRW7BDKKs0G+xxBJcLGDqxH+bfyth7fJAArv5zYwL8CYjE
b9/mXwW6ckHiP5SbANAV0x3A8JH8tWsARB4VPJL4NynXGihhy6mmZlnf/8L8MZCGQ1jm+2boQx74
Nwll6PZuUMqN5PeJARt13ZDcrn+m5lKlsfizbbGRBlJk2k1BfCk2yRnSTc4Quu22dpglBPgPZQ3s
ZaOlX6/l6b/1Bnb5DbLXPIA14VlBPjOHQM70LH01vlMPReavLXrm1tyzpM0u2ir7GNl1QCfYs99n
ucECkvjE0oIEgc4b2w9a4U9hKZWszk+DK5eiAi4I93KAAfemW1PxqjfisKXzD0wNoNy7OjTFGxjb
iDMvtbjZHrY3JglQ3NE4h2GXmDpSIP/T+me/QTKr8l2mFyS86T5gMyE2SjJmnZLY+LbYlmgfqyz2
NHVq+Jbbpvp3dpRZ1FG2307UPT5MCh3PL2PT0p2UnzRz5QaevthnxQ5idwBPgSbBybH2Oy/0TuI+
Ep5d93M93y1g7JkYMHJTG4JJsettzHelSyhWBxyiuXjWRJAbnTCNOzlGQuKilO/3gvhJfmKPVwn4
yhA8usgDea9enmMgreu7cEdiOqPGVn99RH7Hym6r9fMD+oU9A/iIpc6x2UClBqWmfn67+R+koJ5d
GINEV15waWoQU8LeY9MtCd0hqgxYmBP0XjLwsSwUvYFZEZRl96A3CTPTen7ElMzXXnFfi6uTdbjx
bL9aW61TYG0S871+4K8jbBI0wLVCEqEeIj0HoZeiHzJltCLmBPxEGIFSNsDPohSTE/RQkqIAkmyh
xx3F28BRdxeVjLt8w/7Hyl27ph1ZQyE2Ym5lu8o6CgU6tIORnb7RR0dKPd8DkJbjfQTRzkOzsuMw
REB4wn68yTxJ1zLxXcV8LJ7CImEDzwU/rCM3zwgvP7H362fz2wdJpJ29I/wXoz6HearVnAET050i
hnZlNf4DLY0jdBWZWPD6hSavp1ieW5/Y4MysWE2bI/ZSYHqM5xuGgHPVn63ZA2uQR9xj+aL5CVtF
Ul0o/Vds3rqBziSyJOGhIVnQ3r6T921FHm0gpa/Yiu7dfgN7QFiTNC2H+KMBSz0a98veNSRIPIjw
WwWhzxWvg1UAJS/TeB4VjTNbNPeoa+lpOdWU7I0tifs3XsCarYRe026cZOslpFaxqlK6512pWuqs
7vXorT1rtdklc5ZV3jybmdZWWNLBwmYL+a1EJpoKy3irT75NWqmk8DpBETCqf5XUDo0aeM0cmV3w
mNson4FnZoOwomF6PoM2d5lASoyCtzc1wpcja7QRj9uh0MGuU5KeeKGJQLi0HMp5ouYeR+OoFlck
1VS+BNE5Nbp+07tnR+nrpJtfwRIFmbxLE86BOZuI5+1tKCMKIpYD6ZAtIwieceCFL8h5RjpqO0+/
6PwOVHJ/WxwcxxXp9M8qWzopIgW3fDh7EZMd7N4B/PGpkf2RVH9S/oFqM+jLqCfXFE3Zw+ZQVpwJ
VJAqrrsKBf5lkoCyVA7Z8JFgNWdfOjcQf9YFROFkO4uotH181ZEa0q31LamWhKtvZVrX+f2i40Rm
JT3DWMb4+wBompPl5vd15oZX7OGQ68F7d0pekGkULngw3BBqSgXmurkYh5AEzxcUTNGUkn8KTbny
m9NlWjjHGVx6rjyM6eRc36OKYj46vg3mpzmfZQzine+2Q73LikRcbzlT0bKqhgKaUh6V2mOPWU9E
Tjd0GIDN/lNXtnsuMDd95IdbPkpif0hgfkR7yYXXhLQecz7FVCjK4r5wTgP1aBLNorVkHeBnaom5
AriebG/redm9pzNrWhSIqXQsQa/Tg+k4kZKSl/jnTt0/YXzQK3Cs6gTNTG3IZiWL3EI2O7JOgLVR
R19m01EU0lzprVEIZnucyHHJe9/giJaMjCYIOMp/Aj6+oN/b3jNrkO438Udh7BaqVQfZ8oY3/0Th
bYZur8+Vvv7ODGnFNh4H6mGQHK9YAnxQpDyxXnHOPfstaPtYdtY5ZyIG8LAOj3/vUMtwNgxTPNjK
OlBFYzDNy4VJKYp+7D4xMPGJyoo4pAPO4NtND7RYl5ElZjC8Vt3x9SfNtDV9QiaXQQ760y7bDB4m
pq/fn6Qhyb5Ycqn1B+aLej6fiw4Zao9jWS9EYQcqaDC9P72ozdxdeRlqiO6mux5ZTpJjriFnkMNP
2ZnHym5jIyzEXiawDZGqqY+ET8UI1ZwyshjZECOzPXIR731woeWb9VhIhv3y2XHEgF6cQhjI+IJv
kUZgxVATEQUEGiiXdKksUL/E5OZ48WMUOqLAaaufZTSolFQiIqtBX5JRRRqtekI13/ST3BOmr+X0
bKnccNMWyU+KmmBsvWlX3OUWA5yJiEUdxQnhNAl5eFylWyK+VflBhf89/CVqrDmcmwcGISn0u9uz
3cSAF/vcdIzeTHMnVIdLhtbIlE32jBpTbe7WnTlmIfvEGRljLi53BCQOkIKGCu/sg5oE8cP22wCD
LHzzoFWUo+l/ilHHyQAzEZrHSusZ4WcE3lE/rof6CxQRDS1qaFRGhyydOknJ2JRFexmWjDW2DZww
a4hp46iUh+dR7/8e4BcEidEGCU8Q48H4QxrG81Ea7Z115uCu4YUDs4FyU9FRUxdDP/QYkatTuqHv
jyzmDOarrEVp+cTw5bX8hsoi/eQsCoy/rpTjRhxyD3yqiAJ0Cf2NmcSQl/KwgaEKxCe35UEj6rIQ
ZBfr6bvRie52ftFiyegweD3BafnlzfLb3jZdj2zMt+cSJea/8BnlQEkQ5nQyDa3cTPSBxYJUKzMv
d5CzaMeXUJj2hnp50c4LN/NmTaj5yC0JLLGYChj8lhefTEuBYC5NnhCl3PdFo99nBcWXpN+pnIbp
9OuutAFvexSr3xfZppirb4IgyBa53Df28Fnfn+vw9sK/KVv43YFncSBw1/MLKjwusC7srZ4cXH+m
F/s30slDjKT4NUuP022myqEdVCPdD5HT9mYea8iKuh1EeZDNQwou/Bd0J5sJA54eABeJlxzTCixV
SOHXmk0Cs1pRhHxqSvSjkNDGnBle5zIIN+61O6+J7DeER4KsJJ75rFp1t2bUk5HqCGH8663EUw59
PTE0EOiIVn9x2yirXV7ibx5fswvNvQrvoQB85D/SXR/rMqMdOU3vWx2K7F5p5P6FLKYiauE4RQqA
xME4MjUBm5DYBPNndEB4w4RlxMe9Zgi5AB/uPyO+WMZcHeia/1vUhWLyA6+of6c0nFcXwho0b6pK
eKNY2S5qBbBXUI6aF0GhV8KkCItGt62nyqCa/MPYPD1qm0gI96WlpKFyu2iGri0mvVFf/hvi0cD6
CshdyISzCkGOWosRRQYX7FaBFNjnMhTRTPSbxDrO7Ob5l/YhNImutlGXufSryg4f7vL23hM2MmVH
Zbugwfga3Bp1R2W5KLKf56bjqBUq1Pz7d0OFnh++5lkpQ83zyRXBTPk8PUitw50g5j5NAi89CCWM
1RTsxzRV3L6kKKl7TuX5vFHv79DSs+unOqiuUowynMf0VvrRwtWu63gCT+F29H5zbGcsZeCTWQty
ruQSoHvC8g7/DtZkKoKPfm/tR+fkOOmdjhuAGtVfrCqj+TI6AqRkiJvr6FWfDPnkDtFvfPWFjPVu
IJ65znpFpwfw3MV5/1hTYhk5nCREC9oCK9esD4qa6vRsMrOpeAiyTeKcb4hj0kb2AL73lP+exNEx
F1V+ffGA+2M6hSuK3a0wmVQ0wpvQsgZlLF3UM72HPUDo5lO8zzZzIVdNSF6C2ymPJVZhgShn0rc1
8bQaSdXHc5ImpEwajqRS+rhNFyTh12E30/iH87m2YjKIno1+d9oo9C5+aq0tsLj+LFaiTEE/dezk
EvZibNN3gmRG1p78G5LidusM3mijlyLx1llDiHxERL369AHJrw6JNJ3mXR7kSeNKBeg6UuN8ITTz
Eve/cBQjYJLQp6FHXkjiIO5t87BDsT01xjR4l2i2jl7P56vw5hlpU3gGVBlb/ff2tHepUFv0jYxT
rcWFEHlhzWgHlMV3Z+uWEFAXPu7BkwO0edrFWItGZ4sAav5zAlUJWG62nLHcWtRw0m14kv9O2dRI
+MljUAF+Tk+FAd88HRlm7LNRngfhDDjiW2mP0E8k93tN7g5dlA+HQYNCc4KgoNvlWOr2Ns+uYgUE
ySGiYdvcEMrM5l8vcHzkWm0K4UZzRMBzY24h4tPh0NH4WRN6iug/TRbsqVQHchvE4rQ6e+Rh5yej
Ss/bKB+3zQjznSn6P9bjQc+c2LKaioiPSaFf7zpV9z+2so/UDobtko2LPBbMXI4xaQJU+gNXqO7u
iFroV35nWaSUrvhZef5HrogTcysSVJGBefFj1BD51aYt1BM2CQ2IE+2jHST1e4L4A4bagXAvQdfy
qIUYBHF6+dl5NYZDZgW9FY+Q/HkuPPrLVi58ShhFIPHGCoCy1pL/YLHhCe5LsF1pHzWPvjM7/DZ2
ljBEzzdW5K7Lw+rR/d9Eaax+YAPxGdf62jT1Dru/zEqI+F21yEs+9e/xU7O9amW5m6vT1DS2fBRt
daVsOiqUBxPodW0iQUTuTTly3A9zQoJq56v2df4PStHe/uD4MNcXqBrNWI/u+zZ+6kv4qg7703PJ
5LGdYzNdFeiQvccnxUhxPoH3gvDaezYjIgw9yL9jpIp7JUhfdY14Rp9qlPap6HkTVPWaT+iWwoq5
qgg1k9lU7V5psDCYOsKbCkOrkWaDZ8mRffTSJNauiVnWuw0PraYkbstXa6unyK0C2M76agXxDJq3
Fxpcn42B2/GqO6rxYU2RzNzhqEDlrX6ZdIqUpU1g1ZK/ghLfGUkZ7gYTbFm5ub7toI9tqzRf8gY8
PDtFSR4l1dThaYGeqSM7rElDBItim5zi0Ji3e9DLTQ1b72bspyNy2/+uvhiWd9+mKojZPcgPCPF7
Losg4TUA3nQ7hHqZcQhDK+uEdhiLWO2dj6Xg72UJ6d9mGWFSY2L+YKjLq0Bq3ZpnmPuGYa0YxvAa
ndWwa1+lJF/agtW5YKFD2fCI8h9ytyHmiZ5r7mwIl3s+BfezSpbOCJIHJ5qGvwLJ4QVVQA71wx/r
xsGRWyt9Vh4U7OJBjpgmMxSuu1mFlXWFAUNFi1trT7GHMzGQOq+in6dFxI1xWCbgigMXtVCzsuEf
6+yBsU6z0wF3I47LHOjXKrWT8SfopBn1xTXvK+IGs2mtiR20gVM2t14GxfVBBiqMzjPdwObQTQH6
Ui7aGIYkC/zqCaO4GY+X3tlkShFDjjDw9527HfGtwcp8xpQK26j//g9iHdvPbkNj6m+/sKtjus8/
DT8AJnwZBolHiWYEI9Z7N3tiQhxRM3xC9cwBb1Yg1gatTB4pxuMc6CLwe64arEQtfAYy8GOX7b2u
2faHEQbOHx2Olm+vpXcKaxzNGekjvoyM5zOxugL00EF1CW80Huj8HImlz+DcHF4SapkYZW1zxq/E
kFT7FyChFfq4oWa4009XXMeu57DZ3xGVYhwg1l6I/FyaKwpuJJenrWYl+OrrwiWWypWpx+4YFP5e
3MrA+uwTNgnPV65qLGQ9dUnh5at3+cbCInGq0lxhMyUKY8JjwHWfGkiiKs9mMY952Q/RHpF1OLsX
nfjLhya5ONnm8qkFov1dcw1dISBOJ3X8BIZ/BU3R/7mKoAeSDsaF7BMK1uNM+3lSUG50CnPTTlRn
Z+5UIzbKD8Q2aQYlBxWwMcfqxcQkME7lSyItO+CIWryG7lpjp7Hzfyiher7iJNkmeyJ5OFFpjLz+
IIDbrF8NhYQq8Weo4CHDpTYnCzoUFRWd4OYYqfFMHeFZl6LJz3rCcKuGP4BXKD6rDuDySz7KOFog
gDBqp5I26iwG5wDPm25OWjpBQVGLBdGtwY3hd1cbQEGoQYazX2iF3nJhyMRpwL1gmQXZPlxWR5kD
cWZlq0cC49hgNketolUuxh0iWFefRBQVKuOmXV4j5XidS3Gc3WrKKaf/56qGA8oSpcLrCntxZ9ua
9oUlyKQuMsqbQ0m9irirCc/UEmpuDlYP0Jf1v1rY4c0BCidDLqq/DaO+bEI73KHgiqHgA4+laMAA
6mrQyoGkWinEVGKeWMUOEupwUhCySiwvSRYW6IDlAiHIiGltSfUPilxGyXGoT0gVOKuFO0Lt7f1q
QQpDDpj8VMM+eES7+nC/wyWCqU6Idikbc3QcdRhhhHz8pD23p3NsRFiv3uxWWy1NUg6aiMfrIpTJ
AkW6IOXG9HPC7F3lZ05cl1jxrYH4bKGQcbsIk+Q8bD64eSN0UpVOmIKiCi6awl+kyGiHpwcySZzQ
LHx30or8yGcDH+HGcG3+tiLu9cf5i35lfPArsQNUvD0hvm0EdCebvUAxwqSiJGKP6hub4Uf8wyYL
NAxJH7Yn/ybF4Su6hQ+L90qKjydIy8S+v990Y1a3cVj4/er27LblfoQA8C7+BvZaUh7tEegwdOx8
7HOA/VtX708ZKD8hEClsgax2OjXRyhmoEpX+zESiE4dihAjgJgsj+7IbrJynWNAYJCRZMdqODYk1
KFrsDFLQu2sqb3wL/LG4U+Z4S0VKgfFYvVXJVXp3A7LVgfzpWXQhW3fEr6VBjkHJy0+kvPaiNdxG
noZsA9vpAuybSsIXV/0F/TvUQlMBUc7Uh2sJuhd1UbD5GDoCWruS6mdr7Mji7FeuJVAKfHw3BttH
mK6F22qk1+679nwiQJ5iYG7/HNXUxi5WkeAuPafwJBM9CLdWV+7jrk2F6c0bRIB06SufWcNXDavS
V9ykqpwyn2fSXP3iDKSz26cuRHf0F2T9r+Y6moBHf8icccc9pVm1Y6L4T3MystX+03VTOVJ0t/IM
FQYwTCwDT3i94Adrd7mFKbfZE5O1UVNK4HfabIN6xRVAFZmv1KpsqSgKuRPXlDF4b4BJQel3jSfb
Z+jboV7xCBDVPk8Lw5cemNUdpnAs4MhnkDDdrpS1MV60Fd4Qbe4zDJ/u5Zc0a9ws5sYxP51h4Irx
npGm2W2wsJ6zAiudo/F8F3RaPQgjkOlziqUAORd1TFcctwhIf9ZyMcMqyb1kJQxD09Q6nOvayXQ5
yTp71ELVHGs6ZAYe9PvUGyN0t9VY7MOg658wfYwTqEDfIKkzNkL1wRzjCq22JAalI9fkqVbe7EHS
x7CP/XD3L7WGrXh9IhnbqyrgKh1EMSzaKvzQaKPSBr4QKjGW3vJ2xj/pJQywciwFUrvdYm6EsSMV
wChS4v++x1/coznWG0bbcMAJ94A+Nv++6zB3f0XnoYCq2RGMhQ4/6+4jB8VZGEDO1Hz9ux5UPUSX
VUrZznz4NkFQTAo9gT2o5R4wJ1dMXzgrqSp+xpkPJqupYishZnyFcWTxy+Aq5SPHM5z7j2Zjg3Ap
p0i+QBJB6kRnNGOl7/3VnUpf2xTtWVgIr1wCSV7N61c872HRueub7nEiTBw7vUNcGPakMdKXU+Be
eB6V+RsfKiCaZ8M62AbUs9rPwfFP1nid49OGXCp3+JSbCbgrBFPXhKijf+CFtTDZCydclypJOrTR
Mt2LXaD7xp+/F9UbgOYP88auLzhfmCqzI4GrfjPrzRp9tZsHz5EedqxnL/K2JLlOju7SQaA36M6t
b5N/2KmKCrxqsGaonh3/INC4oVTwVGLQMBeO3isTkXCXMvf09vEvdq/GoWz/dPjFT34IDoKZAQ4S
EAANBU6XVdEIZkFe7lOtJGCltf03WAzHP5dAfKBueexzFkndgzITu1kVsl7elWPMq2cKFXsQ9SeL
7QoZth60rr2KU+zzohzp9pVgWE80JGAh2eDg+eCNYEXmqjatSaq+rCXSwW1JOZjLKdxtZVYRTmG+
LXXAn0HftVVa3DiQwLgo3XIJknioewzmlxgasN12riFC/5QCG0tSG2hJAYtQZdXH35P6ds9ewMkn
1dEVw22H+suOXL7WVgbrub2O9SJ5fdc+1RYpOL5CZkS4H6ekdA4RtghHgrJ7xQ3tSUkKwV6rs45Y
Q0TdX8iOBYCX+8HLtPd1MeVwqhRrrMdTHPsjRNyP6YezPv7X8O4AzV7JDI84qDztvmKoCeco7GLE
QY915KFP8Omy2NNVqO2edGgfJnv9ns/ZF0Sk2Th5GcG9xvtv+z2fvy4mEcdh4NAzw0eVK0muLh2d
ZBjpeqUFwyC/01BsgcKvCwqf3iY5tco9BlsPeInvlpubW3SZnkWq+rGQz9DmIDAZDgtA/byEcVNp
uEgaQ5oGIzd+yLPTXSD297TjMXCmgoV1SfIte2e45+hsyid89P46xPF0S39pli01hp0Hyn6+JMv8
pcA6AHCLoKS3viuW/5/c+hlB0w9fzs/8j48u/xdF82s0tCSIhqeL0cnhhNvvfFRqNZb+xvJLc65O
/ZDbAq3UVmHO8OZETtP4EST/687Kb2qLKf6E0F16JCHJ0waLOwcLgP0Rsy2ifDdA351oYMi2lVvD
tv7yQSRrE8h6NYGBScs35PMeLgsGmN2/57UIJIiLT0TpQqQwEOb5hulwM66zOZZihh0r6XA865Jd
v+gI3aW4vAAcaGJBx4XnEs/CDddLnaf+vCYL7A/OulgtlA1ruhcUKLBN/rC7RjZMOY76k48BdlJP
5Zwwj5fyrspUZEHsrLK3AU/YNEBlb+/hcpfKvgc39dMQfR6yEUdrBUDMTMnY3yOOnF0L0YXYddI4
W5WJddHVrcOIK2ZZeq7wYxVSgBwQfWoNwSgdlx8HYn6eT/sW+aUBKQgdtpf1a+x37ZWhQLI57m0W
2e3wGU3CeblI177+KGTeHMA00TxVgu0K8QyskHZFTV7/3hPa4QM3/J30wDiQda9zdz5/9l61d9jS
UJjAF7YufcdZFoPVEQP273rXIo9HKEiX2rwUSUIn0gfA3apvd+l6I6Bn3MFB3OOigqSsTqSkod5c
DuOvYplURpXjUM2J7Y4DIciXsIJEAliQu0iwgIE3eNt+wynNLC8e9T1D0oL1veJV1FUeQ3QczfeO
d0n6NyusGelA87QKRMLaelj6R6zAfsO5WxGVhdsQRNcAXRqB7CW6U3dEq6G8ujMOwcusoLpI1sCP
pmZHv98QM1bdehVgapx5qLBPkdjDyHddSlmPN35QiGcfOYv9SD4lg0UjwmLtPEKqrK2hU9K+b+QQ
ccdhZFYC7nS8t2YssXDq7UEV5nRq7IyDHeCT4tNerdUG4bnx+IG7QLPWd78P9fl9iTDe47WOqY0P
PwskWtVPN/ttW98KsgNruO09F27vfLvtaNjE09U061zSQD41fYUWRjwCiJ8fXkbWySUEo19NbKqX
SoO/ETRa1cSwBhUzDOttlKfM6OD4MH6n32BczkrOgednN4brXg8N2UFH5N95O4PY9KOrV8mr+VcF
+jZSO66q6oVbHYpZEn6NUUp+d4O3ZIUgWbr6hfbULfuJworV0vhuB7+AXZkO7b4AafMGWh4DtXOx
FtwEKuJNx9ZXfZ/i1B4fri+brd4u0HX5HZXgFCCKRPPM0C18MpEpEsU9LqmhHNTS7Yer/99WjDeO
5hUtbqe8nFS1uWyHx2Y88oEAp+9kEZe7EyFASmIpNpxHOAHMLrFX1GNVMdE/4Y8LzPstp/XOQr/y
caRRwHOkWy3lON32xe1r6Uu6irGdRz+E6jaVTeZaRS7PStG64UUAhRCP5oDQWmfuWFbVFgpGvY0l
Iw920ruB7qJnZqIL01AqFajX6+d3zAyZLwSqR8jwBmvlki2aYsZ3oDCuhgZG1X/ltuMlt21KTijz
hvVDkYDr6HzzaC9rG2j1hcwUHb5ZmrD+E7R0s/qQMJsq+MioHnIxqqoHDl3I3cg+JatVaaxkIYnd
0JhXskuUvWu3tvc8PimP+BfZkC9lqk2iTZvtt80BHfl/I1VzroNfTKgSuqtoIq/eeyD8RxfKGeqV
bgWn6R8Itu6vnvqTA2fCeE8osjXPIplXg2OTZ0N8YsAW/QjvtV2AFnqadACCp5klNw5b8rWybbWf
oBCx/sTAqiKeMISUE6g/9iiw7pBH2rjViilNUBW95TaylJ4zLlGhhH8ovGk1y8d7RHmjiKhG/I3d
UrTlfoNcRbGipl//AVYeR82N1koLLw4/fb75oopxGnAGlqmK2ghop2D7YmcEunfW7Xpu/IB54kuX
5zuh/DkUEOxYlHE/J8mtClsks0Dxj9QmSIQMiSka31U5p33awmqPmHisf2EKYF9ZKL9GTAHyd/Bf
+NMuexAhtODshCW9YSow833xws2S3Sgu5TygaZoAlpY/3m++yFdEMSx9f8ExKrzrh8OygFkH/lEw
F0V3vRjVnmHcB79vfiCFhpqxMXNa6/cbBnkiFVweYyVEYmQLlmHJOFPCvG+06/gK9wWpoD/i/xmN
MRxcAvraHF3C42DKM2wfXJlz31U5FMo0siKHGAPXJNgELVpedM/3Gv1Dnkkcn0HC4KF7PNKKJH4Y
OM1hlN6kqJq2yrESIsTCTe5KpFA56dTrC6cLMxYVkoV7PMkVQb8cG7MrkOlp4JfrOnVvlHOGn4vO
iFFlvf1IgY4/ve0bYy39HerN9Nip9LoA9hPPKtfw7ypjsT5LTMGak5hinatnx5DhhZPmI3zq8gl7
QKki/+A+slxX8UET36H2idDhwnKZtsnT5zQPSVl7dV9ydH2XX+kTNy2vVK9tFimg61pPjgYmkuY0
Wve47oiv51OgdR6sjU3IXmvK9h5EbqC1zU1kUmyrqZDkzZo5SxbLqi0aUbV4eqcW1s08hzNKYnli
NWNPmXkSbCNXDVpCIT0sEFxwhme4y1zOJYmtkbPBqIbRQRs0Us+H8GpxGvUq5FU8VoDWSSbFV7aT
RtOSg9qPYgo3889GQ+72MFJJO0yxmWNV89IaQncdXnTyOF5ZTYzGMhb7YiWyOr2U8xH94WNHNAPV
ZlOoh1SkGKbsy636QVEMvekVhtF+AHx51Y4+FU7Bdvub2AMeXyGspVpU2eY77CI7iR/C24xN5tnz
39jg70cMiQ0MUYZgon/E/BtY+7k+aGwNAnop8schInNcyXDnMioL9Qdu7oAO7IgZDRg5ZRNkIhUJ
ONbceGjh27wgmmxrCyZOcJEmRwB2p8cesHGGsPiTbBZwZeMAxME7p/BWyB9vr3NKVZqLzFHMs5qQ
tXiQA0WfyShcaPzbSGccm4Ub9kVFSKjAT4Q1EnxBWFQvjS+CvGbQBSeIJyU1lhccDoYIMqKRhDp4
xWpbE6LqTAtiT/j0aATHoMShvSCGeobKDmt9o2wGcAt6cYs3dtYAmFpf/Nr9sXDhWCmDdTpIYtSF
QV0Z4OGDxfBbZw9CmZDDXIcqGSgAvUb5yzhA8aFVLuB5tSnC28RiGseEGaJHjw1cdJz/5f852Ah8
NOiwL13xwfF6KgUOvgZJ64ZBzWjUxh5FxsUQLF0jif6Jc8mwo4TxcdNazgLjUEcrG2sWO4C2sgBt
G9eNkcVEDvs+mmvpujJUVsEGRnAH5YhS/KaKO3ALLgKut4vqSk4b/sUlD1KgdUIFwqpSS8EhqVJI
nwhAUJgk2VRKkjFYgCtz7SXuyV+kQApVViVEuUFSdkXjmRrFkrYE9568AZHS0HKvIg3646yZXH/J
DIkurc0UA58K15fU9JybAmIvhhvBJfCLW4Xc+LYxhRy8pk62Uz/xZbAPBXDjTa/v0g+woAJk5d5b
gUMzt/KyEUR1iq2PaNbffp1dkgdoDceuHk9jD+rmpSyqedxLO9DauVb9Tx8JiJXfLQM31f66AKQI
5gQE0OE2qNOdsmLH6nGDQkvjKhvIjLG+4DRgGxnrjgejJyGM5Dg92u30fBGk++6X/GlDc2Fl5Xh5
SLePfaAwP8CDyc07kVor9bjx5eYYnQIXtyF+xJ/0nY/N/a8JIlT70eTiaKThR2Lvr/XwPC4rPkQL
jD8/JbqH+cYlA85dYyn9R6osVtgAxkDMr9xPMMDSO71ZcmECSjLbAGYgu+hdjs2JNXCsGWcI2xRp
J4d0RjPviXobk0a+G2Omqwc1ftG62H0PyfadOPgv/cwFVH6hPNY0zR9tSDNi9dkbj3kSDw2ZUfZM
5dRttI4IjqSBwP5weNzdgcuz+XOIk92ljKfopegjpfLT+gplaqZ/ZNijs+pbnaJZHGg9ibfNGf2F
goCTESxQGtUcQwbP9dW4y8N4xUMXGrxHq1z7mSwXIUxSBUrK9HgYtaNJFAC/Aq7nivns7fLNXiJk
2w84F6TK+RX8a011kD3Yk+t1ERA6GlK5bU/kt46fMtfyRFmP3/VYQtbefzK/cm4DLEy/nyU1RE2r
sRQk9oswdOnbFTg2yDmF/4YSJicjfibVynu9gRO4dhG5pd3DX9LR88m+4ExpnbfmS1KnCePk765T
HkSlPSJA78w4MKzb0Kj5C5dt3XLEwC4eilIUevcL/vqcTAjuREbULvYA0WuglJuvn828B3mpFSOb
CZndwUSrH2uOnZnvNJQhNzgrN7nvWVsYJPphlWK5eBEskJFpHa8xN+vmB+PZOgZqoD4lek3SkQk7
WyfraLZFO9BM8Vyvvoan4ijLtNmbliIsHTZRJ4Yb/WAL9uWo7yl2PEpqoMNA5xLuLQB/NQ40T2Pz
ya/plE19TRNnMFsVBzs3IaZtP/1RO9BzveZZVdLFqKYAfXOJS23cleW/aKdeLcT5krvWN/kGSULB
z+PBiH/Go9VHat6F7Pc3+gvZlHQx7FfZIDj5OLcDE1xYvuIQ3Rh1N8gmRJ2a6iY6vcmMesBvlB5/
HdwO5/JTWHQFhbvD2B9pOko65zGE7pStJ88sIQ/FO9w7+3vxPPgWvp6E+kyyNODra/HsGJMUr7TY
LwM5SHtNmhXjpOKKoXUY+LUs9bzKUZnnqX6Mv5f4V6rA0P8VKfCSAb5W5C4f3LmPUTgepO8rV7Qs
fsBgoUAegW1hIl4iQW0iXpqLs4mdUfHQsnWLbEvhzfFEJCYOUgOXK5rIj7tB/ZM3O8UX+0HINxqB
GSNyBiQBWQsim49/Ht9CFtK/sO9S3D7VCQKAKDJIJnbDHqgk0or9FEFt/kRe3FObYtgYiOixluhB
z4xj9OlZCX8bkNx7AkVgFeCmEwoRyKOfQGYIS85MLXBmukBS0nCfqsIa7hWP6LdeJa5CLiYJeG0t
oXbulu9ft4OQNKb0wIb8gyz8/whT3x1pMwMVKYWnkaSoWxoCrbasUIpveSILgLjofRu9y1Z0neKK
MOOCBXxbmBANUQIcz/ntfKs6LQVmR6jEFExagVlunqKf6QcrVW9AMOKZIPrbL02HV+J1aW0//WYJ
HkFCfdXCIZ3mPMNyzTurh0J+39gJ2qcGxy+KWDthnQcZodAmoTwnVj1sQzZo3BKrzfVQIEbYU2JZ
EMZrQOVaeUGaQFFyA8/RDB/3w1H4DeMtfC3qbSMnIWNNwIEuhDiYA0fLVNQVHdPWV4l4q69oqrGX
+kLkSBHX3NrEyNpWyB5PqL9ssObDSgzzw6ByFAeIaLX2l+d9PfRSlL8jcwqo1HUzV+DfrGJXF8oy
MNW/HEaxjzVpsZxfRrnF5JdZQn9IS7R0m4IPbeTrMbYSmpFCjECd0EFu10c7R79oAmMDZFr3vLif
0hXfPX2/szYXj0KwgduQOP5wBcDCNNsfo+YIGxk5gcamx+hgH4lZEMigA5miKF2piIUHLsBt/MI+
OuWeIeksPQB4fIuEzy2XPJ5YH5kR3EDOfhTj8yU33gqxdbyvSlddfwumgr6a9gwzkUEUu2CIimF8
OZ4pr4RCuhpxqgAdCVG9hnixnyhGZaE2l/tqk6+dv4T4c3HyfenLMqV/BqlV7wTxoZxDrKf5TrH7
BL/H1ERxdg0CLlhnkV/ua4gbx5zzlx//N4Gz3GY/TeMSM7LhEG5P8MIuftJJsju1JipzwsR7Ta+w
RSLo0bRv1bEHpASWiDEtbyAkkyx3bR5EA3sLKN2/Adbm7a9VqieZOzP7URuGv/Le5J/QwAI0A4bH
TjFZnwZVBBECARmqu+nhjZcBZXneM/EagKpdIXFpJ7lLIV/66+CDO26DyI3czhe9xOeXThYOHBIB
+X3qPKrobkg2zziHq+4mIfMWK+mh4UTg9GptnUTVK+BsaHMgMWXuih97zZJit1eWOTQuZ8SiYOI2
CF/8/d319MGjjjJqbKOLZn/hZpn56yddOApIWkfS0WpNe8gdRl5Wz9W+5Z15Ircv1Zzl5iu7k3gj
9reBWdDkbIWHvxhN3MmZmevLnX7MydAPjEIyf4528YE59gx0DBtcdMa/dZUZRZ3aA/mXaM8huX9b
14cGj8dHOz7WVay0WDygYoeVDmDPDJtQmT1O/V7GdC81xrtQyBAGYh6AJSXyxv4kgX0kvXDYoGkx
JGI9YN+3lAKloSW7szGHiCxBAx7rpjL7D9Z6V3ELXcLssdQSwqoUJq3AxzekovBQzaS005AmWETQ
U+fbjVxAAuIzSE55zfecXRl0HIBokACBguq1Q2wy2iIGqkrE6hHCI7Ehc8y0Gxy8+yS4lR/rVajl
nDcBp1qElP7WSSEY4E2o9JK6XJTXk2hrfKjSJ7XYv7XKNKx6mHbaZs5dSuT/CjH13hy7reHrCAoj
iD4DbQR0fwcgABvC7Vt30l93xKq8rSaZeFFqAE4e2Nfw8rM5JQj4kgXpLPWVyuNwBt//axVZiVBG
Tw6JdTWRSPIplDHSb2eE1Swc1nrLj4YqMVSE8Yacrxek65izXS16IYkTVdZd4YJZGyzzqgx9ME3q
pMqhQ6Bs9A0Vv03WA24GOZYHWqzE1bg/FiTPDi6TJGUPj0HlwrScaBm6XwiG1pQZb375+Y+yVqke
3pOsHOx08lxuTfoel/J4hXUA/8Xmta4lJnYCf/HO2EJFtjnoTplZ52GegjmW37QV3HRBe0xUcVUB
sXlQisrnFHb30WkaaGUzksjX+ZTBdw+SPsifXqub2bxtfxdgL6/f1lhDssShau3ioI850pndH4lH
o+pZAyTQwfgAxQPnTuzOL82xDkKDJmBzC+liZiK71EPb7jHsNRPgbtn7jIrc0iiUkpEbyuJNJe0r
ng0j9sF8cyNH4k3p6xZN/FOTjPVcHTrzEa1QmWZq6lr8h1yY/WuoQ2G2mb6w+Bo5zZjQmhOMQpiA
wxawxlNXafgdvU9BNFeidR2KCt46pnrqFycp5r0HJKbN1aWJtvoyWyeb3v+qkzjzzHqTqQgD4RI8
x2e5RFb98k9pTCClMI+uMh+6MsqSosjSfhWvuAaUVuKJd+IM6e7aooEw2n+kIPKtDn023YU9ZU+s
VwEzbY6Q7Y0nwxIQ0/+itB5rPdi29IriFHZhtOmJ84WgwkSVxIrsmgXDwFzw/wvm73TBsVvls0nK
CtUYwEU2AVDTBLXsqDupCeQGLAofixJLB89pt1+RyvuaQHL6RKyHIrZO6qT5x23k9CpZg/7csqIW
NGhyHnR5IVbl3PKXwnsbemBXZH/hFxDgyK+xdxFRaDM4TESL6vksHVdn4RCuqyLD7ZpJN4xHRWSA
lGwEw3iSEvprR4rSAUJVrqm0JD1w6AK7l1CaqwoeV+c2uEbjTB0vmjhrnUoVc15SA5aCcitw7qT3
k8uqafsz1j4aeVDf8CvFlsw6aFfnFGKezJOXQtc20lw8DCxpw6PSf7b0pwgJqyBRD2U/F/G6paeR
UKVTWJXPonE7a4J4YyEkAr9qMorfg77cAzu7IO0cLRhDZk+q4L09yOQ8qz8+/IEZ2//P1zv5ktG5
TVxxgx7yrVXA5H4ER1OIBExOie9wBeHCzZvKZxSPQ/H1wphklKzrl/Lt5WGqElBSG92c59xcstNF
huwmuhlzYe1tRcEIJvO5tl0Be7sJwP1wKNkMjmsrfM+sgOb5HzR7pT/KMQsgczqVoTKkQ/xNpVtW
rn1Fl+sF3o+tmy187AtI/9pXEQMdiI5+uPCMeAjbgwW7EQkfYRL5qot+LUKtgIc4ozG3hRZHAvpb
KfyTDAIF2JzBB7b/KGBFPtm4tpM3ArsWX9s830Mwk52qn+lvqdr0i2q9lESXab2eQxSVlnZZ3AG9
eG0AhlXjvTIkmtssClGTAartM1VwR0CN5krfxoFME0IDHx2i5RTkS0ctVcqq531gzy3eIaktoPln
Ad7MmobQA63SJdIpdjkPLph9e8xxF7AJMXAQ6fzTo9zH0SOo9tSOOhuRst68Cy9hS4l2BGz6cPgC
0Fwgcx0tag5kBVHbNo8qrKAF20aghTVWM8/ZTB74M7ZyD7FV9G/NcyYtdfKyxX3Xtc1219QETD1k
sWOoyzMBYVWldJcyVWzdx2TV0aoLdrXFuCOc0TxlZY6YVX48A3WBOzm3mNQM3R1OsXM9J3++nyxo
P3JdLpmg7Ol7rCRGI8D5jw2VowPg1F7rzF3KvIu+vGGCbXUyI+J+7jPJeSgRLTLbTwdyr+8cySlx
9KWxlUAbAUyStXOgoAclU8J3K4LKqyLvb9Vzt1aWJXGVdvFZcG89BP/TqKsAMp+5dwGAbqhxLDHx
boRgSDijh/+99ylntdXB1sPktRAi/zAcX3iSt705/jwFFXheyqWJ+JeYwgkMCQJV6OSxLJ47iP52
Aksjcdae0tgGY7YCwWw7Wl40KIlineZH4W0giQiailD9PbnqLQeosxiRmTivcx2nErSHuddKqdP1
ojqsCQaL5FKWG450bjsWOrV9TNH1vPRYIi9JLmF0ZcU5EZKLrfbwE/QAe1c6keDpveJOdQOI7yeM
fHi1a4tKuZbecDz61fgPfG+DzSZvIuor06EVkpvzqKYAMxcT5TBSdZ78GdpDtW6MG9zTVSwBEBJK
3D1CPOy/Nubh4un209zn66QRjeTa7/eIDowp6vZn9Ps4eYS1jqCBsewRT6arCjBme/BbavFvRB70
r7LKBM/itjZhOV+71Qzys93She6UtLhAUoY6FFTW0by6xMafvsry1AwKESI0KAg/zuABoTSBw4PB
ah5Uu3E7OD2CngJ2VVlHG0o6LXdPobO4QOEPseRvr+akoNF1pL55kCGiJfhktEU+B1MReH7t+cW+
fZWLS7Kq54kfdxnX/C00EcK1d5YxjN67P/lrCACpmN9Tt85k573HnRSad+az9C5XcEZvBxYATaU2
84lvDN1FTLJjNA4CwtBj/5RjJ/lfnl1AvgqN/RbbNB5145egU/FDzpAtq1Olsr6srCgJhpOTnkdL
GQA5ylWKMhtjUQl1hTed2a88pKecBidgkMaqP4itkgcqtWLaqZIAaVq966y2+5u9C7wZNR4LYzn7
ttn0mB0TwhzEcewoddQrfKelXm+j9zM3QZS4NOFHdpaiZMyJDbWs4LkZXTiXyo+Y7oul7U8GLDsP
nW6eYTWsCB21vGladZ9XAtwoWm9ay+p7+goyDl9fqwgFassNqkC4GYyPpsGfSHYfcN0jbbkRyMT3
hIG1ZHyRV2apgF4FO43kEqqAqO/lTq0v9JnKQeEQ8xtnGynOHXLGypkyxqzhRq8RnbF0FIx52lhN
ehtaSJDHvayvh2BSud4PHscz+IicxJpY8k/RuEJnnHmjNgDTMG5Zaem27bdMokRUdRrmkhWRuRnf
ixkBexFZl8/ljZZB3ScF9D5cT36BGWGiJYMNhK5UDjWKzyAJ/mDMOr+t32877sCrS6cworpNnGm8
dJoBTRbKvJLY5UdEBEwur0H6RlS6b37QxZ4iO77HWq/T9dGqsZivUQ2jAGV33EE2xa8etAueDDjR
/lfIypmUxavfyb3aQ3FCQ2uNzJbeLZaTQ7NC5w+693Bf0om0H+7nwDbEptT8wJcLSZ2l13dEeIch
COMyIU4Eps8887znCPKIA+ujigI2CxAXKRaZyvoUV0/jCdwuTOqIq5h+k6fdlczfqK5ghgWZujMs
7Xwr2tLnYKoLsf24zwpYE01+exph+OoZ0ZdF4vRGxDhLNHwDTZ4ERNonVNeTmssrEmwcQ0zbd8pY
AU433WegwSlaOGgmmjdj+Oe3GCsajVrw6Rg3eANcZUuTjBy/RgmQA6GDP4Gf/1XaAfCQwDriO4Iq
d/LSg2t7VqcieKhGP74j2xG52tZoEcSviMbzGVK6Rql+g+S1fKFne1ZxSQ+MN68OtBrWXobu+6bQ
pjQc0x8e9UhQz4OhoCFb8S9Jv+BW8tI2/KsNSVfJzM0vn+Vx6t3+8ZJjuPjWODej8kNbb/EE7BNj
XfFehe9BpGsYvWFVVwhoY8qtU01lkCo4r/neIz75HynZt/PxOyEUentpPAnhIpoZgcPGoopIRl0b
XOpwNfoFUlxBGRCuei+W9HhFzo1idSe/ii1qMuRKsJVwjkp14xpgA4puHqABfGk8VDjtQMoRP7UZ
M/O4G2SctLfaS8AfuzxzctwmTjZ95S28T1ZQDUDouXx74Ue6Whp0ttQhQ4d3ToCVoQdrMJLslxcW
U5BAwccp/kVEXWQnwoKw3mSeu7OG9vQGitAihw+NdACjXtt/rPsoymc4uhzMB7zzCK3DK4EAGdtN
0ScgbX1stdFM3SwsHv3T2Efszh5+8ofkFkcjADmKoundg/WKRRzO/fdDb0q8IyydHRppvWhx1B6g
xvnBWTYPAa/nD/ya6n+5as8qKXRkWliaTBnAFsTQWlYXq2DFoYprbWi8QlFMTTJzo8DyAFVSntuF
MNXTn7rX4g7oiQfZpO80GtzeOseSO2o13XOg3gxWQwhT/aI4EvOQX/h47JcAo9EVIP/wQfpRqKtQ
gg8P+TdLsBYciMdip4HtfAedtf/B2sp6HBmYMJJcGbiJZXwwJWpcbZqUz3QT4xVewnwrswtNR2Az
aitZtkacq0O+tcMi4y54Jow32cEFt1YcVY+3eegUKNI4pz9UBAVa3PcL3vAcjm/DR9YPB7QveI25
3zjCoUR+/aLC1DFoDJW3ylNrK8etRMqctdy6nDx2s4s8vI//YHzRmB1C2rEFLSQk3I+aA/zcn3iC
bgo6uPK1H1aLXg+JaqoAAli3uIVK8hjqfdM5AvQaZE8UVvijr02NNm2WNkyoWbnxdsOKZ8MRsWao
F9YjlX85Wu/Z+yTY1XzG1Ao9Zo/RAS1Ks2spTPF4KG4WMgFm6RqKh2HegLFQlGDsHPiZTTnlFGAR
mFF3/DeLeSK7afPKVKQ+T3q1I1kcTATklF2WbvwUsymhqTA+fYQmDl5XEArqHMtH+R13SmRpy/xt
s+ODvEB25/E1C2BEfMUEukVAjFHcSp3kHnls+0BoGq9KMmLoyt+ccdGUKecvytsldHNZZQPIE4EG
tuEITVjgyMQg/DSeXXaNjxzxSUDjt3HCEhmBZMOzv4qxuiYGhlo6CTDh13ABCfR6pAZcFWvFhD1F
gDHIyoP2Qpz7BjZNPhMuFckCvD3w7kR9rye+IVUVDphzMVWnhmw0fnqD+L9XMvgKElqOZy1f4G2b
R3K759hNqnERiW0mj7IdpPC8EltQWswgjz101ltwjD76W8KVO5uF7/zrDklKwJe8xmVnjM+Nvd9r
qB2qPBW8O6f6wPLu6aOqlgdoImSTrTDlta+pIyoLNQ7cezsmRxcx/ECSjb/mlsEIPlJuCM/Q5w5l
13TB2CIBuxNaE6SzlZPIMVg7VC9VbgxUm953HMkQibUcKLa0LHYvMqL/EMxLOA1AwTCIsl7VYLd2
Hsthbe41zgQBX1Zz7BeMXgkhQWyQ19t8HPErhwU5Pj1eaGT1Ab7UMc0b1kpW8+0j0MBsxcy7bK1z
JYlk6Wc8gwIUfvujhs40tPzWJ09tTibPOxUr3sq/LfJO5hu9Ui+LmrDoHOZkuMowB6O+hCJyT3yf
7z+WG2em4mh9kggdqCFtCAm5gz3iKmYn4v7lBXuiJDqF6TADNgOdF8eA+DmRVFCkWeyaSRFAxf3v
C1kukdzY78Bcyv3eE/tPo1/UvbANpozAm51bnrzt9198bb1sY8RXE4e/kzI/8oL7yZKKeIJHyQFV
JYnwYpQMJZQRyoz0qv92+D25u3ZM2wp1I2hdPqc6z4AYYrEPQ4bJB3WOkWllQyX7Edn1soMNhVHa
Booh+EsOAyy8w7O4zmrQCZjkx/OQRi5llQ8xvKxiDLixTunIHEJupXAkMHXXgJF1OgGgYnZjpCCX
1GSfKGAQ6zZ/AUqJ26uZBxkOxrMzYZb7BNReZlRX4QqW0VoEp24jCk2tHov5dP6bVfdn9yzQXOUz
D91BRJdVJGBFc7/HcUow1fnvewhDtAE51wWdldGIvSNfxoO9U5uwUBIVXn21N9R/1y8fEitA120g
/SWBCszHS2Yw+rMAShY72C5C1eyhjxIUkiu1qWg9KPiKY3YmBfSTXPNcY/81ekUkXgwmHVm/POLY
wZD4JEOeOEudHZ/QlqkpR8xUm8WP6hb+UZBAILe4d0k99FEWhTIg/WHsTSB3pHW3XfX4dQ6YLnjF
laj9le1n1xbGiaZTjZ3pC6GuSVkpI3FPbrgDNxVu1ERVQcyhoheiVTSusBxB32uh+ap31a8qkCha
6oskkpGz1MjG3pdvBnHfZPD6gukcXptCrYSIs6Lq3vZYqFxTtWr94CccrT0bJYhuEzBoOv1vwR2t
QuUlcFYHCLfqvlQjaLZHvzdsWVAjfa+Z4Us0bi1yGyfNNuUcWuygXc4JMi/65+oEYa0rNh8n1ilD
3DvzF7DYjE46rWk6/YWc03VSTsoTzBG00EXtnrVUrAFQtbMIuR4cZTTajqEtCrn1Ba2pQVGMhBYi
VlvgGujyYik7v0kQEbuQdT2FvRr2CI0sxNY5NHanGLPelZml2L7tlrigDADh890cnTGn7KMBI/WU
dKLscmea64H6DucMcvg7T4yedP2Gd37Ho/1d2K9ETOTuMm51d8EgXqZtCrCg+Jyp2jcbkISxm9kA
fCKWwsFxPs858Vpm+OiW+q8GV/ji0eMVvFQdfAdbOEGVonAWsphjMAvxt1x9sLlPH5vFpTgHTxqD
p38GT8DCgKBhrmaskI5p0EqG8+FIjwLdL25+pilyZsjXvmGyuqjcvRENjOfVePly8tTg3U7wLuRs
42N6Tr3GKNg+USWK3fkbbiwZgNEM2StklrfBUN/A8PHDOPYK/xG0rlzg4kOJ0ZMukIZcMCahCS/9
lt4E3M0ZquuDklA3vAHYhcbA2KT5clcjBQ5l4MlSjFj2q/3mmUfc8lTj9d4A4LEKOT61rfovD/9l
ahh/m9OQcYRGghpzI97yD9uZiXmdAVfgw8i4yDyRjsTs3dlg0DN+jFPwLyMPpI6L3NHyI00SvyPI
ckWrR4f2d1xXhP4kjcqGloEih3gEWVw/WKEigAr5nAK6/RA2ReGdNXn7R2bpyr61QfpdyoKwyS8D
p+GawbeP0t3fc8AV5o85cSNwU3J0YRySavtvDkdnHmEQtlUkItjnOeQK1SjUgx9pogcL/F3eNV1C
Ov6NJfhM7FJwLfVEWQnDPrTJt8iQJt63xOkM3wlFqkHw32R2fBFTmbrr+FvSCdOhv8OPqdBOlldL
Rvjv0b4tqYn3zejD7qNUh18HswAWNC30PprJcGZ9bIq41e/ydCbCpITQ7NjnnboTV5ONLiiEe/JY
9fxviRfqIlD2NUbIYJeka6KRw2hRIw328kfEy+NwZr2r+xBDEtmJf8u+osQ8ZbhWaHbcajZAaVqi
DzQSmz6zOmVT/TJhT1re1A56C1Pz3M3E5K2/5RaOk3myIfUnzttdmko2oMgEJJd2RyTWTvJWK17o
EwiAzbE2JIlRGEVWeBawy71tMLljXTIRttccFF0ECCyIngpOOVxkhtrceCVYTgF2SoskC2IwIuMz
vCwkoOUqSwSBCPOPawQrhfVXnaKL02nLtnF2LLuhaed8dB/lJqrnivwOKoFsNUaj2EhF3jmcArCr
3nbyrvP1cvtczJKJIrLtt657fivstHmjozuClCrV1FTNGU/YJj8vPA52wcVolYyYDqbOl4SHD0Mz
sO/n8t0JTpganNW8irqJcfxTUd+JeAQODlZ/IYbePoZ4H9qBdzf6HaN9ztgmssYXregmqQp9SDRv
UGOr2LYoa+rI4blhH6EG7S01x61VW4n5BQ8UWS91G7kr32FTLm550KLohjSRXmzzHDwjAxJIbStc
7K9qx9jZHd1m5+IwHJwyPTZXhcVOoD6kuM3wyOTodQtx4HV8bvD0cenuCD49UffepUcQKE7F3gfJ
4TxaHQmvkbZm4lG1ivhsQZU6te/VB6MENvGHklNTkO4yK004wbFnZ/Des6/1G50+IgYptjyxIf0K
ZL7hXK7wBPmRnujcqNLxN9sodoVsQj+DnTXrCY68cZv1JqOaoK5xni7FZkkMz97dTXNOyoAcmQzN
UJKM5LZI0noi/ESqrpxBiwtHNNan0/ki87vmeT8KaPK0MiWn6geq2/AxJSDZ3eW+rbcOtWxO5FTB
4IC1eLeCf1wCxROw2saeJX9zR8QUy2rKdTFcgl7Sl+3iCNzFRKYBiWWwP+41Nv0N60vbCLDzU3CV
swqO/QZswZPAH2QA+QVmbAgltjAOjwbX0oIhTTNhpxp5CvlvfByYUqoOQQL8d8QetBEONK6srjLq
gchfrf1bQmiT0vlNxT6AAMD1kdKyxvkDHr3stIZ632nwAQ5UQO6NGHD6NVUb23vM2af63Vo27Xl8
QpYl2CS8ns7wnZNjvvfY/s0ur3oYTPdTAuQEBMJvCwgRLFCnZ+3IKneuUpsrDXUAukAY0msPdtr4
+sjY/3nfj1dLAqcVojQ+uK3oDrxXBN3SZIEKjQHs3COLqFnwzV0qMRqR7LxUznNj3TjybBpx5xi8
K3WC35Y4Gvmnpd5d962yyiU1oxQy3gWnN8fLJ3+yBHJWfab1DKAuQc5/O8RtAsrQR4IifmHicEzz
kJtWWlN0I9uM07WWUkvWgY0unNYDpYVZQ+8Y+mDT+CSvMHYtS2XXZD+1wLSdcIHT2ygP5iSri0Fj
/4+VjQdr6Hs9u+Ns+W2pF0rbgQ3vgdmwylXjsrmqEkKusckkRK1Ej5rIUnhGhcsWY1rRS558AFmD
/AKQgUJb9U1GD7oFvRTbscwNOI6um5N2UAgXPoHWo0M85/k2jVURHx2mG60WOn4/PaGCHvvmtYgz
I8S7pkyd5YsZU63IGvOJjPpIPJA/Befh91Ytq6cQeGXwEpOgPbB0+xBWQZTPQyH7zWW8TRhmr/zo
P6aJTfft43elJpjiFrx/zeUWHYpGKO3B/00xqltlBg6SyRWBntDEcst/2P6wr/Aks0exLyxm6TWb
kv6qiZQ1DK5F0O4PpQMAIQW3eX6rBBNaNMPVfWlAQDhM3eIfLOTND14sCIPcyPnVD8awTNPFjSKl
iyAkgAg2L3n+t0hD43F7oUzCzkeubC46wmMyFtfMwoi0vA1RGb3PMy8MsrZJ7ceJjSfvOJWWrVAW
64eao5aDHKJ8Z6njmQSgFnNJcG8vD9/p2E75RzbiMz2IbabUUorOoGV5gqKXtbKi3XGelneFoUrO
bGrOx0qNq4E88vnZCyUUCxYCJLUur25kQ/Rh/sL37mJSOGtAYUFcEs+cX9oSyshDYgmJwitK05Fx
dwyO8caimc3mHnFLIlOnNyRDsa10R7xJnNkF7lxNJRgWgWwqDuA/cvfxYhZOOp/dZqQ0cwkXdG6r
fWh4VWDt+23texDUokIdM+47cryqI6wHyMqj9nsXQIhEgXA9+rcHD/hqHGa0/RLcR6OKEvWZuDYN
m6Oz24xVf6uSkCUmUewLf1KPdAqGIGBsBDcbKN1VT0axy4tdwgP23ozI83lvbXLix+Q9J3mmzi5B
y0PLov8lq7wseo7FYgVc3+GjItKgCm3nUWalXsH+G0AO9OvOUsoMmK+vZhZAfqTs7sjuQ+Sl7t50
I8vfdi/50Fcp6YzfGBCd/3TeNYJAJhWSUr3/h5cIjbQKagTPpvGmnEgsYKiaxgJzVz06W56guxsA
qkb8Cwf1BkVK4o59pmK4lbWuTdSczAPnbT/m+GHmUHgmLbqEZqisZXff9vo/remlCN+7UFp+eQ1z
0APKBEZdHyUkymuE6bni+NCpnr3aizOXMn7LTy/rW/pTJ0TECQDuEIMgRGAkgusMWrjRf2uAOqOF
cQ0y1L9+tZ22pYYZ05pBiaUdAnP8V1Ct4jx+B0z3ci0waGVUkA+pSx4Ee2ge4O8F8AvkQshsLCVT
CSnzL/3BxSs0T5y5MlPjOKBIbhlmWwFE6qGbrkMiiDxkIgt25b8SbbGgYACDm1Nf6QvhsYSwD038
cacP1gvaBkEMboWDBsRsbvn2EsFuSgi/Q+lDYXcvIp5lLdn0CPEGCSWImHfnrhl0juLoJe2KxqLg
McUPKEdb5ZRXlL5/FuHZ0vxjVMJ7pwZMt1Ou6hhKLg7uyl7ZS50sic7li9fB2hGs2kk92H1/1VLN
HJMZ3wHCzc8fpcjWY3Y4TU2Bic/I33hfMg1nPDAixm3mBYCBrAvEBS1+phIZERGcJ6bVle8K7KEV
oiR7HKkYOe97QVR1FOPOFYkKNSKcQkxc+h9HklYRhGQhFx+AZNtocHT2caoxxoUOk4gQEyXPfMKA
+sYZiX4lQMlajIIurRASMuz05W2nQbQg/GpJvNdt6XhCYWs523seXyYoSPl53bLfRealZdiFKkS9
ZppYyBC3hlz5UMHIheslMJYxxiYCY10ufDolXPXDgEF5pveZ6z5g76AsfwEwMCyO2SVbyQ2DffU/
cTORdOSkBs6lZNxl5Ok79p/RNFs+eAAQ1WYH1gKAnaaiZKmJKNbmByBTXv5O/VTazMyZyfgACwnN
FkLIGW6H9X8tN2uLMc04Xm2MPpLpFusOIbzTNlM/iJkv9x2PBxOjM0Gg7i848bxBcEfHKKVoBviv
ZeLwyDefCgSA5d6CMOUGceNOzmt7iHvYStv1ID7QO6cTzR6q513meoQ8hebyjWhwZFyQdUpVlraw
65u++2Qq9ifUmKcTUIYJthSV658OU2OJW+mu8DIoWUSm0cAAhIdW2Q0G221wUVI1EaIowgPbduqe
oklvIPuD69NvEbm32AXI7AkzYMd0MqqXdx3s0XH9JxhrPn/LhpAQEQDzXBiXUMPOakREmkZRXgCA
QN5tJo4phF50uka4dt0Bj+zwqyHcZX4y/I4FfUvluKBAEJpX/5SuVtYY8Q6zPPOl1OtRBkL99GD5
LPVLBF/KwQMwIr5slVXeLOMhxnDqiciJ33OpdwErm3ZgG6y7JND2FrphwG/2sPGVrZw2HO0PHPqN
XOkDQzqtmSMoa7gMWmUJJiwjEiFZp1PMyJKOkdk14AHCJ5qWZdJIr2Scg6bAGYKW1KOb7YKLbYUU
nv3j7E6+28SBDwGNDVIc2k9HLpyoJVSBVnMm5QydKQ6bVBuBaYwhcr9w9DLpx75cO8ouSJzb6VQj
XJulXWm2NxuDc6OlzVheq/8VMPt3UgCie49/OsS2lNGRptvPxQUHrIKx4lF3wEQYL4nYF4rakImb
u7+icy9gkwg+Q0M8TrOSWzITCTWv3+EYBCXfCRPXRMfdmwmpJehCjqn/lx7s5v5rAOJYrFJ3yrCD
N2bX2bJw+Hj/PP6RotxX32I2SxqJ8dCuN6uXed5r9W5m1adWPdXgSKHdxy2E3MFVTLDPEPlNTGIt
DRr1wKFOnLP+uno+eNPyswQaT9meYdsN4CS8r+1UmOsYY6DKubq3YkPza9aPEfup+3i75/+oUea0
XhJRzWuzW+igucIIoSJf3YK5lk+jKJENX4DbyrIkrsPb9njnKRDM28e1bjOAdCZylLPrrEH7fB22
W8ZzYPlqlgu5nVsNKS/skYni3qpJSC9xsZ+eXpo7IjUaCx5oZfSjkxSrRwGC4V1XUj/TE2EvVR0P
R+cWUcntanV1Zza/U2Ria9L/xJQtG0n9HZUR9ZkplX4laHDNoWzhnwFNRLi6PbDJixVneAZf5V69
yi2WuPbFFDGKi+PL7qNESaL3oKK0OHJkHwyLWaf49IC6AUQ2n0J/ySQHhPLs/TSrqu5BM8pOwsxa
q69txMQ7WH1JhSmlmE8yfTC79mVX9+BnYr/JEALvwcDgR4+CJat83bpRDAKtGq8c7ENAPy1gccGp
wrKWmLzA/l6gXTpQjb779E7R1AUVA608OkXWy30n9I3dw/SDwknLRLuKK9f/n60/rIRvH24zisrk
Ml9aajrykFAN6hcM2deovuHrJp+guX9JbwM8vSbvsHUBp3QUGuC4ryfq+hF7lP1ufuEJepbYfLhb
kqjc5l+mUP81ez68gIhHAYJ+Pzzrawf2iGxx2UR+L/jB7V7Y4UPNs77uZvsNjEoad9W12PhowQdi
ah3flMXKghkVKgcI70XhYFANIXqE8G/wn/ZJn5RyVq+S0IgUUPWp+CzGB+b+GSCCNQVq2dHWq+yT
ObClkgkHoHVczRQq18YltojWwcGO9pXMRc6FiZ1P3oTSTnvuoHQSNYVQrT13tkD4qhWdY5T6s2I2
YNilv0sasef1ylJES8qa1+yMStAj6GQItTl6/lOIYNxwfDacAM6XcSZm/wXI/arBP5Jbf0L5H7WM
xrq36czDH/pyWX5/xEyUZbBgBXm328k5ER6zLBoQfRXooRRQwY88iPaPivfCq29W2XCZNE3pzy5k
t4sVH+66G1/RApeCDnEfLuumdyPXydUEwvbbPUu7kUZDX4liSpitlZuH50ik2+hyyWk/jlr67cO8
8d3SOMpuEz7fW5Qgd7nUg2PVqGgfGfzcvdKaDnzdY4b+pZeUxqWcgevuc7917iFx8TSR8Rnpc6/+
VIQ2eJ2YU0Ff2fE1Wm6cKbt7K7rKTGKO9tE3Lg6NGI/8ruBu8p5cp/w9cq74NhrfJQUwYUfceKwC
tCAoxZhHhlAEjwoJGzXKNrqxOGDW15iEikfceU6RzM6IIBW05pkgNklsHwDd7F1O3lVWfnEx9qqn
YwBTd2G9v0E1j41zL+K/WMBAEauvKi7lDsGw+YZ0Ds8wjCMORntU9jN0CzjVtIakQkHItz780YyU
L4lFnmRzBFX+yxsxM091xCzcfS4UzjDC+oDv8YC83PZ2g/81zLi1KjC5PIrIpeqGZXuz/lDjXzMc
9oHw+YXJogBjvjK8hYhbGalJRsth9KNB7TsgEyTuur/qESSS8LmDEwKQuryz3dFKNWACURSFH0wq
aVLiAKWJKPgCnHht7DO4BU7KCNtd8ltqbshASiOMr6VsTz0OjdiAew83M4023qjvLyOXbjvfSJ4H
5LJj+evT0gTzwM5USt8E0M3BUrN+1345kvmQAulZNo5un5398FPIeakRKZwp1kk4C55eV2vrijwI
75hd78KyBHvIL8C3bdvNpE99Z4OJUhUNO/zXLUQ3ghfw2NOsI9GtFB80O8UsqwBcwog2DWAlTh6H
kaX8K69mCxYswrz8Si5gxBZ+GrbAfAZtfz3iXpjiSEc2LiP6eWGKkceAtA+i7YuwCMBAPe87PYRM
mxsSs1tx7rDTtVsbelFu5z6DjVDjB3EENaVxx0HeeenUFIsu3GlF3VuiiuxGgff+mLrdWEiCj4uW
xI8L2QEEsKWzsIBSHPXtrM6SSiWOdtJ2VVIDFqytDqZaO1ahFWRy7WAyEdTyrUnae55O7RMV3mj9
9ku1C9SghtrlG5N9sG+oO9Fd90uy+iG1VNEUDOYQdYrJLKoPceKzp0yFl6c5ZhjjFrYJq2AwBKzo
FBgfM9KjTqdIZqh6AHut4NKRaw8aB7u2cAkDRUlDo1XtVHm7Fu6WuV+b1TdeWWMSSvSyngTSZfX7
ak6zpOvChFl+8N6iYm+3n/6iTbEKV/jhWjLhPJnmiriZCUStlc/j2lkM9H9Hi5EkBMHSTCtFSrXp
bjdDFJMAC0zw6xMOILpYLQ7Lnl1PRgsKUU8mf/Wbnc2qnppCLVfQxOa0KPAqlrot6EkNatXOcSgY
be3kaXoW5hUxX8jQxeMG45gbHFIY5+3wQh0TDKGt2muIPJxikSNFsrmRPL5wmCnlsoaWoUL/TDpO
yiOlcUFtOaxAubx2qVqH7BwzvFWQ6hYhUhvdu0GLmUoiBEjGY5PqG3vureBCh3UduIEI2kvlXeEy
TLrePz747pcrxIFKsP4lpPwojJZkQOV1vqI89vOUvZY1tzsTXGaSL3rE3shZJlMJ7VZT7VQlnziC
Fes0usADjYDhFm9SRMhXgT2vuOnYIey1m/ynSpIo4zgBKJF0XeLd0qpO+kE1vDXe9M3DQdjcfqK7
QFS+/QTwIr9bIlMMpfneodcIlnQxv+gN5rATbqDgXoGqYgCgaHJUjKHNe8Hda2e3n3Wf2gS6mi/p
vcsCD3qLm/dBRxtGWm2Exi+1SMd004TjBNJQ43+KEnCOBx1/F4x/HF/7kp9TJhvqWpG4e07Q/sRG
FQgNN9i7Hg4jsv6F9GGboM+SuiHe+pNqVui41teYY5MnVWoZg3VYXbrYJVB6zr6M0gVryeUzhYlU
QLsee4nEeA8EH51EMNVEC0fNln2JaWtM6JvnFk6kqFs2fuccC0Axa3f8U21RLK6NvMQO7463+Z3Z
eQ7SBTAKTdNUbbFcjuzTaerd/5S0Sjp3y726EYdct6yuAjpXrG42tprCXKmvpUdgZijU44S3ElDJ
7XAmY/bI+z/0KLLFs80Hq2mGNovxIGDQVRnvFAbVAPlcpM0CcdgIUoLOC/K9pPMKuEMKLAG0YZd4
gqkgp6gFqOR9RbhDh580x+nP43xYke6PIT7cdvX6OjZeOMISYTgQhQk2jf5zXlrdKvLH/CAnf50S
fcc6RQLQqJeXaT3t/grgz64A0HTu/cM6pDa2UTxbjUoLj50p7SUAAzBywrl8EvTrT3g/j4tN4cXM
2FWPpTwbsp9qVAYrJ3RekIMkEmuHbt3Tp0ZONpzYWDCiCWanjKjnoiVdB5+ii2kEUb+9WoYN1UYW
ZyPHWxDxS45/sn+qHhVARmDDCtBTl9+Iuv/0pnKTVDZa/1OGqt10NlYM2Ca342toThutCX267pxh
L8RwFulwpaSANiTsjRTgSbv12c9Cg5CD7wp+ZLoVpHDo+u77Dfwzn1RlAROJYn8JZM7krq78QKz2
P/eyBAdr6mHa+kN/EU4tecZlkMt7N8P8Bk4ELI6nUKvLn5XrlwrSguJKTTFyd+o0/jadXkaf7QTD
FSTtLXfag/wbJuRSPqylQrkWfd2GpPUg+Z7zx7bbh8ssXdbYc+O5JDwOr4CfcsQshNyV0LA2comS
SNPEVN1ZBZYel3lkIcgQ9RM4TBTjXUi6sqzDnfIj7qulq9OY1ksRpBL4iKLM8rzoHoOkUD2HiKEW
Kv/0E9MZrb9OgaEOYYcXctqDQEXCcIB9D7ZT4+NnRQj8m6Rm1RlFqCDem0LFL87kxDfYuLEUCfuE
JytLXbwSW56/069y3SmN709odBY8RMGraOgtcT9dp6/42A2xICfl7cKaed4J6LFA2UpSqYkfn4jT
R6PcdehHGG2t+BH7VAsfTpK+l6xNXI4iLsdQ8H+I7/qTws75DIlj7ZoupdBU37CHjXOVaYVM13HM
YaIBgs3jD6sHpk3a+qDKYLUOo1SpIOafHi1ZnQI6n5Bf6iVKN45PW+sACs3dEXjWoYDefImsu4a1
S3T8bDBXA1WY+MKGoNKV8sPZQ2Jv8bBYlRUsSwWeePMTLD0mdG8TT2o+BpwfWy7o/4L+4xySbKew
u3UWd2EVKPppjFMZ8OvH4o2PQazYV9FA5n7jIezXpEQSfZnYGW7VZUvkA5vgXURuCmXTgd7Rj3Eh
h0dm98TZdvplkbEwI6BYSV8jwtVCqGi/KHaqCMB+03gY1eNJci/6TTFzbQStt232ka8PRmoa392M
T7tG77xluP3d953zks2eEP6Tmz2mrmPbSyb/GZCErCcIoKAmyhx7vkuw1JQ/y9SO9c/XloutW5A7
tmE3eicOlkZ8qGzqFs04kPFVqdwByFEubVeE2nLGFAH19MMRrWyLpPM2sPn5HCA9knbDgL2h/CuA
yWo/1fBtpte/SM3vxE1nFlK6mhSJ15UI1/QvR7Dj68Nr6BYmm7N7CQIcZZSDSY3IxTRpXMLfWa3O
V5q/tcangk+QEkjy+uVX+I18TDrT40Ed5mv6gglYABTWKB3qEGVNs/e8p6OLyAq1AHmXkGjHRceN
KOCsnmXtPnvFadqieyN53Du9o+5d7Dt4o1AyGRn1kvbFxvCqeaezj149nKZK4jGX6JEKY9ogt/Is
F07BjqLIoqJcOQkLZS0CpTWQu5Zp253dMvJ/uV7ApFS1tr0HC4YMO4PFcrFFKDLBhtRfzXcYUBfi
NFP4+usMXmB3JvxX2t/7jWCflZjWJ7s8OU5CiOAnwi8sWKIh5mzu5hUtllc4RezKFUp8gnsXR0z7
TvM2lZTek6XkQ0YQqyPACO/QkpzMNBqBgDK+ZDY61KMS75uEoIPwyaylrTQYHGVhJWDVW9cgutxa
HJ8w7Os8ILdDwxJwOs1MJPDfkIC0cUF/CE1/KMVrDnnuUeh7hoos4v5GCHtUqeFvZaqQBZuJwlOZ
PK4WNDWx75RRHiRFpAnqZqymoyUYb6QiEunKE4YyQtP+JNVbEXEHFbrQzFilllDLYfqMMf8EgBMK
crGMU+KOa1an+OldTwyqIkt+HN1rlgFcsWiziFw90L3V1JrMlMlGri/fnLQSZH7b5FZ4dQK2kO8c
0NpdbiG2YQRfd7BCPJvKYj4G7DilN/gEx4pUeMuC7FMYOjOdx5/hmREnaXBLp9XmYPcUTcSBtXU6
oaTuqAVmuReua9oGV0whWsbPEEpE4YtINXuT6sJ+HR2RQnjexz0JyuCCb2zQjekGb6oXqwuBQSIv
HJKoX3Xb2JMvjuOnH6+vO2/Oq+bNq7fyYE3ePNT5zjmy3P+CYoXTr8ondiNhoPNoa/CQidop36MA
P87neschvAHo9n4O9RphZPNzRYsgTFhC54d15wKmptAXmyD6KfB7wAU0PuVLv5pCAkKjPLj/wxnF
qxIKl5YxPUaHi54+698OFkKxUwHKlX6IbWJpb9kyuBOlYGZE4CAnsot3zxz4Bq06CNaZHAOFhUfk
8466Ajh49XuvxvIILSrkIFjTZLGQhz4DfHh87YIbD1XwBf1xBulpdZvvJTo1VHnYrUEZqXUrYNwf
mDcIJk4SYHGRdTq/pgS/A73nlAv17/x5JWFaz6HHB2/9qVaH3kLqaz/IzLPnfieIU+TQJfHLYLvr
hZJBf1jOxDDJ+iJj7zqjoCTvcrickfj+ueKF2vCbQj9Iw4J8WylXACaKjCOMmYpS9DRJbeQ2VNaM
MaBfljgRzypNrrHbtRMR7iP75gGwSMbT4O+5OE57SlI+3D+lAjxRMMJkYk14AMEDsDU2/CmJQWt0
YmGcoTJXxsV45s3r0OEbDcmyDDdXserUXCcuol8mX9fJ1U09Yah3YHpOsgdefpEG/O7+VHHspRBi
xqUNU0vI+2k2yIN95ea194kgsXNvFFy8vwNt024kA62Muzb9h5DcCFCi8lFx3jeifofHEo82tqIF
00+7jsnPNXoBKGBJXfjjMeN3Llu3sni+bCcBL3TRN7MaK3vXsZO3EzbQ+csCDid2IeYO0Xzlwb5T
1phTWsYo3NJhKHY6/e8y3nzibdjbfaLAhanINYG2HYV+hitpy+Ct/mBK+i0toDfaPgrJ48Hmk5ZJ
oqJ113Bhkbb7uHy4HGrI7Y/Zm4g1chq/C2urKqJSZkwt4f20AVdyC228O9KleO7ZlDme4KBstsRR
7rC3dlDy3mj/r32cxVZvY9C2478jF+RILvc+S0dy/Sqc5Da7Fk+iOYv11Wnx4s9BdL1kEHqWiunr
vutV7ouRJy/ZEPrQi8alXbQCUUZx5+qcwokWHKVSJYyPPtw2VRPEkaJUnvDOulEuGkXozptE6WnM
DveO2gj7+YrJZJ0lM5C9m/ALx7NUJ16EuN6dorakXiTS+Hlbl6LCYGq5zxMzqVLJTnGmkfdL7TWc
5PZEbYgl4xTbZJO6uNMsdDqK/A5Agw2uWCzJ+N278Lr3cOVAmWEP5xzdV/TT/ff2SPeOoG2MhGPR
RMHnxvWabh3rNRn0+s3+nSz/Eqp8j/CwhTzI5PXd+6inolN+XBS2u1vBq8sTt3JFLnDEJ55HLAG5
6JillSrtaIqyO9mEhVabDJmDbATU7gbho2lRPKthNmsBm9uy0TjnFpZARCX9iG5DHGnXKfj3x5FM
6015F1xooy8sTqV87Lj1Att9FK3e/ZHwVvPl+eeblymE7kCvCrVeuUklqvKEpVoz5vk0AsiROUdO
YmIcGYgXxLqDSVhv2HdwxPSCqus0OGcPHv2LHMSGn1bGGV3Sb8I4u8PLU/s5aqhiKRuHaZvoy91f
dWkeWQCopqW8V8o5sXMQyxm7SYgqEuWVtZrXp2952BgiVG7x8GRFBJxk7oFiz6in2UXgScMiC+dj
qDEo+bG6RdosNRZuB99LHbuuNEcmYZL3gSk3CDeczto6e82f6fQFwCaMm7y9qXltgHlHmXZt7Zew
pMlvgclV4nu14IxmDzSbay+dffXJiBcxdsi/HuE54mJyaITj9GHRSR8DwdWKWOBB4DHQJedITeOO
wuQw9mB5lduOVYL2GdpaR+8eP/2GPpCkwrrj9kl5J7o0x3ebYrkbAY/OkcerJEX/ZdydzkmveIWn
NHEjlUKjVxTi3e0GgprQPhy3Yklbt7cMeqLgwtv/t3pNvJrjAILiOIoYh2jTz7t2SCAizJbtFPOx
XJvlBYng6lRI6qXRKa8Qp6mNTBuydRHV2GTKnzfZLewkuEKC5hHDGItXe/yNVEme+N+51t0lowcn
Uml2WcroacmNvRKG1BGtUAFB30qDqzOv5BDe21cfi+YL8dOLhu3lfjRxxqfAaIo/akh7VRSd37Wh
PlpQrMavY0Pa/rRML7NzEHbPMUQQt6JJBbQGlTn/NWWaqpwb78VW09ptlD/xmrFTIlWW4uz5EcYy
BUoRSCYOmtNtSsI27h0GPk3bV72+g2G0H7Cz3oL0rBh1kCM64FqFMSxUrP2/ucINdvSfb2SHwPOd
YQjYBXyao7yxcyd6FBheZ80+ahAQUiZPThX/55lZt3YvVTBq9fHAwkIXaNiI7ELGDnW74HO0Z3jD
SOjcPR14bv7YPEayPbAXjBqZYMYKaW/hD4sM5ZOts67W4/d5xTn2WMgQp5IJN+HDTspyl61f4Nh7
hJpkeUkTUP3b6Z4wPd0iqJfrP0nKbKhOKn9ukaTiwoNlUqqnsql4AP0J/nSl6zXHeRaXaXLu1Lgq
qhJiy+XGWxmxL/izVGM8aNobuDSvCGiaap9MhtCAG1RAvy9rAEnPGuJ+0HMVJaNX03vP8G/NUuw1
Q2hYzjeOuMJNI7Ovjd2Dh6tQjBKACSpiDH0LhbE8TBjc1n+t6XSqeUjUyxjUBzwG34xGfiz7fXVj
s/3IZHXwfRcQDllhEy9hIzuYsj/VGfDL2ydSEv7AMYoDYbRyH9Mw1/EI74fe8nFnWAfFlPb4VG45
E595163c6QvpxKtryzCVwJgDw6NX/DdHSPCvMDqwFfJcYkSIz3n3rYmX9/0GpPXFv1gAkfFWVn8l
/95uyy53iPOmOEFDCPsPh5TPHUek0ckRCW/+s/7YCHp9qX2fivMebgGaPrSxFhyXZy96rZz3+/g/
fk0CH5kqNuNsJ60j9wzCQ9cxPs5xo/PY3d7IPr6WspZEwO3FpmXV0yUQZzUCNUb53355QztdJpcN
4X7HE1/ocyHg2cj1/k1qiVw1TGXaAHAeSr10q00oxxEy6Cs1JH15ukCEsctKsBBnJOe1IKd9RfyE
opb3w4nwxD7kRjtMvIrYo+UTgy94+uxLKAVHjxrV5WVkpvXMhr7+Uz3nnmtKnMVav8kyErP9vbgb
kAVKvEEtPdlYrXhnN6CdPzPGgbn9X/U/brLVpspUjPWc2EMgklmPGq8tNVbQdvF3W+uHUzweHBs9
TbcDlWxgKuzBXY34ofSBQqBs661w1Xw+pBnzb7CMTwQ15twWFWrNdYn9dSu/4abZ4aPjP68SLXNQ
tqsosifPt8C2xN15RwO75qMW395ON2s7pODrLVjN6n9+0FyKxWykdOVw6Pk7UNILfTV7XpyNauxt
qu8aIF+70Ie8ksrzaMITYF2rAp/gyGjHPbUbv0w604TAT57CsDFPkhmxRqVdW6WXSevS+7RBrFLr
ZzzYEWcCLVJ+UidagiT9ItB53xwkdVFF0mvSr9L02s3Otl8iGuiQn4lgdGD/TASVVJWy7hLFTDV5
50cQvkbWN6hSMTpUT/WNzYLC19pGH6xQ7QC3vxPEKemKv2O34ADfnVZoy1Hza/S6Vn5YM+4UzHeV
e7r/6AlVDV66dqWYxURuGIxci8eZFEXFTafVBe+KZp9jsuJbEdLY0gWQANi+oXGJiCq68PN0fDoh
GtkVMY4+/Q7JNnpNPLwvoYrgcMaC4azLseCqzNuEUPuDoqiD0oyetvyYU0fSCDZO05ioAsy62fLm
NLADymOXA4AqyfM5tQktlXsDigNsZDLNxDe37aii8nhO6NrVZatFOFcEpPVm+dd5ym24GaSGW4B/
WMOklfvGxl08yj23aRgwoB/sAUwDYoPbQzoFX9clVuvDnOaUJLjMaKZO/dRYBq3IkYOBKwROrUb0
cMOOam5k5dcj38lM0kBIiPZwL0VRjyfQ9ix4VHWgvCEG7DZZuJ68BAbZK0/jkvIhhNcTfhijnanb
o05VyuNDroFly4lo8VC1XbLeb/t1rw8k+mrnLSY0dxIPNU4Z5q4fWfnQMy/wgbxDG52r4NfgoXUt
2/kFECcJq5iQdaN1zXXjPooi2sGNcU4vnYnBcjouA7cRi9ph3SA7C35SUGKSrAMCGomzUsNCDOWO
rDfDknLzkSfkfgT8HPui9zdwBf+ZRLFHa7vofa4gKoBa8+55QurVPlGnYucGe1n1UTtFWt+MZEmH
kRmMhZ+h57YgKk0+SgFDYGBEgAyEjXZeu59k9a/riYLOZl2DZvIs1WxmWAJt8yGMIWmARh5BqAv1
nkHJr7mYPkdb+m/qdeI28rOmDfO16X4ehmujk+uRTvAkT7rmOW7dXEP8/HDMPtvzs/jo+ehfz4e8
Ljb23StZg1HM68X/Cu0vE0PV0MJd7qJcgEEtQKI39TXVDup0ok7sc2xGRjO+lKXD/iHgMxz4O7s8
Td2a/ir1QnekkvJHG5fyZzUmEXPCQMAr310CfpNdH1hRu3Zyyw9GooX/Wqp7GHKMdmchXE2FCAqV
VHMbI4yEyZL3Sd3AU9pqaJec9od3oJ2Qi79qE/Y/q+HvUeW+hwlP/g+D8jV2ogE8h8ZtUnU4r9Zo
p3jNeoewixOD4pOxsJg9owhCo+rbk8zLJuOH7jIGQjwZVgeMwqMYsE+wCj9OpXge0Bb2h7LIKwYb
ZhOGYyz/aCenb3qDUzJqb8KN/ikGgglVUZddM7bbVqeicaz1GhWMnm5TcaqBgtlvidZePpGOBmka
Kt1Bu+pFsGqmoV+4fkx5YG2Xs2T13aFKBAi66wNq9IA0gOqpoPCPgzpO+EjOY2Fu4Vqbm4go1neB
xgDze/OCklOsh1XS7y03zoamThOMMi2VmvRR0GC7O9lnxi0px2oUPtpQKLiRfShsfElFAUAj7wJY
wILq5wtcnBKvPNlN2ZjNmNYyVyDrVUT6AwrQwASM/k84RE2/uyCUC0yDFWZ9FgZ7Y1hIfUo8LGDq
8bB5/uMDC7UO8xLd72ANiFPedGwpzIp2ur2uNToj12XBwD5edbdxo8tPQAeIJvT1r0iqgXmxi7fV
RZ/9EzC81jmsMKH1AZa4kFFYNgLgUQUTE6NaeodSi06w85PAUCSrpBW8UD0uZFhlwuq6fwVWubgl
bDdvL4y9PcSCqfJEE49Grgw+WQm1G06vRbBTDBZjb72uQkIxZxTvspmx9DLhRGZyUrSFtv9y0dn7
1pETF89gNpAwe3Xx0BdBqIUSB3LdwyVvsH+fFH1oRhXMK+Xfezg3cweoy4MKMbRi+O4gyZj1tQUN
K0v1FjeIv45P1+1DgJzdciEEEJzLVjO7QklteC85c0bWxlY01Z1poDEAwVpFdIUMhfjwuQT6Hx/F
mLRTiGb9qQb7X5KVsvUa95v900vxAnGNolOXyEde9hbfSF/fAKcphRuKmFivhiCYqUFpHCW1hBf8
f6jVpMgNPcwh11Mxjz1pB+Tcl7vhhWuWf+tYJfsaBFZi/aEVThRR8QTgSRsfsbImudG2YnL/UpJE
Bm5b17ColSkOtLmMjWpYHwrXas1lPmx0IS8vpoAbnecJrgeLav9IvgJiNtwVFyK1VY0X27kg9Vi/
Eti4kj+g9tkXAKrylak8XYT1IKTbQkiwylS52z284VD+tzkTieEtwe41/gSqzxADm9tlFsqz2fXT
06LvnuenDIRaXygHvjZt5/EfTOWbSCiJAFYap3XxhwYQa0HWD7Z6+LIlRiPw5tzy96Bh7RKsfuTv
NVVlSGmhqDUaMJlENW8GREr2yozf+s2C8/VTKAMeJu2JMaHQmDFSJDZ2RSyG85nPAZqaegqdiW+f
lQ/dva2ukJ+E+/YHGIUodKj2aYWvP2jEa6GdXlv6vc2HHmW2AjwWFNfNCQb4n3+7nj+PvINuFd2Q
KLbkdQ9Pi/AqjwkGaPjqO24YsHGIYD5w5RBqM0bVDn3c6J50NqZbjztED/RUtx2bOUzB7GPIfqF/
pOYGsQgvr+NQFKpj3ANljim8VdRQbI2T6KRZK3edm2iYrtS+1HaQydBMQvQoYkeh7xQjn41Oxhy+
HKr6iRsQB1D561G2Aj2MlIHfEuwNigodlIMzf0zkq58Q9IxBSRxqzy98/O/vU6+Bdv7qJW2NIrsf
qPimUvahYFgNuIShWccTamTl35/fm2VccH7hTDBwwCaaYGkQfXIP5W6eHlspJymYUTm/xLasU5WP
4BGy8o+PJh8Zxht9PqYQfszUGMdFGUZTxYq4bUVS5m3aZE+A5ixuZX9u5lW1m4sKPonhJDa0Uz3b
Y1UK6rb5kiskJNzaB0nIcw2TQhvM7UhnQT0AGvrhQicRGpXO1e2ZPsn4r254j8hrWlePCBKmmNmN
TNCQ+taBDmid1B50sgWOEv3He2eXC7gAMcbmzn+hdZm36wCCjtWV4DJW80tIm0xcja7UbxYnkqvQ
emngaX4qW2yfjiGCa7Z3Y1BGvYaK9rPRPjJBBPuQD6r1Z9njJRYS4+cIycmSKfUW2DCTBvQn/BIk
bwxEF81ks+VxFTzBy1kZABKVRwTtiKewbaO/8VzqdyCPkWdmq9rApGcwVRk280IdKoq5Z5WAXQFF
UuzRyJ/S9Xqfl/S0Uvp4JVVy+xWqVXazhvNWWVnhywX96vxz4rtzkg/xcCILoVrgSU4yQVUViaI3
nlLgMB1OVsPIHEfSzVfdOuLRphLJt4lc2q6X0Mawwo9TnzS+1xL1416TzfDw3BeI0PR1j97ac9kR
nxVgSAhu90tKgxF4uFkge7rpYYsAR/S4JW2HQc4cQPqY/bY04TbHWBLjt7mOF0D6N7a5iQ5rMcuy
xmlsMNOPbrz/CZrTDSpEsQNAOZVw7EIr98IW6EBGi0JlyvQF8cjskK/h6+ZfpDwbs3lPK6SgQS3H
5vnims8+3xxFPFh4b6fetDlweeIXTRbNpXkUtWBhSeDq1vcvtifej7C5mEHeax5qaaX2NG0DAUcP
+0hKUgSPpAekAQxazpiqg1Xj/hfA+LFA/pdBW04Udfr9hHZgf1ltLyz/vT+s81A0wxPGBwYwhI4B
Ya2FVSUnAk0eYNLD7u1EMCJJCQ4DwNpGLlCDYVk3rjKxfcRDuAYjkK+24uhSs0pdLw7eaFMsp9gT
EX1NNF54zu+3T+rJHeLMZssdzXtl1RglaX08PH0a4TUjFa1vbSYHsZkEfF/slxq83+mwbkFCWbrH
HLIMZce4vLrFNw0NlAdCnvl2Z3/ALesKrLXQyCeWleDSiRh+yN8wKiK5JV0N1pwSH0Dw5+XcyUr+
Ly2CuwNXQPgUj+EQHq69PnLOdy2QFZy0tGr2AvS/jnz139SSFE/gh6ZPSOyXUUpQRlLc0sl3irId
HBybhcdGtzkN5gwkS8zLGMbfJ3S08DXmUbDEK19C9y+W9fUw/SjOyG6e8U+ZmLxTL22YnD6q+M1o
11mM9eIPCpiPI5+xUjR8XV18OAwp64fVHiKFa74l54noQPf4w8Np1zqRGW/0zdbu3DE6hOZb4XKS
D/6t39c+wLXjgBMuoWFODH7PXKGDcizHIP2rStdGXACyMNoSfMmRX5jqFmsLdgJTZbag3jHTOEXv
iKgJPuu0+62aspP0FxHz8D3+SXuwwQtyh/1OY291iSF8Wrtk6c99uS4sOf9QbGfxZjyvZ/V3mxO4
gSas/I6dFDc2Ht8JbkBMtmgy5PWCU81FYkk7PnvrYFQEPVc1abQLKFOHstMLNg/R+9yxnQew9uTo
Sw2t6cHZ84RJrdtn0GssHsUvJ/pvxh7oEVpmfDczuoyHcfoUXHYF4Hqe/ay91zxL30uViIfjTOE/
XKwn2tbx0StnAdaMHZHWfs9ZJoCopdJnK1sm4yXhNj+j6QnoV5C+CrlMm0QqzLg9N8+TsvXB5ccP
XxxV+cTzLhO5G949u/XmOcTDAr7XeCIPcTMXt1+qlTxatT1lsHC5zzdRP6EBr1dCHl419KMli6uN
auRJJx5bG6RsfAvFFXzH6TrdHxRiKqUv8DnX7eQbVlvoxCIMlGuBNGh+IbYIp7HL5tUMqnLmAe5t
EkzuPM+2ibwKPDrapHnU8b6eysQ+h/X0i/sb/G6O1piIBRFjmo5W5LhNbDP0KpiVioaRZOvvpf3h
cRhVwhglM7u9KutV+qFQmhBVia9//0IwI409LB7/Dm3yDIEEcSw7OyvaxhWvHtnYz5jZY9Ag3Vpo
5E9N8pVYhJ/z4moaD7DzY8MEW7hLPDDvELqqNBqHiXbbVZ6hRSUvVbuhVlRgLJXFNYdfGpFEpeJt
sRqyBERY02/wMTwOqbso5BC+51sJzWSitAPOwI/pV37bR2HyqX2zgtgvbz3rPoNdYVOlIFXz0lGK
3q/fQCK5viXo3glGu4TI0NMRUst3UFprtA5UekWIpPCmhpU6yvuVsCp1e23GfXGohGwS88oM/q6F
IKtBUSsD04uf/of7qwg4+DxZeAiTjrCJ/YT8Iipiafs1CIwkG0jpanqeWk2TjxU87Imk8jomdNEn
aTqxyKWYDDXFbhwN1fLu2gawuuTfOAZSxbTZllPNB/7S37GLlEnpvg8f5vx05k+DZkgCznzttQ5j
4w6wbfJRnOOKcLGsQKmX6FjNwnDREjybEbuTVlZEZRhHzM7dSeY+RzbDYKi2yqxnYxXaxosL1hfs
hxaAsILVtwWQMVmrJRC9BZdkvclQztnzijyZcW/37hoNxYFIQojmXh7/+bdjGqceniIL7lLsl/tl
7VDvK1hsj/jqAYwkpY1PN4isRvJssPt1NOmZDPZClxIF08vMMQifMTqx78ucLW5Nd4/4Me4cvJJH
YbD8QO2hNKZMt7mlk3M/PbT6Aq8Nt1R3KA+OJz1gtVCYsPjiervD9EMtOvLfT6KD+aTfAFpIXVz+
uAjPFlX5eKiX2JjSzUt4cf3TMknbM1Znqn37zqU5+2f1QA+YbsleSQUYlInSnqnhPkW0wGxiOtu6
XDEr+46KNljhHpVttBTgctVbEfj8qhVEWlgz3IzLj3tmIEsaWL1qL5uYFVPp9Sr7buvFtNmAh9ly
UhqkI1kLJWzNtWHv0uhlTcwBwetgYhEZzYJUAufwyKSnKqUUFxUWGcIzoqMKkNBxO8H9UB7YgTLs
JTIMZ7zXB4RDVfuJ7DuoYBUoy2Kj/TyuWK5WQXLrQn70uW8WTF1XCSC3NruInW+viJRD/pRuouLw
FnBGqdYJfdX7x0HR94MTor8Kh5hMTpeUOG1BD7ngGniTwGJOQLE4zydb6fZB1z+PgDKrjKSjy7AV
jSnQgmUjMhTvqXMGF+yy4IWJacdpNOpqIfw7shGfvjij6NbOmLilyEU85c80jxHelBJFFnRv7ole
GDkwv1oGyL4iNEzA0OpD8o37F6K24+Ly2vFx8Nlt+y7KZYYGh/PmQ0fmVybKVRQLNVQEublqil2W
fcfRYLZBPCEFARXya7xaH3fE4CWqLX7E9hvCgi7foNlMa2N++cNWGT2dASzxSWFiul6xwdhU6tzZ
j/JupatDe5plzS19Bjgac5Tts1zawWEMZ5d6EcnVyRHynH5KDwlsbPG05aFUwMBqji7I6jO7iUPV
UOnIew6jzy1EMdtiw5zz4/kQ0LCex85T7UfWjCiGltlaOUAGpLKzTr9Vp/NihDldJbwtv+YQyf1c
7fnXFiTTbRYpmXpOsphtGqoK4jWg/qiosJeUOPOracN136wSI+OMWJVjIhfD7IFUlo1Z1jIbGYEc
UljGel7qkWrWwEtoytdrGv/sJQff9bbDoVz+0RJzGEtupQi3mhqmnd7g2Xzlo6SWv3YupLNlrFah
F9A3skUIxZKgdoxp6WTD/9xL6X+kNa9fN8b8NByofzqwWwM/fn0X0gjbzp2/kkZwAjqddaL7wXgM
Lhwjr/t5mQjgZL7zNQPx9mnzhzH9f7BK7NALihrOnp0pAuh7//RIu6MVv91RHbNqRBi9vBu+m1Fa
A/jyrkkZpQFlUz/U0pQeBxRbNU8Zai/oCi2q5jvIzdatAiYnkdjbKila34idti1ZsIX4TX1gPYye
nwI7DkoWY7K1bB6cT5RYf61JXfaUJOe15B0rr6SKQQzLrWEipVh7iV0xI3+MRhBCh+c2rZql0kRo
r1UJ92MJ8aB09CJBl4aityBKtQgjlRynu52k657yq3LcrUXvCZH8eawlF6z+lYyt2wsWvuL/kqBy
M3f9jalxn/dTzRRtSFExokTH3NuN2sfGjuFg8GGHFbQqBs6gomC8wxZTEq1W5i85T3OGEFu/GvUg
0dqe6OSL9f6UgHSwGHCn5YDqx8sYs0YhTfT+xfkAzm8e4+kLojkEysiA2PQ2aBlfKv5YfTCUBuXg
EbDpqhccc85XqvlRT7P3qsBHBRns2JF4PViSHOxVGfKzFEl2iFTbmyNKW8ZvMYUjCf+gUG+W8Wgn
hdyCVfSeiUuqOCRSQuPoBw6Pfda35Ie1SdGyTZKN3Ww2D5QLNxF/2XmpxttLkmEqkYT6qfOKIgsG
ohlIbqt2UCjnDAGq0PKYKfbhl8sQW4g7FgoKbQLryR8JjjjHUw6R3gj5H13RcQXiDLopNiuL8NWW
yCznOBAXt7bpHy+GpAQQuzSFCghoOoBVpolOXp2SX9eiEpalEHVZKCuUJFELZuX0inAF1ZH8gkPt
KbSadVM5YBv29b9aXB1xXY/9IQCdn58Od9amMuvqKtd1LhVburB/OCb9tQclYw6J26YOTLEGKaZE
WC1i7qw6D4XTzO72oZL5y4vTZe93mWTuXkvtcpa4aZaFMYcowaRY/HUJA4ovFsEVQvisJw7enYtn
xcVVrRHe4X01T2nqFiCwSsEvcMHWBr3TNeWBkaP/PjuoeI5CPXVNbwCWCrciic7YjV7YabZzaUGx
x7w5KnuN9ChYEX10bhCXCTema9BvXPjGy3BQkhLXS90V6UIwylDq5zYTIJW3BxMORPNDoZ2oVyY+
z+aLADBATVDqAaVP4GBuwpfu4yU3iLRvrwKTu0xqkY1T0xsHnBjyHx8WCDKP5ACHXbgZ67WQ+zLH
1ZCsLLGRN91UysaNuBzLaNNbmEQBLBOnU3TNMCRWwRpWmgSxwX9NzLpYBKS1VXbeAvOFWZtbzprP
muEnP3AB5VUnf7W+6/r/uNPGSi4Bf1cUnI8vrjZRz+CuK3WSNbX46pOp8s4TJ7hv/XzsDO/xB57T
3UlzT4mqftwQkyhA0I1MxQVbMDGjs5mrqPF9gVdArJHCKPPPF7PVT2t0+UJlt39Mis8Osv08DMUI
QHgScEbKY5ofYAqAEsELcGvBi6svxYov+JO1kCPBzZGvNJEUeX4A8zlieQ3vG1YX8oNQiW3X1NjS
MblqgKtGsE9H/yezIHrQDXGGDLO338bWXpj3ZuzKydjgTjdBnfTBAKrzv1/HTh6WJ9m9FMehzXBk
NxVL9wU9h9z81Qj6qXyji1NqY+GNfFgrD6Msd8v2er38FJfpxECCQdcV+0yoQxuEKyG8Zxxvf4aF
adUVX+etUMwhBra/uHI60j0oFdJWr8sBhQCsSxYx2DJH6UG0OtReWNT2wfMgQGhUB/YOlUCKwztD
3EBd5F2f2fEmtqjxurFXfqEJeobjQOvSL55JnjUQlG2jk7U4OvrY28BIRG8L6cEYYdirtVAI4Agt
aSvCHsXXjcEDaW9NyD5CRB8WO8yRMpsRFCY+Nei3p9FCBJ0fcaztdEoteENhyWieWqEOJDZeVscy
0lqGGkjHbmYj5wxT24axpSKbMeCLQJUFHfzczUDK0j7/bDdwJNnoIrd0id8YujtMYpSW+k+G16/+
LeQ/GpupJhtYQ2cL0Touk09pXJ2I/sCDDJjG6lo+1mgtmSf7NEAcKK14icY8VhjJM4UtjB7LXcn2
pK4wn0j0gEEgh+dL+V3fdPitw3oGxvya3bZh/57iJOL4oemQeRrsO81sMrQBSntOKqWvgbXuD2+X
EdQ2mt1K86W34JKVvvt6i5BOwMDJtAulWn6TSn8ykb3TCbA4n0vb82X93efC6gVVQPc8uLpGTk2h
rWeMLpl0ihcBcRPg2zGmkofarmvV0Y7SzJvyiPYZMkrmRO2YbwYxmx8TSbaxWsjPZszr3XVq9LJv
ztFm66K9qcezCwm/78BwWChGVs/eB7e8L1bDEYcA2QFDQ4BYBlXt3P6Ks88i3udZ2KxV4jZtv9Cf
7KaljbvIxWQjKYXd043J3RgQibkU5Q9ss8w8S1B3opEKQxkKZ2Z9aPzgdztdp8DPqY2fcQ2LCQc8
3sn7SBs7gHruvXetpMtsxO4gBnxQUn4dKNd736o0cmj0G8p33TNYiZLWF0ZIt6jNaLXpoz4fOPPY
sJiUdsgGB3PF5vYfyA1ZOoyMpkEhcZ9LtNy0ajU19GdtWp9UhpmLw0E9A6zr/5lWEX16ZWDXvxXx
SursqTeY3B1aEQ8V0fWEsHI11MbOkezx4In2kPFn4VS1PuxJKSVwFLH2IeRfAd8m31SlRM0WWrut
d0LPfxe/MkozuAhaBm7IoxeWQnx9H4xBIKFYygEraKRgsx8juzKwWFXK3sB35/2dbHjs/xtbtCPm
hvjVEt6iWsnINAOO3oOsTA5+FxrJPckK8DP8JEwKtmlyne18ZdA2Bk+xlV0a/a+eSxx+RILqXLSH
Eh+4wNNj1eC4E7hsO5qb/gLHEzUPTGG2UDmLUAcCoU/508bcjyhuQt8eX8kILrJbRfEUxXsebvO8
+6QKfIcDjly7zlb2d95tQ1V0RpGhOVFZ7C9yyE/0d9tTwoC5bu9YX2/OtVa4qQ7ECN7LKcdVU28L
JscjUoNHVD1GEHhKXQcv8jRph3yNqgkZE+n5VO/d602DX3xtbttWQkEHggP7/eXpl5iDfXkNgojf
kXo7lT/UqKswzdOq3R74W5gO+0n/9OGkxeK5RAAi+i3JifFgASbf01S6Dg4oU3qz9l0fQEkYnAJe
IKOQ9uUq3Z/CPBqcMqLk9BWVcDNo8aTtQxQ/aogb/vCnULKXdbyCGHYD+FZXxfvxUX8oJL2VGLoc
5oBSmEm96Mx+BSj/ZmbrE1MAtlLjO1YwvCELYXGoHeCyq2pKdr+aRZR/MbW0vrheaj8kjD9orQ64
FlObkRPwqXot+e01o0w7gju6rUTRNS08j4+ZAA0DTLYtQwTQEFicCFUeAml6OXM/6mUoEYMXK7J4
Nngk8+7rcKDsvvjm6FJUD8HGlHeDCa14vY6YYSHrxDURtvNhlyjHMtb/uGjqukwq3KWYbnzwO23C
s9ndSZxuCFNel+QgEZ7HxtX0i5x7VCaTu/Hd/h3jHPgZe1doua6/Z0xkrB16QtAY8LaTVjE8SgcM
kcjwjAGxQ0gSweH+nrdKDD2RswlbvUTapfNMpzmAFa7FY/fth8u/g5X+nDkqSAJXsvK79VYgfinI
6p7kEDbdNuYlCoaO+W8RT5bMdYa9e1B93vP9Zg4hWHpBLZ3WJBqzUxILzLsGxuf/W+rRLB6FK3sC
KzVkfCnzmHhhgEbLhhQT4WQPPqD6fylh5o4UW8OZqjGDR0HUMGOtpBzx5JYWWzrEa+1e4/aTkYoo
gDbHKTTCesdm/3YYQcSB3tuD9LYmxhSJE5GDHSf1sXuFpGzdVU0h8B8WPe8aAUDxpFRWL4kzqVVW
FO+EnKbpm1Z1NdvP7k7FPJ9WW5ZSFwTPlKJLAHTmsVEFIgi7/EIxET94HPazKgbSOomqYjT9YvRX
DnAY7kOzQmGSW5iqZLX+H2m3gxEWdesVbEw4MYp0sHsMdZbSUygy8kkfNPksJdbOr0MFL96IEF2S
/wuRc91xOIw/4sC0I8tnVKap4NMvzKdBwJ1h7L7Kuzx+VW5skSsL31p6zfLxLnTeJUBDQaLJ9q6E
q5zCCYIcmoIQuAS/e6zT+dzC+exnCUguLeFB1oU8NGEUUkYnpybiOEXXI9NiAPbOtzSo1/5/g/5A
ud2xHRbQTrdqLCgzGazxQd0yiqRJ5BSbitQFcVHASHm8BnyrsUZrogkJV5IgYYmj+fx9OYpBqoRI
VFbqZ3jNWrYIxRYA/+LQV+9BVxIkmXwiFHgYlPW05p3lgoHhAqBv/O3vcnVD19Tvj4z1oEpvdTc2
Fn4Vk13bOo02k9KPKiBc99c0mtMBM0TFD1ztrw/5jpySTpj56l7N96pbWzD2xSObaHeLF5jKn6uP
sB/Q7HPyEL5VxSiHM9tcdZJKZ/kN9l9avDRVQJF4evusVkl05WGtk4xOc/WCyaOTDDQSwUC0KkR3
sCeBJqoKR/wc97w16WfHW7ACtBxyNTv5HNNxVauKu/76/xXm/+7LiubWMHKR3En51aoT8JAmUKcK
IDy8YTmrY+FcHmuQUZI+QWAFOl8hZjW6Cg982npoqJrKEyoCkvFOIe1QwiSsQjKNWrcfM800aE9W
ZrfOAuvaVc8mG6oQ6wQ1oApPBYvAt2zqOtjwLu7+D2Ibww3wtBoXmZ5ROnvC5xiSPb0edaNyTB2s
0lVV2LyyoED86rPFjORzuH1lOY+chhQ+EvlOXMGZrNSzwn3HrpVdfoiKIbRHmf1z8rovuZnmle0z
pi9N7BelRKViOhmKT7OtMMfMqbf6N/yO84W+AzDBKOFKuM6VCZFPNa4ZCjceh1QPbhEytj9pm/53
3OiT07XbK1NJ/vNUKZVeEmBb0PeV4EMo2pPVOXBmvp2gOH1i+R0+qb8YlNwGh9KcvknBta8rM+1t
6yt8tvVYuJiJe25xTAbM56JQvwzEfDr7UETGeZfmKM+XQo/I4CjU4OWGw5loIjYPWZIQL6vKaL3r
RZU55RCrgNtGBPkvtj9MXugnMzxMePfrfnMFj9pXvRgz+Ysr+7RgCesjNjrIuhpK2W+U6UMtZW8+
QVYg+YN5T66018JnnT9m+B/TXVhm35d1gnWWsg47+usFNE9sRvO408aAlJ1y7/D9xoUTVA6MKj7m
+QA8mE0wI+Pqk5pNmF9ap711l6qYDLzLFK1/QcOb5Ysj4+IWTo2U5D4Zhk5RQXPLgcWyn1VArKlR
KCGdC3m6esd1ZPOaW/dJ2KZlQUFLW8IlbtPdcpFkJ2ArK3n1dZE3ZjsQbjVO3jAhRnX2twnSMcmm
ZpydWSboutdwGa3mrN/ebdFv5VmfC+CBokcKCBVkosZ+M7yNMH/2UbihJrhGSJe0cE1pzNUwQqJH
+vYhPs7L2j/bb8t8eD3w5lTEISBMr0uJA+jCSaHOHm8twKg+WIYjUeU6ZYrEUDpt7VXopo1aZnJ4
t3hSVUl857ZoXPDkAzqDCeCVLEUEE4h9kKRvKI8zcyXcd8GyVmX5S37fr71/xd0SVUqbGWeSHUTr
sPNHTSGngt16B08Y/+hVq7O7m86abtw8rtcno4nE/RVM9h+U2y9Whfj2LTZpGAGbD53hphQ9zeop
qAKiUmpnyPkO+WDijGMWbvkIAn9OrqMNTzVtooqNcV0e9svz1JZszookTW3nTIo7/+AiU/aGV/62
9pthyfRyTjG5dqTGGYL8iJmV0OE0feAiIKcxAuTkUIzu7OlqTJqCDaIiywKHQ3ePIglbJ6707FqV
BckpLiFEOX9E4Bh9KJ/cDZqihPVbI84mHs4UvBgdli1BO8Vnh/KnuAf4UMcTe6UZrOclF49zRUhc
GifAqRHetK3PB1eOpGtlVxyCFe+GGE6o19IUzZ+wEmU5p/h8BU6eRu+RdrC6C4NJMRiBgn6YF4EG
AvvNRsm/x8Z47cPGgrMg2FOcXHLcEUuNu9Ksfh45CuK3xsKnzkS/2UjXUEMOxBgcsBLL/XWHvYAU
vpSVIUkB2IzBF95/h3DFTILrpbYOWnZ0lueFHln6BwQ/eFdkSGUQksR1ykA4LY5adYdn2J7iJYAl
+kL/tnvJflr3nBi2ZvJye38BahA3f3Velt6/+jiOrNwj7T+acm6l8ICrfjIRHzED1MNk/3VFpW9a
JpudofKyi5QmDTUE8+4hdm4f2kjn2DaoywQVIBkFZ337aNRaaVmhaPSv4Ir58d/XVuBTWj9wEwqz
lgeNA/3oURFfcIEE4615sNjsvxOhzLvFhrYZNATND7E7gnmW6/hRQsJ4O2rs7Z8ic6W5faXpWsLv
09eie8Ym/fnyqlnTB+43XUI6tPWIbgpaI/1olRHSoHiMbT2AhApONTf2LFdArJsiMejJ8oZaIv+d
0+n3IQXgD5ktXP3TBMh22ytpW2GEAaQZoPDc9SWTobArWlGDjrHahBhHoY3f+c+ltPM7qJSY5AcX
9YS3SeIJNY7/VVpuOgck8OVkWjdLp3pwOWsc7Ayuy1nrEAufNKCPps5UuXHzSs/jbSLU8cHkgPhE
1TEhZo6flr6a+7CzHRPCgpH0xRawfBpMRP6npj9osZeh/viXZU1B4KbWxn7wCd7AODAzH8cEBoi5
X2jdWZp0mpltF7HjwFlfJHXPTtYjRB3KEraSw85+aWCNwMtXq4kv+9fhS5zMvXUOITfnLLpfNB0F
4EfzqylWBAxspoxebg8sJ0EL2+TNPA57A5CW9UKhc+EsBzciF9tUr4VHq2xp84Sa6Olvt8o6CtAe
Aen399r66ogp0HFa5gnnyJo5yVAtlaloKYbBpAv62lsmb/+HRgXOpgVQbeyBboxk+xskOUWkfUIF
ZchruK+2Tb5e43vcWozRAbFCEq4G8E4NbAr3klWcnl+GZAieoh+DuFu0RNnwmtb2mVHO65aJLisy
K76su6FtWDPL1yPiNqZXJ0qNJ9rN5iaWbGpP02+WXZpxRvhAZs2esZiWpqtAxVkbUfA61CRv3bmF
lEWCozasimFIS0lQktm6XSTYlOoT8LexxyQchuhlKcpgJaiz0W2mSYvBjcfgOvnirw6WkvLw6rDb
MTGdg8R6Drja3n/rLcafBJrQbKNHQyWLNCDzqhKb6SNjkHYnHd9oqE/ibwWgdPWHdDr0YbBlST5s
LWD99pgoebLP5A2JY+k2uID0aHTQCtK2XdvSk4y5Kbyy8O4kHCwQ7SNyTAR7HkWsh7SbW6V0WAgj
Rj9ZAYrYGPZizY7AjdElBzrEgWH1Eaeb3dgqlbrpKmRzABUrCiKqOCSCsdVpA4p2AI3wGgFuxZZU
aa1YmYCHRZSRjkMCwgWLcg6L7vKu5tAVY5FUm6H+cq/mN33GXMXs/WU+5YwIxTyky/4JWPdXGQs8
nAOHoRxxymIOAPfusDnDNkCJxt6AP9d+lObB7xLx53GEvISosjVro9GaOD02J7PyHnJH/jN9UmAU
q27HmfApvFlMq8fA/iEoOGeeQgJTL+hfgK9d9WXVd3mttsa1q+TlqxAZVRjQ7zvk4vE68MQGKZvr
AbbfjguNvPNp8NYPw6PG1Nd18Xu5smrGSkssFqHskiDsakESJimKScCjUMMe+Tad4n/mqkyXcvNM
i1Lhlwk6OHypf6Dq5tVPXL3exo1gHKfOD4RRySRWogfoJE5dm3Dsxe+f4r1SD+G5oTyMCgS3WdQf
YZQf02bwPRIQhimGfDf/xR1LqkYOJo4LSKkJvtCxGistuCw6g6BtR/rAp6WXr6fbPjd6pkvZbfhF
0UtnjShP8wlEFSjrzbaCzyQSJ/DhTgfOwCFAgyrTlRfVr4+neY11oKKQmfTboJTLcMjOP0Nl6gI5
C4zdJKDlCyL8N3MmbpXApcGnRVY0ROaPET01iE34ZyQcQxw+didQquqg+NpRR5sWTnDWsveWNMOJ
gpVQTMp01RWyVleUj5krmZbpLqPUhFs7/F2WKZGASdx+g8sJiPsHohsIEN4CMGPy5TtvBrs5CqT0
WVltMEsSZ57dj/sytostX3FnBwXfdawMPscDiyuZX5sw4wB+ozoGAswJHlE08hZSLqpsls8kWS41
Uq5nRFgOxiMV1VMxEWl5vy5XrPSUW3Vua0oCiSroYq2h2PY2AQYucGPgTc2ps57kTEN3Yx+pQX6P
CTUVJ4CbrWvpa02f4F1lEvzEi+/y5vlfJHUyDO0ASLauiGKA0drY4WFn2YVG71qmcA/GcyhqUmaH
lhkqzGbYaADDaYXAK8khubDUdiTHfAH7bEaqQZoHsK8Gte+So3a8S/5nOtBfBidTFwRYotvE3ci7
q57nclDsPxYyD9BwsOjPnk46Yn4CrcJG4MLza4bFvDgtLnAYbzPZlP8MfK51UlG8CtYdf1q7pTB3
cWyD/4GTRoPBv13+a0KxERuaIwWrUeNbVMuNnC488zyIF3CqM8Z7gAZ7vdwJnEXoh6zo6ionYRYz
69opH7WokHIt0cJvco2MsYJNK6v9ppsfdprf1+fZ3lh+cIhR53ToQr8qx6+A/VXevlbZ51L/tdHD
PaYSF4AWLnR2tF/eAbI+K6kWgyETUP+Z9COZN7QYql6iXIGHC0upJZy2qJ8fdIdVG5M71oPIbUxd
qg5wO1KBhDOULwK+QvhPnwjr8UBLwVpfeblPeJvtl9It2hjeM7sASxNDVVccdRaPj7O/dspJh3ru
KRXDrEpnnbln6tBUxDunb2C6369/jiv9NMkAWHlpa5p4DtAmrw7ZHYfTTGsgkwuf3Z3KBjuu6VdY
i0guwtoU6T/LUP/IHhEPCgKbitGaNzyoyu0RhOPTvCc0pdQtOARqv4EPifKr48ZL2RMYpOsaSCnW
AcUG3ScRxysOqbRafATqOeRrnd0sQ4dL9dpLVf1HPQjfsuHWHYv6jekSVu9wVm/y2dA7bftEuF8g
OL5FPv7ZW04UtjHxM0bv2ldntQH5DNbGViNcodb4bMLgwVKhel8eeiIw/JU8m/2Bi8gcxIPlRyk/
JoQIVjYfssJLPDpjJGqpGuAtdMEKz+eWEhwu2d6DP1RQIRDVlGAOBcVnbWe2PRsAs0yhbkp3aS3p
kOfjCs6W4ObxlZ4aYuOXINmwg0NGbmRLEdrQPzYacVnNU3AmAkMR0quDHfgZwT5NKLP9s1Q+nIai
iPndw9yC9UqD1p12xYgJxDwYxRlr81nMcBfDghC4vRC4DipA97QEMgK1OZveEXVwdWdByNjp9Ftj
mhSVObPJH71YHZ7I/dB6c2ZUGU7lewMR/Q3d7LZDSCSJXdVBcbZSIRWjtvRpqm6bzOx7sr1wydy8
IBexdPLBHTm//++/we2dqYYnqYIQLyryieCp9BhWnEuBRhNYIG842hv9MlKyjzMOrsQZLoXMXSfA
rjffsq74mFm4KTk+oM3+In2nipmW81kP+NV3t/QeG19XFRfbVMlpRCB6Z95IBHC3rRsYE/iwMuyU
km41CX0z6epvP60Zm0YzhDu0tJ5wXtniTzlWI3qDJBnfV4T2vGwpzP7EHvYo3fLL7fkrlUv077Q5
2Ajj5KPgtUDDM/8jxXgU4473/1Bp5X/kHNMDHMVPnq63i5Y2ZbvjcD6c/KPFt+j6iWBM54kTk1oR
A142oJjrm4IO+QGBGHdAIHE2PJwm7016U8hkWTmtHg2xxe7FYxks5EwKN+couM9/KwNQl0j4PXAX
lKC16hdHOzbTEeLhHHGbrlvbWmnHHS/i+MxWhBJ3Zn76iyaSGqL4eWsntY9pac/i/z/7f99QW22d
5kgGNoTfbyqumRxD7bYFJVNZcj76Rj0syoyM+l5TYm75Url9eut0YlpxX5udnTQb5YraRFT42Q7Y
aovaYMDvP+9OcQm4v6iTnYZLSerGjsKU/NIHLIMiwaz/CyrBBQwgjt9nz+V9DWNqSknjYy6bsmQH
Xw/W5ctnB5sO7GlaIdmh9OkwLir8+aRU/juSuBjQxJnYVsUe33QTG0Xx/GYWafvx9KRgPV4z7d0I
LD2NwjzTatan7FTjeYG5C1x1fYUnrm6UzwE+cooJoPFxtFUUL1nz/bCBvPxhR0VLMMpt01fGn/Jp
JaejouklLFJQ5YVg2EddvidXu7+IGK3+pCQ4ENlJ39xCrpJL1V/7D3jjhWwkiEbF2S1SFxFvtxb7
+1K9viL+DBSvrAQlBxQjyOQmK68MYZlJsRqFoI03brB9nQZM+CsP2osynjHkGtw+8y8XI0CORj4B
XM3JVX4BbPRIOzrDcLOrwiAu22qZuyRw0lwENJkkVf6KXBin5jhojur1EVGofhh/5NZplOvjEMfH
Y2iplBRD2Z2zLMX3bcL/cleAPUaCHhtvpi8XhZOTtSfey2UWgLIDSWdeeN0+kMXQ2sV4PBXHb4Zs
en2JDjNSMpfbuNsayQXw4+9REFYlzWZCKoEB3lNL6zFMnPqKPr3hhuJTvhPnBCEEgfnlg3xnbnF0
OoqFxNVIrIbW4eLBrCfThLSqTldBzAYJfZtxNwk3kJ0L/Boh7Xo6k84/aAG/xxJQXpuIhh0wrXx9
37JNdyXAvJv5Ckja9scXEIWj6ACMs50Loy5G7pOxe9E3fI4XpLJ9GAjJUUFhKTAMye5slL1mHPos
2EgZzFXrkmwmYh+2IwtvBTkGQKie4qm60b9NNIKfEIuJLcXe/OdN3arBWaTRS3DoBQuqE7NyAva7
fVmoQCl6tmKJUNh7Hzs5Zu6TtmWkj1jOYPJAJEK2IDZZK+Bfev+Oqs3/IFYROuq7a92W3cldrsWR
eCMnfSX3V9OU3d+T1+8Yw63MGlpoZ+hvVVTheIOZMEzg2WfHHyOHcN1Wt2xYThUsAHLt7bI359MG
rfhDJGcml25PMbHTnbU/Paz24ZQTreR+3RWmDbHwozPPQtQObB0uLMY3XYJx5/OiyDc2/riaRb4t
bsgihpO/VzJjtrHPnGNgJIdKzAw97BZEnT0Gz4ziChM/C2asIkpw6rMV4LEeEi9n4xqUe49gx9gX
8iqxWSZY1cnX0l9URQfVxx58MWgbqd1gT4kRMsNtoPryx6AcJyUqNACE6ka8RdWH7ljrI+NqAhGY
CpDmLVHfeGA/waHYQLjGLMUZfcoFYEoZ7oMdcz2kGgmIMd3GBbOUV/p4rR7ImHuxOnqzoPnIh6Vh
5oPs+PO7UR5JuP45KX2olfUERLid5J1tc5tQ5t3+zL3Kr+2FyvDNtJLDRtwSWZPEHYJqpNAtBxvN
qJe5+8ipAGNtK7aCmjEO2cKbvfOkn0XMLwOVayKMlGLP6PzTAMTU1fNupS2A5yrunkw2shUescBM
70p+0K8JOgpvQT8FKN0yeKFkVYXRRnXQ+A4h6FyA1pholc3BM08T35mdUguqzXMr0B1y1PlaIdOR
Lbb/vw5DA4LSHgF9pvVowMMCsvR/bcZXcu+MCJVi2DSDWUy+o0cRkYbeLhpf4rkAsf0hmEgrSPCJ
BG4/yeD49KYPvqznOV1ypq4kWG5cRCNtpnL51PlbQusXDqHzOWFQIqAOKwgatSd4bMGgeBxv0BTH
Myk8Lk1RzH2jxzu1HxM7dqSisRocaOf1O8d0OgcI9hO40sX4vHIcRD/dAdFjYHIqugkg+TQX7pNO
kT2lHwz+HrvRgUvQFIjP5IsFD+dcncaQg4Q2FUmuAewViHoljZTw3+P9DlRxvYduRPoU/lUOi+JE
xywpeFLoQavWoucX0GZBPDXdML1GYXg3aEHa7m1UJsqehayOGxQ/6JaGwM9ma2zONNIp1mTxCiVR
Jo6jEgguyLSqKPoImUF+hKZ2gzs5Dps2cX5y47uwugCkTOoh8CO5PqEEdQs+yUhKMMXEHHmMDqm0
wTMmtcJEPpYfqfV755NcA8TZb/WgbDk851Mha7fypILiEiteY6cdbYj8m81BDTjIJ7pGAe5t04hF
bM7P9Q1vsytOOcdA0Tcc0A0cd/kd6OTYLovCw3jK3NGTEQ+fqeZB47U14Gf38fb56zNxI1tc6DIU
PuZWFgy0NfctjYIC7QZnu0uGB7o5nNU5MfhVXMf5piukOC4xhUUw68lVmMPqGT2Zx9aFE7v8kLz3
Lrxf/heD5WODiuilMcrRXyzRT3AM23mjXTEulnJdiMbmp0//raHYc5xS1FXrTOVfhJKrkqbrbf6d
tpAK4WsiNP9bfvTOVdMqBhstiH0hvYg5k3ju4g29SHeXO+Z7asqBWXLpZ1VUyx+FrtcptRoa2Uza
Jt4vXHgQvU9Fok137BHQP8tV7pmc+KgJ0sHk2dACUGMp4K2piijY0MPmsTAhE/n3fiVnryJ6OPyq
54hyuuJq3QXLVe3JwJ+sf2OEheqWbXglNLoyWNb/isbh4PZl7ogNVJmZy+BAFRJRHjDAfEe0Yl+C
TA+8XIgoS+XudfUWgctAjKErCsi0HSH1xkBcwfZrx3pkt3333FTBPBYJLX6TvkHCVOHeSksNeNMW
mZnyhj2d7T4fzAyA4X7JnVUBRLnKnMO1yVMw8Xy2B9zUvjXgkvDWE4T8sfnJO8j5Z/C/a19h3M+h
pcUSmgjLechFkXGbYttnecGVqhZXsPz/bsWcgQGve8yy/9K5YkTpbQwe7cg8euROa5QiupGWHkjk
8AugCFYWnePdySY+WTEZpQ43CC0ghMf7h8Qhaszsw6opWoHB+IyjK61+dn04+VQ4x5iczvkVgpeF
p8UaJthDYzsy6t20DOVQClQseQUCdU+w62j2beek7qQX8uUOIvQDjqhlqNi+RK1yJPnMkF9R8Zo7
B2fEz2vrFrDIKXv3v9l5xK33rivXjMBVW3aJmLZugl+1J5ffMXvn5rJEBEBajf7Z4cAjr2HrZUo4
DXKqe/krnTHmI5ZnwqpaeYL42TVB88NZ3TRzOvme/hK1IS2ZgNYYyYQc2XIn9ieAnRyw3umLHzhv
rPkW52cLpwMDotkzOgeyf+kaNytBZNmw5lWjDk7RnNQOlg2diHQzqz0Nt1GyL6i+sDuKSllx/CpW
4Gjm2upPaUS7LCeUIPL38/lN46cX6oSRkcrSiFTjviqtsWEtGLiGq6LnNSnUYdT1kW41hPPlCuQ6
0KumxQE6fTkoGvqSr68k9yEpD/VLutOBqEEf1m5KNVoKDL5UhnSNeWqEY1mGlRXFQJqex+Zi/rjd
OjetV7HrFJ+IoqIJV5QzhaE/aR+gj9t2zjEnQ/nsRufwFZ9acrya6/lXp64QlkZh+DxtectTnXAd
VbupA9DDb5snUPIaMwIsKpu8izED8SSnga5xoLp/zKoJx6bzjIUH8RXqPCBHa+/VIYMslQfPB/Ol
oqQD215xEygoJ9LsbTw/4gP65zTbK/N9TyGwpBeooEbPejtqu02TUqxjtyn1BVN+TEVUqZjpiR9k
/NjWJlNBWAGTDX3kbauvPVU6/tg10IuwErL9ZtjoEpKpaPJsKobY7I/hun7rcENmC7dM/numMjQ2
M5x/xiKEZxe5EdlIB51IK2PmEhPMZuU+cXJ3L/kJmzV625TmbersSthNJ5PqCVuxuxAlC0PYOmQe
jFmNWAie7+fLChxbSmhhA10WKe2aOScJJeVFvFz6z4lUnGcCVvkhEQUhwiUuvlqU/sROG9fF5bT/
jmIQyBeeu9Zga5JXzACaGxdDXYEMcPq9YqNGWI5055HKCBXAd+CtxTjY0kAgdazYgkjko7LZSPNJ
VuAAjzEwoTlN/lxe/eOPK43s3W1ZE1XDF2lZzJ/nn0+7ZnPXvvF/Kte5OPrp2Oje3guXyhEhZHSt
nF0DxmIdbncSiNatssFta9KbfvwxmbX+eOwrN0ZsI7Dukaf/OvsNYBqRx7B7CC/gHyjaCrDE1YAQ
NrpaW/ACULnle+6J3eau/Vox59yk1BHcUAVQf0dWv04sh444V9kp7T/PrCueExTF2EQGC0CnO0xI
jDsMDZ8EzTCSxDnzMQRmdmG9+kCQX7LGtfNrFGxwtvp1ZarKnqZCqZuFHxck5tGAMRQkLz+xYqzN
Ald6WWOR/YOLU6JLiZ+Xa3TxtsZ5LDsdsmrJLxtSn1VFw4EfEcVXHdqqdx1Tc/g3i7lDYHopYx5/
aYNt5dMJ34YxYvDWlhGiHPU68TegWpYq+oJh3WgvmwxinSqVn9gAb8IHdw9kZCZZf9Bdu+jFmtVU
lFOOgo3A1f6+awvMq/aholDRflJHYZaE/os2MWHUiF5Cdjy9v3WWWho/kReS0oXq6BAW1pdjy7/r
Ijo/OBSw/i+Dd2hPlJ2wr9wBKMcPkGsOtIzodj5nfi8zPFis8GJG/WPCt+zy9RK3hb+8jWKQChn0
SJ0LK4UJFoM6lfx1c69sR9iB6fUW7DjrzFrkdCJxRCEs3R84qvY1jHjZ+C60fPh80kDdqLEsORBw
7lukX+QpWUUATil7YJ1cNmvQwfS+8t84FopUqUIJqLxfLV/wNWURNcgnLWx0BkBIy7z4uO2xc6vR
odsVQ6kvDA2ghXzBIKS50f06tRRUmsWvxTykhUs0Y6Ot8sSA4uXSKNNB6z58xmx05u2EugnsnRay
0uVjYHDink3voDj+LnyVw0lR23fALJp/0k8NyCBjN4GvL/o6kyY2sZ3oKK1f6n9nWdp8rMVxFNL+
/J8tsTCbwELyQhhBGqLKwLy32ynRIeJWJFD/g+Ye9U7AQIbyVWWmQIktCG8VoWehcQcIYG+bES8t
CAN35dWpItJtsS96HqMkmvU3894bghYwtKDRQ6dvsrDaYYUHvdp4U+UornGC6FZ9p+d6ngBMWN/E
tfdrtQU8YJKX+OvFmZRNbOWskmVfCj4kkBCjQ9Esc3EZg00NEySkbiwV5cr1c360klYYdCt7Eu8R
6fiem+muCvdkj7vQVaXNN5EoX9wr2hMP5Mg0ih062N1UC4AiIhngahCzHQtnqp9qRrravexI5NGZ
SDbO46Se2WIU8EHvIuzg5DqWDobe0gukP6c6u99QKEwur2zrPOVXvGW5c7cGggeSC+NVEcouMOhH
4eaZyyZcM+d7BfliSuwZG+2/Rv/ba1b6/YifbrKF2T0z0KtbM2wdATFwcJVt0xUBjbtoAkqYIIgf
4APkinVffkKnW9vLvKCtVPDK/eWY3Kr/Y6ipX3pm7ha5yV31uhylxVNkgiVWhVOMggPPAH2+a53Y
v9fmEvvP1nlXiGc2KCCqBS+9JQch1QNF6l+griIinVL0lhpeTUWTXG9YpQB7IZGh511Ask8R/mzS
3SoN0zEuYKXGYBGWHCIr8rhd9WqOVTXWNawNR2W9l1FDOxpipecPvu2/+3poLMna/p39noKYAhzr
YBLQb/9IfIm++KiCrm9lkr3Qh7hKErmk5ScZGZUvrciDN3dRZxUZFOvViwsEvYHKp0y+Znsx08Pk
pk/6nuH5pvPlmQsLjdrfhHtylDOOgTKJ+AWh9Qj7MEwPXFwOUSUH1xzISOi+8CTCct0KlB9lMaUX
gAxkN5HdHc+kBDCKzrnWENibdjX3gUeGnr+qs9zzymYpcqt9BdAge9+zWKfYSzgsqQWKvH7xV7/E
o7YiIf1m1xUEL1rmH0Oy9QRW4l5z3aUw4sDifkQRgLqN40EQwISIZtXWwddmF0dh1QhlBsqo+8cc
QvzRobFSheL68WIK/nfsj2a1MFORU7f3fXjwdEgfBbWuNhdRil/R9txTuzA28VtPWuBtvIFrWN0q
0lzhLZdkRQ5UFhnVaFLsSto49FHOInxR8XP4Ro+x4QzuMQRKjW9T/PwqZWYKMUSA4HzpOs9ucnD+
R6Ygx68eMiXGG48F34QtJTV2GHXwX/22wPATH4PPYUj5OXcJHgxktLvbowO1smSKCpJecZdH/c1/
xHw09UPZN+7uys+cHlQPVNUOrWJyfI7qRaEJhaLQUeKxucLQEcHK+SU8fzfEeK6Wa59+xJgFNQDg
+Qb/rTLiXJPXICS3Xg1LVIR5gpkw0kBWhq0lB1o1hL86vJD3CHIoHLjxrFUXG7Uv3Luelkq8g4yF
ma39BLV0N2nHnOCZ7jv+5tctZS7EjeNtoH4lxx0Cor/L+GAM5GqYYAIC7R29/MgfkOnn0PjM9eyn
i/yp3eW8dfEuE4HsRYFIHHhKHof1xJLzV6ffrwNyiYhx5gaoN0y95PJ2cUTrLM9TQPGkcce6mYek
cK6q2Gu1IZzZetWiRXa8gIMSY2G2DjRMhBtO4TOmqlNuX4CS+opC2IhVH2iCtuC/4EplSKdiwiVD
Px2dUMLdVsdN77NGQ6gtAw2lX1ny2rKqzXG/MkfEeJVIseK6iMQkKr+FWs6f3XjyMLfGqx1SPD3D
yengPEnDjvcPvVkvIGF3h8Pud2YDNYXU9uqyYQNP32MfCHf00Bs6OHOUvqJmX1fZzVczRyqD2d2Q
JoFD09b67RRZzGzI0wJO1/DD8Khb3dKgrXCppHSsJS+NO/zpMs33pMhT/BwjFqKbtJUmJYrkDO7o
aeuQrzcI0FKFustDJsUnILW6NkfF4ntiZl9h/Bmn3HVZB0OGzZvPcvqj57ID1/YJjECUy5smMFqC
Am3Ago15eblKSaJ5s14f5kSvwSwBRXcpbTLm0/E+2XDa6YCB1yf6eTRZbsZh6KSRT+C+lHif2THA
kde3nuHYvnYTv0muvAHpUnRBMVMPI+RM5anz5H5cL7bcr25P1bXInaySHcxjaUchMOXm/SPT5jbm
evxYHglvVKvKG85UKqqM/o4zivdIHqdyYOwbKb3hh0FomxAz+DMKcsdZqvY2/Fl99pic7B2d08uG
v5Fug8hy0MJjDdhUjQlLZAe782kgVxSThnhzJz2a6GooZFlbxoI1U7GHaqZheZu58E5OFxx1KoLb
c3VU6DewRyvo4soRWtxTLy4uBsN1XRoJvKzDb8hM4BPNJZb+F77XUCWkFSeyOop2ZVtV9UvNoema
2nd34Nd+C160XjOT2c8NPuUG/b1bUVuI+dp0YJr9Aybb5yvnDRUSGs2+PhrhiCeuxyaXnaIUPcvD
oH1BVVlXS7LxqUh8hGLUvbY0N6X5nTfHrBDLcTOBlHgwEannpbU6jVI2P97ScS9/RFcwi4u/ey0f
nUPt9fnVcb3U0pFWTDngAyMfAAoB5YsskgBY+2e9ILcz5CIILw8zOVqG1V1fvSiDdh70PtlKx3xt
ogwk3PyjlIUUfM3ksfXbdDgwgYCk022BNa906nJaBtyYCxpH0s0w6mh07fY73HOpLEqvJLdr1Qaq
Dydsv/STPudh4Mzp1CscjwO56JAfmkMSv+G9310X9KApMrZxC06yS+a4Bi7qmj18h1s7V6CHYwJM
jDZAigHTIkKdGEz4y6qAdQPHslZjg3Kyl1LZVi2IFvMAR45Y0jKGzYzHJbn8I2lK5CZLecQagmvO
WNhxt5JMRFICTm+X4Ak5jc8MwgzY1i6AO6ZkynaHKErvOCVs/bolXNkNcyOyO99QziA1ycdvH093
2EmeeIweei59MqSuqpSxFyNEaM6ZlWWUM3fSeGansO9Y08SxivRzamdUdo4Cw179f20dONrngDsu
6u73uYDu55UbByUsttedKzQtNr4A3JEdwzjRmCKgbPXtzqtUCQDLiqBQfawZE4W7u+3DR8PO0ZnU
QtBvszhqHhS1fDzUl9nT2WAj3arHBpkrYVayHBX9qjmTGXv6QaBoxR3SPq7upCnXjRB03J+yhYzA
iI+DCy0gkC6hrGR8XtmOpbVhqf63TpXXsUhSct/tZhIq+BROFTl4YmNw/Ozhl4iftSr3Z+DdkKTZ
v6An1AZxZguVSBpHQGeLnq8JYUym0nj1gBcy0sKUZBGtg9Yda1U6A/bzIF+UDVFtpbZY/6VVH/ef
/GFJyVmQOwFZJCtTm5ifevPIaX51PN9KtBGSvCr+HTO/Kdp0ScW0xSzdc4Kq9+0HAZBuP7tycxyW
5RHrRRr/3k+WbMUzVV/4Uhme0M43lDu6xJbWCeMwhqJmMra9TShtUMaBf5ubCABIlTSl74VVCnoD
9cKmyws1CV/IbpEezwmI8qm3qt80ybx98inWcJlgGaaZt/E/Z8NFmKLciwwskEiMisVRwNFs/24f
mGr/8M/6aRjqtS/rLKAfB92G9pt4JfjVN9bh2rXmifHPCq+blSPP3+WGJzR4uC850AwxNO4XrYq1
O1mWXk7Utq83IamSTg/wQ7EnxJcDKJQq2fquo5RLYED9BWCNcd6flV6RsEuBflc6jfI8HynynhVP
8eTr8uO4vmbmC58SwlsN1wSsU+vHWyBHjFTaVHJdIKlId/cZ1iyC08a0pRhFozBqBU/vItl0yFsl
sy+rUW9qDtxIT8MAbHPXFNGq2mjWSeclT9sw6mBiRghE7nX4coeK7Kr2ffDli3HKdT4vBa0A2RS8
eg1GdUXnf4Q4yqUejEhOP3xZLk+4CVwGfXg/a5OvZNpFRV9eNORe8F813fBCbFzsVBBsIi4IfjlM
v1hWzAeE4Zm6xSLltweNIu2hzXM8u3e4Fy7Vec18FTbML9fUCt6In+QfJHYQDAIg/m8RlTn2xPra
ubW2MZ6rmU5tik71aaJCKfYki8g+ZaCQ6WknagRPMxI/jSOW+JVPIxQ7ZnR8LFSaT2b4/YTb6ODc
7GkcZOzHUAZ3Rb56jLQSFj+yUz1xqYea4lk+mJhOR5g8aH+YPVAcb60ROaD8d6sNsGSzHAseyJZF
QrDnTSPV3E8j1opeaul7Ec8VNfRwPLHukXzho9EVCczC1V5tvW8VpEmYEhcRXO4AL+5VwZ5idX28
QeE7r9umcRoWp9/NAeSrEvPMR/jYZ2ZR+/4BEJyNIofM9nX0UM5WNiazYNrPT4HZNtcHn10AdiGv
kSg1u5geS6Hi/5kMSsvfvZbEvK7flfMVeLzi0UgNj3ozEMzkqAFerlfDwvwGSJ7QafWq0XJLBjGw
AWsT4fTwra9+rCeEyGel3IkdvWB+gk6VQny07HG7K4P0GQ5uqOMP8h5fUgYFQ5tjvfNRSFKu2Hl1
TAL7NXoDLgoijXyXxp1dNcN7g7yPZvwRZ4/jS53jnL297QwcxD16GNcMXb7C+pKCStAOHY3PjdEz
vNGGfk45XaRxI2CWb0oBpqdeubNHkaYKkCJpM84A7nYOtA6eeiV1CyzAOnLpPJWDQ1BC0+ihLcD6
s72OUM+SrfiBgKyI5x1v+Ql+hV6EisW+UMoYR2TWcgIzwzYWkrnvNyNMoFcWpyXaU8egfpOEZskQ
I2XU2CzVfB55wdevBRW4mCpeqXttaYYa1dKzXSgjNi29HmW0K6GkvZq+sRXUZMHGKHbbMeflarhs
4m9rdpNgJg0XXlQHcqODUUBnhoKxRF3AuEevFU9WBqyjbNK//Ce9mw76zdrZl0ahWgNgTL7fycd9
xKGS9aWay0Ydl9hLF68A2EMCzSELAGH6VS6dIxrhkOQDouvg8SgKgx+86qR0dvbBZAIdHp7BTWHP
JgJPR9q1aFoNSKVUrWhrNiJg7cGzWIYpx5eSYmM1tdH9vqxNwCZq1lnyenNjJZWcB/Cpxsq4vJUZ
o08SSEmiUpmar4ayFqW47GOAoMDtdBZDNQIlZkuFduFJFdm1CGCQoNsCJuVbngc184HF0w3nC2h2
CGF4Vfaz3wPdUOfCXagUOzgOGACQeoaaJgLEeXe9PQ+xKm17zYV7SodPJHZV4LMJNOsbyZFf1p/C
MKGa8w5iDvt58OfHgEX/f/Iun78fO2hLByNOvoKPR6ynMhG640KtapwmdyiG1BRoBNsBU67Rw6oA
fCBYgeisgA0ptmsvpMOtsvYgcERprQXXGBP7do1JDrds65aixUqfWztwlMts1cDA2518CRh+k25r
nlQwdkdm69gJzBIaq+OM1saz5OCkFaZWqsrPqvLvVHEENzSw3Y03YuHKwuMNUK6sR4aRv+rZ88ky
R0WDPa5aBe+6R24lWmu5jushR3YKNeir5IeyoMRELnFdDB9+6f7noNlyY4BkMfqm2+0Ukqu+ETrC
i7GHGhU223bCBj0CtnJ1ZWuEsKOnore5sJ57TyEaJYcn0f/zaDUuYkcZrCvQbTSjwOdjkBEhZO0p
SnHnb2ICHaJHnvrr0LF706Yq/Z6RSmZVuFQrEPgCkVkSmx5lILL1nQuxRGgvL0QcDUJNTs2fFNX7
khthQ0CHVyaGBt+J/tpuLguhtQhJ5pBPEFtBo3uSADAyXSscZtwkBOzF3r/MthhffBn2qo1lB1hw
47UF590YYvZk8/j+3mlQLlG1BLL3oiMNAljMHixWWc6RT6bN1WQmvtYF8zuMgcBI5tmmMEfGCtji
sMXeDbuGCKmL73/HCzgiKFAyyMm6iqjWtrbw9y11tWjSifTk+d+0wkQYIdnp/t9lmePchB1r3iRt
Z123Vo9dzDCwrVURJDPgBqSXHzdLSAQOEbc69LREXl7QUkFSUMDNb9UOE7beGpVSMhRwYFZkDuGN
HPYQ7G1+XxqaGl08CmXxW8FfpzVyRLIjRRpZtWRIxa3XI1zrxPSV3Bl9CkK6eKAvd3fr+RFARC+G
8MyJfXwT0yd7CaGzeirpR0G8VIHwSmxlrbf6z29qFFLDm4SDeUMqrwH8mxRybH/PWHXcE1bb1qpu
Hs7P53otaMPDQ6nIPcCzTb7a7eaNTMHcxpL9bwMkBHrT2G8Spqbb8DKHLr3g275kgGXi6JLyiyY8
pv8McIxqbEHLycOyF2abeoOJ9DVO+SccIp0LxJgRs+ioD2Kgovrzk+WisLe2+104D74QIBu1LxVL
ga6rRkUCJKkalcr3RdLM6xJ+PtYff2wikAA4P4SINj0R4u1RU+Bggs/J2fwz8FeVTZyj8SEf0f3D
FBTWayTP+X3MtFX184FznBsl1Z3q6J6d2NwA+5OxOUFIcPtrgqT7gGGEwYmoq9UNJbiWr7T2PbQY
0xnY7ZKK6kURGlATJqRobgaUxYQSdxGgh2YfRMp85exIuKDjrb2a+aNy2bVa5HiboLCj9TkrF3N4
zPYfpn8D+ziVK8erM+bHxQMVZynvp2Bp/59jRHxVCLIh3YdQySe4EzORWLu2BfphMt3ymhBvlnrR
GcJizmWKmExUm+5nn8FWc7q675n9NHr8EhvDxqcLPq0h6zEN1lK23L/IQ2knDqJRquxXwqtHpmUe
pKxywQGSosyFRRSU3mDUmxZ9cnpVnuChP+dxYjHMcobHSBDFiStwaJIuoCoLXQQ4gmQxA8MXEbPo
226Gqrx1IbiE0MFvLtT2HTd4720s3ByJRohy+U3xMfm4ErNeehLMcBrKCPUHDHZ+HF2iimLaIG2R
eB1VfVsJRW8SPHmB8z5rh5ZW9xU1bY91mk4cm4Wx40PgWWzj+Pc6majcZIA1sZiARPwKD0K0erUU
+Ve2l3AyHIamoJwPgb4GO1DCJ8I0GluqIT2qpkk1tYbrQAmWa6ujF3PbezSERsH0asfFFsi86AST
Uyydvij1JJnro8PiM5orqqE8ACD8wtLL2Jh2YLvjFjxAK4txYWxOCTwriwa01QN1iOvjEpF62rrJ
l2t+92aklhfJF5fVoJ9m8SOULdje3tSuFn6KrGIvQgVAUbkvWhAhjBIxBYI2QeGFLMhqIYv+AL+y
PXNothPdmTOLZsXYsXApGaaq632p/xfwBeoFhnyR8oQiyZbE7ZElWCJFPNvGXhDb9G4GCOLIJls0
T6VLYoAq2YREvSPv74i177b06/yuYmxY/o28CEy6ah+8RKrmkExsjMktlJJK9tJ6c2aOYnjMNfS7
Y/YqKHPqdv8cDL13Hl6nKSmRc14jvz8ghlpBZYwG3qOOPG6NogLYujMsNRaz1OIOo07ia38XNQxc
ZBBspxBR+WgsooAjEV+jL8RsLjJozgpMwa0QyfIz1c3dsqGs9amCJhKtPOiLlHDt0C354sl2ouwZ
0ETAJH1GmJ8xMToJ3K/hOAaPLaNkQZxovk64j3xdNJOfkLXo4FJYUNyeojK4yLK+sGjgcbdMnUc5
3LP5gnaTjNtiTRDBi73cpcvoFxR0WH9Wx8QxnyYZbR0lfEtl/iV+ZvuZsdFhyHl9786meZ1DzbHp
Icw1IgaYQI/0qoWY8s/tfw8662RePu409Uxg0eJfdRy5r7jIjlC7J1Hnm1QsI1i3PAujii4yg0L1
H+vLcxX5UJneMY8Ob15qXUs1w2luYuvrmmzHPMA4OlQeoOfrwjcRYvF5ceWnPx/6Ng99CmJS8BUs
xqPRzTVoo6PnoMiUarCfWrIeLQ871+8X9JLQicYH9UaRImPaVE3ts95jAbUOEaJx1Qq/yvhslVXv
E+Xp5NsYYp8oIuvn2bnjBU1JehxujrFHDlsMWXLmvGm1eUxT7BnuSZcdbwYelClUGc57qTRgOWuM
jq0VH7cDA5ieAxdAfArAaBDThsVa8b2CZoQjuje+gkoe9eqnExF6hD6nmnb04BbdFQWWLsquGcar
cahAN03WTNN8muxZJ5ZYV1M1OBZNWG2BMCs/p/e7cX5h3Q+x9hRJVg77Fr7gbSHAGihnWWjqkDWw
CnOxxoIlKXKL35qUJQ2z7EFOUliMUayEX9bkRhRive1Z6d1drNiiZtP9OzMXQhGv0CmlLASYpq4b
4VMgqgUpxY0rlmhI81hc97kPfOdtcOv4AuNtlFxxbetarSCarCidPesoJGQVzFf795zTpD6gguX0
xELjcqn6f3/PHW47QexwW0n0bMjfHzAm8WFMCoZ8x1WzPxQdNy6/X5OqPy23eD+WjY7ONXWnFSXf
q7fIRcfoxJeEk/6Ck0YJ+2fS99Rs3MxM/TF26aN78JnjDUx1gRaIQhQo39yv9oswp5zOLiZCQrtq
sLXL32qAjv6dwG4Y6bIswKKVX/bSRbwryKHK1tBBHP02YVwyLZ8crKUFDDA2BRKxYuKyjXzd8vuC
bBwr+A94ylN/FIR7TF0EX377RdApnMhsbAW2aL2HZK9odKVhAzD6+M80W7NAGd7apJ0t4nUOovLL
dpa7NZ1FTrZjZIgqAIQeGsz5K7VTnJygwbVsUZYa+7vDBGQUK6ZVdgGmBbYS3IYtFFTjy03AGuAe
uZzic/Lthv3MZlzephwlPgLcmNAWzt95eP4ycAfTFqUV/YAXL4CGwPUVQzfvQj0F5U6XPoFFS27g
yH0o9na4qzqDz17gN2kAT6YbyK7pc8H5P1B+LOntlieA0WmdkH9q/89KX+7rq5n5pZSvdGsVLkNj
o3Vd13VE6SKSPeusq2K6eWJKQUYxhetDVspIoA7SF17jV4RfA0xF8SBhlfFn0sTApEgYyMD9pdFl
9R1+5y+0CTH6EgJTijBlHhyFU53t/uMPGHFQa9uSZP9+NLmoxovcnJExmqbBLuubV2teZMc9CwZ5
oOo8hGfQT8recAu0+U5f3c6opsa1OH40dK7246lZbP6ADbLP1S8OrPZqZO0VRiI7UWNVO3nT6HG2
FBZtehkWoF4o6/YggdReyXfhWiuUraC7z3pRGGNY21M3k1RUTBgAmVWQbnsM6ni7GPYv2t17pRii
ke2bWoawzKlqnvwYNDUC+FNL/48WK/9YxAEYJZGFmaqBkMle03zTtXcwquEsHte8cBeUaGKFmg9P
5MDr83ZEjqcFM8aXUDv0yPHQZIJw7ZyF8PZ4ZywSkGLfNhw9Kd5LMRyAlUeJvLugNZFDatDJo0uE
9wmSnSHxzUlhn8hRXqLGV5YzVPS3Nbr4MaV62m4LO/DqSox8cCo9+e564qS2hb7zKX55sdTRW65B
KzVHiMbgD650r6rvPROA9igQhef6mrrATT/wTb+A7JzEv6M9ZJWEQ1sfSpxPZ9Cqk21oDkWgYIzm
JcyzAFSDAKDVOCOy6f3n58O+/wexInkQ4byavLNCwKx/4RpiAhdsKAc4pCQV6V3cWrL7vjJhJ7wr
t6yesikhHdF0ulcYZXP8YNCLhJVMWM7eUjaeuVxosahBZM3y4/vwlARAArxZ3spuUHtg3zzB1wrE
IB/415O2DU4jLaHeREThiKdc+QppU6OwV/CnwAUGamcWk+e8ZnYjM6mZBLQQSxqw+oIbGAZyGj82
JUEjFAd3Nw0ulN7ykvvd/cu+1+zpoCyRMEMEd3hppNmZ+MTfWpsUHrNeP9xE6YEGETVs7bdu6cY/
M7fMkIyMhOubUKfbVWk1s7LN8gOmB5bqRiIAJSVMv9o46h+rIPVmr79Fdj4rtEU1WUg6DgxH5E4G
1KGuR5H67SgtUEdB1OjX254wgD9VDsfmtZ+G0w5i/17tX2TeyRqUQ55qyUIYlCLAk1ilSRs4BZgT
6PXFBfJ2TBp/Z2Ybo3MLRUJ5yjA+ABCmX/vtc5AR71zYlPKlt+ZjU5E72jJtdD/gcLBj/MvQonwR
VOSRi9fAn2PE6w3fsda2A6IfPNysTEaiA1LWYu/d6JOrNC3eeRNcFYnyPBOrwavGSAFUOGd7VbiI
FJNSP9wPQZxLEIumcopQ7sAt0BzHNQ4POTr6sXG0S0C2NAK5Nfdwnb8y8azsRM5GzpPwr0+1DN+G
allcvc/GfDt7t1isH8DhbAIpzhL6ZfjkVDVmB3ENv9RW9P2hLZN5HlYnJhnRWwAKDOmDSwgy6ZUZ
YaREx1VCATLPXTWZ7pcUEI+VVX9PQp/PH9amROq+2C3X4X9YDK9x3kzC8M+wpMpwQxtU9gqB3c7D
ckXu8BbxTTYkfViqtL1vKg/lRX18sQXtTVIZcz+4BccNOM6MRszVeqnglJIwi/EQ09fRwqlwuNHc
UVTc5/A+jpM+IqjPesnOVOWxSjAzLm3asP8jmn7b+ffFH80bomjbQ+eJhy+GgtAGu3WEQVtpXsCp
9iKNHwxZ91ZbOb8RblMKAU1qdhu+weEyxfcURCaJfF56z+YsASVLzFgT6UPKPDh1b+d8PIc0bJQy
A33Tyte1WWE0KzggbsMWjmtChCUjZODQR5j9cx7sMvv3LBG3CCfxoWqIsJ7kkVzc8cTMjfPxoKWq
URQytRcd+OFHi7mvEVck6xsrdW4CJqJASgDU7DQs6R8LQ1PGdjNYPZwHGHLX1a8k3FLLrT6Dz0YZ
r+pM91FPcRjgK1CY2Q2h067xrRF4Kz/r8o2OQB0ytkW+KjE+v9yN63PzZbvEFkzlaW5uRhEw4kKE
JSTf16hMJERcoj+iJF97NL2z6hwYALceZYnzFcVHaBAdssViHm2rQkbpVRQhi3P9X/JodXOU1Yhl
ycBxIcpp9nnfQ5h2L3dTQqOOGX5KqfukjcefFXCsvWbh5KVmvXaiEmeHe5s/O09HwFl6Ki21WJBm
Psf/QsmdLIE4Qu7JRn0dHsg7vZSFwUp7sFh7yl86Qqw9Yyn9yLJIJjCEbF8RE93no8bTFapcwvWw
qYP2FOJWWPFBjxOF/7nTSya+IcBVypKAS/WtFvRjmtkKEqv8hGiJq0bNgBDKlqz9+hbaTilQ0zOr
9hmD1QbmgHscNMRg/V/syYyLEhVXnSLSvMm+nDvNGL/xVsiZnIvwlUcg/efEWlC6PxMYBSF6JaOI
x76nTgD37FZ6xc2ysJPt/vxnv/DNKkErhvb06du1Z+6E9Pk0EiUHUWjcmU45TF5EcILRNUauRh+x
tp2bYTlKaKH6KjZ3IWyZvvwCxldVOxY0zwSzHKSMDGrA/W9fkuF6GiJQSjRtVi018knX5SqLCgeC
Op7AGMUuopB0U0kQgWTcG26X0UnacLFHwtV9hezwj1ACWZviiVieOV6IDOE6BUVMMM1a+LnlhJTy
Pop17UAhB9hgXJyJgXv7BCw87O2rSTe0j5jjou08n13XTmEcIrwVECNRGdFOUkRzRrvuWAKqmbV/
4r6dgIGyYUw9mFDPNWrkO+9zTi1MdsOrL29LT34xFvXPQ9ycGStqEXzR+Ad5tu9T2e5NfmKiuQmF
OjPBKknEJaeBGp29H4iODKYPiR6aouwMDrdt+nQNN9iCSSFa7jcVF2kxQsXCOyxfaSyo6jWldQ1U
XDcVGpIHjEGLAUJ2x20k1eivJ8Fx2CeE4ii80+GJB3ZWb83N+B3eQU6hdKybVJ7aepqJTtRdQERq
MUjBh0Ne6PNo1bwq9BrfWpHOcAPC2XHqJtR1mHb1tDLPqUcWqgRMLNZ9P0jH8v6e6SNi1XF+Ec40
43CF0o4VOH3EHzYuCQDZbP+lzhALC30lyxWEKj0ODnx6ZWU3E7/SQwc+N/w3T5OaKaNojFP9BpX+
cDgkr7JhEBTCIbt2stn4xLIGnF1xDKp0PnmJ6w5B7YwG4RFL6TQgod/EjKpXrmsNEM/59Kw8+/ij
3QZRTlDAH1Z8U0UvbDd32dx221ofw38g23QFKnDss4ZbXIyG857HPyqDSl5lJl3vAcE3yVcU4Ian
+PCaB1NxjDU7jtMc6ZcvAhm0aMfuezgT2B/gs2ZFa3eiiESlKD11RruIilhtUMrBxroTkpDaqjMT
bMSp6p+JI9laYTBXk4O4yVv+XqEkc3iu+Yj6j3dj9FLhLsDV0WRgbvWH5LJXTXcyk7kKMU4c11ym
9QnNPdXVNkBPmKhqkipwYO6wuNzLZJVBpPv47h5FSAjdjonXNrzOL5rMAql2u9YYuYYyCj+2S2nT
smHJhLtAHkbbpfFataRlnyJGq/g3sMs7oU/AnTpq4GjsRbTqB5DA3PankcmrQMXwgv2I4uhPfc9P
beToGLUICv7Sm5ejhc0jItOBnWsJyomp3GlN4312RyeZUZ+tV0c2nKkby25wgjT/jhgGpP4imbbc
5fZJK6NI2y+pLQm0HHGtjzL8G69qeUwBz4nuSaC/BsSgowP9RN3fWdE7D6YLlccjbPpA+1EFL5Qz
3KlLj9Pegzs2E1qik75dGtGN8FJI194yHrbmoMKMoAV+Er8FVjTBQKJQteRAxs4tgmi8fPZH65p6
0qERtQ5lNcMuJorz30ByC0ebBK42Mp8R1A6/JLGPYviUa7PUcU1T0AW8Y2WvHFHvKmuulVUmG6GS
fT/ddYKvfsuMGTVi047SITngkpqOjKaOghrC+1vbun+zKXTHFHcdtdCAfz68zFT9mvbYVyQ6w+/0
O8oy5gkwjuX2RpuPGk/lCGlgoYCNANRJucRRXo0J7d4f/RCjhmouLbBitBzj04oGs/Hm9F32lFip
ItofqigWkoPHUudRZvpaFfSeNTYSBGsf2uBs6U2c8zR5FyfDopJ9f40eqnecnUOgXXs+lnCm6W06
forJJWgJ3vnJUK86qh9twUCzyToVQtB/V3fmW2/bl0V8LNeGhFC8IHZJrC/1q6RDCjHmPIOJQfbx
KgAhcgG10Y6xLHqLvRnboWR+b7aDwJa9mJOW620jwxWJgaWj1OpWuqty5R3iEuHLYIxrHts0dOjw
6ibn5zckoewfcw9zNPySb7QayG8AqWQy+DijxTnewq6+EEO4PGUjthClNwDo++gXmPeNPIF5/kbq
bzHWQnt9sL7M5oIma7EGZ5XJ/c7CQwFOiH6hhqJkwvxhHSwwg+te3i5GeI9fzopApjd1s6dsyQv6
fIuqXCUovFzK+MyYhTqrJ4BmrNU/oqyS2vIg+8e1q31G0hmWRSA0SOTMST3aZ5G+9xb5cixQeHS+
MT7ncrMs9Rn2W3gjSvP7xSGvaGvdtyoC7bTZ/7I/DdojoLsum1iJipPDQc8AlkCJy5YGLJPBtBCc
KMnjrFdFKSj6d6L4Y/u6eo4lIl/5sMEvVV5mN+HV0KE/AIbAfkZZRUk2Gff2kwgcgEpZ8rcMZ5sW
CD7rDgTgRs8az5hKdCSvh4Qwd2kZKJ8ewjXO0d+2jVqlnfDheUHk6WIeW7QMks4LMfkG5x79TBWV
r7MPsb8lYLYg/jUiNET/lcEn7CPLyVFNZqzhTaOAkHZYFBHbWba0cz+h3dPO3prhuEuZ70L93qlI
mIbYoaQDERUdO0xBK1twDRlkds4aLdVMLv3EngF+/25X42GaN5YbQUQgzb3NdGXKpP+lGMMW4KPz
hEa2Iovd6hfX5PQZyGkZ+9kaTJ3aZ7N58wx6/ZcHbJSqhIT1hV+OlcrxRXNEU64gw/ZaCqsSTYer
VF4hZcVXgRrqrx7OvyLiYo/J8RfV+CsxVmteIvbgaVi2yPUK9nf4PMn8ehdcPnM8HVfjIrFmh6bD
5Fn+YK9dAu0HyInNQkW+O4/emYKkO7sAr9mfxq+ix6F4PRvenl0RCGSU2CGc/A0M1sbbb8Dy4AZ3
TtxzVLc6LkxaVHzLFm9ym24a5Haoy7Nu77J2wSEbDC0H4mSmuW2J1laTDH/x1MdsN0FoWPR7430Y
tmJH2hKYNFNZEWAjeyBJGFdXBBie4XQSyDxiUSIVPWQ7rX3OmoSlKbtigBGaGbLJfwrXDKUXoVhF
QBfAVdVWch5qKR2wY1NMJVg5NUFv4ERgyvNyXfUZYVZ208eC9MYiT9VWHa8ZK7fIRVTc2/P8DpLG
DhQk4q+uPJf/dv0025DmpKW/aNSPyWbjPTp+HwaBSEaaNRcAAfodX0HpuOA4qj8/3NoMUn2WELYq
GWTKI5U4Cfw08yHTSN629sdIwGqNgZ0aR1mwYv7VlDPGguf65UPvcmU2YHKcos1tzWqJKoNBqji+
4i0eLepbkS0gSHHYEnSqKeWzlaV1kXNKom3JmopMc7ghrzrWi1unQnCLWw0W1aoSnRDboh7SlRyp
Cv2wyR7jjlHWLEm2aPHC1KvZdQtrpLSYrKyymI2wnH8TPWT5FvL3Axl1RJ1q/PVtJO4DmfWzwJIk
PiNKC8p66AH9Zi/HWpb/u3qTXG22VPkb8Yg7osdaleNs4nteqhgpGkre//nomaNcFIjIDhOv88/W
V1/VJdvc0ndMTear3oUwQc9bP1jzAIKz5+GT5m9ekhTCPSP/kg7TKj3y25PdFnMtzptFVu6FHm/A
c37WyzFTwVvw++0Jc6DShwiWaBbJCIMVG6AVMbYc4usFlOYdCGckIfUYEr8z/pMXqWCFjFfW3KS7
zxyz3JXmWf6MFP3wx2chJutnkEQURleCNFSgi8QDRXzoCvNuieEB9HMHgE1wucNRZmj3MXn0dVp4
A00+lO1DsLMrq1HEGQ3oKyNkUEoG9gSZPyU1Nk/G7CrcCjzVCY47Xn/IcBSs9zdXWAXTTlSd2JUG
VM8pCdgAymPIykVaGVFWzmALyp4e6Ep/VKFIsvFLlidjFqZ9/RW+HL2zujdsgNosXWVCAXu1W72y
tMYPatszbGTt5/DRNmKq9uaShGi/+XMVF0nAOrgKpRedRCDaH0ofKREyKcKXq1RWqck+5DycmQtI
8NYu/Uns33pU9SYOaLtzWdxTzSC+PgCWOmUAh+3Xo0DM7GMszUxoL3djyM85KrRBt7x0OyvwKWFd
wyqBWuUHSsr1KsYm1UvjKvTU4WPzFuvV7BkrAX+RMi8nXe+2lYRooLlIBRJy78Gg50zspMX1NEgr
zwOjBkPSZHFIq2yJq3NeJD9HiUg0T9r4dRWSYQZwrxKn7TsMILAWL6SPBVUP5KAQRyCogRsmAZU4
mjeEsCWqEzfQix8kXIxAwiF5ZXBCrFP0l7Sute7PGu7r/iC5C7qrxHHqzMN5YJxyVfuzgJYL4dqI
LbELh8pQTwBCjcO+L6rlDduHHiMANVrukl/rDniTtNuE2o7XtMh0afApbuvsrXABafZHAZ+GC39J
Ixyzw8SnZIJTv43h94MUBvES5o2RBpsfADqiZVIRIiO9Cj9zQw3yTZJaxhmX1xEeRwzjkM0mpGFd
txg/XUZxHjrjaw1J8SVCYc0w5xXE2GfnnZN9/0vZQeKuXkGsl2Hn/twoffQi9LcuhSEgvz+6k1Tf
mf5v31MCsL4iOEVfWKcLXNnhOQMQB5ciYSOXxJKerOGv6lFhi4+JBUUs1N6dCmcLwx2Y4RzzEd2T
SYt87fwkB7eFkeV7gXjLo0iUv4Xvl5aC2NsyJxLOjOb9LAym2B1FHXX8h57sUqYTh6ElEpbt+g39
DrVBEyBSj+AmjJ/edJr2q+UhNZ4rk9QAVvQLxkX7dVS/KI4+Ndmbarj+nUmgqsizzaMuw41uIQYi
abboyW5ZG88tTte5mbh2wadrhiuP3t7f4h4IXgW/Q1RXqXsC9m+IUjR5CD/pBCL2ek9AP/eySCt/
Y5IKiifma5fFfGf825LGJs7+recthtgV2ZsoBWAi6ncdB1F+tfzK8xH2a80n23mNMOapJrQ4qev5
yXcvzxuLJ4dcT+npLTfwjWqJITaNf7vnBweZP70PmmNL9QBUTaok+nCEDQq0n2f48D9aApDqh/Th
pJjhfXQUuBdkdYAxBirRVz/vHC/ag50K9XaChk1gn9TVsllsW7rcnoowWiP9VjchFVJJypzp9RkF
S4bH7/+qH3y06p2pZ352FVcvpq/fKYo4iYsIgChOK8i1CnjmdGPnEWeelo9KL4fKWKC4alUT7ymh
1GHNKUnoaSy/Tf8QLBOPfvxoTAdFIi5lVlQ64zqBzOvTD2BSp2+D7TPqffy9KPKrtbuM1Zmm0eYd
jMRmCgl37G3i5Ej3vEYOagQ6/steRSdooDNKHgoP+fHjfTf8gTRTsygzMLIfUg5sHn/QAQjN269j
BTYk1aZvWDl3lDPFDp2wo7R/Fh6ceyZirDqdMu9bwgPdOPJrCRA0Doz6NgpR8oPXd+QI7yY0JgHw
GPM15KjiUGd+T2adHhw8eMxHBPk6/zqKiK8Ocfl01HS1CxBKMo0VmG3g5jaLhad/oSu1BJqgy2b0
DC4kQOTqkIizE5hv+TYIxPw1GH3jsLiflGNj58X6YP1n5PIwQEJsv8T25VltD3MzB3MN/Wja9Y5E
X27Rp2bDtzzBu3KBEpc+Am45vk9f/ndLTOgkUJ2ZL7GS3QTr+nawArfEluFcAT5Ymct4EJCVw3Ny
PO41leZPlRNR3l5x1qL3VvMn8l9svsCisFl7jZ1yWXIQte+IlwCOYX7aJbf5cNa1w/O6AL6Ks2Ei
qkPf6yQMdZ1EuhgvpA7FiOD/IEcr8PMgj3xG2q7tWrd/NU9+cVl58M4R7bV/BYvRr4IUDVUESRq5
e1OjxthXWyWjVyi++YNd2h0YrC2vzTd6u8bvAzb6050KVNNNeftzaHC/7qbvimdE+0Q/tUEQCFJV
wSF3/Kef8vwwyw/1COYG+YR/X4WlBDN2GW8AQwpn5S1+U7qOYxrKKhxhRGNAllRAlTzna/EsilP+
ecCeZUxB2PZOfWjvpERfoSsW7iKW/jhO3nk2i2b0HlKUAO5cpKBcVjtFg8IBhuNMLHuMQW1Jlm9J
4duwZEFBs7n+dTSkQJbeTRXg4HgASbXFFOMt6Dbr9RkRvkRpoYD2ClZSGpjWs8Fv17Vod8+aIWYx
75Z6DMS+CMmKYVKzRp1gRP9m+hZo/tyD1u1akhtNbQbpS98UYZYaAWXu7FClqD7iFTfHFGOJMGbD
AFIJ4Muu8H4A6SHrf5xkcjWyClYMq2D3kh5xCW3sS87a72aJc7B9wxcm7Pq74soM3gv8HvWauk7Y
82ot0ZDrVLEA5d3WzE+ywEdmJGRxFTaoJWjLmXE/MuC/Gtf4VUbjZyRMu/YD/iQ2TAFNNNKc2Cru
Ror0WkEEAOetP5Jd6hXz0oKt7KbfrXewmaFM11n7FoN7aBsUOUu4MG4wPh+HZwPRwwCFr4nSKSLO
gFkRPUevze6BPBcUgI/6Pl0DMGpUFGZc7U6D/4i7J7sift+DsOuixKTmmZWMEpjJKI0tZ9rIkrTu
ryGUvdazBpPKxEyiwFS4GcCgLdQzjQR2SbtjPuZixlSQ73ClqafgzBPfiWgHBUR5SuD4d6c8wIo4
5tr0FWP8b+YA4ak5+yE+6Jer1AtTGPo2uDoJP6UQDEJv9fuD6aMNHzmwcTxiSelrZu7DnJii3Hvn
qaSWohVu88qwKctFHjBNXsKMW4h8XWQTFhXIT09uWSl8nNv3tEAmyLskGlwTIcyKuUItlL3NEYcJ
HAfTu4LBJhNasGpXCOYcRZ7OyimCt4zuSaLfvb1KxMPRN5w8bJ8UwZQkiIkj5ZrkOTjU2ZHaUvac
CTPgGGhsqunStRC6zMx+1RNkzaNQRHqAqLQQq7S4XrpKAuN6miGu0+R4vBkNMvu9fZNVqBHCliBm
SVPgyWUdPHau+94iEW1k6wPEY2vsZ6uOGfVLw/TQYiabL+JdGASqQl2p/m6CEJdXsLlAjlC9uCSU
SROMOxT5d9U5H+aGMRG8FyoIhqtWTGP/dox0ke5XD+KGk/NGZC64glIFREeIWbsUTW3N5cBzO3XV
48ZrqYuX1c8aqdWA6BwwW0ILLKBqH0X7GcJEFqh+fP9l6+1cyNhFijV5lPmXmphJkDAiyaueX885
7PzX1gsOwXaR8T1UHY/ZEyxKeZ7NlcaOaQaJNPMhafgBXr01TGxa45BnlTwGFx2jK5crC+BnwL8h
jl2zWVjCIAPYOol9yz0FiuQs44yl9iowSJj6ugDNWqE5s9FQbpTaE7gwvUz85orqt6kotEVOedQ2
dwaJLFrpalDQfSoxCId36DrwDi5/BMm8FeUazDjV4drOnrugbwhW1+qlOdYhZaPIArIia4IfJt7T
5M97OGWmy8r4v3sfrDPbZ8u6OmKWzfUFDkh7w+yIyd7kIKBykF2ZyeTQK9FafSNvdJSrDfGaxTje
ubfGSYyaiJt+ksc+Jx9YE/LIWklX8rO+eOGio3xDNY8WVrfCdAcJCfsqWudti5SpdPBpQ6RlijRC
seh+XIwV2loSW8wZDs5xhMIkVHt29EmVfYKaOA52jjbQFRp+wZB1ouSDzufxrPppDqAMz5PfG9Fn
dDq6zwrHxqdON1YNYtnvBclmuThZhnQ8W69IZzo6t4YtSXgVYLZyx775ZweMF19CMKoOak3FCkrx
o9aXdFDBJLhVlb6Q1gPIu189+4+IrH2SCW1vOzqz4i85MQm4/yp6Zdw+Yb4Gdnem0o3EB9WgxK4S
80UBiug+3PCbY6+DPAB4ma9P9y1UAG8/AqV56+qK7nJUNPKMvO7tiGPbyU6jUUeWeYpP7OMaeuYM
d4Jn3iAEVjKFiAZB3mmNxZOSGaiptSzB+DD1i3n6Zbe9imUt1LOrZle16TFFHtJaH3UHz6+143Wj
C8OycMzJ6SZ4U+ofgcXpbhB9iY5UbyuFOc6M5GYm4R/7ht7hl04xS74WgDLsg0JYxnn+N/jv2v/S
OCm3yEncYZ379kdGHMP0bVx9MSY6TUyHhYZcD9Ije07fxOHBQztdxGR9fNxbsL5TRTVdvacrnnBe
D7IcKvWIO4uPz0m0dTKW+atTVoPw6Ss4igjZ1aERChqPbfmGkq2cubXb+pC12I+wWM2ZwSLO8IfJ
dOjUPxsOEdi6cfmAtL/yuXxj0KG4FzxxKsHSABrRO7HH5EAy5PUhVcJuIqfPmsOtv1X2D7ZPfMmt
W6ql17Hg+L5WI7Wxe0yH9cQ3GE5WxRIybnqVe9Dt+nQj+6FagCM0ElJATgXojsNKjtF0sJVR+Ngv
5FyrE08kPMQk/t/lk7+ZfoWpuGObIimIbN72ivS385J4+tRPfVQc6mOnqrv5JSBCIfVJtAaNGuIu
+L9HM9YlF+i7yHEOot+jWEGbt+e5lA23OyxO1M9WVYTCArUjAWc7ELYhen2uy78dnWzdupxb2KvS
p42SvLaGuCDH5Fkp+xgeZlGlMylRW4Jav4oDcoOb0XjO9UvzPInH9Wk+EIR3Pgaguc0QUxvutWpD
0xa4suN/4BXGpZEMSKQtEsb5pbnh6Gp1Cdi/TpdxObFy5ZHQBMs2IKzY8Sww6acyuL6UfkK1EDTc
+cLJpQA//jyncKZlK04+31LwX8qfe1fQJHygMTnWwB14AWMhavnUSvcoLhqtHl4kqTK/3TM7h8pP
NcxbiWqwSkEsqHfK5ZrTsST9Y9xJ92NgJYAsbmxpn/SCGC2mfnNJD2QnFYx8KRPrqN6avfPKB0RC
5E0G3+XRcmKcVOfyCRbXUeTQeBFCLb5glj24G+2tGAf+nCQ56WQJQqhVwML+9N4/le3FZh4uHj4u
0cJQ2a4daWLrFQVlWhrr2mVKjYI0ljNo3qkodArPgag9S8Juqq8dgA0QD3GOamyaPtNE3HobWnxT
42EXDrSVUfw08YGThYlxb8i8TijKqi084ODhv4Gx97qKNv9HX76cKqdduqzRV1RcArlLSEKd5nuq
U3uRYKUa+5QukI2UoMc/BmlKlS9PEuo00IPC3k7rLB1qe0S0Gidjph+6QACZQCU7PRvdwKr8+5dO
2i9DcSZhXxaOsbLaS12RyZBfG87ACG4UvkJ/ILMOptnre8jB/UPZNoZ9jfRt2MYAjZItqM7RRBZm
Y9teA/ed99y3dGKCbvj93LPR0NyXObddZHC5qX6Qj2my/OOT5o5hcr9f8pZpVFd2sxUaFVDPGrjB
QA+oAd4LRhJXjp31ELDWbi/qQAWr9Dwtma2S02Z+6+D52W79AvbQVsILE6j8fyuvw31Ysm8f/ewv
Yw6uWZWi5c7kuWH7vT9vgaBt/9tDQa8Jc83VX49mlK4AZb4vVF9qBarWsWB+HWM7cB9jjhiCcxpw
oB6NchTzOvEn0Zxk+fOxDglWUHoIM5hXI2FQPkCueU2TJV6t4i4g6PAcssHyp7yfv3VjKm0AwP1U
/fyI5IzcFxZK7oQ+yaR/9blsef5SLYVRboqNn5PlSTCAsF0O4E5ovbxhZbNDL8shS3dJwywwozwe
MTw+U3WAkI2jxPGjvBZb+qsmTMVh0yT78mHV7SiU8VT4QBDj3DJFNL9A/kiSJ+QVvbqOzxy+VPG5
EEwZ7EDd6Zw9cK5WUzDhcomwNokDxwLzqnt47qwujkPlWzOrIO/CHEMWyH2RftCUR8KJLaWhcUpX
vZmxlebypCQbhuXkCHrmunX8uHhkLWIHHxIfn1T8AP2RsTa3MyHY58lWdSi4Ce0ZsAqAhcALJhug
HE/pLiIpbMmdZFljHFjNggCmK5nOO+ru2c2QCPNmb2wZqBJ7JtTUnYUWF52HU0DrzMP9ZOuCTOgu
xXF+w5yY8m2Ki4P9G0e09eG+dL8ciSPjqBsc97yM+AiQ8UIddfNQ8Idrix1cYobA1Yex6ixaonl5
KSK7M15MILSqla/1evQaDJl5T6r+rLa/UbcHEf+229YzElqgfqr3D6coi9TKeV+sK6Fmzlo1nI17
LnqZHKdTPboolWCvrrpJ71rqpKe1nqan4Vw+MxZVh5WUq09r8oc6aO61x9e9BgZgS8WLrwdvpUnC
s+4qLK5TQR09FvnIn1L/noSxTGLOJhsC3+iGPLnYY4gCyYCtoZnC3QJGbSM2wab8pCBRD3qQyvnu
lrTKubFMKuHa5T3R1LliClVzgPFFlDAHxz+th2vOu2yob+2nqbU1a1IX7sm6xoZXH5sv9qoYnJmV
qbbfqYAavyIYuJf/tR/nr/wFkkISVEbnKyJkWVJf46mPYaaKPWv779esVsOA5g/LZfpp0/gwnHfz
xSAUVkmywolMDIY/5niJ/VI5HcsxiA07/McJwVMeWPscu5ktgzo/dq2LKSdOBfppZuanzWVwJH9B
Nw8BNB59JnxfbKqOy8PwQGsr1s4NSBzlqrGYLcTUfeG8aVs8zOeOn/l9OpHMtu/f5DW3DiGxgN7c
KyYca/rRfDdrsHlK9wjdg9emboSnHM7tRPjLK9WOuB8Qk8U9COTGyX5lZA57WzX5ALyuw9YYzbds
xMAJkNEtOcsW9MfqQmmAcgo2ZDT+DEkltBfHqsjDEZc10G7kBYoo8SMNQUWZ1oUF6FQ6yqpQ4O8M
SOJlA5YC/vUyHgxZvqdtTLqTwZzqbMdWTNn0VQKrH+Ck4+2sByaT6HZ94CJFzV/g3KJuanle9cAl
1cS4S5rOaEy6JxFuYic8EqtlXJwI3s7gEO8BEtfuyj/JmZtARmVJk6ZPyhJJT7KN2/Aq9DTIKSfy
LhQbI5g51zzniA8y8UejOr+op3Lx+8OeicOCtRA4bzNH9i0IYiki3A53cIoSDVTBjiTeCkMj92g8
b4VwkALBSeLs0rZ9a5TTpxe6jXzwBy3nQuhNC/hnFR2AGSSLfXG9Xp+B3BEfrrY7X+puwPl4BzAK
cWhunXTeHIxf+7wplOZnJiwSeNt40j/Q1TJMHeqc+OZrh5jGifh6/01T4d7YUCEM6salIPnb8zP0
AAofqEnvjJFWlZoq+xgkHjS6er+icLHsGM6Gp91KCfks50KYfqQjYh0yOt4xXNzvZvhMSW/R2fn5
LfT+6yxZHuiDqHX2GckEKJd2ql/Jas+sLvemPDoat22CJa8VR4NgCBepByzUcZL5mtaOlS9hRgGZ
utgds/iXBDduD9YjV6XpVk16kLibm30zC206/u7jsqlpEOfWYYAB0adviuOgePeyEOKWvSvLj3j0
ACLTn82YRssKXPkq3IATYYWrEzWGDyhZyVs00rEBhs+xrilpi84/9erN9x4hk/3T7McYt7u5JcMB
ud9u4mTAeGt5OA+9XDQra6x+3YuboC1J2dUJulKI1rzo6s5wtZFG6Fn7O3WBa6dBqM2IT1659zt1
M3/rQIV46CUnEev91EfoU1Hw4ybzS6AtZljY0RcrTebZ815Tbqj8cCruoPynp6n3dA326MFVKb9n
GeQRcGnGSXgnTOFKhZhvaE7pfmCePuXPMeL4qt2D19UCAjIZLpWWU35ScByLfnixNaGNK+zNpkuO
BAo7Ud42dGRmoXViJcFA/jx/ZDwzL2juxITAfYfuuZk3WunwGI0+LrKpbvcbFqhABswczWDqYmQ3
adpMyZ4Br9DuKvIxJkdA/VxZCGoMp2xINTsnWTrN9Fz0yjUzQFobL3covA57R4KFLbD7Mr9YiwEC
NBk5TWNKJXyDP8I2c7+hRUIYAwRltJzmxVG7Bs/D1OsYv4hrrsN9p4UORZ2tgLq77kdgUd0Tnlw1
fsZ64Egi6ZTwLWgYN46/hb3H6tIcP+seOFlq5dJqLAn84uCwuvszv5kxPYhQ4YeaqZpG6L7w2PX5
xPD2njQmX36Q5DmEq8R2mlAKIdGYhzYllbIG0VxqgbUBQqew0dy7Uiu5J3Tc0+ZZynsmoyHgZjS8
1rw6C6T+zBhJKTsp/elAPjNeD/tWXxsGiqRzAjgfvKPOrXr0DMgyAlm+jkbuNu8E6kk+bfjtvh3P
txq2jBoF3DpQYTaCIwXXfqjDKFhgkIBq4H8AaHq1nM3b3RbqB2zNAFHNQ9z7LVo1ZPN/GWoyPTWK
FahftZ00a83hiZoctPNa+78fH1477dh7cDFSTKCcGh1N9eEi12mzU4rdopbX5Z/JBtMWDWigrujN
HCTUXMrcf7jcprDMTCSBOUvGgIoN5qhcBQBmyQcTsHM1YCoSLGAlSpbAtUdo5+fJLzop7yqEW9dz
FVU0iRbSq+nj1lP/bdsNAxaEu99++Dy8iHsccVqS7b2PW2fEWSIgAhOAOxcQdrvC1132xciligBO
vXus6PF4S8QOLiJJV5woQlWezCm4P8GsOXd3krxt0GuusJ1ssf+v6zmozQH1O1YiVsJOOQH//lMb
+D1JVBfy2Rl5ubDGG1E5aWe7pnhzYa15KSm5HhqlxUffFBBxgvjikKOLdxUfgV0hrjH3H4XC3X4s
Jp32Adu6j9jAjXYuUzrcbEtYKkgOg9wkPB1ji25fPy4eSeAaVbzhdqdooEcCbOGtvYq8PQxRmRQq
5BtdfTcXGG4Y9RPPCHT2Vmwpb6UTpYJM9KZdxWOKQLeumOPXS7rN1iT4sQUsYNp21l75Y0Gy749A
/XRD/ACOw4+QoJ4hCuDm6D874M1YXhUSp6s+0RBmPYMqzowSlVZg6A2O41x3HVqhw46fXhsLHQEp
l97T888nvypMFjxhLMd6+cVqX+B7Qr6bKE4qZzjzz3cnX/9TEedhqpGx0bq070vesQmGwIeJ8MUy
dfLC4vZmi2JumpCd1Phx6xiyBJzR9rHR/96p3j8F4U2z5LGl9TC8gCcsKlsPdGPGg31I/pPmRtCe
iPRCbtASQIwef1XeG46c2xIYlCixFZBQ6iABDUPtA3IxlCOELjwrLI2c3+xoUiVhiaGQjV+s1o0W
a4E/KN35+ZiWhpQqzWP7NQ5HhvAdSfYJA+s6PDo66SfOjmeglcQ4j6Dp6RLhdi9O+P2SFD3NH7FU
bBG2jXjEYoQaiJZE9QRwviKwlMzmeUOasbciQF1Ku9VHQq+U/3+et5oiXpDTrvKdbmg6QmV+OTMJ
GapakiNwamGAOIRJEuplWivzoTtmGdhEVwnwwt2yKKAclioljn8PUfuH/diOHW90sKN85uP5q3Cy
glLW7JSZzed3jOiarz50s4jzfUJ6N+KwdGx1kjNmglCJXhxEe4x5IF7GWvmbvbcnvwGiiVQUDXvC
3YMZSZDorbrqkuIdwQPkga/nqFm/qVBMcjwMoqWfHr8a8tbBocCUqm+34vB+HPsEF3GYwoUgcwcD
9bhxeSUE5UC1MjlGOW1bS1WbQHgvBspZoLNrzUS5D1y6Ngp4ehRXmu1F0Q9366k+IENv4EfcsdpA
eYj+dPmDlgLphd6TdIN6aAEW08dqyVWPZgTXIPZlZBjZbxd2+Taz0Wf7wgP0r2S91Q0KxJgBEKak
hf8rHfVawDWJ4p21RBS7UD3QQMorsUUegk99s9ROg36X6Cg7/Fm62M1nSdcvWiW+UTFkzZivwcOb
tkd8Dmrw13sWSppZbhXjdtj2qfGtAFziIMZazOYbPO8y8kD7IFkURbZZ8ylhl2nj4oH1KOAsKcnh
uIjiKN94cAnJRoC29v37dTnV7m9D4ZdFvGgQEvWz1Fbnk2X4n784qOrXRnyBqoqRJPnpRO/NuRAz
AkDafqNuPJqowu4j8LOZHShep8L/M83P8PrIaG/MOA56V7hDt2n8stExZvXJYHBGtYMf934LGHJT
nheBa7k9VoWjQrt02ffFc/fkAs7k1Mclxfj98fJ1H5u2ScgpIvj/a1nwme2hp74Yn/CB9/fTevSY
1El8ytmIn70wrPnNHBPJBsIPNvtlxz4pEBcLkYAczcJTBVfAnx7sEt6AHUficjqNDppy1atuu3Yg
u8TSgCjG24iqOMsE3p9qf8jtnzSxWhnyMYIZPRldEsmtyiS+JIB9xt3TlO+lW1zy7Dv5Hai5WuVw
X0WzSAkpe1SyQ5i0tBh12gmEKC0aa6IBT3aVsoX3/dMjtS8YcPNFzvTqnrQpggswaw/KwCsqsPH6
APXndCh1xi0+Qcq0JmJBB3bWcKMAbJNdokmTjwk4GNVGQKq1SNPeK4KvVXSNhExP2iKaQC3dvhC1
LMx54k9gLcncn3dFiYGzFalregeF7qT7HiNA1mzIYSz7qzaShUyy7CNnX+zyWOlXAdOzPD83shhP
BlHdxHmntM170pVg4ICEq8DYwgYJGpcH70BTzu1FMUQ9gbzUogEmptpFrYileR3j84P+iV4cl+du
VrIJJd0g+AFyZ5Y3rz6ocJACbOUBY2nYXyFLDDMi/OJCfVOac7S7oqn34lbkkjSwdE4r8MFe12uC
9o3JS8ENCWMpQR6H8wgZ7ZTQ0W/krXOoOH/tQyQ7TEWD56d3fyit1e1O8Sn7fq45L8bDKgATIW4w
TAaY/tAXofZF2KyaDELjciY8+TbP0uqqR/wAn+W5wDZ7m4VRLMPVFSgPYXIcy81n+SGbLtRPmVhb
woC97YxW778FM8wYuTfqfGKmwxkPMLs9w/1G4P9t2p2piI+PGl12IT75z2/sm8CW+RGuzmaXwpeM
YwCR0Ke3BjLJ7A44old5F5CyTUTEz2sFpdxVv2I9ukMR9k3op/BPqXYOrjetliWVSmtIJqulaZZz
pK0KQykeYcz9hZKpbEp/sFKrvJSLq0JOqFIPkRNe2Nfdg9/c//f75oqCCXqeoV7BkLQ4tF4c4xtC
ZFhFkdNPovx0M5fde3MTmrJKpvjhhoDF3a2yy2lh9x/AD2YSehICFaoJWCOk/EydGOxir17fpsCZ
pUUOznWY8UpNtJZnSTfBRpSsNOSD3ZtvZjPMEV+mY6bTMx+R0jFc/DCvbmu+7vI0HoC6DfjKT/51
wIdyS68Aur0c1WobvHehNuTvzFyKPhTxkuxEPnxFgam0z26V8n6LgNnGbp92pa1bvlS6mTY9hcb9
3nny6+LPgIZee4T+9sZZr6jDOQpR8c9+0F6w0MULPlEy+lYKKl+blM3KvcapRcsEn3SXnxF8y823
HKYgTDoTqJRyjP4s7ZF9w3chwgynr8smI0YoDcKeezO49eWq30aNLJ0Z5bGFGYpR+a6G+l5qhGtS
Lqxt36i5nFmf7nXMZ8tHNVX0MUQ2GG2Jf0PgiZV8JIJgzFMI8JymMMSQDQo9+a+XwyG51QJE7nUN
wOQ+1EUy2czoH88879xxOCLOFZtjpb2kmHKlcWigAEsSAepD92yDMbpdghGJ/SfTL18wMqc//0pp
b32ytDCamHuurMGh66b9pfhdJb+oA6fdZc7tbPxlXTMx25NMWYAxdFpPfz/Ud6h5SN4zwEAU+J5C
9YWNkPVoFU4iNBJIy+RN8cxD9DOeLeLwkdOJS+l+aubyl6hcdKAzhfpyACOVmPtraj0LNJOOYzAF
7ng4WfLeKlcfCtdJa38KOc7XJFHpXegBdxbQ4tt2lZcEseoYfvyiHYLSoQ0K4LQNAzSUJ04MD5s5
ZtcGurwWUyM3+lrCH1wAPJrDL4vwP3WB6ZScUZJGnFJr/Zufosp+oij1CAxzigyuYYtRNU8kpajh
IIqM9qNZGO44/9bE4fsjDzMAFLKW0ZrpOpiZRtXbOMi4thvRAarx/NO5pFc4a2jJrJ3IN+HWpaKL
uHWWmDbU9zTEcn3aJo5GvB/f4XrBx2H92/glz9sZ3vqjrgEkdWW//PbWLfWH6ccQhtghcZbxdGWn
/y4V+9JoqWcxcKGAV54ls848C8VhxLyUZDEriekbkZva3OWy3uY9jj5b9oOcVu0jVrCeCsotBl4Y
hcBPCaTA8nFOqBm0SCGGswH+V6odDk44dhgthlZLJBGo4sdxLeQ4zMmXEuYcXNE8LyYOUV0spBR4
yXYjtj7cA9+1FwGyZ66i3lkHMDr3rfUzY+ybOs1P5uxxgoOLW5meFobDjaORL7LaCAZJ13VwQ3Wk
wRgQ5CSN6+p+c5HJW9lnWF1xYzOkMI3MQpmBjs6BKD1XP8YPiPdbT5IzmqBppsBS8IBuzxNRYB+/
6X48cqDh0nFrf8uChGRTIKeHgelINLZ0JxPQu/f8D1CncbQDWrjsCRfQ+mMBBc4RupOn+RAfIWdO
5KFPHj20j6zhbEsXeAGwPvYynOgyW/vAF0OjxEepI76q29apcBsQNTGWxJUSqdTUKPV9jNW2iTmu
kheTELntTAjCr+hRNEUf0j/93VgOatKU7CUQsAYFyfi2bV8Wf80yqD81d1O58WyylCk9Kc2y9Ff9
rYDBb8LxD6RPVMLCRbP04xa/C2WuMQHQXzzCpNfFcMsGyJ8WGICZNcx69opVXUa3G062CYIZny4n
L58vyZmsue4NuqqKWcu3YPqEXKNguM0npFP4TXK6mqE3t262dgZTZDGSjCcqZ577NZTdq5RDror3
QMETEXkA9Y0xd42bTTFLJXXjDqSrFsdudF2itHBym/VqLx61oVGLjdANqHyefR6SeR0k/iueFuxy
zf6SwXJUptAX3ac5eZcskvEn7fI0wtrHPJ7RZZ6nmyboR/4IkGlwJhQF5cp1UfKEEifX4iukWzLv
X8b7hEEEMzW2QQTrC6lyLDuh/z9DPw2ABZQCwocOaXPYPyn/h6nE5B04loLSrL/nk8HaVe2ArwL8
NRmt2jpiGgdpxCj7nN5fibpWPRx5Ll4SgEwFn3pfnhqmxZw4kY4rpmOJgQamgnA7i9LDVTUUqm9r
VGK4YOVp0c0eWt2yfLQSieMsb8YVpUuwBLVRs8IMAAfm78VYBCmsKg80KrKUjbmbcX1V5/y/ztM8
kyTZYGYraWg4YkCVcEMwdMuGnQNoyqPC0ghKnXS/k7dR0IA7H9q4zqgf3v5nm4nA9OknYcKC+3Rs
yzx/s4pTL9XXIgdBfCvAplGOwEpaErOz6FWDQgHZ+XzplajvNySYReh92G6XANQdOrp/ZSl25sFI
hHiJqLUjVynVH13K2Z49pW9Q6xIOZMwVMNjV63OcuMo+Y+bNvfhEigsnLRqTYxmMDRiHiTZZm/Kd
x/AMHwUuek/mvJs3vDNVuPYp/cUmYrmWOqmmImsKbZs0zJcC9JukT4hmTWguhjeZgF9hz73YI56y
8Glb/N/5M/9MpZdSqjjTcWj0UD7tj63+ZlkQZ2E1jkx0WOcmeuNElvP4OB198wsv7EaE1OkVS3Yq
wi5tTfdkn3Au0JB0CQlHCfvUOo65Qu7hMdaK1TAw4KzdLfgq8T9RYVj+ZFFJbTNFfG2G1CqbX68y
MFFq61qzZ+Ku1N7qWTppvtd+6p2uUKp/NsvBZ3GPxiL0Ow6NGAo8iUEnZXz2kGfKDmkyC7gwzqav
KzVR41P/B9zIWIShnUM/BUIZdhZ/NXq4EyeaY6Vi++Uk5dBZuxf07UojR7bTDMKryGZCUzT2DCsk
HjtiGSF/ZTYiNszUyv6UO5f/1TUQcNC5JwUVIqa9jUOF5FO3OSyvE5WmhTcRrPxpR1ncxWe+3H2l
WYlyk3BIIqPz7eCjer4G7BftOnTdELr/3k4IZjrA1SnEbTPh4WIybUhKj4HXyAXfmp2AaP1JAppD
86jvrifSUDBNpWnJmA9dhUFcQfKb4we1wJiWguZ1rtTmRAH3kjT5awaNUH8zumaaA7dSjZZZN37K
cDJGQgUgjtVkhQz+jLIrnT8kZZIXpJw7t5+sDzXaEwYBtj1o7HIZrU7bQdh6Mumg7KeTonpXtW/b
pf9LDMadoEjFSlF7y2Riy/qXk5ZoXX6DjJdVS9C9lWpv7noXJSco30S7oSy5kgyMhNfG+FJL8WKi
Dzdwc+PYsrTIXRZ9fIEXlAAER7u2bK63C8MHqOxCQ421UTybcAkwJI2qgaLO4chSIXqo8MbmtGyF
OpIOywcS7yBSGO9/8jmdX7rHMxwCOt6NHiZxHluy3Lo46FdLfHFgGqtScp9l3d9Vp7JcdgnIxGLl
3pGfsGhSBzz73MccxIn4skZYJlzwwBNcz4ZWhYBnMva8e+gESAjm3fiLCJL97jH31JJvGszvuPas
PLpETDgOiQBRVGUn9RwEbycWBXzFjO3e0vLKCWgbkqiqA6tY6eXwJEccV9QOe2FJO86+JDNF4lg4
GE6l78yiHl1ndrmOfTuAPKNoUlBoOfNwkA4Q7bS74O8cUSnizJd6NFUJ6HOSYBkqtCUfEUODrgyx
3+yDNx/MoTaqRBuA1dZftKNnXQIPa+O126Zu3squfOU9f1sz7TsAI/fOaedwcq60PqBbGXtFrSAb
L1sPuYo5TSD8BD6hpd77epLLG2ee4mKFv51SUxBavQDg0IRFiqF47i9vmmRHFz31fT7at/RtOFKl
vPVsMjpjeE80QXzlp0PwSCIVLRxgul9bZKLFj9QK80MrCpHLsOQezwvJjpnLd2lPZv4PKMccMPAK
BPsXWcdmXqXmlqXLHkvMg/f+vxloqfcSelAAsK2iY+q9m9F/GU/JIn0ZNLnp/ZzYvNpNVr/CATB2
kqapYGVCD8qF8aoMQ75Qs4ZVs2gCDdGbl21UTaUt71thZaVt5NzzyH84XMVJi5G1FGcvu0gKRKSE
Tgb1RYb5tNV6iFkle9gMOlUJUXuRidM9DxQPug6Pg1Pr6mmydh7UnBNxuRW3TA+xw3Og8sPx+KOd
zh8zfdsCkgwp7nLGVkzpdDuq1vu4J/odRiDRhwnjUr22ERhQsHD2lFbwXosLFZXiAy/pn9ENdNQQ
T/D3L4pujJci2pVp5LSZFRrlWbGIkWFXkvMoqPhrAnOMNgM/zsb/nnxGPots7hFHabigty3NYvXo
2MAIqVcUEGs9m8Vq2zF6DdDUgpwYbbTr91rg9f+8iMdU8Ri4JQUmRLaZaEYv+lXRfxBPuphFsCmV
jBOpbXbfO2bdyuTZRnUkO1IrVu/9Jqvw20uSymerRPhJx3BNM3JwBUpniJ43cnm58SZ6pTMWLBGN
Pv7hrAe7UMQbH8GdDUs5ABuLE5fgl68cI6Wb7rm6RG+XlBWUwCwyGZNVaiTNqTq23upKvhwOcWN1
kqGY0gwk9Oj3tug8ONmkSu+XPeiQWByyDwdrVSFCz8vhjKLFwucLuyCNssTY1/O5yma9yXyj+cYI
3a03NTn2JArtURQX7F0+/QsYgjrMSdcDeRUFW0X8vYHPtG0TOWs2OneMN5Fz7WeEDEffW9iuWqOB
Gj7X5UJBRMZaoTfVBDuS47r0NUlrOaKphGuRNbXGOgX1kNlNQpoW8vpknhPu6FPLndU44B3K/uNz
oEwC+JcTRHWO48pxfu/N/G/StBxFttROXyGMGT/4HCmvtuxfqQwL8TMk3OPz5ZxsgxPwpmYJ+ZG5
j38lyt2ckgJGdZaeNPsrHuaEq3dFT90nbtJnddL1kGTTUGtVAuFvGUzz7O/QMic04NAthJFli8qx
lVhG2ebz4ZDcrYk72cM8zqbOqhG4dNR0oCfUqq9yh+GFKQIgUW+YmVPdVXhaJ+CruuUmHdq2DkpN
U2uJjjo3pca/MQrbQ8Ulvb4imuBeqq5xkrUUB28+vFd1/6TKxt/8R0gYuVa5vjzktB+jhV2tEUai
0/7EQ9W5Y4Flukk85iCHXssCbdM7wpbTpxFnR0M3ncjjfCFdOS4sC9ij+7wnqtaCJPgiyTm8uZWN
GI4RLz11eddQKCmjxIcV3mMKkEmiR9csmLAVmHe0xyg8QLTzd5x0PWsKHcgvgIOKuMp19rIYKszC
pCicXveRgSaE+60jLm/mYvaHAV0HS/+X+JOtIC6lD+3aM1H1QnWl2mwssaZsCOZoVmA6/gWnaisw
8lsM2B43uycUq90VTIR+3/PTznkb3TA4B7c/IRI3R/vapDOCVKLUfZLmpVRwUsuGCwQdQrRnnstO
4EzgJG38l551dtiBUNgxnuV+cQpC7kaTfNQs0Jv6WgIeoOV3jwAm+mvno28tlSxPqzKfDkZCuFT7
rz/aTggVD73t/H3MXO3iSVAcNJPN0Iamant102IofwwOPOwI1jNgeL802Ir5dpe4G2cfLukoaMjr
GyTG3ngUAf7Toa8ayzpzACE7yonly/0js94at6+lmJciuY7PvKY0rWJsslxZEV4vtOsGtARPbFd3
OsEiHH8B3x/EiCkko2idzjrwjEPjv7iwIvDkkxYnBMBR0a23YT8kbXOtBaQr3ZgzOsQbEuvelhxC
P7jtzgpSg0yC5XRV5DXjfYrYHQN04KmJcNPEAABZLuqf3KStp9MegFnoFbz/ZJc6ejyz7EZnodla
zGd+coz6O+sGUVlFSiu2Wl0bC/l9HOZe0UlKSMCPTOQGjmFDpMsuJzLfMt8o87oUfDj9WaMKQpko
O+8i280jSq+lwM1DEEiUMRuZ+uh92yg9segz6M7no4WpftlPXPcwl5A/duCDstRSlj5T4hCU7KU/
HO8ofcYYCAOsoowXqGPgZPsnhzYenA+XsddUE9uPri/7p3zF/K9dVY8EroxsYrDmvAomkdG/9znq
ALjjIFCEYD2iLaoZ6d1V6LsRTfSpa2w3qg1AzLZgim/OpXYX8sOtB8t9TDxg/uO4Gs15gkKkUbPR
0hB77v3mrb5sY4Tn3ksP5SKjmjR3zBUNQ/zx47Mol9POJCyuyLUVAKgWKkbZGM86mb41v2/Lkwa7
enuaQ081nieYPmkVKALVKT7E5F3ydh8e4A950NKdtkOtHwlv9hOmBODJ6Jd8MqAJqSXuE3q1ATwY
4Trka0tFZGdvgjwFqxlMtHKQO72jHNMnhi0a7TrqGgj2dmreCwsBwk8T9/IPr2se4ZlEFfvrjimF
wGjvSpdv4GxjY++4A8EWhJEW24pI789Zb+mHWKVn50RNsl2HS/opE68T7u4a0DI0QGg0ts/RFlmj
cPXC93aqXIU42/8NAw9lFLArzi+eeSbkzFVFWuE03Fmf7/XgdXvTcfvdpTrR/N9B3abwNRFpVccJ
o3I0FitWgNAZlBGldd5BIy7gjsX3X7z/PbzvCFC+CNK9GJl6VidUjdC2HO1i2EU/6tTtqyoqT1jE
HTrzyuY6CZlJu6K4wJPppT3+4t/XSdUNhnJ7Z9Edvv8I3i+/8peI9hPe7RQVx/+zNNoqa0PDvlOR
UgY8D+9JDc8cq9VfLVuX3NjzGxgi5JNr1+sfB+LO7tHneE93JZtZl2Hi9lJVFQC2xtm2jvWaolRk
TDmjZcZtQpZAJWxqYmyk0OFBA1LmAl6qipBIuDuzQjNPSWc0w4vCqP2eWfQuwlRzEydC5sEP3GIx
xhbWW9G0F+BCA2lSOsfLNTnPgCndq5rBjMS3xT6qniZ+0WH5pQv2N3mpaqUWBBWYf1jPlR/iNeni
mfvlQI0zDxmS2O7cRlEZH/VWBJ2MzDFv1RecLoOk9wb6xf0gRRJTVbtrbHUgUa/pafUBaYIn1Szk
bwocxAA/e5LMZELlTNFVnYHPrVC9UH6ZPv8M+Pg9KwmgFvFXylNENGTl30jHguv9+GeBAqePcEca
E/y0RVpYNp51PBNVJ8BlXRLLHmv34xpWKnIxTFj3EOEEbYye/JybeQVsWyB89DDRsZF/E7Sy0AVb
9ZfYGmOnBk6PHjIofgrgno5LJRKXqHEiEQtzXR2B8Fhu21/9IwuK4A+D99AQ8YbMSVJq5vh9pZ4o
Lhd4cSyKZRBF5wCcd1W4oUGmjz7QJye9GKH9r8ORix/55WmVmBu3Xs0Dpeg3evZ0t3benlooxKR5
MlQ1M6UsX6+QkFSKisGwqMC8eIX9zCmgwTYqayW1dlt9M5gTeGJuGAiniDz/mrFBHi0N1AKCyjfx
EnhyqyeqfAS6uE/5ug7b7TKvqzLn4ls2hfeW2rPATI+zIK0z7sal0uaGvZRMqmQJOcdyE/Ltd9Ub
TS0hEXgoDahJ5ysDn1lI1irvyjRcOIrtXvw4/kt6qrNqBfkxexLCBsRWUqqAfRxt4hKq8GPuxfK6
c7mO/cakrIsILowelvRJMTdf95aopGOcV5TmQ50MhOJ6k/MqlOyphWSN3Mh+VxIssmQrlriEBPNk
mEgjF5SwbETiv0aR7B5E9TP4zX6irVjCwYLEElav/R9AsBbaidAy5ZHde9abenBhFbvxfQvF/U/U
niCx3Lo0tA3eBXV8XcjNhLwwd48NlGzbcQ+CRfxCTMLuxTV+/UzKHqn+NMmKWOPQA4/YdvdW4jpZ
BjVbSPpsicobC0ZErSmvGzqnJFJ746g6UbH8aLQNMLJzYIQT1XZ7DkINkbedimWTrPtnZ22do1Ke
kWEOBY3kdgs+75eSDVUxLbC2+bXV6m/1XkIwDMyBHBDWy//3OMQEX94txEeEj7soZAU1PB8qCFE8
HKGPvF6RquS0bZ1+GqduQfZ+f4myo+F8bVT28GOzb56Wf+o3tfEPwFGshkcK5TrOOE9KSBQRRaPY
V+RotnFMnDtRQemp3XFBWm9+2FTF7nDieDXAyzsSS+h8Fd8I1/WJ/Jz8wJp8VQToGIycwdujA69Z
n/e6/rCln2o7SVkWnSKvr2FwISC7snPdSU3l8yEdA1XWG91dmapULM90RPxD4OnH6khiv9Z259KZ
JiaGXSRj2rCwpze0r5kuKlPBc9OlOoSopA0eoXLOVPIHiIvhcWmcciaWrf4RiwnBUdp7XbXG0wnv
jWBAkIwh2/FolcT4DBcWEyu/r0WrxF2s/Rv4YPJveHLxZj2a1dj+pdi0r/OF5nl32tw9tb2R4EyZ
1m82G4bJKgGMTNZABL9wAsnm+XkaxxoXkGwtkr+iuZGCXcP6DCHAh9HzzP1UqtLrx0oTz5+T8B0L
2/sK+vrtvwQjDwrNHkxLE49/whd+CkZq94tA5OouYU3i9E/n3GZ5FT7GB3D3NM7ppteP/3GzA5Z6
/SgsiAE/BoOFEFUj6qhBW63eoisu9XlJInj7ORq2LVlhjYbhgMLBvr6k2Nl+zVdTSDJVWery1DXk
5yXtwTocw/azalSbTfh/jDSCh+EBsECmhfbbON3ipotTCJXQBp4g6igxFbjNnEvXlD/hHa2+T37i
A5mS4GnebhE/DcaWgxXszr8CDVsbinzP5Qotzkuz0G8UpcmYHLOUy0rq/4iQkCBU0166WeWeihhY
fBt3DOK5oZOGnjTTmFKX6sP9t4WILAD/ZmaOCzzsHDMoee8gn9lmfFgnGAJ91PGO0ORsDdm745HW
mkKS4TWFM+Ku/wGOu0Lxc9jbLOmW1Hwn7ydMCBtgIb6XQdoNNAcyJYwe2VxiiCsIbLSfMsFBGyKR
ly4KQRoL8O1zeX4w1mFHL+v58LHI/5S1160RyqjZGVUbiy0LapBJPSA4i9K54PM8CjKYznSnleUk
p8c5GrCok109xtbwg43ceoc+0JOMUW8isjjZfPnTQsLyCCcphiTcXRVV0zv1G+CoWAy4hhLgEIXx
hhtbFCPcJsg00Ql5k232PlYXz42AESHsMeBNk9mnpLv1eO0xFQQTg7qYyzxqji+ZTgdWMEtAx7dU
VMu0+Q+ozy7itVll376foiwmQC1RWiG74DXbvSiN2axIq2YqKPdvPp8LzcuN6iyqwIh423BpEnll
5G60Hr/jC/0UzYdb3WLZNMTMejxMRrLaPn5jBgZAKW9+0KHoi6xALeNsw4ny4Xc9C4VEJJur/Ign
cC3AJprRbiosQYrDndS1wHSnRpCZeBK5EAkgV9sxTuq6P4K3IQEGlhOEEdkvp1FKg+wHBm41HP80
01rzeXvou+75hAve+nGLBr14jmARiUjT+OKaAoJul0NO0D6hNpHvM3Ih96n4biOwIaHAHZmpR/JZ
ZGYC4uOnEAw+ojoEqpy+EL3Pk9sqVsr6J30INc4AHD83DekIIJaW4fDeVYf2oANT6WJIQA8bAotL
0ZkqNBuL1EdGRHCZ1mK3pKuOI7miymmhKYPoaA3Hs/tBj30wB38d9cKTo/IaLi0sPxGJ9gBHGWN7
aEbs2CEQ2KITBa/KH1FLE/OyNt4TTQS/xp7heuMb6rhL/hVFxcJEl9elSpimtAsabNovZ0fNZfjW
ynLIdEVu+azQUQe9ei47NigDZER+UxwI6Qd/Cpm2z/NUihXCZZ8wPm/XynKvBjtKpZrxsmcsgO3T
mxG9Yo3+TwYOzcsVMdx40R8PAxmxtytFtwV4ws8Kh9YrhN+AeMSlo2oMvxG8QTFXRt0PbhMfnDYk
B4vZGW4HMXyZDsME8RT1Jym4Mr5YMnjeRfu5hCmhtKL+ug4m7lGHtqfE+lD7BEXYVzDuGkRCplTL
jURaSV4IgsRTd/RRT6jAEYsJU+uzvxP2WqV4g2TWPtjgjwnpw8K3E8Y19EbBGRsuFkZTp53/p3UU
UOf3sb7s8DZ7e2Cya4fabOSpdQZhv2/1gM/EfvyiLhfMbpQ+/uKhwpmj4MZN+aWD+M5tkaq0Neew
QWXh88XYrsMseMjHb7LE9c8yk1vLIdTSnVdrETWOV4OfxTBemdBtQk9qJxM2IqzltUw2DAt7h2X5
PIA1GvzxmW4aYKSAqoWwCgxSycXtYjGfQx3IYsdZfHjzyf3+KzDyNBqsIeQM369vnBazmmmL1yZQ
igXjy5RwClOrARF047wP69EMzCiiLeFzbrJWMkklo8bSBmakXSWN8N0mGGcBYRRNH4WburR0t9jw
ZXnidsaTPBqiMGSL5LWC1MQ/jSKlBfgFW1D+X5wZeQX9iUMoRIQluaxLmae6g0p+ITbGijxSqqwp
m90Hgenlcc3tqnoprl9XInZwhPpevATCK1rcQNyTKr106WkgpPjP2E32di1KqYvZuZB3ibXxR7oC
fiBzrku4cGXIgauzSNzfauzsMsZLLTeL/S+Sk50NBRDWiyjy0sh5vA05uASrPpAHaFKG7ketV0Qt
5lB7kNt22XPYhILFb+g4CzCX+PcNCsMLmUXiVYASbKZNc7+19rOfxTYiqW5PGWfoINJtS0LH+/yj
bu89+IJef8RGRHSPboUdXGtLcl6tMkHqK7xtiGIh4nZm0stehBSR9Htebl2jMz6bzlgcVDqNYg3F
d/SmkSrOsQKnk7Mf0jht+yF3vik/a/6snm94496uMh5Wa3KZUOkhot3n2/2ESd2RbHKhi0I6v7kZ
HZKBzqFmHDTw9MEjkO2kYyAGLkeEiPaib0KD+UvZekyCR0fjX5g0YOw/ZxL7+dquILLjDmSvtxXV
DNhLiOn2UPJ7tAuRLz22PGLFOS0oi5X+wIGf/YEos/c8q/fIHh7bEDzIURUEv1sOxIAIJ0c7LmiF
CfafSovb2Bc0jYqyaEbGA6jr7DTqzPIk4+ph6TehqjPM30PGmJAF4Rw7/WgKzS+MIZm/OgA7Fmye
4Zkyyu5AHojecszuacAZh7g8dfvxomg3dTHYksiyNvLJX+uayYxx3KBg+xW7xm8KKccDN8UkcVPw
e1NsmGWIlRzcq/z9PTkLD5C0qnPTyupZ8ApfyVIWYKyesQfuEr2rAoevDYBtdV9XDa3nfaoCAMr3
Q5locYc+CN4zknIqhmcPdCVsBR5+NrsnD2lzywFGeA9YYDrF3iofpFc9l3p8vmYhy76Vfws4rZyU
ttmBDGSti+UeiHSynwKOTfLUMhy6zIYL7h95tm7YJq22T9jKTbb5O/VoqpT0xnr8/MRPS+MTcI6Y
3q+5GZOs/dQ4s4K2SBxFAATr/VyVsWQXNrCULFKbtwE7C7d44JOs7Q5HLEycVEAulzR5H68J66lU
IYSLEa3GqMIvl5yXxTjJseY638B5/51sqVK4JqRKeIeNXmX+5OTM5pR5kHY/gO/RY9gKrh41Ho9U
qPu7sq+onWimM0z55pMP/7/mXpBIgpjAenACqFvsOR8panoO/9ASd2oHGB8RriCEKlCHW3nBzMLT
x6zcBRlkr1U/pD0UFWemjGc40jLTRwXqBdr3iypsJdBKIZA65/qTKh4TVMYXE8FaFzzOCO1nu32A
Nb6HJPZxQVB1lKPdhmgVfVIv2t7v79Jox2ISLA64Qr0NwW9/E2LyOnpNFQBLMgmlYKvf8ymiPNce
sooiwz9fFBI1Kq+bvesyqc1s6NScINpEe8Qx0WhJifgO74Qvs5g2HezXr8NEn79LD+zNMnirRrvc
0HNINBCx3u51tmCBs1OA7T6w+Op6hy8dVumBvy27Th4aUM/yNBI1xwf0TCCXjCLZlNMYqhubiBAD
gaJiDRSTKDt/x3hhswQVJNmz0vmuX4UccMnm7iVa5suC4hrKy6jVRln8LMrHz0pZ63YPtZMYth22
MJ/pW+6QMSGrSJ1mzOpksqbpEscBxbeeAWsHAdlolErYrwVgYCNk69Zx2fkvOZgdUst8PyyGhHvT
IkU0C4RYinhOGy224PBuZ5opeM7eiOra9B81zvTUNo+efEATLIeEjRSyGMPQcL5Vl2zsf1D4q5j4
W64dD0k4GEyuYT/k8jL6BWHQpC/v4N+GB22fiWwcZ4I5Q6ZArKPR5lHVsW2sIOIMmitxckk0sv9q
Jkfn5YD9SdM7nlMzkT4DPURYNZmUeVr/KvauzK9betr+ReWguaYUHLuRA1DVwoAJMWV+Jw38D/Sj
0Rm5O+9hz6NMs5m5LNibjzgftLVTp+rZF5I8V9C/YQFNRZt2+YTdgnOVBhd9VMBmEz9sie8iAapL
rIjL5zmpVKvDU6KWk9huBjv+eU94JQwL0ejfijrV1jEHrZuqXxggu55GHP9kykRPsgGg7YsQmawe
A6CpRrsGlD71svtf/6hjZg9RenXI2ZkgMhvUuYJhUUBK3GdxmbpGjKVKIZxUBveEmRrUVPmSnlxz
M8/6JvHoVip1PJROEJG3GZtNMYY+ow1c0qYYTVOZi2w3dwygvQy4O1w2dGXSulLNdJzcNmQU8Cpm
Vp0JIF80cRtNNoe6coFKMc8YUFG5GeTXCQ41F5o5s+BTBlhzhQ2ByE2pY1uyxhYMxr1XxOOfzxBa
9mmL6STLLpTLQ7paI3UJnL0pxUZX3w6QIbV3TFYJZugLi5Ldqv9A3ki9/Gefr7GlBq9fWSSuzlBu
nQ82HkRZT0iO0653hVbtHmzKhhtvqorjKHvwOOXwAn9tY0YRGzlXj54zmRzFLteB0w5oTSfrKfvt
ZuZecxoNVF2tFyX+opMtPsev4YXDDBa0wau7M2nxCc6j/FedvmXglDk1C3BGW4TphRTykBo8rset
8VhvK3WltjZHpArwDXsgnjNabcn4N/fJTvr6iCQJBLoB/IwL8jHc1btXRHVrAimZBW2nhgKJC+u1
RSwG9CpWtkhc+UgCSz11niNBlse3O/kW/liwF8dOUl3iu//Hl6kI0P0rt7CrhIWUYCxVUay81Xsr
VmDEkjwGtUp5fVY8Z0kcjHraO7a4HYxZF8Nep00jEUzDw7pDHU0mxZpaKI2O7S2FCCwY1ozge3Pn
YlnNARvkIYWvbpxBwMz0SJ7mLaCw59C5MxYUXk8s9P+EgvOs5CqMlZ9K3H6fKePcIdwqTCT2UTzk
rc8rd1dNq547i95pnxkjukuPY+IiYC6yXJ09H4pv8Cgk6xE8K20+Cr9R6dEjGLGNk+eGrb7kXx5x
CEslSM2EPAbny7ZzbxCTXYjCTIuPly7LYZ8vfqYnxtnqusb0tS8ee7Oj2jGxPwbYxHlmJlyt353z
GLa5iz5kjbiOf+MCw6fZEFz+2pzD6Ftyw+9FpjeqrSG1g3BxmhsLe0fZqVyXh+ITQST6ODqv9y/J
SwZttA2Yh3j0CAo7Eyy96CArhLWSARGmtdwNqHg3vf6UjPo+0tPhBY7QID0rHH4KkpUYHTL1uldK
lRCJDyzijR2b5iWRtP3h/dVaPlaIEjDC18UZ5NZonJ2Cv/YfcZA8+0UflxJtZRvzazVzifuWMyQU
0+ghjRvvM/sBWLMYIcycw15rUhqVvUVwmlBhgoRzI3RDRy3mRI9ZDI661Z2d795E4FPZDGoihxyz
qj5avvc6yScTMksmKkVwrNPrt/6Exh2JRvsUJw3xVTQC1eIiSr0Lv4e7HtRFjfhd3EisJHFQnd/4
BgVCL6QXNx5F5+9bmbhXBWoi/gL9unFldw7TsNKMDVePClce88D0MPgc2e8Syak7a7RO6Ekgc/93
Wb+I21v9UE2l6CkILNTLtG9xwcxqFd1w/k84PrZ70eaWAPWlyuC8Enamx3Q7ziY47HBm3AP4U1AX
wREj8btxA41KML8Rz6OqQ5ayCA57Y+mspUF533nUa4L2MFdi+8ojIjXwyDwQHUW/SSakA1ytBaVw
Gog6qaZa3qfd34TUrEK+3bBRZHHPy3CZ16CTEzGFMqvxzZPbna5jwCcPuern13R9KuHKc07Zgwk1
3LXEy7yLJZUDtQuoI/7DTbQ2KGkprBYt79GvzHPy7OPpnwhXsyekt7xlxfn1ly642daoU1y9g5AR
cuw7/J9AnqTP/A3RdL3Rifl5T5I5rYVXTHO+LHyAyf6hihxfF9XkRdlirCBJAvwxqiRseGQ6GCgM
aAP1sm2h21uzB7moNrMQ5a5NEQqcg+lZf+77KlLMJDXQ8mmScgOuxl4KNoprz71rXZediZVbWSL6
B5DehdYWduJk0wHxylz6DHgB9c0k7OIGsBcyuNg0UdTiS5kTa40aGzQ6vW7ry0mqJSR3pKerDqbS
qsagXakIjf9CLS7dqhktiS3h8pCDEKOUkubKFCkUu9hpNAltMtBk/OHcqde9qftHk42JHbYeuGnU
u2WJxO3lOYJsgnn4PFFY9b5TcAmNh95C4OrlAISr2wKEPJmAtt9F0kzNhCKvVwYhpzBnQsTaFoxu
/s+SRJ0jO0o5yB+QlsAcGQpPEfT1MzeSgr5zrAcnwboH0QnakmrIqE6vY0l4RSMKi74p5U43estA
WVoeLiqcc02dec2Wosip/w29+VEr0CaV1yd9732NJdSm9t0NS2jR456HSAXfvJkMcB4o8ShHICM8
5Pwvr6a/VIVwLFHluUNzXwM5eLFPorpYm9POjI8l4nHMHy3U32Z7bYn++lZ5Z38F/G6/vtAD7PPc
GVTkInrAh9MmF4ywvFl3K7WLk7IbLizegyV1v71Jbz3TdiiISCF2cjwG09PYyMl+Ei0NxoWfA3H1
uPwS6av4I0OunR9ybpJZpG+sw9Ffkc4oZAo+t3eR095oTNiTuBGN/mw0XIrHq7vZXM6+fPJqJCXT
Q/o/RIo/E7XAELQzTZTq+QLPoc27TlnWR1EIMOQnOaITnbdcAE8HnBKS0vfjgX/zKDIkv0uhvGhR
dd8pQYJZ1ooPfs8TWTOrhVir2gLHC7h22g+x8Wt5PZ5sZ6DCaK0Jp52bw3b6iZWS8syBQtdKogrI
Qkhv3cmIZnuCjlVfncmG7+Vx451+mWdoY2szAQcSc325PcBYXZqaPnvnkOF4AeBlPXgvCADVyUmG
o5FXFWmaW3/jllXY5hzGo45ARwUt2k72gOUoVxqhBKB9rFLtOkGoOKWRgLHTKBfvz6gcWXJbYnXz
4EyQV1uvnnRSJWfrFuyORdFKs7eFKGexvODFMvAVrW8QJKG92ReQWt2PyGTdmmFTkuCwIf8WvUq7
hK335xA4gpiwCZ6yFL+K+6MUH5bKgA0OPqwOuRnJGUNgLYgVKqMa34klFrq6XcUZcsYarTcrzOJf
KIQfqpkSRAZtERalhEX3p/iLigQpRT2KxrrOMnPc4Y0i/45iOBIfLUZAu2UkOZrJol2iz5KgShqe
KcMADCvwAqbY0eBV0P9WypH/Nl5WqHg0XzRkw5VpVU5lRYScJtzEGt5tqNLX6Bc4PEGoQW6mPqR/
OJap/FJF05pxQePPmuK4TBzsaYmieHNvpKwduO9VgnreTaFrmibEHQ81x0x7FJGDURj9HQ4nrZTd
0H4O8wGcNPlAiFhFrQFsGpGQmwxJs5l375fYgTqhANAnclQqcnsSswOiiFvc5ewmivyCtJl+uyUR
4Q5rZ2fERxhVjSGQhcTqsK5mUtJcPNmE6efJ2czQ9IfYtpWS6VGZ5wzbYMDA6IybrRrx7UPd8xsp
fzivLA7ZiCdj5XFbnIhVN4aA3KCsNSIk2pMA0JnLN5DGZ6xWRT52gCMfnMJzMTqz4tvHYbxKAz6m
ZBiv+QzTE3XPwznFZGa1bSFXRIWRxMuNvC4MkDTlVMFGJCPhSSLfCQNRtPHMoQN46KGoVB2Df+tP
kQYQo9xoq7Ks/JuHrGRtOml8IjcrufhMKUsWlkifmOsC1z7gCN+7812aAznQ+ge1g+xcdWqVR/zN
t7C36EG5aLfS5wdvEjurAGBmqB8hmt4lIVEdaKt1d9iEuDXxk4l+jYrikx53B90jGlktFELxhnZv
sivw50ypDgiAKpcfuH+UoPAiE3QRQFG/UMtD0GNBcwoPsJgRPrtfaE/LtCkL3llAe/4QTgL4ICcQ
hn3plXJKAIFg8YVZeXOimXKNCjLKstBKXOcoU5/kkVzU8mD020DOwUeRAKlYz32bHrfn91g5QocH
hPI0iunrOmJ3SOxb65AsBi2CHz9Sa1MWkvamknh72VofEPi4ov2SMKlcDwCJL3jWAu27G0qzIXUn
vMHHnMsCMsKRLu7SO9NKL7XnS7NJV1I8SW3AHLwyIgHRCwo+iomScko5xjjbpwuchJmuss7JqO3b
izR/B5c7w60a2GEeppbqnrQf3ggO20Gep2Yiqju45vNQx2z29F8F0HX4emkcc7bQ8O/HOtmgBhrM
ApUQFOm/VFdz7AqYmQ1BBwfk1EszQOVJGzkW8jlzny9o+KpTneEGlOJS4x+SCErjwMW17kD3Q8Ga
t9Tu+CsqJqIzuHQjbnm4yRT4F2TAy1Y3fv9CkerUbQk/5w9440/yXSu0SlsumSk341rShUhsyQdV
F6HwRsukj6ZwkFT8oOaRe/XU/lCGQqp4dG3kiIG+kg4uh1tOKQ1uiwSBjsxpumRVlADcClEIrLxO
wOEloDEP1SbPSXhO5bvHlYu8L47Bj32AHoptGTVod3vROwAuzbWrt72MylMe5pxRwgYDWsnzmSC8
Mq4aFY2H1ZVSbkNo82WuJIkBw4aBUvGfzJm5OGXlx80NCLu2oRhGW0EHiIwsmpdJmYsE4saXm4sc
+nn2cytsPVoI4v77hJdlbxLzBcOvjk/o6N3FLYb4mue1b0s7K50dq4EW2pD5av6YUd3K7fAydlzq
iqPZi52kmPx0E6rgmwq9/Ch1Dq5wfXb95HVTbe/cfJhnDIYoNQ+2H/1Gr25+jzlvE7GNb7bMLW/s
67j5V4ZKuY3sFbL9kZIFbkHdSRYFTwtfQeFk5ELZxsJAHSc/wIzGAqV81wfYgWb8o/LauvEYm3cc
mFGevft5GZmeEyo1uYHmG/bHm1yn3XrYof/7lZUZkKet7eCkdwp3wM6zET5dudH+Pz103AU0/VuR
lyYjBQ9a+mpnqWNA+exXm/8+dupQn0GG4svnR4rtOPCjGPElPb5oLG357SI7h5fcffIkbwmSbPwf
ClTL95Y5kONZ/O0D5Un4QH1krPPZPsTskzpdh0GiiHSHkP9q1QRh+ImDY/psMy2kh/vFNhvCcYZy
dWHPEkpkkqKTFhncJ/caLcNqgqJsEQPPblh0HeB1HPIm5osFjyR+MQZUA7/i9AUdwPZ05x2JYzkq
9azaMF+00rroI41mXSr6syuWcIvUeNIvwL6rVsqIlRX/uHy0/2oNvn41cT2EewM87Iy4XxKQiYJ0
eMhH3oxdPPlQwERNfdA8rMrGG/7i1kVa30lxg0OrrI0R38nHvIgv99gI7NiQmKXhduQutWWvRtK0
YxL8mdvh1H6LWK+zfWlGJPeAzog+CTf2eDvuY0yLG0d9CZHIF3By1CMrmqdA6+1zcOMvPuJr7pCk
6sVSSAo73KLpl5hWjq/vj1E3ZWlcmvLQChNRrQYIVll+RiKtLt6vGMpPWK42IbBoa2/aSbKhOR52
xlG6Cmp48QpHyTohz/FFyeg1X+P3pfBeRFrBYzv/UTO+eYJpyVkyWEs9EXLcJ8a4dLCHv2UYKUYn
KsoqKywntZ7MaQ/UCC44MUkj5se8m9FzEuIQI6fwqoxV7i5rVjO73LPZkWizoFrfNWVC6cZT+GCl
6w53j18S7V/0jOiJZMVuuVgEvWYU1Lumkpjp26thXNvOPy3c8S55mJNiHAVI9jZqy0mM0GeGAhpF
/tT9MlY3I+48X3eg0ZXePf756yWZhGcSEzssIs3+oI/goRDhAkLBKm5WN8YADy3PO5G4sumTsRqv
IMsmJ7Zx7kwn6yKFeDidIcpA1HWYboEBfQCKgqVq0udlshocW+hflmNgDqOtCINB7CKxQPWQj2G3
CM3AZX9kHWymMcIwLDRnsRXhe1kaofg6a4Kgt2eibethJ2fEXZwSlnFiL7wIvZAo0L4PSaOB/8ho
O/Y3nO3kX1mVJd1mgGfLhcl3ATfe2t8ADTU42DCPLK62avmY0Cd16KHwQBaWR1vHXeJBFlirpvcy
T1Kon8X62TRvRA4IJtP8wDyKBA7f2/EDJHaNqE7VEnbOHhwfD4BNVBRl6M438jXBZxdqKB5Qptua
C4L3i51lHOv584KPexQrziD+89tsAMrjkADQ+gQziXLgUkAJ+ffqIDTL5cP0WDKxUuhY32/Vhe+C
82dfDp3NlU7/5LBPp9d1SOwfrWSOWIKDHwrKMLkxaVNRoHXgz9E4lAsdyCvv5PsZ7vDjGbq2CMkG
EkRSuhz6dD1zUnzy12L0tXxeFLvZIOB2JLI161qR2X+YHcWKVKNu41jA7/Da1wjshsIXCQzce0im
FEDsEGGugCZsTBHebOgrzIAk7rn7YjwElNoluF9T67ARVZRBRW1YLu40avYBgmxZ0ew5sewQB1WP
zPN8f7h3vlLlHd11zBDI3S3x3yZtd0gR6vZJLOKRAyBYguksd/NmhGLpJOCs1X1P0N2JCA1TdGne
artheOAVGgacMFYBATJwycs1PrkTmrlcmJeZRUd/WuqNR3yGjROeRoOlDFSTv+fyAPR/nC0yEINZ
03S7uaSDA91BGV0tcKyWAb5UIMCcvWo588VWvjMjQUW4+DRX01YTNlZ800rOrkmFPdG8bSL3/J1m
3SIWvtoNy4NU2elOtY1oiymYEJTZswj5Xm5vxzTkxmxKE1F/rWV6FEC0D+XnCLlq+TL9Qcl2blM8
52wCt1qly2mgMr/6srLypTT+1InXm4UqPiKp1WAfgokHq7kShWxU6tP632GaNDVZF9Q+7JTuMAEr
WfkX3N002jNpnBKIM4DdGKFh8ZDtaIvQdxnjc+RCBP0RirXB3YTwSV3Fwa1kOCFz9JYQbfE0VgyL
hAsEUAN1nQUf5+np3Pjb4AL0EK8CeiZh5OC40BQLBKE0t22huQtnQCJZSLPlFyYjSkQXheAazgfZ
XcSL3+3emWMEUMEXeaSzmkTihqYQhD1dzG/nUtT789o35cd8KV+lRj6f7r4Q3kJl75zp941gemVU
2DYLPXxjT/jiyQO1iMjkqe7e1+3/eFHQWxkTEpirjkF0nnW76qmAzW48IfoPX6XiZiqhxnioDL5Y
6S3scS1PFPV1GNyvd7b3BsMGqytR0ok47pZQWyGtLMqWFwd4GTsHM2WAKn5l+X5c3UdeQ14HkhKe
JzwCXFiOmJlZ470LKHWEULdfO3GLA4/UTFJjoD7ZHqaoAxK+K+RxNDUCcaDNOb/6jTtUfP8nsrjD
LP+Y1Buy+7gIgK2PhrPHHc63t7yfNqV0JFv5iNYJ9Ii6/5++3Tr8YDQ+0AXMr1tnnOm2bP2LgqWK
dPqJWVqUyaqpOfxVJh1RxAo4pa+IjfiXEw/6sqxW0fijDqtiroLLPfmpCzChf1b7GKGWW1mXzFCk
Qzb2wcCC/d0opYKX6kbh95lFAyvMnFgqJIlRaOgfrD2nu9bg/F786krA9zQ/Uc7N8upCskVE96Yn
wpy3WNjUJ6Mfz0kl0JrjeMwtRTFi2KCSBxzV7Js8Afrzt0DbHSlQWIp5GPCO89qIhlcQ0K1+n8LQ
q74mOucWBl7AOZBZoDGhTri/opEYQ9oP/VH/MdxNgr6ESSMQhY/IZLXRv5Pj81h4fZLpKFc7m8te
ZUYt3cICoVN4MqNuFj8hQeQubndBZ7OqKRvsBlrsiZ3CPDdN/aUvT24j16TVHzixh0JXJn+bNHWn
vCAEXkvxzKwRRmx310to2j5KpDKZ4WU71Q7YREJqHzZkJHShS6aYkvDVM1eBcNm7lWbtCA4XnQxL
cQVckEAl6KBfbIMcS8brQLuV4cy3XozGkTV0x0PEMzr7h/c4rhWUhhoYptgBLmIsB9A5iepAVbGZ
+8hfxSRNcLFIb2FlKNxqwd6I06HnAicLnL4MetyUCh2c3eTsoqCAsM5IFYgM+cSjCIVStRJDL1i3
OOpBepHV9yZaGjOgyEAXvAZVRwRg9o0v26U1mtm24fLNQ5uYheOl9eUvNc3VwWhY0ZziecZXUksU
iEOfIleggOGhUmaAhJWD6wNWf3pIHkrhMedMVoTEyHF3CBne3IxwxpGeB7AQTDvdKsJExNnK9+q+
2nN1btKnDGs4aJTybKIwEbUCSXwmMznTV2bwqtT+oQMOvO6TUIOjpSRvqoucAXeYFH6TFA7/wsfY
enKgHVQuDjg9GfjzR/5PNfD40F6YTIvCXoZkNEuXsG50hYCn3kJNaCSfNcBgT3GMBCA+IPAEb+g3
ei7j70RtI3HB1GpmGAk2535/RSJUFup0OPln0OkfNWmqopyhVnEFho9Y0XDPuAv4WZrLAV22Jfzf
FbOBR4pWoVhLpUvdyxXrNhXA48sZK6zVVm2SgL073/Hk0WrHNmo27WWKGisY3l0rHCvvkaV584C0
uCzw2ImNJ6lAR2cpi1AsMwrhAmXe8s9JRAfag720d8HvbDb4Qh2FqWyvr5Lx6995A0kTUQCLWw9N
diqHV+9037bXX1uGm/1f9b7tKyUt8E/Mp/F0f+pKSEOiPmfjg9DZl4yTGI3qLnNOvxobMQ+bk79P
j60obiwwPXRs1sztUQYMUiMmex2kr6GqpJDv3BFTzLF9wBl3o7uJJT6MbNqsKBxMSRqwC1vz8R3J
C5Cs5KhgNlK8Ei8DlsKNODR7zOmFF7XZcXwJ9OxMDlSXjo/gTvDwze5Hgl8QXUFGlucGR4H0WGK5
CyBGpp0Vim7ggmp/54HUFAC/yy1rihP8rCE3khk4NFGfU6ZgPMd5VTvWjIfL3osnUON7+rNSVpLl
OBL+HNaSQZku0GFOOfmJgy3NLMxrNgHbhm/gTWqwQoM36kR2PDAAGSQbE27mEjI5yAj3foTKN0DH
UeBL3ogn+G3TecwsGc95ZnTlHdBila/Ca0uVCzf5NRDgAbWyMgNKJpB5tGpvqyLUpzndLOHz37kN
BVMp2Qgfc7owcXijutRWTW3Wey2le6hvVLe1BPyqaumimVskY22CamaP2LAZH+lM6mRraADg/6//
BMjBIS2epIqiC7QxfQhx53+zT91Iexmf1WhdGGNo5+SAiptMAsspcp9esFZw8NcL4mVj6iEKxLX3
Ir3wnmvagjnR/QEGNZ3flMkZsrBNDiZ0BD/Vz4ATCF4LWm7tg4OgfNrhD1bkRSy9ObKYRLA/gDBK
DrVjzSSMe8Alqfbd0tkSR33jg2z7Q8cgH8vEW94up9N1z9bPArI/jeScI6DAPF1N59jEtAdTLh8s
2Zxhv5sOYoIEKGHUPFD437CraCSsmLYmaQHzz6cjjWY+EMcgMI5K8MD6x0/2rtn8tHdUTbkvVq+E
YDPR+bx5Kk8ryuXwVz/Rxx7csVwjO1seboCuZ26TwTAXt13WoA1x71jRudD09SxU6G695ZileRIQ
jQhJgftbbu9klNNlrBgsFA1ycK8suswe+Iboy3MCDedA9vnaKlIQEDPwlHNnGxSMVm0OMRx1VDOW
rWh1xLn7zYLZ3V/NNStqMF1+nNjNOnoXmWQ7rmPZVYHftIzwULnVCJ1ZqmV1ZMymPT1juonTUCMn
/DF8vPAwE2udEoQkJyiOjV0mqdg/h5A5ITdMrO4L8K8qKPcGvk95URu9cg6u8vzjr83n4+ynaNOl
sndGCqWdSaP3thnCz5hCEdffJQX3rMfCm4l9yh7ZMSFpmUw8KjqdI8Z6KvfYal1yDgon4SUzrf76
wHHGXfkSwQjuXu6SoFlLucB65tWlfXSS0Uu2jWZu1wmL37NpAFjHaEVAN2kiDLkq7dcoPM8zWyIb
Z3NIdA4+ZDbXZRFb3Ch4rpPrHzMteuP6b3PNZFOip3JJCNawfH08H6GOpY3LiImSYUfJv6mLfW14
vM2FCZUt81jkzpQu57sKVvJghJbL8p5ARE4Vt+2xzRtiUfTz57+4fhxFDX818m6bMRf0FHbOd42J
D1oF09ewApB5ZIvT7KP0kzuu+q0PGKDO1OTV/kJPfMrGTsjpjfIOzQXBlUpw5ylN9VAZbEKhlU7Z
7+kv8yXZ4k5+IMcgwLb4dcFM28cLWKLHLOoafB4XjIXxthw57BkIy2JgkjoxUGAWsYPcsXQAqt7k
WcefrF4Krg8YkQeeART9HMHcUOrSXlconWZ4O5vjXu6xPP2Bi4RSBDgqF9YFP6qVMiMOWGGteXCw
OR3AIONoSy2m6AyBACxtVji3B07eCfv/lQ8LAfZHwq5XnbYJhrpTM1SrhsgnJOjloH7hP9NyPt8v
REpJI+1naI3HQcj1juwgQumOA4oOyFyikQL5HmRlzNhSNZlPmFpjVJLY+qGqdguYY5r8YOwFfRW7
hWuRoK//vYsI/Z4FjTwVxvfE204Gvv79C5SCT0ODEWs5eJgvw28rD25BjzOmJXeM4Vk564tWaH/h
WC8izR0EAj5XbNL7ZpuscvtbQ0Hng+WpwYuRMDxfdoaYz4d7M+78rC34/WDuLfn2ccBb7E+tYS/1
yvW1yxSPehiGqmSAqWKRGUfNGu0KXFPFUNYcCANtleHgh0GfoqwgqSSa4c5DZiMx6nn171JVMgRn
TspeEes0KFbwrdQWkRzN+EkAqxdBebBDZJH0UehXNon6t2atbYM9IlGNJkB4h3Arm79zxzo59UTO
rPUkFto1wdd9NoV8jnsadMbcRixWybKK8LgZaR7zMBWvWnTySiQyvMlPZ2B/5Tb8InapnMDYPb4s
YBl2HJ9YgQEwV2kfqzQ1bSPa7zind5bl1cV+aeUL62HsO4PdT1ISWIXVNaRAWiwfRu9swZEYDHpd
phEMP3uSnR6rFAdEawbCh0YW3jG+RXmkLtVeDtl8O6iNBohqpjn+aa289an6gjdfVsoba16Lgo3+
Mgd+SZshWpChesdU1sBobmxgwLPO6hsVBmGIpjv8B3TNEwdkpWfA2JF/U8kyfLajwHIux25o413Z
6JOL5ZRMjEP5e4Gq/DTOav9dYzs/GnJXxdyeCn+eHTMRyfLrZFErS0Xb3r5reeweB6cyELWGSSl9
OZjo74VoPqDqPDQTDh4Z7V4ZgctNLBPPstUXgrapKAQn6nzzd/l2E5haGuF2CAreOHVxPwLZF81+
1Ub614ZHxi0CT+rmPe82Z7HoiDuMKl/r1cFceAFHP56O1xp8LkICNXiRaa9xIsWPWZJaXiNi7/2N
vNiKiOu0nfXKC+aIsbyx3mNGPi+qmOfNfegx+9vTnUcK3RX7z3ciyRCmfFOWNgQSUs4YBf2JP5uJ
hHTM5kQaJvtyBKFLy5NTBhkwOdIxvv6LD+oi97Cca8cSSFuh2nEd+wDSpZGL4EQbQEgSD4L/vegD
iRmtAuRmAB+KiYj8N9y9Ih1DqJ/yuERNIIXDFNNMpgwLYOwDjTxTV6b6eNIaEHeNQ2OB4Bk9Y87x
HNY/7b9G1kWFyt3tDQ7F71K879mrK36yzH7K+HMmqnYscBZc6QHISj6L9OonyJDDUXSb7mwmwd4v
R+k1vkrk1UUYzVLGmR7Tex+4TMT3+kZ5jtaAKOC4lc4gIQTcs0JSdBHs8RFcnr8fBBucecrF2N1M
b3XqGnh87buMfPTiiK7SirKz/HfOFcw5jsl6FlfTKE+436e6EvUMMzi6eOBCyb16TCgs+t2skXGY
0YdQW4FERQxbEnVJpuSGURFoQx6ewAOmgInehKRA5BryQSf6pJ1O1oTlU4d3ajl1h/t+qppOKLRU
eCLemWsW7ntHiZIGgWoJOfKGxnB0YvoZZFjfQDkGbrTzJHa9pc3BAs5XgUjwf+dNDl9LUOuO+03K
MEsJohh27fvcvVP74Q9EHRrce8xPsb2jtqTEpUhzkjA8U5TA35VZw2uBxVi48Vj84UXsqaoYgkCg
Cx2VYPZZ7XqjyIROa0n5hV2NbXXDgZGeHu89mihfOhgYRdmhwTuu8G9FzAQxLPtB7yaaGGl68Ujk
Ey/MU9ucOGMsd+K1QM5NeO2AfAHQNK3OH/Q7N2+g7cXKfhBge9NN1jhYWck8jMWjCVAGUXnNC+0n
cqzX8lsdfzDvGfHZ7OlEINKC1VGg/YudFm6t3X87xZejlZtgGiqq23bhqqW6gIaeuWvRjKCGAzNk
EcVeOoFDa8hn3rzk4TBOl0XawPk3ZVRjq9JIwk1lnW5acTb6HneAY2Jq9Pfbos7RTTwKjN89mfT+
iOgoM9HRbDQWs7NUuKRpMe4gRVQzOCHcgYHTX0HHz0tkSdcHAETRfG6dhUpCAjYHmFD+rYhrc2kQ
ghD6KZWzH/HsyXeSBwNY1bQ8DGWwS/2SOGb3y4oCd9N/w2la4zOZHjZagyAMxrRd72QfzzSVTfvY
Jw90+aL6vAeC00mGDxLzuQPkNzeZ/+IgErx4dip3FtrjfyTRdUT94FDpRJPhM3Htm1OMLb/I8Rv7
hXtxFiG+nYgSMAv/hwWj4wm1EyfqCxPx/kX07y5bfLK6p7mHqaEXAdeKA6i6en1ggMxhkqBK3zFb
R4YSGuY4JoJZMt3koWD0E+qoTPWSAwmWPEWaBmBA8tCUzAx7CgVOKTOP5Tf9ea3Ak6sJl8ROnFWT
1hdDrZTk55tfd0OC658DkbJUVtfBAHtAXM5W5r/sTquRUZsyKRd1EgzLz+aJr7DLQYKxRaniBILV
JKSXR2zhfLXn9O1ouDt8GiwOiG7SPCtu9/io+m8g2OQbrDnypY5fHslwd3qdgSUhjvuYY3GJLgHX
iF+6FcO0f2ipX98Y0tHc5odtIcuWRb0iitDxVpfjSFH4zx9IUezy3g6IXQH5VydlFzvL+kSl3xTB
I2R7xGjz8K/2IjZ+AvfSGsbqU7NB1ug3ugqGIJJjBnend1a3fJNPm8xClWhFdPxfimfQnGA58Gl/
ncyNlT6uiMLbRUH/cuTi3Eeojw0yzNr5a4wVTGclOkRkyeyybLcxcDbvoYJfurm/wcXF3HEBfzli
QFacIE1itocUrLMtuEiRd6j1BVs6WwivepC+lk7ICktLAaQVkmGCuC14JZt9ZT5Mhw4O55MRf7aN
s8waqziT7AHQ4ahEI5Z0DiEgprkDtRKbHSyMbAoeeuFhxqj3DmydNLu2XYgp2Zb2ozDG2UcSjaH/
3VdCYra1Brq+/mGDdO3/uVh+XY7eqk7WWNwGsKGoeOVC5UqUOj37obXvyRzJWctZSyyKvXjvTcF9
RZateqDNE2LqREz/dqqAERrkHQEbrfcIXNcIPQ+th/znqa14NnS6TEDXAiYjUWqdfgpvewAvoKek
0Lxh0OhR99Q4DraLoXeDf0MPEc2zMUC/tcXtskM7Brqo8QPFOcVVxrqJvia6ogf9uRAvL2mfj+5y
TdqKwrO1aFrqi1D2sTRYhaXmLFxGF3GxG/rlwYr+XwSHRUMHidS5Ofas84xvjY3QIigux7jhi+nL
tsgXTOxXDLTXFCe9GF4P2cSseLyWlBUp/ImuIC7L9UutADDoLmYRqZb+tCdB3M+w3DR8RlWseMTv
KWUhimVG2ip6UgA1CSu0xCP2O8RM9WSWsUiIRoZBlXec4Uzdjtm2C0OkrH0XaodoxCFWEBi7iSZx
0wGfUJxbfSz9aZ+zvw1GwygbWLx504dJ91uu04sE3eut89Gw9bGa6tiBf3M279T4m3SyyhyLRFQG
s4+XoeSQU3c7zmp7MVoPOYTmVRAhS7GLUbAt/iHLL50SbDfmVx0T3JfOxzmcxC4OtaBrpZqvzwbY
ynaliqVl9+JQ/TWUQXp/+4un/gp3fNu8W/NM8Z63dU7k29ogpCkUdmA6W1feSxeK1l8ZcPkJKwFr
wkF/ZMemdU6M19Y3x8N6u7S5DrgkQY6grnEsqcANyzU6qOxPP6l6iiAMFsQb2ZH8Q0yB2VYhM0wC
gXbz+YIJIxycoajN83pgsXM/M9/4jARtiKU9l3V2wfQt1Hiadn1uthMXyAvkTZ+zmeO9vT1PKRLS
ioJcpLV2HfgTm2PyPfFuylthcLT26LjdR8uNBVxV4e2vlFWSbJ8Fjbn5ZThYpy4BoPWw3xjw8TIH
wlSeIPObs1ZL0rRTLn96l5wJNg+HNukvHt4N6+wC6+sgaINnyHjOVh6hmEsJ2QjPXNQVv+uO9G4z
YqNMrREmjnglgTc9RWCnGtzCeLoMcLBHEWBuJyNTnBDIl8c8yuwmDlQYip1azQl0f9CqhETrvD2+
VMMDsXS6ZBb6wczlM8t5YuI9lPILaIngqGAYhp5BRfo57ZV4gbKy0hHBZ1IHMliZGToM+cpGxBsK
zly1yN356hW6YFyuXjdfHhe8rEI8Si8LjlWxKCTidyHkCNQ2kCv92C+lJeaQBRciwhOmtAT6dc6b
fztQvQ7BEs/PEJuuX0dOV7+H/b+xz1JXwI4fjyKA0iNtyjvCeXijzOR2VcOs7W1KBHqK6vDTmv+l
3vDWID974Qkjzd7DfiStPh4JJOqN5e2pnY5+DBTgfwi8h/Y1ibRCqHlM4dPTE5G9cLxmCi+MHcBZ
tQgYWDb7vdO74hD6HH+16di4sy8jPDnyLCq95d4i0eQ4FdPPEbAAM0DjLib1exmRjD1+we1uRO87
h1D7c2CnMNE3Isd25qteRwUJCGHR4I+AqW+1KildZNBf3wrzkL3a2vA1mNky+iCta3flzm103Unh
IbNJ3SVN9IvV2haiNRsh/KvGcjiWtyr2J5Q2SnvnWI5hRTbFt4M7F16YmzPxM1G5oSk8cy40bHxj
U6dpViULj5+DKTkRgY3dEFt6eJC8bB9qJZMpU6Ctf3gW3wjIKq7fnK4ezAbMZo71/ST3PjYoYFpF
tbJbMcTaCQeW9PCs5+oyF91duXsUbi++3Pi0d2EZ3OqZpTfAEBIokA5xLAlLFa91n09SHs+vRS6O
uAQDXSQXzU+emd3ZFNyo8L+XSV3BTxX75Ew0HwOWMxMN/I3HFdtCKM4eUBYss2epENbBxBm1wGLZ
3EuGt0sxs9z99bxKK+Dp6squtYcWokl6y8qM8Mj+c3c+L2vm61kIqtxHCJV7VOKYAHXzFVBG0Ch4
/1ttD5EhH4zq7xATlOObYoVPKl0dgjRXXhR/ysfeen7OfNTWB8bp5lPaAa0jQ8zoVfDsYEWqFe6x
4HGMSBj1sHyEPRxysemTUEnljoDxI22CQu+szQ27Pjg74It7llEswidTvQHJribLuLaJPmJuOp3N
S84xmUif0L9vOxx26wXjFh5Ox3dUi0iiOdSnWSgmasmCGRAw+DAxa3FBYL/ojs9IGSc4Kh69ay3K
yk0uz13FNDy5S9eO5i01UxjqFXY+beqQOLBjA0+sAddq98Pe/JISDW4LlzIvGepawLgZwX3vcM6L
Remh8rNhVOz0Uj6m0ZtARhQa5q+v6t2uhd0SirgaquvVpo+OjpjDpbqq9wMstJwAA/BL2HSRA5TW
xFBWA5Yupr96lr7dkg/GO+YPXEehYIButMyoJAAlRS/jUGiMHYAHWWOM6GIIoo5GJB50aV0jPqTf
wdfdT6CjFA2Mzwv9j8apyr6NkMRfpslry+wuBQMiBGi1IwOrQujgeUbfwVKqBCEg1nEtrJ8QhzHE
SYUo3rRjunB3RKlUPEpran9tkSomxUXv5uYz6N4fUUlANnYmCc3KUtm7xdAiDwt8jpwHaTnQID3O
zgJ4OdBBstLgHYSGkQwok7ccpqZDY4pWF8CeqKGTOh5wZsHvlut83/UITwDdjPaGGAdlI++Jy23E
wZpfL3C1OQR6FZzrTwWD15X5XV2eA8301Y4l9MJBL4vapzkrw99pPgcOyVFaj1uifDtG0EGArZ97
HYP8A83xIarlC/PTHUHKyVHksTeueHrUTGzykxa8mg5ZNomH7xTVLnuAv+qxgBKMYKy9ucNOY1it
OrFsDFKwalL5X+/Cm8nA4aoNMHzLuLquDPOdbPSy+qXj5SDtT0sVXyNRMwXFSAE3Q9LSkqA2E2+n
TTBgs1NJCPj4SZIXKHNyGuDO1N1NJt8BQrSGT4s3WbOgC1ZLsipBGJ0d5mIobKyGEDr/xLCHIM9b
QySYzklOK0edhJ0umwII6b9rEhvvPx0VzDleT0oWfS3nWQBqUtXdLTNNathUeDHI6rITGtsECiK1
kXUJ/vHsbKLg5+ACTP+KSDCUb8cy/HyHppksXUgSFkmcwSKZ0a5Z4QmI6tvwbN3AOBVO22M3rtOF
wn2lyU3APsYKmSY29c7hdUALd/kcQ6wHA4I30kW1yhqN2nsJNpVIskHZ0bXs0zrFyCeCGsfyfPJp
E2o3j4auvtFfuo1Pu90n2w1+qxZwELj9HiDlDmAZcGhA6c+Jj16DBG1GRKb5XFSz0PhFTefRuuGU
zqSU1PQhpsVEFuJM+7K+3OpvwIKDqjyxkY8d2ODR24jU0FQ6EcA4EizcvWeBTX8D5FRpV/QqhqQJ
+5oNSDkfLeZDFzDqxxQHAAmTXDPDzm5D9L7QXfoWC/xTDHrWLRzTB/FNT7xN/EdqbdMYnnqU5ZT6
7y5DavOCo4NLT9W6JP0CiNV2JsZb1034Gw5CJsyQTq1qkSf54mHOumU7SlhEdCLwKdwx9UJCTcNL
kIQVOJ7WgbwTczO2M5tElZ8eseyUr45AW39+WlYWnsVCNvZTC0ILyj+9Z2dHutv37Oja4HavBVNs
ZR8HsBkprLX9jC1NHzJnhvriEEIV0HGjXQz7b3o8HlIssWPUVRtajUiBppQnGVx1ghXhyE2X943F
T5F6huojYCmoB4KA/0lLQaMHRV7yHzUhZpfmxwRQ4pDrx3Y/PDwdj7tcf3HPItfHlGgDKB/ofuGW
QPzVq4mw3qrlFD/f/G4Xmx6/bq0XclqtQuaFEZ2C+psw5/J8Z4unSdfovCDZSsQi0bSEBlnQDZeF
vn4ChNuvBssnTD4Feuf6ON9mTLxSkHLjYOgmfSS+Wjelpqc8fEXJMq08dJLqj6bHGhCCnhOuLhc9
mZ41kqDy06KhSAxe9npdx4ffe0KVOE8dbNuwCLGuhtEwJScqjcUuYT+GiiG+ChwXOS0iwJj4n9hj
9o12I5XziNKW1zRs2EIFx4lyrnVdZ3h611WUkkb7xqrFWWbFQyUHvgeBpaQ85Ocw4IjbHyGb8Lkw
UgcDG+LlA8XiMsWgqu20oMoZOQDkQ0GI1LsvQgw0bYaRvc207hqpgTUcZEbW08pZRWJVCiH4tvDy
NdO4Zm+U1iS3yl1qdDaVfhPFW5pXCivM0f67L0HrZTapSUMVdjXhU+BJx0IaEfJHl1LsAra22FIt
tM9WVuVEi8Xc8EprFqzIpIP7dno8Wo8RuxLkFoGcL3I4+9HtqRhkZjxkPb+GDdrvA/UQ5ylutTsp
DZmOT+y58mn75jvK4JSHpcNquM1Dykv9kZKXZadCHXGRAB/bfOcsjP2mKiNj5JHS8m/BU9A5pKQ6
ETyPeAZHsQF5bh6Sy8xUmSlna2YJJIAn0unN2UjpSozCRYERy2narDMC0lwkRTMv/F/hj7T8NZXo
ThW7qzdX6g6SiMgMtK2dZJgtoXEHfQPwZsSwxOdGwpSABn0D6XPIK2MOwd6wo+fdmGtFLCSgk0Rj
Rdw1Gckp6YO1TK1ArjGgo3k6iF+Q89eAJXKXJP51yHoj7YXGGTGGatJquYJuRouNOA1cpCrxbg+t
7W7n2KNL1BYE6y9IReO/LbZA261o+lmakrMydjBp+3UzrWg3b3GwOGY59nzmln9fKqggDCqfNfEb
R3fej33dDK+YPWeXROHKSVlWu9OHmYXnJkqyoo5azNcV7sVnR5hxD5WKcb+Yb3rDLCeELXZeoL3C
sioFOwWhbdaK8ePxJJc+C/HbGb6LqCllRq8hze/bQF37K3cqYw/r5edEu5wJnwZmAd/+1LZg94EC
D6lTMOT32nr1dP4xuqeO80n51AM++wU34UQ7Ov75m/h6wgj5ckTuo14AyHmbkkJAG5MWjWARadlb
cPot3MvV/0c9ZpuS7wdH/rxfdjBm9xp0oMiZnQF/SnTWWQtKj2T6UqhbdpYOmRt0E23HPkMkSB96
u3kgDLHulf2Nw13EHyPPdIRQ7zSvSLgci5FkCvgWX3N+WR44No92C1YoYiLswtZOGF3RA8Puyo07
vP3xF5ZTyCwaPFl7/hdMrYSXS7VLdnawWA9rRhQG98YqOiZnfGaVXE5BkRflYRsJxAqyp1MbIhMr
gRNQa6shzDR2kV9Bnlgy/qKw8c6NqduWUjN4hYfaRrYC4Lo0JIB/rCkMqVNbJE0Q/42ZepXjoW3R
fAmTQvmAGudkwLgzrY/dGyGQA9PawGDnxdTKmrSvH/d7mG/DupLxivAnS0nD/pa7I89bgksLjjj3
QehMoZoJNUcExsEmiZt+bgxEpyq2l49BXyL3hF5DU88futRzog6BOcQe7CeUVYWdGiDhuj/Gh+kz
LKZ/TmuvOD7WR1RJ4YskRVAQtgz32cyjpaWbK9Cl+j6DJEx5s7ZvDOaF87F2iP+NUZoE4rpsHYtC
Jgj9BNjAx0zicI39tP9H/N7y31HqZOPEyPDIpfiU/0BpWW0YjL+fMMWYh+adlOWAtr8sGii1GF0s
Fd+VIDkwcApa2USHIZTyYDyKfoACIpFFZ7RvPJCxi3xrNJDdzy9k2EdobWRZBmaKs+CU+bP90S+7
meVejy42QI7b95JASC2iQa2RmrSVelpd9+Zg3rUIYgoA1q05neaIgfHWjarWycJkqmCkJmdUHbkn
8BAEnFQ12G/Sch9vq7ehDpbujQJkWOVZDzjbi14jDcABeIEBJ5HGjJ3Vxn9N8t6uuR67ZB9K8zxg
FIiOWoKTa99R5gAGYZ6xwptUdRnRNsNYdMkCSB//ICZ2ALLNuvvVAfzMAsZQJuuZnqmdFIQg4qDl
Ea/V3f4Ifry9edWSmw7zHWVhR7K0tvR45GbD+JjPLuomqaFpeAgDnYgQw3qjn4OkWjJU/bwD3TX9
2NZLMAC8b4vEEH6DEt+JGFzHkuwuh1yBgm+UkMH+cN5+kvyFSYxbmzI7wieHrEGUKq0nrLPBPFaE
0W+2QAhizFJxskheCUY4r3h68EjmPl1JODRns2VqoTd7tBFzxaKDuTIJ8xw+L5iyWufSswEzt/fm
S6vKY6btuW3+j2Lg8ee7iRdJL4WWCfE7d/BYS6ieVzhpWj6PAYOnmrkhG+7gZpSUEVUO7wyZEPi3
vxY48DFiRi73G8prnm8VD67QuvyxHbhMSDwgMT4w1KGDdR+6lvcRDfe/dxIAXAu6R/y6zTZMn12G
jxeW4QpUgfN2l36Z75vQaN3HQ9HSOBbMmdGMpSV0emUhe9/BtuzrkOhOtdaohNNdte7YV7ZJc7tG
ic+PY++rbYZ0yLpVjtNGns2vJ60hLZXIGYCGVOUDwmMHgy2eBepdORoZMFtWYsHIhIrSEQVwpCGr
xqGukAleuPnnW3NY5CZeoSfTStasVVN5epfMGFUEbPkiA1b2tudUduNYQ9Z6QRGFTmjNKMvPYWbt
dF/ZMWE9KAKAIZdaimywIrbxqVY+0+dd8Z4gW8ayS3Vk2+BjnItEccH78c84h51XzYQGmRw7v4mr
ElEqaVPGpBhu79RPi7zOCZfHh9YfYCxMToPDCUTz70MEHnm/soDvVYjMcUsMShDHfd+c047pvxBL
dwBuIYOPkOOL9M3QoV9XavRJB08Yr+JNyVQ+dhduI4/oU3yI5UnJJqaVKgr15KywUDr6Vlt9bzd6
qTan8CTIu0SH9z87zyayo5XPmzrEwgccYW/VtzTM8qmY8Y2uJ2Symkm9D2qiOJf64Q3ZSLwlRv2b
GLVTU1aRGq3g3AH84pvRrN0OWuvQe/sgp06/aS1ErHKHayaQnbGDZyP50zoNyr6g+316/pu6gNfq
T2FJ11S1wtZYORMiKfPfgEUBn/C3zGcAAIgS+OkGASfgKcdMzS6sjp2TJQV/zKwLZRwpvwc8x3bT
ZL7oHmk06HU4MIUf9XbSEB5VrHwmxW0MX+GJXj3jWF+UsjiWlkmi2XedIalyv5OVa18dlqal4X7V
atJWBpFD5Q1gGXhEod0VtM4q7N6sro36vczg7X2Otzbvs9IllOdvd+0GBqka1lvCrFbwueFT7DQK
pUMqmDeK92gNompwlXbEReg6dNnrel6rNVCszj1QLRc+AJzwVlvdeHMqLsRnDeMngmCChdqTHvXW
c+r6Wzoko6ZKrp3025YiCIstCHz0QUCV+dGVvF1Wnt6qp7ib6n3YuE7977UoBehZyJctg8YuDyrb
TSweyyznXLko90cd+kRrQ8Tn/T6b1NJaJ/xJSAIprFZ1Simp7wui5kZmIYvxHiD3oYQOBOWigsgL
LF4zv7UMXeBJyfcu2eJwTqk4pwqQ2JOv3N7S14pRaj+ZwuOwXAEhFC1/12mfDw8fwzTgHX6vossh
cq1WfKOddRNK7x71T9L/g2VaO/ExP3xOvRrP08OamtjDQy2Fagxm+2dHrnnCn/oCjkp7PoqfY8Kz
x6ORbo+QhKNaxuWHxNfubvZTnHstC7Vh0UBLyixl/lf/p+SOI17NUQ0eQrIyBG2GcrnjFzGMZpmS
pYxZSMlYS9jjCPGpLadjjP/rkZlGvbuXs+IuiXXaRI86/evOqXjXRlx9+KoEcluVsVJc2BkbQf3g
9HPe6ty22xY3mU0zNvBfMvuRzRa5hsOgeaSya5D0W0/yozRf2fO2aHzp4vyu8v8aBLziL/upPPwD
Totywn1OoysUZvVMrbK0WDPSP+rpkS6U/uLLf3I92NDKDjFOSRdMKav+fJWlJATRbp/37ZlcOonG
4+fzpeiCKymZvpyci8wN2bePSCvwqeTA1vhVz8WU3St+EGnny30p4tSrcHcpAUQR7OkpXVHJmjem
CFSd9CLhzR3K1OXURLy2AYjsRZ8d7kCLX34g8E1Ca4iuC7zoasD8Ey5Xv538ZDKQkpAjm6q6qFpf
LwEcMM+J9qUCskAcaQjW42xI15gJFRpyMrKccd/az6XG+ww3BcIA7PaWItQf7zYKbdNdCSFj3A84
jJdj5Y45rTSj2hEK9aaUrOVu6yEA8Go1cyPHxFGVVKhmiGlyWr8Rw8WccWB3HJ6h3YHyrATaDqy2
WoQQeHoMAYqLfI+I1Co4KGRWExOpVhYXNivAudu8VfvwVslqMnhFDDrHYZ+gaiuluMcF0++bv7Ii
9C5S2aCTw4b7BmgA4MpWgqA1PCza42oI3vHCulGMVnRNVSsABLG9jJHG6DPR8hq+sxwvatKyhnDl
Ohq4m25C3dy40JdxU6F3/5qzRf9lQZ3HRktzvCo6RO7nWFNDd2VorJI2C6sUEIb6QwG4S2386aG/
lyn3hNW+j1BKJzyBwa59tz0IeMjhjOi6EJOOqjcx9+4A222Ak83+Xk5Eq9anxY7sd46BgUktcjx5
qtoPwg/faFNgT0owKFMMqEEADkk359Xij1H39v3iq/3zoWa1gEtbRb+j4j97kz2S+HcU+xEUw3Wi
KkQQyJwp8tDw+5tegoM4KMYFi1SCOrs9xsyqp6xdUmn8fe5/viTUqhn/4yA/lZ09hQs8rPwx9DzZ
nZwcOGjDL0nhhM72yyWEZLtzag6rHd+LbiPPI2cveHxS4WT+j/L8tAZC4UdujIDxrjNFFn+G5KNk
y/AHCuypGigMonr0m36qOpdmNQg8IATqSkVgrNXkOAN3Mf2S46RKI0lgMi+b08NU6DkXkummCU5P
O2YW+kjq1uIcbpD6vIVJKKXI5Obokl1vfLLqNd2S+taNJWKZlFRcluHQhILT66HPGXuFAhZZa4/C
WKEg0ljl6QJlkEcYIniHI6Oq7SHfzikcdK5PLUzlIGX7qkHI71AkztIGbJBURkGzyF80r3Awl6o9
gXO8CwiKdEC0NAiBfeTZPaSwWMGl7EGvGP+1TLUq4yzqBEUUHV1ywvqVnnlSbdiicNX3w8YF4nOI
lnbZja/eKpxpvejA0KEUJ1Mci2QDRODOnYe0wLeMOmFYCSmfaZbDjrcaTqCpNvNxjQb1C6AAuMg0
QRstUwVoaZhRZKNf4uAIdqJ9URRigKyMzMENmiW9YOErdSxd1vB9lfiuSRtk/oqQQLCLKm9201No
2wRpVNZtVBId9wLOxC1zAReyJ0hm1Gqa2mrYT4UAkRm29xY4VJXHPVG0nKNXiSGDQs3UJYiejrru
KWdFepC0x1jinL9EqRA13GalR3M7eHwL4t8J2sZb/owR1oe17pNUtzlhvsagyWDd3r0922cVneLJ
DFz4eU48UV8dwPrvKrTVv7bQQZXFUY0usj/gFu8tyFBkTsvkzAooDTEycE6FCMHI9q73+h76PAUf
Wq74Q8r9Goi+B+xHzH55ibpWPshhBFq+7XDNygoQAn7NyzZyjj/V69CarT783CDB3opaCc2EtQz0
0cAQBewYMHk64QwbD1MWHEjcvzS/0NpiPrIVeo0OLnbOKLeNmGQarAMHuWaIdBpRp9JD9JYkxxRU
qccPWa7vitTu9S2d3OnHD1zGPhU3SKUcYjzP8SruYN6p7iZOemtSwLZuj57xrrPYHakbE5Na3Ebr
YhA6mbjPixovOBtJ8ks0A6bS4R5qwEbZv51hPpGgTtH3GNkeBj8nF0wlrCq3YfQVnjdeILtezW2u
CCWPAF0yczYIqNgkHuoQJaQ77QNGID0GeCWRooUolXacVaanh7Tk5O0gg8sBEHJ1JhZRVCDZOgi5
ZhS4F4HBpPNhkOeqIx700cku7cfjabQmlS4Kxoyn/E4j+ULO2YqbLZ1xSI5+vBquTkxzQRyyeOTY
K//VpmDYpDN9YAZzDGSKCpiIQW2Fx/90BPPc8DrhZCgM8jakWDWF41hR5n8nKW+fzhjY03jOfPhf
JhM2Dp4hQh3/HMq2Z1wzBRoDeYmhY8cmUtv6p1ARtCrC/V+or5B1f23lQrk3GuBwjpkkW3cDYUmV
UAYHiEHlDOv7AYeVODixAWV15gyHpji4isfEQOqJBHfmDOdv0Xy+elXZvRmzOS7xSLg9B1rox4Gh
HnWN1O5IjqCLuUhRVfvvUNj/sm++YrJatvrdpN+bi9WS6ivHFoBHm2JVyuDYHb85MyMDDFFucbKK
ESEbpVKLkcK5dnk5sD9p+MvHw8akfH3zrmTf+/6dKgiKkQdlNaDaIVn16wLqh9urPzJhfOIeHhOY
n+nlgvLExU7V6CwW+4GjY57+/VH9B4qUcHKZey3FbT9BKVuYnKyG+biXTcBlhfQTrB1KOvaBuHcu
ZEj0OwtmaCwWwZ/hlVKVUlz2yKj8/3FVYQHfuACXYf3uwKrR0GzTYRLoBcqkMWQMfAfr6u3fZvW0
kiPs9XjyEAsDZCFIAgnHs2QEeLHotaSvbyW/AH632HXxtlm87EsfxzHM+pqdCYpWkkZFHXJyPXPy
7hPzVdILa+nnLXIP+0/v9rEGvP2mv/8rFbRw+7ucYKaqXYr7Ga32mNXowdj2S8Y9n6b8YrZxGTWm
5JeTPDYtdEx54u3qCsPYhg2ugnh2EB4sB4W1igflREfeWzywV3NFkPzrxZA9DGUf84Yq2RXmNA6f
xe0dPtuKnIF4WUN/BCqEXuE3OhIDTssVq9/qeQ8HZUkvMsd3j41Pt+Bp5VoN+b52G387NYKCiZJI
yIiHjs0o1OBYO0ZIU6gWmwwn5Jk/N4trgFwPscrujEDKUiTFfRAS3SJH3YnueeNGqPRLO4JuTTny
0tLs1Z1DXBUOH3EChJ5HfnaIWWZwsivYB2vMnC5rROX3gT9VolqIa3eBa/JaxRwb57biRFZo/5eN
KCQUS9rdBaOK91ExtbK5RRM7+Xv+APd8njpbY9zhrEUBRoiLmPRGPPZZHZ/oJrAkiS16l0Emmy/L
vPD/k47k4N5Cw0MkNrtmwdh7AqyLf4yLu/6+ux+P071jysKKHBx1qjamqPexd2eKzcVouz5IXxkD
alwLKT2p4Iawp3aYyZ2zvA3c+N3JQOySfHLY8YS2S+k3qSBqG5g4YchrtnirFo6sX2M5hVV3E1s5
Pnp1zv77jPuUCNBXPxu26gFC55vk9rbQJcGH1YZ2FcUkHD/F9BeaykI6ovFRJ6g3yT001SRXpCCU
/S8QbFdt6YrhBBsY14jDwRal+ggveKswr3pJ10dnQ1kxM7gNyhWunJ2dwPHgLwbzDwMdQ2RhX9iq
BbFuOtWuiZlY0bOlBONSaAWhvS9IH/asDGm5fSRD/kPRnp/DIkXaA1XVCSJQKP4E1/rZpJbdowv5
KCMOUqaXDpFgu5uq2jlHwxmczG+3Rs1umLpAHqfLn38/EAoslCQuV3KZclIsU/FbOxyYYZXbMGvo
of2HwQHqFlMSMT2W3aFHtS7uMIA7rbJBH46l2xCclOjGc9FJjtdDjj0l7KdAbRfPGVSLsEZXzMh0
10ijh/46mkpwRVR1qtb7GL82vSwMFpRuYj3q2Mqk694iOjgJ1ishZdLS4jNqMCiN1Be8nJmE17Md
UvvzQ8oqnEtISAOMVbveDlIXhjjAhgn0zqCp3ixKyUVjzvVKsddS8jOCWCFsZWIdJqpjpYFAALh1
1E1kM1YtDIeeGSV8ivFciZrB+6bGk7amipR0PdtsrbY48ar/0z3r74K5JVyC3ozyH7H0UPI/OB/8
6fIGMr/mXfxuZC7Jtwjso9/rbJrCzQBMuYoNsY24iAdQJlVNCiilSQ3J3fmze//P9FghmWyXW1GO
2gUZ741X4M0dTUSCZ6jZ+5lW13ROESYNNUf5kQxvKoZhBE5GHGelnTZ9q2VO4T5kE4i6TEF7tzdv
5fDpDg+1MFyLnmk3bI6eFqoFQqDQgOJ4fbI9t2AM2SyMaKFXy59RjVkZrZHpOkuxu4A0bKBO90GA
1omKvQw2awBKR4XCiFiN3gxQ+HdBEQBrioJ+ZcyUTJrAHKF+GYKv+eJJn+JcvKIPbpFNm8CayHSX
mKPMHpv++6sCZTmYHEutdLYXLPn3wJjmm/x6l3jhuB0nmZF1qIIiu/SlkDlwHd/hru3aLqqO9HP+
x13dt99RN3QjyzkhJVdOJ7PZBhNitKaMGJc/BicVCaUKeBH40ekryzai6t+if/GH/4vL9d7U3wKK
n5OSMnUNN/vTpzfi6yLyC1J0CDKS7sGT6F/ncaIEDIZXbzTZX/JMEbKqqPmbHv8TkhwW+GFjcH4D
K2VrQ9PXGDmxPfgEpP5rAm7Fh2OZ7tCn25ClaVIu3W1XxNRLYbPZC8RCoTMaUaNgIhmGjGRtlPw3
FYzHJ+IQzclY3gx58lLhILRwHMmZaR7GA81f0GxFv95uy9FNGMbubkna+wPyl7i8eHrkw+on1dNO
ES41OjOnILEe4hsT7bBuatQe6Mmqd1I8JMJ1zUfrdgWHed6B8jIbvYdsPELspsoXygQo/MjoMBdH
8J+8SX6F9SepY0x5mj5V61KnvYusqdODLZZweIzB/w1j197pwWtm954lKL0RLTLTzVGgZGaAEYv4
k4Z/M2g1bSLBweRsav7UkTmLX5VBQcQahBJw79TZSaUR75AwaN66dhbLyhKsRt/9c45VpVf4t+Sy
nTJPTeeNbj/sTuBpgkwBVx0tdAojWFbYHOedRnBBZto194+p4MoEc+cPQoJjHT4HtrtA4RAjeT+v
JjbIWNFHjF8LDL8zq6xB2WO2J3YpeC2cIJ5jPWEaq7nJJpGU4YrRIw/VBMa5/qcyzJbNrQiBeGPw
LAQi93n5UjInA7ut5YVbbcD42aSkYcFNjg+9Mfw1o75mgVmkuT6V0/b1UxYNboCa5RF6Y204vavu
4tnZ0uI51mNoVVr7JpcACC3PGTS166VNWxDCxPhm8O7aGPKhiIpXfSO4zeumCv/UGGhwOll35mTC
mvCl7hjCYdiioabbKdnf5fStMgzLfUb/HOINH5OUocAi3QblTSYIlgDvdZy08/th3V1mnaoqYEFK
PnDOWKm53xc4vCiRPyZRX1GSJ7T7TkkcSK9Eo+rL9bjSSH9IicoB8e8drwHpzCLPP6DMvQCcIao7
ca2nysldTDVmsinkKC8MAUyamfBtgLDkDX71aZvPIn1kJ2LTHwtHhG/NMnvMj4f0IRb08G9noaGz
2h1lsmZ1U9wCqWOEAIu5UuQCatKZEsCFHK5p33cNxNj/XV/tXohUGT0KfZGNHx0HJrDT4XViBJgM
AfwovbImp/n+fx/wLT2J4BoqNqr2DN3U3gU4MJAMPFX7ETLZmwygOg2bmRurZqpB1WEDxiippEz6
qVR2W7Xp/UbU6MRYyOvRbmr6sBwoXr5W72wKE35Xfq3HzGpTkGnJvnk3O3VfeOAlIJG0OsAgxU+7
azX54ZmgagH6uqGw/98ujrrUd9TYKytfHSXDrHYMpYfXH7GgWs1WsbpC1Ih7F0NKWo9ZPkBVTRRT
JeFatu5rqUtrvCkdGt4z+TJyTgXegiZ37FM6uGaDADuUpzSQJkbKB7WabOBweT2NlCFMn5Riw9sU
mPmjGc3oz/xIEA6z4cz+vJStme0iuj1OiJW/P1CyqQ3lW2lCA0PumjiyAd9NRwi1E3ape/ov4t2J
mW23DoPrvGMVsrDx1TtUqxoOp8+xHqL36OFPfFqWXvqmUXT6SbWs2npl4ozEkcodmgJcokajD/P2
S+KPTVWNTb9Ag9tSoNXeCijyGP+eg/INcQHNodkIzS2w5dYmz15+tLGBWxjDV7dE+MjQO6Y4Iq4l
OJ2SSTio+RRAM64MYIIbKcSVnW8eO2iGlYLxmuc/HNFNAQobk/2UcRnAZX5nZmMUU53rVRLV/tFU
J3lWf+e4lQ2sWxMVYebQYdg3sDQrXdLa271w1N8oblFUESfu5WJSay3W8xas6MBaFZJOAs0q65k0
0AJy0uRlyrFj0PTY+LvpQlAHh+TmrGQqPNjXP7sLAZeYwwd2et6IiwtLr+Az+hNKo/2NxgrEYXSe
mCnMb/0salSFvRJUYWsqnGvfMLSWCysNoiwknFfdQdaVc3rsLKNbrmXMoHMKqpafJDsY4zDoOijd
2IoHsTFhDWanBAfisd8dLa0nGfa1fhoDQdRbXXtMVkXMTrP0z3VFG4IY/7TMCED7OwZnEs/NgYEP
kKC5FdeN1hbIl8INCYtiRWDLY8yWZk2bwywN4H09dWgwI2mb6hirI9UO54OuIPrdnwkHJ45GEjpc
+dihcKQ1jErkhBvXT0CP3FkHfQxiDfE7CwUg/cmXIrVKUH7nSY+2n4WLLIg/nZNecwRkHmQ57CTi
RJusQg4v9zFduqz9RMa660/L/ggDevmaCANnJ7YtAVE/LceIEdB5giPH9dqpn1BMdxRk1xlLi2fQ
B/JtevWiwALlm78qgbYV742cqYu/zMGGz8AwTKmxmZeQF/2LT27/uq8xvUfxpH00QUKmceP/Eit2
GkJZlGoCvqisnbXFsUocio9LnYOYFV9TMY0V7UjiARW5RcQvli47Apluu3mONLsZ9aV07EDSlRm4
byjTxW5wDpbny/+BSBg1ulxlPaKrRhbcjXqHlORZV3pSKC/B5vJRHRy+X4ZrL7iQkcFH8jWQcD+o
kVOPrSMelyr3JldEsJVfFUNSw8/4NzcPC+kdIHGsk96+YvhoOQxpRI92pQRr4Py72a+OpBg7ggRU
pFPauu0BF/HWik1Vgx6p73ErFxuEIwL4W7sHHHpMCBwRLmVRT9S0G1KlRFbsmH3lwM49FBjzq3VK
xyIeYZ1rNjkkmo2tfQ1rkSHCPcKrtAqLAal67B9GX0A9/1wwDik2kTZ3v+Pq0RlVndJBorM8WsqQ
T38w0O/zN/7y5EWQIN4xiZeszP+rVW1UmanSlm4WfFFU9iHFASstzn4kqh39Ec1zjD+uTJk4dNor
tksHCv4WgSBqBbm5oj5mdIK2H7fv+AhOyYF4qs2CkNlZpAI4t6aru0dezUGPNGYwFtcJuK7bkCWC
oR1R8QHvX6C6+zQV6uPjMMqUJrx5e1TwL/QfPmOoAR/gXHcUTEn4+O5Wj80UrDdCad5QH28s27cO
v3TJc4WG/PNq9esSrtNmP655hQgl1kbMI9ZOKmkLhH4UTO3yZUtpAuEjwHdtKxS1FFhFEunOfQPA
bshaaO9HeOp2LMNB5UyUB9xlBlyi9CSNllsFBcnlu17kl/4fkN6WgdtYExn8Pok1ZgILsNmFbrZt
M2mUd/yst2vLa4TXL/5Q0ozqIFdiGzjw4qZAsNPkzqvTuR1gOCX+1Yf57fEBmuNK8SNMU+Z1uUYu
YkF4TENvcSOjQ1cbrmiCj4J2gE0HA5VbbwI/r/uTVCjcyi1PrsVuDPGhNqm/PvZMiGzASia6EoVj
jKAyeK2Q66jECwDCbV4ZRlfqkFBK7zNqK+VKE9SGmCzNtchrNcYK4+aADKMLNCI4U7C079Ocmxos
lWtzDmi4miRQHFeK129Eljk46Gh6O7VQ/UrGRuQPsm9ZttiUSF1/0xtx/hsxGMIYfsPt+MK1cCV9
gTd35OSACtdBJZlCP8xCmh//Y5685Y+GYX8ZJJCyGyOlLMXdsvYKK2T0RDrV0nHnUPpY4ywN88fh
slUTZhUnqO4B2EzJwYKn2qT1axTa3kdnBOpAAkU1+QnUpUEyxYEu9DQJxpq7DN2EbtrDXe3vRBw3
7IPqdeamUWbxsKG2fbGvrhjPMqm7Ouj91MsvRetvLZf5o2HhkmAS/L4RgZOvdNPekiu3QZQcmGXo
OTwLS/cAxNy4pDiC3C9rD8ul1JIEWatZwaumtYcqhfyvCLqnIMX2jUT41y+ZS9/136/E15mKF8QQ
HBfFe0o9IVeFZP+ECBaKbs9RXTbagMUzRCMwhTQX1cX00gXXmm9nMDVPECvVE6kV35tmnaSTDiDP
ih2S2LvyCyYMsh1qdnLPpSf6dQk2LmXmvgsP4ecbyxvnM2F1VY7MfQLyoPRlhZVZXD+seFsRk49R
/26heh+DB+6hHXRwQqbGSPnEuHecUn+6LeDS9S5lwDlBSE+voaYrspzniF8dwLuNhG3J2HzRT22K
1x0JY/bdm8Xi8woQpq3h80ETLM1exUDBZD3jDY4IDRqLseghB7yG0XCVj7DJ69fJkAWI+OseTZ1o
3oHIuhPgkzEMQQBNWo08ubIbQ05KHPgLIwjM/QgLIviTbJsMasTcjjqgNQ6jrLUpDS4aQNJ9LQn1
gz2ZGqrkAeSwF16PM1WYTla5cnIE30aIp/uEswEcfe1gjJW7ChmHTP2rjB6l4LIqzBehNkyLWAU8
+O0rp8xb6lr2NIwX1J5TCf8bln5ftrGPeiLFIuA+GPrqT6JbGpBgIGqzLJccUA7XjNv3UoOpNt9n
vQyysUCtpWVFrJ0rfPZH3pmlY5nw/OKFdRI75AI9+70XtrlNt0MQXXPHA+iFtZmvmuPHPY7hVF8E
+bAvOIBh+pjq905JIap++Xg6YNlWNzNGfUJ6/pYYe2pcWldozWx0okp2s5toAytcFLPDZnH5mK86
wVkkuSdxAVwQ9Vx0Tp25k+RcMEoAH5ViTrY7YU03nQEBuREauu6BmqpUmExeKqB6k79YQLYDUuJl
Zc0Wj0x0wisWmKeVc1YltqgXrcyFsfcz9rx41/ct/E0UtCVY0F6snL1xT0txZoDF5OiVuPvz3q4A
024+ra/J/ltk4MvRbfhJ1Ea5UjvAERdGI/5eT6hkP/hQqiVw/bJtaS82V1oT/3mauOhDo8Byn3aJ
/X5tLoZIGObJHzLnStA2jSjTIF4waHuvscZmIpJ6PIM85ZVxZcKGInvhG98pgeWq/UFWzg39p+Uk
aRsACz43+nocwzqycdLfBPB9zOP0za2fr4rW/O/kRAWBbNPVbqVCqQPZa3GPGajef0xWNvUb5SRk
4X8tE2Gzkz8VTyuyFrHOp+cJRmbjUSmwucvanu+eBUtwhYh/05MxycBPcgUFJAOvBVG1eEfaY3sv
8GeBJMpYDtOKVnscUvFJNr3lD7+fkMCEXBNDrmdHTKkVQjvSkSheWKhBzqS+2ItSvZNW6qAbAibZ
gBAaMvjiCHrhuCpgM55bpD/w6ohxSUmhayCgAig2kM7bc6hMk1n4Q4V8Brmhvcs4lyTgHZefPn6e
yfinJauIOSgs2qJKmWXsj3f+0dHSAhh2suPSQWgeOoEzPMDla5rlZm1nfRZrCf2Z2qTbcWHIsjr9
BqxLbGJCusuFu+x4q8WHGZi4cAYq7Tq1RB+xEXy9u0uAiE42TyOLI1B6PsDPYORmGLDxZEsDaK+F
SE1ysS9DmksQhBbD2pOBeE+OxTNs6uzZpH00dFXCpO8uVnluW8w6sqcFdsEtfmjgUbBnPhhTfJZe
I24W2CoLVGYfQyCfmltfWxLtCJWUemKug6VNIk7xh1emy+KrpulFRDU/jqhGqXroJl2AHONcuseP
bjp+BPJhL9T10Bx9gvt2ErP1tWD73leZYjwr4WJT16oq6wnV/2gCtiEkfT7an0TB9V297sezlo+W
HQncmlS3ZXJM3DG2AdfV7TASS275EYMwoxcQkou7pf56cadxebDaC6bE1FVI2kxDk+oN5E+Hy7Sq
KCZKK9+fBochmUVqyAs++gMx3HhxVtAFzVwUbUv8rexDji7pLWS1AC1NpcgRDf7fE2uNCbf7Oj+f
nHzgBDF9yFIsc7OTFuMpC2nJv3qWGggqsVR/re4GKkBvCekMFAIzR13UYglk4EKfUSc7ySLBBouX
2R1j8p6hgKmj4e07l9D7UrLe0SkwPDI0S3VKBwZEs4vgJIEsrXxE1nNP+WblYc75J1keoy2bK4mw
1znBG/6n1LBF0suoh8gJ6pTJ9XNfkutIrpMpbQuHeIZlX7PBd/JEvDTpq6p+5q/FZsncZKl3H6Ij
hEzRIuvw31tp1rqBwh96GGwUIZ9YNozUTnqZKJMqlOkgKXuxLfkzU6gfZ+S1oRdGMrPfqknB/00b
69EpJsrXv0My8pudaPTVLMWNHkHylVHLGhmzrDpvtuGAQamNAvPkv+5yTnxr6y8g0najpfk1dRBE
JVw5rzN+A1CqCqoT41/fNv01qmvu2UyIGYOobstHjuIhx9HjU4eSwW+u/6jc4yRiZusEcCWwNnYq
RzWMhG1ZudS04TM9w7fYvhHST2DubwggpqYS3Th0nVjqqRE1rjgZS/BMruzIcuUrPUDckZpjFy8T
v28J0RYXVWY45NiIlAOW15z0hj+4LfzIY1ZZgjf2yb8rov29HTZ891OsufbWBYXKpwGWFil3ZLEb
Y/xNyUNQ/VxQTNlXHZ7MkwTgRG9qa4crrORtNr67N9ixy4eF6dr3DBcYM/ZXO9OV34Kz77AO5kHU
RARQdyoGS0eoyDhTnOE/Nf7inY0JeBajZrRJqT7rC7XyRCapavPxma+EQOz6C+LCzynpBZ4ENwP1
kWG5kwO+fp0cjQeG5orzkxdKrs+zdk8iEXqJGjL8JAriqzOr+MDr2wvW3dZ/5Nsog9to3T1J5zt9
L7cgPgiSuk+UHAIwQmI3DPuXTWHn/rNxOHPoshE94ainOVwd/raUdfZ754AAHkfAhQI9X1VYN3FI
1ZZb3BpYzjFeBwFCuJCZXoBDipg6G9vAcFo0QmspOlGgCPVmq3ptKuxruSrJz/AxqrkNI+hw9Rkm
v8tm1gykZ4We6aO7JdRDM3AhqnPiGPrlPnvLrAEl3w1z5mOWTLDReN2q/UOS5TuelogvYfQsjt+b
BhIehyuSOBojBPhcjsNganfwPBg3ONKdC3pNn5VQ1Am3U8+hoVMumMcD0jL7dlkqKZofGYZW+pXW
WK5sp9JUClXPcwZACX9fd4Hw2m/nQ+GTFbuzkE2iTEVIWgO7pZkOihtdD78ygTHrNg16+PNC6eoe
WuuxLtgPoHnxDrc1QitYX0El2RPON6qIuxdh/hhu3n3bAoTqnX+LVSbkLQxA1AErQXr+7xiN5Xow
BGns4aD4TzsxfoSYvEkaFyX0LBfHQT/bJvMZ1XnI6BVf6lYlN+z0UxrVHYPCp6272c4hojtnosKM
IHcVLv0M6HZ76yfghnsV4PgC0edbdO7v1gg/W62O365l6kkOSLwUgz+bvWEEcC2hKsj9AcfZ99jH
zGNuk3mST4dwL0E86IR+D7dGKZDBMLc1j0+MMUtBTQGUykNozCz792wbMGLLM61WzvhQ0CulIkQn
xoELoZbc6U+55RKDiJIFnl8RXv2ZMpy5FsKO/U5txNFn3lbEqqwARvYOA3YCkTVH6wTcsshqaBvE
LvQ+OAV2Rcam2E/nXRkANBxZaQGYP55R+R7S6ciWFy5uJxl+DGVXdP5Mr2oer1qektNsNJIjh1uy
xHhBN7PQ5gH2sCH9XSSx2nZBZ2Vp6LDtAKXeuWgKDbZPD9SJwbUu2Air8KwnjkAIqLnuVoH4RTHR
+NgvVgOSNOpUCNboYmC1QXIntBMJeBWDjxYjAym9umuyRx5K0jJCMeB2lQ7RIumHH4QvUKq7LhpT
yOmv3++2z9mBA4pe/qVKmpcHsTfxeefmLlOV1nHMtMf6nTr5jAtFrqAar3I0fKQRq3H5/mncIze2
wY45OxtGhpBRu6Jgw81u0Mj0nKJzIm2a5L9LbLD15tGBuWtCnS9DScSTTd5s859qIEBheGm7IWD0
xnMX6KtHa1/P81tH2rlhVZ0+F+GDVYN1KEmXVeTLRqvUlICd4IKZXxKQRW7XWJ9rTn80y0QYziSb
UvMV+0rhBKRCNAzxMUZ/qwCuH9yHh28S9sdfz7YBAhYfMsB0/XVLPkfpnMxI52c8PB4pb0KkaKoL
0yt1BGcOrFFybKGWuYe9fFk+CqHkbY18665hdqOtOxB33PW2gP6rFjnD+TYVD919lrgRsdX6giN4
LrbxYS48mzDHeDBHad/GDMas2lMV2jkyc9RrT02OgvIQbztLFWqOcplkH989LW6uWCHBejG758pf
ISjN4a6r8zCTUvyBE8c9jK19PBczaPzSYBADy+oi3rC7kB6qbqDqnTi6GTOTxwIR7hrgy+ht4LWp
kT2qaJ4EeAUXIUnRF3ctFeLNWqsjC++659z5s+SBHWwySwcP8plKDBQnvmzmCfW3HoqWbxbEgsUc
INZtPlRXOFiou+lkEn8bcnKeh3jPdtPmE4Vvfw+dZJjrUbLPGSC4yxZXjO22/ylKECsW6Aow6fBc
tCBok7QoA/Mg6mGJdjLuS4YdTgcJ9v+NJ65rNWAgtdpwFDM3MSVWCVpmPk9Kjn5htSw0FoM/oZQu
v2UGgy0ZYl7BPFlP4PT7oYBIEyocBGcmBB9sV0MLXhZFHa93R45KEefXvAKEsw+If7helPINN7bu
eVJiMMkSu/tD6FU/q1MHpZM1pkyTy83ksTdpTDEMt41eiDjXkLO/nx/YaenO0v03CNOQX3cP7CB/
0Pc6VSqI7hapwBOgjbzEM/2VDznHIevrgJca/QFkLy1BnGRl+goKwLKH2YSZXxQ4tvERIjkzWVSe
Mr356UCurVWAXMK3tCN0n5j80T+5z6gJsLRNOUT+q05Kops/loU+EOiiMWR6fpqCJrCMrAgf3OKl
n4SkyYgNblHJLreWaAwfDDVQzUU7DPJvR41pgw09NQdw4nWB1PE/qYjtPrqYXDrJrMtklYT8ks9i
CQo0lwzeOpeavtI08e0YWf2892nrkhogBvybOowwpE/rWv0pe9WJGjgpjXBQSaLgVBovsjoAf4xD
HKOuM/WqFs9qFyU1FiVXcLG9ktk7hIdeWyWrbGev9Cf11GqXhrjYgDeW0OJJ6/PsT2XExPtHG9Ks
YkczDlg3tpFWwIE5w2u1lvcJ68AQulCOfRXo/DNgUFkB4ZXoYE7qBuo8Dvy1vqZr+C+8fcsu5aXV
VKP+25nd+MnO/YSPMNOtZhVk9vbB+epjpNe48Bco3OX4miJHWP9JHSoSwQ+7uC97siMRleaJCuKG
a/ZGpDfuFNuGN/oKV0uV1krJLqayLc7N51bPMBkhqoIy9q5YAPJcnj31/lWn4GKSyimDFaHcRvaQ
Ag4b1Hkc2rmuYw6A+tojcosHLyVEuhoZP6Y8nwkcXJnc6kXrcUryVphsu3dBRZrwrWGv3BXs+Cu9
K7RYe6Q3vDQkMDVuRl9a7xdSVREG8dJszns003Txb4hNUzQJhN6eMQXNxSG9J4QNI3y8FoyTSFMi
JrOAdvbKT6oaH9Bc/2d2naoeMyg4nrpn196LD0QSycxjwSer6L/X2zCQKNJPeR3jveb45rm/4YjN
2q7+d6UTD8lryVsfNsPsaMljKTLBwY/9n7uKm6BRASTQNiXcUi/a9ESUCXlCPgND4MKQ302fGfi6
USV9umJ2uADDJKJ+rtLCjS2NwtpIXCiLSUbZKTYCKP2GE5Z0afHvvZX9XaN4Fcxr9h4bSRjwxzMm
8c+dbxZSsbTXuGlvxqwm1eqYa9StbRjn2nNnupslEbyMO7ZVVpfehu1M/BgL/3vV8JeG5hIToWwQ
aLka6FyhNyAWSycjNw6wOqrspQ6381AAJoRhQv6tOJj/VTiCcdilZ1eWSmvMjQtEexkCdr80QNd8
ZSSnNuVgXxdar0H/fRhPfDyhL0vGERJdfL0D1aB96LiSG/sES+6v7rn/aI+33TzY6+OLVHOC7x/5
AmfYst0Gw0hZEZg1VYthKkHg6HHosniTJVDj/82dqRwWChMAjOhb6QjY/O4fnNbbgV9lXzJ6wgUn
Vdyx6Dyb/UWiT5ayaAktuE7+bq5qsj4ECuJNKnLPYY3N010K2O0CQExzI7MlfJxEepT64yDiZHMb
E1xK3G5OwdnyKnk2uknY/RtCInxwDv6gvnuK7tL3UDM1ihSMtEzoGrVYJDox7RH4uimeXr59zYOx
Pl/ofs0jl3XPAYv1vWUAckuJ7LIJi8/MOHTg7yNJIK6Bx2wVaW2gPKcW2i7EPuGEKjOyef1n25P1
cHV8l8n3OhzOgOdokmduBzhbealBNA5OlOydLCBpT1NUFTiX+UrrsGcCS7sZtFPwUTWPMX2ulRFb
0gemDCXk/BBpSXdILQTDZPMzriM/596wYoW0x9nSo6Yk+9BwYILmUyC4O/imrWMRw2HHgupGoYPO
ZpvZYq8nPPA43tlwbHV4RpTOc8OMB8u9fVb32/TmLkAfyZgEsqKwFAUol7R1sRj215R45NWvb1HE
DAMrk6vOBogu6LAd8JIOkoCSR8t1KG08uRYjDiKdzJ6Tj3TiswB4m3RicxTXV7B3AEUWLddIbJ/P
SkNcQMVdEjMKk2fXfI/IyynTkeQb1HngfeZTwVHkoaLjuFVDT4/5ocsAKrba5xNXfPKITIxTz4Kn
LR6r5gjV5Fi9xPq94NcUI4E30/YE2rXCFBNi9Adf1a5UFeZqr00berOu2ljQkVaSLAA6X6C66g6J
we00rAKjTxTKzghNW70I1fmvayJgmz3VoWd5J3fKDReKc4phTbnwwNMH2FTwKK2UKRFqK6g508p6
abkmxuELEHxAaAE406aG0gDpZWyUiyR5ccnUXgr38vSfo4H3NDaBJkN+CEJaD+BrzxN657bg8v5b
zrVvfT7PY74kmggZy8IfUJEHTTQK/+Xhk3uctk6hD9n3HvcvLfovp2usSflUVvzodMDNSmeWHDTY
uOz9eO9sEV/7URg5R7EkFq6AHnaOYscGptwM2w1U6O3F1wqKDhFKToO2QJTDWWdx6pOkrwM/DEp3
dSrZfxcn0Uo4D4sh28x3RyFvvuP1n24ics9nhHWIY/DEm7V1HaUiKvKN92zXD9VAe54foPLjHv5B
U7i1EYpimyfy3ddUMwV+MVD4ypE50pkDJp7r50Q+MaanXvdls8fcdP87ToQGhdZht/o+ZWCHZMtu
40r8XsRhhOKoutu97J4yrr2zqj8XSbRRUf3lxw91JlCOD27a0RVob9faxTX8+ZW2DyrZinsNtW4m
nzG/tRT79ureTKHisiuX85knOtD6+Th96i6nhTvWezObS7WxfkTUHAHGQQ9PFeYsoEcGDODMxqS7
7A5nimTaGPueN+g8XZb/lO5VmLbGJKeukyGfTPNCWtrVIJHLJpDpMy+6EIMtCYPVbZXpD+I9wb7D
APM80Lyv0zVQ3Biq/nW79Kk1q0r/zjwhfVaacjaPp1fzYuRnglrhjKezVefrYroxb/9/dG7rVquc
5OZfQsg/xSsvWfIKWsgDr+bjl/oXVaHN7tcZTyFR0NMhaf+ga4+tcx+Ji6BEOLzJSSdnBwwabNxH
FtADADDmULh9gZNz3bOonDm9lnoQGvl6nHOV81pTGMLzyjo7QcCbOWvEEzcR/z4LyaNiAsN+v3Lc
6dECpLlBjVaECXdYy0/jY62qIgzw4MKGki7qEvegPrFcGYXfxufX89iZPayaNXqzECbHit5m8BO6
upfJMYuX0+hlpxVaGnHZ5RJ13sXfwgNdmSur4RV/PCngsopwZ4C7/umfbLQfVouFKbPVKVyqbxMe
mOeQZeYotfXfmT/Q+iHv8Y62MtqxEusQ8/QsIx9MstIAzqikmf9Xg3nC+0ePny8lFzx7YaYZhC+9
YjkC1MN23x2E4eC2ruiNU21f18DQ1EeJ2TpyxJl0X1K9HFovWvZMblqcnZc+Tt/3/HjIomQz7k9y
4nlGOLj4glOVyjGqLTOFrnogtY1Zmn8zI01YyZdZY85Yz6YfDp5pUEGD8Owk4CX+H3wasdNVyWcV
3T/jPBxhKckfrK37RFGPrPajfIVFNP7B7awFUIskQqjIMBpdDo+Sbp0vs55voPI6kTAkUx21YPUR
fqqs7AQmTXDK6PkhPKv8y40A5/5/j4TyHgG44KcGVkmRYYx83L4iyS1V96IUKvXMfzpIVAxzI9rV
DlFalrGOcnt0hn+KdI3vlUPpl+nKZ9uz9yCbv8/sRXAAdDKOJ5UMLd9Hl5xQIDj9E7IZFfNkNLxn
rMaAvFRCApTbfKcgHDN3IksqSy9EnWE11KWJFHADwk7jNceu0y1u0CXhKDeEAZhcGwJnLmgwQeFO
mkFSP7iuNz+MzudPlsuyyom+3kwPu/rcE2WSmP9VeY/75dhfBOzPJa0vPHsIBbNDU/3wtBN2rhwc
kXVd8+QxFWYzHbEUyvxS3Yt4jItOxBcb0r21av/JoQ8mUpIEpxrNNvMUY3K9yz7fOdfawD00Ewuh
+81qs+XGU5oWUauC7yi+NRqLyzSVJKHrafCNj3eqQhmsMXOIPcRRLb+YwAuxlhVwmOtDz9yK++JQ
bzTl1TXJQCzNMthPsFHGWUIsQLL0g491xhSwpP0UeYoSCGJhr1YHY2sVKusWO6VtWYCBdY/xi7DH
ejfpLEqnjnBjiNwX1iJboJW/+B4DdFoDn4pHO/em0TDIyy8Q77ThcgJMk1Ywf9q6FX+IbE9kNH+l
S+EJGIRLH2VTGT33h9WLBl9qDxVxFaikOpRfCPI86QnR82ruSZz5+MZdj8QU5r+arIsW206/FWT1
WcgFAmseqFjtiZukVNWgo3S83/D246EwkrutkR8ZMW6Lc+LM0Yc9peYd4Dn929/eK3wx7VfTj9w2
5BbpIp7FGlG+fTubHrPVkxUzsYJ2WM5iJYeEdkmepCASP97e6a8u9k3Ldszh3UJ0O/hB14JWkVY+
iYbekqYFw+qikYEr85MoOzEv7Y489hgIVYXmlfwMMvAuBJOuCHwEfo/3XXzOqHctqPNhGobBNwbQ
Tzx9Da9sJzYbfUUfF4lbyNX5D7ytG7xhZcCjMBWKtW8viqlzBFeZlm7twn7VVUWRjZHTAhBli74u
qF4y9B64cQECvKvI5TiymN2oDEnuWpF0R+pm/lSONSqpaMbwqiM2qKUF/wLZK7UJ9o1nzoN7JsVm
Ob67Zww9rM8vBvln3pxw0jfmr5YqPcRR6+4407gptII/59QLb5SXBLEApeDGRQhJG+z23PmyiIyN
9VEoqRy8Bd8ivp5RNX0LT55k9TWRe+4TMrp9mn5NeTU3xqH0v0Eyj5nEaSRyWkfUMnTy7FO9kPT1
JZTxAlmLUIIz5vAhJqBRiHF8D/dggD2VOgJCTFbLU2NX1reVdHIrwrrmnFdDVjy8ogDqkR2UhXCv
hVARbsJtH9NJ3wd/TJClCol/6LwO1Jp7CNtJW/btMC5CTkoNlMhCZ2ew9LQUXqp7e4kdwmCAFL3a
BGXiwLN7Y2H65sd0tweBdWR0aDm8ehsKPpS9rO5jHVFt+TpJ+0c6UehCGirE2+slhgTMmScf/8c1
/2HvpwTD2bzArKc5w2n4LwEGrQl/xs/gV/0aAqvmGGoJMVnU3ksafLW9oY6JrK05ens4fjO50gf/
z9mtvPHSHwtjRnjy8lhESbSzbfS1e9hdMN9UucCFR5L7/JkjFyVf54E1oRWahGxmr/nGwbcoThp9
+erxkyFEAKJ7WyXq4KHQ4FbjQfo2xzrgmBlQNCCFM/yRTyQenqdNGIUlxvHwdJeE6JlaJb2u4RgN
CjdABlXpwidysJr07kDTDkF8mry4XKXvDhjfA9J34xPZN3hFqzfsXBu3lZ5PgaMJlnNhVMkr6kcp
iuJIaYkhm0kJTngBtFNAJmyW+spA/heYswIJzJLPqN939ThWoMS//07RBR/tlgNXV/EAECm8MM9D
PZ3VE245if4v+TcSFpdVU9tALrKiu4q8xTdHPFVKIkuS6P1JRlYNXxrG9hLzw9nAQlqHiGHmmsVB
Zr3yaXQZ/A6SBqTM+Fh/e/p5aAs5UCSCawg13I/FAn2qKzkMWZAUKqLSQ1aqlXBRJazMDn2Fckod
Fu0CTfbiKQr2phPgHw0ategrZqjGVRVAn8DNUB1SxEvwpz9wYJ1Xi0fy3Vp8hZ9wcRNfC+UNUDwj
5h2da13oFecghITsbjzx7haY+Yy1OggUhRcS+HhQkGtV70PRb+NwrBOP2fg7bnbHztt3clU39QqB
8UsfV2nX9ZjuPXdRmbN1zi25iDeI2W5RA6a53edmCyIGutHPWOznkIBv3O4yaSaT1IcCvo3lWInu
mDdn2mJv98Xpyqg4x8K9X2pyZuRkHXpuYCqCs5RyxFa+0tAfcGCtoRr6ONqLlQfWnR2b1DpDg4Mm
zel42HD5FOwent/O3+vpq3ayv0zpptu6QNaqykTUzemkYuPZwrrhlo28jT8cW99qPqmNDxo/xdfW
NuKoqLZYsSlbIQxh1C809lMLa2Hbiq/1sTi99rCJpiKkL5N6nYecYT+OD7HEUtmnTNDUBYcZEMxe
ZkHlNjqjNTXFQk1Bv0hj6/xBNcPNtbvS2x+/l1cGpWKb2lm9tj3J/fIMoQZut/y5hn2Ad/JWupF8
hrguZn0Lp0teJflkIB6iKGWANcHqqAM23LoRWK7Gyay2gwxSnBSm7lShQ4USa4R/wIyKXnb8qMmN
WQDdxuWr/FJYaYY/2Zw+X1Xn3MhTBI+ecyKZN+B6QsCbgrZ3ExwUa0/wzLZaqcWbZLKC3dGMTlB0
sOozirc808mqriIDHsTXwcLzyoad35wTla5YXmhUNzUMYkvoaxwyzYBcA8GmMkDxnNje9QK6QAEN
F/Iz5HFjGnzGeeEkHkghBpDNPB76xASASEOZ+3UtAXIAaPpNx3nvu2dnSFgOBmqdrsN/YMoaSvjp
P+a34wlAhC5I4Ozj9N+Az4LYUvBCoQ0uzjVAk3vtyFsDjZ0z3HAkeSk9JzMF711+n4i7fSSDqxY/
pH0+4pbuPk+H8CFHGB2kouKT+ZJdaxWiA1Xtqqsna5saqSEysa2GPQQLtMBUqSHiSOpRmEYOp334
q/xgroFBdZbRjYyrNaHzzPCn5e37j/FLmkliT9oaSebsGnMQo5HwdGo9maoiEHCMR+60a+IULXRb
oV7vT1CXWsTxF4w6knXj48oTMDxFXekb9kFn0iDk9MrF6gpkWw2NpIVuypiucpyxV2raPdf8PkrA
7yyDPn9MYfLowJ/m5yQZXAMdQqvE4QuYzNpekSbU+gwxzswfcYQimQ6HFU06JJoPXMF4N1hAlgAk
3il7O8qzEPCwGvvZsJE1YAGe4xaGK0o8mfjdzPDAHxHkQ+P96P5U2Y0QSINy3tjpB+B68vaDZwbK
V+XUoJO5wYL6diGUzz2k+Uma1BfBgcKxou/SDow1Kjozo+a9l9CdMh5Gfx05H2cw6VVPyoUL6fuz
FeRMlZ3xRTfOa9Sq3ZcgS+e+cCOmaYb9F1fDtuFf2ygJmDZaw26aOR4TURzCGcAfqaqtLJzSy8uk
yEdIWgphnI+T5XFluSPCaCqkVgB+K6lBPBFn67VFj7p95ZkO1LHefJe8IkV9Sg6ehgsHF9xFPenJ
5DjRobQH2/qC/fZvZQYI94C1SeaqVNnLz9GMFU2PHrWwKBN89HYqtbidxRZfF510ahJAVl/Q2cpK
tbq52lP7G+tA42fFCv53i3zakf1ew1NSZ8noTINQ1W4W08wg0pVEVAa0dyk/WZ5hdq43eTKc/C3s
2BY/6j/g0yFJj6JG4BMIwpJbl4+mJN3ADp965a4FjcB5wS19CaHU1DHmSr5DpRBtVZ5cNTKhUSAS
C2KG1kxUYRu+AbVxoW5s9IjHUFXu2a2Zn/iAFrQU6hdjQEDi9tg96XJh7s3pbknE7usW9poFH/sf
roY4O1A9c0wM7WHSgrqLBrTCrcMThjct4Q8Ay+b6bQyXRafUgqMzjfsL9ApGH+sEEaF9iWUou//Y
+bBdJoXtFyp9/5wQe51TbJAwTPuTA8m6YYT3NCIcm1sSJFDsw1mrNbiQwfg4X1mFzpU7WjW9Utdz
ULPrZSmP+jGxoEWylNq/wDRYXKQdO8Uk76/ygtSpGp0JaEyCbf19MnlrzZd+6PqAbbJz3Es84M8B
5pIZ3sOrwPCdWj7aLVh0M11PJNNxLJUuV5TLCNjnXi0MWrl+RzhZm9iAywSaVcV3b7MxL2BnidoM
dHsSdCuUBeda56p4YFwqqHhevPbtY15xp3mC8ufHgylcbFeqIFAK2kEuH8gev7dHsOdkgauOqQe/
VDuMvPoxdKscDw4cfstAJPF4Bg55P3Tk9ljqlrkUbyfTmuwBDYGRMxXDZQRMAF//W2RXhNgYE3gt
YXIZh9ypfW1aWcdcHv7VozCg5pElcRR849s+mib1JEvvpxp0WtU5rCylsOvKo5CX+dD2a+vs8xok
+003QDkDKtNztK32BT9ixrssDqFxq3k+0sR9aTQUnCd7YtqN3Q/2g4hUe5EynNWClHk0S7VyDdKS
30itJo5AEmygSKXJY3Jyyu2Yds79LMRD+DBJLatflTlAV2H4ABG/sUFkNtIPojhyp+96flRTA+Mi
nUqHPTtWBpJUCDi5oBoC5bwr19UYIyOllvDn5ZWSRsEHiek3LYHV6AKs6Bkvvp+CRmu+KtymSjqc
FSNNl+Wit/Ba0kucqcshTxwVEXxtwuxOM3rustN2gHg2kkyTTpVW4YYZSr37KoWGmyV62PAbOXC1
ZAr2hp/NXXB1lJqmkcvbo3N8QmJD7fXIXyTaqk1pPPleE/TfNYPUzUiD9DZoKfADIYv1PSUz5H7/
NVSshrJgPaUDORKt4sqNszVl6DKLBSVhQ2dN8LVabuU6d7u4kd+cN0Fdn7FMObGUmuiw4r2fsWF+
0w6JwhkkHieiLVoU+hMAMVXMTQ/2H0EqrgJz7owlRaB76ULpSSs1WwDFlkgOyiGPdkJDbZEfWaSh
x9anieYdtCfoYYB0EvxQCSlaj05eojAdZls75lJsGuhcR54zuQ1cWIGIlzSd5ka6myi/G2VEvqcJ
bcsRN0PMr5E1qfjHKdVXlQGyg0sOyOgm4RlHONTKy3PE/WJ47dRyby44Al5cvOG4XADBnDuUzKkP
dQDRcPvFmtDS1F3lFQ+OD87gLOrZkBc0wyPyNRsKg7ibIkEDTIg7jankQIm+i7b2JeTMHUFNZyU3
eQtlofoe1lUR+9NaezRWoKL5AXRPOxJdcBmJUxf8Sh3NhUqMkPmznTi9phguE1Lu4mXfiXOACo9z
VArsF9tF2CtBJ7JeRV7WVpWduS4CRHXW3tPTkT3ucecYjSKDZoR1JKRjz8Gsi4A2b/HsdAjn9Idn
ARNPHmRNzn82tOqNWE6y3sNYdlANKctqdJX0qdU8NUi9WpBsZJOb29BZYvn4f+w06/C3vUt32JSp
3Gm81fJfwi4fPGuSe8ezt8J5T/YcvUcl/GEYf0dS6N+EMW7ugXTTW209FcNPjEdpCikvZIHKyunQ
2pVoBKbN5MhTkfglVh2W0w7fv3igdP7rJ0tMg9aRcC+2Zff0WBHSsGAgGUcVYwmfUMJPFONuLgyT
u4CdBTUzg0paz+0Dj3vYdwO6+9z+SEctFoUy/PKC4bGeUxO/ypb1hJtbOiwanny8nWHpFQLgKnmD
6nB8wJmWfItmpYuwY9CBUEofBj4FsOKTY4MA1NYSohpABj+gL+YJIAOjbkBI4Z8HHI5S/1THaBv3
U5eH8uBaPTaYHylqTjsFPpuTb4JTDamoYnlXW1viPCL8wC2WkzjlasCw91zon6tBKzz+dm5U6Fk8
FaADO7b3bGBMO+riLqid3MozaGicVGBXGe9iWQr45zGIWNlrS8WRMleF+c0i5eT1BxjpOGuXvYuR
a6VyoFcARaNWd92X6RUNOOLLW+cQWc1LUan/DLKPX5qEVY0/S8XodkGPESAk4XZaCtTCvYwhY0UV
4TgNPXQnGVZ76toL5ZSvafdSv8kvpz1sXmtE8SmhYG7aqBR9/MKn6+11S8kU+ijX1EWYGw16fNkX
5+WjToWGk551VpK5JwlGsuim4lzkhY7vIjTBuQdIFuHMrXwYHH6EfPGaQtUmWPwOI1+R3jDGU36I
7rHg/gPx7l8v0EcID0KiVZHUgpherYyb0rwoJda4G25Ud3Ev0osp7rDC3fLTjwqK/pGsHXHhabZh
pXcqTyePKW76CP9rjBvtyjNj+nllCIrpiwoyAmwREOlL3X03s5URQRrY+XmIdyAHCZLzOzbC+ggy
ZnoAr12Kun1wW0MecFKVBC59VTL29PuM35GRzmaW9rFqYq1lixcXNAF/W/cdm+xE5eVyENmWT0Mf
t33mVL1r8B/rwN6SYJ2IUOFJcx1TuN+UzrHIjz1NKR7bw7g1XAXBpc3WfXQUvC0EVQ095yPvsxeN
BQoWv50qnHvfArDcPCu/TDWchth7dwZcmE7Sb3VUMJvnpi65IsEk8QweSMtoB03YUREhPNawlOm1
4oZdKm8oQSxcrd+T5U5Vu0WgDzINEihY8vT/Uflo+oxQT+BDRTM2gNdXCYfrp+o2xVF/vfW5ZgfQ
mY7UiET/ZWhC4Lj9VbZmVSDX/AUdnu/NP0GcEG4f70OebIItS3zZmBG448DfLnuG2mygybcBhLtu
8y1tFwY8qfXR6W6elsaUtDoWMq445MpIN4HlEKYKmCkXn7QUygNZ1bRqxMAaQ6DBfpGHYmQ88NCw
au5czNeTWB+Bn5eHsZFUZfT/tYNL5xdhxANyLdTuzUsezTo3GvhfeFXZEK/61VpBhZ0Wme7vhB29
rzOko5znac9nK/gffL+54FrjhcN4JRHcRGLhdsK6nq8kruBhaV+Zz6VnLZIObf8UNmLPSpILsDA9
Csa6kzcfeqV8yCKB26XtC88bYq1eT+/N/hGsFhLRgwEKFbnQmovtQolx5eV1YebuEUW6S2tQQTAK
QlPkww2jpcrWkFSFmzhlbsH8Y7d9NuJLLBWzVfm25FUm3NB+WBn/FVVCkNW5NhZROoFJPpXL8L0c
A7EEpCFCWofT7+El7bqdgxMkvJEF01ndWPMsdjaBKUuX6OfOOJDCa5IwuTvGTtO5GpYMJYYMw4C5
bGzkIoHAM563RwJaUYVmGIatmrQT/b0gD+PigmhWQ0UT7QIhTqZ9P8gFPpd3QPMh6yv0yDVzmOmX
6taU2J8PSV2RmibyieOSJxZuoz2SC1XBqPk1vSzOb6A5ipojgNKgeuJrjObYvxWSDGOfU+wnujDl
PnT9g8qbCciLBvW/3eAk+4Sn31B50QPHgR9xOlvpWc+rETwpwb1upNyaDQT0Z1n7+zowCqaLgV2U
7phK1I8fV44JXTngWsL1UyPwHlBYdkDEPejltkyNujwt7HPytvrz4pAnZ+JHUUJkFRJNZok+vjtC
n+ii2rDBOEXxJasDPhHLzF335KZye3lFiWd+oF0pt2LUpgOtoxurnq7EJvwWWyolFQqbsdFCrrLS
vswLZf11a2og5FZHuVPWuVb6jlvxQE0HBvCTZWaDfNgRajMDmlkGGQJKxuhnoeEvbwagFuThkRbO
DCey3EneqrHvlTELu2/5S00tOcMVgXl9ohYcvp3Yvcw1ITaVMMpXZUeebXbljHSmf6XdXM7Jm6aw
xIv0TG5oIS6yb+s2Ky5FPaMdnVHQaqYgpmQ+/y3UjSG2pfhp53ks0eaVHIBPey6471tUo+TgA5Cz
yko5kV2mNIFbz9qoM23wwUtqR8RADDgegw4T1RwkHMtmL4lA2nJEBHXV4zUXq6GGyWxJVEUIIxzg
AwsT2Ww353jnYNX8cdyuBQUnJwX5Mj+qgNWrAif0QsjJ+6rs5LZcVZ7KXxr72wk/tNsx0ycocMJT
GcocPUVKzg1oZH7keEGTaDtEVYEGs1Avv1j06FsF9/gB3yPCf074sQ0nx/5Fi0nNAg+EkndoyK/5
VV4rcf8YrS1LVO3IbQgj/PjrLOxJkZCYThzKbQxBI4A597nbZHFWzm2v/IF4RCUB3jeV4qk6qdBK
/Y4SNo0cydK45rgdLBfMutuM35biZXvVTntSYaJ4V1PumeHM6ufEa6EyGD+Tx8D/F2kw/lx9+Mpw
m08aMN45HTPqBzkTPB4TSVohZd0CwuOGyS2WklJjZ8V7nhE4SQAp/lfZGL+2lT/Qv+6J2p+qZRui
yHXeGq9xFEFv2//ycHKyY891JZSEdx8BGeXUTMDXTxgeQOI09RkbXIbW/+0+a1Nn5dezQcJwYukX
KoY1/zCZ213eKjIklBd2BKAYjHOk9uMz1BJnOsK3ISHhU17W/06NHsbM+BU4KDP4t23Q2BP/j2Re
iYP3k4lfbpl4a/Re1yiXiNJ+QoeWOvPbkEvqD4S/f1iBCoEC0gpXelFCVVqpBdfTPtcW/Eh338tI
xjTsTTmKk0kr+3y2kr/yyyGQ0YdRtenV6OSezU0qgq6SZgQjn+GfFqVlrFUKeEDstHU4MFOMFKz3
2wGteDFnk15nNBGy8arqa1utnA0ZBO/ticiKEAnewBlqLhBsEGx06dLq62LgsuJNfqxXpllPyRn6
/N2A4ayK/PTeRh+cJ0pww/u7f3e+sTvGOi+yiJTpisX/fbAtbk1VJ9ENB0PKarsBRFASSGl78Egx
HqDSoUuO81cX3ZIexcmhCS49D76wJx0OlzljB1Xulwr95Q7Jy8kffBNj1sdUvvMJsNIi964F/7bP
qrFu1toDh9JacAHz20n2g0a1RQWm4n0YKUQEPMx9RuI69I9GfOrozV1f6FY/h2vI2ZpOnwYeEFVw
D5ee0nN7GovVQHdMJybQ1yj78cQC9hotm7AG6jRYsxTF0BnYeRqg5Ucm6vBXx49d6fUtbVSPsJf3
zGFOl8AaMbtW4yp2ajah9+gRGXFk8fHZaRlEQWnpeHW1d9K3/2u81i6UZIa2PGH3xlMM/jlwFg7T
qdNXINglRyFCVRzefgfYRfNE7V+rFbDumdK4XPF9aDqupIj/A3TfALL3eaMoZh1sHM5JIuYZOkas
eMvajXNlH+rk+M/XVjgLSeQcOVil9J9/suUkLBP6WEN2jdK+wBW5/TTfWhuArC5jWgddO50m7XBr
KuGcQEumgURsYdHOkOL6wE1YzaI7tF5da8MmeN/LdpFeDWLXR28siIhrnOXitHvS0512YSg4gdT0
HglZ55MzNIdGEUiiVJ85s0K1d87Joo2xOFcnBmKreAVE5QIZcsFx7WUqG8+CF2sxG/akVAHfKMXs
XRAtlshqNcMXWKC8NYIQKiEHBG0ioMgOiTvQXiO5+6PAbQYXwG1JXaqGtpF2M671T2t5fF+3MUXj
ebUpLZ7XztsYgPl92UH7AaegAUwXanO57Q4s25/1otWu2QKVGW+nKueKIusu8hMkX2K2Q1P0Gw5+
OrQMAxMnVVPMpTXDnEtVO/VfWwpDIvbT9UVtpEvRLAysXrp5L3xxFyGtPJmaiBsgEra24cA7IZ5t
4wmHTBwigFEKpbSdqV6NGDwTU0uxa5SgN+6rhBQGmqlEz0vAAbWryv5RxybTkJrE+pLzoXYfMKSs
RatiNhOltoXghTl1JNK1EXfu3JW+ZbsCizlGtP4wvvJQ5UYAGupwK6FDexkTEUwoSf4+3Q0651nh
wfvK4vD9V7N9jgmhmCJSVT96M40ZPnmxUl3lEiZOXEy70T8aaVdqEn0H7oDvZxLvXeYvDgawg85f
NEhA6UiQEzkbZhmC8dPFWBpmz0klrS/cEBwfnseV477dEbwxW8UZOQzRypEJ31Bbfyg0xhOC9Ax+
0o/VMelMkYhmYfI652RqGNZyx0gaz47ZC71e9KrCEi/ecgPTz4uhzCyKSlu2aM1Mph/oesIMDZuj
XHQsrGHfl134hy1/jfMk9PY3Q70iG6tr7YQff4CJ1JbnKrpaQgsE6igxi4rvmXymTgJjndPNJ5Mi
AWC35SysieRAuS5m/XZScYFHX1BtseZqKmK3s/Xlw83h442AcolHEBa9nRrkTYJy6e3bwbJYTzDB
L6ZUeA9PCoKRiKfn/wz8Qt8ydS+5rn0t7Hoa/CQ4MW8D0/j38ktL1IlYayakM8A4eeYTupl14ZAx
D5/GVuLT+phoryq5e5BK1VEfAnwSuytkDkSLXsD2veBXz5nMjGCMwsAhkBw/PEx2SE2P5ledkz0W
3hVBlLFowhMdGuiBlhc1zz+F3YMeONBsMcH+llTAHQ6aTH3e1ghYrM+o3C//sllS+3Qbwygwyp3w
jWJp4PGhRttswD9sLGXLEI+dyA2nk4QVU8KOvSAYEeROKkkCNRSm92ix3ghg9oAK4HyxJesByekc
mOsJE6nPvi27deVQbJunIVfiPiNvFSjaUnM/kAejPYR1HYCqmES9V1FWAWu5zelz55dJ5Y+UCei4
gNyxVudyC+hLsNJr0kOQcrtkQgKIrK7ak0RAGowLSGkJ6fRHn4/G/TZZdG7lsZ6wV9HrSDZ07J9h
MwKbGEq59hJ1Y6Fk4OoqU8328lEvC6njcSbGGEagBjqqPCSjQTJcRXLFDkmufN87UXk+8XPQXx9j
UoSBGA0jsc+wYgIarNLKWTmX/Rx0bHTkZWEvYZ0weEPqE283p9A/hgushbTzNZxQaTYuRaU6RX0r
XVaqbdLdcfqOxsRlK97lIbVVANEYWcJPq9uBDmx2pKm0WjUfCK9PMPVCkX58NkkZ6XlMiXjA4Koz
nZM9fbF9XmpLoDO31YvQF6wc+IR/3+97g4ZrBSVHAnGNh3Yd6Ifr5P0wkRm0r/DPQRLm0GzKGQp4
ezWH4Rzdpv12KTMrnL7ttwkXvkdbX48xYcJieYGLdgTqUhauCrZDJPieodWV+dtUwem/iQO3tjHv
fYXTMckUBVW3kWvp8AIb6Hx1cbHiksPZxYOo9c8igtDE6zFt7FPjkHxS/HZ0tBp1A6BKZSFeWlmD
5sSlGriZ491r+2YnyPKQEUmATr13OXcR1RX4hNRVh4YEbsrzrsW7qXOUJW/2A1YwO1b+dIwD7m1A
X4nwMa6pAxXLKs3jQqpIYMiAP/Zi1G8gmOW87mLAXBG9x3aRDmqZYs/eyKTC74vsfatbw46cnm+L
G4nus7VdUm/BXtrYyYmVgh7xvJbSZBH43esqi7AtQHOFpI3u1dhuECEabmjEPC73i+XaBYVlsXz8
UdCzxLazKCIlpWoQ/nHZ9tyCH/UJSBaCAyQX3UOs8KWwUeso+1Pil2arLrbUh4Hcdi9Lu5lR/ecE
VKVj9t1SFMdPjmMI4afPYhOgai+QCtuTcVauekCrBYMhe2rXOMIafKqfoHORjsMfeUepT1KbFvnT
CDGcVonM/moPnfB5WyyWyXridsFTuJ6xR7W2aSKZUAvV9Uk0dxcMW/BkvJj7oKnZ7FsN4W99/XOv
w+5BzUDnOG46OWgfxr89+UuF+9ipG14C++r64YVbw8p5FFvY24u+YVgEQV/i6/07O92etwqhoqf+
58wsG71foYyqE30sgrkI9gpvlwZgp7yRClDhaO/nAa8DOhR5PfkwL2aU96NXVZbm7uAu+4lHMZ8A
H/jfXkMaRMWAzlU5dHgH+w4bsnFVcbutlHFF0MBOxUcgN7c23VEdhJrPLvIJkAUlckFiPBkyT04E
+0CZkEUEj3Uxr1MMkO2GqkBtq5k+kQPlyfXMW2v480ULTcxXziK7+klGYM0HKN6y52isoPYWW9RW
sGDUbR4Bhrv7nsMnmv+NOl2sLJcNMH/OtwARCGoIBD1xM89WJrZJwD3myXSspfHD1hJY0QzN7Kkl
4NROlVm8Sc1VWTRKGa9KmdJwFdmsYid2VoSHwdDFpoeL7K2921/03iFTJOyIMZC/I1yxVUpuxQPZ
G/UuOy34E0rLFTrLGhk0HUcC/wIWPuqPXKEDKLeBWBNOsTH/7R7Vco3QGGw/lAIa+agjp4UFFQiL
YHjnMJDRPSqXR6iygy4wiv53O+/tqXjhS98LVjLxyr+XV0QAaKI9uMgmjA1mUbNecZHY8le3A9wm
hPvHCYsSQjZyizkXXUKngoo6vWW8ncZt8T6LdviTjIRVXkDRYU5ykpFTmk0D5Iw4guFN+yJjnR/l
GZ5GrVwaK/D6z4yPjgurkooZZV2s++OTs/p1/2irV3DKRJvoV/djSEAskugn5RkOuvBTLYg41UwN
6IIMcLLOYeiohemGZGuIV2Tu3RbeI8YrdeylEuga80mQz7TvUqIEd/PlSkZKTVTCoufPQWCjDwHQ
5uzb35eZoktYIZW6l2j1mgiBaQxDUtY2yry7dn8qyS+5Av7pMdfQ9l3rJrS9yIMVZitNunF8+33g
nwGC31YX5j99rs/zD69vWBfk0N5ckS06YB3puOqkAo8+OCbd4uuyslcNhJ/Owf38raYhO3RGHLxJ
8OCkl5s5j6pIfi2SI/j7z0K8tNB30uQXkkBvUeVE/cwlx9UilSvHVy+fFntJ6GPZJGWZLWwqN9rM
aMyZj+bOXziAefyHxwfheNwAxcCZEZ4wFSOo1s7CEq0O9+R7E70wdTUKPCgNT1el59ES4GZc0nPt
VuSMNuijDZ54rgAL2z7nfxs6koGAWw5BhnH5q3o+Q0oaVyOBI1wZJUTfv70H1G5hHZyG+tUsNCwq
m0eNqECt7ALLXnm8rYojKmoTXMoCSloBqTu9GG3s6iiiJiuGKgX3PR4Asjl2/jcO8mo4v7gN2Ocu
kktIWD+2ic+9mqCxZfuJWFnqD5rQ6fqIVFp7IBp8PYSSDrbbO7b2ZtnvMNe+dLRD91CBRB96M+rj
/JUvDavL+Xut5yrdbV5Fe4yqVHgYjxTrjbWuden4gC3rX6oz+5tV3KJwmjCWjhkFiztK/1EGpYnq
Jf1zKC0mpPuj1tQGNuTzPeja2QSFs7SrvvSXmVjlfg3ozAxXD5wDj2kjqO/OOWTlxSxLE9PPedme
m5OPT3qRHag4PkV4R3HfHXMIIJNPYrCoKQuJ/X/QkOya9rn6vaYJ4LwyPA+QNCL3pr5iVrrYpBFN
HRdcroXmZ/YGzm+PE4USIZskQyQayvnAMX0JBsXun+Zkfmu1jqMyT2/ckpY9A0YrlYI+8jnKs0wC
xzU9fad/mlW+nkbhEpXwNrnFWLq6ZxPf22hSpoh45L42q1Bh7csWM5RFUbjSksgHGHtyDWtIZv42
31ZFDsELiBRu4NioHSICwh37aylp8CbH4qPYsH7VeuqKdr6tN1YCvQgqJGvPdbmZAK8DgvY/YjYI
EVkfxUglSf8l+V7rl9GcE9lW58/TBbRJIKaSiSW5JnsjDOqdmajWccTcj639Ml066yLbW8ZMf2tP
+Bn4GtIXOWfpeSur0WzaSVmUSW3Bq6+Meq12/2RhW7OoSJ3wry/dDs5UvJzNtpcOZJWKSSvfYeoa
QSzXyeB8YAAeRz2Eyk7xt1pFKOs1WTLCyHKxkgIWgzATvoGC+wCvEHfZtnKO5ludjPS2SGh1QJvg
xXM1vVzY1usrM4WdJ5wLiTCMqoU38bKIY9hmpV8xGca2fI7aHJrBPWbLssfy1mjE18n2dXpOkvwi
2wzBDtYdpOlaOd0fESR2srU09i9Trw6y6+imrwCBiMKekFBuK1siRcp3M9xZuj45CYarWItCq0RM
674h6kaMAGw6XmyRDQyYhMMpo42oon7uA8TEmyryJnAL1SI36dlH7DFliuV3OzAh5GArhwKt1uDN
OdPMJNtXYNyO3KCay1WoUBs+Qp5Oszf577r9TDdk6FDAo6j6EcYStg4j4ORItv4uXiDDOsqANveo
3yJQZmkqwRVNXH1K/vOIsNN0Bwx8mMeh3lvjP4I9p/N6R7zxWoRk8HK+lHPtw3wXo92C/BD2+9Qr
5YsZnlWioI3Y5wIrj6Kr0gWotI3715s/f/95fF/PZamjj87EATWq9ScEw+2Ni5pmWOA8jrzFN/xP
isDho/SNW7oXrxKB7UpPeu0RwkDDus4H8gTQ5dIPmRfH99VKHbYr5da+9TaD9a1gymV5nqtICmCq
yY/reduEoIDhyKNsvEP/AcjuEpGElBnppvMHLUXYNJaNrksDvGrdQ2hXRujlXQttCiCj5UmBWjhW
1TZ2AERzQE0uXhgySs27NngJpXoy4HQjXwh+lwj67XjQ6xEAdkjAFkM1PAg7aoUQq/jf5/JaStV8
OC9UGvj5nJco7c3D4DNUepoFS2sHgM6AIQRhx2F2R+X2aEZE1eX6y1zXy/jWnzrhMk8w4WMygavm
5GrF8Qyk0ivX9A4R3fnKAMyEt4fuV6lI16XaLSXtLLD50roz8NLexVqZqw7mrd3B2iQSmHhXJj8a
IGN1aqv1xWGOLKs4TbH0WdGaN7dJzJ9+gZ/G5cyrotb1hyatyh+ascGJdvPm9XQthx9ExLUy+CtT
bX+rUAVk8/vnwxHHGjEFJWdj1Ul8tDMOdng5pmPUFgRgEle80F62QI77iuLo77mo1EW0vjJhqJHU
tKXidUTH9raRA1gsxKUWh/+/pbZ7hWLWs4LKYQd4JTb7QLG8LpilVlIvurh93UolH9vcwBFqaFBA
QVPvVHPdmlHh0lGbms0BzUQDsMWwr6Sp8XsSYm22zq0hOmO67ua2hw3KT53VDKtjOj7QUOsYDMx2
8UQwLB5Bs6lGfb29IBu6qGKNP2BBMqrk0sB1yzff7dFo/VQvtM8nrobRA9Yz7VFBW937FT4ACv7C
wuxCIrEg2u5h+yLbrNhgEe28Tqy7g+0mI8Y4flFAWUa7TX34EtNeL92R9vO/UV19RvpowKEmgioJ
qZcS1JIAszOP+97UU0KqFAvPDmWkdWFQcLJyxr/bjVOcgWItk2Lw6ik3gezkhEJw2ZawNTguDs5Q
oVcuAXHW+914r8WdOyToHmbO9Q0qJi2XnxBz0rlGBBY/k+5CCPVlfXE5tUt5nPm9nuef1/Vymebj
B8VEohF79CIhAu3L1pKAs3WRLSnCQTzw3uUMmL7xg26G5zjDbTxOrl7w3jyzmJqQ6SaOK6xfo+Pv
I6097VeWqaaSfiWOGVq4UHXt2dT6BtwUYEo86rceKLJkzcmw9OrYnL/tYyhNc9sEBZbE6PUujG0f
z4lS95avrPFa94E8Ohx2X8h+O4ESSppwjPstRzDQj0CIHWNmExamnYRZ6zlYXrmhFycjTGg/1RNU
yWWXV5/aEiW8TZmJ55L2Wobk8YPeuen8RA3J3kbQCtLFkVYa6ZQ2dQxmauo23eg0/DNftnediPEl
bBHmZpoPWwv5WgxbnWtZzOWFtGN3CZZ3U62cEaHSNOZ/oRPMv2qS1FWA66KlQllDihZ4mLCtXxHG
UD06Tq7OlR7IZtt15BTgsrX2FPOIq2McBSFEGNzrgZvQoyi/kC9wpgcUj5bbYDGC6V09w6El6/uv
11jT09BiRXBY+aBBpu6xXEim7w9v51bOm9mRbUXr+UT02g7Gr1d2u3Ki9VGToBSKAsunOQseww/Q
8R9F8RzU4LaeE6uNkqTFDY6gnP8mG9QwKkqKAMeMybzIxCXh4hmHilGAr9uALaX67iPZ+v6Fm8Ss
h+r3a4BYe4zWwGv8uqITZpbY32ZuV4H9Djic9w/Jxt0w7gADKAZ3N6gc5aruHnxNe5D54ESpV1UG
IUUiDv9gjgzIuHGufssRo70ldfVcWovMaQoQ8J1Rh7d/firiBwOehBinMhqp0jINY+5iMCtnAmfu
GjQYAP7Eee1gGpurpibhuBpRyr5g/zeruBcr3ATnYHtBHOOEjdYr+MTP1vAnr6f7A2r9BWWS3zmL
CZaYwtnUzUhfYk3XauMrGl9ZwiM4WhHDtn4rOhCp9WVWdtUYOTEZAZ9wwKkmDJgsCe+0a4NyOD99
aKVWSzq+k1grgDO+DFijDdUiuyZhmFf1uspciaLpa0Qc+Xmntzaxt4we4T8lqtVy6NBYx/ZAGOVG
1mF+RijewMSSCiTqfdMSz8dKHm0fEogkdTZ9SGLEE2scUGGFLlphW3/NwQU0SDMD1+BmBTHYIa0K
fiQN6fNTt5YLTcMBSmORthQAvYbCnHY/0QS8eQQM9AvRtmn7nfYr4xLfUAvW6bSB589gu68+e0hD
gEykwvAMgLZhUxG93NmET4j35F3nz4CoUVZnSSJiQJQMq1J/4/L34wvHQQ9lwp6E2u/E4wV0QZx7
4Ymy6HgeZ/kyd0axUUjKZXuRC6SPJNplOrcfjUWkb69teYDLkGxMV9o/muUfp8BIAZ13yQts+A6l
1cfIL6+DqjKKjMeKIeLV+WJXZ5K0dhboXcrd9znG5xeGDom2TlKWAlWPzLSABK64k81W7vzbaLY8
OxLh80IJ0oWlXKcS6/Hau2nKGylYpUQWoejW2ns5VS/j0VR8VOztpEoccES70f4YxYRABKc2P5Y8
zRD9xhyU1s4wPr1mUFnqNXpR+/ngDoYq8yhcYrSRuDo3/gjrRaDATXwQH1EeDRQ7JVbv5w3PXNyv
DHx1u0ACp2VAkv5tQW+kGM/CYN/lHZg6GDm6F/u7YLqrFArUiTIjjvDqEjJ6ustUi6e5Q7bK7eQ7
GdtyIo/iCQVw0J/usiiHA0cthgF+1Fc1X1vtFNei4Axp3rNLnOHonS2TRwLdhNm5uzr6uV4FFzKT
ukTT0xARMNdsMw27ExVALJFLDPBW+GGM+biZsGqxz+bfOYNJ9Yh82ryEpYzSVlmOtlAO7QvmdCN8
SWgZMjgpHxLarfmTC5G71gpto6S+qV3Q87HcdFaVksZf9SELXiIbmrxlLg+KEbA8r+Pb0LIr8rNZ
Zk4RmxDORC41zoJtZDbf7/OFTznF5ASTnuPOt7WZDUrNPppJZVzG/chblK6DkK5dLhNyKiPMfsfu
7WViOoQs63VyyPXJ8kbpy5Pk0A117bVd6Zj8KU7yrHIpkneQtg7NxCBCGqdtVjIiCECid3xVovc/
8l74ilG44GkLMDfu1j7V0gFLMG+bjIBSmO9G6/v1NqxDPTLg4X2j+o4DLX++PQaRrjl+Ak70hTn1
koN5XSBY9mguehTtJmQaB8rHEGlP0ZZOxxrFXsyZ6c7vDFBBJ01A+KRDxTZoINxEz3KVr9K4BjmD
EDLZcvYw13/deI4gZxllY4/YyyXtNka12DHY3VjEX+TI/3SuiBn7XdoYvpusiDOyz3UMVoIGMPOr
cZ8TsuN3jDGcoLC07oFyBsnMR39c7ZA1eUwQJuG8RWDMS/SqQYBIErdQGfsPAR/ZzjINDLl3UQiy
Ocw+xE9oBElOmuSzn9/x3JY/itIWDUjjjupNZ55itnWlSc+AdCcLDU52TeRt6kkoRMbHFfTHreut
Hyhzo2+kD8MSe6Fhe5ngK/u3LaVvI4lwLXiH1V46i+9E0d6VCgUweomV2p/3wAwtQKTdupDUtMLW
ASfBf0b7ymz3FR002Q35vDxfspM2kRA1BPq2peXhDpewvxaFBv0woUOI7pPtuMRBlumWhCgG/W3X
yIESU82FyDirOFnAfR8iRs1cMR0DpP8ykmk5jKDzgcvOVmiEJsI1SWUeuP3ZhoDN3Q//isCWzZsJ
FX6xGouvPvltW8CJX3AWuUn8x1a06LrLNt3GhnmvVlWMyOD2cWX3wm2DMWei3R6WMgvSiyTK5VCk
wc4qh+mvROUjId0qAE9yVpVvv3ey7wJbeGnwPaMqX/HlAIp+JZMWgqriwkcCkRZBUjIyTsVRX+9f
taKi/Vz9yRxVjkWQVBJWrZEY8H8mPxe4sr7UpI9O2s57+Q7awi1/efmE/Hp4rjXQhGA9eeJj7Omb
d6C5EdQJxwmmC13l3pa23cSCEz4S0FKP7GXv9WbIVr8meMUMD1qKZbvObq/8uz/jUIpwgecVqux1
6RGNHYDXBk0Ecp5YKW8RHLtEyvaSo+/g2dhe/warqu4H8ZdJTdNcMF4g9yFIDsScCc0chfFFciLt
DgWmJxpFLR91iP3zaWPH2SL+6F5Lmz7WJk7ZFfb3+2z8VM0SuWg27P0kIC+quLRKsLZzyeuPxxTe
qcc8e3b7kbxew3o0WDmY6XoFZfxcRrlDYyZNYuGvg58H7/BKDvmr1TfPEFFoNRztVg/jaeExKu4k
Spd+WLV5vWs0fVirUITJxEPs+xJcl0s4ROu/EfoMm1/SdvXDygetWE7M+3M51Rk0EIIwk/HIJu12
A1NbPUfWaZ0t+tYhhLSp9yLsFWwI+ptgvRyXYMNEVKu+cNlcmHxBe5Lwy9WCSQe1L8lUmVGxlgoP
/sD5t3XEdo1HC0kCwRfSYyrWb79vVlpYFDQ1Ct3hNel7mqrrJxxBxqBib7w5s0z6iJo8JbuYNh3i
mhNSvgLPDSU4I6Wq7bhMX/g4+sMvJrb+lBmC/Wv6ImVgXdiSskrq9Wz2WMtfKOFYjsvej/JgMGl9
xntXGbGpBcR/yG4AATECBC7Njz4gWQD2mtvN6oyVdqIT8bhk6wfC6skeaNkgkPMNen/DdzgQES3M
PGi6ab3zysFQeYVeBAjmSx0OJfnjjlkGFuMM5M4r76VnvwoZmBBynUZC/ZCNImjdxbsjlQyRDl72
YZEBsAWDNxYp2uS6MT6/3z2Nb3NlUOfqibAANO74TpudqTK9UKy3/79JVNtoIoFvwkKR03/y10+i
hnp+b69YX0kJH5/L01MIMyA+a69S+T55biB429eamDEOw7cil1+EmhS9pPCe3D/PAOo5xILInCk2
ehEiNjlFePWmHFoHIo3z+ggkE+7OmzBCWu07guHQYIS2QC/nXwwx5lpOWWe1zi9GCwe/6tICs0ko
jJOkmiUIDtvGXoEb9xyhUeg/2MxyT062TOgMGG69aq/bzf95WcVmGovsOYE7a9Y0WWL/EUBenn7f
ys/01BRgU4/nM87wdcXYks02jeBKIq1NctKrd5cmr6Claf/7rfMsZSEp/Nvw8hzlwOieGkf0J8sN
e358WTlwHwJ1CC3YvOJwW5J3e5zSBYveTdXHqkUeQf/KIu37Zu4IfXz6tCsTgmWuyXBxPNmCQpL5
r2zZcZ7qEJLdtHLqxRe7MBvtHgHMS4qyZTIQmY2PMnFPZ3Ad0xK0/94UZuv+j8XlX6pzwT5ACSma
4ZLJ6s3VsbEbjYMnmBOIhWCju4vZCPzVHH37EzjMlSPp6FKCtmDi0OmgLPJT1Em4SEpURuoBCUL5
i2U6NsfyAAqTr4DIcmVl6lNwDa+qOWbWiYrbxKhpF3EihPoQg7nXK//j+jTpdPoJPTu717Ig4wOz
13fPeBHwP2SvK9nzDUf/ei+xxak0NT0obmHWTZQAv6iJCj+zcUDzwXYpdp97UzRruSlMWE3t3r/+
mcXHYvunPJERy86eF3az8m4xpx44/8BJeg2x8h7MI5GLMY2eDEmIEZX4ZMDEOM7hoW6WWh0fzh0J
+eyUJsTk/vVGDI5aCO4yL9KTJ5E9yNv83OUTvardV0pOqXGisMJj2MvtXkNL7tkiavYrLnoCvM8r
u7jXeFDjlq6q/Hh4ViNfGB5qhYtKOPx5OLlgKx/dFrxS7ttVoXVQrAHe8anDUlpiyTQHY6rAFRxX
WjovnEUKp48aN0ePCQ8veAJZqewkHBPEkGY3eN3L+3wtKhgggNX6txT8cIUoTYQrBIz9KzBqgyLK
3Yw2/2bjMd+GU8VWsGMi6TJPtmWlPEXzL7JVnc/kdJiT6GqCS1BFqj0Mx7QTliu2O6Idflhhai8e
CF4InNKlJ6Lt9veBTmlQNYy5MevlqftgizrXk45cKFDkpcVcGyrUu1KR4ptxBHvaRSJ20qRugzdh
ULBy/SueoBrHUGGKAwdqwBVuKUFdw4OiFFZiBZr/PMCHXIKnnQ7Rn/1ypopJcaMNspULMYFMDUzi
xt7yqisVj7g8vhMaKd5UWSIdz/YlCTsgIJHVxLCyYzI9UjG7O6L4BWtmYs528RXueczPpbytrKUE
EGmom3kBPlGjcTG/rnHkhwYMHx6b1LS3geDFB8SWYN0Svic8lZOPNWeX0gLiuTvHGn5rDY+mdk+F
Xow29MDD9VsmDnuCUCAmL1rd/3DO7dRyGl4X2aK3LoeGSS5ngUC10JRVneM1h4Ue3qph1aVwzX/H
YeXfbavwnnxFH/BpQsgj3iBeXuftwKFF0dBXaNROzPFmwqbm325Rx+PcX3bMND9UQydk1A3d95ws
F2yAwY9ZUSic3+XQEV0j1FTRHy0wbFOc3fgdAXVqBWKQcVqOB5tf9oTyiJawLlhWO6A6gT6uYLJG
b0kPfaoaXCh8MeFyhAbZAuz6Bp0z7PXL4cdmnA1EJ15kxAhoVOkkYv34P3eqVgDgUslnCoCkY3E5
Y6FDWfYIr/4Bx6arh7VWWtBJXIp30mM4S5838pc8tOxnKY10w+e7oZJoxlRZJxjxjm8K5Qp3cd3r
lIo1bsDBAX3uYsF8vlW4I/BuPWlka5dDdhZAa+LNZdEnupMrpBJ2XPFOAbjoqlcqJWbUx/S6tHMU
xPFDxmq/511AsZLqD23+FlfYOV8TdnS00VEuug5HEmzzU0c/QnyDkmHQ51zjLl8WN+xPU1foW0YH
bRRXdplN2nMdUKP+FaelIPyp/C/X4t2Ns1ZASwFNLdlQ6oGBC4ITWGRy+lNAsxSQd8zFd8T0AWlx
e9FaRaN8OL6/yvx9ndZMlV9bQQH/CXBdolLguXnfSAc2zTHvcIa9WSM6KQBxqhq9d1sa5jOA2LEJ
qdzR/aubZAVTpFYw3+0j1mELWbZ5BO7ojsrljE4U9w8ne2NkzHNpnnVAdFU0Ou9NPqvBFafKDqD5
RtOUcWvcskj6xQbzhEcVGp7scZmEp8Hjhfce30MW7FD8NwmYb2lDsUD6W0AQIM0oT6Kx5uFvO26F
tvJeulaTvYaOyiENkFXtOL8wY8Ok3DGVsqXnjRI1FHUxcrHJI5dXajcFB+Oki5gjXMw6esznwcRv
rEWdnRprVMGWf/MkzO2Pe8BhNnu5VcEa+7aRT2Ec7SGS83PlK61orNZF7w6dyySc3Kq8J/nHmdpa
UFWogTrn3UJAGqNzPqudWJSkYEVCTNqL2JeRc7vKEBVcGEw1lwS3T4zjRCrtz/Q0t+rb41RxL454
EZ41ApNnpelxaLyZ4/5TzFFDIxqExToT9tmAL4BEC+YkHduRc4SlGCsjEa3IjVjbVFxdSRhv3uCx
0IgK8Kdxq1zMjBY/wS80OCg5kbX8NXi0QjDnzAbg9V0Dtu7lWGflWoe/uYnSAWVhcI8IM7/smFAa
p154iKaWCcgzLsRalkgfpMsOgo9l43waYQh5PHZFP6oK8RiyxNPbxlLlmQHj3e+3LDjistgg5Tko
yyl12CdFOqqVveViMIi7JzMeihYp75tM1tbx62Cqi+R70ANCZGhVlNiqMir4UFh9xxbQtyozGP+3
9nGtqaDZGF5uLKglsuNCt5drMBV75eDhiZdxR9DPecKqCgGtezA3Hdxit33GyCdDz5RS+Th2H+YL
FYEoeCgyOUoJWDbZNz5yHXG+q4bRMNWCVoQABf4J6dUs7l11MboIAINdyDQ51aaDnq/ENR63uXjd
ttBHcjwaOAi7S5eQIOGxMyp6RZu9mqH/sGOfQOP3ZOWU4bOYCyagSaPhlWsbfKhkNebVcYz4hAyw
NPlDCGWUy/2rNmSDR7EwNgDstr8Vv1cLx+Plh8MUHYrQoGhJyAqJokpj/m+vCEFo57ApDBHeJvHx
DCbF+36NamQi/JTMLw9luE7Vig06+SpG1Np7M8M5X191Rdtm+xPNWke3DMt2hslcGmtDypcfS4wn
NcALbvz2Sq70XPrUZKBLg/HUNbBEQVIVXZof5F+AT9NisjB2+44NSAi4rNWk8SbtBl2nzWeI6z2v
1YKdXvQgBAOUQy0Fp4gATCZ/znrFQ7hAIWvfBl7MVKJDq6Dc46XypVAuwTF1k9u26hECqB89kbCx
7Nb02IpJ1yhA5Sulht/kVLxPCYT5vRvQga0YiDa1/mhU/LGoOoUkJL6T+deXiXgoUYtg75SSjxsq
9Zx4A0R4/EJgr9t4WguvAZSeRVNxP9OwlnFeGbEHIiRIMk8odjcyLoFQ4CJLgHlk5r2x7CXZihnK
51Kz/O4FjXtVpSro/oX7O/IefvH/LDSbaU4waAPitUh9hkoSJlCfz20VcMlNyZB/qu0mG5361orF
manKXDGZa+eUPGegoBN+uZ/pdnsnjbN190QuApL6E7fHjWcBUk8RrLN1pcsW+8nAq/dldhbraJ+Z
TfbDwa4qCC4F3lh5tFO+VXKD8ACWcfb4IDEz7UChCPmg+z4UL9oHeem78iGkyK5TzDofHkCuPBcH
6h+DOgygsGvSm1rgyZmlPFu4dJzaesA8fxHI/b/wTeNfTVfC6UNgOOOIkxjKxkLUG4PW1gUIiyvv
pev8oMQvyFHvwPFsEX0Q2mOgLGzo242+oGdcEYMQGcmvX6qLt1GO31WB03+uHY6PeoOhz9js/DWf
CcsLRQIUK17nZWdsD8aLVIGwtQd6pjoIhWuUAbgeE6RQLG9B3vw044Yy099L2+n4WiYESyoHVSBq
lkc7f6ajoFeBKj47sU2b2h+sRgi7TgmtxojjlguGEm6Q8FsmD+RfYIXEYqUZHSphMiXrEv5Yq6oM
FfdL7t5J3d03fPVyaiVaGEzmqk4ZXXx7Dbr6dBNVFlGH7F6TvN5IY8db6EA9FTgM0NVmSvmeFush
tDPkI9gX8/AZXsP9EiSrHU9ssUqwaeOPd07z77tKQP64jVGoTQMSuRNEOtuUg1Zir9NlGmt6GAMg
JICkANPKBHfDjFSRp3RSZHdE7OqPc5/H4PpASOqlJ2bN4zAF39YK2CvRXLvBaSEEobi1QNKVnmpd
2jGPmCD/6O8cKjuc4M2ZozLp+6YC3JWhyGJhCveX57ASn2KPXGfZO7fTzG5qajrCvfAOaQ8b29iJ
Cb8w1jkco/rKIhgJkWt0skYFA/fUI4zEZuCrXxEiDzHeBGXCWhETY0qXECQ8gveu7FeO2uOdTIkR
top3Y+AzhXEhe8PNDNOBNYfJfBTDz05bvLvrJCK3LPiQculILN/qS/GR71kZNMYqiXguVIj8fXj1
kJ/y3ErCDQysWvpSaP38DIW/agx1OXuIYoqV/SSiPV2zHDIPWTVIrsorTkIRxeCoiDpb7SPBu0Zd
1KoCaur1zUj6AMCVi41LMYQqdNMiwV5kpgS4xdvkQLhQD0Z1NgKGT9/xL4aSmFCBZKgku0FECzzv
6z8kSJb8jbF/U9H3ylBULMOgnc09Ov4PbhkKHVN8YjEn6Xtvz/Is2iQPs7knIQKZCzzktc+Gh7+M
1ymum5Ber6ZaLx8+gkmqiWPE2LK3/OFiwYAGhwO81qrxxUjvIvsELxxOsRt5ef1s4R+8A/4Lqc48
cSFTZvfjSuRppAwVuhMtuGM/V9Xai6ZGROW1Pcl5zZ2A+VDqxOwqdetQ69c9Z/IcWEkFC5ehWGEt
n73yqED0DqodcIz4k2Z4kNMVHv5LppjuMk+RY/vTkqrbHIQi/LtiWPQ9t9oNq33Eoyccjwpb4bKe
SfCZsc8fzARGqcToxnxiKwNU+hERUh9HQkTORWMuY5vA4qdYykT3NKYq7250pQgthZFLzNKqJyrw
DxmrzdolM5DB65x7IyQIWlhA12BywEuNURznfbePTYnxSoSuWRi9OvPLWy+RZdX8wavH3Q/nMh/d
PvUqRUJlhk3cKgyQh6rIqi3cCY7TEqI/3SfOqBDNEPHBNM3HUF0DxeRCzs6C+94XAm5sxZZaPYSY
t7Zz6495IFoy2TcVQ/4G77tXjExRSAQ/qv8zMBm/zMlxKnHD8XfPr2YLx8aATTbxqgeoP03Zs3U1
8ftp1XHGc40xvwgTfgY9oQF2l9vj7UBZwzO9qppRywAaPPH384G5ce67n6wnRPKqcBrARsKYhoi/
YTUvIKkTGThxzliXGqlvNg9JmMzLEgKbSmWKuZKHpraXxvTmMm/dF2Lwyhpoa2qe0SrH3XOVh/Me
NpOxdrxSu+VHcvo7fCRV+vNUP2zG43VFh9NqgYSqc+EUrdWksErmgQmoEX4eLMKqXjfqgHSse2GP
f6hkpJLX+TMbNzKutW9hzE5mGDZv55TsxQcHBT50q1GJO8qFVYoDbggtiv9Y9swnBz0fNn84205A
6+LgpHxA+fl1neIVcpzu7Wyyy4eliQ1ESrVM0WeVoN+PbDeSEtpvGuO/a+eAVFBT222+7GbBU3Qs
MdE/KFEurFiRJMIyGuBcWwGEWeq1BGmXUPsim8rv2RrZrxJhODwPVb1Au+DsDPxN2viqcdqCNj25
YTgfkYS6gs2xVbzxj6qx7XMp7eDZkdn4LvBtz4MqaDPckoloc9IG2QWQfOcDN8S7ORQ/ZNJRwD7t
Ili1qJy8ZPZNAte4Efk6M/61guFFUe5nbPkoGKEm0sug/uOoLSv0Q6nljepzXCpA9r/iQ6UZthwY
5sgj0Sr9nM7iGxKkhJrqU9g/UMT+1E1BIbHyxOTHspx3ezs9YR5xSukeshV378z1AJoMRgKpwTsQ
6fhEd9heUMrCSoGMxwbVAaOXsD3xOnOf2kd8RvSJnhddhA340zXcjsTgkjxz2LCvXssuS7cFHVtT
TDz9vU76Z2Ff14QVe7S8Dg5s7s43farwTllxaQ9ZrW6999mnVa+nx2Iy2nyxXBXkMEYeFtTqpifj
1+tUZn7TbAyjdVrCFldkKVG/6m3OH9rNVKxfxOfLn//JW82GY61I9Akbr7h5M3BCloAAcNS1GTLO
vMD/pSqWz4RA36svxJDSaZJXpsNOHhNl6Go8jAY9qhQx+LQYt4Pg7/5ehTacc4s1jxqBJh9plwvN
mV8NO/IqvB4JA2i2dvr4eh4eXqAFcWKwsp7SZ0Eqq6is4/FtxXSLUhlCxc7IRM/ioG+mmDkcg1O9
SBt3IyvMUr2BdZrX5n8zlvZy4ebYt7lfAYUL2B2fS4ZLJBhmcmwHCBFrPzpMDdqzTyN3/XAwgt+i
aqaQZCauUxMTzgt81tYsFt0WQeWZVpmXT1vodbECE256BZ9u2p+tT+zdcAjxJ7Xkox9jqBNRcxHP
bf4rVdSOoGT61rggqCF/mvQRUYObVQRGDWFCrFjfLF6smaxp/WVsxgHQJFW63YV1yWHxIxMVN7oy
iahBjGG3XOc7leWoGMz9iSGXrTV2jdwYDftkHwlCJ0GShWIyPy0XnSuYkn2O1YUGiQCqnfPcefcP
MEtbEstChyTv6S+jnlr6JOPNGqdbv9m1dCnLFo8UjREMKhHGg0fC+rsCEgXa77qTFHhWkkrldK9D
KC+/QP6RcM9I4znltjB7RV4fz/aF90xCq7fLIAn3EXg17GejQO4AwQgycojDPriRgjHHwkNCGVvZ
VGRXcASHP8DggsC2+pZw7zxC+T20nu50XL/N55s3Qcp9qxr6OnVa3rBb1CHbgK2OZ6ATvrs+ic5U
nqqA/9PKSSJvveivYtAFweylM2NPRnLAJzxXGEZuP5+fIfaxdMQVbmRhhHtQ41PC7TFA1h1QWr6L
0necwJh86Vv+dO7kleDkDJFAXjntXPU4rLz6Vy92uULSHkgL4yJSX3uFLhJLNw3Xoska7eOGNf93
eOzeSgs85OFKvDUG+bzxjNAUOBX5b4fkj/7JjX6ZrfbQ/U/lU4cU5A+2AryBw4Z9DqXFeChTvzf4
V4xzXqTjQUoI7rCgtZZqOhDo/hf5Z86GCSnBKQ/yqLCXZ8dnah+fDOtxdtSj/cRQ6DrW8r7b+IVM
G6Qm2eb8KgAgFFDd3oq5lJlMadNWgNPeY3DG3zR8U5QPLIOv/kjcl1nCaRhu3iWQ593bo0BMy4qO
uMkCJklAKluxoUQ1AFi+6oVrUbf082iXhI8U+t495ctvWgWwfWqcTyQgGpRgkCEUmb8yydrPdgkJ
aOd+/mmJtuL1HyyH/NilcBszGlQDu1QFYsDFc9qZPOMQq8PxIX2IJCu/PYoupAS2CT/BY2O3SjQl
dhgQrlpYUTkqQ2ZhmIZbjM8Lr0StSc7/XapMjO2w/u2sIpsiCnqUiw/CU6BpBMG1CLtpc+dhWGQ4
fJLTE0zlQKxCpGq3vEDyPv5/M/1lneOID4ajWZ3b5I2uAQeITqryzgRPmR5KrE9lttwRGvzj6/rJ
0fi+FyBQGGXuc81C/mMaNONlP13r5qWgbN0b8K7N71JFafPZytKNiKOKCPtWda1r9g8DIl7+YQEJ
g7CbUG0Tw3FIP3U/HuTEiiQ28pm3UyaxS+4S7defmIVdESya0pKO2f4tK+c1F/tmqzm0V/dHW3Kt
XJ+Py/DpMvkIznmbjsJOBHEM0zhfGYiuoa1O3B8yZ/tyGvWcj99m36cniPKJGehbwQQPkxenn3qR
am1EilZVig2enuHcQKGndkNJ5QHx/mjbbaHb9jikgXUuohcPxplfsBzLff3mppznyYqGoWKSr88t
LbhwJdzsTUQ6f/kiX5Af2CFcOMKtdS1kVB6bTwc53sYJx/2erxkra7PFUO1p9dC7WG/zlZpW6Zy4
X8ImNp0k/UIC5kSpOaK6M0g3xeH7VLiuw/fo3MqS54a+30IZKDu8Wl/NVSDrrz1/1uJaN5UGx6ZA
L+XSFISP3WkCth2rYZPq8/ZNWx8hntryqIvcvD/hNXAmrzY4E0fbjgnX0lLm/PMsIKqN2CAKhmGo
MTZXhHPjxtLZEohKwf65Xn/7fdA+kG+34/+isDuOYb+W6og7nnRgvodFiFywwDTKym8XZmxiYHxr
qB9VrRcC13ROfmnpniALTAPcrSpqG8ehwKPTtfzjV3DlsnRCjMiHsf9fNKesRVoOQGLYSTyEpY5W
sska3Lb8+FsYmAHQKFZ753WkHLUDqn2fS3vRO/rcYtL8kvpk/Nk9mibNl6D6HcVWP97T1hCbexI+
2uwzUMChTvZKoB3KCBLqL4YmVJmpEmZ54M1uBq4SH67IWsEtJY1Du10xNseXzZO7hAON4sg3CDCj
3Mhyu4oFc6Z5Td1lMAoY3P82uI4ocvVVpK/kJJwhsbmvNwf1vA41VUyAeeIMZDBN6ABZgv0eDy9W
QBqaqh/cKCkQylaY3PXjHT1auRCuZ81s2pu8xKSvDK4NzNOq2U1gyh/QWHz/AvJG3gdFc93MskUo
NSIWypmb8yM8NcvfGhoQ/qDOZljrGSpfPg6q6j1n1sXP/9J9SF5qBD7PQ2nY5MASRW/yznnosGlV
u7dFhKYiZxUVjnCfGzeI3ZfrVHG/9QMsL6VD8LMs+lONgL392aQH0llnnmJYoYni32IlLR+rHsEQ
S5pXoqUrxaYsotVWtFxBq9VgQ5mFVR9IdtwrmKVeRsEl4pMVr2AdEq8MeYEyS4ys7Nz6tOo08Dwb
3lrqWlacZO9I43GQ4oC5cb7EzUyhw95nB0pR0k5LkaC4VeMWyze20i2kWv/4Cq+hx0y+gypvvH26
ZyXJasnu9QVYL8oSSjJixOofLfuZOYYLNatjkuWV96XrOMKx52Ku5+ySjJWg4/joiBL3zL5utFQ6
gDjJt0yCGzz6wPlipuT9rS5oWfaTBX9GQUHT+nAu8cN5tb59Y3ltFxAELe/tStTuorCt27ZQR7LD
jP4Z5xPRYZRH/W8eRi30wHKUJB9JdgF3zE5mkfeQg8BdjPd+dx8zKkkTk+JX4xvWnC/71Ecw0bcO
OwnlgqiNcw9DNLmMMXfE4BJ3/5Pd2E9lzwTKdayIdGHR/nTc/C0BAXlFNTStDPu5f6dr0G4+SLaK
W1ne4TAseOaCorinSb/YJBi7N1yhlcm2LRkDGByPvbTbinpQwOQz4fzXFebgXrXHQDKFhNscSfom
ASi/bwOqLucwmhxKXF+P43UXtbuyc8zHQrcNAVmxrbGs0y2Y6926+Eo5xFE3r3E40bmBOYh818ev
2fOhPheZLf4Jq7oFbwgl5vWhwMjVpqxWEu3ciGGI/4PVNNZ0VNA3j9KgN6ENesPrk0T/T1l2hvpA
2X7S5SAK/fJg9++1xj9umMpIN/n9s6s17Mf3gYQGzhdS4wf9NCsMLT5OSVRTCIpu8613+PQoURwh
JzQOIBYhwMIJJgGeSITq6DQGcRAoKXi0e6IpTjjY2fXYYzs7ZX/j5NPzW6xCFzZXzARcQz0AIwOf
yr9LCUpf/bruKkPrxDPKNZBQuhkztP6ez4C0BHA26KrmGzZm5VK+jE8lThrPQHZwGP7E/3fZ75jJ
CDCeKmjWzY2EBXs1OdHh2ucAZz38VLqtmWea1XjenLJnVk4Jp8JWlySPkjH81/MLDsFom1CYZu9a
sL9t/M96/kxzJbw7m0kmA7sADbrGt6cW0ZWQm22LxSZhKFad49m+yjFHNHCQKkVpLv4Xo9ZIgYXu
DziPS2xIUqfzTK5u+H5BGdfnP7afeNzPCGr3RE5iBv8SpvrlTWQHN8eMcMjeW0xZHbquRebICICh
vGu2eCvGzcN1n51QK6vK9PoULHG/mZIlUZ99OL2l2HWief0iIQ7Q8D76zYbq8XFob5LbkCf0tAy3
L1IhPnHSLk9yGKbPXRobkqgOOuoJxMxMyb24hqtKourPKN4MtEVm7oQ3uIOgSj9adCNaFx1qFalq
bAla/C9NV2tZpO6DH+c+iUpvrRDdVdgpCHBvxQsAPQMC2WeHckTtLqSrlLw7s9Oxhrn0pcCOXLhR
UhDUgWba1qFP8QPL6GN9yOhqRji7yzW6n/WotFWM3cKr8U0UkF2X6vTL7Sg1nL4C4PjnxDhboMEv
YuNXryCQG6OQxNR6j23+QkfAem+vPBu0FIpcNiBfMGd7kdP0faI6DN3N555w2bNBWNRgCl9BPTZc
aCSGlw7LoHkOWj9HmNRozMOeTNXufVq3sBgDyyfrHCq+gzhUiIhYg+5ERtgMeFJ8640tiXTQ2j08
ku4ZJ6ptYebTasPZpqBSFSuKQQQ97eeLtYPjt/CFl71WUBA4TV+nFtcqGFqHa5ka1pyXsITa6qJT
X5uelvWljVsnJH7IEig7nC9eq5LEaVTJlBlReLYGaBfejgTtUJcAuqtq/ZxOYPqJ3trLwKa+CyjE
3HmeOHIFV3qcMMYkB005N5CC5DQtB5LtxSsLmQrzzsA6iFpwqcdjyEplrU9jGYUdEzuLwOx/mjMK
sxqpQVweost+MqBb+FPrItpU9CcyWQxDNA7hO3ea9rpL8aouT4cf5zKHGJL2ntJjIb9Kz8QSmdN0
Yso/rINUJAXX8ASiH0UlM8GNs5JWpGSw4xx1IZX/Vz9q+8tJEWA0DwMs0Puq1iYyuHtHiQqLlU3F
O5hwqwQRSNfzJUO18wlLcU3kLqu3St4ZYeiPFx47H6PeLbODg+cM+yXSCkjxPoDJPSYXq5cEfo0T
3L0jaQhD63PFqOKHCFNkTFWYS293KO5aupRiBjfACP2hoIZNv6g3lAoGDAIOpVoXxceLBBgseMGU
4Oy88tVZzQisphOQv+Q0PZQ8o37o6eqJPN1pEZc+KdG7NRJLE+N823ZYgWEDX5O7ZAkJs+qK6rKj
eErW4lWrtKG9Yehrnd5eKLMeyeI2ZC/GHwGl46Q2vqWra+1NCFSATON6NPQ9CSDm7YDqJJaMv5OL
DmNUvD/g2H66vVdhVJaBz9rJSsA/g523bnuFh1cHABIMusK3EAV55oCwcRCQXTeF0lUu8B0G6C5F
/8fa+Z3jz37lMn6B2mk2Tg23hWJ0AWHS5ilQEiBl9+dDCFMIF637mVg/iYccCnkajXdcptNJPZX+
XP+RR+tzr+zcvFtN8N8aELYVxxV3OGthgTFTdYBEJdxMB+gX9pLyLCoUayu6MNVUensgH8cwkoRC
WcKNxFFNWUUXXziIpuc5IeyT+eCIfdfOmdDJNs9Ds1/+FZEti4LBCu1UhHa4gRLr45MUFXGlntVI
isj9cmMyoeKGzYiVsgehf1t+o5NGcoxXN5AC6pddwpJHjqreGhCKRmXQWAkCq9LZEZA3RJ2GwjRR
J/RIvR7hUht2gLQr10KxhJqXrpumwlL3PNNLWWKGLmUL7EQMTy9dzFN/xFETuir4Jcm5VvSP+AXZ
3HUagODveN7xfY6SPDJVuuHpp9q7MmED3JjGi5xkfrfpv3CO+UypOs49Ny9veS++Yyhenxe/rFkR
AienxgXnDMTZRLyu1HJayW4JHeamROMxOWOVIV5YIpTB+NfbVTJKYH48VUyD2kZDJhSsv1c0ZyU4
Q0ucQQtdOD/VGi91qMjId56PW3mcxrSFPKEyWhdKVXpO+1wFaGQjFhosiGeWCR+54D5fKDFG9IMc
2clod4ullR+DaQVMKORw/ZjbA4uiHzUQwhMQ5C18Y8JjEfXeyKSUzG22gi1pW40Gwcoh7kvsy9mw
KRuM2gsdrk0RyFJ+aDhPdomkKnomAC0RwhODEQ45UG1oxyjG2N5pNFDeMBNgKdxpQVKdsGrW9eO0
mckrVCqE3CpGRb5djnkZ9NezNWP6Ed6NWIq62G7T2rvZN+OjqPbgAMvgK9IZ4mqPz9bUXM2hfUf1
aKTqRxi3QGK08pdqzSaiKP5hNhQs0pk7xtstqShpDA/Aph4WTOQMh0AXAziaf0QntWE3XVeYOxRN
WXftyeTQVa0h4httG9iWglU7IXAkymh91e9nIDoMF0Tk4+E9y1yCK5BbxEkpA3Nw0HK7cNbyMaw3
yTkRXrZUMhTfKz6zGWobfYWO6jyrhpZAB7DQf222DoWZO1TE8dLrT1eEJNNUaLFUIL8plGOevwMu
O/mvPlnuwGefjD3hpCyvDXvJpBXqRn5DxSKrnaRWMpuESDKWzCNg7qFZBmr7aK4yqzcu24xZzg8y
c/NNKDV7+i1jINJ3BwiSt6dEJCpw43XpFOWrQ+om3UTsPPPvIAIqkKvQumXlDal87mXCnVnv0CK6
erJRGN7piSnxc2FbrMFsim0I4RocdU0fzC+FsMvJgtyGS53lyqnYlwZNAWOe2V9BtBy/b2jnHwva
V+h2ZRaOKFUi4cQuHJ5AcV/BzA3lQprmZFGXkTEiaQSFNOhnFUZFh4Rio5wXlbCdFUwMGw6ReUhF
V70xeWftSLKwcMjEqYFhNTdQQYFmjx9WDyLPWcVrf5H51nyv7Lx/hE6cFCGQ5G/3XJQm9LC0jNhF
BdEGcmKLyMIXcev7ml3VKxrhc6oDd+I0H44SPnI0NybDjQDtWEJrnuavvaTO5wxx+n3ZQBrVWmYs
4FlscrIQURkHtpvFySAIlxBB+NrC8hIU+e+gWGfcXH9jqKgFq9ZXuygHCrGCjgKJiuvhN+GLA3oX
AIz4qhq6Ncu8Wb5ab5X30L16IZ5gktmFSGRy7L4IpCnKfB/PJ3/WhYQdvgsYfO7vYxHoZTtn2L3U
2dy3LlSDsA01wA6E36M5IEkzVaSFGj94b+VBJUdnYy37sMg8aeEVM8H1zMjDJoKCS1G6+gSjluam
jolKKye1krewvRlk7syqzDa7P4c28JMFKIISN66bmSvNVWlNzXQg6U9dhCRJcX+IU0KGixSlNomw
RxP0/BPcTu9oSJVLLgyR0qnDhxcRFx5/t3JXHrVyJXtsuwamNIRFVBrOxqxWhAI6nUv+aewyZlvD
o28uK3+dim8xmQo1cKciyWjHIVwZslmV8TJjKtK4aqvF2KNHd1EMOAxkqHpb2e6T1ZiJFQJ7vCN1
BdXo9ebG74Sv7BOLr7NgoW7SFpFqGKFVz0yCGR1JqaQ9KJAbKiEM8IG95PjxSfK4EgsqOb9N3fY0
iHnLEwM6tz+PMSY3mgqRHd/U0rIo03v3kFfRSKvcoE/by3Yanc4T21dV2Qk3X59xK9mSOEpiVB1/
5E9PaAVoHbo/gv7bd6jDThFch4A421eEU0lVSyB6WvE4r/I0lYRVb1Ja7BedrKJbXPMS4VSmUzAW
JpkTGab9XsDG2JCtqXoAhcQS+vJfojf8IwYI1pAgjWAh0pTVOoA3PmN5wfkvcnqtt1Q/ZKqsRIzS
Cp32b3ZIsGkVpDF7y6KSSWZ0ziK2mJkhbOTPabMS4H0IRWswD7bIo/hmu+lsdkfDzfHIoUcgsO9T
3bUDeNRu9wV8akV/804f02KUjvOZDnsF8C1hzEMnhDBs34ZJ6xlysKBm6EcoCMidTeKwHyb28kHG
dMUH+u7lpBcx8K6taAo0bnAY101tJ915RbpMhm1dIDFxD7RNyl+vmYDrPbhN4MkrPchEiJc4KeIQ
PyFy5C6sS1kuJUlzV7PP17rXkaiwIuvVjCBB90ChLPbQyhlOwKJRmCRWXKctzF3KaxDw4EAyF+np
nKpBg+lZ8KikUiqs8XlirEKGWNYEXGab+19fgEkv947VH+wrd4iohAie5nJDrHi5Soi27aBmZnMo
T7viaW9FEhwdkiYQsocquM4ohhNEUP5HEMMy6BtfKCUNdY+EeeES+UpvyK2oq6O/DDLLBeOSzoVW
UZ1Ai71msxLmFnctlAwiQFyrtwaCjXXbxbU6vluVwq5FZQVggr/Y0nc4MkZ5AXVmCTtiyy9J0g8b
8zHTWb/PhnEMQdazX6RxyP1J7IDMJ1fQXb6AEuyw+614PSwMKDUAL2aMYw6qLgWg4+op7SFFPYwt
8WK9PkhRtgJwRXZfsJ/nigfgAmjwjjlC9iX2utAQXTIgA8XKxKgAfLZV1MKozGZSSqn7/4QdNp4a
wTXZVJwfKEZLbRfMUy0pWBrPwuWUkXNxfOIZnDXXz3ha824c4UFNlffUobepFcGojCgAaHI49uLJ
UgKb5lEj7d089BtImwasXUXfpWKm6yJJeZshWXlJv/eAAHsbGbYi4jXio1bztCHycM0IyElOjXa/
6BlAr8f1MhQsLrfw0EGedcObsMG75Hj9p8tOhq3yKlJ+yR/uIIK2+pamjdfCX+5nf+RSVPeDOKP5
bVn23RiUbp5rtwtnXBM+QlFSnEGgnovWhRheTTJ+Ykv2/OBp9cnCBzDVGzkYg9uWI/jvaJ6UuCVv
Z4KzTCnZC3TyS/KPxx+TXmIYVAb+iEhyJHTthyKnTPwyfaePOVK0L2uwIVgrgqZExV1PZd4qQZOg
QfFMKwdlOwVNb8IZkEu6Vt1dE3Kbc36Zl10GJDUgXg09sMJAoTfSdaqc2R2Afc1rDFT5JQzPih2V
NCVyVSNIgn4Lnn+XvZAUXdAhMK6jAB/WrlTZO3XamTTl5TSeOY9xVgcG0z0jhqIvq1lKT2Pisf6D
DlqT6YDwWYmahxUmm6a4rBfY1ZmHhNHXLmHXSBLgGwAsJitX2nMmm99Vz66yqDCf0aXrPeTwYCW8
S64ack/fM/s3NtoQbwpeIKRc/CaW/1tGXGROgWYplzSj0sSI828W//5cOXENQtjkH35Z5oA1r8Ue
DAJMKHulU3JGBmCw74hfQH8KTG2GN2/64/PFxnKyvM5fTfDB3WyvIZmvzrOaH656kdkcYiWLDa/2
SRZXUqBaYgR7OfIJEvKsEL0tysM6wCKS42g2sWQFiON1h2kCb5qCUCbcOhjeQ+6Ik7DZ64YidJMr
F4KyCXR0lEp8e0Wf5ZpDSFdE+BRU9TG1/Lixs1H1eaSbmgQpB218BUlMleRI79SuDaKwJC5cJii9
XzSiXiwfpKR3OJTb3+wyXP9PtJBNXjUn0731r1qSaeAFGK7MDw+dmqH8PkcW/S/Q/4AOaeqOeC1f
E7YGzTg2e1/kjfzS8RTfjSC/X34BNIoThCsqiBhLboOi8C3cmaCLq+vaHdSEiffimeoiOsvpDE/6
ELqwdRWI9c3GsWpb7lIiI0ye5jaINZ05PQJWwPak6Mw/Rjqxt63VnGUSatamduWrVxGwM6cGBhP9
PPAilP5U8DnL2V+BO6I6FCl8OmLCGvlAa5wON8ujrC5M/qZR1NbL4GfGJuTfxwK2RsCb8aOZrh4/
gDYtMLitFUf6IexlRCryRdD+f84f6prrYALjIkooGL4yHtXwb6vZSotYcFvt2bnNx4J3RpGRu0Ln
lRBB6838IlDlWG/58XKdJ4mYzKrP5sKW9R2HoH4kDB0m0xnUHRl8E0u+DwCmfuxaC7Z2eeq85V2q
HdUXOshUeg7222rACsiKVUQXy4MmLBdeqYs1xZtmiXCpeyAEETcZAQ9a+8wXx1mII/euzTq7SKPH
ecQJBdET20xhj7g1ffDDdAb/GPiwKxyo8DE4HqarlKB/vCVpoxIzlIBJaAKENBlkmCeQ/luWzdQW
nev+3xhLQflP3YdGPcHfo725V9JLEoVGdhwusunG4avA6jLmw4dtWP5m8xdetmD3veH1LtfryzuV
1IPrwrUO4u81USqOVyovpK5iY0/YRtkRdZSgBl6aeyBLWzdMwNda/eA8XzYVa0mxrL9EVJqENPz6
UtvgQgvUTPX2f+Ay/mcDrOxCpiwRowJiTxpvwV454xe1vzbIE7SvltbHUonucojqOLKi/uLUqM7y
s+G12BIEPBXdoPzWrs8vETJ83KMfVOfxKWoTr1ULeXpWCeDi28bGucbi3sGThzbxc+rQVwgU06q4
cdDtyLsPdOf602NgWnQ53Q8q9U681qO2c7j3oPycYnDPnPd8RNwuEED7YrJQreMIbvc5IbpPiw2v
Zm9fVCbGRZwtBomWler33GODMq3bmbDSAaxJ1Yz+mlOaof6jqhKeNnVf9SQ2g+a9Rlh43bCaZBuc
emFGHIa4teu1Av12eMI/duCjhC4xIF/uLjwHcYaXCnsIH7tl7sQfTao8IE125Ouu26qJqwMiDtSO
BnKnGM08Wnavfi0AftJNFTYv06AdYS8oJhY16JAR7IxSOVJvZGXdQrwr5lp6dyqjjZdhCT5il7N1
okrxcL86tYD20NSlcuQz8iljX/kJ6NIpcJxdQD5pxeOZotEzhUh7OBxzkryyIt9DQX6H0EZgyCaD
kcELM2YdjqPFf7UYE8uDtxb+lbwL1cG3qE7nEVpkAKJ8D/N0dhKmF74i00XoCkhsPiZl45ecE43d
6Pw9GxoiqF9n/h+9g9AKehbJU7noCNFxBMEdOZSCm+M80i/XOdatVnPMBIIa+4E7ILDLP0xeEU7w
I4kxrFXDvT5/Hf2zv05QHtfkSjEGF6y/Z5NMnvmSWF3uCalJDQxat4oS6hpyyeu4GW0JzU19thcO
WU+hTQnhJlZpmXxpwmSWXYxzsuyQ+wyhh6BeVuxUbXecbDesughzA+XLvKrJW/vFmOPILdRu3eh0
+sI7EMSfLF72c7lN1f8BJZeWKPMd9JHXSGXfTbmqklbu8xBzcU4pXOAZQJ9peA2HNriAcnpzpeFP
Wf7p5o693iEid9sQFwb9vkg5SgGuRlIjN7VGk8x8d5YBECTGcSKoJZqegULoVVce6ryHkPsna7gj
u9OEO85hb9C4k678HXbYq1crSQDFOIegCdon9MyZl/IVStBHyzN1XyoOR4QmbxrOPgZLi9LUV/CD
g4FwWBtO6auXkXHnU7Ja8vfmwWvyZobLR3fQfL6ja/6laq9MifzIgEGLn6s/nI9HDOM9kfuRoirj
kErcLN0Z0HTLdKkkiwPQ9ZThHFiZhKKcfYFbjKKyHyH48x/02mPkOeuwYQJEI9SwPytN3iM0yHpM
nmt+LiTo1eGiSN6F1grhcL4t/z5cjJgjsVWUvUfVucPYEOL3xDMfDW0X1dV3IHfDDb8tnX8+a48C
rXK0+dLfp+u10I67dp2v26VZ4bnqLLeU+CuqRibQZwOI3OTUybCOpbKtFcYU2rUYhbp710kGXDAW
gBMmXA6jViXv93sMQzOV6i22CPEUazhlr8z9/wq/qQJa2QufIQONbDdN0La5KV37Nfw7GCPxT97w
iWIw4JcG79zOh05NzIivQXg3Yofu8chFBahJt2oQbqDI4aQfGq/PKjKd26um/b3z9cBcFk5Op86t
Q9uAO+kKLegk3+tUrJrAFqfpdO7lRkRAZOuMLF+QlFVlCpclfeRbYf3kObwB8BXYmDVKT2ZFssD7
3cwVof7FsZfcCJueBY1HVtws8YXPDxMVuWjYmJCJF3/gUEwAMlEvP9wSM/K7Z4A3XkwBRLacyXp1
QNI42C8grcMvJmmufIhlB8IVD7lvdrrN5YmCQrq001qMXwImoDLgAZ90SOjHm+l43y1P4At8QhAJ
FV0ax2BYtzPu4eKfqRzuWPQtvVkkUaHSaqq3i6Ht5KDkIam4XYW/ed/SrE3myG0t0ddn256IUJ4C
kS/Wb4P9ds5XWs9CED3NSGDMWqZYLjQd2Ibs64yiQUn1oGDOfyToj7ePIBRpXbNKjh6zp56k6RBu
pIRtQ8Rp4PDlSwxyXaorHBtuUnbppClzAppLTbzMTHSXKseF1S/OlqzG6oDbg/Vz5rulaGja9ro/
Xec3ptzg8eLr5pzsxsGJ8nEaiAP8JPwSggcrbNxPN9oNAfSR92sgikmnmYQhTcUuN0TN9OSpFjao
Ne21XCuYFej0epj4nIvmwwySNLlztQiWH3xkxEXFiQI0Kl4vtzDGamqC0Sf84nZ3vpOJdKIOSBqK
xWFfTS+Wgm+G0VLHskgCftAvLFNVMY/MZO+AfbyUS7reh1U+L5pgp5kY48pvft7HGfCYNERe/hxO
Lr5QVOp+ymXZS11B8SAvW2mhE9OmAFxP+k51/cavra3liYYP7nAmWr+JOMBMiG7UPw7gJShecPJM
+yBHH+TEzUkKgdloNzzM9ChpCA5FW/VOUvBO2IAZcB6uYBFESc3NwXx+qfa0b1C/AtkZxnfsBHrc
yqAab9vnrUcPGzpgFue+FvL1xyurv/+u1JaNwwUKL37RDMHUH4UBlCFX+RlXNBlzW8wM+rErgfwJ
fbqehJ6v8wwNsiB+cjl7QVIz5QYDrFO8h1Kjb2bV+703xKatzztvzQPpyVVHKrdYn5NHts/sMcZp
rCJT9g4AqAVIdBceZkLYKbzAnY8eI6CF5naIySlgOln3QuWC9pPXNJWixiW5isjoR+AEx9YnVrBK
Bwmwnsl6iuQNKJyC8UWopqUTgyx5igHJX+jx2gIJpHkYMdr8IYtWZBV65uJ2gyoLoDydSStTNPtL
IpC4nUUew/OSwwnEUwqb55tlmkUohhyzz0kV6suDSGR7DDK9Kbm9D331+Vy/vj/x7FCWHiUQeljU
rHGfB+11mp+TleWAMwxslEFxzIQ3gABIt94SmUVP4G6sWF1JWx4vQsrcRgRI0YhWLQ5kBlHr8u+K
ePicIz2aN2mirAiKu35zTz03TGPRTGf6g0+jX5OsFTx156OmmqYnVqHlH/SvUsmzUX3IuCq6JO39
F+Qp1jbTCIBZdJW018gmAYX1GW1KwV6Ta7hnMSnzQ/t0Fkvm54Js7kJpJ33j6LUMuj2T1eylvEFK
lFDLojfvMSBGG2YbgBQSURASTCYvdsRBnCX9o8Yi6kwUP70Nlp/MBMp0WunTrp2DBtoR8ZbvsTiW
ihRoOY8RU7QUPvNU+DfX/zgR0fz3QdyfyUt60HIhaWnXUn2G3TXWJjAHwpDW+ShEkEkEhr6EXHx8
HpQnr4YOCZRSZHkjN337uVXKNaod8xeqjmthIWMPEyBmmnsaYXsIpxZV4CFnVn0LrHi1n2SkGBvK
bK8XAKgltdA/lpdqQihmZuxUpKnRRMtmmwbZih8d/s/IIwLm/xtiZiYFgDgMJFFtxOj3oDXOR3aq
1Cs7tE6on2tkyd06apHyph4eXERqoHpu5izRsI7PicCnn3N0WZ2nYHigWPCbOAXGNvNC3a4h9NMP
IlK3FVFMsL7+w+PiJoHRDtjTJ1XYcM8ecRftI/VFoInfwGxt0CQykH2dmc+buCvLG20sx6uHRbug
44ihRTs8vNYRGecwpndZJyc/Dn/LRutvp5cdR5iZ+QMkY5BWkxgQvpUbtEEi7fVLSTwnWepd+CLs
H4hXO6a35MhC9m/M4x0CAcGq12VWr/taBLNf/p0eDm7UcJWuqBEmP/j3f9n5WrNqf36X5cks0HDl
fjLqh++dMZWMu/PjbIc6FkWYlxmY/KE/Kcl+01t2xvftRSfF0uOtwLZ0KwR+e8gnBvu+KLTy5USM
FBUBTZXPgEKTXyEzml/ZPblMqWod7dnA1UdzCMCSSEwLOD18mhtHfJVGna0FmRBH5QWC5je5Ifpf
UAApt/EsFrgcGi/W+awuiGvc6/mQcnucWJ5/JAsCMvsjtrnfEzebl/kL+GZcO93mL5ky5cuk03fB
T8jMFJGQNnLVUrd9LnMQoZAZQ6X++Jrmh+an/6bRooqNj/77GWH/FH9MpNATX9m0uhbwgbeXp7gQ
WkTwDeW66DQaiKIGHR6EcTKCrlLa/y+BAWilEEI3SssXHHa8PzUgGmsY3yWu+IYCZuz21xyVQU2P
faetrzjpG9aKhjk6TkhbACWU2fGl6ZAMnTxRNGYwbHu7gxcztBxjOyrsn/UcXiWdy/dROzI30KTQ
0H6N0TmJu0qVa18CfLQA+3Si4HemlNYE90Bk9a7nWutsngoXBF/uEm9mfwdT9BVJSwi3+9a0zhmG
YHiXMzKfukMQwzIbnxdprtVnARHkufAdPhdYKkFiK1+sEnHul6VNbgvvgyRqwpAQrartJWfzQfxi
4nXAv0CG15ogYM1MLvQoRgroa4kMGPx67ImAKWzNqv9S8eJVVMBUJB3iAvrEEKJMwbpXxNByC9oJ
5o5azJcNpTHPQtLayRqS7SE3VuQlK0yTTdpOzmXwwhbwZGMAvf0AAvV/By7WSzs/SIdxxxfDWdfR
DotIuDTSKMYjPCfw2imWE3D1zHGaphCMQlRLlic51E45pl8c+CWaFF1JXiCaTdjpcF6Z4RzhSpTg
hK5VOYkOWXunEpyQV2fCFtutpDvy2cnbwYKCfjXQLTM38z0fZF8Tyqce2/ytocgrMQihs4MhtPAV
WwWyK8qA521s3g68b3UhWik6WhQ2INQ+eHWLAEtbF5DP84T8Zguu8v/p2+zS3pIL3n1Oz0k+SRf2
9KfiHVOr/fVQsYU9aG4hs2NKnBftoj06oTtp9Dr5voQZtOBZhT7wzzpw3xn4l351hEJGgzFPtN6G
dfdlKpMIpvnXEQZOX5aRimX9OKHrzPWrs5Krs483sJrf9i4ixMxDZ2dXrxUnQrUHmo/fDO79XEfq
oqOS665szFmxvwm4FQ2xJK8PqqaWIBAbMpFZ88qeioXGocJcy6c/V2Epzkwmn66qVlEIXjeniqir
M92iGDSThidBA9/zxVcYeAExl5vix1g8XVSPV++Zg+wmlTug+cU5WByPY6pwifgXXPB90UCrtx+J
vH+LZgwUepsb4cMljQRzHHPNL5zl+TNKcwU7WZe9B458A0GIZmmgwDo6etzs1Zvge5BkLqw6syYi
dRywiEpFLdndsNmXNCR7wJJhB5s3Qj7Tlim7yKmtGBXH/fPgHvnL92G2sY15RKclI8s0Gyc4kE6A
yid1X6BZEqiVXSvhuuPwjFmz23u6d033w4fXMd+hDvR2bzqQKjzdgnflQp2mrip/nPImD5wthDk0
D2MfRwbcw0gSvS+SblQV3TJZjBN4w4cOegKLdxxkSzLy2eIgKzr0GCRRjEl5cdC9dNWbCHxRFyPG
PhjR+VTzbr8JAyOlTawl6Gjyg8tkxvxxcr0061EdhMZPzYmpqoqduwQIJoqQkgMHQivoO/TJLDEl
s2/hTouHBuIgKFz698+XEq7acjIFNJSmOaoW24HZwiPhsv2rKi4DN+9GygadtC7vQyP/8OBHDCRy
UbiqRGJqz6QpEuwTd5PtGZD2B1HkI7TnqRwaYgG1NChy0fKjnaZCeiBsaqbxXHdORxDHrQvn0vve
aBT9t1+ZF5OMzAf2ZoAEDWa9Je8YSKq6Q9I/5jlqypOP/y5k5w1J7/dCK3/ghNbsF9lF2WMsh0WI
faBgyc1lN5bnp9WkYDXV6bVRMRqmj4IEVVFCvo97i8jIRCGdnjCPP2rJ0dkUe76Se6r8UISDl9x9
DNtonh48W8P+zOQ0WQcua9Rh5oHtR1mYAD8DbC6Zg6zK/vCHU/g1xVIPnaefq2/dflHGnewPkIqe
id8jzk7V/Vg8bgS/WchHRF2clc164Jg6gGjm3z2b8QPmoaao853lx134WS8cxGcp4C7SBKbE1lFd
jsy9nwV8eWudRQ0EkvrEyNlqIIfH6835E6HDWUuJqjKtGg/qcZ/+OSi93aQfbEG6slu4iAUR8Q1k
A8v9/+39kz79SqbfnaCTheFK8hY9eoKwxrWk6FLGkW3K42TdLVSzsC3k62E6tGXC66JStgBSV07m
AzsZemdOqilAUtoIX8ULylvQVsUlAUVmqWC7rGa1v4Rc3xDuk/kQZa//bkvlP+qtOBKp1lv7KypE
Wu8wrX0wvOEO4+/yqRrPoZiCkuLL8hKp2aQ4jwUL27aJMcNo+sJxJ9vTamQN3B4ioFVG9a+K2lJU
jtOPpPZR9wwz4OhwyzHm/ugqkBWUZJIHs/13N84JxmDxxXrpa4S0CD16AIbGDeI2YzEqNLCZN5ew
4B69Y6eqhKugIwp3Yfvq0JWJyzHGtbVDrotIvsNiKsLA0AfvjdYHIiZEYa2PETxJ2IXQ+S2bzFFS
4c69cDwgBB1FBN6d7L+UlonhnBfSLOaEf21dnSUjoQYWKxIYCsygEUgTrG5pVaLGmVsKY5UUOmYJ
+ggFBJBtImZIS9qhuR17iM1SoS7/6JS/qMo2C1HmjBn9Nj/bouElgvm3GYMh9dwaTdf5fMiY1pya
SgnfX796lDcJKRRPoEmxMp+jM8p+UHlu1+Ax1bnYlMUvr32px05pBbOEd9QVDjT5KkPVkBrbefv4
iyp4NIhcq/TGaWQc1RS0IkpjM/tARbCYM6Qr2iJKswuaL9oiMnutP3i6k0znM8gjKobKODq9PXKC
tmH0wFpQYXIl+UGeM43tB371go33K3hrVlHHG2KpqsizJPIjxxbPoydKxlKfBWDRfN5ut350StsG
ee1JlQr+qLZy+cVDYQHE2LtrqWwkw3dQGU+1lIBfisGEo5U925t/BefPqDXP4Vz1ym9ZB7yUfTmn
Bt671n2yOmjFrruofiBwAekoosffRYgLJlfG6ucXuLFshNdYtwVN4nisp3LPgzfZx4tdoWNWbqOX
HVMlrDElxOHhyJ2p/y7G+bsQONy1aSMVppeuV9eFZo7qbf69UTNydcoy5X9hhqMJ7/hIaoKgsF9Q
LHMgLlst7qGfccwYH0ViJcMNl/XlTp1Vky841pnBdK2Fxj62lL4jeI4VG4ZZSiYBop0cEwXi8rxT
fIu+0sXxGlkZj9s3hvZKodctq816pYFF/X3XI/OHB7+l6rTTJuk995O5TU4s5pYEshWwUYGjjWsm
66rS30edX1ijqxUIywyspDuYemPcLElWMkZjy/PZDoBvdkRx0uzoyjMokUvMZ+Wcqhe/QpPuN6kY
TPp/4H5jDXhhNj92owWUWbP7s/WLrFrqSlAo0zwRLDbQFhml4ToSTvmEDecPYjJFNtrIpla5pSeK
TPtCDYK5RbbmXw4jRZUMIJplQjqVw1E2ZmBaMaK7GXy3FjJ3m2/u3YF0aXLRTPlNTb8Lc5e9S7al
Yu7Mus/lQRVtvuNmi6lOpZGXT8rPkoISUzdo9fF9Y+9ZkBuQfAJuW5yttHVoL9H8AtFyNbXxoObI
+0HEmZrXAR0pgkaCaKbytqYqhQYydmyD9Ay1UKpxVxD4wV8J8ASRzvAt8GHJO4zOabHwS+W+L6JH
hWOgSzAMh/36aOnhyOnNuNUVuC6+/95dcWSxiFOmECv+o77XwnIH2FEMeJGbpuJN7El/WEG/+QE/
W3ShsH5/qBCIkEj8zA83QspVN7ezJzktUKczGvGscgcjMMYo34znf/GD44Gm3fucR2imAoR0VXY/
9t1mwGPyblJdoqU5jLRZvk/nrenNvvgzGB2VrncRJSpD/Ax4U1Wg2wlZfXa5Y+GkqVw6zeEA3aRQ
qlv36cMQowRG8zBQSlA5c6iixsgJr2YlXqDbcZ1ZnsyYyvEm/P++SDAjFvXZFAVBn+6zxd9ZozUl
rAitIb/2WV0BUH7JmvxYLVVVATFxSGwjTcgKjIxGPYw9TwxUIz+xX7eHcEI6mhWk7o0zFaiZt0Ly
YSVA+7YRWcBS2N8uACvP0wy6NcWpEF43e81/Z46Gcw+5O8a6x0ozMe/mAndaSrGdv4Maip/heus7
Hip9E+YjMemFkpNzEfJg/feJBnGPTKxkjMOBwEmMfaJwKzRTi1/9WRYRpRUAqjw9jRAEFzBX7GSo
spHwYD/w9RHGq5urWqgTaZYdcbXcU+CgSGrhITMmY89MQEQNhFzmDNQzCSLdvXD1X+YGTxx5DR2d
ImmUbcchZvfI+nCv95R5ygVjJnIbMviIuKGcm3zO3VCp8/xlo/ftZgi4SC5P+WYl2tIcLCXMenXh
06/MhUmVWXvBgZ9CzdkV6THrMJ+4uifvg3C7HLZLGn5dax5d+B+10xJ7WOFwz8d0CO2wzF0W9Xt3
UhLAFzFUEXPajGHxZ0+8f6kk+m2nGj3CojeUJV6BtYfgbu19v7HSMsubK20ktYk6INC33juK+kP6
8qxcFcTiesDeoLA9DlWUqISSQk/jd4HcoxzMbITei1QTU4RomUyE6FYpTSIzNLaiRbPY81FDXhMi
Gzti9cgizs6BGlcSOx46h1+aOXfEnNtOCuxO+YiIV9OHRmMQWL64qsJtFnSgal/MO+Rq8fTWuVjr
WVqGmq6vGN9+Y3r19Awv1DK6wpCOJ7xMJySuGGu2xsrTq8rtisPsZP2X9gkAdWLVQVUYcU9RzpeV
cw3QlFSPaJ8s6fEgC1A7wZDdniefosxA37rYVtEx6fr5aEUfHVn0jtTbEaXNu6Z0ygaDMNoqyFZp
RlF5Y/BAVSss9N5kqz4qdz9FbIb0z7M6WrxLEwYEFf65WtXGeKz3eNpWyjQ0gNUDrkVrS6TrTMSW
eOleLzna3pvmxIB5kEsvvrvpBj1kOjRbLFK4t3j6S2tQ4+CZ6fgsgi7hOvFijYodqZ7JRkFOroa6
YwPkayKYueDx1UYLhgcB9Vh4fCuOCgwdqgG/8i91wa6ECuj1GVHxVDomP/WvMQKQUjd+VdL4u2Ic
VJaO8qET9J/KdZA6wFC4fxRutsW/DSLrFMGsMH1Yvw89o8emf/4ft+kayOWGyVhpCKbD2VIC4Le+
/Y1ab/7bp36Kd9S4k9pUwSadtZM8Jj/myBL7iDnqY4L5ycYuqzmatqhTA7SaL8CwSW9dHF7FwP+x
mJpp3VtljX6eqC9NXB7fMXoXjtGkKHlImSyi4ukF0LkIPBiJORhdcvvb60p1kRrbuxDvgo6TYKUU
2vxZPXXRsPgIyWH5cx+hvmcpJYm+3l9JtWs33BNrmnsfL44IGRgwpQgFlMV5KUQiw/4BRnHbbomO
hmnRwXjdNGeB8NvIxR297IxCA5mjg9lgzUCdZoZLm8v1yBRnmcSSdrkLjdw1Lh3LkLAi/XY2cbui
LWykmeB/4QLPFYKw+DkjMbtIJfxzqxLtTihD7zdNYh1JqrfJVm5KlmJgSAG7QKKKSgPtzUkpbA/0
egXHyCR1l37aZ72eWJd4oZu5wUa4X2vssQKK3xtRlgiRhQIt8byhN7hH5fONQ+3NzyNrEc9B5yTG
hkaWMNWl7qkUKnEWDuEtfZ3bplyIgKy2wLvzmeMZZuXUpYan+66xC6WZ+AFuH0fVgO3kPayTSNbO
XYVasUsDMBPDqOrE+o4pM68one5xOHtMtiyLJ6ArEITSnF6O0//QeobuOwa3Y3+0kPFLiT+O9VRS
m2TIZxF9jUlYZbeGL4MYn7B5YP/L3honC+P/KrSyTN2a6hRyuKZofupGGtQWgopphQiAX0MzBd9S
BI8+xVmxIa0gloKPQ5KlSPcfcOrke85a7cRvPmil6nScbQSIj8SFLtJ6R5kGUZ9D0OKXYyFs1syC
2mVKgGoDevqMnQ3vRGwSYAhwP8nTRxSYzVbqqx9euIw9Wc33yrHpUZKXV6dPQrqlvHo5RrHwD6Um
o63mfFC+naE32waejpstuJ5blFoL+jHRF36MTpfMnShNVSFXJ7k5H+SjPfRAuxLzSxjHmqn8pB18
La522sfhfzRCb4jTAN93lVx5lBdziz8XdT6rGklPWIJA4YpKUvNS6GpcX20FxjfholMstn/lzJnX
wGLwcSZE2AyeoHq1/eaSgCAp0GXAWxmeAfJ9FfFsyv33yfhdA0yn1IWWbR/6EL14c3PENJrSis41
aT1k1NdHd1HpYxDkz1j1CKpqIsD34+BYyIqupuLtN0NwfOaJRBPuSW0+clYek+bKkRjCJF6LYceN
rrsU98tcuVqZeMj1olYeyZ2KOZYRZ+XBhu4EjBVB4lmCq2NS4rPzVTaUJeyjSu8Kk0919s2VoOfZ
Mclm8NcCsMcS3SY7GYm2MiTQWsjW3wOJK3cSyZTFPm2S8A6drRXsQSZ8OaTtrBxv1F907u/nA3yD
hpopijLccDMnyCQQiXM8PMrGfyuCtqTJ5yNqCPfUxJY8PJ8CLTw9w7IuTHJQwpc19X3svT7LNS1n
iqWToTrM9ewQj6W22bNxPgf3+bRxBn61dw917U9W3jzN+wnKq/CW+dVRCobkzc/T6JMqRrAlSOeY
zaKbQL+GgoCS6mrRkFW8mHOqWPaYTnfOrsDlTaRnzyAYMuC2svn/MBPd6D/3Sz3SKVWe0P7PVC1Q
G8fAWpAQldydD/Fcw8Qd5Dqzacwe9wjR+jEY13szxSi9ZZP1I+bqA+P76weODp84yxTzYf1vU/14
S9fakRI9SeEzCMOg+FbeEdtH3ny59sroGegR8IPQbq0ljc8EMr4OS+Ll+KQ6I4khT/5DgLCDBgBI
1f81x2grjPaWDzgl3yTlnOxGop1BdyCFydlDx5AWmlZdvVa6lDEffmD2aCV/CC4s4sSfGBW5sRwE
RMfAjlOAInWXNran4XrP0fHxcO7HEp3aVbC5dfTut6qSSsh6+PQrE8jpop2sW9KLw3b40PjHM2f0
Pwhl7JT6BhsQHCG7y843x/ZQiuYW7fL0eIlcZu0lOa1zZDcA/IiSgPkYo5bmDGQFIhY8r2jVfPLQ
k4kZnBnXX82Nm7FcCaUmprNNqov/d6y7y9ckZOKDvShpWCYLludGuD7p+dsfS0zW9XvLfBJOI1jg
OnYhsLq01UXB6IdtCjbG254b4xfSlasxoWH/vaL61aMSB7EGmb7rYSv6vtpWCfjqhlv70RWuZJvi
BEi4e+NmBhR1tiWZXzudEYghxDWEU2UhB/tCEVdfh++AqTDSoR6pEjpE89kA6SUZq1BS+1Wz3MPp
eaHRX+6sfBvGBdYvaXjhOiC6nPaU0CLMmq7xvAm9QuTeJE0WAk8YvJxE4jPpOj8Jbtho44/R05IX
q7C+U/KXcKLhZTiDdgsU2JACMkVDsMZhm+HIokFcvxml519wpt0TIB9jvOu7gsRXdV1GbS4H4nPS
zNo5ZZzxsUjjtUFn7DU6TM2ssZuo1HKWzkgW95jx/5rrcfStM8lGebR4rC1V2o8Tm6voCaSBn6Rw
N9LUsttYk+1ggDHhth590PO8/aRJ2oAnkJyZoGKR7wNsSzjxwzpw6MvzkpLzMVmOApmvA8PQZ2FK
lJmR/CurBFUR4U+nRQQAYJ7KLb57enZG9YPVa5hgAmY6p9yoy9SUvicTo030+m6XlrXOVImDC4JZ
uuyIoc0NwLN1g4YbCeyCkDxl6Ykm4cAnekIgIbEE/GreCBycN4IrO92o71GH28gtm1DPB18Rgozt
eqkDv4/snfw6VuP1cGAM4eieZCSydFRSaeONeQxb2aszoa5EuKuTffV7gmGrBC5cP3IwkdTXZXmL
pbV8NRnMroej/kG173pMAfePNgpF6DM1TgBSE1Qa2vu7vmaTBU3XKmsdDjBCL+clEchRgZDoDjMx
lWKMmho37HOmy02+8siyDxxSZj8RSigjF325KBrTkWEYWMNF4Zd0Lmr7WwisDEb0FtXQpOgEem6D
yEPK8UEGnzB4d8G1OhX7SevjY3WPvVzij5FCs2giQ2vDC6PmkXgLpo0rSYZEaQN2B/bRb7N81Egs
EtVZ8XByFRaZoEi97+Cf6FAEteUeWMhihScA1ipAidodapeR2kx9QIg5B7R9YcY1O26PUzZWVcol
y6g2qqO4gt42TEPwTKVQMvS8qC53Wa4gAIif7+rtmIsbMSOR+5l2HlsOYecOk1yqf6EddMwAABgN
EDbj35dnRi6rZH7+Qyx790/xyL8QyLCB7h/rkYMo+YqhfQR61FMZeSPkvE5wFXu9XlionCCdyLgy
pADhyYlxQRdiONcllUctuihjom9FoQ33wFAZUISZcoL18idIqJEv86r6gGutOe/erLvtYqmvZ+8U
p9OgFc6WCKicebBE9fUWIQmHJFgw4Fc34dX7iBAtYo5fJ92uP0g5AtDtagQ9ICuTrKbNEWrvaKgP
Z6y1+Yn20MNB5uPZkOOUVcBt8VkIjORQk5zadgOO+zlobvdlLnXteM91NS1qrnwKABkXx9HeIMYQ
hQw478ImmiXW7iwQxR+yghKjQvgK/zEidoCuAfZcFbKVX2wNZQ+ZDc/wqGLhsVA0n44piqU61nER
hfeKrDssiCaj03cjkqiY3JaY0rQTMRvFuQpwzoOlGP4/mZr0WvzjbUWQYM6CZ5qffH9n9rc0C4l6
TZADX1Ems3i04me/REN4sD4sUB+gL+6H/359xuJ6g1/sIGWnvrgnhdeErLFODDY3NI/sBKreTtX5
czajgoUFnawldsFLB/uh/qaMJua6VY19tWOuzP4ClYJ35pHvh+O7d8zWivxp63BLeZpYePi3MDli
+CYOdVGpcK34X5YjLgch8ez+VCRgtvxa2T3d8ku490nMU6FQ+TEPpbTu7vTj/5qKsO4jOeYWrz5+
iz/WShPCzAHqSjhub5sbkwlhMAvnDO0PSTEFvOrDSWz2kxNl7N1+UY6fjf12n51SiBSrglgTa1D6
yf6VmVT1OizpiKg0y5J/EOwDuTlpV5CZab9aSr+QxYjqnBiF1AO1Uh3TbD1mGTSiVHhZEw1Zh2tt
PMSLykRXdNXwm8vx9tW64TkI5Mw64f5mPlBksyOegX29voOBzcu/Lpi54E6Csgxzcyo+yW1C6O86
I4R+dWl2Nu/9K+ns+YFODGX+i2zlhhOfhJF6pckC6n+znTXoBEdTiURloMaiB0YrZmeKOk9D7B34
KwEJDgDLOf4N824KCJW/cNTa42FpFEJLJWgJqdEniJ9te9HuMPh47Q4JmvLHzk8gJEZ78yJ0/Jc5
H7rSgDg29ArJFiPadhGUjRlnpYInh5uh3mOlEG/7cZy1Pjazuh8lTtDABTgOx/Ay/nyYRStZ9mQG
cJk0HiGJ5OAhGiMh69AHOOxe78VHgR9xIgTc9xeKze8HsfxMUHuKpco8VDchXc/F78fVx2y/o4v2
D73FVRYLTbzWEltc5CDgk3iXWkwCIAY060VBFbrk7adJPPPEROLFFFzx3KRZRRAR/MCshpBXQu0o
qZQAnJgmFHOqVUt3hiw1l4mBIhCG1eu7uiMAVIlSdcOeb1hDDvreYdQ1muaKZ1tTRM8dvfLTHgze
otbvI0AdsEBeGs1hXDNmsS/nAuGiV4j6eDrsmACSJWapOZyXa6Zn9u/e+NBDwn0C11e7p+v7Wscu
AMJlaK4j7Lx+rxi96igcyNlTpKaVllMFzP/uRZlOTEDu4udXxKOE03BhWiQgmSvT0lciTZ1rO2Ik
df4/Y4DeMmfTgawyA7R+9oEFcUobtGt16BKOMTdxJFXICP9EfDi9Xva84KmjCD8wDMvqWXiFprod
Y+JduLoQyZCE3c5R+217Ir/ZI1voXvUvFuWBkzb9OdXFyIBftEL6XCuD7qPICUD0zOGumfpP+KOt
KcOeKs7SyBl/c0JD2F/+gUEImu9sSVESIManE+Kctg4Sx6DbVHwaamipxhJKV7S2CCQvz6bDhRg1
xun4oF+GziSpxSsbpiHPvJgVqZhUL63RTDk9bPyvTWTjaKSY6n9KOLYzAFdEgtUtSSi0/a1T8M//
7eDIjjdekjJb1GNaM4srQ32DJ4AaKqJgmTXcKUJ0eKv+2oxYSxvZMHg0dvYs6GZoigIj0WJOdBTZ
QvuKmE/aJR+vkGIcnQsNnEQyjx+HaRmWdvVhDAxQaSHTS/cqvoYTpPhPSMmXRawhQPn2dM6xEJgq
TZweuGoDm+gS6KXs5jsBX4Z3ffChRekS6XEYs6O7ihl1yMHriX/g34XNw4bCqy9c2IJ0/KPnRvfb
aXHJQPqSof3XoNM15TcB77b8gzsVmMoLLlNFOCFV/hqMdOg/DWiLmXBg3wg0y/Iiwxh/8CKqxiBn
KuM+lM7BA/7W2eqJM4ZNNjh/8kLq7JkzJn69md8YrG9Er7/2TrGGDNWAyYgncjHWK4gbj2/CZG5X
Jk99JhXrNb6KQOLvJP1KPvh5z5eimDJBqt+nXZqqnW70dJTh8/Thxmt72D+MDU45cK38II5KrkZu
gGBS2/t5PH0l2Lr2wYB5b28wEKaaWmSHypu5BnrSzI4gZkomM4x/xvN9egbW7uN9rBJeN23UAmI4
OVCBu0oNICpMXPfmMvgHvhY4QhyVRJfgCC6I4fJl9uNvRBqNP5Uv4DNohmu2MkNzftMznWRS7Dbg
hj9xLlndy8MOKL4HKB7ude5WTtOVhiFV8rZVdT/4WvBwY0oimCaYPi8U2AZNZ8BWo5+udXZNWB4V
C0vvxJWDmxFUBaYYChaYMJzgagdPkp1QY2PwXTBE46/KXv6dSVzUs9EgceFwkuN1k2eqj2D6S39n
PNleiOGqC0/aXOY4r+v0VL6+2uKN93HJjxMigmeYapEUPp4FeOlL33pYT5itIsD6xyY6tIkLVEfz
3mOHr5WBOAYqzy3A2ha0K3hj7H/FkoLkZa272b8L1EIr3VIkWRzKKT9+d5R31w9MMTUL3N5+UOlN
X4Ry1P1//TQN9R2rtNw11UjCFOzs0kB1XYLN5kadxeaOKfkd2iTacjR77Reowr+mnukZWUepdD44
QjW1vfHRCA68ly0RAaVtuh53lA2CZ0YX/GRsFU1IsfoSia2Rg5smeDPMAzikY4eOt9BHXBAH8xTG
u+zUzXD6zMiYORiAEQgzGtCvTaE05KUOLlkYaRZlDGV1fCSlh6WTml6q+SwOJrC1ejX2NCPmEWH7
N2tJeaGG3aNrM9NQ8kV9ssUw8B14f2TIw6T2DuzyHWvbImgu9tYeE0xVF0mtD6Z8yrvfW/w8IHB0
IgDKzEkCAe/7orLqkpusP4wcfGBhWW/vEfMqEx1bh9i4kn/8CBuZwqlYSgnQJoU7b8j8RHWAaUiZ
qefejf8gwloeZgzidyPUW6nx4xrogMvxW8kyHUONzlu/K/f4IocTWHYFfBvBH9OK/iIx4Cs53VZ1
abETCC6Y9f6Zn6E+Sy1wW8J4JYb084f5PIhtd/t+fR06YcicQOJq7Gw3i6GhpXEM1kp9SF0H4Jjm
OIk+QQyAWUN57vs2CwMZU5t/YlMjp4AcvF830lWOahhd/YUue1rsfx/UiWpqczLC74ocC07qMVlA
yDGZZs+l9aBKzOtjbDN+XM9OxfqyOn/cwHv26h6Q1UOu3xsh1BZCE/1JAHP5ar6U7wS/Yvl2KmJM
fDKBQIGPzqJU6MJ/2e1llciQ0EYTx+S1iz0wek8RTpuntc5y4Yc/cApCsEzq4v8016D06fSRp8ns
93UR04ZPWOg7imr72ZNGXUUyEcxEZV9vOFjQeAemScX4ZaNutQrK9abZLWP63MQxyK+aO1GVk2qa
s+EEs6qb9gojK0S0gRVbALscn+a6iPKD25gOhaIPYoupmKySR75L2WX50CTgaaawRxbiNhME89km
2QuFmn79OH29A+720uj1HCTJgYEfsOZgnoKPJKzExqWAt7OO7izGDtqSUeHqn71C0f5Q4NXgv+lD
ktfd9R8DEZJDtFIEXjT21spIeLYnUI/5gak7srFsfVPj3bfAMvH3VK6PTtroxUixufavRRHlZQsB
ox1NGsTLNfcABNpSw0lf11n9dlgp5xSjxW0/7y8aF+2yFHWQwx7+uaLjb/HgbAAWsXIdptJaSOnL
UT266g7VFI/E5xfM3g82wyi6Zd0mQW2//EGAU12gFJdhDgT+r840fFFmw47AP8Vd115wboJQKMEo
d6DuMS6dLzT5W2XUI+imEab2rQtMgEnaxEKqQSvpwkn16yck3fdOv9/1mj3YNt+CQMj4JD65TqMs
peBUB29oQhp1zi+EDZ26/r1LVgOxnHhUk79tb8a5ryBQn+F83S6mxRtsCTgGdGGYQnYfa1/Z4gUz
BNyRuLpWo5V8TjM73smUvXQc2VmOIVePtpr055HLuZRZgOfx+bNMjaauae4xoe98K6R9NZUJjiSV
j3bmEyGsETSJGuOnPdxW0BOUf4xQVwpmYWfM5rWYRLIpzWqVJ1KXIRat89mKHABRkwnN/V62gIxw
EyZScP9ngGgjNxtyzv7rlIo0HCUL6tMpxq39BugOgTtOflBF64oFBG91j1IAkfBSwcTVAe6e8Whq
6Dk4UHgdkOK2Pq2BOZUr3Pf1Nrg/FWl3zPI76d5KtR0Rnne5YTGQEOnjD4vcBYpF6Jtv88ODYhS6
AfbLVNtu60V0TfBrR+YLLPED07tUe2QZsB8rfVzhvenzbH/jJFY0EQvuV9wZLGKgklaEvAmU+3Xz
PMGkwp8MMAaD++5UbuRcu4JsXdd1vy2x0y7XPwKedEcGLmHJhBfWlEfvquRCEf8N+bwdlMiZkO7L
EVlMcjkNo7IVejMYK8RfcLJ0UGlm2KTaD+WRdo0yw6XQMiG0d2MkT1nzM39tmBugCk9Y4oprUU/x
UTAxpkknUILJMaWLtXOMbfGAEdcrQ3rlsGEvhZTtaoDPxMO35GEfnP5L3zUrpzSX4yAImO3nindH
iBAP2q96hUNVpUp09ztae8h1pFn21aXp9TEeHVSKxRH+J/eE/RviRSIHqnFH1MXsCV2q8JN+S/QH
ktauXBEdafToqDdCvTdvZrT1uUlBID3h9a6/pT3v6oclWDELWuvZ0EhErTFtXfQl9wpxoCgpm4Bj
dOQI1gItioAX6Pq6rBNSjFwA1DVAT79aZ13BHusqeJsRQpsR4xzRkgEyhoBh71iYZj7jFNAGcxz5
gbNDnxao0q3nU5oKlTmZNsXodWLpo0D0XpWHGma88PeW3wkxvlkTAMw6PYc28oZ3GuHLmFo2qnvQ
EvhSpVKcsDCyTgmHi5qz8YnJGB/fM3u2k49Pd1x+6Yo+6ngoixPPzYTf/p+kfLYlmBHN0Wh/tJHA
vDvpW7K+vJq7IIe0tAH/wzDaY7CcHPF7PaszkFYK3/qOx3l24jybSJ8Ca6D2nIZ0aYV0utmZ3LlF
8yotm1RTgsbfZmuXoN26F4cBO2dTe7B3GhglkIh0mvNI1kmyjPxuYeC3xAoa5T4XC6ymXTXx3oxs
TJ1RXVoTen7dhwn87DD4MDgOjjhJ+fkhHueGBnQNdZJM+hqzPIt1oRMJjpG1KvtbYQtc44EIWsWz
//rhsGM6U4pZWLOOvoCkY0XeQ1ecZB7VJnhFn75fRhwLxBCVcynVp9QrpgX2tTlOzmgobAORR8Sh
HNTvSyFcWtevyVToQL/L4vw5Z2Tnn5+cKqS0C2LEmJgxQVpgm+Fd9GuVPk7I//EsEdXYohLodp98
7hZFKCGjzNFGp8rcSfxsz4/TiMBebB6RwZoBV+jfEp83KyayGIher2ImlE+v00iA6V0E/Wov4FW4
rSge6Q7h5lQrV0BIG/Nmsm17J9wk8Bpg5H2YvFbhYz/JITcrMh/EDUaUrKSxlyNZlOaF63iBPfTZ
ygwbCwJE9ednx99l8rgT5fHrJe/s7qQh+XFcsErNvlgd9RI+U1VuJ5jTZWNgeb0BfBD6D0Io0NHb
PPEEjIJt1hqPjwyDZikL24gKfaBV63rsvnwv0CI7UkFePA6UHXbW0lIOoe+zmlFslvHcshxhz9xO
8n7fSWxw/3gg+T7zxXvL5J2rXiubCSKCIZYwBwf0ba6fqVE9NRCJKzOcJYlQfsK8gEr0ZCDC5sVw
TQDLEJXD0nCMIir+DausCqXiysVHlICYmFSQYx+z5JPvJERhexvDybaqwyFVb00zM0zCZpuSnj/E
87psEm8LjmgGYPOPHwCrsU24jGPmF4y/eWjp5aVWD87TIsmnJztXwkYKk0W2fWYw4JUNujT1v5R7
REEBouSWqS1zoFo2mMYKBoc4tuki9ZOzKVADWUG7wgYW71o4mZl1Nlh45X1WL02g/RMtaATNae8i
EBAN5M/dK0YmnODJvX3rXjXwrxSSVPfMfllXWfUpQYGcyWCz+JsidLCXBOJuTuppdznt1dkWMdFC
U+U+6ULFVDH9Ave7TZN5Uu4/D+Or5N2SvN1yPYkJ3+jH8ZVnpNlG+9jQu9wv9Rgd5+KnlDz4jSPn
KUmyGwrnQG/1k026oeFrHqJ4/4WKHPQ97Fl/G1AItIDc1006tJdUPdxuZfiCh3jnFjBXwBvDVe3H
yNmSloofPlxGQ++BCYZye3gxZ8qqOZU887fX+v1MvOmDsQE765Cio+YW9BBCyvMJWHXk2iv964B8
MUg1YJi3ZgADV2Ma/xXbVcZ+z0iQOKAC88pR1xxj1suVE7MXi7XlGJMxKgrvntoMK/SCG6x4/D/+
6LeNSLaHNWth9B0tlvzCN8RfR2VmY+3HNJaZXcpaBMkkXNzKqm/OOJTJLXIqm9izIZUQ7iVMW5as
g2AfN68oT3Grdek+XmPkO9nxToSZ1h+Aj5XNoyy3jjgnbAtMPq+NEPlo7iqhXDidsBa1iULveO42
2OCEU9Cd7hTicEeFhxCDZcjiupJ/2nZaPtxgyp3cbVjPzfwoAnclir0h3vgLFKxrO0ZyovtK3x9V
JGC0H0gdS4XkGIqXGqcDtL8dmAAyqXa7zsz418lxYmL2IfD7vwpb62vRaC/nyDsXUpWVlP1aK4oV
LlDdpmmUde8JpUOfeQbkN61c1RdiPWAZGt/as/bnznp3OaXQR0CsRlEcMi1eHyv2jYOhgPfRlnfI
T8kWkOXpR+glXB1Ez/qPgZCQsyhSQ+oWvCds1Iur3sut6ZMZFOJJG7WZxHKH9q3hlDii8/O+q+6C
/UjbojYeQaGg/iT0aiStr2c+1T1+ibE3jnCrpy8siz8rp6WAAE8vPJy4FUrQWY1XS8fV/PasIebU
z71pb2W5Chc8gZCpD7VauoNt99mLFl2AGaJgyHe8FE7tkzsh/iYm56s4PBtZn3ZgXi8YcGI0C8ET
/m1EEoX4KkMimdy2YXBes+XzNfLmRw1IQvfLwXO4jZEICyqcICqJUn3FAMth5rI3DOqtKU6BQmB8
haDSbcBPeMY8yTUPrMyss42/76uGwqeKf5UmatGEO2DnqX9zTalqRq1cMTwXEHa1+JYiOO4huphz
a5J1bYpF5caa/5188k3Ut0Yy4yu/Y2NcbJUe7/5VB8Rutly9/5o8BY5lPgl4JzL2oYuA0oO/H/XX
xLq2FwaGJ7ZsXMHo6VzbyrKj9ScvjFB67UP+8/z4OfGZ89YRNn5t5rPC3CNsdICxxHH0AQedSk2g
Tzw3MZ42zof/J6SxJTkwyQsT25gZbPY4dpoJoB70iRlIWX5f1zdI2kgNOxYRw3kf/3kyT2y8QTeS
WqdS4kbDqYRICsSvtN/HaNfzFOEzcMGsfC7Ms9D6ewqMvK5e6LDxIe+Yi57EP/lpywASu1S0P0ws
4bFSVYcv1j+fLHmTSDv2YEnPXgcEAgvFCtYHRDUzvMG1C1O3fB4d5mZ1jm73BfZ/I71J2Ubj8OTZ
NU3UcCsoS9b2RE5HSIri6xNTJPkZtz2Ry/sUy1QhWNOLLMXAmv5AsTJqIRBIVGpbhuRxGcJa528L
fjwn+Y//S/WODJaP4HkCrXorq3PEE8AxFQ3QOl1W8M1ytdHxtXUbiGruE5ieN8IrGrN+FxsoJ4WI
pb2eum37+o+bUPVosVQ7LM98SlUHYjUXtKzZZvpZZaeb949Nb4rvzGWp7lr1uTaYt+KNMY8t0xkj
u+e/HBeNBSdpo1S6kg1bScWuSMuMBjRexrg+B7q+oECXHtbQxYdxV7CzuugVg/kPNm4w3i/AvUGR
R8xuZTr/MX3hhi8UYz3BTt+2q+SGgWfhZVe+kNkzZCmTtImAbrB+WJSQjwS5iPcbhhj8k6S+sGGV
xuIhGT5A2HtBvjj4NJ7RcSGUauhygeVHe8l0bo3VBKy8GMXGrpJqaeJxGTfzq3BbocN+ftWhBXjb
1UR8LqZZGJ7oXlIiDRBEtYVScGfaWNi7fQNbEZecm7hQkEZb20wAQUIGeXj8Cx1TGXSlUtvR8tqS
YOlnv5Ja5qLfshCXinYTPfqZWVXGmUcTZNdaDpwu5xuch7Y/AC6dF93BP8yroRKxW1tUaHAqME1v
ZkSrsGyWp9LRr1ACcAXgBvLZRcVm8RQXIS7PRfqemGWg+lFL3b3h6GB14ymur2SF0bf1SYSECwRj
Wdss6+xvKn58+F5RpKQBaDYx0vSVWhbVGftUHy1HLHrWPGsmyyhg/My6wCWW3wzNSem7RaghqER5
9pNTQXKxy0AdPRkxjGosPEwf2mosp/aN3qx9TV/dS8ZSQ1z7b2/G0YfjGRrCSJ8NfNjkoEWxN0at
GEstQ91l29qX5uSXfjnTHfteV8waTSFwckLaXg+Ne3sCxBca67qdNwvMtfPdLMiT/lrZui+FNQtc
MQOWnLYBUt3EZB6XuEzldUD6Zl9RoQqh8f+EnYAvdqACGNs7ua5TJnnV/KbfTamtg/35f6wBS8kC
4utEjdFEFZLAKloU8Y1jCRS9rWkXDpZKm/gYgK3qih8PISd33ziGRGahUzGktQMuLyn1UR8NqpgO
qGHkmN/KvOaPVcmXphUAWDKKq1m0w2VfopOtDsmoQweqQ/OvUgMe2ikMczru2lCUptQ5yLJKNDLX
ulwnOvSDbLiUcUFt2/1VczkKL7rr1AJiZsS0qIFy2PJAsTni2iNXVTa2K5SLapL6O/DNdu9+/GtR
PB8Ln6UITN9ChYXN3RgnFQisJmo7UTQ8NN/vqGEJHz2VvzO9oVTGZDxtxW9bwGcwtYnk+I+N7nL7
fvvlCfRCkTkmaAblVFzJTtpgzFVPpZVe8coi+fE3z4PeywcQ9USCvMvQOdO4znqaruQp/UHPFJmy
BrG9/+1+5bTEve1rs8ezcLkZVobUu4I/tU7vG2AC57KPT0WYWtHgTSYqjFQaztIWfXpZQm7fFEZe
U8DXEXwfDG/O+IXf6DlvVYTvj0TQn34xXEA0X0Wh4V6a5w0AqaFJgXGj22URm9SlA7pQHyVa8RoR
FB1lNFb/QVJD9c9PYfjK5u5CA4f9k86bFJ0MWPIw3xzH5Ml1k14aW96tcq2/elC3YPxFMV7Mxk+J
gxJKEKbqSOnPqNgbc/+ZYVN9cuzBgXQNE1VzVnwc1wfIPzBtA9GLR5NII4O6HSTiwPgv+jTGkeAP
d+5yiy1re96Uifzj9KZaLWyNa0UIwukHA3+buisqUEcpdgIZAv2Q7Hgs9CcmT4APXkg7nCSbyZ5f
2hg4lzOmXCyVD3LtxirWKYzwlpFNMe+kY4f3apQ4iJPiZgAPjwQ0lhN8TWp7o6wvnG75if2C9ViU
8LAEz2Q08bfc7pjdYcEkIqNxBZ/SryZGBP9v9PANeYzjhtl566sQE7W4vf9m7/eCefa5tFsIvBZ3
lOZDTxDnguGWixyBDp0aUvWqiiwqf5O2tAndjS75W+LUnBGmrglCc080mgpi3YBHZ87RICkXdr0E
oSJANKgRcTQo83hhNExhkPu4FnXWWZx1WGLLOg29bPtWwO/NY4wSujUJVP92/fkLM4s6QVWNlePu
7Mb4KXHrPIOwbEYjdNJgrXTFKGEV8nvTBNk37sTOjFHeOXPSfHzb6AnvZjrOZaxuC6eKkbvMbKk8
APvVYcIUX4MSclz97wIYQXngcvnXDLlfuLphL1d1WCukz2FVcyhgadeWovIfsgIZnN9hyJWdBs9w
Um4Wfl1b4Wi/0PmzwCGGM/YqQbmdyXG3lS2YhROszcESH5XC3jmKElGb0lXrjK2AFrkb9aaUbhY7
GZ/e5uLxuCAJ1/kljGgV5YpClXbJSTyCmtgaUfzfZf8dcJgV7GKYcIHRmvjQgXjjzLDv0DNw090Q
w/bWY7wDvpZ9sh1JIkeFHtI4BHwgrdNFRUn/4NeTG8rwHSDqKZyKiIgpLn+LjLnxDAAuMZL2nAsp
OkDnM8QKbp2l8bEhD0aGyy9zkBqUku8fdnA4fEewrcuBbiM33fs2Fr7iwuyJj/vEizjG4PKqpB00
mdOHTJjpiJF5YdXUgihRraDGUqgHFjyZdRv5UqH0JJqRhM/+33jMrDw5IkV82ElBWW1c7WDChZaF
HF4hznIB28aDioFpyEo3TcCz/sfrpn7nyXDX/MQxBxFhWss7uCLsed0Oo3YHtvATKEeppoHdQNtW
/fDvD9Ay2OqfJAeZGOutXAw7VeyZGZi3bM5InM2aVlKdh6D0jnZO7/m3fesJ0V4dMz1SEhplvKsC
SEyKPs6YO6cdvOKhydr/5Jwid7jDps9GjabIAxq8YKKnmgqbKAVeNWN8Rw11uRVwggJxNQFnar6A
tf+TIbNik4Y4vOkzMBRBMrGGrNxKhzw9BLzk6oHD5zssHrx1+TMVwWqBSd3go8YRiKtOdDmSNfFW
idx7g7zoklqHsjvC1Y6TXWhTH4OmU9StGlzJ/JetQfRNfUFX8NKVE3f1PSzCk8A5+WBGVtVZStal
aERaTnL7w5hMzEeshyHi5gIQDR5yp0cbXCc2TwdzEW4enIg+yIgbcKPDLsBZNdChDgOq33TwE4w8
IAajmcRA8/SOxCBcj9Q4PHa4B3uk8O6kDYFFzAxFHTjHkFeU1p4xuUcIKmBR+qtjRvQBNkvBH1Cr
Pdq+k5WxSZ3YOcXfd9UvmrDhQVwuGs9AszHfaK3g1whwGjlLy3S+ZRowHF3h4vGezqJh0OvsakLU
LK4F0ox8cog2Vxz0CzIEXkAIOs+5zffK8yiGYYDANpUWq5dBwq1UYkCS9LOjmcy/BB5ASQ+TaH3S
18qi0WzS7fG4ym0YhsLaYD6449v5vLRMaJ13OM0kr1p4op3bplYW1lG4LZuhIpw+fgmhs6GcdgUK
7+Ki3bzehzqXzW1gwnE8QklDTYjCODEO07xyWWEUHxV+hK6xNBvK7OgLb2win8WW3jnr5+xcmNI1
RAxckRkfKaueKytv04/RfauIZj/2tTfMjiSRzfcFZMkIbQi0J38XM+KP117sljpAHwJuNOQKabwp
Xq1EMijDcWifJyy00/4U6SXGXYxWzuegNqy/TCC65w2DSO6CfLfoNpafprp/1INl4nJF/rJv3TJy
pJSrY8Dc+X+3b6eAtHKie6GrpgeoVi6UsNccA26Tu5DEWvOjllvblofbD1uSnnft/NitkkEKJKAT
+z9j5uqSMvIf/V23cbEW8cRIjzKQNHhQGb/xXdZ4f6ZVJZECJSftSulA3oCgifpzHt0Uch4eIIC7
RZUUTsZ1zKWiya6YFQdzpQwfPdqlDymsIFsmgOR5Ki9tECt1EfkU1YLi25sc9TNt3xo6i0i0i0J5
QzPM5oiSsx4N06SBfuXII603apJCNQONkzQFFHIEcRTiD4IUg1N5uPWLD+AYkEfXgV0JOV9wSpA4
YpdjeLB1R5QbfBX12bF7TIWSitlDDktXZ08KjjHRQZTP69MB8FUy5LlS6svLQggM7g0aUVEBHIJf
JZo/C6DG4AkDkN7uigjStcXlQ7sqR+rIilPh+MjXyfthCCrS8sJgJwdvdDXr6GqJOO36lyaw/s4d
EEFt3By+HfB36D7WBT9/OW0+/saS9By6msiGxT7ypWgQG2muX9QXDC24rlk0wD17zYD9+BUmWvz/
5MgXEwC3nlAgX7BnyjqwYxnOrJySP0yOd3s5jAwO2hFequbYkRUJpGlXTHVQzmOFbp4n68Y8bCzW
kzsDHaX3nNDtXaZb7dSwHE1m060mXrDR8uDgtDdF5AZBhuoAoe+0Y21qKZLvrDJk6c4IKDLchma5
VvcrcuVe3HpOVMJtn9SRk61OKdj+rBITG0yu3hJfJe45+9yFG6OszEFqwurrisNmgYvNP408WF6Y
L2pQwk3CRYZjc3N7/+zHKMPGOsUszqJEx+PZNXvunWCuI2oZY7te6+bqgDEg/FGJwomG2vJ9xOoT
9Mu9vouR6wSv/Q1d+VULCa/fWCEYv3PJr1sGjHIVs7HxD/rwKvKzA0+etI/qMFHs4Ju/2yxgWoHN
5CG9ydTKwda3gVuMEkK4PKJsmXlO1DMR7hUKb2cA2tenNt8gjO4HFoCQ3kJWi/xX/l/YJKkG9WOx
NowjjBKsgoZXmrNvtNKKd9vU0buUEatAgx/3wChuEcf6b8G/m4Ybp48MxXcOTL0+parK+v79yONx
YfxTJVDfjrhFa7X2hazvILG9FtpjlqqkGNvkFaCiqt4BHWMGvgWoC3bgEKvov0QzIukFvBMrozCo
eTRmZPLgZ1AbEuGYOrrItFXZKlgsSNO/Z7QZPU9kkdeQJN9998kZik9VpkqVL2kiMBiPTL4QjtfT
bPmZaKGKOEfpOCK28g7gLDk0Xryoc7ZkYLr/zIANKAmvNa84sarrHhzdDyGRORNWl8bdeLeUpvUh
mGmXitpTaIokzFd/ofvV58ORGHsArPBqX2k5nYopyjYoiIKYgDN78Y/l5jtxcDvbyptGS24aZgVu
/H3t+xEGRG3m/2CiNjjMsiTaRflRxiSWsc8BJesvIC6Zo4Edt0nI4k/XzT7NNSdGBgOBCaR6IJ5z
sm76ebCveeiCb5jSnSqffoPmIF3rhFozeXSkCkFw+g6Xzu1Q85ouKR3lrA9yV9KlVcQ+y6AhINxR
SYwbeVOiaJ6I4bnHp/jxfviBWlPk3MgC8Rz0mONkMGbLlW87vJ1O7iChPfAL0HJtQrDVFYqtOz49
mhSDh58T3JZEhtLj73vqWRdtGCoFwvoEkmKTRVVoBdx1wmoUoCEcESWpIccMiCHYwU/wH5EyxqEu
YytP8HjKig8KLMXeAYCho0MTtmhaPo1JnZVy1+MqPvwJjNlVU+j2BsKQ3mCiQUNoqXlhQF+8WwVc
B+Qkifu5hyLt2WrOUJxb1eVnpmGudx1s7No1OLVEg8W8hoDCNwcwHXauGG3WQD3zdIobP8K2OIoN
tASvjTngwdmTnpows61Hi5zyh6R85jDoSZBlJbM4KHjWcn4mmCXZd07UsxzSNb/nbDEWMJ3kVf3T
2IA8RuZabEc42DpHQIU4B4m8dOGzTGC42QQrt1VeIL311KJSz0BQ4kexsxA2zZBXzfzS7YNE+zOd
VYi5ROUssivlM5unie16KUt2j7+1b6ORfPF/czkerTcW7fKjRwvu6uxlfcjF8XyyCkjFCdUWu/49
vUZ6o2M/kQCFki7er2lb3/T2JVcUL6wkGSNavhZpibtpWC29ETqZU1FypLSogqpNsKcircJYX3+b
c0weMGJntpEdPlYg4AwVq94SdQF8YbcalgGt3CmiFHfM5z5YNnD5E1v8PIUxEMcJcxqm3taGmcs7
pqC9s+IHzdhp1sKhMbSvd3WwfxTMlFOBAum2zab5GwgwZCV4nWhj7MLv7WbaWHwi+RPs/FC3rkgR
+lzD/QLN9GAPi2+cQ8TSCTBUx2Oc62jtE3ffuHhu6SFcSQTVYCbt2Yh855YlDnXZUrEdfqXjZxus
cVucSsIyMLU6H6g4HERzyugMz1MYx3JfxQW7dB46jv6od8GaIhpLPyu5ZToc1OC+hYE1mC5hkXab
Jx1B0XzcbvNUb7M+18VhVofn1WLluh6PhAVYR9YKZ2VoYQuJcUripqAAOKnszmqx17GUMWPSIGN6
vq6t9ZHdGq0BHHOXM5qXiSeCJm6Si9BhGW5zTWdiAPLF/2zNCVBjv8CmNodNlnzyxDTAgao2pHbw
2kiz3J0tfp+MAKYpRqDJlRqSsRcbSW3r3qH41S3Bcdqtshh8sfukUZn2+/MtTf1+OwCmTLEb92Km
udvrPQRLLiq2wGc7thI/iILQgBw3o0BbPVKrQV79e5Oc4fcTToPRlG7HKUwxWo7SfKd00UyN+b7t
sDx5HCJdxwJ5yeTaeDMVaxtGhbpTxtvHiCAZmMmDEdxkK/zxXvJ7jky5eVgDwT93DeGFKme0ELNS
0Cm6ZVOYcz/9a29qdHl4nHurk8iAdZcrC2AHN4xC0TW8W4HsZfAXje9EyAwPP6XL3vUQgxlbFFFb
flHEUlv1OiJPKW0azldcQblMlKktGWqYlMA/D2yNtAD/bxnZyooZ6GWvpjH+I3A12rC67odXBOpY
Njs5cxG6HPXOwJnK3ovhImamrLvAOmN/IPqFbFaFkwRTrqiRxPoqM+DoB6r+N7c5JlnjjwhgCl5O
RDpI0i5gosMu/nbtJawTjNSoWSi2E4NC4BwEZp/u6DADM10QfcalHA6T3w4o1tHle3FGWeu+ZU/7
Q4Kn6t5e8MY3oCf+rngh4JH4XnRXGHicUKdYejsfe5qXrRvTWN0d0nwbVmHzcNdgL0KSysLmcxiU
wFOT/0jtfHbtueE5I4qD0ihIzSDPZ1cD/iP3946lOM7HScU8kvd1WbqGmi8WwzoKpEcrTdS1D7Dh
vH7zk48cI1xATZ70TdIV8/wAnAUzMigVhNha78YiMgUsoGMyoDjGSjtm6Uog6OdtLnSRyvKaU2iw
Bu1eUWZees1LaMem3b7G45QJdP05oD4QqhT7B1ecMozxuWjjeiSBPvehKOoaTH9qHtO7cjNh5L4f
MtZuiYc2h9sT6aDqLn7WknTygoND9KRtsRKl28LXKoPICb4MNqz6KvnpGJ9fGYftHnkOVhmX4Bdz
+9jagAfTbzW6tB6Sdb28bPr5QKbVUQrBv29T6HRruZbOEvztNKYlH5iMnwc5HVb87xGF8oAvIV9T
ElTA7JjBTnWFlXQLCfHs4g2HqnCHHNqQ5bB7LwjyxjXupZJOq/5OkH1750gja5b+FsgbpvzUHyds
Q2QjgQmYNWHaY2GW/6Ub5Sv2PMqhkYKjqIShUTaYvKe9d07WzyVzCZJmmAl7DpoEsf+w7fMMMJLW
iqhqc9QrYdnJLZzbNy9vHqZzuIaoG3CZ28Eu6+5OYsq45ybrOjdsbA8vGFaU29yNCN17h/8YY1fx
TlIysl14BYTIvkmDns6FBxsYu15yUFtcbVrLPlXsPIrKwTrgE5kr53VcY6hlDvIoS+AfhkwQMZ3c
37+tZ0y4/OsE1KXI7dVeP0oEKkADhgVpsx+h+Gv3bjxzwpltqVoqfsG4G4GAzWsCZwL+UKi/WMI4
vlrfIWBmWdO26QNpcvHBUq2CRX0GfCdtHnh7vWniqb3BxyqdG9kge+dHHiEyeuXp7rzyrfDbovjr
DLrmDWx+ELgDlxItvZOaUPVX/lV2NJElvGj78lJaY3UnSZ3iLGmThx67eWSu9RNPoLYHE4cDHWJ1
ZxGGoBn8r5dlRFUwgfPnbPXJAXMykYPdjYenCgRRbZE056DRioXXc7IIe5kEB7paS6oTRBACh3xW
wfds/7o85HdoAzHR9opuhSFicytqHz32DQq1B1I/vIhBWtb4ogw960/PQD+d+Z5gF9YlNrKAA05K
UCrCIObBL1N9AGajsJ+a9MMpW62mT4IblM2upSG5NYQ/rLVgZyiDkloj9NMuhgjfqYcpczo/k3wV
KPdspRk+FJPiDrIWwM0fX1wSzmKGu7SEVhQkHyHZ0LCuOk2NqYc9rr9VW8RI/sPkDFFgpnAqOWc8
z7TzZvWMj5WuaY5Eubi56Ms4QPtv+nmnH7AIHCfaVYiByhpPw3LfsDw5nBi8lh0W0GM+3s+YzHPO
HtRnXPfKehGVZB5WZGnC4lH2BGYWmCeg4oqL5HhxtaZxUCoZfEXgxyGbPYJ/g3CSXt4TRkOhTmaX
hQsUIkPtSevsKfvnCxCXxjv49kEg9WVC/PsfnZBg7F1VOQF+jQ6eRz6E/KlrkBTqmIr1pypiL1uj
o8jV+1bLYsB8P1TsDoWU5/9VAF86QY78HEF2SQdDo3Pde7ShhA5XAPyezPb//6RqgwSW66HQHP9x
/qeM48oH+ghfP4elaXZlSm66NlaWqhgLK5LZUuNjwiXRyYHXGRQSysPc/TjOmSf/sagi+EEMEruR
UmzDxugNjsIZ16xsiAofTc2ciDv0Wah5s412TGmO8HL+ItUI4hj2N2tcBgntB36w125ZVCtpICno
VNUPi4aKW7OdY2WToi83VN7fqydWQ5nq65MBkkh2BBGKwmSbEkKi9ZsoUfk3nMD7K2jJbk0MRGcF
a5xE2PJYDKDpfcvwWwQhCyKwP3n1uFllasVeP1PPZsEcrZbvZFinqD2rPx92eiz6bsPo436HGqVt
/iitBVo0YDglh2mGT2ofH9afi452H+rloeF7xXUXjT2KpSI8YglYZ5L2RxkdUXSpz4mVbKpXdZPw
ccN/p8EdJyWMngHJcovRfJQAurp6nmXHqPYJe4EdfuBBJeIV2VtYhCmd502+y6xQPaGlJAS5Cj07
A8FT4ynYTphg/x+ptQYKYxDvfB++QbrDsfUfiDuFe/kVYQzUUC3xTTwZDVrWhYrwPIfDTgAeepOW
49CTE4gZWmN4oDpHyp4dszpBI2BlWn8HiYnG1E1tHX+c2CQghioHiZ6w6uCKxiPhZ26QlCCtd4fv
dldDa/mpiUk//L7SId0trP4+nb77MLS4MkFeEET81y3E+vLO8SRx/PEgiYaUjqHDjmfQG8GnvIYs
EtvytbP8jtuoYJPwiLyxxugWhsxfvL9hUpArqtvbIgQy9KPd5t89bJYoEEi41h0JEVtezakX5A9y
cGHW5SueVDItz1FDzMzHuX7tVoJ1NkpMgzb5fqegIuZMp9vHQ3g51ykvMzqxQdji3sv5/P+TJUKR
gTLjmmUKbHit7nSBl6hN0n6h0k6xx+uMifdAbU6g3FCpoxH/SP188K+GFDS8nTlftt4AwmyZUU6K
HmVUHHh/dKgeeuWkVY+1gq5FS1l2oaXMaqMPcqTMEQ8XW8cFSShxmGtc0HG9cE99ghK9F5HYO9FP
2ZtbTYajDqhinLmLv9u2cHwt+P9pMLI+i/HhmxON8vTBe1Mq/5UmcmcI/gg6qXEhg9/FRG5kc562
Bx5q7Gk2K3CeDXthjUlURrfwAVtZtZ7U4hSyRxWn9+vjuMikCW1+oX3ECwNasPgOpKUGqhhhXWK8
6tv/UDhgSDtXu3aCuD7uzKUqfPzW5yb1ySnWv5OcNZzOoFtneNmvEyOLHfZfnp4IFpw//kxO+J9n
ZexdAGzjOOMA8ONlfxry1sO/XglWXMddJkdoZwWrqZcK6AgB9oz4PxwiDuOmaGCi8ENo11NXpp4L
VTR4XVDQlOl4uoO651E/+7yday3vo6iJ8bnaWNexIll7t/0RxTLOcOdVDgVKf9uZBgs6IuekeKPi
b6ebugFh59fRRme1cMuepv/BONnOz0OJJjQjEfyDLKZUgxCMevDYIVj4mLI+nqEFuw7QscaLpJUC
GmLG3FWMPtPZPuf/yQ1azJjgCx6fEYtTs2U5FInmWZ3ueOmnbqJuthjPS1j38yyIajoAjVFs/Q4z
E8NQD02NYiW2zGNueZeyQIFPV7AMLHCZP7No2vj9o+36ip9PIZNHfjynNrnkTW/nrhR2p7Hz/WaK
JXQ9UeJh0L88wlpRDZUF90F1N1VUhjtTZnJ1ODNJRBg5J9g7IKez9CGKIfxGb1s5P5LSssK35+R3
q2rgw/gXOc9R3hSeb8qrzIiE1ruYbG7EouMX9jtW75BmI8fertw1BsgHP1Bld40Ta0gbKE727GiM
dWV0lShy5KgQK7Mm9tcxcsQP/FTUmsfaD0kzssqASHBaHc1cckRXxUqTxep9ZegH/uNO7HASmChK
yyUxnkiJ1FXZikKxo57T/aXmbCKvLGt8oUC8yf0cXrjWt1NBtv46lNzs0gfkpT4H91KUup849C7C
PQVm7MAxZLiJceAUGXwvOzw4awOF+g+D/14Am7aZqSpex6C6AZSduwYbng9B4dMrvw01brtSs2Tc
vvybJsAbc+AfH16rY9M0L2SPNt5zViWqEfBGpqwLxGL/yokb+c4aqnUN9uzXDFUmCrn9A+rd9jt6
jQrvGqd0To3O1R/60E4ajYa8j9FHYL6LS1CStVv+xzIX//FpGGn7OMW4u/Dx52Yc+sn/iYp/DHC7
Z7rKkYUa/WRwA8vK9YsWQ3+zEXWQnCjWFzmXHtZrGFsUrC6NOUVi2vy1kfaFEOac81p48WMGLume
B0FENeNDxlQNvHbbG2FBPZ4XNhUWX3you0Ygsirkof6Z+dkYHoqmkQ7kvFGP4vlz27o8YRD1w8fp
odpOBvrKvuvlcrdpxWrWXvkICshjU/h6t3nOg5Cicca/2m0sqrL3CCxJ+3q/Accgl0bgzrT504ui
xLZdfPQnGbxURV7D2UWIVKcv7ynxZluX1l5ACIxr68N0z+LKOtHREI/RvoLPN1fKXfOsxEQita1t
GWtp1r1ANRD955735YXgBvOzqn3j3Nm5ufLL3wOUQn1HUR7KJTpnjUgD2K8aypqghXwSkF8rAxpY
iIs6Yk+P3PpFvxaDMeQWfXdS9l+m52TdKz+E2wBv7YBIWnOcIg4dTUzu92kDt3XrCE+NAlbv19uB
LgnMBMqOaJ1Kn2omvut5vWgutyDj4wAIVPkhbQ93SpNo59jHNPAkETB7sBHTa6Hqhl6z58ImTqwm
fQN3p/EgdjV++TeHPXypzN7wnjCzF7UWf4uDHLZgN328CsrmLH1Hfw3wsHB4Z0PKxn9h7ySCrLjo
HcNZ9soBEO01onx+i6BErPgCtPL+nof87xPuH8PAc/h9qTCXy71R/zIpyEUr13U6umR/JrxMFEfo
SjCdV46606diiBy0FHyY7czZKZP0MnB2hDLba0X+/+a/Cfc8zD91R/WCYRYJF0LQ8j6e42vK8una
GznNQgxZoaI/iCIaa+hhAQFch4N2LAU/gU0QHCN0IekGsVq0HJEdjyvLJQAeKdAuVFSKo1GRS4eI
fZW9Sfy575NBywPAIE4p/fXd5w6qhGleGU7ctjnxgi/mZAguztuFPjtOUZOWYqneekJeIV6aEZNF
ZYtOwbtGsl0OiJkdDC+1sRGSrYuTRcv3nNaVq3nywQmmJ5xeJ6Y5WNJJvt5DHnrIB5u6HisfVDLt
hbG3/CvG1FmOz/+0aqH2/umDM2oJWQJPPP8yMKH5DNGlH17p/2UUblzqPZ5BMxroGV2Hi9Ntqq9N
X2fr6wNGjfJLVAtQbZAGu0osg8Ub7wcEaIE4QSuK0z53mwubp/HI8pgoykJOvG8AtJiZs///JAUB
v3vRn+MwIheRU7rU3GwKoTBujezR5ymH7bkdjqwk1U5A5yuJS3jsl3ZSdrr2DPtXvqwXg7ZAtrqo
AQkdPJsNuxc4ZjWOBN6U0sVM18cnKwtU37jzcpyTLY4kmjwnJXhhTaxxRc1KjTzuxpgOu+2DwY0t
jgiz/1pmT1KKFd57w23RFwX1evKQh44OJejkLhA5q97cUn1iMhPAT5DfX8of6B8V5wJuqtOkdYF7
UgIlwuqLsLrWOpcwFXKZbbme9w6JNq3EfE8eryEAGrtM2nHB7noWCqPcxYXkXdHIsRnzkLUQFfVM
5ufR1tANTUgRGhVuIehxxOTlFYGchIO1eKPQ6eXZSDaIWr41fsMn2LPqpFnT+6mgi1wxueGRpg8f
z3/8voxcYtYZz82P4GHMioXpX4YMXCWtHCgbpyrDxxRw2FxTcDWDw6bDf0i0BXL9qp7auDVz2j84
zgDiV9Q8/jbliXh1ERYghWF5kGAjKt5QHvla+Y5Es8ciWCEy30Q51V+RDC2O4Dtt8Rc5ZZcyRpcw
z35d/yATTFhjgSg0ux3ZhJU+JwneXEt1jZ2JOvECQV3X/hVR99oRmP5QVu6dpY8zMMQQC8i6N90V
Woi+EWU4rOD9EhrQzOJCFEw8KI9ZwUtmCckjREDY5qQUs2HWxcwtIYoYqBwKShG06UJJbjaq34Dj
E311hKrB5IErRD++OIadX6o6NX2DmXmGIZmYV55MUNUqBJB8hj1AkSKXbXck/EKQIQ4sM2V+5B1P
ZqAom4rEGKE1ouuL3eQo3guzu9DUh9XKVLxqXWX1IpA6CncDKe313Wbpo2fWB4dYo1LCC5POYPaW
EQL2sa0DQdNpab6kPmxly1lL7rWmgAhV8gkmlV2NXJoUMPblA8sP9zHFXFNWDxN38i3x5Qm4236q
IUa2HWXO2WtIB8BdAiQcx3hWnAqRznfapVy9Kq+vzMD5W6wKKuSKjBZ9NaFtM+fzhnEWjOpIaK1x
z9d3OKa2ZH12GPlb+jU6Jmanm1l/UYZvS+YGFyQqGd4ClnFns8Q4MK4uySB89/ClUtj5VMpBzefO
W5ggk8voMgd5QwsIqIb6KxWjC9hJKRiItRHhL3PBxuZQTNROBJH86AOsfNV/uRJmpf1ogCPpq6dF
kKfeQsKeppv7ov5NLFncet5udI6NszjAbg4S5AMpQt1EqtyBJb6RIPStk1RyFCmhaasf+il0HG3C
MA58PfZ2i/RtNSOMc4exrWp0k1i7XgsPejnZkqQhEh/tgqCYfjbBYIDAok4f7vVxr80CzabOx27/
IEBLnp6+2jk2M3pNJAOHWdDAbTh/vdXmxR2adufR93DaffIf32krBcIJcuIWFPrppwI4pdw2vk/J
q3noQkf/MQsjxWzWeshSC99uuKRcwaeMaKpn4w2PsC8PqzYvmNC2KnDywwC/kJeRUA45OMUdA8TF
FBuwLLmo1jbAIC5oa/77OAILQ3s/9U19uSCxxxQ05cgyFKHfE3Scd6jgkoCjAqr8/b/SYlJVncB4
fOxs563mLZJa0zikWAwmBXeTlNI/98WXl+s80aFJW4+GP0Qyq+CABDnm24Hnx3HNuMCDP+4mNJl2
lfjgdDzyKPQAAKFVBoqPxc8mz/1q8tFY1YryAkkvamKFSBz0AFj0iZVZEwkICwewBKFUW733kgJL
/7VyTLPK2KWb3yXemfGzrGJ3V2+B3f54Duni6T1yhPpqLwxLL4cafLS0RdkEMtmPODmiP4OchvtG
1m64/zSnps+1MQPN/VKEIUPq2ktDn6yQ/jd8U9yrUTyHYqI54F7ObhhDgDqhBu7CXnBS9kbGSSVK
307EtMeiBDvdxrH3ghHLN/3I+zzo4mvmcXf9RM9gYqiAgGVSC1k19QNNDiEx4N/R1J7GxDEFAqoL
QMrlaM5MluCZaJ6Rs1oYbkw5vA8j6Kj9VA/yzHNdrA29WG0A4/sAczTb/ATamL5sJycmXSNPcap9
ZiTvcy6pkVwlmsByuncVLJdqARKbNsuOmO+RCqjsle+/rPk22yrUa1nK73Pso1HWNatfj7d7lm4T
sBeoolTIIlG82zUBdy4nrEnfDpX5e52oP0PE4su1baVUWXXonsOoo6D+DGBSQ1GSzYEzris70CYf
ueGBUKr37QdkZQH4F+Q6lBcUMoE+/oEXRXGsEMjT9Xfip5HkP1efdFH9T6gk4SLJq3SoshSJJoeV
8amWXSzum9JQwx0EBzVZdiJPjilxaTaMnHRThvVSlf7TLVdvSb8FXhTBMsHcQ+xc5wtmBJT+I+wN
BxqlJQ80IJTb8oJ2iEe9S7PoSCqIvTcNFk1pkAogrOWADXjuYKvV86MaYIimP+hDB11akJbENUA2
ifHLgMfe/gZpEJKv/zgZ0HeySdlCVcsY5VbWz6McZu5W/7ZH9xdVS8W63BmEst5IdhyOLsooFFjB
QXYLs0tc7YhS08hFKWg1zrVkr3/Ri6qhxEBrEop0W6tweD4gT1X3Iz3Tkj2q/54X5KBh8B8ARaCF
Nbgt93MRJ+WgYtS6QDkRLgFes3rdUDnXghF6vXm3fdMaOYxYgeLkBdsCfFFC8bbPYuVcTyXpfHQr
8q24Og7gvDSfbTpMCyn2kPYEEfimEUew/W0Ph5OIWLt9INAB+tydnNIsyPruEV9L580A6DH8F7UW
t1b+ZL37ZWkVlzdbv1QfWFJYpwlL//52itABHIwK5xDRwvea6UGYbqY2fsa+fiRcBm6sEfA35pAN
f3j17F8tSAP7Qnr/lhlpypMIt4U+cJkFz/T+ZZ+A+uOEA2Rb4E7o9MlgrHU/ZebHOv4HGMX9mqb8
b1lC0lArTAaFCG80ykCTxVHDKlTg3FfZngKnKyt+bbZPWYOgH8O2ZS/DDw1r9rGhu0t8DiEJYEah
ciOTH9JWAMGBthjSlywlsLV+NzDfBbvO0rlbx06adXXDM4tRsMY1ltWE6XwSqals1sOH9Rof2qBx
9uXsl9Pq0y/KLviDs7pyRZ6+fytSMcu94FjUOVujQ0dwYX9rrMhgljs5ZnnMa7JIeBqA2VJCnhMt
HrMnbQWCOgVJZIVSZjeaGIO2Xry8JQ3QaxQkR4dKF4EnOx6wuYCPG2HUqjmqsuJyKD6I0LemWB1T
vAuUakb1cEBZtcd+siWEyRSEt9wK7pTaitmYcIjYUBnfcP0AbSDHMDpJKYBxMsRBAFYSyWhFYTzu
gDcU98u8fqRuSgIZQIGTluUUi9HyA0apaAcxTvpZxG2w/lMClgWiwqyhHhxbBolrqmvZsQtcuGz3
BhdY7OfRa1pJqo9iBnGyl6192tGWsrhA2ULaqhQaUA3WOk9/yAdeSzRKLxORf4M16k9pWWzD3osY
JNZGdlJ2j1AT6dU/N+wiz7IYjiY2m+T6c8kE8Y6yH5pkQuJboCUjGZ3nejbwnIFiFoHpdroNraYm
ZZoFt3kPJ7MP69QNsR+noSlCwXUoIPd+iRQDoaVcTuhefIbEpB8iaakXOTXawViln72vE67uE0++
dS+bzZImsqp9NtOH86uBBlKfIhGvWIPdBMJNPYU6BKsLG9SRdP2cfQPPm4rdOybPcov6pIafjDCh
Cvz4sSMyWZATEPcRoRP6PDvj0FBnubYlgsHczTSnVDMPJ98RrdjOsGGNtCI/6eRdCn8f2xVGrWQb
Z7EzwWXtU0M0riGLBwZx/hs4VUcOLshW3oKnE6crKHTQ/TNr8mLClvleG7O3p+7ghoyRfGTFTHh5
8/6nJ7WzU3SE7OHU7o/Lwal5szUrMfYuiw+MQaUpAeF7P3JSh0Gb7QF1xqQTpxfIuNcwRn2hGDuT
UlamDMvShuOu8DhPkzFZj+c+C/FjFeLgZ3a0KFB1fWJF54zM/E1jMRAwx4kt2PEk269MP14c7Vvx
HHAKDHIVJ71bpxtmSwxiMz9tAosf81NHTlVahes3lW+gTuFEfEOmY/kIkzDKkP8ypqPflT7Dt7aI
dEbEYZEjeQqSIYh/vXWZSvibR8RKrVQWodv5IoViYPr4vGeDuEOox0WMJR0AWIsi/LwP69ysiVnb
PGpmyz9bqePRnPyjKTU00/iDUQRZiTBlTIvi0vTrBum+3x6SclOXVf0gjWyz+Lx0pmbDEzNrrQ7O
mQutgUPnDYcabf3Xcx/mVpu/mCU1EKSF2cFMJxWDkjaqP86oOZJk0jUpQRd0Xx3SVoDyJ4CEz3Ks
KG6qvAZjk9gI74Xr1K2KDju3iDVPSyLj3TojNGnxiEkyK6J6w3tco6WoUCNavkjbR37BNJAnqrZ9
moA/F3sDUO38Zk7B2BPWoN3kBo4plI8eIXVhg3XQqlfHK9kJekVPKM00YQCq/O2pFWcyOwgDlb1b
M9EZAou9eVzhdxUaGiSbkCNFXt7xXAPGcJkVEbgGf4ciECmbbYWxNCIGqBn9HlqerB46icL224wq
SIBwRwIaxYgzhTWthOPCiSgj2GglSr1zZ3FpczU7MoIVV0V+ktvfWj5hMJp98yJi1aB3IzeUUOKA
qY1z/qYk0hRAT7a9+by64QzxM9niQJY4Dx4sKrKlV91aXJoSzLw8vSXje8tDF1PqxkAFWr3HYAFr
po8s0wnKbBYbHvwAPJPcV5mxN33EI5wuVh+Qnq/mvYLEja3wi27GDbCO9g6ZK3i7w8TivcnBclpv
VDBheW9RAFk8lNDR6EaVahC9pU4lc2v+CWA/IuBmrIeUJMA/nUKn3kKvjcNpmAZQpUWlq3YPh8B1
JWDUx4QtH7YsubKInbOtmkLhgwzuqcUu7sv0gflna9E8CrrRs7O1BOb0WbIK6V0UzxWaqnUuZpYw
RuVSES21gCLcndVGxghk15O6byWvsPJ6xusmoERemf9pUp1DSjwHwBLEgHgOKK5RABfyjlwY7yo+
+xpa+8aYcTCkzX7EN/y/3wZOHsqCPWtVEPtL/y4+nQwEfhkXebUBB3kXDHB+UehINW1K6obZUtG+
V3/ylD+AUy1FPFEEmAj1yniQazYvl1lJWjEbEwAECtcEjkkyZ3XyjPbllYaR4t1oy5FWToRgosTT
S59h4Mun7DKzTKKz1KAXyoP+/jAGjFvITi4t6CPVcmitw174f8xkF7TL7fgGMZw6SXo+Mzv3B/0p
+tXl2VrT5KByoKLz50GEBVrIpAoKUe0voLULYajgpGvcJfGfUXQ6h3Wx4UeB3pIi3tALrWODBzPb
51lL2DYmd1V4cNxFBpXSQU3AymZ/p5clDNUENDnGv2QexK1I2kIjFg1ue4uD4PdLYJ7yWerdM24p
t3qd3DW3zidF7Bzs+UBuO95nVu2qlKM7djpg8DV6m+cI1OBMBOsz4XkyICvtnNyUjd2DSqoiSnV9
K196sUur7CVY1rF5pLsHQCQU47v48rn9ayRq9BDKVjUozxr8PHAAn+3WSazYlt66HaX+kmzPfh7l
iL/4VVu3u6MlUj1S027YfoeRFr0kOVk3UkKIO+s5G/hp/loCO+3qBTHoYnK2Ui5nc4L+QHurSFIj
i4m9OoAw/Yhsf8j3ZlVSwJqySWZZdKNqfddXAYQdenbOC6qIQ0PErIIOT9ZFfbsAA8MIOFq+Wri7
5mxcaHPN6YVWTY85nLrwVzI1vCn4ucupAVHajp0TDymfUeIIyyNckUq0rlbULsx8uHlQNp7On2vK
gq/ECBzL1QCoC6PoNH1AscedXiq8X3qa8JHGK/oXxPyghpkDv+jh0snSRrz/gG5dFcFxReniofUN
tOVQ5+0XtYo25SbT1Gf3KkiKqtFoaUyOCLiks0SBet4qAOgiFs/exUWp8Vl+ECkJ76ROPAkeeroV
hYuXqE45Anf5mC20rYHHipYPP4MBfXaVPT1BW/pBa63VxdbzBthLw+biIl8K7ehbm99u15cNEKbR
iGUgF0rDHP+SJv+gThr6AN1/amL0vckFPykqeApyRztx0wnwcmziBYEp2D3euICO6FmQwPDFgGip
qXgsbtL9bVJ79kDPAXkavbPKc0o16k1ql2lznN6b2Uy9p2pfuNIPtUBU9FePm7700JwxJdnQY6yj
gdpVF3X2AFfoKG2ZP2TTuCcM/mqqQSWWSgNIadzYKcR+34P+tUJNaG6QJEQbIW40ZL/aRevJ6jbI
++xpO35e3ohgtZ6KwZ49p2+RY/eXy5TkW3M+00A/nni9cN4sOdaX2L71dcPSnHrk0Yhs7RXtcrtw
hOrJucYTBjtAJmnianoDjuiYcaeHt5Rv55kd5wi0HvdFPrBleQJpCAThDWciHp8/dsv8kBCFujf0
twKGVhxvVATHDgejgNEawNLPsWgglu9ph+35i3Ed0RYfwwZMYMJ0PqF0KdBxFZQlJOOumFNk7fzj
6RydmiofNNnEoVN9yirllS5vHdemcPjKh7wmvmHreB5iQgyfS3j3qRdOo90rqV+yN22i9e5inI/k
PfxZzWn9iFp8MbhsoBrVRJsX62PGZRs3jPOXBgAiPmbym9jUctyc0TK7WtdjMF6H/AzXjQM+FjsK
Xn2ru8FoC5x5xhZarDwGTa3BFMAeriWEirZ1hCQ2CqMRnBAySVzPKHW78soQfxM7V+BBivGhv/rL
MDag0kqrllKHKbkpgYae7YuxB5LQT/uTKBtYseXOM3j9JAoTHtcWSM0+BLwQa65pWrVYtpJHIOU6
ocVzAQHJwE4l4pDrNIbs1sDNKTuf3Pyf9nHNLG28KNdRAwgVm/X/04VyoFOhPH131V8xQxAypQxJ
FQQtWLyJo7lOq1lAiILddGy/UbT4aDdnjC0nM/Hs/0+GSjdI2B00hFpqS3bFik9kikfL81Mkij8W
iAjcQSwVeYAPkFkgA25a9Kv+wcxnqpLfUfp0vH48HCWf4OcvWXg5zViPEY1Pzn7Z0aTlfZ+2upL/
1dkoeISvFOdZ0RUiY2V1H0XCdDo7IP3QuE1MI2OnmjZZWYpOk0KHhuuXMzg0bvu6Ay7MaegF18YN
HbRb3MnzfgSuZZYOuDPsylFsKyzsalRNLZVLDkJjZpusGpT7TmqVYXmvs4TbMImG6Ubggey0VwHK
3nVF4LPe8CjfTXD36QZM+2mw+yPor/aD5Q6UzUVVjzjtOVZ4hwnw2xLNuzL//XoQawfFFH8Bl4tk
StMTpdC0UsrwYqpspoK3tByT042ZeFaudZwsrHJo+a8aIi/UZl4xEwthkDwrBtYsBVqleiiJvC0j
2xipl8i5ejubW39pQBaoRfPeDiF9qK8lp4d34USol4ynmJ+XV+s3SF9DV919bV442X+RPHf9Z/Vm
5JKSvBszKewGpEdKHUnmD0BU8Sv8Ra/DAmJO8wt99Bce6vuSLf87eXRJyr6Aer5bS/QlLIztQ64R
Q+mNaha7i8X5MXrQ2FpJ2pIBmQvc0jAzkcDRFKV1ut2hM4cC08fWWku8ThTuLXAacrG7RpfxErYN
cLM+YYPgQIycS4K1H83UY0ISlYFZ/ovhokJpSFRhdCpOSGj8AaYzh3AA6AoO6FIcXiuTQrSnizZM
3vEFLFfbATG1oy2qyi+E4DhzjSY2/GQTlOhAUSrrqCL3nC4sF7s704AA5veDOUrUebEV6Xsou5jp
+H8zZU78Ps+CgRzbJIb4G3dqctk+J1gqOE+pOOuEmf5Q3umdKszRq9LTvzcFf2n1VAvCOpfv0yG9
1DCcURp4Wk5reedZPq5LgyDgHi/xzsUmJl0itREY96U2Dkfv1AWTN25Ve6LMB2SkDpGrCPH0gfCj
oAjYFiPOWSzPm9Tqr/jlH6kWywYJ+9QWU7oxH6kaR/rH1rsBjwwlvDRirQNgx+gvJDP7PvuUBXr7
ndEpQFY3lPqQ0dRd/bj+qU6d/eqKcwmFYPSX4j3BGefkr+fhvs7R3yDrdIx5EX2I8j0+HZ3gLhQe
ZbrbGlyCRD/3CIZavx39eeeiem+TaxjQPHBPerKCKG3IGO+aMF3nOuxhp9TogyPphdW+NzZL2P9c
HTYmxAKl3bZBVmqqb+rkXP6+LZY8BGh7Dj0zQdmijUpajg6xTyOw877AQeeOFE9kYPa0JTxZRXMq
Mn8rXfkqb+NOfSMzn7zuhCWMiO+afPQVwMp0oqsd0H/QKCK7Ya+ZVCLMa1rpuliMqrUBcmWlV0F+
6SPV3z2n9pADqQuxyVJmbi7DnkJ1OO2p0WQWcjhMIGxwyhCzuEg8xCUdwbwCe+eKl+nZhQlPWTaf
3a3eZcq1g8ofpX9fbci6QutFCV4RF+/fG5KnW98N3+NNlQFwmEZb25o/cieVgcCjOQ9AkIQdt0z5
TFuOeGIhIlkolQ4WiDPOroMhUd/zXU+i9lpf3bQD3iTb8HN/Zd54aIqQ+xtho717N9GFCpr0V9ug
wzHxDNwt5iZwxt/IJ31e0B0TOdscgyNqpvJDmoXnAi014htnSY9KN0QlEt+FXlQBXFNJzVNIA3+s
GUbpSRqQm06GgHAyhXCOAzoqsXHSIu9Vb5hJLmsmAi7B6azjSX2bQVSaVYpJ/8rut3uBqMbR6Sd6
UQZdAglnQn6nf+aOPrfkiXN4xCmdTHS+hBzqf+RqDCK+Qgdg3DCjErBdASvTwQ5nJ9YSelK9hg7X
2WoP9j+HVjUhTs6pwOyDCctPavhq+0Brb6EHDLJo/1BxdK6O+4uwe9GOQzEN3hqjRbZoprXjRUmI
3Hj0dec0y5Hf9iC5UnwPUeHDp9zOZsfC+RBnpPTHW1iMpdXqzfB3WKH2Pt2U/RhI2AkMkaJlzxVa
H1VCe1iTG1dF8Up+ZwuiRbV6gzytEiRA2L5IwMACny6x+lrQ4bp76H5CHEBaBZkHrWrr21/hLe5t
eMI0hroG3X5kVIen2/GgWWxVTsTDfGGdPfMypxZ/c6MyfAxJdVmCidSBMi7403mr7LGl04ISj1iK
K5LyRntdfKGK33m+1yln5Y4RYdwhwVShunkW4w/jDu037x+ID2TPO1IbEMPAdP6QCPLCvSgUSXLm
8OBSXDJkDy1t9rBn2Bzem/6JiLlD38k+nhtMP3jCxsr+USkxAB2ux62BqrUZkejfJqD9kvxXJYHU
vKuYpRRZSyFYLaa4wLvzJ0Ge7A0Y2PGFZ9twebRbUup2+RtdBGSuwU8Nvr7+eCqqTEJQw7hzMiJC
DpfjXl+35ZOny3ot4kvu/klG8xbXmqap03f93JCPU9OFulGK1ExErjXbI9iAIKkt9/uzhaZhvjDP
LGfwmc9CvL2LMVMP1Q4ycwVS045ZTZx1OVKLJk1IN7EEtmftaGLvPe68vbGVOVKgU7Ai3LbpxSY5
9I4FEqh7ckeHWyJbZ+UoD5r3ZNFDBPJs/+BOLVKvyEDi6vohyJjqk9aQH3che0hFu52s7xMbzXwM
2biuivGYHOYeUnAQxvNHisbw4jfJ6XtOL1UJjvBJO0xuyc/iF2BqaHM1yB1c6ZGOnWQn7DWhapIY
7+CpCtiFtk2tpCUt00CrIMD7v4Jg7YLNLs6aVhJsaz4Ry2F9oLBiTKyG3xGI7XHJwtm6qUW3vuPV
8fjJCxokL23SB4ErQ4a1fa8MCSK4exl4YA849WpwOykGYr6F6VQYT7UMvlBfJnM3VcNm6DcnHnpJ
+TP+ybt9FS1ObgWf91bB7v6nTPEw9qdJSa5BLu8wxvKpT29yt+bM1fjjnAH2zDrS8UTztJxlBWJR
tM1y25onxysH4ADiTcMN3CwDP6/v43yzp3umEPkw+z82I+PnvgTRiWiPJAJ3ijYcliSmh6av3HZt
/fClB4xYzPDYhnvTnyjCfRUz56UYjsOfFEr6ER40Z313klCfAu1UNYmXT+F/CzBdbA5Bd6RTsCZ9
swCmrvBgYERMxFmKM4kTlLpewVQ4WiGgqmgAjdnUChF+c/GuMtQmYqAt71EDybevHj7seNAtTZzM
txamuyU+BCT/kKYbtuN4/ZRaC7IBLJqOL4xtLzBhpe2i9qY0ulg5p5MfPlNnUzpHf1MFADBdL31j
yys2S9Az7K17Css93sxNk0qcsnnseu9Q/tG2h5W1kj0JRcrSu1mjpwjb5KCxvtmoowZc9MxSPQTY
wLA44f0AHzCPdt7s2+egDhHF8MVH0qXij8R0MvB7K4brJPzJTypk4VZAchTqCkuMNf5Z3+bp7GkZ
tjahUPVdrL2yxaX/k91Ru+6+lB5vtJRQk/ngSzQJxQdjuvt5ztEpTV5hNbyjIGsrTDrjmvxqm2Zr
KsIZgd77vztTjpsNm0VFZh5sXcG+jxwDYtSbYZ3uWLfLD655NzR77FTNKtJn7UCp2AssNfJIaBSb
MpUZhdRYqdaE5EJALcAU4jKaZsACzWntIgk20QzpR0/fsBoSvDzHx0cfzvOCO/iCAcxxanN3Etj7
UMi4j+cLT8ERccrpOzeJe9pLNdJI4+RbLdnzDoKToF0In8gPUXJB/QJGh0MG3RzQdULuXUWToKMy
c08wCv74bBLkvbouCFz/6qEobk9/ZOj4G7IkAgETXVqPVFuywLqTug7115Be5Wh8PYqm3loIq3rm
0Xz5svHpVMpAuv3cpOD1gQlZ4Y7rDU9qDSU178HiWfTX9lSP9yPyEPmxG3U6aeoA4EpSuwy9F4eP
LDl1CFps19a9WW/P6hd6N6HcV4OinyBtr8dl2qCVMyayydG2kBmjYacIuiPCCUWemj1Q4pfacX7W
NgmulOFFVpsrlXup5a7mfRKq0F4Rl19t5t3iJCTfQCbUJL6tZaXt3jhL4wPt2Maf1XsvN4B4euop
eltSSVZjNFvyu6vSrtMvFBY3pUAQDDJxK6O20mrWk8M9LHyFIpLOzasnaT+PVguXpFWQEmufVC9Q
Z5DPw9B9TO/fe8O6AMFV2vMVKYsoIhKBJgUp7zX0oj/tegtAcheqvX9JdtmJXu3Olew3piZL08ea
sGnoQhlDfDg/lMDtw5L5yc2Eb3CqsXYsyKvB4Q2CuodNrVY+8nIrgVZsti00aSGcomu4I4hEbp7z
RdHG41QnfhOhgbsYe6iGl0Yd9tqKpMrGLwDaV8425uQ2PTKlLLanKovn9Ncw4SOTh3vnN0syuMr1
WiEeficrl+/HWqaSMQ4pWlOhnOBMpj6hRzPML6U7xxWejsrdL0ey0XF0W7MWlzAu1laU/6ROJgPm
gVs4CvQI8Na0johS193KuAJzpSNRqBiiGPtsQntBjkmgYq1kI3SiB5hk7mfMt2rQG9hL0/kOprt6
lCLQWkagm4mdqNkSiE2iJiZVqScacj3emR6nq1Gzn3OQIE8eKyAgtZQ1NUBKIEtXVtNwfXU1JhCN
xtnbBDLidbyWgDQm8FAL/Evk4rE2QskxVZmOkz5aG3sD2mOPBy5Zu+JKisSE6pxnAHtKDAEQLKbV
cDdm6Arr5QvlZUCppJ5bs5vteCZ3dKFnzYnHiInQYRhMHJpWe6cYp5gIRjJ1uOO80rK2tT8/Ahjf
l3141Ixr7DV+V96nJzmn1a8ZSX1XbKyKxZRU8JSbG1MvTmxojxmuYKgjmtuS9TcdDyZxSC5dglxz
jgEdv7qrY65R/2JsJI31xc9RMSarboaVg8LZt8hrYxYKKe140AZyN0DQ7FsGxkK/4ySB2v6lDaVk
EvBDU8YyvP7WlDA17m9XNc4SWdrCz7vg9IYOkDE/ASFbBltbIOe67NufzsN4opeb4/mS20Ui27fU
McvZQuzrXQznyMyEafSlNLtEBUMFfeY1iqjxBaBSvFCTwjj2zASJuaNX0psw3FKN/astjIbBg6bA
XbwQLbwE5dAphHU+W9J/hnWcv9bYov6jrmYOZZUSBgT31QQTjoL9ys6spIbvsiNnBKBc798w1aoP
hx7VqRe2pKrbBC9gfJKwy1KQ76CSzhjYsb2wNTRzLK7+yE9h4U6Mz/iSGVehnuXthEXZReoD6SDp
usF95wexBStcDUANrodPWYY1cjHB6+qb/koVjWL12p/MZ7V1/Azy/Ho8AuafMreOyzS0n056Y6b4
eXP/S/vgINYolkAPE2GRv9XLeFnlCZ3WBD1JSQzUKb2SXrSkbFfv7Ritp59Unwc9TECgeLJG4+/x
ETcvW2EeRC3zuqtBgZcPutMCCvMptnIG/K2w1arMcyDAjdzSkYO8ElFEMEkdz7n2nK3fcLo0s/Ol
sn7V4mQElJs4HvY208i6mVwbAueCpfJXYBwd4P+aTo+SKZTbWauOsif5e0r1jNKypk5JZv87Og08
YPIqP8hz8TW5dbzia7qDSJjnShXyaZGid5Roiehc3pD4ibzBb2fqYfbjr07tBhxvOh0ClvEOvtY6
el7YWXqaBI5hvMOjAHsN4ntehz6Lw9mAqsDRqDNBy4weszxZXi+dshYEr2lvNq3xsIuGIow9zBOq
tYo1GnAetlQVKE+unT8Obse8q9Y+j17rqLMFPkYbXF3eSw6/Un2+5hCVsvVryS/CL25LWuQsh6Zz
GKlSbDj+YkFEOpkm9i+gM6BRCdSMKxp2dQ+lLqc7/1BdPQpqkTrR1KaWybSVDBpWlZPXz/JmeVC1
4vx57Y0rynt8k02dr9AjFLBfxgFFp1RFnaa/wWOmcoS+8RxSakt7mW0EcZp3XboIhDrbZrJvASm6
l4pfba1e14oCJuPGyEnqGLP0dGlS3fxDvw1aE9UbUFkEDL+9g9JWqWFbQeL3g0FPFQswsRCK2wIa
VU5gMjn5PlXAAW3bkKIEBbrjpX/c1Qn19CkcSq74mwu822Drjc251HfE3hY+epF+w1BvKRBC/Gqm
28oKwunGizzSTqqSabn6SN1kUNe7QTKq3g7kE+r7G+1oRfDCOiXqAIuoozUtu/kU0vWa0jn5duT2
0A7AGUPWRqooWiQXnKKXXwJ3KEPyWWQe5f/gGNZ8RQld7gkEeIUaX/b7+38d05XB8s2L5373Hw58
ZdwgNRSUb28tL5ASbCYk73v7jY4uoaRGX3NELsezE/XRH7c+/q3BcnaLr+3mD7yOCO/dlDMF9P2m
cBBvVjm5UnNR/E698xMx+auWJ1eo+lvLoEC6vpSvpWffguxBELR3vlxQs8k8j4yy2oNSHDrnR/xy
g8zMO5BgtL6UxagaawMXcxDhEXUOBjaq8RIXu68wiJrHu98ZYV6A/jYYLCqUToG5CiJzYUKXAiVw
ZsOHV2ph8bPuStQ9MuIxzP0H30Zub0N/A+aJN3p80+JkuQf5sq0wiKe9W8RBtjZqrs6hrRvhLqbI
dOucH+jNllbM9JyDOS0INUqWtftAEkeNCHy6ykpJs67j4bC//9tjEThWPB/S3OAGRn2L85FMeiMn
3Ujd6Fu3kpjy9wTvqvU9XIm3Rqu7xiwr5LkaF1SEJwIVPCMx0aNE3ULLbTqwsG8CitXf+8QjO0U+
y61Yw0L7/avu0r5SJZCHAcnx+19m31/zW1FrxwjNp+UW5EbqUr39p+sHF71aZQU4LasfVSjYRUBR
OOg1rKURWzlmbCX3RtA2ieRiU2XzIJAmOAf6hTxl91J6fN9uWXjYfawiX9NmYufxZSMuBK2gKt6d
zineB43oykKMHDobTFjo/elUJKLxDEskTgJIYtNpnXpacYJrTYZdktbV3rcdisIgyiePJT71ZxJ/
q4ov0o05qTSJTCB+BkIld/VD1u2LVnXZMe6pJJJqqKSsPPwxqBFKvlII7RXKqlE4/5rZ3uW9jPdK
Mbbf2ArXrtBjhTTI6Pbc8oNwkKAAWvvljFr6PX+sUv/mxCXnd9RNI8TK53IdOF1LlGz1/4CCIlkF
pcjJ+K3Jy+sbUcxiwyQAQ0Iga9PdaoKrXosCuuscHEstOa3adPSlX6wtDqcqjlGjmApeqOdzYT7d
itQYZmkzO7MouX9VXd6UR9yzERtGphjMyl2RqzhYJ8S+W0I8qKPqvU5SgKfgf+kYcKywKpvf1l78
xJhlC0HcryfaHuGJqVKOKA5jv8FZEmA0blYg1R+rWFdN6/8sgdKKI4tfbDQ+mELt9MWvZSuVpcHI
ElzicUuHlfMipfnhdrTWHgh4bnO3una/YwM4+m6eSkX/T3e2t/JSLvk1n5s2ppvIsrCXIf9mrwdI
179y/vBnkmFU0buJaTYPqCbo0QL62TwlukZSlXCN9jR73KRvslwg308ZhKagIO9hSDwnAhejVNKH
o4Bp8idD32YCe/xJdAZU6IwSfBeAO4vMn7kZIfjK58ZooTA40Wvpk4Ouk4Pw7CXiiem/UWecMnCY
yiep2Tdi5VjVsmQd0vxLA9zrk6V5sGxgoUQowCegsX0whryHjbqQ2Scj+ZuGsJjANLbXTLMMiofK
5ZryS+HPIRbmx1/rOzzDpTS5D6QkbabS3X/xhKegAmlrnce+WqL2WdYqgKdmVFcIWwYRUdus+1d7
st5I0NTY7wmMENZoL2KvhkdFaIEYtE6FVt1rf5bYMDh/qqaxRXQzCRkYXjaeweHhhIeigyMclwb8
WfrVOSktEB3caQt6cFQJQ6/b+CSBB5yg46sHevXh6Wb68gWN0jOxD2Ums39JugiK0yL7qEsIwsAT
heuRJGtCaej9jOrAp7+jTubsQIa3m6wvE3ayiUFgC2hghnERVn9Uwcylj6MOkVt1h14jz7OE+jiy
cTK8x+87Sq074m8/zH2N70/HqbzwZ557VrD0pACH15HmSN5LbAASs5y+JqugJlSGcCeSeKZ/MQ1t
0q0SfUUVvZzREqtExu68smYCG1mtCAr2uiyLTIlnw+C3RedV5bRT5w/mUcShf30U4p0dkVBl3+dC
limW0nSxR/bzd79DUQwWfHQGgaBlqsG/SK2aaIZoVC3Ve1MV864r7XAa/IVngZMlmJnldm9Lrmhu
kDwGoTOLG8b+7LoA8f4LKHMAtjrvAuMUULPfOdXYb2FITkZZ2/LzEl6Mt46cBaCXJF3nt4MqhZVQ
nIqiqEz7EDRy4njUkaexNDf6z3hlmeUgl1Kak3p6MPhWaY9d+R72EG9qC8/poRmAvH1L0GIovU0d
BIKo5aU6GgeLBgBL/AyUXiWXW+GmQGVd3SZC+lG7Rm5LoVsb2woguoYZ1izqGL9P8TvI1Jt8kPrP
IjB8JrMnJz9dl8xfg3KppQYgbtLG9r0pMl1Zi5UaKz2Zd4gNIouY43mC38ECL7IBokUvUG08/iTC
oevATP6vsTc/biMV7Zkog4C2RppnyWeX/Rk+/z0aLbeGdL5GyoeNzcNwW1Pdvmu0cGhbjb36qb+w
2pz1eDqslRZwSxhCr+krruXVDQIyT68lyaJiXOJNz5mNwB1RJXERFMsGrVWtpf3P5Sprm+u7NKZs
E9x9VvpuuqWoZfIp1E0lNRe060jFKxnShXeK2hI69zrpI28yTMeh7MUVbmQOE5xhGqD14vNP5bY/
ZqCgbiASx8LKLPlsZZE1yCpJCJDYTVK7AGu/xURN1ApeZkQ4TP+H4oRTWll2lu6LK6Ws0kGuDt/k
7qgFNy0S/I8SHFyDdHZ3pJ+0nI3j7eRm86K+G6Fw8MLU8Ay2c4WoLHsegp6126MMow4AoQAkWdSg
eqvlRBxfsjB86zT31/vp359ll0vhxtoyTVRHEuDAlYgfDKTu6zN0dAq7P8rZFRi67hYDE6+NohA1
mFkEDFwLT1zm7VZ1Cs4kkcVr+Zm/Bab4+vb/H/VpefG5bQiiX4mVmFrK+U8aspFxt0KTu5h5saeO
D6a6qYMvKmEaD+PdOemEOC30gfxkYY2nmmeqVTmJ68AuYHItdpW+wjd/Q5GgqAlOh2vvqtp6r99H
8363kBKah+8hcG4FC60PFC0xd4jNNsjGz0G76Ql6/Bj9IPdIAhGK5LEMXGrW0oWBV4928BiFRVLZ
G8rqlKsvbbSC9nVRiEPPwPczGlUV3RItBcXOebMIB1ZWkOOVFGc4t2tHCVqYgPmOGW3MKVGI446j
VGppBrLwtYO2rcWAZFpIeQ+MuSjkfcY3E6btCrXOmAxEiEXXkUdqqcsdcbxkEDgrRN/KC/+P7EHO
PwqOAXRVdV1UBvyWt0GWyroRhm8BF7xc5qBFSqo+QXhfLaYFbHznTYooSB9sT9cp5ti3L1nmJco7
mkDAfcpROalqCFffMAo0q6nHxHPN+JCmnzuWbJZwbT5as06FZSYz4W+IkJCoAYLa5uOIeWTEYvbo
daM1qO+yj9pNGVAp9/yD6xSyXPfPN4m/G3uztn1y4GHsvmzYYh0JqetQxKWo/56OglrZOZ78QIJN
rSw84abMuUAOnl/c8vc4kaA35XtVOkS6AwPjucgcqtWXMwRKokOwj3TpZOQznok5E9Fvb+E6Mi2z
Y6TskU/GLp/kX/sPm/30f8MnufxG+8Xcw+U0hSSovTlySt6A2g8dsvoGkLUpdgZY/yWurodEURMD
Lii6Uw28hJNduxCNjVWo5m50rzB6quroMwjwIP3qwXWCdbZUZOKFlF6sCXUY/gAUjb6xY3JitlqN
7vKFC7XMTg7r7kzji4xtDZPyQhM9cnOnjzAMhO8beypDNQNUFTEDr6P9EKRtA3+jLSRnOvGo3rlf
JI6okHuvi5rtN1qvyxEJPMppDyck6LLHs+GtBAfru0FfsIqYhnPNJwxX6OA4ddnDlyu0COSuBpSt
h0s4iC9l/+473G4dAqw1550LQiKGBn95fYBFRCAyFPSj1TlreivcICX5ClagF7Xy9DGaulN7iv7q
IYV7YVphU27Fe76dBw0eOFr7s4jxWPh/ri37fJIeEisNlazneG29HpSOD9+tSUUg4om7+GDSuiam
g+GdTBw7n8WAlFcM/21VYrZaHptm3LNXoEjXAwv/0nZ333iyg+m3vmrxbQR6wa9JeSPwCYfsDBDs
9p/8IAIul0Perr7x0926+NxVGoftjV4AOjQ/dKWmL35ksKzwAihgrdxe+HqnB2d6PYcgaFWEC4Js
Jd+0I6XAIOkG+7EFhJKdxC8fgpsmY4EqD0mpvWEv54l+IiVi4Ur2I+HMoS5gcTjSSEY0tBrgmhqL
BCzr4xPdKVF1PAIrCCg+lPb89BGMid6DH7+4/quUuJDbjndZ2RIGKL4fhuhs6IqNLgnQfBcvK4dI
9sqUNdBzgEfC3s7rVfojKKSZ6kX9QMqUlomGPeoWiyoRIRy1+MpzSliAHSI9DGnrj41sle3IGds7
EndsFehYSnAdxGRAP5NQJgXGzmNdQ3QV0q3my2WS8EtWKfuAYax8YLtImTu+qvVQPX3mPCzGJlhF
sGCfOeRlqKwG83dRVi2pnTrvMmj2UveU7GXfqPT0IHEWDfes7P90c3NmuIERXcXMPwJg+x5jcImO
lXjzoFJpHbvlKoLMQxAOQZXMqtgmYAQEmUUyHJdL9vBB5UJ2XSUtb23md9Zmx2pkpuUOly6f5m0U
a0fLddDURTCGDFWN7ewy3LQGreRE6nmvzvsyKiROkvCKSAg7IiuKjdAmd9GWrGHFyaAuI7jUFyU4
Tl0LEzmeBXgdkVJ+RuN+rV+7yHnBZKrj6NXe5DXVHT3yOSbKdrkkdNUR89WdxxsAxSQ6SbMiKt5B
g/p3KDdRUw0Zg+yfM+xJ/XBFFsIvl/yYJz66S0sckB9tbP6d0yiQbF+YRsPRrHzkNR8Qy/oPDFy/
pMm1NeyYbTtMtCOvZU4JG6iCoVPhThBGy0a5buoQh2Rv+T8jebG26uTriCm/MopakA91ArPSVPow
m75oRuI2iCyxcFMFHnrbdL5GXglFI9wvLR8EFV7QbsbLsfJby6SeEyk9iFnt3pRSWT/JUUTsz2v+
qA+ORjkrdcb9vwW1wowXW8qQgX7UIRcEwmxytWN3gz6Gb8usVviNOpMPwvntDV5Zwbx8ST0HBMFE
nBQo0GX1Uh+ey64oURHldCXOVqI5vQhKURaYb6cKAayk5pVJ5Niyb4Drjz2gPdy4Iy46A4MZkXZY
Xb/qHrVT7syxauyv36rZpiqcUx3opjWrS6/d7UWE3o6Tp9zPP6i0CQUQLGvmoSt70kN1PEvHzokc
kGz8440vdKTxvkRX1ItkR9ZfzAga9m2OsVbl5JgonsdcbD/6Tzu1QDKFqgTI7WgxEX9H3a78wti4
or89VmCg5wWGH2lWYWbVIXayRfsFEClXph2JSoUAWbpkr1sX4RK2TmFz2m6wvcmGNZ7gNmEAm77T
PVhaC6P2FEntVTxH/Sm3ss7zz5FM0jr3uB1tBUgMBNNV7vwWhU6r3ynxIa6NQzj3tAtHpcz/sfk4
0abIMoU0Nbf3hHWOwmKBR0POd4S4y0UeJBnV0Fe4980LiWqrPeqjH7P8Cq+tjSuqgxHmsPauz2ed
fEWn5Bwm4h9O3ZI8ItchnBVecIhkY9xNyksZKjezcL5v8WPFT8/ZrSuVagQ4+n7/BYD/TZuyMjnU
zBG2xw+cw/3kBa0unFQ/WaOvAYEYx0luiUDm3jAgmMxWmzw7vgK0+dOPlxwv+BB+jAwEb+iuMrlf
qKs7ASH89KAmHvoptOyM0LTshwmjKcm5Xf0VDGsZ1/+1j+HJgJaqZQPKlU1IavZaj5nc0N53qxbF
SWM82UfnQuaPXyQxoOa4iqtOlGR/kkRxcqmmcrbUZDBw0UF8IhfrXR1dR6lObhXXEFdSobOzQj0i
IHFnr/kEjoESoZ1Jt5MySsjGRvOxuYWaRG4HD708p80doxaYseRQnYk7+7uT2KNsOl5lQhC7ObDE
CZoupUg4/KYJCY1J2au6jOjwYsuOJLfo7ahS0YzMArtwH31IDp71UZwtg7Ut+bQerrNbfgNVjuIu
h+II5MpVFOb6vzw6eS6tuO1kZ1KPP6jBuSpabhByrP9zhXvueWg+GX/IomSO0mSLBdP685xVpU8H
eIy8wXS8S2rDjOJOTBM1smW9KDh5G1Lst5Gi9c/W6Bi5zpsRFDeDtWg1oYtML8yA0lT/1mGkJUIM
hSsNaVjxk0RXrsdV8eQd9Np94OumFZqyg5MRWD6wfFUu+EV4Ty4MAE39VPNc38FbmwlXIgWn9qu4
xBUVoW90V0C0I9EHR8BA/5uaQgtqnBt/Ek3PeiruBeKPPuF2Vd8ITAeF2eQ2QIFaC0xXwpH2nmwf
dP9xO0LPbAGSGg1g3rAbcGyapOysCH52Uep9fb0wwsiXVgB/U0CzMMPF8t6LKbnto0eRfNhkYEQy
SFPTR+u5b2yFrJcw0kDM0QkUSxvxlFzxedzyZHKC8WqIV4FtFowu6Ih1YXi5EzACpwuR74uDl8p7
hbl144say6GKaIZBwVgAt6jjpnM2wThaN05dEY99dDCnwMBS5JDWzyXZWjJOedNALkSi4GLCyBpm
iaDNmLl/CfZ+BKgXEyfpN0U2Obwlre9pauXDcA6vA8zVNHPbxOlqi7KGWWcVBBcHwIKMTtc881Jz
hvb5+qcPVTYZWhM4WNKyuxrggubU9SQajXoWEqYuws4OmZZYNeDtP4UlBTjJ/YYFBTfWgoLfonr8
Mm++ZsyfVLKpYm/YYD6dWwIkY2uTYnhSDwHs4BgywTICza/P0abxVAu5tqVK3ngPyK862qEzakuF
3zaSooImYfLUIYwNUYUEoYfKmXgrWZN1UeNN8fRYZNlX5OhltvDyGt5mTYwkzGiq2D3WXfRLFFlh
ZKH0PIECyczDaKBkvPWYod2T3fl7cYls+IpPtqIADUIcBMswmbgTqLCyL1/BvdZo7pf+/2qC1Qge
B5unhKh5HX4pFyMz+fCIteCvdouWnCXrANunQ50dcsh8UsM4WgKuymI3swKOM9UsTVYNbbFTzCqW
xC+Z7I1jcVK5Dh+IxXcXjMb+lj7eTYyMZhxePsebXQ+VD4Q1/uI6VQSO634XIIq1X2FMYPhNICq+
cuPj2Q6ibanjpWpWR42oS1OAYaBHJF9B++ncnc2Mq2ryNWMM/4aiuF0BEnKqtpl01QPnqz4ju1HQ
eBuDaUUVzVN7ScWjwOAm3UjrYk5MWGvLEhxZTwPVHOdIcQ8n4yGtmkWoWqUKferfAG6tzN5oXlb5
qIN94YNlXrZbK1AOLl0xtDphJRMZHPGHgqDqrs831MXEupWHs/nudtKvJK3+oT6Y1UGiuodmQa7t
DgoJgJUPgMFMuNahNLiqBM4mKd3dr3UYRzyhRzRM5k/yxvt6bMXf9DDHCd6SUBTinFC8egTzI8+o
K6FPCc7KkZIi/RR6gFU8N4o7hP4yhfOeD7/suzQXcACior+Xp8QjMlR7VtZeVviudrXMKrBHrnQi
E4hV8p7U21C4Tbg0+9mVNxK2bFZj0K3t8XjLpTaMEvktiiRMivlRZ1b3qKTRVoO2uEIYeQqCp2Md
GpodT6e//hZCundmM4WbjblwfDX9G9OqAFrRLDGGFlInjkRQEBxK3uKSFBtfPorxjfW9pDUOsUS/
7aJEo5+Se14PwtHhbUweYUK6mjgM1TvSWBT/MdM+mcQ4PFxXPgV+kOjLOG1IX0+8w06dsxC042zD
Z6TXsIlz/qXLWX42t9vjDZGCZI/NdOgmioJlQQTafcqo7swpGcwWTSeEhppjvUfEhfz7eO+yECnR
CwzrvaQtgN8AO3TOb4ucQfemGveFZ8QzplgvN1SFf2D1RvOvqrhg0ke4l6yyzp5x/9m9XOmYBvfQ
EITEQxTAmwi51g/tdPhty6PCO0ZDR/b838rm7SmlCBxxETcPFVDKVD6S4qMnhGg5YYQv9mnlZkOh
4I1AkTXq9BJx2FZ3Elej1B0JR/LEG0tGXfpZBrBg8aEpubPJnKwYVcmpcJ5Dz586UvhLWFHzJ88y
M4Vcbtv7GV/cIlrvyqhHfyCKN4wrz7In30f/K0yzOhOUeTa/Os7PNKDDIvHCJJiHUo0QvQHS8NaR
13IYVWeExjreM8cuAyB/DRiSnA23UlVLepOpP08npM9N6yarsNdvH7t/ronxsekvbuALHiF6W/Fl
d8R0OGwn9HdKrH8vpaYjlaNK5haLCQGj/LpJnvJYABtqmz14rGbitqrzX2CcGXS08S35mJFbQdOp
M9qA7WnG2J12z/6Gzy9famZY5VFy3QtcN2K2IEmePhp+dyRst7T+tv/ja6/tLgZjVc5sa0kF7/Gj
M+oQrG6mKlHB5LUllaeyp9mZpyxxaiu3PjAugpFUzxUeJgoXr3NTqs5BtP9WrFTmR6R/7eE77H9A
XJitE5z+aeT+9a1xhc9U9oPcNheQkdtmTfX7Dn4A0P1lXEQTiBD67DcwtkoG7eRY60FWILA3zM28
vsKBy7p+zW/zhlxGUHL8CPa4Johnp5ctgkfe9MSfyHc5y0BcQaNIekxXtHFO75e/KFLVxS55U+4X
sq/ZnEahpXbcYHXcqVhZdM2tSGU/oUbx2iLCiXe9EtrJgvwRcBvcM3kkjnjd5qunNsAJp9xk2ypA
d5R37eu0QuIlvBYjPfAha4exwuXgwMCnEthOcyPA5TH9VqDRX/GVJymfaOgqm4HR7CZVemjktzRV
ZVNZ5dDxr7K4T6r4KoklYnRgBmWZuobufLyvmv/QXZYF9rcOI1fpz9/T8kaJ7eUrudy/cWpbCcD5
6ymKm6Om2XYNpmC+J+p+M09HR/ImlDxgeZ4sg4VcAAWS58EOhd3GoMu0dXw26D1uTIqUPygb3RAW
pvrtVWD/rg2NHPmWrfmpkKyqTIaiuIeq7pDjMxlel0+ziEAr4BZSQd0mI3zRB1+lMVY8B3XOOoru
clPM6SdnO9vuzhwrVG+talHo4H3TSHFttZbXA6/0KUNxdXYvrgEOpRlXiWlbLaOhSXuPM7Cf4vg0
9mCW+ZxzaamgllnEz6PEoyOnia7wghuDyn1T9xD+RrPJdxA8GGLo7wGihHTVfKFBuqU2w4DkKIYu
/565zs58xItNTnwc9s8sUx065+sJDmDws46fzz8e8BsjMHyKHXzjT/0mFZ5FkcAGs+3qH0B9kMh1
fvL6yQK1E4dMJhJHkOtDmZiGz3TERFDJjYMuz4pkZTorexgVLggCxg7FUqTnP5+r7UTuv6Pu+sP0
Ryxo2vbjJQWSuzmb5URdfaLFNLPoQJsxMAE2eDh2RvFACpLmCZxLizfZAqmMjBaGxQly0gvafEn2
Yv5tBKjpaOnKYs+WRyl6K2KOgBf6SdKeaLLokOTOaI8Lmotz3mMtD500XCShPiPrbc/cRBpW6guG
oJac7wgYHEmiI3iw6lWYXyWpU+mjd9VH0Hyh31zd9lXq8mwgSIqKndrZnhlA04O8LwmT2MfK7nUF
0agORquXUeht5pdKjHQZ0acg62vxmmVG0CfbCgWWDKkJPDohfUREZl0RE2DMYqB5MXOVsJwGMRHg
EJOhaRRoxUDuZULM9BgE/9A6jD4L0uzR6PL8kJ/IkSutWKImGSZ/tmNclLK26nP1Jfh0Xvfus73j
F3gs/uJTM2qVJlcyBxvy6HWi97AC+14H7cQgroOMqNA7JYKqu7xq6EMbDgNEpwJ7+KhCUuM9WPPi
Lee9z+fZRebdInciL3mrXU0efIkcJIuIHoMqyqodyWvtTpXsunVs4qpnWd3gArMorJGo3ZWRoVgn
5cWh31A/aPflZhRRf/TRPNqFcdsT6gcRrzVfExyK3kU4J/cd2S5kZhRzzkXo6iM1y+Si7gGzklNV
4GwV0Z0HTKLj3nFZtQcHET0UoVFR27fqNn6WrZoVZmnsq3UM7z6DSZt9L/7CybMh+RlvOhHjgS2w
S/RN47cNnpgVFlpV49KG0TeiuOK0rXtumoy05obB1TQDk2pcnJEBqjQyIT6WiuXJw4fI0xNPt1cw
m3AHZeys56ATLe2eFIS5e0RM8zDvgFTW3NGscijMvX7pvbdm989MCmUqxI0Io74oCrFZCrxo4Rpc
yCunBQZosM2uj2wO7CNyg5T10N7DjWip5BoKcgmvqZ4Q/5/UwfqtGAZEDr6T7wa76iO9k6EpGHn7
AjLMuy4Nc5P1BJvCvYuLAxF3pWn37cIEEI+6UMfbLYWRw9tWOVzMoEMQZZx7bx7XCoe67c6bVjbb
8+ympKZy7/gGELp4XfU2pCgBuWSFwcdGCrrVsL38kQyUnCfzkzQyGHzg2KWOWUIhjNy5FBHbdgkA
oI9yKss+XhTZa0Eyqx/K8z3TMnOy5vVIXnD8H2ttd8nPGZ5zOUmGb3VOyLHti3pOiZTg2IWHugys
w/1Yg3PSkcZpl6no5g9xaM0H3gDOxtKAcddIB2acMHbls8CDaXXHS0tvUUmyASZVmE3eVcNscEIB
Z+xnfmmCwMlsmXy8Gkc9wOh7Us90iqYEbLQpsMJCjnAaGnUTZR76eUh/BE0pQugLulmG92GNIT+2
t3jpWXaa1l/07Ov0YClTQO75VRKq6rHQFk3AGrgkHXJsp+CsLJpsjZG9gkXtAmvFE9r3djiNRBRh
Wt3vDwofjDzmtE6xS6yxpMZ6cQ1Pja0Z50jfPiFfrEmuWfb/9MddtEck7T6fdt0Q0UoOPs8M1NhD
bh7otuEfXo8QY6ufkDTwiCL0E3S7WCNBbS2QljvHyQahiY9jk0PAq6EimYqYdRdfJ+XzI+wWT8CP
Lptlppssg3pjm5Oy1EZAdb3N8FFmlHaUnZBnOLckTutf9URkOaoTwXVY7hNzXCH/C/1XZiNt0Bkr
2XONAnZyhXJS9P9PUrHuC652tdbnNQBnAM4JheJ8+4ZSeqvNMmXekYQDq04dE0cg6aOTvl6Ro+G0
6s0LG9lY9oeLq8hZPFLZ9P99oxAvWU4gjJKy7MW2siPZTMgywGUmsxz7Fpac8WQhjKcwzNNTdrKA
ExCgSFL78jEWa1XXRrrse+uv5JNOfc5G+MMJxE4F6aGsSGHoRnZxcqokxw6GwMteDLlKkUQ5czb9
X6zGjins/JvRh112FcHNBC6DT18fUGdwP6/MsvDo744tH0W1fE9r3Bdp4rnd2RKnok5k7undYnZO
bBqw3nTETnuOyGX8zNhWeX15s1QUWs7ZYkBpg4psGJui0efBhJ0ALhAQodAGegFs45oab0YX9ffX
Ee59pgpcbPOoU11KA3VDKcS1SeyR9rbrxowY+74ApXdtWWEBVFLubHKVms3tj4Lt2ZOq8l2sMEgG
dsz6gXNpepo35LqwAZNsZ95KtJt9AeBql0h7MyDN0Tdd2tO5cER2ZBPZTTdBMPiKZ+ex0ph42vmZ
0sxgnQXYhFnwGlizKoF+lvgKxnTWkziGeTiLlF07CAxj+CLg++4089B0YCSHDLKJvOgmH5c8ZQnm
b7Z/VHVH9tU5ptLl/lw5iTEH8R9FTw89Ol6JCeiuDxfc1H1P+W1XPh1TEIaQjOhziQbbX4VxwFwe
FR2N42KFmr7Noa2YJ/aWKYoIf2xkvpC/Kcd/id/keelbKJTmd9g8VF8BMNyo7iHjoSp+RTnYDiJ7
XYc5CAUpc5mPUdt6RNpNIFrNz8IBE6eA3uEB+Z+GP8TQT0aUgD0TmhBxf/T9dOwlbNO194Ek848F
YatEnQ6vFTWE/7UwnnV34rdnbNU7Yz1ghqU7ZMUOfcKUAnjaxlw9N77k1pNVqWhuQ9y2yWelh3N0
PAtC8FHlsdlOfy1e1WSQCsZXaQYJmayHrT0gr1snlqbsPTvAd9+FyQ7vJxv82+WfsRj6dRJSSi8B
wFMihuXVzsvnlbXBpYqFe8nUFJ6s6NqqcY8chjiEVWiE+Njpl58I8yN/oXwmg5XzvJvVinfVcwt1
u020deWEKaSHXucwzeQy+tF1Hpx8Y6XVi6SYrsp7fctHbEntgTMmnjbOLPQL7RhyGWv1NvAgWWoA
UKPlcu3yfz59rhlz2PiK8JNMachDBDj8GQ3niiVr4B/yWxmiNVK6tXxi6F33BnSrIXDShlTzrCd3
GX3R2gIPSn8nvY0Yip6f4bXxNqz0ocgiPgFE+SDu6qmpx3BBALbBRsNVRXxt/TwiwZKCFm8mFFEH
TfY+zLq2zOkzH5Oh+tMsorOh7td3Ki4N0SYGSTDG+H38H67wLqqer54UQLrnh9446fCK2/BMEGdK
IHW1o3QyhXWf1jOIbWbdP9i2WQ6ZvdHCExvmy3Bb/wN/Op+CfZ91LkBeYuMTaarJMfeQxxmFje2D
EdkSsmwASLvKDtdNcChKcHgbKjflpYifttY1p33wWRTParB+uOTu56lMAqNkamOmApv0yRPrvouo
7uyXz1c5ZgF+ISyKlLlFD/V8TLJ5UhUeVgxFckkJueU91yhlrH3uQWFeCDhWpBR1AYK78jhh3m9I
Ajm8WTygQFFc2BSKBUvTP/8IxlOCUJdG3oODoCNtBjOjHP5hc8vuXYQR2j26NZJdIl3qdDeGHN+f
6oyS0AqlTj5Ujh5+FhDmeX8gCNufEeYK1w5DbSlF92bXkyKD/wvf3DaSmFT7y1yGwEjNIR8dOopy
51B68z19TGcpRAuwyKekNqWfdr8NNJteWAzWBqr9ApiVsdg5HGqtnRxsbs8Ytvb0QHOGKHPkbPMy
lA3N+pMdf1zuP2J3YiVWPwkwcBMGa5EmTMwLrD60HRf0KyiXLtMHjSSldW0OodoipyXb/w3cksJ+
mhIp0GN32oUYNSmRRqY5/JGY+T5YaRrmfN+eRX2lXMJPzUAaPX8JfYRTGihmpU4dx2COR7VPwNYC
G5JXQZ9+PyA7BwjB2vJOYiXhFFlRPblxrKxfNXPc7t+SL7WnJkEDCo+pcESMe7v8/aEey6y/UdoG
ipe0IaShLA9X5ERt/qlKPCvE7POv7icZhSOZesLF63lCykT2RcZHYYmuYmx3r7G1xH75+FfYTawk
CW/oj4jBE6gWb3lv5PBZAr408/59i5Pm+IyzOJd9i8EduibxGPH6BoOoAZknIitJSV3szErd0aiU
9ys/kiXasTbT9FhOb/6uuh9GBuB8RmpCbPiua8w0jL4I1HSRSciVavqFNxW8YnVq9/Y9bRL2dBor
qCpA+nU6iYqCI2vzxGadYopZNJXxNgtV/Y43L+efpPh7p3jXVVysUEAU1cFCkMa2IAN8xqULG+dz
fZ/1PXgN7P1FzdMw8ys+RaBuUXnaOVmDMoWt3+M33U9F2ksBr+MPIhs1bfysSL+T4/q9hNZyyp89
wFiHz3XCiXku7vw0DpnYdUQAdZx2tekMAH4VomPpvb2rV5fOgDtviNmX5q3NYi3IB4abH3FCiYWI
mXTG52QQ/TiOwUkA9gsnxepXRs5GPeis2jU8q9mzAY9v70oG1+xsUFWrwnHqBNV8W75tcoI0s5HZ
907TO4e0RY/Vrx7v2OZve6daoV0e5/DPerqYV9tiHUl0248UbSJuvgjgltoVSYLy2AKeW2b0YB8M
jrSVzG3eEMhADYW/zTxR5nS0kCyY+0kGBwDy2QM00HokjiuvkwhDExSimHjuvt9miKJ3ZICZxxyB
ziQXq5HRBysYcSunjsEx8TbNu/GnKWj6eFIC4Uia3YS/Z6N9NBPyQv/Bggw7Ps1AMY1dRXFU339K
k9UnhowiTAgGyPvtgTQVjbglodHkTm9dF8YQUUUdmuQAYeERA7puO5zcEDqEz7VlDjezjvZenjd4
w6gjqNUft0KASXxrfaMR30SL5rz4rKIIALZfzDS5+KP4EplwBG76aMr7i2ytxoFEs0S58AvbGD9A
eWgXwsAo3vMAZsQm+HumYtk6TKTYwp9DWQhjHAMFIAEuK2eJ9VKRuRrn7d0wGg80pL7H5WIDCSm7
/+YDYGbpPs4uVbP/5Q+AZ2p4byWQNGotVmDuGneDeRezZA8Lxy4J6kJc7Wq3mISWaJAlKD0G/y87
dy5LMhfz2XDX7CzhoKKO80X6B5S0l5DyJhcmjnocP4MqsQeCqNMQju1EYeLCWtOXGxTRWCBoyCG1
c6q40TA1+NjHQqdG+kBripdXqNx28ixhj10fnwq3O6Nb5Ao01oMCPHHwtZhPRqqjUSyDfcm498tf
sFfSYD6V6ikzywmQSMgV4y+LjbzJmDm7unVAURsv6qCdqYBQrTBiQ9gJ9oKEgopfP9EvzxqFaqVu
q7y7Jofu4fuyI257uQShxxmo6+3+DTcVlRdgqBUjI+iVAS1ntAfZksnmBWsSzXMDra5i9cdyx8su
3EBe1SUvZ9W5Zn3Lj/vbKyI15gqXqRHpk5GIMCe0avbJMdxruOXLs/hjL9QVp/z/SvmcBkKchsXu
mZ8VHWYPi/yntiGPinCQTZC/aiXSy5Nnr6dUtshZ/CByV9VfWO4mVdUBWJOYJFkBT/A3iRENFgcZ
gJ7TgwCYFHhQvlE0BGRc9ggld2jmeSHWaufenrQ/38VktbnjPpDO7bVlUvJbh/T7JtpwKmDsxB+1
YF4DL+AqnpJULN7VG19SYoMPPAb9EPtRqjMi9qhCCWVffr+myhC0jYp8mJyorQPvruie0PtaF6MH
G7XTllstCRl5eknF3gTJ52bQCNJEBeMOkCrmucd5StfxWKClplILjQeBSWoT2+iAZrtgSjsmtqHo
YXzksPXfUo184sgoUj+piy2hSUBUcONJK8joyZzLKZ3YuCmnwLX6SgnAMZk1krrdMA3RZwVqVzG7
XRo6CtxEbuF01mSJf2oCbLHOfFUsr5svaT5YQg329Qv2NXqz9S9nOmmP9+AYOp5apt4qf0x3Xahq
Zms4odQFZWUEAM9aF9eiCw+7qcupjvHIzQTZ/91L47MJ/cs0bvroPETnJyXXXtr5kRUiG4w/e2UE
H4LHjoDLYizu1Xm0s8KMx4eMkQ/gEWWqU5Lr+InPrP8HEHf7sfu4L+1NKyBWn3SrSXRa4SQSj4vl
WSohD2mvU/YknCKIYYUH1fNjrRwZ4/sxdHcP6z+FbamWFoZWVhHw+Y232uvLdLD7sGP/CvfHeqkQ
pXxWaSE+lGMhg6xcNZ8W40zxsHjwNs8/HGh4Emu4p4fmiywl0p9s7Y7OrT53XW/+ZX714ekClnDA
MuKP8jsH7h2EmAFXM3vXX/IJgr3Fw4lRR2vtrw844iQHHQdNO11o9OwgyMjL278n2XRtsufMA0ex
K8LZynimjcIBLHQ77nwp5sqQikE0AU3ITDgsNEcvxm8lyI4NAbxFq4bsUvjh0bKQXWAUyVfMwBJ9
EjEFXDPYp+V4XY5M5RgzCmFxrSz7d5TVDnKLmm8q3BorWVdb4CnA+yl5fsJHbwEE3XIsALkp/aG2
o3/W2NgdqqzisXBshG3dkzdVrfPeU1jTf/aLEstyOi00lEeH5ZHJ5WaU+lsurnlB7QGVlF7JGNDH
L4Ik9hV9UREbEWsX2Q9FbEnBe+PgAhrTrvZ+RxhBZ7F0Mq1gwpPnI7ynBD3o3YIXkx3Hk1WNW+Tr
mGVjhIWJ1VJ5xupOXQjHUVyhIXODROD37o+e9GFGcLe5xsVpIA+QS+vtrbl864/yugxfWmRJlFp+
Sf1sOyEDxD5ATzwJW7UgHh5RwXW5sv5IAgv0eaiIhGkMJQ/GawMeL35oGLLU3ewjMzouAeSoAwNi
5g2NSbSa4/5w4+9HVkNbSmSull3t3KYYp9Cghbd5D0hR0p2S30JuFaT+MnYyX3XctieK5eplJFpT
oMJtguqZ/qc/VmkG6o+vuKa23GF5c4dddtFZmlbzKdckte/ScibVoL14qroMV5X7axM6betFd3km
3j6cNgjP0zGoHrdpmXCCsDOl8yekfeTnqTef5qUx6ZOM9wzXvMVMEax3+PLGa6/BKUl4Q5R1d4rZ
SBwAK0MDVhVykrWvTn2aqVxe3KiAotbiWQ439egp8mI8rghppWZs/HsInjYY2OMfq/nXe2vFJl68
4vJSmWs4ka++n66FabrEbmjPZHICf6hMz6SBJ1dadwJDwSMwirIL55jeVzSt4oXj6NBejw780Pgb
XXGfW++jCzmFzU1YFLxfL0xsH+M2U0lA2JdhT1X7FHYoOgPEbRe87SUsrC6Ay347ztgqTpM64Ep/
LBOAXAIHGC6G32ztCot8ZBT/SxwpZyA4pknuyDyMXZJ0wGoQfIFj0RpIExGncJpNcTi0NH93Z52A
tkayMdTzrhPPBfFruhq/7j/Mkui7LxossAeHLNnIoDvRic7bExzJs4gROaYW1magkVrjLmB/mfKd
KBNdvGj/fr1wh7ly0liLWIrZ9KyVhy4sfSzbrSNnRmy8w8QupDLrpGo2Pb9G18V31zhjmdkQuY99
wPNPToKiOyZMKC861HH0r0xmkitUAjcI7mwuK3pKrYPaI+DcPZNnV0FKUux8N2sstiWUCjsSePN4
0XZM0Vx5HAVKfaNkohRkVtFeZWgIcdcizs+GLlonSqHf7oMkMHtx7yGyPylm3sYLP+QyJbifWvV8
cwoxcsyDsOvlMMIodhBw6aHPGlVlgoKKKB47qzJ24hiYIy873mTgwoRL72mKuBmj9/KR4NYI/+Yh
+j36dHdYDs2Grdg8EgzT8yI1YcyEtqTzblfkmRsFDITGb1NeHPnNR3R6I3MsjR/RRaGuRIDQL5Bd
VergQw/cpr4UGO8YTVzwEKerdVnXDjNVUUZP69dndawWpYYhUbsU+Gm0uXahhdsvjrkJI4p1ev+M
2Fxp8IXUUbx8DxrtmIn2evls907OrJg6kUslhMPQxCRTS+450hq0+hHd3X7uuCpRuSCmx60Uv38R
g17EB4/ncVIUzBeg7X692xuZXteMGqUF/IwDRVXLyc2FRMt+bu0Os6cBp0XcwSHAehT4eAbjLr23
x4dYdnW1mX3fbtEL+1m4ngfp9C2xQbou8QcHrn+8bLpWbpfivWtqR3kg09bWP6o5+4hB44mbC+KP
v8wdoJIOu1Sh2FCJMHx7AJdGVK6lBl/WfqMlplr92VJ3Zg2njStBpYwfqbUqK+XOy8U+nHAlvUaG
0iqLcZJkQKB+yNtsPAtIRTCTdm+o/kJL7dMBDuFkUhyKJ8labjcjAfORN+mZq7nHzJbT3ZG+nh+7
ioKQoPdciImCc6Ud2WESWXHLqIJDNx82j9OBm0NKDf42s7AFVvCGl0ZE1lk1c9sUv6HHlSVcbzRa
IRw0oX2s96umoIxZYnTvAVhQSrJi5NNmpfTb26rhX5BQpquPegyZwNtimPHtQYD42IXYNRqrN85f
MhT1iYlsc0khNPb2dSaAaO+ffKQbhoeBJxe+qgeyrBNX9EPPxJNTms501FnsgnIpJ3/mvdJmRxVS
4OEr15SA+6rIe3js5U5xYIndzviuiJxJLWKb1hgfe5uYWK3BUFEW0A3HKsOjoo6znUQrMbgY+W6a
Hbzb3w2WvXVEVucQEUTg2Cx1bZ+N5XyI2hlA+RnloyQ+Rx2rvE1vMEV04+JT8+gcd/fF/qmqAy5a
xztW/4oGvtU0g+yHz88aMkjEyAwZbMX7owRTop3YzapiJtyjo5S1HYs1QDNbolNZkMicxIu5a1XZ
q6ouGNiycaKCoerUJ9Yv6UkGiCKyqFOdCRbKdsc98mj0bdSB4vRRxuA55qfxkXoPQyo3fhrD03bL
1W09B5vnDAwe4OwsKHkZvdiAfXWTUt/zfwS6C7HGQ7alwKIuYjngrEWpZ3hKqAZpmOhjjjV85bzA
wl1wZmOd+FKRetIIaSCBtWt2e/8gEB3wMwNCXCIwjocuBZb5aMkvjUW7pr/e6ORZfcszVEdAIqVe
A5DCPh+VEuS0gi7EeDQZE3P9/W/pFYiObLx9zonKiFyWkAts5+a5LRHg8rw07zPpBEHapNS1T48T
CdlqjU93qlfdNcxKi67XUTxPgSIjHry7emDFrdlwI7HHw1ZPBiG8PrzuCuiPRPeGgcJqLho2cuBJ
H51PiOBQGvJhi3bLd1gEEiutF1E3HEYFX79HHyEVzflvoNqdc8hV/0O7OR4ICq0IrQdKMHvOeq/j
EndnMUTYMrIq1FKhqFpWpFUQFR5zTB1hsC7vr6v9xixYENE0jrWvrgdxkWceZHc+FNATHTFpiMc7
isVMyM1Q2cKwqvnggz+UxiO1fUKgnOQp208PwouMt7eV7TFuV78NFjyTTQWJHu1ppcn96YLphjEu
C29xA7dqSrPEMar5ydTD3OZ5GoOhe9CiZIi7Kx3SyTALIxgKnGj3VzZUfIeQYcLJ8DV//sL4ChUD
EHV2hyylWAXQuzHme1L48yIS57pRtyuZYvikd7R6ooxaQUd4zPitxsxRAqCVTvpKNw1qmYFBpZIo
7EMrtTgneR0ffSPFYVo7U0SlqSZ1lISFCQoSjGOtWMSfM2s4nj0kVkL2dPLYKvMTnpRrVGq0CD+c
8AnEm0PleVx2xy6sr5QpMADQVFc4sPExHLs+kdnVY4mG21wRTEgN5+GkJAOJstC79RX8obQ5ntW7
O/6g1KZvsxsJzl0KL02V+LIgZaTPve1O3AnPkTqWxEzDqI4rPEzNAi0RO2D6pYa/waLlBUQFm5qR
4dNjUqyfMu+XsKVAzXjmLF6qYlsYRwCg4r58bxD2s/3u3bwQWd+o4hBMZDKvDvVylJx4tcgq3oos
qFC36b+fhPoHp8HYzUvPdEU6bTzh+2MNo7wKGFSzgeDVHllnk2H6me1snblE2CVgCw6fN9e+fy1f
goXdJJPamLxTbcgph9sLPasEONlcUKufRcDAjRZBGbPDQUekus9MIUSpixRVrpQLA6GZ91GzW57T
3Yx1KCGl4hKkbee1CZgo6SEPExUi5gPrbT0rtSSjgxGZUr+0RXR+45mrK7lNCYYmGKSQ/hS5qWt9
yEtWlVbAJQddK6J7nGpJkEfltay9d250YVyIlyau7Dc8oFCJXtJDJ6Lv1V0AtEBVPw0pwwIuwJWM
v9kU0sa9cMzNE+9XWqE1ucu1v+hMHM6L683rIjCzrZgwlylOeufklFJsByDuvk/6RSiOccRxJh0D
DciEvUdRzNWo/WOhP4ceX13zDerqrF2EeXiQ49h8d021Li2LRMAOqqyLFXeslzbo1UOV6chlbnym
/XLWjMvfJJEmMwEI05NEKV6bFnfJlwbBKVvOe0Hc2lzPbvkDZrdkGqceIRdUTR09M5oVCnl2R53L
m0pYvBeyI4RyJtBLlWaziwd3VPeLDqoIz4Uu8cS7QLNCXQNUYkFTTJ7ck8W1PyGdkXC8pme3qr4B
aSLutHMmyLt27bUtXdf/QcVi6QulHaT/ij4IjyXV4ZIAMUMWEBTjqk7KRwKcyyP+Mx3zgc9JYocM
WKnKlFzjrS/YhR2FNZVQLpYMBTbeVPQ/dN3asQ8o9Bxnf+fNaElkknqn0WBvOd6e0ppW4yxh0F23
JSWNGXUv4fy/M2tsWAAoYujNDCxB21D6FuMJQLjMgvQ0pMTkQnJbR5YABmXZ+WBjdaJJ7GWpSnFr
TXO6PrCW02EfI4LuGvpw+lQGS1YVw43rLW5mjZP5V3gWKi+ko+kO5RUlePMqIgXNZ7oA5uH1HbmH
3rr0Lj+7T7x3HNQfCpzR6Utux5BPaZY/ZnCFpElv2rUfVM291rbrEn+vhFqIoqlgW2+JHYr9IX3e
HkR4epPb3uIJpBCA2ItFfB6ADT0NTFqpqGL+dPPoi1Ja4pfFnA2lY3rKH48O51dWt++XEEwy/4yE
jOfKMlEYYtigX/5Da9K+4A8sC4v0kgmKLHk89NNJHVWrZ2VJMj4MTTC2zm4ao9oFxch+mpTwWyi4
y+CG/1A9zWikHMY+XunCBvFRvVboZj3dNVrkJWP3rVrL+IWBv/uoxtvM3JqarhFOeUVzhXFs5yRC
yGwFNreWUyGLxwQkBtu/MqeVrBoYtTNtDYLBHbiAqk8JgYmD5pkdG+QOmsZunNs41mqewhoXTlQp
5xhycC9fCmA63b3MGQAR7dFlzxMmY0qygO+4vDlMBfCJAKPWMMqpnQaZe6pDVccmRRc+efRMXqzB
Vd4Zdjph9J4DIKxgzoE6oEj5e+14fBj84zvBpS3JH9uQYEfKYccOakM1thMjVgyyftCuUZryaPHK
Ney9h6W96YhOuhnSusI7dYBlHctBwwziezuC1H7PpAeJdCmvFDTeNbCIQG9zV30863fI5v5YFdCr
/CajET5Fb1RgD1jw8xnGKZtuYOV7jcU/w+1+W5ZExP5dnZYtVA8pFYREy4vJKGMYJ4Q/95vsy++Q
S6bRQUxJw4DIxM5KLr3oFmrdTNdSK6O0gWn6UylS4YA151/mxO5Dm35Lnm8hWuf8IRFvn3Bkr2Zf
lEDR6s5BuBvSWE4YGoxaxbV7m/JuvS8Pm/JXgmMaEaCHs6VqGLFRPUFpRAcALvdCKyA1n7kFxCCF
aVEGoOekmYGjB3n7IvYp4cuJJxR3l9mTiiMMsN3L04MCT9l2SfN5xiu/xMmPoVeT+hibNBYcMA47
M0J4FD1vtJB1rEKpKpKjWINbafEiKtWonKvB7Ukj+t8A08bBYvbR7fAZOSKChA6dctKBw+3NvGSK
XWVwtqVI8irOxXCy/xnmJfTrQ6FhQhj1c+w6pVqTEEuZZGnihW57wVXonbCh
`protect end_protected
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_sim_netlist.vhdl | 1 | 719637 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:59 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_sim_netlist.vhdl
-- Design : zynq_design_1_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
port (
\s_axi_arready[0]\ : out STD_LOGIC;
aa_mi_arvalid : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_axi.read_cnt_reg[5]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
mi_arready_2 : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC;
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_araddr[30]\ : in STD_LOGIC;
\s_axi_araddr[28]\ : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC;
\m_payload_i_reg[34]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aresetn_d_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \^gen_axi.s_axi_rid_i_reg[11]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.s_axi_rlast_i_i_6_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_target_hot_i_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_valid_i_reg_0\ : STD_LOGIC;
signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready[0]\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_5\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[16]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair6";
begin
aa_mi_arvalid <= \^aa_mi_arvalid\;
\gen_axi.s_axi_rid_i_reg[11]\(0) <= \^gen_axi.s_axi_rid_i_reg[11]\(0);
\gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) <= \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0);
\gen_no_arbiter.m_valid_i_reg_0\ <= \^gen_no_arbiter.m_valid_i_reg_0\;
\m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0);
\s_axi_arready[0]\ <= \^s_axi_arready[0]\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0),
I2 => mi_arready_2,
I3 => p_15_in,
O => E(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444444444444F"
)
port map (
I0 => \gen_axi.read_cnt_reg[5]\,
I1 => p_15_in,
I2 => \gen_axi.s_axi_rlast_i_i_6_n_0\,
I3 => \^m_axi_arqos[7]\(44),
I4 => \^m_axi_arqos[7]\(45),
I5 => \^m_axi_arqos[7]\(47),
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^m_axi_arqos[7]\(49),
I1 => p_15_in,
I2 => \^m_axi_arqos[7]\(48),
I3 => \^m_axi_arqos[7]\(46),
I4 => \^m_axi_arqos[7]\(51),
I5 => \^m_axi_arqos[7]\(50),
O => \gen_axi.s_axi_rlast_i_i_6_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(1),
O => D(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(0),
I2 => r_issuing_cnt(1),
I3 => r_issuing_cnt(2),
O => D(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666666666662"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\,
I1 => \m_payload_i_reg[34]\,
I2 => r_issuing_cnt(0),
I3 => r_issuing_cnt(1),
I4 => r_issuing_cnt(2),
I5 => r_issuing_cnt(3),
O => \gen_master_slots[0].r_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => r_issuing_cnt(3),
I1 => r_issuing_cnt(2),
I2 => r_issuing_cnt(1),
I3 => r_issuing_cnt(0),
I4 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
O => D(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => aa_mi_artarget_hot(0),
I2 => \^aa_mi_arvalid\,
O => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
I2 => m_axi_arready(0),
I3 => \m_payload_i_reg[34]\,
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(4),
I2 => r_issuing_cnt(5),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666666666662"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\,
I1 => \m_payload_i_reg[34]_0\,
I2 => r_issuing_cnt(4),
I3 => r_issuing_cnt(5),
I4 => r_issuing_cnt(6),
I5 => r_issuing_cnt(7),
O => \gen_master_slots[1].r_issuing_cnt_reg[8]\(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => r_issuing_cnt(7),
I1 => r_issuing_cnt(6),
I2 => r_issuing_cnt(5),
I3 => r_issuing_cnt(4),
I4 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => aa_mi_artarget_hot(1),
I2 => \^aa_mi_arvalid\,
O => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080808080808080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(1),
I2 => m_axi_arready(1),
I3 => s_axi_rready(0),
I4 => m_valid_i_reg,
I5 => Q(0),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[16]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => mi_arready_2,
I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0),
I2 => \^aa_mi_arvalid\,
O => \^gen_no_arbiter.m_valid_i_reg_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => st_aa_artarget_hot(0),
I1 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[7]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[7]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[7]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[7]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[7]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[7]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[7]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[7]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[7]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[7]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[7]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[7]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[7]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[7]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[7]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[7]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[7]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[7]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[7]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[7]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[7]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[7]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[7]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[7]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[7]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[7]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[7]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[7]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[7]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[7]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[7]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[7]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[7]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[7]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[7]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[7]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[7]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[7]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[7]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[7]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[7]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[7]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[7]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[7]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[7]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[7]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[7]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[7]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[7]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[7]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[7]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[7]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[7]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[7]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[7]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[7]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[7]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[7]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[7]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[7]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[7]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[7]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[7]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[7]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[7]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[7]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[7]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[7]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[7]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => aa_mi_artarget_hot(0),
O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => \s_axi_arqos[3]\(33),
I1 => \s_axi_arqos[3]\(36),
I2 => \s_axi_araddr[30]\,
I3 => \s_axi_araddr[28]\,
I4 => \s_axi_araddr[25]\,
O => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => st_aa_artarget_hot(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => aa_mi_artarget_hot(1),
O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\,
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\,
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg_0,
Q => \^gen_axi.s_axi_rid_i_reg[11]\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000002A"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
I2 => m_axi_arready(0),
I3 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\,
I4 => \^gen_no_arbiter.m_valid_i_reg_0\,
I5 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFEFFFEFFFFF"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I1 => \^aa_mi_arvalid\,
I2 => s_axi_arvalid(0),
I3 => \^s_axi_arready[0]\,
I4 => \chosen_reg[0]\,
I5 => \gen_multi_thread.accept_cnt_reg[3]\,
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg,
Q => \^s_axi_arready[0]\,
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(1),
O => m_axi_arvalid(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
aa_mi_awtarget_hot : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].w_issuing_cnt_reg[9]\ : out STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
st_aa_awtarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 );
\chosen_reg[1]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\chosen_reg[0]\ : in STD_LOGIC;
mi_awready_2 : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[26]\ : in STD_LOGIC;
\s_axi_awaddr[20]\ : in STD_LOGIC;
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^aa_mi_awtarget_hot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \^gen_master_slots[1].w_issuing_cnt_reg[9]\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal \^st_aa_awtarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[9]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_4\ : label is "soft_lutpair12";
begin
aa_mi_awtarget_hot(2 downto 0) <= \^aa_mi_awtarget_hot\(2 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
\gen_master_slots[1].w_issuing_cnt_reg[9]\ <= \^gen_master_slots[1].w_issuing_cnt_reg[9]\;
\m_ready_d_reg[1]\ <= \^m_ready_d_reg[1]\;
ss_aa_awready <= \^ss_aa_awready\;
st_aa_awtarget_hot(0) <= \^st_aa_awtarget_hot\(0);
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(2),
I3 => mi_awready_2,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA95555555"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \chosen_reg[0]\,
I2 => m_axi_awready(0),
I3 => \^aa_mi_awtarget_hot\(0),
I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\,
I5 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA55555554"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\,
I1 => w_issuing_cnt(3),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(2),
I4 => w_issuing_cnt(1),
I5 => \chosen_reg[0]\,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => w_issuing_cnt(3),
I1 => w_issuing_cnt(0),
I2 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(0),
I3 => m_axi_awready(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => \chosen_reg[0]\,
I1 => m_axi_awready(0),
I2 => \^aa_mi_awtarget_hot\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_ready_d(1),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA55555554"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\,
I1 => w_issuing_cnt(7),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(6),
I4 => w_issuing_cnt(5),
I5 => \chosen_reg[1]\,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => w_issuing_cnt(7),
I1 => w_issuing_cnt(4),
I2 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(1),
I3 => m_axi_awready(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000070000000"
)
port map (
I0 => m_valid_i_reg,
I1 => s_axi_bready(0),
I2 => m_axi_awready(1),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^aa_sa_awvalid\,
I5 => m_ready_d(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA95555555"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \chosen_reg[1]\,
I2 => m_axi_awready(1),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\,
I5 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[1].w_issuing_cnt[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => m_ready_d(1),
O => \^gen_master_slots[1].w_issuing_cnt_reg[9]\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\,
I1 => \s_axi_awaddr[26]\,
I2 => \s_axi_awaddr[20]\,
I3 => \s_axi_awqos[3]\(33),
I4 => \s_axi_awqos[3]\(36),
O => \^st_aa_awtarget_hot\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_awqos[3]\(35),
I1 => \s_axi_awqos[3]\(31),
I2 => \s_axi_awqos[3]\(28),
I3 => \s_axi_awqos[3]\(39),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(0),
Q => Q(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(10),
Q => Q(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(11),
Q => Q(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(12),
Q => Q(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(13),
Q => Q(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(14),
Q => Q(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(15),
Q => Q(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(16),
Q => Q(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(17),
Q => Q(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(18),
Q => Q(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(19),
Q => Q(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(1),
Q => Q(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(20),
Q => Q(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(21),
Q => Q(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(22),
Q => Q(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(23),
Q => Q(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(24),
Q => Q(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(25),
Q => Q(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(26),
Q => Q(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(27),
Q => Q(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(28),
Q => Q(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(29),
Q => Q(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(2),
Q => Q(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(30),
Q => Q(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(31),
Q => Q(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(32),
Q => Q(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(33),
Q => Q(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(34),
Q => Q(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(35),
Q => Q(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(36),
Q => Q(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(37),
Q => Q(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(38),
Q => Q(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(39),
Q => Q(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(3),
Q => Q(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(40),
Q => Q(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(41),
Q => Q(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(42),
Q => Q(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(43),
Q => Q(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(44),
Q => Q(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(45),
Q => Q(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(46),
Q => Q(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(47),
Q => Q(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(48),
Q => Q(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(49),
Q => Q(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(4),
Q => Q(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(50),
Q => Q(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(51),
Q => Q(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(52),
Q => Q(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(53),
Q => Q(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(54),
Q => Q(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(55),
Q => Q(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(56),
Q => Q(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(57),
Q => Q(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(58),
Q => Q(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(5),
Q => Q(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(59),
Q => Q(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(60),
Q => Q(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(61),
Q => Q(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(62),
Q => Q(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(63),
Q => Q(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(64),
Q => Q(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(6),
Q => Q(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(65),
Q => Q(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(66),
Q => Q(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(67),
Q => Q(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(68),
Q => Q(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(7),
Q => Q(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(8),
Q => Q(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(9),
Q => Q(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^st_aa_awtarget_hot\(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => \^aa_mi_awtarget_hot\(0),
O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => st_aa_awtarget_enc(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => \^aa_mi_awtarget_hot\(1),
O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\,
Q => \^aa_mi_awtarget_hot\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\,
Q => \^aa_mi_awtarget_hot\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg_0,
Q => \^aa_mi_awtarget_hot\(2),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F2"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I2 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => \^aa_mi_awtarget_hot\(0),
I1 => \^aa_mi_awtarget_hot\(1),
I2 => \^aa_mi_awtarget_hot\(2),
I3 => m_ready_d(0),
I4 => \^m_ready_d_reg[1]\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^ss_aa_awready\,
I1 => m_ready_d_0(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg,
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \^aa_mi_awtarget_hot\(0),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \^aa_mi_awtarget_hot\(1),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
O => m_axi_awvalid(1)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555554FFFFFFFF"
)
port map (
I0 => \^m_ready_d_reg[1]\,
I1 => m_ready_d(0),
I2 => \^aa_mi_awtarget_hot\(2),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^aa_mi_awtarget_hot\(0),
I5 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^aa_mi_awtarget_hot\(2),
I2 => \^aa_mi_awtarget_hot\(1),
I3 => \^aa_mi_awtarget_hot\(0),
O => \m_ready_d_reg[1]_0\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000777"
)
port map (
I0 => m_axi_awready(1),
I1 => \^aa_mi_awtarget_hot\(1),
I2 => mi_awready_2,
I3 => \^aa_mi_awtarget_hot\(2),
I4 => \m_ready_d[1]_i_4_n_0\,
I5 => m_ready_d(1),
O => \^m_ready_d_reg[1]\
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_axi_awready(0),
I1 => \^aa_mi_awtarget_hot\(0),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC;
\chosen_reg[0]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]_0\ : out STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : out STD_LOGIC;
aresetn_d : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
p_80_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[26]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ : in STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_3\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_4\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_38_out : in STD_LOGIC;
p_60_out : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_5\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \chosen[0]_i_1__0_n_0\ : STD_LOGIC;
signal \chosen[1]_i_1__0_n_0\ : STD_LOGIC;
signal \chosen[2]_i_1__0_n_0\ : STD_LOGIC;
signal \^chosen_reg[0]_0\ : STD_LOGIC;
signal \^chosen_reg[1]_0\ : STD_LOGIC;
signal \^gen_master_slots[0].w_issuing_cnt_reg[1]\ : STD_LOGIC;
signal \^gen_master_slots[2].w_issuing_cnt_reg[16]\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_6_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \chosen[0]_i_1__0\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \chosen[2]_i_1__0\ : label is "soft_lutpair112";
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_6\ : label is "soft_lutpair111";
begin
SR(0) <= \^sr\(0);
\chosen_reg[0]_0\ <= \^chosen_reg[0]_0\;
\chosen_reg[1]_0\ <= \^chosen_reg[1]_0\;
\gen_master_slots[0].w_issuing_cnt_reg[1]\ <= \^gen_master_slots[0].w_issuing_cnt_reg[1]\;
\gen_master_slots[2].w_issuing_cnt_reg[16]\ <= \^gen_master_slots[2].w_issuing_cnt_reg[16]\;
m_valid_i <= \^m_valid_i\;
\chosen[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(0),
I1 => need_arbitration,
I2 => \^chosen_reg[0]_0\,
O => \chosen[0]_i_1__0_n_0\
);
\chosen[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(1),
I1 => need_arbitration,
I2 => \^chosen_reg[1]_0\,
O => \chosen[1]_i_1__0_n_0\
);
\chosen[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(2),
I1 => need_arbitration,
I2 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
O => \chosen[2]_i_1__0_n_0\
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[0]_i_1__0_n_0\,
Q => \^chosen_reg[0]_0\,
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[1]_i_1__0_n_0\,
Q => \^chosen_reg[1]_0\,
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[2]_i_1__0_n_0\,
Q => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
R => \^sr\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^chosen_reg[0]_0\,
I1 => p_80_out,
I2 => s_axi_bready(0),
O => \^gen_master_slots[0].w_issuing_cnt_reg[1]\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_bready(0),
I1 => \^chosen_reg[1]_0\,
I2 => p_60_out,
O => \gen_master_slots[1].w_issuing_cnt_reg[8]\
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F7F00"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => s_axi_bready(0),
I3 => \m_ready_d_reg[1]_5\,
I4 => w_issuing_cnt(4),
O => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A956"
)
port map (
I0 => Q(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFF1100E"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFE00000000FFFF"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => Q(1),
I3 => Q(2),
I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AAAAAAAA999A"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => \m_ready_d_reg[1]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I4 => Q(1),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_0,
I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_4\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_3\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_3,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_2\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \m_ready_d_reg[1]_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00AAAA80AA80AA80"
)
port map (
I0 => s_axi_bready(0),
I1 => \^chosen_reg[0]_0\,
I2 => p_80_out,
I3 => m_valid_i_reg,
I4 => p_38_out,
I5 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"1FFF1000"
)
port map (
I0 => \s_axi_awaddr[26]\(0),
I1 => st_aa_awtarget_hot(0),
I2 => \^m_valid_i\,
I3 => aresetn_d,
I4 => aa_mi_awtarget_hot(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F022"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\,
I3 => \s_axi_awaddr[26]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF40FFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I1 => Q(3),
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => aa_sa_awvalid,
I4 => s_axi_awvalid(0),
I5 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => \^gen_master_slots[0].w_issuing_cnt_reg[1]\,
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(0),
I4 => w_issuing_cnt(3),
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEFEFAAEAEA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I2 => st_aa_awtarget_hot(0),
I3 => \gen_master_slots[1].w_issuing_cnt_reg[10]\,
I4 => \s_axi_awaddr[26]\(0),
I5 => \gen_master_slots[2].w_issuing_cnt_reg[16]_1\,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF57AA00"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[0]_i_1_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5F7A0A0"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_3_in,
O => \last_rr_hot[1]_i_1_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDF8888"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_4_in,
O => \last_rr_hot[2]_i_1_n_0\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEE00000FEE"
)
port map (
I0 => p_60_out,
I1 => p_38_out,
I2 => \^chosen_reg[0]_0\,
I3 => p_80_out,
I4 => \last_rr_hot[2]_i_6_n_0\,
I5 => s_axi_bready(0),
O => need_arbitration
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA20222020"
)
port map (
I0 => p_38_out,
I1 => p_60_out,
I2 => \last_rr_hot_reg_n_0_[0]\,
I3 => p_80_out,
I4 => p_4_in,
I5 => p_3_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA0A0A0008"
)
port map (
I0 => p_60_out,
I1 => p_3_in,
I2 => p_80_out,
I3 => p_38_out,
I4 => p_4_in,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(1)
);
\last_rr_hot[2]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A8A8A8A88888A88"
)
port map (
I0 => p_80_out,
I1 => p_4_in,
I2 => p_38_out,
I3 => \last_rr_hot_reg_n_0_[0]\,
I4 => p_60_out,
I5 => p_3_in,
O => next_rr_hot(0)
);
\last_rr_hot[2]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_60_out,
O => \last_rr_hot[2]_i_6_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[0]_i_1_n_0\,
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[1]_i_1_n_0\,
Q => p_3_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[2]_i_1_n_0\,
Q => p_4_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_60_out,
I4 => p_80_out,
I5 => \^chosen_reg[0]_0\,
O => s_axi_bvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.accept_cnt_reg[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]_0\ : out STD_LOGIC;
\m_payload_i_reg[34]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC;
cmd_push_3 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_3\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_4\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_5\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_74_out : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_54_out : in STD_LOGIC;
p_32_out : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 is
signal \chosen[0]_i_1_n_0\ : STD_LOGIC;
signal \chosen[1]_i_1_n_0\ : STD_LOGIC;
signal \chosen[2]_i_1_n_0\ : STD_LOGIC;
signal \^chosen_reg[1]_0\ : STD_LOGIC;
signal \^gen_multi_thread.accept_cnt_reg[2]\ : STD_LOGIC;
signal \i__carry_i_10_n_0\ : STD_LOGIC;
signal \i__carry_i_11_n_0\ : STD_LOGIC;
signal \i__carry_i_12_n_0\ : STD_LOGIC;
signal \i__carry_i_13_n_0\ : STD_LOGIC;
signal \i__carry_i_14_n_0\ : STD_LOGIC;
signal \i__carry_i_15_n_0\ : STD_LOGIC;
signal \i__carry_i_16_n_0\ : STD_LOGIC;
signal \i__carry_i_5_n_0\ : STD_LOGIC;
signal \i__carry_i_6_n_0\ : STD_LOGIC;
signal \i__carry_i_7_n_0\ : STD_LOGIC;
signal \i__carry_i_8_n_0\ : STD_LOGIC;
signal \i__carry_i_9_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^m_payload_i_reg[34]\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \chosen[0]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \chosen[2]_i_1\ : label is "soft_lutpair79";
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_3\ : label is "soft_lutpair78";
begin
\chosen_reg[1]_0\ <= \^chosen_reg[1]_0\;
\gen_multi_thread.accept_cnt_reg[2]\ <= \^gen_multi_thread.accept_cnt_reg[2]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i_reg[34]\ <= \^m_payload_i_reg[34]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\chosen[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(0),
I1 => need_arbitration,
I2 => \^m_payload_i_reg[0]_0\,
O => \chosen[0]_i_1_n_0\
);
\chosen[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(1),
I1 => need_arbitration,
I2 => \^chosen_reg[1]_0\,
O => \chosen[1]_i_1_n_0\
);
\chosen[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(2),
I1 => need_arbitration,
I2 => \^m_payload_i_reg[34]\,
O => \chosen[2]_i_1_n_0\
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[0]_i_1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[1]_i_1_n_0\,
Q => \^chosen_reg[1]_0\,
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[2]_i_1_n_0\,
Q => \^m_payload_i_reg[34]\,
R => SR(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A659"
)
port map (
I0 => Q(0),
I1 => \gen_no_arbiter.s_ready_i_reg[0]\,
I2 => \^gen_multi_thread.accept_cnt_reg[2]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFF4400B"
)
port map (
I0 => \^gen_multi_thread.accept_cnt_reg[2]\,
I1 => \gen_no_arbiter.s_ready_i_reg[0]\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => Q(1),
I3 => Q(2),
I4 => \^gen_multi_thread.accept_cnt_reg[2]\,
I5 => \gen_no_arbiter.s_ready_i_reg[0]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAAAAAAAAA9A99"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => \^gen_multi_thread.accept_cnt_reg[2]\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]\,
I4 => Q(1),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_0,
I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0),
I3 => \^gen_multi_thread.accept_cnt_reg[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_5\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_4\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_3,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\,
I2 => CO(0),
I3 => \^gen_multi_thread.accept_cnt_reg[2]\,
O => E(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_3\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_2\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8880000"
)
port map (
I0 => \^s_axi_rlast\(0),
I1 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I2 => \^m_payload_i_reg[0]_0\,
I3 => p_74_out,
I4 => s_axi_rready(0),
O => \^gen_multi_thread.accept_cnt_reg[2]\
);
\i__carry_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(9),
I2 => \m_payload_i_reg[46]_0\(22),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(22),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_10_n_0\
);
\i__carry_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(5),
I2 => \m_payload_i_reg[46]_0\(18),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(18),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_11_n_0\
);
\i__carry_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(17),
I2 => \m_payload_i_reg[46]_1\(4),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]_0\(17),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \i__carry_i_12_n_0\
);
\i__carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(19),
I2 => \m_payload_i_reg[46]_1\(6),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(19),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_13_n_0\
);
\i__carry_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(2),
I2 => \m_payload_i_reg[46]_0\(15),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(15),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_14_n_0\
);
\i__carry_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(14),
I2 => \m_payload_i_reg[46]_1\(1),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(14),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_15_n_0\
);
\i__carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(3),
I2 => \m_payload_i_reg[46]_0\(16),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(16),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_16_n_0\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0)
);
\i__carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(11),
I2 => \m_payload_i_reg[46]\(24),
I3 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I4 => \m_payload_i_reg[46]_0\(24),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \i__carry_i_5_n_0\
);
\i__carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(23),
I2 => \m_payload_i_reg[46]_1\(10),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(23),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_6_n_0\
);
\i__carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(25),
I2 => \m_payload_i_reg[46]_1\(12),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(25),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_7_n_0\
);
\i__carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(8),
I2 => \m_payload_i_reg[46]_0\(21),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(21),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_8_n_0\
);
\i__carry_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(7),
I2 => \m_payload_i_reg[46]_0\(20),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(20),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_9_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF57AA00"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[0]_i_1__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5F7A0A0"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_3_in,
O => \last_rr_hot[1]_i_1__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDF8888"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_4_in,
O => \last_rr_hot[2]_i_1__0_n_0\
);
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBABBBABBBAB88"
)
port map (
I0 => s_axi_rready(0),
I1 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I2 => \^m_payload_i_reg[0]_0\,
I3 => p_74_out,
I4 => p_54_out,
I5 => p_32_out,
O => need_arbitration
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA20222020"
)
port map (
I0 => p_32_out,
I1 => p_54_out,
I2 => \last_rr_hot_reg_n_0_[0]\,
I3 => p_74_out,
I4 => p_4_in,
I5 => p_3_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA0A0A0008"
)
port map (
I0 => p_54_out,
I1 => p_3_in,
I2 => p_74_out,
I3 => p_32_out,
I4 => p_4_in,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(1)
);
\last_rr_hot[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A8A8A8A88888A88"
)
port map (
I0 => p_74_out,
I1 => p_4_in,
I2 => p_32_out,
I3 => \last_rr_hot_reg_n_0_[0]\,
I4 => p_54_out,
I5 => p_3_in,
O => next_rr_hot(0)
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[0]_i_1__0_n_0\,
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[1]_i_1__0_n_0\,
Q => p_3_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[2]_i_1__0_n_0\,
Q => p_4_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B3"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_74_out,
I2 => s_axi_rready(0),
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => s_axi_rready(0),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
O => \m_payload_i_reg[34]_0\(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \i__carry_i_7_n_0\,
O => S(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \i__carry_i_10_n_0\,
O => S(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \i__carry_i_13_n_0\,
O => S(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \i__carry_i_16_n_0\,
O => S(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(0),
O => s_axi_rdata(0)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(5),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(5),
O => s_axi_rdata(5)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(6),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(6),
O => s_axi_rdata(6)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(7),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(7),
O => s_axi_rdata(7)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(8),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(8),
O => s_axi_rdata(8)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(9),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(9),
O => s_axi_rdata(9)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(10),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(10),
O => s_axi_rdata(10)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(11),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(11),
O => s_axi_rdata(11)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(1),
O => s_axi_rdata(1)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(2),
O => s_axi_rdata(2)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(3),
O => s_axi_rdata(3)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(4),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(4),
O => s_axi_rdata(4)
);
\s_axi_rid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(14),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(1),
I4 => \m_payload_i_reg[46]_0\(14),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(0)
);
\s_axi_rid[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(24),
I2 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I3 => \m_payload_i_reg[46]\(24),
I4 => \m_payload_i_reg[46]_1\(11),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(10)
);
\s_axi_rid[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(25),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(12),
I4 => \m_payload_i_reg[46]_0\(25),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(11)
);
\s_axi_rid[11]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^m_payload_i_reg[34]\,
I1 => p_32_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_54_out,
O => \s_axi_rid[11]_INST_0_i_1_n_0\
);
\s_axi_rid[11]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8FFF"
)
port map (
I0 => \^chosen_reg[1]_0\,
I1 => p_54_out,
I2 => \^m_payload_i_reg[34]\,
I3 => p_32_out,
O => \s_axi_rid[11]_INST_0_i_2_n_0\
);
\s_axi_rid[11]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8FFF"
)
port map (
I0 => \^m_payload_i_reg[34]\,
I1 => p_32_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_54_out,
O => \s_axi_rid[11]_INST_0_i_3_n_0\
);
\s_axi_rid[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(15),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(15),
I4 => \m_payload_i_reg[46]_1\(2),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(1)
);
\s_axi_rid[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(16),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(16),
I4 => \m_payload_i_reg[46]_1\(3),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(2)
);
\s_axi_rid[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(17),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(4),
I4 => \m_payload_i_reg[46]\(17),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => s_axi_rid(3)
);
\s_axi_rid[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(18),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(18),
I4 => \m_payload_i_reg[46]_1\(5),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(4)
);
\s_axi_rid[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(19),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(6),
I4 => \m_payload_i_reg[46]_0\(19),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(5)
);
\s_axi_rid[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(20),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(20),
I4 => \m_payload_i_reg[46]_1\(7),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(6)
);
\s_axi_rid[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(21),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(21),
I4 => \m_payload_i_reg[46]_1\(8),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(7)
);
\s_axi_rid[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(22),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(22),
I4 => \m_payload_i_reg[46]_1\(9),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(8)
);
\s_axi_rid[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(23),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(10),
I4 => \m_payload_i_reg[46]_0\(23),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(9)
);
\s_axi_rlast[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(0),
I2 => \m_payload_i_reg[46]\(13),
I3 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I4 => \m_payload_i_reg[46]_0\(13),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \^s_axi_rlast\(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FEAEAEA00EAEAEA"
)
port map (
I0 => \m_payload_i_reg[46]\(12),
I1 => p_32_out,
I2 => \^m_payload_i_reg[34]\,
I3 => p_54_out,
I4 => \^chosen_reg[1]_0\,
I5 => \m_payload_i_reg[46]_0\(12),
O => s_axi_rresp(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => p_54_out,
I1 => \^chosen_reg[1]_0\,
I2 => p_32_out,
I3 => \^m_payload_i_reg[34]\,
I4 => \^m_payload_i_reg[0]_0\,
I5 => p_74_out,
O => s_axi_rvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_2 : out STD_LOGIC;
p_14_in : out STD_LOGIC;
p_21_in : out STD_LOGIC;
p_15_in : out STD_LOGIC;
p_17_in : out STD_LOGIC;
\gen_axi.write_cs_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_2 : out STD_LOGIC;
\gen_axi.s_axi_arready_i_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : in STD_LOGIC;
mi_rready_2 : in STD_LOGIC;
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
mi_bready_2 : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave : entity is "axi_crossbar_v2_1_14_decerr_slave";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.s_axi_arready_i_reg_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.write_cs_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^mi_arready_2\ : STD_LOGIC;
signal \^mi_awready_2\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_14_in\ : STD_LOGIC;
signal \^p_15_in\ : STD_LOGIC;
signal \^p_17_in\ : STD_LOGIC;
signal \^p_21_in\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_4\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair15";
begin
\gen_axi.s_axi_arready_i_reg_0\ <= \^gen_axi.s_axi_arready_i_reg_0\;
\gen_axi.write_cs_reg[1]_0\(0) <= \^gen_axi.write_cs_reg[1]_0\(0);
mi_arready_2 <= \^mi_arready_2\;
mi_awready_2 <= \^mi_awready_2\;
p_14_in <= \^p_14_in\;
p_15_in <= \^p_15_in\;
p_17_in <= \^p_17_in\;
p_21_in <= \^p_21_in\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \^p_15_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \^p_15_in\,
I3 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9FFA900"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \gen_axi.read_cnt_reg\(0),
I3 => \^p_15_in\,
I4 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA9FFFFAAA90000"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg\(0),
I3 => \gen_axi.read_cnt_reg__0\(1),
I4 => \^p_15_in\,
I5 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FACAFAFACACACACA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_15_in\,
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \gen_axi.read_cnt[4]_i_2_n_0\,
I5 => \gen_axi.read_cnt_reg__0\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg\(0),
I2 => \gen_axi.read_cnt_reg__0\(2),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3CAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \^p_15_in\,
O => p_0_in(5)
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE2E22E2"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \^p_15_in\,
I2 => \gen_axi.read_cnt[7]_i_3_n_0\,
I3 => \gen_axi.read_cnt_reg__0\(5),
I4 => \gen_axi.read_cnt_reg__0\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \^mi_arready_2\,
I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0),
I2 => aa_mi_arvalid,
I3 => \^p_15_in\,
I4 => mi_rready_2,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B874B8"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \^p_15_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I3 => \gen_axi.read_cnt[7]_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg__0\(5),
I5 => \gen_axi.read_cnt_reg__0\(6),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(4),
I4 => \gen_axi.read_cnt_reg__0\(3),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg__0\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg__0\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg__0\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg__0\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg__0\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg__0\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg__0\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080FF80FF80FF80"
)
port map (
I0 => \^mi_arready_2\,
I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0),
I2 => aa_mi_arvalid,
I3 => \^p_15_in\,
I4 => mi_rready_2,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_15_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_2\,
I1 => \^p_15_in\,
I2 => mi_rready_2,
I3 => \^gen_axi.s_axi_arready_i_reg_0\,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
I1 => \gen_axi.read_cnt_reg__0\(5),
I2 => \gen_axi.read_cnt_reg__0\(6),
I3 => \gen_axi.read_cnt_reg__0\(7),
O => \^gen_axi.s_axi_arready_i_reg_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_2\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7F70F000F0F"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_reg\,
I1 => aa_mi_awtarget_hot(0),
I2 => write_cs(0),
I3 => mi_bready_2,
I4 => \^gen_axi.write_cs_reg[1]_0\(0),
I5 => \^mi_awready_2\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_2\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => write_cs(0),
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => \^mi_awready_2\,
I3 => aa_mi_awtarget_hot(0),
I4 => aa_sa_awvalid,
I5 => m_ready_d(0),
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => Q(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => Q(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => Q(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => Q(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => Q(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => Q(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => Q(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => Q(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => Q(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => Q(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => Q(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => Q(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFA888"
)
port map (
I0 => \storage_data1_reg[0]\,
I1 => write_cs(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => mi_bready_2,
I4 => \^p_21_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_21_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBA8888888A"
)
port map (
I0 => s_axi_rlast_i0,
I1 => E(0),
I2 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
I5 => \^p_17_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \gen_axi.read_cnt_reg__0\(6),
I2 => \gen_axi.read_cnt_reg__0\(5),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^p_15_in\,
I1 => mi_rready_2,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(4),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(2),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_17_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF0202"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => write_cs(0),
I3 => \storage_data1_reg[0]\,
I4 => \^p_14_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_14_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0252"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => write_cs(0),
I3 => \storage_data1_reg[0]\,
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF10FA10"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => mi_bready_2,
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => write_cs(0),
I4 => \storage_data1_reg[0]\,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => \^gen_axi.write_cs_reg[1]_0\(0),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter is
port (
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
ss_wr_awvalid : out STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter : entity is "axi_crossbar_v2_1_14_splitter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair141";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\FSM_onehot_state[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"111F"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \gen_multi_thread.accept_cnt_reg[3]\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0302030000000000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(0),
I4 => ss_aa_awready,
I5 => aresetn_d,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000EC00000000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(0),
I4 => ss_aa_awready,
I5 => aresetn_d,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => ss_aa_awready,
I1 => \^m_ready_d\(0),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(1),
O => s_axi_awready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 is
port (
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\m_ready_d_reg[0]_0\ : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC;
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[0]_1\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 : entity is "axi_crossbar_v2_1_14_splitter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEEEEEEC"
)
port map (
I0 => aa_sa_awvalid,
I1 => \^m_ready_d\(0),
I2 => aa_mi_awtarget_hot(2),
I3 => aa_mi_awtarget_hot(1),
I4 => aa_mi_awtarget_hot(0),
I5 => \m_ready_d_reg[0]_1\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => aa_sa_awvalid,
I1 => \^m_ready_d\(1),
I2 => aresetn_d,
I3 => \m_ready_d_reg[0]_0\,
I4 => \gen_no_arbiter.m_target_hot_i_reg[1]\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => st_aa_awtarget_enc(0),
Q => \storage_data1_reg[0]\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[1]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is
signal \FSM_onehot_state[3]_i_6_n_0\ : STD_LOGIC;
signal \^gen_rep[0].fifoaddr_reg[0]\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_rep[0].fifoaddr_reg[0]\ <= \^gen_rep[0].fifoaddr_reg[0]\;
push <= \^push\;
s_ready_i_reg <= \^s_ready_i_reg\;
\FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \FSM_onehot_state[3]_i_6_n_0\,
I1 => s_axi_wlast(0),
I2 => s_axi_wvalid(0),
I3 => m_avalid,
O => \^gen_rep[0].fifoaddr_reg[0]\
);
\FSM_onehot_state[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"F035FF35"
)
port map (
I0 => m_axi_wready(0),
I1 => p_14_in,
I2 => \storage_data1_reg[1]_0\,
I3 => \storage_data1_reg[0]\,
I4 => m_axi_wready(1),
O => \FSM_onehot_state[3]_i_6_n_0\
);
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg\,
O => \^push\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0DFFFFFFDDFFFF"
)
port map (
I0 => out0(1),
I1 => \^gen_rep[0].fifoaddr_reg[0]\,
I2 => s_ready_i_reg_0,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => out0(0),
O => \^s_ready_i_reg\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F011FFFFF0110000"
)
port map (
I0 => st_aa_awtarget_enc(0),
I1 => st_aa_awtarget_hot(0),
I2 => p_2_out,
I3 => out0(0),
I4 => load_s1,
I5 => \storage_data1_reg[1]_0\,
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_2 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_21_in : in STD_LOGIC;
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_2\ : STD_LOGIC;
signal \s_axi_bid[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bid[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bid[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal st_mr_bid : STD_LOGIC_VECTOR ( 35 downto 24 );
begin
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\;
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_2 <= \^mi_bready_2\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => w_issuing_cnt(0),
I1 => s_axi_bready(0),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(8),
Q => st_mr_bid(32),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(9),
Q => st_mr_bid(33),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(10),
Q => Q(4),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(11),
Q => st_mr_bid(35),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(0),
Q => st_mr_bid(24),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(1),
Q => Q(0),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(2),
Q => Q(1),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(3),
Q => Q(2),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(4),
Q => st_mr_bid(28),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(5),
Q => Q(3),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(6),
Q => st_mr_bid(30),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(7),
Q => st_mr_bid(31),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_21_in,
I1 => \^mi_bready_2\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => chosen(0),
O => \m_valid_i_i_1__1_n_0\
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => S(0)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\s_axi_bid[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
O => s_axi_bid(0)
);
\s_axi_bid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(0),
I1 => st_mr_bid(24),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(7),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\
);
\s_axi_bid[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
O => s_axi_bid(6)
);
\s_axi_bid[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(6),
I1 => st_mr_bid(35),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(13),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\
);
\s_axi_bid[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
O => s_axi_bid(1)
);
\s_axi_bid[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(1),
I1 => st_mr_bid(28),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(8),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\
);
\s_axi_bid[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[6]_INST_0_i_1_n_0\,
O => s_axi_bid(2)
);
\s_axi_bid[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(2),
I1 => st_mr_bid(30),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(9),
O => \s_axi_bid[6]_INST_0_i_1_n_0\
);
\s_axi_bid[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
O => s_axi_bid(3)
);
\s_axi_bid[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(3),
I1 => st_mr_bid(31),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(10),
O => \s_axi_bid[7]_INST_0_i_1_n_0\
);
\s_axi_bid[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => s_axi_bid(4)
);
\s_axi_bid[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5303030F53F3F3F"
)
port map (
I0 => st_mr_bid(32),
I1 => \m_payload_i_reg[13]_0\(11),
I2 => m_valid_i_reg_1,
I3 => \^m_payload_i_reg[2]_0\,
I4 => chosen(0),
I5 => \m_payload_i_reg[13]_0\(4),
O => \s_axi_bid[8]_INST_0_i_1_n_0\
);
\s_axi_bid[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
O => s_axi_bid(5)
);
\s_axi_bid[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(5),
I1 => st_mr_bid(33),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(12),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_21_in,
I2 => chosen(0),
I3 => s_axi_bready(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^mi_bready_2\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_38_out : in STD_LOGIC;
\m_payload_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is
signal \^gen_multi_thread.accept_cnt_reg[3]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal \s_ready_i_i_2__0_n_0\ : STD_LOGIC;
signal st_mr_bid : STD_LOGIC_VECTOR ( 22 downto 13 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axi_bid[11]_INST_0_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \s_ready_i_i_2__0\ : label is "soft_lutpair44";
begin
\gen_multi_thread.accept_cnt_reg[3]\ <= \^gen_multi_thread.accept_cnt_reg[3]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\;
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000700000000"
)
port map (
I0 => \^gen_multi_thread.accept_cnt_reg[3]\,
I1 => s_axi_bready(0),
I2 => Q(2),
I3 => Q(1),
I4 => Q(0),
I5 => Q(3),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => st_mr_bmesg(3),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(4),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(5),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(12),
Q => st_mr_bid(22),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => st_mr_bmesg(4),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => st_mr_bid(13),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => st_mr_bid(14),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => st_mr_bid(15),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(1),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => st_mr_bid(17),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(2),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(3),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => chosen(0),
I4 => \^m_payload_i_reg[0]_0\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
\s_axi_bid[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\,
O => s_axi_bid(4)
);
\s_axi_bid[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(4),
I1 => st_mr_bid(22),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(9),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\
);
\s_axi_bid[11]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => chosen(0),
O => \^gen_multi_thread.accept_cnt_reg[3]\
);
\s_axi_bid[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
O => s_axi_bid(0)
);
\s_axi_bid[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(0),
I1 => st_mr_bid(13),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(5),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\
);
\s_axi_bid[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
O => s_axi_bid(1)
);
\s_axi_bid[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0535353FF535353"
)
port map (
I0 => st_mr_bid(14),
I1 => \m_payload_i_reg[12]_0\(1),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(6),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\
);
\s_axi_bid[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
O => s_axi_bid(2)
);
\s_axi_bid[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0535353FF535353"
)
port map (
I0 => st_mr_bid(15),
I1 => \m_payload_i_reg[12]_0\(2),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(7),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\
);
\s_axi_bid[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
O => s_axi_bid(3)
);
\s_axi_bid[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(3),
I1 => st_mr_bid(17),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(8),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FBFBFBF3F808080"
)
port map (
I0 => st_mr_bmesg(3),
I1 => chosen(0),
I2 => \^m_payload_i_reg[0]_0\,
I3 => chosen(1),
I4 => p_38_out,
I5 => \m_payload_i_reg[1]_0\(0),
O => s_axi_bresp(0)
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0CCCFAAAFAAAFAAA"
)
port map (
I0 => \m_payload_i_reg[1]_0\(1),
I1 => st_mr_bmesg(4),
I2 => chosen(1),
I3 => p_38_out,
I4 => \^m_payload_i_reg[0]_0\,
I5 => chosen(0),
O => s_axi_bresp(1)
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => chosen(0),
I4 => \aresetn_d_reg[1]_1\,
O => \s_ready_i_i_2__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_2__0_n_0\,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => chosen(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => s_axi_bready(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => chosen(0),
I3 => s_axi_bready(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_17_in : in STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair69";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"955555552AAAAAAA"
)
port map (
I0 => \gen_axi.s_axi_arready_i_reg\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
I3 => \^m_valid_i_reg_0\,
I4 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I5 => r_issuing_cnt(0),
O => \gen_master_slots[2].r_issuing_cnt_reg[16]\
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FF2020000F202"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\,
I2 => st_aa_artarget_hot(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
I4 => st_aa_artarget_hot(1),
I5 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \^m_valid_i_reg_0\,
I2 => chosen_0(0),
I3 => s_axi_rready(0),
O => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_17_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => s_axi_rready(0),
I1 => chosen_0(0),
I2 => \^m_valid_i_reg_0\,
I3 => p_15_in,
I4 => \^skid_buffer_reg[34]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => p_15_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => s_axi_rready(0),
I3 => chosen_0(0),
I4 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_17_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is
port (
s_ready_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[32]_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
p_32_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is
signal \^gen_master_slots[1].r_issuing_cnt_reg[8]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 25 downto 0 );
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in_0 : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 68 downto 35 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_6\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__3\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_valid_i_i_1__3\ : label is "soft_lutpair45";
begin
\gen_master_slots[1].r_issuing_cnt_reg[8]\ <= \^gen_master_slots[1].r_issuing_cnt_reg[8]\;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
I1 => \^s_ready_i_reg_0\,
I2 => chosen_0(0),
I3 => s_axi_rready(0),
O => \^gen_master_slots[1].r_issuing_cnt_reg[8]\
);
\gen_master_slots[1].r_issuing_cnt[11]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => chosen_0(0),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\
);
\gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(0),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(1),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(2),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3),
I4 => \^gen_master_slots[1].r_issuing_cnt_reg[8]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
O => p_1_in_0
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(12),
Q => st_mr_rmesg(50),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(13),
Q => st_mr_rmesg(51),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(14),
Q => st_mr_rmesg(52),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(15),
Q => st_mr_rmesg(53),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(16),
Q => st_mr_rmesg(54),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(17),
Q => st_mr_rmesg(55),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(18),
Q => st_mr_rmesg(56),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(1),
Q => st_mr_rmesg(39),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(21),
Q => st_mr_rmesg(59),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(23),
Q => st_mr_rmesg(61),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(24),
Q => st_mr_rmesg(62),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(25),
Q => st_mr_rmesg(63),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(26),
Q => st_mr_rmesg(64),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(28),
Q => st_mr_rmesg(66),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(29),
Q => st_mr_rmesg(67),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(2),
Q => st_mr_rmesg(40),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(30),
Q => st_mr_rmesg(68),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(32),
Q => st_mr_rmesg(35),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(3),
Q => st_mr_rmesg(41),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(5),
Q => st_mr_rmesg(43),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(7),
Q => st_mr_rmesg(45),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF2AFFFF"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
I3 => m_axi_rvalid(0),
I4 => \^m_axi_rready[1]\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(50),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(5),
O => s_axi_rdata(5)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(51),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(6),
O => s_axi_rdata(6)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(52),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(7),
O => s_axi_rdata(7)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(53),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(8),
O => s_axi_rdata(8)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(54),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(9),
O => s_axi_rdata(9)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(55),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(10),
O => s_axi_rdata(10)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(56),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(11),
O => s_axi_rdata(11)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(39),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(0),
O => s_axi_rdata(0)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(59),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(12),
O => s_axi_rdata(12)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(61),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(13),
O => s_axi_rdata(13)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(62),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(14),
O => s_axi_rdata(14)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(63),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(15),
O => s_axi_rdata(15)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(64),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(16),
O => s_axi_rdata(16)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(66),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(17),
O => s_axi_rdata(17)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(67),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(18),
O => s_axi_rdata(18)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(40),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(1),
O => s_axi_rdata(1)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(68),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(19),
O => s_axi_rdata(19)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(41),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(2),
O => s_axi_rdata(2)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(43),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(3),
O => s_axi_rdata(3)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(45),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(4),
O => s_axi_rdata(4)
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFFACCCACCCACCC"
)
port map (
I0 => st_mr_rmesg(35),
I1 => \m_payload_i_reg[32]_0\(20),
I2 => \^s_ready_i_reg_0\,
I3 => chosen_0(0),
I4 => p_32_out,
I5 => chosen_0(1),
O => s_axi_rresp(0)
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F4F4F"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \^m_axi_rready[1]\,
I2 => \^s_ready_i_reg_0\,
I3 => s_axi_rready(0),
I4 => chosen_0(0),
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is
signal \^gen_master_slots[0].r_issuing_cnt_reg[0]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair39";
begin
\gen_master_slots[0].r_issuing_cnt_reg[0]\ <= \^gen_master_slots[0].r_issuing_cnt_reg[0]\;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => s_axi_rready(0),
I2 => \^m_valid_i_reg_0\,
I3 => chosen_0(0),
O => \^gen_master_slots[0].r_issuing_cnt_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => Q(2),
I3 => Q(3),
I4 => \^gen_master_slots[0].r_issuing_cnt_reg[0]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4CFFFF"
)
port map (
I0 => chosen_0(0),
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_rready(0),
I3 => m_axi_rvalid(0),
I4 => \^m_axi_rready[0]\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FF44FF"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \^m_axi_rready[0]\,
I2 => chosen_0(0),
I3 => \^m_valid_i_reg_0\,
I4 => s_axi_rready(0),
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[2]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
st_aa_artarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
chosen : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC;
\s_axi_araddr[25]_0\ : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
\s_axi_araddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
p_74_out : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_54_out : in STD_LOGIC;
p_32_out : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor : entity is "axi_crossbar_v2_1_14_si_transactor";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor is
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst_n_0\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_1\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_20\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_21\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_22\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_23\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_24\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_25\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_26\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_27\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_28\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_29\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_30\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_31\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_32\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_33\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_34\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_35\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_36\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_37\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_38\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_39\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_40\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_41\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_42\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_43\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_44\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_45\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_46\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_47\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_48\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_49\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_50\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_51\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_6\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_7\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_8\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal \^st_aa_artarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1__0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1__0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_24__0\ : label is "soft_lutpair99";
begin
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\;
m_valid_i <= \^m_valid_i\;
st_aa_artarget_hot(0) <= \^st_aa_artarget_hot\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I1 => \s_axi_araddr[31]\(7),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(6),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I3 => \s_axi_araddr[31]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_araddr[31]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I3 => \s_axi_araddr[31]\(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I5 => \s_axi_araddr[31]\(6),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(3),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I3 => \s_axi_araddr[31]\(5),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I5 => \s_axi_araddr[31]\(4),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(0),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I3 => \s_axi_araddr[31]\(2),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I5 => \s_axi_araddr[31]\(1),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I1 => \s_axi_araddr[31]\(7),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(6),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I1 => \s_axi_araddr[31]\(10),
I2 => \s_axi_araddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
I4 => \s_axi_araddr[31]\(9),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(7),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(5),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
I2 => \s_axi_araddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I5 => \s_axi_araddr[31]\(4),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
I4 => \s_axi_araddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(7),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I1 => \s_axi_araddr[31]\(10),
I2 => \s_axi_araddr[31]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_2\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_1\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5
port map (
CO(0) => p_8_out,
D(2) => \gen_multi_thread.arbiter_resp_inst_n_0\,
D(1) => \gen_multi_thread.arbiter_resp_inst_n_1\,
D(0) => \gen_multi_thread.arbiter_resp_inst_n_2\,
E(0) => \gen_multi_thread.arbiter_resp_inst_n_4\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\,
SR(0) => SR(0),
aclk => aclk,
\chosen_reg[1]_0\ => chosen(1),
cmd_push_0 => cmd_push_0,
cmd_push_3 => cmd_push_3,
\gen_multi_thread.accept_cnt_reg[2]\ => \gen_multi_thread.accept_cnt_reg[2]_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_24\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_25\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_26\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_27\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_9\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_28\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_29\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_30\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_31\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3) => \gen_multi_thread.arbiter_resp_inst_n_32\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2) => \gen_multi_thread.arbiter_resp_inst_n_33\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1) => \gen_multi_thread.arbiter_resp_inst_n_34\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_35\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_8\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_36\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_37\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_38\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_7\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_40\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_41\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_42\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_43\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_6\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_44\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_45\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_46\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_47\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.arbiter_resp_inst_n_5\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_48\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_49\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_50\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_51\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]_1\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_2\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_3\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_4\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_5\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[0]_0\ => chosen(0),
\m_payload_i_reg[34]\ => chosen(2),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[46]\(25 downto 0) => \m_payload_i_reg[46]\(25 downto 0),
\m_payload_i_reg[46]_0\(25 downto 0) => \m_payload_i_reg[46]_0\(25 downto 0),
\m_payload_i_reg[46]_1\(12 downto 0) => \m_payload_i_reg[46]_1\(12 downto 0),
p_32_out => p_32_out,
p_54_out => p_54_out,
p_74_out => p_74_out,
s_axi_rdata(11 downto 0) => s_axi_rdata(11 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid(0) => s_axi_rvalid(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => cmd_push_0,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(3),
I1 => active_cnt(2),
I2 => cmd_push_0,
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000F0088888888"
)
port map (
I0 => aid_match_00,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA8FFFFFFFF"
)
port map (
I0 => aid_match_30,
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => active_cnt(27),
I4 => active_cnt(26),
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^st_aa_artarget_hot\(0),
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(8),
I2 => active_cnt(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(11),
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF55FF55CF55FF55"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
I1 => active_cnt(8),
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"3B080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I4 => aid_match_10,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^st_aa_artarget_hot\(0),
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
I1 => active_cnt(16),
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(16),
I2 => active_cnt(17),
I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(19),
I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF77FF77F077FF77"
)
port map (
I0 => aid_match_20,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^st_aa_artarget_hot\(0),
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => cmd_push_3,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(27),
I1 => active_cnt(26),
I2 => cmd_push_3,
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
I4 => aid_match_00,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_60,
I1 => active_cnt(49),
I2 => active_cnt(48),
I3 => active_cnt(50),
I4 => active_cnt(51),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => aid_match_20,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A0A0A3A0A0A0A"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
I1 => active_cnt(26),
I2 => active_cnt(27),
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => aid_match_30,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => aid_match_10,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_70,
I1 => active_cnt(57),
I2 => active_cnt(56),
I3 => active_cnt(58),
I4 => active_cnt(59),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_40,
I1 => active_cnt(33),
I2 => active_cnt(32),
I3 => active_cnt(34),
I4 => active_cnt(35),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => aid_match_50,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^st_aa_artarget_hot\(0),
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
I1 => active_cnt(32),
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(32),
I2 => active_cnt(33),
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(35),
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(35),
I1 => active_cnt(34),
I2 => active_cnt(32),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545FFFFFFEFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I5 => aid_match_40,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^st_aa_artarget_hot\(0),
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
I1 => active_cnt(40),
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(40),
I2 => active_cnt(41),
I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(43),
I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF77FF77F077FF77"
)
port map (
I0 => aid_match_50,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABFFFFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => active_cnt(27),
I4 => active_cnt(26),
I5 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^st_aa_artarget_hot\(0),
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
I1 => active_cnt(48),
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(48),
I2 => active_cnt(49),
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(51),
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
I2 => active_cnt(49),
I3 => active_cnt(48),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(51),
I1 => active_cnt(50),
I2 => active_cnt(48),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555545555555"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA800000000"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => active_cnt(51),
I2 => active_cnt(50),
I3 => active_cnt(48),
I4 => active_cnt(49),
I5 => aid_match_60,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I1 => active_cnt(51),
I2 => active_cnt(50),
I3 => active_cnt(48),
I4 => active_cnt(49),
I5 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^st_aa_artarget_hot\(0),
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
I1 => active_cnt(56),
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(56),
I2 => active_cnt(57),
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(59),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(59),
I1 => active_cnt(58),
I2 => active_cnt(56),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => \s_axi_araddr[31]\(17),
I1 => \s_axi_araddr[31]\(20),
I2 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\,
I3 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\,
I4 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\,
O => \^st_aa_artarget_hot\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_araddr[31]\(13),
I1 => \s_axi_araddr[31]\(22),
I2 => \s_axi_araddr[31]\(15),
I3 => \s_axi_araddr[31]\(12),
I4 => \s_axi_araddr[31]\(14),
I5 => \s_axi_araddr[31]\(26),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_araddr[31]\(25),
I1 => \s_axi_araddr[31]\(27),
I2 => \s_axi_araddr[31]\(23),
I3 => \s_axi_araddr[31]\(24),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_araddr[31]\(18),
I1 => \s_axi_araddr[31]\(19),
I2 => \s_axi_araddr[31]\(16),
I3 => \s_axi_araddr[31]\(21),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_araddr[25]_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF5555CFFF5555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^st_aa_artarget_hot\(0),
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(57),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F40"
)
port map (
I0 => \s_axi_araddr[25]_0\,
I1 => \^m_valid_i\,
I2 => aresetn_d,
I3 => \gen_no_arbiter.m_target_hot_i_reg[2]_0\(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDDFFFD"
)
port map (
I0 => aid_match_30,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(25),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"88880008"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(49),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"22220002"
)
port map (
I0 => aid_match_50,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(41),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"40FF404040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I1 => aid_match_10,
I2 => active_target(8),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I4 => aid_match_00,
I5 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I1 => aid_match_50,
I2 => active_target(40),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I4 => aid_match_10,
I5 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010101010FF1010"
)
port map (
I0 => active_target(16),
I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I2 => aid_match_20,
I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I4 => aid_match_30,
I5 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAAA8"
)
port map (
I0 => aid_match_00,
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => active_cnt(3),
I4 => active_cnt(2),
I5 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => active_target(48),
I3 => aid_match_40,
I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I5 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F1000000"
)
port map (
I0 => active_target(33),
I1 => \s_axi_araddr[25]\(0),
I2 => active_target(32),
I3 => aid_match_40,
I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I5 => \^st_aa_artarget_hot\(0),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => active_target(49),
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => aid_match_20,
I5 => active_target(17),
O => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F007F7F7F7F7F7F"
)
port map (
I0 => active_target(33),
I1 => aid_match_40,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I4 => aid_match_50,
I5 => active_target(41),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(57),
I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I4 => aid_match_30,
I5 => active_target(25),
O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"40FF404040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I1 => aid_match_10,
I2 => active_target(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I4 => aid_match_00,
I5 => active_target(1),
O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(3),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
I3 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000002F2"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
I2 => \^st_aa_artarget_hot\(0),
I3 => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I5 => \gen_no_arbiter.m_valid_i_reg\,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000E00"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \s_axi_araddr[25]\(0),
I2 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000111F"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I1 => active_target(9),
I2 => active_target(1),
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I4 => \s_axi_araddr[25]\(0),
I5 => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEEEF"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I3 => active_target(56),
I4 => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFAAAAAAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\,
I5 => \s_axi_araddr[25]_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7F7F700F7F7F7F7"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(57),
I3 => active_target(17),
I4 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I5 => aid_match_20,
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(56),
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => aid_match_20,
I5 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_48\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_49\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_50\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_51\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_28\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_29\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_30\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_31\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_24\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_25\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_26\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_27\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_44\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_45\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_46\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_47\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_40\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_41\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_42\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_43\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_36\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_37\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_38\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_39\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_32\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_33\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_34\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_35\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC;
chosen : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
st_aa_awtarget_enc : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
p_80_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : in STD_LOGIC;
\s_axi_awaddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[2]\ : in STD_LOGIC;
\m_payload_i_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
\m_payload_i_reg[7]\ : in STD_LOGIC;
\m_payload_i_reg[12]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC;
\m_payload_i_reg[13]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_38_out : in STD_LOGIC;
p_60_out : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_13\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_14\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_15\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_16\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_17\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_3\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_16_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_i_1_n_0 : STD_LOGIC;
signal p_10_out_carry_i_3_n_0 : STD_LOGIC;
signal p_10_out_carry_i_4_n_0 : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_i_1_n_0 : STD_LOGIC;
signal p_12_out_carry_i_3_n_0 : STD_LOGIC;
signal p_12_out_carry_i_4_n_0 : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_i_1_n_0 : STD_LOGIC;
signal p_14_out_carry_i_3_n_0 : STD_LOGIC;
signal p_14_out_carry_i_4_n_0 : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_i_1_n_0 : STD_LOGIC;
signal p_2_out_carry_i_3_n_0 : STD_LOGIC;
signal p_2_out_carry_i_4_n_0 : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_i_1_n_0 : STD_LOGIC;
signal p_4_out_carry_i_3_n_0 : STD_LOGIC;
signal p_4_out_carry_i_4_n_0 : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_i_1_n_0 : STD_LOGIC;
signal p_6_out_carry_i_3_n_0 : STD_LOGIC;
signal p_6_out_carry_i_4_n_0 : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_i_1_n_0 : STD_LOGIC;
signal p_8_out_carry_i_3_n_0 : STD_LOGIC;
signal p_8_out_carry_i_4_n_0 : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal \^st_aa_awtarget_enc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_12\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_8__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_9__0\ : label is "soft_lutpair140";
begin
D(0) <= \^d\(0);
Q(2 downto 0) <= \^q\(2 downto 0);
SR(0) <= \^sr\(0);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\;
st_aa_awtarget_enc(0) <= \^st_aa_awtarget_enc\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(7),
I3 => \^q\(1),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^q\(2),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awaddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(9),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I3 => \s_axi_awaddr[31]\(10),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awaddr[31]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(6),
I1 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0),
I2 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2),
I3 => \s_axi_awaddr[31]\(8),
I4 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1),
I5 => \s_axi_awaddr[31]\(7),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(3),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I3 => \s_axi_awaddr[31]\(4),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awaddr[31]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(0),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I3 => \s_axi_awaddr[31]\(2),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I5 => \s_axi_awaddr[31]\(1),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2),
I4 => \s_axi_awaddr[31]\(6),
I5 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I1 => \s_axi_awaddr[31]\(10),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(9),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(7),
I3 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I1 => \s_axi_awaddr[31]\(3),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(6),
I3 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awaddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I1 => \s_axi_awaddr[31]\(10),
I2 => \s_axi_awaddr[31]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2),
I4 => \s_axi_awaddr[31]\(6),
I5 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2),
I4 => \s_axi_awaddr[31]\(7),
I5 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I1 => \s_axi_awaddr[31]\(3),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(6),
I3 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_4\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_3\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_2\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
port map (
CO(0) => p_0_out,
D(2) => \gen_multi_thread.arbiter_resp_inst_n_2\,
D(1) => \gen_multi_thread.arbiter_resp_inst_n_3\,
D(0) => \gen_multi_thread.arbiter_resp_inst_n_4\,
E(0) => \gen_multi_thread.arbiter_resp_inst_n_9\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
SR(0) => \^sr\(0),
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[0]_0\ => chosen(0),
\chosen_reg[1]_0\ => chosen(1),
cmd_push_0 => cmd_push_0,
cmd_push_3 => cmd_push_3,
\gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_master_slots[0].w_issuing_cnt_reg[1]\,
\gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].w_issuing_cnt_reg[10]\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_master_slots[1].w_issuing_cnt_reg[8]\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => chosen(2),
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].w_issuing_cnt_reg[16]\,
\gen_master_slots[2].w_issuing_cnt_reg[16]_1\ => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_17\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_16\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_15\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_14\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_13\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
\m_ready_d_reg[1]_0\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
\m_ready_d_reg[1]_1\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
\m_ready_d_reg[1]_2\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
\m_ready_d_reg[1]_3\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
\m_ready_d_reg[1]_4\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
\m_ready_d_reg[1]_5\ => \m_ready_d_reg[1]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
p_38_out => p_38_out,
p_60_out => p_60_out,
p_80_out => p_80_out,
\s_axi_awaddr[26]\(0) => \^st_aa_awtarget_enc\(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(4 downto 0) => w_issuing_cnt(4 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => cmd_push_0,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(3),
I1 => active_cnt(2),
I2 => cmd_push_0,
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(6),
Q => \^q\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(7),
Q => \^q\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(8),
Q => \^q\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0500050035300500"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => aid_match_00,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_40,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => aid_match_50,
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(8),
I2 => active_cnt(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(11),
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBBFFBBF0BBFFBB"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => aid_match_10,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
I1 => active_cnt(8),
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08083B08"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
I1 => active_cnt(16),
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(16),
I2 => active_cnt(17),
I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(19),
I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDDFFDDF0DDFFDD"
)
port map (
I0 => aid_match_20,
I1 => \m_ready_d_reg[1]\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => cmd_push_3,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(27),
I1 => active_cnt(26),
I2 => cmd_push_3,
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"004400440F440044"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => aid_match_30,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEFFF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => aid_match_20,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_10,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_30,
I1 => active_cnt(26),
I2 => active_cnt(27),
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
I1 => active_cnt(32),
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(32),
I2 => active_cnt(33),
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(35),
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFAFAFAFAFACAFAF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_00,
I1 => active_cnt(2),
I2 => active_cnt(3),
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
I1 => active_cnt(40),
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(40),
I2 => active_cnt(41),
I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(43),
I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAFFFFFACAFFCF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\,
I4 => aid_match_50,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
I1 => active_cnt(48),
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(48),
I2 => active_cnt(49),
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(51),
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
I2 => active_cnt(49),
I3 => active_cnt(48),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(51),
I1 => active_cnt(50),
I2 => active_cnt(48),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEE0EEEE"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_60,
I1 => active_cnt(49),
I2 => active_cnt(48),
I3 => active_cnt(50),
I4 => active_cnt(51),
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => active_cnt(48),
I5 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
I1 => active_cnt(56),
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(56),
I2 => active_cnt(57),
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(59),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\,
I1 => \s_axi_awaddr[31]\(17),
I2 => \s_axi_awaddr[31]\(20),
O => \^st_aa_awtarget_enc\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\,
I1 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\,
I2 => \s_axi_awaddr[31]\(19),
I3 => \s_axi_awaddr[31]\(15),
I4 => \s_axi_awaddr[31]\(12),
I5 => \s_axi_awaddr[31]\(23),
O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_awaddr[31]\(14),
I1 => \s_axi_awaddr[31]\(25),
I2 => \s_axi_awaddr[31]\(21),
I3 => \s_axi_awaddr[31]\(22),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \s_axi_awaddr[31]\(24),
I1 => \s_axi_awaddr[31]\(27),
I2 => \s_axi_awaddr[31]\(13),
I3 => \s_axi_awaddr[31]\(26),
I4 => \s_axi_awaddr[31]\(18),
I5 => \s_axi_awaddr[31]\(16),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^st_aa_awtarget_enc\(0),
I1 => st_aa_awtarget_hot(0),
O => \^d\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000FFEF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => active_cnt(58),
I3 => active_cnt(59),
I4 => active_cnt(57),
I5 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_70,
I1 => active_cnt(58),
I2 => active_cnt(59),
I3 => active_cnt(57),
I4 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(57),
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F100"
)
port map (
I0 => active_target(41),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(40),
I3 => aid_match_50,
I4 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"22220002"
)
port map (
I0 => aid_match_20,
I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I2 => active_target(17),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(56),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(57),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(8),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(9),
O => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44440004"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I1 => aid_match_00,
I2 => active_target(1),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44440004"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I1 => aid_match_30,
I2 => active_target(25),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => active_target(32),
I1 => aid_match_40,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
I3 => active_target(8),
I4 => aid_match_10,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFB00FBFB"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I1 => aid_match_50,
I2 => active_target(40),
I3 => active_target(24),
I4 => aid_match_30,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I1 => aid_match_20,
I2 => active_target(16),
I3 => active_target(0),
I4 => aid_match_00,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
I5 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040FF4040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I1 => aid_match_20,
I2 => active_target(17),
I3 => aid_match_00,
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I5 => active_target(1),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020FF2020202020"
)
port map (
I0 => aid_match_40,
I1 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
I2 => active_target(33),
I3 => aid_match_70,
I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\,
I5 => active_target(57),
O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDF00DFDFDFDFDF"
)
port map (
I0 => active_target(41),
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => aid_match_50,
I3 => aid_match_10,
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I5 => active_target(9),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080FF8080808080"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
I2 => active_target(49),
I3 => aid_match_30,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I5 => active_target(25),
O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(1),
I2 => \gen_multi_thread.accept_cnt_reg\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000DDD0"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF22F2"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004040400"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I4 => active_target(48),
I5 => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEE0EEEE"
)
port map (
I0 => st_aa_awtarget_hot(0),
I1 => \^st_aa_awtarget_enc\(0),
I2 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(32),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(33),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(48),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(49),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => \i__carry_i_1_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => \i__carry_i_4_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry_i_1_n_0\,
S(2) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0),
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_10_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0),
S(1) => p_10_out_carry_i_3_n_0,
S(0) => p_10_out_carry_i_4_n_0
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_10_out_carry_i_1_n_0
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_10_out_carry_i_3_n_0
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_10_out_carry_i_4_n_0
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_12_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0),
S(1) => p_12_out_carry_i_3_n_0,
S(0) => p_12_out_carry_i_4_n_0
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_12_out_carry_i_1_n_0
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_12_out_carry_i_3_n_0
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_12_out_carry_i_4_n_0
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_14_out_carry_i_1_n_0,
S(2) => S(0),
S(1) => p_14_out_carry_i_3_n_0,
S(0) => p_14_out_carry_i_4_n_0
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_14_out_carry_i_1_n_0
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_14_out_carry_i_3_n_0
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_14_out_carry_i_4_n_0
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_2_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0),
S(1) => p_2_out_carry_i_3_n_0,
S(0) => p_2_out_carry_i_4_n_0
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_2_out_carry_i_1_n_0
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_2_out_carry_i_3_n_0
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_2_out_carry_i_4_n_0
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_4_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0),
S(1) => p_4_out_carry_i_3_n_0,
S(0) => p_4_out_carry_i_4_n_0
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_4_out_carry_i_1_n_0
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_4_out_carry_i_3_n_0
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_4_out_carry_i_4_n_0
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_6_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0),
S(1) => p_6_out_carry_i_3_n_0,
S(0) => p_6_out_carry_i_4_n_0
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_6_out_carry_i_1_n_0
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_6_out_carry_i_3_n_0
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_6_out_carry_i_4_n_0
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_8_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0),
S(1) => p_8_out_carry_i_3_n_0,
S(0) => p_8_out_carry_i_4_n_0
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_8_out_carry_i_1_n_0
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_8_out_carry_i_3_n_0
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_8_out_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
s_ready_i_reg_0 : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_axi.write_cs_reg[1]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo : entity is "axi_data_fifo_v2_1_12_axic_reg_srl_fifo";
end zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_1\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_2\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_3\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_valid_i : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \storage_data1[0]_i_1_n_0\ : STD_LOGIC;
signal \storage_data1_reg_n_0_[0]\ : STD_LOGIC;
signal \storage_data1_reg_n_0_[1]\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair142";
begin
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\/FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40440000"
)
port map (
I0 => p_9_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => m_ready_d(0),
I3 => s_axi_awvalid(0),
I4 => p_0_in8_in,
O => \/FSM_onehot_state[0]_i_1_n_0\
);
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\/FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002A22"
)
port map (
I0 => p_0_in8_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => m_ready_d(0),
I3 => s_axi_awvalid(0),
I4 => p_9_in,
O => \/FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i
);
\FSM_onehot_state[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => fifoaddr(1),
I1 => fifoaddr(0),
I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I5 => fifoaddr(2),
O => p_0_in5_out
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => \gen_axi.write_cs_reg[1]_0\(0),
I3 => s_axi_wlast(0),
I4 => s_axi_wvalid(0),
I5 => m_avalid,
O => \gen_axi.write_cs_reg[1]\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C133DDFF3ECC2200"
)
port map (
I0 => p_0_in8_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \^s_ready_i_reg_0\,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFD5402A"
)
port map (
I0 => fifoaddr(0),
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
I3 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFFF77710000888"
)
port map (
I0 => fifoaddr(0),
I1 => fifoaddr(1),
I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
push => push,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
\gen_rep[0].fifoaddr_reg[0]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
load_s1 => load_s1,
m_avalid => m_avalid,
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_ready_d(0) => m_ready_d(0),
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_14_in => p_14_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
s_ready_i_reg_0 => \^s_ready_i_reg_0\,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
\storage_data1_reg[0]\ => \storage_data1_reg_n_0_[0]\,
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
\storage_data1_reg[1]_0\ => \storage_data1_reg_n_0_[1]\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => m_avalid,
I3 => s_axi_wvalid(0),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => m_avalid,
I3 => s_axi_wvalid(0),
O => m_axi_wvalid(1)
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => m_valid_i_i_1_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A8A008A0A800080"
)
port map (
I0 => m_avalid,
I1 => m_axi_wready(1),
I2 => \storage_data1_reg_n_0_[0]\,
I3 => \storage_data1_reg_n_0_[1]\,
I4 => p_14_in,
I5 => m_axi_wready(0),
O => s_axi_wready(0)
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFFAAAAAAAA"
)
port map (
I0 => s_ready_i_i_2_n_0,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => fifoaddr(2),
I5 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => areset_d1,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^s_ready_i_reg_0\,
R => SR(0)
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => st_aa_awtarget_enc(0),
I3 => load_s1,
I4 => \storage_data1_reg_n_0_[0]\,
O => \storage_data1[0]_i_1_n_0\
);
\storage_data1[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888FFC88888"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => p_0_in8_in,
I3 => p_9_in,
I4 => s_axi_awvalid(0),
I5 => m_ready_d(0),
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \storage_data1[0]_i_1_n_0\,
Q => \storage_data1_reg_n_0_[0]\,
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
Q => \storage_data1_reg_n_0_[1]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_80_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_74_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\
port map (
D(13 downto 0) => D(13 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
chosen(0) => chosen(0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_80_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\
port map (
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
chosen_0(0) => chosen_0(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_74_out,
p_1_in => p_1_in,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_60_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_54_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[12]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_38_out : in STD_LOGIC;
\m_payload_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[32]\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
p_32_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\
port map (
D(13 downto 0) => D(13 downto 0),
Q(3 downto 0) => Q(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
chosen(1 downto 0) => chosen(1 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_multi_thread.accept_cnt_reg[3]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_60_out,
\m_payload_i_reg[12]_0\(9 downto 0) => \m_payload_i_reg[12]\(9 downto 0),
\m_payload_i_reg[1]_0\(1 downto 0) => \m_payload_i_reg[1]\(1 downto 0),
p_1_in => \^p_1_in\,
p_38_out => p_38_out,
s_axi_bid(4 downto 0) => s_axi_bid(4 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\
port map (
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
chosen_0(1 downto 0) => chosen_0(1 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].r_issuing_cnt_reg[11]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
\m_payload_i_reg[32]_0\(20 downto 0) => \m_payload_i_reg[32]\(20 downto 0),
p_1_in => \^p_1_in\,
p_32_out => p_32_out,
s_axi_rdata(19 downto 0) => s_axi_rdata(19 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0),
s_ready_i_reg_0 => p_54_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_38_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_2 : out STD_LOGIC;
p_32_out : out STD_LOGIC;
mi_rready_2 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_21_in : in STD_LOGIC;
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[13]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_17_in : in STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(4 downto 0) => Q(4 downto 0),
S(0) => S(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
chosen(0) => chosen(0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0),
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0),
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0),
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0),
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0),
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0),
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
\m_payload_i_reg[13]_0\(13 downto 0) => \m_payload_i_reg[13]\(13 downto 0),
\m_payload_i_reg[2]_0\ => p_38_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
m_valid_i_reg_1 => m_valid_i_reg_0,
mi_bready_2 => mi_bready_2,
p_1_in => p_1_in,
p_21_in => p_21_in,
s_axi_bid(6 downto 0) => s_axi_bid(6 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg,
w_issuing_cnt(0) => w_issuing_cnt(0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
chosen_0(0) => chosen_0(0),
\gen_axi.s_axi_arready_i_reg\ => \gen_axi.s_axi_arready_i_reg\,
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_valid_i_reg_0 => p_32_out,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
r_issuing_cnt(0) => r_issuing_cnt(0),
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_2,
st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_axi.write_cs_reg[1]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router : entity is "axi_crossbar_v2_1_14_wdata_router";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(0) => D(0),
SR(0) => SR(0),
aclk => aclk,
\gen_axi.write_cs_reg[1]\ => \gen_axi.write_cs_reg[1]\,
\gen_axi.write_cs_reg[1]_0\(0) => \gen_axi.write_cs_reg[1]_0\(0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
m_ready_d(0) => m_ready_d(0),
p_14_in => p_14_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg_0 => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
aresetn : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 56 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 56 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar : entity is "axi_crossbar_v2_1_14_crossbar";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 2 to 2 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_2 : STD_LOGIC;
signal addr_arbiter_ar_n_3 : STD_LOGIC;
signal addr_arbiter_ar_n_4 : STD_LOGIC;
signal addr_arbiter_ar_n_5 : STD_LOGIC;
signal addr_arbiter_ar_n_6 : STD_LOGIC;
signal addr_arbiter_ar_n_7 : STD_LOGIC;
signal addr_arbiter_ar_n_80 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_aw_n_10 : STD_LOGIC;
signal addr_arbiter_aw_n_11 : STD_LOGIC;
signal addr_arbiter_aw_n_12 : STD_LOGIC;
signal addr_arbiter_aw_n_13 : STD_LOGIC;
signal addr_arbiter_aw_n_14 : STD_LOGIC;
signal addr_arbiter_aw_n_15 : STD_LOGIC;
signal addr_arbiter_aw_n_16 : STD_LOGIC;
signal addr_arbiter_aw_n_2 : STD_LOGIC;
signal addr_arbiter_aw_n_20 : STD_LOGIC;
signal addr_arbiter_aw_n_21 : STD_LOGIC;
signal addr_arbiter_aw_n_3 : STD_LOGIC;
signal addr_arbiter_aw_n_7 : STD_LOGIC;
signal addr_arbiter_aw_n_8 : STD_LOGIC;
signal addr_arbiter_aw_n_9 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_decerr_slave.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_12\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_20\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_21\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_22\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_23\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_26\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_27\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_75\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_76\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_13\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_19\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_20\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_21\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_22\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_23\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_24\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_25\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_26\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_27\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_28\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_29\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_30\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_31\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_45\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\ : STD_LOGIC;
signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_3 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_2 : STD_LOGIC;
signal mi_arready_2 : STD_LOGIC;
signal mi_awready_2 : STD_LOGIC;
signal mi_bready_2 : STD_LOGIC;
signal mi_rready_2 : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_21_in : STD_LOGIC;
signal p_24_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_32_out : STD_LOGIC;
signal p_34_out : STD_LOGIC;
signal p_38_out : STD_LOGIC;
signal p_54_out : STD_LOGIC;
signal p_56_out : STD_LOGIC;
signal p_60_out : STD_LOGIC;
signal p_74_out : STD_LOGIC;
signal p_76_out : STD_LOGIC;
signal p_80_out : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 0 to 0 );
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 34 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 35 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 69 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 );
signal write_cs : STD_LOGIC_VECTOR ( 1 to 1 );
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0);
addr_arbiter_ar: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
port map (
D(2) => addr_arbiter_ar_n_2,
D(1) => addr_arbiter_ar_n_3,
D(0) => addr_arbiter_ar_n_4,
E(0) => s_axi_rvalid_i,
Q(0) => p_56_out,
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\,
aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\,
\chosen_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\,
\gen_axi.read_cnt_reg[5]\ => \gen_decerr_slave.decerr_slave_inst_n_7\,
\gen_axi.s_axi_rid_i_reg[11]\(0) => aa_mi_artarget_hot(2),
\gen_master_slots[0].r_issuing_cnt_reg[0]\(0) => addr_arbiter_ar_n_84,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_5,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_6,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_7,
\gen_master_slots[1].r_issuing_cnt_reg[8]\(0) => addr_arbiter_ar_n_85,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_31\,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ => addr_arbiter_ar_n_82,
\gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) => st_aa_artarget_hot(0),
\gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_ar_n_80,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_ar_n_81,
\m_axi_arqos[7]\(68 downto 0) => \^m_axi_arqos[7]\(68 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
\m_payload_i_reg[34]\ => \gen_master_slots[0].reg_slice_mi_n_5\,
\m_payload_i_reg[34]_0\ => \gen_master_slots[1].reg_slice_mi_n_27\,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_75\,
mi_arready_2 => mi_arready_2,
p_15_in => p_15_in,
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\s_axi_araddr[25]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\,
\s_axi_araddr[28]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\s_axi_araddr[30]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
\s_axi_arqos[3]\(68 downto 12) => \s_axi_arqos[3]\(56 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
\s_axi_arready[0]\ => \^s_axi_arready\(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rlast_i0 => s_axi_rlast_i0,
s_axi_rready(0) => s_axi_rready(0),
st_aa_artarget_hot(0) => st_aa_artarget_hot(1)
);
addr_arbiter_aw: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
D(2) => addr_arbiter_aw_n_7,
D(1) => addr_arbiter_aw_n_8,
D(0) => addr_arbiter_aw_n_9,
E(0) => addr_arbiter_aw_n_15,
Q(68 downto 0) => \^q\(68 downto 0),
SR(0) => reset,
aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\,
aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\,
\chosen_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
\chosen_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => addr_arbiter_aw_n_16,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => addr_arbiter_aw_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => addr_arbiter_aw_n_12,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => addr_arbiter_aw_n_13,
\gen_master_slots[1].w_issuing_cnt_reg[9]\ => addr_arbiter_aw_n_10,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => addr_arbiter_aw_n_14,
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ => addr_arbiter_aw_n_20,
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
\m_ready_d_reg[0]\ => addr_arbiter_aw_n_2,
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_3,
\m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_21,
m_valid_i => m_valid_i_2,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\,
mi_awready_2 => mi_awready_2,
\s_axi_awaddr[20]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\,
\s_axi_awaddr[26]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\,
\s_axi_awqos[3]\(68 downto 12) => D(56 downto 0),
\s_axi_awqos[3]\(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
ss_aa_awready => ss_aa_awready,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(11 downto 0) => p_24_in(11 downto 0),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axi.s_axi_arready_i_reg_0\ => \gen_decerr_slave.decerr_slave_inst_n_7\,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[7]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[7]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\(0) => aa_mi_artarget_hot(2),
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_aw_n_10,
m_ready_d(0) => m_ready_d_3(1),
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_14,
mi_arready_2 => mi_arready_2,
mi_awready_2 => mi_awready_2,
mi_bready_2 => mi_bready_2,
mi_rready_2 => mi_rready_2,
p_14_in => p_14_in,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_21_in => p_21_in,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_20_in(11 downto 0),
\storage_data1_reg[0]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_4,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_3,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_2,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \r_pipe/p_1_in_0\,
Q(3 downto 0) => r_issuing_cnt(3 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[2].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_5\,
chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(0),
chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_5\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_76_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_1_in => p_1_in,
p_74_out => p_74_out,
p_80_out => p_80_out,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_13,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_12,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_11,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_6,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_5,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_7,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
D(13 downto 2) => m_axi_bid(23 downto 12),
D(1 downto 0) => m_axi_bresp(3 downto 2),
Q(3 downto 0) => w_issuing_cnt(11 downto 8),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[1].reg_slice_mi_n_76\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[2].reg_slice_mi_n_5\,
chosen(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 1),
chosen_0(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 1),
\gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].reg_slice_mi_n_75\,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_27\,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_6\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6) => st_mr_bid(23),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(5 downto 2) => st_mr_bid(21 downto 18),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(1) => st_mr_bid(16),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(0) => st_mr_bid(12),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[1].reg_slice_mi_n_20\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[1].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_master_slots[1].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ => \gen_master_slots[1].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 14) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13) => p_56_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12) => st_mr_rmesg(36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11) => st_mr_rmesg(69),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10) => st_mr_rmesg(65),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9) => st_mr_rmesg(60),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8 downto 7) => st_mr_rmesg(58 downto 57),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6 downto 3) => st_mr_rmesg(49 downto 46),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2) => st_mr_rmesg(44),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1) => st_mr_rmesg(42),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => st_mr_rmesg(38),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_5\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_26\,
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
\m_payload_i_reg[12]\(9) => st_mr_bid(34),
\m_payload_i_reg[12]\(8) => st_mr_bid(29),
\m_payload_i_reg[12]\(7 downto 5) => st_mr_bid(27 downto 25),
\m_payload_i_reg[12]\(4) => st_mr_bid(10),
\m_payload_i_reg[12]\(3) => st_mr_bid(5),
\m_payload_i_reg[12]\(2 downto 0) => st_mr_bid(3 downto 1),
\m_payload_i_reg[1]\(1 downto 0) => st_mr_bmesg(1 downto 0),
\m_payload_i_reg[32]\(20) => st_mr_rmesg(0),
\m_payload_i_reg[32]\(19 downto 17) => st_mr_rmesg(33 downto 31),
\m_payload_i_reg[32]\(16 downto 13) => st_mr_rmesg(29 downto 26),
\m_payload_i_reg[32]\(12) => st_mr_rmesg(24),
\m_payload_i_reg[32]\(11 downto 5) => st_mr_rmesg(21 downto 15),
\m_payload_i_reg[32]\(4) => st_mr_rmesg(10),
\m_payload_i_reg[32]\(3) => st_mr_rmesg(8),
\m_payload_i_reg[32]\(2 downto 0) => st_mr_rmesg(6 downto 4),
p_1_in => p_1_in,
p_32_out => p_32_out,
p_38_out => p_38_out,
p_54_out => p_54_out,
p_60_out => p_60_out,
s_axi_bid(4) => s_axi_bid(10),
s_axi_bid(3) => s_axi_bid(5),
s_axi_bid(2 downto 0) => s_axi_bid(3 downto 1),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_rdata(19 downto 17) => s_axi_rdata(30 downto 28),
s_axi_rdata(16 downto 13) => s_axi_rdata(26 downto 23),
s_axi_rdata(12) => s_axi_rdata(21),
s_axi_rdata(11 downto 5) => s_axi_rdata(18 downto 12),
s_axi_rdata(4) => s_axi_rdata(7),
s_axi_rdata(3) => s_axi_rdata(5),
s_axi_rdata(2 downto 0) => s_axi_rdata(3 downto 1),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_8,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_7,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_9,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_master_slots[2].reg_slice_mi_n_45\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(11 downto 0) => p_24_in(11 downto 0),
E(0) => \r_pipe/p_1_in\,
Q(4) => st_mr_bid(34),
Q(3) => st_mr_bid(29),
Q(2 downto 0) => st_mr_bid(27 downto 25),
S(0) => \gen_master_slots[2].reg_slice_mi_n_20\,
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_76\,
chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2),
chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\gen_axi.s_axi_arready_i_reg\ => addr_arbiter_ar_n_80,
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_20_in(11 downto 0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_26\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_45\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_master_slots[2].reg_slice_mi_n_19\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[2].reg_slice_mi_n_28\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[2].reg_slice_mi_n_29\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_master_slots[2].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_master_slots[2].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_master_slots[2].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_master_slots[2].reg_slice_mi_n_24\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_master_slots[2].reg_slice_mi_n_25\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_master_slots[2].reg_slice_mi_n_26\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_master_slots[2].reg_slice_mi_n_27\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 1) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => p_34_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_30\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_31\,
\m_payload_i_reg[13]\(13) => st_mr_bid(23),
\m_payload_i_reg[13]\(12 downto 9) => st_mr_bid(21 downto 18),
\m_payload_i_reg[13]\(8) => st_mr_bid(16),
\m_payload_i_reg[13]\(7 downto 6) => st_mr_bid(12 downto 11),
\m_payload_i_reg[13]\(5 downto 2) => st_mr_bid(9 downto 6),
\m_payload_i_reg[13]\(1) => st_mr_bid(4),
\m_payload_i_reg[13]\(0) => st_mr_bid(0),
m_valid_i_reg => \gen_master_slots[2].reg_slice_mi_n_1\,
m_valid_i_reg_0 => \gen_master_slots[1].reg_slice_mi_n_6\,
mi_bready_2 => mi_bready_2,
mi_rready_2 => mi_rready_2,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
p_21_in => p_21_in,
p_32_out => p_32_out,
p_38_out => p_38_out,
r_issuing_cnt(0) => r_issuing_cnt(16),
s_axi_bid(6) => s_axi_bid(11),
s_axi_bid(5 downto 2) => s_axi_bid(9 downto 6),
s_axi_bid(1) => s_axi_bid(4),
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[2].reg_slice_mi_n_5\,
st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0),
w_issuing_cnt(0) => w_issuing_cnt(16)
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor
port map (
E(0) => \r_pipe/p_1_in_0\,
SR(0) => reset,
aclk => aclk,
aresetn_d => aresetn_d,
chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 0),
\gen_multi_thread.accept_cnt_reg[2]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\,
\gen_no_arbiter.m_target_hot_i_reg[2]_0\(0) => aa_mi_artarget_hot(2),
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_ar_n_81,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => \^s_axi_arready\(0),
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[46]\(25 downto 14) => st_mr_rid(11 downto 0),
\m_payload_i_reg[46]\(13) => p_76_out,
\m_payload_i_reg[46]\(12) => st_mr_rmesg(1),
\m_payload_i_reg[46]\(11) => st_mr_rmesg(34),
\m_payload_i_reg[46]\(10) => st_mr_rmesg(30),
\m_payload_i_reg[46]\(9) => st_mr_rmesg(25),
\m_payload_i_reg[46]\(8 downto 7) => st_mr_rmesg(23 downto 22),
\m_payload_i_reg[46]\(6 downto 3) => st_mr_rmesg(14 downto 11),
\m_payload_i_reg[46]\(2) => st_mr_rmesg(9),
\m_payload_i_reg[46]\(1) => st_mr_rmesg(7),
\m_payload_i_reg[46]\(0) => st_mr_rmesg(3),
\m_payload_i_reg[46]_0\(25 downto 14) => st_mr_rid(23 downto 12),
\m_payload_i_reg[46]_0\(13) => p_56_out,
\m_payload_i_reg[46]_0\(12) => st_mr_rmesg(36),
\m_payload_i_reg[46]_0\(11) => st_mr_rmesg(69),
\m_payload_i_reg[46]_0\(10) => st_mr_rmesg(65),
\m_payload_i_reg[46]_0\(9) => st_mr_rmesg(60),
\m_payload_i_reg[46]_0\(8 downto 7) => st_mr_rmesg(58 downto 57),
\m_payload_i_reg[46]_0\(6 downto 3) => st_mr_rmesg(49 downto 46),
\m_payload_i_reg[46]_0\(2) => st_mr_rmesg(44),
\m_payload_i_reg[46]_0\(1) => st_mr_rmesg(42),
\m_payload_i_reg[46]_0\(0) => st_mr_rmesg(38),
\m_payload_i_reg[46]_1\(12 downto 1) => st_mr_rid(35 downto 24),
\m_payload_i_reg[46]_1\(0) => p_34_out,
m_valid_i => m_valid_i,
p_32_out => p_32_out,
p_54_out => p_54_out,
p_74_out => p_74_out,
\s_axi_araddr[25]\(0) => st_aa_artarget_hot(0),
\s_axi_araddr[25]_0\ => addr_arbiter_ar_n_82,
\s_axi_araddr[31]\(27 downto 12) => \s_axi_arqos[3]\(31 downto 16),
\s_axi_araddr[31]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_rdata(11) => s_axi_rdata(31),
s_axi_rdata(10) => s_axi_rdata(27),
s_axi_rdata(9) => s_axi_rdata(22),
s_axi_rdata(8 downto 7) => s_axi_rdata(20 downto 19),
s_axi_rdata(6 downto 3) => s_axi_rdata(11 downto 8),
s_axi_rdata(2) => s_axi_rdata(6),
s_axi_rdata(1) => s_axi_rdata(4),
s_axi_rdata(0) => s_axi_rdata(0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(1),
s_axi_rvalid(0) => s_axi_rvalid(0),
st_aa_artarget_hot(0) => st_aa_artarget_hot(1)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\,
Q(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6),
S(0) => \gen_master_slots[2].reg_slice_mi_n_20\,
SR(0) => reset,
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
\gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].reg_slice_mi_n_5\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].reg_slice_mi_n_30\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_24\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_25\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_26\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_27\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_20,
\m_payload_i_reg[11]\ => \gen_master_slots[2].reg_slice_mi_n_28\,
\m_payload_i_reg[12]\ => \gen_master_slots[1].reg_slice_mi_n_23\,
\m_payload_i_reg[13]\ => \gen_master_slots[2].reg_slice_mi_n_29\,
\m_payload_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\,
\m_payload_i_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\m_payload_i_reg[4]\ => \gen_master_slots[1].reg_slice_mi_n_20\,
\m_payload_i_reg[5]\ => \gen_master_slots[1].reg_slice_mi_n_21\,
\m_payload_i_reg[6]\ => \gen_master_slots[2].reg_slice_mi_n_19\,
\m_payload_i_reg[7]\ => \gen_master_slots[1].reg_slice_mi_n_22\,
\m_ready_d_reg[1]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
\m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_14,
m_valid_i => m_valid_i_2,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\,
p_38_out => p_38_out,
p_60_out => p_60_out,
p_80_out => p_80_out,
\s_axi_awaddr[31]\(27 downto 12) => D(31 downto 16),
\s_axi_awaddr[31]\(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(4) => w_issuing_cnt(16),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router
port map (
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\,
SR(0) => reset,
aclk => aclk,
\gen_axi.write_cs_reg[1]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
m_ready_d(0) => m_ready_d(1),
p_14_in => p_14_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0)
);
splitter_aw_mi: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3
port map (
aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_target_hot_i_reg[1]\ => addr_arbiter_aw_n_3,
m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0),
\m_ready_d_reg[0]_0\ => addr_arbiter_aw_n_21,
\m_ready_d_reg[0]_1\ => addr_arbiter_aw_n_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "axi_crossbar_v2_1_14_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11";
attribute P_ONES : string;
attribute P_ONES of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 63 downto 32 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 63 downto 32 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(63 downto 32);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(63 downto 32);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(3 downto 2);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(3 downto 2);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(7 downto 4);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(7 downto 4);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(1) <= \^m_axi_arlock\(1);
m_axi_arlock(0) <= \^m_axi_arlock\(1);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(5 downto 3);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(5 downto 3);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(7 downto 4);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(7 downto 4);
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(5 downto 3);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(5 downto 3);
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(63 downto 32);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(63 downto 32);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(3 downto 2);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(3 downto 2);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(7 downto 4);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(7 downto 4);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(15 downto 8);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(15 downto 8);
m_axi_awlock(1) <= \^m_axi_awlock\(1);
m_axi_awlock(0) <= \^m_axi_awlock\(1);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(5 downto 3);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(5 downto 3);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(7 downto 4);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(7 downto 4);
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(5 downto 3);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(5 downto 3);
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar
port map (
D(56 downto 53) => s_axi_awqos(3 downto 0),
D(52 downto 49) => s_axi_awcache(3 downto 0),
D(48 downto 47) => s_axi_awburst(1 downto 0),
D(46 downto 44) => s_axi_awprot(2 downto 0),
D(43) => s_axi_awlock(0),
D(42 downto 40) => s_axi_awsize(2 downto 0),
D(39 downto 32) => s_axi_awlen(7 downto 0),
D(31 downto 0) => s_axi_awaddr(31 downto 0),
M_AXI_RREADY(1 downto 0) => m_axi_rready(1 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(7 downto 4),
Q(64 downto 61) => \^m_axi_awcache\(7 downto 4),
Q(60 downto 59) => \^m_axi_awburst\(3 downto 2),
Q(58 downto 56) => \^m_axi_awprot\(5 downto 3),
Q(55) => \^m_axi_awlock\(1),
Q(54 downto 52) => \^m_axi_awsize\(5 downto 3),
Q(51 downto 44) => \^m_axi_awlen\(15 downto 8),
Q(43 downto 12) => \^m_axi_awaddr\(63 downto 32),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[7]\(68 downto 65) => \^m_axi_arqos\(7 downto 4),
\m_axi_arqos[7]\(64 downto 61) => \^m_axi_arcache\(7 downto 4),
\m_axi_arqos[7]\(60 downto 59) => \^m_axi_arburst\(3 downto 2),
\m_axi_arqos[7]\(58 downto 56) => \^m_axi_arprot\(5 downto 3),
\m_axi_arqos[7]\(55) => \^m_axi_arlock\(1),
\m_axi_arqos[7]\(54 downto 52) => \^m_axi_arsize\(5 downto 3),
\m_axi_arqos[7]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[7]\(43 downto 12) => \^m_axi_araddr\(63 downto 32),
\m_axi_arqos[7]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0),
m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0),
m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0),
m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0),
m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0),
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
\s_axi_arqos[3]\(56 downto 53) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(52 downto 49) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(48 downto 47) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(46 downto 44) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(43) => s_axi_arlock(0),
\s_axi_arqos[3]\(42 downto 40) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(39 downto 32) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_xbar_0 : entity is "zynq_design_1_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_xbar_0 : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
end zynq_design_1_xbar_0;
architecture STRUCTURE of zynq_design_1_xbar_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "64'b0000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 2;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "2'b11";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "2'b11";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(63 downto 0) => m_axi_araddr(63 downto 0),
m_axi_arburst(3 downto 0) => m_axi_arburst(3 downto 0),
m_axi_arcache(7 downto 0) => m_axi_arcache(7 downto 0),
m_axi_arid(23 downto 0) => m_axi_arid(23 downto 0),
m_axi_arlen(15 downto 0) => m_axi_arlen(15 downto 0),
m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0),
m_axi_arprot(5 downto 0) => m_axi_arprot(5 downto 0),
m_axi_arqos(7 downto 0) => m_axi_arqos(7 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arregion(7 downto 0) => m_axi_arregion(7 downto 0),
m_axi_arsize(5 downto 0) => m_axi_arsize(5 downto 0),
m_axi_aruser(1 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
m_axi_awaddr(63 downto 0) => m_axi_awaddr(63 downto 0),
m_axi_awburst(3 downto 0) => m_axi_awburst(3 downto 0),
m_axi_awcache(7 downto 0) => m_axi_awcache(7 downto 0),
m_axi_awid(23 downto 0) => m_axi_awid(23 downto 0),
m_axi_awlen(15 downto 0) => m_axi_awlen(15 downto 0),
m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0),
m_axi_awprot(5 downto 0) => m_axi_awprot(5 downto 0),
m_axi_awqos(7 downto 0) => m_axi_awqos(7 downto 0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awregion(7 downto 0) => m_axi_awregion(7 downto 0),
m_axi_awsize(5 downto 0) => m_axi_awsize(5 downto 0),
m_axi_awuser(1 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0),
m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0),
m_axi_buser(1 downto 0) => B"00",
m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0),
m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0),
m_axi_rready(1 downto 0) => m_axi_rready(1 downto 0),
m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0),
m_axi_ruser(1 downto 0) => B"00",
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wid(23 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(23 downto 0),
m_axi_wlast(1 downto 0) => m_axi_wlast(1 downto 0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wuser(1 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.vhdl | 1 | 29735 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:31:33 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arready\ : STD_LOGIC;
signal \^m_axi_awready\ : STD_LOGIC;
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rvalid\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arvalid\ : STD_LOGIC;
signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_awvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
signal \^s_axi_rready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC;
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_arready\ <= m_axi_arready;
\^m_axi_awready\ <= m_axi_awready;
\^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0);
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_buser\(0) <= m_axi_buser(0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0);
\^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0);
\^m_axi_rlast\ <= m_axi_rlast;
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^m_axi_rvalid\ <= m_axi_rvalid;
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0);
\^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0);
\^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0);
\^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0);
\^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0);
\^s_axi_arlock\(0) <= s_axi_arlock(0);
\^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0);
\^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0);
\^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0);
\^s_axi_aruser\(0) <= s_axi_aruser(0);
\^s_axi_arvalid\ <= s_axi_arvalid;
\^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0);
\^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0);
\^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0);
\^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0);
\^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0);
\^s_axi_awlock\(0) <= s_axi_awlock(0);
\^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0);
\^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0);
\^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0);
\^s_axi_awuser\(0) <= s_axi_awuser(0);
\^s_axi_awvalid\ <= s_axi_awvalid;
\^s_axi_bready\ <= s_axi_bready;
\^s_axi_rready\ <= s_axi_rready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\ <= s_axi_wlast;
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wuser\(0) <= s_axi_wuser(0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0);
m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0);
m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0);
m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0);
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0);
m_axi_arlock(0) <= \^s_axi_arlock\(0);
m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0);
m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0);
m_axi_aruser(0) <= \^s_axi_aruser\(0);
m_axi_arvalid <= \^s_axi_arvalid\;
m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0);
m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0);
m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0);
m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0);
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0);
m_axi_awlock(0) <= \^s_axi_awlock\(0);
m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0);
m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0);
m_axi_awuser(0) <= \^s_axi_awuser\(0);
m_axi_awvalid <= \^s_axi_awvalid\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \^s_axi_rready\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \^s_axi_wlast\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \^s_axi_wuser\(0);
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_arready <= \^m_axi_arready\;
s_axi_awready <= \^m_axi_awready\;
s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0);
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_buser(0) <= \^m_axi_buser\(0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0);
s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0);
s_axi_rlast <= \^m_axi_rlast\;
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
s_axi_rvalid <= \^m_axi_rvalid\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_auto_pc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_auto_pc_1 : entity is "zynq_design_1_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_auto_pc_1 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zynq_design_1_auto_pc_1;
architecture STRUCTURE of zynq_design_1_auto_pc_1 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit |
dsaves/dsaves-hdl | primitives/buffer.vhd | 1 | 1474 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BUF is
generic (
N : NATURAL
);
port(
i : in std_logic_vector(N-1 downto 0);
o : out std_logic_vector(N-1 downto 0)
);
end entity;
architecture BUF_ARCH of BUF is
begin
o <= i;
end architecture;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-7/src/Max/MaxFinder.vhd | 1 | 2754 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity MaxFinder is
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end MaxFinder;
architecture Beh of MaxFinder is
component MROM is
port (
RE: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DOUT: out std_logic_vector(8 downto 0)
);
end component;
component MRAM is
port (
RW: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DIN: in std_logic_vector (7 downto 0);
DOUT: out std_logic_vector (7 downto 0)
);
end component;
component DPATH is
port(
EN: in std_logic;
--operation type
OT: in std_logic_vector(2 downto 0);
--operand
OP1: in std_logic_vector(7 downto 0);
RES: out std_logic_vector(7 downto 0);
--zero flag
ZF: out std_logic;
-- significant bit set flag
SBF: out std_logic
);
end component;
component CTRL1 is
port(
CLK, RST, Start: in std_logic;
Stop: out std_logic;
-- ÏÇÓ
ROM_re: out std_logic;
ROM_adr: out std_logic_vector(5 downto 0);
ROM_dout: in std_logic_vector(8 downto 0);
-- ÎÇÓ
RAM_rw: out std_logic;
RAM_adr: out std_logic_vector(5 downto 0);
RAM_din: out std_logic_vector(7 downto 0);
RAM_dout: in std_logic_vector(7 downto 0);
--datapath
DP_op1: out std_logic_vector(7 downto 0);
DP_ot: out std_logic_vector(2 downto 0);
DP_en: out std_logic;
DP_res: in std_logic_vector(7 downto 0);
DP_zf: in std_logic;
DP_sbf: in std_logic
);
end component;
signal rom_re: std_logic;
signal rom_adr: std_logic_vector(5 downto 0);
signal rom_dout: std_logic_vector(8 downto 0);
signal ram_rw: std_logic;
signal ram_adr: std_logic_vector(5 downto 0);
signal ram_din: std_logic_vector(7 downto 0);
signal ram_dout: std_logic_vector(7 downto 0);
signal dp_op1: std_logic_vector(7 downto 0);
signal dp_ot: std_logic_vector(2 downto 0);
signal dp_en: std_logic;
signal dp_res: std_logic_vector(7 downto 0);
signal dp_zf: std_logic;
signal dp_sbf: std_logic;
begin
UMRAM: entity MRAM (Beh_Max) port map(
RW => ram_rw,
ADR => ram_adr,
DIN => ram_din,
DOUT => ram_dout
);
UMROM: entity MROM (Beh_Max) port map (
RE => rom_re,
ADR => rom_adr,
DOUT => rom_dout
);
UDPATH: DPATH port map(
EN => dp_en,
OT => dp_ot,
OP1 => dp_op1,
RES => dp_res,
ZF => dp_zf,
SBF => dp_sbf
);
UCTRL1: CTRL1 port map(
CLK => CLK,
RST => RST,
START => Start,
STOP => STOP,
ROM_RE => rom_re,
ROM_ADR => rom_adr,
ROM_DOUT => rom_dout,
RAM_RW => ram_rw,
RAM_ADR => ram_adr,
RAM_DIN => ram_din,
RAM_DOUT => ram_dout,
DP_EN => dp_en,
DP_OT => dp_ot,
DP_OP1 => dp_op1,
DP_RES => dp_res,
DP_ZF => dp_zf,
DP_SBF => dp_sbf
);
end Beh;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/b73b442e1fb83bed/ip_design_nco_0_0_sim_netlist.vhdl | 1 | 97040 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:10 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_nco_0_0_sim_netlist.vhdl
-- Design : ip_design_nco_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi is
port (
s_axi_AXILiteS_RVALID : out STD_LOGIC;
ap_rst_n_inv : out STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\temp_V_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\temp_V_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\temp_V_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BVALID : out STD_LOGIC;
ap_clk : in STD_LOGIC;
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 1 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
temp_V_reg : in STD_LOGIC_VECTOR ( 15 downto 0 );
ap_rst_n : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi is
signal \^ap_rst_n_inv\ : STD_LOGIC;
signal ar_hs : STD_LOGIC;
signal int_sine_sample_V_ap_vld : STD_LOGIC;
signal int_sine_sample_V_ap_vld_i_1_n_0 : STD_LOGIC;
signal int_sine_sample_V_ap_vld_i_2_n_0 : STD_LOGIC;
signal \int_step_size_V[0]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[10]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[11]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[12]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[13]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[14]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[15]_i_2_n_0\ : STD_LOGIC;
signal \int_step_size_V[15]_i_3_n_0\ : STD_LOGIC;
signal \int_step_size_V[1]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[2]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[3]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[4]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[5]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[6]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[7]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[8]_i_1_n_0\ : STD_LOGIC;
signal \int_step_size_V[9]_i_1_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal q0_reg_0_i_10_n_0 : STD_LOGIC;
signal q0_reg_0_i_11_n_0 : STD_LOGIC;
signal q0_reg_0_i_12_n_0 : STD_LOGIC;
signal q0_reg_0_i_12_n_1 : STD_LOGIC;
signal q0_reg_0_i_12_n_2 : STD_LOGIC;
signal q0_reg_0_i_12_n_3 : STD_LOGIC;
signal q0_reg_0_i_13_n_0 : STD_LOGIC;
signal q0_reg_0_i_14_n_0 : STD_LOGIC;
signal q0_reg_0_i_15_n_0 : STD_LOGIC;
signal q0_reg_0_i_16_n_0 : STD_LOGIC;
signal q0_reg_0_i_17_n_0 : STD_LOGIC;
signal q0_reg_0_i_18_n_0 : STD_LOGIC;
signal q0_reg_0_i_19_n_0 : STD_LOGIC;
signal q0_reg_0_i_1_n_1 : STD_LOGIC;
signal q0_reg_0_i_1_n_2 : STD_LOGIC;
signal q0_reg_0_i_1_n_3 : STD_LOGIC;
signal q0_reg_0_i_20_n_0 : STD_LOGIC;
signal q0_reg_0_i_2_n_0 : STD_LOGIC;
signal q0_reg_0_i_2_n_1 : STD_LOGIC;
signal q0_reg_0_i_2_n_2 : STD_LOGIC;
signal q0_reg_0_i_2_n_3 : STD_LOGIC;
signal q0_reg_0_i_3_n_0 : STD_LOGIC;
signal q0_reg_0_i_3_n_1 : STD_LOGIC;
signal q0_reg_0_i_3_n_2 : STD_LOGIC;
signal q0_reg_0_i_3_n_3 : STD_LOGIC;
signal q0_reg_0_i_4_n_0 : STD_LOGIC;
signal q0_reg_0_i_5_n_0 : STD_LOGIC;
signal q0_reg_0_i_6_n_0 : STD_LOGIC;
signal q0_reg_0_i_7_n_0 : STD_LOGIC;
signal q0_reg_0_i_8_n_0 : STD_LOGIC;
signal q0_reg_0_i_9_n_0 : STD_LOGIC;
signal \rdata[0]_i_1_n_0\ : STD_LOGIC;
signal \rdata[0]_i_2_n_0\ : STD_LOGIC;
signal \rdata[10]_i_1_n_0\ : STD_LOGIC;
signal \rdata[11]_i_1_n_0\ : STD_LOGIC;
signal \rdata[12]_i_1_n_0\ : STD_LOGIC;
signal \rdata[13]_i_1_n_0\ : STD_LOGIC;
signal \rdata[14]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_3_n_0\ : STD_LOGIC;
signal \rdata[1]_i_1_n_0\ : STD_LOGIC;
signal \rdata[2]_i_1_n_0\ : STD_LOGIC;
signal \rdata[3]_i_1_n_0\ : STD_LOGIC;
signal \rdata[4]_i_1_n_0\ : STD_LOGIC;
signal \rdata[5]_i_1_n_0\ : STD_LOGIC;
signal \rdata[6]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_1_n_0\ : STD_LOGIC;
signal \rdata[8]_i_1_n_0\ : STD_LOGIC;
signal \rdata[9]_i_1_n_0\ : STD_LOGIC;
signal \rstate[0]_i_2_n_0\ : STD_LOGIC;
signal \^s_axi_axilites_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^s_axi_axilites_rvalid\ : STD_LOGIC;
signal step_size_V : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \temp_V[0]_i_2_n_0\ : STD_LOGIC;
signal \temp_V[0]_i_3_n_0\ : STD_LOGIC;
signal \temp_V[0]_i_4_n_0\ : STD_LOGIC;
signal \temp_V[0]_i_5_n_0\ : STD_LOGIC;
signal \temp_V[12]_i_2_n_0\ : STD_LOGIC;
signal \temp_V[12]_i_3_n_0\ : STD_LOGIC;
signal \temp_V[12]_i_4_n_0\ : STD_LOGIC;
signal \temp_V[12]_i_5_n_0\ : STD_LOGIC;
signal \temp_V[4]_i_2_n_0\ : STD_LOGIC;
signal \temp_V[4]_i_3_n_0\ : STD_LOGIC;
signal \temp_V[4]_i_4_n_0\ : STD_LOGIC;
signal \temp_V[4]_i_5_n_0\ : STD_LOGIC;
signal \temp_V[8]_i_2_n_0\ : STD_LOGIC;
signal \temp_V[8]_i_3_n_0\ : STD_LOGIC;
signal \temp_V[8]_i_4_n_0\ : STD_LOGIC;
signal \temp_V[8]_i_5_n_0\ : STD_LOGIC;
signal \temp_V_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \temp_V_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \temp_V_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \temp_V_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \temp_V_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \temp_V_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \temp_V_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \temp_V_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \temp_V_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \temp_V_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \temp_V_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \temp_V_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \temp_V_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \temp_V_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \temp_V_reg[8]_i_1_n_3\ : STD_LOGIC;
signal waddr : STD_LOGIC;
signal \waddr_reg_n_0_[0]\ : STD_LOGIC;
signal \waddr_reg_n_0_[1]\ : STD_LOGIC;
signal \waddr_reg_n_0_[2]\ : STD_LOGIC;
signal \waddr_reg_n_0_[3]\ : STD_LOGIC;
signal \waddr_reg_n_0_[4]\ : STD_LOGIC;
signal wstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \wstate[0]_i_1_n_0\ : STD_LOGIC;
signal \wstate[1]_i_1_n_0\ : STD_LOGIC;
signal NLW_q0_reg_0_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_q0_reg_0_i_12_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_temp_V_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \int_step_size_V[0]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_step_size_V[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_step_size_V[11]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_step_size_V[12]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_step_size_V[13]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_step_size_V[14]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_step_size_V[15]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_step_size_V[15]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_step_size_V[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_step_size_V[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_step_size_V[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_step_size_V[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_step_size_V[5]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_step_size_V[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_step_size_V[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_step_size_V[8]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_step_size_V[9]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \rdata[10]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rdata[11]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rdata[12]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rdata[13]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rdata[14]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rdata[15]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rdata[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rdata[3]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rdata[4]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rdata[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rdata[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rdata[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rdata[8]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rdata[9]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rstate[0]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of s_axi_AXILiteS_ARREADY_INST_0 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of s_axi_AXILiteS_AWREADY_INST_0 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_AXILiteS_BVALID_INST_0 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of s_axi_AXILiteS_WREADY_INST_0 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \wstate[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wstate[1]_i_1\ : label is "soft_lutpair1";
begin
ap_rst_n_inv <= \^ap_rst_n_inv\;
s_axi_AXILiteS_RDATA(15 downto 0) <= \^s_axi_axilites_rdata\(15 downto 0);
s_axi_AXILiteS_RVALID <= \^s_axi_axilites_rvalid\;
int_sine_sample_V_ap_vld_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFFAAAAAAAA"
)
port map (
I0 => Q(0),
I1 => int_sine_sample_V_ap_vld_i_2_n_0,
I2 => ar_hs,
I3 => s_axi_AXILiteS_ARADDR(3),
I4 => s_axi_AXILiteS_ARADDR(2),
I5 => int_sine_sample_V_ap_vld,
O => int_sine_sample_V_ap_vld_i_1_n_0
);
int_sine_sample_V_ap_vld_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => s_axi_AXILiteS_ARADDR(1),
I1 => s_axi_AXILiteS_ARADDR(4),
I2 => s_axi_AXILiteS_ARADDR(0),
O => int_sine_sample_V_ap_vld_i_2_n_0
);
int_sine_sample_V_ap_vld_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => int_sine_sample_V_ap_vld_i_1_n_0,
Q => int_sine_sample_V_ap_vld,
R => \^ap_rst_n_inv\
);
\int_step_size_V[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(0),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(0),
O => \int_step_size_V[0]_i_1_n_0\
);
\int_step_size_V[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(10),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(10),
O => \int_step_size_V[10]_i_1_n_0\
);
\int_step_size_V[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(11),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(11),
O => \int_step_size_V[11]_i_1_n_0\
);
\int_step_size_V[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(12),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(12),
O => \int_step_size_V[12]_i_1_n_0\
);
\int_step_size_V[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(13),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(13),
O => \int_step_size_V[13]_i_1_n_0\
);
\int_step_size_V[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(14),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(14),
O => \int_step_size_V[14]_i_1_n_0\
);
\int_step_size_V[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \waddr_reg_n_0_[0]\,
I1 => \waddr_reg_n_0_[2]\,
I2 => \waddr_reg_n_0_[1]\,
I3 => \int_step_size_V[15]_i_3_n_0\,
O => p_0_in
);
\int_step_size_V[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(15),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(15),
O => \int_step_size_V[15]_i_2_n_0\
);
\int_step_size_V[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \waddr_reg_n_0_[4]\,
I1 => \waddr_reg_n_0_[3]\,
I2 => s_axi_AXILiteS_WVALID,
I3 => wstate(0),
I4 => wstate(1),
O => \int_step_size_V[15]_i_3_n_0\
);
\int_step_size_V[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(1),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(1),
O => \int_step_size_V[1]_i_1_n_0\
);
\int_step_size_V[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(2),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(2),
O => \int_step_size_V[2]_i_1_n_0\
);
\int_step_size_V[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(3),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(3),
O => \int_step_size_V[3]_i_1_n_0\
);
\int_step_size_V[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(4),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(4),
O => \int_step_size_V[4]_i_1_n_0\
);
\int_step_size_V[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(5),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(5),
O => \int_step_size_V[5]_i_1_n_0\
);
\int_step_size_V[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(6),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(6),
O => \int_step_size_V[6]_i_1_n_0\
);
\int_step_size_V[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(7),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(7),
O => \int_step_size_V[7]_i_1_n_0\
);
\int_step_size_V[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(8),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(8),
O => \int_step_size_V[8]_i_1_n_0\
);
\int_step_size_V[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(9),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(9),
O => \int_step_size_V[9]_i_1_n_0\
);
\int_step_size_V_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[0]_i_1_n_0\,
Q => step_size_V(0),
R => '0'
);
\int_step_size_V_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[10]_i_1_n_0\,
Q => step_size_V(10),
R => '0'
);
\int_step_size_V_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[11]_i_1_n_0\,
Q => step_size_V(11),
R => '0'
);
\int_step_size_V_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[12]_i_1_n_0\,
Q => step_size_V(12),
R => '0'
);
\int_step_size_V_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[13]_i_1_n_0\,
Q => step_size_V(13),
R => '0'
);
\int_step_size_V_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[14]_i_1_n_0\,
Q => step_size_V(14),
R => '0'
);
\int_step_size_V_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[15]_i_2_n_0\,
Q => step_size_V(15),
R => '0'
);
\int_step_size_V_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[1]_i_1_n_0\,
Q => step_size_V(1),
R => '0'
);
\int_step_size_V_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[2]_i_1_n_0\,
Q => step_size_V(2),
R => '0'
);
\int_step_size_V_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[3]_i_1_n_0\,
Q => step_size_V(3),
R => '0'
);
\int_step_size_V_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[4]_i_1_n_0\,
Q => step_size_V(4),
R => '0'
);
\int_step_size_V_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[5]_i_1_n_0\,
Q => step_size_V(5),
R => '0'
);
\int_step_size_V_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[6]_i_1_n_0\,
Q => step_size_V(6),
R => '0'
);
\int_step_size_V_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[7]_i_1_n_0\,
Q => step_size_V(7),
R => '0'
);
\int_step_size_V_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[8]_i_1_n_0\,
Q => step_size_V(8),
R => '0'
);
\int_step_size_V_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \int_step_size_V[9]_i_1_n_0\,
Q => step_size_V(9),
R => '0'
);
q0_reg_0_i_1: unisim.vcomponents.CARRY4
port map (
CI => q0_reg_0_i_2_n_0,
CO(3) => NLW_q0_reg_0_i_1_CO_UNCONNECTED(3),
CO(2) => q0_reg_0_i_1_n_1,
CO(1) => q0_reg_0_i_1_n_2,
CO(0) => q0_reg_0_i_1_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => temp_V_reg(14 downto 12),
O(3 downto 0) => sel(11 downto 8),
S(3) => q0_reg_0_i_4_n_0,
S(2) => q0_reg_0_i_5_n_0,
S(1) => q0_reg_0_i_6_n_0,
S(0) => q0_reg_0_i_7_n_0
);
q0_reg_0_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(9),
I1 => step_size_V(9),
O => q0_reg_0_i_10_n_0
);
q0_reg_0_i_11: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(8),
I1 => step_size_V(8),
O => q0_reg_0_i_11_n_0
);
q0_reg_0_i_12: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => q0_reg_0_i_12_n_0,
CO(2) => q0_reg_0_i_12_n_1,
CO(1) => q0_reg_0_i_12_n_2,
CO(0) => q0_reg_0_i_12_n_3,
CYINIT => '0',
DI(3 downto 0) => temp_V_reg(3 downto 0),
O(3 downto 0) => NLW_q0_reg_0_i_12_O_UNCONNECTED(3 downto 0),
S(3) => q0_reg_0_i_17_n_0,
S(2) => q0_reg_0_i_18_n_0,
S(1) => q0_reg_0_i_19_n_0,
S(0) => q0_reg_0_i_20_n_0
);
q0_reg_0_i_13: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(7),
I1 => step_size_V(7),
O => q0_reg_0_i_13_n_0
);
q0_reg_0_i_14: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(6),
I1 => step_size_V(6),
O => q0_reg_0_i_14_n_0
);
q0_reg_0_i_15: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(5),
I1 => step_size_V(5),
O => q0_reg_0_i_15_n_0
);
q0_reg_0_i_16: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(4),
I1 => step_size_V(4),
O => q0_reg_0_i_16_n_0
);
q0_reg_0_i_17: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(3),
I1 => step_size_V(3),
O => q0_reg_0_i_17_n_0
);
q0_reg_0_i_18: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(2),
I1 => step_size_V(2),
O => q0_reg_0_i_18_n_0
);
q0_reg_0_i_19: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(1),
I1 => step_size_V(1),
O => q0_reg_0_i_19_n_0
);
q0_reg_0_i_2: unisim.vcomponents.CARRY4
port map (
CI => q0_reg_0_i_3_n_0,
CO(3) => q0_reg_0_i_2_n_0,
CO(2) => q0_reg_0_i_2_n_1,
CO(1) => q0_reg_0_i_2_n_2,
CO(0) => q0_reg_0_i_2_n_3,
CYINIT => '0',
DI(3 downto 0) => temp_V_reg(11 downto 8),
O(3 downto 0) => sel(7 downto 4),
S(3) => q0_reg_0_i_8_n_0,
S(2) => q0_reg_0_i_9_n_0,
S(1) => q0_reg_0_i_10_n_0,
S(0) => q0_reg_0_i_11_n_0
);
q0_reg_0_i_20: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(0),
I1 => step_size_V(0),
O => q0_reg_0_i_20_n_0
);
q0_reg_0_i_3: unisim.vcomponents.CARRY4
port map (
CI => q0_reg_0_i_12_n_0,
CO(3) => q0_reg_0_i_3_n_0,
CO(2) => q0_reg_0_i_3_n_1,
CO(1) => q0_reg_0_i_3_n_2,
CO(0) => q0_reg_0_i_3_n_3,
CYINIT => '0',
DI(3 downto 0) => temp_V_reg(7 downto 4),
O(3 downto 0) => sel(3 downto 0),
S(3) => q0_reg_0_i_13_n_0,
S(2) => q0_reg_0_i_14_n_0,
S(1) => q0_reg_0_i_15_n_0,
S(0) => q0_reg_0_i_16_n_0
);
q0_reg_0_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(15),
I1 => step_size_V(15),
O => q0_reg_0_i_4_n_0
);
q0_reg_0_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(14),
I1 => step_size_V(14),
O => q0_reg_0_i_5_n_0
);
q0_reg_0_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(13),
I1 => step_size_V(13),
O => q0_reg_0_i_6_n_0
);
q0_reg_0_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(12),
I1 => step_size_V(12),
O => q0_reg_0_i_7_n_0
);
q0_reg_0_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(11),
I1 => step_size_V(11),
O => q0_reg_0_i_8_n_0
);
q0_reg_0_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(10),
I1 => step_size_V(10),
O => q0_reg_0_i_9_n_0
);
\rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020FFFF00200000"
)
port map (
I0 => \rdata[0]_i_2_n_0\,
I1 => s_axi_AXILiteS_ARADDR(0),
I2 => s_axi_AXILiteS_ARADDR(4),
I3 => s_axi_AXILiteS_ARADDR(1),
I4 => ar_hs,
I5 => \^s_axi_axilites_rdata\(0),
O => \rdata[0]_i_1_n_0\
);
\rdata[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => step_size_V(0),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => int_sine_sample_V_ap_vld,
I3 => s_axi_AXILiteS_ARADDR(2),
I4 => \out\(0),
O => \rdata[0]_i_2_n_0\
);
\rdata[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(10),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(10),
O => \rdata[10]_i_1_n_0\
);
\rdata[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(11),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(11),
O => \rdata[11]_i_1_n_0\
);
\rdata[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(12),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(12),
O => \rdata[12]_i_1_n_0\
);
\rdata[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(13),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(13),
O => \rdata[13]_i_1_n_0\
);
\rdata[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(14),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(14),
O => \rdata[14]_i_1_n_0\
);
\rdata[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFB00000000"
)
port map (
I0 => s_axi_AXILiteS_ARADDR(1),
I1 => s_axi_AXILiteS_ARADDR(4),
I2 => s_axi_AXILiteS_ARADDR(0),
I3 => s_axi_AXILiteS_ARADDR(2),
I4 => \^s_axi_axilites_rvalid\,
I5 => s_axi_AXILiteS_ARVALID,
O => \rdata[15]_i_1_n_0\
);
\rdata[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_AXILiteS_ARVALID,
I1 => \^s_axi_axilites_rvalid\,
O => ar_hs
);
\rdata[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(15),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(15),
O => \rdata[15]_i_3_n_0\
);
\rdata[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(1),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(1),
O => \rdata[1]_i_1_n_0\
);
\rdata[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(2),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(2),
O => \rdata[2]_i_1_n_0\
);
\rdata[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(3),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(3),
O => \rdata[3]_i_1_n_0\
);
\rdata[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(4),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(4),
O => \rdata[4]_i_1_n_0\
);
\rdata[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(5),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(5),
O => \rdata[5]_i_1_n_0\
);
\rdata[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(6),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(6),
O => \rdata[6]_i_1_n_0\
);
\rdata[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(7),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(7),
O => \rdata[7]_i_1_n_0\
);
\rdata[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(8),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(8),
O => \rdata[8]_i_1_n_0\
);
\rdata[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(9),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(9),
O => \rdata[9]_i_1_n_0\
);
\rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rdata[0]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(0),
R => '0'
);
\rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[10]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(10),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[11]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(11),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[12]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(12),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[13]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(13),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[14]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(14),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[15]_i_3_n_0\,
Q => \^s_axi_axilites_rdata\(15),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[1]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(1),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[2]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(2),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[3]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(3),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[4]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(4),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[5]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(5),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[6]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(6),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[7]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(7),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[8]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(8),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[9]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(9),
R => \rdata[15]_i_1_n_0\
);
\rstate[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ap_rst_n,
O => \^ap_rst_n_inv\
);
\rstate[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => s_axi_AXILiteS_ARVALID,
I1 => s_axi_AXILiteS_RREADY,
I2 => \^s_axi_axilites_rvalid\,
O => \rstate[0]_i_2_n_0\
);
\rstate_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rstate[0]_i_2_n_0\,
Q => \^s_axi_axilites_rvalid\,
R => \^ap_rst_n_inv\
);
s_axi_AXILiteS_ARREADY_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_axi_axilites_rvalid\,
O => s_axi_AXILiteS_ARREADY
);
s_axi_AXILiteS_AWREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => wstate(1),
I1 => wstate(0),
O => s_axi_AXILiteS_AWREADY
);
s_axi_AXILiteS_BVALID_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wstate(1),
I1 => wstate(0),
O => s_axi_AXILiteS_BVALID
);
s_axi_AXILiteS_WREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wstate(0),
I1 => wstate(1),
O => s_axi_AXILiteS_WREADY
);
\temp_V[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(3),
I1 => temp_V_reg(3),
O => \temp_V[0]_i_2_n_0\
);
\temp_V[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(2),
I1 => temp_V_reg(2),
O => \temp_V[0]_i_3_n_0\
);
\temp_V[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(1),
I1 => temp_V_reg(1),
O => \temp_V[0]_i_4_n_0\
);
\temp_V[0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(0),
I1 => temp_V_reg(0),
O => \temp_V[0]_i_5_n_0\
);
\temp_V[12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(15),
I1 => step_size_V(15),
O => \temp_V[12]_i_2_n_0\
);
\temp_V[12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(14),
I1 => temp_V_reg(14),
O => \temp_V[12]_i_3_n_0\
);
\temp_V[12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(13),
I1 => temp_V_reg(13),
O => \temp_V[12]_i_4_n_0\
);
\temp_V[12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(12),
I1 => temp_V_reg(12),
O => \temp_V[12]_i_5_n_0\
);
\temp_V[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(7),
I1 => temp_V_reg(7),
O => \temp_V[4]_i_2_n_0\
);
\temp_V[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(6),
I1 => temp_V_reg(6),
O => \temp_V[4]_i_3_n_0\
);
\temp_V[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(5),
I1 => temp_V_reg(5),
O => \temp_V[4]_i_4_n_0\
);
\temp_V[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(4),
I1 => temp_V_reg(4),
O => \temp_V[4]_i_5_n_0\
);
\temp_V[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(11),
I1 => temp_V_reg(11),
O => \temp_V[8]_i_2_n_0\
);
\temp_V[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(10),
I1 => temp_V_reg(10),
O => \temp_V[8]_i_3_n_0\
);
\temp_V[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(9),
I1 => temp_V_reg(9),
O => \temp_V[8]_i_4_n_0\
);
\temp_V[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(8),
I1 => temp_V_reg(8),
O => \temp_V[8]_i_5_n_0\
);
\temp_V_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \temp_V_reg[0]_i_1_n_0\,
CO(2) => \temp_V_reg[0]_i_1_n_1\,
CO(1) => \temp_V_reg[0]_i_1_n_2\,
CO(0) => \temp_V_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => step_size_V(3 downto 0),
O(3 downto 0) => O(3 downto 0),
S(3) => \temp_V[0]_i_2_n_0\,
S(2) => \temp_V[0]_i_3_n_0\,
S(1) => \temp_V[0]_i_4_n_0\,
S(0) => \temp_V[0]_i_5_n_0\
);
\temp_V_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \temp_V_reg[8]_i_1_n_0\,
CO(3) => \NLW_temp_V_reg[12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \temp_V_reg[12]_i_1_n_1\,
CO(1) => \temp_V_reg[12]_i_1_n_2\,
CO(0) => \temp_V_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => step_size_V(14 downto 12),
O(3 downto 0) => \temp_V_reg[15]\(3 downto 0),
S(3) => \temp_V[12]_i_2_n_0\,
S(2) => \temp_V[12]_i_3_n_0\,
S(1) => \temp_V[12]_i_4_n_0\,
S(0) => \temp_V[12]_i_5_n_0\
);
\temp_V_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \temp_V_reg[0]_i_1_n_0\,
CO(3) => \temp_V_reg[4]_i_1_n_0\,
CO(2) => \temp_V_reg[4]_i_1_n_1\,
CO(1) => \temp_V_reg[4]_i_1_n_2\,
CO(0) => \temp_V_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => step_size_V(7 downto 4),
O(3 downto 0) => \temp_V_reg[7]\(3 downto 0),
S(3) => \temp_V[4]_i_2_n_0\,
S(2) => \temp_V[4]_i_3_n_0\,
S(1) => \temp_V[4]_i_4_n_0\,
S(0) => \temp_V[4]_i_5_n_0\
);
\temp_V_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \temp_V_reg[4]_i_1_n_0\,
CO(3) => \temp_V_reg[8]_i_1_n_0\,
CO(2) => \temp_V_reg[8]_i_1_n_1\,
CO(1) => \temp_V_reg[8]_i_1_n_2\,
CO(0) => \temp_V_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => step_size_V(11 downto 8),
O(3 downto 0) => \temp_V_reg[11]\(3 downto 0),
S(3) => \temp_V[8]_i_2_n_0\,
S(2) => \temp_V[8]_i_3_n_0\,
S(1) => \temp_V[8]_i_4_n_0\,
S(0) => \temp_V[8]_i_5_n_0\
);
\waddr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_AXILiteS_AWVALID,
I1 => wstate(0),
I2 => wstate(1),
O => waddr
);
\waddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_AXILiteS_AWADDR(0),
Q => \waddr_reg_n_0_[0]\,
R => '0'
);
\waddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_AXILiteS_AWADDR(1),
Q => \waddr_reg_n_0_[1]\,
R => '0'
);
\waddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_AXILiteS_AWADDR(2),
Q => \waddr_reg_n_0_[2]\,
R => '0'
);
\waddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_AXILiteS_AWADDR(3),
Q => \waddr_reg_n_0_[3]\,
R => '0'
);
\waddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_AXILiteS_AWADDR(4),
Q => \waddr_reg_n_0_[4]\,
R => '0'
);
\wstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0454"
)
port map (
I0 => wstate(1),
I1 => s_axi_AXILiteS_AWVALID,
I2 => wstate(0),
I3 => s_axi_AXILiteS_WVALID,
O => \wstate[0]_i_1_n_0\
);
\wstate[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0838"
)
port map (
I0 => s_axi_AXILiteS_WVALID,
I1 => wstate(0),
I2 => wstate(1),
I3 => s_axi_AXILiteS_BREADY,
O => \wstate[1]_i_1_n_0\
);
\wstate_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \wstate[0]_i_1_n_0\,
Q => wstate(0),
R => \^ap_rst_n_inv\
);
\wstate_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \wstate[1]_i_1_n_0\,
Q => wstate(1),
R => \^ap_rst_n_inv\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom is
port (
\out\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
ap_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
sel : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom is
signal NLW_q0_reg_0_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 8 );
signal NLW_q0_reg_0_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_q0_reg_0_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_q0_reg_0_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_q0_reg_0_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_q0_reg_0_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_q0_reg_1_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 7 );
signal NLW_q0_reg_1_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_q0_reg_1_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_q0_reg_1_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_q0_reg_1_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_q0_reg_1_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of q0_reg_0 : label is "p1_d8";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of q0_reg_0 : label is "";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of q0_reg_0 : label is 65536;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of q0_reg_0 : label is "sine_lut_V_U/nco_sine_lut_V_rom_U/q0";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of q0_reg_0 : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of q0_reg_0 : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of q0_reg_0 : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of q0_reg_0 : label is 8;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of q0_reg_1 : label is "p0_d7";
attribute METHODOLOGY_DRC_VIOS of q0_reg_1 : label is "";
attribute RTL_RAM_BITS of q0_reg_1 : label is 65536;
attribute RTL_RAM_NAME of q0_reg_1 : label is "sine_lut_V_U/nco_sine_lut_V_rom_U/q0";
attribute bram_addr_begin of q0_reg_1 : label is 0;
attribute bram_addr_end of q0_reg_1 : label is 4095;
attribute bram_slice_begin of q0_reg_1 : label is 9;
attribute bram_slice_end of q0_reg_1 : label is 15;
begin
q0_reg_0: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"07FF001FFC00FFE003FF001FF800FFC007FE007FF003FF003FF801FF801FF800",
INITP_01 => X"E0007FFE0007FFC001FFF0007FFC003FFC003FFC003FFC007FF800FFF001FFC0",
INITP_02 => X"E000000FFFFFE000007FFFF800007FFFE00007FFFC0001FFFE0001FFFC0007FF",
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000001FFFFFFFFF00000001FFFFFF",
INITP_04 => X"FFFFFF00000001FFFFFFFFF000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INITP_05 => X"FFC0007FFF0000FFFF00007FFFC0000FFFFC00003FFFFC00000FFFFFE000000F",
INITP_06 => X"07FF001FFE003FFC007FF8007FF8007FF8007FFC001FFF0007FFC000FFFC000F",
INITP_07 => X"003FF003FF003FF801FF801FFC00FFC007FE003FF001FF800FFE007FF001FFC0",
INITP_08 => X"F800FFE003FF001FFC00FFE007FF003FF801FF800FFC00FFC007FE007FE007FE",
INITP_09 => X"1FFF8001FFF8003FFE000FFF8003FFC003FFC003FFC003FF8007FF000FFE003F",
INITP_0A => X"1FFFFFF000001FFFFF800007FFFF80001FFFF80003FFFE0001FFFE0003FFF800",
INITP_0B => X"00000000000000000000000000001FFFFFFFFFFFE000000000FFFFFFFE000000",
INITP_0C => X"000000FFFFFFFE000000000FFFFFFFFFFFF00000000000000000000000000000",
INITP_0D => X"003FFF8000FFFF0000FFFF80003FFFF00003FFFFC00003FFFFF000001FFFFFF0",
INITP_0E => X"F800FFE001FFC003FF8007FF8007FF8007FF8003FFE000FFF8003FFF0003FFF0",
INITP_0F => X"FFC00FFC00FFC007FE007FE003FF003FF801FFC00FFE007FF001FF800FFE003F",
INIT_00 => X"0AF1D8BFA68D745B41280FF6DDC4AB92785F462D14FBE2C9AF967D644B321900",
INIT_01 => X"2C13FAE1C8AF967D644B321900E7CEB59C836A51371E05ECD3BAA1886F563D23",
INIT_02 => X"4B321900E7CEB59C846B52392007EED5BCA38A71583F260DF4DBC2A990775E45",
INIT_03 => X"634B321901E8CFB69E856C543B2209F1D8BFA68D755C432A11F9E0C7AE957C64",
INIT_04 => X"745C432B12FAE2C9B19880674F361E05EDD4BCA38B7259412810F7DEC6AD957C",
INIT_05 => X"7B634B331B03EBD3BBA28A725A422A11F9E1C9B09880684F371F06EED6BDA58C",
INIT_06 => X"776048301901E9D1BAA28A725A432B13FBE3CBB39B836C543C240CF4DCC4AC94",
INIT_07 => X"664F382009F2DAC3AC947D664E371F08F1D9C2AA937B644C341D05EED6BEA78F",
INIT_08 => X"462F1802EBD4BDA68F79624B341D06EFD8C1AA937C654E372008F1DAC3AC957D",
INIT_09 => X"15FEE8D2BCA68F79634C362009F3DCC6AF99836C553F2812FBE5CEB7A18A735D",
INIT_0A => X"D1BBA6907B654F39240EF8E2CDB7A18B755F49341E08F2DCC6B099836D57412B",
INIT_0B => X"79644F3A2510FBE6D1BCA7927D67523D2812FDE8D2BDA8927D68523D2712FCE7",
INIT_0C => X"0BF7E3CFBAA6927D6954402C1703EEDAC5B09C87735E4934200BF6E1CDB8A38E",
INIT_0D => X"86725F4B382411FDEAD6C2AF9B87735F4C382410FCE8D4C0AC9884705C48341F",
INIT_0E => X"E8D5C2B09D8A7765523F2C1906F3E0CDBAA794816E5A4734210EFAE7D4C0AD99",
INIT_0F => X"2F1D0BF9E8D6C4B2A08E7C6A574533210FFCEAD8C6B3A18E7C6A574532200DFA",
INIT_10 => X"5A4938281605F4E3D2C1B09F8D7C6B5A4837251403F1E0CEBCAB998876645241",
INIT_11 => X"69594938281808F8E8D8C7B7A796867665554434231302F1E1D0BFAF9E8D7C6B",
INIT_12 => X"58493A2B1C0DFEEEDFD0C1B1A293837464554536261607F7E7D8C8B8A8988879",
INIT_13 => X"281A0CFEF0E2D4C6B7A99B8C7E706153443627190AFBEDDECFC1B2A394857667",
INIT_14 => X"D8CBBEB1A496897C6F6254473A2C1F1204F7E9DCCEC0B3A597897C6E60524436",
INIT_15 => X"65594D4135291D1105F9EDE0D4C8BBAFA3968A7D7164574B3E3125180BFEF1E5",
INIT_16 => X"D0C5BAAFA4998E83786D62574C41352A1F1308FDF1E6DACFC3B7ACA094897D71",
INIT_17 => X"170D03FAF0E6DCD2C8BEB4AAA0968C82786D63594F443A2F251A1005FBF0E5DA",
INIT_18 => X"39312820170E06FDF4EBE2DAD1C8BFB6ADA39A91887F756C635950473D342A20",
INIT_19 => X"372F282119120A02FBF3ECE4DCD4CCC5BDB5ADA59D958C847C746C635B534A42",
INIT_1A => X"0E0802FCF5EFE9E2DCD6CFC9C2BBB5AEA7A19A938C857E777069625B544D453E",
INIT_1B => X"C0BBB6B1ACA7A19C97928C87827C77716C66615B55504A443E38332D27211B14",
INIT_1C => X"4A47433F3B37332F2B27231F1B17130E0A0601FDF8F4EFEBE6E1DDD8D3CECAC5",
INIT_1D => X"AEACA9A6A4A19E9C999693908D8A8784817E7B7874716E6A6764605D5955524E",
INIT_1E => X"EBE9E8E7E5E4E2E1DFDEDCDAD8D7D5D3D1CFCDCBC9C7C5C3C1BFBCBAB8B5B3B1",
INIT_1F => X"FFFFFFFFFFFFFFFEFEFEFDFDFCFCFBFBFAF9F9F8F7F6F5F4F3F2F1F0EFEEEDEC",
INIT_20 => X"EDEEEFF0F1F2F3F4F5F6F7F8F9F9FAFBFBFCFCFDFDFEFEFEFFFFFFFFFFFFFF00",
INIT_21 => X"B3B5B8BABCBFC1C3C5C7C9CBCDCFD1D3D5D7D8DADCDEDFE1E2E4E5E7E8E9EBEC",
INIT_22 => X"5255595D6064676A6E7174787B7E8184878A8D909396999C9EA1A4A6A9ACAEB1",
INIT_23 => X"CACED3D8DDE1E6EBEFF4F8FD01060A0E13171B1F23272B2F33373B3F43474A4E",
INIT_24 => X"1B21272D33383E444A50555B61666C71777C82878C92979CA1A7ACB1B6BBC0C5",
INIT_25 => X"454D545B626970777E858C939AA1A7AEB5BBC2C9CFD6DCE2E9EFF5FC02080E14",
INIT_26 => X"4A535B636C747C848C959DA5ADB5BDC5CCD4DCE4ECF3FB020A121921282F373E",
INIT_27 => X"2A343D475059636C757F88919AA3ADB6BFC8D1DAE2EBF4FD060E172028313942",
INIT_28 => X"E5F0FB05101A252F3A444F59636D78828C96A0AAB4BEC8D2DCE6F0FA030D1720",
INIT_29 => X"7D8994A0ACB7C3CFDAE6F1FD08131F2A35414C57626D78838E99A4AFBAC5D0DA",
INIT_2A => X"F1FE0B1825313E4B5764717D8A96A3AFBBC8D4E0EDF905111D2935414D596571",
INIT_2B => X"4452606E7C8997A5B3C0CEDCE9F704121F2C3A4754626F7C8996A4B1BECBD8E5",
INIT_2C => X"768594A3B2C1CFDEEDFB0A192736445361707E8C9BA9B7C6D4E2F0FE0C1A2836",
INIT_2D => X"8898A8B8C8D8E7F707162636455564748393A2B1C1D0DFEEFE0D1C2B3A495867",
INIT_2E => X"7C8D9EAFBFD0E1F102132334445565768696A7B7C7D8E8F80818283849596979",
INIT_2F => X"5264768899ABBCCEE0F103142537485A6B7C8D9FB0C1D2E3F405162838495A6B",
INIT_30 => X"0D203245576A7C8EA1B3C6D8EAFC0F213345576A7C8EA0B2C4D6E8F90B1D2F41",
INIT_31 => X"ADC0D4E7FA0E2134475A6E8194A7BACDE0F306192C3F5265778A9DB0C2D5E8FA",
INIT_32 => X"34485C708498ACC0D4E8FC1024384C5F73879BAFC2D6EAFD1124384B5F728699",
INIT_33 => X"A3B8CDE1F60B2034495E73879CB0C5DAEE03172C4054697D92A6BACFE3F70B1F",
INIT_34 => X"FC12273D52687D92A8BDD2E8FD12283D52677D92A7BCD1E6FB10253A4F64798E",
INIT_35 => X"41576D8399B0C6DCF2081E34495F758BA1B7CDE2F80E24394F657B90A6BBD1E7",
INIT_36 => X"738AA1B7CEE5FB12283F556C8399AFC6DCF30920364C63798FA6BCD2E8FE152B",
INIT_37 => X"95ACC3DAF10820374E657C93AAC1D8EF061D344B62798FA6BDD4EB02182F465D",
INIT_38 => X"A7BED6EE051D344C647B93AAC2D9F1081F374E667D94ACC3DAF20920384F667D",
INIT_39 => X"ACC4DCF40C243C546C839BB3CBE3FB132B435A728AA2BAD1E90119304860778F",
INIT_3A => X"A5BDD6EE061F374F688098B0C9E1F9112A425A728AA2BBD3EB031B334B637B94",
INIT_3B => X"95ADC6DEF710284159728BA3BCD4ED051E364F678098B1C9E2FA122B435C748C",
INIT_3C => X"7C95AEC7E0F9112A435C758DA6BFD8F109223B546C859EB6CFE80119324B637C",
INIT_3D => X"5E7790A9C2DBF40D263F58718AA3BCD5EE072039526B849CB5CEE70019324B64",
INIT_3E => X"3D566F88A1BAD3EC051E37516A839CB5CEE70019324B647D96AFC8E1FA132C45",
INIT_3F => X"19324B647D96AFC9E2FB142D465F7892ABC4DDF60F28415B748DA6BFD8F10A23",
INIT_40 => X"F50E274059728BA4BED7F009223B546D87A0B9D2EB041D365069829BB4CDE600",
INIT_41 => X"D3EC051E375069829BB4CDE6FF18314A637C95AEC8E1FA132C455E7790A9C2DC",
INIT_42 => X"B4CDE6FF18314A637B94ADC6DFF8112A435C758EA7C0D9F20B243D566F88A1BA",
INIT_43 => X"9CB4CDE6FE173049617A93ABC4DDF60E274059728AA3BCD5EE061F38516A839B",
INIT_44 => X"8BA3BCD4ED051D364E677F98B0C9E1FA122B435C748DA6BED7EF082139526A83",
INIT_45 => X"849CB4CCE4FC142C445D758DA5BDD5EE061E364F677F97B0C8E0F91129425A73",
INIT_46 => X"889FB7CFE6FE162E455D758DA5BCD4EC041C344C647C93ABC3DBF30B233B536B",
INIT_47 => X"99B0C7DFF60D253C536B8299B1C8E0F70E263D556C849BB3CBE2FA1129415870",
INIT_48 => X"B9D0E7FD142B425970869DB4CBE2F910273E556C839AB1C8DFF70E253C536A82",
INIT_49 => X"EA01172D435970869CB3C9DFF60C233950667C93AAC0D7ED041A31485E758CA2",
INIT_4A => X"2E44596F849AB0C6DBF1071D32485E748AA0B6CBE1F70D23394F667C92A8BED4",
INIT_4B => X"869BB0C5DAEF04192E43586D8298ADC2D7ED02172D42576D8297ADC2D8ED0318",
INIT_4C => X"F4081C3045596D8296ABBFD3E8FC11253A4F63788CA1B6CBDFF4091E32475C71",
INIT_4D => X"798DA0B4C7DBEE0215293D5064788CA0B3C7DBEF03172B3F53677B8FA3B7CBE0",
INIT_4E => X"172A3D4F6275889AADC0D3E6F90C1F3245586B7E91A5B8CBDEF105182B3F5266",
INIT_4F => X"D0E2F40617293B4D5F718395A8BACCDEF0031527394C5E718395A8BACDDFF205",
INIT_50 => X"A5B6C7D7E9FA0B1C2D3E4F60728394A5B7C8DAEBFC0E1F3143546677899BADBE",
INIT_51 => X"96A6B6C7D7E7F70717273848586979899AAABBCBDCECFD0E1E2F405061728394",
INIT_52 => X"A7B6C5D4E3F20111202F3E4E5D6C7C8B9BAABAC9D9E9F8081827374757677786",
INIT_53 => X"D7E5F3010F1D2B3948566473818F9EACBBC9D8E6F5041221303E4D5C6B7A8998",
INIT_54 => X"2734414E5B697683909DABB8C5D3E0EDFB081623313F4C5A687683919FADBBC9",
INIT_55 => X"9AA6B2BECAD6E2EEFA06121F2B3744505C6975828E9BA8B4C1CEDAE7F4010E1A",
INIT_56 => X"2F3A45505B66717C87929DA8B3BECAD5E0ECF7020E1925303C48535F6B76828E",
INIT_57 => X"E8F2FC050F19232D37414B555F69737D87929CA6B0BBC5D0DAE5EFFA040F1A25",
INIT_58 => X"C6CED7DFE8F1F9020B141D252E374049525C656E77808A939CA6AFB8C2CBD5DF",
INIT_59 => X"C8D0D7DEE6EDF5FD040C131B232B333A424A525A626A737B838B939CA4ACB5BD",
INIT_5A => X"F1F7FD030A10161D232930363D444A51585E656C737A81888F969DA4ABB2BAC1",
INIT_5B => X"3F44494E53585E63686D73787D83888E93999EA4AAAFB5BBC1C7CCD2D8DEE4EB",
INIT_5C => X"B5B8BCC0C4C8CCD0D4D8DCE0E4E8ECF1F5F9FE02070B1014191E22272C31353A",
INIT_5D => X"515356595B5E616366696C6F7275787B7E8184878B8E9195989B9FA2A6AAADB1",
INIT_5E => X"141617181A1B1D1E2021232527282A2C2E30323436383A3C3E404345474A4C4E",
INIT_5F => X"000000000000000101010202030304040506060708090A0B0C0D0E0F10111213",
INIT_60 => X"1211100F0E0D0C0B0A0908070606050404030302020101010000000000000000",
INIT_61 => X"4C4A474543403E3C3A38363432302E2C2A2827252321201E1D1B1A1817161413",
INIT_62 => X"ADAAA6A29F9B9895918E8B8784817E7B7875726F6C696663615E5B595653514E",
INIT_63 => X"35312C27221E1914100B0702FEF9F5F1ECE8E4E0DCD8D4D0CCC8C4C0BCB8B5B1",
INIT_64 => X"E4DED8D2CCC7C1BBB5AFAAA49E99938E88837D78736D68635E58534E49443F3A",
INIT_65 => X"BAB2ABA49D968F88817A736C655E58514A443D363029231D16100A03FDF7F1EB",
INIT_66 => X"B5ACA49C938B837B736A625A524A423A332B231B130C04FDF5EDE6DED7D0C8C1",
INIT_67 => X"D5CBC2B8AFA69C938A80776E655C524940372E251D140B02F9F1E8DFD7CEC6BD",
INIT_68 => X"1A0F04FAEFE5DAD0C5BBB0A69C92877D73695F554B41372D23190F05FCF2E8DF",
INIT_69 => X"82766B5F53483C3025190E02F7ECE0D5CABEB3A89D92877C71665B50453A2F25",
INIT_6A => X"0E01F4E7DACEC1B4A89B8E8275695C5044372B1F1206FAEEE2D6CABEB2A69A8E",
INIT_6B => X"BBAD9F918376685A4C3F31231608FBEDE0D3C5B8AB9D908376695B4E4134271A",
INIT_6C => X"897A6B5C4D3E30211204F5E6D8C9BBAC9E8F8173645648392B1D0F01F3E5D7C9",
INIT_6D => X"7767574737271808F8E9D9C9BAAA9B8B7C6C5D4E3E2F201101F2E3D4C5B6A798",
INIT_6E => X"83726150402F1E0EFDECDCCBBBAA9A897969584838271707F7E7D7C7B6A69686",
INIT_6F => X"AD9B8977665443311F0EFCEBDAC8B7A5948372604F3E2D1C0BFAE9D7C7B6A594",
INIT_70 => X"F2DFCDBAA89583715E4C39271503F0DECCBAA89583715F4D3B291706F4E2D0BE",
INIT_71 => X"523F2B1805F1DECBB8A5917E6B5845321F0CF9E6D3C0AD9A8875624F3D2A1705",
INIT_72 => X"CBB7A38F7B67533F2B1703EFDBC7B3A08C7864503D291502EEDBC7B4A08D7966",
INIT_73 => X"5C47321E09F4DFCBB6A18C78634F3A2511FCE8D3BFAB96826D5945301C08F4E0",
INIT_74 => X"03EDD8C2AD97826D57422D1702EDD7C2AD98826D58432E1904EFDAC5B09B8671",
INIT_75 => X"BEA8927C664F39230DF7E1CBB6A08A745E48321D07F1DBC6B09A846F59442E18",
INIT_76 => X"8C755E48311A04EDD7C0AA937C665039230CF6DFC9B39C867059432D1701EAD4",
INIT_77 => X"6A533C250EF7DFC8B19A836C553E2710F9E2CBB49D867059422B14FDE7D0B9A2",
INIT_78 => X"58412911FAE2CBB39B846C553D260EF7E0C8B199826B533C250DF6DFC7B09982",
INIT_79 => X"533B230BF3DBC3AB937C644C341C04ECD4BCA58D755D452E16FEE6CFB79F8870",
INIT_7A => X"5A422911F9E0C8B0977F674F361E06EED5BDA58D755D442C14FCE4CCB49C846B",
INIT_7B => X"6A52392108EFD7BEA68D745C432B12FAE1C9B0987F674E361D05EDD4BCA38B73",
INIT_7C => X"836A51381F06EED5BCA38A725940270EF6DDC4AB937A61493017FEE6CDB49C83",
INIT_7D => X"A1886F563D240BF2D9C0A78E755C432A11F8DFC6AD947B634A3118FFE6CDB49B",
INIT_7E => X"C2A990775E452C13FAE1C8AE957C634A3118FFE6CDB49B826950371E05ECD3BA",
INIT_7F => X"E6CDB49B826950361D04EBD2B9A0876D543B2209F0D7BEA48B725940270EF5DC",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => sel(11 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(15 downto 0) => B"1111111111111111",
CASCADEINA => '1',
CASCADEINB => '0',
CASCADEOUTA => NLW_q0_reg_0_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_q0_reg_0_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => ap_clk,
CLKBWRCLK => '0',
DBITERR => NLW_q0_reg_0_DBITERR_UNCONNECTED,
DIADI(31 downto 0) => B"00000000000000000000000011111111",
DIBDI(31 downto 0) => B"11111111111111111111111111111111",
DIPADIP(3 downto 0) => B"0001",
DIPBDIP(3 downto 0) => B"1111",
DOADO(31 downto 8) => NLW_q0_reg_0_DOADO_UNCONNECTED(31 downto 8),
DOADO(7 downto 0) => \out\(7 downto 0),
DOBDO(31 downto 0) => NLW_q0_reg_0_DOBDO_UNCONNECTED(31 downto 0),
DOPADOP(3 downto 1) => NLW_q0_reg_0_DOPADOP_UNCONNECTED(3 downto 1),
DOPADOP(0) => \out\(8),
DOPBDOP(3 downto 0) => NLW_q0_reg_0_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_q0_reg_0_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => Q(0),
ENBWREN => '0',
INJECTDBITERR => NLW_q0_reg_0_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_q0_reg_0_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_q0_reg_0_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => Q(1),
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => SR(0),
RSTREGB => '0',
SBITERR => NLW_q0_reg_0_SBITERR_UNCONNECTED,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
q0_reg_1: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0101010101010101010101000000000000000000000000000000000000000000",
INIT_01 => X"0303020202020202020202020202020202020202020202010101010101010101",
INIT_02 => X"0404040404040404040404040404030303030303030303030303030303030303",
INIT_03 => X"0606060606050505050505050505050505050505050505050504040404040404",
INIT_04 => X"0707070707070707070707070707070706060606060606060606060606060606",
INIT_05 => X"0909090909090808080808080808080808080808080808080808080707070707",
INIT_06 => X"0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A09090909090909090909090909090909",
INIT_07 => X"0C0C0C0C0C0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0A0A0A0A0A",
INIT_08 => X"0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C",
INIT_09 => X"0F0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0D0D0D0D0D0D0D0D",
INIT_0A => X"101010101010101010100F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0B => X"1111111111111111111111111111111111111010101010101010101010101010",
INIT_0C => X"1312121212121212121212121212121212121212121212121212111111111111",
INIT_0D => X"1414141414141413131313131313131313131313131313131313131313131313",
INIT_0E => X"1515151515151515151515151514141414141414141414141414141414141414",
INIT_0F => X"1616161616161616161616161616161616151515151515151515151515151515",
INIT_10 => X"1717171717171717171717171717171717171717171616161616161616161616",
INIT_11 => X"1818181818181818181818181818181818181818181818171717171717171717",
INIT_12 => X"1919191919191919191919191919191919191919191919181818181818181818",
INIT_13 => X"1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1919191919191919191919",
INIT_14 => X"1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A",
INIT_15 => X"1C1C1C1C1C1C1C1C1C1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B",
INIT_16 => X"1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C",
INIT_17 => X"1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1C1C1C1C",
INIT_18 => X"1E1E1E1E1E1E1E1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D",
INIT_19 => X"1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E",
INIT_1A => X"1F1F1F1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E",
INIT_1B => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_1C => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_1D => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_1E => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_1F => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_20 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F20",
INIT_21 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_22 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_23 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_24 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_25 => X"1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1F1F1F1F",
INIT_26 => X"1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E",
INIT_27 => X"1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1E1E1E1E1E1E1E1E",
INIT_28 => X"1C1C1C1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D",
INIT_29 => X"1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C",
INIT_2A => X"1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1C1C1C1C1C1C1C1C1C1C",
INIT_2B => X"1A1A1A1A1A1A1A1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B",
INIT_2C => X"191919191919191919191A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A",
INIT_2D => X"1818181818181818191919191919191919191919191919191919191919191919",
INIT_2E => X"1717171717171717181818181818181818181818181818181818181818181818",
INIT_2F => X"1616161616161616161617171717171717171717171717171717171717171717",
INIT_30 => X"1515151515151515151515151515161616161616161616161616161616161616",
INIT_31 => X"1414141414141414141414141414141414141515151515151515151515151515",
INIT_32 => X"1313131313131313131313131313131313131313131313131414141414141414",
INIT_33 => X"1111111111121212121212121212121212121212121212121212121212121313",
INIT_34 => X"1010101010101010101010101011111111111111111111111111111111111111",
INIT_35 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1010101010101010101010",
INIT_36 => X"0D0D0D0D0D0D0D0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0F0F",
INIT_37 => X"0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D",
INIT_38 => X"0A0A0A0A0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0C0C0C0C0C0C",
INIT_39 => X"0909090909090909090909090909090A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A",
INIT_3A => X"0707070708080808080808080808080808080808080808080809090909090909",
INIT_3B => X"0606060606060606060606060606060707070707070707070707070707070707",
INIT_3C => X"0404040404040505050505050505050505050505050505050505060606060606",
INIT_3D => X"0303030303030303030303030303030303040404040404040404040404040404",
INIT_3E => X"0101010101010101020202020202020202020202020202020202020202030303",
INIT_3F => X"0000000000000000000000000000000000000000010101010101010101010101",
INIT_40 => X"7E7E7E7E7E7E7E7E7E7E7E7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F00",
INIT_41 => X"7C7C7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7E7E7E7E7E7E7E7E7E",
INIT_42 => X"7B7B7B7B7B7B7B7B7B7B7B7B7B7B7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C",
INIT_43 => X"79797979797A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7B7B7B7B7B7B7B",
INIT_44 => X"7878787878787878787878787878787879797979797979797979797979797979",
INIT_45 => X"7676767676767777777777777777777777777777777777777777777878787878",
INIT_46 => X"7575757575757575757575757575757576767676767676767676767676767676",
INIT_47 => X"7373737373747474747474747474747474747474747474747474747575757575",
INIT_48 => X"7272727272727272727272727272727373737373737373737373737373737373",
INIT_49 => X"7071717171717171717171717171717171717171717171717272727272727272",
INIT_4A => X"6F6F6F6F6F6F6F6F6F6F70707070707070707070707070707070707070707070",
INIT_4B => X"6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6F6F6F6F6F6F6F6F6F6F6F6F6F6F",
INIT_4C => X"6C6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6E6E6E6E6E6E",
INIT_4D => X"6B6B6B6B6B6B6B6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C",
INIT_4E => X"6A6A6A6A6A6A6A6A6A6A6A6A6A6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B",
INIT_4F => X"69696969696969696969696969696969696A6A6A6A6A6A6A6A6A6A6A6A6A6A6A",
INIT_50 => X"6868686868686868686868686868686868686868686969696969696969696969",
INIT_51 => X"6767676767676767676767676767676767676767676767686868686868686868",
INIT_52 => X"6666666666666666666666666666666666666666666666676767676767676767",
INIT_53 => X"6565656565656565656565656565656565656565656666666666666666666666",
INIT_54 => X"6464646464646464646464646464646464656565656565656565656565656565",
INIT_55 => X"6363636363636363636464646464646464646464646464646464646464646464",
INIT_56 => X"6363636363636363636363636363636363636363636363636363636363636363",
INIT_57 => X"6262626262626262626262626262626262626262626262626262626263636363",
INIT_58 => X"6161616161616162626262626262626262626262626262626262626262626262",
INIT_59 => X"6161616161616161616161616161616161616161616161616161616161616161",
INIT_5A => X"6060606161616161616161616161616161616161616161616161616161616161",
INIT_5B => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_5C => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_5D => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_5E => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_5F => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_60 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_61 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_62 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_63 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_64 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_65 => X"6161616161616161616161616161616161616161616161616161616160606060",
INIT_66 => X"6161616161616161616161616161616161616161616161616161616161616161",
INIT_67 => X"6262626262626262626262626262626262626262626262626161616161616161",
INIT_68 => X"6363636262626262626262626262626262626262626262626262626262626262",
INIT_69 => X"6363636363636363636363636363636363636363636363636363636363636363",
INIT_6A => X"6464646464646464646464646464646464646464646463636363636363636363",
INIT_6B => X"6565656565656565656565656565646464646464646464646464646464646464",
INIT_6C => X"6666666666666666666665656565656565656565656565656565656565656565",
INIT_6D => X"6767676767676767666666666666666666666666666666666666666666666666",
INIT_6E => X"6868686868686868676767676767676767676767676767676767676767676767",
INIT_6F => X"6969696969696969696968686868686868686868686868686868686868686868",
INIT_70 => X"6A6A6A6A6A6A6A6A6A6A6A6A6A6A696969696969696969696969696969696969",
INIT_71 => X"6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6A6A6A6A6A6A6A6A6A6A6A6A6A6A",
INIT_72 => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6B6B6B6B6B6B6B6B",
INIT_73 => X"6E6E6E6E6E6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6C6C",
INIT_74 => X"6F6F6F6F6F6F6F6F6F6F6F6F6F6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E",
INIT_75 => X"7070707070707070707070707070707070707070706F6F6F6F6F6F6F6F6F6F6F",
INIT_76 => X"7272727272727271717171717171717171717171717171717171717171717070",
INIT_77 => X"7373737373737373737373737373737372727272727272727272727272727272",
INIT_78 => X"7575757574747474747474747474747474747474747474747474737373737373",
INIT_79 => X"7676767676767676767676767676767575757575757575757575757575757575",
INIT_7A => X"7878787877777777777777777777777777777777777777777776767676767676",
INIT_7B => X"7979797979797979797979797979797878787878787878787878787878787878",
INIT_7C => X"7B7B7B7B7B7B7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A797979797979",
INIT_7D => X"7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B",
INIT_7E => X"7E7E7E7E7E7E7E7E7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7C7C7C",
INIT_7F => X"7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7E7E7E7E7E7E7E7E7E7E7E7E",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => sel(11 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(15 downto 0) => B"1111111111111111",
CASCADEINA => '1',
CASCADEINB => '0',
CASCADEOUTA => NLW_q0_reg_1_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_q0_reg_1_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => ap_clk,
CLKBWRCLK => '0',
DBITERR => NLW_q0_reg_1_DBITERR_UNCONNECTED,
DIADI(31 downto 0) => B"00000000000000000000000001111111",
DIBDI(31 downto 0) => B"11111111111111111111111111111111",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"1111",
DOADO(31 downto 7) => NLW_q0_reg_1_DOADO_UNCONNECTED(31 downto 7),
DOADO(6 downto 0) => \out\(15 downto 9),
DOBDO(31 downto 0) => NLW_q0_reg_1_DOBDO_UNCONNECTED(31 downto 0),
DOPADOP(3 downto 0) => NLW_q0_reg_1_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 0) => NLW_q0_reg_1_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_q0_reg_1_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => Q(0),
ENBWREN => '0',
INJECTDBITERR => NLW_q0_reg_1_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_q0_reg_1_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_q0_reg_1_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => Q(1),
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => SR(0),
RSTREGB => '0',
SBITERR => NLW_q0_reg_1_SBITERR_UNCONNECTED,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V is
port (
\out\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
ap_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
sel : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V is
begin
nco_sine_lut_V_rom_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom
port map (
Q(1 downto 0) => Q(1 downto 0),
SR(0) => SR(0),
ap_clk => ap_clk,
\out\(15 downto 0) => \out\(15 downto 0),
sel(11 downto 0) => sel(11 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco is
port (
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC
);
attribute C_S_AXI_AXILITES_ADDR_WIDTH : integer;
attribute C_S_AXI_AXILITES_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 6;
attribute C_S_AXI_AXILITES_DATA_WIDTH : integer;
attribute C_S_AXI_AXILITES_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 32;
attribute C_S_AXI_AXILITES_WSTRB_WIDTH : integer;
attribute C_S_AXI_AXILITES_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 32;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 4;
attribute ap_ST_st1_fsm_0 : string;
attribute ap_ST_st1_fsm_0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "2'b01";
attribute ap_ST_st2_fsm_1 : string;
attribute ap_ST_st2_fsm_1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "2'b10";
attribute ap_const_int64_8 : integer;
attribute ap_const_int64_8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 8;
attribute ap_const_logic_0 : string;
attribute ap_const_logic_0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "1'b0";
attribute ap_const_logic_1 : string;
attribute ap_const_logic_1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "1'b1";
attribute ap_const_lv1_1 : string;
attribute ap_const_lv1_1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "1'b1";
attribute ap_const_lv32_0 : integer;
attribute ap_const_lv32_0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 0;
attribute ap_const_lv32_1 : integer;
attribute ap_const_lv32_1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 1;
attribute ap_const_lv32_4 : integer;
attribute ap_const_lv32_4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 4;
attribute ap_const_lv32_F : integer;
attribute ap_const_lv32_F of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 15;
attribute ap_true : string;
attribute ap_true of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "1'b1";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco is
signal \<const0>\ : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR ( 1 to 1 );
signal ap_rst_n_inv : STD_LOGIC;
signal ap_sig_bdd_66 : STD_LOGIC;
signal ap_sig_bdd_79 : STD_LOGIC;
signal int_sine_sample_V : STD_LOGIC_VECTOR ( 15 downto 0 );
signal nco_AXILiteS_s_axi_U_n_10 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_11 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_12 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_13 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_14 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_15 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_16 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_17 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_18 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_3 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_4 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_5 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_6 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_7 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_8 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_9 : STD_LOGIC;
signal \^s_axi_axilites_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sel : STD_LOGIC_VECTOR ( 11 downto 0 );
signal temp_V_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none";
begin
s_axi_AXILiteS_BRESP(1) <= \<const0>\;
s_axi_AXILiteS_BRESP(0) <= \<const0>\;
s_axi_AXILiteS_RDATA(31) <= \<const0>\;
s_axi_AXILiteS_RDATA(30) <= \<const0>\;
s_axi_AXILiteS_RDATA(29) <= \<const0>\;
s_axi_AXILiteS_RDATA(28) <= \<const0>\;
s_axi_AXILiteS_RDATA(27) <= \<const0>\;
s_axi_AXILiteS_RDATA(26) <= \<const0>\;
s_axi_AXILiteS_RDATA(25) <= \<const0>\;
s_axi_AXILiteS_RDATA(24) <= \<const0>\;
s_axi_AXILiteS_RDATA(23) <= \<const0>\;
s_axi_AXILiteS_RDATA(22) <= \<const0>\;
s_axi_AXILiteS_RDATA(21) <= \<const0>\;
s_axi_AXILiteS_RDATA(20) <= \<const0>\;
s_axi_AXILiteS_RDATA(19) <= \<const0>\;
s_axi_AXILiteS_RDATA(18) <= \<const0>\;
s_axi_AXILiteS_RDATA(17) <= \<const0>\;
s_axi_AXILiteS_RDATA(16) <= \<const0>\;
s_axi_AXILiteS_RDATA(15 downto 0) <= \^s_axi_axilites_rdata\(15 downto 0);
s_axi_AXILiteS_RRESP(1) <= \<const0>\;
s_axi_AXILiteS_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ap_sig_bdd_79,
O => ap_NS_fsm(1)
);
\ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => ap_sig_bdd_79,
Q => ap_sig_bdd_66,
S => ap_rst_n_inv
);
\ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(1),
Q => ap_sig_bdd_79,
R => ap_rst_n_inv
);
nco_AXILiteS_s_axi_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi
port map (
O(3) => nco_AXILiteS_s_axi_U_n_3,
O(2) => nco_AXILiteS_s_axi_U_n_4,
O(1) => nco_AXILiteS_s_axi_U_n_5,
O(0) => nco_AXILiteS_s_axi_U_n_6,
Q(0) => ap_sig_bdd_79,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
ap_rst_n_inv => ap_rst_n_inv,
\out\(15 downto 0) => int_sine_sample_V(15 downto 0),
s_axi_AXILiteS_ARADDR(4 downto 0) => s_axi_AXILiteS_ARADDR(4 downto 0),
s_axi_AXILiteS_ARREADY => s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARVALID => s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_AWADDR(4 downto 0) => s_axi_AXILiteS_AWADDR(4 downto 0),
s_axi_AXILiteS_AWREADY => s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWVALID => s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_BREADY => s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BVALID => s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_RDATA(15 downto 0) => \^s_axi_axilites_rdata\(15 downto 0),
s_axi_AXILiteS_RREADY => s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RVALID => s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_WDATA(15 downto 0) => s_axi_AXILiteS_WDATA(15 downto 0),
s_axi_AXILiteS_WREADY => s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WSTRB(1 downto 0) => s_axi_AXILiteS_WSTRB(1 downto 0),
s_axi_AXILiteS_WVALID => s_axi_AXILiteS_WVALID,
sel(11 downto 0) => sel(11 downto 0),
temp_V_reg(15 downto 0) => temp_V_reg(15 downto 0),
\temp_V_reg[11]\(3) => nco_AXILiteS_s_axi_U_n_11,
\temp_V_reg[11]\(2) => nco_AXILiteS_s_axi_U_n_12,
\temp_V_reg[11]\(1) => nco_AXILiteS_s_axi_U_n_13,
\temp_V_reg[11]\(0) => nco_AXILiteS_s_axi_U_n_14,
\temp_V_reg[15]\(3) => nco_AXILiteS_s_axi_U_n_15,
\temp_V_reg[15]\(2) => nco_AXILiteS_s_axi_U_n_16,
\temp_V_reg[15]\(1) => nco_AXILiteS_s_axi_U_n_17,
\temp_V_reg[15]\(0) => nco_AXILiteS_s_axi_U_n_18,
\temp_V_reg[7]\(3) => nco_AXILiteS_s_axi_U_n_7,
\temp_V_reg[7]\(2) => nco_AXILiteS_s_axi_U_n_8,
\temp_V_reg[7]\(1) => nco_AXILiteS_s_axi_U_n_9,
\temp_V_reg[7]\(0) => nco_AXILiteS_s_axi_U_n_10
);
sine_lut_V_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V
port map (
Q(1) => ap_sig_bdd_79,
Q(0) => ap_sig_bdd_66,
SR(0) => ap_rst_n_inv,
ap_clk => ap_clk,
\out\(15 downto 0) => int_sine_sample_V(15 downto 0),
sel(11 downto 0) => sel(11 downto 0)
);
\temp_V_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_6,
Q => temp_V_reg(0),
R => '0'
);
\temp_V_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_12,
Q => temp_V_reg(10),
R => '0'
);
\temp_V_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_11,
Q => temp_V_reg(11),
R => '0'
);
\temp_V_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_18,
Q => temp_V_reg(12),
R => '0'
);
\temp_V_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_17,
Q => temp_V_reg(13),
R => '0'
);
\temp_V_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_16,
Q => temp_V_reg(14),
R => '0'
);
\temp_V_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_15,
Q => temp_V_reg(15),
R => '0'
);
\temp_V_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_5,
Q => temp_V_reg(1),
R => '0'
);
\temp_V_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_4,
Q => temp_V_reg(2),
R => '0'
);
\temp_V_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_3,
Q => temp_V_reg(3),
R => '0'
);
\temp_V_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_10,
Q => temp_V_reg(4),
R => '0'
);
\temp_V_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_9,
Q => temp_V_reg(5),
R => '0'
);
\temp_V_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_8,
Q => temp_V_reg(6),
R => '0'
);
\temp_V_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_7,
Q => temp_V_reg(7),
R => '0'
);
\temp_V_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_14,
Q => temp_V_reg(8),
R => '0'
);
\temp_V_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_sig_bdd_66,
D => nco_AXILiteS_s_axi_U_n_13,
Q => temp_V_reg(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_nco_0_0,nco,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "nco,Vivado 2017.3";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_S_AXI_AXILITES_ADDR_WIDTH : integer;
attribute C_S_AXI_AXILITES_ADDR_WIDTH of inst : label is 6;
attribute C_S_AXI_AXILITES_DATA_WIDTH : integer;
attribute C_S_AXI_AXILITES_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_AXILITES_WSTRB_WIDTH : integer;
attribute C_S_AXI_AXILITES_WSTRB_WIDTH of inst : label is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4;
attribute ap_ST_st1_fsm_0 : string;
attribute ap_ST_st1_fsm_0 of inst : label is "2'b01";
attribute ap_ST_st2_fsm_1 : string;
attribute ap_ST_st2_fsm_1 of inst : label is "2'b10";
attribute ap_const_int64_8 : integer;
attribute ap_const_int64_8 of inst : label is 8;
attribute ap_const_logic_0 : string;
attribute ap_const_logic_0 of inst : label is "1'b0";
attribute ap_const_logic_1 : string;
attribute ap_const_logic_1 of inst : label is "1'b1";
attribute ap_const_lv1_1 : string;
attribute ap_const_lv1_1 of inst : label is "1'b1";
attribute ap_const_lv32_0 : integer;
attribute ap_const_lv32_0 of inst : label is 0;
attribute ap_const_lv32_1 : integer;
attribute ap_const_lv32_1 of inst : label is 1;
attribute ap_const_lv32_4 : integer;
attribute ap_const_lv32_4 of inst : label is 4;
attribute ap_const_lv32_F : integer;
attribute ap_const_lv32_F of inst : label is 15;
attribute ap_true : string;
attribute ap_true of inst : label is "1'b1";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_AXILiteS, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST";
attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARREADY";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARVALID";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWREADY";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWVALID";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BREADY";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BVALID";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_AXILiteS_RREADY : signal is "XIL_INTERFACENAME s_axi_AXILiteS, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RVALID";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WREADY";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WVALID";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARADDR";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWADDR";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BRESP";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RDATA";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RRESP";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WDATA";
attribute X_INTERFACE_INFO of s_axi_AXILiteS_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WSTRB";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco
port map (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
s_axi_AXILiteS_ARADDR(5 downto 0) => s_axi_AXILiteS_ARADDR(5 downto 0),
s_axi_AXILiteS_ARREADY => s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARVALID => s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_AWADDR(5 downto 0) => s_axi_AXILiteS_AWADDR(5 downto 0),
s_axi_AXILiteS_AWREADY => s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWVALID => s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_BREADY => s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP(1 downto 0) => s_axi_AXILiteS_BRESP(1 downto 0),
s_axi_AXILiteS_BVALID => s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_RDATA(31 downto 0) => s_axi_AXILiteS_RDATA(31 downto 0),
s_axi_AXILiteS_RREADY => s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RRESP(1 downto 0) => s_axi_AXILiteS_RRESP(1 downto 0),
s_axi_AXILiteS_RVALID => s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_WDATA(31 downto 0) => s_axi_AXILiteS_WDATA(31 downto 0),
s_axi_AXILiteS_WREADY => s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WSTRB(3 downto 0) => s_axi_AXILiteS_WSTRB(3 downto 0),
s_axi_AXILiteS_WVALID => s_axi_AXILiteS_WVALID
);
end STRUCTURE;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-2/src/structure/Var5.vhd | 1 | 1482 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Var5 is port(
W,X,Y,Z: in std_logic;
F: out std_logic
);
end Var5;
--
architecture structual of Var5 is
signal nW : std_logic;
signal nY : std_logic;
signal nWX : std_logic;
signal nWXY : std_logic;
signal WXY : std_logic;
signal T : std_logic;
signal nT : std_logic;
signal WZ : std_logic;
signal nWZ : std_logic;
component AND2 is port(
a,b: in std_logic;
z: out std_logic);
end component;
component OR2 is port(
a,b: in std_logic;
z: out std_logic);
end component;
component NOT1 is port(
a: in std_logic;
z: out std_logic);
end component;
component NAND3 is port(
A,B,C: in std_logic;
Z: out std_logic);
end component;
component OR3 is port (
A,B,C: in std_logic;
Z: out std_logic);
end component;
begin
M1: NOT1 port map (W, nW);
M2: OR2 port map (nW, X, nWX);
M3: AND2 port map (nWX, Y, nWXY);
M4: NOT1 port map (nWXY, WXY);
M5: NOT1 port map (Y, nY);
M6: OR3 port map (nW, X, nY, T);
M7: NOT1 port map (T, nT);
M8: OR2 port map (W, Z, WZ);
M9: NOT1 port map (WZ, nWZ);
M10: NAND3 port map (nWZ, nT, WXY, F);
end structual;
architecture behavior of Var5 is
signal WX : std_logic;
signal WXY : std_logic;
signal WXY2 : std_logic;
signal WZ : std_logic;
begin
WX <= (not W) or X;
WXY <= not(WX and Y);
WXY2 <= not((not W) or X or (not Y));
WZ <= not(W or Z);
F <= not(WZ) and not(WXY) and not(WXY2);
end behavior; | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/c47de30114c88d53/ip_design_rst_ps7_0_100M_0_stub.vhdl | 1 | 1907 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:29 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_rst_ps7_0_100M_0_stub.vhdl
-- Design : ip_design_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2017.3";
begin
end;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/LIFO.vhd | 1 | 2389 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
entity LIFO is
generic(
-- address bus
m: integer := 5;
-- data bus
n: integer := 2
);
port (
EN: in std_logic;
-- synchronization
CLK: in std_logic;
-- write/read operation type
WR: in std_logic;
-- read data bus
RB: out std_logic_vector(n-1 downto 0);
-- write data bus
WB: in std_logic_vector(n-1 downto 0)
);
end LIFO;
architecture Beh of LIFO is
-- word type
subtype word is std_logic_vector (n-1 downto 0);
-- storage
type tRam is array (0 to 2**m - 1) of word;
signal sRAM: tRam := (
(others => (others => '0'))
);
signal head: unsigned(m - 1 downto 0) := (others => '0');
signal data_rb: std_logic_vector(n-1 downto 0);
signal data_wb: std_logic_vector(n-1 downto 0);
constant Limit: unsigned(m - 1 downto 0) := to_unsigned(2 ** m -1, m);
Begin
SH: process (CLK)
begin
if (EN = '1') then
if rising_edge(CLK) then
if (WR = '0') then
if (head = Limit) then
head <= (others => '0');
else
head <= head + 1;
end if;
elsif (WR = '1') then
if (head = 0) then
head <= Limit;
else
head <= head - 1;
end if;
end if;
end if;
end if;
end process;
data_wb <= WB;
WRP: process (CLK, head, data_wb)
begin
if (EN = '1') then
if rising_edge(CLK) then
if WR = '0' then
sRAM(to_integer(head)) <= data_wb;
end if;
end if;
end if;
end process;
RDP: process(CLK, head)
begin
if (EN = '1') then
if rising_edge(CLK) then
if WR = '1' then
if (head = 0) then
data_rb <= sRAM (to_integer(Limit));
else
data_rb <= sRAM (to_integer(head - 1));
end if;
end if;
end if;
end if;
end process;
RB <= data_rb;
end Beh; | mit |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/VGA_play.vhd | 2 | 6134 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 17:12:10 11/26/2013
-- Design Name:
-- Module Name: VGA_play - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA_play is
Port(
-- common port
CLK_0: in std_logic; -- must 50M
clkout: out std_logic; -- used to sync
reset: in std_logic;
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0';
-- following are debug ports
--hclk: in std_logic; -- hand-clock, for debug
--wctrlin: in std_logic_vector(0 downto 0);
--KEY16_INPUT : in std_logic_vector(15 downto 0);
--LED_output : out std_logic_vector(15 downto 0);
--mout : out std_logic_vector(0 downto 0)
-- fifo memory
wctrl: in std_logic_vector(0 downto 0); -- 1 is write
waddr: in std_logic_vector(10 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end VGA_play;
architecture Behavioral of VGA_play is
signal clk: std_logic; -- div 50M to 25M
signal vector_x : std_logic_vector(9 downto 0); --X 10b 640
signal vector_y : std_logic_vector(8 downto 0); --Y 9b 480
signal r0 : std_logic_vector(2 downto 0);
signal g0 : std_logic_vector(2 downto 0);
signal b0 : std_logic_vector(2 downto 0);
signal hs1 : std_logic;
signal vs1 : std_logic;
component char_mem
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
end component;
component fifo_mem
PORT (
-- a for write
clka : IN STD_LOGIC;
-- enable, 1 is write signal
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- b for read
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
signal char: std_logic_vector(7 downto 0) := "00000000";
signal pr: STD_LOGIC_VECTOR(0 DOWNTO 0);
signal char_addr: std_logic_vector(14 downto 0);
signal caddr: std_logic_vector(10 downto 0);
begin
-- waddr <= "0000000" & KEY16_INPUT(11 downto 8);
-- wdata <= KEY16_INPUT(7 downto 0);
-- debug code
-- LED_output <= "0000" & KEY16_INPUT(11 downto 8) & KEY16_INPUT(7 downto 0);
-- mout <= wctrl(0 downto 0);
-- process(hclk)
-- begin
-- if(hclk'event and hclk = '1') then
-- wctrl(0 downto 0) <= not wctrl(0 downto 0);
-- end if;
-- end process;
-- store char
ram: char_mem port map(clka => clk, addra => char_addr, douta => pr);
-- display cache
cache: fifo_mem port map(
-- a for write
clka => clk,
-- enable, 1 is write signal
wea => wctrl,
addra => waddr,
dina => wdata,
-- b for read
clkb => clk,
addrb => caddr,
doutb => char
);
-- cache addr 5 + 6 = 11
caddr <= vector_y(8 downto 4) & vector_x(9 downto 4);
-- char acess addr 7 + 4 + 4 = 15
-- last 2 control the display(x, y)
-- first char control which char
char_addr <= char(6 downto 0) & vector_y(3 downto 0) & vector_x(3 downto 0);
-- -- this is only for debug
-- process(reset, hclk)
-- begin
-- if reset = '0' then
-- char <= (others => '0');
-- elsif hclk'event and hclk = '1' then
-- char <= char + 1;
-- end if;
-- end process;
-- 25 MHz Sync
clkout <= clk;
-- 50 MHz -> 25 MHz
process(CLK_0)
begin
if(CLK_0'event and CLK_0 = '1') then
clk <= not clk;
end if;
end process;
process(clk, reset) -- ÐÐÇø¼äÏñËØÊý (800)
begin
if reset = '0' then
vector_x <= (others => '0');
elsif clk'event and clk = '1' then
if vector_x = 799 then
vector_x <= (others => '0');
else
vector_x <= vector_x + 1;
end if;
end if;
end process;
process(clk, reset) -- ³¡Çø¼äÐÐÊý (525)
begin
if reset = '0' then
vector_y <= (others => '0');
elsif clk'event and clk = '1' then
if vector_x = 799 then
if vector_y = 524 then
vector_y <= (others => '0');
else
vector_y <= vector_y + 1;
end if;
end if;
end if;
end process;
process(clk, reset) -- ÐÐͬ²½Ðźţ¨640+ÏûÒþÇø£º16¿Õ+96µÍ+48¿Õ£©
begin
if reset='0' then
hs1 <= '1';
elsif clk'event and clk='1' then
if vector_x >= 656 and vector_x < 752 then
hs1 <= '0';
else
hs1 <= '1';
end if;
end if;
end process;
process(clk, reset) -- ³¡Í¬²½Ðźţ¨480+ÏûÒþÇø£º10¿Õ+2µÍ+33¿Õ£©
begin
if reset = '0' then
vs1 <= '1';
elsif clk'event and clk = '1' then
if vector_y >= 490 and vector_y < 492 then
vs1 <= '0';
else
vs1 <= '1';
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '0' then
hs <= '0';
vs <= '0';
elsif clk'event and clk = '1' then
hs <= hs1;
vs <= vs1;
end if;
end process;
process(reset, clk, vector_x, vector_y) -- X, Y ×ø±ê¿ØÖÆ
begin
if reset = '0' then
r0 <= "000";
g0 <= "000";
b0 <= "000";
elsif clk'event and clk = '1' then
if vector_x > 639 or vector_y > 479 then
r0 <= "000";
g0 <= "000";
b0 <= "000";
else
-- play-ground
-- play-ground
if pr(0) = '1' then
r0 <= "111";
g0 <= "000";
b0 <= "000";
else
r0 <= "000";
g0 <= "001";
b0 <= "001";
end if;
-- play-ground
-- play-ground
end if;
end if;
end process;
process(hs1, vs1, r0, g0, b0) -- ×îµÍµÄÉ«²ÊÊä³ö
begin
if hs1 = '1' and vs1 = '1' then
R <= r0;
G <= g0;
B <= b0;
else
R <= (others => '0');
G <= (others => '0');
B <= (others => '0');
end if;
end process;
end Behavioral;
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_comps_builtin.vhd | 19 | 32006 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
bdlZLEAewQqpv1o7OoBr4R377V8Hk5Fd8+q/Az6G9nxroFaOnD3V9+lWQZaiTQ+UR8tYlBixiDT3
2rrbvlUYqg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
PNj5XhRRPylbuLUnq16m36512+Iu+tuxUNOB5vui/U9Vyxliy5LDYUjGyTrkosJ5RLmSfgYfmdaq
x3GXyG6MVOiZo15XiDmGz5Xa3WMM3TuUhfpzNItvR+cjVJcfSX1Vpo9/m4Gf2HbgWDY8/uge9Yz+
pdDWTg9IqOS1f9m0bhc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tfy6e9ewB1av8IAVBQg5F0wJVpezM47U5T38niEmKqoHE2EAQIsVtLXdGuC0EVCv8iR27vcg17Oa
mBfBXWB60tzPu8Q6DSJi1RmV8OgW+NgUvCiTMpLKqqsw6FnhMEK3lQVXfOtnfyh9msybPw9byzXC
dambJMmCpKtH2TBazWP4yb5ww1Nsz/1jL5i1zPiiJqwiUek+yJBHinlLsKOdmxiEOjEIxiuXMNyg
LMJzb839xkVhlMYTWXZYlSQVwwm/sLGnZ2Znntlf9sYBoE6D2vYri/PUGcfI5TqvvhrwG3MMHoTN
rPYZvU5TTqkZ0UHzprP9ZbAAvBMMlhHGjyKLgw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
enscaK3Um9KpWwQm1hA2XwO16XJLOAeYZ3URNnasJSAORmdXiuv1QgNvxstTqRmJdf6aiVcX+SBW
QAS4XOQmaHblVVCTrTFxq+i8/M/uWIiPlKdwfgcbq6W9GDVZEH2g71B4sNE7sbY88daOW+dsFMn8
evKdCCrOhrfApxD2w7E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qn8TdDpu0TmAhfXr6OjdWoz6rfyBW7fFZKyqPOjjqWteCvm3OM0JlharuS1oWtO6vCpto2FAzG/S
BlRFnD+qM3W558gotDG5xKLXH54U8vJ9P7HSKDrDRZfcvgzYnDlLOZYqIhF3QcOp7QlIfdgIFJFF
P1RDJ8d43uSYKR66QV0gPXuT19+tneyhi0YpcaupqD9/Z/vQdGHiorXfqzI+zmAX5/7dF89mvr3v
Pvp32AibqOZJekU7QCnp4VkIAFQi2sNR2R1SirejbeSwa+gfCdYZC/MT0OFTfQjM0uxBSK/I4IyT
gWZgfuPijqASxDrsrURmKezc4hgCDujIExBWaQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21952)
`protect data_block
3720zAurmsgjW60V7hP5jyZoOpDRGQjPNH5YywQSPELWgeGQ3NBAz8+c7rHYAMIMsNuxXkEFHaCU
zPPcMH9cI1cAXEs+sh30eU1utZfJbmafnIR9yELpklT+rYow/re6dAYb4N7SrQdoR6JZr/5Sxwkm
x3a+e1tgc7lo8+A8hVtoxxzdXSn42OPzUYMR92aPt4KBUg5B0UFuH2Ei4qFsnef8lp7YjskaYDm/
Qg4FocOSG6rsaieot3LQwOyMckelT8iqAkNVoHp/BL6isOxgrj0myIL4iWsebM/BSdWwwwoVkJLG
VIE1+y1QTOko8QtMLPhHWitmTX6Y2RyioQZbMl+q/h96g+Ee8IQqb2zBOWe+2kn5RSjfEdkGIzbF
4U+/6JwWsGxAM3XQ9KydfDt2vaNMhEAnJkH/M9wpi/V4sfrPhWbxOcywv4bLn2Zs0f05hJ2D06k7
8kIfxSci/rXxrYVvIZTJTUtL23l6CuQ8/kzneKj2alAxugc3WlCf3PkOrbdRBbVhYCp0XdDmOOZv
qWexDotJZ1mxvJyKKGGObHjJK9F9YBdtZ7w3v6XZkBkszPWBLUQSpYDJHSpbWC7fQpJyPzn3zEfx
2iOWUFfpp0+IjxbwrU2rtXkRPHLReEao0HJQFB9F8Y20sTAbmYRxsKCGm9y4N1fSZ+JRRtVnBMvZ
uRr7xiwtwqjxvFtjjTcfxqQTV6vgIl6ARhoyI/OmZQTwLlwjcwJTMmoVbEvi6afCpjeEwFzcqIJX
GqaydO77nm2Ko2yq4PCjeK8rDJkRxW2NQjZKUGKkHv16POsmYsRu9QQmGDh60viU4GxQBeTbvnVx
ZrKwOw7LlGjp8DYH3QiRMa9p2wMbM2S7M7eoMjIhweqkhrSkKCk7m5LaOHuwa58hF1YGxgDd3bgx
3FzK4ODqrnn4XbB2kyd5cZgqtemFPT+oPj12MSf+KL25YZMk1SN9/Jikm70sGxAz5EcGMVFteXQv
ds0IC0SLXSC4AyHJitmqTqKx3aFfjgAejN75bEsPm6deXVGXib24RNWA2L1dGcwEfpW6riiec6jI
7WR0cqxHFJOVB8FF5DEjjRwon409YIy+qT8do9/bcpFluFw8dZavO6wAdDuYAn5vT49XjB6+C6J9
MTm1fdFSsr5yHLztPOodtf3HH53tMCIOAnEA0i0obsFUcP7RnHL2ZzDQM+FIZp/ikPh4NM84y4bJ
XoB5THsjyKl2a2ycDyZfEM5DrKisbcXQ3/zCkYxMSAF1yTaHf/Wn3475klyRAL91qlr6Q3gaCg7h
sEMnktV+59XRczWudkW0tSuKQnMadBBm7xR2enA1THIH0K8wcBec1Ag2ub9Ke8LP/pa+IA3bGCJp
/9etfHIPaU2RoesBQx3xC9rYIpLeSHKNhtuidMpV++DpA/ENogLn7L9Zo7YSnFVINUh8DnoLCHFa
rgtk1h5joV8n4CH9BBUV2NtkdG06G73AuXJuTntefbmYWxDJJLqle3P0WceE/TFyh4e6u6Ubt7L6
bYfin4mMASxI1GETKKcwE/V/1nyH3/DPmMzNZD7B4+hbZnomfpjFNSYb3aplISPSJlEOs9l/DE+h
kmfjEX8XOKR8ERpctZdjWrikhLha2uniyOYH8yvOKfoehR6DDqm7lS9RHESH9aN8LwGa3WhyRBrO
fYdCDrhVYMKjeRCvCPJtiiy83Bt0XJx10yqSPOAobPNGSQAGRyJqdbycbmAFz3oAXGU5WJW5lKVm
EYxdpJXR4Bi8j3HVmb9gg3iRZ6sfAuWnVX3JvV3mjOlTGvjs0/V0JWU/9ApcHBiUmXNtfU9uvNCP
r/IG+7WeKgMx+Thwjsc1Y152aRB/+I4FicycpmebyY4wCwfEkNcf1fPdqEexQ4KQDsIWn/AkN2T2
aQFzRlgoXKVLMMWI4Q1qzvtsesRGoQ2hsDUutWSkFOVhe9/NNmATmPTeYebDgdcDQ0TKybwDCucG
E1ytzCoICQdGOQjZNYYXuIYfvUfXgtjWFGNcxh3QOeHzMYfjhn5U0lQmgqSmLSrSQyQkhWQm3vCa
ttT3CDToi8X8H7jBXDwiY83xtk42XiTR5mnlI+jSvwrH/Sh8Xyfvh32HHzGY6/97wxcKMCOj384X
KUJayqjha9nMDRtRGuShiWAlQopmcN2iYumlDZEqn7qawlTWzC77O8Hyoc8q0SzbaFiQGKZE8vyt
naOApS3ISWAmDdFs7GFv48o2fkqbVvB2dZrOmx5VJ9FUPYOG3Qz5kAlLKoI1FlyNYmShHpVFicXj
yPuLlp12tcQb5q1YryD4kWutESwP3TigJE0f1FiemklAkXEGpcarguhQ2ic5j/iQ4WU2veOdyH3L
TUCbclgB11LvsTc80XIYoSJIGNB+NIDKJtkvIGN59s5oV6TrMWcwbH0rbYcdBKoixg8HshO6+60x
08XuWAcRTzcnHC/B6P51IR3bKHbMXlz105kPjsFPaLaphFesKGCVLWnqnV9FhvrYOXIRfDilmjKO
TZPBh6M+u3yla3mJkhFPK3DTatBgglOtOGVk4aLWpZzT9a6pb/TBykFF/ixnKspwKNWRuZWECig1
IENmcfz1r2N17Tg9wX73tobIN132Xfe7R1wQufRFnBUR7k0Ga+Zdmw3Hge3PiHU2AcxR1CXvZZHQ
Lc96RnFeQM6re20KiVVaA25e3YoPi19Dx++YBUEylHEwlU3QWKlrFrPH1xCoeYix56vts21MTTR2
QBPZcTwAr5R5l9ipmmWs2QuaoF3roEUcIFgNADHSGF3epgbO0xaCXvUpuTP9AJYvhSmc4w+Sqivn
p2Vw8kNuVswulkgYStXjeWMTLd0mKHoc9ZTPG/bS302vM75biwHRlAnp2bXS7vxsHVmRP0eDpRKQ
RD2Zzw4mG3ubd9d337E7X2CIKhtnSAG4Xa0QOEeIQEOs9KZIQUJEUikN3gjW+UoWE1m0UgBm8U8i
seUri9e94G6BmIem4m8SHTHBV2ShbrHWxuofGnllapRUQ9eNwxBQHllDNytbbUg3C+zQreed5EvC
FAQ9Qhe7qA/ukGNAiFb/EzkzI6u/KEZPvHo1obAUD0jGD4o1ab4q5cvfh4rhnPZ9l7Tn75WmUj1u
ioV+LRlcB0ZUJ4tY9HUOygDACt0nChAoCC7Y/yncTHSwR/wWqVL1kn5X5W0mU1Sz2FpgvvUaqlgU
yy6LNv4z7a1jy88wyDojgKW3PUGUCShF+S3I8TB244ypvIfVMyCEygpzNy+jemnD9IPMKbLOipCP
4U44NzljVgeYHCUe2QfoJlVlre56XA1ORyrWc8tK+yAYOAzjzCpYB/ifzC3XGWKXMw//MsgkwzG3
V9pFMAPu0pEj9GOcOGxvXIolvgU4eYsIpg29UyQi9HA08RZIIG43ZV0L9xPaxr95QLsnoIEAaVRn
hLaxnXUHdoyVM1a60TBRYCD1Uzd1Bwd6e/+hVO60hS+U/TeP7nOAQ57Gq2tbGYSPFJFvEzTDcalT
OOmktXDMRucul7mP09X1IOUT1zyiC9MMKASOz6NS/6qof6B1Vna2VIOGpmLzmlulnMO6U5yAA8rh
+II+qrs1wxqWxRjI3sDMA4KXd5esVII7DjerKTij2c9VE33A67Chm7LEbtppmx54zBpRikc9FicK
sknYk6sVwK3oSTltiRUpWY02lQvIgZPKDVGBfs1DEWVAiWoPwnVMkdqFSzSRaBKwXbndX6UOciO6
5NA6giXUjvPMpxudlC+F6d5EzoBQLxkI88bv/ptWDyEcqPbIiWypCuBuJ/zyAb8qqTqIn20c4SZT
EpG7wiRvEpoNztHXkAqe8mgZFJDUC3CBJ+qYCiTYtkJ8RugkokwUqRvxsWIsecEcRVui6avYmDqc
fhMkOiEAgsB9+J49+ba1L969Cx7u9mB62HsTCy36APl0hPyrM567PpVO1cQJ0SaKIYgMS3HXFiSB
R9wwDuLfpr+n21dCt4XUm11yo91Qblj0sMU5WSLoQ8OEtzcF3JCRHyG3kLk7M+EZy6gf3a8lYSdH
sB6CxGZeq3neDhmAza/u9Oh+X7tBmZVeMvkjWkgeS8e3bKST1seDutn/lLCreujhPX3oRy4kzFRc
kdepGVQ9nV9TI9MKeeH3ngqqpYzaMs2r8uAOZozgDZVcpzMheVEkzsj6yIDkhJaU+yGZswgGadum
tPM5jMsCvroXd11E4jzD2Oqpoj39UWXldOIDlq1VFAuuh/aRMt5T/DBtmAVtF/cVcXn1IT+d9Y1Z
C2yd9602K/9EnjQONmZas6oTZbpSdGcL61ToQ43fTl5oFVZXfFXIgbB/N3dRMDJglybWEFkj+Xn9
NhJ0+WYy/MSVO24vXOwSlqNMuWVk2w4uz1iRZHs7ON2vYt0oCKRG5UfIFz1i2io+7biI8o+OPnTc
baQ5HUhQZWIotBs9vc7NwKZTo1BCM0UXwlBj9SeeMjKBFe38awnuQRUwVij5SAe7cMk+VJGxsK9Q
IH3QyoK5+H2BdGys2EP6blBp+g4p3SbUXzRdS/wjlTg1oDnSQ2QU0BbHs9HjOCkB1YOZRUd6Xwrq
JAf1xBQFtjEvM2AE6dZN//gNaVSEvV+n/u/N4GA80aurPzegF1hwvHOFmWyiR+pO4cl8HasbBT7g
3s9li4+ZAyh2PXtiyYoVbBxICFiNhmKspI1g8yF0MMPimHtCbcTOPN1XUbpDXAeH+B/R57T25Sjy
XW+NDe5wxX5jzeytvCw1o3y5GovNQtUH2oWbTnMBovm6fwNbbNqrzsc8pQuqw0GLT4qX7KPtzdwA
sRgE5Te84R0EGGiOqnogQVheb144BCutJ2Sp1F63cQhy5baPJ5Zdg5bbiZsWxX0r8N40IBBXZm1w
o/O6qUpwSJHiJblej/FiGLWUM/2Q/H2Q7reRjuPlccPYyiFJh7yXeapjIZtbqAZvBz3hKG6nAYL0
gdA3WlqQDt9UKdQkEIBw/BDfFOzC6PIpJfvbW3Op6Q0PV06W/uLfBI8xrHWKmTqD6ugJcu/SNvos
fyLG99n7YPRcUtUdxDLwIaaOIeCdKxcV8clR98H0eZYz9EooCZ9/9vuyNaWeoerF3iYc3kwuVE9P
euB7I1d5R3VzsRENBGw7wP3D9HjGRwl+nJx5QeBsYmIRaZN/37pW3OsSgXHFidX1ujiUWoPEmXRv
eYEcZE2NxiWPX99n6NWvrZZjniS5cxUIAjC4F5GodmJfkNCZ8Ycnk1cW2FBskm0PrlFdWflEPZ8G
LERyC88Iw7JrFG92ELkTyjNntfXPZF6yt4TCNIUT+8uIw/j6dw4nmsIqju1ocZnlWfOfcIT3PMAj
KYS5JtSObBN2gIPGdRppnlOtKTMApUn7hhkuBDUNnovH4ZDUtMKx/lCajRToHMQTJapGuLaS5mK1
e6mihcAculloB++HGN/P/17l3fuxfBI3+1N/3+QdFMTyRfRiB5z9tH+QV0y3IeJITP1+cj1kX3DC
+OuxGtlOy/yeJcJLol/wG3ycKtfzMIVe4uKJZ/rK0qd99xK0gHVvCMiYSrHXUL2jF19gdEYu9pqi
/CapVPpiDKgnPPQY8enVQxu/xKHbUucTbvYxDs8ZFxyMJO7kY788k3R+uLhhMCFiiZGsuhAoZZW2
UyCiQEH9mcvgZti/ujx4hj3uwOoEhbMfm+9Q+35LMnJKw+nt4r+FXUBAbQmtCzwUU3Y+MJEbil7Q
mZJttA13gglN1zTF69mSkdYm6odkEDu/X04AVIiuIPj15fYWm/hjAvzw/ocVMx3pmGSvEcg3NnS0
imzSmu0jE5Sj31NBvZXMKE/Rv1Mz8vub7uQRX4J85UEFtsgZKW64dqWM/TAsIyAUg5j3icNKv1Ry
MwcaOaru385QwX0mbYpXrvN4AcPTBTQ5lcz5yH1+4VCas0t2ms6oiMHoOrnjtZep0LjcUPa3rZa5
PEmhd5/qHh7YePO8LteqyTaVHlEBFi3fpejw9TNFjr4N5qlMem5LFbimrtDlQkLROo8QdAUuyy6x
CwmQxTt85x0g8jBMj2Ny7nBulS6XU0oK6iLglS5d5AdwclD7E2jGOQSyPHpLNycEwxGTmZQENqz0
1dLIoBnYLBA7Fv6y2HJERAbLRkq/ksoAEfvc03BYZVtoZTn6QpOTg40pIomiq3qPVLJgPofWhWNR
gBbB2Xq++v80tbYn2n0whbVTM1E0cGZAXH2nVTFDejA1ekIaFJp8XX+Z8ABVXkUY1mFB4v0EM8iv
9m6JwqhJE93/sFkklVgAUVPf21QZxA4/FWcJwBB4l45BRtMkpYa76Dz8mxKhm7yi2ugaN3/PYYgd
c8lYJU1neYCarNFf/9vTygH+ksuRQKY61pmq6vhxM/sz61TUDO9Q2UeSjk78xp3VW9eNd8CgcYPF
8/53waLX8+mqI4DgAs89PpXppVoYmlbvUTPDtRAZDIkGkUMdCMQTPoCZOm1/Pfx6o19rzxo0BpcP
aSyyYQWP8xkFXJ0Kpyx/4eDGYCCgxMFeGp2jRaZc3BFwq47vEfpsvyEBV3oI90awg6VamehV71I0
U1OGbyASZEKxddqC2X/aw+dMXii6Vys0sXhKicGmN3w0hmePO9ZR26q8HQNvW5PFtxAf3laxAz8m
G6D7yAwAsu1waN/OUudOOV+kvduZRN3ecjhL75hQcKapzEf7y9GI2l7VX2EHSvEHhK1KXNoR22bQ
UNvHWuh5sHPnsLgJaxBODRbfq1C+0s+W1way78EHvGT0hZ+SdefcWm/3OFSv9ZP9dMpLyvKWnXw6
QggMCJc2CZH4qIZl1BCCEmhdwSVBp7smGGxAWMelwWE+BdGWa4/o7fuKV85VaASQ5bCL6tF4yV9S
JZOzI6E9vbQyATvRlfoZaFkv2n+1DZR80ilThA9+GIZBVYW9JAgbX2xuttXe1vwA/sQfG1U7wwDg
KYAliOC18LozFOVti6UFDP7rn29izMYOAcwvBpz0VREB2I18puLNpRn3dm+hjG3O+RTdDRY9S4Ig
sXdjeKGPXJo4ARrMtxwG7WzBqhofJgq3I0M44z9+C02FLsHs+WziIgDmm8nmfZgeJqB9GVCWhcSE
CJY2uIJs2iIz8CvWCf/Dao6hwZWCdeEgR7jqNu/QawaJSDheX07ehxz/t3rzKCW53zsoglfLdTaL
/LG3Uira9vekJ4slfXaIS05Rfggg6e0ucvqCGyniFp9NFRERcFPzT4nljolwRwgQYP5kwDClTaF5
c1xGWOQyy1TN40/QNX9Z4gEp5eYfdnwrwSa+FAMa/+pPEuc90h2vgKo3252zIBqry1e8l0rHROWN
tZJeZ/JS1ji6RDQSN6LPhkZzcPgeFrDsg41mnP/vMltaiNCbesTvWAy6Rv4KTv/73fGlNggMIZ91
dVEBUdmJoXPEKxSnPRp/DHB0t5aNyN0Z2Qm1xJP8AaTIbnL/ppWzENpiLa/MJAbJ3lOcXqLFsZq6
mYKs2KD9ilz1FyUeGV9lf1U8rEsjea2oXbe5WA5FYcAevyogtk8MXAzDmevVgRrECIY2Fo2MoFjI
JUvsGiw6fw8eMKwP2dtKUMzi/znjtLREZEzTfL5HDpAGjOyGi6u7r7kI7w+NcguZdEeCCJSHCjjm
/boo3Nh14xPjzr8dtN59hubLuHw0cJdvllU45+PAerJostVptc3oAcYEcCCHMbDl1wGb+kNWgAQc
GwNtad8SrZmO0YqWgdeZgOXECBgxI207GgNd3DLVyeQihHK+y6ndQDld1uMrXL5wYi2XuEzDcir6
TkGZjeeVOBwpER2LhPh+rO+KgoyI61+T+p+ZCbSObQoaR3Oq/dKqbckkK77kbg34T+K1Ud61WuT8
GACPhiT3Mfa3JOq2AzROAGo3SdtpkhaB9xahWbra6AfoRhW5MfdeOMfqH+wIU35FBNcPRfq0OsaA
mjpBEr6MD6+fG3G2w98DgqD/m63NR2MU0oCUDSqoAMQpd/DPEWxF+XKr2fk6aNRVnQKqBT4yWLYw
7T5yhkgP0oCEr/aSDMBGmq/Ui1nGT3cIYr0Jr2IMwM1V8x6PI1XjnplLj7lXK7pdNO9bLWDbYeUZ
Resbmvu3/1Ll8bUybnXzSB8l34h7ATijBiTQ6ldY+6PrSassHU7WlXFNLqFASHYcjkTMFIFO1dvL
FPd6r2I3vKCowdWa/ot8p+6Bu4c4kS04tc+QGBKJ+f1Iw70Jcnl/QWSf0EkNdJJZopJileyq8L+q
PEOp7MvXEh/qfM20Fip0ypqBUmkmN/V7ELEci5N4z9ZU8UMU8cMnTX42HpzOkXrnfvGFtm6dHXQW
vlBLqVsKUP6GabSjkTCUI6qtj7R18cmflsd28y3HASGroQUNCi7+t5S2gOr70tBi2vykUpeXL8UH
OSKOMkXmKiInX93QXaqzQyjD3H0zrrhrYvmKm7OOSUkDpuTARCpSpueAtSENWskyyMgdkG+LVVmM
p9L32lt6uwdXZhsN2KOXKsescvRXHBBkLU01QurEWU9nMz/Wxn1hmvI8SpvGibLRawS+1XM/1OJO
VMvYhjaKWhyhiPgguuFwiIPoQBiWBy3tO1vyma0dZEkYtfRc5mVkA3Wbc6HP9ynL8O/6wGOxypFg
GBGkshRC5Q5F9z1x5w4mLx4cmRiTwCcyXMtWKbSZEM7lO2vSC+ABhVPP7thTvZfwBj9VYt9AOoaG
xekEXIagM5Vap+AhhnBUTHCNp6IKU5SL0mcq5KZwJi97/yMr6Kl6WrxF+OPZ6uLhuNhTmXBbgVAM
FWp3SMw+DPS3HLBXioevMPXRjfahQatzvIr2yELquRu5VCqMrK/s4Yy98pmFQq2COZj669hCE9x7
W/W1XPtLBPUSV9Bkogcv3q9GyvStwlV2FpTtwV1ZMKfwGdp2GFDuJf6HyOX0woEctn1/St8NPPjr
GaI0nXP1RbBgzyBQylauzSojLDh8zfETA14i0rJYyIaA1379fWBw/ioWedKGXOXPx6qdHynnv62n
yu8DzP8S97hM6DDyt44o40hcuA78Fmp1Pejl2r540NtJjB6oUxFE8QTCAQ55sxY0mu2D9ufOVKYs
7nB78gzeyJa2eUALVLPZ/Sl/dSZDkfyB3BwEo6QScemDy3XK9/Mg9NcIdFe+1jYbi/Nuzy2PnKzh
ThIoS0eZ8NEON/31qtj3Xhqrhk/t8yYu0DwDDGFyIwr/I3VQ3irH7vOSw+33Rb7cSPGRfIlPG6GX
IMcjcanXn2XyS/7fagZ5nMVq3V6U4QeW2jFvrO0zP7duEwAWT5Ra6f/mEV2pzAt/C/4S8u0tSGNc
cuF3ZyZZZ7cmS3ijoMSv97uHpLgQM0+cEOYn3VxCUPNjRUmqAQ2i5f/dN4uzguGPUMFTZEaWutUr
rADoIZ9CqSXMYbAUrKk6JOz6XIP/K25YBo5ghK7YfQT6rlTPIYCqK1UPeSW4GwAk1f907S2y9ARo
hlbmElOY2S1ffKgJ5M5obTy8z+jf4b1sRRT8rirmlCukXBVFcjcwFgMCVaztyVpWL/uzRfofjYq9
EozYJ6Y5Mql+3zJmWnEG/a+LTpCSQeildITbEHZEn+8AIeXTGJLQNLf1oZjULeHidMT8Y7scY3I8
5TLXqFksBK/3UpQl9vJfXmbgWDg/1uS/E2dMfTqgjpxxHRJIGZlyoyXzaiPFNzPxQZ9ah5qHt+48
oihEMNkcXiwurHMMFGUPaOkbAlpDFlcvqSNRqwyG1ScwSYUEYvACQbVAMFN465d2sV9LgCzrYTZt
Oh4mvJW8qBjRhqwboMgCdXndhhF+mvdMSI+UHuNJnFcOsfAFdo03KxLd2MlTBKnbbmgqqM18/VOK
zFYJ3NVDOqsSA8bfFUcri5LfnhSkYQ+BIRgEBf3ZVvHQyq/KsSvKPMjHETPzB3pJYIA0w5PYSsnm
o/pfHQpz7Ds9FX1SmkibYPgvNLmRwO29iaiyhRl0QxX3xyplvfb9R7vGYi7qaujUaBXYHCdZXQju
fyS1Nd7SQUxkMiT7Lvn4Z9NEnRnPtvz/p9BkytHG08XSj5qPxTZggBZp7UvXxhWFKzD5GjHztGgA
4SDikRcRGiRh5TYsGGJbVRBYo3+YprwblKK68iraL0p/q6TZRZysbEb/jmIfYTHSyi8x5p5JmiSX
cU3H6u+Q3/pLIH2Z7AVeR+Huao490TikIM/q75cUa5RRKPgb06HnjSV3BwaMJa5Bp3bImZNZngJ8
YW7TAeWNwAi5T6AA0nhzlPfTjL5mluTvHU5LMfbu5lXrfpoZUPLjHpzU8Hv594fNR5DgGtGyPScN
WfdS+Wb4+G2qV9ixJbEMFRU78APCHk/yI/MMEVBYcVz9xY9Fv+jm6iwiLBjng5BtnF24Vrn+8Lcl
KEB1zdkD8tnLJvOXnkiq6E7f1zlhYXStGY1mVsKxeLYMNCVFe07l8SEcLz58M6Cxfgkt/UiosQwF
t726ArOlrmDwTgxENsX6pcsxWCDHpBlAAoN69LVyIrl99qqRKZTVlNw8f2hpjFyYdaholTLI7DCG
kdmRZuw/cE/6XK5Uw+JqEHt0iMcR7M+HsbFBScW75OIOycMguAlzGYMUHjwvml71/8M4autwy1WP
eZnpnr5ZM1+Mgd+DSTjOnTYGrugsbmv2arqvjqS01GqiXT9iz0NnhtRfNoVrJJU6xte3BphgD8N3
Yjai/Wsk2yqaVmUzSUKTF/nodbBbC+KYtJpTURverPqwF88KSCnxrf+xZq0YfTqRrtCy5moACZAd
vlyvzvIB9iMQFddBagi7W94V1x4Jcn/+L8lYR5GleE1RLEEenPCXgzKfnQOJ8AhW0YfRQXBrQaga
XTJrBf0F7lOyMKoRlYEdISYjbIyIC27nNBUBWsUaRzdh+8xXijx0FJsfy8Wkk54Ofqh+v/GJ67gY
9n+rabMChPC8ViJT6onfrTRXwcy0Pm7RAskQUgxZcKhm5bhkgViaP2HJu0QOJDLnL1Lbck/dSBzC
S8tRzwJDnLEeQiUjBXeagMxDMXcjOoq4Ml4SKww4rzfogI31mrDNXcCcWXaYsV6oKxKO+9xC2aYY
FqcOR78Iikvs0/HSRrahcAGRNbJu9cxhrPPERhc4OsGdi5fNKzyf30+lUb2d+xMo3tFwnD5klZYt
5AXbFBPZI2z5fRQvRIldtfb0I5fvxpaS2lr0M6zbv3suJ0t7zLgPKtHHxtsUSe5whA3dvGPzHjqA
DSqwDbdVpCGjEL748sL2YpucLXxjNr9Ia2QH93Y0OuVRX2HWC5xFddZS6Tr8MCVDBPArdZhc3zzf
WCfiZwhuPUHv8Ln1rJtPpO/tL04JcDMCKiXufz2xvov9JvSjZGQi2zMxBy58sB8wYgLm/z4AZvbz
Xta9S406J+FcpTKXFN08p6SVCxSVixDoLZmaEoog2aXut8zIP0H8MORLTZN5T2eAnWalfXfvd8e7
WV1HtL16y0PtF4Xm89+sFtmqgGB0ymtRqP+SH0oMMxWWKxWjYHXUISSq0l0mj6GlW1dGNy20dvTX
U4ULomm9+zXl40ddsz5R1BsGfSuI6aNLc+4UwZzFJjbSq0X0Bc+jrjZRvOO4r1PnfwqaYBUPuKwv
47GSmVkWk/sO8J1/PdUE/1YU+51d5DYOUSStX18FWFoXRiofEDJaHXY2zfAXcPJvirm9xlCGGpAE
ynU1FuPJGkNdKQoRPmZXy3wKAyWEVI3DEFcahHzCNKlVKyOms+5Odc7CowlROkmaI9EqU9y47qM2
v6jh91ngCoOJZOIl9ibUavPLvbHkTeQzzlRzl4dwFpoSSNbMVDh99ZLiNJtjZk432tv+nUI16F1f
acAKUwFXz1D+l24ga2Ou2dMctni3cKvLjUKnpDt6Hy8bWTsYsMW2iaumvQG/18ZW5NOFcWbzGCbZ
mxSVfpLIj4Ssv6eDaCsEXizN/zscQG8zz+Mn9zGAo3IfCPiMvYxjtTg4szGxF9C2bRYHS1+oAfME
wcK3XXXqzYcNDTHWs+hQq5ns9+ZHbFwWs3oqNMPe25yoZ6U15+dX8q/YYTu/eiUxJ1O+GRxS96rN
/OxfrihMAb5fPTzWrwezXfdpMOV9lJMMJULwFhc/rYjSEtFL0z2qOtVHm8y8WCbmlM5H0OtRc4g1
OmzwMYiavoJJc1baltg0iCcZNd7hGhEKFz6izgZnGDh2mKzH9K4wcCgCHWOZ/0Ls3L/RK3kd7ZH9
3nZqB6ow8chs32oTgAnTJocxH0rH+02w+I3hEHpxhf7+mrXSL3KtFExZbCmpA8zumVeXIe8xb9jQ
MJAwLJuxaSzrBVcsEPc6gyvvqg7W11Irf6DIvUcYtSgng34G9ENhT/uvEW7kfhh5Aw7ZNImiRZm0
0o+pmf9qBobc8YF3XhZoZcXI370AuClOX0sC2AC+uTyL0PexILhBSPVxmj/3j361FdUxy1q05LBn
Pf6t0VpjgUVRxzeX1aMF984v/tZ32kZks5i43jBklew9ppk7LOUa+XDfOndX67OdNnPLHLP6imUt
skAGHi+AnaDte+jUFHcZ6uPexPUE77KvxBcB+gVX18F465K3kLE+FwPHPVOKXhEQWDLmg1Z8bTHj
8CmtJ/Mi6PNXw1wjK49/HBYGSih1qQdPCLLRxUUVzs06+cCRmFDqi3RxsRgOn/4d95kDjOKe1vnz
sLj2Gyd14DhqpJxEX+NPStYvinJh6cSMTjMmyTBsiGcV0DdqBHcSFsi2j29ufbr0HOEJUEfEx2U9
uPIMQFVN3mSAdMux1VYBfOn4mLBEq4BrZBH1NAXYsP4qnNA6E2iwCnjsofOyee+LR46eYZtZ5KZx
qRqFxfEm6Kf5hpLGb0DNOZOGpAvfh32YzgaMoZn34+ng6LaCqFJZKKfrusx+PnS68A/JgY6c3Hfi
dQ2R4exvpXZSUTpfLaTBYgzNLtQzcmCjbbSHFgVRNascBBtI3lqt4Z9yY2mc5S9CvxKiyVbJ8qvU
yGaR8PxKAMhgfUgVqMsTW3I21VUpn1k4SH4xLwkdEOcIr0GcdERi6pPEmoThZnvqWcrmhMEvKIp+
yyPlMqVbwKFnXPFXw+E4PWkI6bKNuC0XWCH/5y8jivxyxDiVp5a3gR70+R9dl/spmQb2Rg99nsgS
EDN29oL4MtbTapWJK8DK+0nD39VVMFHMzcstgMupenRB7Onk4XeOKyc7W5Jl1Z7Mkn0/RycTx4bp
Jj5cJI5hsEblKaALwjMBExY75xtOMfIoEl0eI+vGoEBtgXBKsl1uEPVITcQBvd/Xarv/ukpRtxqZ
FnXU+4hc5G5a6Xfsn9Oq4ptSDSnIqVanqfdzkvDYlwlJAeCn6vydDifBPed8mF6Or6mPuABlkjrE
VQdJjCsNvWIvazrmZcLpLYbPZHhgWULvqKBJHVTOIDYKl0phu2bysr/tXWjQHi+fq0fZ/FMEaXci
it9uTvZw94r9BmneAXDlCFSUePXTm2Q97xCY/Orq3Pds4o+1eMTZcqAB9s54zg0sr+218DSDDwfs
8hq6vU46nr8plSbqJf5BlT6gcqF++IElJOFd9VdzhQhTJkuiX5P0RKvtKivXMc5YCgsKsp0jE7v2
uoZ2AtrMalM+K4i51ernFm1tHZuu5qCvTQ9QuKbpz71xDpVgl74ChyDK2KTWeGcdTSeZ6qBmvedS
YSgXJIc5mH3jLP1UPPxIbVawL2qvCc8UdBdixFVH2X4+XF+UuVgqpQnOWFvC+53b6CAFayhlNrvu
IyCD0TcOrJNQb4bsA44w0IpMg6A01W32xSyBHGhlaviWDABa5CzLHPEc5hyvLHnRCsqqBaZVnaRx
rdi90LfaLAKg21e1I2W1x46QKYy9FSpSPh3m/s6P4OETRJ53KRPSSkpPPyjI85AD1NmyJSObIw4y
emZRMP8AbEFZTnRH5bc9ayD8ltlR9HqVu6kQdkv56Yy8cXXCk6ypkKoW8IFeHy8E0mUiDff34FkO
Y5rFvZYMDOWGNwqcAJcln+to5PP8GVl7x9Re3g8FOFD2SDlq0ebyQvrCh9FadBvapka7jwjbX+Bb
ozzUm5ysnWxgElRg/WJH1iFua3jUfo9A+/WwQmcO3KiJ348jIv6MZ1aI7wKHrbpIWbgra6YkXzi7
2ktCQUyd+aYtLq59TghVzqrcmjrqdogZ6OrjT//mI3bXtANc6oRIzRwPSWsQbE4jaSS9dTlhIiLD
/pHwvdZFtUza0/CE77GJ5BR1B261mCb+Oo2k3lIkUcK3ufTh8K4I3FlqnTeC7WqihR0/Wv+Iuka9
dlJX94/1X7Uv5EbOn1kTgRuDjljb+hjWELFfB3Sp2cHFvFivbqgnoZZtEkev1sMeqNNZDJi6DW+k
xIh+c4vioWO6ocXw0xiF6y/DnJmgkOBkvSmrfVVWBMlEHyOtKrHiJPGHNoIXTwrAhbZeFy0vRHYp
hZzwF/rScm+yetu387FevneG8codC88Xn1opOaroKwbTyRf1GjMPrWu05ewbbVqrPZvfTD5bVNNb
Bl4UiqeGv7BaL/wN20YF2Sa4UonAgHypYst/4Yu4ezLXZPuO2ezuSwarEIw9mPlBdIgX+zr7vSca
K95dgEEvN4oahSxStiolOrfuM2Dvwg2ihiwF5gMerhOvcJM9A0qH0p130jNN/0KURb2DmdJBHPrW
l774NHVA1vtGCLAuMFNUb1VZD+qB5+hmXCDhZGJ+g1IwNILLJ9iNOmzgKSmqAzDFMVpcVU9wRBcj
/Lszl/k5+/Hzo0m3RKF7wow8GgaSZGKKbXTe06ZZ94RdjdqAxmkw/2MHS7V7vKiYt4MYNgXF5hnr
OcCVUcc4fcpUAWJZ/X6LxaBkNJkxozqe3h0bxwydonvhtO/nbjcHZZzXfKJsCFh+DmjvXvwzYPjk
ypM2B7KVKGqEPdtsaFwH5yQ5fmjUfOjxbLOCAkeXLwuWRfege3vKV9OC47x50wW+opcim1O6vDc4
u4b0+/J78EFYL0oomGOTZ5iLroxxczvN80BnAuXhmBhL/bKPUo/i75vLkLAIhK9wP2H3NNN/C1Lo
SvXLJCpBntLfeK7mOeSQ1RDlIss5YGTYbi8mSATRh2A8pE64EkFTtKXtc1Zbo7aymsfMtEWWi3SI
RPBUPuI3oUAObJv/GK6dk28GIDBvIGMb/SN23ljdOqyrL/WttiANsGkHs7ub6JkKlJ4vS/5j0KqU
P7W5lks99qnWiH5O2Iu10Xu+ROfuRnxDks2H1uPgW7cC+l1qNnfrtgd2dIJUZkO64qsKugotlHsD
9MbF1v1RToqUjNY7gWdPwI1fSjHmnIVIv5wgcoXKuRuUdog3s+EGgqw0VM7wQe1H0pq3TRHFblwL
U0oa6BPjac4LkCwwTGN/JD5D3WV/1tZfwW5RTpYbCiDul9f9WvICg1yYAm9FedaNFsFqb/23sOs1
4EbZi0KklMaABjzRukhf7xzkc0FevCKJiB06+x+89KZKNhI66FemHxCJLV1Vy3BRmZKGVXEAsu1k
7gG2gS8Om24KD92k1G5OC0WdvAbAflnNh6MpBk+ldMoeQ3oZiLuO7U2IYK4H/EiGRSOYjJN+U7Xs
R5MBTPvK7r6N3tDN/mvXfdQTdvUONFhNoVYdYm3KE4s7OuOeWG0dfblp//VMr2yS03gq6DslrDi6
T7WbXtvfXchxKTUaTvQj8jPnTY1ZUC6KvGpzZx1Yd46pkyAdhRQ5L+D0LJ4E6c9PaErnNKV4mg9T
GXIe4u4WMMFypKqjK8xTGGi+3RXi7HDLZfcZKnLyBMYDeJMYbbV7imKr79i351yJw6vs3553pKmP
XjWfXP8ADmGHLTSICKH6UWsIxRw14QbmBj7HdlDIrlTH6O+BKe52OpxKXL9gB48Wi2ZYeF4OKq84
DQ3jUnWk6pZrs2Y4Be7a6BPEQImv7R9nQN39i6YAhZaygafZvHskKF+Kmw1JzCFKa+KqEOSaZmF2
rKi1z31Y//Ry1/5nrR9D9GsENdFqrroIwYHAijZXNfcgEvi0SvIfa2BMgcFKx3XZGPa53KNouuGW
0bV1X3kkjQBqVxoToKV9nGBqMVS1TarZLwzs5U7aqlyPWGCxc229dKq+Qh0Mlc4Q8pd2/3OwgA2p
NX9qQKrZ5jfZKIp01RO7f8FJ4tcIlW1Cuz5KWOlyg45ydSlRLF18YSt0PZPIHjFeqvE4C97EYI98
OtnGRpxuFN0cczzQJBBCFeuQXB7yb6LmKr0b3hG8RsGmrxkr8N+DNuNx+ySGarL/hqQ4N8Py7IWN
lXpax8VmMb4EawzPUl31EleWHe4jyPGRMEx/MSIBGg+V6c6M0MS5LimeQ7n8OckdFE/JOavQN/Gu
KMR8BG2bqvHGUPgL1DXgkil3Fb8dMh4Ht6OHoK8V4OOJN08OiHUN3LkyzcRURTQhcxkZ8StAfNKL
xUjDdj9cgjJiGKPINkzhXkQUzcATKSPelkWgrqXGhD7Xc4ln83CwydootopmICFmUfHjb5HxyzWF
KIHYz3qYtI7DEN6ejtLTGnL2hQpLoyt1DoW1tCWwkYorZpihy0yD6seaEYCYi6tlhtcOzpt5hkBk
bYoMRueL+zaixR4Ssg+wZrKtL8IZr59MxHgdqXdUpMp2rsEqQaFYvP5O73lWB1R9BEhwBk1cCYVC
NrjaZIFPmM9IYK8nnSAPmplrBGWjFPUMMbO0tg6EsweOBygo1prBGFu6Zxzb6ToPRrsSrcZGr/dv
epNpDjTPSc9heb+65RAgeYOUiPsCisaQahv8Vug0TW7IVPluN4iKR6kt7MHL1LOWPLNvvcAOhPnk
41Vw+DG/y0kwj1LCvXn05QR4SzrIwjcETmF+zDkxqL65a9F5bN4WfZ9UtFODdl7vje77wTNDSl9w
tA2nhczQVI7ZMFtYf8kMDSWV1Ct9josZEvqrfSTnfUoqkjI0UhZ+UVFeP5ZEpel+caOTy95Usphc
OGH3PxgttqBrFuV/YScE38pjI9H3pEXmNtD5dbvltwG2T1E+y5mjJreDKzu3ukpcf6dOzCztrh6F
7n4fj2wtQrP9JhV27NddeNv2YYTkO+6BwpY1Fsj4iSuEpyFYwYA1+SAVFozhyIqdldBa+oLi2C38
wyub9q7hEzTKyem34ecy93x9zmAwIJKGLi6po/XbHIgnUE0QCVWGpZSVDuCEnLjhCvIZWeNwMNBb
z1PUwA9+fIWvls/vJa9rVudcvUruZLWnEZHkiJqlFudZqGFlqmzBBAF8a33h3IGYwz50TIDHmi2D
h9Im3H2dm7XugQD2wxScyywuHM0+JvfQhMKSExttLbCSVunaPfGWRh5C9dfonb6mveCAaTDEOz3p
q4YmTYrwOiJ/KQIhs67jIk29T4j6TMeg4ky2bIanHL+TCJl5k3ZWQUgODJKzpMdQAcVn0sfN1l1D
Vg7SWKqFQkeug1PHI9lfXBlfehyWcpp/M1e2hxDGeKDCOf81VSkFLgxoOaYuPSxDlbOCkepBrAjM
gMqqc8SGf+LH//K1vqSmtxIPQq3+EfYA8F0mamVyNzp+9RxgbxJFX7O49k5LZZRxJIYl4VfmKlfw
ItXuXgFAvnRA8dGIjrlShq+SmlXYTsj5R+gZOcJZTRQUyRNFA0jKaziKo6zUd9JIuBz//E+uPtvQ
VyQn0Yu6SJhrOhDuY52rPhBZBrZfYssSZx3TjRWIbqxpT5rsPERztYrGPnlsNvw9pG9w1QOfbOaq
685RZYDwZGIBStiDlw/angrzJiNzLls9UoIDFIcsFdjag2TCt4/cP9EdqLZao6M4256fMQDPNHFG
LQu/C4hwaDaLy5+hZASy6qrUlkYFKYkcdRfQjjQJCsAjmvAI/Mjpqtkw2dzwW2pSWFM6eWQ56hDx
erFqoNrtUOUzjeQ0ZPS8lTxGGGNUCxgvpx5/G70XmnoEebm1Tq4uK//0NjMkgcmanLFn7AGR24ny
sRniqr/8qYRnhARpjzR0qXJEcNBi2cCKYkLrjXlzVr+dtg/8/Qt42TevVVpQXVmiLDwjX9vq6US4
Z49YQfE/+ueS0xpz3NiuUg6hlXpCRoK9J7iE5JQ6L22deGwu2WSVeYmYL23oEBM0ecJashmFZtLZ
QRO4ggvERHx+F9ji4UlpoNKOBPVxmNyOplECUUuczks7imh1GhIrBJZkYZS8IXJxVqnKwtdtISPW
zt3Awf6jbej+s9oGqTGsQgako/XPPqNr2bA2XtgvxOI2u1Q1tt+ZFyHGu6ZPV5usAHx17bIW+Hpy
jacCbe12sHv7B7fFIk16VlcHtMMN382C0mvPoqvnUrShMZuSFWkeWow4A571Ajk58HVaUD+bKCeK
byaBi3YHD06t62Dt+iYWPegnCJCW7eX02Kj/7plaUq6FiJgJh9HcIbNPH42CcbiZURkhnIDajRES
Scd45TCOL4MqpS/Mq+amGUAubKcZnpPuAm+WFKOxHpzBQkykJrX4+3jMuZtV/F3dOTcwDsOhNfvV
jf3BnsEZSxwu61Xc0fFum4/uWo+g/TwdwFiIqb/E5T//UF8ADv8d/FUdRn7vKiJFGwPeLBf1dRtc
YOVnRhPEavlUG6SakC+EvkvBQrhPOp1w9n8EqncaFtKoS7RDP3ldGBy9+yBRgSTmoKvWMr2vb+k5
iDjEVohi1H2Gjo//wljW1j1C7w3LazJA0VI71xS5jAyvnIlzhx48uwMaqaQLl9UUNG2IE8LbKxzh
sP1zKT83Xm/F3WwoqHuuXThzde4a7bTIUADF8QSkrhWl1uB2lHWD4CE3i6oebSNd0KI7qM1Zp+KS
vjPYMMUN+wSoqOrOVtXkCCe8Q9RVyULRtp/2XhmUHLAwnQM1d0ADnoXg5+8W20/DLAyGUwxCDVn+
zT/Nq6cohAOXFCuWTpdEkKO9zRnRNupkpDP3JXzccXjPaOFYjaVXJWnBi/hB0DZZXK1i6oS7IFhP
JyifULSOATpmU2A8XR24s8c0svdCU6QMb05fl6rRjSFBpZ3mYHUP9cqFKw1yeska1SrHQim2YGZt
xGy4nva2fEQztUrUViCNTz6UpKqhMQnYcfqA9/4e9brhGS4s5RzDgo+Zb8NfzRq7J51kAV1Qp1AJ
Ya6mLK9cuQfUhs1SMP2dJoYXWM2wYr0vyJ0eq2+bTCR8RDkLgNv9Prj2Ybvgkq5B2n7UulnmVYUi
+mYvjZPoDp7N3BKcR6zDFydRjnGfTZ0Bdp8LjqpVXOdUUcUjmfE6XVAmYmPNj162U2qxHnnc5/dd
EonALk1BjXHtstvonWxAzuBxHRk0dxsN2yEk0igqCfYivwA0hZszFii3jEWM6C4BlH8ebiCVjfkR
54GaSSHzMDzX8U3SBH8IVUAQ9K/cmL5Sawzh6Ci4mcXmCdk7u5vPj9YZdRf/gADnQ2TV0E1kuEng
UOt0YHJhRlRBdvoqPtG8WUersSh7r/DgtgZtBUrbsdBroXETa7CmAw/o5p+GIIDtHHX+TuZajgsL
3i799xcJzRZaS6Y26sT58An0pr0K19uOSc2O/bh0ML1SjEtpLKeWl78tSMtnA4Sh1JKUy5Lk87It
woczH8S8H5ZqRRu3nDPLlLqbDxqUWto8T8Y4kySuDbb4UJswqtW5Pjr+dMKIo6zBJ19TZFrI/2JS
+UWvrwAFeN9blWuslpVnESiKb9flzw7m4RfkIVWE2X9XUH/WUdEN3XpX9fkBn+5C2HTIcUvqzWE1
mz1hyvhznpY2s7JGEk1qkdU/r++dXWf+fBxGNrGXk4PqO7jOyPHfNPxlYqx7+ZIYQ4HHV5Azc5OQ
wsqKteA8I0vw1mrkhES5ncaEpI/ridccIJW3nRdzRZtzUaKaHnR9kRU6VC8VQBs8zgZiC37udJKS
XSPdUvb4n8kuA3CTNyKWs2eCkAJjVUbml36Tu6EmSd6Z749yeRcLSSRsn+gh/s32EFjrNVVnoGCY
u/mqUaJhmW2EUZZ07+OOQSBG0FDrNtUpyck6dl4HEVQ3eqc46DezRMs6V85665iR8yw1XDWLIjU6
gRn9Pygd9O1rjdvfiOgSSoBR0vPWL8DrqqFpQUBVXleMz5YHNdnG3uCttXsHJ/s0mnCfzhVc013y
wFvAzB4UCv0CmTP6Nl3mOvvDV7/PmKBR/W2YiclHVkVywYKTA5pvk3KFyFH1Apx+9u3QiK89UnBZ
hP/f7CaIW7grK4v4h0TfyiMiHSll9Piu9n6GMN/4Mn5l/WbL42jGhZyeLCkag06GfS+XyHKlucTr
iJ+QAeh2HcFKM2itJM873D1qBsDezaCFHFxz4DlOcHdC2Mft9PxGNXaUnHaoeDLDQ3ncver3ZmQM
beIXkrDceMKzgZWIn+qlrnniDDNivGFWoVUd1msJgjD6q/zB6AqVjPyKVHbjRzMGW0mLYXRC9x7P
/U0kuifizsUAfjpArD4zdg059vDIQYmzxukbw8D2j/z4relfE6IG+1yTUeB3QREdmeUcY30Mhsqv
tBueokviC7upRSSbM2HToXxag/0AM0wiwi6yJFAef5JZy7pUoR1j9j8rs5cmaACIOwX0rF3hZD4t
wc1xq0I0igtFqgStR9IKK9oEz7IGRlMbactbC48vK/lwiLqpjNDrfgBQhEWsi55VdDxdgFtEGn3Z
Nz5m7FHrBqrAz2LlvEYHT2wf9V547GjaCh5RXzQBHNqxBOFQT6YaySsTqCfFfy1BBEHk9JT45Nm0
3sOIDQ+4piMq13/7ytd0g3V/fZOIkIDLA6aHLhbPv6O9HucBkL1S5ojiQ3fNQTcMEJg4Km2YiHHH
UnAm4iUFV5fz6VazyKRIq99wxAe2Fof5eiRR7jce2Wm22M/UdT2F/pCrKuIouAexBXDwePMr6Ue1
7TTHaAAs7LIuo1k3knAo/ff2yHKd2dTaDBkAV4A2nvCzMuPp2KQbu7pqu/9sN5RCbHUXsNwg6rwl
ZLZ5LN9rnnUwHO3gLeam62lQ75FEPWr3au4XWFwqlS6nZdA1Sd1mKCff1NIiKgzkS/86seg9AYv/
YUCQjRyR5SXWVNGf4d3UsxLLqPfjAmw3arNiKTnoHSFxaq6LuoX6LZXjSpj//Ees4vyu6p0oH3v5
N0XBs2dRoZM3gRoAwvYBOcz1dkyU86hs/c0n2mlUBofvMv/grFyA03oJfh9SFhCDJmgqE4XLjou1
VZ9Le16TFNS6dWw703kVaPpelEfLojaVinoJTquo2F5dywANgu4TZUV/xTfPV8S1z/CobVoc+sDq
hy4V/p63VaFqmDx02NIrr8149Xy+MdYhTJEwkyK80m0ZHcixZD5auFtmYgEPKG2WV4MO7jYgtMcz
2TrVDQ8b0aATA1zA8L4E8VBxnBT0q9FmqJIGl1G1N4jGVNLciwig6yHsu0dkzyvV3Yukv/rj6QDv
6X97qGP0BPGZ9QKcuZIySR6OhyXjzuRWu059FzQKvbNnX8W8wVHovaG6PgvDj8+ANLS7zwqITl0D
gxFLr72JAucsqDXCdIlHwPzmR89T3/5QgW5pAQEpTCPTIn8TGhngjkYf7HkKE17WBVb6k2cTEWJE
liQErPt2+mXb/8UJ1/romHkmgIWD02oNWQxly3ziOa33XP65ftaCdMp/fQsTRMb9UayOjWer5iq+
kyMIZlZafFM1/EJ8VX1dhTvt/vC+EbczlN8kBbnk3eLO5g2EmnBHlsi10XAYqRptbg4TKsANW8X9
xmoBvF3lkuM5PXecV2g+RsXt8N1WB5BeryYrFknlW6+BP/qEMVd9dGlaRv/WoW5dDRMHtBFplojh
F87GcVhrVFdwbjsxKad3k0jBsQ+m07F9IqAYqV9+VOnWfDqSJSgYxvpPdqdACvQDsj9oF0cdKFWf
VP5JBXaK1cAjjynB6BMP98q6Qh1hmik1np/qKNopL0Z2jyjVQBL8kxkIMQ+9t5fvIptTfRAruTkL
beeWbStPSHGfI8f0cUAZ6Pf7k2q07VuPR82AWkE8hZP+0/FipatNScCatvF6Ql9UlOBi9zs1O6/b
IRdpZyAp1mPJko4RFnBEwJ0a+L/qHsYWAeixXD8UvdJdIPQxyrswUIDhYfGx7Z9BT4Df/p9NrUph
i8e2xnTZeZ9LYsTQ3TaGz4UTVVj4yEWR4OqGFZHcy/L81CUmMI8CIKXKtpnlffoO43YQ8gncV2OG
K8dU/DrEUJEknYC8tsSWq6QK25/ikP5dXEsFzSUeSptgRLOUW2eMllHTwcyzvtBd5Vezk5djR7Y3
VjoEteTTDLB0v0XhwKbD57fa9x2aL+3rOXWp6Bn+RRMk+H30OVt3vFVY/IKieF8rQ0jxO6aAxWr+
bHx7Ddy0ON8ZXzuJTOT/kVXALqcFvAlQjLEsd3lwlsE45N7t3BfIbu+n01gIvCD4YtiQVBikXxHf
JyowKc8qlv2iTPL2ak8fxQh7ksD6mFvXiQ+VeyUw+W0hdRuFyRswgKtNGFKkoGKabncysUebRfBF
A/Bk9UPNUqf+fi8aZIk6y+Is8t/udQVGGIFC3kymSHm/nLssVPp4dZv4QqIl2CeAX0qVJa5KzuOv
3u/bMIh9OMfuTJ/tw59klZjEdZl7yVYOzApGdLe2a45am4r6CfLbcvLFvsvAbLLpCOuuk5X+HgIj
HsL6EOPfB7XS9y2AQ37bdXYykOewDE0yVUh8IxH8P3aVsWI/gtRuUFf+efjH2WKLDsQyq3gOLR3s
Nf/UUjcaQGo5xHwwXbh1TvLiNZeEFoOlSsyEfu7MxITHLmBkNQojPMIfhCFFF53DzKiSP6Z5iQ1o
XPfSQEWOyGwD4v4DqGpreCBGy73qE4RMMYjud9kqRlO0NyUR03suBV5JZ4RzAv+sYkA8Idnfa/JR
EumbldJxk5RLPVC/HrQXaUfdBgitZFBTF5Rn8Y3MfhujDVJDzs0eOTiiLtp92rgzMn5zCkXHxsqk
kYF2LDA7y9AVcf0iPDNDljA4rXhHI9LFHdCVWMaqDq/N46l0AQZFJRcNN0qaYacur5Ufsl+V/qG9
WUJPFQjW31G4dqI901VjMvGTLkK39XQuSxmrKiTvuu9CdUJNLg2nK+0DJ6BiVZGQETiw7DVYIzay
UF3dDQeZjbqryXpseJMrkuSfFudWI76LgIbHjxyfGKGmbjTO48pTy1r/8cgBsXVMkrtsJLSH31Bx
hcXluGdIrP7OHu4vJtG79D1L9MEW5lwGOFYqbDRR/fSkmh49dwdXt/ai3ETnnUCxABIWWPi1gz3v
UKhU+52LDK17i5KbQg+7la8hidjaAx3TKjwtBqWKnydKWee5C3AQTRUzS7CPumsYc7G2L407kekZ
xq0xn5QLy66DhJpay7QpSgEuFniUXX8P4Vs4MdY0UVIH7b2H/QVSmkfNSYZ1UXR1E7qwUhAcptfS
0RuUmxPB/mLb6FNqAALaWtBjrjfieabpB1U4PlDd0Q7EXhGJTUy/5Fu8k8YkPNVv7TVjjSz03RNc
PtSXoXpMVxFMrJk2BXwYYnMF2ln6euKQZcIOBs6BKbAZmlwNQqP9EIZ/3pX47vYbTRJZt0QyQBxL
chTt1wpIr8h8Mi2BzmLWsbsEmbg8T05z5zW32h0Ohb/qnbwh4rNoewfLv55TgJBFrShoes2l4Qob
nqxFadYIprKR9+7H1k/VSFlCjFRBZQZLkyFSt2AyUQuMfjdkcOAPi+beYLtUjRks+XZTUewSK+FA
xQaidDHnhnA3s0FRtk1BHaBbhlrybDqHbigQbTlO89vQpWPUpx9pc+87hmtz6WICVjZSfWZrAMKd
njL0WlufXUSX6s1lwhzICO5fWPLpIS32JIDNuqhLLcUQD6SWXa2GWGfCX/TZunw2W9hcmLdGc9Gz
KjpIY/qP+6SPFeC/+LIeizW8Ic2mfNbTgWZOj1MOmmuzOYgWylUCYHiOuOp4NEiQv6fwLtmoL7fC
g3FqUhfI7bLLM2R9M+++q0Gqee5aHRxXTg3aNCCMb9ahvqOz3tJYcPpF3k9u8TPyjWwWUvqvtjm1
iDqGyHL6J3XgZsouStrt5VZrT5AosormV7aGPZFhKDAT8zD5denQmrRP1OAh34qyPux5zwr0B02H
N51Es8Rt8d+OiXbtLQsuPGGS83NhOMHWYsk9vb5+ySb4u37qZBaf5Fx3dJpsEOwMZFZFGCjkbdQD
i4ShqmjjV3LEBfrubz+74hWibWEaHsH45nL6ndRrcaPk+WFN6msUT5s3FOcBjIGO/42zMTAvM8Zj
m6QKF+sol/sSWw/9nEf2LU8gax9dJzEbLwP7kmhlcTNde8DByguI294naTiR7CDXOrCr1dGKOHx/
hNUSQ3A9fZK90KRD3+wMYdtdTehHTlMWnitsi3MFLaU8wqhJ5q2HvSmNLNxKqsCeUYoSckUhyKC8
gfq8lGYBKAGDwXtaMFoWh5Muo1aVSgfOzjukENtuPa26mXFHCdUwYnTNpp+4DyB4NZftJrC4CxbZ
NyHP86Xg0FbhoSijLj6tW49gVcurjyYcx4I8UHp5cZOGgKvFoSLxwNwL5HwTzSsPeNrWHBnt8Aju
TcXW3PyPWM5VkMpgZVu2wQVVFiIAYlUgg024ANDH8f52Pw5W43D+BDduBhP7TVzxFUEV3ugguqHy
OMopSxG6M3X06VlFquiXJntOyH7/xHaVgYI8vVe+cxqML8Apkv0an5J1FbQF2cO/kvwrTFbyHR0E
Vae5B1CrO3Vat6YklIW5nNaS7NTxCDx5euhraCpaygoeL9j7gh8EAawu5es3m8z2ilg5xNScmBH/
1oQRQglNad1UqCtIh4qLEBTIjMsc/0nJ/dBoJsYyiuVuSCri5rz5N1AxnCMSV7G+XTOaOQb2HaGV
PvVuqPrfAV1bIdnlZdHpck4d8lpPZLjNfY9OgXfaZTwSJxhM8pV8e3En4LLvoMV35CpGEXHsslJ2
YC2N5SnKwa4+wI3lN0xrkdVVTMzgjWkyb/U1PElxhNX3A6sMuJTis0PWFTZ4K/ujtehg+dkgwYaM
XDMe5Q6KIsv3jmU7GiMVGTZvgJdshfNjyycoeyBtIneHIpcucdQ6iwltuReaNPnwrvu6LIahD84z
rHWk4/n6AiSp3SrxBzTrAyZn1yPr6FkgX4fbeFApEduK7IjVq4ztH6t8ERVUt5iMF1VcDmBPDkLb
QsJvbDyesqmTt60L6f/exwBf2SO3TLwJmeU213ap7tYxFVpSuAvHfaemtr9fr1NNW3Ua8NocB3Qs
MOmyhBsr4ZZhJFwoKVreLsp1lON1fySvv0+1SQM5UrKglsPvdmp5jSqRfeLZYoG2sjoHKeWkgNKx
ArPQo3nKs+R49VJlPsy2AlPq3cmHsNnPgq2IgK5rjcDYcDPoKaY25weZcLJMPbeuZNE2nfXE7d9S
XXJI3ZrOf9Kfyl/T8eKBGloPTSkSTlndzHVzPfxMOuJs2yi7OYWFe0miibeoQU/eFkcwB+C0lU2w
RT9nUabNk3T/PSkfcAL1SwQI3T1a1dpU32jNFtgOqLsMNuM+PBGnvggZz6w239tVR9CI+qgkLEUK
QG3KNPUyeN95d+ixPTjRwUpEOBaulUpnXued3ArmP+81StkTVbyMB3r3JkDG7zudYpkD3/J9u6sz
T72GRTubjI6a7R8N2fHluAsorYCdQ7tj8BdDfyPI37NGTqL6el2kIBP1sEY4tExqurJhA0ai/wTk
nayGFi/0Rr+KbRn2XP0LpAsd/fryDj1Xu9NftTG7RGRmcii0S6vM/gYuqsrtl6BrFmDfXW18s+hI
r50L0j4XuGgbXI4Vccv9ue7u2gWDLFkXBCNhjEbc23PJVduPzaIFXpyzoMkC27eTpS8c5QLronIJ
luDcwkFQKPVZJZzTMQzkoe2W9e2dn3H89OO/ahCC/emDVFF6iSJChUY4TZ7MY3JM6r7OuA5j6PyB
Ud58NpJPffCoQ3x+rKcU8pr+acivdz7fycA42yPuA6/WqIvqd3ZqwDy/+X3z2pFbk/zZjkwwF/jS
pr5VRHXu778wdbXXLP9/0r8Lm7pzs6jbF+dLcx0Xjatq9AgCX8eKRftI1TinzsbvljdcoTOfDo/u
2pJVkyVSBkAVH5thRwlQsuThLZwVFKj4nzWI3NZbIyNHVucE3cQB7qx7HdPvwXo3b2k958sjS8I+
RnIGifDpN/3I8btgcp5DjM8SdMgI+8KmbVbct/5sbiOmJfv2YnqcZ/nqyvY1nQoKBdqtrVzQ8tHB
kMS0bEZo8A0j7l/DAbLAMYkzcAOoeNyrVmVu4lXpovQtNT82j48gdzkgRuLrNMfVOAk/umJTL8DX
Yfq8noG0GKfTVuckbHARK+bBV3dLUWAkUDuLs/p8rj3urn9z3wLeUR2JBN123/p0RQgRVGFZPNwE
fbFMaCSxEomHOBcaXldGHVJt9LTDy+sNW+WSuoViaVqn968Wu76Zr2f7bPidPUNrdwxYwxPZ0dHb
BYb522Lwmf3mFf6ny7xRJZchADpa6W2wjzuW+6/2eVOpr+lQJ9/YVKpat6d+d8CzYK/mlY+77ctx
v0bRnA6kMTHiKghbguM4BU3Y0JaK91HNC6bnTvuCie+gD6hfYesX+3QU1TcroTtVhXXWH6lqcgVQ
VRILDVdIivXTJma7nl/U2j/fJQJ3mdsy/wno1fdJv11SufBTg6zB/iU/AaKBDdP9a1dkKXg5sbZE
hQvPen8rje5NXerF5XKnJvoD4atcUiuM+eSHvbaydmEAKSa5xKyv8AwUjrNPw9R4KYFGqo3GF7hw
r8Nibrg4TImnA1+nUynUXI3P7Y+kEZT7hA4hq5KzBEOZf3koMWPdrY2e7JS5y78f2U2VCabGdgiC
+YNIJ3Jr409cOuaxDct2QuW78nHDGMbM4Y763jtUbAzwcpXyFgeXBMt8b7TIUH5t1Begil3VaVuE
+nbkfdgKm+7EjGWpmbo6v9oFHbDO8hA3ERhL37Lpm8b2f80Zc/cROxToz7PgFCbJ03vrTTwubuV1
fRuLsODyBPGNOFtNbQBiLuuPXeBp2njxR5Ev8K3g8mZfmj6A1V2+ifgQiRsQ6e37XleMp5YPb4XX
BikzejItCyaSWhVjoR0LaOHYfL+AYkSD+iuV0HLCHFYJZhUPSt3VpxxZ0IlAdz6JnGab75AlU1e8
iJs16Bxu+N6W9hACR3uj0ayieNVeiSF+dMxjkWzNN+TGzPZpFSgneMgkLJO3K2KixSFazOcKGGNp
BlQMfF54UmKJEde9MZncNkVDaMaco16ecSEo92JoPHE1UrOC4dmvKChCOsky2MQuxLPh8w5yGPsj
zJJSfkCUJnpKit/NHeaT0RVQlYJXxzm/hM05bc4Y7UOAODmMKc3P4Ww8aRhsePhpldtE7Ckz0vRb
XEcqR9LMxPnX2hdAAIQlLU+7QfM9YngNZScnwz4U2W/b1o3wbv2J3i/oNfZR4htPvE0XJ+xwEL33
0glXm/EsRj9vB8o/jvwknpdbrcKPFdl9sBzo2AHMMoyd+DariE+j2EMsVgENUUQiUSTUhz7NHPBi
ApCXpdX6Y2OODecSCwK4GcQw/DHakIWgLDDOm0P9a038bOZKyBGXKboL8fbFP1ZxMYVThIvkcOed
+l0iwcK/x2QPAQMWRZaoVQODTjWnPsTN8R+M+dUOSoTqL6b6ZBaLj6QZTUYMYWrr0+wVo1weFSef
HUl+GuDqU7JsXA+gtuD6UWYYjM92oHBjWeHcWs4Nndcy8H9m/+WuFyKlL+HVx1X/sZ7albVAIIu/
t0WGxfT+wXyzB+LfQQ42N/A+VPbJRRpIJmSTmd6WTyoj3ixbtg8pEXN+E8DgDii+c4jef2wGZ6cK
2pdDrdw/oB5Ug3h3KY97ZMmx57Jvk/ugRKtvXTCxHTW0TSk6jDyLkJOCTriZWJZN1twDyLt97jKh
AFNZbZNybLANKvBSsPebCUK2xADtNRDPDYjwDi4ILm86z6ots1Xswh6QVkGVJeustZOo9HbLP0Q5
NxTWBwypf7noSy/WmHIq5tlA9f7y+x9f4sLVI6HPKCtRiH82ggZcxZwF3+EyZTYeUjQEmlXMsFCm
o9GpTqJN1cFvmeSzYNluqEzPO4UrWDyjJp+vvVjA5u/g/1AKS+ha4IXbIY/UOALC+wHZc4RIbpds
b+76m8xA6mkLC63tnPW52Qisd1LSWBePQ4LG55IPhT4P3z6BjNXmTZHoeu/jEn+Orj1BoGz2E4zJ
q7beI3A5FeZcXSUNyCl9Wr/Zhki7k6EtoZ5nDx+3iodvyihJND+acPD9Lnw30KwxE4WD+024AN+f
NyjzRrtMZul1dMW5MYnm1vuRWkm78uGOAZCXggtbNbkLPqAbNrV0VsQQlHx4pnMCnnqSPzWSLtAZ
/DPmG9SurMbeo5/3dnzw48WJ8vdhZQWmSGUyqRbQKmzYOeCP7M6iOfkHrgI+BGVuonjGrHm9do38
M8ri31XdtqZBNPTdX6b70pn/nx2AU4zHd2vIevJYfZPM23et0PI+UkzuNyUDS5s0faHYDbfFRu1d
rqglayaMpUGc13+DikF/yfekjI7raPrvo+U0TV2z04JJiLKS1s+1f5Qf/m5+bd5XuLWZklsL8NPo
rJOPT2vKe+M63fKKqeGLjy1E0RyufMyxbUlmbztfvc+VviFJnei7ljf2bo2NRsOhpvo94aGv+ZDh
7EKRpa1/Fv3NSsr2SlKwfQYLiS18JW+XI53eWWU0Y54OQJiMIsy8QnEIVHBr7NvAHZEre7WiA3VM
QEvjp3ditc57zmo/c+ahbxPM+S4WsK044OtYjHb04loAkK+3H8SJ3+XGpk64enH4u2T2YKr+IKgG
sAiyvu3EN2nXaZkAOVp1Atg4oMmlYKjsKwfXk6fxrgpB3rFkRra0ue8xiB9/woCezQ7I2ZogQFgw
pol10w8Wcr5SyvNiQvEuCpcbKbtqOmORw/wWJtvzu15zYvwjb2JKy7XCKX2v/LoFYIznkigRyZVg
TBsBkNCFty+8py/OtmMCKW+QizcVqN3K4KItDVjEjtVx7D+Oqk13772IjHD4AfQN4YTwWJVF11wY
GGCBOOw738Tf4ItIF3DSeXZL51LB6GDFpOe34YIj9EPAGSBlynRRkafStckuvbRf+h/uNEbByCBT
Qnb7pYEhMoqejgPWCpxnXAcP70Y/EA17+vk3ALQZsnrIfIPJOjlO+Z/4h1qUNWHLwiDwIF73449R
BjycTxFMi23U94Dq2ZchdGD7J780IjyABG8SAY8hpDi0JOS222VmhebLRgS9OlW6zwMtHriHHNeZ
ubOj30qL3obaizkYQV56m5QFyT4sfYis1PSOMtAEVRniOfjo+3C/8iCLLLrHg07RyE558N0XrrWI
XuA3zF/h9R+j1vkm4Oof6M1KxexBJESv0gbpQl3UxlG/FSzCNO5Q6E81fe/Y2xGvaGkd/mDkvrz/
1k/c81PcAQ==
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_comps_builtin.vhd | 19 | 32006 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
bdlZLEAewQqpv1o7OoBr4R377V8Hk5Fd8+q/Az6G9nxroFaOnD3V9+lWQZaiTQ+UR8tYlBixiDT3
2rrbvlUYqg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
PNj5XhRRPylbuLUnq16m36512+Iu+tuxUNOB5vui/U9Vyxliy5LDYUjGyTrkosJ5RLmSfgYfmdaq
x3GXyG6MVOiZo15XiDmGz5Xa3WMM3TuUhfpzNItvR+cjVJcfSX1Vpo9/m4Gf2HbgWDY8/uge9Yz+
pdDWTg9IqOS1f9m0bhc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tfy6e9ewB1av8IAVBQg5F0wJVpezM47U5T38niEmKqoHE2EAQIsVtLXdGuC0EVCv8iR27vcg17Oa
mBfBXWB60tzPu8Q6DSJi1RmV8OgW+NgUvCiTMpLKqqsw6FnhMEK3lQVXfOtnfyh9msybPw9byzXC
dambJMmCpKtH2TBazWP4yb5ww1Nsz/1jL5i1zPiiJqwiUek+yJBHinlLsKOdmxiEOjEIxiuXMNyg
LMJzb839xkVhlMYTWXZYlSQVwwm/sLGnZ2Znntlf9sYBoE6D2vYri/PUGcfI5TqvvhrwG3MMHoTN
rPYZvU5TTqkZ0UHzprP9ZbAAvBMMlhHGjyKLgw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
enscaK3Um9KpWwQm1hA2XwO16XJLOAeYZ3URNnasJSAORmdXiuv1QgNvxstTqRmJdf6aiVcX+SBW
QAS4XOQmaHblVVCTrTFxq+i8/M/uWIiPlKdwfgcbq6W9GDVZEH2g71B4sNE7sbY88daOW+dsFMn8
evKdCCrOhrfApxD2w7E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qn8TdDpu0TmAhfXr6OjdWoz6rfyBW7fFZKyqPOjjqWteCvm3OM0JlharuS1oWtO6vCpto2FAzG/S
BlRFnD+qM3W558gotDG5xKLXH54U8vJ9P7HSKDrDRZfcvgzYnDlLOZYqIhF3QcOp7QlIfdgIFJFF
P1RDJ8d43uSYKR66QV0gPXuT19+tneyhi0YpcaupqD9/Z/vQdGHiorXfqzI+zmAX5/7dF89mvr3v
Pvp32AibqOZJekU7QCnp4VkIAFQi2sNR2R1SirejbeSwa+gfCdYZC/MT0OFTfQjM0uxBSK/I4IyT
gWZgfuPijqASxDrsrURmKezc4hgCDujIExBWaQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21952)
`protect data_block
3720zAurmsgjW60V7hP5jyZoOpDRGQjPNH5YywQSPELWgeGQ3NBAz8+c7rHYAMIMsNuxXkEFHaCU
zPPcMH9cI1cAXEs+sh30eU1utZfJbmafnIR9yELpklT+rYow/re6dAYb4N7SrQdoR6JZr/5Sxwkm
x3a+e1tgc7lo8+A8hVtoxxzdXSn42OPzUYMR92aPt4KBUg5B0UFuH2Ei4qFsnef8lp7YjskaYDm/
Qg4FocOSG6rsaieot3LQwOyMckelT8iqAkNVoHp/BL6isOxgrj0myIL4iWsebM/BSdWwwwoVkJLG
VIE1+y1QTOko8QtMLPhHWitmTX6Y2RyioQZbMl+q/h96g+Ee8IQqb2zBOWe+2kn5RSjfEdkGIzbF
4U+/6JwWsGxAM3XQ9KydfDt2vaNMhEAnJkH/M9wpi/V4sfrPhWbxOcywv4bLn2Zs0f05hJ2D06k7
8kIfxSci/rXxrYVvIZTJTUtL23l6CuQ8/kzneKj2alAxugc3WlCf3PkOrbdRBbVhYCp0XdDmOOZv
qWexDotJZ1mxvJyKKGGObHjJK9F9YBdtZ7w3v6XZkBkszPWBLUQSpYDJHSpbWC7fQpJyPzn3zEfx
2iOWUFfpp0+IjxbwrU2rtXkRPHLReEao0HJQFB9F8Y20sTAbmYRxsKCGm9y4N1fSZ+JRRtVnBMvZ
uRr7xiwtwqjxvFtjjTcfxqQTV6vgIl6ARhoyI/OmZQTwLlwjcwJTMmoVbEvi6afCpjeEwFzcqIJX
GqaydO77nm2Ko2yq4PCjeK8rDJkRxW2NQjZKUGKkHv16POsmYsRu9QQmGDh60viU4GxQBeTbvnVx
ZrKwOw7LlGjp8DYH3QiRMa9p2wMbM2S7M7eoMjIhweqkhrSkKCk7m5LaOHuwa58hF1YGxgDd3bgx
3FzK4ODqrnn4XbB2kyd5cZgqtemFPT+oPj12MSf+KL25YZMk1SN9/Jikm70sGxAz5EcGMVFteXQv
ds0IC0SLXSC4AyHJitmqTqKx3aFfjgAejN75bEsPm6deXVGXib24RNWA2L1dGcwEfpW6riiec6jI
7WR0cqxHFJOVB8FF5DEjjRwon409YIy+qT8do9/bcpFluFw8dZavO6wAdDuYAn5vT49XjB6+C6J9
MTm1fdFSsr5yHLztPOodtf3HH53tMCIOAnEA0i0obsFUcP7RnHL2ZzDQM+FIZp/ikPh4NM84y4bJ
XoB5THsjyKl2a2ycDyZfEM5DrKisbcXQ3/zCkYxMSAF1yTaHf/Wn3475klyRAL91qlr6Q3gaCg7h
sEMnktV+59XRczWudkW0tSuKQnMadBBm7xR2enA1THIH0K8wcBec1Ag2ub9Ke8LP/pa+IA3bGCJp
/9etfHIPaU2RoesBQx3xC9rYIpLeSHKNhtuidMpV++DpA/ENogLn7L9Zo7YSnFVINUh8DnoLCHFa
rgtk1h5joV8n4CH9BBUV2NtkdG06G73AuXJuTntefbmYWxDJJLqle3P0WceE/TFyh4e6u6Ubt7L6
bYfin4mMASxI1GETKKcwE/V/1nyH3/DPmMzNZD7B4+hbZnomfpjFNSYb3aplISPSJlEOs9l/DE+h
kmfjEX8XOKR8ERpctZdjWrikhLha2uniyOYH8yvOKfoehR6DDqm7lS9RHESH9aN8LwGa3WhyRBrO
fYdCDrhVYMKjeRCvCPJtiiy83Bt0XJx10yqSPOAobPNGSQAGRyJqdbycbmAFz3oAXGU5WJW5lKVm
EYxdpJXR4Bi8j3HVmb9gg3iRZ6sfAuWnVX3JvV3mjOlTGvjs0/V0JWU/9ApcHBiUmXNtfU9uvNCP
r/IG+7WeKgMx+Thwjsc1Y152aRB/+I4FicycpmebyY4wCwfEkNcf1fPdqEexQ4KQDsIWn/AkN2T2
aQFzRlgoXKVLMMWI4Q1qzvtsesRGoQ2hsDUutWSkFOVhe9/NNmATmPTeYebDgdcDQ0TKybwDCucG
E1ytzCoICQdGOQjZNYYXuIYfvUfXgtjWFGNcxh3QOeHzMYfjhn5U0lQmgqSmLSrSQyQkhWQm3vCa
ttT3CDToi8X8H7jBXDwiY83xtk42XiTR5mnlI+jSvwrH/Sh8Xyfvh32HHzGY6/97wxcKMCOj384X
KUJayqjha9nMDRtRGuShiWAlQopmcN2iYumlDZEqn7qawlTWzC77O8Hyoc8q0SzbaFiQGKZE8vyt
naOApS3ISWAmDdFs7GFv48o2fkqbVvB2dZrOmx5VJ9FUPYOG3Qz5kAlLKoI1FlyNYmShHpVFicXj
yPuLlp12tcQb5q1YryD4kWutESwP3TigJE0f1FiemklAkXEGpcarguhQ2ic5j/iQ4WU2veOdyH3L
TUCbclgB11LvsTc80XIYoSJIGNB+NIDKJtkvIGN59s5oV6TrMWcwbH0rbYcdBKoixg8HshO6+60x
08XuWAcRTzcnHC/B6P51IR3bKHbMXlz105kPjsFPaLaphFesKGCVLWnqnV9FhvrYOXIRfDilmjKO
TZPBh6M+u3yla3mJkhFPK3DTatBgglOtOGVk4aLWpZzT9a6pb/TBykFF/ixnKspwKNWRuZWECig1
IENmcfz1r2N17Tg9wX73tobIN132Xfe7R1wQufRFnBUR7k0Ga+Zdmw3Hge3PiHU2AcxR1CXvZZHQ
Lc96RnFeQM6re20KiVVaA25e3YoPi19Dx++YBUEylHEwlU3QWKlrFrPH1xCoeYix56vts21MTTR2
QBPZcTwAr5R5l9ipmmWs2QuaoF3roEUcIFgNADHSGF3epgbO0xaCXvUpuTP9AJYvhSmc4w+Sqivn
p2Vw8kNuVswulkgYStXjeWMTLd0mKHoc9ZTPG/bS302vM75biwHRlAnp2bXS7vxsHVmRP0eDpRKQ
RD2Zzw4mG3ubd9d337E7X2CIKhtnSAG4Xa0QOEeIQEOs9KZIQUJEUikN3gjW+UoWE1m0UgBm8U8i
seUri9e94G6BmIem4m8SHTHBV2ShbrHWxuofGnllapRUQ9eNwxBQHllDNytbbUg3C+zQreed5EvC
FAQ9Qhe7qA/ukGNAiFb/EzkzI6u/KEZPvHo1obAUD0jGD4o1ab4q5cvfh4rhnPZ9l7Tn75WmUj1u
ioV+LRlcB0ZUJ4tY9HUOygDACt0nChAoCC7Y/yncTHSwR/wWqVL1kn5X5W0mU1Sz2FpgvvUaqlgU
yy6LNv4z7a1jy88wyDojgKW3PUGUCShF+S3I8TB244ypvIfVMyCEygpzNy+jemnD9IPMKbLOipCP
4U44NzljVgeYHCUe2QfoJlVlre56XA1ORyrWc8tK+yAYOAzjzCpYB/ifzC3XGWKXMw//MsgkwzG3
V9pFMAPu0pEj9GOcOGxvXIolvgU4eYsIpg29UyQi9HA08RZIIG43ZV0L9xPaxr95QLsnoIEAaVRn
hLaxnXUHdoyVM1a60TBRYCD1Uzd1Bwd6e/+hVO60hS+U/TeP7nOAQ57Gq2tbGYSPFJFvEzTDcalT
OOmktXDMRucul7mP09X1IOUT1zyiC9MMKASOz6NS/6qof6B1Vna2VIOGpmLzmlulnMO6U5yAA8rh
+II+qrs1wxqWxRjI3sDMA4KXd5esVII7DjerKTij2c9VE33A67Chm7LEbtppmx54zBpRikc9FicK
sknYk6sVwK3oSTltiRUpWY02lQvIgZPKDVGBfs1DEWVAiWoPwnVMkdqFSzSRaBKwXbndX6UOciO6
5NA6giXUjvPMpxudlC+F6d5EzoBQLxkI88bv/ptWDyEcqPbIiWypCuBuJ/zyAb8qqTqIn20c4SZT
EpG7wiRvEpoNztHXkAqe8mgZFJDUC3CBJ+qYCiTYtkJ8RugkokwUqRvxsWIsecEcRVui6avYmDqc
fhMkOiEAgsB9+J49+ba1L969Cx7u9mB62HsTCy36APl0hPyrM567PpVO1cQJ0SaKIYgMS3HXFiSB
R9wwDuLfpr+n21dCt4XUm11yo91Qblj0sMU5WSLoQ8OEtzcF3JCRHyG3kLk7M+EZy6gf3a8lYSdH
sB6CxGZeq3neDhmAza/u9Oh+X7tBmZVeMvkjWkgeS8e3bKST1seDutn/lLCreujhPX3oRy4kzFRc
kdepGVQ9nV9TI9MKeeH3ngqqpYzaMs2r8uAOZozgDZVcpzMheVEkzsj6yIDkhJaU+yGZswgGadum
tPM5jMsCvroXd11E4jzD2Oqpoj39UWXldOIDlq1VFAuuh/aRMt5T/DBtmAVtF/cVcXn1IT+d9Y1Z
C2yd9602K/9EnjQONmZas6oTZbpSdGcL61ToQ43fTl5oFVZXfFXIgbB/N3dRMDJglybWEFkj+Xn9
NhJ0+WYy/MSVO24vXOwSlqNMuWVk2w4uz1iRZHs7ON2vYt0oCKRG5UfIFz1i2io+7biI8o+OPnTc
baQ5HUhQZWIotBs9vc7NwKZTo1BCM0UXwlBj9SeeMjKBFe38awnuQRUwVij5SAe7cMk+VJGxsK9Q
IH3QyoK5+H2BdGys2EP6blBp+g4p3SbUXzRdS/wjlTg1oDnSQ2QU0BbHs9HjOCkB1YOZRUd6Xwrq
JAf1xBQFtjEvM2AE6dZN//gNaVSEvV+n/u/N4GA80aurPzegF1hwvHOFmWyiR+pO4cl8HasbBT7g
3s9li4+ZAyh2PXtiyYoVbBxICFiNhmKspI1g8yF0MMPimHtCbcTOPN1XUbpDXAeH+B/R57T25Sjy
XW+NDe5wxX5jzeytvCw1o3y5GovNQtUH2oWbTnMBovm6fwNbbNqrzsc8pQuqw0GLT4qX7KPtzdwA
sRgE5Te84R0EGGiOqnogQVheb144BCutJ2Sp1F63cQhy5baPJ5Zdg5bbiZsWxX0r8N40IBBXZm1w
o/O6qUpwSJHiJblej/FiGLWUM/2Q/H2Q7reRjuPlccPYyiFJh7yXeapjIZtbqAZvBz3hKG6nAYL0
gdA3WlqQDt9UKdQkEIBw/BDfFOzC6PIpJfvbW3Op6Q0PV06W/uLfBI8xrHWKmTqD6ugJcu/SNvos
fyLG99n7YPRcUtUdxDLwIaaOIeCdKxcV8clR98H0eZYz9EooCZ9/9vuyNaWeoerF3iYc3kwuVE9P
euB7I1d5R3VzsRENBGw7wP3D9HjGRwl+nJx5QeBsYmIRaZN/37pW3OsSgXHFidX1ujiUWoPEmXRv
eYEcZE2NxiWPX99n6NWvrZZjniS5cxUIAjC4F5GodmJfkNCZ8Ycnk1cW2FBskm0PrlFdWflEPZ8G
LERyC88Iw7JrFG92ELkTyjNntfXPZF6yt4TCNIUT+8uIw/j6dw4nmsIqju1ocZnlWfOfcIT3PMAj
KYS5JtSObBN2gIPGdRppnlOtKTMApUn7hhkuBDUNnovH4ZDUtMKx/lCajRToHMQTJapGuLaS5mK1
e6mihcAculloB++HGN/P/17l3fuxfBI3+1N/3+QdFMTyRfRiB5z9tH+QV0y3IeJITP1+cj1kX3DC
+OuxGtlOy/yeJcJLol/wG3ycKtfzMIVe4uKJZ/rK0qd99xK0gHVvCMiYSrHXUL2jF19gdEYu9pqi
/CapVPpiDKgnPPQY8enVQxu/xKHbUucTbvYxDs8ZFxyMJO7kY788k3R+uLhhMCFiiZGsuhAoZZW2
UyCiQEH9mcvgZti/ujx4hj3uwOoEhbMfm+9Q+35LMnJKw+nt4r+FXUBAbQmtCzwUU3Y+MJEbil7Q
mZJttA13gglN1zTF69mSkdYm6odkEDu/X04AVIiuIPj15fYWm/hjAvzw/ocVMx3pmGSvEcg3NnS0
imzSmu0jE5Sj31NBvZXMKE/Rv1Mz8vub7uQRX4J85UEFtsgZKW64dqWM/TAsIyAUg5j3icNKv1Ry
MwcaOaru385QwX0mbYpXrvN4AcPTBTQ5lcz5yH1+4VCas0t2ms6oiMHoOrnjtZep0LjcUPa3rZa5
PEmhd5/qHh7YePO8LteqyTaVHlEBFi3fpejw9TNFjr4N5qlMem5LFbimrtDlQkLROo8QdAUuyy6x
CwmQxTt85x0g8jBMj2Ny7nBulS6XU0oK6iLglS5d5AdwclD7E2jGOQSyPHpLNycEwxGTmZQENqz0
1dLIoBnYLBA7Fv6y2HJERAbLRkq/ksoAEfvc03BYZVtoZTn6QpOTg40pIomiq3qPVLJgPofWhWNR
gBbB2Xq++v80tbYn2n0whbVTM1E0cGZAXH2nVTFDejA1ekIaFJp8XX+Z8ABVXkUY1mFB4v0EM8iv
9m6JwqhJE93/sFkklVgAUVPf21QZxA4/FWcJwBB4l45BRtMkpYa76Dz8mxKhm7yi2ugaN3/PYYgd
c8lYJU1neYCarNFf/9vTygH+ksuRQKY61pmq6vhxM/sz61TUDO9Q2UeSjk78xp3VW9eNd8CgcYPF
8/53waLX8+mqI4DgAs89PpXppVoYmlbvUTPDtRAZDIkGkUMdCMQTPoCZOm1/Pfx6o19rzxo0BpcP
aSyyYQWP8xkFXJ0Kpyx/4eDGYCCgxMFeGp2jRaZc3BFwq47vEfpsvyEBV3oI90awg6VamehV71I0
U1OGbyASZEKxddqC2X/aw+dMXii6Vys0sXhKicGmN3w0hmePO9ZR26q8HQNvW5PFtxAf3laxAz8m
G6D7yAwAsu1waN/OUudOOV+kvduZRN3ecjhL75hQcKapzEf7y9GI2l7VX2EHSvEHhK1KXNoR22bQ
UNvHWuh5sHPnsLgJaxBODRbfq1C+0s+W1way78EHvGT0hZ+SdefcWm/3OFSv9ZP9dMpLyvKWnXw6
QggMCJc2CZH4qIZl1BCCEmhdwSVBp7smGGxAWMelwWE+BdGWa4/o7fuKV85VaASQ5bCL6tF4yV9S
JZOzI6E9vbQyATvRlfoZaFkv2n+1DZR80ilThA9+GIZBVYW9JAgbX2xuttXe1vwA/sQfG1U7wwDg
KYAliOC18LozFOVti6UFDP7rn29izMYOAcwvBpz0VREB2I18puLNpRn3dm+hjG3O+RTdDRY9S4Ig
sXdjeKGPXJo4ARrMtxwG7WzBqhofJgq3I0M44z9+C02FLsHs+WziIgDmm8nmfZgeJqB9GVCWhcSE
CJY2uIJs2iIz8CvWCf/Dao6hwZWCdeEgR7jqNu/QawaJSDheX07ehxz/t3rzKCW53zsoglfLdTaL
/LG3Uira9vekJ4slfXaIS05Rfggg6e0ucvqCGyniFp9NFRERcFPzT4nljolwRwgQYP5kwDClTaF5
c1xGWOQyy1TN40/QNX9Z4gEp5eYfdnwrwSa+FAMa/+pPEuc90h2vgKo3252zIBqry1e8l0rHROWN
tZJeZ/JS1ji6RDQSN6LPhkZzcPgeFrDsg41mnP/vMltaiNCbesTvWAy6Rv4KTv/73fGlNggMIZ91
dVEBUdmJoXPEKxSnPRp/DHB0t5aNyN0Z2Qm1xJP8AaTIbnL/ppWzENpiLa/MJAbJ3lOcXqLFsZq6
mYKs2KD9ilz1FyUeGV9lf1U8rEsjea2oXbe5WA5FYcAevyogtk8MXAzDmevVgRrECIY2Fo2MoFjI
JUvsGiw6fw8eMKwP2dtKUMzi/znjtLREZEzTfL5HDpAGjOyGi6u7r7kI7w+NcguZdEeCCJSHCjjm
/boo3Nh14xPjzr8dtN59hubLuHw0cJdvllU45+PAerJostVptc3oAcYEcCCHMbDl1wGb+kNWgAQc
GwNtad8SrZmO0YqWgdeZgOXECBgxI207GgNd3DLVyeQihHK+y6ndQDld1uMrXL5wYi2XuEzDcir6
TkGZjeeVOBwpER2LhPh+rO+KgoyI61+T+p+ZCbSObQoaR3Oq/dKqbckkK77kbg34T+K1Ud61WuT8
GACPhiT3Mfa3JOq2AzROAGo3SdtpkhaB9xahWbra6AfoRhW5MfdeOMfqH+wIU35FBNcPRfq0OsaA
mjpBEr6MD6+fG3G2w98DgqD/m63NR2MU0oCUDSqoAMQpd/DPEWxF+XKr2fk6aNRVnQKqBT4yWLYw
7T5yhkgP0oCEr/aSDMBGmq/Ui1nGT3cIYr0Jr2IMwM1V8x6PI1XjnplLj7lXK7pdNO9bLWDbYeUZ
Resbmvu3/1Ll8bUybnXzSB8l34h7ATijBiTQ6ldY+6PrSassHU7WlXFNLqFASHYcjkTMFIFO1dvL
FPd6r2I3vKCowdWa/ot8p+6Bu4c4kS04tc+QGBKJ+f1Iw70Jcnl/QWSf0EkNdJJZopJileyq8L+q
PEOp7MvXEh/qfM20Fip0ypqBUmkmN/V7ELEci5N4z9ZU8UMU8cMnTX42HpzOkXrnfvGFtm6dHXQW
vlBLqVsKUP6GabSjkTCUI6qtj7R18cmflsd28y3HASGroQUNCi7+t5S2gOr70tBi2vykUpeXL8UH
OSKOMkXmKiInX93QXaqzQyjD3H0zrrhrYvmKm7OOSUkDpuTARCpSpueAtSENWskyyMgdkG+LVVmM
p9L32lt6uwdXZhsN2KOXKsescvRXHBBkLU01QurEWU9nMz/Wxn1hmvI8SpvGibLRawS+1XM/1OJO
VMvYhjaKWhyhiPgguuFwiIPoQBiWBy3tO1vyma0dZEkYtfRc5mVkA3Wbc6HP9ynL8O/6wGOxypFg
GBGkshRC5Q5F9z1x5w4mLx4cmRiTwCcyXMtWKbSZEM7lO2vSC+ABhVPP7thTvZfwBj9VYt9AOoaG
xekEXIagM5Vap+AhhnBUTHCNp6IKU5SL0mcq5KZwJi97/yMr6Kl6WrxF+OPZ6uLhuNhTmXBbgVAM
FWp3SMw+DPS3HLBXioevMPXRjfahQatzvIr2yELquRu5VCqMrK/s4Yy98pmFQq2COZj669hCE9x7
W/W1XPtLBPUSV9Bkogcv3q9GyvStwlV2FpTtwV1ZMKfwGdp2GFDuJf6HyOX0woEctn1/St8NPPjr
GaI0nXP1RbBgzyBQylauzSojLDh8zfETA14i0rJYyIaA1379fWBw/ioWedKGXOXPx6qdHynnv62n
yu8DzP8S97hM6DDyt44o40hcuA78Fmp1Pejl2r540NtJjB6oUxFE8QTCAQ55sxY0mu2D9ufOVKYs
7nB78gzeyJa2eUALVLPZ/Sl/dSZDkfyB3BwEo6QScemDy3XK9/Mg9NcIdFe+1jYbi/Nuzy2PnKzh
ThIoS0eZ8NEON/31qtj3Xhqrhk/t8yYu0DwDDGFyIwr/I3VQ3irH7vOSw+33Rb7cSPGRfIlPG6GX
IMcjcanXn2XyS/7fagZ5nMVq3V6U4QeW2jFvrO0zP7duEwAWT5Ra6f/mEV2pzAt/C/4S8u0tSGNc
cuF3ZyZZZ7cmS3ijoMSv97uHpLgQM0+cEOYn3VxCUPNjRUmqAQ2i5f/dN4uzguGPUMFTZEaWutUr
rADoIZ9CqSXMYbAUrKk6JOz6XIP/K25YBo5ghK7YfQT6rlTPIYCqK1UPeSW4GwAk1f907S2y9ARo
hlbmElOY2S1ffKgJ5M5obTy8z+jf4b1sRRT8rirmlCukXBVFcjcwFgMCVaztyVpWL/uzRfofjYq9
EozYJ6Y5Mql+3zJmWnEG/a+LTpCSQeildITbEHZEn+8AIeXTGJLQNLf1oZjULeHidMT8Y7scY3I8
5TLXqFksBK/3UpQl9vJfXmbgWDg/1uS/E2dMfTqgjpxxHRJIGZlyoyXzaiPFNzPxQZ9ah5qHt+48
oihEMNkcXiwurHMMFGUPaOkbAlpDFlcvqSNRqwyG1ScwSYUEYvACQbVAMFN465d2sV9LgCzrYTZt
Oh4mvJW8qBjRhqwboMgCdXndhhF+mvdMSI+UHuNJnFcOsfAFdo03KxLd2MlTBKnbbmgqqM18/VOK
zFYJ3NVDOqsSA8bfFUcri5LfnhSkYQ+BIRgEBf3ZVvHQyq/KsSvKPMjHETPzB3pJYIA0w5PYSsnm
o/pfHQpz7Ds9FX1SmkibYPgvNLmRwO29iaiyhRl0QxX3xyplvfb9R7vGYi7qaujUaBXYHCdZXQju
fyS1Nd7SQUxkMiT7Lvn4Z9NEnRnPtvz/p9BkytHG08XSj5qPxTZggBZp7UvXxhWFKzD5GjHztGgA
4SDikRcRGiRh5TYsGGJbVRBYo3+YprwblKK68iraL0p/q6TZRZysbEb/jmIfYTHSyi8x5p5JmiSX
cU3H6u+Q3/pLIH2Z7AVeR+Huao490TikIM/q75cUa5RRKPgb06HnjSV3BwaMJa5Bp3bImZNZngJ8
YW7TAeWNwAi5T6AA0nhzlPfTjL5mluTvHU5LMfbu5lXrfpoZUPLjHpzU8Hv594fNR5DgGtGyPScN
WfdS+Wb4+G2qV9ixJbEMFRU78APCHk/yI/MMEVBYcVz9xY9Fv+jm6iwiLBjng5BtnF24Vrn+8Lcl
KEB1zdkD8tnLJvOXnkiq6E7f1zlhYXStGY1mVsKxeLYMNCVFe07l8SEcLz58M6Cxfgkt/UiosQwF
t726ArOlrmDwTgxENsX6pcsxWCDHpBlAAoN69LVyIrl99qqRKZTVlNw8f2hpjFyYdaholTLI7DCG
kdmRZuw/cE/6XK5Uw+JqEHt0iMcR7M+HsbFBScW75OIOycMguAlzGYMUHjwvml71/8M4autwy1WP
eZnpnr5ZM1+Mgd+DSTjOnTYGrugsbmv2arqvjqS01GqiXT9iz0NnhtRfNoVrJJU6xte3BphgD8N3
Yjai/Wsk2yqaVmUzSUKTF/nodbBbC+KYtJpTURverPqwF88KSCnxrf+xZq0YfTqRrtCy5moACZAd
vlyvzvIB9iMQFddBagi7W94V1x4Jcn/+L8lYR5GleE1RLEEenPCXgzKfnQOJ8AhW0YfRQXBrQaga
XTJrBf0F7lOyMKoRlYEdISYjbIyIC27nNBUBWsUaRzdh+8xXijx0FJsfy8Wkk54Ofqh+v/GJ67gY
9n+rabMChPC8ViJT6onfrTRXwcy0Pm7RAskQUgxZcKhm5bhkgViaP2HJu0QOJDLnL1Lbck/dSBzC
S8tRzwJDnLEeQiUjBXeagMxDMXcjOoq4Ml4SKww4rzfogI31mrDNXcCcWXaYsV6oKxKO+9xC2aYY
FqcOR78Iikvs0/HSRrahcAGRNbJu9cxhrPPERhc4OsGdi5fNKzyf30+lUb2d+xMo3tFwnD5klZYt
5AXbFBPZI2z5fRQvRIldtfb0I5fvxpaS2lr0M6zbv3suJ0t7zLgPKtHHxtsUSe5whA3dvGPzHjqA
DSqwDbdVpCGjEL748sL2YpucLXxjNr9Ia2QH93Y0OuVRX2HWC5xFddZS6Tr8MCVDBPArdZhc3zzf
WCfiZwhuPUHv8Ln1rJtPpO/tL04JcDMCKiXufz2xvov9JvSjZGQi2zMxBy58sB8wYgLm/z4AZvbz
Xta9S406J+FcpTKXFN08p6SVCxSVixDoLZmaEoog2aXut8zIP0H8MORLTZN5T2eAnWalfXfvd8e7
WV1HtL16y0PtF4Xm89+sFtmqgGB0ymtRqP+SH0oMMxWWKxWjYHXUISSq0l0mj6GlW1dGNy20dvTX
U4ULomm9+zXl40ddsz5R1BsGfSuI6aNLc+4UwZzFJjbSq0X0Bc+jrjZRvOO4r1PnfwqaYBUPuKwv
47GSmVkWk/sO8J1/PdUE/1YU+51d5DYOUSStX18FWFoXRiofEDJaHXY2zfAXcPJvirm9xlCGGpAE
ynU1FuPJGkNdKQoRPmZXy3wKAyWEVI3DEFcahHzCNKlVKyOms+5Odc7CowlROkmaI9EqU9y47qM2
v6jh91ngCoOJZOIl9ibUavPLvbHkTeQzzlRzl4dwFpoSSNbMVDh99ZLiNJtjZk432tv+nUI16F1f
acAKUwFXz1D+l24ga2Ou2dMctni3cKvLjUKnpDt6Hy8bWTsYsMW2iaumvQG/18ZW5NOFcWbzGCbZ
mxSVfpLIj4Ssv6eDaCsEXizN/zscQG8zz+Mn9zGAo3IfCPiMvYxjtTg4szGxF9C2bRYHS1+oAfME
wcK3XXXqzYcNDTHWs+hQq5ns9+ZHbFwWs3oqNMPe25yoZ6U15+dX8q/YYTu/eiUxJ1O+GRxS96rN
/OxfrihMAb5fPTzWrwezXfdpMOV9lJMMJULwFhc/rYjSEtFL0z2qOtVHm8y8WCbmlM5H0OtRc4g1
OmzwMYiavoJJc1baltg0iCcZNd7hGhEKFz6izgZnGDh2mKzH9K4wcCgCHWOZ/0Ls3L/RK3kd7ZH9
3nZqB6ow8chs32oTgAnTJocxH0rH+02w+I3hEHpxhf7+mrXSL3KtFExZbCmpA8zumVeXIe8xb9jQ
MJAwLJuxaSzrBVcsEPc6gyvvqg7W11Irf6DIvUcYtSgng34G9ENhT/uvEW7kfhh5Aw7ZNImiRZm0
0o+pmf9qBobc8YF3XhZoZcXI370AuClOX0sC2AC+uTyL0PexILhBSPVxmj/3j361FdUxy1q05LBn
Pf6t0VpjgUVRxzeX1aMF984v/tZ32kZks5i43jBklew9ppk7LOUa+XDfOndX67OdNnPLHLP6imUt
skAGHi+AnaDte+jUFHcZ6uPexPUE77KvxBcB+gVX18F465K3kLE+FwPHPVOKXhEQWDLmg1Z8bTHj
8CmtJ/Mi6PNXw1wjK49/HBYGSih1qQdPCLLRxUUVzs06+cCRmFDqi3RxsRgOn/4d95kDjOKe1vnz
sLj2Gyd14DhqpJxEX+NPStYvinJh6cSMTjMmyTBsiGcV0DdqBHcSFsi2j29ufbr0HOEJUEfEx2U9
uPIMQFVN3mSAdMux1VYBfOn4mLBEq4BrZBH1NAXYsP4qnNA6E2iwCnjsofOyee+LR46eYZtZ5KZx
qRqFxfEm6Kf5hpLGb0DNOZOGpAvfh32YzgaMoZn34+ng6LaCqFJZKKfrusx+PnS68A/JgY6c3Hfi
dQ2R4exvpXZSUTpfLaTBYgzNLtQzcmCjbbSHFgVRNascBBtI3lqt4Z9yY2mc5S9CvxKiyVbJ8qvU
yGaR8PxKAMhgfUgVqMsTW3I21VUpn1k4SH4xLwkdEOcIr0GcdERi6pPEmoThZnvqWcrmhMEvKIp+
yyPlMqVbwKFnXPFXw+E4PWkI6bKNuC0XWCH/5y8jivxyxDiVp5a3gR70+R9dl/spmQb2Rg99nsgS
EDN29oL4MtbTapWJK8DK+0nD39VVMFHMzcstgMupenRB7Onk4XeOKyc7W5Jl1Z7Mkn0/RycTx4bp
Jj5cJI5hsEblKaALwjMBExY75xtOMfIoEl0eI+vGoEBtgXBKsl1uEPVITcQBvd/Xarv/ukpRtxqZ
FnXU+4hc5G5a6Xfsn9Oq4ptSDSnIqVanqfdzkvDYlwlJAeCn6vydDifBPed8mF6Or6mPuABlkjrE
VQdJjCsNvWIvazrmZcLpLYbPZHhgWULvqKBJHVTOIDYKl0phu2bysr/tXWjQHi+fq0fZ/FMEaXci
it9uTvZw94r9BmneAXDlCFSUePXTm2Q97xCY/Orq3Pds4o+1eMTZcqAB9s54zg0sr+218DSDDwfs
8hq6vU46nr8plSbqJf5BlT6gcqF++IElJOFd9VdzhQhTJkuiX5P0RKvtKivXMc5YCgsKsp0jE7v2
uoZ2AtrMalM+K4i51ernFm1tHZuu5qCvTQ9QuKbpz71xDpVgl74ChyDK2KTWeGcdTSeZ6qBmvedS
YSgXJIc5mH3jLP1UPPxIbVawL2qvCc8UdBdixFVH2X4+XF+UuVgqpQnOWFvC+53b6CAFayhlNrvu
IyCD0TcOrJNQb4bsA44w0IpMg6A01W32xSyBHGhlaviWDABa5CzLHPEc5hyvLHnRCsqqBaZVnaRx
rdi90LfaLAKg21e1I2W1x46QKYy9FSpSPh3m/s6P4OETRJ53KRPSSkpPPyjI85AD1NmyJSObIw4y
emZRMP8AbEFZTnRH5bc9ayD8ltlR9HqVu6kQdkv56Yy8cXXCk6ypkKoW8IFeHy8E0mUiDff34FkO
Y5rFvZYMDOWGNwqcAJcln+to5PP8GVl7x9Re3g8FOFD2SDlq0ebyQvrCh9FadBvapka7jwjbX+Bb
ozzUm5ysnWxgElRg/WJH1iFua3jUfo9A+/WwQmcO3KiJ348jIv6MZ1aI7wKHrbpIWbgra6YkXzi7
2ktCQUyd+aYtLq59TghVzqrcmjrqdogZ6OrjT//mI3bXtANc6oRIzRwPSWsQbE4jaSS9dTlhIiLD
/pHwvdZFtUza0/CE77GJ5BR1B261mCb+Oo2k3lIkUcK3ufTh8K4I3FlqnTeC7WqihR0/Wv+Iuka9
dlJX94/1X7Uv5EbOn1kTgRuDjljb+hjWELFfB3Sp2cHFvFivbqgnoZZtEkev1sMeqNNZDJi6DW+k
xIh+c4vioWO6ocXw0xiF6y/DnJmgkOBkvSmrfVVWBMlEHyOtKrHiJPGHNoIXTwrAhbZeFy0vRHYp
hZzwF/rScm+yetu387FevneG8codC88Xn1opOaroKwbTyRf1GjMPrWu05ewbbVqrPZvfTD5bVNNb
Bl4UiqeGv7BaL/wN20YF2Sa4UonAgHypYst/4Yu4ezLXZPuO2ezuSwarEIw9mPlBdIgX+zr7vSca
K95dgEEvN4oahSxStiolOrfuM2Dvwg2ihiwF5gMerhOvcJM9A0qH0p130jNN/0KURb2DmdJBHPrW
l774NHVA1vtGCLAuMFNUb1VZD+qB5+hmXCDhZGJ+g1IwNILLJ9iNOmzgKSmqAzDFMVpcVU9wRBcj
/Lszl/k5+/Hzo0m3RKF7wow8GgaSZGKKbXTe06ZZ94RdjdqAxmkw/2MHS7V7vKiYt4MYNgXF5hnr
OcCVUcc4fcpUAWJZ/X6LxaBkNJkxozqe3h0bxwydonvhtO/nbjcHZZzXfKJsCFh+DmjvXvwzYPjk
ypM2B7KVKGqEPdtsaFwH5yQ5fmjUfOjxbLOCAkeXLwuWRfege3vKV9OC47x50wW+opcim1O6vDc4
u4b0+/J78EFYL0oomGOTZ5iLroxxczvN80BnAuXhmBhL/bKPUo/i75vLkLAIhK9wP2H3NNN/C1Lo
SvXLJCpBntLfeK7mOeSQ1RDlIss5YGTYbi8mSATRh2A8pE64EkFTtKXtc1Zbo7aymsfMtEWWi3SI
RPBUPuI3oUAObJv/GK6dk28GIDBvIGMb/SN23ljdOqyrL/WttiANsGkHs7ub6JkKlJ4vS/5j0KqU
P7W5lks99qnWiH5O2Iu10Xu+ROfuRnxDks2H1uPgW7cC+l1qNnfrtgd2dIJUZkO64qsKugotlHsD
9MbF1v1RToqUjNY7gWdPwI1fSjHmnIVIv5wgcoXKuRuUdog3s+EGgqw0VM7wQe1H0pq3TRHFblwL
U0oa6BPjac4LkCwwTGN/JD5D3WV/1tZfwW5RTpYbCiDul9f9WvICg1yYAm9FedaNFsFqb/23sOs1
4EbZi0KklMaABjzRukhf7xzkc0FevCKJiB06+x+89KZKNhI66FemHxCJLV1Vy3BRmZKGVXEAsu1k
7gG2gS8Om24KD92k1G5OC0WdvAbAflnNh6MpBk+ldMoeQ3oZiLuO7U2IYK4H/EiGRSOYjJN+U7Xs
R5MBTPvK7r6N3tDN/mvXfdQTdvUONFhNoVYdYm3KE4s7OuOeWG0dfblp//VMr2yS03gq6DslrDi6
T7WbXtvfXchxKTUaTvQj8jPnTY1ZUC6KvGpzZx1Yd46pkyAdhRQ5L+D0LJ4E6c9PaErnNKV4mg9T
GXIe4u4WMMFypKqjK8xTGGi+3RXi7HDLZfcZKnLyBMYDeJMYbbV7imKr79i351yJw6vs3553pKmP
XjWfXP8ADmGHLTSICKH6UWsIxRw14QbmBj7HdlDIrlTH6O+BKe52OpxKXL9gB48Wi2ZYeF4OKq84
DQ3jUnWk6pZrs2Y4Be7a6BPEQImv7R9nQN39i6YAhZaygafZvHskKF+Kmw1JzCFKa+KqEOSaZmF2
rKi1z31Y//Ry1/5nrR9D9GsENdFqrroIwYHAijZXNfcgEvi0SvIfa2BMgcFKx3XZGPa53KNouuGW
0bV1X3kkjQBqVxoToKV9nGBqMVS1TarZLwzs5U7aqlyPWGCxc229dKq+Qh0Mlc4Q8pd2/3OwgA2p
NX9qQKrZ5jfZKIp01RO7f8FJ4tcIlW1Cuz5KWOlyg45ydSlRLF18YSt0PZPIHjFeqvE4C97EYI98
OtnGRpxuFN0cczzQJBBCFeuQXB7yb6LmKr0b3hG8RsGmrxkr8N+DNuNx+ySGarL/hqQ4N8Py7IWN
lXpax8VmMb4EawzPUl31EleWHe4jyPGRMEx/MSIBGg+V6c6M0MS5LimeQ7n8OckdFE/JOavQN/Gu
KMR8BG2bqvHGUPgL1DXgkil3Fb8dMh4Ht6OHoK8V4OOJN08OiHUN3LkyzcRURTQhcxkZ8StAfNKL
xUjDdj9cgjJiGKPINkzhXkQUzcATKSPelkWgrqXGhD7Xc4ln83CwydootopmICFmUfHjb5HxyzWF
KIHYz3qYtI7DEN6ejtLTGnL2hQpLoyt1DoW1tCWwkYorZpihy0yD6seaEYCYi6tlhtcOzpt5hkBk
bYoMRueL+zaixR4Ssg+wZrKtL8IZr59MxHgdqXdUpMp2rsEqQaFYvP5O73lWB1R9BEhwBk1cCYVC
NrjaZIFPmM9IYK8nnSAPmplrBGWjFPUMMbO0tg6EsweOBygo1prBGFu6Zxzb6ToPRrsSrcZGr/dv
epNpDjTPSc9heb+65RAgeYOUiPsCisaQahv8Vug0TW7IVPluN4iKR6kt7MHL1LOWPLNvvcAOhPnk
41Vw+DG/y0kwj1LCvXn05QR4SzrIwjcETmF+zDkxqL65a9F5bN4WfZ9UtFODdl7vje77wTNDSl9w
tA2nhczQVI7ZMFtYf8kMDSWV1Ct9josZEvqrfSTnfUoqkjI0UhZ+UVFeP5ZEpel+caOTy95Usphc
OGH3PxgttqBrFuV/YScE38pjI9H3pEXmNtD5dbvltwG2T1E+y5mjJreDKzu3ukpcf6dOzCztrh6F
7n4fj2wtQrP9JhV27NddeNv2YYTkO+6BwpY1Fsj4iSuEpyFYwYA1+SAVFozhyIqdldBa+oLi2C38
wyub9q7hEzTKyem34ecy93x9zmAwIJKGLi6po/XbHIgnUE0QCVWGpZSVDuCEnLjhCvIZWeNwMNBb
z1PUwA9+fIWvls/vJa9rVudcvUruZLWnEZHkiJqlFudZqGFlqmzBBAF8a33h3IGYwz50TIDHmi2D
h9Im3H2dm7XugQD2wxScyywuHM0+JvfQhMKSExttLbCSVunaPfGWRh5C9dfonb6mveCAaTDEOz3p
q4YmTYrwOiJ/KQIhs67jIk29T4j6TMeg4ky2bIanHL+TCJl5k3ZWQUgODJKzpMdQAcVn0sfN1l1D
Vg7SWKqFQkeug1PHI9lfXBlfehyWcpp/M1e2hxDGeKDCOf81VSkFLgxoOaYuPSxDlbOCkepBrAjM
gMqqc8SGf+LH//K1vqSmtxIPQq3+EfYA8F0mamVyNzp+9RxgbxJFX7O49k5LZZRxJIYl4VfmKlfw
ItXuXgFAvnRA8dGIjrlShq+SmlXYTsj5R+gZOcJZTRQUyRNFA0jKaziKo6zUd9JIuBz//E+uPtvQ
VyQn0Yu6SJhrOhDuY52rPhBZBrZfYssSZx3TjRWIbqxpT5rsPERztYrGPnlsNvw9pG9w1QOfbOaq
685RZYDwZGIBStiDlw/angrzJiNzLls9UoIDFIcsFdjag2TCt4/cP9EdqLZao6M4256fMQDPNHFG
LQu/C4hwaDaLy5+hZASy6qrUlkYFKYkcdRfQjjQJCsAjmvAI/Mjpqtkw2dzwW2pSWFM6eWQ56hDx
erFqoNrtUOUzjeQ0ZPS8lTxGGGNUCxgvpx5/G70XmnoEebm1Tq4uK//0NjMkgcmanLFn7AGR24ny
sRniqr/8qYRnhARpjzR0qXJEcNBi2cCKYkLrjXlzVr+dtg/8/Qt42TevVVpQXVmiLDwjX9vq6US4
Z49YQfE/+ueS0xpz3NiuUg6hlXpCRoK9J7iE5JQ6L22deGwu2WSVeYmYL23oEBM0ecJashmFZtLZ
QRO4ggvERHx+F9ji4UlpoNKOBPVxmNyOplECUUuczks7imh1GhIrBJZkYZS8IXJxVqnKwtdtISPW
zt3Awf6jbej+s9oGqTGsQgako/XPPqNr2bA2XtgvxOI2u1Q1tt+ZFyHGu6ZPV5usAHx17bIW+Hpy
jacCbe12sHv7B7fFIk16VlcHtMMN382C0mvPoqvnUrShMZuSFWkeWow4A571Ajk58HVaUD+bKCeK
byaBi3YHD06t62Dt+iYWPegnCJCW7eX02Kj/7plaUq6FiJgJh9HcIbNPH42CcbiZURkhnIDajRES
Scd45TCOL4MqpS/Mq+amGUAubKcZnpPuAm+WFKOxHpzBQkykJrX4+3jMuZtV/F3dOTcwDsOhNfvV
jf3BnsEZSxwu61Xc0fFum4/uWo+g/TwdwFiIqb/E5T//UF8ADv8d/FUdRn7vKiJFGwPeLBf1dRtc
YOVnRhPEavlUG6SakC+EvkvBQrhPOp1w9n8EqncaFtKoS7RDP3ldGBy9+yBRgSTmoKvWMr2vb+k5
iDjEVohi1H2Gjo//wljW1j1C7w3LazJA0VI71xS5jAyvnIlzhx48uwMaqaQLl9UUNG2IE8LbKxzh
sP1zKT83Xm/F3WwoqHuuXThzde4a7bTIUADF8QSkrhWl1uB2lHWD4CE3i6oebSNd0KI7qM1Zp+KS
vjPYMMUN+wSoqOrOVtXkCCe8Q9RVyULRtp/2XhmUHLAwnQM1d0ADnoXg5+8W20/DLAyGUwxCDVn+
zT/Nq6cohAOXFCuWTpdEkKO9zRnRNupkpDP3JXzccXjPaOFYjaVXJWnBi/hB0DZZXK1i6oS7IFhP
JyifULSOATpmU2A8XR24s8c0svdCU6QMb05fl6rRjSFBpZ3mYHUP9cqFKw1yeska1SrHQim2YGZt
xGy4nva2fEQztUrUViCNTz6UpKqhMQnYcfqA9/4e9brhGS4s5RzDgo+Zb8NfzRq7J51kAV1Qp1AJ
Ya6mLK9cuQfUhs1SMP2dJoYXWM2wYr0vyJ0eq2+bTCR8RDkLgNv9Prj2Ybvgkq5B2n7UulnmVYUi
+mYvjZPoDp7N3BKcR6zDFydRjnGfTZ0Bdp8LjqpVXOdUUcUjmfE6XVAmYmPNj162U2qxHnnc5/dd
EonALk1BjXHtstvonWxAzuBxHRk0dxsN2yEk0igqCfYivwA0hZszFii3jEWM6C4BlH8ebiCVjfkR
54GaSSHzMDzX8U3SBH8IVUAQ9K/cmL5Sawzh6Ci4mcXmCdk7u5vPj9YZdRf/gADnQ2TV0E1kuEng
UOt0YHJhRlRBdvoqPtG8WUersSh7r/DgtgZtBUrbsdBroXETa7CmAw/o5p+GIIDtHHX+TuZajgsL
3i799xcJzRZaS6Y26sT58An0pr0K19uOSc2O/bh0ML1SjEtpLKeWl78tSMtnA4Sh1JKUy5Lk87It
woczH8S8H5ZqRRu3nDPLlLqbDxqUWto8T8Y4kySuDbb4UJswqtW5Pjr+dMKIo6zBJ19TZFrI/2JS
+UWvrwAFeN9blWuslpVnESiKb9flzw7m4RfkIVWE2X9XUH/WUdEN3XpX9fkBn+5C2HTIcUvqzWE1
mz1hyvhznpY2s7JGEk1qkdU/r++dXWf+fBxGNrGXk4PqO7jOyPHfNPxlYqx7+ZIYQ4HHV5Azc5OQ
wsqKteA8I0vw1mrkhES5ncaEpI/ridccIJW3nRdzRZtzUaKaHnR9kRU6VC8VQBs8zgZiC37udJKS
XSPdUvb4n8kuA3CTNyKWs2eCkAJjVUbml36Tu6EmSd6Z749yeRcLSSRsn+gh/s32EFjrNVVnoGCY
u/mqUaJhmW2EUZZ07+OOQSBG0FDrNtUpyck6dl4HEVQ3eqc46DezRMs6V85665iR8yw1XDWLIjU6
gRn9Pygd9O1rjdvfiOgSSoBR0vPWL8DrqqFpQUBVXleMz5YHNdnG3uCttXsHJ/s0mnCfzhVc013y
wFvAzB4UCv0CmTP6Nl3mOvvDV7/PmKBR/W2YiclHVkVywYKTA5pvk3KFyFH1Apx+9u3QiK89UnBZ
hP/f7CaIW7grK4v4h0TfyiMiHSll9Piu9n6GMN/4Mn5l/WbL42jGhZyeLCkag06GfS+XyHKlucTr
iJ+QAeh2HcFKM2itJM873D1qBsDezaCFHFxz4DlOcHdC2Mft9PxGNXaUnHaoeDLDQ3ncver3ZmQM
beIXkrDceMKzgZWIn+qlrnniDDNivGFWoVUd1msJgjD6q/zB6AqVjPyKVHbjRzMGW0mLYXRC9x7P
/U0kuifizsUAfjpArD4zdg059vDIQYmzxukbw8D2j/z4relfE6IG+1yTUeB3QREdmeUcY30Mhsqv
tBueokviC7upRSSbM2HToXxag/0AM0wiwi6yJFAef5JZy7pUoR1j9j8rs5cmaACIOwX0rF3hZD4t
wc1xq0I0igtFqgStR9IKK9oEz7IGRlMbactbC48vK/lwiLqpjNDrfgBQhEWsi55VdDxdgFtEGn3Z
Nz5m7FHrBqrAz2LlvEYHT2wf9V547GjaCh5RXzQBHNqxBOFQT6YaySsTqCfFfy1BBEHk9JT45Nm0
3sOIDQ+4piMq13/7ytd0g3V/fZOIkIDLA6aHLhbPv6O9HucBkL1S5ojiQ3fNQTcMEJg4Km2YiHHH
UnAm4iUFV5fz6VazyKRIq99wxAe2Fof5eiRR7jce2Wm22M/UdT2F/pCrKuIouAexBXDwePMr6Ue1
7TTHaAAs7LIuo1k3knAo/ff2yHKd2dTaDBkAV4A2nvCzMuPp2KQbu7pqu/9sN5RCbHUXsNwg6rwl
ZLZ5LN9rnnUwHO3gLeam62lQ75FEPWr3au4XWFwqlS6nZdA1Sd1mKCff1NIiKgzkS/86seg9AYv/
YUCQjRyR5SXWVNGf4d3UsxLLqPfjAmw3arNiKTnoHSFxaq6LuoX6LZXjSpj//Ees4vyu6p0oH3v5
N0XBs2dRoZM3gRoAwvYBOcz1dkyU86hs/c0n2mlUBofvMv/grFyA03oJfh9SFhCDJmgqE4XLjou1
VZ9Le16TFNS6dWw703kVaPpelEfLojaVinoJTquo2F5dywANgu4TZUV/xTfPV8S1z/CobVoc+sDq
hy4V/p63VaFqmDx02NIrr8149Xy+MdYhTJEwkyK80m0ZHcixZD5auFtmYgEPKG2WV4MO7jYgtMcz
2TrVDQ8b0aATA1zA8L4E8VBxnBT0q9FmqJIGl1G1N4jGVNLciwig6yHsu0dkzyvV3Yukv/rj6QDv
6X97qGP0BPGZ9QKcuZIySR6OhyXjzuRWu059FzQKvbNnX8W8wVHovaG6PgvDj8+ANLS7zwqITl0D
gxFLr72JAucsqDXCdIlHwPzmR89T3/5QgW5pAQEpTCPTIn8TGhngjkYf7HkKE17WBVb6k2cTEWJE
liQErPt2+mXb/8UJ1/romHkmgIWD02oNWQxly3ziOa33XP65ftaCdMp/fQsTRMb9UayOjWer5iq+
kyMIZlZafFM1/EJ8VX1dhTvt/vC+EbczlN8kBbnk3eLO5g2EmnBHlsi10XAYqRptbg4TKsANW8X9
xmoBvF3lkuM5PXecV2g+RsXt8N1WB5BeryYrFknlW6+BP/qEMVd9dGlaRv/WoW5dDRMHtBFplojh
F87GcVhrVFdwbjsxKad3k0jBsQ+m07F9IqAYqV9+VOnWfDqSJSgYxvpPdqdACvQDsj9oF0cdKFWf
VP5JBXaK1cAjjynB6BMP98q6Qh1hmik1np/qKNopL0Z2jyjVQBL8kxkIMQ+9t5fvIptTfRAruTkL
beeWbStPSHGfI8f0cUAZ6Pf7k2q07VuPR82AWkE8hZP+0/FipatNScCatvF6Ql9UlOBi9zs1O6/b
IRdpZyAp1mPJko4RFnBEwJ0a+L/qHsYWAeixXD8UvdJdIPQxyrswUIDhYfGx7Z9BT4Df/p9NrUph
i8e2xnTZeZ9LYsTQ3TaGz4UTVVj4yEWR4OqGFZHcy/L81CUmMI8CIKXKtpnlffoO43YQ8gncV2OG
K8dU/DrEUJEknYC8tsSWq6QK25/ikP5dXEsFzSUeSptgRLOUW2eMllHTwcyzvtBd5Vezk5djR7Y3
VjoEteTTDLB0v0XhwKbD57fa9x2aL+3rOXWp6Bn+RRMk+H30OVt3vFVY/IKieF8rQ0jxO6aAxWr+
bHx7Ddy0ON8ZXzuJTOT/kVXALqcFvAlQjLEsd3lwlsE45N7t3BfIbu+n01gIvCD4YtiQVBikXxHf
JyowKc8qlv2iTPL2ak8fxQh7ksD6mFvXiQ+VeyUw+W0hdRuFyRswgKtNGFKkoGKabncysUebRfBF
A/Bk9UPNUqf+fi8aZIk6y+Is8t/udQVGGIFC3kymSHm/nLssVPp4dZv4QqIl2CeAX0qVJa5KzuOv
3u/bMIh9OMfuTJ/tw59klZjEdZl7yVYOzApGdLe2a45am4r6CfLbcvLFvsvAbLLpCOuuk5X+HgIj
HsL6EOPfB7XS9y2AQ37bdXYykOewDE0yVUh8IxH8P3aVsWI/gtRuUFf+efjH2WKLDsQyq3gOLR3s
Nf/UUjcaQGo5xHwwXbh1TvLiNZeEFoOlSsyEfu7MxITHLmBkNQojPMIfhCFFF53DzKiSP6Z5iQ1o
XPfSQEWOyGwD4v4DqGpreCBGy73qE4RMMYjud9kqRlO0NyUR03suBV5JZ4RzAv+sYkA8Idnfa/JR
EumbldJxk5RLPVC/HrQXaUfdBgitZFBTF5Rn8Y3MfhujDVJDzs0eOTiiLtp92rgzMn5zCkXHxsqk
kYF2LDA7y9AVcf0iPDNDljA4rXhHI9LFHdCVWMaqDq/N46l0AQZFJRcNN0qaYacur5Ufsl+V/qG9
WUJPFQjW31G4dqI901VjMvGTLkK39XQuSxmrKiTvuu9CdUJNLg2nK+0DJ6BiVZGQETiw7DVYIzay
UF3dDQeZjbqryXpseJMrkuSfFudWI76LgIbHjxyfGKGmbjTO48pTy1r/8cgBsXVMkrtsJLSH31Bx
hcXluGdIrP7OHu4vJtG79D1L9MEW5lwGOFYqbDRR/fSkmh49dwdXt/ai3ETnnUCxABIWWPi1gz3v
UKhU+52LDK17i5KbQg+7la8hidjaAx3TKjwtBqWKnydKWee5C3AQTRUzS7CPumsYc7G2L407kekZ
xq0xn5QLy66DhJpay7QpSgEuFniUXX8P4Vs4MdY0UVIH7b2H/QVSmkfNSYZ1UXR1E7qwUhAcptfS
0RuUmxPB/mLb6FNqAALaWtBjrjfieabpB1U4PlDd0Q7EXhGJTUy/5Fu8k8YkPNVv7TVjjSz03RNc
PtSXoXpMVxFMrJk2BXwYYnMF2ln6euKQZcIOBs6BKbAZmlwNQqP9EIZ/3pX47vYbTRJZt0QyQBxL
chTt1wpIr8h8Mi2BzmLWsbsEmbg8T05z5zW32h0Ohb/qnbwh4rNoewfLv55TgJBFrShoes2l4Qob
nqxFadYIprKR9+7H1k/VSFlCjFRBZQZLkyFSt2AyUQuMfjdkcOAPi+beYLtUjRks+XZTUewSK+FA
xQaidDHnhnA3s0FRtk1BHaBbhlrybDqHbigQbTlO89vQpWPUpx9pc+87hmtz6WICVjZSfWZrAMKd
njL0WlufXUSX6s1lwhzICO5fWPLpIS32JIDNuqhLLcUQD6SWXa2GWGfCX/TZunw2W9hcmLdGc9Gz
KjpIY/qP+6SPFeC/+LIeizW8Ic2mfNbTgWZOj1MOmmuzOYgWylUCYHiOuOp4NEiQv6fwLtmoL7fC
g3FqUhfI7bLLM2R9M+++q0Gqee5aHRxXTg3aNCCMb9ahvqOz3tJYcPpF3k9u8TPyjWwWUvqvtjm1
iDqGyHL6J3XgZsouStrt5VZrT5AosormV7aGPZFhKDAT8zD5denQmrRP1OAh34qyPux5zwr0B02H
N51Es8Rt8d+OiXbtLQsuPGGS83NhOMHWYsk9vb5+ySb4u37qZBaf5Fx3dJpsEOwMZFZFGCjkbdQD
i4ShqmjjV3LEBfrubz+74hWibWEaHsH45nL6ndRrcaPk+WFN6msUT5s3FOcBjIGO/42zMTAvM8Zj
m6QKF+sol/sSWw/9nEf2LU8gax9dJzEbLwP7kmhlcTNde8DByguI294naTiR7CDXOrCr1dGKOHx/
hNUSQ3A9fZK90KRD3+wMYdtdTehHTlMWnitsi3MFLaU8wqhJ5q2HvSmNLNxKqsCeUYoSckUhyKC8
gfq8lGYBKAGDwXtaMFoWh5Muo1aVSgfOzjukENtuPa26mXFHCdUwYnTNpp+4DyB4NZftJrC4CxbZ
NyHP86Xg0FbhoSijLj6tW49gVcurjyYcx4I8UHp5cZOGgKvFoSLxwNwL5HwTzSsPeNrWHBnt8Aju
TcXW3PyPWM5VkMpgZVu2wQVVFiIAYlUgg024ANDH8f52Pw5W43D+BDduBhP7TVzxFUEV3ugguqHy
OMopSxG6M3X06VlFquiXJntOyH7/xHaVgYI8vVe+cxqML8Apkv0an5J1FbQF2cO/kvwrTFbyHR0E
Vae5B1CrO3Vat6YklIW5nNaS7NTxCDx5euhraCpaygoeL9j7gh8EAawu5es3m8z2ilg5xNScmBH/
1oQRQglNad1UqCtIh4qLEBTIjMsc/0nJ/dBoJsYyiuVuSCri5rz5N1AxnCMSV7G+XTOaOQb2HaGV
PvVuqPrfAV1bIdnlZdHpck4d8lpPZLjNfY9OgXfaZTwSJxhM8pV8e3En4LLvoMV35CpGEXHsslJ2
YC2N5SnKwa4+wI3lN0xrkdVVTMzgjWkyb/U1PElxhNX3A6sMuJTis0PWFTZ4K/ujtehg+dkgwYaM
XDMe5Q6KIsv3jmU7GiMVGTZvgJdshfNjyycoeyBtIneHIpcucdQ6iwltuReaNPnwrvu6LIahD84z
rHWk4/n6AiSp3SrxBzTrAyZn1yPr6FkgX4fbeFApEduK7IjVq4ztH6t8ERVUt5iMF1VcDmBPDkLb
QsJvbDyesqmTt60L6f/exwBf2SO3TLwJmeU213ap7tYxFVpSuAvHfaemtr9fr1NNW3Ua8NocB3Qs
MOmyhBsr4ZZhJFwoKVreLsp1lON1fySvv0+1SQM5UrKglsPvdmp5jSqRfeLZYoG2sjoHKeWkgNKx
ArPQo3nKs+R49VJlPsy2AlPq3cmHsNnPgq2IgK5rjcDYcDPoKaY25weZcLJMPbeuZNE2nfXE7d9S
XXJI3ZrOf9Kfyl/T8eKBGloPTSkSTlndzHVzPfxMOuJs2yi7OYWFe0miibeoQU/eFkcwB+C0lU2w
RT9nUabNk3T/PSkfcAL1SwQI3T1a1dpU32jNFtgOqLsMNuM+PBGnvggZz6w239tVR9CI+qgkLEUK
QG3KNPUyeN95d+ixPTjRwUpEOBaulUpnXued3ArmP+81StkTVbyMB3r3JkDG7zudYpkD3/J9u6sz
T72GRTubjI6a7R8N2fHluAsorYCdQ7tj8BdDfyPI37NGTqL6el2kIBP1sEY4tExqurJhA0ai/wTk
nayGFi/0Rr+KbRn2XP0LpAsd/fryDj1Xu9NftTG7RGRmcii0S6vM/gYuqsrtl6BrFmDfXW18s+hI
r50L0j4XuGgbXI4Vccv9ue7u2gWDLFkXBCNhjEbc23PJVduPzaIFXpyzoMkC27eTpS8c5QLronIJ
luDcwkFQKPVZJZzTMQzkoe2W9e2dn3H89OO/ahCC/emDVFF6iSJChUY4TZ7MY3JM6r7OuA5j6PyB
Ud58NpJPffCoQ3x+rKcU8pr+acivdz7fycA42yPuA6/WqIvqd3ZqwDy/+X3z2pFbk/zZjkwwF/jS
pr5VRHXu778wdbXXLP9/0r8Lm7pzs6jbF+dLcx0Xjatq9AgCX8eKRftI1TinzsbvljdcoTOfDo/u
2pJVkyVSBkAVH5thRwlQsuThLZwVFKj4nzWI3NZbIyNHVucE3cQB7qx7HdPvwXo3b2k958sjS8I+
RnIGifDpN/3I8btgcp5DjM8SdMgI+8KmbVbct/5sbiOmJfv2YnqcZ/nqyvY1nQoKBdqtrVzQ8tHB
kMS0bEZo8A0j7l/DAbLAMYkzcAOoeNyrVmVu4lXpovQtNT82j48gdzkgRuLrNMfVOAk/umJTL8DX
Yfq8noG0GKfTVuckbHARK+bBV3dLUWAkUDuLs/p8rj3urn9z3wLeUR2JBN123/p0RQgRVGFZPNwE
fbFMaCSxEomHOBcaXldGHVJt9LTDy+sNW+WSuoViaVqn968Wu76Zr2f7bPidPUNrdwxYwxPZ0dHb
BYb522Lwmf3mFf6ny7xRJZchADpa6W2wjzuW+6/2eVOpr+lQJ9/YVKpat6d+d8CzYK/mlY+77ctx
v0bRnA6kMTHiKghbguM4BU3Y0JaK91HNC6bnTvuCie+gD6hfYesX+3QU1TcroTtVhXXWH6lqcgVQ
VRILDVdIivXTJma7nl/U2j/fJQJ3mdsy/wno1fdJv11SufBTg6zB/iU/AaKBDdP9a1dkKXg5sbZE
hQvPen8rje5NXerF5XKnJvoD4atcUiuM+eSHvbaydmEAKSa5xKyv8AwUjrNPw9R4KYFGqo3GF7hw
r8Nibrg4TImnA1+nUynUXI3P7Y+kEZT7hA4hq5KzBEOZf3koMWPdrY2e7JS5y78f2U2VCabGdgiC
+YNIJ3Jr409cOuaxDct2QuW78nHDGMbM4Y763jtUbAzwcpXyFgeXBMt8b7TIUH5t1Begil3VaVuE
+nbkfdgKm+7EjGWpmbo6v9oFHbDO8hA3ERhL37Lpm8b2f80Zc/cROxToz7PgFCbJ03vrTTwubuV1
fRuLsODyBPGNOFtNbQBiLuuPXeBp2njxR5Ev8K3g8mZfmj6A1V2+ifgQiRsQ6e37XleMp5YPb4XX
BikzejItCyaSWhVjoR0LaOHYfL+AYkSD+iuV0HLCHFYJZhUPSt3VpxxZ0IlAdz6JnGab75AlU1e8
iJs16Bxu+N6W9hACR3uj0ayieNVeiSF+dMxjkWzNN+TGzPZpFSgneMgkLJO3K2KixSFazOcKGGNp
BlQMfF54UmKJEde9MZncNkVDaMaco16ecSEo92JoPHE1UrOC4dmvKChCOsky2MQuxLPh8w5yGPsj
zJJSfkCUJnpKit/NHeaT0RVQlYJXxzm/hM05bc4Y7UOAODmMKc3P4Ww8aRhsePhpldtE7Ckz0vRb
XEcqR9LMxPnX2hdAAIQlLU+7QfM9YngNZScnwz4U2W/b1o3wbv2J3i/oNfZR4htPvE0XJ+xwEL33
0glXm/EsRj9vB8o/jvwknpdbrcKPFdl9sBzo2AHMMoyd+DariE+j2EMsVgENUUQiUSTUhz7NHPBi
ApCXpdX6Y2OODecSCwK4GcQw/DHakIWgLDDOm0P9a038bOZKyBGXKboL8fbFP1ZxMYVThIvkcOed
+l0iwcK/x2QPAQMWRZaoVQODTjWnPsTN8R+M+dUOSoTqL6b6ZBaLj6QZTUYMYWrr0+wVo1weFSef
HUl+GuDqU7JsXA+gtuD6UWYYjM92oHBjWeHcWs4Nndcy8H9m/+WuFyKlL+HVx1X/sZ7albVAIIu/
t0WGxfT+wXyzB+LfQQ42N/A+VPbJRRpIJmSTmd6WTyoj3ixbtg8pEXN+E8DgDii+c4jef2wGZ6cK
2pdDrdw/oB5Ug3h3KY97ZMmx57Jvk/ugRKtvXTCxHTW0TSk6jDyLkJOCTriZWJZN1twDyLt97jKh
AFNZbZNybLANKvBSsPebCUK2xADtNRDPDYjwDi4ILm86z6ots1Xswh6QVkGVJeustZOo9HbLP0Q5
NxTWBwypf7noSy/WmHIq5tlA9f7y+x9f4sLVI6HPKCtRiH82ggZcxZwF3+EyZTYeUjQEmlXMsFCm
o9GpTqJN1cFvmeSzYNluqEzPO4UrWDyjJp+vvVjA5u/g/1AKS+ha4IXbIY/UOALC+wHZc4RIbpds
b+76m8xA6mkLC63tnPW52Qisd1LSWBePQ4LG55IPhT4P3z6BjNXmTZHoeu/jEn+Orj1BoGz2E4zJ
q7beI3A5FeZcXSUNyCl9Wr/Zhki7k6EtoZ5nDx+3iodvyihJND+acPD9Lnw30KwxE4WD+024AN+f
NyjzRrtMZul1dMW5MYnm1vuRWkm78uGOAZCXggtbNbkLPqAbNrV0VsQQlHx4pnMCnnqSPzWSLtAZ
/DPmG9SurMbeo5/3dnzw48WJ8vdhZQWmSGUyqRbQKmzYOeCP7M6iOfkHrgI+BGVuonjGrHm9do38
M8ri31XdtqZBNPTdX6b70pn/nx2AU4zHd2vIevJYfZPM23et0PI+UkzuNyUDS5s0faHYDbfFRu1d
rqglayaMpUGc13+DikF/yfekjI7raPrvo+U0TV2z04JJiLKS1s+1f5Qf/m5+bd5XuLWZklsL8NPo
rJOPT2vKe+M63fKKqeGLjy1E0RyufMyxbUlmbztfvc+VviFJnei7ljf2bo2NRsOhpvo94aGv+ZDh
7EKRpa1/Fv3NSsr2SlKwfQYLiS18JW+XI53eWWU0Y54OQJiMIsy8QnEIVHBr7NvAHZEre7WiA3VM
QEvjp3ditc57zmo/c+ahbxPM+S4WsK044OtYjHb04loAkK+3H8SJ3+XGpk64enH4u2T2YKr+IKgG
sAiyvu3EN2nXaZkAOVp1Atg4oMmlYKjsKwfXk6fxrgpB3rFkRra0ue8xiB9/woCezQ7I2ZogQFgw
pol10w8Wcr5SyvNiQvEuCpcbKbtqOmORw/wWJtvzu15zYvwjb2JKy7XCKX2v/LoFYIznkigRyZVg
TBsBkNCFty+8py/OtmMCKW+QizcVqN3K4KItDVjEjtVx7D+Oqk13772IjHD4AfQN4YTwWJVF11wY
GGCBOOw738Tf4ItIF3DSeXZL51LB6GDFpOe34YIj9EPAGSBlynRRkafStckuvbRf+h/uNEbByCBT
Qnb7pYEhMoqejgPWCpxnXAcP70Y/EA17+vk3ALQZsnrIfIPJOjlO+Z/4h1qUNWHLwiDwIF73449R
BjycTxFMi23U94Dq2ZchdGD7J780IjyABG8SAY8hpDi0JOS222VmhebLRgS9OlW6zwMtHriHHNeZ
ubOj30qL3obaizkYQV56m5QFyT4sfYis1PSOMtAEVRniOfjo+3C/8iCLLLrHg07RyE558N0XrrWI
XuA3zF/h9R+j1vkm4Oof6M1KxexBJESv0gbpQl3UxlG/FSzCNO5Q6E81fe/Y2xGvaGkd/mDkvrz/
1k/c81PcAQ==
`protect end_protected
| mit |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/Keyboard.vhd | 1 | 3036 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: ZLX
--
-- Create Date: 15:22:18 11/06/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity Keyboard is
port (
datain, clkin : in std_logic ; -- PS2 clk and data
fclk, rst : in std_logic ; -- filter clock
-- fok : out std_logic ; -- data output enable signal
scancode : out std_logic_vector(7 downto 0) -- scan code signal output
) ;
end Keyboard ;
architecture rtl of Keyboard is
type state_type is (delay, start, d0, d1, d2, d3, d4, d5, d6, d7, parity, stop, finish) ;
signal data, clk, clk1, clk2, odd, fok : std_logic ; -- ë´Ì´¦ÀíÄÚ²¿ÐźÅ, oddΪÆæżУÑé
signal code : std_logic_vector(7 downto 0) ;
signal state : state_type ;
begin
clk1 <= clkin when rising_edge(fclk) ;
clk2 <= clk1 when rising_edge(fclk) ;
clk <= (not clk1) and clk2 ;
data <= datain when rising_edge(fclk) ;
odd <= code(0) xor code(1) xor code(2) xor code(3)
xor code(4) xor code(5) xor code(6) xor code(7) ;
scancode <= code when fok = '1' ;
process(rst, fclk)
begin
if rst = '1' then
state <= delay ;
code <= (others => '0') ;
fok <= '0' ;
elsif rising_edge(fclk) then
fok <= '0' ;
case state is
when delay =>
state <= start ;
when start =>
if clk = '1' then
if data = '0' then
state <= d0 ;
else
state <= delay ;
end if ;
end if ;
when d0 =>
if clk = '1' then
code(0) <= data ;
state <= d1 ;
end if ;
when d1 =>
if clk = '1' then
code(1) <= data ;
state <= d2 ;
end if ;
when d2 =>
if clk = '1' then
code(2) <= data ;
state <= d3 ;
end if ;
when d3 =>
if clk = '1' then
code(3) <= data ;
state <= d4 ;
end if ;
when d4 =>
if clk = '1' then
code(4) <= data ;
state <= d5 ;
end if ;
when d5 =>
if clk = '1' then
code(5) <= data ;
state <= d6 ;
end if ;
when d6 =>
if clk = '1' then
code(6) <= data ;
state <= d7 ;
end if ;
when d7 =>
if clk = '1' then
code(7) <= data ;
state <= parity ;
end if ;
WHEN parity =>
IF clk = '1' then
if (data xor odd) = '1' then
state <= stop ;
else
state <= delay ;
end if;
END IF;
WHEN stop =>
IF clk = '1' then
if data = '1' then
state <= finish;
else
state <= delay;
end if;
END IF;
WHEN finish =>
state <= delay ;
fok <= '1' ;
when others =>
state <= delay ;
end case ;
end if ;
end process ;
end rtl ;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/rd_bin_cntr.vhd | 19 | 13156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RZm5UrZFV7JOtGxR4Pzih7NQYLp7LmPE59R/6o+hZN+ZT+nCA+l5YH+/j+E+cmHHWo6IUrn/ULaG
ZkaGINks7Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MRNQzUt4f7a/v9KMrin25EUCYvWi/twJzLlDdceTmDN2GCvOURSU7hHpsmsqqCb1xCeaV7xbvs0c
MXpZkAPeQc5Coi1irNf+9eKbc5uIh03B/PevhS9S+La97Aj9rjHplzcZDEBFN6fiyAdKvJgOrOyz
87nOO0u5LoaEOeyC6ao=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
L17wVQWzSUChaUkUbjAqDK1dFxRQ9orAmYas8htY5fjqeIDtBkS/PldQL1EGRGrFVbxZVbStDyiq
iWMlaMSfJiAW0codwFWqGkqnH6YMctbqpTZdQPbprA8qa73Xmy9S5tgWXo6y3vZys5HBTFHxXMXj
HSJZBGLfj5+GGMkAkDYYBZrgDs/jxx605zYzRg+wKonRxjx8C7c4r2cekqFXXjEfMC6t47HLGKZO
Wp8oqSV+SdxjNfsxTeAcFxqhiABG1hbduxwcNIQO/0mgU7awDWqjimqvnE1+KO7vQU/MVpl+J+Y9
bwvxkUUMkYnqQG/HGWvvQ7Zp0u8+rRyDh2dzOg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
yJG5RZbV6QsAW4khC+YjJnbI2jNRxPOtee58pTXfgJVvj12BYVsRuhi1xiVJgak8Vy8V0UJ43Wc3
ydXie//gOHZIACOddgGz8WdlyWauaZ9sd1K4GlV+vX4K5HkoOyunq5QSLYwU2X/ZYYkTAGg7My6m
h1UvByaO98o6pNd+n1w=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QjcZeibYm0SAHW7YliT2StC14hkmhpmI1+m8klXbQfAK/yXQ8NfNnDZicIHqHpAbgVQzoGSkcmXa
qhjmF7JhXI4I11rujpUqz61fAf/3PeUiYimqp9l0xnePLlrRBeItzqfetftMnQ8hBAuI+sARuLin
j4+kHDvo2V/A6kndknmKA6lyd7gI8Mgzy1xgvua2Bfq25TZ30r76kaSXXo5N6hFVjtfwPGqnYepq
02yTg3lN97x/f3REjUh0T05iK9mOISMgvqQkxFwl6hBnLhp8WW0zJBjFvAguLZDf4CMBuYBnnmGQ
axcOzl5DWDcYTgPm/DTciq3eoilijus/JUHuFA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8000)
`protect data_block
Wy8avf52SKtFRWpdKbuuoKz/QISNFt5qyx1njgupdsY1yGpbX3zodNM63ljgbYDMC3fZW2KyZA85
bRsP6RIcYZOndRqOE7OfH1ur2jFen4OVLRXLO+1hOqazA6KQe2iZsxqSqjfPf2LX+tWfJO/eUBuu
NN/DDOvWclIkj5bWWjAOAtaj2ThrtTqPf/Wgm1e+aN1qhMvvZguqwpBvrrLcckW0KeLgbIZPyh1G
5qPHxWqKah52yTq7Ywnyt1sm4WIZ9hJU5H4a26cTUQzChHK2Zka2hkSrxwwmTmZ7I0ooQWEEHQG8
g6UQzKhhk9CGAy+kKdPs2/vSoI9RkxrUY4HloVEOl3p1A3FQMEsUHDbAMiQGAznYA7a6JSZCkgp4
lKQsS5bZQZ29rLBvJAu3DbPvK+fyUaOYB0iucF7/zIPubiPgf0+xTr7LiF8k6nTnh2QhOaw3gm8u
VqPnG/linjOiqwPlWr4/HVhCukQMM/yk+tHvBsdClSkzmOVr739g8WAxqh8oUvQuXWLmvcZ10PR4
4274FDLD2E7mjEq2oLGSjrS0MmLK1S++yWo7WqUMLrBMdBcef4aE5ZT9vp1/VmxOLlvne58oqvhh
/1744ufYxPMpdJvpMCyUynJm/v1Lyt9NI/TbG+74DQNz49lJCJK78lZcME8EM7UHuc6B+ubWNVA1
7PZPdrKbMLAwoI6eYJ9w96HfaZ2dMZBhZwM8mbQ7FThGdy1U9ECwxeQW0rxzTnlyRWnKlHdgBa79
D6e9hlTgXS1JoJwleRFdZccR/gtMATd5yiSpTsbf9d1cyUv2eewvsgxWaI8I+HPhOfd/uyzlZjbO
zDHdS7aILW0PSSw4O4LCbM7zQM3i/ui1KnxwXK9Nuw4tTnreS2LmjvDzcTrpkGGEI+JnAFIGll8+
mxMVRO4QndXwiNfHrJHat7vAfZ/XDXuUTrRPRc643RUhz86JZKC1aOYdP3Iiy28FkRoBkn87bkr6
tVdgCkjh7utXVwv5qlhc+nWnos9u8PggfRXAaZSi7Ajw8jX6s6FLAYXVl92IYdDyYJBZT7I6pUOi
4ql2ucfkF9ql5+8RiWm1SeDPDajH7w/ZNsbt7Sypir3H3M3KM+1q/ZxdZUyhBS2WZyw3ow0goIgL
9hEtchmsW1n+OtYDg5bISQvtjPouiXGoWqdyLc/fEVsBOeuFUe9DSYn0jF6zHSSSLLS+DH+N5s1y
MVcavlbR7r5mtqnhnbxsdICqX8CuCAh5hUleVbwlF2YcEVXXeCEPJtT5vsdDQXpoUXvWHjCFHMtn
Z80WkY0Qfz1Cs2o6IIrrUwdjKHMsXi5x4QdBFOQXy6sFXPWu14LqzGxfiVUW/bbl8v/VzpBslvpq
AvcVSGbnhuqqzgOkoqE12mfG89X8GRBWTIs4jn2TMpzVCOKEd76p0Gf8hwAA2t5xHVJELHM/CCNZ
25V1MVpsscSpUoY1AR6NgAoRP4DvAqJsN6C7UwzNHR/hNuMed5pS/kzhB+xMZ9Tj3J74nFKRn7Q3
JM5W7mHmdy9n0rkJUR6jgJRl4rU6SCkCOGDRnZW4D7LF8j6axIQYateOcd2mSJWUFht/xL0ZuZoW
4kOKSFiGNzhFNBqIAzRwhhe0eNSuFiixdsaVPHuPMAzBGiKUv/zkEjjSuIhev0pB/t8MmWdPmRzI
AlNbN6aVA32Bod7Rs6FSX8sdBNn+WmosAMd/mPmGM95pO/NNz7GvF/f4uShaRx6W66UwDkWcbhxX
7PGg6Q56g8ahaetujwOvhZQQdhIUgqD5hBzpSeCVG2tKWzKrSb843P57jICJRb0F6fsDuy5eNuhu
b4QtiRYcuog7Yh/puCz+rIfthFGg+7Ki+4UD7v3yO6SIbJkuwwx9YQ0oHHyir8MpSB+KJg9wQWsS
/MFNTlx6V+j2NfzBjyDRhLomU/xDnppWkQy6Z7mPf1LWILgouCIR3htQ0Bd6g/OqVJQGRmdePgok
3pSaO7rKefY6QmcdsYHr+9lsVGSIc6HZZafJcmGJvD1tDFl/nd8m7Pq37Gh9sn2AdppYDl7Y50Mc
1yG9De/Yg/kpBGCbCTQJ/X41+nTtCJZV77L/LDxZvMUfHqrdsb/sqjpHaF3AID2Z9EyG5kjFzvdk
P9MhlgUrdWNeI173BW/tx5ehaY1CmscCFrOFhSJmstGt44fmo4tH526BKNSs4FUK+ddSAXuZtEEo
qXoQOzRmAxsBpWeXRlxhwANqvwmFSVKB5lDW8EwM+6smFOkAlxKec8YFMwk7nqDBad413F2OdQe9
xHgl7d7GrdH4EgGSxRYfOwyBub5qDKRlQG2qdR+7RYx05hi27pL+R7yu2bZGcFDVlBFSPHt+oSWc
ryXBF2Ctyi1YdBYCnwXeI68GfdlVaDZXIvrokV5ytKkxicZv/+pPBeSucbqZuvMwsoxdzTEYXl7H
L1PcpVDt+KCV1q4Wb//2OnUatdXlCHzJ0b/Pv8XSY9RJdjTqKeNnTq7Y0O3Xwz/Ra8oVoTuNrmlg
SSq2RqxEBaBaQuMuxw7ryydzDtqKo3roXTYslewGVJ0nj3PB1WNEWMrA3x7DXm9xPcF5cuDNXeGQ
IN7Dgnui1QCenbnrc+vYKFeTg0AdNg77HJtYSGbdPl7ADpZpIG7ctckmTUrsm0sxK1kC/qewHJOb
uFG2ik5gET8Q9StUfddEMqNUuookgsb8IgD8uyb3duhstmtmx38BtaQbqJp/vqv1c4k2hg/s6G9v
zTDVfmPG7Mi+e0kWFymeDeTcPjYaLty49QShB+W63UzG0E5c33t1WHxeb/y6MW3TE1kN+59grgH+
C1EnM1q/SV3l9UKUeledCorm3ndJGEqaNIdnKXcrM4d/uuACPOl8hzo52dPYt3JEE/3MuP63PFCK
PBgzqhgsfStKaSrrAR8D5mTuO464ga+2d0ka1Q+u9e1uNs4uFUsRpqZkImpkFf35blE1txie39F/
DebDjawhICUb/F6iCA1BEMGt/ymt3kaxWoXmrcsNLfaKQptZhr4sq5TJ16GPdsr32IIuY5qatDeT
9F//kq1VRtuqkWaWYoWuSHCI02uOFFXaRZpppvkswsANVSfcB2+IatSk7GQb+dXWTDtqniI1t0NQ
InEU/RtjqtS/9x6LRHIo2e3gb0J6kyVTjfMoDXJv0EiOMizi7mn1c+kusLTDctMMeW7QZnvmZ68+
R4wRxxHusnPwHDstaClH2ZwISIE6OkH7MmXgxqG/wn7WN4qWAVI00ZLVAP2nUo2Rxbjpz4NIldZX
RUQG4HLiE3ifaZU1CsVfuRKvAn5RufBRJJsWWSs+R1batomtbpytu+1glZDv2qQaQiAtrAbM2eot
pVrEJXoeGJ9kyGDJgfbciIjhHwH+yVX5M9xu102ci6uOqGSFGn97ILP1QlP5E6fRe26LiF4jD6hP
DQa2uavFGESi7KblVupdYchk+cVeoVNIoexVvFgAWe5KXYpmXTQge+NAaVrGwqWrI5qLv3BOSVd6
u13CQjG1e+gJm0CHKsc44wiiGWTeuixnaLKWGoF0o/PQdfb6qwgOAWqkr7/RwjKmDsCVJBQJGs1a
AnRzOgoBUl9zg6awHDqX6uCyynFrywGj9ZCde9UqrYPy9w9oxqjHH9oFYfg+yWxxNzN9a0rt9Qy5
E9yEron2LBl0johs62Lbaemx23DrAOnBR0bmmNzwkB5//37/mNGTfbCTYCp9AhbfNair6LcHbtv7
1u4+QoDzdPz/uGQ+VDD+wVNkYS4It+dE3tdI+d5kGoLOU01y5Q229fmPQI8Qx/gvTjVDaIm4PvTD
hSQFsrHEe2Lbrl1HJzM9dHCBUfgca9lSsUt21PmojBDbkY5Vqf2uC4kU3oXcpsan4O6M3AMBQALL
p/H6CiUp8UbKFLC8tPQWls1Cz5zWFeu3H9zs5b4NbFj03IdGuuLzNYRQqT9Xgb9VIcpFsS7p8RDD
4WEVgqDaUHAujKK4vL3Rulh9dLEA99wkimdlcZLNo/WaM5QPhNiAfqVC0/1LZpKvAqoSL16GzWuT
B2ohp92tT7e3/l1E/pvu4zZuI4XezQoMzDgFUW3AoQxg2J43mAtbvufCl9u4NgkoMpsnDBdjxc66
VF6Ff7YADCb3iVgQqTh0Y3iA4O+nymCVfxHn4qoIa9sSnXGgpaavd4JgoXX+qVtu73OaCPzKu+Nm
wXq7JWHUgrUONz/I5yS+/BhuwMiG0dSydSeQ8JMLH24W1pOJXsoZoJZjtPpvV1JNlUQ6vKh4sj1p
VYcT4eLxYJINamRVEPox9iMFfxyvytbpaQ0ALxV1DEDg0u2SAFDpOGPsDvpLvJwEVdZMnB1X9TCH
ypAIbXEbTTBLSnI+KfMvaO574MHBHQGgQyVs0G/k+ytC/Hcjqa7MbT89IfwUP3Pcp1mHJNNbdWlF
i3LGgHNOnkqEhXnHynlE0B7vmkxxgpAGa4PyYkccrPI0Hw7CXcAIzfyc+necZADAPmlPSXds3NMq
Qgx2p4m0kPkNTeDGlbXAjhuRz3UOEVo19ojtfshlAPTgNDL4UJoq+jQS4Ro/VQeq9UU6ZST1Yu5L
nVQTN0pYifK+O/FRJhItgMBFbQBeD0i5RAV6OZOMC+j1ap459ror/H36czaHEDgp/LRlTzOA3XEJ
9DCodS874t+9SEi8sLFgToKyizki0HsM0d+1jMKrnIjuas3D2GcnRWZBhy5YB9Xvd8lPME9/F75u
ux5+GONncO2Swk9hhxX5SR+e+eJxgJvRGbXNROOQLqm+klu7rs8nG6a34b9jF+8XT8McnH5nixeR
a4LyDX48lh4iZ1YAEtdtPZ5T+yqjQ3OR+7Hon+xgw96hXdyCr8NiKPF5BRQtCJ3ZWe0U/g/aynwa
I1BvvzpKt/1G0zdDGDhBWMMGd4t0n1jMPWdEBZYX5WJ9mGRLQaK/YIzCSB32tsKCiiiU6AEKNkoB
1mPuqe5sYJCBhGOrHvlVewKUFZINfBkfFsd8ovWXVWdLuwOLKyJnLtt2uRQC+cswAd3xFtkGADgJ
NWh4+ZS/w4xgSzLbUFnTHtq596pZF5AHvK1UVdD9y+b3kob4Mfjay8E0UzHLMCs5jzkDNhifek5o
y8q8S/oSwdvv8UbdOv2M8OftwNgker8a2AUvfgFTRVdoQpGrSTvbIN3kXFNSRj7t263N8AGlJIvW
iYtqCI+ZudZMePrcfsxkuk7Bgd1hRFpntV6I7iX2SQIh8LdgojuPH7G4WnNutcE7Ah/WPwSDCuG1
mSKCVi5b7F/XQJg6Nxcbo1sIz/+AcV+VxDmf932S6amkNBWTeB8GX8NUS2BaEhUoHgQz34yzP41s
0SLtkfkFsTseKzk3ULdLZ+wuwFPRDYrnYoLnQTK/VLynB7JOifadeS7w/46RU6Zp3FbmEw1W1Vml
Ud9SypP0x0XGurN+Ak7k0wVq03D0kqXe3Ys5c7JYdxiQOHifKGvwCXOW+VxO2FAPRY4NRDbsLL55
mOi0yXjYRPRiqjx3GrsiiFxWGPq4lMhb8h57VGz1e4ExjcU1lT26LZVP4RiP5392DpL5+P5wjF/g
G/8sWdphmruQ7uKG7Qm5QirKr3tE4VBvrFpSqJOFSvML4/W21UpOf8RZA+xgScmauH2mRWF9fUXO
xr6lKJq+Wl66lAe+RXGA1ji9obfhAxerDaHH9NhCj6oBcTf+DzDvC8AAJKc33YXFX4eLwb4WgOVy
BKlsyCICd/6+4HwWqbgsc3G967uj7njxd5uWsHnl1hOjIj+B7zByVAb0DPQnu/0kyYM/mLKYkavn
4QI+0zYq/xENovVx42TUE9HWwXgk393/m2hCuFwAXWvM1uWztXP2OZcANEQfOLt/ZmPEmkKbwcTB
EkaUi/ME2SOUuw8ZbGLi1oH1qAk+kf1V2P0Ab3HrC8HyguzftxdFA0qcMMqHDcLeljHItlTzk59F
Chklymd+wFc7yk6unM6xC8q4hzF+0QrAIT+0s/G7rihsH9UuOy3Zp7js1PQUYXU9G5+RmAoiyX3f
N2pQ2nsP4VOKMLQlIjkgRhe/Io01lup4pqA0VWtYzuqdzi9oB8fEorZ5vUPzcl4j5k0ZIlxwsPtn
s0FWoGie4OC5i9J5job6Tb4sh9cAUQjhSmzr6Yt+dNJJ/F+4RWDfe8MdQUDLmy2qSvbHKJSla+0y
n/A/+9dANtZ0CmEipO1f5aqG2cMd7nEqzJh89vIOIlT/qQ+hZ+4vyhjud3ndpPTQEzbl4fthA7XY
eCBohxqj2lIMDKpkYRJGLN0L5JKH5ThTU5Vipct1I0YAFGn0CmMz+5yuLPtwLpQvWaxN7aX5A1WI
VLV7XVYuNcZpCLXcc2MRxFhjuHEXVXCru+fNPSA/J5hzhlo69cmR+9eYNpKA+2KJPh7/FEC6RO8i
AiLCriezmda155lyb5P/DWqRCNfoYAbWWV+DoVKeFvMc1OAN6KjyNHVPXCj98InKBRbZ24knjS+C
+M/EInkQI6czonIzW8l0RwXxG4FhUML7Ck0rXe+b1ELBhE5FnCT+T6r9F7muh3D83Jh0gAQuQokQ
Q97rLAmh96cjplgtfRXzmGvRYpe/gyDV6BFQo6PAb3mqI9644OiqWwVjtceZYkkZfs+zZFKKurCH
Qb6cpuy3+lB5JCk9NTP4IyuaN4bLgG2VT0y897yWX3caTh8IKUNM/f2ekcIGqP7nkE832yxpcgeY
UxpKV/hAMca8HLNw4zaasJwOrlraA6aIp8yUUX4WQjZdNfWfFYyCxQfylhsze6W7ZjqgtPCw5EMz
zD24m5wPoRRTc1YLTejkEPbdBwEUl9L3QbxOUZP38PG5u0t9JzyTm3tu+9/CRVn/3ftoHb/lN0aj
+ksTZtmYqIf5VauLa0zePBfgvXQ/P6/kduGDK6/wZ/Kcpk3uu5OBoc7C/bfA/QwJERmqeIyp7BLH
b5K3jh3qnztSFHUVsonmSoyOC3vZMcQmeOlS7D1Izubd4n20QCRW2TrdC9YZmT3k2PNPsYuZgM1+
r4JLBbcDtw4OsYm2qUokL9nhri5vRrlrp9p0pPiGg3LalBlvJrqA3O1PUj3MRcCObWAloKo931lE
6PrrrwyQAx7vlgrWiukxTjUk056MZvXRR8oCqbICtoxt+bK+Jy4Hl8k9KJLxKqLiH+XmQ2LcverF
QZ+3xxzJdnpVR8737Vd3qMBk3YkaOcK5TGYXqxAEiO/Nwqrm594E3wkOcygCUc+84o4kWRTiEUKQ
SH/qYUyW3IGTl+SfQGQWrsWj4dwpTc0jAtl8qyoOX51dSeKV70QLoi/SD8cLMK6CzevccMHUCDRr
7rqpSakvCAMkhYUyyp6taGB+kleFplZ2irPusvvuwwrHEguzDA24a/p8IM8YZ5kxBJkFW9HNX25O
p5gMYX9qFxqjsa0qalBuhJnwng5C0/VNNcN/xr8B71u8OPBpxDGwX8tkfDUWUVodFh4TgpQ/GiES
UWPvMRg33Qr4r5cLq8CpZEah5QxGtz7jDX8BuIhUI3cl6n0X9LUT3B7lfm+hgyT+DDzonl0KlpPq
en0wJ97YiOENJfOmWkVv57O7WCcXUwGqE+mLgVTHlS5dykoZRDyFV0CImmu7P7iuOjMpD7qTRgXN
i6Xnfn+N1lRA16ujst7QFSopVhhI/lKTk/6XZaZkGvXyIGzncyHiDZzZqGTdtPavJ1X9KS/tX4Mo
jDCv/qkBpaNex88hLq/88SuirtHuUsPIBIsYAC0lV08wASR2ULV1CG7zWPxpQy6sdFjbLBlHu1yX
GQW76lZLKfcy2WT6tEYeb4NCctVdsw5udA/G/ly5OKO0ZUpzhTpNF/6i1EL4BGAbySxTasxcXsMc
Tb8FQIPva8+Nl+JthCk7qsf8TXSxOddXtBYYWbNVKgc5S1yngoew+65sG1reGYTFYh4PlhUSxMIM
LbPiX/fEEiLSXySx26il7H8XnZN6zIDcP5WVeVLemtqXjXRvlRmibXCwFGYJgv2OBwtee27FId29
zdtuk16FJ7JWQIn0Xr2QRyw/8EMJf1J7NItHb0cdvZOTzfJlfq+OAD1aDvhdvIpclkq9bhb/do0X
FGHVGqSHDW+WG5YP41JiNHV6fSp2XskJYaorOuTm8GvPjRtT2l1m7lI2FXTzJPFRZ7IqCYbRY1iA
6WI9b5JjRa2hfEuakX+vv66nueoCN5bfo+2kgaAHYxvbz/CnfD+ez/vg76tpSpmlbE6gPro1YPFN
jpzCzZY/8j2aLf5KLWgdzd8fyf2KXmUdqAA/q8QXeDqtHKq99j2AFtue2yVHcoTGNIl6EIE2mkeP
kMecfC4fJ/kWeBUt5mk1Pe+2WFnUHY1XhRa2U+LI7NA4RjNMk3rBomWJPwqaIhnhrd746pRYzRx/
SW3l0nEV11PX5Tfo7EVdkgN/sZj36WD2ByPsfCR9ILHmIQaXSfenuIeqiwdlSLF4R/y37LESSs/0
rdFriXT+jdRUzpFwAoF5Imh4ASI/3lfWKest90Kmci+f4u5zrMqH6s7Cz+OrSvY4t3iWK/hNavTW
N9ARzm01uuMhTve45InkbyvySl1+PHvAie2jSob86hD9RF5Ka+fi1i66XoGFrB0sP6vdC3RS8Ubu
JpaXWv9GjEp7qR8b/GMFjoWtohqeQ56+pMLIGCI3g4uQr61211YN1w5hpMz4VsO9/0DoOcaZm/To
6HqRe0q7L7ur/aCkIt4Y33HrdMY7uu2Jh/5/qoneg+2trQCGBJ3KrujDStJR/cUuDeystob1ZYOb
eVR7kQZCSjldBJQo7Sjb7V3/t9bz6VpDB7P9lusb5ORI8iso/ci9il0TkVv7CUtkTs5OZ/yNH0wT
g82s3KivJJaiY2fZtVKwX6jeMF1GyubkFVeu9fpDDhb3sZptlQTpmFt8aPzf3n3xzCQhhOa32bja
+nKV/tAxcdUVKRP6JEWKscGRObH5HBxjSQvMQUTjXISoNwKyhZiuW8lgC5pJgUb89pqd+tGzwwxE
3Q2UQv1vYpqwDLwWPHnVY6mlVAMsp258/cPR22xYVuMy2usiw8DcqAkceLzuWKvw0udsumBF0bQH
+6Pm6xzFPw3Wj+OkmvVX1eqplimNf8zCyecJO+yslyR0pWln7NJRQua1LE8csRNO7dN0DyOfVo/W
+e7nIT6YI9pwRkF/hSkQgW3Aj2Ynq/KdtOn7hEUr16OPnV2HbdEXxngrbS3/1ImVWn10sPBT91sF
aocEu4uCMlpVpqZYIw0ItV2BQXXEdUwUUpjX24H6eLvc43D6S4Iohet9AexoI9oZyM0lYHMuz5vr
RIJtUnwzBu6xwSmRfQAZdZJRQz6WksA2/DGtFBaGyTVrS6e/t6c2Hdjj239GQslN8JfmqpoyhsTK
awkteIknfE+3DCQAMuWApiWehvLyKyFsGMqDpDiy6zNL9Pgrvm0dn/uSJ0tyST9t8TdHIFeNNwuc
Wm0uxQ4Wd8D3XB3riuwZPBJHp02rHbeSlWGswmVw0WXRjLbS3BGZzwuZhMmCGq/I60eeqEV9LU2k
rLsbFB5o5ywPB++lWMs+ulXMLmuJq1kBSbk0hJXIsGU0icC9T+7m8HsFKr2Sh+wUq17jB2xLrSeG
apPXFqnWZXS8HqHSEQ9Jzixtesv6QPfrpx3VR0hjNwapkEozhmwtmfMzcRB6QN65Sjl0g5g+PiMU
MboAXgTM81BFR+44m7caW5DDEc5YyGhz2nHpMgG2CN7/n0ey8JQpKrbggYvM0lTVOrJ+QPozL0Na
N/WWjS3B/MSQuBJHRNk7FLULgi4OV4oUYd+hKeXe/OnPnNXwHdP1rI7LDwYXCtl5TTmqE6opdQmg
ZW9n4xA0nVTxOXjehNc4AZFtNNN8dzzz+V3VBDpB1dZKpd8w/4He3R7+5VrUfTnhFR/FeJBrTEXk
eFGxrsfmowM0L3w+VY3G+wHCkCD2OQHxAjDq7naKHsQMENQWn+5ZAnRwIhRGCJHAAJjByYoBlFSD
xBaYfQ9+hOjAs5TA0yx14jslVZ9y9JrS4G33H9xFBNtHFqhdEOOaTB3oJQ7fUxLUqbONqb6nyV2r
4SdCX5i/LHZsrfxuaQAIJjRokscGk7MtiGomP7aHbnSv85xG9IRrtj2yNyVw51OoCbIjYcqCLsBo
YgJMxKcva3hWTMVRZv4Sibr2LUt21wdYbPIR647lyyv8aOzptM27empRWYaMwzkPXM6mOpXMo8LI
hWpfYxojbCtrxLmKvdLWxKcwDqdu6b1UoKJhnicWHG6qZyw/ao/JsCnPdmb8yBSf5CzUvMld48j/
EpTRYjsSX4O6Cw50i4hnqR1ADkWDnz9yluKXd1LJQSkKANLZm0AQ0sHbM9vKQABSYO+dEJ254Qmg
Yh1vYP8Nok5Mqu70XNOYqtmf3uSRx07El2OfZpEDy7QXomRmerZGcYYWRbkIbanmjxB32O634/QK
Tz+lW3CAhXv2W3OBPP+mwMFvyjK17xnw8OdfjQd6VXE0m5bqRMjaMBrNuSHSVDSn/W2wAcDo9HTP
LmkP8JWU+RTpPJvrWBu27folYM3OIthIpOkqgqnisxXfcbxJocR2dI7sx4D88onefwASCcibcdVb
EsbuI4vP8z3p4t0/zx5C6yzJpglCjU0laVdmR5mZkFA7iZqNzzFOVp0vMaH5dXKND6XkJ/OYoP2V
APdV9HICzjHWii2moaCn+hJw6OY=
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_blk_mem_gen_0_0/blk_mem_gen_v8_1/blk_mem_axi_write_fsm.vhd | 27 | 61464 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
b5iEwcuh/jbBlgyw+948d3lvWBbFsOTNVYtA4pJb/+7lAHor6DKhd4akfRWg+MPGWaTgwtrV3Hjr
bBdLdBNTBw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VtyA/tLK0cCJJRwkcmojHVnJYFSH/hY10K0O1xHrVFcESK6dXqpZL9jghTqU0K8Rgfgyj2mbpSmS
d3OjaMJOT/0rjwEIwUBTQhpYCQbUdyb5e+tsu6Jle32rY2EO1nN6daySTSkOW0tup2zZBsIOCr3t
+ejm/NK+miEBBu1xCLg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Sf+0xczGTqZZx6dcqp2GTylMp6ojNl/Es91rC3p2Qk7Z8FK5U8FSMHtByvmeihj5pitp5aOxAIcO
cjVP1mZpqkA9QTc6UkTBmHGnHSpwqkUrzOtsT2ws44zFj3ryr3hssigeWwtnVK13YgLrM+5chsUj
26gA0jBZIt1YnLsbFPdAg3CFuuIkHWQ39NEQDeG2BTbW5KtUVyDTnpctdLn+1GQ9lYJeC7lVtfwI
4B4xEL5dhZYik7uaLaobO+7jlipeHv29o8EQsg6BnOj1c1kxrXtTLsKozU5mRUSyPYYAw5cgAAvI
P9ELz58Fq2bFhjjPjC0ULrxEE7cl3R3lE+lEcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Qzj1t+dWRPGHMv8nVaAMZRu2BQPWmF3UL/i0LvBgsHGjHy3fNoKTLAs04wnbPCVtn8n3ytCSqZ9j
YDEGkJeQd/ctkBALil+9bfKGzVPGZiyWs36ilhf0nuaehXbM+Zt3Nfkh/wd1LKqVrJhOB/A/iGYL
jRkozXf4ccRU53dhQZE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eo3jj49OyneaHUaTvAS2/lR4/3L9GHwLzRAoxweYog0SBxlqFd2rrO0OlKoc3GfXgogda87o4tmz
l/UHxih0uJyK1snlhQ6A1EHKpMBpfD++gCN+S5IJFV1QgpWejKXt+0a0zp/A429l2cS7KMD2pUZc
B0C4VRE2SAMGJhfx1GIRczPJREH6ZIkDU1qmMs04rSp0PaGn6eV7+euaxeQcoqowg8QlRFnxfvHh
5JrqhxNCP2z579eEXYXH3AWOzWM/EnKEFUTbEaxMGP4W7RzgRCZvuM41apmXDWTVjEj3gQq6xKn9
0OWO8TXN0ID1dcJmFJe2x6yA91duGkuqWQQaEA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 43760)
`protect data_block
jfWNGfCyrs+vti6Bu+94ljTD07EXewZoc93xvKrueEL/5Z76UIn9W/y3zjWHKChs2BchQnyP5Dl5
UN3ZJ4XyJ1WDAGZXUN1lxidERMCeGEISnqIL+smKbpd+QV50DR82YghDiVceFoXnUZ+4LnESsqse
aKqwFsbLF7Z9qU1Zo8RbmNGmBq5CkDyb8iRnHbhtJT7hGauzb5txc+7gbluwsjbF/FF5E5pS2YpY
XISBTbMJwgG5cHk0T/jHEYQPNzpViht6RCtszfGGIEm5Jm44OQK8RFj47WECw2ro9JRzDWWA8XYT
XsmQ+Zh7Zh+iK0xZTSPX6fOYnYYmVzvvjhlWMSzj6HU6A1/gGW7o8L+GqQmrdzIu2Pa1KqX95xes
3k9NtQy4TEbFXbEkUJfkMNGNCOmrfdh5KY9AGNQ3qSdcEHHyq+FxxjMATT3NHRoPk07SbNSXREbo
Q4SYEIB2cSxkAvhBxRYxOahWb+tMSoxtmG+dLeoFJFemjA8CoyIVZH/u6KiV29Urnd59oAjbttvJ
vTiPrnf6aa7OsNrYFdrCqYPBD320AnVm6eEuRtg/00VWzjucxAbWwcJxK/JqFYAaGuGXnwkv9GNQ
wfWAJrFEqLQUnyCUICwFBXS19wLR/j7gFiDvT9d1IfkTaXwHZOB96ib4A6gEfhYsZBK9rneRsns5
r9PLoagy0Wz6iz6w809jYCq34TuBM3/1HcXwN1rGU8q/F3ySl6ycShHLfM47DLt6U9/Wkb27NlkV
8+9fwmlgan/a24XhRJSOrCc5UTIt67u081zWXRrsdPZngLVDA+NYWS5Ak37e5DowD5MyFuLCoEvb
tfzD+BhK0m0KXtJt7qYAG5FZrptryA7CJ0IHDxPoMBtmfEXefvrYQFBC5OgrbRccjp/+4z+0vUt3
YUew9PcSzTUBdDWNBHe36LSb0OZZaSbIiHzH1WKBjPorhzZbOzsMeVXkzEnq2iU+JrIk5k4cmewo
p3Gv9lq7KaacuUeehJq9v7gma1CLdllkA7oxV5qSWpkb3zlTP0edaPZebGmtsrsymULZKG2WJ05A
knVDZIONtfHG/ZX/qo3tSRBYtw1ps8CEyxTL5v/OgcV5J6+8vH+IJ4QkdiH5o8bM4CvQF2XWIg2B
QzpOH2jqPDCsQmpMkPuJ+0W6sBnixbmFooMa1TaAh+tUgE1KYesan5VaYBdAfS8njDWWDEmKHH5m
nECGTG0pRQucHGVyeOdoNLumjTTlHyYyqbZAYDrdqyvFGzDD5z7ieJ8ql7G/UCWt8XZXzSoRVpXb
1hqh2P5suheYCddGAzd9PLEsZkSEflJQQeBLtkFY6PC+VsKjXFdtJ6hMgsi2MHPtEyIJOKNCXooI
jcO9DKk62iZFqq32G4jSot7hrAA+oL+7tJdV+iF2BCjAkDfCmgnMXLJhBIfjLa7NYTaAPlGfe7AL
imZN0p2mc1syslAv9UmZ+ENwH+fs3jMql2E9UaEFlizItHrUiycme8c6Fe818Bh4dbzYzLIlc51I
I5bNlwPY/OHTbC2C0vhaL6mMQpFuzQN8CTK/G+sgjHm6ireBExcM7ujmSbz7ryOWb8XGnh3F+AFe
MvCF9yIOJxoyHH/OLFlrYFbYI4OMGGleU0TRc0JD1ECzwDF0pZMo46dIqMCO/DvwwTy2OmCjboM1
07CMXDE6TIPmD50nZR6sfEHPPr7sFIID9tYCuWVLSRSQFGvrDNYJf3M0KolBoXEmrWWO+oznWDlq
RZTOVynWA8qdGKOqMkjtIkTA5Yn+/gN2z+StWUl/UFyRM9Qk7XyLKhkcokgtVT+4/H9dGgknvjdd
TiR4J0ScOINuBFRExC55bYCqfLr9NKQ1WJ8WZ1TzRcr7zuoatrOj0ZmOmMnd5iquO3uiLOwB+K2e
c/84AO3xsRwf6bjBSaxtkw5KmetXM7m0YiEIAq4VQuYVyM0XyS5OddkrEFzNIOkUvTm9qX/1JOSU
JuTGO4REnIwVkPBUlEkFb3bAtNnuvQ2+igYEVE1LYi/+dun+9c1p3VolxupqOOqevQGvr+JaK4jR
awSxNy6ZiCuQ11busX5eVbDuvgf51VDgUX4xqU2HJQL1uzirIpcYHa+bXHNmSl9RDvrljIyNmOIH
rXEUvDyBfaGk49QQUbtRQ/vkLSedxMUBklD0LDOEc2RNcR0fZyyOnswaANhT0G4faFRBCvFm9yIs
LuPme92+0b4iV9/jaEWfiPtRvljonavt5hYfnZWSDA5doO6aF16uXh1flx1NloDXfLvfYiw9Y+wY
lTY+GtNwL2H/wmdpK0yosNL42Z18rp6uNJZBCPo0rR2CWLyORsnrbG/EA3YLp1e81pXV4gxgqFCM
yI3OdyzwMHsRgBVVwXvTkxucbcoT/I4CpfB5SpA3tQvbSyjL32mUGPCpu4mRBhGtmDtJCWXpbo2l
aOOqu5YSFc4Sgqu+ZX+AM9RdOSHhBWGKYtwNNrgKB1T0V1pj7RzAKKP53CGUaYE5IMUp8JYCzNL9
ErlnoHMfVz/BwpuhFGE0iPNtAS2qNdaaaUbuJggB4lcgeQHRan5xB4+oLK2P/ROjiTbUH7hBwquI
hjwl1sLl+A++YHUKHvbM8skhgqRUDqwG5WAy23lm/cTfXlSGyH84ypUuuyJABdPCTGc8tPgBAKdc
yg/4kG3kLPIxLIAYL3W6o5gTweAOG4HWa8n61rDkYvGxe7ICugw5R4t86s5QJBNxO4SJhsIVM9U6
oBi/GUan8NZ/PwDGPc6/7//PeJBD/ZLDPL29zMPqGxesJZCIIy8k3uDgST9CY41MumsJG2dn/YND
+7f6p1ltHWi4Kp7D4zM6RstTbha2ofQQxfox8PNpirGPPmfH9jSt8KjEG3q1IdK+mvjGgE7tXcQy
CFKulQCldtO/eAjF9uN84A0xfUfQMvhbRMXVIhSPIkepav8t5KjUKcO/GUwkmWhdjwN2VYooHSB7
yH6BLd5xXbJ47lM3IPZY0FvMe9oOpnmTxJNLBNCisbGkqLjuyd7mkQNhyAz5fbQVxvs8FKu9Ta7P
dEcjWHL+Dh5GTXQKa26kq6hrC+RrnKOdofzolCCn/KfK1QJYEG+ObkntDFLEq0CMPDYPgcj/A5X9
fr/AeU/ZtXg8fQrbcvDVh+WODfAxHdllm/saGa/oPpgz1awac82qVf4GP5RPIPhrn5PBMY/IWBVS
zfiXoACTrR5opMITZ5LT4w71bo7GIFxx9+PBpD2EZFUl4HZokHgCQ5th63ivX718cJltWXhagVxk
NXTrR1my9asve555lT15wrZR2xsfMS6oYrTClOv6zK1vJUNfvGLP/Xva0lZha5fSOHAc13B36Ifq
H3s7KKwTrfsEr3t69ppue+nI6HvdOmIsfkE4YCNcloCT/BiHpxIy3zZhjH304w7qudbxJoSA/LbD
2GpdghcqbIdByGPSsvYvUVAH27KyVHeRFuF9LE2T+GuvtJlrO6e5iaM+LLlXKQKarfgiZjGRqENR
oGygOL61EEtCWGFD6dCMF1nXWP8G/W+zlLqxxqaItPFEowrEiZv3okNnPx9YRnvSkgJychzf8BE9
CYYGGTBWmYbfpXyFliWGpQPF43FIRh5+6ow8ZR7QK/E9A3l3uEgsSxw9SfrdfSO3RLb0sOl21z0G
UsbaUSFZ5z6ucjlTZ3SwlwFi3LYmTdSID5AIyiKIy8o+sQA6CG8+8Uj24tYKFT1ym5ebef8+iYBX
+6A4BXce/O6QDhBgUelR4zAAMzSv/MjVrKHVSpb41d+U9QIorzG2DvDHRfUhiwqjTmtIZmM5bdMV
Xz5sUM61qoB3LT6wooGbpqItJg8T/Fxrvj3u+jRdU0IphfHDYT6f0KpeJdmxzbdaDZLLiQj1oI+o
LcPhCW4Z2TfgwBhQbJeivCtATJ0A4FKdLFY2lHKDDJqYpWTSI1qYOH5eCvPlzyn/gMxnBjHvWpEM
2uwZVlPCXg9e4wdwl2JKPgS3XGtoyrM/NRKMU42AwEo1VFkE9MzvWCvq2QNA5wF//IOkZpGZ+T85
yv+NlFwB3Hycsq2RGTH8Ihjdv1BTlRkuvyWsdxQBTGTtfqo1rVeJUcCYHKPC72/KwQGH+ZO8JY89
jghrFSq8ZNNshLLqNGRldKN6RfgmV4Y/crk7xQdqtxGmAZXrl5IhB9XQ9vg6f33JTT+jriTj7nJ1
LqdI4Ex7R8KzF3u/Od/Za3hBl4QG8VKFovESB68AFXzyDeAsGub444hrPkFA0NHLxyhn9mmRnlJ0
6uYQvEDBK6hpV7IYoMqZI32EtkgjVq8VBKn+EhaVFVZmNDBOygT51C9WM0+6kevS38jKH6yhlZWm
5Lwm0Bf1tO7+5tOWbWc8xx5ngKA+UuG2hrc3r3KVebgb0sbbSwQmd6gxvnfO9uEmuiQMI3hPlg01
T2kOl8cjBmEuAph/ok0UEpAzYA74n9Htp0FhcCQRsJdMbVqMqY1Ur9H5cQk8BTZoeahUmg+TqQIc
KZpxjfiz8hPm/CIWuZa+eGavGlIZ/PK7jpUfN1+e1TUx5ha7MzNQU6QwT++IySetuaFNNd9PwXy2
M2WHDvu/OAOtJzYzEWuMzlNHLk3p1kC8KdehZQhM/cNp15wZ0RgbdmfmjjI40TT6W7YK1FdGRVfj
lEWLz6zeaf8HV0foOwj4QcdZXalcJgkg9r3OSbbzJyRNCK8Jqk8VCJG18/cxzKL0OrXUzyC/vC0x
74VmSHi26vzHB/y2cEWLntkDN+z6PeLNie4Z6w7JRScFgwbNXUt2H9w2fjrpCF4YAj+5n4aWMCWz
DsAMVxEYTPWhZNgMive3dpLNYZGJh5uj6t5qya8o/8v58/93guEbPl43B1svG2iYP+/qIZxcZbg4
tZ2Sg1TkQWGk1L1KnvL4+sMase5ZGHXGYpRqYmjOboj9BfT0ob85tS3aYiaLEyMxazSFoAASmqp1
A99ykd5FrJ8O0mnePIgEQnane3GJb93BCuA9+R39IQc0UoT83+PjlnH6zy7ER6ivwPY2JuRog3x7
pLSYwe2AZZlV994FMn0A0/+V8RE0oE9xph2ZpOYtAO0MES1qDw0wik2pPcgxOia0iVJcV/qFDqyk
2A4DO9hHwxvEZ3ApA5VeQ0+EG3Zrsix5rfoLyot2bWlW+Q4GLkdSv/8A+lwoiz3Ln9hKJO7+HHiK
V4JavqGL4kazVIDfsnxmRVu9xE04jPyzdil/nq3nd+0duJi09sxH3zNKMhX75yLpRk63TvvS0afF
Wi35gqz4Ix+jkPBrhkDvghAHrmcHm367JT4y1qxZTrjC147lJpOKCRi1pFa7qWnpTh6BPT7SU22L
WreceDrxjnhcRrAizFdtUNBcf4q9mmlRIyksayXRPeEcreYz/kBBfVdQiuzwRblRN9+3hOmofsjL
yoek7pvjpKMqDbIE3rWWvntXYYrk8Xneg6cxICQxVB4W9fT6e7DmxWo4BFGzMgOIMW3eWHaWU3U9
F+7zH/ypyDOKFNTfjo3OHaNeeykeljpglKkCUgJO4VJO3SD2TYmtQ7vXOXEJ+DEKSuLb5sE7AAig
EbSS9VBIVrZq+paELsI8a1JqDqQZRd+Lpcq805VFhz4oBf9ItwnFYjDGd+MyVR2KzjHSTPtCEUTw
RMqifv/Fy5NTbKM7ERI+4dvt1rcL3gfSUMLBuKJ2hr7SwOzoOzeWMMNsJPJ7aWiho385lS5Vm8+Y
8aYKEbZ7CbGpQICf62dYTuIX8x3b+ulwC15WDRtjjIJinI5/RTwY+PlnerInkKJIbXoXy6aDu2yL
f9Yr4ggr5zhEWuGv79N1ox8nwNuPgLxjhI8przoVMiyvM9kxz9xe4xzaw+JiPgYchB8Ncs60qyZk
89Hn6xYvhHTIaHGn5mX5vMHpGfsPTMXKevIk8Uam99aXU4m0Xl35y1SyGIvJ6eH1wa6U2GpaTL2e
DoenWCPZBbCc9pXZk50K8giw6bLCt/dXYDEUTUONj15EE/SP8iJtQHDlhiTR/hJtGkXxE6pLGTwl
Xr+Quxj+yJKJ5o45rfdzFoiloI/a4TKyBQQgtg5CCOagtPfm3CSBVXuL/oyLKJwDGrsSav+tF/KO
rZ0UkBuuNAvKAa+O8Pb7TFdYp2szXOBCAEuwtReg9kqDTGL9b+BNCOuGF9ST5t9vwd7cvw0dGNt1
1Rq1AnhX2S/+KF01GcMW6IGrDVgW7PqcRZao2VIZ7louF1q3CC0FXHeoa8B/bt0GwGKBqrdeAjJn
k1R0nqzYgc+LXbZEc8R0NpfGpHvKpqpZ94vFQKzasuwwbH17GeC/KrWzhxjnMTU/9H0PNWrPf+rm
gZherS6lHBeO6LL+A28KYd8EBszyEWAOI4lUzKXVy+sk4WRmYzCWn+nvK+f5TeyeudEniz4fKGOj
2JVjEvO9PPYiW0tDaqRky0RGraS8RGplby1gRBffePtrPFSupI6wXGolysl8TUOGjXDGX+qoE612
8tuCkhV5/wXj2prkcddNHXa0YQBPTn/6SQvDhVIT039lo8CPTJmgSniV1glsVnfbE29kpbElyhDM
0Isyk9M4qm3gE6WIA1bPqR10nmPgd2LfHI7RkJRuaMNioYoB83a5iIChRAahpHC3dRINEJpEXNvl
d6T370R5NBRiiOGbV+fDpmyaeDQMxZxotEDYubAvML5fZ4lEz9q9oebsTrLtKKJCc2H++zUcnzUp
XVpr2Hhle4ugYbkvidhLTXaQWcWsIucjW7Er67M5bvBxGoYByoFwcQ9FBLGBggKODY5qBIJPOz75
vi4bcv4bqpFUE63p6oyVTgIVTCifnLYJWZYbNpkWt6STsdQwIClF3tswWi781VfeI+7VOC5dzHOx
T4yB2ZzjvKSL7XvcqKnMAJXkEKw5xjt104xxkHnCIsonnj2IFI5tVQW5OaSVc6RKSPocTyPAeicA
hVBtEyGmVHCByVsxpd3tg5a4k4bg4gsHguxHGMgBjCEq/fTrSem9t6G6F29/DdbjMZ5msaEG+Hj2
dQz9DgV8z7teis87q0EqHRD1LGfn2lYfVilYHFTHYx1Pt95kUpc9fSwYm3GECVHiQuP3LPtP6kgA
OiNPQhMbNms+MhK6+egsW9QgVDvkCu1OwyW+dPGMHqDIfqUGTpXDjTwTJ1wMUF2pNaCQ7alF1VC/
7xhWdlZ9VDUxXrWy8xdUUE9uzD/BpOufrEgc5trNsvf60eLjDbGWWyjuCYYKumdPRvxadmRGipVY
uP5aZqjd7nWBMm/p3ckrIDbIVuMn5An+yAT6+hqOh4vDh07afnSxT2VM0L40AbvqS+8x37/98AH0
hWATrwyhfR7c6HCfRr726Pdq2359rCyreCXUM5ijF5ZUzqAJAOeP1VqKj8xg6TcO/xlctwgXFnow
SnE5MuGXGzXc/Q7afOplYt7eKqRMjBOnmCFnWEiup6Cjk52fy5vxEc5d5RPNM+VK9zdO0y564Tds
XIHFyqSg2g7lpvqYZDo47owKLDl+9CcFCEeHqD/R8uIiGiCXOCiDqB/rCjYw9x95LSU0VL2yd4KE
GGprpBQZo4w+0zYGfYGcho1WhaN+y01EC/l7yvoq/HIpuLSoh4udv5X454ZlDaQ654OPpDO5gEeV
Wd13CjNdhuSqvJi0HCSIAN9tnee4B5BJBpL3abeEg1dilvx4y064aHqM72xKs7+iXJ73NOcMZlxc
ksNxSrc/+Omrr9vszuncPoXHt9gFAlMlZaLUfLIfryhvBPZTUuvO5cKlszAKQg1RAAbMZgl/LpWa
XZYAGtWJjSuPbnFZQuAuZhpqtFVuIwB9krRrkpqP6UtRWOPmyr8XcCXIx93HgPmpXrUS2ea+lVET
q+Hj0w8ZS/zoXyylI4V6hJ7pnNG4D488IP5VSgM9TUKHymyjWCVDPbrgMflvGj8wKD77y/yhNpTw
aQt1cKq4p0nlsUegiG55ZuqihLZYHdfzF+/6nCFzaMSQO0S5hJnuzCeXSLtGuKkfXkg9XL1eyVrS
ZQVCXORJ1Bn4l02LHftKf16bL6e5ShJjZ0C7IDVNkOCa26HalIyAu4OOOZqB03RBjo3Um3HkloOx
BHB75NEuH17+8gsp7euycdqvOJ+9Kpmwpt6XPCAn9e2k3yVB1oMG1Bt8Z5XsMeXQBetdn22gmHTs
ns3t9RAp3E3IayDDLA2jReb44TYRzZlBhs+F4qKc0wVH7SYwrJCQ90Ew1/EpQ5AoEGJdKfVe8TrC
AIFrJx5TckV6q01ZUs3wV2GuodH+gX3A4mpLiLl6PnuQ5yljqd3jWv49qRJBYrnw1Bxb8Kzc+4+y
eV9TU2F93FoA7CPJ7OQ1+l55nRonZ6Sp9pI1iFvzEU454f6MzDZySD7dfrhyjY3eH6cOIYWgWlRu
0Bb45g0V/TZ3KhoK4jWOoxKQj35RW0mzY/9+HUyG2/3QoukqhZblZPmEb25zOI1uXQMoMqICGHPI
/YuF57tG28SeJ2eLs4LqXFODP4ShUdGQ9+pT5R2HZLJ4gZguimC+pN94ELZc1EJ8k9bqordbhD4r
2/NeFKsISfzeE3RTUE9zZ8rqC1M4GRQGD98j1kxx9b5Dz+JftHB8Nu87tDST3wrzSuwMym0EmAL/
k/lzKGBrc3L07lqmtQziNbG4q4NaX2rrPfBXN7YA/nYJznHDsRxY+QHIv3WoIVra597w1JhjmULX
k+VxZ/NP/hTM/dt75f/5d7HDcBhHuVipOFl/EP+qTpXJec4I90J1OUtHJ0JR+VrHHQDktdrlAN3z
lqZ0vLw2WBFcz69DsvZE2rgetLxCan0K/oaspS5v+uXSY+QNhIgGA3zGBR1VXN0VFeqg/Vd60oEG
JT1NO2X89H6vXOTS0le3TRrsxTzzg9pN5u9d51Tb5TR3l03CxUd9n+bqWajIzd7oRH+c9B9Eavi8
t+nbK6nZkfWtu3azxpyDQo0goWD9+SPCxP3XMXcXsYnzM3iHP7R4fJgaFva8VTdhn8RgrZ2V3YhB
FHNGCWpdpMWrHVu8XtIKKycAApoNRHekdLtbxbs0CronnzMQAfaqmScoSX2k+E/saQfEqLJ2qrPy
5mQWgQXS363ITeB5Mo63qNBMsKfEdFqIAw9umuY+tfjedUlggid9PDW9LMJZbp2QpJz1A4baAEf3
BkNYO2IiqOcwoAvutp8Y1EFGkq6QHib1j75PjwCTy7aKvhzqBuhH45War6klRppH5VT4+mk5Kpfi
5D1GizKzrKfqwXVxy1rHD6nM7OE6H5FcGvmAzUGxUrEA9d7DUrwz09j8hrEIjo0VBvGpVcuwflF3
9EKljvo63igmGaakGAGNwARNxE5h7QKNala5V1zjzAEjeGfa95AW537VTTWrz77NycRoZ4h/VLYH
fSJEoVrHOFuj7NGz7p12UHNwc7NGzE6jJ5xuhKaNDo1qKYuHrcpqYC4IS116K9+oxxw+Q6gx/tF4
iqO557Nkh7hJouxYV7EJ7wMCKOW9RY3JYFOZDPQ/k7ECv27T1yvi0v1pEYbEWSIrjskP+9gpwtiZ
v9gAiUOMuucCk44EWlTX5fbpQF43JAPnRwjGF4LE0tKSETQLklZXukUcfA/KtZMepCiIKZODvoMb
fyn3ziYsi/Z9FgqlzIIaGVvCaob8remP6daHk89QsDmCi+1pdPFZEItcdn916zP7xfCpeMT5EaWA
2q+hUmOtOLmvLJvKrLEUWNXvoWTq7b1aMWR+KRPg1mHYUWKLVzz4C9SCLyo9Z+6CtHuqwaUoWRJ3
F3cHWmhKS8GaIEXwHSQhB670fclGQxEaxM6Bj7U4vpK8TaVCrT+tcncY9JkR1w4zvNQ385wmDN+r
2Smu9PYHe4pLxbA+zmfL3Qmglfv5L0px5pqjHuFTTsNu6tnKW0i+yS9oXidfmAYAt1JlZZcCUm2+
ItuVliWcJ2vDdlRkpgSL85PJxmLRzM4jtWc8H1tnnYfXlZB+dbab0LzeP4ghwFBzuGppjeDO2etQ
IRpM1NzVaSKTU5meykQTqtBkIIJOtqCWm1fZIHe+w9bX+XoPicYFwVGOxGJGa17uzVhGdyRrcN3b
0EG7m/ANL3gwHYXelspg4jLtoWn0x2+nHqpUBVlPa51pHsVmxO4tbxK9dfngs3PLu8E+EF+pZPeR
2fUQkT42q0f/L9WSgbsHwednEsH87s6jP2Dy8X1VZDnT0OZmP5tQxtTgnhsdGTsPuScikWOejpXe
BkjHxfSUwul2dMWUvv4IaiFOQyp2adlz9UbSdaRZicmx3lkTO0J1/vZtb0kPwVODvCO8IROMs+UD
aOjUBPRwokxwLhm86YtyHPLdk5gyKPfrTcPaN7ljsB4fA++6OkOeZluQV7Dtn4XE+vpZI1x7z2m4
ZsS59XkBg9qR/zxuAQpo60UK+3VkRG8SkYgifyZs7mPRFUva/1o8IeAuTigmHSy/E9MGjagbMbia
C0XqveRAYJ4/it9Ywdy3w8f9+K5lq7GehEIIESlhHLScJNvENn/M42QEkO5qIQGVw0rYuCjfBZGv
EfzQ2uVPdn4a7NMt2mWhlD6UuuzA6AdZ0GjtxI+ZlpThQkAoNe1VAFctRqzwwHsovXJhinIuaHoZ
2uHLuSdp1ZI9uJQfIad1vNpyMfd/XPYrcH9QvFV3ohfanJmbCi1nQMjGI/mI15LV1zA+rTbXBxPP
QiHdYH2ydoBmmpp3tk2GMRHPT9jQWW4i9gt1z3eM9ORFyl4QtKouIYI07+59kdn42bgqYKrjOmzd
SbflAWUWpm73jHnnzw0W1HvEcd8q8BEuiLBjPg0pA+ilQTVJQ5LiQybd2F6c4Cq7kNcSv3VVVrWg
/TlA5YslVA+/LsB98te4/eyLc9XS3eg8ZjrRu83F/TpLqu+H1V/k59uQfNDeCOiQwWLx5ml8/9MG
SWwUW4Vy2GQxYho47Qvz+QzLhiSaGpRXR66rNprkUqAGzJm1A9OID0tdU5mI3M4cpuYx4+5llqWr
Z+ClAsWeP0ovNs/fidEPnFlu9dV2ZNH9hMgYAchl+ktIIiGpMFucoeySPHoaumd9p4YDXnWdXjYM
uwxLnn9OwNYwQYnXp4qsd3Z/AKbeXjYmeV+S8VqFnO0V22WmT6Hj/D/PAWwDxUhd/8HMf/XsrvUH
8lZzZtn2RJcj1nQDAclAdNmFkWAsM/UxSdS+omv2HZ6UNpHVoDOrtd+nWsH5Hy6/01jEePU+4U3H
LVGPhDKaDU/7VE+8mJjOU1cmFbmECA4zyM8i+nFJ2N0PH1dum7G84wEjTjPJ77teE6RAVQodeykJ
8GqvH2EzhmebzqkpopjFv72DJcl9K8F6/l9EqZ2fBIynHTNlXkXg2BIrWMRO/ipw4hv0+S413uTf
WIUx4fV+PZnJ6Ldnp0uiAdYUvIg+g2WFLm4dPcrC9fnnXto1sVwwOrXkSAOfW7FONqQtJPxc7wyv
ebc7TXhOMZpg6SKVOavfHq9cL+G0G99NfD3b3igY+g6BRZRVjIezkx6Lb1Oup1dtrAofUsZ6HI/N
dDXd61gAAfKypE/7XmZL3DxiGSIE6xHgg5oelhis3GX7G0a3f0cJfiPs+zaqbl6V0nyvSqifBR1e
maAOyIhRzaoDILXTxnUKNzbRflgJhVKcluKrjCiVyMOgVYyqGtOReZuk7aSbZuMRfi+gRd3+JFvE
YBV2ufUcbnY8xsWBYb4UIXjIMsZcAihTrwMHjPhTRWhoJ9DyeuSiRPHjDTTYRk2j9P5d1LC/6ZSX
S6Gx2UaYV6LGCbT5KpidxVtYGsDZ3l3xLT3fmF09+wX7BDTkHuhaJW82xVOXM1eu1dlwkPfakpqG
fqEblNp3NEWbHWpFENSMJ9J/MvwUQY7xpUDZ8GjWqzY4cMgZiOvoK4swPIDFsaQO495aaqSwzUj5
ECK04q5I0jtIwT5sQj9T+RUO4hpHT3pe5y3aFD/9Wj8XCHLjR6kwsJrWbJcKlrDFkz8FrCJwE/h8
9lt3mCRh5lZmfG2R7StalC39sSZrp8Nmmw3JVAGf+HKv/MhCJBgPbcQgNfy7ly/uHr2ZI9xSUBBb
ww/U+W0eRFgXfT+Dv+dqBW5FVmPEbUIqJypU1WLKMhw9xOC8oCI218o4H9Kt7eyTyX+ikMKZKBLx
V38am+Mik9ExQIzJr3ZvAfVU+cVNnazAi3oF9Z2r7WwICjuvsQyaj0qZxNh83ATpkiLh9wUUhc0o
d5cS4jo37Xlc9N5a05KeDNn4M0l03q1OjqahMwNUSBkcDsycsWTxlLEhpWh8siu11am0PDT3cc73
pcU9WOuZBLGjG36CCUN9yhY/DYLSHcGMtdZfz4CPaL9nsvtdEzs+uXj7j2gi55EgThvZRkivAJTd
F8eJx61FqJRREJ/jXuRXMUMBMaA2QhEKMDelNThbVk1v9GuQ1CjlRHxtnIP4FbUPaKeToi5fnjCt
ZiRyPi+5+MKHWCEPpS9qpNP4DTkJtQSSuZ+xcDE943480YEgQ7Hui3pfwkGTX86S59Fd/mLFX7Up
fTuxAvG0H15aj9z0uaqCkadmfbLRY5dUrfGRko9P+KwHfrgxym6gRFuZFCBDQEBHoPE1PAHhP4/K
zozbWuGuuKbUfbNHnOYIpvIZGrt3bsUdzBDTliWjsBxFvVDknWtDHVrgvtr2TdDQgf4P7KOJlrPd
46v7O9iE3lgxDJOq+o/s3E+aCJjOsbeMwAR8PCWcYUqLJeENDfVl0LaGNkjB/hRNMe914qLsRTtO
6kSWoDghsiTpoLqSVec0qs4AqSkZLcu8WtR5BcpVXNdhfigQ9FVJRXJbMbErJjqdHBrvLQNV/iM8
DzQyq5F7u9Mk3l0ZvAjH2Gh9lXiyLnJuByZgxsC/zP+TlBIecnbqLx0g7OlXeu4+t1+arNhGMc3I
SuVge2FUrJeiQwq0kqtZY4NXSrBTsWEtdFV2Mt+r0tgLuvS9oN0Jj7ehdNQCwSTfMHJKgFviPZ2h
MraTZFpSH3w6cC+XFKVwUb1ScLNqocEvb/hkOFJLOOCzI88O9Zri2hz18ERmzcdPZpqcxYbfcVir
rntvnw6M6lhcVm0X/0rMYNC4+JqI4URkp+RcQBMiIX1FZiAZxktSIajQQQUjLEQ2mGDEhdfDdpq5
xHoqeJoSMlW1X8LIqDE2YKQVprFd2JFd6aChSmcq+Z/bY9ejc5pZKetmrVCfXCiQFFGmxI/t8E9c
KSO0Dx6z2vdqNgg0d2VC5aZNxJK2EagO/0S3ivQO7/0JKdYhtIdPMdLSzMzUq15SZqeRlgpBy4r9
4LAQuByoqBgLKbNdDeNLhh7cb7ME4MBjFccBtM5OZpHkHU+xjm5l7ww5wVsLg7eVUZAILPi42cw5
ZP6wMro/pz9Mkh42S/kY1wfMGiigbFtwh9A8c5R/4KA6wssjFXAUJbLBgsk9MBcQCAe65wGxWYkK
ZBR3oAytjban7ewECmJfolv2RvxrcspAMaUgerDr1knJMrGy1XbaEsHrcJfMtviOJWwc77eEY5iO
hEqDSDKgUgf9vG6esiD1SVN/wlDM0r1LJEmLSlpafYtX/1kBD1jFJAsxLpCcqIXqZgzRwuxnMHFQ
N20h51wZxz0B+sfSkdBK+mx/xcZ5Sa1Kf77UIbqXCKq6sHeofrOpKU2V0GUwfW4xueDjTgcl4B6M
Z+MIDh13M8s3uguOcY+7fWpIQRsGBCtUpoL+QjQcwp2BZD5EOL9dUGSEPEF0L46WqMqBVTIWcAt+
LRFBCdqnUFEu2szYuQs3wv9XfuOGgiGcxHJc2bYXnPIJFq00c5dA11TkGqstW9RB0FI79BNPXchA
KhBFcQWID+8uufAGfsFS9Bj1rD/EkDwGNEj5mmqznl29Xi2sFe29Z8ksxG1/RhFpbzMHH9tWLY5+
mfr0qGE6iHUe8k+k75Y3C4WA6rq6cH2NV5mklHU36yEPQRjA7WNRgrieUr0QWCS9N7PSJAmDm4ey
gZ+wMS3zqb5h1wXUP0kWJddij20ytQFec6cRuqJryl7plFL9lu+ARpvFbc+dOsl3/wrmWSIFTtHH
KWZpLKt1DDCV2gEaDubtT0ha/GRHnGQ+qbvwOQjxPXmxsEzvPxjnVtJdPwiaqwu9nLDkn5NoDP7n
clwxJaGtKQzcP1WGfcBkm8gOVqtSNGJ4gNU1/JJ52VFjwHIdrLv8j+oseYK5sL3/eimx2lA3RYua
j5DVk41t3ut/JqdJMSuhAPJZwedQnIfbKmWpNHSdyWsq8keB51t7xsKjnDET8gE5ru/CJWdlzvY5
4Gst+VI6HKVeyUoQQFCiPIE5HaAR26JCrnjTDkOx7tD9WKl4Mdupxyu4KpcSeXC5699KBmqGF3dc
RJCDXAT4ouB/bo5Q16WHcai2USQCZpyXG6HcXq+5dyTJxPuOGUQHfHxiLfba7MTvDgHAbX+Y3EFD
rTBBdImbFCjw1evaJF+RRHkxDFalTXopdJhapyNoEFn0ldQjbRdB0+JWrkWKRts2AjVWSQ787ZNQ
PrlCWMiihPfdMfB2XjwDNE/iNnj1gc6OL4JORN0UG/3iuHO/+PLjBRkFVwjyGk783QiDHVrYwfbX
lQiE9RPUjxDy0m2NpCEF8WpYZk9Ytw6WuiFmdIB9NxKNoPy/kqPliNrr+s5N85qulasib9BdufCV
Bu8Od3USm2iXhpRk67KLtLik7Olrn525S5zYmcTCoEHNTbylZ/1ui+cNxrroHFVW/k4aWXuiq5QY
8kevvUIbM/re6mzv9Vw3XKd0WPkoCw5E/S+h8G8DyRZkxBeiEmW/hZJbFVF62plcG+J+x5NXujji
Zluy7ZbX8w2l+t4QjvGTThLrQmBpeWLvzPmzIqlPRmQF6YknHWKsqw0tHTkyjkSg1EDy8wIeITOV
J/aUzVfidHDNAC093iW9Qz1q5qO9bVOu9fMGnMKjqtNaqyyTl8Xt/2Q+T/G6OdS2PdLMNZIfo+4c
S9Wl2eYNXFZCu1QIeT3VzRkhMBYzJnMvgu9sPk0VMfKlGLSEAcqdSx+xQbT531o4gNZLQdwds5MZ
doF32y0STlX3Yik+ror9RRG3ub1U2Eh9N9p5/MqPkX1M/j8BwQiXmNtw/lIZK74W9AwFGiYDcwzz
J4zQbolOukiyFRQb+iK3L4yTVT29Wp5MRa+f+PnUqBETidz9HavBHOCl06BQ0v/lngKoRHiz5mdf
ZuinJW+Sr2VR1CGO47IOu3YYUuiwSY7cJl15E+/jDwtCTxiVJGYD2ibGAd4HY9V3TPGUPM+2YWil
RcaqnxecKz7tHFGMh7fhFn4jUAUx22xRSw8rKjpa3ey9A297Uv/dp2Gb8xHPuvSDx5cQw2zkag4/
AavOHTtUtAPemQ7CdbwNmghfHoriy6H+2ShROEjcZZGK/uDXoRL7r+s+8gaqB8/uzJFFoq/yKrsE
aMSAoltkU5mENgpJevB+9Bba4YV5zVwbxneAkT3pMevbu1vSkkcQ3u3eyT9zK1ckXHBakiBmCQV5
wAGcscwAaZuDmRhGVbNSPdp7cUdFOiNpLlc5yFSbXuLpe4cfIS35Hu4F+1coCL0t4x+W5ZKTe/c8
sqofYZCIHdiYIqT0pXKYXxdONlv5RxRvhJT2cGM/OlkXHkOIemsLuGzgFKu9U4J9fXlHeR6VdE3r
Tj7VzUgEO9O+vwYWqSzprAUydrZZvDdu4WC4PD97Hz/BCuhfCtfNzn5XcRvIbZR2L/QNXpeThS4A
b8yC8tF02GoeMEhECohJ29USpGRrMLVNj0JEEcI6Y5RJmD1Vk6XwNYEoTaEvBic1m/CR6bOWcBy3
7Sz7LW0GEVMwEfObOd4ItTdH7C1Cw+dMCboj2Ql+PhPHlPB2rWH0RIKGvDYL9ntxORd84wgfOJ6D
224z4deZO5MHLOmGGgIdn612is72ubcFcEU3AlSNBEEpubE9J9bvJqBODpbxyB2hxhEW3ThDSeyx
NbdpFCU+99ZlVSYBAmsqpDZ+dm7DAQqrQUQTuEk63cOxcwrm9R9ow9aM1lUDqJR+K63Qwn5H+hWx
Ea9l4E8dn50hsaa5qeKyK6WkW7vRB6rUAiWxnmBPBMO5a6HAOFGGwLsHwlyz3r4iFqBeQco9nWIt
YZol2eptzFoqY8fbGg6vp67DxhyjShxog/bSIWwpYZAPvGeTVr7j+W9A3MnfTCe2fun0vifTWneL
cVJIDOd6NOuUs+833TCuqDsidlVlqLBucDbZ//NT8086h29VWnLEfgv+6oLGZNWRNZGFZKvhB0uc
EnV0CM6qE6V6wekT9LOFasnnLwOJDOKhJYiaDIT28qQ2uuMJkCtWAJHvdTXKcU3kyx/NVByxg3JZ
3zR/pJt5smxIKqju1lPl4RbvBpzK0XyHR0pD4hyxbv3Dp7TnfPOWBiN5+j8xdSdwf3UCY3BprhLX
PgPt0kG4eZRhlTzlgYFhaiG3wcjantOpaN/3wAjijzBxPd498ZawzEgfhERmOXxBKxws6BGxOuA6
e4LkqMfHwPWoX/I6g/6KjiHQ21wph+0LCX7lWDULzpX9dkY2ySjd/0X8bB3DG0yrWNLXEcDYeQKk
VZthmCXj/SvP3Qj5NiCU8q79RvCPehaSCg9+qAuhzlE07EeAPKZn4xbgWZnd83LHyWztsXIs5783
EDTdRlHmlQTin5WGd6qAEtOULX92gcogbE3+kLh7OXuFFFqDerO5llQVieWOxz5caWRd2TF3V8V/
iI0DvQQEZkS6/jHQ846b+hAxuiVKTonU1/PQAXLzW87RqL00K/Gk97kvK4+vKdnJaHZMufI/MP2u
Xoct/hmqSG5vHkmxHywqw1BrzguyfsGngIfONSXwO/AMK9Aw9+LqSsvwmaB10Dw5tbzf65uVzQjx
Y3fsg/K2YcLLruSpzBVaW6+mx9cLce8UUxnCj8H/jmrHhbvHIIhROmBDVcbNtZ/Rmh9+JYwEy6xz
JJ7XNXZ/GKHRt8dckUQrt+iYS9FwFlmE7n88UzeylB7aRtWS6X2kxIGP3+T0Ag4BtIcNvQVixFNl
R4X9DOzyMCwuvUEJYkHJ6bFmsnJ2CrS9XTUo7BRvUUtlVYryxGUfws5GNxzU0r4lNwUA19Ct5QNA
GcBTmqUes3L4RdJjJLl1EL8DQbrD5DDUSdsrfzF2tFZeD16oefDN87e4bkNa2QVK7tCVpnROU6Vc
tTpVKwz5g1AjYOAbmKCjKHYX6PPM0OHqLcgoQ9EzWaF363Ob44VDZB0WrgjRuPrfPPn2iA+p3VVg
kuEgdLUKdh/IhsFLHjEB+WYOAk9laRrtGlJIXj/4GUUjt4cTWirCO7dMVw9jMB8aM+CWR06WxRKx
UEAOjWgPAmk/M/n7BApAWkotv2chaLD+tY1Bi5qggAbUS508ucqLBn/h1B8tIK7A7fuqmA5sUurF
TzrDqHWx5hjuMNiTCncbsMAzIcOqPBC7GmyN6bm1kGgkXs8+O5CD1Sb1e4WaVXBCyhUPuAFhUxXy
c6U6sFbiGvsIcHV1eq0KrQ5jRkyo9/MorGu1oJQuS6OOUdGhq67VQdbWV+5+RDFUfvgV23jtEBMB
HamRQ884RiCohjgf3lVxcYffVnjIEuFtdP3kojONjvFvIpypXy/kKr3mGRX4MTmAN1LQW3af5dSh
CV55UOhD9CB3Q5QOuKcbyZQC3KXNy1MRw3Y/3VKfpvedOVbqVuTO0H+9ydPeey6rTQOgVkJuM3TB
tC5sKdUmdahlEYrvQavuvJAzSMFTU0mfa/nnKPLKdwIkPcXlV+or2BqOTXYXw72tHe08lW/0p8jX
Ec9fbTZ8+aY9yH7FoKeiKsL7lecyHIZPhO9p08by7Xsg0wuGWAgm1jHrcTinGv42ayxaMshc2X1M
2isjqYS+oDkT4/r3dAwTdt1e4Y9tXJ502d9fh4q2aNAAwE4U+9SlDxUa5jSuHmVhbULlZD5GlBJ+
1e68t+mrxYdrxFkmlE0KwXWmkRC9h60BCjxNXwiXDkW+RZg0GNGLXQJ6wNNfP11JQtCpCesNqS8v
XWzHbJESnRMHnP0KWeFdtunsphNhzEYldWT6DC6fVwdrypBJfRkeB21KdVUi0YZGJ0p/N7zyobz1
d9AEJG22JwwprfEvwcA/5glsnpiFrpUTryBpyH9SlkeyMJeiM+73UQhglH0TD9qDePhkAN/E2lEY
kuuogJZ5NC9liMbKEMQ8FdBcWkuU8YySnjFk83Rq9h5lKqEVLaskeajaTJaUy2FU1iGUBIlbwZoH
9iyVqNcu2Gr5Pjo2tRviG4O0Rk7eUEdl8QkUXJ7Woa4C3CQAgRpqt1MUIFoS5Fw48CdtMdOXR4DG
x1zJUDAHV/7x7tgy+b8H/bXNsnP8cwmRU0m9FBlTINDLCAyCe2sCHKtTomWXu/CTBm7Veftg5LT5
qKbcKoCxkxLq1UO5AqM+ND+W6HDDIo0aNGg7F8ohi+sybyktA88iGJncLdZJ05YKdrPolVWI8CKU
yw92DW9SihnwbVzMNA2w84oqbivXbkVLWywBbsNtHuTR5QEK/9DiysGahsZcjwEMvWjsRGCVATrC
9AFTGzK4oeYVYDxhTbMrniQp4OarQuLe8U8585tdOST9YmxXR0qABNidK1nTQ5wxc/xdW1FMpfWk
jS61+uwjpByV/rfTuhRxK+fZjPsbU77qU65wJEoyInmgQ4bUVfBJKTVS6CiE7SW7F6BhkYVgl3sk
3YsJDAhxa+x+eYvxgpjX+clH3ap3NVhf7GKhoYnA8PnMf8cCiS7HwFn9odekbhdXNd9ttPe6N3uH
6qXiJAlqaiMXXzi+AG29NEhSQEFg/2FqklfrUY3f5pGd/Go0n4eAfsLCDAeM3aaAkvOQPASjtRbJ
AgzUjIT7eX5MHZHBPwygLiejH+qaVGYN+pQe0YeARGP00pUMMYY3GdMLbPyaWFJUVX9ZQbVrsxac
+a5rihWns3VGOq9kJZL09sgJXC5eiZkU9JmRnMAJsT7TdOjy1aCBIC+WwIBQ3JymVGoQbNdoSEx9
D5RT0mfN40aVU7lD0hfMsSPPEnHmjy3u2MqhEDjhjdXFuQpbAmd2hlf9pFTbVOxkI9aYxiw023uO
yd5x2mJQX3tbW6BMtPT8Q/IFbMFycjrnAI6MD0ebEykYLH1bfhmSZLFbBf9wufDhclQ1VPYf75xS
gsSvX73yRPYtxtmHuajowNCKLg7Q7HudexhJfpyNuf7weKQYdV7lZn4JJjJv6Ra2Zjazpoy/cVqS
oIRPblG4G+Tnl+g79BdMGTm0QtJBKTa9Aq8bYJAnK6iusi7cbiHmcSjsAdtPjHo+faXngkLdotA5
0w1ZblZLLpYo90k+b7MNO/6tXCUSe479mBh68l7itVeDuQFRaVshyTbnji0Zf0DrNeIz/xSwS0uX
0hlUJUsI1bEKBsIJfe9bU6FnA/grRov2s5WPu+6DXp/NxS+x0lt1i8wvXjwBiAx+q7/k04HzsxgZ
f21OllDdOiqg8dw43VeCjnxzwsXefwdBYumFnt9c5B591XdOeDZtO0W2KmOkwz/yPIvWyryzZ4V0
y4SA9tm26xCk+TmtaBYzwm1TzXvsFHUsbMBxhY59EucbsnvFCqs5LhK89sqSTprtC5SruHP1pSxm
4I5ieVbAHV/P8phUKBOuapvZh0d3hBoeJvPkzK+QErCosG8akCRZj2RQkZonLNxC8RvFNsFeJLYV
8nml7ML52wJZPOJZJBAoXgxHr+LPjcNiaN16/F1qG2nkrENaA99r1yx/9xmXuQhbQX6HD88Bayve
6adSSyNl0+yY+qzCAv1G2s2be+IYv1gCowlpjx4rWfwG4k88mm2CT/LW8NL8+J6sOksfvImxskvz
Uk3P5sywAiXURAR2vl9Ro1oytx9TUxiRk0hDFofoFHAblnYN/RSTqlwSNPQagLcUXnY0EtMV2IYP
oJnyCIC74gIekpBrGhuqtaTovFoaiLYbWDTdUakYOE9I2ClNDsw3O37kAc8bYiezFeoeGAn6V9bo
rRyXxYC64Ug02txFsvGa2dFhRnOGTLyqt8osHoQR/DIO1Fs7j4AVXbJ1e9h8QdQGA22hth0djzq0
ujGDJ1TaFVnbvA5EYV5+NyZ9TzKBAhdroUkzRLiWIiojoDiV9vo6bVE7DMPq/LlQenR5AH7uFMQP
KoO2FCjfLmviZxX30qlRo1zaptq3TFCXGSoplsMWzOKuWqqkGCoUk31BWzo448sWYB6bN1yx9zGE
rVfEH1ekYGpD3nvlHqlyWENFp9m1kaXnORz49EDmfpCJ2Jrxs79i26uJ56tNABpb8useIf5dVam/
4TXhsFdfRo506XGDAoZkmrt1Gmm8l+gdWy3lE4DNXpeJkNx2J9USyaz5Bz1na0uIuBtDmM7RbPvc
nEQ1EDW/A7Esi5vPxP9MibyGyAhZii3JUFT5Zxbt9oc3cXaq+aAwtHsJS3qPjoqTkG6e8oEQhwjq
xRNeDiZUWQeicEZC6oXzj3qZl6XM/hNh/GLPtrfCUMCHOa2C5sMYGtNyxexjv7yYeTHHMKZd3Hkk
C03jTATe82MmRsrmpqPvWUquhNM5U3x0KHdq/SIk2WjvaCeEIqUt9Xgz+Bt5vihCWFKT92sCMfCK
d1eaKlpu0sCcvy3vouFhj/atulPKpyzkYD3XaQYXZJNwauASjhf24TU3KJ//kBraDlNn6ESKgVN3
TgptBT1bUp9i2WY0gM7T7UGwELdhaPgf/5vKrwtsA49Bp4xakLTodrZSc0lXrr6QCo3otS22zdKb
/q6grwK6soY15nkc42R4v5BEIun0eQJZ6AOgo+QsNARDqC06GDrSBHJsFSvqcV/9TAm+dvnreg6t
cTyrTxi//0gfzA38LFenK4FDpEoIHG0kl64bh7wEWS8sImZR3BGsTPOgQkS6jNND69X0o5ZL9KYT
sLNJhypH/Fq4tivrJn7FuMwKaLRVW2AuBYUfZkxVbliyLen4CnoTISAYr1hyj4xJMF/51kY1vcsJ
nJi2JnE02/lTng59gHbZy1rdeWdutXna4zSEShQWszSaPHvtz4x0SZ9oc/5OFo38abmfi8088CrT
sMEvqbLCiR2MiDLor0xX1qgXJmoaCFyGZffyRutL2JzpblPBY8f8WN4gWHXKyaE4yS+PG7aFBzid
cB/nYau+oIN4l5yJPTkPsiyXOReKAsBpQtD/0aotfKNq3naB80E2jc6p4gQFbYtqNm1eI01VDytM
n9Xf9Ry5pjJ3/GRbViXqW9HAyTM3Ip6kAjmp7DBcmkSO88+X/cW5DpLG2NBQSI1vhgVs7enB2237
yve/NBl70FK3REDcxJvxkgiDfWaCl+J0/FjSddQEf85Wv1fZMxo8OnGYuzYAzJPx7YIXFAUFJgdt
jx/TfA0x6hh+V5EAuw9WQ6zV1i1P7UD5sCElar61QdmLyi/Jr59mFYPm7ygQw5zBqzu00Cu+DPzV
R3hNdUXLvPeK/ddH2WC3KKG+CME/xTsN4X+Sko46hPzjBYzHk9RCSbvp1PFmoKkbyBACo2jlr4tX
eeZEGSIcyWIy3qLA6tnhnHwIwBEG8/rweRYIXBOv7ZlS5BR7QsycI/i5WepoducrpjKkcTXMoZxQ
E+StdqRQaeYIoeaKHqFz9OXPHc9KdSV+bKX2/Zns4PKzyflVcpiOq0AtGDEqTF0DtSmL4PqK3xGE
TM4IL3ZqnLPvKfACEBkF9ZGxeryux7AqEM1lPvmaH5xZ9JKw9snKoVQgHglXk82oGcfQIV76ibzb
MeAeQs1jJCQkc4lY89Q8yetXR3Vb+GtsZyP9sj7MpvzLYQq6Jm8bz8pjHWDziBKDz7u3rXT2345P
pTmljzg55wRuOVDG3z6NpwlHbsoHN2RbiqiOKd4EbGKHTwl0/AKRATWsg31bSCHjbpJ/jOgPLgR1
1CdlC1u/q+0/wKp48IqyY6fC4sn+aIM8c25nUvXeStiTZmD1B2QudCnM2nkiguTMNbreMZy32lHt
H+uuhHGYHoIxkA2BUHDPPMeXDxtiwECNMZrvCGp4r3a9QX4R2bt+t9TqIHlx68IgjZk77umvXZ0N
3LE4Gk16jZjyArH20gIu1Izlh8cE0Ihbr+NMWeQwsPUAliG0qOPKKRQGrMpAfU2OC+XQRIscR2qd
zNhsBLUsak5PzooJACV+vqJGCMtC8kYZ05pXQqICTpfYVJ1nO6CWHG9Ijph4bfOCMn4btGm664ot
MaLK+bVFH+cUvXjap0PNtY6HQCc82L8IXydU/NlRwfOg2G51IvF7TqWhoTEsOZv05+I8sbfKJ6qQ
OSLrTo+FW0JamA8PLdyYsfINTriLTkdmdp9F6huZnWVnNj7Gb0lDdQSURB3Gp7Z70HMA98aeftE9
D5mavXhf7b5k3QsTtyh7AXXb49oiMggjw6x8Qr5pJM1a/3574hCgTJlWMQm74yzj8JfitTcdUNl4
yA7pU1lU3HUFaZA2vWiMvnNjPwy3vLbHbLJ/Ec71wrPozEu8YRf/N/T4I/izfYFEaPu9YxRG4vQB
woX9EqD9hxC4hX6Ojy6uTWXNz8KRiPQO80l98yO6PSA9O7oNbMi7GXMcGxku3JlACd1lV6rygvS4
2m+1IY+t+7G2721X6jYbxGXEDPbXlBdFPZJbJOfzH18X3ezyxxrh1kfeO2YTOIl3T3aaODaP+Xiw
c1Srp/wxUmn2+RgjXdMitYsror6/Q6WqN6kZNbJbOSBht4o7gqTeJtlC+eBrn2JpyjEIG8Ricvzk
8EfS/f6muqCQEXyKKz9eMfGWN1RI09jDuzYlFe5UoW6/cm4dx2qmpZfI5BeS1yH07kdpniOOMoUG
y1OpfueXxL2usA8Bc0S/uTxL4HYIMSHfKGhEOcUtmrZtyN9P8Hdr5bVefi1V/1/UxxAed14O8YHe
noGS82NljR/fpkoozqrBKPe5Laoy9g5dGSR5ednSegmRtUKaeVUH2CmlpLXfpHZ39NKfvhYgKGUv
LateIIKUFEVfn5EaD74zoCYoeAO+pJa9CKqp0cFuvZ6CdFvlLb9XajC1pgNGXEGpwLx5j1RCRowZ
5z1M1lI++ph4tH7bCP20lwiFnvSbcNXWQ2pvwmzsDVm1s35/LPOzztPhTmpwh/uBkNwMKucGF4RV
5PtGzTgS2lM9Ww01mgiXzRC6mnV5Jf+eBUJJUjW/ZBwujF41UlmupyLliWQREb44qCYyJeuj7cxP
q0WBQiHPe73445q3Dp/jV7z5R9DGtnS9txNqSLlO1DwuQMiY+cnrp7rxQPUV0L3v4DwM3xn98HXN
81Ac4qmNPcZ6KGJ1hBrvqZRjSIJZbpPMpJmHmHsS3W0vM0CNx2g/Z2JJPh3NsTC2kPKWkeK+bKb5
5/lfBsWeeSmbfdTdMdT9hX6jJ954GDQGZXXU13DpY9AZbwFgu3U6/3eVqWvNxk+dhp3WduZNSX2J
DCz/hQYwPMwPJN77WXMiqCfnlBgXeN7cmHaFPUT0R2NWyOv64SG631hsEnT9j+7ZX7rtWHLuHnLw
IK6Xhe4OHPw718xqlGFZYxFlvgCYvA7C+1mzH5z0TFMKVc/PCULEYEyNs+dZkSvMcphrVbWrC+r/
sO5tC5f+my+eBDzxBgnpHDDFLGVCNEUBLimntMTjd5TKB4SSAghNoJfvzoey4JgGzCmFdzK9I+WD
sYcPk3E7SZCe4jz9VDNn/al4B21/EBT2Ru444Ci+wUgM0CpgI/GWLsTH1bsaaTBOsnSD6mIPL3gH
6IzuBCv7L7++Y7grIrd81KFXbSDIOTwDPCDRRmszxEyjpd1n9Qt1egh98CWUNybJAR9E9PYA0XVg
2XQvoPl4rEP/wBHVsGLs7tzmn6nVJxRPLbEQfA8L3VdW2sXPv8yhomLwq3p8GgBIcsuemkjeQ2pz
dJRvn0mq0rmvPsa/HEUSxtA7b1cpEEc8Z21kNTgYAyhxVv/fiUQiwrGn4CK+5hjOjlL1PMuJrGm1
PJAeKZTrwyhtn0RdyXCO72iIVpDLEEhn6f4hRlGDfCFDvDkQ7Hd3CWW9eCmiU6CYNikeIY3QSIbC
mCSBxeTqbwLG4lGFz/exQgTGoS5um6fo6+sH4lefFs8IS93nkQvqJ0UP0iF7B3GeeHlzvea8gZmX
T2Sq8JDZ4g1ZgPhQ0R9JhhPThUfK4aqsaAHybnPqSuXVC4lASv0Byer0dn6CmKdCTRvNiy16ocbq
VAtOwScW7s78WlYXANfYTkSaeQOrMyvFrv6XxycQGZupOHTUko67GJUrGSz1XvtTXr7tKJlicEkH
CHisdSd8ckEmVfcmPwSwCasaUVq+gHjN9Ku0eJCqKii1UzWDlA7JiShmSknL1hXv5I4QD2jz1iKh
bsxLmVxKaxOwokO8cX2BQjBUq9wM7syNsBYVTxgs76qmTZT01MptLaUhIMAJfst064DRJRiripvb
1IiJORlvxyIk3HZ/MVzLxtfJQB5EgcUzc2XVbkY5OfrweJKkqnV5Ya274B2On5AXJjPq0FuRxCOJ
Ts9col6oUJuOieaX++EHisKrgqID70wp24U+8eVuEyZtg9x7GTkGCyGshgkJGUyaQ4jNOmp0mLD/
n3K0UfRZzV3m1vyubD0k/B3X9AgPRTxzrcB/kRb1bY2b0IHz9SNpBl3rFUHS9H379hb0/qVcL3ya
0SN/fSiPNNT2YhN0BRaSg9+r/I39EzGkHDoK4R+jEWNpkFLE3mM0KKcvzvkoISLNwF73s1UqhHN0
MyVbgyoV6lkpoRVRCJMl+y9iUGijgHXymeB75EtzrnH+umyjCJs26TtrZ4JNTbnG+B8pt8BQC6tL
KTlkPzuSrciJZGlY0idZu4HY/VP0tC0oOMBb/xDcU0YjJvydPzMtSPC56FT8CohPPXMg68EAdPx4
l3eCDCbpA4UQqUnL2xd0C4570l7OYZAlj6IZxZfiS+Uz2Mt1iH5QSS8xmsnZcFoy+BJ5dclLiCqI
MpzFK0Fx3B1dciDKbLRHaZCObCaRflfCS8Sla3domgfAJKpLwEd3sN3r80caTalW9ISENb+NOSOQ
aGmq7IESkrsn3V/fR4Dt+aswpflwjUJ4ffaamYiaQuMofOqeIbEWv7eBpYovrtSjJpS1h0BdtBcA
gol4GF3OFnK9NBNLm+Z6U2glIT8r4U3Vl0JXCUALEYUPCbDQvr5cmHPzDzZIH+ImL8VvLy5dBdJq
DpsA5+wbPGNSFwBqLk/j2hEySPLENfGO7J7fLvxh9BBDvKCvRzz/Vvm3rCTBptx6gfLjUlUjQlqT
Vhqe4+zyunMRF/p1fXca7SwfyzalqNEgX2L/OFtA00vh8LUEgozl+k/UmEUHOAJPFMYZeAsPZ3tV
nVr4DVEm5kLul3YGKSHFBbvyDv2F18FZYa+XArGRxVrvAXqi9fpFQ4q+goBgS4SSfoIR2GDEzraY
MU0D0i9sTbDVPJKBY/WS4TojFdTJDTChKhzIcVNF6J3JLU2hFErl8kZygZvsTZlPABbPQyqJ4/Jz
n8DDeE8yLKOxx7oNdSBW6YfBQvQbwRkfCqBpjwPTNGOciqAXpDsvr5AIRV3TeJt2wWthtOPLtb1C
ubXWdGLM+Yr8SPTbyG4/Od9UntyyZcttsBo5T42SYiiSQMfuBXNJNSLH9IRUhcBJcceLX/8dducy
ZP28cI6qyBO3L/4XnMOFM3I2jfNXNu8Tl26dqUk3ArajHS1ydGCBOnAniY+ZeI6p/FWR9E3RxJQ7
VHAVSLrrvFLPHCBmf0Lt6jHAIjHjzbW6Uzjco07OhVtlrIp7UVk8oxBOWF3BJ87npaUrBQHL4lqY
wwyjfA1r8d/U99o2lhY0f+rvpcK3/Ew3adlrhPqjlZu5ChaupTUcA984BvRUhnu6HLWyLGh98Qd4
n5IylkoakSRuLKg0yMWeTJnNSkffmT95c287z2GtuXr4Vdiedd6lQJob6VZUO+X6qwf/uCP0TrX7
RICgHSOngjbwH3yzhUGh3dFxZRObPL5tvw3iBwdu4gOu1D6jmayZFMGkuuMcH4I4JravwRahDYaN
86+4bIHkV5OTszaFsgTNYgDq51JrhRipK69YK7st6+deqAAh+7mWzG2x51IU+SqKqVCoa+aVmE6H
QAfjM+6XnwOtwh6zjR6VuWoyM/O8Of4+/7A0Wui4i1c+RW3BUYtCpnbC0FUtpJYLTj3cbn1wvx85
aDu3UvAaKa0dtTx9baUB9PLQa+Idd8nE92JdeOPPUs0u7xA5x7D5Xfnf/BESoJodJKtyBaKj5dOb
3415r1M3nMDujeG3cvF8nJ64FFoDsy/97BOLKTjPDISPoQ1qQqvYUoKoh1QeCrmuUv83ZSAK8u7H
94kb4RC7VyrJ0GF5T40IpLcZi5EnxSBXvhJ6kBQXoJ0NZupe7h0mfJSdfUIzXvR1l6YzbwQm/aVR
yowqUW8PD2EmMBexlABBm3yWGsGIyyL3pY30Y+IhGcIWWJTlSz8ZqjHRp2wq1bPzYOlUos32W+W4
wjnjx7b9wtgSPHgtOvO3lKiplcjTZVvJLKCuXwdcWIyUuy9/iSYUGsCG/XzAUVX12jsTxyWc9nvg
7eSDzbeH3qNAq45o5lYhHD7TLAu37bzUF6F0KxJHu10GYuHsUJxfSGXmZHBdQd5GXGTFjJ5qDwZr
RqJw7FI2l4eCS8n6k7KPIFsDkuYZiXpOdv6k/3ocueM9GSWe/2ZeanTM7EXwS8nFLmYwXxBHh+lC
qLmCVzy7zw7xooCsObyLQ3MdmDQTkuc4q4h6fXIrxCLV3AeK34rYJOoSlGEv/a7lGOjxkJl1ZnMS
jSfOZXnj17etgwcrvtyAC+9WZjdv9WJ97W0iFWwLb6RynwRNvVkmtj5GGB3zXmsgwMgrx5arjPol
+tNiFQgijEevOinsjMQaXBcWAgzNuFFsOnfkt8SXbFm9eeN/VMH/wq1d+P86BHGiUn+FW5wSXfsV
P4yFdVbprAb9f6sEyQugfqlGh034zWDy15EbNvjW9ggN1n2R+Aawdo5L7BSFq6sEOqcbk5654O0r
6MXxBwJN1C11OybzzTgyKZBm+ubMnMlpZzKyqLXF2Rjws/AUSCNX/DOyrWLTrTOobCAnkayP/w7E
A0QPkM5CiFg6S6F8/Xu+AecG0pRlaPbSTPLdD/VhbX/4OMbttEqXyUdjwe0OHUOpSrOmFrKMOcmE
NPC+yf9Q1n0siNB/mqrr0S7enkD5bk7iesNtaUx9kSQc++CPxyJASPEWcT1yKqLAcLQj8BcDGSrt
3YDTbZrAAPHGXz/z7c3wEQqbtaeU3ED6YBS0Snwds4BxiEWVuWmMxxsrrZK8tH1UrM7DBt7PS1Tf
vh0aBiWUw2MM5FR6eqzuMVmUkk17/ft3kxQr+EP/tPXgtWTumq3Yfeoe2B5yaVaKxpP29H5zrEAP
tfadxp7QC/D1uKvMNiywMqpjNatQZOmz3WHfsEndN8MospZPn8NBUYP+Jz+3Be6JbXYhU4M8GzED
+ABD5fVPeiHqecaToqIq2pYc8lJ1E5qfB3ZyqBbSmgwpxs/Cqsknx0VDC4B3GFHMPruLHY3T/vew
8F1VK6WhhrjHzovxWMgdR4ZARdu85dV19wFSdg2C0qTtPDMmHAiMTt2RBE/sZQzc6V1iXDmyGTXw
Cx2l5sFuEfeObfgiyOq2RWz/tQRZY7aBWNTtHoGchz+wDPXokqKfwtffxFE8iW1RzwA2rH6nAMz2
9g3Epx8c53vaHU25/8IvimxsGnW7MS3YLAZQ/OA/5siuAbfi9C9UR7jQal4HCD70oFj/R/jJmv74
c1DtgXguhT8YupSvgnAoQMOJot3z94KERFOug6+P4HA3xaXJ2bYKcO+2Ez+A9mDJOH+Z95GgsYR2
COqyj/PfU75k7hJMnEKqkZ6bBhqYHsBuMY3SxMmkFQZ8auA1iKHEMy3CAvGKdDXrOEP6JJW5Si/B
oRNnt17QOiHqzy7oPm9tdPihgGfK9Aze50JnpYXadXNccHcNsV9iCYnKZ7uwnV0QjS2Yu/tOhA1o
mxsFacoBtj8PA+r/5djmasQlXGRZD50nL/lmMmC/mcmttumI/Y8A7k9Bt57jjScF/Y6pUUdxakl7
W/pJqFYEOoDdhxumBTXD4zss5OEgDgUEgT6cJGGVr7NfKNr/9J/nR7/LjhHdeF0bcBGFxi8FG6ET
q230fsHLJ6MxR1B3sWvK0m9aF/anJCCDzaL2k6JvXZ31cK0qaxGADIHUngxqOyrgDn9g2vLgPrj2
NkwewzmF3OUIlYN7YJc8iEtvZeo/YROvSjAmqSKHoaYGz/Gc7H68r8FlmxJ9X8UiIejOiSxBBrIU
LhTV/DNjIPVfskwpjXq9bwqGkpvenHjOtJjEkVfXdjlXhRtgIep3OGT4udOYep60mFoWMEmfMEA9
z4Biz8ncxKE1ErLAREdmYyMsmnSGwU2oIO6rFWYg6Pq7nvTn0e3VI7JmD3mJNw0NKdQFgzlwzb4e
bomf6JCmzZqYaDRPKoUosUBSYHwS1PdXtrTxSvTCwjlh0/LsjLQVMOTBkpVHX0dKueDKEoBMFj1q
NyjChm0UlReuRlWUbnIBoYV5wwTdknQieHxahiGI6im/aRXjwN5dPMhfLJwfDI3Jv7QfWY6uz1cn
WnX0GuhTBC3pTe7BnFTW1xdPjf0aC5/ZJeKUc8rbphDvUOzPgEA34orEi5O288ZKdAAGaq9zem5f
281hzY307mSQIwRr6Ifq+aZQQ/jZeSVLwj1MoGN/A+aMOHI9Pv23nuih7PMSDkySJV0JaMuNxkrL
CKjFy5YCQ9NwfQGFR383DRJWlVk8hpsY91yV8PZY+RWZD7kNHmve0pUkAp2CtuWMWT58YkDGSBn5
bQsFe/7ttNZc2rVGDVo7GCl6Dra0GP4sDEyqil8A5SLlHRTkGEQagac9Aj5rVyLUvhLi3aJyjwkC
NVs8YR7yoxl4DW4gN/3TzHRJUg5srNa6ReW85xJ0LkOK6w+2ewBpnOeAHX9z6/4OwF+TIdHpkdGZ
vMl9+cTzntuiMVxCnvH8s8QNjpLjFzvDPweqqXUQD8JS2QVygQI8PXTWISXxu6urP1x+C9aNYFj4
F4j+pC+Fjw//0bj37PEU7n0S5+rH1RzWItnYJ4dzPJQtol0AjoiaPlF/EqNZqK3OpDHU+24bDRHa
qPmX+UEHlYGFt2u5ejYUecLd+8bIyGmlsIRMizKDuPdqh6Se2d6GdjdYnpnU+bTl/9jreCNgiTwb
fpTwgUO2tOXfuNKBvJvCY4G62cbR4nhFDrtm5z6ylTCVpCcurv1sjqhMjsZ1laoUoPuYXXGDgriW
nQxnqtWj3mXgIz5MxWhYzzP+LHcR3YeAMmjQZlOOHFydZcuWF68vA4bHW7UQbCgUaydJFPxjLAjK
ez1nk1ST8R3sKcbPuCOeucTeAZSXEsm4OA2X17t2a6UUmiY2oOaTqpRyK7PafRNAsFddVOR2JBqi
7Y4Ahg+rd7oyEioAosszOtWhN7wZHFfgw/W/X7BpSuW3vt6dLEyUQKemAjtRWf2++XxrLmo+Qm6z
IeyscRnwtn/DWUx/g8bqKQkAiNQNE5HN+f4EJ4NIm3/6+SK9moqk1AusLXaOyuc6+My6HCAztZ3Z
l658t4bHSzNcd9TupnN7XgWWdQWPgeZXDrYaFnvJ58lnIJIT3/Z4pb0jh/ag3a/s3SdCYsALW3hb
q/NnBlqTzCIlZrCsghznrbLpebQYgvp+Ikaw1981DyJyy9RuKySGfsA4qs9LqHZoMwklHTIC55FI
+4GQbwOFsrJIwwTcPafLh43V8lFDQTbaNXVXMBazCazioWCHKkiSDWaUsgAbrb7TnfKvgxIy465N
VSEZ000NdeZNcFmX4ckwtUOWtElaQyPM2eLJqTbvxYLV4VB9B6fnjuEdMMHREFVss2SdtEnqjGHu
rtdGjK68MX4VNNsm9O8pGzHdhai8kNpJefTzlHJZJjjPDx5PcgMb3riH2/dSWkfnck0AnL1L8yKL
kPLgxdOHZb0EIsyKYYBtWhNcqGjIdNidnHUbA346CefdP5jJ1qpiZabSC3XfkB2iOKaDjL2d0UYN
IkBOrexH8MFpXfODqnhPsJcIYS/M82AzJAtQD6TC0Z5uPO44Wq8R63BMo8BERWqbO8d6nNsHagTs
yXWKwNggkcztmQ5C8WyurI2ybMHO6NJVwSt5c8mZ9Rwuajk8Rd7wcJeGVqpnkQ/abBFdck7YWr90
QDvB119gGuwq5TyMdYkuDcKTxc+a/lxKzQqlxZCn1Nqx2QNKCSEwSbagnOO6eD1yDGKi7kG/w6Cj
zNIux68rIigq3iPKmdpqql4/UP5U6At0xA5jmHfpcMlBN7f/YK+oTbVr8w59/zv/ssi1nh+nCuj1
Ix62meIHePOMhdkSLbCQnWKaD3uKemCG0jfzXwUvjrwCnjrHENVeZxTS8l+G+f9L1jLHar0eAB3l
Ty9wfwZroyk8rfpUSpaITMBlH+fPmXwsMFY7H0NvyJWXTBG4RGCHy3s+eIEu1lHt+LmNDkXiMp/s
Px/tUllftn327/g5LS9P3E3kgVad6WkrHjwMT5NrDk8WvvzI+zIOrdUzzdw379nsYQwE2dCR4XPK
cFp9Tsp89yL0ZzJprCUL9nwXLkrT+0TrojzuONzfsP2+wdhUdxYQqElPrJdndn0yfbITItGhRgp1
eLLiahBgcPb7hE+nfk5RigTH/QQ5nBPNfl3vhAao5VNmnHapaSWmnSUa8a3R4iwd4DczOTDyrFHi
ZCBr0/xNzv+XkKoKHJWbOyOJEi9fMgJnZos5YxlOUEpW8huYgjPUlzivkScYypBt+9HjMG46eQ7G
pJ09F2fCwg/p8Enw4+/TUREAS5PJXnTMqXxZb2zuTN3hRTI4XTprQm7Q3Tfq/cD9rvtyhV6bQ6iB
p5VFYXxEdI0PUQiz95ByktO998iyiD5j1Y4ruCoVBJaE3DP+FDEsyv1a8hCpPGlTtEPMMj65xK09
OL9Lh/cYdjM9bcrYWbaWLHQIf302UG3J8+FCRcu9HmYs/Rv98w1pOFm0tAhSuMHNyKL62BPdA5n1
L8FydOPrEo707A9H+BxqeYu8DZGABmfJ4Zt45KXLIf7kxdITM8c1Ue15Noi9nPZ8jAYUnd3eMdze
rg83zgWZFDDyUxCweG+Syp4Im5KnkPvnRU66nlNde6sgK4ClWaMbNyaZWzEyaHGAOS3/FW5sFo/Q
xByV4wou2ceKXAE8vmx3uum4gulUy33cl9B9fekFy1Yj/RqPdyjJEr4ZUPTRCiLg0Q7Lf90oxtc1
2TDsttBo0KjaJwXWYuOLFZZ+idsHm/F6BDDv1ilWtwSBTdcdh0k0KEn1MgAoiLYw/KM+vx4VWUat
XEsugD0Dg5GSznO6I8YHASvb3oChd7zBNo7A/JEi7oQYFJRhs7Kr2DjhrFQjCbK5rfVp4SRpEMCm
oFiPlhRLN9hhdM3879Gg6PMix9h5tbC/5Mn/MMX4ZGNu90s7bRStJk+pUnW3QALO0td8W/5vb+ea
utvSYnFLPdtj43rrzKS1M+mHPny7AKlKD4OHXmIiJza3c65quwf8quuO1k+CvI6EspBaIoEQV9CX
DC54isNZAdn6K6MEbzWCJYDkXBnmYlG7+E6mwQynQTEgntruQ4g3tU7n/lUwv5kmBRL7Hbxj7zXw
38Gk9jlNDvn9iB3gC8WwFb+QRSwTbnvxs0fODDBw+vH9Bp/Ze4ux/3I2ISAZaH6/Sp/EJW01FoLA
eaiWu11EuR0gSZSaKE8bOA6O8Pe/Ff8s8xVv9bPkWjGc7pgmGcQ7ftnCe4to4OnblybX2ZYkn1Bx
WXun0WYRBLiF2dCs7xv3O9fEPOarJHZiVKpjq2SY8zPhfQkngMqdoUFUW6nrJEWnSn5BfBl7OCnk
olDIq4lMbczTWYNq8pZJXjZU+AE4jL/qPSeJ0kXRiyDSM/KZYXkq9xCGxp1azuQRsXKYYTAM7N+k
xvuH5w5wBwsaKf7DaxExXyYOASEeQjpCa0W2cpmNpAdOAoMgBuJxE+ELk6+y2ZgwjXFTtMp1DqWe
FA/w10kb78X2S3mh2lAheGcbmFuS2BQJJ6+1qo5lD/TOqQgyE2DKDSpUB6dJxYCEHG3yDjTITIFV
vSCzggBijI3kJ7OZhFCzpb5TPX/HqbBkBYpgb/yXTLonGDu3SnustpxNobqsSJpslKFsng6OiraK
IYxsDqkdqByI4vAGrAOVx2a/m8IO5m83vItNywCd8cRpABt0xp9IFEYiwmixZdK+Rc0H16EkC61R
pVCVmYq4n26i421/fT5SVDb0kwQZmzmrnV9pTYL5W0do0BM8OyYCB4EyUgzPk022BIMbdNLcoLZS
7we0tXuHrAGMNgtW1e5OUGUki0hHFSHRGybkcFRjPlIJMAc0oINiiE41MkxiHAgBP0GP9sYQPFOK
YCb8M8yLgTNe/PcJ3EUOiV5+knvTIcJUJY7o+0uft1El4u/fxu9GiDfj6YcBKqgx4W2LcHyLtasb
xnAlXJcN5ixKUn9BS9CedbaUROrMzabJ2EShJ2KgJ3d0KuRYtlBP26RraW9pg9/pQ9IVC9ExomzE
WX3yn0HBDzaSRfqL6C3LOz4Caz/NcOAu5AxT5IXpGuMXV/L3vNvrWuR99hYYeOZ2fcQUeFuT5bt8
IvKhCJlAD6XHD7sYiDeze8L4fVYB5SQ2Y/sCpLVS6/lHqZkks2a3YdU1uFi/M+8fzzFfVYJ1zbho
8phFM4mtOuPEwdNFVW+UbI9RGLVWkhZsbLZD6jmR+sH8UlE8KAp6zBp8JEhdm6uqJbt3+4SS2MA0
BAvfC7a/8yNRER+QQ+71Nqno4H6oIVNuCG60hCEvwSoC9IKo/VHrKrpgdtieCA96KAHu+iZLEz/r
eLAgGkKJAx65JXL+vzICzUGVbUZYrGmbf/iYv9oo07gjQ4h3ZkPKhtLPunxAqRD2c4ZjFAziNifQ
wrwwlBcgf3Mk1SY3x4R8G9iA13I9ENycj+4eeLwjKz3LOGpOscZvXmw8cfGzuHF/eIDrtKyroi7k
4Txzibk61mkbyPZhaYcebUf/+yoatfay/5TQ2kwMJ8zdLcPIBcEg1t5SKPisYzDOekJ+KIfkJ/AJ
AYKMWulKEW9WP5LLQcvgpsFYSl7E+kVq+5rrd7Frkzm0cbV9A/sIpfXClpt/+/oWo17uVkIF5KMg
/+hEaevfiTNf9+ewYG1JBO2udPqzToSyGbJU/v5UEWh4X5M7j9ASJfGzikbuxA+gQnulFw0eFAqF
FXVF91zKbWCFzPVku/88TQ/c5gQRM3UPh1rjKeo8HsRvmQLGjOE6sIlkWSt8U7uWLrshWAB8XPRq
iIr29gpSa7n08r1rHiS1mewdCE/RvdxoKUrqhIjy03b7GwBPy/8PaGkVyXM6N0JuOKpYQOPkGDF4
BpIaqn/O/yLShOD4ZgrLfHUU9n5YKwKNVMo6f26QTjKSSuIhAr7/7TAptxfBqKKNb4mTcgEuUslp
SGNpVliIACCkhYgJPr7Gqud4v2EDFkXIbfi6dYntmgh0q+JS3Himp+WRIde0GquVto7DMkwKx+pB
ibN4buskVPVjtdTUxtDxbyoOq/1CK9qp2y6ZcxJkuTAeDxvutgaeS/Zzf09H7Wr4pfl7A3i/9UPV
Siqks5JEw/7y80zxvrk3bEdN88FdDGp4Qb/zcF5qSqNQvW0BeHIY0EMy9aSHP+BGtTUvGF6v7YA5
ppTGPIP/pLG8d61kzL5hxeGpSYMP3E+yeFTTnoYvsAEMm733+qrb67JUCeOUa/FYjmR+NqdrLkY/
4CKpPyBGjJR/eXRdMfK/9OMYaQvddnFPA60eBAyDqWB9pCXJs/7jT4zqejns5jZkgWNLaPc4z/13
vYJqEBF+I7F8G8cuKsgEB7RqywXa4Gl7IBSLyC67hL8QB23gRVv7IH3TgsQsfPoaZ363sRm/wa6G
sdZp/bA40WR90Lxo2eK0QXD6cwTTxnlKIUISdPbEkCIMVN0X0Dpg1P/LUsbev3O+Mqn40YjYxDSc
eeKafze2FfnlRRSMYASfug9ZiG7K5BlFy0vw+O+5PHbZ284hBdErTRwL47guqo3BgXBzP6tV6TYT
paGUwdDxhYpR6+OMNr4ew3STH35qRzzKLc2Y2paNkUOUfbiSDU9wY34vOG6wHo5x4og5z1bdtSAo
GISXaxkyh7AyxtsygNQGdG48+/bb7BoWCbbUJZfF60vUdyHfOtwHXzVbgbF9XUdYjBsZiAFZrLdh
1YXiQlxPfiSGoFMwuVA8uZFHUN+2uU/i6oPwYnMhmyTTcPHef1YMrOcm4MaJSZMxZhfS6Ei1O009
DSVCQMe7QkzO1QfAGUbE7Jrtc4b45g92GkzaUCS9jRCYJWeeptlyuWJvHP9ku9kgtLsMjT1MbcYH
CMxf52LYZ4NTkZGN9z9Q5XlQ9ZujUs2/0X5wXs32sWPHaZbgbPQnB6p73mbLedPpIX/Jgx/1JspG
rIlqPMnhYXKsoAlgSyd3HFcRgbH8O5OpLl0qOTcI12owzZRc0TaMquIbNB27q2QehNr8YFMk87xl
9CeMbiXmyGPZHKwrqttJ3OkVAP5MAseQlQiB4UvHywrNa3qcCTpzbpP/PQj1j6v8ZzNYF0XcL0us
pOoX7P+kwDiu6wCtYC/Xc0Vz7V6GxiDhecP2DZb6OP2fSftB+4/0SjFTE30Vz9nF3TSjVuVZ6FMP
sg2fFRak5oOF5W5ivACgk6+0JbbGcs8wdVvoEmdmkN+VEwOnYy7sUfty542jOJwu8WKTdF4UJSjV
8FH6ecGerQt6JwpoGewJbHxrgzlKimNkFXeAHi9dpW0kYXUuwmVyd1whEMCRsNsyX/9KGeSzIaXV
H2YfZTiMex5YFD02sDf4FPST1usiVjaQxTR7vl5hwEOsa8Cc9wTbZgUv84LGlBfFYlxEokDLq8Td
gKkPdNIzm90+udY9sO0JocYKVE/N0aNCZtJIg5/c/SyH0tiRYbfOgxY8dNgIljL3zTdbREhjrSbu
fYuIBEY/k5qRatEQdFzbl4IYwCSD7MKoUjJ/BcYIreaP4kBRKrWDQzj/iJw05GCfu/clAcAZtZVd
XgMrK6wYyLWkMjJ1cPUUcPhlU5Zv06Kcv9PzgDCdKYtBx2PgrCJ3Nk9CZhw1NK5T4asmNBHY+0am
9JPWkaot763cJNZjcOUM3jnjS/CO/19GS3Jit7zWdpz6ZzNvBfoqFgzj9k8jJGOSDoHE38cAUPdz
SqsFOj8cOr/EXadXOxUdLM10HYrmCTHMkHwC1Lpu7JGeOrivg63NUagBByY1Pd0osjiGy+koy0E0
SAoAiPV/Hno/mrPNA8eR8yrGkHIihqJYsIzky5HujOKKVqk/Ql5gcMuWSfnDohHPvu6sgZfhfp5O
AAutesFBkAjqsQpmUXX7qKeH3ecmXfW2lfigGryHiQhf+2GJaGC/ZqM5s1QA2ISWGXged8k4P6uB
zeatr05bFh33fTNv4vEofNnQtWK0F5S6AP0Ude14QFSxzttZf2wxjmwX176NAQQzTWxv438s+BdZ
202581pFzLLlo5b4Bzxkb2RcQEko9taIe2YoL9ZQnBDawaNAM3yyBEJlrqgYL+Z0A/Zm+ika/Kkp
fIUPFGE9fCwnWDsRD6KZ9os9z2UJJ8f426bO8chAiJnBDNGOdu/ZArqZhq8ujdnl/n5+TQW6Nk67
LQAjC2FIdQ4rqT3MdhHXu9pikG0ghqLNx9XOEkjwupNPSBlk5Ndg4Od57VOs/84Kkz7mRbmjHezF
IX0JXPusiBpR++2PQkk6MWqoreiufJtS6bDeoaQAuyUSh+8TJdqb8IHqq55T8Rrdac+dJQnkOpAg
0IPRSgOm6j0kMQkCvLoctK5m8uV88okq8YBxoJuDBaqLPxg96o7a0KRzZlUHj8vM5ey4d3G+PQre
OQciMV8T76KdCORopq/omKj3+UXBoYKB8uUPfJQx3H7f46pTRgMBTnUeEj3tVUShO/OGOrAjFk/k
K9AZAOSLu47fbR2I9V6fuJagnvgDX/epA/CY6YgYAdSdVGsB5ow8pDfCpVD356m1AVyajNGv+cKu
01jGvAh/eri87ydDezQbVLCmJyai1eHZOon+wx7hDWXmnlc2CrV7NgQ0vLBbKSHkYmx3BtTmYLZA
gLVdNS04TVl/8Xpdm0savDRrKkNupfE4xKNANb9qMALqMOHuLvlnQUIhHqUthFLm/OMCL2Tf3Bqz
Z07o87C4sputUS8m46Od7JAZ6IAsEt/fK5eI243w0nX/mnYrFf007PIIu6CQFPuAn5tsX+6coKXx
TmbkJrPi9BkKB5FyldB9LfggXmG7Rrar+ZSIez/guozdjQfBYtWbKjUyCGVl55ZzRzfsegZvGjGY
/TkwaoG3L4m0lINEIML2uBlD+MyPgY4TXPnQHjNz8NLOm+bVlXmZMVXuC0dmex3tkutWFUnlo09f
eecpQ//jHh4QhwKpdEGOcogm+ZzLcchdVIeLQE2dLSZjcZJWHE4ylhBhonBP5aFLKCqWHgky+1ms
qwgRtV0xzH774LnWzsnGCNwu1IOd+r/wUmnCCbXkrXjShmRjgV/M56j62QbbQJtzUrhrWf/k+d1Z
qCmyBEXcn3GWy+IQWqJe8eepuoUDgd1+/uodZ8piBb0B5pybwQBIqPCdqLp4h/h0rmXiKgaykwRj
qTo1nc7c8aaEZZhBqDzpGWIheVhyXgFBjNMO7jdBXihcQCFulXBSrnquj+hx5zwO3qRNsyBUl7f2
ghDVIdOgrOIh7s4OxmK1xqvL4qK9/6farblM773tRc2S771oTX3gLtKdRHieF6UTi/cuePZ7a74r
E6Mj253XNvCJ19iYShxJeiw7RFKtAetiURHxRvQPqD09DtcGis4BhVZqSDFd5DxfPQb5ASy0/H2R
5xQYjPuPYXeECIxh30+WVhu7B54otattUMtQLl+CWVpV524UTSZSIiuRX6wgknosHBm0fnII1TjE
ntek8dtf26QOmfChXuV5YF+H4QRbB4FSeysxgvGRynlpSNzB0nT2Ki5CGsRKmr4zw3cPsLDclSHc
PiqSR9zEcrYYXdf/J6FaMNSgaSB39s/W2nNU/7tsu83EsZ1V2BFTBWkHp7BzWyRCZiW8hWCQEAiz
S5+/SzE0tRSgabxL3zhjjv77yhNx2z8Q47GetT6ctyAy+dOVLCWMNgpWymzzgzU1IIMfGKTcBXQh
hlai8ctEY5KmiNA3Okacj4W9ZVdrzd+VqDFQAmRL31NRAQvTecFVD/CtXoRXA61+IvKGk6njWfII
Wty7qhYl88TPxBJEynP1qNa7/Bcu8gomTRkNAA16ifQKPuBdifqjOd5XWm6kA6wrqG6YaLTr0YGY
l/FPhgDmG6IzJopHfmE/4IGax6rcgZEse/DaoltZtn6jL3cJVc4e8RnfXCE910Yzt/1B+x2emF5H
FKBCOfabp/faMj+wcYfQjid0MAiEluOyTd4kYqeNM72FTvYvbxEIihfGyuhM8sWyaqmAy0XZPdpl
vkxrqwZ9kObsAABNlLL24TYKaWp05K5gxG9VAkcHdliXM2b9idstftwMwbM9Ic/R5v2ZevimrzEV
6rvJgrmd/R9wjgJYX2kt6bzv0QF9226mR039FB/9YeR5yxlNH2WrvI4irLbp1zjR+QHgC0FFQEWu
FQF7DAMzYc8O0JKnnoPIPw6g66c76GAQpi+/vurd6lQVfz4dzHfDz+1HfHAfJBBiM5sQp2L0w/L7
S10tRWGoaHIzMGbWoeoXs+25Nt8gGb8nXtgcNlbnXS2uztiGzcJg0/C63viBacSbgCmRgYy5hdgE
jpuP4+JZiYMUwklSpunXYFoq1nDwCZV/7UXYesZjCQ0cVv2OxSW1wtQrRQXcEWd6i6vgfQeUfS+Y
/+/qiNwVpp1jEfueChrxM69eE81DKJKdxzELoiDcARjRa2sXJp8/k/vk3igVt5CztiN7Tcj6H9QU
LzjVOOSoF/XBO5ArZEzLcpq8CVSBAv8MBdCjrh2qz9z7Fo8+sqd25mlXwljAgaSMYeLiiqO49gXo
UKDE+SIR6tuomR+s0dprqiGmKz4wxFZxDaS3IVt1rfkGo11O45oJ9p7VLOp58sDBPzNzjG6Rlbbc
JdXD7YSmJGY+oJmsGJlLTXfvcqgRlGAyu4MQo7U/PPFAvGTDSvewtHUyHyO2UyQKkAuhG4yC6h89
1EXuqdkx5C5Fojbm406c8gUYvMzhlNmWUzSK79q/XXw9+gLKm2sHdO6/ZwscS/pz7iA2f4LN2gaH
MCOF/4UUuLI8rOW318RcC2zPhe1SIIKkiJrOZoJ+x9tFs1OaF7Sc4DDYXMQ3XefVCdnKygr+KqAK
8tWHOSKFBHgUVVHgzA7I/4S1FHhoVXcDSZlCbc/QOmOSK629lxF3wCwBh9keqQOJ3zwX86JfMsX2
NgYNFw2xy5XsmWrbCfFIWLokq+GRb15YT0OP3kjKPpTqjfptIzFAdVb6m3r5afzdkmxfOP6q/1lF
/eV2nkBqTl2ettKrGuCYZnKqw27k0RssENGfc2J9SpmiUE1/ZWeEwbWgDvL3UNOQ558gzm7i1rWF
LHskmTqBJnjrHAdnW5UWI+esbgfZxTcXe6MkTAu7XxtitxQUUdDn76f9C0PCWvB0ktyjFv+T9zwS
D22Bul7Bt3PWihYKYgA9LjpYtFg0CWhfXCHB88HViuSBRpxr/+M3S/W2lvTDr6wadehb8nh3Q7FL
TQczWerFbUSK9lB+UpLrGxWsxgfsHmS8WSm/hsRMNtV0Idv97HXKmGxytwPp5c1VQqgjvr2kY3JR
eXXX+cTAdV2sZXf7EbKQqLD0SJf7k+U86f9Cy0wkcZjWM2xs49wZy4k3mrWesgLP6RhDYnQsYhTG
SrkmBrVV//8h9T1R9rtMZ8rNBr1ankA4PGiZC0TgzDdoSq+QqPp3pCeJqOSLaI1ZumgYgIOhp5ed
FzuFTDff8qUeT9e729UVBep45WRguHhF9LgbCdl5W6yR8ogpLzFTFQnQ/Sm+KDMOwTy+E+wWHPJf
9ord7iuOtLOzeY5wDE3xawVEswv2M7PoZA0HEPcBHemYwheUsivt3yrnnXff0Y9m7JKtRkeH5E81
wBA7x1ILSORZqpxNdKBbzZxY7aTyxuTanYvEneILxW2/wvia+JCefzmova2grtGAJfLLugyygqE6
cCMkUbGvcSVYvsu3HllBN9BziZEDPKorab0cgEzVOfAsAskh4Nz/Pb6S/+AH3tJKlw8vyI3qWaws
54A8a1Vk4w2e/+TLeVDmWPTLmVsHET9MfzTKRHKD78dZKIf7vgn5yXEpDyqvb/5Si5mQXnun0QQM
ZhTcz4mqJ7K2xns9aXjQGhYS4qTvC7RhSlGgPQ+TzMdJ1+9FNMtiSV5AY8sK6R2QYLMf2enl3Cqt
inic4bTS74fi+7bFpVUCG4N62xFXU1DDz2dQq2NDeETJcbcgJUm5DGaO3mu1+CcWohMlZXxlJE0P
hlQnAkeepbuJgwsS/ylJeGgbYU1v9OYDZwHYFR9lBL78p+dQ0JRLh5RXbdIKQ2BHIIhE8wgOM9gG
zge3uL1KGTMb/uYUPu92qFmIVc/imGnfMp7qmhIUk1gxkMQnK2KOIvs1oAFOlEhQDj3+OGVhTayG
NxyeYLfOJxM2k5xBQN1hshQgxxe1p4jkeRbOpJB+O5+gltTQWozUc1PIw37f3FwgFPMzXl8RtCAA
p32RX35piF1mO9Yhhdg7rq8Z6GC53Iq1+rx0ik70jFj6iQRmTcjkn1LboFs3VMXOMhcfC///hLR9
neVcPvxEwwAACJ9fmW8hYmvfZtZhBexGfMDNL2INzPs7N+ZaVD7egyoTd7hE7m4RljL7Tv/o9doN
TZqend0be1p+CCoZ7ZclmhXfs7qd6aTJzow2PwF/ZEnUsU9tN7YQQyKJRB0g9Y/iBxKhaqf/w509
dj293G19mzB1gOvmkZBzKN4OqacRNOHGl9YKOipKzudtJbXpChxD+0tpeWlmK4RxR+aHhPLx2OfW
arYnoxH/hb2+28RIqqCWHzhPkG1Xpq0251TU/UMHlzsGd31v4aiTYEnMmAnrxk6s3+YIIjSrrEsG
Rs8vNOkEYtnKL8rK5kzCpHz1OxGOAqbtICFUSaBHZkfKzPLewpBN7JvZXnyyHVjz8hfIV/Svmhug
ESo5hZl5UUcgWiff+H/9ITPiOGuXUxBaaRmTj86yFNWQk7a7nyxFoOtIvgR3IMp+HQR1aaR5y4C8
kxiS/lC0XhDGodQ0WkVsW6b+BnCOdyPqVCqKgwjDMQuf6j0ULWSiLk83R3QFhO8dtXE+M1YhyUJ5
UUILLBfBkg2fPudNebnrGkfTwgMLY6CiUgyVCJ6TNNKaeKvSebCn/KXVX/uLs+yOzfB9YOEZsXsN
a4NSPKh4JydYhodAqeteX7kS6fFy1RHWS4iRrKEmnu6gVHNxhdlfgDYDfqvdOD/bpn+X+2PXGa6e
6YaVKzw14Rjy+Vjpy/4IONCItUeKM1Ixys+uPzuDDxxZj49gawP8sQs8nMndpCmJ6dQa0+7EnZdj
ydOwO+qZBSuJlf9OKGgH4pJay/3MVAeaMkxTJPWU0Gw6r5jgrIGR9pxSKx9f7raxt0eFeGuOgH62
lXj6vKj27SylHCb9ZGvwKVITXME02j6/HgGOwcvsi4g/XnF5vUuGvIVp2aqPeHiWbed22Zh/fd6P
1b3DTp0kebosX5h5OwB6aCg5HfyfcIBvd9/ER6H2P+FRDg+xW+CiY90bN3x7E7I87Sxe3d/ueyHS
FTSIxp+s8wE9Ifn3MVX7Lr1gF/aQZ7IS86G8hxU9926jc+NedbojKswWQvRjskxCZAa8lcNlFpFl
7uv9ILERYi3oL+c5jtwkSUuTLcmHh/WqRSt8l0uF0oaczEatSnxM31/SdCa7iertoKeNvavY4Aij
eWqD/oTXug7JecbRsE4ZGRSy5949oYTqMte1ONKnj2XMQaqYiJ1hx8m7MgEi8mV8zyU+dHwQm154
b42gFpoSCJVEoZt1IhdPI273wNLwXyKq6k/eOHFw51901TePUnXMAdDToSW4Ilj3jx2R7OXqH97D
u3qiR6aGI3Q2/g6Y0SohqmnJ8pAqfYCzwvXDithF8rMRUfkdFy5/yYERs0/qMOtXsN+ui0lnLdDZ
ScYSFEm4eRYA3wyytk8wJsbEbwXxZNa4WU5QGkcsLLpTDrvR7luRwgPZnwphcemPxyjP8FvQrcgb
lqWuxc1xWlrLIu+k9UsOwJm9Q5ezC+xVYsDL4mGclU7ZY/X3Lx5ZVaemBhC5xtSt3IVQB3Edwucj
MDoLLpNQSxSX/ljHMEFKIFBk4WBHusA40YL5HaYRX3mlX6lA1mSQjWPlcBrLqEWCq47a3sQUjJ+x
vfKB9Q+uQ24q7h9zMF4EbYluQq+dwkOApW0x9meEKX5VgNPlyH7wcwhRke9LRjSPHfAogkg3OeFs
ikoRWBUFcRtvj9Iz61cpqV736zmfXSBePj66a3MzSAKPuQYEHV+ZfTQ74rJ1cRj0qG5p3DEGy2ti
vxMevMqa0KIQHpsvNN1oT+V5ApmS8EngmEuSMqyr57axHCf0pDMDDZ2wh44zs3RQNJMlsa/qJh8J
zVtTvyG9CLdtTKee3r8Jmz0ucc9MZcw9Ka0xeckNwRMPwh2ktVwPDyHXpFKW7XeJpx8w/6+CrSaD
LmRIhhRSyOzxgoyOddOjju+RoyG5eDeojC7W3WMDv7pJliX9EkPSLI6aI7zzfT0X5QQ+UXlBVS7d
1h9u1/BqX3S9iUnVRVhLiKUzrq0Q7E7JWQsMjmzRv22h9ELgMDSUEFZ5Comr6FWAoyA0ADCK0P2T
6SA30ohuhbTopDsu9VEGj65ekauD9GRPojE/wEj3PZg/1sGqg1AvWRsovSHw/dhHkn2x4ujJpKhj
weEs2Zm07iycvP1oqtbzJpjEODR8fYBXJwicxg4PQddS5RUpJEbvtPquihTaeCa+JZyTSs7sZuHW
9PtRxyfmzdSbmvHIVKFYqtTka1wVvkUHRT24PZoZTKoA220QRL9Pe0+ymZrfEWnV10NYFtO8mtJN
sgi7QHEn/MLBfrBuzqld6Hxmcg94hbK3SZk4EagYn6hWQuODE0Wysl8pQdtEyAEM2eVlJfrxQsfa
k4i/c5Wflv8+ouDZdAqLHzPZ15sbWqb9B/u5dIkUzLbT98UvsyGvYbajtvYqCpGShDzBAsKhsmOK
ZmJn/TAsFCyumAAlqT/FYz2rRcjmWRAE4a0UkWm/eoCdzNmdwxUh1D+uvhi6Cc2cgrEN5BOF0hXj
xnt0dQKalZgUxtk5cejdMkw7X2w1REgzdePkFcanSNt75heDZ9Ud4PlyCHTdxa3Wd0OwZttuZWrq
aOVkM+9GBtq9lg0UJN4itRKJ/u5nf26CJLKgCyGMqaK28EgljlhOhW73Sqf1nbsbbknnhqsTFkjD
+kdWUN21UFpJZ+4rwlOTeAJpoigLaROFcbb+BADErYD268UmAJbT+ltaFxjFRIgy6vzBZnxXuI16
l989BWyifkV3mXsIR9PFHmknH97rnHnhvRTKAv3gqWmvzCykeTbvSezFTbdm9PrYn8IzOUbb2pxb
usxTiuCZwpMiCE54h+sfhnkAfwrwhHQD+ja8scuxZ27FM8nQwzPXgBf2fTvqNOYlcYhQ1NqazKU+
KXexYKYiOyk1Xrmh8LUL4XSYRnq6IQjz2e6nY7BuHZrszWFTPdgSHg8AeCD2RydFiclNjc/7PqO7
V889Fm4HiimFtMoXcXT5rrkGIl08if+m3C3XU77NsYfCDxL6wJUL7FCF9hEWEEF5EPARZyArDqVC
sPL5cO1dhNQe/fwa1dh7zyp9CWpGBKUFvh/U4slxPxO6fAdZW2iOhyygYGQK+Iq3Up9ff2e3aIDg
7sRqpEBywoudwP6wzmf+Pnqp5A3E59LrUfzZXqI9QVbPSTM6FQM/C537XdflfcjEBfVdp19pERYj
irhuz7qqfY5IruAzo1Td74HvhU5T874S6y9q9dbcCYFxaY7xSUzErQ/ffs2S36ljy3kY0aL9aHNR
fb7ehQF4dDGkKkxdfuYo6G+J0QIu/GvNFMrYNNoR6H7HGNUgQ18db4p7O/pbOQedvxGvAHjb6tn6
SMeMw0bAJP1+VLkobCX+kT1Q6SYgzm0OPlxpbVL2yUdCtN0vU+7dydQuJFtkn49m/ABIQkO1ZxLY
+8SqKo9tAAvdnYAL+LP1cmIzgZ37lOa9Vf2wBW+pR8JexsNQJKfmWjg42yWQmyf1oIhsXkJpuZpz
eLVBykZIVMWFf3oHLYOeP8m8aVEdipPhiVKHHFlY9xtONyDA0Fz858vFoEi1GxRm2ZernVl1QCuC
ojvgIsE2Z+L5kuFQRzFSeFZMvnkzmVEwQP/nBNrQw6ISCWvKfaFi87J0BvyoHT6nne812hVE0s7Z
XC7e123ndZj6eTLUta8JR2Wevwyehk90doemcDuXvQJdijHrehOP9GAH7yHv+XBKuMAafrO12yPE
ZDKU5jth9POXBpFUflXc0LbgNM25+03/Au++wfXkdi3a5K2hCTnDDkWafM1QHv/thGXvoxwKQAx9
q8uNBVZeCGCH9+7Uod5FAKeLDs9z99wfTac09/WZMdRHTfspR/9mXlBVmncOcZ3If2xZug+Y1h0L
tTWwq2mKqPFeQsu4H7+INgr450CwjM41RrJs8B5b+BMN9mPqZmFYirzvyZNfUTvLZXFgfwRvlhl6
k5qMYxJKz9ELTuU2QPn91tpIQAIVOuL1u3g4xs/Mzz7HkTOjHmmdXd83OJv7A83ucNlyFYhlTboY
BH2aVYTDIG9Su8aNeo4096rJCv+ssjn6sfFjk2FcbLFnNtK0Wgbe2E4SyXG0jQ7xJGhyhq608TpD
Pg6ujYu906PUnemLTCImF7Zt4yYgWr/QO7hzYN1U7nm0SkpW5B+eNEFd2TN9FeEU8ZRiZUAa8q21
BWa7nAIW+03rKqSG+UJp1oQUA4a1NmBTi3QnXbXvPsQlWHJ1o29L33L+W1lnjSrPZqemDyIy2+q1
e1EP/07lGkMrmmFl+W1QqX9BklMPymr8ae2SrI+Hk+UmOMYrQVeduhMz1hL2kmgEn9eSwewANAGg
B67hgVLMCgwnFbRttKUuobr6wucF9EHMBbdEE3BKlFs+PD5fWFX/0EEgX1S0CeZ+UcjdEswMlr+V
+pik6ySprYBEsJeALtlDlvAdR6a63dgGt+ohe4dICG0bX3EOtYE6EIoIhqSiRLabAru89pQ+p5LA
U4guNAeHImdWakqe02Tx5sjvFGG1hQxxuerjYl/B55W59K8V6h5KoSeSE6hpF5Cg0u9VGcWpvNyU
IAMwc1j6ffONLSs3hfqOy37nVIIzeadv2gzg8AuecG8mmT8yzVKzhsLwAKmxPW0RfgBT/7/OCRrY
ZI0lVKo2fdFm5ktbhqcSA4H8WvSm6gPCHRVz9mFVfuRHv7fs3SDkDHXV3toUerGGYcDhO2JZcZfk
oS0pjAWdDGh+fGdPs14O7bEjgbqvcxX2XMeQ4Ie2IpKHqIxyfVunQ0Tedqkg5RsJd3tum3SwaHu6
mam6QCEATFxklDsfY5kktLbIZ9UC7xIDQGOfvJiwZh6J9Cdz2UUMrkBb7o06OPtMB8ZT4LlM15SG
dPtRtSYqTvCJO0QkkaOYXd1760b7lR6hAjZG9+6lwGsgTdhHvivUpoRB76iPme8uAEPcPKURodmM
IByetDmnojbb5S3heQba1AV0cmrm86GaSVLhGDr7yKDo2w1mLUKZGOhTYeA27pMnghBneszTOWGK
o2+qtzhVs0qwW/LWIGRP9HMgULar3lWBuDuBbwr4B0SqMzYx+qb0dhVc8VuhAcIRLrwzwj9ytuFG
cAniIq0jYcDveQQaVf7ZP94waFmkh24iKvg7yrE560Bvan64llN/TqhIpaJwUbXrn6VwL9ToDo+l
IMBRIt0ALTeDKchUuJokQkTTqRU019g3EdJTNcXk29LG9Ve1Q/IXHilLxB12rCF2HlAD1e5iyBLj
e53qAiJzXK3biYfy5uyDKzZ4skRlCJkJHSQp8gDQla8TzVGft3/ZP1lKemPt2wXUD8gFb2pmiAzS
c8VAbfVO0wag/iniXZXbGqTXjTWHxteeFaFu5TChiaoYeHQXu8a4wnm9/J/L40pqFPIdnlHUPrMq
lz1sV32Xln1JKLIfWu60LuTDFRLS6AG6EMXi32mHbGmAZs2bS9klowSpeLilCPjOx6XJAWK3oILA
2aIbhc0eep1NGerS9GVrgg/PQxRkPp5dgfzMx2Ufpi6XEl3iXblkqGSR7MM7aVWEqX61hQp639ha
Ne9MAmrHkABx6KwVRPjNxmaNuiL24DUVPvEE6uQqpbxnuY2RLqc1ayH8O8Bmv1DhNWmav55GDNpd
9OSz67VBUzkV0XqlLIyFKclnfjG1AYI2yMvd4FG6DbuvRNJtcUaEZ3buy8TgJ+ArYIiPYeZ4jqfS
tgSMkaFM2phx0KDh2O17O+QprJl4bFwOejkx5cXwq29un/RdvvZayCwZJB8I/3bDnEEuKJ4a1zDY
DBfFdhwF7WZ6csTwHle/inD+u683fvEAhdnXyBft3t5Tk2YqMc9ymrj9wDC0ULD0NckexXHMKuid
Y2wpmPswokA8vItRM7C9WBDbzauwOeLO/0rFhPJBfM/4p5gLORGnfkx83JgBhibyZpoAl88q8qZG
DweVWu2ay8V3lspYPgk6GWLMCkp5hmwzozo/icXwQ60R+TsqSh1YAkZmadoYH8R3uIVqhq1WDft2
LZ6CiLDXRhup48XAeYcpo39Ch7sp1MJ3HV9EJDK1p36vcBOrNNCPuavg2M8vYmE4jOxumxMruWfc
GsB/D5SbPv5nVH8JET2Wbniqeld4i0+1fUpIm/BYj6klHtMBQC6GhAFoCKmTSasJ0pDh4+uw/tnc
Bq8U3dm94SokX7uapCNfBfFQwJ2BpAnGZ2f1+tdwSw8sDaWZ3/SH79Z97VjJfo98oEkhYzO9lCa+
LxHLSmPNEVT/zmm571Gxi98wE9xh/58ZAh8TK/Cz6t/Y7o02j1sf0alEx8tBSCigp/Bdzhn91XYB
XE1QMKAUElDXy5xAwYuxf+Dog20SIXDMv5X515BJOGyHJFZlFgh3JQd7sPSBlF0WxEukeSYsAGZl
ovokybdnZTSzAvrrBfvinPppuRAhkHbxIiK/Rw7e2RGfmPV446Xc8iZfCFG0VnG4pNFDZsTugovk
GyjbL2ENBsuPyFpkSxH9vk/Bg0xNrRasVFYmsisGUM9olWYvg5isDgAd6nPISA8OLLtuhGfOg/Of
jMHPXgENFBbu6Bxn2Od2iqkB51suZcZ2RznurF3tizPxS4/qxC1r1M7Y/+7RAYpS44HtaaglWHRp
tn9pEXyvL1JG1buibyjKDweY0z2pnsoU0xsRr21IuvUpvUlxNfP8UH1w9+G03aB3gzC9X+IxQGza
NMpHcUZdha0J8ryCDdIS3/TPs1wD+KweSVZkxOq4Xy2W+GUdGw0nFudI07ibTMbDxSf7fvseUPz0
AFWQyqwDGjk/ApSUi5q623WMlkK41bbJE0ewy4Z0hWh8WNFBWA6/Dka6Y+inQLXODwvarP5Xljzd
SMJeZ8uprkcSJEr+3nR0GFXEFIJinFJqc2n35iqrxNVGUc51l1RjHS2pKzzHuKVa9w5Bn0rSfyRI
jMq3zkEBaV/UAIOdNEDP48wQ19qJy6VJz0S3RFojeDXiIhfjZwXvk1zdV1bbaj6e09YBOyqMdNYW
4KEry2fjRBl60jH3T21oJPPXYKZIYEvcDDkuKGNerqP5IloQP6GxjVV9gUPMwgkKodnlexBwaagk
mWUMiDrGFcFpk5cb6nYnY4dAV+fM4rvKiXc7UdI9LPrFwH+znw+i1YZgMxlFu3IJsqwByz4ljpWe
b0p3R7YygD0DlBgtXNMYAqwPGonanUEebu1iheaIvRsr5ztaRuC3EBnSdkBwmCFrHvtKP//Tn84A
ECv21mDOUFy/L24WLtekSHb0JyRYjfDsAbjqIN9HF8A0kvFZrn0+YCQmpTIQKKFz4RATGJU7IPxy
xvlOgjBx6tz4Yx1Vc/aPn7LER2TiyKY9EDYn9qgDAMfFFQF03pz+qiiBv77g3iP40kZtl/25r1t4
LVMqJWQvgxjtBjv/RkK9F3y6+reCRGXmqyDdEY5jAbf0Lf7hbsEwF7rkKCMRT3PqEqyvRAskvbzD
f8Tc3qrwZgz5/OU4DKPhnr/VLOu5NF03m/XNpRmUCUdamzwNa2+qGO4mYeNH+okliGzqbx35hiST
ziK5ju92i8nxUYzxdR1qfgKuX0L2uq549nDWQ1Gq+RWGpv4eHb01zLSeP23lTTns5GzCqwihnrXt
cJgggBwDz4NsWWjH70m9oqcZBP5jzA6ddxBPydnlUMRgDQ3KcJQ0w7L4fZUpE9iH5oX60Jov9VnT
SKpIFlw5kGs6rnBiRsA8YGzNIXUWlBZG88xAcYEKAAOpBhVioe2PesKjZzABzfUY1Zn874mPiMgg
gEgEjm2Vs04b2gwf9DC9/YgikZxbvSXHnJI0jn/VfBsp88LH0d4ntZ5kSag+TENtj3aw7Nfw7OJl
QfiKJ7G3cyS47WGZYZfSr5+pQFTsFcXr1RDgZTSc2VBIs1otKovQ0p5kmOjpulm9UDzbZUQRY2hu
jMwUOnwrOuTP4wEXm4NrtujlS1Y2pY5lWXSUWGWVREX0T77HFqhjPnUMq+/SordpJnF9cWf7P0AD
bA1kyUF0Uf/189AYY/hsS3nNq7cwawxR9ghZQ5T2IEKitChhesX+hDVq2Uq8Yp6cstJQtv5oHIz+
/M7Nu9WOglgT13TenIvJneRldfjT9msOoIcUouif/dZW/PeOAyKdFFYQgP7+Krbu2/xE63fKVtWk
VzZdfFhtxMUq7Mhpy1hlwxsKXru6vgp1GNKR8gaXf6C1zm3Wh1cvErT996s6udJgOUb8hFHEsgcM
eNdJeC00tn4cG7A1I4Z/z89w3yi8QGpV0maoHIUvDsABiFfuxHDwPBwoKMes2+6l4p1r2nKLwz1B
73/rzQ2D45wfBTYvMGSvQ6yiBpFlKDfZ0kXBFthldBJ2XlDgBGbvPZBbf3SNGV9z2DnobzoAQwkS
Jb71qomL207tdyLncecUKhkSrQHQE+CkKo/QP9ix3dhfEipcrzkNSUtl1UGLOSwhDQxrXK0OHkEU
6RRxUkHT1SVlbeh1aE6XxfjHscqp1dMlDhfvr36RSRifaheYyE8L1blY7lx5+WG76kWEB0VddWF0
WSgYLc4ZxWMyHfObhL48NF87M2tAheYb+fXFipeXFcBrIyu2ADwOdky2S4mT4ywAhy0EiJWDu4zu
VACMo4JOZZXNTDosB/TCo3g0jamP5yTGtnMoNVaJ/BRz7NS2OTPz6NWfneqbD1mBROCRcfYQvgA1
ZHjYkAYCZRFLgDwVgbKFIJDVYW5mhLuvbMHbe6hMYaRn5vv/D2qT72OIiX0FzY5C9mdCjMeHyCQh
ulQIhTSJ64DM5xfa/t7rDbcXr76CTfWI1o2xyI/LmCcaKnow6y7Oa7ebrhlkWVdM0TtPJu+i3SLR
FBHwxfnRkE+IjY4ebhqtN70mq4wz23zhia5w4nvsppea7ua6AArU6HDyt/cytBPX/CvG9/NI2P+H
J0Hme+zwYHW4ipZwIfdmhF0YeTCW6j9lKq/kJzmXIzIl+4BrxKL9EtmntuAbrFbP/8AjDZTH5qM1
eZgBYjt2J9y5XMjP8N9uLq90H55SzGtr9RCuQmIT/sjZ+9mPEdzXteopn4x9HBTW7db46Mc4NzcO
CpGhj7pQQ9F/1Xiz/1WutpkgSegCQjv83iwYmnAvnIeklD9ta4VeoDqwneQ0FooBdU/slWlM7edX
boY9L3GasPHLEnDp4bGtkCg1gc2LcESghHHCBmNMtwxgXc3+w3aOz5tl8gO3SEI2LK6NyDr0TDh+
Gj+A+u70nq1QZQb69BIIV/lqcoUHTI/SDIa7BuLrjJQtOCcEalsZELKsqlJFrI8yyPeOJyvVCXUQ
7tXxlkT9V4cF15vOvQC24xlwc2mKoLdPnJ8Ip6boWWwd2IFNn30W3i6zqitOiYE0e3r6LV6A5cF0
Wq50aqnMJpZuUw88Ps9Er1MU1dA5mD++fJWhG6HhNVV4pvow+0bcpxNnUnVxu62vgKlctTGmdDud
UE82IdV7w2xFePGk+hZJczy8k6zot1CUpsqmGKNr3yrJ1+H8pQSyAPc1TLZT77X/ZaOMz9PoJEvl
yVRqCej+h5YYAf3ejdIGWapzZ6P5xW1e8LIOzvBsV/pCL41NJs/GY68OpYxeT567rDHINzmiYTFx
GRL86Pnv8pF9YczNX64tLUG3DZAcGfzeKPq9Y8b//YXh7Ie9p1pj+ygTuvgwLTm8c8i8H3jDX7KA
+m4BBopgMGtQdSG/JgJ7yAtR6nrfYOc3Fl9RUr2DXAxJiiyhiZRdGkZ4E2twjUVXpsfEcGpQMjvh
hMhikiGIoEII0ANzURLatr0uUoM8/kj/IR5HcuVnDj2X3nUFxn0u41g1vXB1H70MKLB+5p4tA4Mw
KP9gIo+LF5IVUa6bWf0O0LcG0QA5W1gGG1ZyAYuDMRYikrTGRKll7fBoMbcDvYsWwVZDVqTn1XwE
KX0F63rINjboUSjCfW1dtCapO67kSZ2tqC8YCeQhyw3uxGXKAVQnjXa+vVD3r+edPrFhfhg5emA/
R9hUW/oZi+v4KIRqS8Wn5dEI/772VuNiuuSevUr7fdpn11LhfpA3yLQYnwTjqHZytmo5vYMl3Mca
JG6RsIIE496A06v7cb+SzuPUliEKAjOo9bjA5jsKJx7knLdyR+Uw7VFejKQMbO2/9Xbp70680NCS
6jO26ib9ixUctukngxXp8YkWcIxhe6Vg5bpVl3E+SV1d57dMLXgQ8ni4lc1G/fj52g83ZwDBYITF
BqiGII+Obnu0Rd6MECI3aeWCTTY8zOqXO2kOHaQhHIwVrGWNUpHTKne92imFDrowoIozH4DrriSB
TQVrJVK4AWanrCVBP3j6FvEY3SGfAj6f0SfuE4oP1+MaHX1KP03LMzYPPPkF9vOm48FJrzreyS5d
i1MNI249iMaVWTm5Z/pDDMUEKQm/LI8HDkd5/hVu93WeJPo5dZSU1Q7HLMP107aHu9t0FTAJqCEh
MvHWPzVzLF0sfeRYAtSl8ACXB4VAme0A48g3UEp0ZDIAcvZ+Nv7HSIee2/zX+Ob5TBopW2CviAaW
GCQtvuGv8rg+748LXM72r8FV//OeCHBz6d6y1pw9b1eHkhjMv+mE0AqSB5EK7soZaLHFqmJ17u1J
mSrCmGyV6ZRXntHUihnoEGDqEgdctPRUV4Hkg1CmcNNPySe4DKnIKC9csoTZbz2eQllPnVERtMQj
VhFHz9tXbrBo71ez6V4mE4/MYIbfsz0kfLRV6Cm0Y2W3AazPOAOSSu0qPAsq57F2r62kq0dB/bJP
8K5aWALnTKZQfRBmHpD+scax8PCVeXkeXa6rQt5UArq72n5QjUxhu58tkEIoHejNelsvaSrvr+H6
p3KeQlsneiHxgfSCdVMVfP4DMWkN54VWrBOFu912NYbsXT9dLOfs8uYdsWEN+hXj0nUd1ZGGtqVY
brLEKsSUzrYJ6j8fADgwnCYN9B8AHrlKNSNHbdvpOCXfs+hqvmZL+A8mZTQYPqyil8+siciP9/6X
shPg8Qvwx0hiqP6gIdSlQI1siUN2pAMYIM7dq53bnQ+v8Z1A6IT1XkyqBWrId5JQPOcyECUrmD+v
eFVgZ6IeDLpfTU0Q3T190LroSdtMaKjy7As0BnS6fGsljL5n4G/Oh8QPT+J+WgayuEkICYl6fk2f
d9ZsAX9YvSc+IOBlOwNF8tAaaOYpwmCG0DhyyS1XFHDDo1kCUdSN8sCE1ou/Gr6YYwzoul7pocOE
cZA7b+i0wn7sAZ6Kl+VNzApCrnGxniKeyvvMod71DYobmB5OEKh9K6m6zX504NxltIhD0gRFIC3L
X7Sm+Ip6pk0aEvkwaT07rlP7uvgkTcZ529N28VVHY+ZQMMFn+Nx8zX86MB8T3D5NMLYy01cGPKuq
m06lRmlnaZl8lQ2CuLctgmQP8nmcuS2q1q/Tg/5yXJglbr1yb7cbcdkC35XO9GJ0Jvp/DhCCTHFH
MxIEGt9+gyL+rkUIQ4Z3kJ78LHpQ+1JI0kQrHGNvyeP+sZVN9E1AdSolksLtdJFfQOAQzo3I7IHJ
IzMcXlDWu9PWCZn9iPEmcXNk25EUYVHP6f+rDkAOlwScZFayVpbhmfCkjBGqLLVYV4UTFPwhn8wa
xWdFwGGkWVBL+q+TMRGaNGRH1g+mXuzHpQeFy1maTFRBmBuTSOviWaSXrtzZh32RLraMsRf0BpOY
ViSjFnN3o1jgkc351/3AxdZOkRRA4MBgnozAkq/dohg4C42kPmDRG+troR2NG2T3EeHqYpOv0OsS
4M+g04B5E+29Me0aIs+cTlnF3naELk7UMnXEde8SUKZ+fEWtxEfiA5Ilc4Vs6/3o40S5SGHFIeqW
OKoMuo+6fR5lpQWaTxiUFfH6GGZgKwuwYX3Ys1tQueKGW6pj1u0si2vmLYCQf5NZWLrHTkkFRuAv
mhZcwWd0Yu1pYKK9Q7D6buuF/KHJjgq9L8/jqDTNC2FME2w4Pzo1h7SyF1AUnvcKcgXunt6IE2Pa
A1fGl0Jdf+CPnUhfwXyfQTxiON4InFIaNCs74D0FCuwpWlh2gO+f0a4kC5iCKbup8aNjxu41PiwY
dxKSBAHJhFZKkvt13JIp77BNBrSKfP/KWG6Opfblu+XmTYbqjYo6gAo4qPhXvgdvhlParv6gHgNd
rBZ+UhXBSpxsKLqwyJxA1zc9AjHVbSTv7inPOCdQJGxsT4t4lt2r+kqllkoDHZKoTBMM9ga3j+W7
nGqOSQo3PtRKaVF6EbO3aZrYMnDG1a5RkCkJgNfiJoWdpdGKb2gP0YkyqJ18zSN+0xe7unduoR1D
/sRaRG3ygmQhlTHowLUV2GGg4mxvQn949UjV7k7fSm5yciSU9MU4Ae3ansEtQhnWOh1Zt8DlAx3P
2Xq1JLhkRBIi5KAzzqwPq6B1if5s7Cm5Z5Ha8pYI1I2wxQ6b1VqkH/AOqLACyskFMuCGUMSdGvT5
PbzygkKFpsGvlp+Hz1opRoKO8sO9TQKss0dyxQeYOMuD2hri3lNGg2C5e932Y/cs4Vu5fKlVz8zz
Q5MFVLYSyHnFUWOs4vjuYO064mWJUvFq43ZyvPInnyxuxfk24r0m/DKDzXGrmgqURVYc0BnDA3za
TTkcw0MWrA8C22+fbcr9aWCwJP8D0n9lrzRLEb80Cjw7IEFHu92a/0MaNGcuASTiYQp316dLmtSt
nfoVBF5weheFSGIOL70Xd1TNYdEOG6rYqYt6NfUG5f1sEmfnJtAG1TJEvPF4CPHE1S4r9lQo1wz3
YZRz7pEvZy4Pt5Em27XIcJZX8gOG/BaKz5OmIXdVqm8gUAqy0dQ2SPyXe4ZzomdbBUFz7ELyujO7
oaAnqcAjtsRlCLpR+1+kDbW1igIAmE80mtUx3TutxohYWnK4H8QR70yG9cYq7IHnhZjmt8ROiOmc
FFnyPbiYc4bfNqay2WDLZdjjOK2sm4bsdo8Zpetf3tjtwAwXiuD9F3OV+HluxmSP27t90obxXv9f
omRFvzNTK3jEmeN0HR/feCRGkJTbCKGnnb4vpA7Bn3nSiEbnGNI3nLF5k6zRkVcgsX7jd5+E5vQ3
yXBD0bZtinwJSn6KGke4d6Z4ZoiNoL+jInB6MtjqsvFsEYJtbEz3ekvlWwfdZplv+NfBdnEL3r25
0Yr5mgj7qsj+a8L6TmbqTdK8tHa7t9Pz/9JUN1xjhOQ5Bi0CIiYJtabBk4Hl44ltZS5XW2kI6Z/X
lqFJ0HD1FxUq+XoIHIXUMfuZpu+uA9xUPVHn/sNLLyIXKL/c/V632POKBdqfffy4SEDEjQwyWD5j
6fZG9KMrhZKAHAU5lFvPDkRBjnEjSX1geu5JCi5mp/4qLxoOg4vkW5ZLpcDfozZxGw9S6vCX9L7M
0cPF3nP4LXzn5xBlQ9+R9iQi/AbHaxVEIxgqPK2O33Y52HpOFGVQ/nHuyl8dUv9+Mtwm8KI70k1n
i2bbCk6j6AFlvyxGnXDaCYWpwAzcVvz2nqJLADYFmYtXRaTaTqcbUoS5Uw3zwILVysV4K3+z08v5
aeNJVZcC3KXIhlyK05kP39LDfQ4JsKwHfywUTeqfKwpcD/7lQ55IFb5Ah0s85eB40z5S0kobr50L
B3DFjirH5qG4cmrpcfNIy7H6hNwED/UYt74tXZ64yHOWCiX2Dp4hHqXKaIDBiEvJHvlt99vJEmZB
xsFUg8pSDCHZ6cEft5uocndZmO9HTWrKHuvYuUkmmnw4d79kGu/bRjFFxmD5/cH/Z6u3HHftOAKT
90B4IV6FeSFJtyoD/TwT+X9RaFZk2KMn9qWEyGz3JsoQzgJ884rd+tCJDps9+Nk4VRQkUnaWIZ1I
V/IQ8jHHNm546VdsYIz1PrRt2DEzx+0/Sn3UUwlhD39RTQ/IAc9M7znA9+5tz6cXomG5wgkQv1SD
KUCSd/Db9hnm+C+E57VJboynZezy2Kgb2G2VM91CXgSYM/aXrTPJaqPx6+WGTBB3Ph7ttsNJNONM
iKHSEfhRTjmwSLFi6nTYcMIGiUTD7/1Eoiz5KCUXdVelZZl2vALBjtGYpxtuMS25EWu7shOaP82P
2CdveVm+Wx0tmBl+UKQG/yfk1FNwMQpq2dcK4Tfr3cMjSdKj2YG7zOCwc4pozXWI7lz0TCCRKZXG
/7sD4QI9gSaE1XjNEItyMd6LjpU9PVOCffpkSD2FPQbeNPWoP0lA7FvDlA3TnXa9LEH2+Ml6WofO
ew9zfa98GQvFBUykUr8vAf+35CATo7E3oPsT7y+FAfoaUqvBZ/saTcO4/Do6AxdR8fjGN60Oz94W
TJ3W3C8B/e0DnE9jn2hfXpf67qzfapnztI0V5QbzmuyrEJqkOqwu6gSjGqOezdzXHA7UrUyygwu5
SJ6mrxfeB3hp01Tfa33+WSLl7YqFV6RRWsrS4ug/oWP5mqN6J3niz45HX9HXIkW5Bw7kEwwgYqvs
PdsJITLDj2eOk0mwryPaIJlnlPUBs8jKxPJQuSRbZ5i29Go0ArnkG/86BaBxmlAVCZ1niOkAmT8X
48wLSY6G7O9Yqb6FOoz+b8tS1WdFkx6Oz7pxwLKnelEHwy3AZtKxKqfDuCd5KgGul+3w24+7h5Y6
N+4nesuzCQM2tzdIxCVaTGj3IU7MT6CKBgBbBFl5pC44KxIFXbl9iWpViGmgQnG9J6cNJrSNRWOf
GWziuj7MmYplLEVRr54RKSz5hYhFz8Uig+Hv98GUFYA4ubIf8Sfh1vDzVgj7AfJeJaCrZriwPTgZ
Ga4Mqfk/f22RvjTszpW+pyAtTleV5VagnkQS5S8pepwKuhQKSt7Iv7RwA4rCNDfYZ24evx0z2EtI
63q/Iz1FeFP6i2Z0NlHkuvYixrfKqmgUdWPxN7Cu1xIed1G0cAxrVfiL+wUxS775LC0rybtaP+eN
EihrdGUHmI6w+E08oBEunAUisNuN2jE/XSw8r7BIH4J8JgZGCp/fBQ9vWTe+nI1j92897Cd0b+7I
pj0ksYWLYkFIEHzn1s4IpKrKtwY1tM1W/M/7Rhycy8QyRtIRRo7UpHmSNOovNEbljLCgv1IiR/cO
GP3KZu8LK1fFWWL28LLvVXpTN7KDIC07/Pz1yIEVXTrjaXwinVVBsyjvBOdDek0EPXdbNrbQlIQU
SvJi7Sr/TOD0ARdd62bD9wLWl/foZbrMHQUsUF114MA2qdVT/0Pidysn5vMbzJ1SeovyLwPlCnZE
tx8XkrG9qZ6mm9FG6CjYSuZgHcQijar56TUnA7c0dTsjOSV52bqfAbodsRn0lyk197lPrWsCajXt
ATcfISyxBv0oa/No/YWbF/lj7X+U3QEHZ2LkY5CYXHkP6/mGEahkVWVvyUCXCEYkLtTyC/dVx+lA
cFQo0ItSFBqbFAZY3lMm5/kLxJIJ///v96J/jNijidnrlcu8+SeGKMIxkfCgVTGHyZ4eMETupGGy
6QesywvxnHjJl+A2VQmcCmgH7XHbmNa2GH1jBn/EKs+ONxkGjJg9V082XHodrV+w2y+vFuUKGWIM
efwFsFIbNDUnJRhPbwusEqdrTugXsVYZDLsT9ahXGY35w1W5tx35iPwbjjyqsGhDiexjLt9zegDk
usiRE07SM+VIvWRGKEfBnBK10irUV3D/2QbQ6x/Jr2abDxfvyItcrvgvj7yukDKw7W1V7mw25yZd
cOB0ttqGu+j0V1AAaH6LaGGxD7PTsabR0ZKUzdhLI6Kacgur6nSKDIPdx3Wjfm+bQxaP0Drlrn8P
6bT3dWDdfQp9TabwwUimQNB4jxD9wVJTkOobIbW78r4l7jLqwrrhiAmdGirwMxATlUlkAUPbTrqw
5Ox4fE3k4Dw4+mYJnflsCqJmCSvEfrdO3XswRRQbIauYhWCZ0mtbwSmyVwhed2M8OSLZPVSfAT9O
2+UZUGlJaXWgBxfUJpqFNMEj/9bZ3wHEXLVZfOf5PKobkucGTpefFgDJVaohqv9DmMbDZGwDJb2I
PDsl+m//XMufrvgm9z6ccU83lnh8akFkPrOFNS1lPhJqWUaGqrTPv5bJzKyHGnRg7XiY+mi1V90Z
vOKAsiyYbkokAnxd2MF7aZen/pPGvaF5dHYRnrTCo4qN1p4uz8e20SP7dS2Q5SmgbHaciCbRKIcG
xjSMTCpRI8SVs4lvUjV+lNfzWCjL6AAmgKsvjWVQsJhHjsU0ooPWdkhXq6E2H/cjjPpeaAtWX3OP
SVJrjbOFq9T1aA5wapp/yRnSBGqvi4HufCcU0+I1JmUs1PLqrweabeNZko2ZeV1nCpyn8KF09Jgv
7EbY+9Kn6zaS0Ke6PbxKXiY5xGkh6mpZqIN4t3tfHdAVTmW3oNx5ttR1JpkufbmdUO5g1VLo9dwJ
72KcmxQj9w1v7v0h5ilqNqqTmMZQjODRicRqdOZij63mJqDkZHl5dSrO2IAjuevhZSvHI46k1226
AjuQu8rKRf6oPIS0FhQ4c2l6klVPQ82QImnKLnlZgT+LwJT6v4g+SzLFptnkJgiCrNn5SVrfJjSM
TJZncV7TaE+u8jgwx1LBTf8phVlEyTmUdF60/nfpnqWoV/aoBnIxFUCYOYXsWJ33n8cyH41mi5kV
uHrDBZwuoiLT9zn01O0whaO3LwqaZGC/LiXhin/kKSm/utcCuCy0x84cESkMiE4K6c9STU0SFqqm
XmYLroaBjCdzt13My9UgT47hnnumKvvJPn/oE9cTrh/P+pCR1E3b2Qr6MHUnuhqXKZW7uy0HPEK+
dmbsqM//3qd75rI762k+uTKQrBqgXk7AaKjmSY75vWhfA2FyIOJU8YNyV3p1FrfTwIPAXiPWcgNv
jIVE+rsz7ODpExz4+bS/cf7oz93YT9hbKJpEhTFaTHCPSFMS8RvonXMNfM/WZd5sYUwLyvNTEl44
HIONdo8UyaLeKvYnnG2ni2lpkNbJrilj0+AcurY0PCoYQ+GsUkZfRstz8lJSGiB22WGp3uzj2IoN
Pxng60rgLERg5zw0w+jvQW3KIp8zE9As6s5JZXpAjFstMBscv4D15aKXH4mHJyAmyXQHlB9IljNb
k41iX3+ly77mnU785T5XINrsKT4xjay6l2+SqyNCe/s8lX1ZjXoHSebXonh5p9dNCleQPFZU5ELb
Kjxe/C6mWH1PBeYtX/mZ53sCBM8WlOQ5yAXWJi2oFickWPNDjvH9as48zdj2pQI+7PS/LmbwyDk1
khURYfjEc3jc0ckWYcKiLx3nA31yhslL1RXtu4dIAuqkPL75kOSnZI6oQeLfVGfcxHaOoshKI60p
Hujmq+AXOo4HIfUpA/H7MQccz862e6uZMrqQeggTHJBC8f7GkJRPgD33xLAM/F6xiyCOUYKQaKKZ
anVYdBGKHQKNNxHTEX2UvZBJeaw1XGvyT1udW889as4wA3WAED4RKS6b+VJsVFUMmtgBz/Hfkg/v
VFh4e8byv9RayUb3aJHLTDMgYnyMM+1l4Rf9jiEYA9cf+2trsyDtNPn+I/lq6vvv96/jwlOnytEs
csSSOgsBEseSF78B6WGb1o3zvkj3YqKnBseis1j5WtuAUad9Gs4EHqMt3xUrMTwYZu9u2vRKBXRV
06k4q4LvO2E1MGBVYBvxiu94xtG/2zuO8MYr3BCbiSktqcTHAxKYuF3JUM6mKv+91vJ29W5cW0NT
rAXKpqXn5WFrtazTbw1GHJ0r4rjMIj9Sgat04yWRqYuPV9UAZQArOLgq1egnQlfRUQH2XGQ/K7Dd
u5Wz6b5YFhSdM+AT908VXaasdpyGAEeX3nisp0VEog1VZn+VBjEO3z6MCJS+4q32C4F91ipEkxvh
mBUBgPEBUuYqOG6RcsmjbYWShe7C1xY5qNlqp8Pv6+u7FWEElIe1NnSjFRsHayncavqUFEHKqjvi
GxdzQOzeo7hc43hnOjLoi7gWNBbd4IFVH6k7Xx2sHDG2hJ5aUT5FWPV75CfLBC0gLe+Wo7xGpZaM
+3/sMKs597Ahrh5JdpDwJFlSl5ttSXruqh7siUxJ8p1dhr2HV/ZnAjJsdHl3vHBZ/m6cTlvOuLnI
KbLIdO/0I9dgVLOsr5MnRSDb/SUfhOgU3YAAO+xz64An/LGFYQO+zQUhFbuufd8XgC4NTeRCFDFC
yNBUVt0KOVL5m26ywY/VHiL1M8RZHTYxi2WIwssumJG3ccPOveo8QS2tUsnb8KOPsMrv6erQnzdb
GQkr7B8GKlCJR3uzIiQUc3eImUxjdHM9j6yQ8iaVjfKC6kPHkwcnvnLGDqWPjaOyDzeNMLFgLiWY
18pR67M43lj/ygvqniAX0WhDpJf715nEiCHivg1WkmFrXKtTXVkmR0n9KMz6i8VeLTEtzYFDRHpA
ugj7vy6lG6DPIsEVr40lhng0SL2cfpUXU2EgsNK1bS9B4nR8qXgQY3f1xSFHInzCp249Ld8BLWd4
ybaGtFbXRqlW35KPNFxPvRaD/1+G07e4JYA4J/N2jN9lBPM74nbdG52OMG+OIHLv6LpycdPLRRT8
gUPFk3uaFyqIc6SX+ZbmjSVgBAj/NhMK0JVcjFubOtfab254DWIt8xjXe4wYyBUCLqiluhaTbH0S
Uc6qxON3YE3jae7pTtzqF0vnFyRhFnkQm1A86KEMjNOB50Ylj1V7VIOn+ilvVW6UD5IPvfmdN/aK
N2vxYDoYRTSxGqpVJ9M46YkOao67JFv5d/NF08C3WL+BOOWJp14uLqpjBMJ1h34DyNL+VUrpO+Gu
OmISyarE+IPQmMEqyirR/OhtoyVLLXA6eRtboA8I5ji8F6FfX7fmhvk=
`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd | 19 | 43742 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
L9EbKuxxzV/09pnAb0OGW9DxPQ+o+m/MvX4x5f3JCiR63+KWt2eYB17k+9mGgVY+K1VLxoYz0z6V
YvlDefublw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gJD53XIM6IXGcoGao7b+pChhlJwhGxOuVwSTI1iU+aaEVIG37JelabzUSiGlwgboK2Zv8N9/EzBK
Y9pDSGcMvhlTABOa75VEGmta9QvVzRVMjXtd0b/jrdUkZar600zvkPbB8+QESNshxT7B96klkdIo
XvMdlDR/SEQxmh4Mkpk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
uMh613zg14bfl9MaiMXKdALr5q+gvlBiCCfJpnudkmj/VEzNaqE3gABSgWbIJEk6l3XEblsHwoSZ
2eueijgOoGBjZq9eDXqLeir52M0Z4RoybrJFqX7YgYE+2quggoW8XJjUPK7bExWH1Wd6un6XRwZo
+XQ53VUhkTgctFKNHRr7bEqxJa0qk8dm+fTRKVmCc1Tr5X6rd28yRrr4koH3+liBwEPKquwcMKJL
zK5B0g+bSiHJvGXlQQpKzQNF3+4MebcveUUQPOYG2FAjfRJs1t60dgE73q6y3I1DMI/3MguCuvoX
78TA3nOFRYGLkISVFXDX28xYA0EnciH3BlzGiA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2ADp5V47yVkwRII2+UsRY3zvclviExupZdil2h787eVOjYg5odQlZCOMnldkarIbxDBoj52vjMGc
rG04pAKa/Z3oDUnDkDe8ZMmBI29kynugqgc8aGxYPVKp3KD8EvhnicB6/4Tt66g9A8WsjHtxXLuC
0ImlGHU3T8u48JygeUs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
s5k0DDcwk1Yhkk6mc4rW2ITc+jBCojX0QPFrzARjmvIjcmc9EJT8pAYSdJK1ykoSIGmT8u4U6vaF
5pchZ1NWV4+0T78Lu7ir0M6lHPYDFRgXZTR6CNdPGqAe+Si56W7NnXEM0Yylf/w4tAQ0u+05yvCg
wK+mPCq/91Em5ZiPcvKOHOdJBSTTkSYC7/n0QNniR1mBmd7+dgsFr5yshClYY/q8HngDDE/aNYfx
P9AT4ECjL+OzARXCnbTA6RjbHEjVx1ewIc83WIXkwbZjUYAzp9rYNjFdx68zjq8U1XW92RXAEXCc
AYKv676uVGq/WAryucxGApaihL/izu2+HGUsYA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30640)
`protect data_block
TGoYSUtq9QXorwtXYAiku5PRRrofa1QO0tKP2kJaj3QuzD8XFFlvgmBxexyLYDE6gDfD3y1MimNL
y+GFR4k8uGqsTU4X/c+yG7qWrgec1Z/r4nV+jBcL0IflUtTCMpq+DQitly34B3lyEm+/ewhdWbag
sQU92u1xDPqyW4Fay+CZNGjpJEW6bQ6IDAJc7vACSdWHqRQ6Wrr7OvEkDQEjVx6I5FstZJSKRDyM
kkrVQ7wugbCgqedvuZCna1k8+ZH7dyRcyOIbqwtOUx3+ole5A/bpTq1405Z8HHOPnnLBzuvKN/i2
h3Ik0stJQYc41NspCzWtUqxX9Bi28wMdEtl98p6niJJJspPsNRs/+hdLPK8mB93Edi4KWJ/uhRqS
yxZFf7LkvVi+N1jLa10d3keQqXfEUiWSaCDXPOWY79DklbnODKMFO7yWaBJejaztQDzeKsm65LPQ
Y91glKNdw1T9F6Q0eGTfDji1Oh6STnGcLF7Q4+ft6I3sAcFoa+GYAMcQrxcbYV6gPRP/sHvDS/U3
x/6yx4C33M5MP2lMb77YET1MfVMdENnCd+z/ngchRAtQtgE9fg5naOmX5BLqRMHmsj5DVEciFiRM
9Q2PPHT1Qjue1AjcxPnr77595F06MYAipT3yiyNQUYDWEWMMvCiA0DFt+QLyVZD3/1MNiyEQf3FH
Zr907KKaoTMl1xF4Yv18UQDSznABhvA96BcMNpT1h5esJcK7ItvTbfgEWeyOA5V5Yz8+tR8sci7C
pNVbCNrqiJGQqZeZ1EH/K24sMAXcLfjDa3GM1U2aNCNu22TYqw/XKixHntS2NQpSiwdvOmenWtbw
GivCdLZtIXa4ljb4VUy91tWUSdz8zAt2PbUiCBtSRd039hzHSdmTaFIewFsALp6CMFqAmkz50reA
XmQf5KrBDyqp5TYB41NCgltZKr2YxvAdTkIRfsZROAbF0gSraAulVoNdx4iHJRjXJtp4jDe5/P4A
ImbYhhVcSMmqZW5yilWcRLwAH7RsCrGoQt7Rnf5PK4FCKZ/HB91QUxs5jYlwy2C0brNaw3D6r0u/
aPjaIjX5UYhLBF+qrrxRiXnv/OR5LZGSUkwXKvfrj6kAae1s/up3gtdS0L7SZDcBWmvCps+zxhie
URaAurKOkd5D9miHbmFaJwnF8D28dFPSHcUH6O99UiuNgDbNHJ3QAZanYKOWRTa4sILwaHcGaAhO
4J1kYV58zGQJvk0EtxO7wqeP0ldw2qJIfrLOyT57CVvHU1yZeVx5YGakuNvFZSJ+JRtLWT/IuzK5
/k9qNfBfWVu8IoE9VS8TS5kH+s8Hjg5+Qyvvdj56/ZqN5C9R2BdDFONDEhVNPzv9OYQ9bZjPcLGm
7X+s7R/QMCX7MAgFk/KGsYmuNUrNdkfoZojYQa6jX503LHuaAzL5h4qUGHnbMKfqZN6QQNlwlpoa
NKz1kMyED3ybDh4pLlVxvj+WUM03tEEpjZA8UInhTtsQW2AO6/cAXDmA+05f/P8BZ/v2zdyJySVF
lqWiFxf6z/onF0Syr7rENw2MqlwysBHeRhhmtblDQqlzmdAQIiCmVVF90KuXeJcwx01ae7RwPOsi
6DTfuUDOYh2EakpUfAUqKekEUX4SrhSHXGEiUy198AvUQyTz0eOsf3WHYKH/yjasn/4n93pQ8xAz
Vl6qLyqCl1MGp4seT8wPilsm2U4MFNIPX4NWd84AYv2QtqLwfpRPK7UVStfosKqBNDfk0lOJ5OB4
FgfH5tIlwSnqlJUri1nCu428r2/9+Z4Wa3VttRm0szGwD7FSTcR2UIpJ8XxNz+SErXlg19nXWK4A
4P/Ga83z3IcITvwrGdoipK6FnLwOr4YJqyVFMYdzeTBbgnkIOcGDbhH4P+myKi9UM+e1tLA3Evxh
KAcFsV2qWFHtrwySV6c4Gf66w3IGbGXe4kiahq3XXSrBzR4MnYzEvCcPWuczjwbB013/QiXFxy5w
cTa2TWgJdieJaP1pHEqGF0Mf6npoWD00lz31JWqDpIJk8yEPB0wfkerXQmbSOVsgjbAJOqGqfbUP
hxBu8VBTRZ1T5QzCTgSJhSqhopqqowHl3IkRiZ7F2svu8sFjMbHaQvs4VNofyULsCe8G8i8Rze1R
YDtncIsDgERqpZKI/feDLTI2rp/Jo6JQ5bviikRxE2nWKFevLgQSwDD0wvB9eTBhsFe9dHP0lyjE
4ixjvHSZc9EygzYAFrZdkR6AgUF183PVKe2SHNbz1VdJ9HGcux04kk0j+Exib6rj00guXOB3bA8q
ZLg8Rh1aX0K96GB+F/jWPWP6n1vCrcD8PI1GwFXOixPr30aP8LQMWE9Ugyfz+Wvenr3bjF0lUlGQ
JMjzf3OotTF2mxJoTnOSEf/iL53/gD97k4HKqRniMrqcqmJ6KVmttoetm3VopYOaT1TNbpn3Plpl
vaViAQI6dNtQkJO27IF3bi/zJamZ7Y70OeP6VE6+mar3UiiU0kdO2sHDMiK9awHiZnq2PeaEtBiN
55KnxvUnN+p8SyagTY1YeImKTk2Tg5DXDGrpBshLvT9rBFNWwVE5UGLBfV0s2FbgxSZbdqJEyXr3
jWmYBeOD1s+inLRYM2wm1WmGsuqeOZqve1le/8Gzr5fqRhHkVFLqELxEnfnvdGKLP+wle1KSyslW
mVylpNhvgzE0utV6ceJk/yYDtcJXn9YBAfWhnQInYbAORTgcEDkWBC8jr8NSM5+3jpANsWDBZ/yR
gT78qJCAuvNvbLDCEbsmQGFg1518J+2glNpcE8RklqB6svX24Cz2uclo3n/bXyDFASgfSLEkzJvB
9oY5rca8NlYzoAYy9DdlrQ6Vu3GWRAmhf+QsP2HHp4QVL4KBH16YEeycvdYVpy8+AWKZUEOCQDRc
ge0knitBMwnOTbAqwuyEY+gfmaGQ+sRWeW5mm4M6br5HIfz/PHjS9IOnywHOkLHkPnH/jKVnv4dm
sA1HodHPqK3Aj3jl+SPoyGLK7jpwlbKrUvIylrctEx/Fh1idtsjX/OH0jyztyzNW26O46MqwABzY
SYsPvVkeLWEMgGlmyOztG+zxCwuQ1yBL+gzn5qqH4Umai0MooYuwfbgWaekV+zngNUSxfjnjdALl
M871nLkSg1IeDMJ7+oOpWofT3zh5kE2avJInti9kCY0Qy977RfsqUliyAmMy334n2R/ApIVS991w
HuAR1BHV70/d4BJuQi/Le6jbC53YfIa7smiPYqmh5L4l3eVcsuhTUlrXu/FCM+tddtGtqAgjTbDH
95+ajvLbGshRUxAqnfLyd5t6EplRzI9eScZ5Qf37tmPWl+RhKhz/TduXvOGYdZlP3dI6jZ3LrQ5y
yOaAMB1tATpHTrROY8UR+Fd154NjDfwjLNpnuSfMc/zk/1WLVjIDgMY6OAY3TCD0xi0auWNBoeD7
h5tdUf7Xa4cuIGwgwMtKh9T0s0Jy9WBtRTcOMfq0nbJ+9tgd+zPUp469pmYqFeyJIIgFr4k53E5T
CPAeWCu5dBGcXFJesqqidpxzdyQlpm8dD7T8gs1+mrEAm/xcemVe1ATdTFwNxKh+6O5yso2dTFOR
fKPaUdN5LdKJZbiXLnvJ0/lHkkDsxNIj9F2uHuKUfbX+Pe7GdPJtI9mkc/Mb0VLogkoXvUfs5T41
yi7yRnXyAtT6HA1X+8sTCmRxuUUPIg+sNXqET8hWH9NQfVEXbNpSbCtqJghJsQoErl2UeDmT8buo
mSZHpwlbp3CSZmq8f8mfEramnP/Y2NxlpPKz75gqcnqx55eDzA5IblKd2UAw8J+wW5/lNi/X+pm+
RjrK2oE66sU2MlF/oZfWVImW/BFWOj7BAz3cE1yXawUzh48T2zbcRbZAoe3T8teaBIh5HlEEWIZr
aK92PgDTI0Gso4a9JxEUGwiIaRKgyjgV4L4saDQpoeczI0n9kpXlSOpaiekyTSeevk+Ac05wxyb2
oM39FNwn8WmOnpjAS4J8SIUm87TOotKSH6gCy+ohBeavPcxsQxIH7j/9nAyxzCQlGxYtF7Q4xeri
KHCfRs3ryIkGnTmg1saA2HurhpCvHCUJshFbFHlET6mGs4OqBu2fnvYvrF9kAf9c4fPzd6ZiThZw
8Y4wqAtEvQNNcHVn0FNZ6Eb+EFrQRHMVHOv3LonoGbog9D5J8KGXPJZ+Md3hyrCCCZ1Git4sXxii
L/N2NTr256VJFqjqj3VrrewhH9vZR9UAgmjoKp9Jz+NliHpAvNenmkgQkrlY4nEMwv5B1kx/wtVY
yqJ/o7lFG+F4BxBlDnFkqAHeAV0GA7vYqaK2Uv4Te8nbe5p/Foehu/Klp9rVo9+sszy3ru3w90nw
kxKeUY9jp9OknHi8i60fnRsn9IWNn3j9F/MTinR5cNgQjwugr0XUv6Ec3viOS0mn7VW8qb8aCSjN
lQGpux65BrnQ6lYVVR5/p5B7WsEcjkcwwZkHmDgS8Im+AGsjCm5JcFNJBbJBiVfBZ2LnwdCI8G7m
vNXdMfqK+6/dpVATWgCaEZZj2pOQaUAlhDUKJOM2SjnGL1sgTwZ9BzYDlvT8k4rQKkQPN/igN0oU
71JUm2SG5IIHfd7/LK0po9zS+Nr6uw1Jt0GZJSn3+8v4mlPjytuyd43MkgOj3tcsGJR/k5SMqLUp
tNJ5Nf+Y1QJDonBnL+YWKnUJkqb/rUq3kv8CZce6KN/Ci9qYfcxlich557zc4O98XiBPOcNdOzGh
JoUKhV2rT05NfrJRGt/pNibySgGKkYSZBDMva5eTI3L6DUhhXtg7FZh8Vp14KsCe+IC5iuvmcvTD
6c+IdCQfAMiPidWrErtl90RX81o5W+zqXBdfmzLpWi/aVF5gHUF0mlGdUKvjjagQaFcsaPmAyEbt
lJHrKShj05cr3YYjCll+0m3Vj+jbwWdEUuplOb20HYExLwJJo4QwEP2omT+wu0rd4/7yHOjKVF34
WtBc3K4ahYh6dayIcJwic6aBgjFWbFYzaIwQUq/jiX+DF7AZHlMVatOiKDJ6pMhsEMwR9vCUdVSv
6y3o8DC1PthJm7io+7bJD+H7ubiHyLs+3+fyX2Rl3GkLtjVYBw+opCs+BjBWJxxormB4i3KatRHK
dXurWsq7g4ixaHZe1fEuWDKQEAy6A1qNFIHO4MN28ZltrhzAdZ2FFWU8KxQJgSdFPsC375yz70iW
FR87V8uAWnXkeqolZ+4lb9E4mBihCm1Eypqdq4pUK9E0HMvqbf/+kCZNgkq27NEx75aR4ISwB1iR
yXX3Puyu2y0w/PzeY70DQgF7mBLMxsHAI8I/3eCor8GEBVvGL+qe057ZeT4+bfG5138ImAbgel+g
q83E4TMUtNmVQbtrATA0TDmKCi5pkhfqvsOlnNVzCBlOfC9Xj2JVRyyR/hSMKtQonEXOEmHRpGRB
w7KNStcdz6wdDh+8xITFUssnAeqnkAheJxAMLlJuqQCTTlyG49WhjXjBhRopPSrKRz6067ky5ZBH
AGajA6YTodjNNrB5ucOp4jtpzMSm7LvL0IeUeZnHnbIKNO2XjU0gsGPV8mghzjQZTsZ1HsN3L5uj
y29CxsiRb/pmmnUA+RX51e9uiItoTngPJSn5cMqvkYOCWUC729xmUqB5D4ssHZXCQhUVkkVxRvTv
ivbXATJpUmfYoAubq+HwKx2F9O21Ky2kmt4nOD/8EApeVTkEgchE/p1YLT/T38NlDSsEzaKYQeCW
iUL0zSFgLseNbQBUwJE/B8sH9LAEC1pO3Xa3psCF5oROyIWrffkJcE+G0iAhMJnzFhxQPdKE35T1
HTPIDoO/Kiz/qKIlLWLFccGieF10JudKFl1/aFGrPGy//4h4SR4KUt1nWFy1lkVLB5mIUtVtHdne
ki+gE3/kgRz86YqfptvlLLvOeXs18aQB6w0TZYarvYuphCUcRBlVVZXHUQiCuGPhvmXDF552gpRs
nFs26+qNYYsK5vPYTOXC32bOpf2ZFGserZtB5EdzMhKJUXSFwll/RiApitHu60VUlAm7PofH5HW9
QxHS02wKVU0AbJ1hvQVPpaTlF++DgP7vFGNzb9cWjOBStSpxCWcRE3AHCiAcn+9yKR5tdDapYss5
sIuCBbrI4LkdJzgJeLb5FcCl31jbXfRJfLK/w6i/kunqsBvz5iZMB1O2RIlzhcn+ch80aazjR3wb
COEpkhUiAe79zTb74s/NB2oO1JMnduKe4FUa+UHRI2yKqHRZE3odWWxc19axUVi9lkwK+JGb8YfG
sYvM72lP4wKdMpGLkcQ5ViIW2a2TVbxWYd/CUKLDcV7g23+I1sP9G+AkwpbjZfSKUrlXryJ0ddLB
hjGo556eBsFegvE7k9Mbz7rAahlkYVHWQYbdUXaonO50ExdPsQAGFWiP9Odnsso0Vh7RNffmj6Hj
paXR+XuBM8fPNv9BjbIk4ZERi/ZQALCP1TWmet0v7Wp+Gbze8ZAbByfCSenbSsq4L3tl4Fkuewvd
hUrXrO+9n4kGNcwcAvJEZ63oEMI/7h7ZiZ0b+PO7UoUIqEGuPlT6/5ojvqBqvhqZZ9n3dr/+XlMH
UIy8N0tp0K2WHTo9QwOLQxZaJReaRov6ElmjTP+19vKtL+fQYUbf7x04j24/iz0E3Bh63Jz80oMw
7O/YhnzfM337k8bfzNwWcSFYpQmYm6xn1JIFCihbpCSWFQNDHxF6bNPx79HxhP6i9OXq2bvJn/im
CA2GUXnLWb2WVMMUH2msUAm9EvbrDkxgR4Wy65ivIj3hpC4EdiRZywKyDi4z43xiO2+YxSZsRvo4
M0nj5huxPJVYI5yu94LGNs5xiNB7LyT5VI5m+mazs702nmBJg6Zs0wIB4Zh7z+etFd5P+P1405cV
N98TBmYpyz0+E8BkzT4j0AqqJmi7v6yqL2VosECHytAmsGtXYps4xH/y0LvSDApXc3X1J2RhAcHy
ynkVfHBV2d2wn0l9ky2JwboSOZghQd4peAUUwsoK+54WI5qrCU8oYUmjNAIszJlPVtrzunTodBTr
Dmw8xG/BP/evShahEtryAKqs9FN42drmAT32gnY1y4i4RxVveazgELV++vSQqdqXJ7UXRKq49pqw
U0T0fgnsy2FPv+/acDaLHLQ0YU0LMmprZhxmjcuwkbDhMg/r6zVv5i2VWxvTpJpFnmUytm6cCLJV
ZVaBRLsIL7JhWMunQwjRm4hX0PZ6yotYm1OYCFnDWLUurL289yFYQ8J4xa/UKsTJSl6ljRxIFivb
1yBYsLzfwO6eVyyYIBWRqNRcMjPtMeRHlBVRQo8443UNdQc1Ybql3QjPEP1/9rt5PnFaEktZwOCS
pMQCHKGxQj+RlzOndc4l4KB6Q8bazUZcNGWkrLf9aMpIUqJuLWGrgoILroiMowoi4NmFAqal2JIr
T+GYRKn27xcF6pEAz2bNuB7itWcae8eGEtNFOAVs9Yg+bqVLDXt/0Gn/H7Hl2CRJZbtbvhF7QK7d
AcK7fHAnWZDPFUMjUYcTJTKmT7Bxg9DQB3gmdDrm6EvJ7ERI8xamYq7uZzi2xe6zXNtaZe0gRwsk
kDGPxOel/8qh/59FPOn6i/a/Q2KdMI40pCg6Ms/xoL1XkYjo6b/6ADyiAmuaLC/8qvNg7lyZRCLo
lOxw8Yh3DErNmWop0jmoSHgz7GrozlmiDpHxHtdYK1xLhGMQc52A7CLyy+cZGFneBTj/fO13doZ8
mfu7D+KQqxWLuKVCNRppCAAqL3zziPujlLijRE6X3QyA0wX907m9/HUhNJVg5TIv5njZGAueHxFq
8dad1eK171B8Jj88+ROAme0jWs9jlSgplbU4AEU/dfylM1xQrlWyfNOtzrgFeeOyJ2oOmMFgFl1L
5lLnZfB7ww9KbXh0+g/eojwEuhcem8J8AMDl5151xwNJJXOYhPmrUbJGD/tkN8dcsY/5CnQJmBPt
Z+IS/Z0O2OXovOnAgxTpeOHI43l3l/Lb71Y5Jni5E3egmkW+Ja6ZuqyRMx0R0DZ92EjyPPyVMyHR
NYWkB+lDHt+6mkUidgYxxt9RHAf0uwhH2zNT3A8JGJQI8CZM76c2cBFkLgBsiIfKdh9djuF72GMc
rxmJFspzTlT/Cb4fKUW5HxGqYUWK6sCnI1hQNBDxtQNG9CLzeXaclw7+EZffOAxofg1+uJrhpfRD
wMSfZJkCV8xh2rG7CCRzEjPgwV6wK88qlCm8Sdt+/ZPnsvmfA9w8e4JEB6pl5wyOcZFiiBKWr3eu
jkGFrhOnwZHxs6k50xAl7dGp0gYRcgV8uP0qHQbm22bOHnu1ohbvMHWbjFg9+yIzYoygQlEvL5n/
Ouojl00kgURmTqKgxQLduDaYHsgDu/jj/RZ+EtwWauZoBxeRrcueOISw6XQPBzrVl0xqEK36Og4q
gg4LbG4UMs2kgseKE9tVorAg/eCO/LsU/CXZcgoEFQRrAxA3G4NpacywrkWdzp4r6FZ3kZQxN266
NXzDh1JkVhIp9HW3b8wwG89x4FmOOVkZXxUeANzyw4pPlQMuBjHYPb+Sg7hAJdA/MJpb9koOlg+5
nAB5YELjVC8HEZuCKI9k5xhLAFqxhnndL59xifMkEWc9pwAMuz21KQA4Dt79DvedYRY4xV5sM9Bl
pe9iI1Vfrt4/yMkvLoCpIARN8MpEGf2OZQlsieGy/h05kmRF/18+Ozxll9sN1fTX5FDKd/HvExTi
4ed3QLkIyEBiXCvq3rlFdR1lsU1/u8z9PhZWHgrnPlOcavoDLTSpI7wEKIitRVTMYT4kW1I1M22Y
XKWMciYGomrKsS9z8Vcwe6jOE82ho5sdlDjElJLfhKc/QF3bCBOXgOFl4nUBb7zxbYZ9M5tzZPaT
rHVKJYGt3GxEHSyN0jcTWzeP/q5M2KgdUXcCAp122YZEMDx/DtKMw4ehNJSPeOnvQFRe+97JRcCS
jnn6DWL8wYKJsg8LfhlzOTSFEUUI1ysT3wJdFa73E0vFbIZrIj9juKKttE1ldywfqJU5+yiGT2nF
y5N6iIRw9vYJIoPte6mHvWlu7Sf84gtco3s2IZdE8YxUHAhfA6kMZh7sEgtxhFiWgdb4zPU43rFj
NAuw67zVorjuL4Z2h0lOXyHKgWokn8ZYpHB9kCUhST9sm9kQiJffrWEFcLnjBGU8aZoivQxWiuwc
tkHfLUFQoXSdc7yBB9us+EDxCtgmyEPy0AU0r337rTQwCXN0n0N1fpAbA2fYnIe5fmQmE2OSXQ8k
QJrxJ3ju0TI3UEEY7RobS25NMAT8ts25YiaozvA8GOh4CStLwnJdAuAfEpAcppv9LoyTon231VGU
H3mmldGPcN0iHzitwcmBYeADiBksPN1YD4vItVG/rZGdf9J0aaY7PykOZ7IrjelWfm+r2GKuJ8yW
pIn/QrvyBeX5A34FBr/DfyxhzQfG8yHKu0mR2XmTJSLqeMIpEcwBayiMsbg3ndfRaaO3MCq20RY4
NVKAgRnV1O+OtUGJJYhUB7BBm3b7SNXjFAaUzb9KDOwVV5B4NDNLEimPxWMTadBnT2VxPrSUhOY7
ezjSELppxST1Okxzh1rDnWslq2J2UziZT24brOqnsKUDNTHIH4W3wRBa2pcGd95R+hz/Ev1Ig+Fx
Vi7nNCJlgGSUCpVrwXAQUzdFEk9YqM+5/kgp55D01+3kRj0sPzv3b+MgPG4Jo4bzJJW9vFXi4Ww8
r8sIayL840HWII1kuN6p5p5MPzZ6TaeZP9Gv0LxSD3lUUutJiJbbUa9aSk5HRb75dTPE8n3gkuxf
ilXqzkLngGDlB4zuOZXylr+VYLB0rh+8i2S30RgMHyd0VGTWbOj5eptQI7gcyI5oY79km2lp0vAJ
u39R2kYooC1gnR26OWa7IR13vVnYt/CHh1B0sjLvmOEbrrCzSr8UQSMoBW5JeeyCifs54vyBfa08
LCiEnU5+5h4S0ljethY8Dl/Ri6vb8oSyMSYCZjnZCYaTekqzldN6lY9/3//9Yr0PAhY8xXnGSqx+
1RfUiHjYVQXuQou1+HC09cykPSkQy+QKAkTaEhBnpZhpAgoGc8SqhreANoWJ2mb8cSe7yo7jS5wf
4ZbqNgS6fCp0qNNi4lf9PIO3QqNHgnZqvKRd1uPErCsBPNdxHhb1Dlg8EvwVq0Nn5xEqIQ/ut1/D
4SpjYdHBmDW24JLtD98uo08D5Et6eyuloy4INoP3t4IgTbZcCO6iqqCiQ3g9cjvt2KYdCg0xX859
ZZa1dXTool2QrYYujfnUMHsnPsioTQLh9dQySy0xpj2fqKpGWl1Zzj/InZbuBVsHsRGHQqAufQuL
Mp3K4JsArcoqZ6i8P81eNW9Yqsu9wRYGQ0VwkwaMqP+fdTFYGxoemmu55WleUA3kwKmv34Svqu1r
AB36TYk312qJL+1U5P6IUyVh/65AFAjMJSSJKrF+cLNtYhU7ohjjn7E/Yo5ae8UvWwbneC4LaJ9t
eNOPOjKIeIrHPVUCJP54LMkDDrPI8xEyqSCDKM4jtHUn4XzjT7HLYfUj6gMtkrcCknnn7XPiEbbr
XtC3Q/jeTz0teyw0vXsDPYyVUPpt8KujbQ5qHCcyFt0xN22OEs0b0w7trMs7Zo/doEc8w5JWXjig
QDCwI4zN9juOmnNopDvpoXlcFcEdJpiuzo4gE17QpcYrmeGvRx/SZPqJ1nsEl9wTQZKARML2w9pu
uPnjd5II+uCx1SVb9II4q4PhlDV6LZ281x4w8iz+tPr8YfSubg2KprUU06SL91kNa/vOyPN7p4SJ
e+ScRT3e5FCfHlspx5WqGt5r6ucybMetQTksX4lpYkJhDA726KfPqH2QEjpZo75L7DZcf53HJXQq
ahg++BnFxEp+MOMDeTiM3H/AnC/gojFYf+NRiz8pZl/6e8IONF67hZjSGHXYM9XLP40BOMn7Rv7L
jXMZgDpv6smKVKlsjZTXvpCEaREWl3uhYN3/+NjBCtmAfFbuQuVsUW+lwROm3GBoAwEX8DZ4HPBm
iZRA42zUG0KsaDA1U1Gf7+JrkBflXiCcZWrlK9cid20cUKb79uZ+NPzjQOlUnRivOUlZGOum69mw
o9bVM/17o87hkNd+5D6o36gC30lIXDdt1uwCjGlw6agsdtPHCTIBG4SfqIl+M8hzKY/2JKIjeNoN
xBsbHpsVXBlV6ZijBEuDIhWpgYFiBCtVtXxNRMtOfuAxA5u6ia0wF/uGAndAsLVovEYrrQKNWSkH
V8lbtB/JzLrOGM/Vc1v5KZUzjoVsS8qTLymVGrZyytAH3y+O6YuGqj4l21EQpZnn8cDPlNgukmki
f98x62qzg4qPatKEnBU3OpY7vNS5HzXgYDqtJKem5lwQ1jHlyypq1q7oy/mwrbIE7yLpxI5qbb+l
KWOB+gKrPpL8HXBKQpMavvby+136p04XrjGGVSsiIh/VSi60L45bhLy6pijXXGyefhZR2+sT/J6K
2rbb4I3iqLATPm97J9+TdinJSaLmJEMyFjdD2dOPqxeFdz9m3UFzYyfstjBa8mDdxGENP0YI0V8m
xzEaXmgJQr0YPgUqssMYRlkEyJm4U61oEXuNyro/J3G3BC0PuyQv5fwlC5v3zuFMyLrJJi1B8fXs
/2++SD958Sk0xGLC/G+I/PrYspRT7wqdTNfj8U6C2ondc4hRvJnAnqIiW5bMnE5k39T8ibObDbxv
k/8oPvAQtAyuewFciqi0NAtEVgPaRdZ+ejZ91z1D1N70t4C1n7TtuMQiuBqwoQc3/xZur19LuFUG
uXeYDohsKjS0Oawr5mIABa8OamOrJjnvCn0p9clnnon15s16HKG67V7rYYvnRbmQLVY9yWMAzwKj
FOTdfQi0Vbkkapb4dHXYdt/H/UtJGj4EQtRfKAzl+wxbWAOhV0+8r3xWwZjPmR5OzGUQRPX7roJs
Q2owRlXJt01eZh8dbEteaWpA5TnBKQdT+7nJrPUgAYcEQAxM2h2prfbpwv0VIHNa1UMqFfG/P6vW
OJmL6eUKwDw5DAUlFWFTfJpJ6zckzPi1cONRWkMKr9YcH1lcA4OHQZ7MB4e9V8qVlhWwexOTj2co
ZJimIBQMkHzORpDxRBhN4IaxVmcGfDZMB0haB8rblnxIKtGFAlxOk269nI4slWvhyR1R8WFWVTUP
GVRfak2z5/8mX6nd9c8gp19duYndNobRCPcIR//NT85mvfYYD8HljwzmPXsnNIFHOzQ+a1fg62lT
vaRcO6OwWnSw+zK9EBijvJsUaSvFv2/oaI1nYJE9eNVBhy3u3Bor7lvzeupqd/nBVhx65ueILiEZ
kf2DE5qX7zIxx4N1xnAJyndThHAGHQKq3uKNEA9ao11fxjJse4sJN29e4rpe60WQv4wmIZcDkv9R
2yzgQDIhZWYE/3GWDpeUUZNVO45LHrqnip/wuGWZuXntFnfZE3UwRJoSQxLyYQ6IiAokH62cFtrL
cOL3exG7yC3xMbAt3C+IyOSHrkajhC6xIumC1y/RYgB3ydhy83Zs3pn4YVruhwvxsOtX6NL5Hg0/
LVXnOeuLxlO0CK1X8iTQaF9E48zrUPuCWUuuNg/aPnPLTPC9eZ7xKcvp4kFG4YmYNevPTjcL80Ve
Gzox0jXIXx6YhiELET3hG7EmxJ3Q9UBpqDpwF0BXexmRjt5IWchDImS/c0cmOr2nfAwUvbOygUfn
Jq9jDhpeC+r/Wi1W3adCvAKhFeIa8ZrIpfJ/SLSnmhWrr6BnNmOuqtQIZcUM1OXb7sbOIuRjgs0l
lV4p4HHklWug74CWRUmgrEJBlLm3FswkqpjyIWbGhQlq3fWIAWvhcEWo7y1CPZxhqV4TEYBYVrSN
UApeqNnAW6aJvlgAIbQZjvOC6cU49vGdlooE1ujBphGQtZDcSEa7X/ysKa71PAktVxBrObI7uqD1
+g2NuL6pxbuuNmVaIwy9Gmswdp7Gc20EdLvZd+agwDoLcG1ASC6A/7+3QpnonfnNHy1oQTca3qA3
rEyq+4mepyZjJXFNVhi7/p6yxY8T1Rh7nTz+5T++NF8zJ420Jgk3R40I6A6072fG7aPZZAQpvwWp
PrKv2F32zx9KLKd/+a043rUVCmPIeVZgLj6bMiX/FPOGQ7TNFfrNv/iMviEuvZNQ3qlIiOj9JR/F
WvA9MywpBKq8J1evhzjm1hBNEZIGgyfMxbO9tuEg03nt6gw7aU0Svd2WvQ3nybAtueUTUPvoJ4cX
2j4SaiWtcuKo/9zNr7eTndT/1r+j8f6xDJMU9XvYDgY0a4YL2xnsky8SZbrsilbvU1fruKroDpKu
k4wJE0oY74OIjfIgHcHJphJPZvhnI+4NS5uKo6yaMjG3TI2cjngS0ePLsZMI+OPDcgwYHHYzs1Vj
pXgLKVZTuVRIpQlrK/a/tMJkHOvfKpXDBMuhuxfG9Fvai9+mxMjjMyC3A6vyk2B6zRSswRsAGV4+
olznfpclD/lbOv2HSLBrjePUegwabQh1PrZMc6KYWYfnUVarLBulT58wmFUEo3NqrB/zygGaKY2O
F47hFdfurcjy6XgL8RYus+ZNW704cKwhQCw3D1wDLHCbALNgVMg+C+bR15oAdOrlZwzRMRZv9Jg3
YuzsvwAP0Rrq4X/XWKq6qTWzcUxH59+zsizBMnItQt/9tXPYO6iw/umiB/xdrXkRbawFI2XczDAv
bdfzn/mhTzM6dr7J8+lD8PBoL1D2TRrUVQTpQ7sY11nHgL97DnEZFZdWqpG68d3XKpobACZP2Mte
jppDE3T9OOD+jpaq2R8ba7C3uwTCiK9Kh4uX+uRjVnb7Zw6hhi9yo/Nhj9z82tKm8t84Mu7ByRXn
8qa70XHeqx3J/OgvxBR3fi3/KAMp+aXca2USfwBFcWzHsC3SdAIG7Lw3QV4jAbVpmBOK0SVqWE3Y
9UBKNhwHsSLy/nA32jsDjQUYUQDBE5e35hfgdxfl4r5FqzOVAMN27eOuX0E7mh0pl5JgLWAyvvwL
uVjdan2aRpQf+4NqRPj50x807hoBCTJYziEy6sZbLMqGgKgVkULOUCz433f1qyuSB64Smf6/Z/pb
2E/NQnHc0OlwA8/fiTpmO1rJhXQur5aOhHF6/JrBMVDjDM+vd/B/GxGr02vWGo4S2vNBkhh1qBLR
YZZMwV0cGYYB7RtvYXOQxuvYLrxURwxI7FHkAeZnMB7wGSBHqryJ4b9BB1dUzPHYUzosk9CYvUWg
2Nx4A+JEm/i3107abP6ONhfMMPBlnvcQfGL/TFa4RcIN4Zk8XsNe0FtP+DW/cArZ8N8wXC4QnttF
fiXKyY0gKb0R8iVk3pXm7KHBhWUTVmwxscRwHnJG3W7H3MesL7HmS091FxxE2jHIjdzJ5eHOscT2
kEEGfQ3D2eeL0gS3OQzKddiN8N5iQUg4D95Vx+AG5FHzOi1KhobIO07cT11cCo28HtR6pvGqJdwj
fjnb9zdBSdtZyeoUzTKVcsoEokaAYdgNpuC5Oah7v1aO3ic9tm6aIX8PzTaaxAQZPclLMnQp5+Ja
rbnISugkCcAwvUqiNATgAKDfqlzgGMcWtM6eOA1hU0gECfVNc92UkssxgRQFCd81j5j3GoZJ0po2
ov44k08SRTnRsmWb98lym8793srV5xl3pS+s9FIV5oC5U4m2AlyW4r5S/aPwRfiEcjoAm9BK0Dan
fm9KMwqNLSAUYUychFPThu9rMEDXTkDqeVEZDmc2i5wDTtrtIdDAyLrf3f850So67uoON/egsm0D
EmIjJzetZoq789xUMfw7utsx3HBKKxLEYWkA/D01Z01umEWYdnvnTKSbFAWXAm9IRkXItGyHLyYe
iZv7n5IEAWmFhtmrz0DM+eP4C7uEfcAofjh/kVEkaEBfPAeKgfMr6W9jMlZ2mmvAQFmc9uw1x3E3
E7tTmUhKurYqSzmBUHfP34UlR0wn324orTozeuiaS0fVMiohnz2PscCYZNhfBJuDveYt5vzImjXO
pn7nk+pcg9vnu0ilC1rHTFz/BIe1cLqj0yUjY6/V88ZAvS2MNA9jU2RiVO+D2pUAfgxe/7BXlCVr
pEslLJmNFncJiFAO+Gz6gWaqU0zcDJNELMwBF3lv7Kp7xfQgMwvEf5p+8KIUKl6awYWciMHiEFcJ
Ubd6qQUX7950Dw+9WcYsiSx2UgDttFo9PAJpY9ZXpAIroChhElKgCT0OodieThT5cw1v3GUQHOFQ
kcSUoyGTomggZ7nAusxev5mx1cAIsl0SSzxIm/oz8Vgestx2sMs5D1mNZUZ0XzrKkeczRUcHW/Yz
yQszcgqNPTSWNV1VaqwGpTTJPQpEHJK72LRK08rQH8dOw48NNEwU7eqGwZuFOqc9g8iMOlqAdTjJ
TQA/NGCQiTKh2VU8O++4dKFwL21/C542yUNGVZiPoQU/kKMO74vfW3Hg9krWLP3skH9syKL0GY8h
RSgXP7DDN+mugCeoiNJg81n6GlvQOkz4nCR6HEQcvzCfXlmEfkMaZzcVJt9LxzFe9+iGRb3ydtYZ
SMblEc6buNH6Q8zSgERsAE0ZjvWybmDheqRz+BBPqZw/164rA/Jdfngr2av8HmXqqn/zPwxu1lMW
FOqRBTksxN+VASCQDRAhcTUqDYlzUejXF1FrV82bs4Z5huYXYdltvfGciqXyMEPuRmRo4z39Ct2I
Yek40cyu/5lVFeGy2m3d9ZkHcpxVBW05cI4iYtOUUhZgq9rzL+PCChZ8J7xfC2Kl6vAqKEM0VnIL
Arq3KCmlj96/c9bSNhIIl0PamWixKOcx/1RI5IPz615X+N771Kg5+RE/MjXwXVVkTBRPdiz/er7K
87NXNAKh0w7otpcLeUJBe/1/ScWfJZBBkJP9hIFzIAYtGQYtxR8ctIOvO05uxvb7ua+xG0gU+Ted
ymjmJRnIfJ5oi185GeyP8PNcC9Ldl/CEL/tft5N4UZzCYBnvnGbVqyUO2g3s7u3HFCFDQIVHr7rs
8r12W3kNZzHFuZj1+OxpLuQ7GdkdAH7tbLQusFf3eBn4Ld9vpgQLayxrU1P7jKAAuzOddJa8eyNs
MU3dxifBjugXA/jV7/tdpEPZ4aQTpMksklPJ21GWgLQ5qcV3X5dj+ylscUzzUGzKWFznAzariR+5
1TEGF0WEs+dwNPBJ/F4iJwLuBTUhFuZhqxJHtZjZyW5mmBU/Jw5kKtCSFpYw6Olzg0EZJCRhjs8K
O7QY/dv1CSiOjTVmx+Z6paFZUrPwN5HbUeRWV+CNdaNwrSoRRsXZq5zycZrH4172k+GyC/XBt8ow
WAcjpKdfqHcgMvHbi7DDlKVHL5st8Agbx/szXlIJfu6MmsJwzNxxuzvg19ZryUXDUkFoa1Q17Iqc
KCs4G7GlfYUEhNlqgzwENNaGiYu53plO66DT5NYOA6Cv9miGS1XKBI+wxXWqtC3bSvJ3/Qn/GRjV
uZQdwSRA5rmSLWCtTGX07+a+us1y9/oe52BOOufrs4vb9XIcrDTeP4cPm4DUItOFuOoYooC3dQXO
fTwA977v0rLE/MNwiaKdJkhmmpbTJm9jsBGDH+ULmxlepKglH5bI0lGMuH8GUJV2AvFtaA3cgIyc
axP+CUJdQBexfkffZsf+DNFmFG7sSyuNvjojK9ipkpOl0b0UfUrHnPJVV3RoZxN58r+dho9BNBhV
ynxYDldRGDEAsZcHuRPYDfUxlFCaXMN6/4jD/49TtFA7VXJ7troq87YbBwVVUuM0ajX3rlfIbNgn
C/4eVQ5hdlmyVvJeMRrDoCIu5Oo7je2VQ9eHDZezbLOKn5OFuQQcWz94C+6JMemE1oT8WMuOKsd5
EDRFC645Ub+8ifYBsMsugzV8xOorlr22coU15rkPLxsihW6rcl5wLtklu5/bdYEsXxPrAg1H8Tqk
8Ms8ugyhSb71k885eFgI68Se1ciU7sGCFtmofgomvPWDoeBXFmkzcWKPuUwjRyU9eekpbj3R+uMf
M7j2bYJZUOAN04nrAEKvdkNumxrNgRjMIk2vW6KvXO7Q4UX6346i9/KRk+YHrtWHCW9zeQ52LKSt
uzr8i5lQBGBei+Lql9Ca/WDt/ZGS+poUcOv0WyqnARiK/Vq0ZK2lrvvdalXgHcZVp/qWWBdhlCBL
VZMJV47gGz1Ol2gu8piZPEscWy35YB6vr9wQGSPzLYicHdDYk/SLsRSJm8Ut418ny+CkPn3Kg59A
I/9hWmem6Ji08RTAOP78dTFPHClHB7ARzCweN7Hq60xXmxJYV0Hs+/8UwzzS6/bzgUVJdvIXsiFJ
0lifsU0v5Qub5adsUd/8F62QwcnTmrB2KU7H+9L8SfGaiKRZWbkZ0Lmc4N0XXb4FqkmItjEGFdmN
vTGHEVDjFzS6x78BouPNKwVv11RVBlHTnqpvIJv4B99CD217NltZ4KIpTHqEr4hI+o1NLusEud3q
09SYoR31HJTouuvPXsJCcYkJlMsC0hEGWFc5e4+w8hLY3A3aB6ASlUFjrBGBB2UXR9mB9ikDlTyI
ccctIaDW+KFbMELR+LqSVJyrD8PGnp3oEKAwIr/dPaRpIMfe9xC0tOZNS/AKBfkmzSRPHJH7QXaA
DUusnh1biVxabnWrMEtvdFWfJv5Ftk53CU1TRM+zdiYuPCgK84pBMYXsnkF8qyMLLNLsxFsEj/S3
Y6IdAdLfyFMeHgNOXpl/9ln5nEozxROUp47RyVBdhyk6uDZTIVoCq4O3HnmraKpkMxyseIgi1yG+
YQ0L7EfFCwZD9MIETGTuIc/FrryIrOvis0teaMul4DAcIJqMTlzFovQRqh1iDOf1mzTcT3wDf9Ie
qZ8zdFSsFmC71tyygBsij1NvYtGaqGdy3QiZdVHCI/TVCHgUJjmwngsuoIgRCBLIMHgevP59UY3l
+l0drfy/R8sQ7NhxqY9Gm46K8PL07LJm4kUPQ/97PDAYwGt0xzqE00q+2NfLO762VEiPGtY6c/OA
g9WsXCEHTvWm3N6BHiLlNZLRRc0UYIfX8XGHxcjeWHWYHPSDx0EQfqV5yWg9zZrFOds+NfxGy06C
tB4+Zmvbzyed/x7RwjYzVAmOKALafH87fd13luC454u92aZ7QQ6kUUttPpYaHn4yXrFEr5C+LRIc
XScPXP5XQ+6uhrLNMJttnyI4uG4/rZMknLAf2w/xF0cysxVcfoOnhQzW8UwtGYJdNK6UnxmGXZw4
ViHBkFwSnOG20QUet7N6Hjk/A4AO7p0hCjWdmGK6/X83wnjFRs01PuOr4hAyuELxL+kXtKRn1tGk
prW9Ex9aLlv7IgABcJxtugFYQUnWrQBTV+KKJhy7VDAuIg7XLAOSeYkLOsrXrbIwnTxQeQnqleuB
vPXnP1fdnznFMmD8s46UWcrXShnOmLZAzKv2CMsfdDfK7SdQIif2ct0AtSZ4m+NU2yLKOk7BeSLy
izMEFGhduj/zN/FFPPGQAgD7POsazwRvim9M6vtMqXPr5qLHvwFlLtdQOyK9nC2ah4MPeS4lbk3O
IPzGxnvwtqFhfwVnqoE1IZqHOTrOJeNdWYbWd+bdCV7c8hL9m2Nq9K8igq2QMDFXMfwPTmkput6l
ojn7D5VFfSxIZymx+fFXzyoqCgtsJLgJ7VfP8e0A5CaRPhNwnCs1hpS5Ivt717cu6I/9ga9XQalu
ACsf7A14OZ8P8hF4iAhccw/f+LL5uvAzSvpQiZDwAQgACwxoOyZBelt+aMNylTdqoQLY+O5FGk9/
IrgkW52gElixWGWLiiQqH+fsdcMkV8sacdX+K60BDhYCYFXcsuy78f6sdknSt1ku+czmn2v6wQuQ
FmufSYFBhRUaz+/8MxUXXHiXWfnGyVp6/thTg56821RKSlysHyt7vunC3VlR1TZUOa/GT2k7fKm6
k9Iyz/nHm4CKCcjVJhoW9aNPuD1j2bWHX2TS9N3XJrV80m+A5CoJQ6h3y1t82oIYezx634JPGe3t
XqDeF3trcrcqIlBBuAyf5H/1WI9vfQxw0UXStHlP2zMcWdQKvT2JdaSAC9RchjJMvmE8clhpsuUT
atReYo7DM8m0/E226eWXr25orDXHtonYw+eN9AzVUQMqE1P+LYhvJY4k/3jxN9qC2uRmFMbNey1+
1Niv/xrUadmNrp3vZMKep5RYPys4nTtUaeDaptSCvTcsTFfKNP53CFJTWLi9WA3f++8UvabjFuvb
G0pwidFFuV1hXcienQFnwjfhSkZ4veovTEwdih3XPoLAlQ00JT13/Q/Ez7APiUL7jmjZNHZK1Io5
UNSQBORWobuPVf4L3mZTL6w8vhgF5kdhSxoG+TfDYbaXv8aseVn/zzSN6LuQJFHR1UksUHCHu5Hz
Zi7tPLHPLt4ZFUNhMyeYOXrzGqqNKkFmsc/2D3ujGelCAHeOj3m+Ecprvvy9vMitTWvlX0H3Kuh8
hX6f4lCdgymD8mN7MBbe8cTVlmPld17CVCVxGFGS5Wr2lxC5WxR7L+o3VBtP21KZ6wGRnaiYzDJc
LHIo04MoGj2I+bhCG0lS0qgsyWHo9XWd0HcQo2ck0Vc2TmGAZX66qUmshVpGe7iXLJi2mTbPMiSs
rBLa8M4dMFayiqbkI7Qc5LsKdljUfUR61RDeQ5zQq62LS6m7p+v2cAZ6Q6Q9/FsWHxGzgGeVxX4x
uSdWczGrtY7OfZq7EVxHQ3rs33C4HVOdRJ3IK9vrakHafeqcEfbArc07Y8Xf8CBKvbZ0/mHrajFA
bLh7tCSOgOTZT1sfYLorGr90J1PrtV/3GWtwZ0MLOHMwzG5uKSW/g5uYMhjhWya6j1jVqC7b07+9
ORFPGYL15ovE01ejzcwzNqQo13J9yNj1SS7skB0AKRElrp2EhzQuneLM/72ayLnHblmCOcdp7FQ+
Mgbh2iVGL9LkKBVwZ9mK2MkV0/j8gyAcYMVNboJlbk+10sCjp9w54s/oHh6pMRq51v62jBIIiZyh
4xJAYY1xjAoJZeUz19HWG52dekGx2NR8ox8NVo6ZULH0J+e04Mfn+IFQImZOdldOMsEFrGuUR9Gk
PwraHqk1/HrZ1Sc2I6InmDfTiD4VmeLlwUQ/1TKIXPejuQd9a6E/eJ8YtcltjG8pmYDa6NjxZF+M
8/9k3Wn1l8F/5l292/9z6e3a28dB6cjCE0+bRnGYvxdqc254sJhuD5aAtJlZW+4RAJEnipWkhwl5
keyQzvWUHXgY042U0Hl6rGbvYeFED6ENcXiRT3EInmJ8dhZmWilSuXJFk6PtSry3uuUktonZwmV3
fykTLQXRBYKJtj39gumV3vALvRC0QfnjDA8IWCr0hcYIUJlq8zPo+wW5WMwoxW5G+LVbckaDQwea
N2qOSIIHG0pN0M6iwk2YRjqMn1xIYMPpe9Z1hK5AGR9o9BMVkSczoUFP6M4lJjUsLGT4g/SH0HDn
0kFOhJVSbg+IifsDWVHkKzte2UFvvD8kXgcjTwNn4+uvQHJm7hUkG8siuRxCNrQNHY2F9lWaJuoV
OOyRXjv60+ahYs4FnKRmT4c8+6D8rNMbjv1W6V6GYKXs/9ENWvc7V2e1bGMmXdUH/aDizgT/2QDe
bOnsqwRc0YKG235fw97g+7BSpExQKrUxJHD89nA+kptuBeB8XOBbGfGBEGDjuBz67OylChs0VrUX
NteXi1IUX9yXlaABoK2Gb7CMe2RlGPsWhwN55aTBgXpC8kieeMs+KGxpbVH5MYy3xQ0ICC+OA/so
cV/hxtxc7pKlj1SbJlvviHuMyr7Mr+zxb94qRagHqvGjp87YNX8VafqHB/Ka4xJmM0ktskRG5Ph+
XciUdFj2U/hk0PWXYEWeI7LcRHd2u/+lbR7GiFVTzhBAZ+jzJVIiP7lTrBkxBHVUQ8TkgCKAM5YP
dLULS/FE3c1pGxO4TguMioSXF/QJjOpPbA5q5WBH1gNACjp7Ond9ISI9iap6SFBL0zxy2XSaGG+z
eanLvGadvjNlhxjzdPjLhiUsJh076gPE/h93UxNXq53h0THbD1BYncSD8xoPQ8y62pFmm2+wh54V
rXEJgkKTgGeW9dIeBXW4xF/aUsw3puXBHOKcbXtBk9En62xM9PKKxR8FTnfid4MOQuVTMCfemoHu
w2wT1p1K0Vn7OAsHfHqDqefR4JouEyvjd1u8uXKiwIKJ+sK02GWX0BgBfYdv0PN7syzwn1Ttt3AJ
Rtb6btRpb22eDN7ZNxlutbQUZP8IZ0U1ZG2bnfbYrXCykPf1SBg4401ZV+FMNXQeE9tBTU3G9vLY
iA5y9uKlwd90BcqWB5CpA4+Mw4Mz6ZAtIOqWz7vTWpgncQJT9uwVUbVHCQyfkieA5Mgxb6L0Y8xR
Y0RG7VQIxhX15fp28GCxVBEteL92h3Lgnt5Rhq6bVuYrNPfJAezSs9npw0EGFFgM3ujWeDJmj169
HFaGpQeQM/QlPRkVYSbGaseaeXsSuSYgTPGMQLE5jtX4jGGk3OqfFHbSyyhE04v26s1b+hqWiQzv
GPUlotujSvJwTHTPstUG9d8jGkNYnWOxRFr5lvdSPrAMq3mVMTFgTTUpE06Z3GN005WcQpfSFgYf
98Ink3APLg2vlm4jez+pQ/2wF/mCFxNdlMfypPy0TqYztkD4zdS5UeK58BSGbDVIP0oCUetLovAh
w/cLKy9EFHu6bCOhyjkXl0jCJ57TaDPs2bL3C7pQUbGM/FJhKp/J8Qsb9eIJmHmjCfE1WjaGgLq2
k3HtvW6HfG0KeYRpLLvUXKSPn0PjCSi2wRM3rZRrAwZXAP4sdzWyFH6h2ZDtjreKE++t4HJDdl2j
t4y+vV1274AGzOY+IUAmV6wLMlTd8k0SpUa/5+lfYMs+0aTUjbH/DbNxtRoNm2eHz0o9x9eykfiF
fImmxMNdU9SKcEEvkDrcyy96Ngkwv6s27EXO76BfcB2TyLQMv5BqmnFBw9ToUUqlBiCJrr5uQfo7
MW9fcRJ4N+OP6OQH3Qc+PWyhyFLY6dBnE6ehyMa2ZBS4eeZxGeEhErbHyOjzwA3GCuFzB96t+QVm
szK5EDEblC376eS0WGm2uBXwssZI1UaU66DCB1xlGtxmh1QGf28E3jaiECwrgUT0UvR0wDnNty6e
kmTZddFBrQdGNkBnDlZ4tS0WipY6tknpXugLqW+teHUkOlwS0rWLFN0ireqahiO743KfV9dzIkL0
y/fQ43bFjMgPmZt3d4oYZv84DxIG665/x8BMpuLyF5OJsAaGyvQnsOXutg8ggXm998Q18Z1SvGu7
zkYbD53IxqjqpW3fyaI2702gB/SYWkQjU+F6UIyam5emmlcgkhChHasbJcGPY+/6tt1hVCP4Blco
arn9ty+xjeZooAtoa4D9veu7mBVBjCB3Uc3WMn5eFfex/V4JX6d/P725pNhej4RIs0JmS0H0E/cf
niXmZKaLhPJutqcz6sfKSKucVoSpE2/5BllRMJ4d2gmZwPePDAAtBwvi+j2O0zUWq6mG0Bd0BpXV
eL/q6RiuBdVo9rLhSSX1jvqmPCUqvrWs/I6DZw1dNYmmtr4hFe1H6alN24S/uEUx2eaptx/w7Y9T
C4qg4KgmHbZ2hHQCxQEvQrxd628I8zBnmiuEW5PnRMQOl+FyttqrABQhQmVj760mIHdFETGF4yHE
MPhrbuDLOSLQR9eJgcGE5Ym2UfQiFsZWOhR5JbZp/2NcOT6287SiO9ilo2lUlxgNExxqggdy8vOc
xMtHl16B1GQpxuu7NGrgJ7pulcNMLayBUNHPttnpKuCziY9nmeEKuiV7x607GGzH9kTanFuUzhO7
n5LPZaB1fb568BCh1MF45M3JzmM/kzxn+ERby3vpf5WSqNfjFpqUsypINWxJRfjJc11z0soKuQI+
08Jec4L8tY93qD547RthvNEuvI9y8o6x35sPdAazIwfGz8k88H4oD7yxC6On2oJyuuLarW7yFRNH
r/ufDS87IWYiLirJynSLopx1kpOC0skF9cfBv6uK9q//XQC+mUuCEjrcF6WpvR3LG/unDu6rupLW
qkAHNyRKl2LQJuvPtFFKr9bkRkwRWEUP+U0OItqKZBp+AsdVJkMioDpZMR/IXxwQXi0uomAW6fok
8ktBzXvodPU3roAJo8F8MSE4I72Ucj43Eq6Z+Xv82Dm/LyafMJFUOT9zL4KENZ1DglL9Sz3AJCag
f0RLyq7ZKC3QNWTMEfY9btqmaE9/40l6Par4vRzGoJjdVXAPRMTVIDD4yeoAgRFxTkwnceKO2kqX
+V1O6/vXhfIP8rtNTZADzBDj5DTi0BJtar+374eMGckRNKl7PrdsaUZ/H9DvV0Jaq26nDHd639Xo
/rREDszFzSj08iS49o+CRUOK0KSeZUlfzfxPyyQ5Q4u9EjEPSmbdLochUUz+OFSPoA3esFmM5Pfk
6fp17oQWoQQTNCh+apx/d3lvUBL3BZJXnuqWSmy5KgevcjCoZwVlk6FH7ARKNsOlAvwIahZNTu+m
AhDuo/LqYVxhg7eNCwk4DZlA/opw1xm40i26B+Qvr6t+etojmT7Tnr5DtKCRFeGBfsBKlh25qXKJ
eYbNr/yj0YxBn9cO4Z8jhcBXoD7rZhHtP5T3eHMT0Hz4rdP0jni6iq0FVg8WQ+dt+D/nTniclBKM
CJHy9SzfeDEwY5NgWRTmadp+nUELxhXvy7Kk+VgZxpW7JzS2eTLgxDa4o7CGnFGA8sa9jU8RpyFz
0YTcjmkvgbwxa23L/KK3IQX5antoBVpcc+d4g/0XdYdlM2rZq8GRo/pZ7NtSjjSzGYtmzVzx9WaS
t6nOERQyT25Cdykjm+5CJSlUpMYT8db4Qk1u8MLcTuOlGvqN4P+O+RVS4BLt8guqZyRwKCWTWc4p
P12+7U7wCxNkJ41IZlc5YISK7E1oKZBjCi31GOdx2PazIayrVzQFhSdhS59Y2kTYpz+yZefk4wqD
vxO62W5BaDzDy4REJEjY/uNYPnAimlePZSfm3r80npC77AnuxOLLEcoWArtx27Rnqty0yFf4/XVf
KfjPslGypVDas8FlNk7l2Jp3X0U2jKGb7ey2w2JLErj5OY+wR9BAc+xiYbJSSE2iR4/d9iZgK9XZ
O03+aRlUwzgDiVbQBjrq/WIHMBmN7P5aO4+bkOjukjmsC1fVd7W9dNR0SrF2xBX/hoTVY/ZXskRK
jYWs9dXXz+UrRSXcVoSxF+fAGBo++x38RhjA2qe4z8MMWE6ppg3D8QYGgw4XRQQ2Is+NdmhtgnWz
npdOJ2/e7NYpEV7TaVE/UDQmcnaeyBYvukx/tJlIlfq+Cg3Q68rjLkpIp83kHvO2YkDt31jmEs5m
eWAQSymqMKnPmx46H3bOT3jikzoeRzb/hKSPxZ8cv3OnLjoj8aXfbUP3voPrXIQwBCmKVOcBDIEs
Nb/i6ps6ZyZ8+NESrTYnd6059aNLjopVxHK5zR6lka/xF1x6Kq5DtBWz5k2z88EaPKA7Qfb5LVOW
5NOs+DB1tlF4u90xP8xqM5DXnxExpn/SDCL0l3XT4jfhI9Qa3BHKauCByOXqnLgVwHyQOqQh1Tvu
lHVTiE2ZWgA4GHR3ZkZ602JtchLpAgDBR0EIspScjNIKMqDqKtKdCHUR40XfqO5D0/UWhCjnR8qx
h+2ebVvW1uXOkZDZuCtolMbrSw9hPKD72t6+f7WyyTmdAax7CXU+lzzaytJdGATjyOA+f18dUXg4
BxBkh6Il8rsix9FVEP8v5lToWeXC2hu0BWbjTek6FXKqC41MMKPGvO3ypUQ4sBbeKghAk+qiHnfK
U+7F5y36FYh8yLpqZ3h/uoR61pdAjJZmXDvHYxp2BIOYTHvK/4MAKttthHnEO6zDYyAOQ9qp9vEK
NW4MyMy142ar7y/xaO1s1l5bHsUCniz5G5pzu6DE0Wm4DCoKjUKkzVqTUsPq8ven+MrSLOM5NptI
wI18rmBGadNdTGBzM4cpUcmYyqy2h2F+SrzRqyFmCDB58MLbCm2ASPluQnPeiszVn+iHOeuCZRi1
onglYrvUpgPUp/Wsm2Be8y3owl06YJhgD2BYGDZHYQL6kfs6qTc8lontRjRALnk4+7qXQu8txsb0
1u5s+shITLgfUsGccoI8DLn1Nc07ziIDc6GblSP711WGcNb1M7Bp8MzWDfJGRAfmEy+dQVuQ4Z+o
BfmP+cze6teVmAoCik2unjhIF/PRTlExV0yu4Imk5aaEbpceVMpDeHqs3w9mDc+EWU6ZlAq0mrF4
DV8Gpd15Y2V2L3LHaXWO9BZ8li+cFajE/qT4dTVIC1cvCsaJK8+ktj7qvAZaD5ACatqveCeIVoS0
0gHu4xX94V/HOT3aVqHyAjZC0Pyvwgnxl2L01qzxPKgZRGbXMekafiFzhXfwxPDmmsMgQACQP10U
CtPA6HwqeCPn9LE6qk5fAFJ7B+LCrXPx0g4f35n+CLeOf7JafZC2jSW5SJKFnZJUj/wmKP3XoyP1
Ocro4fgs/tlqrKHm/V5Zdn1s1tdfu99JXTstLhC7KgRhC9tbyLG381UUdVLsul2C0W7z4lXI1iCV
9GlCy0UCG/jGH/3XOu5uDu1MMoFOn+kJNC8GTvFTcQEJ3jWoeANoAeAKZQVl2nFS37VMHN8K/L4V
GVhtNGkSsAI/XChJJPS4BXPC4zFn9bw88PIglxCCu8R4LcYxVZcC4CvOlGeVJeyf2cCjFD/eBMol
c7Pp2zucJZShw+k16XAaLhmnOwYh8yzEuvhm+DZWP//ja+JYuzbIxgT2SB+3q0cvrz9wXEfhiPJx
7Q6bfns7BSlGtD70FL+VdafgJvz5p5lo0joAb04FG5owtvEYGGA0p7QpPa1ORN7zFC7YRpwCgRkE
vobqyoExAO4XcjJ3xUb2ddtVtL9So46tkN4yuwvneC9lIy7TLijVEOuYrJ0A19AFoI9I7HlWQI4e
prNB7RLpfYv0GYcXo75dORHIxA+rNoFAwu52mJFUCmKaGczg6E+DBdcUM6ulChSWzUsgfsWS3YHt
wm785BbfYbl+mhVHEdDGQrFddv1xBLgnAq/UdF0WIOB6XL3cTJbYMWHuj0xCWWBMZcUE15zEqjj6
HmesxfF0WqIgTkt0hFqQq9L3aHfVM3CYwcFU36SSE4SYlX8OiOSRCl5JqoriH7z3sbYyKLKz+w4T
gi+Px9sULx36VvhgeK+Xk59XZge8YlxDKow5zALfvacrR2wudv8ic36yS5NL3UEjMjWreSJIU8eW
qDubFL32s1iVbyI8hT3EwQeKnTEJnz0g9D962/BMydH6KubgijHomwjf0MyECDeKEGUgAydIzcLV
N4EeQBIOw9nbz7IqLdwKrQsy9MaxLLpSVdI5ZDRpOHbnJd11eSBDL3cDkyZmWPsWBIbad/lsFggA
GPb5QPA0YUpk+DGi5lK1WmtG7a1AwmrAk70q1jCgUCbUE74f6hEgRk/UytBJEGKMTlqWm+ykqEJn
85XX/bXVsk+RAuF21aFUoUcWSqi3ZTXOjjbbCJHbvECXmVSifPocf9ObV5YZKNeEKzntartBm8fP
qe8U0Ll3X2QiGx+ufdli8BOeHaf9dlw70vlfrVLrYZqztqKa1M7z9ZnxtXFiNaSegj/5FaXzVcfz
yBqWwEVGyNPWnYM/uDJOdlwUPssANnDq+L6lgH7rMxRadTLEYra0+Sgj0Ijbzzqg7VV4O2oonmj1
gbN/QTjfmSekAUjCbIf7SykNI5CURt+R1oheMGWuxhXYiJ2TRLkaub24sH1ZVCNU8i/JBYbjsQij
+sCsv4GeBumqCencsFUuWY2lx3E13AhAMFZYQIFcRenrNfJpkA+qV2lC5IuOZnjWhhRQg9WBnhBj
u9pipZ5EPr1gu+HoeNuSkRyygOpdT8ln/kkF8U5pLZAo0p0GD/SEsJLqXSfyDQGw0gMYxePjAzFd
EYp4zB1xqXzbumtpbiywh0i+feqI/gXwmJzoVjkDWDvXJCSM2uhxW0MuWNLzhJ4XtGbYGruNQBZU
PvcaevJrRylHDSGVuQyz1CyjaW6M8ccGzudYK7mk7zTeItTv7YLXNqJyHxxQYBIzWy7cLFTQR9Qr
lKp6IyshUpTVwxt6JTCwBgk1tFr7OS0TqNwjgJzy5XWmiq+MgUthVoSfJEQLCoA4skdduiXm3Fa7
SIqhAXf+QNSoQB5HrJbxUPHfGnNmzXP+VS9xOjXd+tmBWzYw1uL/KuWBWmIuZG4dn2upjVBgy5n6
+6JCvjNl5rGIdFMgCLCLwruS67aIrutPmGdPNfxLN9hU/7tYbvmyPQpIpSljuRWArIOBZpn1vcVu
jHh/7KSzvees5EiVplR7T1asqgDclK/TvtNaVuy2R3q7kZHFvPyp2KNjV2jJFF0B+z9fJRAGjylL
+I2lqDYhHk6sLl+m4SV1qiBp+Skh5T8g9Y8eUrtF6tfbHM/mEVeVn4464q4ca9VS0vbjLij6cYdw
VuYdEvmBunnPXPiHd3EVMKnpU4HwvUWlr1+UErzEnMnQa4VBl/CYBLY7FYyPF1Fnm0UQ7RI26VP3
jmSqD5t2wZvMVct7edDUyXhbeC+V7UdAcMALP7x/v/8TPWiDhrFz8B/T6fx7DNx9gydbW5owXtpW
JE1cIwIwAKf1T17MBbBy8SNRsOcGUw316RM7mFcqHi92L3LwGrdfvCHMAHsijRTO1P8870RpDBJD
m6SLLXzSBdDJp/oi4ryTQKM/2ZMFzFw1LULe5XAHASQmsvotwbIGdVln7IhkgH4lEgNC2BITyOOU
TxSFbWOROavC0NuV5X0UokCnzvERs4LrgRH2qak5OkpPKIarj+R7WvpL6Nok5uMS/eqdOWS0qEPg
ldSgZIoNMOKZ+DK8CzEEBLbL+J/Buk9u3hqhaUlPHAgabjCjnABW2aC+K58hdwyi9yuD/7z3swEq
JoBoYwt6hEw3De7GsxXj0r1O4y3ydH5Jkcct8cZTuZPcRaB1HcZsqO69JzWWIuWSC1XEcFYqvBn/
ilXtUuslgUhFpJHLhAUsetHmEkO556Ph60pXqQGhIFgPoQvByO5jyQNchCgKjjitcWeWw3O70nN5
5ImLRSmMee+vCnOdH5IbZnEnb8eu8mtv4Vttwoe0pe5PX4tOCOznzbvgB/ylOohgnYm4FOQfpvtP
4dI9z0aDBmz3GrmlmsH237gzscM1piIkpIFLxWA05HXySp6mGehem8yIEE6Z72RwXtOZQtEE1fRr
+hu3OTQkOzhS5O+tHwnmWVFmWG4vVSqbPGaZGsNopxiG/gPXDsHR9d4PmgkMb/m2QDf9WTJi2YSZ
QwZJtzpnYtuiy7PhQ2QBH4817QrFn0aC68LMnSYNK+Rz4VB2M/iqIVBt/5OOh+ECjaq0UsEio3v1
YLpxAUTc4Lv2eaK0viDPiPrqu3FJfnRcAq6wi9EsvCwiQWSplN7Cnq0drhm+ZM4RrShYaMMCz+3z
heaRK+4F5GsEYTDHReW7cIpCShGHESriKvW0QqdDsfmUrG+xYo0eBNBv3ypoAFCo64Jm4YnhsLA+
Ytcoajf9zVvKBxHEwPyumtrvVxODXT20U1nzQQ9fiL/Hi/mBKHyjmrU7qBSJXjZyo57GSPifRZmR
OxZHT5W5nvA0+2+HX0y5fgZxlhaX1fDhbOUS4/g8K5cjs+9x5T7S2MsS6F5ws89ZY+InbHKyo78d
DkAYcgMT6XgW9ui59dL0QabK5MJD2ZOAsSOch4ZmjRIf5cTU5ZNmdEDAR0w+NX62kVCP5aJWDixQ
8jQC+j7sj1ODD+iraPcmv6+UULeAOlRYgqGa9T6/cjvmy+SnycWWuD6W5oBq5pjBE3N6Qq/nZqwF
48u1O/6OwKIq4r3FZ8OpwV0ELrpcTYm1AM8r79OALDZp5U1mlZLDCzBlrlfQryWPtEmHpEdB/hhZ
uoVS9PAbZ5VaknR6mjkTp+DEmEfCGczlRFP3T4LGulCxYxVOsEBl3rbevOkuUvXfHbjFi38Jc/oP
mxdIy46COgpCWBmDsEpm719PWZly/GA2FCTDK8ZzyFP/NKFPOTkfjaeIoa+vKJ7k8zbxcO5LVKxR
6/K9rPsx1Qec4xCTwVnfrgPl/Qbuvwdj0gUAJMtZY7wjerGkrkthnLlUG71ka1FP19AiJfvIdG4h
xBBHeIzlRL7+o2uleI6G7tvJq+9v6C/ZSl2AVTB2vjDMpVGZYbdkVyDDzV5XNZSzulR35hbdSKjS
zEBeJLt9tqHwABFuxS5EKqNU6fku0Tig4ggeaAzTA3NE/99v5NcS5UFz/stsZTqQc85kYzKzQ4pH
7y2jSaMD0vU/MvfGNMJZt41nxF/yl32iNXM6lGeG5GQzQmNueOeh1CYD7SH08hVbp2c/LgmisllH
se7P1TW627pev31H8MIJklJf/OEjr+KpTC4Ey6dmslWLV5IDRlgTjPRGiERl0Cbe8yZuSUt59lzx
wl5ggzjuheLikJS7zYn9Ezit1hffQmsP4ShDJvhfKNPb8AuV/mlYUC0rF9iDYJv9GAOhC076M0a9
yK7sRExvyiqwxMw84OVj9dWIN5pwxilB8K8+xlOmbQf+1CPOV9W47amHBFK69PFJB1UjjOPZfu/u
bm4UeC4VRUaLmBVm4G3XVNti0Ul5MumDmbUWd74TLFNUFG2XfTPBBOG0Z/gji7/9mvDlcjnNQLPx
Kiz64RV/5kLs/GQw1YU010i5JCibWiFJ11t6wfFjN0QZlqaJ9YU0SDeFFAmA72dX0nOQJBwDTWqC
QtdQ/ZBHtPQtO1OfoyDMTMe7DDgBSzue6mZeJOYyY9kDUrpL8l9eYXQY7IJaXffC2tek5amAuZVL
lyNyxgHsutR7PL+npb1HJqSJqs208S6N+QgW22Uccw0AWfzTjV52uc/Xn8EdN5Cn3p2AsugLLVJK
hFTlJI35jc7r39LiBCiZk9n8quvHPRVqi19wTcD24m17diVWcVnQHCFyDFZUQ1cTcd+7AlEEjARn
znmr72t4aUVtN149Li/HPQYD/8hIL1QgtPO4G6ModqeZanxfu6xGF1WMJ72kkuX9e9BfEIEl4lSV
xypFIAzmbMqE05/aNWFmVEAWB6kbjsVrPnPPWJsgTovBS+K30jiAZ8h7Wu0D9za/zl2B1vetgoaY
mkfyrLhfLBOY8P/GJ/YG7G1M4a6yJ0bCXkDDBpLJwzBLH6QCk4z5V8e7VPUJTyFTks7VsiDPzLJ/
U0qeJOit4DG7TFP1544AeQT0Bf2K8E+OVfXo60dDCsuazkaI17OEP2Cz+AUbwjRfA4CjCy3R1KpK
BeIu0rwUcgpQhKhGdobXkiL37YtIZiyMmIOxyeIHz3F8U0cecwsY2KAM6iUDuf+0OvRjYmtlKezK
SF2trMWwT3Tw9e7a2e6mieE3suEmhguJ0o+bCzdXDwgFxD4uf2m72X2Lc8m6hOdpYYPRU4QfbCV5
Xwsou7CXWdxmXTnfQ3l7+RTRe/Vt97h6li9C91LT0NvswYp6UfjhLUweVRnJuFt2tdmI2bbT610k
IEcK6AZWFqL4TrlTbB7rFe/MjqStOQFLQQy2FNNVcIWkdcbUlVt1vwwydKROPV7SPTFdRsn8jKS0
ST0eE79qmwrFHHpL9vl4SZ9rhdYPuZGkv5blSf2cMTuq87H+5CFG7OlyrUSCPzk3wQsny0/9z997
1tLgYljjHnw5nCf1vm0wEWRgitbpqSz4m6smUoJOEEtOpG6Wi+IzdLvbhnD6Kd3yjH6jdNzrwkb7
Wwv09H+nnVrl3rw3rha4KgUQDVyW2zIyeEEI1mjMeLahesNctfdoAPw55p0lSEFqIDzIL4YS7w4B
6wH3E/7Z1sI+LVLTfySYShyQ9oXJukj86dnsatcfqD5L3f8QXvjCpEKLAKlxHYHscBT2Yw/9uvBM
KHu2Pkk/wTNavDu7Kv+lpunIWrlBFQxjz7+io6axqMxXu4JjHnppCTuBpvBHmnRMspKij7t6cpOW
Lhdwye3nS7LNGZe6v/TawxXDRGuPK0P4gf5lQsff2CBljPNGXM2fDWaD7ga6bm40SsboYd7wEN+z
MdUnEXJgM6LgjMlpgHyLbwf9coLW1hPHEvE6Vs4ndlikMR1ZtsaOR/Ph2jOlBM8tI5KbUoPobqN2
mBsgKrTRd9J2OFnM7LEVkkKoWaPZ/mmwTxcNuqc7/gGxpXCVhm4xlWFZNRFPU9M1S4VftY3vfoLo
w1pV1imvFvlOX0wzFw2gJ78V3EHh0QBbcGerEhphEA3eH98RqHIu4vlYMpV84y3j3DRx6e4Lkg3q
uBO9ANRKTJ1iUQWsyXSHK2UGRJ92LtdpRi1MmfDnytZHGwgweObaquUBEpYhrWbxXhOr/Mk8rRuB
aYiggw1y33YvAK4G8+k/LEoKUbd838ZvYtt06LkDaIQN3cPYm18AiPhuGItbagn+L15vYhWoZPkl
KPufvoEtNwhvMJMLr544DNnUrnU+3Igb8B90puftRpT7mV6a2FWs5gO1wonCNHjxYhbZtPsalY6/
tQfP7Gn6JtuTkhErulUlQvpmpFcvzHBuZxlYCXSR0OxE2OlyldouYClcxgaA807L5ex0xUlgcO90
HAr2U5w2dLU3LWkKSHhCeMESC5G+LWIwDy/jGfMhMuVKMe63GZQKWdnMCkiguTrVCBX7q9c5yIlw
890EpM5oPP83Qb15dcnBeQW/w5uYF3NLZCtBO+cAPjtjAPJYZXkA+gMVa3QCzNnvPu+UhQVZZWen
S2YRJhzt4LL5CIAnm62k2I+FsXULNaCn8BNQOKOSXSrT4zsVmKvaBk07nefS9iWBbeyy72t1m/4m
szQyH0lJQLSWkTwKzpKI1U9tDxR79saYqj+WL82JtyYY5NEiaZj2i8a2IOABF/yV3iL5JErfGgYk
Hq0Rcwgw0Eck7IyhLUcxomyVrMMPYWsWKMURv88hOYYCW/37ZPoVTumBdrf1lrpSybFSUasn3TOv
mTGrCB0b9bEd9wBoqkGB22CN361paAEGsIR+7i6QeEY0PFjMhyAkWeFQEaxXCWlifB7ILn/ZHHL7
91KpHWmgSj5SfdfDO/FG6cHJyXUa0NEpcrhhZgSBBESKIeJUiQiOafvoulrqsSOY0LKFfSJECTSs
I81A+sybB1IAuwKwvPc8po4g9V9S11q3/vSfDHKXTc2Lks+yHr8Mz8YvvXGfj4IbaZVihZtuctxp
Gbn8chOMiJFtGhDVNhUQiMhlonHs3J73MuN2gBna3mpJ8S4BIU7J2qNP5ftQ2yghuVkHXp7OQyTC
uuy93GqiT+0smnbxGdumKCPbG2JqGuw7YUHLKX6/nuuvHY1ElRin95uYimf5VoQHImSc//zyFcVU
gd+VeFBt/KSCC4Vw0ZzvwchZu9gF/2Xh3JCnNmvinvL9xpZhWrFyQsbjdJgpVWU+xRDlcXn+CeLD
ZTBltdomr7Llep8O4b0K4Xy40Mc5YDZuyhmHYtSuVNMx0G4fxd5kQpYJzLQEFvQ7i6H5xYmgTf28
xbu0PvI5GfkGpM4HpgLLSjLatjBW1Km7o+pgHyOEyHVSapcAx+ktLAuM3gvcWMSoZRthhLBig5h+
Lhp5aocrZpISOGRLYegxKvMQKvXfed5zH5lACvN6u5p9RuJQUBbHD7u+I4rejz0WzeYVDO6s9NJS
RG9O+UJRfu8qZgs8taFj0lB+RPcBmQHjrfMZc1xh5AgG8EWvNYInk1z4TdAL9qn9fZiGhfPCNdHV
hYIDEqFVOb70kBhHuLYrLzSUJ8e9F7rroseafAzT77czcEwNRUFddRJ9o83O8ifxLj0pEDpjNDP8
nhTN2zwlJ33OAWCGW6hStFLbdJOScEaibNgc5N+BYaFStLTSe7D5+SLfvjULLekQiUjv2nyjOuyZ
FyPEj+PxgRSvilx9xZYNyTw3oLBVoiEhTbwVemtflSqB7n7NlgrWHHPmEB4jt0Z26SUDjLOkgGXb
c1Cobwgc24AetGmRA28irlpJe4UrE1HSmLXIqdUpuF5gM7STOAeEb1Taw1R4b+NI6ddQ5r3jYsb2
7BK7UFLG6Ulq3Xy47CbyhU0yYvgkGKZJvXpdRWj0UcGJtx0xbKZ67hDCltM9Qq5u6B084++dc0Tb
S04b6fT8XKR1WIZl7h8NVm68Gf0yThh3QEH9kt9xYctJdUPunzgzU8wUh+ZUgwQk2wOiedeYJ8vv
PsjRgvSY5vZbNg70ejnOwav4ozKDaGQXZToa7of2JzvIdgINA9YAKuO4mtLotcX0zZb2xkFxrPV8
G7+Wuo2pODfs56rBa0KiYFjTKryLUroMEDzfBP7R+vmjCbQ0Rn5T4NVbv/gxoQOKtZH58TpfPDfD
AjqgNbRUbRQ+uQtUDRgcq6hNCEJtj7SFXTzPbKiKwQ/5d/y4c+eLjOwHrEeqP9fBkh9QICcF2XLZ
qszUDRAELNI6hakLyn7h9IRzTr2iWEzER/SlgvU9QIcHY/JYDV4JRL0SQjInEjwx1/V5yE3q50D/
de2e55xejXVxV37B+5DANUrKWtGo4drxzIWnl/nXsYZQ2ARzEYWGDaurv6DkFydV77YEC3De9Tg2
QsuV3T/3AUte3vbJ+WYdkYautI92fzmQf649ClAkCzM22008zdwHJUTLt/TJHZ+/85v26uAMMb4N
1RLWBrXEiNH2wyC5/5KOhzdkNTtEOFcsuAuFbSzItjNHJS8U+wd2zoJVJciyPSdH0TaX0VCAUF2n
7SnhoYsvVdmbW8Dl8C+FQ4XmpgGmW81ZOyvSJwfBLDPfZQLL9zLCHK8sfyFOeOPP+8/oo8FTwQUq
M7nzEs0LcMD7gVraEc/ZdzWBTb7B/XrPLDRhWJu5bQY9+9OaTGRn+o+sPQhMFlhBmky9qcEC1LjC
Lft6qGkc3WePcpmDbB3t42eLgZ8RNmpqd3A+ryDRv2396Gi5iXs/r/ZlvVjNN+LV8lkUuQIFhoOY
JSC/H/PNCfpP0/R4Eqh+eARm1iyUty0HNmwkdJfADhRXVGUKThw/PIFNhbF8+FQEO/V+6CelDd8T
6M8FcSaExXVduu30ZtM+7eHp0oqQJlmaXWRyiQLIAkZrD76BpB9e5bhMCgDpHo4qbch6NTXrWVY+
eh4v3xMEBofVCTkxwOrkU4JP2NoOvBJAHoEBOoHToro/bwII3UjQX2FM9nL/apD7ae86EcCN9iid
yDGKK5GKkmTlQtP3mgaQ9JCGNh+rYfRNX6Nm9xufoSXIOXW6y7OoQ937uqjpdQ6UqVudbFKE4IxC
sbc+YPD16q8nrAwezaoy5xYBFWBUd3HUtKiTEGslHmnIbdYgTz9wLxCcBNjS3VXQxAs81sdusw9H
IjpP71dWZyTSjtzbdvZ8LK+h0+9OlvlM2EZ7lWXHd7KMr2aShzbJK2wNbtcXo0GVUbPX0T10zGgb
mfxL4LgMlQJVjm7GgsyZAPiTHlsNwSCvCva/9ZCuHMMDlppFMU+qo50dxyDD0AXPB9zw+ZSBQeJ8
3d7T0IY2YUEoxnNd8G+kq0Xt6rqv0WOGYhaH9VDK4vvjaP0hcq/m83eEBmnf72hauQ5YuP1nW12Y
B+iBgahzGY9u2601MfPHqgcFfa1A3KS073BeRrpl0sgEq3YCWBMwG09YUwIjDTgxwA6Bi5vdLqGB
LOgAFf8FrgSwjtqd1PSwrFUbjnik3p6/DkuqKev4AiV0Sjm51gdpa6/OcnoOOCqHvBh8SAakAAXt
kdUbDF6IT4wuaJ07TXVo6DTtSkIUVx+a8mMHIhOVl5n8eNDY8KL7+vviu7avkCYh/+emRhis7o9G
9v0MpHZIehcqNQTs7+9d2bPbmZqDs0HWWv6k6wpP5vs6l49vwAM8MgzBlZNqf5vURHVn/ABpFki2
hT08R3XNlZ+bQPtMcn1Bea5pCyW/KDrNGqh8Qi5r7DwZ80+a6eNw8Cfex+YwYJTth+C4oilEhzql
hVsMLFf8BuxxW8mD3PZ9FtIO+5nZzGB7NBnkU14rTIt1rXsyXAplapDpmikxZpa3o1gbLYymzrPu
tavHXd5JVTYRqSNw/KWJiMsN0FLGAYHqd2eyLHqj0jNSN28b57AcuJ405GVRQEFP9hGeSCeKuVX8
m4sEKU9xkkQJCjnH//7ef/vGxN1jDJcagS69wPPkmh8phCpnOw6n3V0IVEfZWG0/3mFR+lEzrvSl
+HXTb/5m1Bg8YywHXjwCKyEgIx9jx6QWWMYVI2jTBiYScStOvEXHAhsZAwxr/5pXvAPmQZuqVH3t
vKzbf3/t4iQrUwJbB4WHRDLx+O4wbKno+g23V3oU5CfSRaYtqAIcAaMEHzwveigwHQr4solMW/ct
IIUv8pFqJ/J/bSKGhv/M4HUbP6nOYPo0E1c2PUAF9XL5gPhVGyclva3FZWjLTQyfAwx6rIVYo8fX
IqmHmIwqyco6GNJjV0WKN+B7jTuZgpRQE4NKl8sF0eyf/7B/O3lnoW/+nPhzqnKx2MMZWHK6Ms1J
pXS1ZrDJ8tNiWV0aExi/NOTtPXevLPAQXSUVtwpP9iE83L8mr1E526rgSvhqBNEYfaBROCY7LCmG
qZ+hhL/HyDQP4JD1D3Lg4688gSpbIu91pO0sSNShsG9ODVbczbWh3zRPLUVTTFrl2bWjWz11j26J
5sYpV0LTasjjTu3Jwt51wbSJLSre1011WFSnnnCrQbUsIqOBfVgJtp7R968axgbZdvYC5Rt/Xq9O
4YDaV9WVdYbYToKEjjbjTKNoIdkQswqTcKwkxYb8qJ+909jBs9g79AnrhgmdhpAoAr8daF05Rgb8
7xPHKOgmLgLSMTNhDEFK/8jndmH+JXu1nvriC2x7yMEpkce1VAkLekAfKrKwmGnhjKHn5pUKYguB
vwubOdYSi5YlILYrvQH33RMKeBen/LT33kendoKeuNMg97sBMQ0CRRS4hXdg3QfRcH9Wyy+161t2
mepa49zyxF1FEFa4EGTYhv3WIw3sN7sjXESNjglhJT9U37Qa2YIJQxyYZezgkhl4+FeZTLwlOsJM
7o+uc8hKkj9Yxr8F1eigVA+9iCnXdCEn1KYFZ75RnDrrtzdqxpLhlz4Pw+wCCZQ0j+5O3Ly700yj
RmEo/LWprH4J0DV77+izDsjLXschVNcxqCxJ6AHLUamJ2kws8pNfmAi7KAuEAyEQ0qRN7GvUl8hR
3vd1v2lEJjamt7iuya2WPT4O16H7rdGMKTu1rfufcoPZNId8SC+L5U9E/Sn7EgWXR6eN4lks5bhe
RFYRNtrClQG+/fz0a4jFJ8M1BIwvbizo7bQ6AgTbMFxCu7SWgR1PURpsvhtAkhRLGBxHeU6Em1q6
NeIuVAxUOang20rtBeTXBBzTwWmAeOnbH0sEzV9d8Zg/U8G3ZO4oSHXhCv0TFPVtfe6aXaE/MRv8
DafwbGuio2pnSbWnRtjYf+0d6U3/cqzQxfYnvrP/C4VkgYPGAK0+b2NSo+oUCa+pc9fWr4H85pD6
Y9PD0mD+UjmSajjDky7oUsLjm0lydyPb4pRcJaaiVeDq1EU/JbiDn7+Sl+PYHsVoXtW5xj1LY0iR
4A5UltHxo8CtGX+FcKLQYMOkpG5jtACekWrOCQFEIU+dN0gdkr39Nqq+BfQH4v13pEOxBbS4J/61
9W7IdY/FqgAJrE9R+yqbcZ52e9wKrMJf5jt7SOWtsAYYUPXWxTOjzI1vUdPtCoWmkXIUfAFSG/qV
x10+NQAVTVhHw6ZOT0PV7UYgPCkmK4qnNHsONfDaOic0UZ46vOx3o3FBg6SjaWYIvCnl5280ginr
hidV80vVObuCpdZPiky5//rYUSzic0cb1LZzoIREyehnrnOdoCNHjSIcGpmoPrvStUXkQZcU7hvf
yA827Rfc6LkTxQRXVTc2uFAe60OubmFKX3+sr/Lu4XvuOyNR6exC0+cErX7qsCDiYBXghrfwQUDt
5pP4aKSUlWQhNEAuDKrSkZSTZAFalQPJy7dvfHvlmLlQC2N+RGfpD/nXNTRBz6qtalIfKGWInCKD
WTDyWjgbEHk0ET1oI6G0oVYYDRAovJlCplEiZu0028IlS9vu+SQuvYc5lTlSckCHi7rwtQ8vgElq
iBKPh8xHzRZJI1665KJfjAr+lSY6oDACEU0T4XgBTczAxrzq35Ta7G9tLso0bYlz8sFcl4sAhMwv
HkTGs28SB5+pxF+mE61FAjUdJbW3Ug2HZfGalGUnBSBJ+Fb6Ten00wE79eRC5BfoRBTR26xPmkMq
S7bTYcb0ZZWQxvg2oTdjqDQ9MY/Rhs1fd8JMPV/2CloaGn7Hg2KKSXKi87LAmzeiiuDHsTqZv81F
PrHT+CNXwUZZOYXS1I10jSktxylQI2G90v7rl6CfYpWJDyZPEfLtW6AUVK08u9BR7u6EhoJTvfOO
nODboVLDomxmo+MgqxvVmWgxRLE6cC83k5vpP51uMtc0X0XofnCnNH7W4OUeEdupk/Ps/5WtzTAg
pzqt0J37l2pGJ55CslGsglqqofyZ7AfeLC8YDP9p9erfH7bSN7JmPAsIb2FqfJU/Kc2csEhC7dKs
7Oim+9I4tCUTX4TLyqu9//XulL5mHhDt9mfXneoGojQNN64MGntoiK7FMHVBnlVmR0XGXkHRnlGk
aMTgwdl5eU+dZkKzLrql5ba7gl8+gmMxukJX3611Ka1uAvRuIeOfx0zYlXPWUKTA+U+skTAGvwjj
/6Tc5mmwt+IftZbNpdicIcjB4TywLDemeVj56ItLUG8kpHd6O8ZiwBcSDWUT2im6X/f4ORva7yo6
gXP9qiJgMwNA/B788b9R/x3LLVTuDQtsWtrGYFLH1aNJBFsk9Vyoqq/t/qiozeXn0h4yarLw15vO
q6jeQrMti65ROYtvnsnMKrZ0XT3sE0BjQxM7KvV4hoTPPTNmCu7yjxROYFnyavYZ19/K30UuRc1U
1UUPWo4K49MxrwHR7JH0GTb6juEAFsKUAqhHDEbSpdZFRll0UpnybsBrqdZBcT77iskviokyiOmR
1LQgyvRvbEgF8k2cRAxLeWf1VRmypc74ZK78btoPS9zINiS9/qMnGnxBhJySr7V3qF1o6RvyjFG7
1YxjHGNJw3ybvDqdI1xgRCzfkPDuoGpgqSTGpoed+XR88H4nY7sr3YVxCH4ieDGk+6hKa4+1scSS
wa15J/b6OZ3p9tyYs0SwNzj83f/sVWCfxpesy9vNRhssctlky4Huwcp0/f3drZxBbaQftC1ZMbhW
/aHwOE8dgQF/avK9dsPhwaP2k7jnstKj/KME+eENB4vQuBDB/0D5FESkAz98UBwYbQ41RLQXSA2+
LpmSAKG7+oLYb0GlANI1ZsYewyVBHOSHnwsMQEFf8isuaok8Zfvionfv8dtA9AR2mQHY2IE+ucPl
hzk7Ho1K5jIVLHwq4YYh708YezPy/DamfovQBhW+1Jho1lxVWE4zN8LT3iZggJdr+vQPUdbxT9BD
yvBF3UngFa3fNJkvUBqsfb27XS5BfoYxT4BhFklsdQ7zwWg8+IuUcbWlGTRBwm8z6xlvy2X4pdoX
tLbZ5kXGJUYArZwKOiwOXg/HHi6bz5+9ezmK/RdnvhDzhwz5gEoso/emr+UoH9jzeUndLk8Cg/qL
6+gems6rOTy0PckBQ2Zy1/w5ec+rXr5uSlCypXaBMdhhxZ0lDmpWHi6YIGP9cHzvuZLNqOtxiSFD
AxLWTNr54L/mbaFw7IGLR4odX1WTrs86TyC/40TNoXThDeRsYGDMjhjb8ij+pA2RlNUjP0L11jfn
E9kCBN2/coeMmWHUC+v2CSJ0Ig0UiEghGjvGQvjZB+GfPAQrfDZwzYrIXzuBpVuQVlG31oWqoG8S
MTqwy+/FaZcgT8ZRdr0bmrHOSRSMdeMvsVQneJXnBcDNTievGYewgyfzJDW+7q5JoJphKiB6PeWF
jRW9XvWGsyuHelHAMy8LQxN9IoLo3z07qRUPsHXaBSNcnSpHsDOozivCF3JmdpzwfjzQGx9r34Ie
KNzwZqIQKik6gDOX2z3EI8/dJuM1uCvimPN+Wm6ArYx1z/qCwsGxjPSVXvgBkh86Ch2Ty1cN8whK
4Tb/JNrfX4du3nXwfrl1l89/9Ss4pKtV8BdDd0EdZMOS/w1CNRdZb3Pjb1NTAaFAkIZzuyXq/HMT
p02DY2vFuNnceRVsepbx0t2RGY76miwGFTtC8qNpqMdpGjuDmOUn68vkuYi3ma7xSq+7FA2aEfWL
D7RlDagO2U52ALPIdrbY3grIiTTWj3XZyDOdNxmpysb1pmWdTvple8Q0nYTtn22rvmJAbDPjAvkD
cuth1nmX2+GuQz/ed7YQuluDHazs8I2Rdy5fOsGzcwjDO+UCNCuBXOe5sGJA3/Kc1A+0I0b/te0l
eVWPF3VhpIr+ZTL7CEIFSBRgIJ4OVKCamwNV9ydlByPe6QiVRZ2n55+I7B0/i3AljbzbvccnGSNa
pQUGFvecyRakcpu3rDhyE9KWALsHFNoDdUWvzBZTJqJeUmSSW8gnP2Jb+LE30FgM16XLgOOdUIma
irg7KHJhNVcsts5MRjQBKeuttGv0F1tc5wkwOthKguDJAuY5MSUL6gsAq5gA4nTt4oE6uIoSeRrr
4eC7EoIbJHnHLqTDcEHH6pmk1BH86pf5W2ghmMHBO/AJt8sdmSHuD7xyltRjuAmFQtnKLZ3/66PR
MnajYs6Dq1kBAeFvQm99NC+/s8GOiaEL3toNi2hZHXSe5+j9cEI+Qp3ROFosvkyV3gUU42Ha0hJ0
Kz+47zvxYwED5ES1+S+RwOl8LgoQaTcoID80fsK69hIgsyXRio376j/0pBPujGDZEx2b7ztyGgkE
lb0n8CKYYc2VHCJfpbK3DXzoHmHuH/AJXod7qh5haIO4o2hqToH+aj2a4eeECjpQnwjhE55QMg+a
u5VCUHb1JbUMi6gSfwKYaZR7Jx20z3LNAXpZ3LPW7HSjxa767OFx8JLHvgQwp3G8Rjdyrq5LdnnO
ZRo/5xQC67IoWIYZP092zNtLwo1hkGmFuiaQR7yIofPWrwTdXKkZQFjehMwco6Qgv+67ehOenfiU
uIgHrclA2U6mwqasjek/KmryjgMg89H2BtJfaRznIBl2LwKBfTD2AoQJ/zhopvJHABbGA2RXFpMu
8g4TwCuWUAAqLFLdfdr+FhQWl89mYozDJcH3S9PBfMmMVVa5Ggz8lURVjKcg3yY2+WuTnV5ZEPRx
qiAWz57P59V/ATUsXfScRJHvvOFf8tC/gpLBKe3CbMx0HfUh9vqexyKahjnOUlNseCxATV6cDbf1
N/hdbaERAz+xgz6Dh5LENEwgUjNIn4Dt/uSsfXbNnliL6hdE0VaGkL76HDfjrdPm1w/Uol1CyFvE
0zjDNrUjrptFGzi7GHSsJZ32+sy2JF7b2w7Po98Q08MQIRsuvSaRx6vYjg+UpKZvj5IAbDL6lieY
FdU94SqqWa6XBYHCDFhn6VLeX8tM9yB/pNCUGgo753py0FrkNiaWTwuttgN0v4x8kSXLIAlxe36+
YN5ohHQBmLr8IBDvOuhL33n4OexPOE3DVlshLZC+Ec2g072gUjhhMhVS5uOLU3DzYST8sSxqFxn8
KyZuK4ZzM5bfSfGlRQXRbV69AyNMAlkJsFj/7l+Q9TTVO3WwEaldE7rTA5oTj0j7TUqtZk0ohjvU
pXF1jx10/a7EoJXC7NMaonRnaYrhoeiu/26jrH94xXKqHWh2pFJtz6GOehqTbhy+S0NiVmI9U/HR
3/QcHFv68FeJie1zutQPA+BQcYr5u3/i6Rd7Pjd9NcMOUEMUwtYBgsOwMLVvD31IG8Q00X/zaPYK
y27CRGvB5MeXKNNWgeEDoPWEa+gVI6uKKMM110VIuPgM/Jj2U8Tbi1I3VraIASJ00IyR414Zrw/B
BMi1MNquwOU0tpxorrhFGP+Sh8Bym/X9DtcHR4Svp7TjvXiABM87OFMs12iI9HFLxXh+7NH63bYP
VJ4PoEYraNc4671+i+Ny+NPoHbLhr5yi1tiW4YV7YhaXdmMKQOcJArkNnEJdKSpQ9gHag97UOv45
DlzBfCYHVpqqaLdhkpP5sQYsflbHiRdSBjkFt9s1Pg==
`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd | 19 | 43742 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
L9EbKuxxzV/09pnAb0OGW9DxPQ+o+m/MvX4x5f3JCiR63+KWt2eYB17k+9mGgVY+K1VLxoYz0z6V
YvlDefublw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gJD53XIM6IXGcoGao7b+pChhlJwhGxOuVwSTI1iU+aaEVIG37JelabzUSiGlwgboK2Zv8N9/EzBK
Y9pDSGcMvhlTABOa75VEGmta9QvVzRVMjXtd0b/jrdUkZar600zvkPbB8+QESNshxT7B96klkdIo
XvMdlDR/SEQxmh4Mkpk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
uMh613zg14bfl9MaiMXKdALr5q+gvlBiCCfJpnudkmj/VEzNaqE3gABSgWbIJEk6l3XEblsHwoSZ
2eueijgOoGBjZq9eDXqLeir52M0Z4RoybrJFqX7YgYE+2quggoW8XJjUPK7bExWH1Wd6un6XRwZo
+XQ53VUhkTgctFKNHRr7bEqxJa0qk8dm+fTRKVmCc1Tr5X6rd28yRrr4koH3+liBwEPKquwcMKJL
zK5B0g+bSiHJvGXlQQpKzQNF3+4MebcveUUQPOYG2FAjfRJs1t60dgE73q6y3I1DMI/3MguCuvoX
78TA3nOFRYGLkISVFXDX28xYA0EnciH3BlzGiA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2ADp5V47yVkwRII2+UsRY3zvclviExupZdil2h787eVOjYg5odQlZCOMnldkarIbxDBoj52vjMGc
rG04pAKa/Z3oDUnDkDe8ZMmBI29kynugqgc8aGxYPVKp3KD8EvhnicB6/4Tt66g9A8WsjHtxXLuC
0ImlGHU3T8u48JygeUs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
s5k0DDcwk1Yhkk6mc4rW2ITc+jBCojX0QPFrzARjmvIjcmc9EJT8pAYSdJK1ykoSIGmT8u4U6vaF
5pchZ1NWV4+0T78Lu7ir0M6lHPYDFRgXZTR6CNdPGqAe+Si56W7NnXEM0Yylf/w4tAQ0u+05yvCg
wK+mPCq/91Em5ZiPcvKOHOdJBSTTkSYC7/n0QNniR1mBmd7+dgsFr5yshClYY/q8HngDDE/aNYfx
P9AT4ECjL+OzARXCnbTA6RjbHEjVx1ewIc83WIXkwbZjUYAzp9rYNjFdx68zjq8U1XW92RXAEXCc
AYKv676uVGq/WAryucxGApaihL/izu2+HGUsYA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30640)
`protect data_block
TGoYSUtq9QXorwtXYAiku5PRRrofa1QO0tKP2kJaj3QuzD8XFFlvgmBxexyLYDE6gDfD3y1MimNL
y+GFR4k8uGqsTU4X/c+yG7qWrgec1Z/r4nV+jBcL0IflUtTCMpq+DQitly34B3lyEm+/ewhdWbag
sQU92u1xDPqyW4Fay+CZNGjpJEW6bQ6IDAJc7vACSdWHqRQ6Wrr7OvEkDQEjVx6I5FstZJSKRDyM
kkrVQ7wugbCgqedvuZCna1k8+ZH7dyRcyOIbqwtOUx3+ole5A/bpTq1405Z8HHOPnnLBzuvKN/i2
h3Ik0stJQYc41NspCzWtUqxX9Bi28wMdEtl98p6niJJJspPsNRs/+hdLPK8mB93Edi4KWJ/uhRqS
yxZFf7LkvVi+N1jLa10d3keQqXfEUiWSaCDXPOWY79DklbnODKMFO7yWaBJejaztQDzeKsm65LPQ
Y91glKNdw1T9F6Q0eGTfDji1Oh6STnGcLF7Q4+ft6I3sAcFoa+GYAMcQrxcbYV6gPRP/sHvDS/U3
x/6yx4C33M5MP2lMb77YET1MfVMdENnCd+z/ngchRAtQtgE9fg5naOmX5BLqRMHmsj5DVEciFiRM
9Q2PPHT1Qjue1AjcxPnr77595F06MYAipT3yiyNQUYDWEWMMvCiA0DFt+QLyVZD3/1MNiyEQf3FH
Zr907KKaoTMl1xF4Yv18UQDSznABhvA96BcMNpT1h5esJcK7ItvTbfgEWeyOA5V5Yz8+tR8sci7C
pNVbCNrqiJGQqZeZ1EH/K24sMAXcLfjDa3GM1U2aNCNu22TYqw/XKixHntS2NQpSiwdvOmenWtbw
GivCdLZtIXa4ljb4VUy91tWUSdz8zAt2PbUiCBtSRd039hzHSdmTaFIewFsALp6CMFqAmkz50reA
XmQf5KrBDyqp5TYB41NCgltZKr2YxvAdTkIRfsZROAbF0gSraAulVoNdx4iHJRjXJtp4jDe5/P4A
ImbYhhVcSMmqZW5yilWcRLwAH7RsCrGoQt7Rnf5PK4FCKZ/HB91QUxs5jYlwy2C0brNaw3D6r0u/
aPjaIjX5UYhLBF+qrrxRiXnv/OR5LZGSUkwXKvfrj6kAae1s/up3gtdS0L7SZDcBWmvCps+zxhie
URaAurKOkd5D9miHbmFaJwnF8D28dFPSHcUH6O99UiuNgDbNHJ3QAZanYKOWRTa4sILwaHcGaAhO
4J1kYV58zGQJvk0EtxO7wqeP0ldw2qJIfrLOyT57CVvHU1yZeVx5YGakuNvFZSJ+JRtLWT/IuzK5
/k9qNfBfWVu8IoE9VS8TS5kH+s8Hjg5+Qyvvdj56/ZqN5C9R2BdDFONDEhVNPzv9OYQ9bZjPcLGm
7X+s7R/QMCX7MAgFk/KGsYmuNUrNdkfoZojYQa6jX503LHuaAzL5h4qUGHnbMKfqZN6QQNlwlpoa
NKz1kMyED3ybDh4pLlVxvj+WUM03tEEpjZA8UInhTtsQW2AO6/cAXDmA+05f/P8BZ/v2zdyJySVF
lqWiFxf6z/onF0Syr7rENw2MqlwysBHeRhhmtblDQqlzmdAQIiCmVVF90KuXeJcwx01ae7RwPOsi
6DTfuUDOYh2EakpUfAUqKekEUX4SrhSHXGEiUy198AvUQyTz0eOsf3WHYKH/yjasn/4n93pQ8xAz
Vl6qLyqCl1MGp4seT8wPilsm2U4MFNIPX4NWd84AYv2QtqLwfpRPK7UVStfosKqBNDfk0lOJ5OB4
FgfH5tIlwSnqlJUri1nCu428r2/9+Z4Wa3VttRm0szGwD7FSTcR2UIpJ8XxNz+SErXlg19nXWK4A
4P/Ga83z3IcITvwrGdoipK6FnLwOr4YJqyVFMYdzeTBbgnkIOcGDbhH4P+myKi9UM+e1tLA3Evxh
KAcFsV2qWFHtrwySV6c4Gf66w3IGbGXe4kiahq3XXSrBzR4MnYzEvCcPWuczjwbB013/QiXFxy5w
cTa2TWgJdieJaP1pHEqGF0Mf6npoWD00lz31JWqDpIJk8yEPB0wfkerXQmbSOVsgjbAJOqGqfbUP
hxBu8VBTRZ1T5QzCTgSJhSqhopqqowHl3IkRiZ7F2svu8sFjMbHaQvs4VNofyULsCe8G8i8Rze1R
YDtncIsDgERqpZKI/feDLTI2rp/Jo6JQ5bviikRxE2nWKFevLgQSwDD0wvB9eTBhsFe9dHP0lyjE
4ixjvHSZc9EygzYAFrZdkR6AgUF183PVKe2SHNbz1VdJ9HGcux04kk0j+Exib6rj00guXOB3bA8q
ZLg8Rh1aX0K96GB+F/jWPWP6n1vCrcD8PI1GwFXOixPr30aP8LQMWE9Ugyfz+Wvenr3bjF0lUlGQ
JMjzf3OotTF2mxJoTnOSEf/iL53/gD97k4HKqRniMrqcqmJ6KVmttoetm3VopYOaT1TNbpn3Plpl
vaViAQI6dNtQkJO27IF3bi/zJamZ7Y70OeP6VE6+mar3UiiU0kdO2sHDMiK9awHiZnq2PeaEtBiN
55KnxvUnN+p8SyagTY1YeImKTk2Tg5DXDGrpBshLvT9rBFNWwVE5UGLBfV0s2FbgxSZbdqJEyXr3
jWmYBeOD1s+inLRYM2wm1WmGsuqeOZqve1le/8Gzr5fqRhHkVFLqELxEnfnvdGKLP+wle1KSyslW
mVylpNhvgzE0utV6ceJk/yYDtcJXn9YBAfWhnQInYbAORTgcEDkWBC8jr8NSM5+3jpANsWDBZ/yR
gT78qJCAuvNvbLDCEbsmQGFg1518J+2glNpcE8RklqB6svX24Cz2uclo3n/bXyDFASgfSLEkzJvB
9oY5rca8NlYzoAYy9DdlrQ6Vu3GWRAmhf+QsP2HHp4QVL4KBH16YEeycvdYVpy8+AWKZUEOCQDRc
ge0knitBMwnOTbAqwuyEY+gfmaGQ+sRWeW5mm4M6br5HIfz/PHjS9IOnywHOkLHkPnH/jKVnv4dm
sA1HodHPqK3Aj3jl+SPoyGLK7jpwlbKrUvIylrctEx/Fh1idtsjX/OH0jyztyzNW26O46MqwABzY
SYsPvVkeLWEMgGlmyOztG+zxCwuQ1yBL+gzn5qqH4Umai0MooYuwfbgWaekV+zngNUSxfjnjdALl
M871nLkSg1IeDMJ7+oOpWofT3zh5kE2avJInti9kCY0Qy977RfsqUliyAmMy334n2R/ApIVS991w
HuAR1BHV70/d4BJuQi/Le6jbC53YfIa7smiPYqmh5L4l3eVcsuhTUlrXu/FCM+tddtGtqAgjTbDH
95+ajvLbGshRUxAqnfLyd5t6EplRzI9eScZ5Qf37tmPWl+RhKhz/TduXvOGYdZlP3dI6jZ3LrQ5y
yOaAMB1tATpHTrROY8UR+Fd154NjDfwjLNpnuSfMc/zk/1WLVjIDgMY6OAY3TCD0xi0auWNBoeD7
h5tdUf7Xa4cuIGwgwMtKh9T0s0Jy9WBtRTcOMfq0nbJ+9tgd+zPUp469pmYqFeyJIIgFr4k53E5T
CPAeWCu5dBGcXFJesqqidpxzdyQlpm8dD7T8gs1+mrEAm/xcemVe1ATdTFwNxKh+6O5yso2dTFOR
fKPaUdN5LdKJZbiXLnvJ0/lHkkDsxNIj9F2uHuKUfbX+Pe7GdPJtI9mkc/Mb0VLogkoXvUfs5T41
yi7yRnXyAtT6HA1X+8sTCmRxuUUPIg+sNXqET8hWH9NQfVEXbNpSbCtqJghJsQoErl2UeDmT8buo
mSZHpwlbp3CSZmq8f8mfEramnP/Y2NxlpPKz75gqcnqx55eDzA5IblKd2UAw8J+wW5/lNi/X+pm+
RjrK2oE66sU2MlF/oZfWVImW/BFWOj7BAz3cE1yXawUzh48T2zbcRbZAoe3T8teaBIh5HlEEWIZr
aK92PgDTI0Gso4a9JxEUGwiIaRKgyjgV4L4saDQpoeczI0n9kpXlSOpaiekyTSeevk+Ac05wxyb2
oM39FNwn8WmOnpjAS4J8SIUm87TOotKSH6gCy+ohBeavPcxsQxIH7j/9nAyxzCQlGxYtF7Q4xeri
KHCfRs3ryIkGnTmg1saA2HurhpCvHCUJshFbFHlET6mGs4OqBu2fnvYvrF9kAf9c4fPzd6ZiThZw
8Y4wqAtEvQNNcHVn0FNZ6Eb+EFrQRHMVHOv3LonoGbog9D5J8KGXPJZ+Md3hyrCCCZ1Git4sXxii
L/N2NTr256VJFqjqj3VrrewhH9vZR9UAgmjoKp9Jz+NliHpAvNenmkgQkrlY4nEMwv5B1kx/wtVY
yqJ/o7lFG+F4BxBlDnFkqAHeAV0GA7vYqaK2Uv4Te8nbe5p/Foehu/Klp9rVo9+sszy3ru3w90nw
kxKeUY9jp9OknHi8i60fnRsn9IWNn3j9F/MTinR5cNgQjwugr0XUv6Ec3viOS0mn7VW8qb8aCSjN
lQGpux65BrnQ6lYVVR5/p5B7WsEcjkcwwZkHmDgS8Im+AGsjCm5JcFNJBbJBiVfBZ2LnwdCI8G7m
vNXdMfqK+6/dpVATWgCaEZZj2pOQaUAlhDUKJOM2SjnGL1sgTwZ9BzYDlvT8k4rQKkQPN/igN0oU
71JUm2SG5IIHfd7/LK0po9zS+Nr6uw1Jt0GZJSn3+8v4mlPjytuyd43MkgOj3tcsGJR/k5SMqLUp
tNJ5Nf+Y1QJDonBnL+YWKnUJkqb/rUq3kv8CZce6KN/Ci9qYfcxlich557zc4O98XiBPOcNdOzGh
JoUKhV2rT05NfrJRGt/pNibySgGKkYSZBDMva5eTI3L6DUhhXtg7FZh8Vp14KsCe+IC5iuvmcvTD
6c+IdCQfAMiPidWrErtl90RX81o5W+zqXBdfmzLpWi/aVF5gHUF0mlGdUKvjjagQaFcsaPmAyEbt
lJHrKShj05cr3YYjCll+0m3Vj+jbwWdEUuplOb20HYExLwJJo4QwEP2omT+wu0rd4/7yHOjKVF34
WtBc3K4ahYh6dayIcJwic6aBgjFWbFYzaIwQUq/jiX+DF7AZHlMVatOiKDJ6pMhsEMwR9vCUdVSv
6y3o8DC1PthJm7io+7bJD+H7ubiHyLs+3+fyX2Rl3GkLtjVYBw+opCs+BjBWJxxormB4i3KatRHK
dXurWsq7g4ixaHZe1fEuWDKQEAy6A1qNFIHO4MN28ZltrhzAdZ2FFWU8KxQJgSdFPsC375yz70iW
FR87V8uAWnXkeqolZ+4lb9E4mBihCm1Eypqdq4pUK9E0HMvqbf/+kCZNgkq27NEx75aR4ISwB1iR
yXX3Puyu2y0w/PzeY70DQgF7mBLMxsHAI8I/3eCor8GEBVvGL+qe057ZeT4+bfG5138ImAbgel+g
q83E4TMUtNmVQbtrATA0TDmKCi5pkhfqvsOlnNVzCBlOfC9Xj2JVRyyR/hSMKtQonEXOEmHRpGRB
w7KNStcdz6wdDh+8xITFUssnAeqnkAheJxAMLlJuqQCTTlyG49WhjXjBhRopPSrKRz6067ky5ZBH
AGajA6YTodjNNrB5ucOp4jtpzMSm7LvL0IeUeZnHnbIKNO2XjU0gsGPV8mghzjQZTsZ1HsN3L5uj
y29CxsiRb/pmmnUA+RX51e9uiItoTngPJSn5cMqvkYOCWUC729xmUqB5D4ssHZXCQhUVkkVxRvTv
ivbXATJpUmfYoAubq+HwKx2F9O21Ky2kmt4nOD/8EApeVTkEgchE/p1YLT/T38NlDSsEzaKYQeCW
iUL0zSFgLseNbQBUwJE/B8sH9LAEC1pO3Xa3psCF5oROyIWrffkJcE+G0iAhMJnzFhxQPdKE35T1
HTPIDoO/Kiz/qKIlLWLFccGieF10JudKFl1/aFGrPGy//4h4SR4KUt1nWFy1lkVLB5mIUtVtHdne
ki+gE3/kgRz86YqfptvlLLvOeXs18aQB6w0TZYarvYuphCUcRBlVVZXHUQiCuGPhvmXDF552gpRs
nFs26+qNYYsK5vPYTOXC32bOpf2ZFGserZtB5EdzMhKJUXSFwll/RiApitHu60VUlAm7PofH5HW9
QxHS02wKVU0AbJ1hvQVPpaTlF++DgP7vFGNzb9cWjOBStSpxCWcRE3AHCiAcn+9yKR5tdDapYss5
sIuCBbrI4LkdJzgJeLb5FcCl31jbXfRJfLK/w6i/kunqsBvz5iZMB1O2RIlzhcn+ch80aazjR3wb
COEpkhUiAe79zTb74s/NB2oO1JMnduKe4FUa+UHRI2yKqHRZE3odWWxc19axUVi9lkwK+JGb8YfG
sYvM72lP4wKdMpGLkcQ5ViIW2a2TVbxWYd/CUKLDcV7g23+I1sP9G+AkwpbjZfSKUrlXryJ0ddLB
hjGo556eBsFegvE7k9Mbz7rAahlkYVHWQYbdUXaonO50ExdPsQAGFWiP9Odnsso0Vh7RNffmj6Hj
paXR+XuBM8fPNv9BjbIk4ZERi/ZQALCP1TWmet0v7Wp+Gbze8ZAbByfCSenbSsq4L3tl4Fkuewvd
hUrXrO+9n4kGNcwcAvJEZ63oEMI/7h7ZiZ0b+PO7UoUIqEGuPlT6/5ojvqBqvhqZZ9n3dr/+XlMH
UIy8N0tp0K2WHTo9QwOLQxZaJReaRov6ElmjTP+19vKtL+fQYUbf7x04j24/iz0E3Bh63Jz80oMw
7O/YhnzfM337k8bfzNwWcSFYpQmYm6xn1JIFCihbpCSWFQNDHxF6bNPx79HxhP6i9OXq2bvJn/im
CA2GUXnLWb2WVMMUH2msUAm9EvbrDkxgR4Wy65ivIj3hpC4EdiRZywKyDi4z43xiO2+YxSZsRvo4
M0nj5huxPJVYI5yu94LGNs5xiNB7LyT5VI5m+mazs702nmBJg6Zs0wIB4Zh7z+etFd5P+P1405cV
N98TBmYpyz0+E8BkzT4j0AqqJmi7v6yqL2VosECHytAmsGtXYps4xH/y0LvSDApXc3X1J2RhAcHy
ynkVfHBV2d2wn0l9ky2JwboSOZghQd4peAUUwsoK+54WI5qrCU8oYUmjNAIszJlPVtrzunTodBTr
Dmw8xG/BP/evShahEtryAKqs9FN42drmAT32gnY1y4i4RxVveazgELV++vSQqdqXJ7UXRKq49pqw
U0T0fgnsy2FPv+/acDaLHLQ0YU0LMmprZhxmjcuwkbDhMg/r6zVv5i2VWxvTpJpFnmUytm6cCLJV
ZVaBRLsIL7JhWMunQwjRm4hX0PZ6yotYm1OYCFnDWLUurL289yFYQ8J4xa/UKsTJSl6ljRxIFivb
1yBYsLzfwO6eVyyYIBWRqNRcMjPtMeRHlBVRQo8443UNdQc1Ybql3QjPEP1/9rt5PnFaEktZwOCS
pMQCHKGxQj+RlzOndc4l4KB6Q8bazUZcNGWkrLf9aMpIUqJuLWGrgoILroiMowoi4NmFAqal2JIr
T+GYRKn27xcF6pEAz2bNuB7itWcae8eGEtNFOAVs9Yg+bqVLDXt/0Gn/H7Hl2CRJZbtbvhF7QK7d
AcK7fHAnWZDPFUMjUYcTJTKmT7Bxg9DQB3gmdDrm6EvJ7ERI8xamYq7uZzi2xe6zXNtaZe0gRwsk
kDGPxOel/8qh/59FPOn6i/a/Q2KdMI40pCg6Ms/xoL1XkYjo6b/6ADyiAmuaLC/8qvNg7lyZRCLo
lOxw8Yh3DErNmWop0jmoSHgz7GrozlmiDpHxHtdYK1xLhGMQc52A7CLyy+cZGFneBTj/fO13doZ8
mfu7D+KQqxWLuKVCNRppCAAqL3zziPujlLijRE6X3QyA0wX907m9/HUhNJVg5TIv5njZGAueHxFq
8dad1eK171B8Jj88+ROAme0jWs9jlSgplbU4AEU/dfylM1xQrlWyfNOtzrgFeeOyJ2oOmMFgFl1L
5lLnZfB7ww9KbXh0+g/eojwEuhcem8J8AMDl5151xwNJJXOYhPmrUbJGD/tkN8dcsY/5CnQJmBPt
Z+IS/Z0O2OXovOnAgxTpeOHI43l3l/Lb71Y5Jni5E3egmkW+Ja6ZuqyRMx0R0DZ92EjyPPyVMyHR
NYWkB+lDHt+6mkUidgYxxt9RHAf0uwhH2zNT3A8JGJQI8CZM76c2cBFkLgBsiIfKdh9djuF72GMc
rxmJFspzTlT/Cb4fKUW5HxGqYUWK6sCnI1hQNBDxtQNG9CLzeXaclw7+EZffOAxofg1+uJrhpfRD
wMSfZJkCV8xh2rG7CCRzEjPgwV6wK88qlCm8Sdt+/ZPnsvmfA9w8e4JEB6pl5wyOcZFiiBKWr3eu
jkGFrhOnwZHxs6k50xAl7dGp0gYRcgV8uP0qHQbm22bOHnu1ohbvMHWbjFg9+yIzYoygQlEvL5n/
Ouojl00kgURmTqKgxQLduDaYHsgDu/jj/RZ+EtwWauZoBxeRrcueOISw6XQPBzrVl0xqEK36Og4q
gg4LbG4UMs2kgseKE9tVorAg/eCO/LsU/CXZcgoEFQRrAxA3G4NpacywrkWdzp4r6FZ3kZQxN266
NXzDh1JkVhIp9HW3b8wwG89x4FmOOVkZXxUeANzyw4pPlQMuBjHYPb+Sg7hAJdA/MJpb9koOlg+5
nAB5YELjVC8HEZuCKI9k5xhLAFqxhnndL59xifMkEWc9pwAMuz21KQA4Dt79DvedYRY4xV5sM9Bl
pe9iI1Vfrt4/yMkvLoCpIARN8MpEGf2OZQlsieGy/h05kmRF/18+Ozxll9sN1fTX5FDKd/HvExTi
4ed3QLkIyEBiXCvq3rlFdR1lsU1/u8z9PhZWHgrnPlOcavoDLTSpI7wEKIitRVTMYT4kW1I1M22Y
XKWMciYGomrKsS9z8Vcwe6jOE82ho5sdlDjElJLfhKc/QF3bCBOXgOFl4nUBb7zxbYZ9M5tzZPaT
rHVKJYGt3GxEHSyN0jcTWzeP/q5M2KgdUXcCAp122YZEMDx/DtKMw4ehNJSPeOnvQFRe+97JRcCS
jnn6DWL8wYKJsg8LfhlzOTSFEUUI1ysT3wJdFa73E0vFbIZrIj9juKKttE1ldywfqJU5+yiGT2nF
y5N6iIRw9vYJIoPte6mHvWlu7Sf84gtco3s2IZdE8YxUHAhfA6kMZh7sEgtxhFiWgdb4zPU43rFj
NAuw67zVorjuL4Z2h0lOXyHKgWokn8ZYpHB9kCUhST9sm9kQiJffrWEFcLnjBGU8aZoivQxWiuwc
tkHfLUFQoXSdc7yBB9us+EDxCtgmyEPy0AU0r337rTQwCXN0n0N1fpAbA2fYnIe5fmQmE2OSXQ8k
QJrxJ3ju0TI3UEEY7RobS25NMAT8ts25YiaozvA8GOh4CStLwnJdAuAfEpAcppv9LoyTon231VGU
H3mmldGPcN0iHzitwcmBYeADiBksPN1YD4vItVG/rZGdf9J0aaY7PykOZ7IrjelWfm+r2GKuJ8yW
pIn/QrvyBeX5A34FBr/DfyxhzQfG8yHKu0mR2XmTJSLqeMIpEcwBayiMsbg3ndfRaaO3MCq20RY4
NVKAgRnV1O+OtUGJJYhUB7BBm3b7SNXjFAaUzb9KDOwVV5B4NDNLEimPxWMTadBnT2VxPrSUhOY7
ezjSELppxST1Okxzh1rDnWslq2J2UziZT24brOqnsKUDNTHIH4W3wRBa2pcGd95R+hz/Ev1Ig+Fx
Vi7nNCJlgGSUCpVrwXAQUzdFEk9YqM+5/kgp55D01+3kRj0sPzv3b+MgPG4Jo4bzJJW9vFXi4Ww8
r8sIayL840HWII1kuN6p5p5MPzZ6TaeZP9Gv0LxSD3lUUutJiJbbUa9aSk5HRb75dTPE8n3gkuxf
ilXqzkLngGDlB4zuOZXylr+VYLB0rh+8i2S30RgMHyd0VGTWbOj5eptQI7gcyI5oY79km2lp0vAJ
u39R2kYooC1gnR26OWa7IR13vVnYt/CHh1B0sjLvmOEbrrCzSr8UQSMoBW5JeeyCifs54vyBfa08
LCiEnU5+5h4S0ljethY8Dl/Ri6vb8oSyMSYCZjnZCYaTekqzldN6lY9/3//9Yr0PAhY8xXnGSqx+
1RfUiHjYVQXuQou1+HC09cykPSkQy+QKAkTaEhBnpZhpAgoGc8SqhreANoWJ2mb8cSe7yo7jS5wf
4ZbqNgS6fCp0qNNi4lf9PIO3QqNHgnZqvKRd1uPErCsBPNdxHhb1Dlg8EvwVq0Nn5xEqIQ/ut1/D
4SpjYdHBmDW24JLtD98uo08D5Et6eyuloy4INoP3t4IgTbZcCO6iqqCiQ3g9cjvt2KYdCg0xX859
ZZa1dXTool2QrYYujfnUMHsnPsioTQLh9dQySy0xpj2fqKpGWl1Zzj/InZbuBVsHsRGHQqAufQuL
Mp3K4JsArcoqZ6i8P81eNW9Yqsu9wRYGQ0VwkwaMqP+fdTFYGxoemmu55WleUA3kwKmv34Svqu1r
AB36TYk312qJL+1U5P6IUyVh/65AFAjMJSSJKrF+cLNtYhU7ohjjn7E/Yo5ae8UvWwbneC4LaJ9t
eNOPOjKIeIrHPVUCJP54LMkDDrPI8xEyqSCDKM4jtHUn4XzjT7HLYfUj6gMtkrcCknnn7XPiEbbr
XtC3Q/jeTz0teyw0vXsDPYyVUPpt8KujbQ5qHCcyFt0xN22OEs0b0w7trMs7Zo/doEc8w5JWXjig
QDCwI4zN9juOmnNopDvpoXlcFcEdJpiuzo4gE17QpcYrmeGvRx/SZPqJ1nsEl9wTQZKARML2w9pu
uPnjd5II+uCx1SVb9II4q4PhlDV6LZ281x4w8iz+tPr8YfSubg2KprUU06SL91kNa/vOyPN7p4SJ
e+ScRT3e5FCfHlspx5WqGt5r6ucybMetQTksX4lpYkJhDA726KfPqH2QEjpZo75L7DZcf53HJXQq
ahg++BnFxEp+MOMDeTiM3H/AnC/gojFYf+NRiz8pZl/6e8IONF67hZjSGHXYM9XLP40BOMn7Rv7L
jXMZgDpv6smKVKlsjZTXvpCEaREWl3uhYN3/+NjBCtmAfFbuQuVsUW+lwROm3GBoAwEX8DZ4HPBm
iZRA42zUG0KsaDA1U1Gf7+JrkBflXiCcZWrlK9cid20cUKb79uZ+NPzjQOlUnRivOUlZGOum69mw
o9bVM/17o87hkNd+5D6o36gC30lIXDdt1uwCjGlw6agsdtPHCTIBG4SfqIl+M8hzKY/2JKIjeNoN
xBsbHpsVXBlV6ZijBEuDIhWpgYFiBCtVtXxNRMtOfuAxA5u6ia0wF/uGAndAsLVovEYrrQKNWSkH
V8lbtB/JzLrOGM/Vc1v5KZUzjoVsS8qTLymVGrZyytAH3y+O6YuGqj4l21EQpZnn8cDPlNgukmki
f98x62qzg4qPatKEnBU3OpY7vNS5HzXgYDqtJKem5lwQ1jHlyypq1q7oy/mwrbIE7yLpxI5qbb+l
KWOB+gKrPpL8HXBKQpMavvby+136p04XrjGGVSsiIh/VSi60L45bhLy6pijXXGyefhZR2+sT/J6K
2rbb4I3iqLATPm97J9+TdinJSaLmJEMyFjdD2dOPqxeFdz9m3UFzYyfstjBa8mDdxGENP0YI0V8m
xzEaXmgJQr0YPgUqssMYRlkEyJm4U61oEXuNyro/J3G3BC0PuyQv5fwlC5v3zuFMyLrJJi1B8fXs
/2++SD958Sk0xGLC/G+I/PrYspRT7wqdTNfj8U6C2ondc4hRvJnAnqIiW5bMnE5k39T8ibObDbxv
k/8oPvAQtAyuewFciqi0NAtEVgPaRdZ+ejZ91z1D1N70t4C1n7TtuMQiuBqwoQc3/xZur19LuFUG
uXeYDohsKjS0Oawr5mIABa8OamOrJjnvCn0p9clnnon15s16HKG67V7rYYvnRbmQLVY9yWMAzwKj
FOTdfQi0Vbkkapb4dHXYdt/H/UtJGj4EQtRfKAzl+wxbWAOhV0+8r3xWwZjPmR5OzGUQRPX7roJs
Q2owRlXJt01eZh8dbEteaWpA5TnBKQdT+7nJrPUgAYcEQAxM2h2prfbpwv0VIHNa1UMqFfG/P6vW
OJmL6eUKwDw5DAUlFWFTfJpJ6zckzPi1cONRWkMKr9YcH1lcA4OHQZ7MB4e9V8qVlhWwexOTj2co
ZJimIBQMkHzORpDxRBhN4IaxVmcGfDZMB0haB8rblnxIKtGFAlxOk269nI4slWvhyR1R8WFWVTUP
GVRfak2z5/8mX6nd9c8gp19duYndNobRCPcIR//NT85mvfYYD8HljwzmPXsnNIFHOzQ+a1fg62lT
vaRcO6OwWnSw+zK9EBijvJsUaSvFv2/oaI1nYJE9eNVBhy3u3Bor7lvzeupqd/nBVhx65ueILiEZ
kf2DE5qX7zIxx4N1xnAJyndThHAGHQKq3uKNEA9ao11fxjJse4sJN29e4rpe60WQv4wmIZcDkv9R
2yzgQDIhZWYE/3GWDpeUUZNVO45LHrqnip/wuGWZuXntFnfZE3UwRJoSQxLyYQ6IiAokH62cFtrL
cOL3exG7yC3xMbAt3C+IyOSHrkajhC6xIumC1y/RYgB3ydhy83Zs3pn4YVruhwvxsOtX6NL5Hg0/
LVXnOeuLxlO0CK1X8iTQaF9E48zrUPuCWUuuNg/aPnPLTPC9eZ7xKcvp4kFG4YmYNevPTjcL80Ve
Gzox0jXIXx6YhiELET3hG7EmxJ3Q9UBpqDpwF0BXexmRjt5IWchDImS/c0cmOr2nfAwUvbOygUfn
Jq9jDhpeC+r/Wi1W3adCvAKhFeIa8ZrIpfJ/SLSnmhWrr6BnNmOuqtQIZcUM1OXb7sbOIuRjgs0l
lV4p4HHklWug74CWRUmgrEJBlLm3FswkqpjyIWbGhQlq3fWIAWvhcEWo7y1CPZxhqV4TEYBYVrSN
UApeqNnAW6aJvlgAIbQZjvOC6cU49vGdlooE1ujBphGQtZDcSEa7X/ysKa71PAktVxBrObI7uqD1
+g2NuL6pxbuuNmVaIwy9Gmswdp7Gc20EdLvZd+agwDoLcG1ASC6A/7+3QpnonfnNHy1oQTca3qA3
rEyq+4mepyZjJXFNVhi7/p6yxY8T1Rh7nTz+5T++NF8zJ420Jgk3R40I6A6072fG7aPZZAQpvwWp
PrKv2F32zx9KLKd/+a043rUVCmPIeVZgLj6bMiX/FPOGQ7TNFfrNv/iMviEuvZNQ3qlIiOj9JR/F
WvA9MywpBKq8J1evhzjm1hBNEZIGgyfMxbO9tuEg03nt6gw7aU0Svd2WvQ3nybAtueUTUPvoJ4cX
2j4SaiWtcuKo/9zNr7eTndT/1r+j8f6xDJMU9XvYDgY0a4YL2xnsky8SZbrsilbvU1fruKroDpKu
k4wJE0oY74OIjfIgHcHJphJPZvhnI+4NS5uKo6yaMjG3TI2cjngS0ePLsZMI+OPDcgwYHHYzs1Vj
pXgLKVZTuVRIpQlrK/a/tMJkHOvfKpXDBMuhuxfG9Fvai9+mxMjjMyC3A6vyk2B6zRSswRsAGV4+
olznfpclD/lbOv2HSLBrjePUegwabQh1PrZMc6KYWYfnUVarLBulT58wmFUEo3NqrB/zygGaKY2O
F47hFdfurcjy6XgL8RYus+ZNW704cKwhQCw3D1wDLHCbALNgVMg+C+bR15oAdOrlZwzRMRZv9Jg3
YuzsvwAP0Rrq4X/XWKq6qTWzcUxH59+zsizBMnItQt/9tXPYO6iw/umiB/xdrXkRbawFI2XczDAv
bdfzn/mhTzM6dr7J8+lD8PBoL1D2TRrUVQTpQ7sY11nHgL97DnEZFZdWqpG68d3XKpobACZP2Mte
jppDE3T9OOD+jpaq2R8ba7C3uwTCiK9Kh4uX+uRjVnb7Zw6hhi9yo/Nhj9z82tKm8t84Mu7ByRXn
8qa70XHeqx3J/OgvxBR3fi3/KAMp+aXca2USfwBFcWzHsC3SdAIG7Lw3QV4jAbVpmBOK0SVqWE3Y
9UBKNhwHsSLy/nA32jsDjQUYUQDBE5e35hfgdxfl4r5FqzOVAMN27eOuX0E7mh0pl5JgLWAyvvwL
uVjdan2aRpQf+4NqRPj50x807hoBCTJYziEy6sZbLMqGgKgVkULOUCz433f1qyuSB64Smf6/Z/pb
2E/NQnHc0OlwA8/fiTpmO1rJhXQur5aOhHF6/JrBMVDjDM+vd/B/GxGr02vWGo4S2vNBkhh1qBLR
YZZMwV0cGYYB7RtvYXOQxuvYLrxURwxI7FHkAeZnMB7wGSBHqryJ4b9BB1dUzPHYUzosk9CYvUWg
2Nx4A+JEm/i3107abP6ONhfMMPBlnvcQfGL/TFa4RcIN4Zk8XsNe0FtP+DW/cArZ8N8wXC4QnttF
fiXKyY0gKb0R8iVk3pXm7KHBhWUTVmwxscRwHnJG3W7H3MesL7HmS091FxxE2jHIjdzJ5eHOscT2
kEEGfQ3D2eeL0gS3OQzKddiN8N5iQUg4D95Vx+AG5FHzOi1KhobIO07cT11cCo28HtR6pvGqJdwj
fjnb9zdBSdtZyeoUzTKVcsoEokaAYdgNpuC5Oah7v1aO3ic9tm6aIX8PzTaaxAQZPclLMnQp5+Ja
rbnISugkCcAwvUqiNATgAKDfqlzgGMcWtM6eOA1hU0gECfVNc92UkssxgRQFCd81j5j3GoZJ0po2
ov44k08SRTnRsmWb98lym8793srV5xl3pS+s9FIV5oC5U4m2AlyW4r5S/aPwRfiEcjoAm9BK0Dan
fm9KMwqNLSAUYUychFPThu9rMEDXTkDqeVEZDmc2i5wDTtrtIdDAyLrf3f850So67uoON/egsm0D
EmIjJzetZoq789xUMfw7utsx3HBKKxLEYWkA/D01Z01umEWYdnvnTKSbFAWXAm9IRkXItGyHLyYe
iZv7n5IEAWmFhtmrz0DM+eP4C7uEfcAofjh/kVEkaEBfPAeKgfMr6W9jMlZ2mmvAQFmc9uw1x3E3
E7tTmUhKurYqSzmBUHfP34UlR0wn324orTozeuiaS0fVMiohnz2PscCYZNhfBJuDveYt5vzImjXO
pn7nk+pcg9vnu0ilC1rHTFz/BIe1cLqj0yUjY6/V88ZAvS2MNA9jU2RiVO+D2pUAfgxe/7BXlCVr
pEslLJmNFncJiFAO+Gz6gWaqU0zcDJNELMwBF3lv7Kp7xfQgMwvEf5p+8KIUKl6awYWciMHiEFcJ
Ubd6qQUX7950Dw+9WcYsiSx2UgDttFo9PAJpY9ZXpAIroChhElKgCT0OodieThT5cw1v3GUQHOFQ
kcSUoyGTomggZ7nAusxev5mx1cAIsl0SSzxIm/oz8Vgestx2sMs5D1mNZUZ0XzrKkeczRUcHW/Yz
yQszcgqNPTSWNV1VaqwGpTTJPQpEHJK72LRK08rQH8dOw48NNEwU7eqGwZuFOqc9g8iMOlqAdTjJ
TQA/NGCQiTKh2VU8O++4dKFwL21/C542yUNGVZiPoQU/kKMO74vfW3Hg9krWLP3skH9syKL0GY8h
RSgXP7DDN+mugCeoiNJg81n6GlvQOkz4nCR6HEQcvzCfXlmEfkMaZzcVJt9LxzFe9+iGRb3ydtYZ
SMblEc6buNH6Q8zSgERsAE0ZjvWybmDheqRz+BBPqZw/164rA/Jdfngr2av8HmXqqn/zPwxu1lMW
FOqRBTksxN+VASCQDRAhcTUqDYlzUejXF1FrV82bs4Z5huYXYdltvfGciqXyMEPuRmRo4z39Ct2I
Yek40cyu/5lVFeGy2m3d9ZkHcpxVBW05cI4iYtOUUhZgq9rzL+PCChZ8J7xfC2Kl6vAqKEM0VnIL
Arq3KCmlj96/c9bSNhIIl0PamWixKOcx/1RI5IPz615X+N771Kg5+RE/MjXwXVVkTBRPdiz/er7K
87NXNAKh0w7otpcLeUJBe/1/ScWfJZBBkJP9hIFzIAYtGQYtxR8ctIOvO05uxvb7ua+xG0gU+Ted
ymjmJRnIfJ5oi185GeyP8PNcC9Ldl/CEL/tft5N4UZzCYBnvnGbVqyUO2g3s7u3HFCFDQIVHr7rs
8r12W3kNZzHFuZj1+OxpLuQ7GdkdAH7tbLQusFf3eBn4Ld9vpgQLayxrU1P7jKAAuzOddJa8eyNs
MU3dxifBjugXA/jV7/tdpEPZ4aQTpMksklPJ21GWgLQ5qcV3X5dj+ylscUzzUGzKWFznAzariR+5
1TEGF0WEs+dwNPBJ/F4iJwLuBTUhFuZhqxJHtZjZyW5mmBU/Jw5kKtCSFpYw6Olzg0EZJCRhjs8K
O7QY/dv1CSiOjTVmx+Z6paFZUrPwN5HbUeRWV+CNdaNwrSoRRsXZq5zycZrH4172k+GyC/XBt8ow
WAcjpKdfqHcgMvHbi7DDlKVHL5st8Agbx/szXlIJfu6MmsJwzNxxuzvg19ZryUXDUkFoa1Q17Iqc
KCs4G7GlfYUEhNlqgzwENNaGiYu53plO66DT5NYOA6Cv9miGS1XKBI+wxXWqtC3bSvJ3/Qn/GRjV
uZQdwSRA5rmSLWCtTGX07+a+us1y9/oe52BOOufrs4vb9XIcrDTeP4cPm4DUItOFuOoYooC3dQXO
fTwA977v0rLE/MNwiaKdJkhmmpbTJm9jsBGDH+ULmxlepKglH5bI0lGMuH8GUJV2AvFtaA3cgIyc
axP+CUJdQBexfkffZsf+DNFmFG7sSyuNvjojK9ipkpOl0b0UfUrHnPJVV3RoZxN58r+dho9BNBhV
ynxYDldRGDEAsZcHuRPYDfUxlFCaXMN6/4jD/49TtFA7VXJ7troq87YbBwVVUuM0ajX3rlfIbNgn
C/4eVQ5hdlmyVvJeMRrDoCIu5Oo7je2VQ9eHDZezbLOKn5OFuQQcWz94C+6JMemE1oT8WMuOKsd5
EDRFC645Ub+8ifYBsMsugzV8xOorlr22coU15rkPLxsihW6rcl5wLtklu5/bdYEsXxPrAg1H8Tqk
8Ms8ugyhSb71k885eFgI68Se1ciU7sGCFtmofgomvPWDoeBXFmkzcWKPuUwjRyU9eekpbj3R+uMf
M7j2bYJZUOAN04nrAEKvdkNumxrNgRjMIk2vW6KvXO7Q4UX6346i9/KRk+YHrtWHCW9zeQ52LKSt
uzr8i5lQBGBei+Lql9Ca/WDt/ZGS+poUcOv0WyqnARiK/Vq0ZK2lrvvdalXgHcZVp/qWWBdhlCBL
VZMJV47gGz1Ol2gu8piZPEscWy35YB6vr9wQGSPzLYicHdDYk/SLsRSJm8Ut418ny+CkPn3Kg59A
I/9hWmem6Ji08RTAOP78dTFPHClHB7ARzCweN7Hq60xXmxJYV0Hs+/8UwzzS6/bzgUVJdvIXsiFJ
0lifsU0v5Qub5adsUd/8F62QwcnTmrB2KU7H+9L8SfGaiKRZWbkZ0Lmc4N0XXb4FqkmItjEGFdmN
vTGHEVDjFzS6x78BouPNKwVv11RVBlHTnqpvIJv4B99CD217NltZ4KIpTHqEr4hI+o1NLusEud3q
09SYoR31HJTouuvPXsJCcYkJlMsC0hEGWFc5e4+w8hLY3A3aB6ASlUFjrBGBB2UXR9mB9ikDlTyI
ccctIaDW+KFbMELR+LqSVJyrD8PGnp3oEKAwIr/dPaRpIMfe9xC0tOZNS/AKBfkmzSRPHJH7QXaA
DUusnh1biVxabnWrMEtvdFWfJv5Ftk53CU1TRM+zdiYuPCgK84pBMYXsnkF8qyMLLNLsxFsEj/S3
Y6IdAdLfyFMeHgNOXpl/9ln5nEozxROUp47RyVBdhyk6uDZTIVoCq4O3HnmraKpkMxyseIgi1yG+
YQ0L7EfFCwZD9MIETGTuIc/FrryIrOvis0teaMul4DAcIJqMTlzFovQRqh1iDOf1mzTcT3wDf9Ie
qZ8zdFSsFmC71tyygBsij1NvYtGaqGdy3QiZdVHCI/TVCHgUJjmwngsuoIgRCBLIMHgevP59UY3l
+l0drfy/R8sQ7NhxqY9Gm46K8PL07LJm4kUPQ/97PDAYwGt0xzqE00q+2NfLO762VEiPGtY6c/OA
g9WsXCEHTvWm3N6BHiLlNZLRRc0UYIfX8XGHxcjeWHWYHPSDx0EQfqV5yWg9zZrFOds+NfxGy06C
tB4+Zmvbzyed/x7RwjYzVAmOKALafH87fd13luC454u92aZ7QQ6kUUttPpYaHn4yXrFEr5C+LRIc
XScPXP5XQ+6uhrLNMJttnyI4uG4/rZMknLAf2w/xF0cysxVcfoOnhQzW8UwtGYJdNK6UnxmGXZw4
ViHBkFwSnOG20QUet7N6Hjk/A4AO7p0hCjWdmGK6/X83wnjFRs01PuOr4hAyuELxL+kXtKRn1tGk
prW9Ex9aLlv7IgABcJxtugFYQUnWrQBTV+KKJhy7VDAuIg7XLAOSeYkLOsrXrbIwnTxQeQnqleuB
vPXnP1fdnznFMmD8s46UWcrXShnOmLZAzKv2CMsfdDfK7SdQIif2ct0AtSZ4m+NU2yLKOk7BeSLy
izMEFGhduj/zN/FFPPGQAgD7POsazwRvim9M6vtMqXPr5qLHvwFlLtdQOyK9nC2ah4MPeS4lbk3O
IPzGxnvwtqFhfwVnqoE1IZqHOTrOJeNdWYbWd+bdCV7c8hL9m2Nq9K8igq2QMDFXMfwPTmkput6l
ojn7D5VFfSxIZymx+fFXzyoqCgtsJLgJ7VfP8e0A5CaRPhNwnCs1hpS5Ivt717cu6I/9ga9XQalu
ACsf7A14OZ8P8hF4iAhccw/f+LL5uvAzSvpQiZDwAQgACwxoOyZBelt+aMNylTdqoQLY+O5FGk9/
IrgkW52gElixWGWLiiQqH+fsdcMkV8sacdX+K60BDhYCYFXcsuy78f6sdknSt1ku+czmn2v6wQuQ
FmufSYFBhRUaz+/8MxUXXHiXWfnGyVp6/thTg56821RKSlysHyt7vunC3VlR1TZUOa/GT2k7fKm6
k9Iyz/nHm4CKCcjVJhoW9aNPuD1j2bWHX2TS9N3XJrV80m+A5CoJQ6h3y1t82oIYezx634JPGe3t
XqDeF3trcrcqIlBBuAyf5H/1WI9vfQxw0UXStHlP2zMcWdQKvT2JdaSAC9RchjJMvmE8clhpsuUT
atReYo7DM8m0/E226eWXr25orDXHtonYw+eN9AzVUQMqE1P+LYhvJY4k/3jxN9qC2uRmFMbNey1+
1Niv/xrUadmNrp3vZMKep5RYPys4nTtUaeDaptSCvTcsTFfKNP53CFJTWLi9WA3f++8UvabjFuvb
G0pwidFFuV1hXcienQFnwjfhSkZ4veovTEwdih3XPoLAlQ00JT13/Q/Ez7APiUL7jmjZNHZK1Io5
UNSQBORWobuPVf4L3mZTL6w8vhgF5kdhSxoG+TfDYbaXv8aseVn/zzSN6LuQJFHR1UksUHCHu5Hz
Zi7tPLHPLt4ZFUNhMyeYOXrzGqqNKkFmsc/2D3ujGelCAHeOj3m+Ecprvvy9vMitTWvlX0H3Kuh8
hX6f4lCdgymD8mN7MBbe8cTVlmPld17CVCVxGFGS5Wr2lxC5WxR7L+o3VBtP21KZ6wGRnaiYzDJc
LHIo04MoGj2I+bhCG0lS0qgsyWHo9XWd0HcQo2ck0Vc2TmGAZX66qUmshVpGe7iXLJi2mTbPMiSs
rBLa8M4dMFayiqbkI7Qc5LsKdljUfUR61RDeQ5zQq62LS6m7p+v2cAZ6Q6Q9/FsWHxGzgGeVxX4x
uSdWczGrtY7OfZq7EVxHQ3rs33C4HVOdRJ3IK9vrakHafeqcEfbArc07Y8Xf8CBKvbZ0/mHrajFA
bLh7tCSOgOTZT1sfYLorGr90J1PrtV/3GWtwZ0MLOHMwzG5uKSW/g5uYMhjhWya6j1jVqC7b07+9
ORFPGYL15ovE01ejzcwzNqQo13J9yNj1SS7skB0AKRElrp2EhzQuneLM/72ayLnHblmCOcdp7FQ+
Mgbh2iVGL9LkKBVwZ9mK2MkV0/j8gyAcYMVNboJlbk+10sCjp9w54s/oHh6pMRq51v62jBIIiZyh
4xJAYY1xjAoJZeUz19HWG52dekGx2NR8ox8NVo6ZULH0J+e04Mfn+IFQImZOdldOMsEFrGuUR9Gk
PwraHqk1/HrZ1Sc2I6InmDfTiD4VmeLlwUQ/1TKIXPejuQd9a6E/eJ8YtcltjG8pmYDa6NjxZF+M
8/9k3Wn1l8F/5l292/9z6e3a28dB6cjCE0+bRnGYvxdqc254sJhuD5aAtJlZW+4RAJEnipWkhwl5
keyQzvWUHXgY042U0Hl6rGbvYeFED6ENcXiRT3EInmJ8dhZmWilSuXJFk6PtSry3uuUktonZwmV3
fykTLQXRBYKJtj39gumV3vALvRC0QfnjDA8IWCr0hcYIUJlq8zPo+wW5WMwoxW5G+LVbckaDQwea
N2qOSIIHG0pN0M6iwk2YRjqMn1xIYMPpe9Z1hK5AGR9o9BMVkSczoUFP6M4lJjUsLGT4g/SH0HDn
0kFOhJVSbg+IifsDWVHkKzte2UFvvD8kXgcjTwNn4+uvQHJm7hUkG8siuRxCNrQNHY2F9lWaJuoV
OOyRXjv60+ahYs4FnKRmT4c8+6D8rNMbjv1W6V6GYKXs/9ENWvc7V2e1bGMmXdUH/aDizgT/2QDe
bOnsqwRc0YKG235fw97g+7BSpExQKrUxJHD89nA+kptuBeB8XOBbGfGBEGDjuBz67OylChs0VrUX
NteXi1IUX9yXlaABoK2Gb7CMe2RlGPsWhwN55aTBgXpC8kieeMs+KGxpbVH5MYy3xQ0ICC+OA/so
cV/hxtxc7pKlj1SbJlvviHuMyr7Mr+zxb94qRagHqvGjp87YNX8VafqHB/Ka4xJmM0ktskRG5Ph+
XciUdFj2U/hk0PWXYEWeI7LcRHd2u/+lbR7GiFVTzhBAZ+jzJVIiP7lTrBkxBHVUQ8TkgCKAM5YP
dLULS/FE3c1pGxO4TguMioSXF/QJjOpPbA5q5WBH1gNACjp7Ond9ISI9iap6SFBL0zxy2XSaGG+z
eanLvGadvjNlhxjzdPjLhiUsJh076gPE/h93UxNXq53h0THbD1BYncSD8xoPQ8y62pFmm2+wh54V
rXEJgkKTgGeW9dIeBXW4xF/aUsw3puXBHOKcbXtBk9En62xM9PKKxR8FTnfid4MOQuVTMCfemoHu
w2wT1p1K0Vn7OAsHfHqDqefR4JouEyvjd1u8uXKiwIKJ+sK02GWX0BgBfYdv0PN7syzwn1Ttt3AJ
Rtb6btRpb22eDN7ZNxlutbQUZP8IZ0U1ZG2bnfbYrXCykPf1SBg4401ZV+FMNXQeE9tBTU3G9vLY
iA5y9uKlwd90BcqWB5CpA4+Mw4Mz6ZAtIOqWz7vTWpgncQJT9uwVUbVHCQyfkieA5Mgxb6L0Y8xR
Y0RG7VQIxhX15fp28GCxVBEteL92h3Lgnt5Rhq6bVuYrNPfJAezSs9npw0EGFFgM3ujWeDJmj169
HFaGpQeQM/QlPRkVYSbGaseaeXsSuSYgTPGMQLE5jtX4jGGk3OqfFHbSyyhE04v26s1b+hqWiQzv
GPUlotujSvJwTHTPstUG9d8jGkNYnWOxRFr5lvdSPrAMq3mVMTFgTTUpE06Z3GN005WcQpfSFgYf
98Ink3APLg2vlm4jez+pQ/2wF/mCFxNdlMfypPy0TqYztkD4zdS5UeK58BSGbDVIP0oCUetLovAh
w/cLKy9EFHu6bCOhyjkXl0jCJ57TaDPs2bL3C7pQUbGM/FJhKp/J8Qsb9eIJmHmjCfE1WjaGgLq2
k3HtvW6HfG0KeYRpLLvUXKSPn0PjCSi2wRM3rZRrAwZXAP4sdzWyFH6h2ZDtjreKE++t4HJDdl2j
t4y+vV1274AGzOY+IUAmV6wLMlTd8k0SpUa/5+lfYMs+0aTUjbH/DbNxtRoNm2eHz0o9x9eykfiF
fImmxMNdU9SKcEEvkDrcyy96Ngkwv6s27EXO76BfcB2TyLQMv5BqmnFBw9ToUUqlBiCJrr5uQfo7
MW9fcRJ4N+OP6OQH3Qc+PWyhyFLY6dBnE6ehyMa2ZBS4eeZxGeEhErbHyOjzwA3GCuFzB96t+QVm
szK5EDEblC376eS0WGm2uBXwssZI1UaU66DCB1xlGtxmh1QGf28E3jaiECwrgUT0UvR0wDnNty6e
kmTZddFBrQdGNkBnDlZ4tS0WipY6tknpXugLqW+teHUkOlwS0rWLFN0ireqahiO743KfV9dzIkL0
y/fQ43bFjMgPmZt3d4oYZv84DxIG665/x8BMpuLyF5OJsAaGyvQnsOXutg8ggXm998Q18Z1SvGu7
zkYbD53IxqjqpW3fyaI2702gB/SYWkQjU+F6UIyam5emmlcgkhChHasbJcGPY+/6tt1hVCP4Blco
arn9ty+xjeZooAtoa4D9veu7mBVBjCB3Uc3WMn5eFfex/V4JX6d/P725pNhej4RIs0JmS0H0E/cf
niXmZKaLhPJutqcz6sfKSKucVoSpE2/5BllRMJ4d2gmZwPePDAAtBwvi+j2O0zUWq6mG0Bd0BpXV
eL/q6RiuBdVo9rLhSSX1jvqmPCUqvrWs/I6DZw1dNYmmtr4hFe1H6alN24S/uEUx2eaptx/w7Y9T
C4qg4KgmHbZ2hHQCxQEvQrxd628I8zBnmiuEW5PnRMQOl+FyttqrABQhQmVj760mIHdFETGF4yHE
MPhrbuDLOSLQR9eJgcGE5Ym2UfQiFsZWOhR5JbZp/2NcOT6287SiO9ilo2lUlxgNExxqggdy8vOc
xMtHl16B1GQpxuu7NGrgJ7pulcNMLayBUNHPttnpKuCziY9nmeEKuiV7x607GGzH9kTanFuUzhO7
n5LPZaB1fb568BCh1MF45M3JzmM/kzxn+ERby3vpf5WSqNfjFpqUsypINWxJRfjJc11z0soKuQI+
08Jec4L8tY93qD547RthvNEuvI9y8o6x35sPdAazIwfGz8k88H4oD7yxC6On2oJyuuLarW7yFRNH
r/ufDS87IWYiLirJynSLopx1kpOC0skF9cfBv6uK9q//XQC+mUuCEjrcF6WpvR3LG/unDu6rupLW
qkAHNyRKl2LQJuvPtFFKr9bkRkwRWEUP+U0OItqKZBp+AsdVJkMioDpZMR/IXxwQXi0uomAW6fok
8ktBzXvodPU3roAJo8F8MSE4I72Ucj43Eq6Z+Xv82Dm/LyafMJFUOT9zL4KENZ1DglL9Sz3AJCag
f0RLyq7ZKC3QNWTMEfY9btqmaE9/40l6Par4vRzGoJjdVXAPRMTVIDD4yeoAgRFxTkwnceKO2kqX
+V1O6/vXhfIP8rtNTZADzBDj5DTi0BJtar+374eMGckRNKl7PrdsaUZ/H9DvV0Jaq26nDHd639Xo
/rREDszFzSj08iS49o+CRUOK0KSeZUlfzfxPyyQ5Q4u9EjEPSmbdLochUUz+OFSPoA3esFmM5Pfk
6fp17oQWoQQTNCh+apx/d3lvUBL3BZJXnuqWSmy5KgevcjCoZwVlk6FH7ARKNsOlAvwIahZNTu+m
AhDuo/LqYVxhg7eNCwk4DZlA/opw1xm40i26B+Qvr6t+etojmT7Tnr5DtKCRFeGBfsBKlh25qXKJ
eYbNr/yj0YxBn9cO4Z8jhcBXoD7rZhHtP5T3eHMT0Hz4rdP0jni6iq0FVg8WQ+dt+D/nTniclBKM
CJHy9SzfeDEwY5NgWRTmadp+nUELxhXvy7Kk+VgZxpW7JzS2eTLgxDa4o7CGnFGA8sa9jU8RpyFz
0YTcjmkvgbwxa23L/KK3IQX5antoBVpcc+d4g/0XdYdlM2rZq8GRo/pZ7NtSjjSzGYtmzVzx9WaS
t6nOERQyT25Cdykjm+5CJSlUpMYT8db4Qk1u8MLcTuOlGvqN4P+O+RVS4BLt8guqZyRwKCWTWc4p
P12+7U7wCxNkJ41IZlc5YISK7E1oKZBjCi31GOdx2PazIayrVzQFhSdhS59Y2kTYpz+yZefk4wqD
vxO62W5BaDzDy4REJEjY/uNYPnAimlePZSfm3r80npC77AnuxOLLEcoWArtx27Rnqty0yFf4/XVf
KfjPslGypVDas8FlNk7l2Jp3X0U2jKGb7ey2w2JLErj5OY+wR9BAc+xiYbJSSE2iR4/d9iZgK9XZ
O03+aRlUwzgDiVbQBjrq/WIHMBmN7P5aO4+bkOjukjmsC1fVd7W9dNR0SrF2xBX/hoTVY/ZXskRK
jYWs9dXXz+UrRSXcVoSxF+fAGBo++x38RhjA2qe4z8MMWE6ppg3D8QYGgw4XRQQ2Is+NdmhtgnWz
npdOJ2/e7NYpEV7TaVE/UDQmcnaeyBYvukx/tJlIlfq+Cg3Q68rjLkpIp83kHvO2YkDt31jmEs5m
eWAQSymqMKnPmx46H3bOT3jikzoeRzb/hKSPxZ8cv3OnLjoj8aXfbUP3voPrXIQwBCmKVOcBDIEs
Nb/i6ps6ZyZ8+NESrTYnd6059aNLjopVxHK5zR6lka/xF1x6Kq5DtBWz5k2z88EaPKA7Qfb5LVOW
5NOs+DB1tlF4u90xP8xqM5DXnxExpn/SDCL0l3XT4jfhI9Qa3BHKauCByOXqnLgVwHyQOqQh1Tvu
lHVTiE2ZWgA4GHR3ZkZ602JtchLpAgDBR0EIspScjNIKMqDqKtKdCHUR40XfqO5D0/UWhCjnR8qx
h+2ebVvW1uXOkZDZuCtolMbrSw9hPKD72t6+f7WyyTmdAax7CXU+lzzaytJdGATjyOA+f18dUXg4
BxBkh6Il8rsix9FVEP8v5lToWeXC2hu0BWbjTek6FXKqC41MMKPGvO3ypUQ4sBbeKghAk+qiHnfK
U+7F5y36FYh8yLpqZ3h/uoR61pdAjJZmXDvHYxp2BIOYTHvK/4MAKttthHnEO6zDYyAOQ9qp9vEK
NW4MyMy142ar7y/xaO1s1l5bHsUCniz5G5pzu6DE0Wm4DCoKjUKkzVqTUsPq8ven+MrSLOM5NptI
wI18rmBGadNdTGBzM4cpUcmYyqy2h2F+SrzRqyFmCDB58MLbCm2ASPluQnPeiszVn+iHOeuCZRi1
onglYrvUpgPUp/Wsm2Be8y3owl06YJhgD2BYGDZHYQL6kfs6qTc8lontRjRALnk4+7qXQu8txsb0
1u5s+shITLgfUsGccoI8DLn1Nc07ziIDc6GblSP711WGcNb1M7Bp8MzWDfJGRAfmEy+dQVuQ4Z+o
BfmP+cze6teVmAoCik2unjhIF/PRTlExV0yu4Imk5aaEbpceVMpDeHqs3w9mDc+EWU6ZlAq0mrF4
DV8Gpd15Y2V2L3LHaXWO9BZ8li+cFajE/qT4dTVIC1cvCsaJK8+ktj7qvAZaD5ACatqveCeIVoS0
0gHu4xX94V/HOT3aVqHyAjZC0Pyvwgnxl2L01qzxPKgZRGbXMekafiFzhXfwxPDmmsMgQACQP10U
CtPA6HwqeCPn9LE6qk5fAFJ7B+LCrXPx0g4f35n+CLeOf7JafZC2jSW5SJKFnZJUj/wmKP3XoyP1
Ocro4fgs/tlqrKHm/V5Zdn1s1tdfu99JXTstLhC7KgRhC9tbyLG381UUdVLsul2C0W7z4lXI1iCV
9GlCy0UCG/jGH/3XOu5uDu1MMoFOn+kJNC8GTvFTcQEJ3jWoeANoAeAKZQVl2nFS37VMHN8K/L4V
GVhtNGkSsAI/XChJJPS4BXPC4zFn9bw88PIglxCCu8R4LcYxVZcC4CvOlGeVJeyf2cCjFD/eBMol
c7Pp2zucJZShw+k16XAaLhmnOwYh8yzEuvhm+DZWP//ja+JYuzbIxgT2SB+3q0cvrz9wXEfhiPJx
7Q6bfns7BSlGtD70FL+VdafgJvz5p5lo0joAb04FG5owtvEYGGA0p7QpPa1ORN7zFC7YRpwCgRkE
vobqyoExAO4XcjJ3xUb2ddtVtL9So46tkN4yuwvneC9lIy7TLijVEOuYrJ0A19AFoI9I7HlWQI4e
prNB7RLpfYv0GYcXo75dORHIxA+rNoFAwu52mJFUCmKaGczg6E+DBdcUM6ulChSWzUsgfsWS3YHt
wm785BbfYbl+mhVHEdDGQrFddv1xBLgnAq/UdF0WIOB6XL3cTJbYMWHuj0xCWWBMZcUE15zEqjj6
HmesxfF0WqIgTkt0hFqQq9L3aHfVM3CYwcFU36SSE4SYlX8OiOSRCl5JqoriH7z3sbYyKLKz+w4T
gi+Px9sULx36VvhgeK+Xk59XZge8YlxDKow5zALfvacrR2wudv8ic36yS5NL3UEjMjWreSJIU8eW
qDubFL32s1iVbyI8hT3EwQeKnTEJnz0g9D962/BMydH6KubgijHomwjf0MyECDeKEGUgAydIzcLV
N4EeQBIOw9nbz7IqLdwKrQsy9MaxLLpSVdI5ZDRpOHbnJd11eSBDL3cDkyZmWPsWBIbad/lsFggA
GPb5QPA0YUpk+DGi5lK1WmtG7a1AwmrAk70q1jCgUCbUE74f6hEgRk/UytBJEGKMTlqWm+ykqEJn
85XX/bXVsk+RAuF21aFUoUcWSqi3ZTXOjjbbCJHbvECXmVSifPocf9ObV5YZKNeEKzntartBm8fP
qe8U0Ll3X2QiGx+ufdli8BOeHaf9dlw70vlfrVLrYZqztqKa1M7z9ZnxtXFiNaSegj/5FaXzVcfz
yBqWwEVGyNPWnYM/uDJOdlwUPssANnDq+L6lgH7rMxRadTLEYra0+Sgj0Ijbzzqg7VV4O2oonmj1
gbN/QTjfmSekAUjCbIf7SykNI5CURt+R1oheMGWuxhXYiJ2TRLkaub24sH1ZVCNU8i/JBYbjsQij
+sCsv4GeBumqCencsFUuWY2lx3E13AhAMFZYQIFcRenrNfJpkA+qV2lC5IuOZnjWhhRQg9WBnhBj
u9pipZ5EPr1gu+HoeNuSkRyygOpdT8ln/kkF8U5pLZAo0p0GD/SEsJLqXSfyDQGw0gMYxePjAzFd
EYp4zB1xqXzbumtpbiywh0i+feqI/gXwmJzoVjkDWDvXJCSM2uhxW0MuWNLzhJ4XtGbYGruNQBZU
PvcaevJrRylHDSGVuQyz1CyjaW6M8ccGzudYK7mk7zTeItTv7YLXNqJyHxxQYBIzWy7cLFTQR9Qr
lKp6IyshUpTVwxt6JTCwBgk1tFr7OS0TqNwjgJzy5XWmiq+MgUthVoSfJEQLCoA4skdduiXm3Fa7
SIqhAXf+QNSoQB5HrJbxUPHfGnNmzXP+VS9xOjXd+tmBWzYw1uL/KuWBWmIuZG4dn2upjVBgy5n6
+6JCvjNl5rGIdFMgCLCLwruS67aIrutPmGdPNfxLN9hU/7tYbvmyPQpIpSljuRWArIOBZpn1vcVu
jHh/7KSzvees5EiVplR7T1asqgDclK/TvtNaVuy2R3q7kZHFvPyp2KNjV2jJFF0B+z9fJRAGjylL
+I2lqDYhHk6sLl+m4SV1qiBp+Skh5T8g9Y8eUrtF6tfbHM/mEVeVn4464q4ca9VS0vbjLij6cYdw
VuYdEvmBunnPXPiHd3EVMKnpU4HwvUWlr1+UErzEnMnQa4VBl/CYBLY7FYyPF1Fnm0UQ7RI26VP3
jmSqD5t2wZvMVct7edDUyXhbeC+V7UdAcMALP7x/v/8TPWiDhrFz8B/T6fx7DNx9gydbW5owXtpW
JE1cIwIwAKf1T17MBbBy8SNRsOcGUw316RM7mFcqHi92L3LwGrdfvCHMAHsijRTO1P8870RpDBJD
m6SLLXzSBdDJp/oi4ryTQKM/2ZMFzFw1LULe5XAHASQmsvotwbIGdVln7IhkgH4lEgNC2BITyOOU
TxSFbWOROavC0NuV5X0UokCnzvERs4LrgRH2qak5OkpPKIarj+R7WvpL6Nok5uMS/eqdOWS0qEPg
ldSgZIoNMOKZ+DK8CzEEBLbL+J/Buk9u3hqhaUlPHAgabjCjnABW2aC+K58hdwyi9yuD/7z3swEq
JoBoYwt6hEw3De7GsxXj0r1O4y3ydH5Jkcct8cZTuZPcRaB1HcZsqO69JzWWIuWSC1XEcFYqvBn/
ilXtUuslgUhFpJHLhAUsetHmEkO556Ph60pXqQGhIFgPoQvByO5jyQNchCgKjjitcWeWw3O70nN5
5ImLRSmMee+vCnOdH5IbZnEnb8eu8mtv4Vttwoe0pe5PX4tOCOznzbvgB/ylOohgnYm4FOQfpvtP
4dI9z0aDBmz3GrmlmsH237gzscM1piIkpIFLxWA05HXySp6mGehem8yIEE6Z72RwXtOZQtEE1fRr
+hu3OTQkOzhS5O+tHwnmWVFmWG4vVSqbPGaZGsNopxiG/gPXDsHR9d4PmgkMb/m2QDf9WTJi2YSZ
QwZJtzpnYtuiy7PhQ2QBH4817QrFn0aC68LMnSYNK+Rz4VB2M/iqIVBt/5OOh+ECjaq0UsEio3v1
YLpxAUTc4Lv2eaK0viDPiPrqu3FJfnRcAq6wi9EsvCwiQWSplN7Cnq0drhm+ZM4RrShYaMMCz+3z
heaRK+4F5GsEYTDHReW7cIpCShGHESriKvW0QqdDsfmUrG+xYo0eBNBv3ypoAFCo64Jm4YnhsLA+
Ytcoajf9zVvKBxHEwPyumtrvVxODXT20U1nzQQ9fiL/Hi/mBKHyjmrU7qBSJXjZyo57GSPifRZmR
OxZHT5W5nvA0+2+HX0y5fgZxlhaX1fDhbOUS4/g8K5cjs+9x5T7S2MsS6F5ws89ZY+InbHKyo78d
DkAYcgMT6XgW9ui59dL0QabK5MJD2ZOAsSOch4ZmjRIf5cTU5ZNmdEDAR0w+NX62kVCP5aJWDixQ
8jQC+j7sj1ODD+iraPcmv6+UULeAOlRYgqGa9T6/cjvmy+SnycWWuD6W5oBq5pjBE3N6Qq/nZqwF
48u1O/6OwKIq4r3FZ8OpwV0ELrpcTYm1AM8r79OALDZp5U1mlZLDCzBlrlfQryWPtEmHpEdB/hhZ
uoVS9PAbZ5VaknR6mjkTp+DEmEfCGczlRFP3T4LGulCxYxVOsEBl3rbevOkuUvXfHbjFi38Jc/oP
mxdIy46COgpCWBmDsEpm719PWZly/GA2FCTDK8ZzyFP/NKFPOTkfjaeIoa+vKJ7k8zbxcO5LVKxR
6/K9rPsx1Qec4xCTwVnfrgPl/Qbuvwdj0gUAJMtZY7wjerGkrkthnLlUG71ka1FP19AiJfvIdG4h
xBBHeIzlRL7+o2uleI6G7tvJq+9v6C/ZSl2AVTB2vjDMpVGZYbdkVyDDzV5XNZSzulR35hbdSKjS
zEBeJLt9tqHwABFuxS5EKqNU6fku0Tig4ggeaAzTA3NE/99v5NcS5UFz/stsZTqQc85kYzKzQ4pH
7y2jSaMD0vU/MvfGNMJZt41nxF/yl32iNXM6lGeG5GQzQmNueOeh1CYD7SH08hVbp2c/LgmisllH
se7P1TW627pev31H8MIJklJf/OEjr+KpTC4Ey6dmslWLV5IDRlgTjPRGiERl0Cbe8yZuSUt59lzx
wl5ggzjuheLikJS7zYn9Ezit1hffQmsP4ShDJvhfKNPb8AuV/mlYUC0rF9iDYJv9GAOhC076M0a9
yK7sRExvyiqwxMw84OVj9dWIN5pwxilB8K8+xlOmbQf+1CPOV9W47amHBFK69PFJB1UjjOPZfu/u
bm4UeC4VRUaLmBVm4G3XVNti0Ul5MumDmbUWd74TLFNUFG2XfTPBBOG0Z/gji7/9mvDlcjnNQLPx
Kiz64RV/5kLs/GQw1YU010i5JCibWiFJ11t6wfFjN0QZlqaJ9YU0SDeFFAmA72dX0nOQJBwDTWqC
QtdQ/ZBHtPQtO1OfoyDMTMe7DDgBSzue6mZeJOYyY9kDUrpL8l9eYXQY7IJaXffC2tek5amAuZVL
lyNyxgHsutR7PL+npb1HJqSJqs208S6N+QgW22Uccw0AWfzTjV52uc/Xn8EdN5Cn3p2AsugLLVJK
hFTlJI35jc7r39LiBCiZk9n8quvHPRVqi19wTcD24m17diVWcVnQHCFyDFZUQ1cTcd+7AlEEjARn
znmr72t4aUVtN149Li/HPQYD/8hIL1QgtPO4G6ModqeZanxfu6xGF1WMJ72kkuX9e9BfEIEl4lSV
xypFIAzmbMqE05/aNWFmVEAWB6kbjsVrPnPPWJsgTovBS+K30jiAZ8h7Wu0D9za/zl2B1vetgoaY
mkfyrLhfLBOY8P/GJ/YG7G1M4a6yJ0bCXkDDBpLJwzBLH6QCk4z5V8e7VPUJTyFTks7VsiDPzLJ/
U0qeJOit4DG7TFP1544AeQT0Bf2K8E+OVfXo60dDCsuazkaI17OEP2Cz+AUbwjRfA4CjCy3R1KpK
BeIu0rwUcgpQhKhGdobXkiL37YtIZiyMmIOxyeIHz3F8U0cecwsY2KAM6iUDuf+0OvRjYmtlKezK
SF2trMWwT3Tw9e7a2e6mieE3suEmhguJ0o+bCzdXDwgFxD4uf2m72X2Lc8m6hOdpYYPRU4QfbCV5
Xwsou7CXWdxmXTnfQ3l7+RTRe/Vt97h6li9C91LT0NvswYp6UfjhLUweVRnJuFt2tdmI2bbT610k
IEcK6AZWFqL4TrlTbB7rFe/MjqStOQFLQQy2FNNVcIWkdcbUlVt1vwwydKROPV7SPTFdRsn8jKS0
ST0eE79qmwrFHHpL9vl4SZ9rhdYPuZGkv5blSf2cMTuq87H+5CFG7OlyrUSCPzk3wQsny0/9z997
1tLgYljjHnw5nCf1vm0wEWRgitbpqSz4m6smUoJOEEtOpG6Wi+IzdLvbhnD6Kd3yjH6jdNzrwkb7
Wwv09H+nnVrl3rw3rha4KgUQDVyW2zIyeEEI1mjMeLahesNctfdoAPw55p0lSEFqIDzIL4YS7w4B
6wH3E/7Z1sI+LVLTfySYShyQ9oXJukj86dnsatcfqD5L3f8QXvjCpEKLAKlxHYHscBT2Yw/9uvBM
KHu2Pkk/wTNavDu7Kv+lpunIWrlBFQxjz7+io6axqMxXu4JjHnppCTuBpvBHmnRMspKij7t6cpOW
Lhdwye3nS7LNGZe6v/TawxXDRGuPK0P4gf5lQsff2CBljPNGXM2fDWaD7ga6bm40SsboYd7wEN+z
MdUnEXJgM6LgjMlpgHyLbwf9coLW1hPHEvE6Vs4ndlikMR1ZtsaOR/Ph2jOlBM8tI5KbUoPobqN2
mBsgKrTRd9J2OFnM7LEVkkKoWaPZ/mmwTxcNuqc7/gGxpXCVhm4xlWFZNRFPU9M1S4VftY3vfoLo
w1pV1imvFvlOX0wzFw2gJ78V3EHh0QBbcGerEhphEA3eH98RqHIu4vlYMpV84y3j3DRx6e4Lkg3q
uBO9ANRKTJ1iUQWsyXSHK2UGRJ92LtdpRi1MmfDnytZHGwgweObaquUBEpYhrWbxXhOr/Mk8rRuB
aYiggw1y33YvAK4G8+k/LEoKUbd838ZvYtt06LkDaIQN3cPYm18AiPhuGItbagn+L15vYhWoZPkl
KPufvoEtNwhvMJMLr544DNnUrnU+3Igb8B90puftRpT7mV6a2FWs5gO1wonCNHjxYhbZtPsalY6/
tQfP7Gn6JtuTkhErulUlQvpmpFcvzHBuZxlYCXSR0OxE2OlyldouYClcxgaA807L5ex0xUlgcO90
HAr2U5w2dLU3LWkKSHhCeMESC5G+LWIwDy/jGfMhMuVKMe63GZQKWdnMCkiguTrVCBX7q9c5yIlw
890EpM5oPP83Qb15dcnBeQW/w5uYF3NLZCtBO+cAPjtjAPJYZXkA+gMVa3QCzNnvPu+UhQVZZWen
S2YRJhzt4LL5CIAnm62k2I+FsXULNaCn8BNQOKOSXSrT4zsVmKvaBk07nefS9iWBbeyy72t1m/4m
szQyH0lJQLSWkTwKzpKI1U9tDxR79saYqj+WL82JtyYY5NEiaZj2i8a2IOABF/yV3iL5JErfGgYk
Hq0Rcwgw0Eck7IyhLUcxomyVrMMPYWsWKMURv88hOYYCW/37ZPoVTumBdrf1lrpSybFSUasn3TOv
mTGrCB0b9bEd9wBoqkGB22CN361paAEGsIR+7i6QeEY0PFjMhyAkWeFQEaxXCWlifB7ILn/ZHHL7
91KpHWmgSj5SfdfDO/FG6cHJyXUa0NEpcrhhZgSBBESKIeJUiQiOafvoulrqsSOY0LKFfSJECTSs
I81A+sybB1IAuwKwvPc8po4g9V9S11q3/vSfDHKXTc2Lks+yHr8Mz8YvvXGfj4IbaZVihZtuctxp
Gbn8chOMiJFtGhDVNhUQiMhlonHs3J73MuN2gBna3mpJ8S4BIU7J2qNP5ftQ2yghuVkHXp7OQyTC
uuy93GqiT+0smnbxGdumKCPbG2JqGuw7YUHLKX6/nuuvHY1ElRin95uYimf5VoQHImSc//zyFcVU
gd+VeFBt/KSCC4Vw0ZzvwchZu9gF/2Xh3JCnNmvinvL9xpZhWrFyQsbjdJgpVWU+xRDlcXn+CeLD
ZTBltdomr7Llep8O4b0K4Xy40Mc5YDZuyhmHYtSuVNMx0G4fxd5kQpYJzLQEFvQ7i6H5xYmgTf28
xbu0PvI5GfkGpM4HpgLLSjLatjBW1Km7o+pgHyOEyHVSapcAx+ktLAuM3gvcWMSoZRthhLBig5h+
Lhp5aocrZpISOGRLYegxKvMQKvXfed5zH5lACvN6u5p9RuJQUBbHD7u+I4rejz0WzeYVDO6s9NJS
RG9O+UJRfu8qZgs8taFj0lB+RPcBmQHjrfMZc1xh5AgG8EWvNYInk1z4TdAL9qn9fZiGhfPCNdHV
hYIDEqFVOb70kBhHuLYrLzSUJ8e9F7rroseafAzT77czcEwNRUFddRJ9o83O8ifxLj0pEDpjNDP8
nhTN2zwlJ33OAWCGW6hStFLbdJOScEaibNgc5N+BYaFStLTSe7D5+SLfvjULLekQiUjv2nyjOuyZ
FyPEj+PxgRSvilx9xZYNyTw3oLBVoiEhTbwVemtflSqB7n7NlgrWHHPmEB4jt0Z26SUDjLOkgGXb
c1Cobwgc24AetGmRA28irlpJe4UrE1HSmLXIqdUpuF5gM7STOAeEb1Taw1R4b+NI6ddQ5r3jYsb2
7BK7UFLG6Ulq3Xy47CbyhU0yYvgkGKZJvXpdRWj0UcGJtx0xbKZ67hDCltM9Qq5u6B084++dc0Tb
S04b6fT8XKR1WIZl7h8NVm68Gf0yThh3QEH9kt9xYctJdUPunzgzU8wUh+ZUgwQk2wOiedeYJ8vv
PsjRgvSY5vZbNg70ejnOwav4ozKDaGQXZToa7of2JzvIdgINA9YAKuO4mtLotcX0zZb2xkFxrPV8
G7+Wuo2pODfs56rBa0KiYFjTKryLUroMEDzfBP7R+vmjCbQ0Rn5T4NVbv/gxoQOKtZH58TpfPDfD
AjqgNbRUbRQ+uQtUDRgcq6hNCEJtj7SFXTzPbKiKwQ/5d/y4c+eLjOwHrEeqP9fBkh9QICcF2XLZ
qszUDRAELNI6hakLyn7h9IRzTr2iWEzER/SlgvU9QIcHY/JYDV4JRL0SQjInEjwx1/V5yE3q50D/
de2e55xejXVxV37B+5DANUrKWtGo4drxzIWnl/nXsYZQ2ARzEYWGDaurv6DkFydV77YEC3De9Tg2
QsuV3T/3AUte3vbJ+WYdkYautI92fzmQf649ClAkCzM22008zdwHJUTLt/TJHZ+/85v26uAMMb4N
1RLWBrXEiNH2wyC5/5KOhzdkNTtEOFcsuAuFbSzItjNHJS8U+wd2zoJVJciyPSdH0TaX0VCAUF2n
7SnhoYsvVdmbW8Dl8C+FQ4XmpgGmW81ZOyvSJwfBLDPfZQLL9zLCHK8sfyFOeOPP+8/oo8FTwQUq
M7nzEs0LcMD7gVraEc/ZdzWBTb7B/XrPLDRhWJu5bQY9+9OaTGRn+o+sPQhMFlhBmky9qcEC1LjC
Lft6qGkc3WePcpmDbB3t42eLgZ8RNmpqd3A+ryDRv2396Gi5iXs/r/ZlvVjNN+LV8lkUuQIFhoOY
JSC/H/PNCfpP0/R4Eqh+eARm1iyUty0HNmwkdJfADhRXVGUKThw/PIFNhbF8+FQEO/V+6CelDd8T
6M8FcSaExXVduu30ZtM+7eHp0oqQJlmaXWRyiQLIAkZrD76BpB9e5bhMCgDpHo4qbch6NTXrWVY+
eh4v3xMEBofVCTkxwOrkU4JP2NoOvBJAHoEBOoHToro/bwII3UjQX2FM9nL/apD7ae86EcCN9iid
yDGKK5GKkmTlQtP3mgaQ9JCGNh+rYfRNX6Nm9xufoSXIOXW6y7OoQ937uqjpdQ6UqVudbFKE4IxC
sbc+YPD16q8nrAwezaoy5xYBFWBUd3HUtKiTEGslHmnIbdYgTz9wLxCcBNjS3VXQxAs81sdusw9H
IjpP71dWZyTSjtzbdvZ8LK+h0+9OlvlM2EZ7lWXHd7KMr2aShzbJK2wNbtcXo0GVUbPX0T10zGgb
mfxL4LgMlQJVjm7GgsyZAPiTHlsNwSCvCva/9ZCuHMMDlppFMU+qo50dxyDD0AXPB9zw+ZSBQeJ8
3d7T0IY2YUEoxnNd8G+kq0Xt6rqv0WOGYhaH9VDK4vvjaP0hcq/m83eEBmnf72hauQ5YuP1nW12Y
B+iBgahzGY9u2601MfPHqgcFfa1A3KS073BeRrpl0sgEq3YCWBMwG09YUwIjDTgxwA6Bi5vdLqGB
LOgAFf8FrgSwjtqd1PSwrFUbjnik3p6/DkuqKev4AiV0Sjm51gdpa6/OcnoOOCqHvBh8SAakAAXt
kdUbDF6IT4wuaJ07TXVo6DTtSkIUVx+a8mMHIhOVl5n8eNDY8KL7+vviu7avkCYh/+emRhis7o9G
9v0MpHZIehcqNQTs7+9d2bPbmZqDs0HWWv6k6wpP5vs6l49vwAM8MgzBlZNqf5vURHVn/ABpFki2
hT08R3XNlZ+bQPtMcn1Bea5pCyW/KDrNGqh8Qi5r7DwZ80+a6eNw8Cfex+YwYJTth+C4oilEhzql
hVsMLFf8BuxxW8mD3PZ9FtIO+5nZzGB7NBnkU14rTIt1rXsyXAplapDpmikxZpa3o1gbLYymzrPu
tavHXd5JVTYRqSNw/KWJiMsN0FLGAYHqd2eyLHqj0jNSN28b57AcuJ405GVRQEFP9hGeSCeKuVX8
m4sEKU9xkkQJCjnH//7ef/vGxN1jDJcagS69wPPkmh8phCpnOw6n3V0IVEfZWG0/3mFR+lEzrvSl
+HXTb/5m1Bg8YywHXjwCKyEgIx9jx6QWWMYVI2jTBiYScStOvEXHAhsZAwxr/5pXvAPmQZuqVH3t
vKzbf3/t4iQrUwJbB4WHRDLx+O4wbKno+g23V3oU5CfSRaYtqAIcAaMEHzwveigwHQr4solMW/ct
IIUv8pFqJ/J/bSKGhv/M4HUbP6nOYPo0E1c2PUAF9XL5gPhVGyclva3FZWjLTQyfAwx6rIVYo8fX
IqmHmIwqyco6GNJjV0WKN+B7jTuZgpRQE4NKl8sF0eyf/7B/O3lnoW/+nPhzqnKx2MMZWHK6Ms1J
pXS1ZrDJ8tNiWV0aExi/NOTtPXevLPAQXSUVtwpP9iE83L8mr1E526rgSvhqBNEYfaBROCY7LCmG
qZ+hhL/HyDQP4JD1D3Lg4688gSpbIu91pO0sSNShsG9ODVbczbWh3zRPLUVTTFrl2bWjWz11j26J
5sYpV0LTasjjTu3Jwt51wbSJLSre1011WFSnnnCrQbUsIqOBfVgJtp7R968axgbZdvYC5Rt/Xq9O
4YDaV9WVdYbYToKEjjbjTKNoIdkQswqTcKwkxYb8qJ+909jBs9g79AnrhgmdhpAoAr8daF05Rgb8
7xPHKOgmLgLSMTNhDEFK/8jndmH+JXu1nvriC2x7yMEpkce1VAkLekAfKrKwmGnhjKHn5pUKYguB
vwubOdYSi5YlILYrvQH33RMKeBen/LT33kendoKeuNMg97sBMQ0CRRS4hXdg3QfRcH9Wyy+161t2
mepa49zyxF1FEFa4EGTYhv3WIw3sN7sjXESNjglhJT9U37Qa2YIJQxyYZezgkhl4+FeZTLwlOsJM
7o+uc8hKkj9Yxr8F1eigVA+9iCnXdCEn1KYFZ75RnDrrtzdqxpLhlz4Pw+wCCZQ0j+5O3Ly700yj
RmEo/LWprH4J0DV77+izDsjLXschVNcxqCxJ6AHLUamJ2kws8pNfmAi7KAuEAyEQ0qRN7GvUl8hR
3vd1v2lEJjamt7iuya2WPT4O16H7rdGMKTu1rfufcoPZNId8SC+L5U9E/Sn7EgWXR6eN4lks5bhe
RFYRNtrClQG+/fz0a4jFJ8M1BIwvbizo7bQ6AgTbMFxCu7SWgR1PURpsvhtAkhRLGBxHeU6Em1q6
NeIuVAxUOang20rtBeTXBBzTwWmAeOnbH0sEzV9d8Zg/U8G3ZO4oSHXhCv0TFPVtfe6aXaE/MRv8
DafwbGuio2pnSbWnRtjYf+0d6U3/cqzQxfYnvrP/C4VkgYPGAK0+b2NSo+oUCa+pc9fWr4H85pD6
Y9PD0mD+UjmSajjDky7oUsLjm0lydyPb4pRcJaaiVeDq1EU/JbiDn7+Sl+PYHsVoXtW5xj1LY0iR
4A5UltHxo8CtGX+FcKLQYMOkpG5jtACekWrOCQFEIU+dN0gdkr39Nqq+BfQH4v13pEOxBbS4J/61
9W7IdY/FqgAJrE9R+yqbcZ52e9wKrMJf5jt7SOWtsAYYUPXWxTOjzI1vUdPtCoWmkXIUfAFSG/qV
x10+NQAVTVhHw6ZOT0PV7UYgPCkmK4qnNHsONfDaOic0UZ46vOx3o3FBg6SjaWYIvCnl5280ginr
hidV80vVObuCpdZPiky5//rYUSzic0cb1LZzoIREyehnrnOdoCNHjSIcGpmoPrvStUXkQZcU7hvf
yA827Rfc6LkTxQRXVTc2uFAe60OubmFKX3+sr/Lu4XvuOyNR6exC0+cErX7qsCDiYBXghrfwQUDt
5pP4aKSUlWQhNEAuDKrSkZSTZAFalQPJy7dvfHvlmLlQC2N+RGfpD/nXNTRBz6qtalIfKGWInCKD
WTDyWjgbEHk0ET1oI6G0oVYYDRAovJlCplEiZu0028IlS9vu+SQuvYc5lTlSckCHi7rwtQ8vgElq
iBKPh8xHzRZJI1665KJfjAr+lSY6oDACEU0T4XgBTczAxrzq35Ta7G9tLso0bYlz8sFcl4sAhMwv
HkTGs28SB5+pxF+mE61FAjUdJbW3Ug2HZfGalGUnBSBJ+Fb6Ten00wE79eRC5BfoRBTR26xPmkMq
S7bTYcb0ZZWQxvg2oTdjqDQ9MY/Rhs1fd8JMPV/2CloaGn7Hg2KKSXKi87LAmzeiiuDHsTqZv81F
PrHT+CNXwUZZOYXS1I10jSktxylQI2G90v7rl6CfYpWJDyZPEfLtW6AUVK08u9BR7u6EhoJTvfOO
nODboVLDomxmo+MgqxvVmWgxRLE6cC83k5vpP51uMtc0X0XofnCnNH7W4OUeEdupk/Ps/5WtzTAg
pzqt0J37l2pGJ55CslGsglqqofyZ7AfeLC8YDP9p9erfH7bSN7JmPAsIb2FqfJU/Kc2csEhC7dKs
7Oim+9I4tCUTX4TLyqu9//XulL5mHhDt9mfXneoGojQNN64MGntoiK7FMHVBnlVmR0XGXkHRnlGk
aMTgwdl5eU+dZkKzLrql5ba7gl8+gmMxukJX3611Ka1uAvRuIeOfx0zYlXPWUKTA+U+skTAGvwjj
/6Tc5mmwt+IftZbNpdicIcjB4TywLDemeVj56ItLUG8kpHd6O8ZiwBcSDWUT2im6X/f4ORva7yo6
gXP9qiJgMwNA/B788b9R/x3LLVTuDQtsWtrGYFLH1aNJBFsk9Vyoqq/t/qiozeXn0h4yarLw15vO
q6jeQrMti65ROYtvnsnMKrZ0XT3sE0BjQxM7KvV4hoTPPTNmCu7yjxROYFnyavYZ19/K30UuRc1U
1UUPWo4K49MxrwHR7JH0GTb6juEAFsKUAqhHDEbSpdZFRll0UpnybsBrqdZBcT77iskviokyiOmR
1LQgyvRvbEgF8k2cRAxLeWf1VRmypc74ZK78btoPS9zINiS9/qMnGnxBhJySr7V3qF1o6RvyjFG7
1YxjHGNJw3ybvDqdI1xgRCzfkPDuoGpgqSTGpoed+XR88H4nY7sr3YVxCH4ieDGk+6hKa4+1scSS
wa15J/b6OZ3p9tyYs0SwNzj83f/sVWCfxpesy9vNRhssctlky4Huwcp0/f3drZxBbaQftC1ZMbhW
/aHwOE8dgQF/avK9dsPhwaP2k7jnstKj/KME+eENB4vQuBDB/0D5FESkAz98UBwYbQ41RLQXSA2+
LpmSAKG7+oLYb0GlANI1ZsYewyVBHOSHnwsMQEFf8isuaok8Zfvionfv8dtA9AR2mQHY2IE+ucPl
hzk7Ho1K5jIVLHwq4YYh708YezPy/DamfovQBhW+1Jho1lxVWE4zN8LT3iZggJdr+vQPUdbxT9BD
yvBF3UngFa3fNJkvUBqsfb27XS5BfoYxT4BhFklsdQ7zwWg8+IuUcbWlGTRBwm8z6xlvy2X4pdoX
tLbZ5kXGJUYArZwKOiwOXg/HHi6bz5+9ezmK/RdnvhDzhwz5gEoso/emr+UoH9jzeUndLk8Cg/qL
6+gems6rOTy0PckBQ2Zy1/w5ec+rXr5uSlCypXaBMdhhxZ0lDmpWHi6YIGP9cHzvuZLNqOtxiSFD
AxLWTNr54L/mbaFw7IGLR4odX1WTrs86TyC/40TNoXThDeRsYGDMjhjb8ij+pA2RlNUjP0L11jfn
E9kCBN2/coeMmWHUC+v2CSJ0Ig0UiEghGjvGQvjZB+GfPAQrfDZwzYrIXzuBpVuQVlG31oWqoG8S
MTqwy+/FaZcgT8ZRdr0bmrHOSRSMdeMvsVQneJXnBcDNTievGYewgyfzJDW+7q5JoJphKiB6PeWF
jRW9XvWGsyuHelHAMy8LQxN9IoLo3z07qRUPsHXaBSNcnSpHsDOozivCF3JmdpzwfjzQGx9r34Ie
KNzwZqIQKik6gDOX2z3EI8/dJuM1uCvimPN+Wm6ArYx1z/qCwsGxjPSVXvgBkh86Ch2Ty1cN8whK
4Tb/JNrfX4du3nXwfrl1l89/9Ss4pKtV8BdDd0EdZMOS/w1CNRdZb3Pjb1NTAaFAkIZzuyXq/HMT
p02DY2vFuNnceRVsepbx0t2RGY76miwGFTtC8qNpqMdpGjuDmOUn68vkuYi3ma7xSq+7FA2aEfWL
D7RlDagO2U52ALPIdrbY3grIiTTWj3XZyDOdNxmpysb1pmWdTvple8Q0nYTtn22rvmJAbDPjAvkD
cuth1nmX2+GuQz/ed7YQuluDHazs8I2Rdy5fOsGzcwjDO+UCNCuBXOe5sGJA3/Kc1A+0I0b/te0l
eVWPF3VhpIr+ZTL7CEIFSBRgIJ4OVKCamwNV9ydlByPe6QiVRZ2n55+I7B0/i3AljbzbvccnGSNa
pQUGFvecyRakcpu3rDhyE9KWALsHFNoDdUWvzBZTJqJeUmSSW8gnP2Jb+LE30FgM16XLgOOdUIma
irg7KHJhNVcsts5MRjQBKeuttGv0F1tc5wkwOthKguDJAuY5MSUL6gsAq5gA4nTt4oE6uIoSeRrr
4eC7EoIbJHnHLqTDcEHH6pmk1BH86pf5W2ghmMHBO/AJt8sdmSHuD7xyltRjuAmFQtnKLZ3/66PR
MnajYs6Dq1kBAeFvQm99NC+/s8GOiaEL3toNi2hZHXSe5+j9cEI+Qp3ROFosvkyV3gUU42Ha0hJ0
Kz+47zvxYwED5ES1+S+RwOl8LgoQaTcoID80fsK69hIgsyXRio376j/0pBPujGDZEx2b7ztyGgkE
lb0n8CKYYc2VHCJfpbK3DXzoHmHuH/AJXod7qh5haIO4o2hqToH+aj2a4eeECjpQnwjhE55QMg+a
u5VCUHb1JbUMi6gSfwKYaZR7Jx20z3LNAXpZ3LPW7HSjxa767OFx8JLHvgQwp3G8Rjdyrq5LdnnO
ZRo/5xQC67IoWIYZP092zNtLwo1hkGmFuiaQR7yIofPWrwTdXKkZQFjehMwco6Qgv+67ehOenfiU
uIgHrclA2U6mwqasjek/KmryjgMg89H2BtJfaRznIBl2LwKBfTD2AoQJ/zhopvJHABbGA2RXFpMu
8g4TwCuWUAAqLFLdfdr+FhQWl89mYozDJcH3S9PBfMmMVVa5Ggz8lURVjKcg3yY2+WuTnV5ZEPRx
qiAWz57P59V/ATUsXfScRJHvvOFf8tC/gpLBKe3CbMx0HfUh9vqexyKahjnOUlNseCxATV6cDbf1
N/hdbaERAz+xgz6Dh5LENEwgUjNIn4Dt/uSsfXbNnliL6hdE0VaGkL76HDfjrdPm1w/Uol1CyFvE
0zjDNrUjrptFGzi7GHSsJZ32+sy2JF7b2w7Po98Q08MQIRsuvSaRx6vYjg+UpKZvj5IAbDL6lieY
FdU94SqqWa6XBYHCDFhn6VLeX8tM9yB/pNCUGgo753py0FrkNiaWTwuttgN0v4x8kSXLIAlxe36+
YN5ohHQBmLr8IBDvOuhL33n4OexPOE3DVlshLZC+Ec2g072gUjhhMhVS5uOLU3DzYST8sSxqFxn8
KyZuK4ZzM5bfSfGlRQXRbV69AyNMAlkJsFj/7l+Q9TTVO3WwEaldE7rTA5oTj0j7TUqtZk0ohjvU
pXF1jx10/a7EoJXC7NMaonRnaYrhoeiu/26jrH94xXKqHWh2pFJtz6GOehqTbhy+S0NiVmI9U/HR
3/QcHFv68FeJie1zutQPA+BQcYr5u3/i6Rd7Pjd9NcMOUEMUwtYBgsOwMLVvD31IG8Q00X/zaPYK
y27CRGvB5MeXKNNWgeEDoPWEa+gVI6uKKMM110VIuPgM/Jj2U8Tbi1I3VraIASJ00IyR414Zrw/B
BMi1MNquwOU0tpxorrhFGP+Sh8Bym/X9DtcHR4Svp7TjvXiABM87OFMs12iI9HFLxXh+7NH63bYP
VJ4PoEYraNc4671+i+Ny+NPoHbLhr5yi1tiW4YV7YhaXdmMKQOcJArkNnEJdKSpQ9gHag97UOv45
DlzBfCYHVpqqaLdhkpP5sQYsflbHiRdSBjkFt9s1Pg==
`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd | 19 | 43742 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
L9EbKuxxzV/09pnAb0OGW9DxPQ+o+m/MvX4x5f3JCiR63+KWt2eYB17k+9mGgVY+K1VLxoYz0z6V
YvlDefublw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gJD53XIM6IXGcoGao7b+pChhlJwhGxOuVwSTI1iU+aaEVIG37JelabzUSiGlwgboK2Zv8N9/EzBK
Y9pDSGcMvhlTABOa75VEGmta9QvVzRVMjXtd0b/jrdUkZar600zvkPbB8+QESNshxT7B96klkdIo
XvMdlDR/SEQxmh4Mkpk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
uMh613zg14bfl9MaiMXKdALr5q+gvlBiCCfJpnudkmj/VEzNaqE3gABSgWbIJEk6l3XEblsHwoSZ
2eueijgOoGBjZq9eDXqLeir52M0Z4RoybrJFqX7YgYE+2quggoW8XJjUPK7bExWH1Wd6un6XRwZo
+XQ53VUhkTgctFKNHRr7bEqxJa0qk8dm+fTRKVmCc1Tr5X6rd28yRrr4koH3+liBwEPKquwcMKJL
zK5B0g+bSiHJvGXlQQpKzQNF3+4MebcveUUQPOYG2FAjfRJs1t60dgE73q6y3I1DMI/3MguCuvoX
78TA3nOFRYGLkISVFXDX28xYA0EnciH3BlzGiA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2ADp5V47yVkwRII2+UsRY3zvclviExupZdil2h787eVOjYg5odQlZCOMnldkarIbxDBoj52vjMGc
rG04pAKa/Z3oDUnDkDe8ZMmBI29kynugqgc8aGxYPVKp3KD8EvhnicB6/4Tt66g9A8WsjHtxXLuC
0ImlGHU3T8u48JygeUs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
s5k0DDcwk1Yhkk6mc4rW2ITc+jBCojX0QPFrzARjmvIjcmc9EJT8pAYSdJK1ykoSIGmT8u4U6vaF
5pchZ1NWV4+0T78Lu7ir0M6lHPYDFRgXZTR6CNdPGqAe+Si56W7NnXEM0Yylf/w4tAQ0u+05yvCg
wK+mPCq/91Em5ZiPcvKOHOdJBSTTkSYC7/n0QNniR1mBmd7+dgsFr5yshClYY/q8HngDDE/aNYfx
P9AT4ECjL+OzARXCnbTA6RjbHEjVx1ewIc83WIXkwbZjUYAzp9rYNjFdx68zjq8U1XW92RXAEXCc
AYKv676uVGq/WAryucxGApaihL/izu2+HGUsYA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30640)
`protect data_block
TGoYSUtq9QXorwtXYAiku5PRRrofa1QO0tKP2kJaj3QuzD8XFFlvgmBxexyLYDE6gDfD3y1MimNL
y+GFR4k8uGqsTU4X/c+yG7qWrgec1Z/r4nV+jBcL0IflUtTCMpq+DQitly34B3lyEm+/ewhdWbag
sQU92u1xDPqyW4Fay+CZNGjpJEW6bQ6IDAJc7vACSdWHqRQ6Wrr7OvEkDQEjVx6I5FstZJSKRDyM
kkrVQ7wugbCgqedvuZCna1k8+ZH7dyRcyOIbqwtOUx3+ole5A/bpTq1405Z8HHOPnnLBzuvKN/i2
h3Ik0stJQYc41NspCzWtUqxX9Bi28wMdEtl98p6niJJJspPsNRs/+hdLPK8mB93Edi4KWJ/uhRqS
yxZFf7LkvVi+N1jLa10d3keQqXfEUiWSaCDXPOWY79DklbnODKMFO7yWaBJejaztQDzeKsm65LPQ
Y91glKNdw1T9F6Q0eGTfDji1Oh6STnGcLF7Q4+ft6I3sAcFoa+GYAMcQrxcbYV6gPRP/sHvDS/U3
x/6yx4C33M5MP2lMb77YET1MfVMdENnCd+z/ngchRAtQtgE9fg5naOmX5BLqRMHmsj5DVEciFiRM
9Q2PPHT1Qjue1AjcxPnr77595F06MYAipT3yiyNQUYDWEWMMvCiA0DFt+QLyVZD3/1MNiyEQf3FH
Zr907KKaoTMl1xF4Yv18UQDSznABhvA96BcMNpT1h5esJcK7ItvTbfgEWeyOA5V5Yz8+tR8sci7C
pNVbCNrqiJGQqZeZ1EH/K24sMAXcLfjDa3GM1U2aNCNu22TYqw/XKixHntS2NQpSiwdvOmenWtbw
GivCdLZtIXa4ljb4VUy91tWUSdz8zAt2PbUiCBtSRd039hzHSdmTaFIewFsALp6CMFqAmkz50reA
XmQf5KrBDyqp5TYB41NCgltZKr2YxvAdTkIRfsZROAbF0gSraAulVoNdx4iHJRjXJtp4jDe5/P4A
ImbYhhVcSMmqZW5yilWcRLwAH7RsCrGoQt7Rnf5PK4FCKZ/HB91QUxs5jYlwy2C0brNaw3D6r0u/
aPjaIjX5UYhLBF+qrrxRiXnv/OR5LZGSUkwXKvfrj6kAae1s/up3gtdS0L7SZDcBWmvCps+zxhie
URaAurKOkd5D9miHbmFaJwnF8D28dFPSHcUH6O99UiuNgDbNHJ3QAZanYKOWRTa4sILwaHcGaAhO
4J1kYV58zGQJvk0EtxO7wqeP0ldw2qJIfrLOyT57CVvHU1yZeVx5YGakuNvFZSJ+JRtLWT/IuzK5
/k9qNfBfWVu8IoE9VS8TS5kH+s8Hjg5+Qyvvdj56/ZqN5C9R2BdDFONDEhVNPzv9OYQ9bZjPcLGm
7X+s7R/QMCX7MAgFk/KGsYmuNUrNdkfoZojYQa6jX503LHuaAzL5h4qUGHnbMKfqZN6QQNlwlpoa
NKz1kMyED3ybDh4pLlVxvj+WUM03tEEpjZA8UInhTtsQW2AO6/cAXDmA+05f/P8BZ/v2zdyJySVF
lqWiFxf6z/onF0Syr7rENw2MqlwysBHeRhhmtblDQqlzmdAQIiCmVVF90KuXeJcwx01ae7RwPOsi
6DTfuUDOYh2EakpUfAUqKekEUX4SrhSHXGEiUy198AvUQyTz0eOsf3WHYKH/yjasn/4n93pQ8xAz
Vl6qLyqCl1MGp4seT8wPilsm2U4MFNIPX4NWd84AYv2QtqLwfpRPK7UVStfosKqBNDfk0lOJ5OB4
FgfH5tIlwSnqlJUri1nCu428r2/9+Z4Wa3VttRm0szGwD7FSTcR2UIpJ8XxNz+SErXlg19nXWK4A
4P/Ga83z3IcITvwrGdoipK6FnLwOr4YJqyVFMYdzeTBbgnkIOcGDbhH4P+myKi9UM+e1tLA3Evxh
KAcFsV2qWFHtrwySV6c4Gf66w3IGbGXe4kiahq3XXSrBzR4MnYzEvCcPWuczjwbB013/QiXFxy5w
cTa2TWgJdieJaP1pHEqGF0Mf6npoWD00lz31JWqDpIJk8yEPB0wfkerXQmbSOVsgjbAJOqGqfbUP
hxBu8VBTRZ1T5QzCTgSJhSqhopqqowHl3IkRiZ7F2svu8sFjMbHaQvs4VNofyULsCe8G8i8Rze1R
YDtncIsDgERqpZKI/feDLTI2rp/Jo6JQ5bviikRxE2nWKFevLgQSwDD0wvB9eTBhsFe9dHP0lyjE
4ixjvHSZc9EygzYAFrZdkR6AgUF183PVKe2SHNbz1VdJ9HGcux04kk0j+Exib6rj00guXOB3bA8q
ZLg8Rh1aX0K96GB+F/jWPWP6n1vCrcD8PI1GwFXOixPr30aP8LQMWE9Ugyfz+Wvenr3bjF0lUlGQ
JMjzf3OotTF2mxJoTnOSEf/iL53/gD97k4HKqRniMrqcqmJ6KVmttoetm3VopYOaT1TNbpn3Plpl
vaViAQI6dNtQkJO27IF3bi/zJamZ7Y70OeP6VE6+mar3UiiU0kdO2sHDMiK9awHiZnq2PeaEtBiN
55KnxvUnN+p8SyagTY1YeImKTk2Tg5DXDGrpBshLvT9rBFNWwVE5UGLBfV0s2FbgxSZbdqJEyXr3
jWmYBeOD1s+inLRYM2wm1WmGsuqeOZqve1le/8Gzr5fqRhHkVFLqELxEnfnvdGKLP+wle1KSyslW
mVylpNhvgzE0utV6ceJk/yYDtcJXn9YBAfWhnQInYbAORTgcEDkWBC8jr8NSM5+3jpANsWDBZ/yR
gT78qJCAuvNvbLDCEbsmQGFg1518J+2glNpcE8RklqB6svX24Cz2uclo3n/bXyDFASgfSLEkzJvB
9oY5rca8NlYzoAYy9DdlrQ6Vu3GWRAmhf+QsP2HHp4QVL4KBH16YEeycvdYVpy8+AWKZUEOCQDRc
ge0knitBMwnOTbAqwuyEY+gfmaGQ+sRWeW5mm4M6br5HIfz/PHjS9IOnywHOkLHkPnH/jKVnv4dm
sA1HodHPqK3Aj3jl+SPoyGLK7jpwlbKrUvIylrctEx/Fh1idtsjX/OH0jyztyzNW26O46MqwABzY
SYsPvVkeLWEMgGlmyOztG+zxCwuQ1yBL+gzn5qqH4Umai0MooYuwfbgWaekV+zngNUSxfjnjdALl
M871nLkSg1IeDMJ7+oOpWofT3zh5kE2avJInti9kCY0Qy977RfsqUliyAmMy334n2R/ApIVS991w
HuAR1BHV70/d4BJuQi/Le6jbC53YfIa7smiPYqmh5L4l3eVcsuhTUlrXu/FCM+tddtGtqAgjTbDH
95+ajvLbGshRUxAqnfLyd5t6EplRzI9eScZ5Qf37tmPWl+RhKhz/TduXvOGYdZlP3dI6jZ3LrQ5y
yOaAMB1tATpHTrROY8UR+Fd154NjDfwjLNpnuSfMc/zk/1WLVjIDgMY6OAY3TCD0xi0auWNBoeD7
h5tdUf7Xa4cuIGwgwMtKh9T0s0Jy9WBtRTcOMfq0nbJ+9tgd+zPUp469pmYqFeyJIIgFr4k53E5T
CPAeWCu5dBGcXFJesqqidpxzdyQlpm8dD7T8gs1+mrEAm/xcemVe1ATdTFwNxKh+6O5yso2dTFOR
fKPaUdN5LdKJZbiXLnvJ0/lHkkDsxNIj9F2uHuKUfbX+Pe7GdPJtI9mkc/Mb0VLogkoXvUfs5T41
yi7yRnXyAtT6HA1X+8sTCmRxuUUPIg+sNXqET8hWH9NQfVEXbNpSbCtqJghJsQoErl2UeDmT8buo
mSZHpwlbp3CSZmq8f8mfEramnP/Y2NxlpPKz75gqcnqx55eDzA5IblKd2UAw8J+wW5/lNi/X+pm+
RjrK2oE66sU2MlF/oZfWVImW/BFWOj7BAz3cE1yXawUzh48T2zbcRbZAoe3T8teaBIh5HlEEWIZr
aK92PgDTI0Gso4a9JxEUGwiIaRKgyjgV4L4saDQpoeczI0n9kpXlSOpaiekyTSeevk+Ac05wxyb2
oM39FNwn8WmOnpjAS4J8SIUm87TOotKSH6gCy+ohBeavPcxsQxIH7j/9nAyxzCQlGxYtF7Q4xeri
KHCfRs3ryIkGnTmg1saA2HurhpCvHCUJshFbFHlET6mGs4OqBu2fnvYvrF9kAf9c4fPzd6ZiThZw
8Y4wqAtEvQNNcHVn0FNZ6Eb+EFrQRHMVHOv3LonoGbog9D5J8KGXPJZ+Md3hyrCCCZ1Git4sXxii
L/N2NTr256VJFqjqj3VrrewhH9vZR9UAgmjoKp9Jz+NliHpAvNenmkgQkrlY4nEMwv5B1kx/wtVY
yqJ/o7lFG+F4BxBlDnFkqAHeAV0GA7vYqaK2Uv4Te8nbe5p/Foehu/Klp9rVo9+sszy3ru3w90nw
kxKeUY9jp9OknHi8i60fnRsn9IWNn3j9F/MTinR5cNgQjwugr0XUv6Ec3viOS0mn7VW8qb8aCSjN
lQGpux65BrnQ6lYVVR5/p5B7WsEcjkcwwZkHmDgS8Im+AGsjCm5JcFNJBbJBiVfBZ2LnwdCI8G7m
vNXdMfqK+6/dpVATWgCaEZZj2pOQaUAlhDUKJOM2SjnGL1sgTwZ9BzYDlvT8k4rQKkQPN/igN0oU
71JUm2SG5IIHfd7/LK0po9zS+Nr6uw1Jt0GZJSn3+8v4mlPjytuyd43MkgOj3tcsGJR/k5SMqLUp
tNJ5Nf+Y1QJDonBnL+YWKnUJkqb/rUq3kv8CZce6KN/Ci9qYfcxlich557zc4O98XiBPOcNdOzGh
JoUKhV2rT05NfrJRGt/pNibySgGKkYSZBDMva5eTI3L6DUhhXtg7FZh8Vp14KsCe+IC5iuvmcvTD
6c+IdCQfAMiPidWrErtl90RX81o5W+zqXBdfmzLpWi/aVF5gHUF0mlGdUKvjjagQaFcsaPmAyEbt
lJHrKShj05cr3YYjCll+0m3Vj+jbwWdEUuplOb20HYExLwJJo4QwEP2omT+wu0rd4/7yHOjKVF34
WtBc3K4ahYh6dayIcJwic6aBgjFWbFYzaIwQUq/jiX+DF7AZHlMVatOiKDJ6pMhsEMwR9vCUdVSv
6y3o8DC1PthJm7io+7bJD+H7ubiHyLs+3+fyX2Rl3GkLtjVYBw+opCs+BjBWJxxormB4i3KatRHK
dXurWsq7g4ixaHZe1fEuWDKQEAy6A1qNFIHO4MN28ZltrhzAdZ2FFWU8KxQJgSdFPsC375yz70iW
FR87V8uAWnXkeqolZ+4lb9E4mBihCm1Eypqdq4pUK9E0HMvqbf/+kCZNgkq27NEx75aR4ISwB1iR
yXX3Puyu2y0w/PzeY70DQgF7mBLMxsHAI8I/3eCor8GEBVvGL+qe057ZeT4+bfG5138ImAbgel+g
q83E4TMUtNmVQbtrATA0TDmKCi5pkhfqvsOlnNVzCBlOfC9Xj2JVRyyR/hSMKtQonEXOEmHRpGRB
w7KNStcdz6wdDh+8xITFUssnAeqnkAheJxAMLlJuqQCTTlyG49WhjXjBhRopPSrKRz6067ky5ZBH
AGajA6YTodjNNrB5ucOp4jtpzMSm7LvL0IeUeZnHnbIKNO2XjU0gsGPV8mghzjQZTsZ1HsN3L5uj
y29CxsiRb/pmmnUA+RX51e9uiItoTngPJSn5cMqvkYOCWUC729xmUqB5D4ssHZXCQhUVkkVxRvTv
ivbXATJpUmfYoAubq+HwKx2F9O21Ky2kmt4nOD/8EApeVTkEgchE/p1YLT/T38NlDSsEzaKYQeCW
iUL0zSFgLseNbQBUwJE/B8sH9LAEC1pO3Xa3psCF5oROyIWrffkJcE+G0iAhMJnzFhxQPdKE35T1
HTPIDoO/Kiz/qKIlLWLFccGieF10JudKFl1/aFGrPGy//4h4SR4KUt1nWFy1lkVLB5mIUtVtHdne
ki+gE3/kgRz86YqfptvlLLvOeXs18aQB6w0TZYarvYuphCUcRBlVVZXHUQiCuGPhvmXDF552gpRs
nFs26+qNYYsK5vPYTOXC32bOpf2ZFGserZtB5EdzMhKJUXSFwll/RiApitHu60VUlAm7PofH5HW9
QxHS02wKVU0AbJ1hvQVPpaTlF++DgP7vFGNzb9cWjOBStSpxCWcRE3AHCiAcn+9yKR5tdDapYss5
sIuCBbrI4LkdJzgJeLb5FcCl31jbXfRJfLK/w6i/kunqsBvz5iZMB1O2RIlzhcn+ch80aazjR3wb
COEpkhUiAe79zTb74s/NB2oO1JMnduKe4FUa+UHRI2yKqHRZE3odWWxc19axUVi9lkwK+JGb8YfG
sYvM72lP4wKdMpGLkcQ5ViIW2a2TVbxWYd/CUKLDcV7g23+I1sP9G+AkwpbjZfSKUrlXryJ0ddLB
hjGo556eBsFegvE7k9Mbz7rAahlkYVHWQYbdUXaonO50ExdPsQAGFWiP9Odnsso0Vh7RNffmj6Hj
paXR+XuBM8fPNv9BjbIk4ZERi/ZQALCP1TWmet0v7Wp+Gbze8ZAbByfCSenbSsq4L3tl4Fkuewvd
hUrXrO+9n4kGNcwcAvJEZ63oEMI/7h7ZiZ0b+PO7UoUIqEGuPlT6/5ojvqBqvhqZZ9n3dr/+XlMH
UIy8N0tp0K2WHTo9QwOLQxZaJReaRov6ElmjTP+19vKtL+fQYUbf7x04j24/iz0E3Bh63Jz80oMw
7O/YhnzfM337k8bfzNwWcSFYpQmYm6xn1JIFCihbpCSWFQNDHxF6bNPx79HxhP6i9OXq2bvJn/im
CA2GUXnLWb2WVMMUH2msUAm9EvbrDkxgR4Wy65ivIj3hpC4EdiRZywKyDi4z43xiO2+YxSZsRvo4
M0nj5huxPJVYI5yu94LGNs5xiNB7LyT5VI5m+mazs702nmBJg6Zs0wIB4Zh7z+etFd5P+P1405cV
N98TBmYpyz0+E8BkzT4j0AqqJmi7v6yqL2VosECHytAmsGtXYps4xH/y0LvSDApXc3X1J2RhAcHy
ynkVfHBV2d2wn0l9ky2JwboSOZghQd4peAUUwsoK+54WI5qrCU8oYUmjNAIszJlPVtrzunTodBTr
Dmw8xG/BP/evShahEtryAKqs9FN42drmAT32gnY1y4i4RxVveazgELV++vSQqdqXJ7UXRKq49pqw
U0T0fgnsy2FPv+/acDaLHLQ0YU0LMmprZhxmjcuwkbDhMg/r6zVv5i2VWxvTpJpFnmUytm6cCLJV
ZVaBRLsIL7JhWMunQwjRm4hX0PZ6yotYm1OYCFnDWLUurL289yFYQ8J4xa/UKsTJSl6ljRxIFivb
1yBYsLzfwO6eVyyYIBWRqNRcMjPtMeRHlBVRQo8443UNdQc1Ybql3QjPEP1/9rt5PnFaEktZwOCS
pMQCHKGxQj+RlzOndc4l4KB6Q8bazUZcNGWkrLf9aMpIUqJuLWGrgoILroiMowoi4NmFAqal2JIr
T+GYRKn27xcF6pEAz2bNuB7itWcae8eGEtNFOAVs9Yg+bqVLDXt/0Gn/H7Hl2CRJZbtbvhF7QK7d
AcK7fHAnWZDPFUMjUYcTJTKmT7Bxg9DQB3gmdDrm6EvJ7ERI8xamYq7uZzi2xe6zXNtaZe0gRwsk
kDGPxOel/8qh/59FPOn6i/a/Q2KdMI40pCg6Ms/xoL1XkYjo6b/6ADyiAmuaLC/8qvNg7lyZRCLo
lOxw8Yh3DErNmWop0jmoSHgz7GrozlmiDpHxHtdYK1xLhGMQc52A7CLyy+cZGFneBTj/fO13doZ8
mfu7D+KQqxWLuKVCNRppCAAqL3zziPujlLijRE6X3QyA0wX907m9/HUhNJVg5TIv5njZGAueHxFq
8dad1eK171B8Jj88+ROAme0jWs9jlSgplbU4AEU/dfylM1xQrlWyfNOtzrgFeeOyJ2oOmMFgFl1L
5lLnZfB7ww9KbXh0+g/eojwEuhcem8J8AMDl5151xwNJJXOYhPmrUbJGD/tkN8dcsY/5CnQJmBPt
Z+IS/Z0O2OXovOnAgxTpeOHI43l3l/Lb71Y5Jni5E3egmkW+Ja6ZuqyRMx0R0DZ92EjyPPyVMyHR
NYWkB+lDHt+6mkUidgYxxt9RHAf0uwhH2zNT3A8JGJQI8CZM76c2cBFkLgBsiIfKdh9djuF72GMc
rxmJFspzTlT/Cb4fKUW5HxGqYUWK6sCnI1hQNBDxtQNG9CLzeXaclw7+EZffOAxofg1+uJrhpfRD
wMSfZJkCV8xh2rG7CCRzEjPgwV6wK88qlCm8Sdt+/ZPnsvmfA9w8e4JEB6pl5wyOcZFiiBKWr3eu
jkGFrhOnwZHxs6k50xAl7dGp0gYRcgV8uP0qHQbm22bOHnu1ohbvMHWbjFg9+yIzYoygQlEvL5n/
Ouojl00kgURmTqKgxQLduDaYHsgDu/jj/RZ+EtwWauZoBxeRrcueOISw6XQPBzrVl0xqEK36Og4q
gg4LbG4UMs2kgseKE9tVorAg/eCO/LsU/CXZcgoEFQRrAxA3G4NpacywrkWdzp4r6FZ3kZQxN266
NXzDh1JkVhIp9HW3b8wwG89x4FmOOVkZXxUeANzyw4pPlQMuBjHYPb+Sg7hAJdA/MJpb9koOlg+5
nAB5YELjVC8HEZuCKI9k5xhLAFqxhnndL59xifMkEWc9pwAMuz21KQA4Dt79DvedYRY4xV5sM9Bl
pe9iI1Vfrt4/yMkvLoCpIARN8MpEGf2OZQlsieGy/h05kmRF/18+Ozxll9sN1fTX5FDKd/HvExTi
4ed3QLkIyEBiXCvq3rlFdR1lsU1/u8z9PhZWHgrnPlOcavoDLTSpI7wEKIitRVTMYT4kW1I1M22Y
XKWMciYGomrKsS9z8Vcwe6jOE82ho5sdlDjElJLfhKc/QF3bCBOXgOFl4nUBb7zxbYZ9M5tzZPaT
rHVKJYGt3GxEHSyN0jcTWzeP/q5M2KgdUXcCAp122YZEMDx/DtKMw4ehNJSPeOnvQFRe+97JRcCS
jnn6DWL8wYKJsg8LfhlzOTSFEUUI1ysT3wJdFa73E0vFbIZrIj9juKKttE1ldywfqJU5+yiGT2nF
y5N6iIRw9vYJIoPte6mHvWlu7Sf84gtco3s2IZdE8YxUHAhfA6kMZh7sEgtxhFiWgdb4zPU43rFj
NAuw67zVorjuL4Z2h0lOXyHKgWokn8ZYpHB9kCUhST9sm9kQiJffrWEFcLnjBGU8aZoivQxWiuwc
tkHfLUFQoXSdc7yBB9us+EDxCtgmyEPy0AU0r337rTQwCXN0n0N1fpAbA2fYnIe5fmQmE2OSXQ8k
QJrxJ3ju0TI3UEEY7RobS25NMAT8ts25YiaozvA8GOh4CStLwnJdAuAfEpAcppv9LoyTon231VGU
H3mmldGPcN0iHzitwcmBYeADiBksPN1YD4vItVG/rZGdf9J0aaY7PykOZ7IrjelWfm+r2GKuJ8yW
pIn/QrvyBeX5A34FBr/DfyxhzQfG8yHKu0mR2XmTJSLqeMIpEcwBayiMsbg3ndfRaaO3MCq20RY4
NVKAgRnV1O+OtUGJJYhUB7BBm3b7SNXjFAaUzb9KDOwVV5B4NDNLEimPxWMTadBnT2VxPrSUhOY7
ezjSELppxST1Okxzh1rDnWslq2J2UziZT24brOqnsKUDNTHIH4W3wRBa2pcGd95R+hz/Ev1Ig+Fx
Vi7nNCJlgGSUCpVrwXAQUzdFEk9YqM+5/kgp55D01+3kRj0sPzv3b+MgPG4Jo4bzJJW9vFXi4Ww8
r8sIayL840HWII1kuN6p5p5MPzZ6TaeZP9Gv0LxSD3lUUutJiJbbUa9aSk5HRb75dTPE8n3gkuxf
ilXqzkLngGDlB4zuOZXylr+VYLB0rh+8i2S30RgMHyd0VGTWbOj5eptQI7gcyI5oY79km2lp0vAJ
u39R2kYooC1gnR26OWa7IR13vVnYt/CHh1B0sjLvmOEbrrCzSr8UQSMoBW5JeeyCifs54vyBfa08
LCiEnU5+5h4S0ljethY8Dl/Ri6vb8oSyMSYCZjnZCYaTekqzldN6lY9/3//9Yr0PAhY8xXnGSqx+
1RfUiHjYVQXuQou1+HC09cykPSkQy+QKAkTaEhBnpZhpAgoGc8SqhreANoWJ2mb8cSe7yo7jS5wf
4ZbqNgS6fCp0qNNi4lf9PIO3QqNHgnZqvKRd1uPErCsBPNdxHhb1Dlg8EvwVq0Nn5xEqIQ/ut1/D
4SpjYdHBmDW24JLtD98uo08D5Et6eyuloy4INoP3t4IgTbZcCO6iqqCiQ3g9cjvt2KYdCg0xX859
ZZa1dXTool2QrYYujfnUMHsnPsioTQLh9dQySy0xpj2fqKpGWl1Zzj/InZbuBVsHsRGHQqAufQuL
Mp3K4JsArcoqZ6i8P81eNW9Yqsu9wRYGQ0VwkwaMqP+fdTFYGxoemmu55WleUA3kwKmv34Svqu1r
AB36TYk312qJL+1U5P6IUyVh/65AFAjMJSSJKrF+cLNtYhU7ohjjn7E/Yo5ae8UvWwbneC4LaJ9t
eNOPOjKIeIrHPVUCJP54LMkDDrPI8xEyqSCDKM4jtHUn4XzjT7HLYfUj6gMtkrcCknnn7XPiEbbr
XtC3Q/jeTz0teyw0vXsDPYyVUPpt8KujbQ5qHCcyFt0xN22OEs0b0w7trMs7Zo/doEc8w5JWXjig
QDCwI4zN9juOmnNopDvpoXlcFcEdJpiuzo4gE17QpcYrmeGvRx/SZPqJ1nsEl9wTQZKARML2w9pu
uPnjd5II+uCx1SVb9II4q4PhlDV6LZ281x4w8iz+tPr8YfSubg2KprUU06SL91kNa/vOyPN7p4SJ
e+ScRT3e5FCfHlspx5WqGt5r6ucybMetQTksX4lpYkJhDA726KfPqH2QEjpZo75L7DZcf53HJXQq
ahg++BnFxEp+MOMDeTiM3H/AnC/gojFYf+NRiz8pZl/6e8IONF67hZjSGHXYM9XLP40BOMn7Rv7L
jXMZgDpv6smKVKlsjZTXvpCEaREWl3uhYN3/+NjBCtmAfFbuQuVsUW+lwROm3GBoAwEX8DZ4HPBm
iZRA42zUG0KsaDA1U1Gf7+JrkBflXiCcZWrlK9cid20cUKb79uZ+NPzjQOlUnRivOUlZGOum69mw
o9bVM/17o87hkNd+5D6o36gC30lIXDdt1uwCjGlw6agsdtPHCTIBG4SfqIl+M8hzKY/2JKIjeNoN
xBsbHpsVXBlV6ZijBEuDIhWpgYFiBCtVtXxNRMtOfuAxA5u6ia0wF/uGAndAsLVovEYrrQKNWSkH
V8lbtB/JzLrOGM/Vc1v5KZUzjoVsS8qTLymVGrZyytAH3y+O6YuGqj4l21EQpZnn8cDPlNgukmki
f98x62qzg4qPatKEnBU3OpY7vNS5HzXgYDqtJKem5lwQ1jHlyypq1q7oy/mwrbIE7yLpxI5qbb+l
KWOB+gKrPpL8HXBKQpMavvby+136p04XrjGGVSsiIh/VSi60L45bhLy6pijXXGyefhZR2+sT/J6K
2rbb4I3iqLATPm97J9+TdinJSaLmJEMyFjdD2dOPqxeFdz9m3UFzYyfstjBa8mDdxGENP0YI0V8m
xzEaXmgJQr0YPgUqssMYRlkEyJm4U61oEXuNyro/J3G3BC0PuyQv5fwlC5v3zuFMyLrJJi1B8fXs
/2++SD958Sk0xGLC/G+I/PrYspRT7wqdTNfj8U6C2ondc4hRvJnAnqIiW5bMnE5k39T8ibObDbxv
k/8oPvAQtAyuewFciqi0NAtEVgPaRdZ+ejZ91z1D1N70t4C1n7TtuMQiuBqwoQc3/xZur19LuFUG
uXeYDohsKjS0Oawr5mIABa8OamOrJjnvCn0p9clnnon15s16HKG67V7rYYvnRbmQLVY9yWMAzwKj
FOTdfQi0Vbkkapb4dHXYdt/H/UtJGj4EQtRfKAzl+wxbWAOhV0+8r3xWwZjPmR5OzGUQRPX7roJs
Q2owRlXJt01eZh8dbEteaWpA5TnBKQdT+7nJrPUgAYcEQAxM2h2prfbpwv0VIHNa1UMqFfG/P6vW
OJmL6eUKwDw5DAUlFWFTfJpJ6zckzPi1cONRWkMKr9YcH1lcA4OHQZ7MB4e9V8qVlhWwexOTj2co
ZJimIBQMkHzORpDxRBhN4IaxVmcGfDZMB0haB8rblnxIKtGFAlxOk269nI4slWvhyR1R8WFWVTUP
GVRfak2z5/8mX6nd9c8gp19duYndNobRCPcIR//NT85mvfYYD8HljwzmPXsnNIFHOzQ+a1fg62lT
vaRcO6OwWnSw+zK9EBijvJsUaSvFv2/oaI1nYJE9eNVBhy3u3Bor7lvzeupqd/nBVhx65ueILiEZ
kf2DE5qX7zIxx4N1xnAJyndThHAGHQKq3uKNEA9ao11fxjJse4sJN29e4rpe60WQv4wmIZcDkv9R
2yzgQDIhZWYE/3GWDpeUUZNVO45LHrqnip/wuGWZuXntFnfZE3UwRJoSQxLyYQ6IiAokH62cFtrL
cOL3exG7yC3xMbAt3C+IyOSHrkajhC6xIumC1y/RYgB3ydhy83Zs3pn4YVruhwvxsOtX6NL5Hg0/
LVXnOeuLxlO0CK1X8iTQaF9E48zrUPuCWUuuNg/aPnPLTPC9eZ7xKcvp4kFG4YmYNevPTjcL80Ve
Gzox0jXIXx6YhiELET3hG7EmxJ3Q9UBpqDpwF0BXexmRjt5IWchDImS/c0cmOr2nfAwUvbOygUfn
Jq9jDhpeC+r/Wi1W3adCvAKhFeIa8ZrIpfJ/SLSnmhWrr6BnNmOuqtQIZcUM1OXb7sbOIuRjgs0l
lV4p4HHklWug74CWRUmgrEJBlLm3FswkqpjyIWbGhQlq3fWIAWvhcEWo7y1CPZxhqV4TEYBYVrSN
UApeqNnAW6aJvlgAIbQZjvOC6cU49vGdlooE1ujBphGQtZDcSEa7X/ysKa71PAktVxBrObI7uqD1
+g2NuL6pxbuuNmVaIwy9Gmswdp7Gc20EdLvZd+agwDoLcG1ASC6A/7+3QpnonfnNHy1oQTca3qA3
rEyq+4mepyZjJXFNVhi7/p6yxY8T1Rh7nTz+5T++NF8zJ420Jgk3R40I6A6072fG7aPZZAQpvwWp
PrKv2F32zx9KLKd/+a043rUVCmPIeVZgLj6bMiX/FPOGQ7TNFfrNv/iMviEuvZNQ3qlIiOj9JR/F
WvA9MywpBKq8J1evhzjm1hBNEZIGgyfMxbO9tuEg03nt6gw7aU0Svd2WvQ3nybAtueUTUPvoJ4cX
2j4SaiWtcuKo/9zNr7eTndT/1r+j8f6xDJMU9XvYDgY0a4YL2xnsky8SZbrsilbvU1fruKroDpKu
k4wJE0oY74OIjfIgHcHJphJPZvhnI+4NS5uKo6yaMjG3TI2cjngS0ePLsZMI+OPDcgwYHHYzs1Vj
pXgLKVZTuVRIpQlrK/a/tMJkHOvfKpXDBMuhuxfG9Fvai9+mxMjjMyC3A6vyk2B6zRSswRsAGV4+
olznfpclD/lbOv2HSLBrjePUegwabQh1PrZMc6KYWYfnUVarLBulT58wmFUEo3NqrB/zygGaKY2O
F47hFdfurcjy6XgL8RYus+ZNW704cKwhQCw3D1wDLHCbALNgVMg+C+bR15oAdOrlZwzRMRZv9Jg3
YuzsvwAP0Rrq4X/XWKq6qTWzcUxH59+zsizBMnItQt/9tXPYO6iw/umiB/xdrXkRbawFI2XczDAv
bdfzn/mhTzM6dr7J8+lD8PBoL1D2TRrUVQTpQ7sY11nHgL97DnEZFZdWqpG68d3XKpobACZP2Mte
jppDE3T9OOD+jpaq2R8ba7C3uwTCiK9Kh4uX+uRjVnb7Zw6hhi9yo/Nhj9z82tKm8t84Mu7ByRXn
8qa70XHeqx3J/OgvxBR3fi3/KAMp+aXca2USfwBFcWzHsC3SdAIG7Lw3QV4jAbVpmBOK0SVqWE3Y
9UBKNhwHsSLy/nA32jsDjQUYUQDBE5e35hfgdxfl4r5FqzOVAMN27eOuX0E7mh0pl5JgLWAyvvwL
uVjdan2aRpQf+4NqRPj50x807hoBCTJYziEy6sZbLMqGgKgVkULOUCz433f1qyuSB64Smf6/Z/pb
2E/NQnHc0OlwA8/fiTpmO1rJhXQur5aOhHF6/JrBMVDjDM+vd/B/GxGr02vWGo4S2vNBkhh1qBLR
YZZMwV0cGYYB7RtvYXOQxuvYLrxURwxI7FHkAeZnMB7wGSBHqryJ4b9BB1dUzPHYUzosk9CYvUWg
2Nx4A+JEm/i3107abP6ONhfMMPBlnvcQfGL/TFa4RcIN4Zk8XsNe0FtP+DW/cArZ8N8wXC4QnttF
fiXKyY0gKb0R8iVk3pXm7KHBhWUTVmwxscRwHnJG3W7H3MesL7HmS091FxxE2jHIjdzJ5eHOscT2
kEEGfQ3D2eeL0gS3OQzKddiN8N5iQUg4D95Vx+AG5FHzOi1KhobIO07cT11cCo28HtR6pvGqJdwj
fjnb9zdBSdtZyeoUzTKVcsoEokaAYdgNpuC5Oah7v1aO3ic9tm6aIX8PzTaaxAQZPclLMnQp5+Ja
rbnISugkCcAwvUqiNATgAKDfqlzgGMcWtM6eOA1hU0gECfVNc92UkssxgRQFCd81j5j3GoZJ0po2
ov44k08SRTnRsmWb98lym8793srV5xl3pS+s9FIV5oC5U4m2AlyW4r5S/aPwRfiEcjoAm9BK0Dan
fm9KMwqNLSAUYUychFPThu9rMEDXTkDqeVEZDmc2i5wDTtrtIdDAyLrf3f850So67uoON/egsm0D
EmIjJzetZoq789xUMfw7utsx3HBKKxLEYWkA/D01Z01umEWYdnvnTKSbFAWXAm9IRkXItGyHLyYe
iZv7n5IEAWmFhtmrz0DM+eP4C7uEfcAofjh/kVEkaEBfPAeKgfMr6W9jMlZ2mmvAQFmc9uw1x3E3
E7tTmUhKurYqSzmBUHfP34UlR0wn324orTozeuiaS0fVMiohnz2PscCYZNhfBJuDveYt5vzImjXO
pn7nk+pcg9vnu0ilC1rHTFz/BIe1cLqj0yUjY6/V88ZAvS2MNA9jU2RiVO+D2pUAfgxe/7BXlCVr
pEslLJmNFncJiFAO+Gz6gWaqU0zcDJNELMwBF3lv7Kp7xfQgMwvEf5p+8KIUKl6awYWciMHiEFcJ
Ubd6qQUX7950Dw+9WcYsiSx2UgDttFo9PAJpY9ZXpAIroChhElKgCT0OodieThT5cw1v3GUQHOFQ
kcSUoyGTomggZ7nAusxev5mx1cAIsl0SSzxIm/oz8Vgestx2sMs5D1mNZUZ0XzrKkeczRUcHW/Yz
yQszcgqNPTSWNV1VaqwGpTTJPQpEHJK72LRK08rQH8dOw48NNEwU7eqGwZuFOqc9g8iMOlqAdTjJ
TQA/NGCQiTKh2VU8O++4dKFwL21/C542yUNGVZiPoQU/kKMO74vfW3Hg9krWLP3skH9syKL0GY8h
RSgXP7DDN+mugCeoiNJg81n6GlvQOkz4nCR6HEQcvzCfXlmEfkMaZzcVJt9LxzFe9+iGRb3ydtYZ
SMblEc6buNH6Q8zSgERsAE0ZjvWybmDheqRz+BBPqZw/164rA/Jdfngr2av8HmXqqn/zPwxu1lMW
FOqRBTksxN+VASCQDRAhcTUqDYlzUejXF1FrV82bs4Z5huYXYdltvfGciqXyMEPuRmRo4z39Ct2I
Yek40cyu/5lVFeGy2m3d9ZkHcpxVBW05cI4iYtOUUhZgq9rzL+PCChZ8J7xfC2Kl6vAqKEM0VnIL
Arq3KCmlj96/c9bSNhIIl0PamWixKOcx/1RI5IPz615X+N771Kg5+RE/MjXwXVVkTBRPdiz/er7K
87NXNAKh0w7otpcLeUJBe/1/ScWfJZBBkJP9hIFzIAYtGQYtxR8ctIOvO05uxvb7ua+xG0gU+Ted
ymjmJRnIfJ5oi185GeyP8PNcC9Ldl/CEL/tft5N4UZzCYBnvnGbVqyUO2g3s7u3HFCFDQIVHr7rs
8r12W3kNZzHFuZj1+OxpLuQ7GdkdAH7tbLQusFf3eBn4Ld9vpgQLayxrU1P7jKAAuzOddJa8eyNs
MU3dxifBjugXA/jV7/tdpEPZ4aQTpMksklPJ21GWgLQ5qcV3X5dj+ylscUzzUGzKWFznAzariR+5
1TEGF0WEs+dwNPBJ/F4iJwLuBTUhFuZhqxJHtZjZyW5mmBU/Jw5kKtCSFpYw6Olzg0EZJCRhjs8K
O7QY/dv1CSiOjTVmx+Z6paFZUrPwN5HbUeRWV+CNdaNwrSoRRsXZq5zycZrH4172k+GyC/XBt8ow
WAcjpKdfqHcgMvHbi7DDlKVHL5st8Agbx/szXlIJfu6MmsJwzNxxuzvg19ZryUXDUkFoa1Q17Iqc
KCs4G7GlfYUEhNlqgzwENNaGiYu53plO66DT5NYOA6Cv9miGS1XKBI+wxXWqtC3bSvJ3/Qn/GRjV
uZQdwSRA5rmSLWCtTGX07+a+us1y9/oe52BOOufrs4vb9XIcrDTeP4cPm4DUItOFuOoYooC3dQXO
fTwA977v0rLE/MNwiaKdJkhmmpbTJm9jsBGDH+ULmxlepKglH5bI0lGMuH8GUJV2AvFtaA3cgIyc
axP+CUJdQBexfkffZsf+DNFmFG7sSyuNvjojK9ipkpOl0b0UfUrHnPJVV3RoZxN58r+dho9BNBhV
ynxYDldRGDEAsZcHuRPYDfUxlFCaXMN6/4jD/49TtFA7VXJ7troq87YbBwVVUuM0ajX3rlfIbNgn
C/4eVQ5hdlmyVvJeMRrDoCIu5Oo7je2VQ9eHDZezbLOKn5OFuQQcWz94C+6JMemE1oT8WMuOKsd5
EDRFC645Ub+8ifYBsMsugzV8xOorlr22coU15rkPLxsihW6rcl5wLtklu5/bdYEsXxPrAg1H8Tqk
8Ms8ugyhSb71k885eFgI68Se1ciU7sGCFtmofgomvPWDoeBXFmkzcWKPuUwjRyU9eekpbj3R+uMf
M7j2bYJZUOAN04nrAEKvdkNumxrNgRjMIk2vW6KvXO7Q4UX6346i9/KRk+YHrtWHCW9zeQ52LKSt
uzr8i5lQBGBei+Lql9Ca/WDt/ZGS+poUcOv0WyqnARiK/Vq0ZK2lrvvdalXgHcZVp/qWWBdhlCBL
VZMJV47gGz1Ol2gu8piZPEscWy35YB6vr9wQGSPzLYicHdDYk/SLsRSJm8Ut418ny+CkPn3Kg59A
I/9hWmem6Ji08RTAOP78dTFPHClHB7ARzCweN7Hq60xXmxJYV0Hs+/8UwzzS6/bzgUVJdvIXsiFJ
0lifsU0v5Qub5adsUd/8F62QwcnTmrB2KU7H+9L8SfGaiKRZWbkZ0Lmc4N0XXb4FqkmItjEGFdmN
vTGHEVDjFzS6x78BouPNKwVv11RVBlHTnqpvIJv4B99CD217NltZ4KIpTHqEr4hI+o1NLusEud3q
09SYoR31HJTouuvPXsJCcYkJlMsC0hEGWFc5e4+w8hLY3A3aB6ASlUFjrBGBB2UXR9mB9ikDlTyI
ccctIaDW+KFbMELR+LqSVJyrD8PGnp3oEKAwIr/dPaRpIMfe9xC0tOZNS/AKBfkmzSRPHJH7QXaA
DUusnh1biVxabnWrMEtvdFWfJv5Ftk53CU1TRM+zdiYuPCgK84pBMYXsnkF8qyMLLNLsxFsEj/S3
Y6IdAdLfyFMeHgNOXpl/9ln5nEozxROUp47RyVBdhyk6uDZTIVoCq4O3HnmraKpkMxyseIgi1yG+
YQ0L7EfFCwZD9MIETGTuIc/FrryIrOvis0teaMul4DAcIJqMTlzFovQRqh1iDOf1mzTcT3wDf9Ie
qZ8zdFSsFmC71tyygBsij1NvYtGaqGdy3QiZdVHCI/TVCHgUJjmwngsuoIgRCBLIMHgevP59UY3l
+l0drfy/R8sQ7NhxqY9Gm46K8PL07LJm4kUPQ/97PDAYwGt0xzqE00q+2NfLO762VEiPGtY6c/OA
g9WsXCEHTvWm3N6BHiLlNZLRRc0UYIfX8XGHxcjeWHWYHPSDx0EQfqV5yWg9zZrFOds+NfxGy06C
tB4+Zmvbzyed/x7RwjYzVAmOKALafH87fd13luC454u92aZ7QQ6kUUttPpYaHn4yXrFEr5C+LRIc
XScPXP5XQ+6uhrLNMJttnyI4uG4/rZMknLAf2w/xF0cysxVcfoOnhQzW8UwtGYJdNK6UnxmGXZw4
ViHBkFwSnOG20QUet7N6Hjk/A4AO7p0hCjWdmGK6/X83wnjFRs01PuOr4hAyuELxL+kXtKRn1tGk
prW9Ex9aLlv7IgABcJxtugFYQUnWrQBTV+KKJhy7VDAuIg7XLAOSeYkLOsrXrbIwnTxQeQnqleuB
vPXnP1fdnznFMmD8s46UWcrXShnOmLZAzKv2CMsfdDfK7SdQIif2ct0AtSZ4m+NU2yLKOk7BeSLy
izMEFGhduj/zN/FFPPGQAgD7POsazwRvim9M6vtMqXPr5qLHvwFlLtdQOyK9nC2ah4MPeS4lbk3O
IPzGxnvwtqFhfwVnqoE1IZqHOTrOJeNdWYbWd+bdCV7c8hL9m2Nq9K8igq2QMDFXMfwPTmkput6l
ojn7D5VFfSxIZymx+fFXzyoqCgtsJLgJ7VfP8e0A5CaRPhNwnCs1hpS5Ivt717cu6I/9ga9XQalu
ACsf7A14OZ8P8hF4iAhccw/f+LL5uvAzSvpQiZDwAQgACwxoOyZBelt+aMNylTdqoQLY+O5FGk9/
IrgkW52gElixWGWLiiQqH+fsdcMkV8sacdX+K60BDhYCYFXcsuy78f6sdknSt1ku+czmn2v6wQuQ
FmufSYFBhRUaz+/8MxUXXHiXWfnGyVp6/thTg56821RKSlysHyt7vunC3VlR1TZUOa/GT2k7fKm6
k9Iyz/nHm4CKCcjVJhoW9aNPuD1j2bWHX2TS9N3XJrV80m+A5CoJQ6h3y1t82oIYezx634JPGe3t
XqDeF3trcrcqIlBBuAyf5H/1WI9vfQxw0UXStHlP2zMcWdQKvT2JdaSAC9RchjJMvmE8clhpsuUT
atReYo7DM8m0/E226eWXr25orDXHtonYw+eN9AzVUQMqE1P+LYhvJY4k/3jxN9qC2uRmFMbNey1+
1Niv/xrUadmNrp3vZMKep5RYPys4nTtUaeDaptSCvTcsTFfKNP53CFJTWLi9WA3f++8UvabjFuvb
G0pwidFFuV1hXcienQFnwjfhSkZ4veovTEwdih3XPoLAlQ00JT13/Q/Ez7APiUL7jmjZNHZK1Io5
UNSQBORWobuPVf4L3mZTL6w8vhgF5kdhSxoG+TfDYbaXv8aseVn/zzSN6LuQJFHR1UksUHCHu5Hz
Zi7tPLHPLt4ZFUNhMyeYOXrzGqqNKkFmsc/2D3ujGelCAHeOj3m+Ecprvvy9vMitTWvlX0H3Kuh8
hX6f4lCdgymD8mN7MBbe8cTVlmPld17CVCVxGFGS5Wr2lxC5WxR7L+o3VBtP21KZ6wGRnaiYzDJc
LHIo04MoGj2I+bhCG0lS0qgsyWHo9XWd0HcQo2ck0Vc2TmGAZX66qUmshVpGe7iXLJi2mTbPMiSs
rBLa8M4dMFayiqbkI7Qc5LsKdljUfUR61RDeQ5zQq62LS6m7p+v2cAZ6Q6Q9/FsWHxGzgGeVxX4x
uSdWczGrtY7OfZq7EVxHQ3rs33C4HVOdRJ3IK9vrakHafeqcEfbArc07Y8Xf8CBKvbZ0/mHrajFA
bLh7tCSOgOTZT1sfYLorGr90J1PrtV/3GWtwZ0MLOHMwzG5uKSW/g5uYMhjhWya6j1jVqC7b07+9
ORFPGYL15ovE01ejzcwzNqQo13J9yNj1SS7skB0AKRElrp2EhzQuneLM/72ayLnHblmCOcdp7FQ+
Mgbh2iVGL9LkKBVwZ9mK2MkV0/j8gyAcYMVNboJlbk+10sCjp9w54s/oHh6pMRq51v62jBIIiZyh
4xJAYY1xjAoJZeUz19HWG52dekGx2NR8ox8NVo6ZULH0J+e04Mfn+IFQImZOdldOMsEFrGuUR9Gk
PwraHqk1/HrZ1Sc2I6InmDfTiD4VmeLlwUQ/1TKIXPejuQd9a6E/eJ8YtcltjG8pmYDa6NjxZF+M
8/9k3Wn1l8F/5l292/9z6e3a28dB6cjCE0+bRnGYvxdqc254sJhuD5aAtJlZW+4RAJEnipWkhwl5
keyQzvWUHXgY042U0Hl6rGbvYeFED6ENcXiRT3EInmJ8dhZmWilSuXJFk6PtSry3uuUktonZwmV3
fykTLQXRBYKJtj39gumV3vALvRC0QfnjDA8IWCr0hcYIUJlq8zPo+wW5WMwoxW5G+LVbckaDQwea
N2qOSIIHG0pN0M6iwk2YRjqMn1xIYMPpe9Z1hK5AGR9o9BMVkSczoUFP6M4lJjUsLGT4g/SH0HDn
0kFOhJVSbg+IifsDWVHkKzte2UFvvD8kXgcjTwNn4+uvQHJm7hUkG8siuRxCNrQNHY2F9lWaJuoV
OOyRXjv60+ahYs4FnKRmT4c8+6D8rNMbjv1W6V6GYKXs/9ENWvc7V2e1bGMmXdUH/aDizgT/2QDe
bOnsqwRc0YKG235fw97g+7BSpExQKrUxJHD89nA+kptuBeB8XOBbGfGBEGDjuBz67OylChs0VrUX
NteXi1IUX9yXlaABoK2Gb7CMe2RlGPsWhwN55aTBgXpC8kieeMs+KGxpbVH5MYy3xQ0ICC+OA/so
cV/hxtxc7pKlj1SbJlvviHuMyr7Mr+zxb94qRagHqvGjp87YNX8VafqHB/Ka4xJmM0ktskRG5Ph+
XciUdFj2U/hk0PWXYEWeI7LcRHd2u/+lbR7GiFVTzhBAZ+jzJVIiP7lTrBkxBHVUQ8TkgCKAM5YP
dLULS/FE3c1pGxO4TguMioSXF/QJjOpPbA5q5WBH1gNACjp7Ond9ISI9iap6SFBL0zxy2XSaGG+z
eanLvGadvjNlhxjzdPjLhiUsJh076gPE/h93UxNXq53h0THbD1BYncSD8xoPQ8y62pFmm2+wh54V
rXEJgkKTgGeW9dIeBXW4xF/aUsw3puXBHOKcbXtBk9En62xM9PKKxR8FTnfid4MOQuVTMCfemoHu
w2wT1p1K0Vn7OAsHfHqDqefR4JouEyvjd1u8uXKiwIKJ+sK02GWX0BgBfYdv0PN7syzwn1Ttt3AJ
Rtb6btRpb22eDN7ZNxlutbQUZP8IZ0U1ZG2bnfbYrXCykPf1SBg4401ZV+FMNXQeE9tBTU3G9vLY
iA5y9uKlwd90BcqWB5CpA4+Mw4Mz6ZAtIOqWz7vTWpgncQJT9uwVUbVHCQyfkieA5Mgxb6L0Y8xR
Y0RG7VQIxhX15fp28GCxVBEteL92h3Lgnt5Rhq6bVuYrNPfJAezSs9npw0EGFFgM3ujWeDJmj169
HFaGpQeQM/QlPRkVYSbGaseaeXsSuSYgTPGMQLE5jtX4jGGk3OqfFHbSyyhE04v26s1b+hqWiQzv
GPUlotujSvJwTHTPstUG9d8jGkNYnWOxRFr5lvdSPrAMq3mVMTFgTTUpE06Z3GN005WcQpfSFgYf
98Ink3APLg2vlm4jez+pQ/2wF/mCFxNdlMfypPy0TqYztkD4zdS5UeK58BSGbDVIP0oCUetLovAh
w/cLKy9EFHu6bCOhyjkXl0jCJ57TaDPs2bL3C7pQUbGM/FJhKp/J8Qsb9eIJmHmjCfE1WjaGgLq2
k3HtvW6HfG0KeYRpLLvUXKSPn0PjCSi2wRM3rZRrAwZXAP4sdzWyFH6h2ZDtjreKE++t4HJDdl2j
t4y+vV1274AGzOY+IUAmV6wLMlTd8k0SpUa/5+lfYMs+0aTUjbH/DbNxtRoNm2eHz0o9x9eykfiF
fImmxMNdU9SKcEEvkDrcyy96Ngkwv6s27EXO76BfcB2TyLQMv5BqmnFBw9ToUUqlBiCJrr5uQfo7
MW9fcRJ4N+OP6OQH3Qc+PWyhyFLY6dBnE6ehyMa2ZBS4eeZxGeEhErbHyOjzwA3GCuFzB96t+QVm
szK5EDEblC376eS0WGm2uBXwssZI1UaU66DCB1xlGtxmh1QGf28E3jaiECwrgUT0UvR0wDnNty6e
kmTZddFBrQdGNkBnDlZ4tS0WipY6tknpXugLqW+teHUkOlwS0rWLFN0ireqahiO743KfV9dzIkL0
y/fQ43bFjMgPmZt3d4oYZv84DxIG665/x8BMpuLyF5OJsAaGyvQnsOXutg8ggXm998Q18Z1SvGu7
zkYbD53IxqjqpW3fyaI2702gB/SYWkQjU+F6UIyam5emmlcgkhChHasbJcGPY+/6tt1hVCP4Blco
arn9ty+xjeZooAtoa4D9veu7mBVBjCB3Uc3WMn5eFfex/V4JX6d/P725pNhej4RIs0JmS0H0E/cf
niXmZKaLhPJutqcz6sfKSKucVoSpE2/5BllRMJ4d2gmZwPePDAAtBwvi+j2O0zUWq6mG0Bd0BpXV
eL/q6RiuBdVo9rLhSSX1jvqmPCUqvrWs/I6DZw1dNYmmtr4hFe1H6alN24S/uEUx2eaptx/w7Y9T
C4qg4KgmHbZ2hHQCxQEvQrxd628I8zBnmiuEW5PnRMQOl+FyttqrABQhQmVj760mIHdFETGF4yHE
MPhrbuDLOSLQR9eJgcGE5Ym2UfQiFsZWOhR5JbZp/2NcOT6287SiO9ilo2lUlxgNExxqggdy8vOc
xMtHl16B1GQpxuu7NGrgJ7pulcNMLayBUNHPttnpKuCziY9nmeEKuiV7x607GGzH9kTanFuUzhO7
n5LPZaB1fb568BCh1MF45M3JzmM/kzxn+ERby3vpf5WSqNfjFpqUsypINWxJRfjJc11z0soKuQI+
08Jec4L8tY93qD547RthvNEuvI9y8o6x35sPdAazIwfGz8k88H4oD7yxC6On2oJyuuLarW7yFRNH
r/ufDS87IWYiLirJynSLopx1kpOC0skF9cfBv6uK9q//XQC+mUuCEjrcF6WpvR3LG/unDu6rupLW
qkAHNyRKl2LQJuvPtFFKr9bkRkwRWEUP+U0OItqKZBp+AsdVJkMioDpZMR/IXxwQXi0uomAW6fok
8ktBzXvodPU3roAJo8F8MSE4I72Ucj43Eq6Z+Xv82Dm/LyafMJFUOT9zL4KENZ1DglL9Sz3AJCag
f0RLyq7ZKC3QNWTMEfY9btqmaE9/40l6Par4vRzGoJjdVXAPRMTVIDD4yeoAgRFxTkwnceKO2kqX
+V1O6/vXhfIP8rtNTZADzBDj5DTi0BJtar+374eMGckRNKl7PrdsaUZ/H9DvV0Jaq26nDHd639Xo
/rREDszFzSj08iS49o+CRUOK0KSeZUlfzfxPyyQ5Q4u9EjEPSmbdLochUUz+OFSPoA3esFmM5Pfk
6fp17oQWoQQTNCh+apx/d3lvUBL3BZJXnuqWSmy5KgevcjCoZwVlk6FH7ARKNsOlAvwIahZNTu+m
AhDuo/LqYVxhg7eNCwk4DZlA/opw1xm40i26B+Qvr6t+etojmT7Tnr5DtKCRFeGBfsBKlh25qXKJ
eYbNr/yj0YxBn9cO4Z8jhcBXoD7rZhHtP5T3eHMT0Hz4rdP0jni6iq0FVg8WQ+dt+D/nTniclBKM
CJHy9SzfeDEwY5NgWRTmadp+nUELxhXvy7Kk+VgZxpW7JzS2eTLgxDa4o7CGnFGA8sa9jU8RpyFz
0YTcjmkvgbwxa23L/KK3IQX5antoBVpcc+d4g/0XdYdlM2rZq8GRo/pZ7NtSjjSzGYtmzVzx9WaS
t6nOERQyT25Cdykjm+5CJSlUpMYT8db4Qk1u8MLcTuOlGvqN4P+O+RVS4BLt8guqZyRwKCWTWc4p
P12+7U7wCxNkJ41IZlc5YISK7E1oKZBjCi31GOdx2PazIayrVzQFhSdhS59Y2kTYpz+yZefk4wqD
vxO62W5BaDzDy4REJEjY/uNYPnAimlePZSfm3r80npC77AnuxOLLEcoWArtx27Rnqty0yFf4/XVf
KfjPslGypVDas8FlNk7l2Jp3X0U2jKGb7ey2w2JLErj5OY+wR9BAc+xiYbJSSE2iR4/d9iZgK9XZ
O03+aRlUwzgDiVbQBjrq/WIHMBmN7P5aO4+bkOjukjmsC1fVd7W9dNR0SrF2xBX/hoTVY/ZXskRK
jYWs9dXXz+UrRSXcVoSxF+fAGBo++x38RhjA2qe4z8MMWE6ppg3D8QYGgw4XRQQ2Is+NdmhtgnWz
npdOJ2/e7NYpEV7TaVE/UDQmcnaeyBYvukx/tJlIlfq+Cg3Q68rjLkpIp83kHvO2YkDt31jmEs5m
eWAQSymqMKnPmx46H3bOT3jikzoeRzb/hKSPxZ8cv3OnLjoj8aXfbUP3voPrXIQwBCmKVOcBDIEs
Nb/i6ps6ZyZ8+NESrTYnd6059aNLjopVxHK5zR6lka/xF1x6Kq5DtBWz5k2z88EaPKA7Qfb5LVOW
5NOs+DB1tlF4u90xP8xqM5DXnxExpn/SDCL0l3XT4jfhI9Qa3BHKauCByOXqnLgVwHyQOqQh1Tvu
lHVTiE2ZWgA4GHR3ZkZ602JtchLpAgDBR0EIspScjNIKMqDqKtKdCHUR40XfqO5D0/UWhCjnR8qx
h+2ebVvW1uXOkZDZuCtolMbrSw9hPKD72t6+f7WyyTmdAax7CXU+lzzaytJdGATjyOA+f18dUXg4
BxBkh6Il8rsix9FVEP8v5lToWeXC2hu0BWbjTek6FXKqC41MMKPGvO3ypUQ4sBbeKghAk+qiHnfK
U+7F5y36FYh8yLpqZ3h/uoR61pdAjJZmXDvHYxp2BIOYTHvK/4MAKttthHnEO6zDYyAOQ9qp9vEK
NW4MyMy142ar7y/xaO1s1l5bHsUCniz5G5pzu6DE0Wm4DCoKjUKkzVqTUsPq8ven+MrSLOM5NptI
wI18rmBGadNdTGBzM4cpUcmYyqy2h2F+SrzRqyFmCDB58MLbCm2ASPluQnPeiszVn+iHOeuCZRi1
onglYrvUpgPUp/Wsm2Be8y3owl06YJhgD2BYGDZHYQL6kfs6qTc8lontRjRALnk4+7qXQu8txsb0
1u5s+shITLgfUsGccoI8DLn1Nc07ziIDc6GblSP711WGcNb1M7Bp8MzWDfJGRAfmEy+dQVuQ4Z+o
BfmP+cze6teVmAoCik2unjhIF/PRTlExV0yu4Imk5aaEbpceVMpDeHqs3w9mDc+EWU6ZlAq0mrF4
DV8Gpd15Y2V2L3LHaXWO9BZ8li+cFajE/qT4dTVIC1cvCsaJK8+ktj7qvAZaD5ACatqveCeIVoS0
0gHu4xX94V/HOT3aVqHyAjZC0Pyvwgnxl2L01qzxPKgZRGbXMekafiFzhXfwxPDmmsMgQACQP10U
CtPA6HwqeCPn9LE6qk5fAFJ7B+LCrXPx0g4f35n+CLeOf7JafZC2jSW5SJKFnZJUj/wmKP3XoyP1
Ocro4fgs/tlqrKHm/V5Zdn1s1tdfu99JXTstLhC7KgRhC9tbyLG381UUdVLsul2C0W7z4lXI1iCV
9GlCy0UCG/jGH/3XOu5uDu1MMoFOn+kJNC8GTvFTcQEJ3jWoeANoAeAKZQVl2nFS37VMHN8K/L4V
GVhtNGkSsAI/XChJJPS4BXPC4zFn9bw88PIglxCCu8R4LcYxVZcC4CvOlGeVJeyf2cCjFD/eBMol
c7Pp2zucJZShw+k16XAaLhmnOwYh8yzEuvhm+DZWP//ja+JYuzbIxgT2SB+3q0cvrz9wXEfhiPJx
7Q6bfns7BSlGtD70FL+VdafgJvz5p5lo0joAb04FG5owtvEYGGA0p7QpPa1ORN7zFC7YRpwCgRkE
vobqyoExAO4XcjJ3xUb2ddtVtL9So46tkN4yuwvneC9lIy7TLijVEOuYrJ0A19AFoI9I7HlWQI4e
prNB7RLpfYv0GYcXo75dORHIxA+rNoFAwu52mJFUCmKaGczg6E+DBdcUM6ulChSWzUsgfsWS3YHt
wm785BbfYbl+mhVHEdDGQrFddv1xBLgnAq/UdF0WIOB6XL3cTJbYMWHuj0xCWWBMZcUE15zEqjj6
HmesxfF0WqIgTkt0hFqQq9L3aHfVM3CYwcFU36SSE4SYlX8OiOSRCl5JqoriH7z3sbYyKLKz+w4T
gi+Px9sULx36VvhgeK+Xk59XZge8YlxDKow5zALfvacrR2wudv8ic36yS5NL3UEjMjWreSJIU8eW
qDubFL32s1iVbyI8hT3EwQeKnTEJnz0g9D962/BMydH6KubgijHomwjf0MyECDeKEGUgAydIzcLV
N4EeQBIOw9nbz7IqLdwKrQsy9MaxLLpSVdI5ZDRpOHbnJd11eSBDL3cDkyZmWPsWBIbad/lsFggA
GPb5QPA0YUpk+DGi5lK1WmtG7a1AwmrAk70q1jCgUCbUE74f6hEgRk/UytBJEGKMTlqWm+ykqEJn
85XX/bXVsk+RAuF21aFUoUcWSqi3ZTXOjjbbCJHbvECXmVSifPocf9ObV5YZKNeEKzntartBm8fP
qe8U0Ll3X2QiGx+ufdli8BOeHaf9dlw70vlfrVLrYZqztqKa1M7z9ZnxtXFiNaSegj/5FaXzVcfz
yBqWwEVGyNPWnYM/uDJOdlwUPssANnDq+L6lgH7rMxRadTLEYra0+Sgj0Ijbzzqg7VV4O2oonmj1
gbN/QTjfmSekAUjCbIf7SykNI5CURt+R1oheMGWuxhXYiJ2TRLkaub24sH1ZVCNU8i/JBYbjsQij
+sCsv4GeBumqCencsFUuWY2lx3E13AhAMFZYQIFcRenrNfJpkA+qV2lC5IuOZnjWhhRQg9WBnhBj
u9pipZ5EPr1gu+HoeNuSkRyygOpdT8ln/kkF8U5pLZAo0p0GD/SEsJLqXSfyDQGw0gMYxePjAzFd
EYp4zB1xqXzbumtpbiywh0i+feqI/gXwmJzoVjkDWDvXJCSM2uhxW0MuWNLzhJ4XtGbYGruNQBZU
PvcaevJrRylHDSGVuQyz1CyjaW6M8ccGzudYK7mk7zTeItTv7YLXNqJyHxxQYBIzWy7cLFTQR9Qr
lKp6IyshUpTVwxt6JTCwBgk1tFr7OS0TqNwjgJzy5XWmiq+MgUthVoSfJEQLCoA4skdduiXm3Fa7
SIqhAXf+QNSoQB5HrJbxUPHfGnNmzXP+VS9xOjXd+tmBWzYw1uL/KuWBWmIuZG4dn2upjVBgy5n6
+6JCvjNl5rGIdFMgCLCLwruS67aIrutPmGdPNfxLN9hU/7tYbvmyPQpIpSljuRWArIOBZpn1vcVu
jHh/7KSzvees5EiVplR7T1asqgDclK/TvtNaVuy2R3q7kZHFvPyp2KNjV2jJFF0B+z9fJRAGjylL
+I2lqDYhHk6sLl+m4SV1qiBp+Skh5T8g9Y8eUrtF6tfbHM/mEVeVn4464q4ca9VS0vbjLij6cYdw
VuYdEvmBunnPXPiHd3EVMKnpU4HwvUWlr1+UErzEnMnQa4VBl/CYBLY7FYyPF1Fnm0UQ7RI26VP3
jmSqD5t2wZvMVct7edDUyXhbeC+V7UdAcMALP7x/v/8TPWiDhrFz8B/T6fx7DNx9gydbW5owXtpW
JE1cIwIwAKf1T17MBbBy8SNRsOcGUw316RM7mFcqHi92L3LwGrdfvCHMAHsijRTO1P8870RpDBJD
m6SLLXzSBdDJp/oi4ryTQKM/2ZMFzFw1LULe5XAHASQmsvotwbIGdVln7IhkgH4lEgNC2BITyOOU
TxSFbWOROavC0NuV5X0UokCnzvERs4LrgRH2qak5OkpPKIarj+R7WvpL6Nok5uMS/eqdOWS0qEPg
ldSgZIoNMOKZ+DK8CzEEBLbL+J/Buk9u3hqhaUlPHAgabjCjnABW2aC+K58hdwyi9yuD/7z3swEq
JoBoYwt6hEw3De7GsxXj0r1O4y3ydH5Jkcct8cZTuZPcRaB1HcZsqO69JzWWIuWSC1XEcFYqvBn/
ilXtUuslgUhFpJHLhAUsetHmEkO556Ph60pXqQGhIFgPoQvByO5jyQNchCgKjjitcWeWw3O70nN5
5ImLRSmMee+vCnOdH5IbZnEnb8eu8mtv4Vttwoe0pe5PX4tOCOznzbvgB/ylOohgnYm4FOQfpvtP
4dI9z0aDBmz3GrmlmsH237gzscM1piIkpIFLxWA05HXySp6mGehem8yIEE6Z72RwXtOZQtEE1fRr
+hu3OTQkOzhS5O+tHwnmWVFmWG4vVSqbPGaZGsNopxiG/gPXDsHR9d4PmgkMb/m2QDf9WTJi2YSZ
QwZJtzpnYtuiy7PhQ2QBH4817QrFn0aC68LMnSYNK+Rz4VB2M/iqIVBt/5OOh+ECjaq0UsEio3v1
YLpxAUTc4Lv2eaK0viDPiPrqu3FJfnRcAq6wi9EsvCwiQWSplN7Cnq0drhm+ZM4RrShYaMMCz+3z
heaRK+4F5GsEYTDHReW7cIpCShGHESriKvW0QqdDsfmUrG+xYo0eBNBv3ypoAFCo64Jm4YnhsLA+
Ytcoajf9zVvKBxHEwPyumtrvVxODXT20U1nzQQ9fiL/Hi/mBKHyjmrU7qBSJXjZyo57GSPifRZmR
OxZHT5W5nvA0+2+HX0y5fgZxlhaX1fDhbOUS4/g8K5cjs+9x5T7S2MsS6F5ws89ZY+InbHKyo78d
DkAYcgMT6XgW9ui59dL0QabK5MJD2ZOAsSOch4ZmjRIf5cTU5ZNmdEDAR0w+NX62kVCP5aJWDixQ
8jQC+j7sj1ODD+iraPcmv6+UULeAOlRYgqGa9T6/cjvmy+SnycWWuD6W5oBq5pjBE3N6Qq/nZqwF
48u1O/6OwKIq4r3FZ8OpwV0ELrpcTYm1AM8r79OALDZp5U1mlZLDCzBlrlfQryWPtEmHpEdB/hhZ
uoVS9PAbZ5VaknR6mjkTp+DEmEfCGczlRFP3T4LGulCxYxVOsEBl3rbevOkuUvXfHbjFi38Jc/oP
mxdIy46COgpCWBmDsEpm719PWZly/GA2FCTDK8ZzyFP/NKFPOTkfjaeIoa+vKJ7k8zbxcO5LVKxR
6/K9rPsx1Qec4xCTwVnfrgPl/Qbuvwdj0gUAJMtZY7wjerGkrkthnLlUG71ka1FP19AiJfvIdG4h
xBBHeIzlRL7+o2uleI6G7tvJq+9v6C/ZSl2AVTB2vjDMpVGZYbdkVyDDzV5XNZSzulR35hbdSKjS
zEBeJLt9tqHwABFuxS5EKqNU6fku0Tig4ggeaAzTA3NE/99v5NcS5UFz/stsZTqQc85kYzKzQ4pH
7y2jSaMD0vU/MvfGNMJZt41nxF/yl32iNXM6lGeG5GQzQmNueOeh1CYD7SH08hVbp2c/LgmisllH
se7P1TW627pev31H8MIJklJf/OEjr+KpTC4Ey6dmslWLV5IDRlgTjPRGiERl0Cbe8yZuSUt59lzx
wl5ggzjuheLikJS7zYn9Ezit1hffQmsP4ShDJvhfKNPb8AuV/mlYUC0rF9iDYJv9GAOhC076M0a9
yK7sRExvyiqwxMw84OVj9dWIN5pwxilB8K8+xlOmbQf+1CPOV9W47amHBFK69PFJB1UjjOPZfu/u
bm4UeC4VRUaLmBVm4G3XVNti0Ul5MumDmbUWd74TLFNUFG2XfTPBBOG0Z/gji7/9mvDlcjnNQLPx
Kiz64RV/5kLs/GQw1YU010i5JCibWiFJ11t6wfFjN0QZlqaJ9YU0SDeFFAmA72dX0nOQJBwDTWqC
QtdQ/ZBHtPQtO1OfoyDMTMe7DDgBSzue6mZeJOYyY9kDUrpL8l9eYXQY7IJaXffC2tek5amAuZVL
lyNyxgHsutR7PL+npb1HJqSJqs208S6N+QgW22Uccw0AWfzTjV52uc/Xn8EdN5Cn3p2AsugLLVJK
hFTlJI35jc7r39LiBCiZk9n8quvHPRVqi19wTcD24m17diVWcVnQHCFyDFZUQ1cTcd+7AlEEjARn
znmr72t4aUVtN149Li/HPQYD/8hIL1QgtPO4G6ModqeZanxfu6xGF1WMJ72kkuX9e9BfEIEl4lSV
xypFIAzmbMqE05/aNWFmVEAWB6kbjsVrPnPPWJsgTovBS+K30jiAZ8h7Wu0D9za/zl2B1vetgoaY
mkfyrLhfLBOY8P/GJ/YG7G1M4a6yJ0bCXkDDBpLJwzBLH6QCk4z5V8e7VPUJTyFTks7VsiDPzLJ/
U0qeJOit4DG7TFP1544AeQT0Bf2K8E+OVfXo60dDCsuazkaI17OEP2Cz+AUbwjRfA4CjCy3R1KpK
BeIu0rwUcgpQhKhGdobXkiL37YtIZiyMmIOxyeIHz3F8U0cecwsY2KAM6iUDuf+0OvRjYmtlKezK
SF2trMWwT3Tw9e7a2e6mieE3suEmhguJ0o+bCzdXDwgFxD4uf2m72X2Lc8m6hOdpYYPRU4QfbCV5
Xwsou7CXWdxmXTnfQ3l7+RTRe/Vt97h6li9C91LT0NvswYp6UfjhLUweVRnJuFt2tdmI2bbT610k
IEcK6AZWFqL4TrlTbB7rFe/MjqStOQFLQQy2FNNVcIWkdcbUlVt1vwwydKROPV7SPTFdRsn8jKS0
ST0eE79qmwrFHHpL9vl4SZ9rhdYPuZGkv5blSf2cMTuq87H+5CFG7OlyrUSCPzk3wQsny0/9z997
1tLgYljjHnw5nCf1vm0wEWRgitbpqSz4m6smUoJOEEtOpG6Wi+IzdLvbhnD6Kd3yjH6jdNzrwkb7
Wwv09H+nnVrl3rw3rha4KgUQDVyW2zIyeEEI1mjMeLahesNctfdoAPw55p0lSEFqIDzIL4YS7w4B
6wH3E/7Z1sI+LVLTfySYShyQ9oXJukj86dnsatcfqD5L3f8QXvjCpEKLAKlxHYHscBT2Yw/9uvBM
KHu2Pkk/wTNavDu7Kv+lpunIWrlBFQxjz7+io6axqMxXu4JjHnppCTuBpvBHmnRMspKij7t6cpOW
Lhdwye3nS7LNGZe6v/TawxXDRGuPK0P4gf5lQsff2CBljPNGXM2fDWaD7ga6bm40SsboYd7wEN+z
MdUnEXJgM6LgjMlpgHyLbwf9coLW1hPHEvE6Vs4ndlikMR1ZtsaOR/Ph2jOlBM8tI5KbUoPobqN2
mBsgKrTRd9J2OFnM7LEVkkKoWaPZ/mmwTxcNuqc7/gGxpXCVhm4xlWFZNRFPU9M1S4VftY3vfoLo
w1pV1imvFvlOX0wzFw2gJ78V3EHh0QBbcGerEhphEA3eH98RqHIu4vlYMpV84y3j3DRx6e4Lkg3q
uBO9ANRKTJ1iUQWsyXSHK2UGRJ92LtdpRi1MmfDnytZHGwgweObaquUBEpYhrWbxXhOr/Mk8rRuB
aYiggw1y33YvAK4G8+k/LEoKUbd838ZvYtt06LkDaIQN3cPYm18AiPhuGItbagn+L15vYhWoZPkl
KPufvoEtNwhvMJMLr544DNnUrnU+3Igb8B90puftRpT7mV6a2FWs5gO1wonCNHjxYhbZtPsalY6/
tQfP7Gn6JtuTkhErulUlQvpmpFcvzHBuZxlYCXSR0OxE2OlyldouYClcxgaA807L5ex0xUlgcO90
HAr2U5w2dLU3LWkKSHhCeMESC5G+LWIwDy/jGfMhMuVKMe63GZQKWdnMCkiguTrVCBX7q9c5yIlw
890EpM5oPP83Qb15dcnBeQW/w5uYF3NLZCtBO+cAPjtjAPJYZXkA+gMVa3QCzNnvPu+UhQVZZWen
S2YRJhzt4LL5CIAnm62k2I+FsXULNaCn8BNQOKOSXSrT4zsVmKvaBk07nefS9iWBbeyy72t1m/4m
szQyH0lJQLSWkTwKzpKI1U9tDxR79saYqj+WL82JtyYY5NEiaZj2i8a2IOABF/yV3iL5JErfGgYk
Hq0Rcwgw0Eck7IyhLUcxomyVrMMPYWsWKMURv88hOYYCW/37ZPoVTumBdrf1lrpSybFSUasn3TOv
mTGrCB0b9bEd9wBoqkGB22CN361paAEGsIR+7i6QeEY0PFjMhyAkWeFQEaxXCWlifB7ILn/ZHHL7
91KpHWmgSj5SfdfDO/FG6cHJyXUa0NEpcrhhZgSBBESKIeJUiQiOafvoulrqsSOY0LKFfSJECTSs
I81A+sybB1IAuwKwvPc8po4g9V9S11q3/vSfDHKXTc2Lks+yHr8Mz8YvvXGfj4IbaZVihZtuctxp
Gbn8chOMiJFtGhDVNhUQiMhlonHs3J73MuN2gBna3mpJ8S4BIU7J2qNP5ftQ2yghuVkHXp7OQyTC
uuy93GqiT+0smnbxGdumKCPbG2JqGuw7YUHLKX6/nuuvHY1ElRin95uYimf5VoQHImSc//zyFcVU
gd+VeFBt/KSCC4Vw0ZzvwchZu9gF/2Xh3JCnNmvinvL9xpZhWrFyQsbjdJgpVWU+xRDlcXn+CeLD
ZTBltdomr7Llep8O4b0K4Xy40Mc5YDZuyhmHYtSuVNMx0G4fxd5kQpYJzLQEFvQ7i6H5xYmgTf28
xbu0PvI5GfkGpM4HpgLLSjLatjBW1Km7o+pgHyOEyHVSapcAx+ktLAuM3gvcWMSoZRthhLBig5h+
Lhp5aocrZpISOGRLYegxKvMQKvXfed5zH5lACvN6u5p9RuJQUBbHD7u+I4rejz0WzeYVDO6s9NJS
RG9O+UJRfu8qZgs8taFj0lB+RPcBmQHjrfMZc1xh5AgG8EWvNYInk1z4TdAL9qn9fZiGhfPCNdHV
hYIDEqFVOb70kBhHuLYrLzSUJ8e9F7rroseafAzT77czcEwNRUFddRJ9o83O8ifxLj0pEDpjNDP8
nhTN2zwlJ33OAWCGW6hStFLbdJOScEaibNgc5N+BYaFStLTSe7D5+SLfvjULLekQiUjv2nyjOuyZ
FyPEj+PxgRSvilx9xZYNyTw3oLBVoiEhTbwVemtflSqB7n7NlgrWHHPmEB4jt0Z26SUDjLOkgGXb
c1Cobwgc24AetGmRA28irlpJe4UrE1HSmLXIqdUpuF5gM7STOAeEb1Taw1R4b+NI6ddQ5r3jYsb2
7BK7UFLG6Ulq3Xy47CbyhU0yYvgkGKZJvXpdRWj0UcGJtx0xbKZ67hDCltM9Qq5u6B084++dc0Tb
S04b6fT8XKR1WIZl7h8NVm68Gf0yThh3QEH9kt9xYctJdUPunzgzU8wUh+ZUgwQk2wOiedeYJ8vv
PsjRgvSY5vZbNg70ejnOwav4ozKDaGQXZToa7of2JzvIdgINA9YAKuO4mtLotcX0zZb2xkFxrPV8
G7+Wuo2pODfs56rBa0KiYFjTKryLUroMEDzfBP7R+vmjCbQ0Rn5T4NVbv/gxoQOKtZH58TpfPDfD
AjqgNbRUbRQ+uQtUDRgcq6hNCEJtj7SFXTzPbKiKwQ/5d/y4c+eLjOwHrEeqP9fBkh9QICcF2XLZ
qszUDRAELNI6hakLyn7h9IRzTr2iWEzER/SlgvU9QIcHY/JYDV4JRL0SQjInEjwx1/V5yE3q50D/
de2e55xejXVxV37B+5DANUrKWtGo4drxzIWnl/nXsYZQ2ARzEYWGDaurv6DkFydV77YEC3De9Tg2
QsuV3T/3AUte3vbJ+WYdkYautI92fzmQf649ClAkCzM22008zdwHJUTLt/TJHZ+/85v26uAMMb4N
1RLWBrXEiNH2wyC5/5KOhzdkNTtEOFcsuAuFbSzItjNHJS8U+wd2zoJVJciyPSdH0TaX0VCAUF2n
7SnhoYsvVdmbW8Dl8C+FQ4XmpgGmW81ZOyvSJwfBLDPfZQLL9zLCHK8sfyFOeOPP+8/oo8FTwQUq
M7nzEs0LcMD7gVraEc/ZdzWBTb7B/XrPLDRhWJu5bQY9+9OaTGRn+o+sPQhMFlhBmky9qcEC1LjC
Lft6qGkc3WePcpmDbB3t42eLgZ8RNmpqd3A+ryDRv2396Gi5iXs/r/ZlvVjNN+LV8lkUuQIFhoOY
JSC/H/PNCfpP0/R4Eqh+eARm1iyUty0HNmwkdJfADhRXVGUKThw/PIFNhbF8+FQEO/V+6CelDd8T
6M8FcSaExXVduu30ZtM+7eHp0oqQJlmaXWRyiQLIAkZrD76BpB9e5bhMCgDpHo4qbch6NTXrWVY+
eh4v3xMEBofVCTkxwOrkU4JP2NoOvBJAHoEBOoHToro/bwII3UjQX2FM9nL/apD7ae86EcCN9iid
yDGKK5GKkmTlQtP3mgaQ9JCGNh+rYfRNX6Nm9xufoSXIOXW6y7OoQ937uqjpdQ6UqVudbFKE4IxC
sbc+YPD16q8nrAwezaoy5xYBFWBUd3HUtKiTEGslHmnIbdYgTz9wLxCcBNjS3VXQxAs81sdusw9H
IjpP71dWZyTSjtzbdvZ8LK+h0+9OlvlM2EZ7lWXHd7KMr2aShzbJK2wNbtcXo0GVUbPX0T10zGgb
mfxL4LgMlQJVjm7GgsyZAPiTHlsNwSCvCva/9ZCuHMMDlppFMU+qo50dxyDD0AXPB9zw+ZSBQeJ8
3d7T0IY2YUEoxnNd8G+kq0Xt6rqv0WOGYhaH9VDK4vvjaP0hcq/m83eEBmnf72hauQ5YuP1nW12Y
B+iBgahzGY9u2601MfPHqgcFfa1A3KS073BeRrpl0sgEq3YCWBMwG09YUwIjDTgxwA6Bi5vdLqGB
LOgAFf8FrgSwjtqd1PSwrFUbjnik3p6/DkuqKev4AiV0Sjm51gdpa6/OcnoOOCqHvBh8SAakAAXt
kdUbDF6IT4wuaJ07TXVo6DTtSkIUVx+a8mMHIhOVl5n8eNDY8KL7+vviu7avkCYh/+emRhis7o9G
9v0MpHZIehcqNQTs7+9d2bPbmZqDs0HWWv6k6wpP5vs6l49vwAM8MgzBlZNqf5vURHVn/ABpFki2
hT08R3XNlZ+bQPtMcn1Bea5pCyW/KDrNGqh8Qi5r7DwZ80+a6eNw8Cfex+YwYJTth+C4oilEhzql
hVsMLFf8BuxxW8mD3PZ9FtIO+5nZzGB7NBnkU14rTIt1rXsyXAplapDpmikxZpa3o1gbLYymzrPu
tavHXd5JVTYRqSNw/KWJiMsN0FLGAYHqd2eyLHqj0jNSN28b57AcuJ405GVRQEFP9hGeSCeKuVX8
m4sEKU9xkkQJCjnH//7ef/vGxN1jDJcagS69wPPkmh8phCpnOw6n3V0IVEfZWG0/3mFR+lEzrvSl
+HXTb/5m1Bg8YywHXjwCKyEgIx9jx6QWWMYVI2jTBiYScStOvEXHAhsZAwxr/5pXvAPmQZuqVH3t
vKzbf3/t4iQrUwJbB4WHRDLx+O4wbKno+g23V3oU5CfSRaYtqAIcAaMEHzwveigwHQr4solMW/ct
IIUv8pFqJ/J/bSKGhv/M4HUbP6nOYPo0E1c2PUAF9XL5gPhVGyclva3FZWjLTQyfAwx6rIVYo8fX
IqmHmIwqyco6GNJjV0WKN+B7jTuZgpRQE4NKl8sF0eyf/7B/O3lnoW/+nPhzqnKx2MMZWHK6Ms1J
pXS1ZrDJ8tNiWV0aExi/NOTtPXevLPAQXSUVtwpP9iE83L8mr1E526rgSvhqBNEYfaBROCY7LCmG
qZ+hhL/HyDQP4JD1D3Lg4688gSpbIu91pO0sSNShsG9ODVbczbWh3zRPLUVTTFrl2bWjWz11j26J
5sYpV0LTasjjTu3Jwt51wbSJLSre1011WFSnnnCrQbUsIqOBfVgJtp7R968axgbZdvYC5Rt/Xq9O
4YDaV9WVdYbYToKEjjbjTKNoIdkQswqTcKwkxYb8qJ+909jBs9g79AnrhgmdhpAoAr8daF05Rgb8
7xPHKOgmLgLSMTNhDEFK/8jndmH+JXu1nvriC2x7yMEpkce1VAkLekAfKrKwmGnhjKHn5pUKYguB
vwubOdYSi5YlILYrvQH33RMKeBen/LT33kendoKeuNMg97sBMQ0CRRS4hXdg3QfRcH9Wyy+161t2
mepa49zyxF1FEFa4EGTYhv3WIw3sN7sjXESNjglhJT9U37Qa2YIJQxyYZezgkhl4+FeZTLwlOsJM
7o+uc8hKkj9Yxr8F1eigVA+9iCnXdCEn1KYFZ75RnDrrtzdqxpLhlz4Pw+wCCZQ0j+5O3Ly700yj
RmEo/LWprH4J0DV77+izDsjLXschVNcxqCxJ6AHLUamJ2kws8pNfmAi7KAuEAyEQ0qRN7GvUl8hR
3vd1v2lEJjamt7iuya2WPT4O16H7rdGMKTu1rfufcoPZNId8SC+L5U9E/Sn7EgWXR6eN4lks5bhe
RFYRNtrClQG+/fz0a4jFJ8M1BIwvbizo7bQ6AgTbMFxCu7SWgR1PURpsvhtAkhRLGBxHeU6Em1q6
NeIuVAxUOang20rtBeTXBBzTwWmAeOnbH0sEzV9d8Zg/U8G3ZO4oSHXhCv0TFPVtfe6aXaE/MRv8
DafwbGuio2pnSbWnRtjYf+0d6U3/cqzQxfYnvrP/C4VkgYPGAK0+b2NSo+oUCa+pc9fWr4H85pD6
Y9PD0mD+UjmSajjDky7oUsLjm0lydyPb4pRcJaaiVeDq1EU/JbiDn7+Sl+PYHsVoXtW5xj1LY0iR
4A5UltHxo8CtGX+FcKLQYMOkpG5jtACekWrOCQFEIU+dN0gdkr39Nqq+BfQH4v13pEOxBbS4J/61
9W7IdY/FqgAJrE9R+yqbcZ52e9wKrMJf5jt7SOWtsAYYUPXWxTOjzI1vUdPtCoWmkXIUfAFSG/qV
x10+NQAVTVhHw6ZOT0PV7UYgPCkmK4qnNHsONfDaOic0UZ46vOx3o3FBg6SjaWYIvCnl5280ginr
hidV80vVObuCpdZPiky5//rYUSzic0cb1LZzoIREyehnrnOdoCNHjSIcGpmoPrvStUXkQZcU7hvf
yA827Rfc6LkTxQRXVTc2uFAe60OubmFKX3+sr/Lu4XvuOyNR6exC0+cErX7qsCDiYBXghrfwQUDt
5pP4aKSUlWQhNEAuDKrSkZSTZAFalQPJy7dvfHvlmLlQC2N+RGfpD/nXNTRBz6qtalIfKGWInCKD
WTDyWjgbEHk0ET1oI6G0oVYYDRAovJlCplEiZu0028IlS9vu+SQuvYc5lTlSckCHi7rwtQ8vgElq
iBKPh8xHzRZJI1665KJfjAr+lSY6oDACEU0T4XgBTczAxrzq35Ta7G9tLso0bYlz8sFcl4sAhMwv
HkTGs28SB5+pxF+mE61FAjUdJbW3Ug2HZfGalGUnBSBJ+Fb6Ten00wE79eRC5BfoRBTR26xPmkMq
S7bTYcb0ZZWQxvg2oTdjqDQ9MY/Rhs1fd8JMPV/2CloaGn7Hg2KKSXKi87LAmzeiiuDHsTqZv81F
PrHT+CNXwUZZOYXS1I10jSktxylQI2G90v7rl6CfYpWJDyZPEfLtW6AUVK08u9BR7u6EhoJTvfOO
nODboVLDomxmo+MgqxvVmWgxRLE6cC83k5vpP51uMtc0X0XofnCnNH7W4OUeEdupk/Ps/5WtzTAg
pzqt0J37l2pGJ55CslGsglqqofyZ7AfeLC8YDP9p9erfH7bSN7JmPAsIb2FqfJU/Kc2csEhC7dKs
7Oim+9I4tCUTX4TLyqu9//XulL5mHhDt9mfXneoGojQNN64MGntoiK7FMHVBnlVmR0XGXkHRnlGk
aMTgwdl5eU+dZkKzLrql5ba7gl8+gmMxukJX3611Ka1uAvRuIeOfx0zYlXPWUKTA+U+skTAGvwjj
/6Tc5mmwt+IftZbNpdicIcjB4TywLDemeVj56ItLUG8kpHd6O8ZiwBcSDWUT2im6X/f4ORva7yo6
gXP9qiJgMwNA/B788b9R/x3LLVTuDQtsWtrGYFLH1aNJBFsk9Vyoqq/t/qiozeXn0h4yarLw15vO
q6jeQrMti65ROYtvnsnMKrZ0XT3sE0BjQxM7KvV4hoTPPTNmCu7yjxROYFnyavYZ19/K30UuRc1U
1UUPWo4K49MxrwHR7JH0GTb6juEAFsKUAqhHDEbSpdZFRll0UpnybsBrqdZBcT77iskviokyiOmR
1LQgyvRvbEgF8k2cRAxLeWf1VRmypc74ZK78btoPS9zINiS9/qMnGnxBhJySr7V3qF1o6RvyjFG7
1YxjHGNJw3ybvDqdI1xgRCzfkPDuoGpgqSTGpoed+XR88H4nY7sr3YVxCH4ieDGk+6hKa4+1scSS
wa15J/b6OZ3p9tyYs0SwNzj83f/sVWCfxpesy9vNRhssctlky4Huwcp0/f3drZxBbaQftC1ZMbhW
/aHwOE8dgQF/avK9dsPhwaP2k7jnstKj/KME+eENB4vQuBDB/0D5FESkAz98UBwYbQ41RLQXSA2+
LpmSAKG7+oLYb0GlANI1ZsYewyVBHOSHnwsMQEFf8isuaok8Zfvionfv8dtA9AR2mQHY2IE+ucPl
hzk7Ho1K5jIVLHwq4YYh708YezPy/DamfovQBhW+1Jho1lxVWE4zN8LT3iZggJdr+vQPUdbxT9BD
yvBF3UngFa3fNJkvUBqsfb27XS5BfoYxT4BhFklsdQ7zwWg8+IuUcbWlGTRBwm8z6xlvy2X4pdoX
tLbZ5kXGJUYArZwKOiwOXg/HHi6bz5+9ezmK/RdnvhDzhwz5gEoso/emr+UoH9jzeUndLk8Cg/qL
6+gems6rOTy0PckBQ2Zy1/w5ec+rXr5uSlCypXaBMdhhxZ0lDmpWHi6YIGP9cHzvuZLNqOtxiSFD
AxLWTNr54L/mbaFw7IGLR4odX1WTrs86TyC/40TNoXThDeRsYGDMjhjb8ij+pA2RlNUjP0L11jfn
E9kCBN2/coeMmWHUC+v2CSJ0Ig0UiEghGjvGQvjZB+GfPAQrfDZwzYrIXzuBpVuQVlG31oWqoG8S
MTqwy+/FaZcgT8ZRdr0bmrHOSRSMdeMvsVQneJXnBcDNTievGYewgyfzJDW+7q5JoJphKiB6PeWF
jRW9XvWGsyuHelHAMy8LQxN9IoLo3z07qRUPsHXaBSNcnSpHsDOozivCF3JmdpzwfjzQGx9r34Ie
KNzwZqIQKik6gDOX2z3EI8/dJuM1uCvimPN+Wm6ArYx1z/qCwsGxjPSVXvgBkh86Ch2Ty1cN8whK
4Tb/JNrfX4du3nXwfrl1l89/9Ss4pKtV8BdDd0EdZMOS/w1CNRdZb3Pjb1NTAaFAkIZzuyXq/HMT
p02DY2vFuNnceRVsepbx0t2RGY76miwGFTtC8qNpqMdpGjuDmOUn68vkuYi3ma7xSq+7FA2aEfWL
D7RlDagO2U52ALPIdrbY3grIiTTWj3XZyDOdNxmpysb1pmWdTvple8Q0nYTtn22rvmJAbDPjAvkD
cuth1nmX2+GuQz/ed7YQuluDHazs8I2Rdy5fOsGzcwjDO+UCNCuBXOe5sGJA3/Kc1A+0I0b/te0l
eVWPF3VhpIr+ZTL7CEIFSBRgIJ4OVKCamwNV9ydlByPe6QiVRZ2n55+I7B0/i3AljbzbvccnGSNa
pQUGFvecyRakcpu3rDhyE9KWALsHFNoDdUWvzBZTJqJeUmSSW8gnP2Jb+LE30FgM16XLgOOdUIma
irg7KHJhNVcsts5MRjQBKeuttGv0F1tc5wkwOthKguDJAuY5MSUL6gsAq5gA4nTt4oE6uIoSeRrr
4eC7EoIbJHnHLqTDcEHH6pmk1BH86pf5W2ghmMHBO/AJt8sdmSHuD7xyltRjuAmFQtnKLZ3/66PR
MnajYs6Dq1kBAeFvQm99NC+/s8GOiaEL3toNi2hZHXSe5+j9cEI+Qp3ROFosvkyV3gUU42Ha0hJ0
Kz+47zvxYwED5ES1+S+RwOl8LgoQaTcoID80fsK69hIgsyXRio376j/0pBPujGDZEx2b7ztyGgkE
lb0n8CKYYc2VHCJfpbK3DXzoHmHuH/AJXod7qh5haIO4o2hqToH+aj2a4eeECjpQnwjhE55QMg+a
u5VCUHb1JbUMi6gSfwKYaZR7Jx20z3LNAXpZ3LPW7HSjxa767OFx8JLHvgQwp3G8Rjdyrq5LdnnO
ZRo/5xQC67IoWIYZP092zNtLwo1hkGmFuiaQR7yIofPWrwTdXKkZQFjehMwco6Qgv+67ehOenfiU
uIgHrclA2U6mwqasjek/KmryjgMg89H2BtJfaRznIBl2LwKBfTD2AoQJ/zhopvJHABbGA2RXFpMu
8g4TwCuWUAAqLFLdfdr+FhQWl89mYozDJcH3S9PBfMmMVVa5Ggz8lURVjKcg3yY2+WuTnV5ZEPRx
qiAWz57P59V/ATUsXfScRJHvvOFf8tC/gpLBKe3CbMx0HfUh9vqexyKahjnOUlNseCxATV6cDbf1
N/hdbaERAz+xgz6Dh5LENEwgUjNIn4Dt/uSsfXbNnliL6hdE0VaGkL76HDfjrdPm1w/Uol1CyFvE
0zjDNrUjrptFGzi7GHSsJZ32+sy2JF7b2w7Po98Q08MQIRsuvSaRx6vYjg+UpKZvj5IAbDL6lieY
FdU94SqqWa6XBYHCDFhn6VLeX8tM9yB/pNCUGgo753py0FrkNiaWTwuttgN0v4x8kSXLIAlxe36+
YN5ohHQBmLr8IBDvOuhL33n4OexPOE3DVlshLZC+Ec2g072gUjhhMhVS5uOLU3DzYST8sSxqFxn8
KyZuK4ZzM5bfSfGlRQXRbV69AyNMAlkJsFj/7l+Q9TTVO3WwEaldE7rTA5oTj0j7TUqtZk0ohjvU
pXF1jx10/a7EoJXC7NMaonRnaYrhoeiu/26jrH94xXKqHWh2pFJtz6GOehqTbhy+S0NiVmI9U/HR
3/QcHFv68FeJie1zutQPA+BQcYr5u3/i6Rd7Pjd9NcMOUEMUwtYBgsOwMLVvD31IG8Q00X/zaPYK
y27CRGvB5MeXKNNWgeEDoPWEa+gVI6uKKMM110VIuPgM/Jj2U8Tbi1I3VraIASJ00IyR414Zrw/B
BMi1MNquwOU0tpxorrhFGP+Sh8Bym/X9DtcHR4Svp7TjvXiABM87OFMs12iI9HFLxXh+7NH63bYP
VJ4PoEYraNc4671+i+Ny+NPoHbLhr5yi1tiW4YV7YhaXdmMKQOcJArkNnEJdKSpQ9gHag97UOv45
DlzBfCYHVpqqaLdhkpP5sQYsflbHiRdSBjkFt9s1Pg==
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/coregen_comp_defs.vhd | 1 | 13913 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and AXI BRAM CTRL when XST elaborated the client core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE coregen_comp_defs IS
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_1
-- Component declaration for blk_mem_gen_v8_1 pulled from the blk_mem_gen_v8_1.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_1
generic (
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY : STRING := "virtex4";
C_XDEVICEFAMILY : STRING := "virtex4";
-- C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_AXI_TYPE : INTEGER := 1;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
--General Memory Parameters:
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 9;
C_ALGORITHM : INTEGER := 0;
C_PRIM_TYPE : INTEGER := 3;
--Memory Initialization Parameters:
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "111111111";
C_RST_TYPE : STRING := "SYNC";
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A : INTEGER := 4;
C_READ_WIDTH_A : INTEGER := 4;
C_WRITE_DEPTH_A : INTEGER := 4096;
C_READ_DEPTH_A : INTEGER := 4096;
C_ADDRA_WIDTH : INTEGER := 12;
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B : INTEGER := 4;
C_READ_WIDTH_B : INTEGER := 4;
C_WRITE_DEPTH_B : INTEGER := 4096;
C_READ_DEPTH_B : INTEGER := 4096;
C_ADDRB_WIDTH : INTEGER := 12;
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
--ECC Parameters
C_USE_ECC : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 0;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '0';
REGCEA : IN STD_LOGIC := '0';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
--Port B:
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '0';
REGCEB : IN STD_LOGIC := '0';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
--ECC:
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT; --blk_mem_gen_v8_1
END coregen_comp_defs;
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/or_gate.vhd | 15 | 9199 | -------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 64 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate;
architecture imp of or_gate is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/blk_mem_gen_v8_1/simulation/blk_mem_gen_v8_1.vhd | 14 | 211393 | -------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: BLK_MEM_GEN_v8_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_1 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_1;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_1 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (BLK_MEM_GEN_v8_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_v8_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_v8_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF BLK_MEM_GEN_v8_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (BLK_MEM_GEN_v8_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_v8_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_v8_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF BLK_MEM_GEN_v8_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY BLK_MEM_GEN_v8_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_v8_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF BLK_MEM_GEN_v8_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT BLK_MEM_GEN_v8_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_v8_1_output_stage;
COMPONENT BLK_MEM_GEN_v8_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_v8_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 2 ns;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
reg_a : BLK_MEM_GEN_v8_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => ENA,
REGCE => REGCEA,
DIN => memory_out_a,
DOUT => DOUTA,
SBITERR_IN => '0',
DBITERR_IN => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN => (OTHERS => '0'),
RDADDRECC => OPEN
);
-- Port B
reg_b : BLK_MEM_GEN_v8_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => ENB,
REGCE => REGCEB,
DIN => memory_out_b,
DOUT => doutb_i,
SBITERR_IN => sbiterr_in,
DBITERR_IN => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN => rdaddrecc_in,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: BLK_MEM_GEN_v8_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF BLK_MEM_GEN_v8_1 IS
COMPONENT BLK_MEM_GEN_v8_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_v8_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_1 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_1;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: BLK_MEM_GEN_v8_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX8"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX8"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY)))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => rsta_in,
ENA => ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB,
ENB => ENB,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: BLK_MEM_GEN_v8_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => rsta_in,
ENA => ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB,
ENB => ENB,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_1
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: BLK_MEM_GEN_v8_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd | 19 | 31831 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Pb7E+qNVEP4sE5d3TkwQJMYKTR/FjAPrexB6qdDJcLdscPV5w27UvNCqw/kg86JgS2hNrfoEvTNF
uJ9eNTpy4Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Egq1eCtVuCp02bpffloqFi7UMw6fphk3UOZCcejhe9NQNeC0Z0b1+S1NY8yEfAVY74l4oz8pZ1vA
hbrAzplanZae/BDY57rCQ6UjD8G9keaOwYv6mG13f+m77D7Y1nVpXOE4Uujw3cZ1QgwXR1H4YfYp
ysjb+lxmo0pqYRikRIQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KJqrZ5TKkbTlecBRrKRCsxKhAd1omWJvIin7DNafgTE5a5N2or7GsTSawdWWjYWHESLBvStvRGQE
jVUeK8m63dYVJN98fa8T9iAHTDt9yiBRki/VqfvAejvDOEI+l8row+LhhHMvCd29xmkCeQKiq4Qt
hsdsz+jNufnCYY4Y1CVO/4preMZeG5Ow85vRd/341CoWEOBji8o4pk0XyIttBBgjBzWO8JyhLpza
R+Z8LgFoZ5OTfgpyTJ4SjYRWp9IHP2HL9TShNo3PmM36nFNBvQSLoEjLgk4+rUr657++ugJH31/C
Y/QScvwJcbqMK15awb6twj42y2gxJSFzAPzSGg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
KxmYEF19quU2lnDIx1hLVbiBV1iU7MlwBSbpQKNAVv6HLtZNpIjv2UPtz6sPs9Xac0T26s1Kjo2c
fAw+uaSeKdgWE1BMMV8ya3nIO40+wJlyaPYGp3qW9dt6kM+FZZl/3MCpgIMx24FXg4CPHrHNKu54
/3DZJ7o9x/QjyM8WSeM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
n4InNydlMoO1IH7Kq1VdB5tuRxM6d++erhleefbfKU7rQGdfSjRtqcQ+h67LKfA/jQJYdDdZMjd3
Jp84+E2i9v4ovZP9CPOifgPGXKRtOz0XzimXarAjLF+OJp3As1WqoTrPJI1DspdbqtDWx5caLezn
hcZVfRSFpZUoLc9H0HW6DXtxAWvJT8e4ntjJYO6koEzzHlZPpMhXvbbH/rbArm4iRGWLOVN205Pq
oJcFHv1n/e24XGuCRksBqssUXd+D0UgsxKn8Hy5kQi4Q8xdFEXxEOVBI7ivvG+HKnJFOOr+UNhLY
+rNFOKSwlDtT8tPfpzjKS5GdaTuv7j2GVoF5Tw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21824)
`protect data_block
GL1YZYDJgDckyO08ofxRV1/pUFEsLFUJ7FG9V3wrU5q1PVe5RR6P10/MHVXWhk+5f/BIV7iGCM1S
yxrVJWgpgQE0zIKk+cqoane0m/fhmYouNVngFOzauOOSHglx/Xj1qiziwsB6rnrm6ssdaZHViXsy
qd+5reSc7U7KPFUy2UIP7UCeKR1/Mfd46D/BPP6QPlNQM3r4/SrTCwKPZZ+Q8zK3jAXyciHfyvuy
Y2nXTJ/8/xTMjPM7t/Gnmbz0DoIH1RJWvsCkyHMsHwgPkg4AzC8WlHoefcFQJPxwPEH8pv8oIdLa
aviOnBJU57ToHZOtEOck+2AWqCf1L6VMpdGgJUnxWkIDathwDoJ8iRrpzUyz046rlY0tuAv6f5FD
HQ9jXr3GYUnbGesTWa9DdO5KnSFl26UOtGG3vEZ3qCvzrVhmENEx4gg+pYCxfkacFoupDlWUg2Fz
wWD3gNWZPXpVd+eQE8iJVtdhuGsObpU8ZtGNzqO16j5sPWzS4anSQT+81DTxw+bvw3o5Z3PZUMxi
CTTmnd0Y9GLe2wfrYfo3PkJrR30yWuyi2cdZ5Jwx3NNrBwi6lacj/NPTIbl4eJ7Map2wKDL+nsc6
saEUCwtFM6RHPrYz9xiqGLeEohToyY7VRmnEESrjCD47YkLFKZHlik7kvpfUvbMwBYVhedhdZ+84
vjlSDTmluG8dBm4CCXVQcaQE2Pl22IVm1u97zUrYufiFwy9osNPoOlKSeT4S3h5+5IlzTmbwOInb
T23s9P8VRHLBgqfABAUabCClwJPH2oi9yf6yhV2WS/zU/ceHZEcIXrl5b07z9+L2slj347lpKdHv
ya2SknjfhhohVmu+iZYuWCNcQduTQteKf9KOWxR+2fbRxwO2SBSM1VJGFt0c9OrQ+usfpTftyKSQ
Ux8FVw8mNobabT5JGnucunxvnDuK2B1M8yPIJLdW/ap4x1PtolyAQz5cw2cLX1EoNG1b7YjNs+lz
qbAeE8i+WaGR8ufZtEz7z5ZBQ1SIQJhWW9MC3kunFWZDeg8A9uPNl0kJxU3dB6xuVl4q2/TpsrHb
VQJL29H0UQtKcGG76Bo2mLFpoTmnhuZyVI1sUZWmkLsOLfNF4zRtOxtaF0MBZFGhhLKnmhjXulVb
SI9cG3nsObYhF1CPRsCVPZwGUg/2pYIt2rH1B3mHruUSN9UrIUyKd6FXMQ7GaB5B8g7l07oG4WB8
Eof1XJpx9FV6FO+aYuYOSM6rHfxqqSqnt7ndr5aMBpMh6/QbFHruP5Es4TPgmE+XLih/9DIw1dBK
LChokfMqg3KdigkNSwYVp9tqaWAPcmNm1Q0V90ikaMxwaeAMj0alEoVEP7M3GaOemUnn30Ej5nZ5
X1f3lvobLpLuD9nojK9VqFbknH2R76IbJ+3VSRwYUKg5cpHghZBpmN9kRmWWb++hkJMXa1p9JI5O
lO3TB7G87iCTV1v9gThSrNr5nsJCSt8CO6Bf+NXNvPz4oy7sLT7zUeLdnEPkfE80jQ+vb8uOVact
woQBJfuH86F+e30E66xp9buL91Xb0aOb/NMcLMSpvpvSh3uHEISXyS9NALmUsxKzWD6jJmbYgoLI
wcMB5iCuKIih4sAHM/Ts07tcDhAxCaHdQPvCxI+P5ZoVnjgpbkScYxQzR3Dw4Vb0p+0nv3Ug5Fj8
Ym4sHnC3EP8kclAEUjP+vvbfGVo2TMxDkQZFRVuFeVBCbFAhlqkJES1KoRHdKx7qiGrMeTJ4T2MZ
g5HTx7mIMDxWqAIf4Lj6nhI29THih26hZC+/q/724Ki/a1rGnSDDB9XozfzHIhGTa4+STP1cm2C7
SYendl4HUuL8dpGMD2IGx/l1Tem3S6afwr6BVlU+wReKxpRTvglHZhYnR7wyjXqqdfoaG1aOXxyL
jMrgL0WtKiXNN/j7dmiEn5eQ4YvaNucbsRpvv9tXNvZIXfezZqVX29DitX7Fvm73Ca9oUGiNOkdN
F3qBt98Drp6bMIl7JtyXkzaolXHupugznCi1T7BFXumY7mSrzLuvawKOjmzlAMh7nSBmty8JEiHX
T+M57PDGuySgERDBhksXC7MtxOdVxvcREvPZp+wjakWoNPOEc3M7+ka8QxhW0L3D58PYFsaBSBx2
76Gxhg7o9dGMTfrdPBW6IrJBT5d1ycSBBhro2VW48OgqU7z33WClLzqeLXPDBzBXS9Aj8Eh16Y0F
/Qk9Q9bzJsOZBBVEN+ZU80lf3MjtUvOacV6UvOX8ngAZjnG5RRlD3z96XPOVZj91SaTJ1IQ9It7j
Wg3I6nfM8hTR2W39JjQiduQcubZTbWcqR3X+x8puhUNvAcxURxHJagOSpOfYqWVBtOPYtWC3S2md
6BMcyMotwK2sPpuTcCHv5HsOpb7ZiMa5OMhAS5HLSaj7VkBXHo9Bu1IpuaqLFUJ/5uDzzwNIsJCy
hmFdgyIuq3JwNs2tlD9K6LQkedkzS3aClnU83sJpFLogm7frqNtrbun9Tq1sgOtUqnl4xEbLzunJ
l/LYY5WGgSnQYiQv5IDXaChaujy3d3Ih5ISSb2ZruEtDn6EZAjcThefiq7+TTwgiMgkHobbNmiWV
MWA5jufViWUciakKo5Lv5hwerMMHLIaqrKx9O5Y5E7w5R7U9/hKhMQk9QjBuw41QeWRf6BkNnRU0
n8oY3thIE5p/tPkg5seFv6Y8lT1LrDT02NlI4a3wXPJDlVIDJKzQX1i2PzW1kTh6sU/PQCXwy6ft
1y/SF7uJnyBNQWJ9YPopqxsivGLLE57K+lxhJwX2e69tl6Ylyj0lMSBmzHQ3QGYDCRNMS/uh/E8U
K9YDzc+ym4T+tCFH6jClLgaBa0in39Pv2Impc64PsPjJWKKGMuZ/HQT2sA21fHCTxEmlf40JQLaO
tvmEHgfWpiVbV4gt+AAWlU6zNI4hOLjK73/+Xz4rLmKZWr+7B6GvaLzfyoBm4UgLRCtmmWLBOQVW
naNzc9mU44CdFJdIHRt/vOr73EdqVNv8NyPjyo9dTPGfUtN5fTv4EdHQme4mB4ukbJMEHe5vDGrS
pj80BhT21ooOO+mxLp6wNeku7c28JJwGyC+PIQ+uqlHwjRLbFvy9gHuilBxvCNSxmsEQ4n+PWtk+
jc/dQ00F3lRn+WKMHUvjLXcMxpr710Aj9wPkDeDnPhn5puKSIURmUwJHN613L1LFTTnb46vvHVKP
Ru4itYBD7pUZA5NIgfcboTRlmxIkcnMKRtOmn6UPo9fAtlJl1Y79c4XII/Cxdl7sYdZpNd9tSJyE
JkspxrvAu4D4peEk8xblSHSBQMAa005ZMtEgfTXbiZhNUmQtni2XcnedgbUn8vsnmQhH3aWhLPrw
/ocojbyrXSKUrEltYUDW1w6evRoJuXo+IxkdY+OWr3ko5TRHeJ3oWZzzXIFLtvOeDGUirQho81Iq
LzpWPERpaTSep6ZSY0ZSI8GlqLH5lnWlaPmpJvZskV8zaykMGcadKKz4bF/BvtF1VKWqpzKPCZ8X
cZ29FNKt+n5dAK9xy1RfpLnHIdcHMV+/8jflqfw+PExXM9mQ9zh8HRp7f+lRC6IIHe5KY4OJ2VnY
REwrEQ0h04HIgagWEJa1rpGTg44FiJ6ydMvUAGTdJAW54zUlh72kxk7chcnSNVe7IixoqzDY2IVy
5sDyPakXpP6not3wO/6p8CaQO/iNJRlrCZtZYPq9pq3xsu2oOxt3jlBl8P9ieWnv3RVzkOGdXyZ1
aGAFxi1ZStUMWEQ/0hnxZP5uvNmQVYiJrVo87MrAXyN6hSLAiALqD7/7gWmSvH2epKijCe8tpXHZ
lz4rD8yawb0i7A1XPVdCeSXEsoY745e0mpA39jv1J+oKaJW3Xd+Vy1HRsW29fGw19G1BviRvTwHz
h9j5oHHMAz0g8GuTdqgpLe56XAWdsQkczdBM/MZVd3tT8FSjqlDNMSt5TdjIbL1CB8FKSAAvHDoN
8SCKDkf+3PsRZcZy1gExsZhe/b7wzA6ex1hHcPdlSfFgyiOPCdWnVPTKK37eOfaUeOHcQsBk12x0
829WJPkEsiRt8MNhk803E9KQUoOWhYKf909YoH/xSGPm7L11//aXbDnlTZ4uhexTV0rdBeNY+E97
SCRI0Mk/0+jKR48hRIm+G27YwmEoTnTEjTWndR6JXl58CrUzBAsd0fqO8NcD/P7seiZiQVK7Oukz
m+Nl20hMcBiVkld3Kj2oF+5JH+C8tWUWAxuoWWXY4rhCatxYTcX+xX1M6Cz3SS944FIMYw+llILE
UWyCtnftyaG+/m4pHVIv2UJ9SyKyutrE0ykaACPWc8Ok0ab3kN8tlDpn7xcJXCxCWUfQmus1IROg
nYe9QVyfMkqW77GJUGDDtPuDsBx1h8EJrwaLuIwGS3fvMvsvjfkXnfYMVurL/op07YkqpBNuGxXp
0MivwG4s8ykBMnxMtKZA6G90kgUOlXvw51NQhSnEeHaUssIsnNFb5ggu4Y++KoacKv+k7cfitjSc
0ayRN1In7/JZRMztWaaG2I/KDAXxiafOWP04OesIQylXjBujNsiEfYVYbQY0fq6FEI6YQbt6SbwP
ldl0rM0qUqTi+Ws2wVRSMwYXTIi/rqsagt1MLiL63ueCA+4H9d3/faKgjb+pAGVmf7L2CEVgHblU
etcqvLSKdKvlB+ZHXuW8t29Y/JSf0DvDl9YH5RZ/QlQIY13inkVPVm4SIxoq/rMRlg4c+y/62Ya8
N9gr4Ir+y0Mo42tNH6IXdBjisSVkHTnS59x28BNLObsDF/seGyWeEyKeBwNwoF8LKyYuc8TeraKX
oypV0RUkYtuRvNZWqTDINbibMEweAw861HK0fKZWflfoQ90NeprUlV05JG6yIwtQ4p2PX5rBWJ1s
sOY3llk/BOHjN9fP4l96C9gHwJ+xwYBS6oXIGiRzm0zm1VMaaGQLgFz+kc3cuoMwYi8Ao8D6UZ2z
WwrcKlDrOdAY8o1ydoSMljfITfDtcmofpLfSWXLfVR0Vtyj4H7Nw/bFTmyZRp4+ABtgzn0ZFktDz
NUSgWeAjpH02qU3ITiYkFQVIjV02ciUEItgsN6J7PpBnWYRww9WX+iOJIcc/5nvOY+7Osp+8972s
4it9flDYYhKTtz+YdUrB7XH11ptxjzoRgTUxEmQHQzJ/K0Y23gpJBK53fWYhcbesrXiDQ058UfEH
dIuG/OYFUS45jGwIFuow8Jcjg2i5L0MMJoqk2aBxEtszCbfkIFWOGLVjaF9xaduGTVi7Yr7JGJxz
COksTVkWoBlwB6WXR112ap506ZTUujCs+kvcc11PQ8Ea47Xr51tRflakapV49H1ca0uYQdyET33y
1NKPAZvxhDFY+Q1OQdurjQfSJiOihOQ0BFhOEW1Msijq4x/PKqnAZr57I0gUkuMDuAAsIDPmq44a
W79zb1Z43nQL8kqAZx49h/AY/DlyN6uVZrCtqTEnMw/zQ84/WZURInKw34AzaxqFyJ10tLqbnHVq
FYT6T3Fd02MV7NjLl+9gjLnYKNn3lyIOBhLXUnSxK2XELtb278f5HTBvLPyirMXOHIFBuO+QJUQg
cB/A70V35Vw4i+Pui+h/k7i5SPvZS4VPxozRfGSFNo9pSKf+Ha0BiX7h9WJVjVJ1lMRjTqwFpcOA
q3VrIaZVQI8cnUzaClEwC33BLcK1PY3IPRR9eSzvUlem2hC7AWgW7E7bQjE3fbl+sjk3zrMrJMcr
UVYk5DGzPdLrMNN4Jc42zmbQ0QEV/x8edEqAemZdQmM4t7e78PRWHZoPT5gjulpumFhkhgQp5kjn
xW7TEDUq7OMhljIpZnB46bOp3b6VwHjyU0JEWtWBFvbBbWHs5U8PNRDwODOB0AZtkI9mT6WRqWLZ
speKrQi8DcEFkHF2hzzfonei2senk4NT9kpp52ymBImdnZnbH11lP+RFZrCiDtx5lwFj/v49aIuf
U5Ft05lbXlR9sazBfMsYMX8qQj9eHxXPv2Vfj2srZn+7pgrt2FtIa6UUacDuxoah8slwcT619a7a
//K1zF1BEi1UEdr/bNyZNBFqZnT806OIPP5x17dRsdtRjHNFgqm3nBab3unK7fV3Km/ngTTU1BFV
SQXAOkL/CcWd4PxB6yXx3YvKX4UYYI0AWUOIoUM8bZ4Z//xguZnPeOFCkpJNLSBwfRj2Lenw6sLv
6eSi9Ospyd3yhblWxbBAhs69gYGVmlI0Q85F2uVxmRsTgoZrj63y6NDLhQQnFR8blS5ZUy+vPEfG
WpcJUyUMyMCLUbjbIcktr5OSkyeZDg62esbPic678pm5JmjAycxmSvJHhPNDUi42XTPaNIvouVWQ
aom3QVNdDyufE1I4Z1GtvWvJXNDC+xvalYYuvPyfhWY3idJsQYhutWKZB2fi+q/1bOWN7OopjdF8
J3gyLaonZ5HcCzof/Sajq7B829ltWsqdtiWPbTuLZkI7PHvPegaBiyY++1JJk3RiafoufqR6/hkn
nuegmGT8bq2+1u1OeQ/Qb6T24yZkIrXSHedgJ1fnl6Nl8/0Zd6QKKzKj4B+qukQbjouBoqB8aOMI
oQXQsB+vxQr4hAEJhGHFV8PtZI7AWI0A/tgDLdPz31u5+Dq8BUc6A4hucFzyBzCQlO1WHBkKFNdV
hKSvCILXFpVzfQ1JhjLjaYmLhkt7quyKwX53CqkGzWQBCuZYteH9rGP44jk2ZV+dZufunVvU6wre
X7Ok5Sy6FAD3cC3owIu662zlGoc/EPV5XfLBzM9yJTkv0U1L9C5xibiy7qvXMIkbctV9N7dkbM/5
Q6mQX/QoTVxLMshO7ZX2LOf2gg0Qfvkao3zIng/IwNEY75PdiYy3xXOJj/h4+qKOY+0dSTQ5NDt6
PBrc7xNVGx0qW55Z7uW1PZYqU/zSBsyKwBJ4Jw4xaCwzFdSyvtCJJyZSOROC01SN6rI1fwZw7KdO
0EhTbs0KfCB5VLu3QSJauT/jRbOdYG3QFNg7o1NvbHnMCL29TyYz9wON4XLzKpMwmFnl1To+PK5a
NbMqgFhn7WqncfHc7dsMoh8Gr5PV2GDOpTYuKZi0TCe7igVmQYWiHjE4W78IA5o6Eri78K8FZbsn
x9DwCHdQvs23NpG4r1YO254opeX0Uqqy6JCfG3NB/CjQ0xiXyfT47Uz5ehILt7ZhdmqwSIiz7Tss
MGzXxtxKJhSsMOilim4FspFyXQZulV9sNTehdAleeXusAr4lMmAh511Jo+oSPl97wycPLJxg9MdZ
tew1IAq444EEGj+a/mXSkayzsYTtrcCFNrWQeskeSyUojYLIbunbxiYraHfcHWjdYlL0efN4ENJk
8IT5mA3HzmICl3YYoLSNRSohuyXUUfGHam84dAB+df4iKJm1ILm5c/Zw52vixDWtA05mrZFhfQdI
kf4bgLP4YDhjKppCKAUdGKh7zHPRC844W9uBuNn/IE9ANY3JZDWOPhDdrZjlbeny4sBlNXMdw191
uJZfMb052ntwRlPpqSwFjwcVuNN2MwKOXcTi3u1VfbjxmZ066S2O32yD8lXrGDhLm6iAul2355JT
XFkgMVsNPIyUoK9fOXMpFjeJPaRNViTVplzK5OJdcpit3h4Gad4jobdTB1Rwmy9TbyKLpVsOMnnw
QJQq/957jexDeGN4JTY9uDhXhdOWr4ezAvt2uYvfWp64vhgduW0PxknXpNMwli7jTB2yK5esUcNs
WFmyIzkSbXyNkuafPs1Pv3ZKCiUHv8sxcm0bLTEpfxa0XVPFtH1KegFu2uoAL0CDaCs0m3mRg7wj
7BTI8r2qQIE5ESoAoIOMjEkdkamvn+ViI0ewLjXe8Xsl4WT7AhExW8gJzN9X0NAcBZBD8BLprsUw
0HIBpJG+IxV57psLUpmUC021uYlxgkpiI0TwfBQiHZqa/PQQ13MOs1B8Wp1DexWBhiBiJ4QeWpRt
C1zjYhdbHvfzhTqNQvWs/JeuzyTaSzvkq+AMp/Q8Ehrv34+pm0IlCJaoiJW6BBSC+6HvEvmDKZzX
CbrTwSt/o/J0fRNU9nG3TTrJcE1TBL9kh9LP/cLMhGe+9+py/Rs2NLN/c239ed7RGFVJfv4k1J76
tOrYC+HJy2IsDgj82KayCtMFbbpeWKUYNez79VmV6oFDIopWTi0YjETA1PjJ4v5/Y8gmtWFGa6HH
3d+1VO8grgwRCMzrHkAqV7N7xTfwDuFdYSq46uXvrKR9mLKdRH1V6NpcJXXtAdtPtLT4qM/XkuQb
caO3c9BsifgH8uthIqzZbqgvlpyJlCncA2yYKY8icQdn7h5rLeImyArU0yZDVJEROPK8Ww38b1cU
IMezAD9q/jsJcoK+Sa1lsLSwUMBpWNEghKel13AWWLT+J2Baapf5stqLw+AMF6jiUdb8/xnIbLSs
ZNO9tQU/Uyqlpuqgfb00+kUG53Z8vXNwGdbQ2QpOtnTb/FTXxHcQiR91bua9FDoQ9qhbdRXIFWgz
QJIXDCTEGjpLdFk6wtbTNjH2361B8fyW5m6vRhX54aUJTNRkW5ZaMqemKF6XOV/nhCikDU9WQIew
sYIVMbrGNVNASNyjdtf2yVZxyVyKkuh7DA2QpdTjjknDvajXevuv2wDzyyRVzYL5tvbz2cm6uoIU
2qrz+SJbJ7mWMDeuhfObIeCXY+iSkOEEAN9pPKYglzl5ZV5n+j61HRHZ8tA/M8NKbCO2yhrucXaY
L7CwklJdoNfNHvOSXKosWUzydmIub5PwnB8sbLN1omQmhVvKcZQ6zbc9Eq90H4NBQUWvWZhcTeP6
6WKG65MzEMzsC0tT7kklqs/KYcvZhyBsW0rDjqXVcBLTi1as03tYDfPu0SB11e1DcKa6Kofk37/Q
a259Qe90+u4z8oSYgRxSjPz94fCR1ZAtnTLYKWU5VVruqxkDYZDJaIQHUSEBT0kGtFeAHdiHHRoK
3GQGG6dXALfuu0JoaK7s2KliKBHOPZXDiZYS5giZy9hRETBhGLQRLuvkM+2sXRcQ+q1rermfPjNd
mddJdVQMlLav2OPtD1zZEC/HSUiQqSZcUiMSEcgFpNeF+UlP0of9TePnj7/VR9PWr1AFonh+l2X+
ldNBExt1bcqWSHuCtaOIoVAxUSqvCl8VVV9Vmw1O/5AfmGRXbdgzcnK4cBCUvi57nVJXtQku0gxV
3J5NiZ/rbza71Pjr9NeiLh6468gNNWqfCH103JkqTb9WiP4zj6SZwoqNm8aeCdgYCBWUBVaRlVnb
LJ4kGeu7VEVNC1FFuJH2FX6KjOA/sBKrV8DXtOBaJQ/biIwxwryHEmdJmprE2lv5huiDl/C4Izd/
x8BlCnN/tT07HA55WKcYg5dEgXHiLrp3O76hZgQeaWbSqTMhamFi72hAlreEmvHt7iAXPT431wwU
ISEwbyXk83tCJrXmfMUBeyoHh3fAlWYyj9asBdqp/73EM1KygRh/vGW+HKn6Z62DbgYLTAfD13W6
oCMEx5JtAqkmzsm+KV80huXXPIkfsg4An9gWLcXVkKFnsJZpqty9s8nQo0kA9BruVWs9syyK5YQh
9cQVlOaPEG7df3IqWM0Sx0kn4wWcsG3weDm90cMq1TvuOTA1Va3/1LvQqNhrNR+/jKqzjRQ7x8nM
RlU36fF1rTYGg2g0LxF3+ICtfM6XDVII/G7sHwQv2uESH+TSToEhauqIzDaeDNNN33g+SXisSpms
HAEMdebr1y+cciQPisMPvi7t7shEith9/dg79n9IKwZpfrfHPbib8ITQYQmK62LcvGC/b0FTlIr3
MKwXoL1lD/+gE8TBbaehHHWI3/ITmI++InZadAYzEjMNQn/YBjlf72DmU1b6rIXBv+zyxscmJrwJ
kGwsHSedNh0Wm9l5buaMrLcvtfx5DpwwmVqb0qIuJ5tj9n45e0mqWypjP6QKnOf84+BATVXmeA30
xVNQ6DD4xp+BqiIAMk18F7KnOt6WWzA1GiLKCNBsTkzD0B4iD57q780AakZdYbbDVCeKlodUG8LJ
+5qHo09LSqgA1kHj8e8mjqyPMJ8P/9C2S102Og7HgfczmQygXIasmH0LSaMIFa2Zt40VLfHOhCD9
RPOXl/m8QWTWy/3EBIRuttl89Ja7hF9wHXxwS6+9yeAITeDBVOLMIGJYp8HFLPphQbFH5Kunyl9u
JnvAAg4vw187iEBNiwuFKYo+D/Bvso5pLl6IS0lyqf1XrxlKoSSYXC/H7BnwA2dUHuwQsEg+QKC9
AQEwSZKLH+WJFUtkHt8eMMpktSMltLxMeoaqCmUVszSm4dlIcZ1fFLpaItmmW9McnbRl0BYO7yti
WRrW2+VV1V8bxsQn7Pk5ov9ZTR0bXf/t633iKnjWbsmg0Olts1PgfdXDPLxXKqJSdUBgh2hhJveL
61I4AT8br4KuTtjzFJb+HN+w/Nk5McsfezNwHrrgoqWawoRciTfd+tqaVWKh8vfOfkgt6jGdPnq8
J0cKyoat8Oat7bGYIsnEH4WQLHKMYHGnVXQ0BmW3lMZGvBPXYHe8XaCOLl74HC5RGTPn25K8ZRRl
ciUQdIehcBjtWYZCe06D7MOLdLm2F0yGdYijmCwgB8isAtQ1o4LAKU/V8jWHScf/cCqlmQr0bGPt
0cwWK1IE7zNCn+Q1aHbcPGLNXWSGwTHKE+hnvgIEhBSnMCh+rJFIOIAJ52RDRbAtWysIIX0+b6OF
r5p3UWhFXqC+YDqPMQARQ64gSd5MbLY+pZjJe7DyyNpv/gqWAV9hkX3ppcZ88YWg6fqbLsOXIhS5
2tpCdJNwxPBoAy3rkflxgzpf+73FPvpLIqLG6qnC7ZW3FfmWdpLwhNFNx2A/OLbCpZ5xTn5rPrm7
TOtb/yJoJN1nObTKHXtMO2sKCjGA5B6M4iRbVuJ/M0HBxynLZ9U4bAK+PYnPPH2e4I8LqGvdYMbG
7GzMm8uXTECwBjB0FLEnw17jpPGFBtDJWjvTC6JfTQpi6lNNQaedakh5Lmh+cM3DmfolP23IpFuF
qmx6jLN/Oklti8wSjMk4ggoboaCEwKnyby7jkH19ohG9r+7647qSnSMEAMrVp2FQ7D5W97MRIaFH
SjCQ2hLBUhOjDDfTUlJ/p0ErwczvXx35mDJZCPI+FeAH1zNhpDwT7cCYYi6VBqZBim8Y1/MAkLdO
MrhpdWlbTeWAumEfi2xzOIkXAtO1FTfoU60g7qoEky19drzNtvgJ6U3WIsw/eE5jRxIQfsnq0FT2
bQ6On2l3YE66BXdafRNEyOMiF8TZDbhUcig5bMJxkeaaE1x+X+Beyq1f8Z2WVVTSEhsMzxU0aHsK
KeQhBlmBWkstzFVByJ/URyZiFrHj94JZvUwwfT2wDY3oeQE6nQYq1IcftIwe/3qEfIg8ha3gAiy4
1agcXpyCWTnflES9Fk0xqwmoWIx4sPfq2vRvCZf1OQzrbr/7hYZuvMNH99b9KKKD4m/RtnQP/w4m
6a7aLz+qZkgCHPlVBM2wuVxivmJ0bLrnhZhRDCTqqOTf2mheyV7Z0XvWPWm5rq48bmgCowkymTrJ
+kPpcpMeUJwfIAeHKppcaQH98lto710v1+/yzLCiep0+w0vEsg++5wzzJZTdLjZatWjdG4lSA4W7
ilGrh6mvnczpT+T3EBDfkzIiVoH0kjryI4RusYYQz2ndjo4yIcMxjo+s4RRXwpjQnH9WRRjWazd2
K1ICGJTEmQnTOs9kfK24NdndZUZ978Qrzy8+gaoTFMJyP3x5q2eRRTWV26ml/de8wHLPatxa/3zL
YmF+DQG/lK/9vQ3oTE9zi1NqdnYvKQkUIpj1/M8u6jHReNpTLnfX2NcFuJdgf51QJ+EEuqW5Ljfg
ylDowkGaLLih1CHh6DKSACLdxcz3PRi/eEGX2FWAcNiPC0aPa30TEfq2wNfJjUMyR2bXgQ01xoQy
cX6HpnkaURWNFJEXeXRGLmLkodi10Iobgr4fBhusczsRQBcgDHRU4mIptV22YXh7bI2WthbH6I6n
FQ9pkaRKwwBzbYTaTn1oiXh+9FJEaYY+ni+1dejtYOcHoG7v5Xzn5l67oIfm/fmihSjZNsHjlGyn
znSundTnUCzcJWfagr/2gRRXVyfI6YOMoi7Mx3L0Cwesbar9NQ+SWlvQEMso3POgxm6wazrh/L3E
9YOUtgbNuG/KJ1b/O8sQCprchUtgjQcUmMIPjN7TEwN8KkQpnzxHnVwtXLzW040IkBPEP2PVHClu
GDv0j916w+FFVSYekYWa7g3ERYuOMeqF/kRfW/d218HbLmrZM2RJvewL98GeVD/alJtvELbpHUSN
OAcS1TsmQMbIXoDJkdcIUzLlFzkX8K9XI0MmMdktFP7mU29hrHmf3vYbxOTEP3Ri4+KQogvEE4d7
fo9xDp6LfXYJ4jsLg6fLI1xMT3PyOK2G7F4yN9FKK4myNsfP80qdf4sQLdFBZqZ4WwanCpGu089J
/86TLGP7hZlKPTvrwxfft8upfbR0UO3kwPb4NPEDF45T1CHFO0eL7RsiswwQmEBvVEbIbTlaELji
iAxsMP/Ot8pjMYEIrksPN59BTagjNJCOH2fplS8YMSuB0NGh6hFUrq3M6U+0YOrmsBsRcDcfokBk
3m87t8nFJLXR5WWMM1f38BHompZYclsiyC4vahSvBDoI/ix+zAcjPo5CnsPUcA0ArM5wojcOl216
+oCzg7Jz2cHtac+FIppvE7zuQZYlaT3aQM8whjcPHT9hx/d/1Csn+/JQcTkIOfPMo2S58KDfu+cP
PYhvnHkZ1qyGzwHnar5Q9jaT3VSuu3s66msx6MEEJsx6j0OSA3H37xCC6EKevl9/suV1E4d01UKy
rmo27AI9yNQVvFuSBK2U1bn3zSgcbqY61EuTeklY0e8TjmtoQ3jQuD3xhPoWNSrnxKk0r/ZWBkI1
pdgdBzUjjA0unbXJKtlARHxMR7AnCQ4JdJkrk+h/cimU6iH2bovq2m3VbDnpW9Li+bciOhNlce6C
T9U0yjDvg0govkLxnQpUYfkXU+ptlE1P5wZstzoiF0uNEzTYjlulhySbM2/ovtMlLENm+fxBR32P
DoqMqxbEU0T07kn7tflj/bbGveXJfPggWFXftn0+ZdpgCbCPH2Ho41MMHnZfE+pKC8lX+AHSZAsG
XR/1ypH1ccPofSmnUT2TgSazX6EeiAioSJ0RwLKu9tAGg9gvzUj5A1/x4PBfPAeJrqrw6ya1D1jj
+3GdtXItk9eqnqDhmPk/MVWns2gIIps6RRlPesSnwzsldkZ+p9A7Vl+4flzvC0AIhP7MYZlReqzY
VQ4vbZ3Xl8r9HK+/7hFgx6K3MHWYvRzkLnetmV/BJrtTKMsUgYdliij07JFLCbtlh8qLyNq4EOxm
HJAv8FV/Nts6aJKD5sjFdCAovoQ0I3XoUcs2+lRt3oy/7R2XAew2JxH14Wndw0Uq14b+hWMRoN/f
TzUbVnRf24gfqi2Ma684OU2ErWMeX9uIblx0eMqstCULNG61NzHqwuvyL5PdlPUZLwg/WSPQWItH
PvVdq0+PO0cbVV0ORB9bV1N1qnlJgfMhqdtevzv5MT6WUKTbvH67MnTlkzwP+8+j5UfbcYll9qnf
ZWwYtzmuf6Oy7gmMQLuHBjf7SPdOC/GxypFsXIb81wcEvPDtALtKI27xpZuIYr5YSmHxR5LWj2Tl
xckNZePGlCEoUWpFCl2wDvO5qOSx051MakfpFz0b3Xu4Bf6OiVGS5m6Mux05zRxq4rQgm0lWJQPV
7KaFY6XGvk6rJmjHBzit1noFtZTsqD110cv4t2o3AbebFH8A7VsxXG/SIOP2Lc2HYQz90Nq45gKN
Q7kQ7s/91CpFjfnnXWNHgu8R1mdiQLz6aXU+2HKo005zABr9rM/T6PJNBcKsFgbWiQVaqnVhcHLk
LxWfY3gWIXUcGWPE/JBRM5/F3JaYTprig2zTqCzo3GFsDgmhtYAgK+yC+YStkVLuvi3o1XuBbFy0
TVOQMmT1holVPO3ijbIFiUmIGb0XrU/C/q7DFuQsqf8kYV/0OpSuPTUfFeCid41Ktu1QsajHeQxd
KSxG254B5GFFkldj8CXnxjXQGYIMQqLpIqcBD6qKbQk1c0mO9WhfzMaI7n/ttCbApyrHoqFVyrje
m9ViVikr5JsXr6obcV5ado+vE0k1RhDTgSlHHfCzlyzMj5mnn+rgeZjxQlYGqvvuXGZ0w9HW6kSY
c5xr3aWOdPvmG3vZFmGMDg1kSZnRfCx+HIWqfQXFsPh5mfO4KWHGeyeI3zRoSIv6978Wse9DuMpT
E73SPeL15zpPmYfXs7j1o3fjuUMWNRM0w5+NFSpFmCZ/pG3G6k7do1ZH6pXt4uTzgNnPUS/JEcY1
w8YkhAMwFCwFlanS1tnsLABhUkTGc3r+9rbdPFHGxeh1iseRS9Y0X+n+/RB0KOKam0FpSrvLD1Rs
1HZSR0KJWZA8bhPEWb2V8OH+BC4iBHX+9y47QuisD8ZFhrTrrswNkcN2uSI421Tnv1s6SHwTVfLW
L8r3fDWGDWk6Wh8z5nf3GJd8BjrO5hxmKZNzaT4UF51hhGvmLbOkXeyGufx34TskzdkI5bmjIcaW
TuNFwAf0ap+xH+dIDmN8JIln44WpjRbiyp217w63m2HvvLrXuXtFcY/EN8/vtbRk04cdyfQ7JHBM
910CJtsTqqDp5cqEXdHuQNTT1g6zW+bnS8xOhgU6bpG0yPMrt2JkTV3bwULIdETBaSLP0gG2quBB
yVrCEHClRpJ7wti9xWX5x96okEY+5KFHVK9CuSt8jdOIP5zkipnKwHps3MLhOB2QSzFj8S333IfJ
Q1Y0tlHcqH/hJW19ebwmUNgg0ZYQkicgxEpBpAUNIlxPCiqX5CcHRWuvhrAoSGwcZLsDNPOdqvji
mS29k6CVUmEjxxor6+zT4LiGoflFrltcTbOUEKrmw+TBPdW+B6hzygEy6suk2hXYD86euxQA3/Ly
mXdM1m8PfjNcl62F44ZEsy34NtaS9wtIFEz9GJMiBgg2k4A8uDY2MDpGICvvnSQmSvsKquplpCpU
hEQQW6BqWc3Md2pNOqpi4cyD15EGb2LdEKevySlrApbosyvlOd3VgyOFlcWff/UM5DOVDfYFUwYc
J0jjVv22wmXf7T2iV2vB+yYXs0ZiDH3N9x3b8+pyhB4VncC2sh+t97IE31lt7PzjVOZR4LNt9sep
vQqNqvoiGd3l3kMEy8JJ6Cpl3cLQx1m2gPRn+x29TvmRL79yCPPRdsy1QWsmnaC0/UyaaRjGCZ0b
8fcfnu+QX0CORI2MGyIiPisPsosUDAsd1mFL32zZNO4iEeJa9pUjcqSjSl2Zj58iP1cWAswnE++q
11It3XNzZRMtDi2hvBGo55lRGB7iV8bnvhkvcsD/BKC7mz6+gZkTAZu+FUkoM6pUCnvvG8lN0hxN
POoimTgwkIh60P1LFpK3yImRFxnNrBRAlt6YL5V3elU3yyi3SKrT/QfqtHTSGnMa4ReoPyoEfzXs
wTAiCdcFS0+kOuT6uX6WHY9cRIxwdygOAJaVe9VOyH/k/E/DMStoHSP8jMDrPm8t7opWY1f3gm59
Q1HEcd04uDOD2OMfRz00J83xKX+uD31HgnY08az84/5ZHwpqAVR1oOM97C0HyLgccr0hdcWT8ezK
ld4WubIw8vHJPdKqWogZhvvbVGImCltnrQDcasZ6C4Bw1FuQhYbNsm1OlNgiLZQat5R2nSJ5c2SP
iddfRQCkm9hliCLeArM8ZdiCbvT2v+2TwJZyv0HSBags7yUfJLeOm1KfD53YuIOs+XpJbEC/tiuf
UPJPSNTQtf8t6tWU64r6KJnolhyc/FZ4SruuAqy22BGGo+0IhKj/g0R+HjzsQKkKT6fxixOn4CAw
drZzNit9T1u/OTFXZkrKMh4rNgxDY50EGWzk8VmREgkyaUdoD3Ezr0dTsPxEw+VVHp3kwt4WdL3K
q8E+UmYUxXRt85BXx7TNk+RGtx7otX72YVPKrpRBSmRNXzYngWD+nn9mhPJvDKuTX28UCHRXNRlk
b+5sg+/UKr9Z/qfrrFnRXTzva9zy/wKgWDtQIXbHlj9HW8vwrqhAckQQwBWnDoOYnKDHFkW3AZE2
d5wdUnhIMm3zjSyeItyDNCZHjHg6jp7x8hW26vA7M7aLwamcYBtH8xDJjDquE4u7zAKdsZdkVbil
L1aNlBzRh64KyqxV9mlOce6EPshBCAuaKYEfjvItwHD3S9oloXyyjtc587z/CHOD3nGLgNI7UuW1
7AOuyojEp8a0e8DuZEsVePYho/tC248moLYQpJnu54dWUABGlEFbe3uJXe5iZUsLiQofFZCEZR+Z
F4CVP1vtRzVfaQ9IRUhRDRKtH7zPlDroTHI8Y7os9Ie3mQ95INVuQbnSrY1zcShmDJXGAfzjhPlG
Vy9OXm+JwTgjDo0mxRE3s7rNLOGC0lNIpL5+5E3Co1cEld40rrQWdRR3/wsMC6Sjt5NYkcJCs5lu
xTDYpgGevb9mV0kwMObh8/DdiIZWwf34rytfxe1CtOCBqP8B7RZ9C4h0e9OZrjfgiqgE65dD344N
a0SphcY1hVPDsvUHvu+4JgtvvhmIgN59nx6LlrWXqjbIqZQdeVis1MjHjeO8qPtq8T7hIx3aR+R2
RXUwjAzxF+H+wOWfwT3wrKHdF9CbZ2qfcOR+N9X8XzAELJS45WO9l6fkH/+AFhGscsqkxwpiz2LB
i+UkwfSzDfMZVkVdypOWNkYVtf7N/POzXb9LZNqKqUSZCCn8HiSZ6gtx/TnkgiF2dygOImgQ34bO
V+qztVSqGrOamg4XpQnqqAd70qo0+5uQXIQTn3QoKV80/uA9zbCckNY7Jz1915GDAgjFGtsxuvMO
sOMHAOs8hUi3QVjzpaVC1yVSlJvTvPZUj6M7H6wpwsaqZaf29ZZdqE7jjh2QoK73PIfd9ROKj8Qd
2ZnhF0IYbIRblSE7ODDENvbPrCbf4bhS4RyiNvlY9h6UbOJA0Fm+8skyZK8xnyl07MoB4Pky+XOI
ndQDJmFbD/JLITsAC51D9KMckeOk0fYd++r3e8osec+t7kf9rZsOiVsxFHe9KfFA1Ydg2wMiqw2y
qNR+UqVyl8zSNk2B7RtQvw+WEzfOsxFmxJuhyXAokKhqmDwD9/PnERF28egBfjRCTKL7QQ6Jmq1C
JICi5gu+rwMgttdN8gH6rTPER9dI66qA9kK94KA3jYMOR5tiia8/dPysdV9dOypCQlH853DMwv3E
IfbDDW9MfXUj1tbfJI0GBEMeBAWyQFeGDs0Rtr8CP9m4xTsAMBugEau0hOjgGpaGVyI++aIj6vhW
/remCggzCCJL5IKjO3CXGBCwy8vdidEO4Urt7w8jliZOnqvFizFiY89iY2UyngxGIeW/UO0xVC/i
On+YMs82DDFSOZirq8uDLwb6IT+DtMAmLIgCt/LnYJzshP/ZtVW1qTOJxy/pvbG+69KKnGm23I8t
8yEHRLcW+OuAxYiIja1eMDAUV2uKHWXgqopxuQVDF57U98qAUuUt2GCo08oHqaf4V2ktKJKVvpJu
I6lT6y4BgzwhgvMrc/vU7PCE/4DzREhNBFyp/sENrcoayYGvZ1L15L3z+Qh0TOlj281Aybs7dwnd
IompbYxkZzKJaEn1vj8vjyeVoXH+uzmRtp0SkhwNWtR/USYm37mOVp45KVzFi13VMaptsve8Hqhg
iiwlCkrl3wz5veTPguwEmQQfYCK3HhwkqB3vRuIFLpJ6GExZhpr7/AFlh4VBxJL59E3R6YwHDCop
TUrIH+b3dhAn97liyoxJcfzMh+PA958+QPSB2WsPkP9kcSkErx73JflKdwJDR4mGoFFGfN0/5OlJ
a1svOmY3vKj90hJePtImXQci2AuC1m/hhV3FsL+doM7ugvrEYGojVlC5dwa/aMSxnzeoPmwjY/Yr
nSQ47XTthUkM67e27p4+/29X2E7tUXMF3aNJcP21IsukLeImOOr7QAvqhWgNSfAk8d0xOxUf0ZVr
0hKnCofHBxugS8ESpLH6vplnMsaL8pSaAOwvWYD6HBcsRRtXCqFxqpx6xxN6plow3PSGYiDokI5R
+15APrOU4L24bI/xwy6/fK4YYJJHKEnR9KBYa53vBmegcecSDjoDhM+Wg9qTzndduDep/zB3kxFX
vtTbro7m6qozpuRg4NV73vNHs78izF1oYn47VnzNNg1C4fdDt5jVvjn1ruDVVn3gvA2hnPCg+1Kx
sHn83DItmeWxyixmEm8pMW/EC8korZ66Q0emrt+9U2SXaAyZ1MKnSjeP63asBEsTH9GzIYnVJ6m0
GkD4khuJv6gebUt89Aiir6u3eIpTVS3myUaqZ2lyGxH9K+kSfv+Cu3jKrozPydwoldSEIryVbHx8
6cWXy2FixayN3nHnHOvkFxeovvXWAdYQ8W00Ip6OmXZpyoql7aUyWTvK6pBrh+JH8mF3VCn5RiaD
+p0w+CPakNFh680pyuOE82MhK9n6oW87fAqVTZI63JbAHF2V9+tqY9im3QeKZdfQkCuDHxRM8ZH3
3Zj1N/v/8d+Zrgwun5In4wEadO2wcvocJvAe2Oi8KX+VfhUmJXitWicdCQvcXbV9iuhcFRRvbAjY
WcN9NmMovlQSdHaIp1E56+ZZrpqePiDWlv7MUxdr6fRgqzWQr2XXJLld/QxERueVHprnS766o2iW
oyZ0eRho/COpb0WE3m4ToRz/0ejezjFwg8iwdaHG65dAXcL5I1H9BeepufQo4X5qUhNv6dbW7W/h
TrRvwn1qkGmBJM5mdPJdh8W435XNBicfjGF5qU350NhCqEn+QBsD4+5xxFGSuK5mviH3QcIicYqD
q5mZro/TR1PvR0MIp3kfnO+iYGwdq46eELNLuBeL5XHfbzuqpqaPWsVzDdUBXEpKq19PIek46clF
XCXNzQznufseCmDHYITTMQLPt4sqViaQHxqlfc64k48CKRswSotdkmE20rBZVgf+zMWy/bV0Geda
QA4JQPJXJ27UHOvgFOhsRHx5XZ79Q3tGuUa+ZxwEIS62Tx4YCTjPxQYYpPmutJor8mXHh24yj3Hu
oxLP4YXBLDdmAHFvpwu1L0WFuOY5qmTKHEykUf+548OYV5Qv8q52pi+f7yCkSAvlGcgvMdU3OsJD
L4d5mWAS1lC4WCDloqrh0gUw7H+qB+lZNNFT15lYEEhNTka8zqg+VPEmx9Eg19bTG8P06NM4G7JK
VeKrRe2jBEuexPM3o9patXF/HvFEOiALz4o31jbL1yUaUVSS3CKx/TSIZM8jJzCINmVMCnnfLgC5
L08bkgrMoX0mmEfh1JdY+/gRCnDWtuEE2Ap/AFBSLUL1Fni5LZsMpkLrYvSui9+8PT/RNdNrADlS
p7fXJoekKSHTqf3nENyZuMbPG2L48zlqUWKy6AY69tOcYg+USB2cHED9tPVIf6aaxGZ9mNaj7cbM
1OTzxo5/QQExquFX2CI0jtuN4rGtWZo0P+YXPwF1iZIs3P2NhbQ8a4ei8FtxtmOSV9UbQZOoEL2I
pt5RHHB+SH/1Uczx4LgkOKrpHiRb8o4gaRLfktEqbDnKRLZaYcY6toPwNbwSZ2HVVMknAPK4nWiQ
r2AC5uTZ7mubWDmaJ6xhOA9+NU7bF6eNwy5TKQKIoL1fnUD/os5gMiW8sxF69MSIJwqSQQHyRRAr
mZV8HdYkp5r5zhyYDnlm9m1ORK3yI/GqSIZUd6FAnoCf1RB+hYaouHY3SyUjbubDgdy1vBJYhkOj
t+ATMT/JvSgOlFryWpePHqkPFaiyRtsW768s8Yb9x13P/lwMO2bDhMh6TLR+aSF8yQ9aNTLP57H1
+kNzAwc9IjPcS1TmQnuSLTVXT78D0BktUbL6vz+YI4gfECXFaxUvJRRXGXv5QJMwKkJ7n4+chOQb
c1yzsjsA0Q04R1dkaib4VnqDweVJbpzjkKjxrg9QGtEcXu+zc4ADVpBZyW9X8HNVLkRsJVzehf99
fVjLQc++/ltLk7MN2xy2Ngc/mBBuQNPCczIeN1B1GzwyWqChpcTMDM3nEBV4Qk/6oMp1//BjBswX
UR73fyA9lURqIHggVDr1kmFp0LUCwo1NkIdet7xA9iux3NVtJK/dG9SLVO/ZZ+1rQ403p6pVIila
4UaB6LjJajwFOosjbApdqU+DheP94IahOoOFabm2ASxW8kqeWm9JWw0AnWAGeXmRfGVktZWgMU94
LBiHwO5tkd9TR4Mrh8zjgBdiLXclYvFfYsqxcXAbyXupJ1PErlZ5uO4/z1NmHEOBdjnE7gqVGf9e
jwTpZxx9v2JvFy58sXLUDxCV/0K0CsQ7J0DrLZl6qJCqcG62i7tgJG5JRIBf7aTL/vg+IzKjTaZL
kTTe+zvRmOEyw9rc4AyEksn6PybWQ2PrbtD2IoQrJYTMMGwdk1svr8xFajwNLRS3X8tHpgUasgCF
6yZTKpDHSq4up5CabRCbv/NMcHOpFS+9emkzIG0qaed+mWtgsPPiuKHrezMXWi0SkrrjMIF+tn9t
EC36ydlGVNcuV/P1v44yuEgUCIeXvLg4sv5pSZWwQXw1K+kOLpb+B1pDgRbzX/lbcL3OhnEnot0V
erVL3uf3bxDsRlBgOrqDi9WPUQ5AfoLuB39A1L50S6fQ9WmOAjtfolNTQCWyNEWPm0Mli7bqlcwL
7oRYelAI6MkCZFd0v8+Ii8pcmduhu7Xjq+Z+MdedCql8fqF8hZABEVmZqgn4TGmZP/VuhRITIZez
N7QCvsVZL0d5wZWMwOSSD+oVPIOeEfPlR713pyeQ0QUgeABYbl1YUn4s5prowmKcv6xWX4u2Zb67
XT6ulEGrCEjk3ZvJPVx98RVfnsQqbagMU5VMDuzk1id2ZMcGeEj5gGKJyTDlru/rXFpMMk+hwLim
OjGm5aqr06sMdnQ4gxKLUsd9E8k6vgbKf297LntvQcoFnqnRD7azv+jqLVNd3mxptAgYfEkE2uUY
2s+i9BMI6saES09tyNxedNmDHP6wKs8Lir7nU2Z4H6BgE510gM+HY6W86QS39wJ8e5BcMF+mgSeN
nvt/cQNM/2xcYBshXm4gh/sIdHInI8rcsRs28Paljh/beclolASvblCpEtHtGwRQhjthMVOpHPU4
7qxKwiTE50wMj+8044AFg/F9ppleTSfvVde51yH3Ehf2NBbi2D+eiVRlTX9SPPCPghDQ29cBB5Mb
1y6SEMqmhgA2B2Ne9aH7/ySh1QgZvcDVTXRwr0nxOaom/QeO8on153tsUACOJkz2g6vPBG4/DP/A
dofanl4gFYMGsK2a2GMfTPH3jXnvWHJPzsG3G53O1tVZLrbKL9yn5hTrGo+c52/7u1mxDmRVgI4+
6Pj0bN5YCUKwGAJ5Vh8a214LyEXe/0HtVUA4FDG+iF3RLUULRxlCXWx5yrGFjHa+RKGO6Cs2Epg+
Hz8P1qA9wnpwAF0Q3pV5b991DFnj8CbNFDxuYOXZDgJ8lMFbb2Skz+snq6BAGJpJfEdUHx3CBII+
QcQlCpqdgpnXqC3f+qxBEiemJUIzv31Ha2dRGZJ2fCrmyIlMvvql/1nyxzRelNm4eU+/i2z4BxHW
9LdnMZBMfbctKugyuLevDpYCcPebRO+qYmfVg0quqy1gjrTXvSBV/ZEFYWQ7iFqy4qEoeifTK+/X
wrUCQtlEsm5Si4LG2FitWPkEshmSLJdUosNeJbWhVjb6YW61MNvDlxsjGMiHzVPu5f29E79mC7aE
nJ7n4RCmGgUwX1vgIfmcys56rVLtrE8SNDzL4n5ji2CUpAKhsEgPF4Je9wjlxazl8GnchDT3y/Cz
ESkVJyK9THRgcjCISZodyxpaBoHXN8y6diLfncKeYycXEFhDDdwtgcEhCf6hhuuKBNDjd8Qw2zRp
vcHxDS7LfAP5eqHrgdbwuojGKnQkhOJ1u3iAYSLXzJvFw9UbCWrT0QXsuLx8lzG8kq/xs1vJ1y6k
00uKjmgQkYaP4WeOQasy37fMbIchsBKW1VNCdsLR48P7B0bUO6f8PRzDSKTw/xGWp2JrchHHAAEc
wfpSYCvL7lEUznNF60bI9sMb6AXFogjtQZVVc0HewqV0tKq0qNYsWXnN8EEbNxhTH9XY+4f/4wX+
ILMcMpE20RI6iS6fcRVhc36IIlZA0Uv8a8Z3A5M5fXNR6NFIcRjD089IcG1KW5YxaJbGH2GqwXQ6
3hehcD4B91BZpAVGh0BUSBbeilH4JoeV9LkWij94dzYpSqi/QVOjIVDCverrO0AoWej/HDuXG1zJ
HOWEzuzaxt1mFaJ4LsB1lm8DRTEWnWxcR5FWy1b/ZSOj8v55y0aP1tHGJj53Ue3OnrZzbap0Etk3
6FjEKr/kd4Xz8ch6IAXyl020g+l6qzi3gY/gGVnTuX5h20cKN4F0KbIvK1rfTT9C6zOQItf786+P
0wFWOFPZkQ6DiibttU4jITaI2KcrQ+KvQb3FzokPB9/8rQRfeXQ4y2roZuM9rxzj9SPRZH9aVuly
7EplO3+BnFz7+sdKjzfmpcsPaO0ZfFIksywV40118abh1vkRR0ICYt2tHaspqPTYp66witblBJoL
rMCTr7JmJtjzWv7O5uK85PKbdlSV5PLO1SpNS4XScMQWq3ad+dAa4pL/V2mI+sN/jYPBZdwoJZv3
AbUadk3+NC771mtWEjHF/eqkH6n7FtJxjGSwTbVrUV8QzTNk4rlIim5GLBz0xwOWRyf65+3u5zTF
/8EI5+kDWrFWUXLZwAoWtzsBok977BtT15p40Y/lpZmy+c7W++ru1+LLy8N/72krEbNgGK3FVawd
cMQ3xz/OfIOa72WjXgqWa2uvGdQKPO3uSrp8FR3ZFKKFMkEyCzwShPN7x6e6ZMIfK8c2wUlAxZnb
mpX5l0QuzBnKZ/WMl6D2WwxaUG9dwbvaUV0dekv4Tk96O2ssqe08QHuoFGiJv1t98tKmbBDeMBeM
96AHYtYAxUIc15aEfv+kLW/asmqUF2UBbCMVmTSY5ZqVDX/nnHkJGeqkqSaMbNYxSPoJpvie/8QO
xc1Mk6zKrhY0j+SIrfLT69W/4vCfd+MZqhn6lQmzhUHhme7rXASt8FtG1L515/SjXuLpuUGXtRLT
gWsBWlGfPpKLOiq0b7B1cXRxNdSZYSDVygxXSTBQGv/NDs3m8nQwBlktLXfmd+hqPK0AgCejvE1c
dBqE3VUkKfbdJ1adcbrXrfXYpt3Hxm9tWe9FE8ODowybIEq4SBoyWnncfxpd2thEPZs2Sw8dVU/B
Fu2ZDkQ8sP70quTkZUTnrdyrArnBSg70QHo/eOYKfeJCD5KGTVzsZRFa4b6hKaqyeyPBv3/2KaK+
VBYSgH+Jzve5wrigt5clYnb0KjfezMzD87PXOmSK2wnjO4kmkRZtqR+qHOUrUuBQLeqm1o9jS8PZ
odpn3wIOqZEiwHSQXNjUyv5slpMH3wPOrVtswMmEzkEqXHH3kTf4gpVRM1s1LstElQHlYRFteOxv
PYuHRNIsB8fGh717sRkmc7CM7f3GOJQlzlFOKNmNVaFwD2yxBF0+j8shsOZPAYROzyUq7QZMXGiY
tRRJBAr3yhh8pd0eCZr/G62drU49ViXW2APHtMHEr8MHjGycFUEZZWeNfGM8sV8FRURDs5s+O9mj
S+nRlpxHANa6vjauz5s0w4+jq6cD6/YNtw5kC81DTxPhvTzGvQcwZqBnflTVi9HZ/ALuWzMEMkgK
UF+HhyY5+CNO/3k5FEgDwjN6X10rb9q8VhLUjmx2AghgBVJm9UM6w5rYntKrCG0aaoiIDcxvyIQb
2+eqMXHZnaEy2bD/Yi+AVd+wONmmrFjhgSps/swRfiUma0NaBy1dkUB4iHL0qAX/clu4t+UQyudI
CqmgDoOj4nU46/AeuDM64NHb7F0QJ8nttD22riLBTZVygt+HspqTDxoGrouMKyRqk2uz7HGDl4eC
MhDkRh2HO9R7qnzHH3e6O8cME/JureTbZ9vxQEJ4AVLhK5uqYNrM8tCiQ2Sy1WQfRWeHYRU+j8hi
RO9m1Yqn4QVaEq8On4M7p5Y5S+Z9bTtj7WvpD8FmvYgSRGEKpNIs2V9HWGfZz8xUD4/nS0Z98BsD
8IQK4I97fKFXD4/FkBZ4AK3ir4tIqeph0bsERNiEGU5EH6ekh1HnySV8QbxIBdCKFtWtN5t+/rPJ
oWSxlmUMt5TjHiqCbdFLp/FfjXtX1/jZ3aprP2lwlCzq3rvDDa2wrdHjA9bqqtoxZ2dkmbEzL6gg
jEzogJ/EnDmLbUaHnxH8xFukpJVepbqT9NS92XCrLH9EdVbzdtCqZE1boyiaOXSIFWi8jQZAeUMs
uyZDHhJAw1SktPnZg/30R6ErHmbpo4JggD4RsC0qJXFNUJf8cVs7sCo1Z1sBzpICF7J54ekQkgaj
wuIX9Bnl9258vxOtZtU6MvSBBwu9rwCgkprt2M40hG2D+Yt6LjEJm8jVOvigB9nB2NzfMpBV/xjx
eRmxNZzxr9kx4yHmYbPA4zJj0g7SiGLP0z2oWN1Ih+NbCyw46knHwjmRnzCs0g/bcLg612eaIgFl
1hPDvvznPE6e/DpwkzWOtuQo2njeiQ4G3iG1Ny3zBCZr6hitK9j2Qcnfgh7IBKKUUsv5ZlrSH2zH
tW2GxliSGAZ7k7PmtfJ4izfVLNYh5e8fJc0kHivPtsBGtJCWwSOAuUM4FiAVYaHmI6FKZmXBr8/C
TkInd8Vwby6dN1qJsGB5S+QduT2aoJNQMIuFHKZuowLiKEbZcSXT51RSahmYkn0BXswR6dfSHbXt
iBF+qQRd+JwIAD0zcDOySN4fDONDDqLTOpRoYkWi37KpwWzG6B1DeD6pw9rr4QUeHHXKzlRz6T+d
vZxSfqC4UWFHPChNDrrg5y/a5mxvfgwD8tRw+4pSk4K6rotgDYyP9M7C96Hczxu3Kpvp75RZph9Q
iSqz0FfXXTZPwBvpQTf5iQRoRthoVhDXMBgwoGVBve7s0iHYYXkCQzdc7QK2lmS4T5q8TXEi2eWR
kyBCIe49HhIFCMdoa9yld88xqC8yZ1N6mPLhLyxnY8yyAG6bpoSz+MuPv1X8f+KntEgWv8ijA3Rs
AJPpQ7SCyJmkgOFspSRbtHRG/ZCE+34vGHiDxeJo6J8c0Et9sPucZ/a476pTjorPU7jNlYIMK1dw
NMGdefGHJAEZuf918ui0NMFglzIoV5SErPMd5SRSl472pZ2Vw/Dm+USm9+1g+zNgomJhSN8J8agB
zwyy8quWv2IX/9xToXyP9d/E4MzgOtu7YPFWVm1aY92bRPy/c05MLPKPo0iAMovqyu90r/PkaOs7
FNsbTdbkXGrP/xRjhxQNoIDnyuYZxrFr4MyMmvCtiQJXcz0sP2djDKnfKxmy5pqnzsxQkq4dCLkD
wxJdPNITg/lcVgpzS3S1bIL3P5tNxIu3MlJNUOleBvbd6NbBvpd7ShwUzjpcZKsDeb1BfmDgbjcs
uQoLrEka7bAooblkvhr9J/dz7ONrNT758zZQ2edzivsC3H2Zd2XQ8AtNZNCGSbX78JKVym8RyF2c
w3CSADYR0mq4Dbv504aGcWhoBTxPBzm3hLAZMyAygP3I705mb1JvbGyhJa+Gja4htuUGsC9yf8eX
7v6N7/9SFD2nB5f+oZIw0fTNwjj4XXs9z/Tz/xNIwjyj7fDGHSLHsRPqtIedjDB95dGjSlxHjqsz
uYro1UmyKoEyOj47mC8I9HUaTpO7C+DNriAv7dzThJhpyJAZ9wijhTP71kiCdwvwlV93x2atytBe
19NKY+1J6o9Wc+OjixPc7rVLx/ayWm3j9u41ScXuimxBAeBGF5WLqBv2ogrf03PcvHBI6ZyPBRvm
D8TNhGujH0pwHKGbOKIGBzyGWtKv3lml01XNFLxxK10cCXZpSYimyGqZz7T2jvESTmo1+khJy+lG
u9W+d/XqnhxY7TgijN3HU7bddf3EK9rDTJ9w8tNQF2bEOt1+kbflSg7wipw3SNpXDo2V8luDPJIM
gnFVCgSCfRh/YTTU+SWbYdQqYe5jgXEwWFahi7F2rezd9CDgrnhRGJR0Exmw3/yv6LLnQlAIWht/
V5JuWNWttysPB49ngEOwpccvf/YXVfNQdwPYwyZa0JxIKLwYpJVCT4ZpRQ1T+qCWQj1Vu66/r8W3
QLRg52XqENu9ZMSnvOmDziafsjEDhNjMrOVwoySwYd9pLzeya/jrK5c/dco90MASfHinFWpIyEmi
sXa29qemzfhBSQXLvXWED9DpKgi6ZU35GC6tUvrfyEeztgH3sDoshNSCt/W1h+32LDJcjR0OVf36
bv8fSErvFIvcSm+KvUt1YsIM9PyrI3j3sgHTS0+NdMmOz4FMNfpzG6j+lnn+366GRJvj17iVU1wA
KTEDt6bit1xk3ZLrUa7bakz2DPqWkxjOVjL4w0f4rzNt9tjZx9WZp0E1jWpSZvrVLmI8rwRdmGy/
uGjt01aai6blFB4XcU+GxpKlSpCWrBErYCud/UoTApz5O/Nhmc/U6eJ02iyPlENVHQpaEvsVymrV
77YT57NE1DSdV/H5Dyl6hYJczwZLngAvKxlfnihnPR7SeZW5SROt7Z9emAB6rjdRoCgErA40v1/2
XKzKaD4fefIrEnmIXrewHJDiOK/5Vazn+KSUCOkoRDk/aGtuFBmZUrKwfgKafLQtT9CMMd/ylUjT
YLmMUQoKA03BOTZLPWFVgjxsXRhybtv8qs1pB2fRegR2cptOWUjNLhwRzpR588psBDxFMclUZ0qp
z74UE9ROPlEOFHHJ2uqh5MtNbBGHhjyEQ19wPOeauq7WPoA9BVPr4/CykYcg/Cc6/hzI9PTBuW90
jM7azxU37xGT3g7HMENPFJvS7E3M3Bm5Eht7y6gm0Sk9uuEs1wNV1ifkCvtYry2vkuFg4f8toe/v
E7pMwy4vAb9YmzsEJMhuxgghC64pXTWiZZBUVYyE3zMk1V0Qzbfnl9dtsZZQrZlCwK6IN2Vaflnu
jV+hOebUMrKTP6jkKIxISbTspi6SHDOQrZN6eJEyVdEgvTG9IQ81FIGumPF+d/1X4+i9OknVG23q
GDYGLGls9lalhZ6GjzTJyRp+rCijmd63VLofUeDhVcUkeBPUrSl4H+2AZ6+KracEhwLbzCaCU5sy
3RFaVz48lwnMpode7p5nsrEStIB/aWf9iZapBQ6qxTpRxlMFh1xjZVHy19lMYXBuyKCtViPcAVoN
0EomOpPNcSTHZiSrwYyBsittFXYK1wKg/Iz9HBc7+mnkX06pyGtr9O2IRm11X8isfZJZ4NpiJl8U
wIryujxsKhTUWAR4ldTVYsY+ifHg8/xmf754K7VCwhoXyyMhM/ocuJHdIMUs51eMOkcqLOOsBS2k
1yqlN7e9CUrEaPKoGMCxGdg4u30hx5jt/9fWWnDCFb0uTubVUn3cGjLykq2ZZOkMIrdDj6R3muEe
zy457dqkPYDWQ9HscNi4d1/XTiHlC14IDFDArXpYYAMljHLadsTSBvEbDzbg1MEo8HMJFBmzMNX8
qnjeQOwyYFtYa/qtB7dV18/V1HD50dm28MIQbnf1125X1n8wTBcdZcf4C7cPYn6yiT3ZB+GaXias
e4s3nb09mYyXz5Xa7RvLrg+XgnjpvrIqJ875CdZCQSe/7GEvBDKorcb0JmGy35o6o+zakWc5nYV1
hheRFRDI7UmLXtsKrj5KcLXXywjvXsVcDiieAB2TfgRtrObT1U4yjtmjZROZNAHvNmaiphQ9LMUx
+FZuJIi1f/fddV0VS9aqJdaJqvbxfyL0k3Mk1Sb/FcDzEGr+uPB/HGm7JwPhem8xJafvXZ4SHowW
UY6uZcn5Hq0I+qixMm3iE7GXo1KEMXarwaEHonNAHRw3tGTB9AXZ/y4tIhiDikzALmt6OJnOEwEI
wrLY4TeEGFZsddQ+CB1yqyBRfaCHQLMchZ2KH7BYH94NROwQ5Y/eBWopGlhdBILwCOmbIPGPmCp9
j6H9WeEhg1My21qg0mS7yUoR6jqrzXdWSdAzNypG5cQl4wcr2zld868LXKj1g/ZKAuFiWVOGepam
iHu8OFxXX3BLi7qSVdbKruEBNxtwZ77VZw4v+iKiO2vnu8QB8Ft3ROTTY+soVVckzlCiYRRaXROt
7LfDfofv2tdCVz8V1MwWS0aAcUEt+M2TWes99hm7nbDlQx5MPNMOBQ5FPKC+iYg1KjT2NO6tjXXU
LkqEPolrbSJFJVdv+xVaUZ7hCu0q6uQygXeKYuNy9eak5f3PiCndHYl11gXKYkw7Axm3vvvMrUJQ
qEqPXHhv9SB3CXwGfTe7/9buqjbpSa1MpNIjPWca6+wCHv1Ib38mTLaEDpUyPlH2B+QzE1/b8NvL
Tg6+vX0PBj0ORzOQVsfCeznTdb+8ZFXBOQ6d+ZxopyoUJIf6tRpBs+uObyt9QyUMvTycuobzNa4p
PUFQaf+RADGWryL+4yX0bMzrf2NQUpQSIcBkBxi2I9B8bkPYcs1s3cIh3OCgKbE8KhsfcdrTZfcd
ThVUQ/QOqlr5ANS/0MZKGduIP4of9zqDSI+XzmFYAZAfwSmWWH+H6kQ+iZeC46TiSxgGGvHWLWGp
az2/bhhbkxrJJj3mT5xfcCUStjLPuRQbvZ9xrXOVwegabts6iEBYsHEUtPKFR/nq/uQxkS/OaAkB
BpR35Kh8QKs0jCaeesUeUxOA8B5jRgFpGMu1t+vCzK7jPBub71KWlIou2Zlh11dxbMUkxZag2Egs
nP/x6K99mVxwpg0MH1NSzX1aKOeDK0oM7cZVdL0HBpaoknUJIZV4j/mu+pzm58UNH1ra8owbkc1e
UgN9LH5Sc+mJ1J49DC7rXQYuEtqSeb36DePewk9U9h2Di3FYOzpGRAdULrrLKAoJJrEYw3xvqFMo
7G+mysnjZNocIw/O15/uDz/K0WIPwme46kGKgSm3GO6NMJbdOxYcdoxQSudGow9whNonRLFsWjsS
lfoKu43MnLOtINvsTyEw+LWO4D6G6EZtJFrsJoJbuejSyK9eBjocG8kp+08/0Ks85Xzm7u3VwhRI
ykvBLWq5lXdXYzBjFl4wHRGVTnM+xABCm5txRSLPEQYpnk55GRaKDQuddw0npy1GLcHTJF9crrbL
nx0tWQ4HWHED2eMPaWGYexKavCDQGVXBNT6Ogmko9AOado2qKIebpCBBPlq1P/IGWnk=
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/wr_status_flags_ss.vhd | 19 | 23791 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/or_muxcy_f.vhd | 15 | 12722 | -------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy_f.vhd
--
-- Description:
-- (Note: It is recommended to use this module sparingly.
-- XST synthesis inferral of reduction-OR functionality
-- has progressed to where a carry-chain implementation
-- will be selected if it has advantages. At the same
-- time, if a rigid carry chain structure is not imposed,
-- XST has more degrees of freedom for optimization.
--
-- This module can be used to get an inferred implementation
-- by specifying C_FAMILY = "nofamily", which is the default
-- value of this Generic. It is equally possible to use
-- a reduction-or function (see or_reduce, below, for an
-- example) instead of this module.
--
-- If however the designer wants without compromise
-- a structural carry-chain implementation, then this
-- module can be used with C_FAMILY set to the target
-- Xilinx FPGA family.
--
-- End of Note.
-- )
--
--
-- Or_out <= or_reduce(In_bus)
--
-- i.e., OR together the bits in In_bus and assign to Or_out.
--
-- The implementation uses a single LUT if possible.
-- Otherwise, if C_FAMILY supports the carry chain concept,
-- it uses a minimal number of LUTs on a carry chain.
-- The native LUT size of C_FAMILY is taken into account.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 07/06/06 -- First version - derived from or_with_enable_f
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity or_muxcy_f is
generic (
C_NUM_BITS : integer;
C_FAMILY : string := "nofamily"
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-- Makes visible the function 'supported' and related types,
-- including enumeration literals for the unisim primitives (e.g.
-- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.).
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture implementation of or_muxcy_f is
----------------------------------------------------------------------------
-- Here is determined the largest LUT width supported by the target family.
-- If no LUT is supported, the width is set to a very large number, which,
-- as things are structured, will cause an inferred implementation
-- to be used.
----------------------------------------------------------------------------
constant lut_size : integer
:= native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => integer'high);
----------------------------------------------------------------------------
-- Here is determined which structural or inferred implementation to use.
----------------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and
In_bus'length > lut_size;
-- Structural implementation not needed if the number
-- bits to be ORed will fit into a single LUT.
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
----------------------------------------------------------------------------
-- Reduction OR function.
----------------------------------------------------------------------------
function or_reduce (v : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in v'range loop
r := r or v(i);
end loop;
return r;
end;
----------------------------------------------------------------------------
-- Min function.
----------------------------------------------------------------------------
function min (a, b: natural) return natural is
begin
if (a>b) then return b; else return a; end if;
end;
----------------------------------------------------------------------------
-- Signal to recast In_bus into a local array whose index bounds and
-- direction are known.
----------------------------------------------------------------------------
signal OB : std_logic_vector(0 to In_bus'length-1);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
OB <= In_bus;
----------------------------------------------------------------------------
-- Inferred implementation.
----------------------------------------------------------------------------
INFERRED_GEN : if USE_INFERRED generate
begin
Or_out <= or_reduce(OB);
end generate INFERRED_GEN;
----------------------------------------------------------------------------
-- Structural implementation.
----------------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size);
signal cy : std_logic_vector(0 to NUM_LUTS);
begin
--
cy(0) <= '0';
--
GEN : for i in 0 to NUM_LUTS-1 generate
signal lut : std_logic;
begin
lut <= not or_reduce(OB(i*lut_size to
min((i+1)*lut_size-1, OB'right))); -- The min
-- function catches the case where one LUT
-- is partial (i.e., not all inputs are used).
--
I_MUXCY : component MUXCY
port map (O =>cy(NUM_LUTS - i),
CI=>cy(NUM_LUTS - 1 - i),
DI=>'1',
S =>lut);
-- Note on cy handling: As done here, the partial LUT, if any,
-- is placed at the start of the cy chain.
end generate;
--
Or_out <= cy(NUM_LUTS);
--
end generate STRUCTURAL_A_GEN;
end implementation;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/or_muxcy_f.vhd | 15 | 12722 | -------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy_f.vhd
--
-- Description:
-- (Note: It is recommended to use this module sparingly.
-- XST synthesis inferral of reduction-OR functionality
-- has progressed to where a carry-chain implementation
-- will be selected if it has advantages. At the same
-- time, if a rigid carry chain structure is not imposed,
-- XST has more degrees of freedom for optimization.
--
-- This module can be used to get an inferred implementation
-- by specifying C_FAMILY = "nofamily", which is the default
-- value of this Generic. It is equally possible to use
-- a reduction-or function (see or_reduce, below, for an
-- example) instead of this module.
--
-- If however the designer wants without compromise
-- a structural carry-chain implementation, then this
-- module can be used with C_FAMILY set to the target
-- Xilinx FPGA family.
--
-- End of Note.
-- )
--
--
-- Or_out <= or_reduce(In_bus)
--
-- i.e., OR together the bits in In_bus and assign to Or_out.
--
-- The implementation uses a single LUT if possible.
-- Otherwise, if C_FAMILY supports the carry chain concept,
-- it uses a minimal number of LUTs on a carry chain.
-- The native LUT size of C_FAMILY is taken into account.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 07/06/06 -- First version - derived from or_with_enable_f
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity or_muxcy_f is
generic (
C_NUM_BITS : integer;
C_FAMILY : string := "nofamily"
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-- Makes visible the function 'supported' and related types,
-- including enumeration literals for the unisim primitives (e.g.
-- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.).
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture implementation of or_muxcy_f is
----------------------------------------------------------------------------
-- Here is determined the largest LUT width supported by the target family.
-- If no LUT is supported, the width is set to a very large number, which,
-- as things are structured, will cause an inferred implementation
-- to be used.
----------------------------------------------------------------------------
constant lut_size : integer
:= native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => integer'high);
----------------------------------------------------------------------------
-- Here is determined which structural or inferred implementation to use.
----------------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and
In_bus'length > lut_size;
-- Structural implementation not needed if the number
-- bits to be ORed will fit into a single LUT.
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
----------------------------------------------------------------------------
-- Reduction OR function.
----------------------------------------------------------------------------
function or_reduce (v : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in v'range loop
r := r or v(i);
end loop;
return r;
end;
----------------------------------------------------------------------------
-- Min function.
----------------------------------------------------------------------------
function min (a, b: natural) return natural is
begin
if (a>b) then return b; else return a; end if;
end;
----------------------------------------------------------------------------
-- Signal to recast In_bus into a local array whose index bounds and
-- direction are known.
----------------------------------------------------------------------------
signal OB : std_logic_vector(0 to In_bus'length-1);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
OB <= In_bus;
----------------------------------------------------------------------------
-- Inferred implementation.
----------------------------------------------------------------------------
INFERRED_GEN : if USE_INFERRED generate
begin
Or_out <= or_reduce(OB);
end generate INFERRED_GEN;
----------------------------------------------------------------------------
-- Structural implementation.
----------------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size);
signal cy : std_logic_vector(0 to NUM_LUTS);
begin
--
cy(0) <= '0';
--
GEN : for i in 0 to NUM_LUTS-1 generate
signal lut : std_logic;
begin
lut <= not or_reduce(OB(i*lut_size to
min((i+1)*lut_size-1, OB'right))); -- The min
-- function catches the case where one LUT
-- is partial (i.e., not all inputs are used).
--
I_MUXCY : component MUXCY
port map (O =>cy(NUM_LUTS - i),
CI=>cy(NUM_LUTS - 1 - i),
DI=>'1',
S =>lut);
-- Note on cy handling: As done here, the partial LUT, if any,
-- is placed at the start of the cy chain.
end generate;
--
Or_out <= cy(NUM_LUTS);
--
end generate STRUCTURAL_A_GEN;
end implementation;
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/dc_ss_fwft.vhd | 19 | 9156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eRz+leRSRPpou0Iyb6bnhB8hg9kPbBirrzFUAdKqw/be3+N8ZrhDizYaLfXqnwxlgZsSWJCzRfM7
HvMw/rTLhw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Rl74r1iJC/bnSjzA+Rx4NZe56NnmjoVRFzUux12uAkwgT++rVuZ0cWQxVSY31Gff9TGn02lNxavo
U1xWF81U2u/Zi0XY7ZHmbpbdUEdpSv9huiEIrpuLuTgWjBSUwsGYqRxHLx1vq4vioRXFlAhPk9JA
iYodwxjKI7YbbZElfVA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lO1ylq105LQ/xiJNZcB3fPTy1RngsQ3yQ/KJ6FM1qs+SoXmUQjQaEb6hJLPAypYN8r4VdJAzSC/U
5nFe27DWNjEKmiIleROkH20okne+9N7+PhPIZQnib521U3SV/ecBImKKPYRpHhAeqE7OE/DzQFWx
10ISqR1I6WBii4R8gkz5k4dkFHhiTU6fgkIHLUXXclJrpQ6fHHlk7MPcpQDjK7bXjIiQ81qfpVmp
P5Kh8wiY7VppUj33GlIcYsNio8GAIV3e0kBKLoX73uDqdvJ/2zBzKOZoDd0As7C4AHF8YSixL0MC
djalIDRCSOBX8Rd9h057rIe8ZIXNMu/BHoKk/g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aJoUzTg4Ju9hNY+ZPcuNUmGg+rCD8aivgSTst8VRB5/g9QHuzghA24ad2z08gxWDFeIOT/HFgT6H
g4nDsyLlbHK2gxUijkJ6ORkRfGOxb8UwHTzLEIRJ5zmkHtJXYM250JOsiukrgEDT40HqdtSgre6O
kXXliGFm9MU0LwRby+I=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ca/+TaSll/KHF7mIE37XMZRKDQpSdluwuJA9x/CRPHNmOrubSxRKoPtbXlxVM6ehE2hXp6yB6qBf
Fup9ZI873BFwgulDsuQHuOSUPGo4bBHwDnNbSi/4G2je8uxqj4KeP/bv0RKunNMT/FTascQdDh6n
SVSARZi75+ElUvhBfAjPHB+yugMvSxDk7TRPn1RomvNtW1CJTL51/PQt26FoAtnxmwYDcU5wo8WT
ATzZmP4jq9ClSvjXHkf/VnlLenBFunDj22Ef6vdvxByXWMZrDdZyqqIvDvktra69BBPdtD2LNyW1
FCI6v17qDRdmShLAB1bJHs4PPkDtQbDOwcgx6g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040)
`protect data_block
lmDBhH2N1dVyr6Nx9UJnCqbVIGTs6xb5a1JBLsQDb1u6ak2Y9w+hzQuzpRQDI9KwrFRgnvEs7ZT5
/2erdWOBCFUVk9MvsY6SAEvX2k88OrHzY4L32DgAn2B08x642ngwasBeTvX8VL8MoRQJwU3PdcZy
Wm8tffH12U9ZCPcY3faNFcNHlW051suOnfhwVur1Acd+RboAZWFS351l+7sjVXC2Ug5yGSPPem2C
Aowk//TB8x4Fae2mSF24p3Wmp9Y+7oVzba/S+Ugiiyu57bz4wIibGxEqwNnL/trVC+cqtBRWjusv
ngC93W2hrwpIEk9Y6lgmtzEF/nlJwrwOxrCTr8vArV6LVJeBH2KBXmXeqmkxrtbBmOSikXxx9482
jucheBC45w1g+LoBZ5zEmSSc3rCy6pFz5VzgW/KttQkODde8MvrnW5r/rTjn4hAqgAO1HWckbiGU
PtNvd5p59bIHLawabEjLlYMzD2rj2DeSOsn+PYdQ4vbTQdMcFUOkCH+b6swNhu7wmAhO3L6CN3N3
pEiGCGRghrq6YNBracQVnVto9A6XRFBWoHVSkSCVztIUquL3cRXMzp7ma8i2024zbYMeQrl6wmrH
O49189DsMfMHpEqkgT2xz+yo3f/xKnioXiA9U57X1NjXq91HpdBJhhnaV3Eg8POTstp5r7qjfPyI
zTkYJ2IWioJJNcmpBYAn4SgHyFOvM0246AbKxV/41P5qosEGpXTFGdHJj7JmoyRVhOFB1m73FnUf
zc/KQzh5O4tPC8dBGscN6Wun4JazZ1elhqFIUFO8eTvI3YJGNmDhK5s3wQ8OKL4jRhR8+vdITPOz
IyYPrB3IUTWNdkjLa6ulgzE3DTCViGZGo0eLe/3b6GEPHDTTGV5+BQ76B3DbpBa9/CEs/O1OCGLv
+UjCNdus18u8jAQla6cPSnxHmwLWVgS1g8A8LRM9eAE1Jj2gmPdRRj9sT2QQke2QVKW6IuJwgrJN
f/FoFD5OdmpSrWLo8URr+8yEImFkkWG1rlZMF4b2agX3TvaaW9CD34M4kIXyaekKGw8t4bRNB3xi
K0EGA2DeB0Oev7MZOBzgEZms1kziADkBhbpUzWy+PMq1W0yxcWLfAcB1qLlpEhqozaoZbajQN+kK
ObDEAqEjqd0lq3DZzLpAQmOtFMHH11K8xUt5Z2yPLk7F1bmKLIUNbhmC3bS84YqNSTFNZyWWdZuc
srHnDyZQMVn0IxLD9eRQjDQHmFsNZWMdKxzQAyXEPDnavZvUnKl4+SqLkgpTY+nDn2kRFHhxg0nh
6ArlHZjGlkQJjjjK2tTwgeG1a63HcxewMNweCEauYZmmxUr6zHNoczPUrwyjIHJBv9d5XORZjJrg
T3HRnIi7rZKXIl5VVrpIiTVJuFmXdzDHRhJ6IK7OJccm2VelAGD51/zpKLnNNbuJ3HJ/9yLX5ge8
NidA73tMAV4wcIvRZyJK0vNLogsqJoVZAj3Kj9CGYhIjDW7hW85wwhvMPmDCRki0K+xy1E//nlES
y6rfoJ85cVWV5K7DP3KOChx02VES41J1UCbHnjaVdtJFlTPU3KB0+vNpK0VpzTmUcF2sGwx5qAxD
ClIFz9Di3URw+NZnChUtx1McpqVXNFVPV+xrS0Ck2O23oFAuUFjulQdwnex5GgE58FzAHlC7HnY+
6sXcr/s5h1gcsARWYeYLRkWGVfSOLdCRxl5DATlAIhyIP9Bd17WjGZXVjnmnA02q8Mcl/pRds46c
FmlcifhVs9fm4nE3OtlQmIFPD5mFG+pyH5Af/k3o/GKUGeLs2Ypko85ZgYVxEw06ChO1O4VVP1nZ
L28f6BlUpbB35ZaIQ3mciDJNWgK68e1H4yVtcn9k+r8aVx3Hf7x6Ok1QgxsQl5d1o2JWJKiciik9
tLScTYb6AzuJoVEhv2fuwSGFklwcS/kcOd/xZ1A/P7dZOMikjt4zxbMZ9zrjjmSzdMOh1UaXFpe8
QqpcE7Jfme23o36SmMVWdSsEY/8IYRZbgtfSKmeauL6EytxKgnoBDwOBaFPr0lcfldP6YYLlFGpS
AXfkWz3FgQ+xTkg376AhR2eaoh5T2EFyYqtt5fX6i7j3Krx6b5eKY4AG9XkUBdGagR0AFXWoAzWB
xbkuNijBmGa031l983iOGJRudR6GuMMiXrWroGX/9OxJHuK1GBYzE5AVox1wLY+XIdpE+HnhDvJl
3wU2MfyoKVjHQ+fyCZ11RV9XHCfb+SwOSxDCkXPhvICDDb+x1zpTeO0XW6jstwxPAnw6W9XEEfza
OjbuV1xG0zaFjtRPN7T+iT/ZtQZTxEvuUcKB2j+uZ2+UUJiCLFw8cIE5v3/fSWlqOolGXCMGMq2s
o8dYztDbgAiw+1bfNAvh8kdQSdNYuH6dpy3lYA6cVWI6xQmg0h+9Di12mK8wSLHZmG0v0s23bFLr
CcFXNXrDmQosuPGv8SZ971bOEgB/tf7NTSYOhUpFaYaCvCtKcwZz0hjuEvurLylbQ9Xo6eVxWhr6
g2fptgjKo/Y69iyY9PlCs40MEkYhKuv8m7NHhOqD+XKhd3GpePG9wj8Gq2iU6JAb4l5zcTaKCl86
IhUZKv8nb5nj+bYOjhJWZFpa2d+/SnNn2OjeG8ZiD60mLd6aX+q+eQw9jdrSu8dfvER+2t+ri9wa
HfRggp6WK6sPH32/bzHP/lDJUrV7jj1I4MCfPz8P920ZfS1He3+wlI4PLHQ5m8ohhWF0O1VBJ7PZ
LqnufhPDBPM1Oy/Omc61Ff2U5HzupGucnyK20yxVB2QG15kPh5gPXV5DWLZHOlGjS9tw+mSJPYhY
06HSLSNCu8zZFM1vCRE+vC6/dDyxVFD/h8gbW2szMbk4JvyI6ZO9guQksuJHqB6IvoKC7iy/qM0u
Jtwzm8YTYox/nr1FhMC9+CJJrIJB8wEjjUJAJsXA1HTKFTZsq2ke5nP1m/4ic7kulCDJOkB+kFNu
nuT1hoEJx0U4HkFOM/am2XhpCgh6z/9gCu/g9/pIg9tnIwgu4s+b5AJOrBvSHmYIkpIwaYO9h8I2
c33ILAQNN30g8gITrEiwtA3ontgYKs7T35wqXVWGzZba5E6WgOHYa5tOOaYK711AtLBy+Q+MSZQu
tZdI0bYVxMtOfuwkvUlmj9n9zinCzUFNH4gudq67owUeiqDkZWmWR4xDkR47aiQaw+y0yvPK+RU3
0KQ43vOVinHfM0MIAxQnKQz3bkd5Z3qc1/0eFTmNOZSZKhSkTIdvNBJV1FgkDnvVdPuK6lGF5HB/
YeSrCDq8h+VofobmP1TUVyBaU8OQBNCq8PQ+5yBvdV7Isuvcfii/YG5kPg1wOEValNRm95CmC/27
j9Hx9xeSVD2s1H9hjBcyD/PnkQ1+wp6oueFJELGVjD89FAgzPL+JKWyhfp2O3yLktPu0ye04L3mA
9qD+NMvTj7S2Fl+cBtDJZ5S/nx8MQMvjYh59HTTFIq+lKzp1z4zLtGK5loV07nBY2iacMyXy2U7W
RPFQP9tf9mEmgxyyAaO69qCni6ZceE8ol3tHlBTP6uP5p5ZAVkWOCrqjBn6QpIh6+6H7jrU8IfCB
eJf7xvoSuWoxlyU70I6x17PIsMBeD9ZcEbCSTH46lC0rxxn8oT+wbeFOvcDJlmkvkb7/Zfz63gWQ
wv2kifQaDz2pOiCm/P10e/s6PHUqLp2xi8TDS00ij6LFG7vx9wiH8Y18MYcD63MAeWDSsf08MBn6
Iv0ZP4jK3pjeBFDuOTFZgJrDclGUgNRBtEMHNS9TGfgNuI22bkCgHsYJNVJPQBmeNg0uTFO7+p1e
OrmIiO8H9zX2PQ/Omvzryy7wFErbdnY6sdF163zGG5qxLQycSpwy0sD4pKlbBHNK8l8ZSo+8xCbh
Kq84GuuRrY/R+KHweqaEHvsJgIjjq5ZjczptHbNtSDUCBiERI4NCvJOa6EFaqYBu+LId7gD4811Q
4FxHJ/XUTEPk6ThI6yUFuciphxhIKLVP7Mxa8N4dobMuv9qxAr8LbCkj23LCE+2UXmBq2zTzhwZk
KH1sA2xbzlr18apIzOtoZc967m6xlAlSyKF5HM1SE3P7LchsEaOxLsFKs70NmPJMwduqz+Zwq9ua
ZfSsAsKb6n1P+IXOKhFirAWa0qgDRBBtxO+5WXkGjlM1zmGLpweMBM5RoeF9QpHAq9rrpJTfnY1p
tyt0k7AOUNyXgEgjQyC2+/co9g7uz/XK8PXDuXySBXFXsuxMAgiPgelLCRWt7F3/lDe8triJJhuQ
MgUT8wPa0s5uzXKG/bWwIiIuKHcoYmIUjkNAB3FU1822A+Uk8HlVepEQp6hMIlnoO3zrj7AZysqc
m6MEPSKdheyazLGL5cGbh6aciijwuW97/fUn/G024GElt+cyjfruFqNDv6GysNvQmCZLbUIzFYY7
ONKQ3YKkqASZktW9B4ihPnmUioQI9N85QGbRS7wHXhRxr047aKvvRSK0A3V0Dhm4OLzbOA9f+kmI
JY9GXS5hSDAmNl+fvpZ7QHN9lp6JSJjqMZ0/3qDA+985TbNEc8rQWOIXMf6uy34lrdAueCEtCWWj
Rqd69+2zunb347VIu6iehnnuQF2ktRSUlywzEPf4fUtyaZWFUFiI02+z2FGdM1uCGEQXujSIaIwA
qVqjAir1gYCpSYyMjlcQP3//pRIUUEIxKUPf0kxPKvPKCJC5yBpZ7OrnGBHNp7LMM9NkhS/CKC8p
xgclYn1jEf3Dz5IIhuf7mAAB4UscZFYYn00e35XyWV7w5BA9m2JtFFyj5B6OJRsGdt22oI1sVwrJ
AZs3/KLCQZjidrz8KrnVFfkthy9vzO7js9nkusH2lWtqeE+U0h8V8l7llJ8wyzUquu/C5qQnhD5P
wcpvxXYdaMb1QTv1U1YR0aV7elOo2m+PYJ9NK6bocwfTzaTvKmQ+yqgFvwHpb0pWvnvfk5Z5Q0bl
iyIw9VkzpNSNocrLTuUjFq4CVbdSZhtCkR6DxTPLhJbHApv+U5ZJslsk54X3PuSxflXV/WVq6ezo
Z4ZFwpry0o99jRpRms3Z0NiNr3ojclLNbNEjA+WamYvdV2jLI4DK4wsCpJj8N/Ezs/e1PSMUl6lY
qL9Y5JfkrBs259nLqGV0Szi0my9nMlj9TJ63bDXwMuaFNuCgUkPOSttJEMVGwfK0G1AGwxE1t8gi
SpBsF9wxVKCBKBmeIpShdEJ/aBEYt9R5lFc5tmY94lbWhN/qWJzi62RLA/lEmOdbDjXLIKwcH5Yw
P3eF1LrIL6bPrx8DAYa/ODRa5CCFOO2T3m6/rnJUUjusaM4k2/poGhBggSEnuxfGeNCbOP0sLMZR
tEeJ87YFl3Ye3+aH584rU2YEdmPLKZjgU5ISvddJfy0t3Eeo1QAFwGUZl/RWw0KEPYkrVSgH4GYe
Onmn2q4D3DjOhdpxdzk5CFq2LoySnjWsiHK6LKBVe8IShyKeXOEaiMoE2Sm+buUg0ZtYpqtHD03/
fjK4V6Yss7Ix5o2C9tObxOyU1PFNbzZwFNXE+rewrVHOs4PtZEjox92MicT5rbKaVs7ypAcqX186
fNHsmuF7Ew8oK2Nf2aMqMsXtxvDCHShdkVqfrz6bs8foMM3DXhvkbwCz+KfR5woBrloO9XOdRP/k
HD0ifbTPkRkpTB5c3VEVSwFVJ1aMGYrW9WM3B/FW4RZy4q6CLd5ndxKnwSWoZCtQjOTlhs1g+jUd
Tw9Z4FIl18PUkQkfCmw3DKAvoEhB7s4fdDMDOJ6zuU+WQBYGPkS/5FMd/sHTAVkY4V2A4W35hQ53
8R13l8jjzxFdTJmfOLSoen0jZroaxI6o14oKneV7tTAAxKSS/1gM5zglOZPF443KbZN44Tjh3x5+
ZsYm+KPYzhpXgHsVS+rjaynwpSLfs+btL5bE+uJaq5w83ZN7e0o2cFoI8F55TG8266A37qJlykTO
KAU2vr6If4NcaGfyUohm6bQHtlqBe6Hj3Dq84G13YYK/PmwkEN1WYr+8k3OHj3W+JrlKmSOrqg8k
LmhgZCNPEaxEpy02mX9L7MzJmjM8m0Nhp/AexHcUQ+US32K7sUBaWeILqmVK+cvyZwFMM0txRf16
uBCgtpZD+O4Y9MR6vLP/KVm9JjskGiD3Gy5IlFlPYQC8fQJUSAsClV4b1fosgybEcjgyuUxlBgGE
xYVY2CCY2Icev70wmD2TF33n4xQhsckOCWDszK8yET6GqGxv4XFR+zTvX+QKUIQwKeKU848NCkdz
SQ98ueA8fa3rOwNwpbYQuyDm1N6svpTyyWbENkhqpisBigCy+ljENhP5/cAhMAjUbWjBsT2EMzHS
LR7o94FMhuK/57DhuJ2nBOzURhWA8S37tLjcBppwuv/5X63BINd0+Z9KJZH8CAcnxwaXDat6LUcs
uCGCwP9u+00kzqIsb1YbYNmjay3ZRHAjAQLQUCK5Fjwqj0LOn+i68cD9O5brXT3kiQR88U/mX9+u
ostJ5Bv2YpM5DH2pO/19VRGSerGS33Zt6QCsi1nf002rRK9AwKkRYA5nzWJlRIj5bhkDQPdyikLP
dN/B36RPI18Wzm/6GpcJaB6uWhG2nhhk0/dCLMXImhFqzwtp6BLGb1McNq+v6X1CTE3cGvOnPz6P
Ev287hT9ddBV6TL2BPhg39fZujwYYZbG/nj/2TOqGsJ52HmLTlydSs8JAQuox7XaavT++8mFCLLo
K7wj7KZNA65Tn09kpA9NLItcw1uuCbCR
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/rd_logic_pkt_fifo.vhd | 19 | 44022 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
SYUpj6do5sFTflpbsRmqzQKFPQDYrJyRQArefGItBrRpeTStPf4iOexrlL2KuY5Tjxr42gzfz2no
s00d/SuK7w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NR3ykkYMNFMRKu0xHAyt5DYiOktc2YTf1JOlIURJ/ThqHJccRXVvH+Sc3vg9x993epLj5za38fd9
R5dBjv9keX+G5g1u3CtBsdqXK+hNOz/uDIy23yxr7rHw0ImE57TmiDkVMvMwv3eYKhw+6jZKYes/
orVUKkqCIC9qrUn5RTg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HlVxjhtCNCKKX+WIZOv4bglrDneJvrVwpTadJxqH8bLj9DfFux8A76EOB2zOay/g3B51jEHFXs1k
cSPeVifBOPOW+4hnoJ3TimbzQC2WXDZLrgI3HV0zvi2+v+260AsNylQU2ks3dLwbxExBHvawkhdm
qLdLQIFdyzjRMD/G+fo3ZOpvx7tOdM4iBWXd2qur6t8wJth9ryhPu98XGfaQXlmJP7Tzn+0ub08s
DCWHug4G341eF+dWmcugGtWe2Ca08XjibeU1gRioez7LDJacBlMb+me+eJNl34Hg9trbjeo+4u2p
UhjBKGy0TbAWhSuuGKcCtfIFOUbYcwT6t2Yt0A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
DoI+R7m0zbJxCq9A8c+QbVnIsy2kNMG29/strbjpu4rQhHX3C2LKQKMwC4UXbs35yFBTN82oCtQE
LCzB557xK8srP2DUb2FdCBqlo4nmLOUDlZKHLRnMjMktj2MJoV0ExtbMFAErwe3zZqIBchZgf5Be
0C+OuuK2xw443onEGyA=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
jkJi3dDxF04M0w5noeJKvbYmN6cGn5suzWOH55jYT8k6r3UxrWZdHPmAWJgyGzXTFa2rcCzw1zFN
8CUT3mqhUaMicnmv3k1IZXtmQp8LLIMHIhFQWUBUexg49lQQHlMizPzJBAEcyMQJQl2JrQBPC4y3
FtPjOGWfsQSXXVoSz8O8MOKUSTmbuzqKeAR7KYOBiW1PqJBZo+vP/teWIw2p1h9/ADBVH7fQiL3s
cyUleDPcPx934u+grxqX5IGh+uK/gO42i4Ms1tDDhMblp6piYQ998xcC3XiMWw8hwmR+KGnfqU8Q
VD22eRbZMxNB+D8sxEO3PnV48eApa0h9wT+rpw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30848)
`protect data_block
VdbSybMI644lxlJ/GwYDEMswMt+jI+aQz0PjhZSK28Ludhc4zXb9cc21vfbliKToVVl6OjZIuV+7
FtgN0Q+hnsfPLLJYFFGKbQVwK5YZ7TVNVu9vGV1UR26HRtZaK22OtN0b5C2vJD3t+/CHKATE+mzr
EC5rZt3oRfVCUw4LzfgG0Vm/mtZFG04aQ327ye2A5Ws97mv4O8BHRmmQ/81JFOeh4O0mYA1GP2VO
QB53uVN4jiS9o+VKia637VXg6i4fBZ+Beml8ygEGmyVdSNS5R4j7ippYQo/PPo8QQRKtsGKU3VD8
HW6jVYclR+PZAQru09gRzIcmX9cw/q+nwdNjwS1wADv4W6uziI2XvPQBnUYrRczk+vW2eqb9DiJJ
eXYuA6VvN1bMB94saIo297NOfXSIMD+UN4av+15qfddRlAPC1ujp00c+d9mTwI+vNbxk0Q97yfTz
tZ1gdksABr3tomyR+qoHVi2bSwAP8OKIUGQLJQqo+BSRJ6Vz9kwmvbXdt8GT6stAQJ3hzhqHaYV1
4q3Y1UkfYF5oFxE5SiOLR4J8lYeZZM3bJe9T2skQBNWkyabbe++E2eH6v+QQP0gYrqksHD+c1HDE
RkHV+4pa3JOQquBiKs/Ndp27Ec335NN+y66xU2nihKKiIfIXBamzQtIigUXRnOOfXfhIxIVKlxNG
gfOErOz/CJ1kwTi+CnhEnWZyTAOg61RKK5mvqDrJHjAWtXd0sYJgIKwq7IU8Fhvtkob+H4jh6l8t
G0NxypMjOJYaZQK25uGSdXSJnG+Cb7UTBJ40hIYvtfYSDhssd4Rn08uaO5Yt3W+T0NfosYo38fYp
sphSe6eY7xhnI2lRTDkj7IpnXhubSnkgM+KTb9WwJnnMmqcIiiQbS2+ALbzPJDDh68QqVCmBBUuc
FTdpNNXGB1c4OAszfTOaS6vecPP68pKuKvvQhFML79xdhfQMAG5KLPd1tAI8UdXmtXc2V1BqCrOR
GSIYucpsrG+y8Pm7to2P0baoJ8x2EUWnJ4Np/HBsVJDTcaDclWSgBrgERhX10I8bVUNhep08BJMw
oU1m39iem1As64emNpRDF5qcnS2lTWzeYtBKbOuoIbAc/mD5nn0TyUMiEYPDp8SQv8Xsbp1uMbEv
mtBygNGL8xyDgqwqsm/sAohbuWMFQlY85c3bkBCH+ZV6v54VZCoszf8ErMj0DJ8Zhwz9gYIHonuj
O/5AqoCfv720lI+ApbQmh5kslKPbaxOsfatHV7fQhJtl1dxpHyOqtZFCJpcpwihquS6VbJg4dAWe
E9ObYqJAON4t+vPSpSp9vX0tvmec1Er734I1kg+df+IkNZt9FvOJ0KSzpes5TgdVleglB7/Hes8a
3ZTMAefkSQwdKHTgmkpC9GvRWn+cqBgNUxP1X6hG435UEArAJZQgZTmUlPgHy/trhoIySEJEeNhx
av/T0Ji/12WkNCUMWEr7OC1i88e8nlrXYaDXWQNAngP4UDuOJHMhN9bLs9UKkFs9O2pKvNC1nmEL
QaN5KHquFLhyCT6s5RNXzixgTZ8Hn4/0YxgFg3evppCbW3/tSpuhUiS2Q2KffTE2T9Tz80Awo6u3
Lzmf/kqP/g0Cgk1SJ//q56UuXXDMx42yJ8+kDHxxVUfFcSYHzClp75eIqP9T56hKv427qnh8HalI
DPweH3uiHa69LL1buypBPnkWVAJFQIqFCos4LVW1EsI1AnA5UmKIZ2mxr65XVTld3tvQwLMXJUY4
pfL3XzN0PJmBqBeQu62NtdO6WXcNeD2gJnyovUl/Jgfz9WLHEYlXAN9Tsjov6zIMfrnWjnvheHba
hROjms5V1TPCeKD4l93gn5kZeHOyDcYdUC2CC+QRweHyq4fsMnjoRT/07gwqrxc9yaUB5M0ChTQY
EnnxTClz+/RHtEURVB3h3Tzi5qAogPHd2KbL5FWDucbyQkwj5akuDLtvN3zrR5+1Iju2IMRfVYDq
nQc5muQgvVAYQfpg1wfmlLXP6UGNsjveTN89bypN603wR0x7GR3r9Tg0tpfic+bnv+QRmQtpm83q
HfbaCqDF4Q2DEymklS7vIfmZ68pzWAUi/DM4RL6MDZ8s9+hMsF1UyyzsOtuqE+Y9cXR3mlf9Qjnk
5vkqrSWJEIuWZ1NgeWQkvGQmk3fnW71Yoms4GldYTrpvtw4AQHaUsZFL20uDl701pyhAdHTilHd7
EcL5epl8xIXxxrtBEKh0XBMLSNbIt0QfrlzJOuDAuOXWx9a2iQWxvcsaacfGgGNa0pRGwGVePuJY
FkFP0gLuYVWDQdEkp4IYDrwN2fieUTTTXqPDDAcBY7J4a1+d33xl7TgCoOqBHJpeXPaZZ7CNqf+u
lUrXfsrg9ZmvAR7TEPeQkSMWF5T9Ek/K2QQXct3E98ajX59mCuR1fPvFULpuN3HqdzkEj8r0j9Wb
my/SweyUBHFgBWIQnOrZOYY8He2jXJIMhRfw61LUoTP/iKgsKz3RNrRC07zPrPtMIEnJItcVq+1l
c+T7L5Fv6nXXJjNQdalXLuScTBZfkOgnYKvdBu9lgXFq8zgDfFlwXvNuxUMSHeT0MoxT4Ldut4mB
Yl2/kOaQ/QRq5p0pXKXR3gK5VINmyjE6fCLewk8MRoxr3pFmTV5TAwd4KBhTSNd6k7fix7gMDVuj
z4aSGdA22fFOx1fvZd+cn5mUn/SBpyo6JyvgnAjxPBEZA4rjoQxKR34Ntmcq21F7IaZAtxm5i3Oa
8tCWtukaF4vc31geOdDnnzyr+Bdr1xJGax1NA0OSTU/CAaKx6Hu3MTynyaPoKac3z1aIBsr99VLv
ssKt9NU/wlsvwSGaJcLDdF6pId+hQVR+iqD4vDDr1Eoy2EN8ydC+AUhuWYBIRFInMx9c0pXOgWB1
KCt4/CfOzXh7dQQUaMiRjzOWxWIAweY+kOIIUZmdZJSW7aB0D0Ic9lUSwaQ6lGfm5s+Kq+afMdRM
TqWXmwwXVRRpWR3NkT2p1KcHw3utW3UfQycVtfVK052BnaSZKZBTkgwHccYmyvlPJyw+VGIyK5td
5XfTynRKe8IZzwpzk4lTwD9PPZVkhTNjQUt+GwOgKa/yXuwk7f45mboATVph/iCUAGeBFgryrdmB
dSK3LM8GTdsnv66Jq2R9yz+IPMXCE3tXnGcRTdnzQ64XkH9r/ZvOFjjOQkRBlBCjJ7G6cUhf/SNq
jLteKFgzpm5OfsjgOH4fx259Vq1Ye5WREPz9ZQrvccwWHGPN0egbUnpNKCp52lxyyDYWjdNr1hX7
ckzs2WS+5QZYOwXDvhidhz9XlhoHTEbk999TXr1Jktia/qI1gSZzZaYESDWCSd7Dwn+zmJtu/Bi/
elErPgyEF43VRVWPWzzUEHmohSclx4CFzcwWG+dAIp+nebSOMHs3ZOGPuzdWCa0r8YcJzFpZU14X
5uvkhjynk0MRUk95hOW3QXix7juOkm57wq0SaAOY+fFmmdJj1SfqOJLopqnIYRpugW/D4OOzj3Vr
J1L3uJwpIJ/Zod1GNcL+jgv5H+T/cM1KhAFAQ2oTSYnvUdODUnQ1ZpHgadSxZEMgAQYOGlHoVi9Q
g9+9vzTj//GUqWLk3YH/Xfl62Kf7eGmIzevEGlvtP42F8wCnat2aWpoj8sfGNF0Rjf9OvcBLQ7nl
k62vyJpSWouq2OuiN1nqJNYKzkV1w57o+Pbed54epTejVnZlAqb9Y2gt43ql0yYdgukHuH+5DlNm
LF6+ppJ5JZ6YixZ/oeJaLQBl6unie2LPSs0xJClSAL89VPCLsTttsz/AiCFBH7PJcJPWLQagEdqZ
I462+eeB1+Usf9Gd2KZ5WRbeUNOmiV289w8Pb1IB+QyRt0pvoQp7KyiqdMNzI2EnsFh82UrLsF+Q
PiD4WlFe8l1TnHlWI5p1cfpOW7+jJFh/XeL/M22nMiz3gJnDJy3sLJwTZrhPaTB1CY2dDT7b8PZ5
/qAg0QRqBdL+U6fZv8sH+bJsXexQ1aqBs4J3clPs29efQgLnOyRekql/8I1LeLwcKgz3vBxhmuUU
McY//1Yk5HXfMv29+8SzoUU9kzCKQwieHtMo2q9qFhany28L3Zk1+tN8p9mHuiQGi24LFAojRYpP
PwUopMdcE4JUO9R190FOGNLWSVHo8i8YX2hW3jvnYOws/iTnGNHciH5V+uaKW0qOBgJVI596ChR9
AV37AI8CCOlUhVmXv9CAq5EEwM6//B4E1wULLuSY5phWjxKxCpnWrlc5U+r1fim+WdgSkDRp5yRB
AM+uy9MtcQBE+Dy5jA2qlCFf2036C7OkTw7x1Ww0zoYAIBu0bHKHHYt4RWVDG+zTrc2V1iKjkpdy
MtNHr1DgrlHglonOCgLYI/H426yto3lN5ntIqCO2OJdiVYbAQRU21hAco+o1CYVJStjO4qAtd7ip
1jd6bfXY6VFLEoD58ogusJRyAjvWLjPhD3KjfnyIAMctVJ2sjBZ7ryrz595HmZrTObT4zusBLjGx
3cwSMdlswTVB0nXN8rpH7NHSRbGaJG4etgOPLs8aN3bmsVaWKXREJ2QTzr0DN7b9fFLfifBAFX8X
60wVfhTP64yTFehc5pAKIT5fl7jYyqZO2LanK70AZtvVKuwf+8X7DBHizxzACRdYWhHU1tqiQ9ZR
zV+nLBBxS4oUdEzvd9E4SqsafCt7rqEI0QRC+Emr/ro2IQSYPWgCIETGLdDxB95eUpPgvAbHuKRd
OmtRP7CBy+bW4YOO+VL2ILIJ+JrjWYn80Gx/vjPFh79XoTQTEQ60roWnsAYfR/6ZnvtIEFkAIu7L
zD3L9dC44zwjtjogVZUXk15PbHvudwqbqSQBeckD6uQf7rZnxxWxFobRxmqxqJYnJhmDa3QTlusL
a0rLsuc1/qZGB36iWWw71fUl37e9C95HA4XSNxpjfu6Haur3EVAcC+JncZhrxBiu4ZArZ8E321dO
Dd1DxAQwlM8EgV4z809gUvZIr2babdpka7lpjzLMHMChgYaW6ZVtHfDiTEGeiTfObPLWI0PwaB+q
77tOtfxT1+6Q11s3hSRUSjPPLJrznmc4/YFEpJ/zvyvMS+BmKNHEht1+7wHx+aC2XcJ0alRJiREN
Nn+jNk+3IWW4VBPs5puJAieIFeGx8r1bGSX6CDGgFyM/e5KEnZ70DzMIqTGsynrpGHHdZzc4XU5G
NDXe5+4ou6pkBVtEcUOzVfk/+RnjYbO26Ju13YnrWLtDyVQTLCxaQKRA1oS5Gufzzp2NGjs/sHgY
DnQLPUA0vl+l2pmv6/EQedbiXSKfNKwn4vKhvS+Mox9jL85ry4uDR5IN2mszazOiiZxHnMsvCu44
YNhg5g3QXPPPKZmZ3WsCLmAk/hrYa+VVRf1wZBA2lNiSRtOSIRb8EZRWb9t1oa8i37Qk+ucEonqs
MeAqMilTuVxJgdiif3NXHIgmsqsAkzbgAI2EOKP1Qq2SH7j1rNRcvGjeO4VW3t+tVedesOlVrGsa
RmGdeA0iUqFc4QKodjXP4HOHanxxTcU/GlyfUz+U69jsUrx/8UmTvkvlqfcBJkAriq7yFpiabip6
SCgxV55T45ToInPYxwFfnkxaoDGcsBG/DZ0G+aHaBazD/Mfgitx2RgRz85fsC37rF0LkHeDwwwZM
VMbxG0vgtP1G8Vwja39LxIGGvI4iCC/hKeIEYI5NwHkOD6A/JqM37/JFSI2VcZxbzkkGSqI/rVQa
m7aPdlAvu37+FWO0KKxt0oKVBt7ZfTAVqdm5uM0sKe0EDqPY5thJYnB1/1wqYjtw3vLvRusSHnmV
ZNGGMc6oWO6wkK8PQV2MadW5o7tQ+lx6ExSn636tZrHL38GW+oSVSn1ScOS+5gsO/Wt7vLwxUhWe
zyudDwVdaKW4TTSuEq/6kT91dcAw2DZfCvgFng72w+4rU6KqxLuEmmzJDVNDx0sBayYhlz5K+LWI
kWOH+WdHWvmbTT1NcH6AZEmh1DlEov4QZcHPo2jj8RraYygsmpzS/qK2Dy70yMRghcACh+0mGHjO
r8HowKm7fIShl/rtZtvnVpjXcYnaNUl2f8Svs4MKMSH9QAYLuf9GZjph7tL+9TSDj/yNj/eG38+c
CP9mU6D52sdz70BJHDU65LvmvCQ36SABWPLY8+eZjW9xogoD1wusHepgPdeO7bfz0Xh+makPlYLG
67gp7jKCRo3ZzQuLQXp3q2z85bDkboiyq9P8tmU8dsxCbL6ndUQtOitKsk1iQoynoWW7C3bcbXue
VoTFa/Jpik/A82+497rnuUDKouNTpwUeferyqLYrGBZUgFz21/sjvqirsyAcjYL6R0tvZq24bxmJ
ig5ECWKtgUS0Rbo0KFWALA+7NF8BCKopI5IroWaUYuTOEABzsN5W6DLJFdFBy7ZCgndzbjym//lM
iFRDA1VkdzJMEynfuQd9StBmdMlbdkEpAp5AkVxQKA1l6kZwwjy3xLpA0LCwASQbOC1nA3VLS1rk
AntSBqgutNLpaEbHEd3Zn5Lwur8u0QRDX8U+UnWe6YsL99nxpB2w51xcG0mDBSBv3MlTYSeaItAi
kpR4YygUij4CaDzmxevD1xhHuuTyxX2ZemLi+LEBxEDnuJ1jRZm3l5D27xBldLesvOVcVNFgKeyB
GPTrY2Oxy5UJvwZC5dSqNakju2god4PNs9+KjdJEkiCZqF9otxMjuRpcYpzLDLuieTjUPZlfOw/+
lvwDZVW0kTQOkqyfXbHGoYUc7Fk/r/aM7Wi3WRx4HneWY1hGt+ImTfA0xPv693HkIWnSPsQ110j6
8TjxNW7EqzRk8LWhR6Cr8Rs4cgouXYs82/cbd55suoobbBTXUPu8LDplVdR5F8slsRVzvi6FAOOQ
Ktk+yIBmU7yxf6hJ1rVrMP2TgCJfDtX06HNKyHzw01pnh0SJGWACqwvzJNG0x5D+BdaPi3xWNAZp
9V1n6RDN3LPeHauA30WKlx+KDsiXJfYwd9Lf0YBWoK2nlI0YDahKOypZAWq6Wd23rt1mLwYRWloP
vv49Cvo9pjOX8JSBJTY08Dr76MRqen2H/IbQUjz7wxIwYGS2hE0T0+FeknNMeWNVMwLt7q7P61CQ
yx5oa6obJaMQ8mmDtNlEUXAJV4EU7bZpjGJ/LNG4uHyuvuq3jvJWxBKAU4ywHpho6cnSl/WC7JSw
fhzDDCHOovJKJH/Ett6AXF1ZtCkW+gryg/Erdh1j36PNtR2Qkpx+jsoFQRZXI0vsQKQA24IND2K6
UBVZxbahD77pNH/xYNZGURvs9i/sM9oc6jWR2I9jm9P6hj9KzXeTLBCZzgDiDoDVzBG70LBIxZjk
miPx4ys/bwOLUQ2kjAfYnftBZsxFFQOaoSfcO3p3jXmU6TJxDjKJXaxZQLPePVP2eHhq40rY1ER2
3bOG6QagLi6glT/nYAl2dzWDgfUA2gpO6JIhWBTE5LlMpFLZdAmNGxFCG0CzBbhFPNFmAnaRqswa
1ndmblPtp2nmxcbmnc80LV9k/hLCqMzd+gFb0vpSrJpzW9Uvd+mRpTIbP0cCtbCVj3ArC35WetaR
EQNuTPh81H2DluP1DBhfDrTxokmO0UpOKnBLtAlFIeVQSg3kLMsZazxG27Rjf98mm6YZIRCFRbro
/R8nM5MuYMNJONMCVCyyKsis+qVnN8kI+BhVjo3ZwJ1Y8dmTQi7jNKF/RGRVNThwWFwMY+1iF1uD
/FAgLJth09GnAC4k0BslsJSBiyi0YfDjoY+iWLN+gkr1tnUR3atI/Bzvwn1zxdstcYo3Uf8WsoaX
jpfvZgbT0JTyJyOvTLxS+CRJrGtuayMPi9n4Ky0bfgNhGPxsX4HVn6jzgl+S6qBgXQ8NQto5n3ld
o2H+w7u/1xSJqXQAGrfpXWJjssBoH/PsW7JjsYt9tCeRZHrUtqGkuh5Z4V9Rm+oPCw+NKofQith4
4Eq6GkNngt21s4yf/6pYxDv9Ps5Enq5oC2y61NUned0Mspicn8Pk5eAwOIglls3E2qdEZ7m4Ov5M
nkRNmWcG8YmaVZikNGysKzLf6vf77b+cKey17WufHfZK/p1ll2FMaDeURkphibLIOdmhkhL1W4aM
HX+lLd4oJKuKnJTkLTnH6xHxt0H5zzdpZKWBSoglhFi+Acri4PUd/BBcbc0/BA4l4JgeB0UD3lCr
mfLuIsf7yBMKH4h074a0iOGxQSh7ZAcv2+MMwmMA+Xbujqc10DgQmX71U6mbolPrwjxXzblxK27R
jnH+gNgNeD6ABOHtRaCfTfqsDkm8vGzNmLNgIpT5qDAMcRHm1ej7JawNE+jN6boMFu6PgB27N6Eh
3APMMjQ0YhHou0rNa2PQpycVv7+cdf89YDae6Me+QnPHxe9dESFyQ6cs2gm0RgPl5ZYWbq/7OsFD
ptMsQuPRI3XGIZcVb5JtmPyjucuPG1Xz/bwLwRX0HYbFddxLoYqoD/oQMqjLHj/MNOXtpG3YXmoB
2eaFAE+xq+JA6F6Q9nXW00MjOw8ubzviLKy1sZ11rxRavc0x6hpM9dKPSS2NJ+Q6wSiw2HdUrmvW
7+ddzc/EeNoDm/nKnWF6cz/RYEej8hxa5DbnTmy5eGdiGx8EqM/4hMAkzQiWoDGt4rwV96aVDk/h
SvNhgIclQISX3kuhOw3mNADiRpgS9CVCpsaLRQji+yGDoMrtkwYzOTkpAy5ew16X2bAx+dm1+8fz
YcMjOvbn0eBThPqbkBcOa7Nni1Z6r6GY0SAlq6zUJ8DmLVDDzd2LJQttJm9lGltNKKgeBMehhNrF
Bj/ZI8FQ+yZBezv4JpQJgiuA+4jHbb3EaVeycQ6EeqpsZvscW+iQjkk/qhGFey3ZnA6QQTfKYRqj
nv6rZcAB2RxkcLXb9uY/+fhnQrSKfAax8Y/2d3nMks+I/SiBf1oRp6Sb0S1961wWhph+4SumFpSr
9b3gi4Wqyy31yJLZX0RcftzgwC5TnhaUGcwJAK+aeqlxhTf/CH1mbo3bawnpuct84sAnzrtQsJmy
UfvgR/ieVFCm5K9kVkf/m7V5tWytJf0zapgF3e4kRgoYUa7gM1pBcGaJ3G99oOJ962xTo/9jte6n
LSkCH8zZ0P3Vl2r0MQvTTLajbe4OBG2AJRqpwqVQ/2kTuALvljf2z0JoYDzSSxGH/b/BcUYVRBga
Me+g9s2H0qdIJ3eivXaarglvJH6HoeQyi6YuiwWhavw7OFi9JT1dHapyND0muiSDyK8WeN0CZ+9r
8em3U31jIZUpbOLmfHN5L1M9FFt0+uMlE+ShIpApv+6bQjigOMfVvK3do5IBVonr/cJLfcp037af
2eJC72XVf+bGOj1AbjvgFm0RW55M05fKgDB8YK9D0ildtFn4Y1CSOfluD160HEnZKgVSe+2WmJaL
Yqk9OPxJl+Mp+25ACxD7/FbV3rCuvdpV77rMIIb6HclUdk7JffIbwUx8gBJ+9R7WFQeyaPM71lSl
E+3xVcY8TfAsxraQs4wOATgkx+QeaFIApWrEMgi6pTO+Lj6F7UGejTq8WaZbXqy/SXy0uzcGfysH
GJRWYfBcsf4tOzRMfI9cXIeIVJRPDbp5/jyZparuV7MaA7KEjpYfxC0P1odSypbyXVhHYWCmxC/O
aV5Cxkzj0tmnZEovtRvrIxcog8PckpklaxNWYE+u4smNawYFVcdArJoYE8F+ETRyjqsFIgkXZ37a
9X+voNEv5pD6cYYkXVAB7OZHmuSzxyU+JhuEjn+nVqMtnhodE0bmn1UosWeUGNo5QyxmDBQ8xCyc
3kovMBU2GVPng7H7ZEv1KBHs3atMQ5luI2wRuE0VZphmP0jlMQqh9w8AeWev4kU2Q2LOIJF39v21
HcxfQUnTePM49X5kXWOt7lTd08RIM8vE7PeGBpy37iXUp7cJXAt3+IRZF+zaQYMrLf+Yavmt8mFl
2NrcnP6K2BbXyqZBUT4W5NmkQq/kcVj0difhkBK6toyRlyQM59ZPf/m/fY14r4XxDMcOPbXUspDy
i+lr25Zsh5JZc4zVaK+HgTjvNDGAhGC9sCa3ehLl8Nm1vBO/UKR4l2KxmqVfl1Iah2RFvwS9T84X
vdQAxqZ0ayk+9R24h3NrDlT2BDCjh7xgsjrsww0GyhSxSoaNCMdX8Yg8z3ab6A44Ezj8HQtqBm/8
iCkG0EeuH3wzb840euNRle6cDwHgDxCl2B65J+X4fSwJZEeDQEFb8vL3PZvBktDfEaWj0zaEC9Ge
W0NnhNu0seZJOgp1N2NCFDjpAJ9IxkhUXKNnvI7UBO7xauVJh/DPJ97lmaw7DiICuRbBExIDp24v
IBlTYdnUMIx4SC6doXaJsMyQS13T2dADjm5VZ+4+Nl2OfSunqJBabqZ63R8ijG1iNTH+qq9RuEGn
nGxlCUGdXqiqyxRu5Z8+4UhUVoUPjFAH3JxC/0ccqqEYfOeHS+OykJDeDkQaIsYaG8sM0tDEYYUa
kjTdW94xRRI1FsXf7uaB4z1Sw4KKrnjh1NH2/ABP+Ge+4haXIaMZOjA/TtWisvTWQaiDkY2l14ZJ
U6/GpBlsOC9ubYCWsqCF1um839Lc0SV2260U8R1wyvxIyHVctzf5XBZi6qhjYWQc0sCrV9AloSMG
qZ4mSj09NbjsKTJ+oZeNzKuC1f1QaPeWl7Qkx+b1/u5uBl6IoHXUDIlQV/vF+tOfI5336B8R4ylQ
IlDJyyL1rodu+CI3gbXyDvcp5r+CkwHZ/o6Te1AZQLC+QwSr0jfPMJzfgQfuz+Z2L8gp3y9fyV4H
q84M0ezBa0Hf8/yIJDN59wyuia4tsD7j8Lpx9fiaFhJyBlBi+mRSW/VcvdWlHu1/POQe2CZxkqMJ
s2GWcj1L2VRIt05U2ayrM2Fg5edm9cX0l0cDt9EjFLHEgK1J7MXQ0/0pgg1qDz1s4EYfBTuTtp5k
yUKITdweHjbNe8PiTemZFa8FX/x+2/NdEgpfQbhFnzo4T9trWvn5oUCsutNqKwXlD7f7Fhq2kwtx
acV7M4Iut7NoK7AAzWTquMAL/m4zzABTDvF+EJDg8EsWtUzCPLUeufiqZqB1FVmb86N1N8lyNouY
HVNW6fZXnV6qpkDX6Ta61TPET6pSIJ98DRweoJ75fuumgOIvnXDKZnb6Az7CwqNriBOcfmok1lF1
bLO/nS9GzO7kG9cgjhBeSwnojexAv+/voyzBbg5ltjUd/gI0q6CiTMV7vxPS8m08iCPrw5cLnGGm
dVsmnWBK+KgWju25Kad8HBxPBQkjYtz5Tc2OUpHYxg3DC6vLOn/jLjUsW6nDMikMwNRRVp7FFQM6
IpQtKZP3ni1TPX37PbLi1oAr/NU1M6o7rlpNU+m8hKXr/9N16hcslHdP/tnvJxPsOKXuqr7Y3Y9B
AUf0Iq5cxtB7vvivf0muSC93PIys3VTdFgoCACHTcjXMSWMR2UI8J4z6NP93awuzjh6sUF4EAFW3
qtL/lw2tmIc+M3YqSAsVKPNl9CUyb6TWjND8HnyUEUKIsn06WA8uA1N/ZrJsTpQnppzOP5NfvmyL
T8mTe3GL45i3kKm+z+4tC4gTYhM5qIQPWrVIP0gQHwi7nc/wnmYKgkPoQ9JQK80ZiBv+oWKA/L9b
QVG8qDMyHu7YlZ4W5i0O0k8h5wYtS/sMeVhEoOEFsKpanGF1HNwBauPh1HIr1TlzjzDh+7RI0HNb
Tz3kFJYeO6kwbWdHZlheJLT984cVR//MfpZBHl9mBN3jOQ+A+OKj24ZgoMuDY2RD15XzNi+pS6V/
wzF3WvYVJmVav2h+Td6obH5FD4YxTXqm6YBce268GQ+Guz80kjXHMKoQlU+njj4ik0c3SYBQ+eyE
8phGv6hyW37Z1/jg2zZ+hJm8p1WI67pVVrCQG/3e95MVISGYpVuN+nkP+eZ2d8h4aKEPke+l6i/a
tSwssTQJxDc90kLYIcCts135zgSeuEgt1B26GSP3OQYW5zq3n02v0P9Y1kcuErPDoqaCwZw9YzdO
AYr2yFtce9/PJGN39SWpl/zWpsS4mycLa4gk+H7pbdjs78N1FiJy30o3jUoF4E5GOdtVzrVGXwHr
kAOh4o07zIRjUWhp7W4nDluUCbSsJaSngvAyUe0NnqlYp9mh1lrIsUtxdQvcVOqvXVblV0zcE58y
EKLT9B5CsmTQPIfY/RWnmjvt8Cq+S6miTJYx71U7FwAnh2tLj0RjowCHQxi6Gc/pzeq0REuwv1Fk
n37ImYzsNJZEoq+BSNj93ipfEau+sqgQ8fY3DpIO1wxcIcXduReXpBYTbr1YDgS1xBZVVjbW4OxD
DdIlYezUvVTNwWeI+jCDsCtv/OHQD5dUFMbLu36DQ6DGV5gWG+USs6dxujpuofUofDUbZIG+IB+d
H0ggg/284JK9K4KWe7eqTCKn+O6AvXG1V1/sEefnSxaajVd8LaRGRA6+qjvYE/mGD96ewSV5bEWl
kE56R1gWE8TqLBoHT7J+t9XuGhOIgT/GhYlwvpjK5MeanF8j4jcnXV3E6k4CAiAri0CfuahprrPs
3Yk4aKossqitF4jVkB2CpjZLyKR4zPvsGvC+IJ/Gsd1vlxRtkPmEIj7b3iEMoxamXrOyETewbDwm
9L/wTQ1ZA7TY6wp1x+4id/UtU7ItXqEWMfMldkdBdmE/Y/s+lUClFQswchVK3tbmzcluayCzJou9
+6ioZHyoGiWF7HI67MlnkYBL9fpKMzrdKKSbvjgaQQd22jRb8KOEbwjMOQK5lGKjQ4ytiKYjrCKK
/vcBNjvzX7Vmhe2Z5u/RPG13BC6rnpgs80wDxovh/y/kq7oFbH6BMoYgQnqn342w4EvHolga+VLx
Xcxj57pmnBuLOjXVq/X0VBr+mdWLLMg/Q287L+iWLVSfiP/YoeJULT02Y1ebW9Fd+VorCPe8Hv6b
K3IX+ERCEAyyCVDV8vkBs8GDAeWWdHnicR9PwWeAQlFI6cz4esyV+RQgxci+81FfqyIH19XFX2ri
sHgnQ5rYS10czi0XXBeOdmVmdYmsW+kqL3wwZAeU4SI30cOKNCSVDKVoj/RrH3EoU5aurFn9VTWe
ft3rSnVu+Yeeqv8/6EiG1CvHdjEhJebdb3T9cH+jSN8oAzFLlg4pd0m/6lN58YLsH6w9CaLrkl2x
egMzEyr4Y/V6gG/UMk+0h3kQGbNAc/NOed6Acc6RxT1/K/XmZEU2vkBuDJOwlN0D82zP1CNk5bGz
Z2VjUK1KG3Z2KXL9F8XWaP3oXjp2Gu2icgG4JKqHzKg8S+oTob7trP5EPW9DcCEULM3oFeOXT1hc
yx6enZbBx9lKipuqmGEDygXO1zFzXVy/eNbU1IC7kXpWoPdafb8/Wt0V2STbBGB9qCyyeGsol0QW
3TcFmLtP8j2Ri1Ja1KQqm+C66Oh1SxSjOHYIM3Qdqj7g/yaD1nxA3bE3I5uM0c1fLgVhlpKKxZ/D
8oMV1b+MR3DTXY2LV37H5AGPaPKiML7kQTMgLqccLuqmuymGj3cexrv9dOI+NYZhQmZrMZ6U+3dX
IgjywavgpMpa70MJcSI5xRNWSDNa2IvXv2+U9tLYw+/lO0QnYa3Q56tnAPlR/AlTAwXDgB3uatvK
QpIQAky/K+JjPCwqkP0vI2OU+Kw/0L7OAgo2X/BLk1huMfPokJ4q7R2O9KKXc8H7qcQ9gCP89n7Q
Ze2aDXLcZoOiXxP3Ve6I2qy6UWnJpF0vd7QR0UE0Mzq6Uw0EHl1I+CJbbNx8ILKUiW28zgEvBBlo
AVPDmMpIPWA2HOUtAusoUq5oA7EgLfqs+vEWkNKIzE5tL/csu8WxYZrNeBC56fYT/VF6lLupnsi6
9LiVnjm5uuiXLDgrB2EWeWa1entRPakk2Z8VsSOUDpwXLOPblVwCpZ0t2avYxhMBWT1ZZ/BSSBYQ
BOoL1ybJGqahr+8z8yuh6dDGmBdvde3Hkz9sszMIlTg4zIFYCfk4WPyVknSBBTGOlwB1JmXjuwUZ
lOGH7z99nalX47gn0Um60ZzVpHM3z+u8kR9zlXm9ltS4kJgl/3O8OJYwdlz+F7tKJMHn4uaFPXzk
gi53B7rD7hvlHgwIxmtz9r1M76ZHxMKjBIXDksL6rtVhR+64YICWyvawu/+JPei3S17C3vAzymfY
W6udmrb512WD7TPHJTF9ilVCVkhDHP28XcLlmlRqJXUx5SaUvjKGbguPRv6FHppodBZZOLKDMQWS
LadWBlJSVPy/UEudm2WLZQJQyifhGtuNOgIFeJvEeC00JFGqcEqYVLy9PJTP4qfTVjv7ClgCSqoS
bp1jWfKW4ptsTDdUxLeMSEntcM6Jbaa2wY8Yw/deXelFSx7CpgYoM+C8SpRw8K8OJL7vuc2YZrQN
y7XgV7v4YnQhkplyloD78v0NVZ/xH66JNlrUV9uvfRMxamRoLCK4nUPZyco+1VCyq7y6CIR6gYrF
B5Ldox2ZF3m0RkhXm5wyESJ5w/74rwMyVqcdyCijNbIyaE1g1O7hSRsaMOENuC36+0jPtS/IsVix
Nosxb9Gp/wGu/M1jUbgk8BLCRoT6eYKYuC0GnsJhRJdtKDjnBsoOpC2ETT3NsB17MtgCsiXMocDX
A/SqqyK20kY/fr81fWuaDa8szzBjl1ZQrIGWOFnVsKN5PMgHdO1ottkEadDW8KlDl18FOvYncsgc
tFkq3AKWyTyC1fXeL3Lbo6uY6kkUDgxDBvUPfC1+gPi+JM0hdAzXkhRKf/xfcMkin7V34OnNlNlH
v1IyPGI9C1R2TcPtr1bKkYrodWykO7/Bn4nRKX3RitTwaq+kMeiRHR2xKxlYgyvkYdJ8P3OK/foP
cGF+6/dVBVcKpm5Q3ksYJu8R54BIb2fhSFxE39dSc+FSZtQlmdLAaR0T7rlftR/iPhCnMdGZQAUb
A0sS+t7plBDq7FPoO/GMnJ9CfAs67LNIdyzsxRJyRqLZcDKHmm9YDHXFgjn9n/XDfC/DTAKuZAey
e5f3OdtveRgs7J6MR/5OXgMLU8xTsBK4Vt1kSW2/Mk/lWCTIfJ+qMoyWgV+xXSkN38LeoWUsND/H
rD2Ddu9c0/+5PTtjTysQ6kisMpnDGGR8zOZWb/mwltpoXDY57j3n6gw9yu7a5y72Iwee9MlqV4vd
JQ9JsgI1Z1Q1IDqMRNmH828N+hDG7kZorQCDgHfBhgYR86AMoIfwuJOLYNQ6V1TtNddz6u5R3DtF
dIZxNYDTxC3wXkXwSeR674HWX0ozSenJj4+MTU4YQITaxa5j4cZUpg2bVwISZzObGTFjdxxY+im/
zznmJh1WuNtVf+OqSFOqRz8n26HdUSrzHQDtg+bj5o4HexoUMvRZK5S7bycUvQmOWeIQRZlxXp8F
8TzfeQL/ac91EgU8Mj9aeLlJ/cjf9bmHwzeYdItwSvkVP1jEMTTAlvDKizQmkVQFgpdG9An5R6Cd
1Y+LlU0fquEER+OmP4bCFawrTML5GiE6i0vDbIVUZqiqf8TW6lTwLJXPlyZtqxye9lvlixdGZYDn
vqpvWy6n3/UNunA+7DxmJPzQrIDoGRNLpGI+0buKKNV/tGI2+JORs1mIJO6H7NvNkYgVoTB794W9
nnwGmthOpHWmWQJu0HePQXEDxWLAzTuG5CkJgAxQhbrv5r0Se8thsVTDekjtJqaCqrTzEmVC/wIH
yT4cQjINBoZutEHUneHqorvrEGi/ZOS6Ho3UrTU0MDgNhhDQm4tl8ZnjOka+eLpiFM5XPUVdEpKN
eFUh1AdVusPmKEYbLU0TA3HEOEXlqzL1cxEY8sb9KiuI1KciZfCFCnj2CAEY3hcwQ1LEpG/1r+C8
XT0mgIBKJk2A41EZDZ0TKK/qPZw+5tSSqt3g2veRuWY933Dc3DqJzDQF8Ic0GzFIRMGE23a6qrvG
x/pRz2EdJlcPAtXtbE2Gsm85jyX5Pf5nPgl9tp8Bzuo6jSJOIFjsqoO510AO8fmVADdd/p/1DPU6
JXdUOvzC3coBAXQalsszXQFrd9nEyIYaFSRfAimW4dnrDCZSrmk2hHXAiW1YY7rcItUG45hmBmsa
2HhwicuQqk0fEeI7S7FezuGrKt77SfZmZmTnNMhgKv4RbgVWLgdcG4aftA7NdcSiTnMTa71zIoN1
iVOTUWhfznSX4JfxhqziVlgUruee/c/pkAuRH58+MxwKHCP5rVhgQNdZaF7bWPvtL+CxVWWnh3uT
46nJGekkNsVSKtPT2u30lOf5k9E3gRmFBrjykIl9ZCzWa/1sjERHsQ6ZBAU3GruMQj9aoJNn/aNb
kJfGqQVivKk6L4ck21x39UI2QFKf9rcpFWv97hVhQeGZm5WHL+DspKXUb9FZl+O0lBHytcu3u28u
aL8RYPfDucRdbp82AhIr80wN5DKiwutLFKobYZO4tYQwsguv4djDJZaBxrGZ8JMf4qwiZdgNWKRU
toSbZcGSC5jlGP6qzQRAnGXT83c3EWd1b4qeidbL5egHXuxiqqbitWT9Z/QUWumt3MlO/lqGehzB
Dwq1lKrea3/xm/A+eBL7N9MqZQ54f2bQq9OxRrlzpD9fauvRVDmKP03vLGD9tm02IzYzYNd5/dss
9lj8RrPD8v4OEWHOr1IwIqzQcUbDH/A7Wp1xLExPNZMLyVZxxyJlZnnWdDKXPjphRnDgtmTFZOd0
4LScXwDfKE5nCo7nMUgpeFE/KoLhy+Kj73BK1DAfdcJP+/NDnPwKZXQHWj/CAQ0hp5vhtfzja6Qb
VKpK5qc+OxrHSQwRkpB6XRYdzUj4tYbkLWR0TKm/f+23+S3LMuRVbhXdpdKKglhXI+kEDHUQwUIN
zVv6fSwq9BQmLebdjj54bxgF3r88lBCJL+dpZsRTqxMifnK9w2/Ik+DrXDhe3m6nhnbFQQVnfuD+
8tbi1VniecxSrQiN1LT/9QWONP90ik49i4oj9Be20lOK0QEMUof6Lz7TIf3aqKUkEwg0txtm2tk+
iGzvpBDNBauCmsW11LHxbyd594KwAUfuipJhmzZU+mwDg4S7NpoBS1Eb5Oof2ZgcFLb3yY7nyOBL
NTYN8BTkXWXPxyAjCGktIOjqk6Cb4FFC+LeMC50Yq3O1FvAm7LYaJPc1CBNckOuTxshZRMXwPOij
fgKH+T130ayJZjRBaRJl83O0WNMHi0UpShkt3bnUnVFS0CNl9K/pTrKC+VHVZsKkPJAnw32OE3LQ
6BEJ4pVKg+rWM9Tl3d6nQNLM6r3UWnNknS1EttydVwy9TvOXHyAvwYuC7UdKtg3E1ykyBTbNzI9G
zgb3B0XUr9fV/LnfWCWwtY8Gs3BIAEnPTw3vxJGGUQdHfOFlwZHWarREEdNP81J60Y+SICHY83VY
7E/SwjQR+rPAfGu40qXhYJV5VwqlsukhMXVT5llmGaVi/QytgA6vT059PwSAY2cq+j3QI+CIhtT8
j99ymtVfVVbn0s3F/Ts6dzB+CRgz3MlgDvXwngMZBXEuO1DNTBt8Y+5cttXZ66VsKUltEPCgNlU9
G78bnKu7x2QI5FPSNNv7IGiVtU8b3HI6kyOyYXfvYUp1+UJOLHMvc75iqJhD51NygZerEAmLEJf5
AMz/hWEHMp2s8aKTTPhbU48mSkbWdNneG+qOQ20ncom2a1bJ1QKzAnn9FQhIoXwdXGR/UqwC9D75
yfCWagmmE8awf02xR3+yYgVvDjUzF6IAyBL2fYQ6IF6MapPPQiUNEtQcjMWdjh2CLSltOEJbSwwI
Nijygt+rWAFnZGiekgmz+2BFl12lsbFs7UjRtGrGIVqFPYkwIQAr4eJ49qSIr46YLQLHXkCodrqB
SKVk04rab+m8K8Et+HQUkulNnApqezADZMJVtw76YqQP7oRXyIlrXqf2KHJF6l2Oc+E68JG7pdbR
DJWdRJGGimiDffvmGaUBlMwLYr28zCwjWmgk2YU5jNeB7nCLHwCgplhrx7iHxKkW/1ImImJX7S0A
Q2ooSqQrzIkncenme/uOd0it03exD3QrfI8mT1UYlf5E68+10VgbyDJ6JUJleJNpGwdh8/Xaeh7V
7f8XhzMzIfLDQ1dAW0T7MfJ4civnvWBG8GsotOVutQ8wWkbG3QiRG4lxzoEy5r0NKAsdcYRgRvut
C9kJ4vx4ofqcJNy8cn3+wYMtyIDEWbxQOvp0Zh7OyPS2k3dHTjuaj5AC0POMsNgO3jpQYwmizuC2
adkVXquWFEzRmN38acPq5drZ8LVNWKooqUCTn7LcR+AwVZj0XblPovSan1ss7siTfi4BxawvW1Wz
LEo42cpDXOKZq9uU/FAWvfLT7xSWfnmL0o5Gz2IJoFLo+HMokd8Ho9t1FwsnkZ6s6eCVhNm5z2//
Do3LrBrVJ/3XbORYxFrXQa4oCuKy0wFYDOf+2BN5TP9QWQzivZjW5WYe+oXBhWR5tLIef+u8Xjqr
Ehn3t0qhaKs94wfdkOFoX/YARqzCaJmiA42Mkr4N5qWUwqLFTR1WFgZmrKJlKKmRV5myPlRs/10b
rHriFWRIcqddwRzZjVuiMTVehEQIDYLdY/gjQJR7K7VVcRyvLNVHrbD1UILCZr/m3pjUow2UKE+a
NRb39mzxlN0jzLC+Jn1MQKQedvjSy01xCCdleCfnB4aECTSi+QkrnBQ7jwu+wbqAjzGDZLwx3XXg
hIpfGsfEOMLRMbzNzDVbhXOzmjeVL32bp2VWIGrRcUuVfFt1kJx5EW1AGNVaqBaa2UUES0NndAvj
vNhV6lQZ3t42PEYHTc045qaDiiFFqd89fAKdtJm/fbvGJxMTlgwcHddcozULZ2lwyI9XHmQcFRVH
dyvvngoKrkJXH4qTIjJ7/XQ6OUJzVD7lMDFbLIH08dWdl5m1Rg6Q0AKI9kX0cGMduxuPYgi6z+XR
cs8YW2NQcXlhYW58o9jdtNpf/f9RMks6+BT3oAds4/CW12ZaYfrXnJBy3PCm6TdlhiOM5DhnfASw
EMjLXfzQR6GFf/eq6Utd4CxMVnCNeH8GrG0DZo1JFiNCxt32/NNQJ1JSsEtXFKLAw9ZOJ4vk6Fwx
jKVFFL26z84OZZCqfAPOBMmH34E7fRB6EPDgyBXKEoWDEE6CkbrIde+h+45nALf126efA7GktewV
XbrWnO21GEzq0ef7Ymrd7iUL8jk3IjPFMkL/kxaJ+kmTDrSp11O6Fho69cbHLaeeT/bV4Raf4CaO
nJxXpYihAGq4B6NbCDn2zSsuRM/MM8ogj4IIuH3iDZ2cXlrpKNU7YHBVXk16OnMEr2ZYcaSUjWxU
rqe09Xf3OyYC9/p+50e48g2SkBLYanPe8bJgV6GupyCzm4rZqBvppg8zbymsx1tKUX3lpp4HL+7k
bjVjtiodUVEY/zcyfn649RpOUqCIV2ibW7K5ZvQ+zetEexptWzgvbL7T3YzS1rbEWcx2KYgEDJd3
UpkMZ2xVOjJy+Chbjy7+Ru2kWOKGit33eGyOGXFYFtIc/NwjujFHL1iXUrFm5vhBDeCouBXAJ+zO
siFadhLgPMav0cIVLQ6Qjprd9nqpGOUfUHiEWjtN7K6jUKOnmPjlQZMiRqMPNXqPLmrcX3yOfnUO
++pMdZqKX7WNh93a8Q+p403lYDJrrWTkGCIP0CtQVmjJC7nnrkq4M3ZH6e3QkiJbErVHiCbimMvg
eMBSSdwwyJSJRBa924HcY6mue4Av7o1z+gYeE7UpXPot3+oRaMpOQ/CAVLl0gnxNoThuK/RW1C54
97M2LC3vCsApiYqjUvUbzM8K5c5jG2PDTIZg/7W+ghi5itNY7hd4EoatUBsEpDEGA/iSOT1wDLd3
RQlqZRgvNV0aIdf58IoRgjGUjkJLWNwwM337KBgHfMipTkYmQSEQjfft4hTnrzTTMfwDaDc9G/2e
PQTZlSE/5miws1pRmHbAE+QW3f/sWWpDlMYhmoOrZ04PKS39AiK1YaVOhkuGzhuqcHdbQzgA6tWu
VPHn0m1FpPINwzFu+iKaHDYnz0K9P4gSMXlShefjniA8Kru95oaogbYFhpSbwsGjdfzj2Qn4tZy9
sOsM8e21POdu/r5Zvr08TLdfi/YtPmsEl9lwWzUNeVrVuCA8BLGZYEFbyW7IvBUbKBdOZMgiN8RC
xF3t4zF2it1xg9SO5hI/wmTGjv2OVwkHjtNlYs1/9I/luvvRZxcVzA4RNqsteCga13FKPECbB771
PgG9gqvJQRUs7+4EvoOHvf9MLCWpFocIgDvSl/cUMj+np0f0bKtnEkGkvMKXF8DH0q0wDrEPZ9ob
+IfFUb0Qtt309gIU7cL8wKdfQfmr/+Vnr1Ii/vuy98dXg99mDvT+0yDGeOoZcplqIEkFqZVYrl7O
MmAWEKCzr2qG1+xh16BKi6fzMd0MQ2hOZcJueCOgtFFP/RxbFBFJcaDjWoI4F/R5hca6ihK4jfQ0
LW75CWvnfV69ZGCdDmUe4RX5chB2cKn920xBK3eO4xkE4MLZ9AahxaJGvC66LOZatkApPU08NZIJ
XMFtzrp22iP282f9WpsXJIe9kjU+tzz08jRqhbZZ79jAKvK5o97EZOO8H0o21u6fU0y+Btr7KAJa
Ht70izRv0/PlRa/KO+hcHsCBcVhlewDIviJIfcy4+spV2sp/r5NziFhuxYFbycZOwDZas4w5MtbP
yVHtoOZPjehZaqsf9MvcH7DnzVG1C+4oSlwARkGCfUMldn/lC83zLuyl+GTphljtIiYH2tHaYm2Z
xLApE/Bi7n1o0V3pq5/HwXMtKdn1Ye/IDODVlyxqEym68vjUeSZJmvFz1iK+M4fK2VYf7aefiv0h
WzoNNo5oAeJomcc9kWGjNiLQ0QvVhFVzdgPdQmetoYxfLBwk4psaLvyNTKsfWZtGlXXEsq4P8brB
5Lf4QiY/Z1QsyzIIu7BwWGVjwxSxwrCc97/MssKNjt8HvK8s1+geQbQzF5olLxDjEWBiy2H7ybI9
MwkeIX21KZeFybGQMeDHgWuLiJFOlYnajdLniDR2TrQhYdZgjoS5yCDhB4Ri7lJv6Mdy3IvXfdfQ
nwt9mM6VQA+iOvQu9zZBuJ//j7bJSImIlo0McETtLnflEDN7oo0/JJA/PllL8cXd3wZkFfJBY2wV
+ZMlxSegEz9msWNt3Hg7VagIF5apQF52q4rCQktyxI3gpte2FEvv6rm2zPRGUpDjX3QjaiuZEGhQ
U848/HfWQbGHKP+J6lvrFcm4QHHdgGcm3R5verXzJ68bVYe3fegLDgoExovSoT5FVnF47/5E/vE9
UsY4lTwQ2laIF27iAYrb3CfSkQIy9FR0IIRNnbRma+AdqHIYwWcBmoq4TKfxEJzf52fdf8hCIgEc
7K5q+YhucMeYHoxa53OR7TfN1c1NxvLb5Fx1mg1db8oS2e6Mv4lr+NS5EZjWi0GEX34PH2YOT2sk
n59ZcJS6pILJaWrzd1onJEpI20osVxooVdk03Dgg+zzvkAxQcafRKObJtraWVPm2bw3sEICKseIv
pOW2gqG2f2SnlOVlIIaJo33tfmIknr58NbrRXqdXkyCqoI8B/0FlxpwFqN3FgTjz66GIsNaAq1yE
w375KV5inuMr8db72VOHnTbHSwyL8vCW7fHBAiaRrBRZdCSHeChsYMG/0Rqec68iISXTAh1UF2lw
m7vK1536JVUVTzhugJJsGmFbBblPidYRgHUstY5s+WEQhV0w68vFlbSq2YxuShEnHghcFqE5aRWb
OpednCc3DBw6MFkNVJKdgZwDqNAlwgiCWRB58gQ2NxKV87Spyv67QJIALh4czdC4AqzuPGP3PKYc
eYiU6g1dDBV3Q1X3fYYXinJG8XiOT0zkfSOyGgPH5z0NBpqdHvsZ4HR8BgvBu0OhJS4erPSnL+e6
CiYxsKUhs8WU8s6cS6JYMZhk4GzBNVZz7ZBymZz7SbBGkdwNyLDEEwP3kSZQFrQdMNdg/2QGOq0P
FUtja53C6UxGiV1q55fG+bon3Lext4mEpCeeARtQOWPMR0QCIkBP5OlsUsymGaxl35D3HY2d/u/8
1FvbSE9WG4x4SNqa4cpuuMftzTjqd1go3bt2T9fQNn1a26+YuIPsK+Bl7lSs6TiTR9xKL9yQezGz
kVPKNmd6Jf2nlnQE2aTf/iO3JBoEgSH/Xsj/9fp1i/N7E95rw90jiCZotzxkGQeo24R+kAeogslR
FWrLLDwMvv7KY5QEx0B2CX6ovftsLOPfn7JyNWacBjIAgzdVurDjJLGdTC/v2UKk84tIMNnACjkL
OOkS9aX0LKZzwIrRzFTq+I7YfI78pUpB0olYRfQoiJ8gAF/rcBOb3+VmRERox7g7XK2uV/6mH5Y+
RZMsq6qkm76VRtxTtnzi7yiLP4wzZOtzEfGNRqGy344Jpdkh76xLbmpjNtlswkf/YeU4cScLFKOT
UTKSUqpjCniyO+4p5k1QSg+6KMd0xn8NHnM/MNCV+yARcD1qSruuHTlOdz5wfTZvhDmimG9ZgpkK
/Sp1YqhbCfi6tI/CuI+G+u7baeu/RW3ah5tO4hsNA8pyEP9uwujUN8oYalMkKmEewedHekDX90kD
O/+o3RNtYThFStcimI0wNInabaL8/rVQlGSGHMgToxmrur4lYmjqoPJOXP0RJsN4748nr1ht1wOM
dO9KNGw1bDjJar0BHkq4w3NbOpVvZJHI4rCL2HhOO1RpSYF9dyL9c1lz/Y8LN0vK0/nkXzfJfN8H
2rk7BWWblIvanMmE1i7xIc3OfsRNwFHOQbjwW48P+3eAxsNxfVbkwTeXWGTtROtFNXqu9fQNJALb
LTgqKUZmHhwE3BcoAtJAcjSxl8iVmYhe5XKisci+cWRMmYr4IPeD6XrD0VQyRmI3/hUbhN75/dPQ
xjN4qBrNHGEZTdi6R2cRtuTCH+rwU2JGlZZJJ1U0zkpsf/j3p7erDYT4xz2erlDUDdXnL43RoBwF
XWfgtz/jtlKTY1YSoDH7+EoP+W7sMbV2pgkvojzNbosFLewZPeRync3fbjqi0vlbMDeT46lHnuOH
Bz0ASJFbdgmYdxTM3d804pMSjGNZ823cbvIN9CHjErQRYih43iDgOHOcMpQoINKyBre8LRPz3fsM
6zOav5AsX2LRuu+/YruRYR4jD/z/dsZmcWxRx9zcR8EWR8jI6fRx0Y8PxnkUZeePpAGZY/YKl/CR
mAmnXhBKM9djsfepZ+vX8fvLsB7dM4a9Q9YlkCGr8XaQOv8yGUKFl5p2D/0abM/ogNtYsOcyGzFc
w6XqnkyDQwvLYAZCkCpO8+BhOTbQMaS6gYojivrTZ45AYvcjn99ZxSfE4HXuzVRXTLsMgLXRmhnB
SqpKxWbz/ucOZK/4++yjpd4/pvzvmN1Br2v4Wp9QZwWb1dOWoUMjmM5jPRNyMbhng7Hyp9I9GPVy
2YtrCnPiFdyK3TtqB/ZnLm6K3WSVxD5gP1PFIcpJMdQT52C0kxbAj9YzhmAp8CbSJzmwmBpHLBkr
iv1uCRr8XUS6g1/o7d0OpBqxm+wCKvlm6eZ07CK9Bnt87Xf8u744Y3h0Yra75jE6u60Sa9qxLAZz
QCsob+2IFZwxwabRJSGUhcjYQw0VrJZsmkGLTStuL2QAynqUenY9s7GCJQGwmh7KfI9SHci9goOD
PTmai/3t9rWEkVZcamPczoEkBONmkDNoFWx/OC3ZjIxeZ6ZkrEQ8UHghqExEL0BqfaEQSns+Zybw
5V0JYzxO8gDjATw1oH2PF4tqfxyw7D04HC8JqkAvt91wbDZN+POFj5m9MmPwuIRHlYc4uCwFXHOI
0bDHOxe4rb5KZH4Vi1Br1g5UR+qYM4xOkEdOiiCvTudsQ4gYE4+VwhzyUwZr1d+8zupHwNmqwEIi
fkRlT+wjPBKranA8+7eqfOvd+xvG1aJKlJsoaPv+Quzv+YufPVAVaLU2xmScoGCKQM74wU8zdJZG
6Ux0sjw4i/AaOtoL6S/EyaZ0HUdD0DBEFbtSUu9MF7Dq4q/zrzdpKIGa5QGFFnsWHKniIgLp0wzx
H7rmQGaL/0HML9BcSOe2qUXHKAAsGxG3fnA7A7NUogglP3GxnAGVUnk/2hr288Rauqm8K8uJjt9l
VeoCPtuGfUtinBy27uSAaJFbcGXPW0Pj/V5UWZ4xSWooBdZOrJsd/VMruw4Kvtt6cdyK2r8+f/6q
LFDmkSFinBmECk/44ZUvK3JlOkybqoh9aSLhqhBtxj2UY1Zlx0cEPjSmGdjhJgHuFLU8JxzcmImn
NBHfvju3/iEvvhqMrCTRpo+fwBfTO80Ja0ZkkvPyJ6LCv1G1+rEt2EMuyi0/IW20RAoNwLmKj57K
xRNx34f7fsmDzhgkDWjmjXxZL/vch+EYioWpGn77zmcaUIsExPzA9oXOb6Y0OtSNfEEryRxY5MpV
tjjhVqtu3pz7T070aXwByBKJA3pCkjmmMUtbDTvRhJEsb/a0Lpcs8dYZJZkEkG+HhVswAMqI/+rP
C3tKBTo8cprlQjhyVGfRNH/xIHpP2qHH7aJphC5rI/7fjIOQKYpMLcnrfcXcDLEvxnb8wPSIQ8DT
4cuUfCqHcTclgqg8WqHMCnbvjc8SOVEJk/pevUKrhkpgjUHu8HwYxaF744pAcnbjkvd9K97Y7Y0e
ZOMjuAYM2QCgbNUuhUxoW0N6IauhRbzU9ei2Vs1lZiNWEhAHjh1uZLq4+D6MjhB+SLmVDoHO3HqA
jcJ5SRaiSeaBFhQEx1KWWZN/ip725JwCNs2iYyL+jfpSPuifoCFtTb12HUZf0CqHvdYfixeQs3EQ
11j4GHLyRfI08q0kkzkKry41NRKPAU2LLYR3M7mUQ/uRmZrLM7YL6nORZUdTg2FgefEYOEekJOGM
4z3czWjmadIe9E5DrIfMjlsOFgZXJnG8x5se8P553j3keRbW89H1SsK2eZBwh/ZjZsuAg9pIzEIb
seZHb2OIWBRXgsCF4XQx+pUJpinxZoUGOBb0rclw1yBMSzGKkqOs0NEKsXCV7Xk3w0/m+7EEyk56
Q+HxYWtNE2XgfhADqF4YRzaWt7XRmIKU7moNjhskpFMxqOqHvwm9/lXgF7bkBik2De3I/s1e3IjC
gNQc80qpfDNpAcsVsDUrUlF0yXEU0BJF2pw5lIepY4L7550W1zSWgWaiuOEQykfXNSYdvYgcs8iI
xc/Nju6mYmhs7FsxvMp68dUavQSVc5/OEZADd6dlOFvbD4JxvlF+UNU549/hV6BxBgESb52tTngt
TGC/9LIIwzAezudAs5T1YIlRnpb4k9SI0nQEMmMcOOe4id301pZS22LiRXnA1rPgN5GD/g3LX3fQ
wZ8GdgFjCc6TehAyIc6Gw3gsbmlwps0vyD+EFDTfowI9k9p4MCXRpF+TTcPt/JTvrugQJ3xMJpOy
enIcgAr289rIEBSsnr2Le4tTSAsZIkWqikKgXOwpLGT+fMQn4sm7bfmzrQT78ezgXlEPlQurNpSx
/ojf2LlX6TAjj9EMg9ifqMbDWVNpVlJz00xrzKdIGpoBgTZs7YZB69/pD5Zlm70umBvglU25s87M
NLFQgqUd3QB2zxlkHAMoqWBEOzdN3KTeWHqV8iYde24QzT6cuf0CVwMXd0AEOdZ8TC8n2YWZBINO
h8yE/fJmPx5lwgrE71ps2zzsswa8HU5eqUg4YV9APKkh5kMUw3mnYiFLzDLW3daB8wZ9QsB6AR8x
TFiH/6/cjbGMsf9vEP5UUAZ0f34ZUNsKJpL6Dvpk3/qTxdLdWBcegQj7OAtpGOGwFICqFfr/OQUV
4s/gdyrytzywazzEWs/tDKsIOjb4giXtNPnan0JJlPIQry8mVW1JzAXF3EkEHvrNaeCar5VFa09D
2WckikDdJkQPsUrrvTUAqONKmjlsOyWOT1m5S1voxYzc0AAJsQ+ITXoA41JU0t8OGy2YwUdUSRZw
UWTCXAJYXmuyIOQ1uk8yOWLCM+y2/rqBj8s2+6xHmJ3qM24JKPyOfq4CoGK+nXs60/Wh/hVw2FJk
YHnmmAhDxZvNidRXGkoX+to6+DYBcZ5zny1A5SxR7kqtFvnCq5Fn/DtUzyuwSPg/HJ60aWnSMwtv
/244iihTejwfmxGPRn+Wmq0OF1uLWov6iYKYlEzKiJ0ogSrJ25do9uO+U8ivuFMlWBNpUNVjJ1Pi
00eET+nOzMogy+G2ZhZyedBD2ZgqWN2A+in+8NKXccGzeICEcH/f/b6umkcOqTD+HFOYkQ0ebZiT
4YnwQMV+u5WhpmOgmZ1CV/puGRNW0pGZmATzvRpencQgO8q08keVxFhuAVnlws0zzGBrFch7MEIf
mBNwgn8HBLJXIqQDUZ2wYt+D4gcsn9+xkeVCPvIcymOgp3X/qsMmSR6OFsHyD8L01WUxku7a7MDn
gNRyXsbgC7sAr30W5Vfya+b0I0/qIwoQfG3FM3OctMzaAeCkrPKRWoBVVFn3xt9tCIrsGhDr0Hsf
mD6XvhLgkHcw5c5R1MQj468o5746idWglr3xZe5IDm7btj/cJcvoB+pgf3OBYXkyDQCDoNL2wwqn
u17y59WcER7TbVhGL9Fd1N88EzApYxuTgfaencyEaPE2CH96g8gLwEjUD8NyGmG86r1bfczwUF+V
r3ScWOTZWbhjGWY6tfJgGZHYHNn+IH7/UFqnZQbdfDwP5z1/liJPlU3x/d4ALZOdK9jMSm4XZe/7
QdotVDuueNf1Abk8pb/L60oGVMMTrug1f8lLEZSFw3unLg3m8GPEFGy0X+D1MSnagAla+BPer/P7
eu2tVgW0uHxUWGyFu5RNIoCFZ0GNUQy0Ep+4GMwxq6kUHV40cL5yU94LAg95rw6fLnp8h4C7cYGP
79zLthlkbfym4eNH5PD5/xvUVSBqjSoWH/jbUBUiOKBhjOY6iC41BTR/0qFQy+IjwqWP8WiVQA4p
7UuT5Cw9kLJYwJF1S7j9HAQvFSZjo5NIw40hsa0EeYhlCNGYPB26kOa1NwWsj6QnitWwlCMsgWj6
41omObvZmQvQbA2DqIbHhoodoGMP7ZZszIsVwmHiE6KeMhgPqAXiO804qu8F5qqnLcdudAJ9emfj
yZRS6/gPNO4gAUM6HExKh+n9x6r/AyqTelFp6uNTr3D5N/yUhRe9PIJk/UVIwfqKh7vtliNrk9+8
hETHfBXA6DCHomnek4XlIMjnTCN2VT4pJm1PApDrVmWZIMNcDnVeOvPOVluPRPw3t6hh3pk2na3s
jrVzJBK/xrth7mHgPLMen9GasvpC7Qq7gvvGqt5ARRl5xeJbLYSZhNYWPoMUaI21ni+WH+/VUM06
INlm7v7Ew96QN59KXQ3qM2jgRq7u5pAhU061bcafFVVI01n8rmMamEjCD57qGRSU3ra43ofMn0lk
8UiLKPNrnZ9k2jjC3E7VGPB1hknqZ0r+UDNnk6JNR3CF1nQ7yB1Ps4WgeHpjjN6veVfpdTcDt0l2
Xx1XdK/keTz213ar6Gm4Z+geAC+CpGxssPlNd4OAtSRD+E49jMhYtvmdsoJT9vlfgo+CEHu7ojKC
S2uXKdvRzzZ3NesfG6q6PrJfcxSZdLeSpm7N3BSzeF2b40lAT5pUQ1PKLZOZfTZLj2+WqkEYMQHr
b2KbCCArcaf15hDyaBWeiBnTGtea+qPTxRVIo/yOtR+ZRe5nP52x4k2Cz3U4hFxl/Sm1WPqB1Jnd
lKzt6SlMbaAxxadSYF4Z8WeDyYyw/IwV63vCEy97BbKVnJ2arz0X6orC5G/kRvXhtmSooHSyQgSi
7DHZEpVSam6Z4MSneyM0i9BR9MrD5MYPCxGPzZ+Fh5rka7g42xj1VXfd72rdJUSyzux4TRXmxPA7
5amqIjtYBcdNPgSZ3m1fwUj5BkhrrhpUcTfIExvFibNwS+7rb7oLycBgu9yZF/BlY3FWPG/IAnPP
Ty5LcZQVpV6/jS7osdf3+1raL74/CPcZUuEeTqU1RhuhShn1yRz2IPP4mjD7xGLdA+Y6l5CbkFz8
FiOUqPEFkbQEnbojBoFFG/f1hpuQo8LCEAHicT5HSZVQ52IkVLJ2PSzjS2FP6NxegNOgIQ3z4xI8
NmJRdvpRV1zqTzyWSbcE+nnMDlgSIIyNMqYWXFhael3cbRM+ANjPdTYEAfH4q30IdxnUjGcnr/U7
fNSMG6apmqrAGehvoPqAErYH+6hBG0uBbgroebtdBl77IqG7SmmrEXKAGYqFv9Lo7nMvn1HP1NIz
U4o0Q3J1jry8KvA+l0pdTHRzq+wQxraj8ujzplkJhcJtt167jPSuQB/IYU01QabbWoJ83NtSQbRV
MsCheA3om0app9agwdA1dct6QAxLeF5aUzd8/drL/vZdy2U/lXVtV5uCYGwPAWXEigrA1PSBx11y
SHmtnmsGCvgLrB1uXF5ZgGna8nHkVxH+L872A06qoBxRR+cMWcTLGH1tTJ2YR/19b+4KhDS6XFb/
A3QpMCepLz3ydYw0UMcSWwSCjvwu4kZo/rKnG4Gh/RwDsmvo9zUOwDKvMR4zKwml6cTy+TmV0EzV
Sgk2bA7VMIAuGxyWTcHJ364LIyypxrVV5pJMP3RNCymrEx4av1kJwP/r5pAVUm2O/YlsiRWtVG3d
xqeJxh1UEgAcPvy4dRAYd6Vh/KVThAmXCSIlAOtZTYwEmZnOovFDifv2NQHZtJZ2wGUUIBy/HBm4
bT12LUDHmA9oGhASegLPv61DPfhZmBhUlIVQSqyyUiI8CSNEcypi5qc2SMo/LnCdKxqqd5AxcN5o
D8o3b+4ZnZ/d3hQ6R757gD3qfbywOiVbbdue68u59i3r7D10O7ihqjG8yRzbck9AgLBkCqeXE9zK
ysx+gVuGOCHUCGl8ddu4aQ3YaPka6Hm4+LPr7CQLp7FMNR8hdZFKBSQTv2tWoVkEQL6bHbpve/lo
zC0jdHFR1HqR6uj85IDWtXjnvoX/F8pbckU2a+Gwbff/ebcv1qr08jnDX7wz1Lq9bWJvXbTOUr+1
3NUMPPG+Ylf2jwYpa7llnxlETPvVCEDIk3Gyj58mUEBVVk5aZwNoPOvEaPa+xhxxm/UUpyY+4yGb
rnpD6LkLIiqisNw5UrU6FNqxBCo0gFQELUrkz+7qdUaKoXau+CUGpkBolHacXVHZKLz/aAyEs64g
bwnR0m9kUvpdSjFGg4B5+JrCdz/lHO3WnGIozf57zxcHmetzgFvxc4WigxgDQNqhKfo1KTKH4SmN
tSVt8irIFqofqSIPU4Vxa91SdwxzsWxCC2AYWjo8NMwnaXpQfzakfUaGlkpVRxoFGCTI/nshrKn8
9Ep0+UALPrrGh96FI00TPxPjAXHbiBCOdJgAb2TASnbeu6+yppxTdYlgm2OXSP2keXglhKkRcm2B
GI0JuqFuSam6V2EmFo/Yo4Yl+c4DMn2EbCybXZaT+K9g4nOirp+YuQXpF44I0g5js01ClFT+Kpvv
etdwQ5VN333kmwQ4KjuwM25vQ+mu3Bdrnds87nZoJ7vrqKZO6wRk/MJwZ/HlNcAGL81GMX3VhDpm
qP9DZL2BLpkLZ7EtNsnxVVT8SSKWDDKpPHYixJXPmeZ0l1Vk3WimNXZbiryKUZEpVt5NuLYKfQsZ
3R4mfG4B637NrDgUUECR3GSSYqLNEN29wP0Gv4wSCiIiwhU2BHZn+FtJJKC1Q9XoLzdwXA+sLvMA
5o0qmmxbiU2H0uU9ePKpAa89qfN6UPz7wfR7pd8uDi5jnzZfHSPRyzTvtyCXHsWW8hRI3actf0NC
zFXHjE4dmJhZhGYehSK1oyVI/ySXQuUQztfirYbmgN1M7gj6vIyrKbHWgF76vWeq91Mwha8eGKn0
eah/najD+b7caWzdTC9YQhbmXRDB4Ydq8/aYgmTNsl+802bAiatAnATbVg1SGqzORuEO1jtTbtUv
HI5ZnXok88EVxtlIyFQJppGvWKKrVvr6CDD5G2zaw6c7qyyl9FAaBCc4RLMyHPd8al9izxVIORTx
HFYo45L3n7tqkzOiOylXQ/XaP5fnHqM5GjWUlJuz7nDzpk0G/LDN6Fyy0yco6ZAXoEhH0DcymA29
7xJf/6xAkSympB/kYvOWqm4Y8n1eyt424bYG/cW3YTHPw7ZTURHTaJh7AV9d1QM88gPDmN5s3v7a
hrMWWDPvF3hg3FrrI9FT6iYcWT3rE9NPeJWtMjeaRg02Cux7kc34OnTTz68DdTt53cq9TPSKCN/R
fxwVXBnB1ZKyL0IniP1bRdVwD33BMFaeImNqQIC4GVHdU4Pd/1xpkdHWG5PsKuhADyqmXUVDeiD0
zY631eKQ+X+eHL6P5ERb7brGO8T7PAzPKnBsZ/ffMoybGiou9olgFeYOBWDBMnxEnVBrH8D0NQ5a
WOitpCsaUGCFerVeRf8NZK9EJuMiZbbNIup2SBOhezYBccUqDLlH/lyKXfMmKNI9nAzirSGa3tJ8
bSigxXG23gzHuaOB5Je1Yjqa09+cUp+zBUHyEsK19N+O+y0OD7faIhDgkhxCBKSgEUS53SDzgW66
pvU/q2elsG7ClnWypBNGjGE9FHI5jT3hIEIJzTXP1pBc/i8c4NkgQi8aY3u2nBau2tHh/UcxQ375
br9di86dXMLxCu15Sk2SfIbnGinq1JgNHsz0FxIOxto1FvxyM8EgmD6fPhzqp4aUs+yEsbvryAjW
4oCVUnsg/Q4UTUppcom85H/GoDebDwnPkeDBxuCrhuig9zDmfa5Wk7abA3DCv7zwjMQ47Kt+LGg2
QmkMftpSycyeyqfQYOn+EAW3YiznZWl2FyK1rGCrGyPlzVYkhtyKFAUFDa2szPrJMCcjYOM1sqyP
j2bBPFzyHBt064nfsToAPIfPNUmUl268B7OQS70GQfPZO5Uc17uJ4NrI560QtwD/zdBuYSq/0d/c
iv5wqxf8+oEJhd3SOh1oO9lFH1sJmTHxnTZRwT2ERO3dYNCbWsvuyuZDDUvZplt/wsBf7MTAoPEs
StzuW+Pe5F+CMFs+nbDdn4CUcdmQKSYRo/6SdIvtfMDFS3DP04vZeTWvoaLRYrVvME2EVA1h0e69
2wxpC+yQXamb+MUcPB/wyyg74fLNsbO6RW/UaVI+7IvKKGpd+fnMpI1lFYYjPjE8ga2ieMZMiMKg
DMkE4oNg0Uo0V4qB+rbF3ASwV1yZVCeOkHckZWN3Bz1oxsdWCylGBBJmFtoQ85IQwEMnk9bGBD8B
KckAS4fpZu9a1KXogNdWOZRvAY0wqg+VlGzb47gRf0j1u4o5vNBsZCGBR1CmmS+LfB4IMJvzhX14
kQkKsAgNdN6hBXKC0CFSTpRIzTm4fvych0Cv4W2gjes5jYv1mmqagwh1meOUWrlqtVocsH6l6M8R
z7R36CwE2wuWM7ALICZBaixhhG3a7I/SE5uauHeZnL1sCByFgdEiQNtEPscM3iC154hyKqUKVrPH
2wAqSA9XjxSu5EvjDM/67pbd6cti7ugvCpsfiBj7DajzKZv6SUEoCmnG9o+gJYlbrlv/wtsfnXRS
BCn+4twCf4Kk/9ZQWc5vsyaRRe1aQvzSC+Jz9AK9Fdm3BTG5nSxc749BobIcsyXo5gliM+T3gSzb
P7yrJJw2oWyruoL/WoHRLjOx8CFNFGA9cpqaDovjPGxtH5eApTLH9x83gVZH3p5O51gWEHqLDmYS
RI3SOPZG+QoasvtmqOehVnEKqs0Z/eLcxqjHtBbpsuWxMgDcUIdNd7QFzBgostS9aJ3Ae9yCMk7K
C2/U7C2bHzyQYMv7UpFL+JGzG3S8e+kfYnbDkDKvk4vNys/x4qO0BmvMUABSwb8aCtY2uS/tq+6O
2N+eLrMlBvt+Vw2XIJnuiBEkU2HQd7RifT9JqournObcMoxFriBW3qaVBjvftb5Y7GAXfaqjHXgq
VC0E9u59zZ7+bk+N3RgaZg1PgY6x5WDWdyM1KeVBEMCz849cMSZuTyS2K2Ve56zDqRmdbfFmlSxU
QZbuZg0pmy9koXbghPzRNVTm9u6yvFSZ3apg5ol6pXGWY+BgZV8HX2+XazhJAR3uoYgMha0QOakR
bzGF/Dt9AqceBYOzCaSF0eF8tfSE80n0rr00aDUerxwWXLum/yaFfWxACQHR4DE+RNWiN9kpZL6h
tdCTiEEw5QaOXhpQzrlnQXDUrwcuCWyDeWBwXcJAlTds12QKi/7c2tKgJlL7DzqHwj5fSTIgGhCT
o9KG99KnQbcLUmaO7wnGmcPEFr1vE3evrjAgrivFGraxT4D9MI+RYISS6GReDhpgEp9p4ILgUoMU
yb0IwdJvcYNk0M+zc5ultkK7izdq2+dfrsf2VtkaaZb/xl77Y/QhdIXAIaayStZCPGWyCODxDj0j
EUwBrQUGsZ0goqtuDSpZX5nlBtBRG43SoveNCbOJVMTvMnWtGVpKJ4FnIVJQJn95PP1YbDmS2yie
wQBWGgVPtUqhcm36nu+et37jh9511Eyu0BqsqjpN4lmoClqQi6klqAZ28FrhJDrlRmI+nXphxQ04
ZC6Z3cofuVPqHEXlA+i67nUBoxhaP3Kmz2a4TMWOS95nzOYlTuUZv/gpkkdxjvjfL76qSzRXs9m1
fMNSu7bruEM8yXh4qke7kHIqmAsHQJy5pfNM9ByeuTT/dBYEff0ie3x8bnMF0ZdZ+Qt6h1WJUuas
cZarJSAKkCUU/dAt28eIUIeTIXte/qU1p9q+lUv7IwWrnBuNj5OpsDQvi6R/PWcem2HVPxcaWORO
JXirmsmUFjyLKFWPIRwQEYkOdvq7MDl+kD2MUKG1pswAQ3yCwznNNgXp2YftYZ8tfe33W+PvPfmS
0/fNXERVN1yqympOjbYrfNrCnE1shyd2Nf6kQx2CR1LwFFS4A9is0cpUWa90O/jrvMMsgk1JMZ5i
DDmuAFhcKS0PI37TryDME1K47GEniiZ46gw59c63eD8Aookl8L3IPcz4p2T2t2hH7J7WDHjNo9Gk
BNBUPwprIswS1YpAqyYGQGOYg9Civ9a4PKtbvT3y4e0dbPeIVEfpQg73R2bwOSs+inHWKTIOACrj
xjTzVz7IarCyaefK8g+lB/Vp2wQ03i2kHa3zgPQTyApBFBo4JNvUGupCmJjBGuDuJq5jGTiZ12zG
CJW0uzxq0Otf2nMlmkguQ3fAw5t9HbC3Yca4oL8tv0CfRkQNMu4z6JuWzX87PGHSQCCIrjTjjHGu
1xrmoST5OuZvqFJh8mMJT5h7y8yBOV+NRKCIG8PrSndtIIkaIK1/6+5gMqC76R8jKL9kUjJQcuT4
c7wdtrpwikHJ3rGviJikJuCFtA8G9CPwJapL/HeToT/eNEQhtBbzl2Ba1L1n3U77vjqxX995mnUw
fN6wqemRIhW9harPT7CIFfSVbY+AhFgNiRt3GXNGd47YAQHc1641S/NzzRlpLfxq77ww8JWrJDJg
qo0eGeAyfIZbZp1Kry/WOYkiXwL7pSgTpCDv5/UGn3RZVNBlgmWLCjyNszbP+kcViNEzolhokb8O
1alTL+N5ODGLqXO1WifO3pPOBLRqWFHLywlauwpF4oFtcV+IJD/XNXX35OkvMqMCb+/fdmN4T8Fd
/9bv+BXYzM69wgYjDfMfQtM4LvucFPEkmXggWHU76bGqwHE0r1idSNrwHHdHBU1OfrvfpE0wv+bH
Ngz/haeWEKzppP2Z1tN4PL9XGT+Dktg/Co50xKm50bHRWHxB/xUwcNX5+l4xJwvsKlX5yfWpQH6E
Gzv//gre+h7qy4+Dh4p9rRMSHPHGGJYYIdy+snpGofVEF+qeClWmVsCqRQoj3VJFx1VpONnMZ4ha
Lsr+5lLCLhzfdluaBkx+nbudWr0uSU/Xc0C5DkX1+7NjgZiNB47oZo7+daRFE5IphU67TjerrO6s
FqdnSyeXpM0wsgnSgU7BJRruVWuseNAky+GqcMqaqZgfSKMNEIqLdgjhx5BWAGmK7tB0M4uwotdb
I2Eq8vhJgwHf0US/TMyJG9MQOr8bl7b2c5dFICmHZeBsMjIEH9URA6yDIZTgiQBvfdz9EjV/B0Qs
SzjqiRSuCKp+Oaoj20AGbT429MkQe/yWzZdb79K6mUtbG4Mr85w1veB170bPD81kBtyX2R8bnXmu
/zyWKwBw6GafYrEa+m3strqjQL4QFMPBz4J9qX7PkSYD4wbJ7cx3YLYykg9YuzgYy0FbUjKJlEDR
X12Jez60T87CjtVSfYQgfyXiC3cEJ274GEewIyNoHZnXBZc+MSwmnfNVIlXzVX1hd3Mr0pjJ/KdC
jglLlXh2LKbU2qfGRc9DkaSg8C84W59GdMyG8S/k9OR4+zrScW14WfTVYwZFi4dQOU3m1ANg2FPL
nTpmCEQ3yz1eQOvW2QSX54zZkJkTjdxi/SNzs8QRfIYERF0H/T7X9dA3DUMTS9T9UoEffyrDnC1r
Y5ojEj/3Jhouo0P+MQKlfOfGyMk8/XAHONfGPwtcUi6hYfjL2SnhFzBmEzP8h0j/vzkWdmTdvjiA
Ol/bkXicBoIp3F/O9d3QAYP2W6mr7D/LgAaw/khD5iyOXZWyymk/zsulaURcX4QZJvP5jehBIO8I
EQaiCOhbX4yah6K3sFO4ohQml8aK6PWUEhY1RTst45HToIfUkw2juB+eevcb1ykGqpBTbX3LODaA
XkEdnFy/IZngHcSg+fzIGnZf2NI5+yIzWTx8TdSOmD2ZqhC6PF5Rdhz15HbhEbltrgzT5OKtBbTK
7hqFIgforarN+Yp8WJo/XdwtXXHREu7LfWUvZD0vkxjUDfz7jUWuOvPQo2OzJRRSSkHlUV67B7zF
1m4Gt3RSAyV4PujW41Oot03o7eRpcDJ5d74cFDldyUQkmB/FTHCQReggnmr4goRUTlWymjHVTutm
2W8dq9dWelkkoJvuv5d+cMG1LtgeeQ9RokXswDa2pF4kV4EwDTlXoo5+Vb8RHYUhSU0B82wx+zqR
WYUS1Q1c1U5rivyst67wp6FHx7twT66pjMZOVkAnWr+HxT5mDXehvrUpbURDHlTRwU1X8aFXUNqq
gp+LAPO8iUebqHp20ikxabjSqmUd6iqTGxuy5D9Xb84i9cy4eaEXMkmVtuYzNh7UT2iMdvKsiPfP
CK5unylXuKo4lCLSHbmRV7FaX7JIGoYzUuCnTzqGxRHFx/Ufp+ypZeBTn//pMhbjjYGZ8jql6Lxf
QhMWJB+fGv7sL43i/rK3ObG+T42V1u98yJ/88Vrs//zDSpJ6ucaZxKSyV16AbN3hLmp238T9PDoa
vhct2NSoUwMWxnyDM3oDQYh7Kc2gqEBtdDJJl15XlGNxJnHzzwCKtTDHSyXTTILt61mlQRFTM7Of
hKxqlFAvDL9HohHh3VHs/87DiqFFI3ApizTKREq0vEDGUtp+hfYaZnnxS+mMFdoRdpFFn+HZiX9T
wDABR+OHdNo0+j0fBj25MpKPhDVGASXeIPw2cpNY6mNPimLpdVYMum+HMvGk8aKmC49AxVca5E/I
ffbKFrsiQ+VjO4a95NMtz5pdXxS1EdtyzmlS6pvOVNZE3MIbYHUNVixjkj4WrLwSFoURWOklRRJZ
CG+yZ564fMOHj4mtfz39QK3VNIDBf7jOjaVnGbUrhmkpn4L1EZmZ7usDVKtfxQlCxhWk+WX5v6Ky
ioefHosY1NMF+Ij+7HQFNoW0paPYqkTTB8YOL71CilCocscAeTpuLKns11G9T0NPNfHw7TM15KFi
y9tDOSVxcVhOAprC12jU52AzxQ6qyIqDpuWQ+vctbyNcMTOsiuQSyUimf/1Rd3e1+J8weqEXSUIz
LeR9vyej+UYRtnNLEtlhEWsTvBDJNBcoRjf60SygqO40qo277xo7Pt+WkVIusN8mt1YoCi+rPYb4
h58/TlDE+xR5YRo0sYOoZmUQTx1ZgQIyTuUtBLaUiv8piRhrSGXbH2++4yrj3gPd7VPkLYI8kpme
UmvhE/0ohuROmWrmkSyVAMPmUEosw5RVREIQvDJwhN59F2VgW0BunN8umtyE2PrgfSsfJ0uWdsE0
A4LSDPqJEddERIsmM34x3+iF3TVhVYm2TUYVBALMHOoRKzutzBQ81Bu5F0B0FuZZ4NUcif+3Dnjx
qoiVXrqh4Y5AoL1CoTZssYf21c18No+3WQnIEHPBzxOW347EUOuUIuamK9oomLQkeuqYvUTacIAr
QI4093qrCJQJXBgmKx8AWhi0mcUGHOrfUimKyr+YiHeJKbrRItLQ9FFkeKfCDx7v+/cqd6EY1afL
EHbC7RkIEzokDvAaAfMNgcgIYDz039Zi54u6TKXaKtrChKZVrTotqHcOBixbrMO7D/OdqaLYxr2Z
EIXeiDOMsKr9qPMihRGI1aQ8D5rQGNUnDu18BxUOe4Uc5Wwr5SNy/+TC6xWEdTq0B1sE7YcnusSA
nPPkYtn3NxFgI6BuMzwGaOCcVIr4/2ODNQx6Ezdn1i/r1jtEUXTnOg0fOJTM1QTrr/AmRBhI0/Y7
IwbFCilLw6saUGMHA2JceXHpNQKuPua9eEIi9ODk8Q4JnkfwHqoKCB2kikgWwt1pqo6FiRySAEMC
jlsQ57UU7VWxCPMmjqYgl1bfRglNzsaM2wJFaSyfTCIHmlylTPrRu4wFx31gM5Ipo/TysOgpHc7k
9skAjaX1Xenx1I79iQlR9Vap0ZREiJgMV/Rqze+15Rg3sFcfaEnhQQPFmd2dhdjaG3v/S5TMDd8Q
dCERmfb4fO5oXJOs7D6kQYMJheVWsh5YRce+vD4XSbu9VbZZrHWjDs0XRqu3m81iFgIGYDmexrLT
tWqkzkcE7MvFkJTc08t0vA9EBj6JtXrZmSN47K4Gj1mS4eVjB988ctMsbbiVQbq4DoIUpVqukujn
zNnQVYHYZaKXONP7opb1uAypUg9xB0l2IdOcdAowtvbDxujf9e6Wp/W/ZCxe1IGBprXXx4gX4pzS
Kegu6KH4wjMc2jWAz4CwPJ45yRmi4ssItRnyQgt67+QGl7fQA7E6+mzSR/vFPnTnQLTMMCYDtB8e
ANxVL6DngoNEh/U/OBmPhyD4A/q1tknEnNqpimkFScyE1H+gC4YuMtG2bNtY8R7FctotL2em3B2O
8LiiBiRdgaytNt7EDrZ+32L9fOA/O0dbmTAcCXxMLgXtXgW+2EXT6LH9eo59nEAjf7yic2cdISGj
sXkoVm8YrxZu3sZxQMPmo6flxUohmVawABOIltqtT+jCGs91m2GRtms6Q51bRWvfuGId3hr8oljF
osK7ANAkxJ+x+WaX9Uju98h0Dwi74rByn4nQKQVmec+JaHx6khvOvsm7+lkwgb4ixWVcOt/WWWkL
EyC0jK/SHnOwnY/hLP5yg/rhMywlklDPHIa7LLdaPwWKKkMeUFnMCOdPMqLh/mymsTdI/9k+hz18
eCzNxUNiFr1iqJsZtntGtjb4XRuuACvcLRLXg7NQcQJXXu8MQ8BQ3eDCV/sbP64fLIPoAqshHzD/
bdiflwnA6tF7AiiikMG+CX4CYOIhhKbb0v9RQrKC1Ke7YPpnshUuISTw6mOY/nK+SetAvfoZi6fp
8IhspBanBSUR0XmnigwQZqRdj4i4xz8VZM9LDRfilvL0S0zj4r0ZtrOsvyVZQHbf5MBhvSHtMxFO
Y95S5rjeCI/p/0TsXw+9L6VA2kh91BH7OW4K4cYoP5XzaiCFCoDL/EDQQDcBSNC+f1qAdv44Wsfz
3IypPq0SoqhScJQI3bVW+GjqNyxbFaIY7r+xqupMdIRBC84k7J30dbPrYISY0wNG5SDPJ8Yngx6R
MDQtdJCIljalG9eNUk+GWJtDMEFtWE9QvErpwLVa3VkfHTsEb1drRM+anYJlpg6jI26/AlBuo05M
dIZlmbq/mJEd4Gj59ZQtKPsXaboPZ8cQ8Mq3qXHL5CPajRvDrclHLiUrNJ3OJVT69fVgGioVP8e9
ayWXp424+TmW6EVnhujiMourA5tIQogmIHbfwP7KzPktysNM2VuFsg+3HcPdARpNblnwsi9BEpe6
PvIP2d/uflnckHi7dxEI+MVzgUB77L1HNDjkiYGjQLzXS488Txl2igzgEkyDjWs6VW9ZLOKhMfo7
i3UPt5pVLUCXZJ97vzYQnGk9VtUPU9Ko0rrq2nhxA9Dn1NGjxNsCt8Oefba/zcApc3Byt1Nym20r
RfhZP0PrOsaQJLMmAp0yUQLT+4d9pwe8qEC75JUrj30hSLsiPL0jVaxybS/RszEFul6QjWpkAyKq
C+YnQ11ZAgvXk7lqglu1Qw4/ZYLadjn1de8lmCQMMnb2da2oalgKJkMa6gqHnacQuQeXsLgcxvHk
YcaX4Gb466Zp9OdT3Eq5rJvs/o5CbUD6xrRvV3mZis49ZyQ3OwDJmlT8Rvho7g578hrigGrD0Wwt
4YQwGT1QyriVfaG2jDcmyaDK4JBpUGfysJtMXl8UqdkYbhB3xw0CPGgyEvzb+271X1QSzsWPLqkm
Z+9GM5juCmzXtg55kKswsx8JkAQ636YglAtnZXWs/eLTeF9X8PfmnASnlUBuWBlX8V9nAC4IExCa
0K2fJvXTqjwhmC7dEKNobUu8zJDDatbXXT/r7hKgPfW9uqempeGX5dBzdh7K5SOfdpGfJi+0Vcoq
7KH+z/FVlH1LWNh6LvNMsl5qq0BNpet2Qk1ZvUXxFxkSOjOSJDMrLsyGx6uFcvxZVFdQcUjfMVKo
p10hRM3sYpF0KXOMRxHt67Y2pyDzu0/70nUmwv7KHsg2f5+ZpQjKfk+oDx6d9TfaqBPIRq3eSjXV
YQBSZvbfim7M5Ah/rbhFV5MEEgwlUEqHGwCflCf4dblambXPOHGSzq0No62LzfLL7PXn0bmx2w1r
EAUsTRq4O+ba4jNlgsm9YqHQ5bHCTxSSlZsYV6GiHjig7HInlEzb4lfpvxZdqXXVpJ8pcmlGVfiW
4EOs8ocs/KAHdgvzlT0piSwWI2QSFt/B1PUEB2juvCQKWaEH0cmcbQsNtBQ22VbiekpnybHW6wx8
pL6pmsWD/xzEOJgGOkVb34S+9xvqtZdW1s8KtaNUbXt4aXDrvowrysObsj7TZAGKEOk3uH9iFnAh
/erZwJnC6vqy2wkPaFqUQfBOzRW4r+I+9IlrtFiR4S2F3bh/Ok1mh2+HBPNsIQBy7TL4O3aJBXZi
9HElfm5tnCDjEGG60CY1tJrO7R+j4PjWVhJG+/AClcopteoNAiWSXmwE6YcKxYkqiSuH3Eda30wO
z5kxCqQYUBZNBoS75IlqV4KcfsOq3N/kH+8KVTb61fHdC0/3OG9HKK1NIyDAEXbcZ8eYWILFDQUg
0BK3oj14FnQ4EZ34pX5+hmmIlpRDoUoQJ/goKi77WOF76E8jHXet19s1dq6UClwoxrFypE+v06AX
Sx00Ps3Rr21dOpyc5wyFChZsTb9gXIdjTSELdXxxZYnPLz5I+O+kSiNpOwtefcQ7qmBs5pNuBhpt
yn13XqjJa0c4mlj8kpeUEbrquhzo5G30AckNBBzsty00bdqJZ2rYjbUpwQrcpYVqXWn7lzW1mFAM
l/KLCkr1GvKMJK1VOl8asCX9BNA1Q4Cu81TZKe7vg8zEtoA7amrpiwvaRolo7bZmwvo0G5XvlRNB
13EMCq75auO8EQGFNyvvUeZZtsMqI3MGzlH1xBhzz9AxO0arFFaN39EoK0aQCyoN4i/BF4rIpebB
8PP6ONMP/O+CVA1QhQ5cWqx0J8dwxEplhfJ8MsdVgDXf1RpcqFLsr5Ngh0Hh0dnmZup/rBiPu+fn
0uJ8VTtSwUYrh+1cRuZu403mScpVcXzSM78YNpaxljUQOiuCZF5JE2ugiTYfUI1pLPr1jh6S9mZg
swCPf/Bnf/O/6CQiGiMEQ0oWAc64cPNOHoMQq6rb3vG9iOHD/+Xd+nBDRi3hHhsrCxIBkG75ou7q
0d6PYddTtOGuIUuuUXvqB9+XA6Z4A3YiqZDjfhi/srbZqNN2Cy7GdZ1f112PxJFsSv3plPyb/KmH
nwy87EnLfYtqFcZLJgar7O9CWA34dC58CVesOEZ3h97xTyncXI/cMlwJ3xtnTnlhMGgIf2KKcvdL
J7oNfGpfOoOuhgnS/aWCvmf8x7x4lKTAx6GTwiqk55Pbe9oEPPd8NCrw3jrgFTboWmoz5Jy+DGZX
fSnO0nK1vNtnyywzsJgvCpB0+P1hNm8PqcuNBPD5P1nKQDMugrWtqzcKZSm+lVaUjs55EfOApGQA
IhzdZNbyxgYgIm4ByXBTXlZGhp/Wx2TGg9PuCdx95BJ27noKiI5+R5TU+/LwwUfzh8dYrQwi8/DG
ZwiceMCKtjDJd14H6ZMqsmui6V5190E/E2+qDfxSTfmphS2zZIxBiCMnd2eNNgg+6x9b1ezXh/r5
7DwH3V/HpkOvfWuaskJ/sJDp0MVozEQW5bo1SldP277HweDpkq3C2bjG3S2fsjSHcxBXpPVQ92Z7
ZTJ0NPJV3gcVlFHyxIWh+A5hRQJoQexJaLvLrWWuIbWErAjrRDgS2yq46LGybh+YujJqrg63rjRt
7oE1pLzw94JH5tC7fGvGbD3Crd7YYbDE54ub1MOBY3iDbrUY3mLcjNkWSrRif+5on4G80pNMgxiH
4KO3Vrv0FGjVXmbTbQLHLvUDOPqYuWJ3Nh0+mEwzQ9YPUjZsGeJguEFI+YaulOWm0x9hTIIZ9LuK
g2ZD9jpX75rSTQNAXpzzKvdCwJJOHPr4bfnsxVI68v5xId1YBWHy8xKyBNRW73Vxjrhz6x/s6S/C
SXJsNUYpasvM/OWavXR2+u0kZ157iyQd5fjeGPvYAfXmD6XKJJHSo1LuPguTcUy3k+4+1/IDFQmZ
qmL5Sd3cm6uBLw1kEhEsAzEKPOU50aee+QMUlA/Z+yIAAhKeg9qfzYkgo/oMgtNiS6ZqYGmiPtUH
Lm0IrlJZlRq8KuRxhxPyl5DSXIp8GUDLFvQPAPc6e5LP88wgRXCbbFurH2K7VH8OPwgB893FNcDc
dwExUB2gp2qL52jXHpExNkcdeIRzUzdmWPBlFZEdNuWxZIUyN523Pf4lOaHJbusbbh18Y9PVsQ2S
ZFNReS6AlaSKaZ+o0M5juUnihlpDWXf5HcDSoJ/Rywn84d1+NJcrkIOCSXflZeM1lmv6t4aFFdiF
aOSPjVTw50XzbmlC5fbzppew1jKD76oNA+PYjDeOXNpQhNNAAGdTNPghvfZxHybfnMcWimc9o8ZQ
mY92+rC6IISMCqg1tyDw2ohQmdT/sFOiwjV38MW+R3nQzaq8xBERzcnNupVagjVVNZJ/Ba0qSch0
ICsM+m8wTVt6I7Z/D51qH7JSToqClqj4rumaYMqJE4VvhFUKub/Of1zRdTnHK02UvKUvj1iB+o0v
3ZSCgGpVaZXaTRM=
`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/fifo_generator_v11_0.vhd | 19 | 89172 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Ya253+37kdInKtzN3pd3f0ykMvIJsSTHE2tRr5TaFzMStJPqyqbq8G0/aCj9umOixPoTbod1oPEi
NM8lNQufqQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ZnAl3olUb+r5fzAKtbT+P9BDg9y9NfOiCUm1R2Jcpt91ydHcXeu+pZ8D0lxHNM0CXXGhs5RFFeCB
fQNmyCQv4qniT4fHHC3wrH5hPwmAH8kqSEyGt3c0SvSsHCYTeXhpF8Chp2XvC1WNZGYymRNjehFn
t70d4j3zNeEsu5WAW84=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
iKnL/TA899sfLGiFOsNtfsGv8lNgBNaSxC78jj2+skMz/TodvgTxrRQVQ/h/L38N/D5FIkKYR4II
+olODWgmPzea4VBkBMLQ7z2XenA/M8Uvin39meT5Qbx7/ksgG2EdpyOtsmAvmeXZQgf/A59DevU7
Mrm0rcVFwLpmjNvbnBOl5iGpGgx6v231GzIUzFEiOeCx1PkRai2IOZKE9lG2BMKHN7Bhsm6JH1NF
XhuV8OyupD6h/Fr6EDMMNZqriSBB1MM7btJKN6VC9jmTT/Bega2BSYjqAkfYdUTeyup0UqEM3znP
2BL1mUmUOgL1/UMAmExO5qz/A5ddH+Ai46kqhA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bwfblhQfYU7J4v01pOh0vYth2hZJ6Xlf2qmEYdxkErcnbM5+VpJUpwU8+A/bDOJB4gUPbJHCeAw+
tmj2AabGe4D0Pf/UukkjTsO8eFOUvoPbwDwH6UV1AKQFszUSN+Z4NTgaKs8pxWumW0juNgJujhCL
2ChBu6ddPnHdB5HG8uQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UTW+eKUNnZFWLDMo9paR505jK3kaKnyoN1JMPNm5SlY5iSmlguqsHIHMaqSHkHrYg25dIfFqsLa+
ygBhaN4bDhxyus3QZ9m0sw/aVS4ly/5bNlw+8ePaK1evrFFnRWDzqTt8U+H1O06G7NfpkTmeK+am
Q1esOyihSrmjwIiD3aw5SiSY1J84QcBDQl5D2DAd5uRtMADgrmEFzx9Y7yHel0j2iF6Z2vom7g5G
7K31eIbiTPvCntdYde5+aN/nl/kdiT8a+6o8fslm8ZFdkfMYbKE6CsL8CG+5F82TWbIzOMfxbILY
sXfUaKwgi3ZDGoeeudit9zXCRYxReIG0hfQ27Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64272)
`protect data_block
/bcZV+m49oZuF6FYMRCgeXDBoi+tDtdX0blPrXZW2WcdMTVIfSVBSCAcvKerZqg5DwgpZ4zc1a8Z
PQnazme/gUNwsrQbTFBj3g7LXgBYG44tA6xE1n0KrLcGlntfqBOsHgTpASSEkElb4HJXZB55DmKH
gnveqK1rWnpq2sitK06fD+nm/dJBi/j1kOtyPVhNe7g7U7MTUoaXTurpQdwDUXpLtnyNAr1HRKh6
TE+MhbRskxJTdlsPtj4nEHfTMmvtIQtS3g1rN/+9QI7yr8C+fI3PYWqyPuFyl4GbBd1CDSLS1GHv
8tnAJq5WQFJ6vmIs/w7+Sv+PLCGEG179A2QgWQ8MtCN0XZ1kuWBbsXotXojnxDLY90u2R0EuGz9r
QfGgrh7JEPNpUpszWqXEcKje98BABWOnQDRHBTiEZw0mfODfA2Zj4+W2A+xfymGgYXsPK9QHtYw3
gD9vNUzTpdBVsXKvYtMgrPsO+u/1VovOSGhOAzsAcXM02z5fd0k4USfVlxlVLLKv8caObncWQgJm
MGL72VNY0xx7xeltFMDKx9YGODZcfdjWXPEGr01Pk2ejHxavbLDb1Egai52yI/ycoQch8OT0pnnc
Pl5fRw1mRn4sBeEPrt7YNjq6jvTloylkKMcY1eQVQX/VYZz4WqSPyWTodrQR6+JZQgtHczBMWvkg
I8QtywgTuPbcu+FAEXqhMFaUeSZJzOEnDQP5rvDKbkQurWUe8Y0q/wBLiAV721gDAykZdoMZJWA/
6myOZAVyC53lZhlhXyJNp4SGD0wpZ6AK2R5N3tWAG5aMjuPOQk1Kl0yvbKhqEKmQcInSVrPpILPq
qWmJMlaTmq4chBAFFeCmrXGRcb3EjB6cGZ1lQB+2IfmjxE+c5kJKAdTMDF0s8VepeHluNnYZpx4+
qQyG0O/tQ6f8w0+v6w0QO39BY4VtsblKqabYmms3h4fJTvNUfajj3lmoNbE9954B27Nb9xQyP9Nf
SYnW5AHb1Vd4LP7eNG4wiOT/LT/FHeJTTfEJSvxdwUHqEZf6E7JNyfoutIZC2cZFK8o8epS9uDW6
C1fYaqsd4vOQM+QMcuafumTdYH54TIcVBwXwUaH94nrxwSaLhcsmdPB0R+hDrHvAtAozp2Vk+b4I
07nWMpciA7uPVEHI8x2VK1ZhEPt6lsl8UkRsXo86COEXC3iOjnx3WABlQfCHNXL8BqtYOOBbFkS1
Z3asfjAWxbjOK/mmBTvlZrG20fdqzESmJpkIMuIH9cv930hBXqCcaahuwnwFpw7drRZX6JXIIf7n
VPW3aAHlplSAYFMDH2TC7QSvMBghwllnYcO2oQCfUccsVqZovLEaOiN9wLAXKp4p02jBumDy8zTr
g2R7rqar5CfbHHzKnqUXtsCu9plM72c3Str6ucms4iY0CE1SdlnCEPUTaG9qHTxr5kqEcFUHnLVB
ivaMNRjBCWv0yEm3xHSjw4Lo5DhFXhvhJO0ZhrGrRRPaar84yUewvh7BJYPPnEZBwyzcCaZRJ6Da
nK8931tqFzUt1EJOSR9SWCd+sh2740m9yAkNRYV2ydtlYCPXeNCt9Xla/KzDDMhoVhCUybNakpiM
34sr/QFWxS3jfw/dKeaBzIPa/4xLDeqwEwo7yKVRR1JvngbJCkyj2IqnWz47FePc4LiF0898B65R
OPM7bU7qazW4awk7DlKEhwhYTZQyASAeyxEPNg9qrrF4lcZBChwne0TNhtbOIYsXiE3gSpreksYF
ObN6fRc/7WLe/mfxDEFjfX+QSQGhdu3dIhXKi9Ivr8y0G6gm1OqUEy28YHNehvJaIQOlgJdNQ7Pb
ibFv6Z9KX74UUybO0QvIk8q17XUPQBQtnYtfHh5bdEbfpt246ZnpA2NLC8ZqZ5FVOlUkRNJXFduC
BjuVIIUheFtqt758+CMesl0sCdfdOEN+fMoINSXUd9hh1r3ajQnOBjD3IoRqvRTAObC/Kqsrb11c
e/Xxv7fDNBBZ0sDCU6d4cq3vxrYr/l6EoypXbZLxeRJktfPKuLxQFPIFI8KX3CF1U3TIkxJNtEqr
wTU45ANMoGJJxXMzXK/QkoRhvOlevQbKUjEp4cu7Lk58h4/AjWPDLMgaqecLlrcMjPHeWLDYysjt
3E/kTIDJZxdX68mKkpMNOBKaEfsWECiCrcwpfdc8q3YXUJU8cRwPQwj/wGLozKU8wtj+NNozPiJ3
K1aFKTLMnWSqebxFeQnUyDv4WqUEZrWgmxBj313FagzJANB/2bLA/+k3xGTiuQC/Adz73IhfhC2g
VOZXyslyEObEpdWCm1L0KMvAyE2Cg/rNWa1Z8kCdW9FZZuO5p1dHhNvGZN4iJMcXeHfEa8bnFgWt
sD2BvzBbzWOB6T857aaDMNQchVWvoZEnnE5LiRMxNi8SNfNaq9foJYDJVaeUsvKV4Wd2t0Oohtpt
UlSV5k2wWXA+vW/sQsW4713yRFK96/0bYA+7o2p/X9vbCu7FzxUFqg21ZswZPBNLNRki0HF3v/M4
sjbh9GHmjSe0ZrWmpgX4yYWhi78l0x8tI+bzwB58O7v+/6G3TEoThVP4W6BUDU35qNyFF/EUOrvN
VNKer3v5RfuEJrK9XB2siDBIpSrw/Qzc486ur4Ay/FR/S1AjLVVs/6rtcBg9zeTu/LrB5QOnHaER
j9i+KvuRbMGj+zym9AizphF3kP8Cv5G2jI0KF1fsBSOMKUcU3Za6TXX9SqxyjfoTsBMZ+a0F4pmN
EA7jA5c0HynlS4ppxjegZlLM67kiCi9SEJlKnb49j6PjCPt+hc7d87WQ+Ddg7ut41Bqk0sU8Npfr
8WL/zdRRiMFjxJJ2TqFJFPJpkK2CZYrqPyiHBoySEgia4h2JoF79I9SoUQtwHapGXC9b1dZspcwG
dC1059+/Fe3VCuEIURlTF/YjYv9/cgjwh9ET1FSeXgZSKg4/iA0ibrqnVy+H5gN/8DU6GOY5OIpI
k8y3tC2VTPKIGTUDxyDF4kVVrYm1LF0Ob5tNApaXEuIXq41yly2/E0HIM57QwxgoaGJcvdJ2WAjK
AxFVEa+7lnqtzZWmj0nIc54Ls1n3TveouJePInJ+OqYgNW5ISG13qJReX8lOIcnP7w9gTAuzZoMU
lMpCLNFaZwMt76hZNmSoB5nOsBjgeXD8GLMR7QuNK6QGjV4C9WIrVLNKNF9GvDUVuJ5GMqKWKAYq
RZFspPQ6Jx4/cLcvne3t/w/9Pe7HxGfAQhTrNh9NokqAdlil2792YglaMBnVSNQxPZVYm3rDYMwf
YPhVN3HPuCy6Yp4KNg8PvC5Y7IumWbgGnVGvSpHa18RGoSNgrxpcN+eULaX5qo7gVuOn9wFBGuHG
v7iQujfQD64Td5sUwWYLI/M4AjGXVoG0hCd4+bf421L4xuUEeHPZro8fJUx/PkcfynQ1Z1C/YfiN
Bl5FBzHs6Eu8i6w1enOuvcO/mu54ytgUHpqk7WTBT9RAAJjoCr9vdH5fGvNXSvZP9VFhHmKsIshU
f+H1+j9lHAm7+zqz5lW6HUMhCUThuA0bNO3ShfTBAYma61Vyb+BoQwfE1L4FxqkVprjQvSlzUHpX
MT2TqKOIFJP7M3Om5/l52oiabuCa67RMcBukRomc9lqcmVQs7ea7ezeKQaCT1VGEc0DrHGogP6H+
AKIF1AUb9whYplivB7Hpe2HMpkLd9ZLoegn0LZyIjKkTThb0HWeM5zyibSFQ5H+zGMe2JzRkjE5Q
Ed7/Xw3qQ9QV98Gn0/7FUUK+VgDjQyLNcINA1PYBCi50iELJXLj2vebZ97A8OAZy+5fvV1pYNU6/
SHNWcRTC5OR6fgBWfbZfarFQpvs6ukJ7l9tJ+ZJcUsSoZYO7JxVqnXr3nsoABKn/l85BRznM7Etv
Esiv9Gv05vzIN0HMUZBI32ws1//KkPf0JlAATpIBXBJrGjKktk1r3n7K2X46+LBnNCmyj6yLa/WM
bU2va+bkyJEUua7zZDqEINntC+Sv8wXQe4JmzagjoLGCnYveerStX1wKq0tlAV858oyrJexKSMr3
sAzu7D/C8Vlvb86YXLfL5ZY464oiMjcJoKn4Y5BPEEfY6wiOCHAyGYiy4FJSbrJnFEwtMuZ3r3D4
IMASoGJ7Wb0fwHha0EoylTkqPVH8keaYpZAfY7KmL+p9tbrjWWrX3WAAX36OUy6W8EtkrtWlhpAe
VvzaWIHbcoq0HOLJmxnD0a/mqoHxjzT6S+RpiOBzLQh+AXLWuA5g4fHsqBJm4Gcx+DZYx0T5qkqC
YJIchEoDORrr/+ugse1EqFW7/UWfka+BQxmDmXOohnEFBCXgl1HCrzuNrqiRaubWrR3x/lKhesGf
laADOC+gxidQxFiOKcOmzZVnbhPWFauGPjQTGEk7uPwoZCbh8avmsHu/aZwq1LU3WL/K41GR1p5G
Afjxr48iZzPUNJeUq/mMBXMuE0kgmb++iphDi2WDi0bRIVfeMMYf3g6o6pT2thb47ULDh7ZQfn8O
gZaH9GczG4yPM/mFfTUgPQsP+WwBcMGPTNnM2wNlmhejvGt859eZO5EH9Ia/Zz2XuR0/1NwNP1i6
b5Rk6wPSdt201KDgNuKFzLcfTgIfJAKiymS46Fft0OOd45+ak/1WMkB0mqtRc+tRPdRlv9wRcKiA
mrdphuJrcmWAiEaURL1j0Y8vYRomdCsJwxX7EZmMEZ7ijU7qaoht/4R8uK8joH8amrmOuVABVz+6
e7LPLxBv+wFrSYxSak3FyKAY8hzNVSYjSSwDX0xcyRpVnDh3/8n/YUEr+IQFM7Sht2ZRzGy3gfIR
6lK+85ScZTEAPv4Zp2gBRRlmYt1jYNlBBBqV+JwvmfNDXCCnSZyooI658yfeaRrpyQkCmluN7mcn
NtNlao7h+tINcyCzDIKNRQHhl8rxDiwiR+NWZYDQXCJ5n9AiWexKPqb/P9Yn3iZcAQBMf0Q7KFyb
QAT85CmlDzg3RTrbhwcjk5CzBdT9i4LAwq3+TvtmUWiF7OUxDMibG1G51gQlfCFNApoEqgIRskaQ
dzf2/qq6uL8AURHSn27CWKoHVdcDoJ3Hh9RzrKuSKD6OYkYUPUX0hLvnWVSql5LaeQPBcf34hqVA
OHNZGRZ4oGWO8VBdKPTwtlPev5R7HrI2pAa6XcPs9JWqWkDlcFTmmDACU6kGPBMhvRY8eaAD5B1q
+q2pPfmNmStP5aQQ0Ek7ottldDtPzTAursOeP8ICQ8N2A1WojnHfmF4APLmsovHEkL52e+TYjVF8
mL9+7DNKFFX/VzAfG7/FBWi5V7YVbZ5AVBqlXv+CTqMBPzgoEUh5ewiPsRIE3AsqAUFTJ/cpI7Nj
h9vY5cwqQP3UA8OEzOwgYwzttpN263RfhWg9o51fM799dExFTVxcJSeLuvMniOnzOhKT1yGjs3UO
OOKcA4rambP00nfSqdymoPDj4HDgFWREGO7fzGv+je4WzbtFHyR/13YOWrltnKhQAzgqUZYFqrH8
Tv4g5F8JNZym9k+6mR0cVSvb+JNjwzzIXaorO9OvwxiLCyiayBHxipgFa5NYOQAT2Zhg2NOjaYnR
Fq8MpJeUHUXC1hddNiy0gh3MCBkxDP9/2ULpOayaZl8xt6NLQRhVTYUFP+DsovEng7bToCO88FvQ
wQVUEnDtwXPklpnnfUswq1buY/IyN4IE2GYn9rxDcNvX0QpQkFOg4HYteoJLdhJ3UpRaiyvdbjk/
9pNod1iJ20feIAvuhU5UzaPCQKWf5s5cKfjVIxFhwXUGo4C2Qx6qayZEDH/+Mkl4ou+Bjuuru8ry
3gA8/qN9rID853UCeCYfzOQIrvDIgUF9ExtRnewE77oIHEtu8jsn6i08dc7p+QVav2FVSx4jyXLg
lO5tqAxwZdC9j0ALyhyBvO2CroePgPFMlIG4yGWs84ctc3cl7M7yBDaJBSQh8qvVB/vBX1aOoCKD
uofEDJPVA6VVfYwtOfmTn4Df5Z47/euTsxz9/IMET1TCy7CJrFO0Xr53h7pQNHlyo9/9JxK49QmL
aocW/Acf+GubXTZAYrYEjar77jExzHhCcyAgCsI8Enz2yHDJTs1UH8XW2h2dn9Qopzp7EUGiXG4B
GffQmit38ypdgMHzleM3Km8tRdqeHiaOvlBRakf82txopBi9NiH2px4IEoz1+ss6aoKer+N7JjR0
rSEf7hFDpbUKNsOi9ATAeMADlNIShbC3y6K2pDmP1WMnRCCMLRa0a9qObyQp8Vd7V1JcMFkID7+f
H9jCtBMJL9XwWYD3nSS5EHTClRZJxR1PLeb07/O1igaLelwTnDtGRBc1hiIsnivV26wLgd9MUqBj
s0JnkplXai811cqyG4zkzERGfcLLAmQLnrORLYxebUz0Kk1clT29tYTotr/8itBuVEfkgRDgL2OA
GIdDCtsyNOZAI7Yer+TrBJXHMRMgebcztFJduNpi1RPMCniXHfrvtWtp4YotR/MnX+4BYDAGmyGz
waWKQHoDmJO5/6AQJ33sY3ubyTKazntlh2nQ3HVS6d5xVrkO3hRPnOjpDbTWA9S6a/Ptlc9cb0A6
7Liv0lF1zDPGpC6NJxeghMXl3y7hQEJyvfaw2Ir2p+Y2UEJaGGUshgDIe85lvm70zSnA6UN8s9sD
ZSnb4p79DebHVO9nA9Hoz3O9hSHdmQWp+6OZtbyZMCrHfpG6zc5J4S3F9yA6eYy/4QXe22q0R9AW
lmMcCFqkNedUApeaZnbLSUJsLQxf1b7u23+H5r+VB4EAgXt928NKi+sXlGKoLdp+ihXw+czH8RLI
dasR3Sg2oFkUwj7ucxOeYlPXk6EpOLaUjtd5F7kAjj3NtCiAuufSEDTSQWttVtT9OS6yAptS6BCN
4iKgRPU6X1pDXMfS/c6DCfeURUMdArhXUaxPdOpiMKNkYBH01ilHjlnkzG7luuMKp9PtI0kXwev9
1Y5TZNbTHc34QH+CCu5e9blSNtxXYuGijYcyoZDigBeNaia56qTIpK4fliSuoCwvTiFV1N7Jr6dK
2/6VM2jwPFo3QrIMBpL/Jcxi3zesTduTFDrPsXpgT2MFPRvD9v7ojmvic8/NUhodJv9jhEqOgN1o
fdNp+xj7AECHPmeIxi27ZO5SCwwBge0kTDsl6vqxaxYkgT+7QjMHIYzOGgLwwYGgU2wMOIUMSNgi
mr1uxNVCTf/quZ3jVcMA0/Uy+cwc8O4aRQn1iYivhp2fW4wEhx94ZiVV8Wjgh34wTfk0ayArzi1L
v1feHLE2zC6SJHUgHipatNYNkwRR/N8OeWG9OKM79Rwh6+lsfP4T+MOQHWE7iPUrIEeQ5Vmdj2Wf
tdGaHPyt46Nvsu4TkJ/WCyxiXko+DmrMkl95kUZT3k0d83l2JK+4JswPpHRstqrKk/OGv+ivR3m3
xd2/AnLkhUXIq/P95BlWTVw7ikmcDTmBd60RrPm4/snU41RB6WOeQJBQ+cXMCfCSLIR3aFcVz6QQ
tz4SQvcv4Q8NQ9Hdt9WRrzsKKErd+KzdY9GvkQSX8ckz3fcmkG7h81xukMT2Fw+ukuzCbsVUeeGG
YenSqos6EXCCd/NaEHzIwx68C/rz7kte9bM8dKS+X+4ppr1Wli3DMNZ8LPapOA0cQOUZcdJtZGD8
CQIvVClnUduVkOHiGp8bNQ0BWEIyUcxdXLJ5Y8Uc9iuprkZUh6xRUQ2UzfUZCxOinmkI6AcLMp4j
Pc4yk45b+9NodEK2DHO3DBtMsSCPpcbSRN4XfFc/gsaREiwVSJsQxpTXXdu9mi3mYQU7JW9ziywK
UoMF1uEboPXp8Fv2/u77Io8Kh9PZIld+CQFNtRD815Zt6ba8YBkYIi8uAmX6GBRmto16srCbMrYW
GzBPWMvf35+MnmHHVM1vV39jUDp2BI7Qx2P7IwEMGl2DIAteV18xf8hVtYltf1/dptn2kf/efxZY
oPhsq/kMoxow4gspvgpLHmPrqrVitONQ49Ga0qU+0z8PATa80IJrwDTVjGROEByK/m8cWyRZoA4h
0uIc56V1qjMA/ilACzCk7dyVecYMc1hrg+ORWxy/mOBSw+7JJ224JsihTdNgkzhvz8xI+EQK4zJA
Ab2qi6kCPfyJQXeBCLc0qdC29oX3XnfUEUn0b7POj/TWCAqH7QX2CjgVKM0gmC81tpomvc4ND+If
QVrEAGPBjo5jUb0fX6kc5/HzpaWNoIf/jHFRUBI8yUCHx29UsXmKDhU+bUXxluTZhuq/QVOVna12
vasYiTfDcs5eYY8uDNuVALHL6Lo3MZbfnOT2JR8PPxxyE6iZ1cZasxSO1JrwXaSy9V+yNTL1ZuPj
RNNJznXS5rqg4dk6pGxjIi1fHkcaWp+9sH5xADILcIWQbRwpHvMJ7nbsl1brVcgnxEChdrCoRjQv
88KP2qRfSljBwG4t+7rJXqz4wk7Ip9o+9vVYaX0t8tZr1UmIZ5HA46hrnngEw9cmxTUMFoN0ffgv
Z9jEGoX2u++LyRAXZn1hrNwmHwaYe4t/Y6/uLQ8sSohejFe17BoO/qUEfpwcwhEGHX+tovz+A1LT
2ffoacviFmxsLh2UPtECcYt3eNnJ9wRi/WN2KOaqY+am07yAW85zJbgUhtK7rlEl7FexVpGnd0YS
uC5CtjINfgFMMFsxDjSgw+Luomvp7lK8Rv4lRQoJxMKV0qzD5nnBU1l+WOVvzjU7vOrEM6TIHlcY
o1opbmPoMojuztsp/60iehKb3hW5ocBgC84xnpgZ3RuKkJZ4fwr7FXF14nAqdpzK8zbNK+HQ3kbm
LS2/uqkW2Tpy4JNMl3eJoSa8S4W1J4TYiWtNlFC5RdwA49gkuyguY4hBkjEdQMVwc0hjqaUwFCOM
1s+m/SUyJMLn7mqyhWJuGDNIHmU9VJysyDKHlHl5sOGIabnSJfcefiXtOKWwUDfs0yY+hJ9xHzHD
cKZcsSEeKKKDJRfxXcotkSC07zom5q42vOAFBUqxNqbSuR76QnLq7J3ChfSB7e8kR/awrn3kkIAn
h3+iOC/Cz28ug6k4gE8VoJ0ElRw4qY5IaKLGhL8ETEVU4snf0cAotS6seEH+BB3pF+pWQwrCb4fy
C7pPP6tXTWXum6fk7wC9nTK23vDQHWUfUUwDbGawg/HTea5IlkGLh16jyIjC4SWE51fRG+XqWKrX
FcrnrmG22E2lEm/jCyFDB02rJwu+Brhc2p9ApFBHgon3rheZYgDe9YLnXA4E4WGADDa0PDM6T7eN
AQKAsaZc6ODCPcSHCBbaDn/OHbehdWRrmToT0uPbGpGzg78LlLmKatxAm6lAXrV5mlTObs8ZZsDo
1Pi5wl/2bk5IhPZAvFlKTHl7V/MK4OTaDvKZYMDlN54tsnCnyr/2GFmGOFrWeZ4QP0KXPv7ZhnC/
x32INWp0YH41fMqliBJJDxRQZM0MpYbmPfc3PO62fZpQSuf8V26MLMFRJdQPjrb8lGXGKEASv9J/
flJRMIP6jWu0LIY44NlTonXPIN7w/ZrpcAiOmbpxHGoRrzu6Rrf5egIRHHB+fummHEq/TzarMVE4
GSQTn1ujewIWskL997m4f4sB4U0oDABj0jUaKL0iE5OmGne//+BVuA9PWjCqXNXUxq84Y271cKgF
rd+a5SHOh5H4xw4oKtzIfRTWar6G96bmPLGJ14YmOumylGKCnhlWoKrbpZTB/v11NMdZMn/PAq2f
fRyKq9YqgC4qVIeTdGP24XsJXjjTTdr8hZ7uzvDOIi7t7CPH45PuyMobmVjpNtj42VdBeX0k/Rul
PtjHCQa6ApHSrtTqAIplUsm3kZyCl0CWtgpft36LjnT20PbJG1Fn0T4KCe134wlUx4dLMdCEeBsQ
xX4fQ6WItCij4O4H1CoLR4AxgpWOxYkBUcX5emSk6ORukdcyQSEIYyluEjLfF1AG3SCc5/jnxpQk
Y49FRSOh9x5FiAx+BPvC6xnXyywDbl0n3PGCmZcy7wHbj4pXv9kjQyN140VZuVtSFVw7q4noRyE3
CPE0B+5F/eB2WXYoi3h6dy/UjW6jcmfJDZPzsL0ie+dgP5w6xphUKJgonoPaD7DCiVjw0RxdVB7j
2onej0/0pwkZsf/lH1WLDgkvTwifvH/6+SZGEnWmyOKzBSDFBRDJ2aK1RJ4+jHaq/1pfj15PWian
IO6AgiHX5MwzgS10upWt/mOiE8u3eITZ/Bcz9eUJ4ScYOUgCG1fUaf6EhkNXH0q8jQj/+8tJQkUI
3auAMAh0o133hdzmUoUi9nxjWeWHFZIuJY/bYIP9pkHcDHobZjzu91RHISCHiclGbOkGq/aKvOqS
vbjBfHbxe858F0Gk3uW+RloLgZtwZ3jRs5SobYY5R4+iBiFWp3NLvwusK+Ppomw7HnsZky8cZTn1
yFxPWfboF33k+pJtZVVa2y++jY6OdOZyNmG29tYY1X7EXmr4O8eYvRntGjLCm+vYOJ0xd8FXsfeG
vv6+yLEChJYYAv2f6jGKRo5EEqdrnaZsUbas5VYtAvqgH1Vy7sO4Lidgi6Kznsd/R9QxN4C/2+Vb
whSxmP7F+5NpjhxPAGigOPeRlnyiS2ZPtZ0ghDZwPvFiJ9zPrNiUKszD0zCNCft4K/VfTELqYeDl
v5i2dd2Rl0fGmuPGHHdRvHVblUmBl+wDIDfPhV8sX2j5PzWtb6datmQ9K7Mzy8wzjfNawJs6Ri6L
ZujEJf3xo6hXkVDeGXnsLY8OhY14sl4wxjjPj5H7Ly8d6B3q/U1C1AcYZAvZC4N752rxqkA7C9Zo
YYOnmQLzzucnKPaMjTgSLKhCnQWWGOUL4sbbGkOP4hr8goTxRHwJGKttBtsrFi1v6+R+WE19VlDG
neCqquRHxMra3YBgAk2Hs6SEjA3nP/065FHvpHYafoaFtATODPYx+A5+LmvJpSd9uw3HUGBJlUxv
Utz/WHRlVrx5B5sFqMjVvDOL1UUsSb2E21Ixp2nb052EbRJgMMUxZblx8IY+WKk6om4z91BK7DkP
jSn0K5oytTIfIDYemNDvsmrbmKc06Jaax88sAzyx9vVnwPgkVKLt2ZMSZrG9cKyO3ASJm5fG/RIq
6e3p8Tsmmcux+2BMH63KTZMy53NvlMURrDXQd52a7WOHuqhK1JtAfv+h7HTjWOrosNsYur4gGGTB
0VRKZx4Ztrk5On1yj2fpQfmG/evYYF3aFUKh43KzgKlPCY5VDUGJw9gbLeeZzNjy2dTDG1z1yf5Y
Nj4VviPANCV+FYELblwdHYPQTLFzefCWk0P0GfrEU1x5REtBeRjJul7W6qL0w6GKHAeHWj9FyRZV
nTGSE6eMnwWDCYM9+P72I2oO7wXrVqQotD5v7/b8IGvnW4b6hHXEv0AVxgWsD5Sr5rFjXqNLhLnA
ApKswN2vtHU4J+p+8tgs+OZ3StfcPvjGtL3mnAphbwhxEkrBu6bRj4BR2LK2Psa2Y/hD1v+W7+om
ObO2CEMXobOuWXpou9UMYDQ5FmAHpsMB1MMOu80sKwiKLKtyHCB8sDq+n13e/T5BeRfI11LLNJgg
vd0pOH+3kVgW7MnKVAEHdAjjXFfWsD9XYspBE1+V/OMPc0FzbTG3usawNUiHAq1EVzNVan/B5lC1
+9XuuZ4ty51VcuhfgKPtq8lyxtWhpNZ1fqV8hP5vHf44VafIpGwtFH2KHFhl9302cKxl9XBxco6M
2kZhEJukHKqCfzuaCPctPzVilG1Sl9ydUPgLBjz/Dssd8fDR7cHb17XSR039ar0nwp5Zz0gvCCIn
oPoK2exYVdfyOHGjKPXW98741BzED/ne0RX24gMOeqX+8TS+kXXUIE7HHOMielsQ/h1FpgySNCKk
MLKJhhaLg9tK/Ww+mXre0BUOvhqtWUvDJENHKIsitJx7EenfK7mTuc6MXlSixdy/OB6pZw8zQP+h
GOhVykw7Q6YvCfO2rZWpU6VNa94nymNR6dUxGBMa+pRYrMO6JvYfET9voRLbX+K/O/qpXtIEAX/y
Cb5FVEDL3Y4QXg4WYWg4I6TCSeR9jWN1na3VJ+6YhlmSNhG1nrauh2Emf96kAoWeMU9v1cBGMgQ+
oL6OQQHZd7cnbEZbpVtst+BjzrFndYnYhKGMmYeMtsNXXbcE17wOdmTfvWYfFpXl9zcBhkexNkwB
rANZR47A+lt5t7pJP0O32XZ79PirRopgabe6WWUQiakToIbrc9LjR4Grp12ujYBZ0NKOccIDvnLM
RGkpWOSG4i8Zuv5mBu9MVr6ZqZfpMWDc03v1rDyZM/5RrnTj+bXZHAKYIb4iOdri4pKW+mM5FMhd
4LMHSv1nN8AfcZMODA6emRQPqANtQlapREtkn4ZNI/AY6YO/EVbw+0l4BIlxtsF3r7E9e3Dk9n0o
GAe8D0f5Wp+bcaR9QUoiCPqX9K69W2qN69lpn07xZ9rgMx7qyCOc0FMICAyEiPepQ03MIqycg2uo
NQQWEqSBtm6EeggN6XwV13uSDpOy9E4Vk77PpU0Ju4pzEjli51bfOIyWeYp+ktAMRbBo6G15iioz
Lf9TJXztjVw7PJ5EerzvO61QM7Bqeb1Tfglv4SatlSfmEvQcNx0gYlxnOhr6VcaQSQ3B4jAjsFiq
uFrEUO34+f2Jqal20gANvn+rcEK/8dSJIJrHnGyqbz0mkr4WT3zoUYydIMahLaAgmOATbws2WQs4
UEruwXq4DyDpTGoCJ7ETQwarSiCdXR2wDk52JXiydlzdbwb0XY6PCHSA93XX7rbs7113ERXEL2Gk
V4wuP3mVcRqrWN1BwU7z1vO6THAlWHIc36Ox8pTJqGRMkqIa7G/qBmNh7Zu5AfhFygLrAvXuCM2L
kp5ibKAXD5kVfLIqEKkx9VCihq8VprmK/4KFHedA00K1+zVLvdJ4NCjAlinKbODXb2oqXbU8QFzZ
7eJn4gj6avdBas7HSdd2v6nz5i1h0Xw5trqR7LRiHBstTHlVJU2k9Bd3H7hLa3shgV0eLWiGCK8f
Bu0j4zuzZHqp1AX8h1n1BqRajTSgZuTzaQDTIjApjjHt7B0lICdThARuTJmAUBrxLbIso9Wwo0FW
bQcGO1pr3yw5pBgWBgICeV4Chb/Xh/3LMirhGrQ5GmMlP4/NY0xcX/cGZOoL7CvD0JeK2yLae5ZZ
WJizT2RPB7RSm1ucG66C0V3X82zemJyQPcewGiIwsNGGzxbJ7Zvaj6uqHvs3/+W6kURAkMfrZAph
VAadIwrErQAK1sFYQHaIsJ7XyZPfDfEB/p7sbG8srQEmWRub1DYySbiMNDU8GMIpjW81XxfMVCgQ
PZFo+Giu/aNkNJSsl5PqK+iSelPyrRDKhbLT2hyjIlW0Bpot1egIGAAVjFwQ/NmQ8L7GmzRE7qI7
D9nT9C1E8LivHu9ylI7IyDUiGptGyg7PKZusVQxPlFJh8DRUOkq7Xq8nynepo9ggW6PSPcAqEygU
KuCcHCqyvlfI0aYNBu2jovA7K2N+VMMCVEv+IrUhvlfuWPgnBdVYKobD+VINtYXHv9czKXttbBDF
nlTtI+XX2kzIxlB3uAkUVGnmg/qOwT2wwaSrrVfNcRf4LUhFX+Wihr0ti5EVIACDZcRaPd1blygg
sghORnb5WrehrPFU305zezBb2YGwoVG1rpAH0xR3k8FxHpao+CcbMYSWAHZzao2Uk6Hz5JcfUztP
G1OuVLlrzATyVleRk0ToKtQGzNO2fWZlUrjPxT0wC56fqL2gnMkAApmPhIeUMny5YFe2MVIx4E3b
T4mjXE87XtgEzSjJ23tq3kX00bg/+MQ1crAGbiPp4Nv9VquPi/ls1lUIj9H+sYOasBUeie8wwJl8
tDaFrzWbqQCzJLsEz8j0dqG0eoMu7m1/l1zYRH7Wr4PCENR2i3jRXVSrPMB+U5yc5EXWRLtBe758
/BDcdF/HLvxdNHAOxKd//QJMlwVmHcXlBadtS9Qc4B42309sjKREdX2spIF1srDiXZ1g2JdQ6BSj
nA/vf59W8v2C0G0BZ62n31H0RVKzPjFFrzQoNo/9mBxK46ay+bDNqervvCXzywRteHbxaHS4sFau
CPaKZEl1iVJpjgfvvG/iKMQxm9/E172GqQgz9nnyraDwVU3KZYKnKwJmjlQKKisVezR5jc5mc2r9
FiwNItD8I/NBnJtlYE1EbKBsgRW4OFF9KXuAfhH0UYK5WS7244fwKADX1iKq6lz5TbY7a9lGzC+z
qRrr3eYPpJgLerW7Y9UFFoMeFA1M2omIrACfR8/01QrCQr9jhiNLBaDL9CS5LDrLFJbNXDXkq8qb
HB2W3xDwEmy6l4XfmKtccMbNPVN05ZmjJpc+tnZxqVzpuBL9/u1ii4HGJh++Pr4rxLqTgKEMf/Hm
Vz8IL2WId9WurF8gxg4jPjfAtk7L+p70zSrNREkjl03gpR5rV7iiO6vsNAK7+Hbh0t4csOMRv5J5
a2PNj7zWV0uaDl+OvKBtbMUWtClAwV4n8QzFBJb16s0VNRF1lt0+QSfG0RIDAVQze1NwPQfSD0pi
A6COeX3DFZp0FmMqcowB3FUT7AlYzDNiOBwv/OyZMO4+8dmzVKPxQ8TOImmnedaLNHn6AfNUFx2Z
2K2vPknPvij8jBJNzlXFDhzQulp0pt8cORWYTB/4L1rDCRLCz/WDGDVRkXNA2T0rHQzmC2rGhJ3l
xBaFIV4IjsW1Om8eG3YF/rRzFXb/gjo+YEWxguy8HxLEvmKWuf30jTyY4h0s+1wJC4ChXriXRutY
Tv6Hr3giz4xEZF8Nb5dn72S6luxoQ/9W8Oq4HKStqMJ1vfxYFMOQorA1nsNfTOSwBqJZX336GtvN
vsCRhHM+qhOTlR/C2SM916fUedPtSpxZ1OfJDY5gLNz/t86ul9D26sBuBmc/qQ3SJNjZddnULLUR
G2YFl0OpmvTRRJV3S1N2T89soS8QoJCArzpmxMwZc1XU9hEVxH5JtJMy28ImfqyrAPX/68I+8h1i
19rLZF8HPG6vB2AsitzuxUtebX2YBGB7UV/CIXbkpiP0zqVfsFScPx9e8bps39JYWcQi3l+aBpyS
nvp+IHpXw7qi8EzvNUkoTMRI8xou6JPq/ojbCIbW2SKLujmRLMfvRMH5pQdt4E4KKJodU6/sdW+U
r5oEauRiWz9aGQYjnE0ecYUBgl5vBYxlqZFirfHoclunUi3nADQ0reILFcl4N+z1byx+DfJ5uP6h
FD5l+2G4p8DERHYHBUIYnxnR5detCvCAU9eLDliMO9EsyGz6CLVoWFWWH46etpMt4AfdU3T8Dc/0
cferhdtOPivHsyAmDgB30zMk6hyYwOeHKj9TcHO3xoiXVSyLqfcWMyef/M5oERQ8dRMxdXleDTHz
nfv6HTxLS84gGzR/Bh3dqLLTIFsyX5l2dj97ZQeccSB4EMI67MUUw86VGhELEDj3swDKMNgswEQd
879+Zn4DzP1ES/0tDZk3dqqXS2hA3XoKiVwYae2bYKGk3ttfMnS/Yd6aybDj3W7IVO/ykstPQUel
4qEjZb7OuwLd3yJ453FKuGHiiuk/0+eGA3HtBuFPJCs41eIxZ3Rjm9lmN6eUZh5IWeMZYNXnzIS+
tVZ6nnmwXFn/CYWXsgSe/6QjX0hOQq2qRO/n+bqnPFaB3kiMBNy3+WCVsqkyEq95TcgUVE0SZYhf
W3Lu2ZuHLNlKbC2Lc7XtoaXIhDkHVbIB3Qy+QWfrRMgQDThnjCpFukLyZ5sK7r9JgL359WFuNBmH
c8wecG+ArBS7QwSnCnVfDQd32kbmWM5Pxyxrhqe4CJSachpdGH05ypd6qAEUCnMKajI0UjjtmBwW
mq1yYaDNjxsOb2LABUaPZuEYHG9Kp8r++PkkC3A4At2XHfDybI7MxPXmkOd8Cua8lGFhoPwzmgmU
bmUj8Q3SuPMlKFPG9tXGF+5JAPO9as+8hCNAo1h791IY8VRBnTCSHc3zWpv6V1wh9BN2MF5Xx1Yb
bRkmD9NEPtVqcdFc/XxnBZY8ckbrS1KggXaNq//O7+oF+0PH/4VMARJ8IioFE7p9gB/L/Pp0hECg
Klpn1d4VdhTZZWzotjFTxO3dCd3wptT3MfXB24o3irDHMpPayhCzEb++HBqeXHK+/+Wrf42I/JmQ
ZrdqIgaV80zphD2dNzMfifmM2VLhiAqu6I1sVYy6CwoU0rPI+oWxM4WH9a2imHk5nk0tR3YfAymG
dCH7UY6qFGFLOLE/UdXrGv/PJQhb9ZG6YbsXQ+gAIT+mZH86EGw4g3VUDcfAPuheE3+5mMdf/3MC
epbA6OzTddkIsgX/8mp7BrRjunnfYPsrOGAZW5Ui8L4NlmOwTJ99NkL33j7MUrCxeD2zMlFQVGC3
6v4cEPLDUem6fG8ltEK0zHaOCNU2pHrhQoO+aAhPCeEmsTrJh04oHxs7zAgRPN2VQm8HlULWAw60
fULNvWstzTXhlND8S082Ry1UvhtrN+QyqkUI6juRT8g7fitdWCPwXaqrJkh7DoDtfnFcLqoXyWwn
XyymswRtWFkhQ7B9MUrqbuiJ0QpKkjglp0qyVttNwzG6Ao9taEw6CL0+cMJ/G9H/Or6cqYlb47tl
u+KyTjby/8B/jm3aqrHOOu8Ha7/eyJGMnyniasU8Y1JanwmnUMnpxBRS19DVyoSE31yoWIOVyIAY
b/yhOIVbB1mm2OTwl82WBfGcPJJXg2P5OeIo/fXGvx8avvQXLHkiePUveNP8zpV2Rj6llbkc1TZy
KH/99I6wYFEMNssaju7acEns5p6+nu/TtXIKWXp9M8SMIm7MBUyqwNB9tV2k6+WtYuPf+Nlng456
0UCJCLDHlOKwdstWoSTRsBCbpqSbRnQHFcmlexXytMjP4mCujRfqHA1l2AiZYefQPxG+88unMak0
vSOWOFRx/h8l1daLzGgcr94RE9TV/PqQg0ijcg241NGJnK+nHtTBwTOmcfzF8nZXKTUV+oInhp4o
F+moQG86EuOGTHgU6Jj1RmiPiPVQ7XmvLS7TQihv1yK/LJovYJZFlN6kG3Susj3Gw1FEvSgsrdUw
lvXM2Dyx0hw/MeS4z0uWR7oiLa69PBaV54jWVwdoJULemXoVbgsSNyKMAyxEzx/gr3N+XlV8XALu
7tE3kQbO0h1qsnEuXXMfm+NmDvay/vFi8Xz8UolVplHlEFWrsoRIXRezdRzumdU8cUoHR66Zh5eu
pxcA35p0YDLMDTU8MU2ixuuOlGz3iKq4Qz4/5lIFS/ChSdoENfbSjIURrss++tTG8d/3fkDGGTMW
nQs3np/bOu32Zi5Hb59sWPHQzd0JdUVUpoH7bfgqtSx4d6rX8KRwS4BqrOmHCotIW9160J17jTVs
MP/z+kle5wiaF4NQcFOhUhQ+brQesrwygs0r7H/5aHOpaeJer1Y6BfgAyi4xlP6uRCJJa9hQPubL
9ppnyAyqH0UnPdNgpxxbiriK/2kd3soZC41JjyO56K4WF0GtmX2AlFC58Qq8dkrXR6TB0qdnMm16
Pm3QZ6ZpQ6uppjeCcrlnJFk7Vv7lhUv2SxNNchXgW1JPzI9R5GKPGd//2Iq4XP7hVmqRVgD9E8Lc
40oktIafvxMMT93c5s4g5vOLNZ3duDJZzEgf/yXnb3WiM3L1x6dWkYeagh+uiqFfedP7RGhou7Y/
BVoJ5YPKG8kqry6kQ8/EmWlBFgVjVXw8hboDCOd6qBj4tNUWcMwDWPHMtUqs7miGyNcMMa3wlDZ1
iCSDS2P4aBBCVrWwHbe0NS0AEoI/yrrRf58+k17dr+Xrrr2SyoPGB5P9sNvaFItTjW4Ocy7v+NuE
D2CWwu5YpMO3iKBlWPHvIAibm201Zn1WTWCmt8y/sLjH3SOf0QVpG14AEEsjtLl38ZVgp5XSzinn
SSbN0sbxp8xU27tPbbmeJ40851Vb7FeiOc46nXR54/7BzUW6htuJ10Mbhj7EeidAKpr+cxmhB1iE
cBh9Ju5Lhp2FrrQ3ajM0lJ0OrDbvGdoAIR8yTR0WDwgb+q50MH1kpoU660EaLew5B5f2bZUHG614
qrsMgTP8FLjziEQXBPbrf6DbLvSnHKnxInWTQq1jHEiQr1UF7NMYrLtg6AmVfM9Avz27ZGPOAk0Q
ju60FarDIpte9MH5Wyk+mBgGTb+ziEVTU5KpTRcAianlshjUb3ihsrUspURkXR5t+GBoamiBRmnD
KNiLtaV+++nSDVoKZG9Ds/ynPrvYgf75KaC6e1v8STcxduQx4eqc5Dn+3/LuZwxnBz9Uor0yjnNs
nKDsCHKdhZfBfMHUZPhPxxyUeQpsqpywgb+qQPMud7wveC9Brfhfos+Nktd8lllIUkXM9ffZeTqw
4bg1qL+5jAXRxVLPZdOX9yHS1hD8TyUUmNZDsbB2lC9r41vTBk1n+QCw5EQ3p74ihBZlGVt2U2mm
VgroS9bcNNxa21BBY50W8EYwI7HMwLLkZ6K8/75rUFm8pNZaS/tadnByxlOaSfKJAfhSIJTKQJVM
TeHw7oVp5/0RBbj1jbkcGSOMuTvIXmE2QOYX9RgcfIipAID8YaXsx/kup19M+hd2ulUsYdVryU6F
qEezpahSBYhDF534B6z9Ug/uUi+xqwOeigNqXBKm3o0Ks2Nhm/XYgIlxBB5q2BkXRQJOluROUag5
TC/Ej2S4uFYsn6vQ00s5yz0vkGgJlMpSnth48yKi1hu0KmB4/44uGdYfhRCvYyyXhTpyhu3JBJJC
YVwWNcGal7lFecmol3QVVFuMs18Pmp4pI9KtHc0QnGiOsESTsLd0gQkKVm4L0dQNc9NirZtdQr6W
MIshYDo8W3NM+Tgfkuam9DAQhZg/UsjqvUmEvYaaBht4fxJNdAPiqO8KjxVL2QdgJtljfw5Y7cmE
GwSopNNZGH/6AK6x4IDIajL6dJk9TZ79dTLFKHpRFz8QhMCjaIoYcOCvoVdgpthO1Von9qmx+tA4
OywZOw8YnSdv2Z9RKR56tq0bqjIOjAGKk9Zpqv/v0FJMmhm+0aXlYsEoaEr5HL7Zo2GpEEUJ8e/z
2+hVXF552Ja8zgUX4czTFGp5fyPRg8B6wB/FjRtgxq3lNj+luqljvDsJAZLAgC+jRKNPF6SM0O8A
Ewrqf5rabx4YJEp0AXRO0m4lw+poSZ07bRItvOUZSmKfDE6MQJOTjHYP15huAsqUqQ8Zb7Maad8r
+JvcyqmehsFK9QRC8wPz3Rhh1cqQnPfbKUktcLAEDAajINYvJE9/FRMZtS8f8E59J1KW6VZssn6E
0pQYzocQRL6ULTwc858I1xbiZyBsURC+8n131wPTS1Pbw/ky1zn8mXvDkY71dwHyQtKuzwteDNQQ
v5GqNazRxFDD3n2NNAC3e8QvQTV7chxPGfhTGwy3z5iJTPxs7s8BIusvHvh/zOhPAP/sUo4u3NGf
gxL+aN7r2m5aFQ85SgaFVnFqGJsH/bP0Kxroi9pS36jZBVkdEiI//uoX7NvyxejKalxgaY6AW+bP
yNSFiya/R0ubgvJ7P0NztUFNLCWED8/HIp/2jn3euMaqbOXWSiFswaHxfKyS8f1y7Gdmz59uo8U1
aePSAoQAipmrQzzxvSshQTmYgER9FnAnlPAeTZ1NErfJe4QgCXuXnYZDHwrxtvXh5QtQwlLioT2m
ZYK0GmK+5HpmUDEIyThp6JZgubQQ7AqLbDBVqpwMwVfsY1QaC7rZ6arKvED7UYIy1Rfr8VcxmPG5
m0MqFZoeX8DdeCqIdEv2tef0S2HqGHSSi6WkEhiURe/X39O5Dy1LogCD83ztOfahn+oYhkRQpdKE
HDH3yqXxiwhQUtgR+WogmKEyXaWPEB5F3MjUe7eXD5wMJYLPO4W+punyrz5+IeMKCqHz6VTRnxg7
ARRpcdX87a51K9JBmKE9iKPNH7hbWNQBNnr58k++jqQGwF1xb7RNhB25hiVzwLLBOvzlwiXTFvwv
TQncRF6/psH06TeR11VLgbBwScKSJK9yPwJTTbGMWs696xDdJ3YLHi8swTjgOITBM6uuHIfm1KnG
hV1Nj+BEdUVgqWuNBcQlcLB+GycG/f5DpHL5+bZ445vuZisv9CVQZIwEnCvvFMfcoGauv5R3BAsG
GTuatWAl/AkbcbNfSYYvAqrGgUJLP+Q4rezQR+Wog8Qp0h97q93kgk0Yi5K9hHXpG17wGNPtG2ee
VtbIJZPEAtd9ETjL81fL07nlVcEpewouj1FyrfunzAe5VpNqk/NnOsKTL7jdMnEVS3ahSOZQDtC+
+r8gwFQiXUFU5w33CQgxqsEcNaizdepbSJ4/wQse2Ci3tEUdh1GH4LnVXSc1oX8PIxVkXEXZHqXf
r64RmleTrYNAbLCCCIa7lAYg+w+hQEYtS8fKAq82YT14QR2M9yUNLNWJr0VLlpzHHNLBvvIV9WmK
hGLfj/GLgdeESBV0wvBRcw4ryKjBdQCiegJkLmGWDaIcxSlUepNyx7LLxqsaHgzClXVFzlKa/G3N
wV5pYtrnS5s0cOFzcv8B+DgpNZzhs2D445Isn29UTgprQV+SaY4ws0OHVHcUPPZvesaPe2uTWdGS
7tptiqDuUEaYSLbQUk97B5VzatZwjYNM/XKLv7DqUmr4aXTteF5E7SN+zn5XQlYIJx4xPy+DJ1js
8Sr50SQ64WVQV3q/IlRPdLSQA5oQF6GaoVARp9wcTbq4z3xi5cTt3LTl97djnu1JFIMyXs0Xm2bz
IWEzkoj4b4lpVJrpidHPzHc4vgDKQzVwv4JaI9IfXIlU6J19+y/nqQ0a7giuf+k8lKsI7BeQoLGi
B58SAQTPv0W2Wygncc9JTsXRMsjExNWgpPsfsvUh/xSzCPbK7jut/Sc1GWCai+mHTGPWpJcrdfE+
VJzDnyzbAmkFfBQ45nhy+urvR7nzmlKEARA/7AFkLGDJosmSSk6ICHLBA3oJ78zlTgprTGZyWIHO
s9VgqSdNN2Z0SizCf6t9mZzsgoZWmFKEb6s3bQntfn5kzQUCZyIOu9nDdHIEs0vtWBzSpHmThb7g
6wLCPcQqV+YrRKlkLbLpxaz5DV3ls6FI86R6XqDycllne4hKV6LZWGgy8uMX52xGtnxvXsYlW0rY
LR1RgO52udbW8FrlC2E+2lGkYVE5FOVj/3POAfGnGdYx06bTYYFXez04B2z6AWJWjLBXUbNgK1p6
Gyu01YmQv1dwilv6Z8qTnIebGNDtMvipcvmRqA6t6CF+cmaX06B8QXu7/xEJ7t9NKOmfuHcQbbxT
OLoiw4kcv7blm+jzdjEUX5NCFLK9ROYEX9OdEfHnQwwuH56sz7liyrTCjPobgzB8RZGiMDSxaJ0f
JT+fYXvHuYepGALs3oV1nEGEWQ1OkVUvltGZKpSRexXOv+xsMV3kPifgs6nmss8KAkBNwJ+W4Aoz
r+TLWwKIeDCMmt/1ZKR0TLE/vPV8WCbyUBZXLQ6JlVjrmzSqf1D1EZqAJ54nAQxaNyi1iLNFG6+9
FUxHC9hj/eTcfb1tNibbJZ8X0oEhlrNvfyieGfycd4Imqj7k2yp9gFGgNxRBPBYx/7KdRfx34TQm
IDhhGlJoTE9w9kwdVf8piXBpTnSZ76pSiDWY9G3EFvhryEpk9yR3by9kA1rZvprbwkAhFSfEfU9o
qvMi2t0147JL3qBovULTm/m3Mobs0HO2PcXHu8eCXXnlUSyPhOQVQtojXbfhFm8a35rG95+uTR1T
kbML6pmOAwQjDlm7qLkNMeDflpbRYaa33QE1DV58WPC9eWHi1G/Q/1Y0vS9iXyLWF+FuCGbyTFZa
Lyfd4Jve7bkLrcOt7aPtc/leoojWvC5S0RCLeJz2KulhbZ9ylMAM9a8OP4haRULzf9ZMzXqxpKAF
FEgFFvZFYO00TCKupoJ6MCHQN0c9IXyIgN1i+STQS/TDnVrUUHJqnJz5p6A09OgCTKv377GY3Z7j
59LTIXqzNt4RtmfU30XMBai1RUqUXKcl7eM7n29VBPBIZDlgooXpAXELWqMnjIW+v1/YwdcQhQdy
TaUVWC0H/2JnR3b/NR4Gjf+YBHMygMJVT6AbSuQQisE0qnJ8sElY36FbVzzdqBD07AbLen5kqBfD
8sfJ1EfoWEvke5c84dF3+5Sk/yoe7Ax2UOEoKuQRpzkxr8lst6Bfq/Sn+0dMZl872JFpY85k8NN/
QThVxItzJvoIoynuX46LgpmmJs8bjGdfYw0lBK3VlZ0oslA6AfwmXeofzSJtT6aa6blwlujF5jNt
3xe+UBdZWqTn0spV8FLRZNRbRNAY1ANAzxbmZixHbuVT85dSYlmBgzUFP9aIK57VvqErxtT5Y3ZR
Dxgluc7jhRyXiHXlxxcjHH3Luy5stEm80Ohl/6sQK2TgwBZGx4uqgf/EHlDEba/x8zA73JgGvn2G
+VZSkHI608pOuqIJc4QVc9hsPhdzNOMXix/DYQXY1joJD+z9wzp8PBklIxX8+v+tWBQW15ZFOsT+
I9JOYNHjTVd0AL2YrO4ksqD6UVY5eS7tbMIwTPEdpAkFV6L/ISf/dQl0sgmO3kKzaLUnvgE7RmWw
VlG37siWjzLwyI4feWOvqQkoBVh4VwqX+7DRU4NIlnIUNwAs//xp3UrPHef7gB/dXgxxrno4Ejg0
g7LjGuMODSu/m7duM+GQuo7y6SF9s2glSBLS/coauOvLiuCd9/qMIdpvuUGHYny7c/XGYowVsNJ7
IzSw7Pocn857UIc+U2NCo2RIb3ylJB+IC/fiew1VMEBsdsK7gLnQ9l/UplTJX8byK8G11K8VrVSC
zLBeqyxcnpD/bz4yv6+S8rPy7t/ZGnInLKdSw6SdCKFa9m9MYjADVehqusn3eage/27inN0OcTGc
a6cI+LsyANlrOi9ruNgwAGHw8MATUcDH4fsSD+/kyfKrkRR0Mz8B1P5PLV19HUoGCiprCn/hMQtD
JI5fXr6/9+qLUd27exyPjfXsubVYZbieYhF05yH+bG+RzflsC/yVyTNLtocVoVKB3+5XF490wEGG
Ot84V54AEAhMzTn5Hs3AKuY8rR4pb0KiciNSlfvY3CkU0gBO0xowvAyx1PskrXFzD7byI1l/Ns5M
t/0p/lunnDEQdJ/EYsmWEZKQDUcqwAwNdy5R0jxzCS9BHlbfGnOMnOzdOd4wy5qJqgfVg5fJ/CMG
2Jd1I9RCsAV3nlTRwGnCnXFiWFW+2fGHCgxr5pf4bsMEDOwRguGbXZ120upel1l4azsOm6Ors8Jn
22fEm6ZSGOBRfHh4KXjd1ZtL9U9GwxwH2FwVmeXCqwbNlEypbonFsKCX8IAVG8hd9sZc8YSMtrC4
nWAmMUHLXwoudOFamk2FOHrRgJ4P+aBZqdiehR5kCscrJQS2oR/zN1F076frHDUHPmkX8jPTvROo
UrlMzFDVF5zsWl2mEnlFxkG9Cj2153Szj5RdbfI8DgJZqC3+juohKJP5LMq8Mt4jYEShixjiIgu3
IG5L3R3ZV9aebEuneADXL+fuW0smSsXmaAV64SrE8AwOH/VJVZhaPmno/1O2QkP+rRY73pp/qiL3
74w0kg5ZoE4JnJt+FxsljeCticUnDbJVGXYMd54527x2Q+vHG82zQcmp04ZAJlkhmv+LloxoMoCH
lW/WD/eZzPLo6ZE7SHBLxrRwSOXxq7ds01wx3pWX7i+jsJg4bAutTSoDirHx0BJmHBgweix18wE3
P6OdDKgB4hUfufVAaSAqPBnK96aPr9bqDfuJ/3Djvj8JsHsz8Fxojc1v5SEpxfyWDwD91EvgvfYV
BXu8gCUANpshkxCNIHKVXb5hd5p9vGmR+uATo0bKrGADsXaMo/V/J+459HZzSXO+lRgjhurnsTX6
oCjHfhTxMkjv1bvQgekPiVHHDTdi/p0IAiLpKaMmJJy6v9Z1AeJOvQb2WQmfS100ReQRi35eOv45
njDJwAUHO64YTb1JAHXZUeadvRHJ8OhBpIy4BgOIDLXGj8oC0yxp29l/i+VTZGpjhd+vLJrfmT/x
yo4gG1l9t1bCchZagBLGRgfCUy0mrIQ7W2SWOLt/x8+QmwKiJUvvsr1XITXExkrQH45k2vEWFEFX
iQ5e/AkPO5W5CrpMiyKEqMjMms5EMm5cO6q7v1nRd/UBK7Q6KVByww+h3OvOsdTJZ7OyObaPPAv+
baTwM8Yczdmy2HLLO99i+N5wnMOImZnZgExJO66OLmOfDzUo5HGiX5i1FvupMJVY7lrCTtpvdv3u
PdfWTve2j/auUMGHSdkRe/zGLYRQ1rA2T09eyPV4imensmOsTJeRz0ihLImtTYAHBAx2Wgt7AeOy
qs25a0W7S2LXaFdBvtmgth8eddQxmp7978emvZMB1dOrrL7TYZUrOGS/OC0LpE16CbuPWBHqxlnX
ImqyQuD8+9v1V8ZUtoqPgQi2HnLsyYo6FRC3j0QFctM4Fl9bUCUOOmmsd5aC1uXYcAUkDbZE7TAo
VV2VegKK5YwqGUXxB7e7U8kwtrg0rTfheCZe4NSCfBK878GcjGRTy0LpiglO7NbivQOKSibmCUSn
ifvgCCdo9g8QNHnhdsV+kC0/CO/1N5l2RXl6CsYjB+yGFhUeI1WgWOlnWGLt84a6PMILX8M8VV0T
99COrJ2ZfjRH9grZ0Mcv/ITq2eWusIbgXKy6lp7zCI3U092i7Q3Krl94avvAvKNkkJoO5chfGRtP
uSxa0sH7Bjo7ALfKH3ZkgdKea138MWe3uWATpUA/qRMlSPJgeCIIivtI+/6xrNqW2U9kifVEYNg9
8LpJhM5FAKcn0DdxKvJA1Z1M77M3Bvbug1QAW3C/u1P5NvGo5tiHn3IyjBmM55Y1X58cHVAgKasH
GJ+fygLTC2JqdVv8Bh13Rmdn3Y/88RrsvF5dboAlLhQV9BWnUjoMaFDjaM5BTyK/MzEkx3tZNJhK
XEahe5Sol8blvEnlRi/hC5exxXUFa7KhohScY5vBt9caLz4j9hcnD1THC9rx3179C/jNpV3xFX5+
Xo9i7MeTpgnfmzh7BVRX0rE3sMGNLCWI34xtHeLNtbPeGnOnVwllXrqPRzptwl4UsTx5Wyxdf0c5
4VoktF2zlwnq91LAxFRry6TnAgAh/8iWN4VBMSuUy7f+uJ6cNEnesXEEFi3mWhCARgvkaSxohTiP
YUhewYGxSCwL2FMcBs+3b/iXKwg1bh8/B0mgEbpWalwQZCE8QcbiHlpCrsnX2x0JBGbNGYqVz4+2
cG9Qat4vDGSx3Sp1NsL6nW4A6qA3B1XPpMfBmjy7tAITrI/wKs2Hd10gTbpRc1571dkqxb0z79Uu
/OmQBjbo7rP95IqFdxm+qbQzo5trFTW3JFVlbojH33xvglrFREstqm7RWU/SS17ucQoS8RnBaDnp
T6f16OWabiUeTr9g0xbCvN7+lFkrMNdyzrc3wTkKZZ1SViXxrFd5bGqnlkSLa2QIMs2Edo3elLMY
fk1eNfurIDoot16FOx7pPzTLGwXrva6eCXqf/93/YGg7+NTqycSdTCsnH28NS78JQvBOQX8IQwdu
TAFTkyk3cO4Krn7L/eT4/5j0sv/smQcs43Gcx1kjvQNluFc86MoOcuikN4YY4iJp1CbHy1qNmq4N
Tl+e1poxvQLepaf+SjueXxj419q5MH9jG0rELaeZayw4Ig6n7W0Ih2jJq0CYlt+C7lawrJPMG8gY
iGHOHaV7yFOJXWjHrXHX1jSqduox2x5ElNRvCDBs0MpZ43R33OqwZOmBix6SdtYUySeq4fVPfc2q
8blbRcagbbIUzJHHuyrmw5mRn2wkb0yVs+IaO/22TsLa1yHNExgA3aFxSGYhZWrK2QvWSUDKa8bJ
mOdmnyuWAg08Om8LiItLQr3iD37vxTcxoPspgtg6G2vdAfRFk9zObcYL1Fm0ZeD4i3OnDC2+oJ/P
rMAl8FnC+a+KSHdPUGNW4SIUZG2ErutwheURPkkWnUlteDD+HAdp7HQzId8SyhRFJc6OesLhvIVW
OpGmthv4kNifuy540CZGN45xovWJI8BVw36/lY2Vb58bcS41cf2F0SdP9Yk140nM8QOx/kEX7xBM
VTMfVFOTvaAGznl/eR5ZbvHaZIwD9VfNb/7zU4K/e7reZs8eNY86r2sXCSkeXTAeIOuWUJI4tbgO
f6fPG14wYEkfKyFbZ5nnUEs+WCL2AS/CzuKE/XkQllnCcy3hi7Q58CPpKjfQHBubPzFu3iyV8T5C
2UeGw9aLoa744xNPKXahxhGX+efafZ3xjoN9sJ48xvrf64Es4fA0ugnsYAPiDfdrIbwGRBozVWGU
TfIiM7X1FD1avp8cfh+9oWm7muVVwqUBm9NZbRu7WVz2fxeckgnT6ePKttvUIk7aibX9/Eic5sve
0FCIoUnFMkJ+ZOhqR8CQ+ZcalTqXLHulado807ZLq9FG+yV0VANASZcKCaIcmkCIii0/MMJNUzcH
SIkj4D2TwiZSIxv0aWSJ8ERZpbaJjfHQ3aI0cgSMjwBcw4EzHy6RG7io+kURvQVG1yax+WganfMT
9YFBRjYXTCs57V9eXw/HfVtXg20r/0cun4D96f3TJ9mdesIsOUGt54vix3oLLxdQbuA0bHjJfBqS
5DVPReuUS9JjmQAkygKcUxlxB6FTsPikRmoimn7rDw6bJufGkgmJZuT/p4EVHHtmW9m99vbhIU60
aqiXVkdlLvBajqFLUZgOZkxQhrfy6Hv4ZvjyBB3bZ9tSrCzcu/gWY0jm097yhS/pf3gKNXvfRDZk
P8/lxmM4vDErByRQPubmqVQUQDvqRdHd3iZbV/8HmZawlrctiyvkA9AY4PwkEhglYyM69HyD2BpM
Jaax1xdUBJXOipJMOkCjqJq3WrBT75UYUNmudFI9vRL+V03HLmVikY/C3psPq+T4NtESkFpqCIGh
LW/yhREylQAE56vl4An1UKd+7XD+fsNaEKYML19DoS6f7elxa6OIRy/wDGPJVsPJgFWoxsmOPxbx
jcq8y6vyY/DhyJ1uRxeyAtI7GECrJNDmWRUCiDY6wtxK+kxjJbqnRvB3+Q/DKoX4Uv+V1+2ikFbG
Q+Phmy/KzI1flxnQNuMaNBU4hzv9hIttzt2zcK2Faiv5RJkLYPty6ESlV0RVWtkGMLrhXbIBFocW
sz5gbQ2Qn4SdL+PgZ10QYHlsfFj4D+wV40g+GrDt6WRtW0gtkwJGchlQ9O1xm34visVgevCdV6wi
hWdhc+45bIxEOetce4dpwtKss9h9uITnUlyDonuiUyD/RclFv7/jI3G6ZYzbDJqaLFhvuOoGI7KT
fA6Fm8PBKh8Utbogr2RyOoD6ej3+I979my+30mZESR6GOUIiJIpIKiplylSFtNNpg8VsD12bQklf
L0RMcjgH/pHcUUfWmcCnZ8smxHAZqbw2mvrtMYKPExBr79dsqYIhK42df53Av8eX0kPS7EuBw9UO
oO8hol17Ucsz4KGEJOygaNY4OMmt58/3b6HlIkD0unWmda3CnuDUSkqvPF0MIvRNCIpjC+PKeinA
F+SHltmk9Lg5PtArxexqO3HxgYc+xxMwLNDyOC2vLzwB+0MdJB2NrcviY1qEZEdzlb0sh6g82M2v
PouKs5GjHDRJa5OGN1ZaIaaoLx75aGUAMup/uJaOB71c3GVoqSb4zhY5NXVBjZaJ/PQaXDqjfEPd
z/CJLu6B0dt8ueq/y0tVHRQ9FGNUEBRgjuOBg/Sck+txZH90HuNgoWsC5oJIr+NzOMXBp2EEdkBW
rPgOOJlVYNtCRMgnUlFsDeoaygoewx3X/PtGJr3EM54riEBy+1os6QkHrS0GzT5zOOE/cDBjDQG7
h315BzbvLJQ+1BPd6g/oJ/nX1zXur1Hqf7cV3ru8A5cp5bt47MGITsl6APjg0v75+xxy+uvlPYdI
9jWlCuQkjRNbGLHHvxXLBi4ZsTzmnFkznzVD9spPmkCIJM31QPN186F4dIWtaaYE+6Hv+WoKDDnO
uswbF44r1KoHjJtVEU+vS+Wmu60s1r15Tr3NgM0mVZit6WHvjfOe5hrMvniFOY6wpCuC5OqWw1gz
jZJxWGTDjImlQTYD9n4m0Ow8b9ur9oy3RtRtGmStdWGOqloZaSvy8hP/lmODwZkbEkCRa1e0VFFy
XUK1h0/cBQ0WO5cFk1qTCMsyePH+IIESpiHMFxEQr+3cjbIgqLM2CwqeTSlZH0xkWfNoTle9xsxx
S+pkIj0xWDX6ATms2ac019y+fUilU7VJbCtY8OmsXZilRzt9XX3yaHH0sVB/BGQEjL4M7RfLgEXm
e/G3e6CR+uHJ8n1TzsqbJD8IzmmcFC3PUbk2rvohVtbN8yU4XXsGka5ctZ+RYokb7SgcYF5EKqka
UR7u89XhvWNFSt6TbcuNum+NQOUatP4KvZrXJbCg8pdWvES8cHTm6pqv99q09fIKkX0ES2r9hm2W
Q3vBEE86YbsmTRlOWFT3RpKA/giRlP3LJAQ/TMdMDaFp2nK6cUeAwS2ghcgVfGNTMHF3Dje1VsQW
zUlZZBmvnDr7/gMRfPnwL5VpconFrt7XgRswG6rm0pcZTmMk014byRUiyJy3Qo8IU/2vDGipEn3m
r7CXnKpaQnQu4aBXb8Ey6VfDQlEIdAiE9SO9MLwOcKR9qLsqM6wg3CWMV9Ajr3n4UHySwZPd5WGy
iNtJdovV7ms59Oas6OFxab0dguDeTHqjGF46uWZgZdfbwx3xRC0BQj14ZFA/OOcyV9v0JFZxDKFw
mxUox3VZsy9+qSenNslBcoBcjgazly64QiV8cYBPv4zoP6hibY/Jt6CK3F4pJAev2V/qiG03pYCK
2/F0CIj7as3LwIi2Kyx+X56g/fjao6acai1/15I0QVJTO3JyC03tbuidFXtwuFIUQnBYcsCJAP82
/jQwnosODGC8XXNz81GQMV8IS7CF1LNj9n7K1zHTVVSeJsZgxoN49OxOL/F8cnCqZS2kUG1QO+o+
5D+8wPk9gZxwAgVrrG7jpsKYHtwRgkya563yt5GEdsjuw5SJD48UG1FUmkJxC6Sya+Wse/sbWXcW
0PKvDsrd3KVi5Zr9uX9YMfs8DtHFbsfwTb4oc/EsDTnm49yJ31Q5+vjTszr5P2wqozTbwSBpBhCp
FUsrW4wS0FlnUWePB60iGrqqf8w+/w5mAHKSh8FOo3YRgyhxz0c3ViARboTVf4sA2+AKlrtc8TQV
7kobGIO2TebyJ3uPDXg84bJVuQgmw5m0KmAMsF1CdDF9tkgbAlIoyzV+VlT1HjDD+F4jmtIksaaf
s64RJz1godYfyUb4nFLSmqpzPI60UM6cNz6xx97MhxsodHfXi/wMpuDcFNlz/cALUxveg1oeGiwg
PgwQ4VeqfmaLe+7wzX3km3lEuNQtd3oKjt35L2iR3TVjWEvBvs0/BZvCZyjzRZ2N0ZXXgAsGt4YS
Z2zKTDb9t99lvR3/X4b7Os+ltegFFl9iEnoDME51iRtZhdhK8X8LBqkQ9a7SALKAoNsI/SOngfdo
TARgaObXdK/E/Vj3v8ZFgn78q37arxQUgU+x6MeWCvdpb5UkmL/QwcGpQCR7lEP+8207Cl1wa0fp
onEXUt/OwI2+Ean8qhzlxtP8/CIv1WgUcWkHSV6Xn8hBHwKyqt3l05RLmWIagz8s9b6SpqSroAi0
qcK4BsRyxoag0f1tfTyB+SD95B9f1m38WGjJ223itm5wOlFy8h5yAwQH5EU4XAn/46suaTNsbv0J
BTfgYMqmyVa7/p79EnIUdl3CH/OrwNnrIye/dZvcFd+nZ0cM7RgWDDKe3WxOqX2mZpkVazf9V+JQ
i04ifNzXjIh1YiR8CdgSUqi7AYFSzwPbtzUixpnSt23D0eiwN9F7TzCg1lyqrcKeu0D0dIPy3zw/
40lSlUV0O234lBprI31twmalsuYt5Sg9VYxq/xDS+AcS/HZcdePr/QTIlrbT3fCyHxLU9QvgKmhs
Dk7ioqMw58tgqO+9o5YoY6K1Gx2CBcRpNJmWW3fNX8pil35vZEbO9hhWTvdXIuc9m64XXzd4u9OD
n1w1bEUiNtaz9Ulk8bKCuTvUL67eStNZ7WoQqQfWAIjfsWtQm1dsI3zeJWmvJpixtmL9vXmAtHIt
p4z8+q7oFq5JoNtUyJgOjy17O1aBhbmXdwET67Q0xWbcr0VlGpd+0bz8+1GpRXgm0hNLmavsYLzG
NJ0ap85VEEYsbvEyHoAuZ+pd4EIr4IyO6qlROYU96srsvUmZBsSVoZlexQZw7tpAn/QdCeHwDdAd
lg2x7nyrowkcOwv1O1JNsQz7EMh0L3Y64tm7WJ/msu963YKYTcTtx+hVPeqPVYeGP4eg9Xgo/zVb
n4P+CkJH3rT4pcxyWyH9NkHxqcn9Nu6Ot1X9kpTX/Mqd9JqihIQUq9zQhvOcJEQwLx7eUiJ7fCum
kLO4iIN/udl8f86+kFf4g7k44f4nvmaisyszuSyyv9fMHTu8WDfZCc/U5Xr3lBVss69magaMxkuL
JpCh4nBFfMrkeoPiqVfSd0DigLJlvrhv8wkncAoEMoW8Xq0onCh7G2eckDZSjGTw7HAvCiUsH+Le
8TyWeIX28/BdbSUDyLkceE09jzrNO8ui9Yv9NgQ8k93MyaTE2TI+3wVjF9pUvKHma6P5xxKqtU+L
iQaWLilW76l3yTbaauUUoAITJD6fYQqMSNHcdxqkRYPRUyYe1hng9vg4haS1uf/6Vvf8A9JVdmnU
hlI+rajXfGqCoaa0H33rnuSdYulwlD8veOTqm2Dr1YZfuaBrX8eIfhKB4A6pylVz7rKXSUyN/6of
dts0j367Z+aMQLZfGGPimhd6afHpdK2232f7mid0iahSQMC8dihIDWGhMn3EeMc8/hWMRn6e3Khp
vftjAavt4Ine4NQxjocW1wyOr0qdWvzd1E5AGi6rP7usO70cU1WkY0WNUUuNDIS++61jfuUMNmAS
kWujjt4MJhV4JrVoR/v9OIwrY4oRNhdA2U6fPFhIlbutvUVVz805k7mNUKy1qhPjNzpOvr7btZ0w
3XZQ6y/Q97LcZ00ZGNDoUfrWh3OKNIXuJOspbEJWN4iSZ5sUGgqVSsLMHHnPyHH7azP1I/p82mdM
OTLvavC/8Z482lzkTe55kugLN2bNW9wh1Wcc4MKkRdfUq7KNtXvLyvKILNIl2ADJtEt4AhLSEEm7
msSJJq1i/sbLW2DmPIgJip/SuC/ASFA+YgXupcR9TL1+DHlR/T1ANfPhEpH7LLZX+jX5u7Y54awr
02wDYc8wEfAqM7GMsRmWVEyVwL9SI0kqnLUznKtHj6k9oPHOQXQOsCWbccSCUEAtMA6DkfHKEEwl
PJdsmwCsf6srV3Bt7Qs12t5OfaSS2VqUlF/5M8DKbk5QZ7fwACCvt0yYA35JLKL5ZQ9oV3brEhm/
twhyCLjq/rtl1bcxYBJFDG75qSiLrPbo9ojN13KSuttvsS1sdAyRsUObLGJ4BigAhG5WstTuvKkX
RbjFwOkLH7FBp9RvqnVL4Ip9OmDUe740EeW2sdfWThgzmDbyvvlxnWbNseZfzN7ZOESFD5WnRff8
XS7/2fmu6+1NGuWrt6goLcJoE6jfgkkc1etq5uw1iAB0mcPlmhINiEpaJgYmM1U3qKMB0oNGg2Md
+W3vTUvROnw80WStJRRQuCUfTkuosq920kK6x69eE0tUJ6r5+8tpE/mPdVkoU4OKGbZ0wfM47a/h
Aol/ZeygSNjhXiBb/YEECkGFfkUaZt+1wXJ9vN+SORNPbmp6A7Of5R2bF6+qSwGMj37JT2hYiWp7
h9yBShPvKF2tE2IBs4EvjsJ0FmaSFQ2NAkpVXLvtiNPEULbODfbcPjCduBS5zbu9Tm9KWcq9SgcK
s6f5YwIGf8gIVOeo9KsFXXRY1qqDO5Mezh2Hr0vIGki3RPVoSSOQii7Z7xMyhc4Z9uFmHk1FKp0u
d/2blPm1KzYrHY2WwvqbK5lWJfvhQI0WQ+ZT/bh23CC0+d9HyxJt+e5hebbk5wwZ8Iz3rEEyrvEX
8NNRiVO3NS2E4rGwKLAo2J7Cymw3SbrWn0u06TBXyBE+/5j043xoi3tOCesU2/6FjLRbLA1O7rjJ
R4ooWR8agL4Q6t44bIHe8iJDB75FQV+T+uuEole7IuRg8VujL+Yt15BD1mbBSRfV/sTBqSYukIsp
uRCAMhEfZTswHzmJUcIQJ04xCOHtj6L1TEFbVq+e2/5IUowD38UbqSIjQycNhHBxsuHr/Spdr7pf
y0JbCg11eq3kT+l044QfFajCjfMAIxToHkjbytU139ANTI+zmvipXP79pfTg9iyDc6VY+AAgR2oa
WAlEu7dxE2VxVU2/dTt8RUV4nZK1VuzCUJ8cQPS3NY69fZCslJL5ZnptVENBoQS+fMc0OKpMyUJz
zHhzgVOyBvDcrglzSKwKJDe+ZnCfq6LuobPITg31R7R7GoXGcv77N21nTdyASuA46dzugNZsZi58
dK6e25LqntgMzr5mGplwpyLX3XDcGcxITbz+HHZepajkQu0f9WucP9IOEx8Q9LGagmKFr48FwfqN
MVcB43e5trfMp9ABcnQN2Hg2G+226vU+GR92VglAIrDjYtdpEFRr6+EbYmOA6fmeeGek1qKbMWUB
w0ZNPSA4/lbYJY0wTbEzKtNsPwJzQqXy5TlXgJmZ00ovCdxDY/tAU2FqWFEJWyLyH+EBMq8IbcsT
VbGs/R/VmvtZmk/uMdV4asUd2GSShM7EBWUWwXkVM0wN32+d3OG5gKzlJ8r3fDM+0kDEqKXFSjNL
9I3Zh0Oz8UNpKEmjErPJz79J3/u6xdKyBiSvl6DTte/6O0+9VAZP3mNSxgONo3bu/5dcstIdLq72
3pVAMSGO8L1/BJsMtVz+vM2JgmNbw5QhRjmxrrZ0S7fYoHXamFMs548vm1/KzhdulMGCnZ68DDNg
lWjeYTPLB5iCB+DR58PWcxCvflHVeJ5GQ0JHpx7fItSmmg7K4/0fwn/W6tm23bcCrnC50BsSIilL
dOEGdGIxZcbYc7lfIKKssyBO4p66h7i8t3wf4Cx3qTl4Qj+jHNDyxrmU+8+4iAIQohmtnX0mvst5
/uzWBuuv9oyxPbFIOyUTENWu/87OCRTBoWziePeNbcxDsJSpEjJ13QGMgZ3Cp0PPb4fvMX7nQG8h
7M5NvWzA5XMQO5zOXp0AT1RItr2STEonBvg5XCLv59LPPUYR0mKnIImzndeZQGS2UVCyr+xx3rTX
FJzwBneL3FTPdbUcwgCDLPppGRZwDuRbzo5WroXurPL0AfNJYxr56eJyzdazuvyKTYsdC9nO5f/4
G20LCmbfixD/UTmW2a/cfMEf1VJC+veIJxGnsiFvYSMPyX2P/tzFDIqGB9Mjl+wTYD2x6yTCfCzH
E+kNN0ielxLpTXIHCtnM53UDa0vbHwfR8k2DnmYy7orzLSzDx6N2AsvmvQV/wsMw8hJD3d9D2m2X
P4pZT/b0uJ6rFEep2wWH6AacO8I/Y7/2fg1TIZRFd+oZf4Jm2oYuh3Lh9Ny6kZJxwr2BiOaJbloZ
HsN9s0CDntezGbGFrIlitLTj8o2V3mKzgeCSSgMutKITBqFo8Q+wQGyF/DUV+MilsoqEmFLImgem
5Yq7RcqWXAU3r8r3FHvQwFE8cjLQGw0h6OJxU5e1uXTAqZRidpH8nKXErYHFzhHLlMawkQkk/lvb
owM9tlrAw6g5RiCW9VbhXweCmgTf0lw73CuF55pa7YVixOucEV+ysNOEHk8kInSWGJ5G4RznlMkC
CMtea/+5JvFtNgyT68tLkhqxbMrVM4NK55Gu4dESA0WzYpAFEDPsw8tWJTQuogku6pKYtumbIygS
6XnXZ535S8yQOl8QzqxWoUTQi2vloY0T1rjEbc0/9OhHaGhfdBFTgtTeSiSsWIR6vUvtsDFtK2yE
z859TiWAYipLL9Yv8mJlTc4n/UwuKfkvcmYgIdfZjI0yZXRyt7C9thobx04JbZ3mv7igk3xGkOTL
t1CXNWm24il3EOsI4RI22KeFTUW0I4yYXOXtX+Wtn4WIL9rgCxt6OR95vbr6e3s5vhPmdLUzX52E
LAc0W1MTw6TPB2N6ii7Z6XdiQy1UKBiOHyiskIfN5c68N53TShQq0OTEizLrQZ7Ax6XPcnlpjxyI
zSyt7N5OHX6bnLwqbCixGCx9Zs7ddffPD6Nys7cfdx6vBdwOcNPi06RIMxIEeixob7An3A9fhMuo
4oPbnPbp23aW5LxOOqHfIPnJtsPq0f0YdvR/C2lJ6vJKDq5CBMGbBUbOw8aphCvApEOODta6Knvq
KljVcwIjAGGORivPdm84rUBQJibXJ+h6FWVWrAs2B+n8CqqVAHkXM0ORNgBNrEDDxZcvNVqJuLDm
BnI60VUZDcwIQGcIZttQCaWEsFaygfasSf3c73qoBkx3ZyTa42K+1Km2cJH/h24ppnqfGsMCDzKK
VS8jJ+1F9Re7oghSZaeHZv3u4m0GNRJd2/oI8yLGs6nS6solBC4gwf0dxTPKnarThvz/wI6t/zJY
sBRBa16rADvfgAUC9z+ClLvUMRI5quG21+TuBX9vb+Lq1s78jy/a+ct2ML4LxD+gBDxNYZo26bH8
0ipOb4d/N9Wg6WJXsnOmP+3vFgSBcKLFx9o2vfbKjkspYrDMjAjezeWLm4Z3oekVh9fSU0GP7nwV
MPr6X9aEkRVVZZU4/MdwI+7sYxB/lnpv2aawFAb8yVQTrjtVUSzAzWqszkXdh8/2c+Y+VTNb2J47
Rmalj/d+LpxtLg66c9wnMM5NlEKxE5X8wyrB9Bwk/sy70bOXwOhcQQFsJiAUbpeU3rNxKJeNq70I
7adnRrQx/+Bcc4pdsc+Eso9cmL6uicAIHdwlSXTBaRYxqdMa3tyGEPEDo7EsRNMqISrJbThLvJ81
BBIMXuO8pzcRSfG0qSbIKqJY5qHpktYVHm7GB+Lm1gbmKjB3BbJfTT4JjweIOmnt/sQiHq1Tvn2f
ADevCpk+zCLIiCBitTW9huC/z8/j8S/Iu/r+TJuG8D0fGsSom3bOjDcaFJdz5H5vJ8QJr2j3Szqi
evT14OSjtUtFJHnB24pWwjFdOABdpTz87WAkzLwZyHJoFy4OUkiFf9ad8pOESZt/A5Z2nAV/VSBJ
pt8qV+V6WfoblXM3JgvjxMgwUEGsn5qPbUbXiNcdE10l0E8DzH1nzD+GaQsFyFJxnaZQcD5AVnU1
F8RLhBR5C29pdGLQ8gLQsG/GwFF0qz+A1FqHo9joJOAvXRuWX5Ni9KZsd3KE7f84CcA7VQoFasFo
NaBIDqq/1n/CFfh/HOAEMqnerkpBOP/tI7BC8f2EoGPsnsJhDU1z/xpwEcyiKGMd58MjFQvVQNQa
0xMU9NBndZdGA5RlT7suoFEwMMwxOZjhjKEFyJTPK/YXkgLwroHTm1T/H9BTQPUviW5Wztf8LVko
PoH6CYAR8mseJMVMRF5V6iw9U/eP3Dk76p2XPNTbEqMWnHegbMC5oPAwXcREVIeJwMQVLuSeILMH
vAprC/in0KeBjFsKmOr6N2xDmp6/VYNCs09oFPTN2mtZEokxPFPUiKbdmSmPjVX07L8ifq541kaO
EiZypncRASmteF4f9APTVWXTQJWoy55GpSiEIa/qtSbKDKhhSw/7x4bTile7RQ3RVdtBhXEoiIcx
99kKgwUPpjpvH/h3ZUa6lnGerhIOVUdkP82sBXbz9vYRQpn3VB3yQi1TM1bFen8UK6nm7VpmxXMd
MszpZtDQ4GDxhBIZ1NOZesUY1FhcoPd04dePYJJHGpdtS1Lu89SAL/YIP44sRVKmTUAmzw8XQ2AH
qJvgRjeQQONRRuWpZEBP5nyzAxzeTws4zwIkLuplhTRSoafJ01agLtSoYjDVofCMtsSReixyZBiy
lMz+t4zPTMIGTEKk2GWh+cYTv6g/W5cKzyIzd1Jx5LMuc14KFZ1fOIvSruycqrNtfz/+xDjrdm/x
Th6DXcNCF62GCxcOsx2eexcAS224e24EfH3+BxLEDz3qSBZ1O3WkMdQEddJ1xuTu6G4jFYav9xNp
reldnsiALYTXJK+rrGbV3pEZsiJBs1lceXOBYBNq5TSaONwdlN9p2DEhHwsJ14i7LL5ThSUaqy6U
xhVGDwa1lcs5MZT+3TyogXwqqUpt688G+OpQF6VeSjgGxMGVNLPpbTjZFw4w4qWmxLxPqz486vt/
lJ7kN1/2rA4h55ZxZ2z37ZdMQhJzIsMCH9lPvUwt9tBvMrvxtOV/eabJH6r+bEDhp4TCPjDgkpkx
gugvAbg6J/V/ocSRVuIUwXS+IEwy8IN/TsFgaxlM5vnogRPsF8yOF6gYqDf0cihWCHwwm1mdoGO8
Hl/DGyqPafMERg86uqRLNtfkdhsgrWot4IYxckxO/6urfecTJFCQAWVHoDyP8Pb/irgb9WmUJWym
2FdhsPvXmo/c5X4NtX6mzbCsYRr6k1byHq14a1giL29lcI0qHmFz+RPPYjMD1XEx/iuIIeEaaOnk
5saJYOjkv7BtZ90O344+5XboHQuk5D+HTz6OCNmoy1p9Vfhh/e1PhEkNvqSe+klQCyjpPNOj2wT8
ViI0+lXXnghbmvf7O2YRnEKQqmarZOBsFj2o0b3qLXFM2pyJqt1SvXAofCxD6ESt8ugA7DdYwp3E
3YHh4EYmkWHPnRGWx/tegDG6MrgHIyCHinnYM9GPZbg0EXXoAiJFpQinPrR0fW1vTUZZcFGl4Zow
EFcPaWJzCECnQVAJ4vjDcSleE2yDcQbwfCHVnNZuyF3SD5N/oIJNAmiNoXaIf9NGXSDYVYT21Y4a
psMLhJSRf8ewtBvCrP/FDCaCmw6nd5pTU5gN+l4InHH2kq3THNKBE7TBXYeW7wLBDd+AOpb+kKNO
5F88xrur3Ay+wp7MTwftPkWO+9nI+vlnIiRHxKt/Dqs0IESzfmxcBh/FTqVEq7HPmHV1D8vKxNE0
T67CBlsxwXpTgqK2tvM3JgcD9d2IvOkzFLFl4fdmPtPyfiy0QsCbm64q2p6L/KpQL6R22xlkMXYe
KKPSiAPNWXgvq61arbxBx6ZQ/Pur50DlR+9SZfa3mCsk5jnhx7It31etcGMzK3Q4rES+WAddn3wU
wDKnVpj8WxsO3ymoQaZn6bgfLHK+xLgHwW8ZkdpQez4oO1gcX9kayw/86coBpvwv76zP6q3LWkuE
JCS3TQCRSwiX2t7I0EC0msbTw/Lw09mh5Prdnyi3YkXM74qaY1nOEvct/OZSBFhEdLvXreYWvD16
sexYnkDhu908rABKs/BnGuIa2XEjU7XdTfj+AVil8yW5L9ufwRK6Ub1LsKgpFqKNrEgwLvB7zCfz
7jClgT6RpOFANeAzP11FKt60zR3BPC5UxscW386dQISYhejcZlxnsLooCp24Ayqx3RuYcfjymuUM
ch1frySu6ZfHp3Ya5keTlTkl58rimKNLScoNK5aLvMjom6qeREdBVpNsw2ulIZPcqutQf2lhULZg
E1g955QDBqa5OhRGkpNmBp/lFvtBDbBHWgLQBrqo132o55GxmF8ej8RQVqjbtQpXeHYhJsArOXwU
GgQomZtSNEbg7UkVj2/ihRLBQuUb3IoHWZjUEy55ozs1i6W2sRTx2h+To9grPWfti6F+gGZuYpY4
Dm6NVQh4FtNixvZ2NLWfxL7B/74Kk0QZ1yvXSACaDV1SRdyD7+7lmAJM+XS25tcUKH66HWd58LiT
xPkd599/52J3tHJqmOgfnyRaJwvtMUGLC6f21ran0HhmUt3jepzvy9AUFdUySARvajrxA2B8pAx5
OHjxikXyu/NvXEMFmm6GBcMQhzuMOhMcv7G7hohez3kjLxYaFzGnis4au6iTaQ4jo5iOSfmpWHdA
DD6yrvZTI3/kOfcWGCdra5OA5crdeHgBFh7Wu4ki3ydTMYlmEOCwUXFfgYR7HETCuxOBp3UcY3eO
Myn1l2eBVkhPL1ulAr5XNIOCTn7xfffkoLMXMHDG4OajEOMZOU+mhNCyDhRApmAT7SRR5wcgoz/U
WD17JQs4rxBQQWRKL0cEdBXeKGKml6uy4HnYbIrwJHcuVrve9HAGw8HFNCI2fuw1O4j2NfETqiK2
e4eNYvtBYP6K9kTLqo5uYbFEo+VUOYYEYGxlL4m12mP8kBR16pSLNg/+kKy/CFuCJM0ehP97/2F0
BDtu7hZXt7skoUaYz1UVjAz8Y9VJIXz0dCp4Sw9Tid67yrZsO6/o8mPxCmFQcC5rKg0kFWt1fRmq
MGWTnGGaw8kVUELMfVZnqIyxOMy76RMCbuw8KqMRrDUbBOiTmxLViuf01KwJBs/VvBdyxfrZzBAr
umrEuOc8zvWnRDhq1lBLoeFX7bTsN827yNgQX3VUu9n6FaJlVte/9ZhFi7bwLG2XqSArHxuYy2aC
gldf71r6EeY8TRQazkmRaKyLG2m4r0wkfI26wKY7ZKQsIedDZ1T3Ko9z/H87B2bRXYCI8zdQDP54
Zx+CGF/f9ARTjKqU6IW1zxeRNtNguyJ45HVMacTETQP4u4IP5Nuas9O0+2s1b8UwW+zJqZuw22r/
uIRD/DzAqbK9gRux7dyjwPImvu9QZ8hcsyGGSA6jPL/LDhEzgIKOjWlqVlVkuYFwiTHStyU9r0dg
VDEEepEbMScFz3lKV2XjChkTiBcc4kjkCaeFNeRdYE/9Km8tMWo80nLQTXKgtaCD13Wc7V33G30g
BbVd8XMIZJymTzlEoOEpMG/AxXGeQYkFOEE6q5Fsa2X0HNX7e1IYl6duBkm8+Zd5oSDMmn+pmSOM
rPii8tp5RLl/opHEDRn72gSSI5oDBWrSpwed7DMGacwmY8QOYodYlcku+6JL5dIdmnKfH3hkdPwM
4SiUruExFI9yYgw40RGb9VKc1h0kXwW3uWF9H5uq0UeEpYqWtLTmjPIzcz1NnQtvLjQ1C9t3YJ7b
9rXUhxK84RwKMehe2s43FKy4e23bNbVh+wImO74JNXp4XKEPkQM0zqvCGME4XgksJs6XGhG/xOyL
nEBg6sOD9MicgYFII8PeQlgawbhaUWZDV0120l0A66T6MsjMG/DuVj6XSZk9lA4woCQnKx7rhnGE
Scef3W+xuK/f9F7AA6HYGvn36Ric7O/LE/FKAs7aePIxGJu3UkfHBRGKlK0v2RLK1lnd5rO84Nry
44AF54XYxHHJfbnH20XRS3B0kMHGKZaUE7zJ3d10OT600BZRQ76j3CyYFTyBbQKkwtGU8uVSbauQ
0GNas15vuJEKGKw1jN5YqnFS3Q07E3JNp+Q4PQ+tqijfaIyZ8ze5P0GCuFaDtB8xga7rDMG4zjbE
iPxZxFdWQhPXc5qDQgPZwMramglUb6AW5mRKbGGLotZHaSkZsUxSaGby/ntxM9h60xcwGurkTp0T
/1T5qVm/wxYK/N2fWFZkba3Cbnjj0BfVMRmI8Nb9fBrx7XGl3nSPBCuNS997w0zoocx5ifZSC4OB
7XBAWeADyLkRypgTQkMtGJJTxpgFY6Mp8DbT1yYvPGMMCEYud+rS9YEL/PdT4+2htbgGV2fXMwaH
A6uFtqRCdHzNMGsfF3aHxl2WopDO0ixZlZcqBUx6V+SIhkaEw2bIW+n9VxvUEC6QaRD4nkXosv7f
SvxDqshnuHa5hc/+7cSX9nkw+vQN+wAjfpAzUjBW+kUp0YQsASKfhjpQCnf+hE6X0EkgjpgbQqqj
mjPplpVrmzSf/zAudHLxXxPC/enWwpXe6lelTNKYJgxRa5po0j/bWwsni/YeIKCE56FbPRx4KUW3
tHsJiIRE3/LVLJSn85U5O1MZ0AcqdpLzv7FsdtVjyrHwN+wx5zq4bjeLBLUe9j3w6LfUc+Xs4J8B
0/Yx2aZ1cNnGLqjEdLuvVZBrb6+aAz2ZuAz/+sJKIF2ey00ThQuaqRbzh7wrgtHbf+IkektU4fFt
qN4F1wy9+rpLhmzT5vAO2Bygwj0cbyuM9McpykDhKgugdmtzQ2kupqYQ+SAUi1UEZ40NKhWel0th
nCs08iaXcVxQ6bp4ZrOykD4eHNMYlZpbYu7o0RdpweSBBFByfecFezOSoQ/3I6QZX24nK8wN4uAk
RwveJdxPiZReACZ/obvdAoEOYh2gOdjy9M7xzIMED1GjlhfRg2am3cnIOcXo9r/yHDryE5kkGMcx
ryk7MZJvAcm6HYDLJeXYudReLGutuucFOYyWJ0zyCE3UX8ObsbwA//rwlcYZfjof2LyVWATqOIZU
ANA6jJIzpSte7/RB9npRpHLb74/+PiuBu+1TLK+8DYrIiV+I7e0kfuZu3K5R1LmmGpo7PO7R29oz
HJW1aCGSzOZqaQxDZSKG7eM6xLRTFp6guqAK7ccmOikcUpgga5yNmJtIGxBpNBEaQ0ZhUnm1eV/D
yf/cMbSSI8rubCpBr8/mOkgeP8hreT+iPiiWXwCp/XJOY/stRU561ePxyzOmY7uUzdgjqQXIUlLC
dymjL6TAaJb5+BVZ8glv54NAz2u64Ir1kzKPX2mHK+oerSZwaVTh1QvRffT9T952+1Bv814Eq6kw
H8vv0TOEGXgnBbblkyI02nAc/tJ9+IVmU8UXvYMoO4SBS9qrx3Ff4fTxdw4cq5pdx+R/xMjN7lzp
OTVNJ8XiX85gZgjOViitMT6cN9hNhGpB6yyLMfXGp/LxeSHLuD72i1fv7JPRbIi60V0COZ/3wsRw
YlBJvpnuVeJ2exDsPTTOVzxdY6DVmvV7nx0d1XUNio2sNMfrOK3YHNnyqP5W3NaISUO4JB7ZMRum
lWCVBxiBlsukpC2JthFgZ8ThutD/jMZq4dQazzWNscJkTelftmLry0QrkkxUyjlKec0xflfH3ElH
3chYo7mx50Dsd2Y+cEGhgU4atdQTXPxXgGHHSeLL0h09MId9MTAagDBVVDmQcpFqGVBnpvGsOTwq
I/U842as1Xdy5u4vRlJBvXD1i+8/01X8+MjNDCEPwQ3yaMCnF5PAy9Ay0HQLQ3xQY0jkmtebci6j
9Q2QAB7CKg8+2kMwyfIGZwbkSWQN5CUlSSmy7kQTe8pbeT95/Q+yh/x6J2bOL+uNqMlrk2mF3wKE
QKTFo+Io8468bRHjmfDqu8DcldJcZgF7aFOQN2teEftM6VWm032sRyxTaJFqD3c0rt+GOr60LqgJ
0354Ypb7QCi3+V5xlaFVJg/B0uHTq/qNpk5Pu2nx3SwoMC6l5BVgrvHhtwjHybnoaX0F/H3tQmZO
nAZWCAFczWQSrRxFBiL8e/8qMkQFFf4AlyxVLJEd4q9lcgRUNPf04i70ria28Bd9CMkL8VfVTkE+
jMCGIuK6LzxOrbzNr3vqJP66UGqg78jDnvOjFtRPXmTlAfrmiwogseo/D50U1PzznW9DT77eYPtS
W2IYt7O6hojJvqC5dJCurqudcC6X4vIfUJZxUEXc0k66USZBrVZuLEMCycHLg1qXMYW188qjNuom
WF4czvOMR7dx1IMI85budjDel+ZtOBm5udkGKPz19XWfAUq1jovpwmltQttx6PcB8ikxYLZe7aHJ
KV8qKxmMzYZE1VZHGoYuqgY3i2RjA9f8+Kz2dRP8nKVeaQpkpVzjjzNAY+iQJr+wTw4BZDMTRMtr
YqOSkGNAqK5zxqt1NvdlsrbcGkorjZkoK/9ouY1t+vdp5XfRCOq9vC1TRlAmVwk0y4UQAd1cUmyr
hzdFOP4IzR/3RiMmVnYVbE/mMTZAXN6i+cgywntT+v0TI9JKcizAIBWFBOi5Y2N4Li+PdhGKSHkE
ddx0qSHgXOW+7U1TmvqvzsAGglcNlJYtyuovQ/CbumlTIhlMmVfmXs3N6i/O3V0o2kmLFxgIx9IM
3IA11q0KLphqDCHmYymakWTQiGwJHEcUQsigGRqAYjIe4I/Y9ROcgF67ID1LVW9N5h7I+ze2omH/
EbpOLKygdYfljDtCsiIy2tysag1VU0OYwA+pObKVDopg+aWZe2lEOMiAmefir0eO652BSiOj1skv
+Sct9iRG7R2+u7jtXS7jCRhhruLfAoIkRZ8qO9W3BqjzWxKalo1jqbgz5bYpmTY33fCSsR9xQHFx
C6Pmh9lLO1FfvIrBKXznYSQ+LQRLaBl4NZxHD3i9EBwN05xVxbhRX4xf5SMkijjbSM1pXSjexOqr
MXpJTI5RHmvS1X8/KP4rsrRFxui0Lq5Soka+4MumZm3oV7fS0ScwE3ZnRyF1cOUXipX9OrEHJ355
N8QyG2UQ8TbEYFGVMWWgEaoEZJDOasrraSIhYfExSnTFwJvV5pm9GyuvqMeJobE8ZehyqkzbG5ng
E+P9vXjTtSRhcJ8MVCUuiiVpmk4o6o9ssAdBUrTgkRQmiYSfXoerwFutn9QCGceUB2gNG6G/MXVc
8VZK+C4H5039dTQQGRp3nnEq8Nr++vOcHKcDDoeb2A6JYaaoQAwN2sHGI722lQafi7gMsfCw4rMG
bRd/1kVtgIsMOYW3Wxc6CqeF/6HI0T1a1ALj6zBHwrlkEBG6LzYoBKu6ThMX62N60jRKiHMOtES9
O5XKZqRtIZDKsVzeLKgKeykSQPUdD21e3xJxQTUUn8WeBisAPToY4CXgxaQJEkB31pjhDhggyLoo
0QeDhvZ6oA+rQqQfL3bM6WSUmm+seJwd0sHY437Q7lVYHuLEnNhbs7QBs42deg2VfeGRZZqQjXHj
bgtv2Sz85xcMnPz8Gmj5FElWa1KS9hGdT9H1PiHmsc1Iy6WjwNRBU7SS6VNQO0UimbJA5nxbJAXc
0dRJg8riN1nZYAx9YCj+m0L5JQ31nQkWqJPgjlUPcG5l+WuVq+PX3xRWSxguTMz5utGr2zMOHxHi
76IIBvm2SyTAbycARJ28gKbMSva3BSp0bsTIxYVTtkFAXtCTk+Cdw9t3wfnqE36SojkuIOGMl1h8
aJJoCzzfKVXTh87GlG6jr/p8pxW0w+5YlV7f14WGIB4JIdQZ5DH6AeYXorSqGIVa6pVXX4XguzNH
RtwT1dH+RPvAJvqGJPYbzJb5s/JnAUt+nMYl5mmceqnSLmmWiPGjerz8d9hX3xmUnqssUfhEVhFN
NCF5wXARjHT++hojcLjj7SS2c7eu+uqTOUrqfD5huKvrGpQDzjKaIRxLZitkTWxZw8p0KlJYNFgx
UPaTt9FzF9HCACfRDLwNjbgGSQDQo4V6EfcMUMGbRb7tXFRzTJ+JtgGO9f1BgLhth/HTPmlH9L+y
5PJAew5VEDJKTytJmlCw91rDb9L3Hp8q9eQJXTYeuXhetznegbFbnMMowilZ5o2kPZmnn6QXqV8+
35oErk2Ggd1tu9CjQGH4xypj8hqji2V75NNGP1KsWzRarvihIcsDni7LBNF/kAI+SBXQX1syhf/E
lId5dDtAbXDrVSx7LKkCA2QhNHeRF0ZE2Ds3nOtu+2sUoMvOwcDqaFX5lEmf89epdAzIyJaOq6PG
k218BR0Oex7vpJi8oldpPv1lDl7oyHFcnAV33drJFsP0oMlSy8zkgZ7IQlrQ7K/grOtM8apwsVkg
0tYLnLh8KhC9CvcvStH1GDkXZJUzQHu6exgKeYFNDqaI4F95Sxnpr+aJKy7kWMW2Ff3YJwOzd932
OklEtZaRBXyBOKETxHGieImngQEY9PeG3HPXIgH0aeHO3WeCjN2P08C+xPjF6vwkOgBzMGbN3xgT
3S7XgnEE5U1QUJ+xs30jCwXvpbkINJPj7RAMGGGRP3evRbPeUBDIMKV4YMoEsYowlNm+wbak7L78
1PmwCSriLNMu9pdygCBIP2r01sQmVWbeBeqhtVTVMvGyum8wj94wdE6bvl8QDBJ04UV2Qvt9ylok
QRYKRlxf1uAfv3R5//PxJitVDCzoB/ghVLi11P8FviHr+uFOqNyWAb+mfcVomBQUnOM9IEwuoZnI
Dv9xMVjw2yOI5EvWPDRryfQwZ+XWWDUjyV9EnS5X5LchI9XsZ3cvBoDkLW60Toav13HsGIOGnE9G
XZGkO1HnoY1NsqH9k+TfTnrJSs5UD/sz7O0c7EH5c7LNUJyz1LdXzA6bHxlCF6KVnJ9DPqArmptM
rSmcOLO42Pa1QnEJOBdshO7eAo95jP5IKHpMiiTgxd7Mtfts4QHCWkFeFfsnQF0gEo4cuvLWAgz0
I7N9YV4gNd0u0Kt6RZ57BrhwgBReGYEKV5Reyt/LBN+Pjjtl1SGulw+MyDwzBrXypPwGKBFFChuG
t5v7RfXx8Vi+W9KfEkyrgPXqSSycbunpgrbNNUr4D0GU+5Yimv15OboESsdGPhHEfaqa5c27OzBE
qI6bHQYzk8cMCK27/+NLW9s7J1fy+VphqmKniZO/ujI9vZj3cGgaAMtpKdLGkVFQQgUQy8Mmt1kG
7kLaP22FvTop6C9HFfcufCgqLgZFenZzT1LtDE1UFZ+tfKdOA/ZUL12383YGZ3tF3mrxR4nK39fX
IMdW1jI7Fbd74ehs60B9WB+4uHqXe4HZi+u3DtJtQ9dlprG/cVtO56/g6hYLC/DgRvvw7xBpluN/
tLqfo681SmIM0Z8CG0azu9NE7JqSaHvhnLbqUVtHVoOM1yT81eavXq3dOsHD/fnHODKR/XC4TM+p
Rb3Ts8JWlOsYDj0TlByDon6kLhC6/NHcmOvn5IcRUBuIFSWdut0UgQqSWw/O47kt7d4zQxs4E61H
3UGwf+cvAHPxLibP5RG5X4s3P0hGUCe90Irs8qVUnodmjITDOIdEld4NpLBFWfx3JFVI1kIzGomS
ojScRN2gIstBNJO3bMOoJ6ZqV7ClVqBZmhBY1yzEFk9WUXG+zQ36vR4DK3rKmXzNIgTHUdyIaCrG
YZZ5zgKN3Fj07r2zhpY9/CH0qGHhH4q++sQlNxQzvmvokXepM9xDjjUJxpimo7w2YEuEb6aNs/au
CuG7d/Hsapuk8JijniPR6k6FyPNOpzsXGszWhlmSmHPmwbgIKjpAE//wNqXlK1om0quXCy94YWp9
2vZii8BXMZU73pX+mGGUzL2F7vZrNsAyHruJI824nywCAAIna1soCy5NxTvwAL7K8JslwdjOL8US
3TOn7OSxkR9rhBhxP5uEN2to/6Tb4SI6E+9LSdgX7bM/VReXVEaxjWp5yfjyV1QHH708D7XWJrYK
qhTRijSNpQQn39SWOMWV2cOCcXayRDXq25OQv0BYuAz99UpeL/Qt0hni/kf9788RPCjXPRxIXX7P
vw0qzs6Ge/ZkIOnNlv+JP+FtV1wtk9OKzholba7R+n8ga023gMvRVp8SZgn4VfNELO1NcFl1wMKL
v6/jgQf2BAdrRpxB3pM15NGQmXp/nZgwfH0jK5/YUObJZ4tHxK1TxOzmr/aEoJrOkCzy192f8LfZ
pf+12AAXsC70Lr5q7kdsV8M+56vX4CWtgIp7tlPgW8OzoLHH1t+mvgrsm7G16/yYpKGV9/VSJORO
CaUK8hmrn5PZX7Rr+8pTQm6TuVCyo/m0qjAWk4HgNjfVJWlYxLeclKW/9OuTMCiCxjw2ipXSsIjI
yfED2XnlSotBtri3Oe6kWEov7wp2KrMlegacZxQZ1R6Omm2wI78NjH+dqnnj2Wgzf64Sg25bDfGO
g+NfwHbMrGNFmEQnnOdfehLKaPtZ6+TMRJQlmAXwnVySu87FREttDQHh1rTq7jyPUYXWJKXXxc7c
L7t5CepzkxK1Y90DnwyoFOtkMiAqxfpdZAHvdmWGK8m1GLF6Q3Fp+G1WVy+Vr6EbRcJbUofAeGPY
r7Leb21P4pD6gGTHRk1zpkO4ojmvJsNZRu977kfF7kH6XzHl6Vq3ub+wICJCohCAHOO2rsiUGPRo
Uhv/WsSB5Fa+lIufVzNIZwa9M334T/5CYmI8UTLXzaHbutvUKnNnTmeCR+hhZqeP5IMI910oOGUp
U5HaMJ8m5bVQPLFuYKC9cGxhJS623gBsY9K+kSBkKle4t0UWqGK9UVxWxcRCJYvOHmz/zKbHtUDx
jjYSA0StvnRair2m1YDI+m64xIOvABgUZEjYi1+HZlzPe/T8FzpXz+sWTrgqnLElnnXtJnRNq1qQ
z6FJb2MFW9WHxh9In0tGXXr9hE3GtSxJRYLqccIq11ph0JR/CJPr7pYYKgRdrG8mA75A2T9sanpO
HaPjV7MwhxrpXvW0wzfQP3By0wC0WmXBmzNQ/u2mGYUfcs0rt1mpuVwuwjOpmKPkUG6PBgygSPev
Xu095xP09RqOaQ4en+5zbHsxfvYJLoitCevbaxih+T3QTXsuVY5gwkzvabVcXFlu8lZUFuO1NTRH
FojUkjZTD2uB3ufj4/sfqCPx2+jzDokj9ZtbcUKAbY6cKtmBK3F/wr68c+BS8tXih7MLEAQ0GiYl
pX51AWAYdJwGn/B4CK7lWmm/WfJXvPzlbudeBoxaEebOIGcm8grjllTRl1W/CBO0FHfY1C6P38Wm
1l6n+Ngx049loMp5xvDiqdFT637qCKNn6AhX41wqBGYSkg3lQ0HSrJX2sHQTH84j6sAxb1FnVkmN
9g7/GaohW41PUStgBbriqUFzx+NZMyarIM+BAInApEHe0uyHHz5BjkfjfUgOeyMWdZP0wJ1PKeAF
BsVB/Ya6Tlum6MAjXdjyStT1EIQevO9Fv6nQFDeiw1DgkhR6Kv0F3DC+eDos4ZN+4wBmVkrlLjHy
xfsefPPNixYAYPYL2Ax4c0GaT+v+nQ+B5GRWEowSPpPJFk5ynzqZHS8b/L1+y0EcmMfcgyGj2Zh4
DURCP51WJ6srrVK07QWF+TVpvkfgT016/8XfmN2SzJdENq3f02YQlWhQtsYICxORsqIeMwXSmHJG
teUGbZGXBi/+4+tTVMPVO63sMpHK2+t7bPjpNL6vTpsl6d5Sr1qdh6QXhgXAswWZE8Uvo9jnIux4
hLDtR3MVMLA90tQgsnraX0DbVQITIHC7mgX4B3IHeJg8gmlI9auWYrC1NyrVIDzFZNpMCjWOxitn
T5sGdnIyDRBfy/0CEj7/llkTecbt8gyj+X01cDx2+s7HvpZ9U1f5DglJXsKbyuT+cTJAxAfzM9Zz
dDYwEB+U2MgpIdL0o46BAFdUW/ht6pcFDPlbCADDS2aQcwWMkwwKFr+VoZUR1bauD8HmV0KDf771
/kNlNhbVx3cGV9kFkf6/QGNbg39OPkBCNJz8Vzxf6OXDJhAtN8CAuGFrxuVx+slCKKgbdUXkjcch
Gy831LwAYs/D/u/WjEz2XUQ+rJUwNpTOSIgeHk8FGITcvz7giMx9p6d79umIzykzs/kG3+JlCf+N
gJW6r1w22HqGmiE8/1zd81SOaWDwTgRbHFY41DSdVQ1Oj0XGwdDO4XCk03e8hNUyz6HGxSiF3hN1
DRuM00tEYNge1yjolkPpraLj51RMy1qIGpTJxl8FXbYvfWbZSQADVaIcrunWjmdYLsnFKSrNC6PG
HGegOYVrT1nQjmJb+uTkFfHHmB8vsYJGSB6Lxxhlsp2dF5HP+/jCTGdKEk8siB4+VQsd7Cb56rW2
rhMKzfjM2IGl4fszfAChdp5rDgegS3v5xbKgp4PA1TxcQORGWwNX2Woy5gDPCMdDdkHyFPVWBIFU
4itay7LyZgfJ1VGX4VPCv9qCeTbyBUvL1N0H4qpIjd6ndrQFfty0g1AelS4yR3Hp2h1vXN6scIUY
9Q2Yd7XF0WoJZ3kUQPOchtIYnp+jOriEBcyCXnCf4+eEPUL8HTJNPc3jFuGSpnyEezjYDpXmbQ93
vRWoPfNTwiVfYrxBhBnPic/Y1BEtHxsUw7DL7ItWpd3dW7Dt0jZ2NNGmVwbHwlx8MfZ84pH4Z4wE
YYTACNRSzXT5DGbGzuMuvRxO747O0BFgNISTLoIcCoNviPkarl+wiQRA0Qll5Uv75qSDbA2+ZX5l
lnw3idIxYEfpxjTzS+Tgjmh+CJykMUMyA1I4DPSG/YT1ddgN0oTZ0KNbdSYQEZ0Z8JWOqkxosP31
Cm2Dz9QcKGlRIrDDz5zARy8yFgtu9avHvFUBxDUoiSO2GQ+kDUNsH0vAEDoxly+hMvmJG6Pt0VWa
AVFJZZ5X7BaLRrbDo0ZCykquucMWadl+JpzAFrBwRQBBUNwLpRTO0KB7gGJUlDsFWlN3hATLkKsT
AJjbujZZ6JuFuqbl3LXM4/NbSA1iFSpvBhaKLd1H4ru7VF8WeunUej3/Wj7NYBrsTi7nwSHRnR2B
KeeDDGGzT1skHpFD5ISnMBhmb+zJo5phA7JzJxjbFXSnegISjbnqT6lYbXtvKJjgQkh0GRGB/nLV
i3cmebka8cY008DlfMFmJCwuTuT+ZnnIUPsf/bzospYdttJA7lDohfJ2ohgH835HZfBPHFzjFpKj
pODBQd7iRJRZfhj8E/3nNFocO3KTpJHfr2towNodjFcK6+hdQdEjqAa4Y+UahWy3x5hnzgZ9EGkx
gb9FfXVE5ghaYQVnO2KeaHPEtloLCWEvTk9nehUPlma6DY+prpAGRl8BpZXwapDsN9dPNWKfOyr+
4VhJ09LKAAKitZErUCqBVgCD/1owy4zHpbuUFzn2VLQmLZd83/kxPF/ZcqIr6qXb7pMltvN6lC3W
dffcnIFJ103nOrO68gGQZ8AWgmFSMBJKVfFeAJf5y8xUpPxsTcWDIvlu47lzZUR0ptmJx8bYXDFZ
TiM1BxG6ZtLCS6oKrUQWbrdumen/cb9ZQ80amXU0/dwF2i6diVb7eiDYjCXYpUdKwMk5CftIBhrz
3g4FxLR4e0xG3he37+sWG/GazCmvIL+yFKkOqTsjmOOhlVf1tWQvE9LLl7oS0UKpeCGOKenLpGkX
3t6PY1jfSBMGlzymONv6FqwbD560fMabfPkfyJmSkaDEtVNP77yhO7JxiUUxFsCPEQAs1bSHlee0
kagzB9w2jipWMhv26VM7SCfmxR1QsV0bwNEEpN+OTLqb2u9Z+pOkfE4gIQp5VFxMd0/r551FyPwV
ZEkB7dvW6Ndd/xJ/AEPJxZ1hjX0XaUKGw794gRTqzs+i6VP68UBsbfCr0LjmHWymoZnObnJ8n+ja
z6OKb2v0phMPSAOfVSROgXKbY0zfPEXfxgQAJyo0Dzuqwocc8VY0nB7iUhKv3/paMiZdKfbOmh3B
/acjrrG4VleAnKM+4+zd6XGOJULfGLH1ejKF86sS/YVnqXOzaYId96sHWJRFj7HAKRFdcvcs1136
efIByoeBnFCoPcvelwltGxrv7Z4Mkb0MDGucE6lFL7K8tnaKgF8Qs91nlC/kRkRKTn3FbyNCIj/q
bMVa17pN91+6OLCZgEWX6t+ZOJFtbN53o9DDfQd0z+jGCmoG1c6Ko8hn/jkaEpmeakzias69GueN
DIyyo5Dtgztnku4b2y1wF29Olb7bIPX5s34jX5SpmgJhe9qT8Q3o0JdOT9ylOrwPvUI9apuKvnEy
tdn47Xudp2QABWbCKexI7m/nk0LisHiTFqyhdMNcr4NkFn7NoC0Vivy2efOQufddbq9+vOOSCuYy
aBctWeIEWhjzsRoOXLab+kNcnYjub9ttAkz4h7vjBTe9zNLfM80nQTIv2bDczI+DB2/QFyJhDYoe
GLqrFtqB/mnoheS9+p3oPCegLk4gcRIM1DjbtYgP6KCACJlWz5DhFtmymaZ2CYsY0l6JqgSpSQtM
hlm1q4LRwCZQglYnjKhRo77mmCADtw8y1UIWGC3XVVeMkVJxSKEV0E5ZDX2ijBJtvROHYhWWM/Tv
DCJT1PNV0eHjEyfBi9xtc4SyIbYav+f6jkXp9qzlMOQRBh50mZkTb+zGhx6JH7XKLQWF21ZJ6Q+j
mos6ih+8Xe5rkszRVPVa2QRfOqegIWbSiEBk1mnO3Vn2gHjFnjhzRb0mTGUrmNc079Ba758rBdvI
tdZFEmSq+TpDVmMBdmatYWv/RzjjxVde7T08AHA1E4/HLAVe/7Lgs63U1llJ66PKaZbEzOTrzhv0
oZcdWS7abDXfUWlJK9T5DtKV++CV9fs5g0sfXPnpYlUNyys8HA90nE+gCvHwi4gYrzl+HA5fxczK
sciEb9lokFTBvjXHdJmh7/dX4YUz4RVIk0xfnQTWXeF8TpWvwOrljhurbIDmrerxcqj8E0IbdbnH
ryGQHqMm67q8uWJ+E8HaHQb6RFghTcweknGecdYwK0x28kCRqS71M5SXvqGyi34vDja887GU8Sek
yRFp15nrqSQbqgjrZZaR7ofAB8sbYl8RdHMzpR6rXNOp1jYgnB/OK6ijWA6x7iKdme3c6rdR3hz4
qRf1xXH1UXcOFbA1wVHWYV9k7UkgW+PuFpnT8qtzexzuAy2YlfGrl6uecahwtBNZU2J91VqCMCVb
AXOD6ie7xZBZMNMDN5eprg6jpr+M7O7uetx7pssMknjabMH7x15/WnxcmS+zInk2wOsVlKZtpx32
WtXxDoDc8c33P2VYWnHck+h7vr5yENRwAk0fPE+xNNKtFyCLLrQThUK9R7SiFGnmE0oejr6qWrGp
hAWzflzSQTwjfUhMXm+hUxrf7hhK/imznH20RjjzGOaC3aMjlUvgSRa378Fsc88mPsVmeiskghju
UdX5LxTX5LbxcNBbxtDDcy/KlR+oNU5mOVLO7YuiR/FNMsJnOTkOIJF4AXJOkW0zqMWbzwCYStKB
Yf+VKdwfKCi04yXrSfW4HqwHWFS3DKTgDwHaRVfNsDxBoDN/vYWhM9SydOakMX4wF2e+0Z1x7Lf9
JUZxPPYvBgsuJtMqoMHJwqrhuKR9wL9o2eEOoiTeUpRsK2kDpCHywCqy5i17q8nGNREYRbsnFidF
aKwjHgYHgQwSzGNu3xQn2jJPCIeLVVCztlo2AJ/iYymhZaU4YUymdpb4T1hRWU43v8brPjEY4zCk
y9fcKDTr1Bi5XLeGL+rbqNfThz5Ab4jkhbSLUqAjY6oPjt184NPT7pf3rW45Zn1U9isku0yZmKD7
3+9qLsAs8VwjtHkoRqAq+ZMAAt3L0wq0DoRinFrOGp5+Bu+mbg6GFKGzXlxBM12WWFylanzcjF11
9BjvvnnIym/dA7SocLFzpBPizFqiDngsdVfeWU/oObK28fnrCqm/gtyUEnrm6AffvCgy9NNOVADn
lEx3FDl9fbrezN88QN37L2pVBplMzQbgI9RZQN1YqsMFUjM6gGYkbiGOTVeddhnCVm2SI495/1V/
IXxcddpJ/+dkWs7W8GazjVo2EW08xR+PPp0QZggmuEpA55bod2f1jyJ2ARU6/qNMMFYnaPQoeryr
T8Voy6u7at8Gv1CWbyJU/lIYiqVPq7BXPXogIVQ2f25daGmSzjn6yuAYVdaYN9ub/gtWq1Zebebk
AZUTiiLozPl+kHixJzNUZDofJM8r7D34+7L2uAsQ0D1PpHitlFKA563gA2LW6Z5W5IW+pPn6Jjwu
pN7JDgI+u49oL/Y/ZhICsOptReVlnI+uZNhlyhMZMLueTIR9mHEpDJTR0/aCRSV7K/cwxHmy2Mez
cDeUE8RrlOzuCjMxKJflLRPoj0U8715QamjhyuaonYzbpffkQ9q7oBMveEvMzh6n63IgxKDZfKfo
QEOs7EitIboJUuR0/fUrQ5xZZikdX4dblmNPYGlbORIjyfSvVOEXLVYq9BmdaON9G/U14YhJJuah
pUR1FTV45Wpn6E5eU+p6c1tIm5OMgG8LPjjw7z+abBm40uc1L1C/Ias+VzAKmp//yI05Eus3NAW4
A0NRDTFKETDrrx+AFPxHnR7qgyV1Fem07POOQcgdl9ZoxqahTnFKvcDkaWaYbVZA570Pe5YZll7i
VJyXki6rWsL+Ghfijy3EP2zbVt6U/9Ao4Dr+k0ughgDdJ4uwK+CO3UT1JbPog4scyMRYw7Bwz/Zr
5HoZWRE0SYjkHKSHt5hjfNl+3vGDqSPl5bkK+K6YdcvBmVSodimb9e+yBTO+nAeva+JXP0hxfXeX
j/s4VI6cJIETp/YLbtN6+2yqAfVOnhOVjzPr6Dj8i6iH4EmGpJAVjkww5S3/pYKuTfzxNiWTNLhE
wKEZ/I2GlwtT/78eIEUoI6ysUbqlT+URYZeN1ECj6iDLmDdlBHUO6bgH+v9XEwKfAGe7ymh10rtB
lZjFBW8itPsUPm+SvaumW56KyUkmfQgxFKlUVQc6xftEWGCgl2MGRj1kH5RjgJQs423HUHMx9rYZ
Ly4ccjDRo3Ef3PHzPFMX3vXxkCB17RsZJ5Y7KVbZkpGCtZhsmzPWGXuA2Xbq8iISteFBddrRND5E
CQY0weiWOzWfy1b2wy8qz4aWwpubD1wCU1kY0EHHjl6hM+NinUCN92X6YYgIRDSd+WG4sTAweLNQ
HTom3X7eoyY4GwpD35P0Xs/Lc4LGfiyiqL/uIdP62z8ZmpySE1SS0tl4rEbteVET0diZ5woCAfLP
yyjBKAB2uHOWlCfsP0OqCe9Z//DVwoTVZ5VnIwd6sbK3HcuyuLS1V+vTBQpjTNDmiIUe7ZtVRkqw
LaS1VVa3gdoDtZa6AD61Q0DPYkPwCCmLn+37SU7+1hVehPz/Agv1LROZgRJdAhjD9Txvfs8d2NoE
YQX/70O7/ALqgCBXzAQbhnVCyG4r07S+n+LhnDtGWgpcJwY3jsKpZvtDY345fuPEuLrz/AwgrD5x
JXypF5bL9Jh9l5b1PtnPSEvnuLqvRD6MOVBN8fyT6/MaGoUJdWiupG5Q4+QoKZtnv7hwkWox2oaK
hq8DWUNZk7gTqTElujmUOZhlhszJvUzgdC41gCQuvZ3vRRL96SHiWqZoSXKfrTx9d0eY26qorxyX
PDl5S9lShBaKaBzt8VEBfqI8AoH1YkDZS3cYAazmmN/5AjZoKE59yLwrWB4PayzFkJnMqmSNtpE1
TyIKUpArmcI5CmIeS1G+ESMNSyUbFwPPrOel7rSUC7HVzBT+V3dT6REHqj0GKIW4DQE4r7CEjI2z
yWCl0tb5kFxG4ZEF3LwH0DgUm01mpSKbgM9JNqtvwoBnWV1gff31msrIUVZpxFGlM8VGvhWWpKgN
AAtsQDqxOcDPUYePol2t4lomQ54qaGvA7gHbp6mf7erZKWpH97qqWeAsW43gxh+YJVizQWzUqSbG
MLP3UEWmhK2epEGqB0fCbWZH2LpyZYyD7dgnbIV91NQxvxKIYMm6hSFtndCMyUpOacXI0ME3ni8w
WodwuGSm0ySezSMvRGZtdqiUo/K3wWDxreSwbBhuxHhR+FTpr2dFmW5tCXtkflYrzuOoreJtrHYZ
19afXLfNzlI9LToeVpAjWsJ6Q46z7fMSZtEEVIt8GPl1TehJfXZGptqAWJ9YZUE5j0iJOXSZ6Ol8
NFBAo6odA3oqh4qBc7k/lUF/HLST16C026UnUdDfAxmWE15Xsqu7fDvghx7BdsqDE3qT+NEuA04B
4ssomCkNCCQnljshOw1H8cNCRHxKtTzmEFZcwLSnJxfdt+mIcLa+B6dMcBvGrlzgDssC7BZ5K4y6
IUtN02GJLVFMxn+/8a5y4JcGlM/uy/3TLqOXoMz/2AexsvLJ+sQIvQeZbSVfcftm3cMtiqQrgHUs
1GaozHLAOhNouLUgUXnsDXfvEQIE26t9H0ISKsq0Eab1+1XX+kjz6AomkvXm1/ppyGBxCDPGJZIk
0+KP3Al4f20gx+zZ543zcXIhrZdQ0d9Ayudg9LtGPm6jVIhSQNUEJbIWtVqRGtYxWI6yyz/zipwy
aCxrVLQRpR4jyUMR+En10ljQS/ORh2ewweDoN17pEghpgxryCmfZzFURpH6SDmc8ZkVNKW+i1Jq3
ExsN9eSCnA0vD08gw3iikLHRH/Rr8LnXneMBRiY/tdUJvcUUYcw1W6DKq9vlzGCa44ealC/I2mT+
lBET96eUVOJjTgZzcDWbGEFY8ui8KES+53l1vMC5CU7H4FDFd2t5X7kXjcCJwgsr75PWWFGyc88/
T7NM8JrPxEwz2c8hZesQGQDkHWDiexOuyeEKN4wljSyoVNpnZtT8atIA705umWvRokaDKWUrQNEM
1KvziuXiSwMYU2CCdNwj1zx6vpfCwDaoEZ3DidQSbjq0OrFT9CQMwcOCrq/Jf7hbHtfs80Xg7RFf
9psLtBvzitSXY3+AKScsv0jIOuT4xbEYc6FOh5IRNnMMI7fIS7oIlE33CfCT05nxW/TS2aMXZ1T1
zy9/294oad+HtAlVQImNl0nnHL7AqDhHnG1ohoXpJi2pu6kAyKW5RuYts9W2JdJV98WPkoUcjZK+
11guYML6hud1E+0/7ndiyzk0h7JFC8lyPttxCK8o1+IrnA/gyFur+9LtB3f8ztSBRTci/LLbUAkf
kWO9WguL/W3fZ3bF8sejGyZP2kF9/0sk7WfkdoIQaXPv5AdFZWjVsonrahQfchRJRxj83WC0fPEs
2fbPmd+LDkjkGhIoLmBqKcdKTiGUXGaRl7CYRrszYvuup6wBxslJFvofDZu/Xux13FgTWr3fkN+1
urfPxEOlcS+91R6lZT650m2GFn8T2c89Up9E7Dq/udac9W5t1jwiE/UKCsLQp2+X4NE5z4xqtYdQ
VKj5OLZoAM92lS/Y3eV+U7XJZMXmMK4KsWJv/0Skx+AD5jHq1EugGfCeWEJpCXiw2RH3UmTFHPxn
rwuTANlt0KMbQy+I00OPexkbpxyRfsmZCDQ3GDMBFleBCvBGEayXToGqMBs0vd7M+Dob377//owi
cdUHw8/sy8zCD22UIvtiHgyF19oA6gd+zrlv0aLDZj6k7Gr0M29BWxSW5hkafM+Mat9yuQJxF8Gq
rbAeaBAkh84YEcMHEUK0bFWHzBzw5gtGFR5uN6HhLAMRlvWGy3UKhEd5bCILFPDibnJHk6nHrs8/
PEThxO5ulMq7LcsHy0x/0VlXHmdBDLFItQZvMoY4ka82Alamv7JRbhy8u7kV8mJ22X95weC8A+cF
eeqOXvErMPeeapi+yK1tuzY7emGV642E9lye/mXygOLLtweTupjBU+kKC41r3/qADZeNIKQ9KycK
5wCAm7g7/n7crCTlL+s4sRGUliWC+g8PEhJHTLmCyLpw88pllFpvwhqCwChLB3w1nvB8IHuVxOJ7
qR9B+sRAQAm/JnwOrfirxlGA9JNcEY2a2YIc8IXIOacQNXuBKMCuvMoDxpAPhYt9PZRwr3M8OTub
U/FsEN8TTyANcxSbD/2QTufunBE7tWXb6sPoxBjLKPG0oZrMbpROIJVQpbivyij0YqHip8UR068W
wn+9EzEBax/XENqEzPWRjgkHkobuoQGsKPU8S5duHgDkfs/vqgGifwu27i/1KP1la5Od0tBc/rXC
OZN8l72FJW7HVt3MSkUgiddF30ai7Q2Fo/UJYQ9i65QjY4JZzq0X8VDd7Qh1KUVDp6gvNXLaKtRv
okmmJG9FJp1Pohw37Du/J8f9o/NPX7W8kKpB3O92wikcBGAT265VfOpT96YYq1CDtaARfMzS7qWo
XWGdat+N6sxHHEjWavbWheXJ8GjBkGyOGEtHibOLdHazG1UPohoj1efPs+E2ALfEOg/vuLlzpfSi
fCzNT96vhfNq6X33EdlU2fLNt6D5F9uq2lP5S571ZzdpJcfHfbRcVslvW0fKZIVbKrdtLDYw7rkH
YCNhWLDxWfzBAY8bF2gt4F7cjlnoK+pFVWDJqIwlCZd+ALmRIf6e+10MnVUX2vgx+CW0tsFCFrhy
sXF8GPDsI/BCQZPkWGPtEFK0aV3TP3ZjfLrwAr9PxTtdZv77ytzALTe7I5vsSr59el1MB7bBQrGo
81hpAH3DL6Rg8rrLd4XLp5aX8s5S0C5wuHkppFAdB1lG69sAc4Ag1vs+yobO4ptStFn/mHYWY7HJ
HjRLJWhny4c1XEFlSFWKEh+7K/hPFSzVIROaekYREYrG6VWfR/Ufe4/uzOAVs3NeKAkF4th4LnSy
Yr/J/u+lgRA808pN2mMPEYofPDV9z4Xj792MniSQcOSssxdaUIeDkKUMC1pFNNPL4p9rn8HHIf8j
KTP530bSWSQ4Qq+TZMdEoBsQliJE0b0HjCfqN4Dx6t/sTKttD5hWeN7m5HKvGSSOBR8zs129lGpq
uz0npxdKR1GTRrLBg3kcWL6OEgigIbs6SSqGxVQknpfoCZqa9/rT8Y7mJu4jzcx5pVGO/1dklDH5
npZAbcZpCJPUGls4+HwyKNDegInJ6eBncJFjTiZGL0m7oYeJP3ZsHb1GknyMDrcmBqgowV65pnqw
GRiBjcIqGaL3ZGK4w4cNzKlGxONw+8MBl3uJPuB6fwMaxElHHO6CwJmLb8mB2g8MNHV2MSBL9qx8
yyrC55EEWSkkXEqcbMhJNB3HGyK24Veeqs5CbiInlF4dF61tjVOfLMjEX2vJbjxXEGvw5X5CQqjm
ZrDgijBF4EUlD7QVoGsm6K94uqk0prXartOvasN8gHn2iNVJs6wl/8Os11puNLF6U1Cdy+mZjRQ3
+2Sw51OU7ac9ZEVvS/TvUqZSPONBwMsBVdLPMsjHqeJaiZoNmQD57BxHxdLvYQVy2xaT/IplS62e
mT554imNy3ckK6y9rVaYLHvpfpMVbK3V3zj/AnSwwWnUooTG7mhcIY1Q6HveBOQGBxVw92xUuKHG
tsAntEcMnpo7tcDdrDUW+5DpPQcuGd8eTrZeRX/f9Kxnxpovj8CV7DIezNXWvvEumeuKWTMowsz4
iR1pbWf8IMZCirZO3zW13X2EFbb5b/ma6BT4YuvN7okynBOf2wBIJEt/8LDCo9ikYaGOxCrnIJMb
r8M0zhtJ5NojykduiAAOyMzo0Pf4A+JCk0r3WQFmcHIzPDwZLHz8Kx0FdVA3t2a/mVC0wvWCtp0Q
E2HrnKVPsdCzBQw4rbkOM1JZuXbDqUCRpZqsUaA4q7IiRB6zCr5HyrvzZiwe6xholKbImwLjFaho
+jlEo8+CF/4TsWzLd2L4G+53mVqU1QFEXCuNxFw+T+1ukbhWza9sBTYgvk1hvnw7O9o3RMUPNygu
0T2JSB0u6PLFLOD/lxgVTWcl8rgEl/K+b6wAK4R4VuMMtvrZ2uBLjxzmSrPvPBWuvV8cYY5TY+Ch
7u3fq3vggUzDJigUQmE6Nhrc+KQtjhrQagPWb+0Bx3cHqTkoQiDCRP1dhsQ5/63peZsoyyxSmkJc
eYhV1GLzFGveXv4N0309LMht5J18YeBVgS8nZP2eJSjyz3iHzTlRWctLHbu7I2EuB/7+RaEbl5gA
OzRSl2N/gkJBJHRthTkWOMcSGVsWXaL+PT4nbwSH/aHQy0X0w8FiYyVmN3BiuCIJmpi3Y84V1Uug
UDs+olWGZbh8GGjJvTHcAv2EO8HImg2N/JOaJ4BMtDjaDFcnBKWuhd531S7leMYqN/mGggN7hzWE
15xH7eUOY1OkqY95Yj4M4epyGnPpLzWRrQokVLQHBiF0tQuldkPNnp3uX36EZrMWm47C8kdWNtUJ
oefEZD8UfPDQnfZf82dwsrvkArJ8KmFBU808VBBLkpNks1pp1XbsXfKFSBrDX//41+U4PEZTR3Iz
5g+1f5ESkn6Y63ATBDKLM0fAKxRRhGxzg3SfrhmSWWB1MeSzN3WKZyztNlFIorcUkfvywfGLBFN2
leY3MPm4RiQc0qFmpzNAs8KkP7Cb1KuA+IV58xycbUiCde93ZA5IKnVpJWUy/d43PywUHDO0HaJM
ePjWlekQM3UeIAQ78+gUKYjVkidu3XHmg0pERHVK9EfSQrKLvCRKAVKyVBH65VfayH9hP0lfMMtn
32oxypQgzX/3z4qpFjOYtzyPuejp7opg9RZvBop3boncCQblW7Lf9mvbdognHWXKpBkZg1+jRZaK
aUkRPFp/twKx4ETB9kjyxLcT1V7v6pe+690mgQ+xlomgiUV+2de/8zWqJZX4oVkoihSAFsxVaxQa
Ozwx84dKNa2JyB7YoSzE1yh98pWgd+1h5Moa9CI8QFgVN2BvxohHmebPwp6xB9b2+mgnLUSc8I4a
7/U2h4RlOpADJV8x2yLX0ZvnqcQWOBRZmFin1PoI5BAHSBaW+MUP6LN+z329HtLGBFKmGh63CiJT
0dMSVRm6ndE9BwefZqO9HyU6TAK1TYNj4JIAhgORBVdlOlnMghwQ9Wv0XufhZjKvliQDMlXXzU9k
0yrsjoaLgXdJoJEnx1FBnThtvZ4DYBmzYIRe4N5SDzM2HwTe2kqGNsBwun0vxtVvM8oQMctfGWKe
EzIC7dytBFUX8yA0oADeSTFDHe0o/NsZj7rQGI77QPFFY80YDDkgIK8pZdTGOkfOOqvgXuxYbLPl
qkMllknjximPjJcpBl5tnPiAd2E34ZL/XateOWHjthPzPNV3YxClnNkuxlUutd3PfGH1NYCEKPfF
+N9+bqM1QBWu6v35i52KQpJjTUcV3BqUtKqMo94XouhL4XsJ7hOr7jxWkyprCWzJ6HCFBkKHJ/JP
bflqTN/m52qUANrMD3CDk/EpRJGHF5lThEv+UTrXYFrYlN0bK7L1s0aXcafaKm422Z+ayB3iuHol
8i9OPl0WENKUAgYOvgvxmuwmFAEcaf1bzDq/3o402dOJJufIl8hdkXW/m1mBywgYparkJ8APBbl+
/osvUZdiueqB5y3lSpwVCKjL3+suokGzowwrMTkqNYp+306v0E/MHL+2Bk9AOlITJ7Cs0oPLlCLn
IF3I2igktLyZ9ADtV1jsaT/zFLW5L+LUuJPmyJicrGGkZHg/H+hT78dtkOj61S4OQqgr5qykma3t
TrF1d5w+U71awwQpf73gA4fXnzCCdYUFBLLtTDCJQZe3VZdPwZqG3sQe8U7lkG0sNgAp1d7IMT24
l51mMOXalP0jk6u+iPxXk+kH+AJUOwPpOl4Ei4b8XrYmHOpM7Y0tVGIbVtLApH/UYDjcD/l1efuD
DPSpwZd4fPTQHWZIIpfY65tAGRvXlvPcHT6EkzWW+/1meUPE4wIOT6DbcNTtYJZfLXBCjORbugak
UL90ulx/uuWHjHxV+pkovYMSxr/1LskoAbwhacl0X894Dq+SPKaouuIcBRSZuoK+BXz85irYY+jI
vheUUED8UXfoaibTDsobj+U6eZtY1JEcl6Y9yk8BCpnUVCZaRI39K+P53mKCVVK6+gGy6n22uH7A
VfKnNbdvDG96r+WN9lo3KwqV0JufhUtE6pipiyCX4cjto+33fL9FuPuaIbQapLm7/Bh4171ecbsV
OPcYI+4RkYgp49AJiIGxVQc5i94rgc5/mugHlUOR17ec5zup4IwSPZQ0flEvjYyzuvg0MogLLaWi
gImdaNlO86HVj9nm6CfARlrdBgWlXjtkX8OksEV5v68IoeOx2KSOkE0M+N2OQ/aJq8LaRCt2sRNZ
BmmD4D7Ru9ylDO97gGlT1O4cnb7gSqyAexc6Q0VKtDzbzlffEOf+rp5I4eQCaRtkUzh72s1QZRYq
J1vXJ6z9/RByP0kay1BXim1/UxjuDoWbURUW8nnTtRMK60JbHiWVAenJDIXaSpq3sc2zAnlou3me
pNCtCI4vlrJAKQJvLYNz5eYi8M8x/kXBm5J5+H4IIxvbNB6tHtv7u+s7tIfILeOlE7HVq0Rtr1BY
Y6538799joPl5048Vq3H5sOiciNJhwqKAoXo4gwj0T39roGxHBnvSPU++WuyOcys34ld0HCEvU9w
/iA51Zr2KMBvdkKVNdtouxmFDYTFWdPpC4Zhc6AWt3ecMJamm+CIRFtmgEDxYTjHvbAPx6p5qjl4
1u6ZO+bZZYGYT5PaIiCq2qXNUzQT6pfFR6PBcAGLrAEp0qlQC2wKZkpjCZTdSJIxSz2j1yA9AIIY
0A34CMPoNURnDITdRNikTvQxGqad9ZdM6FChkbOFsot+Hu8MII/qfyVBQfLGca1DXLmMKTfN1Yy1
4zGUu1Lf2u5PxiowwpT+SCIEtmrHLNh8JX4iYT/BJbutH5IRzk+FBTHZ3PUNz9tkkdQfL0vVF18a
bgnqWsYAkrPgCeoBi16fUf/Y+7gnOj5BA4mlngEUnezUZ51vzthImtduuYkxAAu1s4g/5kMa+2po
4F8YDSfbVBuobHoPKOGGVa1r8JYZygXqqzyuG6gInHXzMwZ3ohPTUaQjgmgOsnD9z16oLfYr3DtS
OCAza8Nd129qh1owfbOB+h21wG0d3cNE41PAaWMkfcvBbQitBCEsufE2i6wfY57jzmDwSrnna8/b
EeZ/pIAX6/XjIzuDa6AacYAa0yWBKqPtP3nbLnu0rrwDyqmSZGeRzr0yR0khGJqWLdljZ9QsS4pt
lxwrREvTagYpoQ5HzgtLYPaqN2mvjeFfmzMuiDUicAyp2R7zhyhS06LGgJ0+VtLIBIVXaALPsbpH
8fGMzcpoVo2YLBmXYSK+3bTJaTa309EIdtwl/b8hJO3nqTftMQKI910llGZKA89yv5/rj9wquc/9
PRNzfq4JXBKCbX6xS+7wWOtu4nCVUFUYaCTIlHDT6eqYOl4B6mdfqmoNURUD1OWZYhgyOYmQHdRv
TaCfQ0elB7RCSl0Gqn6x/ysmNMO6kpOgjsMFkUu9EwlQSt6xTs9sTabH1jIuXcb7/gDWqVEvkGi4
qjHKyDaf7/eHvzxGFO5yGZGbEa35MFrjqBjxpQZZQ3PrLCCcmmFN/SzeWoZohJLExFwAaBTdvJkz
SQJ8+JT8GEOrzOGEYSiqs3FVh2/Mq+AjDWYZ9f0D4TrzQPJ8NxMKVzaIlDuf89n23igPSosb11MV
NgaIpe3qlwtNVzodpPlB2GdxUUTr09FSD/rgMlJfq6CCc2RmGgkv+qzxrHvo4AXiLJExvkAAAAiw
4l+osyjEyhX3m42yRX8bFAWS5ymnhtdiIVN/Z6AHk1xRrIUGRwwJfnJJPZUHzdyRXWoiRKtwZCF1
v+BV69M+XNleCRwHEZB6DAFswuo+bhjf33MslwBPjiqgsij9r9Uk319Ui5pvtqALcS0cjYrQ+Eya
fwB/PnPt0zbDNtK8NWDF2Qp5zgPBp9hPXp9UZTeQ+/qgDRtz/65x630k2B+Dm8d69vFmF0Hf8hzb
zUXzUtflMADqQdYqJHL4vXDVIhmNKnTc0nNPBr9iDSt9I2lsrFyAj9/+7L/cCqPe2za800FRXnaX
YZcKz0mFIt9fmAHbLhFm4TBbhXhgw9l5udi2RcBuxWkh4iQMQTeLYlYgRz6agAK0cIENN2l3X5Hk
HPHkqCR/a7yXDI+RS2eHgjXfwAO7ld1WgO5EEN1sZPK+bcg1SwZvZAEJIl/T2f3RQXKrV06jawvB
Fd8ewLjHo+sjvqMCtjLF0oht+LiKeJfVWN6lg5VWumlQjkjKSed7tOZ8KHB7wHjDvIAXEBLZSduA
w9Mvn6KVNL6fZT4qCluVpHApxUshP/M4sH9vwOEt/5kX9YmqftHAwJ3aEbPZZU5vJ/2nnA5wluNo
5ISxxilerxIh8KwTSt9Qw2iaPJc1cMHG09rczMUTGFEQ/masZYxWbd7BF/NvpHIDdaItPs/r7iZs
3w+6rUCBVx4dTKc/jn31P7QGhnzapZZhF1ENwnj9GLu+uJQbp/9MJjt4UUQ1PQlHV93nM5U+lP5t
wnz/4XzXh9oXOYO5W8jfKJpbl8AKT0vmzrnUeej2hci2KiJVZEKtarJ/I2vFvKK5H2IKUWEQaJZy
go7uRT2guapplnkjztSxyzEYiOO9UXzd8DjEGig2tLjvcgfwa6qxj6vYbHCfK6ZekQiAEIdDeMfl
knxSqE6Dwhdi+JK/VeTvckvh7VrRXFoD7F6vRngXvKQRpWa4sMM5g/38fpZZdBT+I6J2y4R0avmQ
MTaUDrXb3V/zpeK2070waLGp527wK1w3sgIQ7+4c+qZWNpDabYjzs9DZpAhXRnQwsgchXIVZSKxb
xWav8JFj3a6HAeVJX6tZCxJYGujd1YY5fFwzxvdzV4OBqcI3L5J7w1wDsGS1odW4Fm5N34dWRlhB
ZIoTP4eftzGIzSP3zhUE/ylFyA9+rwmfmkT7vDeJl2YCB3VE1D9UFeN/gPWKDkH4lBui3sexn0kh
JkBgLbvkVsgAEnurUkVAllCSUdQS3h7bSB8LKr7ht6QW9QsGC7xVdPun0S6hi3faeolzIU5kEK8S
oixGTZrMIVRSB+IW17n272GSzHwsGk0tBUo9NCqBcsCRPO/F9j5FI1ooqRfhKXaYDKhcXJO8nbG5
WktATpyA/BB38++nTcJhWD9DKN/s38tEaxs1gTcSmMjp0fPTt7EbZx6D5aqVKHOaTtuCp683IPgn
5tykYJsNnK1dxi0FT2deBHKy78wI8vXnUrWAGN6iRivnMxXLxXbv/cXkcc6I+XJdJjJNWowP9NTn
dMJj1ITk3DFsZfhvk4vcpXVDD/Xnl+iJarrlRHflRBD3dQ66n8N098MsnsHMCMIPc8krnFwfw+s3
DUbDgqcuHGJwjsE1VUwuqRUpE7wzaBhUbHb+Flvxr6RC5Aqt4JcwxYBosDehonupSqhqJ5vzawQH
j24r5guSZEsDGVDHM6g7gfx+pa7ormRUbLnZzmSqX5VHpBknhLpUi8QainPSsC5cGP/ITzh4BwyM
2F+D8Qf+GyfYtRig6hXNuwvmgZkUbTUyBE+0oz+BjWXjLAYar182z51EZvbBD7mmG4yfqvNKRkzU
hhRqSufvqKvymEYgPFWLXlINHfP+JyN7PM0xWAKoXP+lObde4BPHC4AaazPe6T0OPz+uEq6Zzn6f
VmkQ9SGDdMxIGVvjPMrzjwIIpGwAFlp1xx55NlFIQcaOnJRdkruap2s8dFgxQN9zKG2Zx95njFQm
oXzZO0DxXpHNZaMHnMhJy/PlYy67RqBCKq4YXM8R4a3wOvk3Ol69MXJnEfxrbVTP0gTLOV38VKdo
QI2MOK9n91zjafIO5U5VK2mCDc0Phq8w4jSmJRoPspPT1nwi3sHPmMMColUp7O/+Na4jnz0tu+xE
Iytp+qcAmq7hx38UQ2qJ7UUVhEBO30e1H/fTCUd3iLAcGsumjZx0wM7p2Em9G0TML4zBJbG/XQaY
E9w1nZ3qgta2eWIY+4yZ+wXfLTkGxli9gDNOy9uyHT7o5bS25S9SURgOBcvWZ5DMycN3EWvoQhc1
ZVqQYre9OkkTZliGdr1srPBtAmE4pJoM38zQjhE9mXsqLsn/bPyx0pvN3fUY1PACCwnlDe/5Mq/B
7nOSKecn8x6ibVZoUV11IsssRQ8IzQIctjO8RU2enWPq40FLDIIP1Nq078L/63XtIlsVQ/3KJPmi
Y790eWjEFGehsdydsleRjFzPXxjhmIKqMZ/zcIyveZipaitNz+luPMmhw67ejL6TmpQXplu7CmlD
UZnDTB0ZN9MuSv3CXRgY9Af3qH32gcc+pI0HbKI72P6RZKc1UJWIB7e6DHrgOItdjdSmNyZkFx8g
mWYx2qzaPRAlbabe67V1VFnPC/Yxi3MzBaXBqzcNRi3/zqjyy7Mr2hV6a/PuGeymnamHbC0cSAwl
M/ZI2e5/+B7eltOQvi2RNHMT3uJMAN4gfuSdFvCrQBlRYXDGqGdfwkFrwXrBcpCTXdXkocTlmwBR
dzrr0VwT9Ids5rNJclmayidmYQcOJeej+k5WF9hlljbygNWo/qpCBMq53raYPIP03LK8AC1UIH41
WcDCNmZt2U0Bw1nFPGYyyHi3eSv3sLDiVIW+jPrMho7+twmWqY9dyoJFiHKXPL6YNxk13QR80MMT
bCZn+4IVwTixVdzk3+F86kZLixjhEUwdQbGz8Pn9hCNhd4XyNu6EvBaHPOdjXY6C8CoNcjRi4AMe
l0W5vGq7LAHNBsGck7Adk7dUPGhg7dC29Wmj2Hy65EV68A/19I2HMzZVsQdouHNIk3u/PogVAMiQ
nKyY4sqktdjexHyW5WFMpPi8RdpH06pL5OC+epvlcTe1SlOF247kGMuPMiNtGVMqq3W2djLKkXoK
3w/7QYp4Espg02LpdOsoIgYVzHmJQ7SkSbNoZEdzeNuelcaI8mwZEjU71thQe3yJsCabgAnIx1hs
w0LEch5pJr0QVk8dQIwRwN8c7yKrxBtR9Ng9IXXedhBQZaN0gn6b3kzaf80QnA65FyGPrq7roIp4
yiM3dxvXQ/Uh1Zk4sk662U5Yx7ogUFivAkTwtY8BtLPjxdVJsJfVRFcafKr5igYJJ3+W7dJazTFw
ye6bzTXuXNN2U7hUsjNp6Z514UfMAsi3/RD+rkXidIvIqEUrNTdJyqteJKT/dHFGCWkErGN7o/cW
D8woqE5xWNn9uYMmJf2AFYBmlILreWJp8HvW86PKbOQnaO33DydOzG7oGKuR4MIrHhK3gWACa3jR
6bXGu0QJuXh2YS3yXH9zqG2B/LxGHRWZoMBxIRr8CTCcX9qG55Up95SWB4HGZ1/4Oxj/foKpPn3H
6GdIX42IUFWYGEHmeWsGlwxc44I/Q/I8FaRyR62Xmx0szxlJxYS3aT7KzV1N2L9J046dqeRnm7nj
mdSYVhGVSjd/szrVZMq5wj6Fgbwd4CPO+ZnlqLedE1bCIXsgmAlqRYeu3AFZ+u2YIc3JaEk8NpX3
D0BTtKAYn6NCbhN1cQy7s6AEooDAynJTuvJ0x5dVU1rK0dWRc9LBbmJKDqlCQVMQvVFAvUOH8+ve
pf9y1rreSUzXAFdMKqwXpCDDPW0fbqL87xbkch2WosEuK7gSqWXfkolpGvKbxI+EksVs6PV/pBVN
J1z7Gg+OHNYflckkSza4KuR/0U0E/OTC9kb9AesuAolAnoy0AIdThkhb6hlPtIZRw/hEQ9ixYedB
Vgwa9+1f5ikaoNH3yWifKVKp+nMQqxyy96sGy5/susvpVOS4+fuhfrxvrlWCYtu5oPp7HiYJezfB
g8IU3p39Q4Ndlk1+ah0PSD7hX+TKrqgaxH2wZUZ0rUlO4LFUd6Zn2dvHANsTS4gyZ27i5mgsbKCi
0Kd2cemCbL3oSVFNTUU9RPaUeFbPDSTfCDxwagUYGIBsljUA+bcNJ4dw33Jx7QhGeUyv5NBEbmUI
ZDT4TlzhdR+e8CRcSn+T6753w1PcqhKQRYyhlDIqatEUJ/StP5pkNg0vCEXyrJr99w/S9/qIMpJV
dMDoYBARoWtrtcWt0AIJ1zFjxCr6om2tKBGf+KiSk20+EJsDQv9ImKOCOsUVPIyYhkIyQ0EM/SlY
yE5to6T0rCRW8nEHrA8ifafqFTkw0LWVqEv5Dj01gsDjiKuJhEPP0AqoUa9cDF47RjMrF8RXa5Mb
9Zdh9YbI2ah8FtJ6ZOwGcLh3J+7nxLvIPk57lq3XzJ+1lkKavznNaM9E9fmFHrkETEbIAJcVyt2v
7rq4/A8Sm+QjGxIz0tBKIESs1z491vi1AH5As4oRBjLypm6+Srrt9FcjFPFWdaUMqfATL+OAXRVa
K0jjv3MtQ1elk14sHu5C55c9AzpFXsOKEIla3QijGfndltVNXGjV9d5xP/z89GvYZ4f1/F06SzyE
IK7HYbbXSbYp+lyKOkj3wuZD01znmpFUBQ8PTL7dG9jpmWgemB2wuGG/FotN3JyPzqVXjddNNnG7
JIeG2IAHwapf0Mi3d985YEt1ZKMCs7vnGGucJBYiYaa4WCz+fVTnNKANE0DJNfcQF7F/sr3Kl+o2
oh6Edhy8jcyMzOWwEpGyz7GpMfrTAs79BZ492TQF8mbQnQPR37LvMoFPdA02/+R1NK+8j5Uq5gi+
eyIXlkcQqggy5g5pL6IHF3Bizp/I9DnXqp06VIvOrAsCgo1Q6uUHEvv9H5M01Einlbk7iRvJqpDH
iMY/zPJBNK4bpQ69W0o6pmc2ojB5ZXCNkOJPi3MOVtjGsTRbCwDcz9NqKM3e4fwIvnZgl5YN992J
e3Le0FWKmtqZNfxIMZyYRCUljiug56yX4/Ru6vfCY7x+cHqN9qBdh2R5vEPav4Bv8ll+eFgzvT+m
lROD5qjBs0Bfr2ielduZKTHc5NdLn8qqchw41Qu6PRmLpZv5vwfmMUQAT1gz5ySYh+3ik6BC4Ul3
GxxZZ30jSSNAFSbp8Gd/6Tr68DBVyQSPEVtTy9cYbEseLGAagv6zdiw9uGfhVzaQb3qTpJuEV20/
l8QtJuYxBN/hhL790CpMz42XU9ro0+BXs7/MHgYOUi9XMxGBcXagdR/okqKj9vgz3GdWuTaU3mHu
01k7uS6en+0gXnEu0lk/xIeLcdk6LkGm8PlIhp3eRbI6ZcfIv4L0xTWE9IxDMixamacaSo/SMeAE
spvGJnPhB0ExMzi+EiT/z9iiUETtEeMZx2h9sHKjDzv6iKC6Igx8k+eVP2XMdF/W8JhDsAsfudIN
dgXkKLLMyZF/xRqV11JEue/fN49PZwu9O9qvMnQso1ZRHlsB0Y+CjuuBOEBSUksz59hyhI9/GpIj
DRsZ93EMWIl5+pX+2QRF4PMAhN3oWpA0ijG3qLVydHIhkQK+FZAxbAzu77sJFywa4YmEaau99gBP
qW9YJZVSM8BoAWJSAhhum9J5l9tu3ePl7TZZntJ4QUtfO9d1brSo2ZxSDrBAeRvs0/7nw1frn6lm
JAXDWKXg3NLR1wj/MN61gXZJ9SeGx/VQKKwbnIpj5cdoB25QQRWBDyRkKWlCaadQIDurl0HgHfud
qswo+rbVaiGIZEnB27V2UvxdqKt/bwfMxfF1i752o/3fSfVpCEpLAJi5UQ6P6MaRsjWgeYjI11XN
jZ/z0eZD5I4s2INf+b8Be9C1EHBo2PLfdCTCXMhXQ1qWeglDB4CeaDC4+kp77X8JIavNEghpI1DY
Vc0QQGrqNumLf7mxLxLS9um/PMABaxpg0GnuqnZnwAYCO1eovCAMztMLYeeKtDch+MEUVq0T0Kh8
xniMdHkq+STMeB79dZKVw5M/euCMcMHiXD/zB9qfT999Ooc3nofcFcp+x76UggX8MDRjRtLbBtd/
8yUnlUdgQG/MdRG9baSS5mOMRUl1wMZCdKbirr6sn5BbwtVsuew6m3ceHOKjApRYSdoT/VPtSuEA
nRZ4sP+XtWcHU56el6bOA4GzjxVx8Ghy7Hma4STFXYNLXYLxf2J9lrmC3i1rfoJJaTJs1dR2mN5N
A9IvVNI7CnVA6UpCIupXKfmbRxTnX0o95oehRw0E3kRIsqlCKrjkt9HkKU+QSrOGWmAbTUtRFKYV
rH+7CaOy6z7GPX/aaMI9crQAlQlC19kZPlOGtkU94gwX5Z0KCvUHd8vXgD5x6T7c177+C7uLw/aI
egb0wQ3kwV2dg8aeTn3nyEMjbeNac1kdfTshZwbll9N2f0VLiCxvBLLFdBc69EyRHQcZaH7wecNq
fK1qBilMprq7yap4zmxWeskrq0JgK66HzWVDkHDh6trnrVl6yRUM5kn51qpekAAaL5mKuqeDjJU9
oJ9OpgZW1Cc7pMGfGp/edQLmNEHfxgyQ26zycgCfVi16wZR935u8D2BzFOBE25k/1yUSEl3R3ima
JUc76mG1WkGdE7EPB0kDc0ksbCMJknmCyX+UYEotLWeXuJdkMiSGYarHOXmHSQ0KIcVtlPP9uGA3
jPq2pZStraHRsY4EYN7sS2Zh7J+5bBEJcSZIQU7TPKUMsAvwy67NPdjXnBLc9eSxYEewinod0u3A
xh5uLk7TCB5GHwGDWsWP+sl5tY9tHuvQdbCAxJRTMLK6+vsqvmVztOcLtEUA3zRo2pvl3z0y/KFU
HrCmegaTxdqTVsqLegOzmx5AVQzRbEQUB9hBsJ8QMG2vQQvWL9KmZ8ye1sqOkbTB+zV+fZGEEOSV
FQRZRTf5l01GZd1138jVe1Rghl8fT/OdlXtAiRik0P1B/4qwUQe1KceL8zl+xZIij/2QKmoQEkal
qIvTi4EhsJjwoYaHqL7KZrK1dHQUaee8ODu3DAC2ctIublIAoXadzbyFix7DrwX5HBENumaaixbc
Er6xYi4ONKlptnkm03Vh7uNxYfpgYSqRCUv8N32AUvJpUTBuFRkYZlVFGYAM6yEOIVqsRyUGf0qK
QttbNxC5xPpnhR0WHndSjyXdp4i56XMx7x7OqsoeRo/igcPY+fQ1RfoyjJSAk5hZQR4MUONo+lYl
wHaGC3WzyfwJPf4w5l04cWdMJlMVgd1YZkTxcQqYYmpSyn7dsI5ZDXXozwZPVPSsm52sYYIw03f0
B5LaesQsTLmgWvD2VLRMKdVP3edfPCHenxiCqHNZdWz9pLyxyPXMTizNrUoZ+0XqOWQCPrQxdryR
R7k8UHDRLA57+b6w9XA4cmNd9CzuzP0xpJdkETrJFPiYqgxtyYz5USsb29meuoFhHiUi0dCss5SD
szzYBNpYQlnPWm21wzWvC2QJ2/fP4PaxOG+naNLJ70E370JkoTzHrtG8aFSFls/GxWZOm1cSipeT
bJ3ok99Wjaj/O6GrGQ7/jOYaxoI4k02KmB37/MbGdNcTw+YYG3nbF3IpdaRzOPrv2scXH62m5Txe
3JhiO3abchQDRhO2X5uFZUNkowwsykwDOb/wzMkvr0v0PqnexEBHLWTZhXqcnReUJTzlnfI9Tlaw
Rj89aKyXEWjnRHIIqZMr7WqfJyPPm8ipDcXMHXw+s3ljZ4SFEy2nGAKdpS7H/ae7fH9dpWwlconB
y+VKC/Uv8wy7gk3jdsyGYFa7zDjWZ3FZ5VHQ3FxVYqGxu/cNlHV6I31SuJi0Ntt9n0Odv+TL1K6s
86zEFQ5i0XmngJMm/MXixa/Z+FyWXrGPXf0ez/dav71KynHp9sHMTF2dFtwENnpksUSFnS597t/6
YxapkSnbHCzbWjjUh/RQh5VW7C4J5BgkPl/OWkN6kfWKraBX1UrLczi2vOcmyp3Mp8o73rhDjFp2
dEj+1LDth3HvGvDZeUG/AuDC0bzNx9MVJkluNvCicJYdngCQ8aaevR9wMzroiHBzUFHbGtME1Es2
n8t9E4M0SLCMV3n0l6Ps21vvONR6ICwaSFy85cirQwjImSsdk1oXbhWP24xb5xpvJm4Kowma5wly
0IGpVuaWK+XKduuVqb5zEA5bsokSLwS1GMsGnpU9xOXnwOYsZDIu5VjfffY/phS++TYAxJGrEVCY
c+WPNOhmW/oiiArnp+jJNCuZEVj2naFd3ucKtNpMbL0No9t1Q1hfr+b4kP5+AoPnWB2hriM6GFpT
oSPbiL3JAyYLyg7mD9ThyCsuPQXMrdxwM75hwmNmdwxFwRNGX86f8KYWoF0efAU+RVfTOVY7eKCc
Uv9z+FQUmx6Rg1y8Vhc51eZBsj/buaX7a66Uit6YgN5HBuFhwT2qe20D5eYm/jM7lBH7WgYe0dqx
GxU3uKUsEO+oZuruVsmzW63QVMxK1whBreZ8ikqvhDsWXrWhxqAui68pFUfTMW5fyR1d+9jRic4d
+PHjfX4xmy3YpPZIjiGStgN7WhXrgAylXnB63sDSD03ZEhwvNzuXmgpiy1XTifnlPQon+7OAU0RU
r/C85+PxOXC2565cpERZhrd+3tJ912CvvSO8bAS7ey/BnGSwSZUr1lUUmRaRfS44zivi1rkAH7wY
znRNZVsCNn2PBe6U+cNGge1pprGa7CGCmqR+R/l4SyM6B6eH8Hl+fJqaPSJGUyXfZDkFkOJ5/zaf
NpEzF3Ko3wXRYy1QLW82yvyjFZHsy3juAlDQapEZlWqp7O3nvIsbk7Erkki0ff1I3L3ESoe3+YNm
ZsdIZQnYRSHm5pYTUeVv5wA6hthJc2T1/vD4yyufM5omE5DT4SaB/5rXGflLQJZRUkpkRvnRnEo8
v4nhdfk8ZeMxbOatbPI6AAe3cWMbiAaUvfr7cOceRK/OwsmOn7/aEUCwOR4uf/saE3CBhSOV/Afz
4O9MiNN9wck0tRqcRPehRBIi8wCNi3+L8NaIAojXwId+4XYqDSZEfbdmjTzWwfBZE/m3F6Z5HsUV
CwxD1qkW+pi23JLVFOnpGYB+vCcqJDdMtEHVpATs4ritgd7u9149XPqE8rUk811aMz0afscyuwve
sIXW47L1i3i2Sp70QVvLQJA81RYMm8vk7RalhN5G/401pQK8ntKRWgL5oeUODUWA2m69h8S/I02o
I+7RGO/bomr419QU+s7ax93IVKQdSNP+Jble1s06EW56UCHJ1sLEAGUuA0X4X7+6PxteI9m3oNPE
ig+J8gw3LwNeJ4HC7Ulw6WmmnDY552mwm+QEHSgeTAYo8n7pOpPY1imyMVKKzNAxzJ7Uhahv9YrH
74deuWrffilgf5hVCQH4H6nliN4Bb23+vxZE2vXfVyJnVaZooaVKX2LepCARwHKGcL3betoCHylY
WS0j1X+jaeQ9uT9vk31cdaJsfPSchc+suUAu0Dfx/gVmZ5aXhPxoUkWl+Z2oZGu95OV+3ok5+cvU
sDcR+ilms7UGjI2wSKx9KDFJENE3KAFnxv1sFw9J2jstZnZZxxljMTsGihuijnhzFRAMhvR6iiaQ
NjA+dbkIx+yYOp63Ja47vzcSdFQAR+azhjvLChKE1nYQa1wPcjsNikDvGqi/ffjZ7uORp2atKYvJ
4d6558k75syLs7LMP8G5wxoIkMKFYdd2N+7qguC/NH+Iu5H49999bXVCyJ7f3xc5n5CC5EKuFW+8
xQZ2MVferNB1sFyvPj+9okSuKio64syUcs67DWMjlATpwybzZjJKBH6cL1d2LQOiGR1X4GcubGsV
Sbf0SwtTAYNEDoq2gkan6Yp6/b3YznWx/9DqsdnuAVnW6nfUM2GpR11u/6fDenEZfcGTy09PwUW4
Tb+t8JLL32TpaaaA71GubswxLz3i81f3596ywGnIJZH7gzh3QLwDzlgRq/HMMdjwM5U2P+JJWnFg
yXQFqti7OS7p0/8P93ePOd5hxCdN1QfhQY5FxA9ksZAnbCAOsYoRyv/U/mYdHna18WJv1ZrPQOlO
j4WBDZQxOsBjeG1f+MoIQKt4bX/fz2fqCvse8IIw2hjA4xgaYZeP0dfOF3oTqb2JOPDbRPQjMKNM
y40Zsm5KfWGVeQBRG8Y8FYgvRvjHIiv2EFZZBFAUr618MyCsXdF9PBpWOazj8G+pd6kiFQQok3cC
l6udq9eBnFJBkQDjbyZHQTs5nbKfgcS1G43IkxO2S3uNGtOOxhWxBjmqCNdI/DUDvV3I4XbksTHE
ug3veaSz6iWctJbfqWBa75T4Tp2/+B4mt81Kb9ARfOFiVDaOaUlVPAj125eUMHNWlu7qTlk/Gywm
ZYEDFfDcdFND/ayhRXTNCMiyQ3ritgdX8miG5BHBQLcSjRXSaHtQ4IVQHZ3aGT61jQpdR2Plt5F+
m6U39juDn8AVeeiIduH1wYCZZuoplkDKb4dQgBY2dq3w6ZeWD/6lDjHCt8+7Cva58MkIo0aLwqH0
SjiPFritaA7xPAB8oPbK0jbRVL4xe1IbC7ZLRICAoZKeo6ZSCzZyoOm5SrE51NLdVmz3hmzVezNb
i7IaiC1eZ3WsHCAjl8CId9ybhLyG3kRL7V8ds3AbYE8o1CCcaU+4LgkVyvJMsdhUm7Rxg9Z+J2w3
4gHHagS1khcQcabmtU+1pmfNXumdHuFSssX4sr9gDysod6ck5It4iS/Z4fbtf5KrclzWXnfOWpfI
0oHst9BqImYyaQibo6BDJS7QfmV0MVDN9zOvQjk7HgTLYchPzPV5WW1DAMhXpTYTqwvpIUYXJo5J
D2F9TgawfTJw8KCU8l0HoYzn/b+fkCNdpHiLJdvse02ScYexlhk/WtV0fnPkgFYst4d0kdj6VWSI
MLcSt5aRjKqsJfmA9+W9yF6lQitUXclEW3kVvF90t7RSXzQjcDNIf/fmEmfDlJJYW0mpFSD78fMH
GhwZb7ObcaazBCtc00nQGBjzApVH0vrf1WfjGnjb0urvi/OxBMrQE0xcTp9gkMzgFZtZQgwHI198
ngG09dJXRUBF4fWF9OKl6qN7NIO7pILLXqNgVZZ1Eq++xoEGmVKORth9bnYL31wndSa9emPBpMWM
WZBwnv+dIHh3PQP+KAfUInkpY3iHA0Qra9lkRclcMk84Y5njttsDLgaO5mz1l+v1ZXGC/h5UCk3o
vOM79euvzswcBSo17hz/hQBlC0ND2FtnW9NuWRCiZTuKCnJIAzfr8cj4Um+XHEHPXU95VinIc1wt
jnsXgFO7TlVvnalUcmN4dW9MnkkgsqohT1fjUy1lpzAEKi+vQpXFkRQIc9jBa3zwecaxvdiB4kt2
9yReB4mItZzLpFyg0JJtOCbwyi+gNHC4Ux61FagxR5V23hb+ClL7DxHCFAU8IZxHyKSvV8S07kMN
PFeXDMnKcGJywG6K36bZ8w7dtkRtxVqpWwCsX3cBSMlH49S7Ee3sGBdzCdGNpY72Y3DUZn8clTT5
QSwyIAIz6en3Z/HOS1UFZV0ws8FtwN7QIXua6EFr+GoNHlmCv4nnpQTWw4u0OPV2I793fZoctLLO
vkkznpbdfhWFsjiU+IVYYZiEW/KP/SLAD3dL/93T5MFJn62T/YDKjK2x91wKZ2Prwz99Vga8/EoE
k6eNUm4zGrjd4ja97tO9jaBmbshNiVlCL0RlQIFnSVD3gtb1lF4gPtpKYMws3SFGJxD+EUQRKUqy
xewpQFjSaUFRY0Dpot7A9Glb6KTnTaSrxChgpPjncSafqUMo1LQPw9Hem4x+6IyUZ9P4CmUhvrWw
FdmQJ8sktB6o+9UFIQOcVH87e4Gni9CfDn+NJdVIDteg/aLyyufNVihKicA1ZS98tfULzW/4UxFq
x467A/1U8vpFPIC4+OfWpEFMe65SNmtUPC7KEAH5GYucnlqzfu0wBMrxx6/gIPCgWSW1WF/R0lTF
8LAvQL0XcwlHMd9FpyNewnUcDM1FcRygz6oeSRrnlHS27NaxX5ufbDx7KEBTRWX1YORuhYORpaw5
LmoCzmoxbiZkn216BIyVR0WbILBc2DGRX6xi/Q2qH938IBZ7R2BWJhJMmS3w49+cn19V1sBACPfT
r3/5/q+U4vOkNDf/6/3VYdGYq+uirrN5juD/NDxNfUiDiMqlCtBnnFQbeOLCBKDTltAQZXfW3byP
iQfNkGC3w88RkYmwcUHv5WZIc+U1Oo4yef/xWsCQlztPLOh0lgfbKt0aNphgDo+lteKISNUGld8n
OLkjagCSv2T5OZOgMviGjLAV9+19VkarBo+4kVFv68dHg1N9eFhwSoH/ZDHEGN7y/+jqjQ0Xj+Z4
Ui+nu4EhaPSAJoeGaoBbbgn0OfK5+oyvpq1q/WpjiRf6ck7NjW6D9hNF+15aR9azDwkFiXmzLdjr
Top2JCZjSFJ6SzpZX3QyZMdfmfFBtRdVKKYL0nsGAAqKzSp1SjCNR8joNabV+Bt4qQB8GKkpTqLj
BNf9nK/ZlxxjElDFwWO+0RRC2iEBgN3mQOvKypQU5JRAMVIQeSU8wkj13/M8TGGCH6pLA2WtHp41
840CoH473SGkr6pcwfWS5/QfY7cvdM5RM37xjFtRdoI5z4aTuT1/shE5b2HKSOkg/2e94SlItraL
iRvx70OoKPxmSxSP+m4ics6+NdYP/4LlHit/MDATA4AUBTru8RhcCHXLsjCsuBTWWpeLZx/bWhd0
ZCAj0S0aICBrXmGAiCZPoN+S9hFJxmV43LEjJDN05tm0cjkbLBb3ognID367Vgtp/hv6Iw3UsiOy
RMfI6r9sDnJPaK+kq81wg9WIkg8yu39e5uFrSQ+n8ek3QAVFY9G7qasm1MWl/6CemYB159AqEnv2
kEaW5qstP5g91eEA6Cv/7NZJQ/ObD3UZ3xdkPdkpiZDbCiCJuDpns/y0FtTbD8nZ8B+7jNWMa6Ch
/+HfAs3HIZSjfIp6Ks9bhhip3cB+jLnNYv2KLhoxo2iWafN+hYzcB7otTjtDjiaAqlzOoDBgo+Ku
fiEfBwop6VaCvrGe8QQi8tsMaiXk+P0rZgWxR58VnnmS19S31ni01tK5i4LDq4ycFefnQrhovZNl
HHkouINj16ak03hrYKm5+iHhDmzC1HFrkB7kChFuH+Mnx6LO3zvvfn9RCu1UjxpM1hJJsjJQGUfd
WwVAg3/gDQU0Dc25RWIpx59r/qe8teNbg03qaLEDCt2xUhoqrGv+SW2MhKfShDYyFfSEq8OyzM5Y
BepLdPB1sEP9DVtK27VaFmrdkGaWwGbf6QJDTwGHpozuHhRg5W3yTggiNZrzknKtBm3D1WfmHJW6
cN2U/IXaFF1cHIDBxFiepZ6RkiBUVltEF5nI0NKd1kQIqv+mSEpKqIl5GgVwwhJuJQvabW5dgzSi
HeZJei5jDG+XtIcEg1vGMmVWL349SrxlSmnJ4eUExgCZYn3cx23XpbkqTU88mmkVxx/Jyre0WDgr
kQFn1hCTiZXZqXsmd+8Dga/w3cYbvyp5oAa4r3ZEa3l9ALIhkpDG33fpx/xaVK3lhPLdRbKrusSB
GpmONoYuX3+ebh/x0wlcV0jwiDWES5fMVUOs/m8N3yprTjkRjOtoooc7hn+4Vzgbt8ZGqER543YO
15lqs83XVLqkQ6yxEJa89k8h4fqiuJKwCdcmfzGjyJVQUzKCWKlYaOJzBUQ2UyKkbqiqbph13Yeb
/zWeSrYwAe4XOd/vu8WaUhFZW4l0Pg5JTfhGfcgXgcEEoW2IWG2B1FSOwacaotS4JgXHCfrl2ViE
049cziV4Zyq86b/ncMiuR8U/oqcIRQYhvSJm6zn2UArlQXgBjPJOeLdAdREdPbhXCGpais7lOW8R
z6/wsU7puG4HO2ZZ7zsj7/xLYelFrFWXsz5teflbssMeN4upMxe5aVhNktm//KEgOLnLGOfVkLYa
ysC7aK7RN0vvXsF82qXutvya8qA+UegJcj5o+qPPRxEAz1Ci3TFdBiQQbx4i8Ht9051nA0ijggi2
wQDdCMSRKR0V/hNuW9rNpSbL/+YHHE5aPKimkkmk9grNP2s1fwOvWeO5vwZdDa9it0GNHSvlEEXD
enm9GUX+3DnDYeZhgX/hRZfjOlgCo/aBW/skM09q8SXUNNe4E2IucdrRi1yXk26e1WsSAOaselZQ
2lY46S5zniqbQGaai1TgJdGjmKm+d6mn8M7T20G7CPp0pB+aYX1bKZAN0i5lUs77Sshk/ADloJAY
N3yJpUzzxQTqhf3FEksZGjyjqtaQpb0we2ZajjPUNlnv/9Nxu9RhHKaGtAy4y9287LdQO4xUxnns
JOwPo4i0jvIvoRONPpyKq7w5ozfNbKj2pJP41Snr38vDa6vPtV9vlrer3VNqFz5OHXufw3GMlrbY
nFLaObZ6pdzEZZUV3RJA+8jH11a9gbVc55cjE/W5JmGWJj0Kstzz4yrTMgD8CfgQ5KbyvrELiDAJ
oHUpaE+AQsPmdWPKvHzpCV+uzqPthQMRDi6R+vR7oGi/xzmDWPAFXzK8ZFdekyIUVjL1+DtvdCI6
evcPm+u8XiH84uAus+GPopnkia6xWAoupSnl35F1BII0caz6DBQDC5lFRgLxoJ0WDiaykpcWJBmc
ghlkYb6UGABtvWeFCtvvP6u+JwrfpgZWU1Uhz2s/usk/4voNHSaw7j96Lihb/yjH8NdtvQfKEv/Q
zZb2JvZY704SyINaL1sEXaMEMV0CikrB4Gg+5Gm2HNPwDZF/0UhbX3Cv6MG3HHIcauwgLN6K9gAu
lzfn6y/T3bI01u5PJ+CMiN220hs1w3gxzmSt8e3g5lazk3HF/vszfKgKm9yQyTJf3B0ZD3v1SsoX
lqkY/NtymMixXiwbHCaA77ncOxLTJ/EOOn5aYH9dGEbgAgNAvUEehg2Llf+n9B6esnt9i4sBOptx
c06W6iLuKCJXT7zKl0fhoaWY7zCZaU/vXq3MZUT4IcXdi1PBG5AtnRcFLjck2cYLRuYY985P/UBU
5AlqRYpf/rl0RAHepAELVtQ44dj7DXsEKaCO3LZSeu6UeivYo5m5phZhUnwExvophYRLSlQyiMhT
sujqGW3U13ZvvxBXGIKMKfsbUAq5u/JMKonfxAeSkkSTW7WkuM4WfnnxLpqJBkYT5fV/uv5L4TjP
usI9CZkaN2XulGzYJuBhk+C/Pihz8uY6hWTWLQUc9YbdoKAbukpic+wrNg8GOB3ZZ6ZITO1XNQZ3
U2Z2n6e/DfwEJ0xfpWUllRh56HzBWCpvYfaLkBST7TbkcsQhvpZcht/yReTpCuLWhrMkfca63Huc
Cjhk2VklyUmBqYxCZ2WeHqBjX4hHH+weWkXdcQ9NTtKP2ePL0wfBk0UJLEkw2B+10TJ4Wy1OL0VP
PZmyUPlVsh99vEESR0ACInHAVvAuekwP0VIJEzf0CO+u3poBJYOsQz3toj6EA7bwL81dv3S57TVL
wH9QlOOus4jTHjsAnsm4JatWdrgCdeuIv0WJhywvvkZu9S68uEpwE42yyHYVaUrOT95bl7huqL/4
uzoAoC4y5CXnRgH3DOMA6OuFsMqWezE8Y8wgesMvW6F4bxhaVo/tGorElArmQbm+p+LVK0Zxarvt
kV2CBVNa45A0L+Lu7NCtkP77XHtZ4Nv68bo5XLz+bnQDr0drArr/lWgsQT1+pNFqMO4GEbgKy1vv
4l8fhEJxin6FEpjpaRt+KTnAAG84KKvRp8DMXMYZEkhXTv6es7fQLtO/nKX6EJwvVx+Y8kLwDECg
hlgi9qGIo74KqYkh2swOsQBcU7a6L2vPFc3nVDQjRFUs6e0LOBSpgyB1BqqCIu41kWrvOmX1IpXf
kthJwru8j/JL4U3lQasY2uDginWk2pGVTJ6g/pZBGHvFOd/d/X/MQ0FFKIu3DzGndU+jJfqHUKy7
h15w1MLX00a0qVAZ68CfIA/F09ASKSs6oUeQ4K7O2EBMpwPDOtCParJze1jZU15RoAcvBPeRulMD
oj+XVKLQLQAA8eMzVqMGr59089Htx6ZLLtSNgrAMsADvu+Wf+LXrjCOeTEMaJXV5vboL3ARcSZqx
fbZTakC4AQzLAI2Asj10y0R8xvc2RZfSbRDvPvVR534TVbux5HLGfxGiDjj3zgsfBfFPUhDfIRU6
6a4j8iscAJNQzs2wKSxjmMABjr/h+tHrOcmjM2ZVBLeZmIEnOYh0GYWTqCfDxKm/f5O8OIDBKO1D
Ri62PFKoVM0uH5KRru3TfjTCL3p6doPL8Itbi98RlyraL2ZSVdGW7GG+OVSTrB5jZHcfokfNIeLR
ZAE+473Oi2fQxfaFfU9KtDIZzNnCmsH42g5+TQS6cwnKfj9D1GK1EOpo4djM7BdGf8hjBmhEikg3
kxUTLyQlYsfCWabk12eLnP+CcN48gm61gOHj3RfWdhtUaNQy97116mTzx+CBX6LpE8Rj7P/xIQRf
uELXFJikt5SJQ5x0fA9eyiYiUjphPaWSepLwjqWIgwZZfljEhG+qNIPrzA3TtXfI/01t3YfweIYS
5Nfl+p1P5+zjLGex7cGm964TlHDaZAbOnhMk2XyxjXsPwkBrbkFt97ejlFhXc+LxA7eEK59OBYX2
gLjQY3cnnB/uAfaKUoOH3im7/DHDfgX2drOwJgGjLiJNYl40B3785WrK28y/r1HrNwDExPEleEkO
yb6WHdlyHNbZvEG9a9RwXEm2jJOxoMIB23macmOoIlK1IXP5KH8rZVLa2M07Mf6935LDddxMDxkt
kQzNDu6gtpY6O+jqCQjakJBHzmrPCGNwT7unIt88jPN7knYmxbFRxDk1PdDT34JGGHU2A+LeAomF
bCe7XxAy3/kIgtWARSq0cURcvzsf0efIKn+tlVbxYX9IDVWjxZoh5dthwJh24tEMHhEZhjdRkjvb
xB68L9bOl9AtryPUqoZUu1+Yy00+hmbTR9dcFb24ivo0ohiGc2dB0sZxqTbDCTfMsI5SwLaUAXaC
ENQYymOhWW2pYy1uBTW5+znI9PIhFDpHtNEjr39HlrK1tNu1p7VDgNsY2tT48TjRJ7dH6+OtJ2aA
MlZj8ij0eSdCNQwwj1TI/k51ND2QXTaSSprqgxgZY68HHgZP4vTf7WEGtNePodahpZqAcS3Wa2Ou
Pyxw7XEBgKTFI/1V0zMBRy+1Q4ZlSdyyWRBhfvwrpPQmfc2tgeltG3wjiu/9j0x1vh4AqakotDZx
zFw0wJwrg56d8Ia6j1AfJt2i6+PR2F7nrEBtLo+svjlTaJ8VxS4MuedT62Azfaqt4vPGLqiOViwQ
UHSSsFo3uxOOZ0CvXvokNbH5UbqVF4P2gk76IpE9ad0fAyir/P11Rw6ViM/XvQBKbol2C138fY3F
0K7LyopIjDVRaac9NzymZTKUqVyu4RBPLjvG85b9U3RhzChjn/mAbpYf3koTgMggx9PygNOgpk9A
PCc3cIMWwpKFgqaujO3AdYeFnbZQyWuXQ4eNnLTZ7tJoRSfGX0EYU9HS7zku02ul8Pa8hJO/zRxX
rTp4Q4aefyjDI5oE62pxbyODhv7KtaNunYaPBSlCwkKub+d6TzEqlGP9gKWzwkK7p8f3KDjX1n9r
8dzcuDwbyWz3sX5rZqLcoJPFht+XJQUT/oEukhgec0LHy5qoBYA+2+RvEDa47m6/Dz8ElmELSIyQ
Wg5rcTC3dMF63isXcHKDXAjQBZDfnFEGjGzItg52NgaC7n5cf3TFnG7x9Rc5awl40yOyP4qCFK+e
+4ccKmq5Y+48E9f8iC1fXQ+0Mw1qsWs6Ewm79mWwMQQA0Cnjej/rO4H12z/T5d7MguJJm3VpJ2W3
s4REAnTpfn2L/X5X5af+0+qkdDnHJmA6KqUHNzG7F4vbZRC9LzRRsZUsP6F4U52DqScx44dNkFYY
zv3c9W9kgJ7lwi6uWjq9L0DJSORovlY+LNkr1+WRsc3ya41Wmkubmk4zdDL0TRl73i5b2Wr4vOv/
afdyG3WwsfPWuVIqqeklTxxXo9qoijsF8hXVStYJxDoNx+wOya9+UfHbOYuwU3FtR6+FupFkKZ/B
gkiX8kGtFwVX522KPdO2fWCj0A1Ob5S5vJdiu0rPzQ1uKNuZEfqf4lcS/7gW3kXh2FCrkUhwhmxM
MbJu7tlSyyCjN0VIgfPWe6llpcDDVW+9VmcaELN/ovGC23jmu9huuN8wgHt0SOJpQl0oXHMAOD9d
nZSP03E2RA3bGLXdgcG8TtRiBz9urhS43E0sELi7xi0mUeAmaQ8MnzGtK+IJsoFRi3UCkUoN7qez
nIVLESu9Z1lYLZ6hBePj3w2/PkxI9Xh47YsrnN2oTXVQz0kyuqkfskKBGIjKBAyvwLNmoENUhceW
h9oWYhfgTqM1sebmxAOKM7vhyMGxJmcdl7a09KZvNsWSirkbaOSIq59lmupehaOZk56ArM1x6QMW
Qm26FBn6RF+MOQu38G7Vu2v6dXu060NbM+c76EUrND1OU00IAJTgutLiaqkVwhDqo0LMlw9MCHov
oJRpBqi2lHCf7/6SOf/jkNu7JrQ8s3YZUhOk5ZwvR6FZDqJlQ1938N4CYJLR9ndthSFXUGpt4zPD
eRtPcG7+07yLUMuL8ybCo0PiCQFYTGXj0Azj4dhV1X+gVk3wCWsAX9GI9kBgcGSpT/vvQxJRswEV
jR/tCIANjPIt6Xjz46SjVYvXpkwyWsl8n3B29IOQTAS9G2pR+R3ivxfbAijC/LRZq2fqP8xrkmsa
GbyUlWIP0buQrgz61FMDE4yhIhnRGoyLBDBD4CrN8/Opduz5ybDn/+/jot5Kv+6f13Xm8dGS3sBv
679haN6A1+A6BS7Sljmt2hIvGheV7yKeIOa2IyXhZ3qYveH342AnL+qBctjjaVpqSu5Q9AuGvb5k
Ti1cIUBufpNhpKJWPraZaHt5Tl7dvL7Y3OSTi6tOTGZsT2BOWaJLq4sSYYNheDncaHyb3ynwNvu4
FmmkipSX6csAyT8Katg/+eW67xbJFrC5qHbi5TFAn73+O+HOvDpcihqHfNNu4Ba592m6c4/JS3ER
l2H2y3rpLeYwsThD7gV9JwqE6fci0BBifsqWNfzbjyKOupIbr1vIUG27xyiq6blrU2uh8lgRvuPD
V/ZRH7xWkQ2XK8hYsUcgx/l3Nz3HI/nzUzsu6VxfL1/PHN49JepkHUxtpdI1nbq/UhjrurPRa4o2
7eRt11I1mqKDU/7hxKtB0x6iM9IEEwzuSNlmkHyw2C//kFuKy2jbnQnofq8+va2A6HsrtwJLf8Xd
IxnbPQNtEqS7Zo+x5nomuuv8bYOc+mA9Rqf3EgCuuaK2CgM9bTT/6mta6mVjLsbmBAPV4eXxSTp3
dQ7zVP4cwRSjx1PemFZn7fzsgyvHY10IpqeaFLcS/JW4bA1obuiYwSZWd1bTFZ66rtDxubwLlD5w
1mJB0deRLlBk/Ig8jnNTFWPwBGgLTWGRirYcxY+NCkIixXoCpcqDssUTUVou982UuYr8JAqqFk2j
ZYU8o3WhXsTuhqEKNGdbfV2Zh2IBRS+wKRdsFfHK5HcaBTqoVc/lt4ORrEEj9/06jR3xf69/rypR
c/seB91Xpo+AROFtWHpHjYFa0E8QcTQyZVRas86VeYq/Sgg3MnhLcZG/6NnBFYn028H74TNX7cfQ
dWQVV9AN8QkQhyxe0KTqdN4STyQHHzz08dzYBNK9VXBFVdL951Kg+LSDIc8RtSQEYw1DRZ3LvFp5
0aZFHrsj6Wd63TvIVhRRGgSOBguyIBenM3jNGi5gMWzrMYhrMQauS860wm8AgOedz2aiGLztanzR
KbRha1cux0ZLnyhuzbtifCFzZXptv4VZPH8KWUvCQwSl8M74H/znlLhXja377j0OfI3OjBe+pDti
78EB374OTWol+vOUmjkDZQWPfumEwToseKPmQLy8n+eTBaqWCMS+njwJ6tjC8HMY87oXao0m4KFC
nDfri4aeiTJsG+8fgdXcPzOibB3MsX6XwXuq2ANiKH8sXApNsgR9+SjVkY8UNAK0lOrOJwCkedTz
DK8cBlysnI1yGaQTNc9N52+IsAxU7ONte1y8Zx/+mnDaji5PtwQ3vqF6eSoQ+tdgSWZRblmDdx/t
uY8AYQo2O2i+6nuGEmsl5HD5r3ptoOOoRopbax7d3j/9wXuz2A0EnNZYYJpfAP0fQEYDfWJSLdUX
5mrrD7o0o6avGy8pL+at9l8Sxe2IrFMQ7tmVpuiYcNcZ+kBeEFJ7Ixy5aClZ5AWtbNPHF8Uxg0aI
YmTiAPiEgstR84M+P27GDJMMloIGdjuvw82OzeyfpcAmPcRoun1yRR2/tl3LjEoHdd+bP0MQm8aG
SY7g11irHR9Dl2OjGQJPT6Z+23E6J/XEWoikp5prZKJoiV0b7wATNhF0idWNFZ6Y1/ffW3hacaDP
0n4hSVP9uMwazCScrvxhKkYO8ODu5RGLGIxj0V03eNMA6+2Cn+fpIpP76wPG5n9u9l5ehIXFBgzd
4879qfki4RHkduOAZgvDTZuK0nLOFdtVt4VqTW/D+Fy8RhVjsIAztCcki0gEfFT/WaBW+KTTRbgU
/fqgDyZOF+zskKrM1RlsoUcj7aHqX0V58tUXHkp4Pv2umVReEAIAQTRSiFxN0mp6AvGlx7eQ45wg
DAnri49x8M3DqULRPRPLhXC7Zs5TBH8vSI320Fi+t1PqA9sP40yvfBlh4dqme1L3IRFj0cIS2FfN
F4vOeY8Sa0VUwPUuzP223oqGklnKqQd0BHvRwJokIsNQB3cREwYsn1cHO/uOWousfWnsDlEoA2yZ
UdssRRfdtMLPVkKXDkmGYo2ujf3Mk3BJ85jfPInEBYXgQ2o9QYD81WoXJ3hiDhDDZdZafsz3GglC
CspG0PVhIpflY2MXW492jlqLFOZufRGA27AjcZVKPcxQiAGwyyz8fPgV3QmxinLgrqbDTvsGXu8/
lB6hVLbjDieTTxefZLSHD0zA9ieJ8wjTGICFpanN505r1plaj8SC3kBcuFHStd5oNKRb37cvnCSy
ZDVxvtg2qAZQApvH5Md8T4dqf/a7hBZXSCXq/nD+aodJaMABNilT43+p5kuC88ZeTIM7jB/1qWm7
nBaZyc3Zr6K0oEDBS9rRnlkQD6XvGJMvnpNuqkDpZ6/oglA0TKXof22MTvgx5lnvrgGoSFjBQyWV
3gLJTgH+aXy7ws0ybOClS0Fg1fTSUYKKNQ6ihYb7pwQeBWGe5v/ksKtNyTUH12jbxqtK3zTkbeFc
SxKxZq1H9GeeC66YVDQzuZTaJqlAmAFNuwmzuTzee5It/b5GUEgsu0WoW4h56FMCjdUIMnvb5UnL
2H/6AWI+JAx19KURvlxSaKeA+eQjZf1A9EBVoC4kR1Obf0tvwXH+cZh0mrvr8q8IQueRwkPELt5Y
ZwLGs3CzgUE5nD1lJao9UhWHw0LHglIWJPurmjZ9rYYuAoMNfqpzvXNHKCAUM1TzR9fbFDaXrxVi
BOsjoKoYFieUltYDYhxsZv0HoKFheVX9NJB/dQHWQTOOtPCWsc1lWzcpgfZZ6GAIs/w0rMIIiW5O
jgZZg2uKYVXL7noHkrVu/XXi2C/Mc7ZbYCXvbhgVZ4ShRwXS+hc8jgFrsl2axmzUsdRaEK7zJZe0
LuZ5qAyBQg1Ic+AXGpESNDJoO5pay3nvE0NPzIXTp7RrlcFZfFRFtOZyr1VeyD6G5SV8uBXTwVYB
H+ViTv8P83R8NdjF44RdfNDWGq1izhDuAXOmsOQfft6ndCqUUivSnm6B3x8BNLR4rByf7O7zPXB9
dn4vr9tkA0D37AsQ8EX94U8xMx4d9+0h0eUNB9j458IHId3as/cYaVciIm0+57uEKMiU7mgSLKlO
qok2/w3G7O5xFXTneFecUPD5GYz9RcHcz9AXq1zzxFHH63nuUOqd0pYwSb5/Nw+I4W5xBxfJz//J
uP+/Qn/zAZ8Rqx/FXGNmuROzVyIef/tDMsMSy9eqqtskBnsV1WSnZ0gfeRzO76HUj9vOmE5xBvz6
tQZSd3zF/01vd64ghdqKGcxNYCUhyT87+m8WcZoJ6EjArXFRhjs3Wj04twXoYZmdl9Dw9nprYw/f
frIy0MD6XhCM5vtyjhMhtL9mFioGi6GF7pcZgCN0MOvgoNn7JoUldxgAiXHB+6o9OyIjTsSc0w32
I+4ufXRqX0jfChvMZoaN1IFcohcqpnCdDVRmQUrqPWSkjjmn5lQSYEYqfssP8CtZgwxk5afdlIpR
wrDkF6IrnWirPT3J+S2G/t8uhSS1lwPc6nm5hOip7LK1jR1Zz4BYQ71sw3ikb/cd2aVsYam9WhBg
I9NcXAgfXiGiwzaroD3fHaFAkmwp4nxhEAjf6M+nVPkE5W8aGQ5CGHY333AQEiwsmrdWZEzkcRSY
ZbJb+fbz7Y7VByc6ekUUK+9vOfHYhex3Mzce1WnLBTEfqp4breBEjcpW9mtvOUBT5ZRSIFOmVeUy
yZaI3ff0FkHSOZzVFpKdSLk4xLMQyQmtG4UVbBGYxQJhY3qOSPUQHaDdDjbaZg5BO5Je9BqyW8Zk
7yf5ugjz3xXVJ+U/ya+rIxN3Mua1pDltyHW/Y9jqQr1Zt0lDRNL0oWr/MEe3Umu0H4vArHtEEI74
UKVHc9yzl2u+b6AqNG3vZdtHJz8kI52rPE1b1RD4iUviKeioDdG0EytM/w4ciWiSl0Yn8XJ8IBtx
SXN3n+UFeodqH5Qpj2l4EEOo+t2PeOakaj+H/5iAgRf+dovf+2NGo3No+QNvD9o+GA8hOrEk8xGL
ybWGTKjIQfl6XA4+4XP8r3ZxC9/KNxH5dbs01U3uPIQRwJqdfl21/xg0GFjBTY7a7cYg8D/GFK/d
vMrHW3HMMr9W1JMLFlICMTfk89bl8uQJfbQHlObmSIx9H5YqyOYeBuuSgZTpLOSz+Vv2UeylDhgY
hzFEJwPpQP37vQpc7qkk5SRM+ISLbbf5/+jDqErQStWp2SrtEZIzST1FXWHSAPxV/Fd+yQ4BIPYq
ZkWE5k+k6+o4NuZ/OkycqwWswCh3w+C9oIRF+qkDLKhaHKI4hb3GdOVJnIQThN24DkJDwlOSN/mB
0tI3AGgsWXoyb0BcU9lAoGQrZPyDZnYsxpali30DZZnyP0OJzssnFTuRUwnuK8eOCJ0EC8ApBVB6
W9s3BhbhGS//5w3+G0gaIm7Vd9vtdvjl6BcOikiSAh5VTg4uuNobv956ugbKqyO7Bo2tjyagzZPF
mgvkLfTJjswj7WS4lP+B7ZV1jUzdpHlIe1VWrETOM0EYjyK1eZflocsr9BmArkQ9co5RqH9pLFlv
KdHUaR3tW5ALzLJkBnE2dHMPsZ7XXQhsNdAM8gLCh3r3gb3vsEHtkDRvdx/wubg8ViCkEClFPBCZ
lalExRGfAoGDISG+hpsjxWgdBIBzhdNc8eDqh14YLfRZZq+PcGP9N4GAhMf/vrRRFPvolgn3yLh9
HKouI6dYfBwpSUpLOaA3riJRL8+JwiREAB2UcUARjbDTGk9Cf5Cbz0X38k8UFP7WCSLbw6ofdQQL
ytISA9N24xAuFI2WRcYXo9oj6bcbR7eAtWaoSzCJQolD5H8u0yB+g+HyDGQCjv9/uvJu1twtCa5E
8f0ys6VEoKvLZntjvJNwbyuCc/nJjgetAM1dDxzqqfy2UJE4kJJhcUOnPkZSnpkuxBEN5j7YIrTM
UkrDLF6aOmvyAM58HUZk/9d3hZPelckdKHfTdBCKugT2Fi0NHmcPaEha0lvCouQGAvLicNIGIlwP
MoOKvOAHHj91gDYlYA7QSutUyYcagGrl6lacHhV5BNwWYrnrDTcCOk+4vF1mVRNTP7fmvBE4/L1x
F/Bd7skiFyvBrukpdLAJVL5jG6dKrmjp2vKKgbhJ90ozrECK4DztOkcdVO3xKrmw7cwjGRVl/9gw
P8ZEYngLNqnvIVy1/XQ9Hkb7OLxiJOyFs6o1BQ2DcsxLFLZowDuzzUAeyzJtJwlh4WCFqrx6yzxT
wKYTvAVegTHO9K6OAem9vIRLX8DnfYGLefsQICpCvyJSCTu4UmcvvQz88BkZIuNZOYmSYoX0VaQY
vsDtQMvzOXe5c2tHtxENBMq50ionUxWpmPOpA522XAidzBs4IQ2Q0EqSthbUJabm4ekb99YfMBi8
pIseF1FSWsJWWMFmEDCFkLMsO9BlFPyqy4w9AiFMlNVXLO8Pct+S9kwzdfFsFRyoj+kiMJWbVc6N
nw6Ucpm4ko8bRv1omBEAoG+Gtj9nKPEr4gT8Z10rNrj0OwjTQHppf8ar6wHA8X9TD7/Nbdzkkccd
DhaQzn800fSUH4Av3N3nnx9XkdnddDn/PAewG51kEgPB9lWvPFaJpE7Qqajl94V8Mn30qPcJgP87
IPC6ImAxTXP+gRdHbO2Pndy8CT4iThDn4VRUn2tES9TllBvJqHHJilTJKRalIuKRJ1XF2vMk+Iim
qkbdMU8fk4rZUQfudp4aqRxcUseB8HNjnmEzJFSMEgZpUkCmmgrhcqAWcQ1EWTcsntAl2nMFxF7i
VgIcCjoOfOmAtrqlUb+CHZ6o88WfnlReysqfOVjSQPjdtzDc0mcqcHAFY0XAbRAGFYiI+2I90nED
WaaXTRQxBDxh86lVjZB2kovLyVgfKUASJey+sEeA26w++6Nnz0GkAwow0pB4pCgRLYxwjL9m8z0G
dSk4k5YVqKXQxPL64kqc1sg3/kjZEh0zlMfKJo/euPVenQ5PYcN5HaBvbrfiRb8Evk71AYeaSQdV
EXS0m7hcS3dHbnQBE/ae917jyH2X4jYCFce7sHrlu5Bk04mQWB/ET2Iuw2AVdSQwjBbHyqK/9L04
FSFcVgE3KvclBvfh4bpCDwbPlv6uujbqMRzAh3MVqNIMqVKP+kRQ7l1A9BpB2oz4clPc+7V6QEIH
nPZbFi4NZK4F3wDzsQaHDeMXglX0bGK6EVY72+HPBhG6EMvBIPkmxk6DUaHmjCz/cZSEp2pPUfvn
VN8mW4QTWLx8XtrWTXONu418CFmN6J5Ltu5yQ/rG9UKCCx3LvpluLq5MXhQFbVtHlLDslx58dkJP
qyI3IBVnAjp+pV7fMLoqZ52ZygWM++pnh8u8bFsQT3N8iGKSHTR/piTfXRGbEuIM6gyOeJsDfywj
Il/8V0j4YnNK3eyDzHctrENapkUnqO5hFLKwAZ4mALRVL33KJTUnpcobEIaIEjyT4086LPia1SV9
RhyseN5T0EQLEIARXK5Ictc0rLqpgTkLSxyGYRNP7ReV
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo2.vhd | 15 | 14428 | -------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
| mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/s1.vhd | 2 | 3979 | library ieee;
use ieee.std_logic_1164.all;
entity s1 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s1;
architecture behaviour of s1 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
end case;
end process;
end; | mit |
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