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`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/blk_mem_gen_v8_1/blk_mem_gen_mux.vhd | 27 | 91985 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 66352)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/blk_mem_gen_v8_1/blk_mem_gen_mux.vhd | 27 | 91985 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 66352)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/async_fifo.vhd | 19 | 33343 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/async_fifo.vhd | 19 | 33343 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
`protect data_block
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| mit |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/ipcore_dir/blk_mem_gen_v7_3/simulation/addr_gen.vhd | 101 | 4409 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/fifo_generator_v11_0/builtin/builtin_extdepth_v6.vhd | 19 | 50137 | `protect begin_protected
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`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/compare.vhd | 19 | 11879 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7056)
`protect data_block
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`protect end_protected
| mit |
frankvanbever/MIPS_processor | programcounter.vhd | 1 | 2001 | -------------------------------------------------------------------------------
-- Title : program counter
-- Project :
-------------------------------------------------------------------------------
-- File : programcounter.vhd
-- Author : Frank Vanbever <frank@neuromancer>
-- Company :
-- Created : 2013-02-13
-- Last update: 2013-02-13
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: program counter for a MIPS processor
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-13 1.0 frank Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pc is
port (
clk : in std_logic;
reset : in std_logic;
PC_in : in std_logic_vector(31 downto 0);
PC_out : out std_logic_vector(31 downto 0));
end pc;
architecture behavioral of pc is
signal PC_reset : std_logic;
begin -- behavioral
-----------------------------------------------------------------------------
setPCd : process (clk, PC_in, PC_reset)
begin -- process setPCd
if rising_edge(clk) then
if PC_reset = '1' then
PC_out <= (others => '0');
else
PC_out <= PC_in;
end if;
end if;
end process setPCd;
-------------------------------------------------------------------------------
resetPC : process (clk, reset)
begin -- process resetPC
if reset = '1' then -- asynchronous reset
PC_reset <= '1';
elsif (rising_edge(clk)) and (reset = '0') then -- rising clock edge
PC_reset <= '0';
end if;
end process resetPC;
end behavioral;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/builtin/reset_builtin.vhd | 19 | 19078 | `protect begin_protected
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/interrupt_control_v3_0/hdl/src/vhdl/interrupt_control.vhd | 6 | 57024 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_0
-- ~~~~~~
-- - Modified to used proc_common_v4_0 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
Use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/ld_arith_reg2.vhd | 15 | 17134 | -------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
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-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/ld_arith_reg2.vhd | 15 | 17134 | -------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/dmem.vhd | 19 | 12333 | `protect begin_protected
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7392)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/builtin/builtin_top_v6.vhd | 19 | 52905 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/builtin/builtin_top_v6.vhd | 19 | 52905 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
hB1MkDF7gDUjtp9+r0pYANUYTDYvtQO1sWNXspOA3ppM8SYB929/qlOMzanhENZQcOQ3aiyEm3Wb
ozapXP+k8w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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gXG23tcqWGm/l3ZWHVqrETjEni8mwIO1yFoO4g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/builtin/builtin_top_v6.vhd | 19 | 52905 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pf_dpram_select.vhd | 15 | 118961 | -------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
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-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** Xilinx products are not intended for use in life support **
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-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
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-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/proc_common_v4_0/hdl/src/vhdl/srl16_fifo.vhd | 15 | 13201 | -------------------------------------------------------------------------------
-- $Id: srl16_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl16_fifo.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl16_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl16_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: D.Thorpe
--
-- History:
-- DET 2001-10-11 First Version adapted from Goran B. srl_fifo.vhd
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x"
-- Bus_rst signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_adder;
use proc_common_v4_0.pf_counter_top;
use proc_common_v4_0.pf_occ_counter_top;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity srl16_fifo is
generic (
C_FIFO_WIDTH : integer range 1 to 128 := 8;
-- Width of FIFO Data Bus
C_FIFO_DEPTH_LOG2X : integer range 2 to 4 := 4;
-- Depth of FIFO in address bit width
-- ie 4 = 16 locations deep
-- 3 = 8 locations deep
-- 2 = 4 ocations deep
C_INCLUDE_VACANCY : Boolean := true
-- Command to include vacancy calculation
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
Wr_Req : in std_logic;
Wr_Data : in std_logic_vector(0 to C_FIFO_WIDTH-1);
Rd_Req : in std_logic;
Rd_Data : out std_logic_vector(0 to C_FIFO_WIDTH-1);
Full : out std_logic;
Almostfull : Out std_logic;
Empty : Out std_logic;
Almostempty : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X)
);
end entity srl16_fifo;
-------------------------------------------------------------------------------
architecture implementation of srl16_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Signal sig_occupancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_occ_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_addr_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
Signal sig_logic_low : std_logic;
signal sig_almost_full : std_logic;
signal sig_full : std_logic;
signal sig_almost_empty : std_logic;
signal sig_empty : std_logic;
signal sig_valid_write : std_logic;
signal sig_inc_addr : std_logic;
signal sig_dec_addr : std_logic;
signal sig_valid_read : std_logic;
signal sig_addr : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_srl_addr : std_logic_vector(0 to 3);
signal sig_addr_is_nonzero : std_logic;
signal sig_addr_is_zero : std_logic;
begin -- architecture implementation
-- Misc I/O
Full <= sig_full;
Almostfull <= sig_almost_full;
Empty <= sig_empty;
Almostempty <= sig_almost_empty;
Occupancy <= sig_occupancy;
----------------------------------------------------------------------------
-- Occupancy Counter Function
----------------------------------------------------------------------------
sig_occ_load_value <= (others => '0');
sig_logic_low <= '0';
I_OCCUPANCY_CNTR : entity proc_common_v4_0.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X+1
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_occ_load_value,
Count_Down => sig_valid_read,
Count_Up => sig_valid_write,
By_2 => sig_logic_low,
Count_Out => sig_occupancy,
almost_full => sig_almost_full,
full => sig_full,
almost_empty => sig_almost_empty,
empty => sig_empty
);
----------------------------------------------------------------------------
-- Address Counter Function
----------------------------------------------------------------------------
sig_addr_load_value <= (others => '0');
sig_addr_is_nonzero <= (sig_srl_addr(0)
or sig_srl_addr(1)
or sig_srl_addr(2)
or sig_srl_addr(3));
sig_addr_is_zero <= not(sig_addr_is_nonzero);
sig_valid_write <= Wr_Req and not(sig_full);
sig_valid_read <= Rd_Req and not(sig_empty);
sig_inc_addr <= (sig_valid_write and not(sig_empty))
and not(sig_valid_read and sig_addr_is_zero);
sig_dec_addr <= sig_valid_read and sig_addr_is_nonzero;
I_ADDR_CNTR : entity proc_common_v4_0.pf_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_addr_load_value,
Count_Down => sig_dec_addr,
Count_Up => sig_inc_addr,
Count_Out => sig_addr
);
ASSIGN_ADDRESS : process(sig_addr)
Begin
sig_srl_addr <= (others => '0'); -- assign default values
for i in 0 to C_FIFO_DEPTH_LOG2X-1 loop
sig_srl_addr((4-C_FIFO_DEPTH_LOG2X)+i) <= sig_addr(i);
end loop;
end process ASSIGN_ADDRESS;
----------------------------------------------------------------------------
-- SRL memory function
----------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_FIFO_WIDTH-1 generate
I_SRL16E : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => sig_valid_write,
D => Wr_Data(i),
Clk => Bus_clk,
A0 => sig_srl_addr(3),
A1 => sig_srl_addr(2),
A2 => sig_srl_addr(1),
A3 => sig_srl_addr(0),
Q => Rd_Data(i)
);
end generate FIFO_RAM;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Constant OCC_CNTR_WIDTH : integer := C_FIFO_DEPTH_LOG2X+1;
Constant MAX_OCCUPANCY : integer := 2**C_FIFO_DEPTH_LOG2X;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity proc_common_v4_0.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => sig_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end architecture implementation;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/fifo_generator_v11_0/ramfifo/clk_x_pntrs.vhd | 19 | 35009 | `protect begin_protected
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`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/inferred_lut4.vhd | 15 | 7214 | -------------------------------------------------------------------------------
-- $Id: inferred_lut4.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- inferred_lut4.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: inferred_lut4.vhd
--
-- Description: This module is used to infer a LUT4 instantiation in
-- structural VHDL. It is compatable with Synplicity and xst
-- synthesis tools.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- inferred_lut4.vhd
--
-------------------------------------------------------------------------------
-- Author: D.Thorpe
--
-- History:
-- DET 2001-10-11 LUT4 implementation to work around xst lut4 problem with
-- INIT generic. Adapted from XST France work-around
-- solution sent to Bert Tise.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x"
-- Bus_rst signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end entity inferred_lut4;
-------------------------------------------------------------------------------
architecture implementation of inferred_lut4 is
signal b : std_logic_vector(3 downto 0);
signal tmp : integer range 0 to 15;
begin
b <= (I3, I2, I1, I0);
tmp <= conv_integer(b);
O <= To_StdUlogic(INIT(tmp));
end architecture implementation;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/full_axi.vhd | 7 | 43438 | -------------------------------------------------------------------------------
-- full_axi.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: full_axi.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller when configured in a full AXI4 mode.
-- The rd_chnl and wr_chnl modules are instantiated.
-- The ECC AXI-Lite register module is instantiated, if enabled.
-- When single port BRAM mode is selected, the arbitration logic
-- is instantiated (and connected to each wr_chnl & rd_chnl).
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/15/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter and mappings on instantiated modules.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update WE & BRAM data sizes based on 128-bit ECC configuration.
-- Plus XST clean-up.
-- ^^^^^^
-- JLJ 3/31/2011 v1.03a
-- ~~~~~~
-- Add coverage tags.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add signal, AW2Arb_BVALID_Cnt, between wr_chnl and sng_port_arb modules.
-- ^^^^^^
-- JLJ 4/20/2011 v1.03a
-- ~~~~~~
-- Add default values for Arb2AW_Active & Arb2AR_Active when dual port mode.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
use work.lite_ecc_reg;
use work.sng_port_arb;
use work.wr_chnl;
use work.rd_chnl;
------------------------------------------------------------------------------
entity full_axi is
generic (
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Clock and Reset
-- TBD
-- S_AXI_CTRL_ACLK : in std_logic;
-- S_AXI_CTRL_ARESETN : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- BRAM Interface Signals (Port A)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- BRAM Interface Signals (Port B)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity full_axi;
-------------------------------------------------------------------------------
architecture implementation of full_axi is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-- Internal AXI Signals
signal S_AXI_AWREADY_i : std_logic := '0';
signal S_AXI_ARREADY_i : std_logic := '0';
-- Internal BRAM Signals
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_En_A_i : std_logic := '0';
signal BRAM_En_B_i : std_logic := '0';
signal BRAM_WE_A_i : std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal BRAM_RdData_i : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
-- Internal ECC Signals
signal Enable_ECC : std_logic := '0';
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Wr_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Wr_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Wr_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Rd_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Rd_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Rd_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal FaultInjectECC_i : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Wr_BRAM_Addr_En : std_logic := '0';
signal Rd_BRAM_Addr_En : std_logic := '0';
-- Internal Arbitration Signals
signal Arb2AW_Active : std_logic := '0';
signal AW2Arb_Busy : std_logic := '0';
signal AW2Arb_Active_Clr : std_logic := '0';
signal AW2Arb_BVALID_Cnt : std_logic_vector (2 downto 0) := (others => '0');
signal Arb2AR_Active : std_logic := '0';
signal AR2Arb_Active_Clr : std_logic := '0';
signal WrChnl_BRAM_Addr_Rst : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal WrChnl_BRAM_Addr_Inc : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal RdChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal RdChnl_BRAM_Addr_Inc : std_logic := '0';
signal RdChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal bram_addr_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** BRAM Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: ADDR_SNG_PORT
-- Purpose: OR the BRAM_Addr outputs from each wr_chnl & rd_chnl
-- Only one write or read will be active at a time.
-- Ensure that ecah channel address is driven to '0' when not in use.
---------------------------------------------------------------------------
ADDR_SNG_PORT: if C_SINGLE_PORT_BRAM = 1 generate
signal sng_bram_addr_rst : std_logic := '0';
signal sng_bram_addr_ld_en : std_logic := '0';
signal sng_bram_addr_ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal sng_bram_addr_inc : std_logic := '0';
begin
-- BRAM_Addr_A <= BRAM_Addr_A_i or BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Arb2AW_Active = '1') else BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Active_Wr = '1') else BRAM_Addr_B_i;
-- Insert mux on address counter control signals
sng_bram_addr_rst <= WrChnl_BRAM_Addr_Rst;
sng_bram_addr_ld_en <= WrChnl_BRAM_Addr_Ld_En or RdChnl_BRAM_Addr_Ld_En;
sng_bram_addr_ld <= RdChnl_BRAM_Addr_Ld when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Ld;
sng_bram_addr_inc <= RdChnl_BRAM_Addr_Inc when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Inc;
I_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (sng_bram_addr_rst = '1') then
bram_addr_int <= (others => '0');
elsif (sng_bram_addr_ld_en = '1') then
bram_addr_int <= sng_bram_addr_ld;
elsif (sng_bram_addr_inc = '1') then
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process I_ADDR_CNT;
BRAM_Addr_B <= (others => '0');
BRAM_En_A <= BRAM_En_A_i or BRAM_En_B_i;
-- BRAM_En_A <= BRAM_En_A_i when (Arb2AW_Active = '1') else BRAM_En_B_i;
BRAM_En_B <= '0';
BRAM_RdData_i <= BRAM_RdData_A; -- Assign read data port A
BRAM_WE_A <= BRAM_WE_A_i when (Arb2AW_Active = '1') else (others => '0');
-- v1.03a
-- Early register on WrData and WSTRB in wr_chnl. (Previous value was always cleared).
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
end generate ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: ADDR_DUAL_PORT
-- Purpose: Assign each BRAM address when in a dual port controller
-- configuration.
---------------------------------------------------------------------------
ADDR_DUAL_PORT: if C_SINGLE_PORT_BRAM = 0 generate
begin
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
BRAM_En_A <= BRAM_En_A_i;
BRAM_En_B <= BRAM_En_B_i;
BRAM_WE_A <= BRAM_WE_A_i;
BRAM_RdData_i <= BRAM_RdData_B; -- Assign read data port B
end generate ADDR_DUAL_PORT;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
GEN_NO_REGS: if (C_ECC = 0) generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
Enable_ECC <= '0';
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
-- For future implementation.
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- TBD
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
-- Add AXI-Lite ECC Register Ports
AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
-- BRAM_RdData_A => BRAM_RdData_A (C_S_AXI_DATA_WIDTH-1 downto 0) ,
-- BRAM_RdData_B => BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0) ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC_i
);
BRAM_Addr_En <= Wr_BRAM_Addr_En or Rd_BRAM_Addr_En;
-- v1.03a
-- Add coverage tags for Wr_CE_Failing_We.
-- No testing on forcing errors with RMW and AXI write transfers.
--coverage off
CE_Failing_We <= Wr_CE_Failing_We or Rd_CE_Failing_We;
Sl_CE <= Wr_Sl_CE or Rd_Sl_CE;
Sl_UE <= Wr_Sl_UE or Rd_Sl_UE;
--coverage on
-------------------------------------------------------------------
-- Generate: GEN_32
-- Purpose: Add MSB '0' on ECC vector as only 7-bits wide in 32-bit.
-------------------------------------------------------------------
GEN_32: if C_S_AXI_DATA_WIDTH = 32 generate
begin
FaultInjectECC <= '0' & FaultInjectECC_i;
end generate GEN_32;
-------------------------------------------------------------------
-- Generate: GEN_NON_32
-- Purpose: Data widths match at 8-bits for ECC on 64-bit data.
-- And 9-bits for 128-bit data.
-------------------------------------------------------------------
GEN_NON_32: if C_S_AXI_DATA_WIDTH /= 32 generate
begin
FaultInjectECC <= FaultInjectECC_i;
end generate GEN_NON_32;
end generate GEN_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_ARB
-- Purpose: Generate arbitration module when AXI4 is configured in
-- single port mode.
---------------------------------------------------------------------------
GEN_ARB: if (C_SINGLE_PORT_BRAM = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_SNG_PORT : entity work.sng_port_arb
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY ,
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr
);
end generate GEN_ARB;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL
-- Purpose: Dual mode. AWREADY and ARREADY are generated from each
-- wr_chnl and rd_chnl module.
---------------------------------------------------------------------------
GEN_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
S_AXI_AWREADY <= S_AXI_AWREADY_i;
S_AXI_ARREADY <= S_AXI_ARREADY_i;
Arb2AW_Active <= '0';
Arb2AR_Active <= '0';
end generate GEN_DUAL;
---------------------------------------------------------------------------
-- Instance: I_WR_CHNL
--
-- Description:
-- BRAM controller write channel logic. Controls AXI bus handshaking and
-- data flow on the write address (AW), write data (W) and
-- write response (B) channels.
--
-- BRAM signals are marked as output from Wr Chnl for future implementation
-- of merging Wr/Rd channel outputs to a single port of the BRAM module.
--
---------------------------------------------------------------------------
I_WR_CHNL : entity work.wr_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_AWID => S_AXI_AWID ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWLEN => S_AXI_AWLEN ,
AXI_AWSIZE => S_AXI_AWSIZE ,
AXI_AWBURST => S_AXI_AWBURST ,
AXI_AWLOCK => S_AXI_AWLOCK ,
AXI_AWCACHE => S_AXI_AWCACHE ,
AXI_AWPROT => S_AXI_AWPROT ,
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY_i ,
AXI_WDATA => S_AXI_WDATA ,
AXI_WSTRB => S_AXI_WSTRB ,
AXI_WLAST => S_AXI_WLAST ,
AXI_WVALID => S_AXI_WVALID ,
AXI_WREADY => S_AXI_WREADY ,
AXI_BID => S_AXI_BID ,
AXI_BRESP => S_AXI_BRESP ,
AXI_BVALID => S_AXI_BVALID ,
AXI_BREADY => S_AXI_BREADY ,
-- Arb Ports
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Sng_BRAM_Addr_Rst => WrChnl_BRAM_Addr_Rst ,
Sng_BRAM_Addr_Ld_En => WrChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => WrChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => WrChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Wr_BRAM_Addr_En ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => Wr_CE_Failing_We ,
Sl_CE => Wr_Sl_CE ,
Sl_UE => Wr_Sl_UE ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC ,
BRAM_En => BRAM_En_A_i ,
-- BRAM_WE => BRAM_WE_A ,
-- 4/13
BRAM_WE => BRAM_WE_A_i ,
BRAM_WrData => BRAM_WrData_A ,
BRAM_RdData => BRAM_RdData_A ,
BRAM_Addr => BRAM_Addr_A_i
);
---------------------------------------------------------------------------
-- Instance: I_RD_CHNL
--
-- Description:
-- BRAM controller read channel logic. Controls all handshaking and data
-- flow on read address (AR) and read data (R) AXI channels.
--
-- BRAM signals are marked as Rd Chnl signals for future implementation
-- of merging Rd/Wr BRAM signals to a single BRAM port.
--
---------------------------------------------------------------------------
I_RD_CHNL : entity work.rd_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_ARID => S_AXI_ARID ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARLEN => S_AXI_ARLEN ,
AXI_ARSIZE => S_AXI_ARSIZE ,
AXI_ARBURST => S_AXI_ARBURST ,
AXI_ARLOCK => S_AXI_ARLOCK ,
AXI_ARCACHE => S_AXI_ARCACHE ,
AXI_ARPROT => S_AXI_ARPROT ,
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY_i ,
AXI_RID => S_AXI_RID ,
AXI_RDATA => S_AXI_RDATA ,
AXI_RRESP => S_AXI_RRESP ,
AXI_RLAST => S_AXI_RLAST ,
AXI_RVALID => S_AXI_RVALID ,
AXI_RREADY => S_AXI_RREADY ,
-- Arb Ports
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr ,
Sng_BRAM_Addr_Ld_En => RdChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => RdChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => RdChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Rd_BRAM_Addr_En ,
CE_Failing_We => Rd_CE_Failing_We ,
Sl_CE => Rd_Sl_CE ,
Sl_UE => Rd_Sl_UE ,
BRAM_En => BRAM_En_B_i ,
BRAM_Addr => BRAM_Addr_B_i ,
BRAM_RdData => BRAM_RdData_i
);
end architecture implementation;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/muxf_struct_f.vhd | 15 | 15871 | -------------------------------------------------------------------------------
-- $Id: muxf_struct_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: muxf_struct_f.vhd
--
-- Description: Given a vector of input bits, Iv (not necessarily a
-- power of two). and a select value, Sel, this block
-- will build the multiplexing function
--
-- O <= Iv(Sel)
--
-- using the MUXF (MUXF5, MUXF6, etc.) primitives of
-- the target FPGA family, C_FAMILY, if possible and,
-- otherwise, using inferred multiplexers.
--
-- Since MUXF primitives are targeted, it is proper
-- that the Iv signals are driven by LUTs.
--
-- A help entity, muxf_struct, which is instantiated
-- recursively, is used to facilitate the implementation.
-- (So, compiling this file will add two entities,
-- muxf_struct and muxf_struct_f, to the target library.)
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- muxf_struct_f.vhd
-- muxf_struct (entity and architecture in this file)
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
--------------------------------------------------------------------------------
-- This is a helper entity. The entity declaration for muxf_struct_f is
-- further, below.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.family_support.all; -- supported, primitives_type
library unisim;
entity muxf_struct is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_NI_PO2E : positive; -- Num Inputs, Power-of-2 Envelope
C_FAMILY : string
);
port (
LO : out std_logic; -- Normally only one of
O : out std_logic; -- LO or O would be used.
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NI_PO2E)-1)
);
end entity muxf_struct;
library proc_common_v4_0;
library unisim;
use unisim.all; -- Makes unisim entities available for default binding.
--------------------------------------------------------------------------------
-- Line-length guideline purposely not followed in some places to expose parallel code structures.
--------------------------------------------------------------------------------
architecture imp of muxf_struct is
--
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
--
constant SIZE : natural := Iv'length;
constant PO2E : natural := C_NI_PO2E;
constant THIS_LEVEL : natural := C_START_LEVEL + clog2(PO2E);
constant K_FAMILY : families_type := str2fam(C_FAMILY);
constant S5 : boolean := supported(K_FAMILY, u_MUXF5_D) and THIS_LEVEL = 5;
constant S6 : boolean := supported(K_FAMILY, u_MUXF6_D) and THIS_LEVEL = 6;
constant S7 : boolean := supported(K_FAMILY, u_MUXF7_D) and THIS_LEVEL = 7;
constant S8 : boolean := supported(K_FAMILY, u_MUXF8_D) and THIS_LEVEL = 8;
constant INFERRED : boolean := not(S5 or S6 or S7 or S8);
--
signal s, i0, i1 : std_logic; -- If there is no i1 at a particular mux level,
-- it is left undriven and s is tied to '0'.
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF6_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF7_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF8_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Below, some generates and component instantiations are one per line
-- to show similarities and differences.
----------------------------------------------------------------------------
-- Base instance, just one or two inputs, no recursion.
----------------------------------------------------------------------------
E2_GEN : if PO2E=2 and SIZE=2 generate s <= Sel(0); i0 <= Iv(0); i1 <= Iv(1); end generate;
E1_GEN : if PO2E=2 and SIZE=1 generate s <= '0'; i0 <= Iv(0); end generate;-- No driver for i1
----------------------------------------------------------------------------
-- Use recursion to get lower-level mux structures to feed the mux at
-- this level.
----------------------------------------------------------------------------
GT2_GEN : if PO2E > 2 generate
constant NE : natural := PO2E/2; -- Next envelope.
constant BOTH : boolean := (SIZE > NE); -- Needs recursive call for
-- both the left and right sides; otherwise just a left-side
-- recursive call is needed (with C_NI_PO2E reduced by half) and Iv
-- passed down unchanged.
constant LSIZE : natural := bo2na(BOTH) * (2**(clog2(SIZE))/2)
+ bo2na(not BOTH) * SIZE;
-- 1st option above: LSIZE is next smaller power of 2
-- 2nd option above: SIZE is passed down unchanged
begin
LEFT_GEN : IF true generate
I_I0 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i0,
O => open,
Iv => Iv(0 to LSIZE-1),
Sel => Sel(1 to Sel'right)
)
;
end generate;
RIGHT_GEN : IF BOTH generate
I_I1 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => SIZE-LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i1,
O => open,
Iv => Iv(LSIZE to SIZE-1),
Sel => Sel(1 to Sel'right)
)
;
s <= Sel(0);
end generate;
LEFT_ONLY_GEN : IF not BOTH generate
s <= '0';
end generate;
end generate;
-- Instantiate the mux at this level.
--
-- Structurals
S5_GEN : if S5 generate I_F5 : component MUXF5_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S6_GEN : if S6 generate I_F6 : component MUXF6_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S7_GEN : if S7 generate I_F7 : component MUXF7_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S8_GEN : if S8 generate I_F8 : component MUXF8_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
-- Inferred
INFERRED_GEN : if INFERRED generate
signal h : std_logic;
begin
h <= i0 when s = '0' else i1 ;
LO <= h;
O <= h;
END generate;
end architecture imp;
---)
---(
--------------------------------------------------------------------------------
-- Generic descriptions
--------------------------------------------------------------------------------
-- C_START_LEVEL : natural - The size of the LUTs feeding into MUXFN network.
-- For example, for six-input LUTs,
-- C__START_LEVEL = 6 and the first level of muxes
-- are MUXF7.
-- C_NUM_INPUTS : positive - The number of inputs to be muxed.
-- C_FAMILY : string - The target FPGA family.
--------------------------------------------------------------------------------
-- Port descriptions
--------------------------------------------------------------------------------
-- O : out std_logic - Mux ouput
-- Iv : in std_logic_vector(0 to C_NUM_INPUTS-1) - Mux inputs
-- Sel: in std_logic_vector(0 to log2(C_NUM_INPUTS) - 1) - Select lines.
-- - The Iv values must be ordered such that the correct
-- - one is selected according to O <= Iv(Sel).
--------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
--
entity muxf_struct_f is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_FAMILY : string
);
port (
O : out std_logic;
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NUM_INPUTS) - 1)
);
end muxf_struct_f;
architecture imp of muxf_struct_f is
begin
MUXF_STRUCT_I : entity proc_common_v4_0.muxf_struct
generic map (
C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => C_NUM_INPUTS,
C_NI_PO2E => 2**clog2(C_NUM_INPUTS),
C_FAMILY => C_FAMILY
)
port map (
LO => open,
O => O,
Iv => Iv,
Sel => Sel
);
end imp;
---)
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/proc_common_v4_0/hdl/src/vhdl/muxf_struct_f.vhd | 15 | 15871 | -------------------------------------------------------------------------------
-- $Id: muxf_struct_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: muxf_struct_f.vhd
--
-- Description: Given a vector of input bits, Iv (not necessarily a
-- power of two). and a select value, Sel, this block
-- will build the multiplexing function
--
-- O <= Iv(Sel)
--
-- using the MUXF (MUXF5, MUXF6, etc.) primitives of
-- the target FPGA family, C_FAMILY, if possible and,
-- otherwise, using inferred multiplexers.
--
-- Since MUXF primitives are targeted, it is proper
-- that the Iv signals are driven by LUTs.
--
-- A help entity, muxf_struct, which is instantiated
-- recursively, is used to facilitate the implementation.
-- (So, compiling this file will add two entities,
-- muxf_struct and muxf_struct_f, to the target library.)
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- muxf_struct_f.vhd
-- muxf_struct (entity and architecture in this file)
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
--------------------------------------------------------------------------------
-- This is a helper entity. The entity declaration for muxf_struct_f is
-- further, below.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.family_support.all; -- supported, primitives_type
library unisim;
entity muxf_struct is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_NI_PO2E : positive; -- Num Inputs, Power-of-2 Envelope
C_FAMILY : string
);
port (
LO : out std_logic; -- Normally only one of
O : out std_logic; -- LO or O would be used.
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NI_PO2E)-1)
);
end entity muxf_struct;
library proc_common_v4_0;
library unisim;
use unisim.all; -- Makes unisim entities available for default binding.
--------------------------------------------------------------------------------
-- Line-length guideline purposely not followed in some places to expose parallel code structures.
--------------------------------------------------------------------------------
architecture imp of muxf_struct is
--
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
--
constant SIZE : natural := Iv'length;
constant PO2E : natural := C_NI_PO2E;
constant THIS_LEVEL : natural := C_START_LEVEL + clog2(PO2E);
constant K_FAMILY : families_type := str2fam(C_FAMILY);
constant S5 : boolean := supported(K_FAMILY, u_MUXF5_D) and THIS_LEVEL = 5;
constant S6 : boolean := supported(K_FAMILY, u_MUXF6_D) and THIS_LEVEL = 6;
constant S7 : boolean := supported(K_FAMILY, u_MUXF7_D) and THIS_LEVEL = 7;
constant S8 : boolean := supported(K_FAMILY, u_MUXF8_D) and THIS_LEVEL = 8;
constant INFERRED : boolean := not(S5 or S6 or S7 or S8);
--
signal s, i0, i1 : std_logic; -- If there is no i1 at a particular mux level,
-- it is left undriven and s is tied to '0'.
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF6_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF7_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF8_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Below, some generates and component instantiations are one per line
-- to show similarities and differences.
----------------------------------------------------------------------------
-- Base instance, just one or two inputs, no recursion.
----------------------------------------------------------------------------
E2_GEN : if PO2E=2 and SIZE=2 generate s <= Sel(0); i0 <= Iv(0); i1 <= Iv(1); end generate;
E1_GEN : if PO2E=2 and SIZE=1 generate s <= '0'; i0 <= Iv(0); end generate;-- No driver for i1
----------------------------------------------------------------------------
-- Use recursion to get lower-level mux structures to feed the mux at
-- this level.
----------------------------------------------------------------------------
GT2_GEN : if PO2E > 2 generate
constant NE : natural := PO2E/2; -- Next envelope.
constant BOTH : boolean := (SIZE > NE); -- Needs recursive call for
-- both the left and right sides; otherwise just a left-side
-- recursive call is needed (with C_NI_PO2E reduced by half) and Iv
-- passed down unchanged.
constant LSIZE : natural := bo2na(BOTH) * (2**(clog2(SIZE))/2)
+ bo2na(not BOTH) * SIZE;
-- 1st option above: LSIZE is next smaller power of 2
-- 2nd option above: SIZE is passed down unchanged
begin
LEFT_GEN : IF true generate
I_I0 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i0,
O => open,
Iv => Iv(0 to LSIZE-1),
Sel => Sel(1 to Sel'right)
)
;
end generate;
RIGHT_GEN : IF BOTH generate
I_I1 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => SIZE-LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i1,
O => open,
Iv => Iv(LSIZE to SIZE-1),
Sel => Sel(1 to Sel'right)
)
;
s <= Sel(0);
end generate;
LEFT_ONLY_GEN : IF not BOTH generate
s <= '0';
end generate;
end generate;
-- Instantiate the mux at this level.
--
-- Structurals
S5_GEN : if S5 generate I_F5 : component MUXF5_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S6_GEN : if S6 generate I_F6 : component MUXF6_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S7_GEN : if S7 generate I_F7 : component MUXF7_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S8_GEN : if S8 generate I_F8 : component MUXF8_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
-- Inferred
INFERRED_GEN : if INFERRED generate
signal h : std_logic;
begin
h <= i0 when s = '0' else i1 ;
LO <= h;
O <= h;
END generate;
end architecture imp;
---)
---(
--------------------------------------------------------------------------------
-- Generic descriptions
--------------------------------------------------------------------------------
-- C_START_LEVEL : natural - The size of the LUTs feeding into MUXFN network.
-- For example, for six-input LUTs,
-- C__START_LEVEL = 6 and the first level of muxes
-- are MUXF7.
-- C_NUM_INPUTS : positive - The number of inputs to be muxed.
-- C_FAMILY : string - The target FPGA family.
--------------------------------------------------------------------------------
-- Port descriptions
--------------------------------------------------------------------------------
-- O : out std_logic - Mux ouput
-- Iv : in std_logic_vector(0 to C_NUM_INPUTS-1) - Mux inputs
-- Sel: in std_logic_vector(0 to log2(C_NUM_INPUTS) - 1) - Select lines.
-- - The Iv values must be ordered such that the correct
-- - one is selected according to O <= Iv(Sel).
--------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
--
entity muxf_struct_f is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_FAMILY : string
);
port (
O : out std_logic;
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NUM_INPUTS) - 1)
);
end muxf_struct_f;
architecture imp of muxf_struct_f is
begin
MUXF_STRUCT_I : entity proc_common_v4_0.muxf_struct
generic map (
C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => C_NUM_INPUTS,
C_NI_PO2E => 2**clog2(C_NUM_INPUTS),
C_FAMILY => C_FAMILY
)
port map (
LO => open,
O => O,
Iv => Iv,
Sel => Sel
);
end imp;
---)
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/blk_mem_gen_v8_1/blk_mem_gen_ecc_decoder.vhd | 27 | 24873 | `protect begin_protected
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/fifo_generator_v11_0/builtin/delay.vhd | 19 | 10088 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/blk_mem_gen_v8_1/blk_mem_axi_write_wrapper.vhd | 27 | 66283 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 47328)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/blk_mem_gen_v8_1/blk_mem_axi_write_wrapper.vhd | 27 | 66283 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 47328)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/blk_mem_gen_v8_1/blk_mem_axi_write_wrapper.vhd | 27 | 66283 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 47328)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/blk_mem_gen_v8_1/blk_mem_gen_v8_1_pkg.vhd | 27 | 123409 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 89616)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/blk_mem_gen_v8_1/blk_mem_gen_v8_1_pkg.vhd | 27 | 123409 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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bTzbr9/qZQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 89616)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/pf_counter_bit.vhd | 15 | 10926 | -------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
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-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
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-- ** code, or information as one possible implementation of **
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-- ** code and therefore cannot answer specific questions related **
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-- ** of this text at all times. **
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common v2_00_a library.
-- ^^^^^^
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
Use proc_common_v4_0.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pf_counter_bit.vhd | 15 | 10926 | -------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common v2_00_a library.
-- ^^^^^^
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
Use proc_common_v4_0.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/fifo_generator_v11_0/ramfifo/bram_fifo_rstlogic.vhd | 19 | 21262 | `protect begin_protected
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`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/pf_occ_counter.vhd | 15 | 10945 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter.vhd
--
-- Description: Implements packet fifo occupancy counter. This special
-- counter provides these functions:
-- - up/down count control
-- - pre-increment/pre-decrement of input load value
-- - count by 2
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- D. Thorpe 2001-09-07 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst signal connect to the pf_counter_bit module
--
-- DET 2002-02-24
-- - Changed the use of MUXCY_L to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Cnt_by_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_occ_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter is
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal count_clock_en : std_logic;
signal carry_out_lsb : std_logic;
signal carry_in_lsb : std_logic;
signal count_out_lsb : std_logic;
Signal mux_cnt_in_lsb : std_logic;
Signal carry_out_select_di: std_logic;
Signal carry_start : std_logic;
Signal carry_start_select : std_logic;
Signal by_2_carry_start : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
count_clock_en <= Count_Enable or Count_Load;
MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
mux_cnt_in_lsb <= count_out_lsb;
else
mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1);
End if;
End process MUX_THE_LSB_INPUT;
carry_start <= Count_Down xor Count_Enable;
by_2_carry_start <= Cnt_by_2 and Count_Down;
carry_start_select <= not(Cnt_by_2);
I_MUXCY_LSB_IN : MUXCY
port map (
DI => by_2_carry_start,
CI => carry_start,
S => carry_start_select,
O => carry_in_lsb);
I_COUNTER_BIT_LSB : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => mux_cnt_in_lsb,
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => carry_in_lsb,
Clock_Enable => count_clock_en,
Result => count_out_lsb,
Carry_Out => carry_out_lsb);
carry_out_select_di <= Count_Down xor Cnt_by_2;
I_MUXCY_LSB_OUT : MUXCY
port map (
DI => carry_out_select_di,
CI => carry_out_lsb,
S => carry_start_select,
O => alu_cy(C_COUNT_WIDTH-1));
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate
begin
MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
i_mux_Count_Out(i) <= iCount_Out(i);
else
i_mux_Count_Out(i) <= Load_In(i);
End if;
End process MUX_THE_INPUT;
Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => i_mux_Count_Out(i),
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => alu_cy(i+1),
Clock_Enable => count_clock_en,
Result => iCount_Out(i),
Carry_Out => alu_cy(i));
end generate I_ADDSUB_GEN;
Count_Out <= iCount_Out & count_out_lsb;
Carry_Out <= '0';
end architecture implementation;
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/pf_occ_counter.vhd | 15 | 10945 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter.vhd
--
-- Description: Implements packet fifo occupancy counter. This special
-- counter provides these functions:
-- - up/down count control
-- - pre-increment/pre-decrement of input load value
-- - count by 2
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- D. Thorpe 2001-09-07 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst signal connect to the pf_counter_bit module
--
-- DET 2002-02-24
-- - Changed the use of MUXCY_L to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Cnt_by_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_occ_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter is
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal count_clock_en : std_logic;
signal carry_out_lsb : std_logic;
signal carry_in_lsb : std_logic;
signal count_out_lsb : std_logic;
Signal mux_cnt_in_lsb : std_logic;
Signal carry_out_select_di: std_logic;
Signal carry_start : std_logic;
Signal carry_start_select : std_logic;
Signal by_2_carry_start : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
count_clock_en <= Count_Enable or Count_Load;
MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
mux_cnt_in_lsb <= count_out_lsb;
else
mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1);
End if;
End process MUX_THE_LSB_INPUT;
carry_start <= Count_Down xor Count_Enable;
by_2_carry_start <= Cnt_by_2 and Count_Down;
carry_start_select <= not(Cnt_by_2);
I_MUXCY_LSB_IN : MUXCY
port map (
DI => by_2_carry_start,
CI => carry_start,
S => carry_start_select,
O => carry_in_lsb);
I_COUNTER_BIT_LSB : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => mux_cnt_in_lsb,
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => carry_in_lsb,
Clock_Enable => count_clock_en,
Result => count_out_lsb,
Carry_Out => carry_out_lsb);
carry_out_select_di <= Count_Down xor Cnt_by_2;
I_MUXCY_LSB_OUT : MUXCY
port map (
DI => carry_out_select_di,
CI => carry_out_lsb,
S => carry_start_select,
O => alu_cy(C_COUNT_WIDTH-1));
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate
begin
MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
i_mux_Count_Out(i) <= iCount_Out(i);
else
i_mux_Count_Out(i) <= Load_In(i);
End if;
End process MUX_THE_INPUT;
Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => i_mux_Count_Out(i),
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => alu_cy(i+1),
Clock_Enable => count_clock_en,
Result => iCount_Out(i),
Carry_Out => alu_cy(i));
end generate I_ADDSUB_GEN;
Count_Out <= iCount_Out & count_out_lsb;
Carry_Out <= '0';
end architecture implementation;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/sim/zynq_1_proc_sys_reset_1_0.vhd | 4 | 5845 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY zynq_1_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zynq_1_proc_sys_reset_1_0;
ARCHITECTURE zynq_1_proc_sys_reset_1_0_arch OF zynq_1_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zynq_1_proc_sys_reset_1_0_arch;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/fifo_generator_v11_0/common/rd_pe_as.vhd | 19 | 25238 | `protect begin_protected
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`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/fifo_generator_v11_0_synth.vhd | 19 | 237901 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 174368)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_sys_reset_v5_0/hdl/src/vhdl/sequence.vhd | 30 | 22215 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence;
architecture imp of sequence is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pf_occ_counter_top.vhd | 15 | 12619 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/proc_common_v4_0/hdl/src/vhdl/pf_occ_counter_top.vhd | 15 | 12619 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd | 7 | 7208 | -------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/soft_reset.vhd | 15 | 13928 | -------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
| mit |
frankvanbever/MIPS_processor | testbenches/Control_tb.vhd | 1 | 3724 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:24:09 03/13/2013
-- Design Name:
-- Module Name: /home/steven/Documenten/Codes/pcarch/MIPSmodules/Control_tb.vhd
-- Project Name: MIPSmodules
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Control
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Control_tb IS
END Control_tb;
ARCHITECTURE behavior OF Control_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Control
PORT(
Instruction : IN std_logic_vector(31 downto 26);
Instruction_funct : IN std_logic_vector(5 downto 0);
RegDst : OUT std_logic;
ALUSrc : OUT std_logic;
MemtoReg : OUT std_logic;
RegWrite : OUT std_logic;
MemRead : OUT std_logic;
MemWrite : OUT std_logic;
Branch : OUT std_logic;
Branch_ne : OUT std_logic;
ALUop : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal Instruction : std_logic_vector(31 downto 26) := (others => '0');
signal Instruction_funct : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal RegDst : std_logic;
signal ALUSrc : std_logic;
signal MemtoReg : std_logic;
signal RegWrite : std_logic;
signal MemRead : std_logic;
signal MemWrite : std_logic;
signal Branch : std_logic;
signal Branch_ne : std_logic;
signal ALUop : std_logic_vector(1 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
signal clk: std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Control PORT MAP (
Instruction => Instruction,
Instruction_funct => Instruction_funct,
RegDst => RegDst,
ALUSrc => ALUSrc,
MemtoReg => MemtoReg,
RegWrite => RegWrite,
MemRead => MemRead,
MemWrite => MemWrite,
Branch => Branch,
Branch_ne => Branch_ne,
ALUop => ALUop
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait for clk_period*10;
Instruction<="000000"; --testfor R-format
wait for clk_period*10;
Instruction<="100011"; --testfor load word
wait for clk_period*10;
Instruction<="101011"; --testfor store word
wait for clk_period*10;
Instruction_funct<="000100";
Instruction<="000100"; --testfor branch equal
wait for clk_period*10;
Instruction_funct<="000101"; --testfor branch not equal
wait for clk_period*10;
Instruction<="111111"; --testfor error
wait;
end process;
END;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/proc_common_pkg.vhd | 15 | 18735 | -------------------------------------------------------------------------------
-- $Id: proc_common_pkg.vhd,v 1.1.4.46 2010/10/28 01:14:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-- DET 5/8/2009 v4_0 for EDK L.SP2
-- ~~~~~~
-- - Per CR520627
-- - Added synthesis translate_off/on constructs to the log2 function
-- around the assertion statement. This removes a repetative XST Warning
-- in SRP files about a non-constant assertion check.
-- ^^^^^^
-- FL0 20/27/2010
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end proc_common_pkg;
package body proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body proc_common_pkg;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/proc_common_v4_0/hdl/src/vhdl/proc_common_pkg.vhd | 15 | 18735 | -------------------------------------------------------------------------------
-- $Id: proc_common_pkg.vhd,v 1.1.4.46 2010/10/28 01:14:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-- DET 5/8/2009 v4_0 for EDK L.SP2
-- ~~~~~~
-- - Per CR520627
-- - Added synthesis translate_off/on constructs to the log2 function
-- around the assertion statement. This removes a repetative XST Warning
-- in SRP files about a non-constant assertion check.
-- ^^^^^^
-- FL0 20/27/2010
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end proc_common_pkg;
package body proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body proc_common_pkg;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/proc_common_v4_0/hdl/src/vhdl/ipif_steer128.vhd | 15 | 44922 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer128 - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer128.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer128.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
-- GAB 06-27-2005
-- ~~~~~~
-- Modified to support C_DWIDTH=128
-- Added second Decode_size input to reduce fanout for 128-bit cases
-- Renamed to ipif_steer128.vhd
-- ^^^^^^
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity ipif_steer128 is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64, 128
C_SMALLEST : integer := 32; -- 8, 16, 32, 64, 128
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size1 : in std_logic_vector(0 to 2);
Decode_size2 : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity ipif_steer128;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of ipif_steer128 is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
-- Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_128_8: if C_DWIDTH = 128 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 3);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-1);
case addr_bits is
when "0001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "0010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "1000" =>
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(8);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(64 to 71) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(72 to 79);
Wr_Data_Out(8 to 15) <= Wr_Data_In(72 to 79);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(9);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(72 to 79) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(10);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(80 to 87) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(88 to 95);
Wr_Data_Out(8 to 15) <= Wr_Data_In(88 to 95);
Wr_Data_Out(24 to 31) <= Wr_Data_In(88 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(11);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(88 to 95) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(12);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(96 to 103) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(104 to 111);
Wr_Data_Out(8 to 15) <= Wr_Data_In(104 to 111);
Wr_Data_Out(40 to 47) <= Wr_Data_In(104 to 111);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(13);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(104 to 111) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(14);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(112 to 119) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(120 to 127);
Wr_Data_Out(8 to 15) <= Wr_Data_In(120 to 127);
Wr_Data_Out(24 to 31) <= Wr_Data_In(120 to 127);
Wr_Data_Out(56 to 63) <= Wr_Data_In(120 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(15);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(120 to 127) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_8;
GEN_128_16: if C_DWIDTH = 128 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-2);
case addr_bits is
when "001" => --2
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "010" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "011" => --6
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "100" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "101" => --A
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "110" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "111" => --E
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_16;
GEN_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "01" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "10" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "11" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_32;
GEN_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4);
case addr_bits is
when '1' => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_64;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/axi_qspi_xip_if.vhd | 1 | 341829 | -------------------------------------------------------------------------------
-- $Id: axi_qspi_xip_if.vhd
-------------------------------------------------------------------------------
-- axi_qspi_xip_if.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_qspi_xip_if.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core
-- in XIP mode.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family.all;
use proc_common_v4_0.all;
use proc_common_v4_0.async_fifo_fg;-- 1/8/2013
use proc_common_v4_0.cdc_sync;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity axi_qspi_xip_if is
generic(
-- General Parameters
C_FAMILY : string := "virtex7";
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_SPI_MEM_ADDR_BITS : integer ; -- default is 24 bit, options are 24 or 32 bits
-------------------------
-- C_AXI4_CLK_PS : integer := 10000;--AXI clock period
-- C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_XIP_FIFO_DEPTH : integer := 64;-- Fixed value for XIP mode.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- Fixed 8 bit for XIP mode
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 2 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters
--*C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer ;-- range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_0100_0000", -- IP user0 base address
X"0000_0000_01FF_FFFF" -- IP user0 high address
);
C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
2,
1 -- User0 CE Number
)
);
port(
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
Rst_to_spi : in std_logic;
S_AXI4_ARESET : in std_logic;
-------------------------------
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR : in std_logic;
TO_XIPSR_trans_error : out std_logic;
--------------------------------
TO_XIPSR_mst_modf_err : out std_logic;
TO_XIPSR_axi_rx_full : out std_logic;
TO_XIPSR_axi_rx_empty : out std_logic;
XIPCR_1_CPOL : in std_logic;
XIPCR_0_CPHA : in std_logic;
-------------------------------
--*SPI port interface * --
-------------------------------
IO0_I : in std_logic; -- MOSI signal in standard SPI
IO0_O : out std_logic;
IO0_T : out std_logic;
-------------------------------
IO1_I : in std_logic; -- MISO signal in standard SPI
IO1_O : out std_logic;
IO1_T : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
---------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL : in std_logic;
-----
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
-----
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic
---------------------------------
);
end entity axi_qspi_xip_if;
--------------------------------------------------------------------------------
architecture imp of axi_qspi_xip_if is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant NEW_LOGIC : integer := 0; -- 3/29/2013
constant ACTIVE_LOW_RESET : std_logic := '0';
constant CMD_BITS_LENGTH : integer:= 8; -- 3/29/2013
-----
-- code coverage -- function assign_addr_bits (logic_info : integer) return integer is
-- code coverage -- variable addr_width_24 : integer:= 24;
-- code coverage -- variable addr_width_32 : integer:= 32;
-- code coverage -- begin
-- code coverage -- if logic_info = 0 then -- old logic for 24 bit addressing
-- code coverage -- return addr_width_24;
-- code coverage -- else
-- code coverage -- return addr_width_32;
-- code coverage -- end if;
-- code coverage -- end function assign_addr_bits;
signal nm_wr_en_CMD : std_logic_vector(7 downto 0);
signal nm_4byte_addr_en_CMD : std_logic_vector(7 downto 0);
type NM_WR_EN_STATE_TYPE is
(NM_WR_EN_IDLE, -- decode command can be combined here later
NM_WR_EN,
NM_WR_EN_DONE
);
signal nm_wr_en_cntrl_ps : NM_WR_EN_STATE_TYPE;
signal nm_wr_en_cntrl_ns : NM_WR_EN_STATE_TYPE;
signal wr_en_under_process : std_logic;
signal wr_en_under_process_d1 : std_logic;
signal load_wr_en, wr_en_done_reg : std_logic;
signal wr_en_done_d1, wr_en_done_d2 : std_logic;
signal wr_en_done : std_logic;
signal data_loaded, cmd_sent : std_logic;
type NM_32_BIT_WR_EN_STATE_TYPE is
(NM_32_BIT_IDLE, -- decode command can be combined here later
NM_32_BIT_EN,
NM_32_BIT_EN_DONE
);
signal nm_sm_4_byte_addr_ps : NM_32_BIT_WR_EN_STATE_TYPE;
signal nm_sm_4_byte_addr_ns : NM_32_BIT_WR_EN_STATE_TYPE;
signal four_byte_en_under_process : std_logic;
signal four_byte_addr_under_process_d1 : std_logic;
signal load_4_byte_addr_en, four_byte_en_done, four_byte_en_done_reg : std_logic;
-----
-- constant declaration
constant FAST_READ : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00001011"; -- 0B
constant FAST_READ_DUAL_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00111011"; -- 3B
constant FAST_READ_QUAD_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="10111011"; -- BB
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH : integer := clog2(C_XIP_FIFO_DEPTH);
constant XIP_MIN_SIZE : std_logic_vector(31 downto 0):= X"00ffffff";-- 24 bit address
--constant XIP_ADDR_BITS : integer := 24;
constant XIP_ADDR_BITS : integer := C_SPI_MEM_ADDR_BITS; -- assign_addr_bits(NEW_LOGIC);
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
constant ACTIVE_HIGH_RESET : std_logic := '1';
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
constant ALL_1 : std_logic_vector(0 to RX_FIFO_CNTR_WIDTH-1)
:= (others => '0');
signal updown_cnt_en_rx,down_cnt_en_rx : std_logic;
type AXI_IF_STATE_TYPE is
(
IDLE, -- decode command can be combined here later
RD_BURST
);
signal xip_sm_ps: AXI_IF_STATE_TYPE;
signal xip_sm_ns: AXI_IF_STATE_TYPE;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
HPM_DUMMY,
ADDR_SEND,
TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,
TEMP_DATA_SEND,
DATA_RECEIVE,
TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ns : STATE_TYPE;
signal qspi_cntrl_ps : STATE_TYPE;
type WB_STATE_TYPE is
(WB_IDLE, -- decode command can be combined here later
WB_WR_HPM,
WB_DONE
);
signal wb_cntrl_ns : WB_STATE_TYPE;
signal wb_cntrl_ps : WB_STATE_TYPE;
signal valid_decode : std_logic;
signal s_axi_arready_cmb : std_logic;
signal temp_i : std_logic;
signal SS_frm_axi : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_int : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_reg : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst : std_logic; --_vector(1 downto 0);
signal axi_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal size_length : std_logic_vector(1 downto 0);
signal S_AXI4_RID_reg : std_logic_vector(C_S_AXI4_ID_WIDTH-1 downto 0);
signal XIP_ADDR : std_logic_vector(XIP_ADDR_BITS-1 downto 0);
signal one_byte_transfer : std_logic;
signal two_byte_transfer : std_logic;
signal four_byte_transfer: std_logic;
signal dtr_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal write_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal dtr_cntr_empty : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal last_data : std_logic;
signal rd_error_int : std_logic;
signal Data_From_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal S_AXI4_RRESP_i : std_logic_vector(1 downto 0);
signal S_AXI4_RDATA_i : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
-- signal s_axi_rvalid_i : std_logic;
signal s_axi_rvalid_cmb : std_logic;
signal xip_pr_state_idle : std_logic;
signal pr_state_idle : std_logic;
signal rready_i : std_logic;
signal wrap_around_to_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal Rx_FIFO_Empty : std_logic;
signal IO0_T_cntrl_axi : std_logic;
signal IO1_T_cntrl_axi : std_logic;
signal IO2_T_cntrl_axi : std_logic;
signal IO3_T_cntrl_axi : std_logic;
signal SCK_T_cntrl_axi : std_logic;
signal load_axi_data_frm_axi : std_logic;
--signal Transmit_addr_int : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal Rx_FIFO_rd_ack : std_logic;
signal Data_To_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal store_date_in_drr_fifo : std_logic;
--signal Rx_FIFO_Empty : std_logic;
signal Rx_FIFO_almost_Full : std_logic;
signal Rx_FIFO_almost_Empty : std_logic;
--signal pr_state_idle : std_logic;
signal spiXfer_done_frm_spi_clk: std_logic;
signal mst_modf_err_frm_spi_clk: std_logic;
signal wrap_around_frm_spi_clk : std_logic;
signal one_byte_xfer_frm_axi_clk : std_logic;
signal two_byte_xfer_frm_axi_clk : std_logic;
signal four_byte_xfer_frm_axi_clk : std_logic;
signal load_axi_data_frm_axi_clk : std_logic;
--signal Transmit_Addr_frm_axi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_frm_axi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0);-- 3/30/2013
signal CPOL_frm_axi_clk : std_logic;
signal CPHA_frm_axi_clk : std_logic;
signal SS_frm_axi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_frm_axi_clk : std_logic; -- _vector(1 downto 0);
signal type_of_burst_frm_axi : std_logic; -- _vector(1 downto 0);
signal axi_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal load_axi_data_to_spi_clk : std_logic;
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_to_spi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal last_7_addr_bits : std_logic_vector(7 downto 0);
signal CPOL_to_spi_clk : std_logic;
signal CPHA_to_spi_clk : std_logic;
signal SS_to_spi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_to_spi : std_logic;
signal type_of_burst_to_spi_clk : std_logic;
signal axi_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal wrap_around_to_axi_clk : std_logic;
signal spi_addr : std_logic_vector(31 downto 0);
signal spi_addr_i : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap_1 : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0);
signal load_wrap_addr : std_logic;
signal wrap_two : std_logic;
signal wrap_four : std_logic;
signal wrap_eight : std_logic;
signal wrap_sixteen : std_logic;
signal SPIXfer_done_int : std_logic;
signal size_length_cntr : std_logic_vector(1 downto 0);
signal size_length_cntr_fixed : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal cmd_addr_sent : std_logic;
signal SR_5_Tx_Empty, SR_5_Tx_Empty_d1, SR_5_Tx_Empty_d2 : std_logic;
signal wrap_around : std_logic;
signal rst_wrap_around : std_logic;
--signal pr_state_idle : std_logic;
signal one_byte_xfer_to_spi_clk : std_logic;
signal two_byte_xfer_to_spi_clk : std_logic;
signal four_byte_xfer_to_spi_clk : std_logic;
--signal store_date_in_drr_fifo : std_logic;
signal Data_To_Rx_FIFO_int : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal receive_Data_int : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal Data_To_Rx_FIFO : std_logic_vector(7 downto 0);
--signal load_axi_data_to_spi_clk : std_logic;
signal Tx_Data_d1 : std_logic_vector(31 downto 0);
signal Tx_Data_d2 : std_logic_vector(39 downto 0);
signal internal_count : std_logic_vector(3 downto 0);
signal SPI_cmd : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal Transmit_Data : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Data_Dir : std_logic;
signal Data_Mode_1 : std_logic;
signal Data_Mode_0 : std_logic;
signal Data_Phase : std_logic;
signal Quad_Phase : std_logic;
signal Addr_Mode_1 : std_logic;
signal Addr_Mode_0 : std_logic;
signal Addr_Bit : std_logic;
signal Addr_Phase : std_logic;
signal CMD_Mode_1 : std_logic;
signal CMD_Mode_0 : std_logic;
--signal cmd_addr_cntr : std_logic_vector(2 downto 0);
--signal cmd_addr_sent : std_logic;
signal transfer_start : std_logic;
signal last_bt_one_data : std_logic;
--signal SPIXfer_done_int : std_logic;
signal actual_SPIXfer_done_int : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
--signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
--signal SPIXfer_done_int : std_logic;
signal mode_1 : std_logic;
signal mode_0 : std_logic;
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
--signal receive_Data_int : std_logic_vector(7 downto 0);
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal sck_o_int : std_logic;
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal Shift_Reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal pr_state_cmd_ph : std_logic;
--signal qspi_cntrl_ps : std_logic;
signal stop_clock : std_logic;
signal stop_clock_reg : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
--signal pr_state_idle : std_logic;
--signal pr_state_cmd_ph : std_logic;
--signal SPIXfer_done_int_pulse : std_logic;
signal no_slave_selected : std_logic;
--signal rst_wrap_around : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal addr_cnt1 : std_logic_vector(1 downto 0);
signal pr_state_addr_ph : std_logic;
signal SS_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal IO0_T_cntrl_spi : std_logic;
signal MODF_strobe_int : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal MODF_strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal sck_o_in : std_logic;
--signal SCK_O_reg : std_logic;
signal slave_mode : std_logic;
--signal pr_state_non_idle : std_logic;
signal mst_modf_err_to_axi_clk : std_logic;
signal mst_modf_err_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi_clk : std_logic;
signal Rx_FIFO_Full : std_logic;
signal one_byte_xfer : std_logic;
signal two_byte_xfer : std_logic;
signal four_byte_xfer : std_logic;
signal XIP_trans_error : std_logic;
signal load_cmd : std_logic;
signal load_cmd_to_spi_clk : std_logic;
--signal load_axi_data_frm_axi_clk : std_logic;
signal load_cmd_frm_axi_clk : std_logic;
signal axi_len_two : std_logic;
signal axi_len_four : std_logic;
signal axi_len_eight : std_logic;
signal axi_len_sixteen : std_logic;
signal reset_inversion : std_logic;
signal new_tr : std_logic;
signal SR_5_Tx_Empty_int : std_logic;
signal only_last_count : std_logic;
signal rx_fifo_cntr_rst, rx_fifo_not_empty : std_logic;
signal store_date_in_drr_fifo_d1 : std_logic;
signal store_date_in_drr_fifo_d2 : std_logic;
signal store_date_in_drr_fifo_d3 : std_logic;
signal xip_ns_state_idle : std_logic;
signal wrap_around_d1 : std_logic;
signal wrap_ack : std_logic;
signal wrap_ack_1 : std_logic;
signal wrap_around_d2 : std_logic;
signal wrap_around_d3 : std_logic;
signal start_after_wrap : std_logic;
signal store_last_b4_wrap : std_logic;
signal wrp_addr_len_16_siz_32 : std_logic;
signal wrp_addr_len_8_siz_32 : std_logic;
signal wrp_addr_len_4_siz_32 : std_logic;
signal wrp_addr_len_2_siz_32 : std_logic;
signal wrp_addr_len_16_siz_16 : std_logic;
signal wrp_addr_len_8_siz_16 : std_logic;
signal wrp_addr_len_4_siz_16 : std_logic;
signal wrp_addr_len_2_siz_16, start_after_wrap_d1 : std_logic;
signal SS_O_1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal WB_wr_en_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_DATA : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_hpm_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal wb_wr_en_done : std_logic;
signal wb_wr_sr_done : std_logic;
signal wb_wr_sr_data_done : std_logic;
signal wb_wr_hpm_done : std_logic;
signal load_wr_en_cmd : std_logic;
signal load_wr_sr_cmd : std_logic;
signal load_wr_sr_d0 : std_logic;
signal load_wr_sr_d1 : std_logic;
signal load_rd_sr : std_logic;
signal load_wr_hpm : std_logic;
signal wb_hpm_done : std_logic;
signal wb_hpm_done_reg : std_logic;
signal dis_sr_5_empty_reg : std_logic;
signal dis_sr_5_empty : std_logic;
signal wb_hpm_done_frm_spi,wb_hpm_done_frm_spi_clk,wb_hpm_done_to_axi : std_logic;
signal hpm_under_process : std_logic;
signal hpm_under_process_d1 : std_logic;
signal s_axi_rlast_cmb : std_logic;
signal store_date_in_drr_fifo_en : std_logic;
signal XIP_trans_error_cmb, XIP_trans_error_d1, XIP_trans_error_d2, XIP_trans_error_d3 : std_logic;
signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
signal arready_d1, arready_d2, arready_d3 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
signal axi4_tr_over_d3 : std_logic;
signal last_data_acked_int_2 : std_logic;
signal XIP_trans_error_int_2 : std_logic;
signal s_axi_arready_int_2 : std_logic;
-- signal XIP_trans_error_cmb : std_logic;
-- signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
-- signal arready_d1, arready_d2, arready_d3 : std_logic;
-- signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
-- signal axi4_tr_over_d3 : std_logic;
-- signal last_data_acked_int_2 : std_logic;
-- signal XIP_trans_error_int_2 : std_logic;
-- signal s_axi_arready_int_2 : std_logic;
signal Rx_FIFO_Empty_d1, Rx_FIFO_Empty_d2 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_4 : std_logic;
--signal mst_modf_err_to_axi4clk: std_logic;
signal xip_done : std_logic;
signal en_xip : std_logic;
signal new_tr_at_axi4 : std_logic;
signal axi4_tr_over : std_logic;
--attribute ASYNC_REG : string;
--attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
--attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
--attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
constant MTBF_STAGES_AXI2AXILITE : integer range 0 to 6 := 4 ;
-----
begin
-----
S_AXI4_WREADY <= '0';
S_AXI4_BID <= (others => '0');
S_AXI4_BRESP <= (others => '0');
S_AXI4_BVALID <= '0';
S_AXI4_AWREADY<= '0';
valid_decode <= S_AXI4_ARVALID and xip_pr_state_idle;
reset_inversion <= not S_AXI4_ARESET;
-- address decoder and CS generation in AXI interface
I_DECODER : entity axi_quad_spi_v3_1.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => XIP_ADDR_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => XIP_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK, -- in std_logic;
Bus_rst => reset_inversion, -- in std_logic;
Address_In_Erly => S_AXI4_ARADDR(XIP_ADDR_BITS-1 downto 0), -- in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly => s_axi_arready_cmb, -- in std_logic;
Bus_RNW => valid_decode, -- in std_logic;
Bus_RNW_Erly => valid_decode, -- in std_logic;
CS_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
Clear_CS_CE_Reg => temp_i, -- in std_logic;
RW_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
CS_for_gaps => open, -- out std_logic;
-- Decode output signals
CS_Out => SS_frm_axi,
RdCE_Out => open,
WrCE_Out => open
);
-------------------------------------------------
STORE_AXI_ARBURST_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- S_AXI4_ARESET is already inverted and made active high
type_of_burst <= '0';-- "01"; -- default is INCR burst
elsif(s_axi_arready_cmb = '1')then
type_of_burst <= S_AXI4_ARBURST(1) ;
end if;
end if;
end process STORE_AXI_ARBURST_P;
-----------------------
S_AXI4_ARREADY_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_ARREADY <= '0';
else
S_AXI4_ARREADY <= s_axi_arready_cmb;
end if;
end if;
end process S_AXI4_ARREADY_P;
-- S_AXI4_ARREADY <= s_axi_arready_cmb;
STORE_AXI_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
axi_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
axi_length <= S_AXI4_ARLEN;
end if;
end if;
end process STORE_AXI_LENGTH_P;
---------------------------------------------------
STORE_AXI_SIZE_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
size_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
size_length <= S_AXI4_ARSIZE(1 downto 0);
end if;
end if;
end process STORE_AXI_SIZE_P;
-------------------------------------------------------------------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RID_reg <= (others=> '0');
elsif(s_axi_arready_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_RID_reg;
-----------------------------
OLD_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(23 downto 0);-- support for 24 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate OLD_LOGIC_GEN;
---------------------------
NEW_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- support for 24 or 32 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate NEW_LOGIC_GEN;
---------------------------
------------------------------------------------------------------------------
ONE_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
one_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
one_byte_xfer <= not(or_reduce(S_AXI4_ARSIZE(1 downto 0)));
end if;
end if;
end process ONE_BYTE_XFER_P;
TWO_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
two_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
two_byte_xfer <= S_AXI4_ARSIZE(0);
end if;
end if;
end process TWO_BYTE_XFER_P;
FOUR_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
four_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
four_byte_xfer <= S_AXI4_ARSIZE(1);
end if;
end if;
end process FOUR_BYTE_XFER_P;
---------------------------------------------------------------------------------
STORE_DTR_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
dtr_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
dtr_length <= S_AXI4_ARLEN;-- + "00000001";
-- elsif(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then
elsif(Rx_FIFO_rd_ack = '1') then
dtr_length <= dtr_length - '1';
end if;
end if;
end process STORE_DTR_LENGTH_P;
-----------------------------------------------------
STORE_WRITE_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- if(xip_sm_ps = IDLE)then
write_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
write_length <= S_AXI4_ARLEN + "00000001";
elsif(spiXfer_done_to_axi_1 = '1')then
write_length <= write_length - '1';
end if;
end if;
end process STORE_WRITE_LENGTH_P;
-----------------------------------------------------
--dtr_cntr_empty <= or_Reduce(dtr_length);
-----------------------------------------------------
last_bt_one_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 1))) and
dtr_length(0) and
S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 0)));
RX_FIFO_FULL_CNTR_I : entity proc_common_v4_0.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => S_AXI4_ACLK, -- in
Rst => S_AXI4_ARESET, -- '0', -- in
-- coverage off
Load_In => ALL_1, -- in
-- coverage on
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => s_axi_arready_cmb,-- in
----------------
Count_Down => down_cnt_en_rx, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en_rx <= s_axi_arready_cmb or
spiXfer_done_to_axi_1 or
(down_cnt_en_rx); -- this is to make the counter enable for decreasing.
down_cnt_en_rx <= S_AXI4_RREADY and s_axi_rvalid_i;
only_last_count <= not(or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0))) and
last_data_cmb;
rx_fifo_not_empty <= or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0));
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
last_data_acked <= '0';
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then -- AXI Ready and Rlast active
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then-- AXI not Ready and Rlast active, then hold the RLAST signal
last_data_acked <= '1';
else
last_data_acked <=(last_data_cmb and
Rx_FIFO_rd_ack);
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= last_data_acked;
--------------------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RRESP_i <= (others => '0');
S_AXI4_RDATA_i <= (others => '0');
else-- if(S_AXI4_RREADY = '1' )then -- and (Rx_FIFO_Empty = '0')then
S_AXI4_RRESP_i <= --(rd_error_int or mst_modf_err_to_axi_clk) & '0';
(mst_modf_err_to_axi4_clk) & '0';
S_AXI4_RDATA_i <= Data_From_Rx_FIFO;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
--------------------------------
S_AXI4_RRESP <= S_AXI4_RRESP_i;
S_AXI4_RDATA <= S_AXI4_RDATA_i;
-------------------------------
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
s_axi_rvalid_i <= '0';
elsif(S_AXI4_RREADY = '1') then -- and (s_axi_rvalid_i = '1') then -- AXI Ready and Rlast active
s_axi_rvalid_i <= Rx_FIFO_rd_ack; -- '0';
elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
s_axi_rvalid_i <= s_axi_rvalid_i;
else
s_axi_rvalid_i <= Rx_FIFO_rd_ack;
end if;
end if;
end process S_AXI_RVALID_I_P;
-----------------------------
S_AXI4_RVALID <= s_axi_rvalid_i;
-- -----------------------------
xip_pr_state_idle <= '1' when xip_sm_ps = IDLE else '0';
xip_ns_state_idle <= '1' when xip_sm_ns = IDLE else '0';
rready_i <= S_AXI4_RREADY and not last_data_cmb;
------------------------------------------------------------------------------
XIP_trans_error_cmb <= not(or_reduce(S_AXI4_ARBURST)) and (S_AXI4_ARVALID);
-- XIP_TR_ERROR_PULSE_STRETCH_1: single pulse for AXI4 transaction error
LOGIC_GENERATION_FDR : if (LOGIC_CHANGE = 0) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
begin
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
-------------------------------------
XIP_TRANS_ERROR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d1,
C => S_AXI_ACLK,
D => XIP_trans_error_int_2,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d2,
C => S_AXI_ACLK,
D => XIP_trans_error_d1,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_2: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d3,
C => S_AXI_ACLK,
D => XIP_trans_error_d2,
R => S_AXI_ARESETN
);
XIP_trans_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
------------------------------------------------------------------------------
--mst_modf_err_to_axi <= mst_modf_err_d2;
-- TO XIP Status Register
-- LAST_DATA_PULSE_STRETCH_1: single pulse for AXI4 transaction completion
LAST_DATA_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
-------------------------------------
AXI4_TR_OVER_AXI42AXI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d1,
C => S_AXI_ACLK,
D => last_data_acked_int_2,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d2,
C => S_AXI_ACLK,
D => axi4_tr_over_d1,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d3,
C => S_AXI_ACLK,
D => axi4_tr_over_d2,
R => S_AXI_ARESETN
);
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
-------------------------------------------------------------
-- ARREADY_PULSE_STRETCH_1: single pulse for AXI4 transaction acceptance
ARREADY_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
-------------------------------------
ARREADY_PULSE_AXI42AXI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d1,
C => S_AXI_ACLK,
D => s_axi_arready_int_2,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_2: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d2,
C => S_AXI_ACLK,
D => arready_d1,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => arready_d3,
C => S_AXI_ACLK,
D => arready_d2,
R => S_AXI_ARESETN
);
new_tr_at_axi4 <= arready_d2 xor arready_d3;
-------------------------------------
------------------------------------------------------------------------------
-- CPHA_CPOL_ERR_AXI2AXI4_CDC: CDC flop at cross clock boundary
CPHA_CPOL_ERR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d1,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR,
R => S_AXI4_ARESET
);
CPHA_CPOL_ERR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d2,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR_d1,
R => S_AXI4_ARESET
);
XIPSR_CPHA_CPOL_ERR_4 <= XIPSR_CPHA_CPOL_ERR_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (LOGIC_CHANGE = 1) generate
--=================================================================================
XIP_TR_ERROR_PULSE_STRETCH_1_P: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1_P;
XIP_TRANS_ERROR_AXI2AXI4: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIP_trans_error_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => XIP_trans_error_d2
);
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
XIP_trans_error_d3 <= XIP_trans_error_d2 ;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
XIP_trans_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
--=================================================================================
LAST_DATA_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
--axi4_tr_over_d1 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
--axi4_tr_over_d1 <= last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1_CDC;
AXI4_TR_OVER_AXI42AXI: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => last_data_acked_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => axi4_tr_over_d2
);
LAST_DATA_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
axi4_tr_over_d3 <= axi4_tr_over_d2 ;
-- end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
--=================================================================================
ARREADY_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '1';
--arready_d1 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
--arready_d1 <= s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1_CDC;
ARREADY_PULSE_AXI42AXI: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => s_axi_arready_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => arready_d2
);
ARREADY_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
arready_d3 <= arready_d2;
-- end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
new_tr_at_axi4 <= arready_d2 xor arready_d3;
--==================================================================================
CPHA_CPOL_ERR_AXI2AXI4: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIPSR_CPHA_CPOL_ERR ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => XIPSR_CPHA_CPOL_ERR_4
);
--==================================================================================
end generate LOGIC_GENERATION_CDC;
XIPSR_RX_EMPTY_P: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1')then
if(S_AXI_ARESETN = ACTIVE_HIGH_RESET) then
TO_XIPSR_axi_rx_empty <= '1';
elsif(axi4_tr_over = '1')then
TO_XIPSR_axi_rx_empty <= '1';
elsif(new_tr_at_axi4 = '1')then
TO_XIPSR_axi_rx_empty <= '0';
end if;
end if;
end process XIPSR_RX_EMPTY_P;
-------------------------------------
TO_XIPSR_trans_error <= XIP_trans_error;
TO_XIPSR_mst_modf_err <= mst_modf_err_to_axi_clk;
TO_XIPSR_axi_rx_full <= Rx_FIFO_Full_to_axi_clk;
-- XIP_PS_TO_NS_PROCESS: stores the next state memory
XIP_PS_TO_NS_PROCESS: process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
xip_sm_ps <= IDLE;
else
xip_sm_ps <= xip_sm_ns;
end if;
end if;
end process XIP_PS_TO_NS_PROCESS;
-----------------------------
-- XIP_SM_P: below state machine is AXI interface state machine and controls the
-- acceptance of new transaction as well as monitors data transaction
XIP_SM_P:process(
xip_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_RREADY ,
S_AXI4_ARBURST ,
XIP_trans_error ,
mst_modf_err_to_axi4_clk,
Rx_FIFO_Full_to_Axi4_clk,
XIPSR_CPHA_CPOL_ERR_4 ,
Rx_FIFO_Empty ,
wb_hpm_done_to_axi ,
spiXfer_done_to_axi_1 ,
last_data_cmb ,
Rx_FIFO_rd_ack ,--,
last_data_acked
--wrap_around_to_axi_clk ,
--last_bt_one_data_cmb ,
--Rx_FIFO_Empty ,
--only_last_count ,
--rx_fifo_not_empty ,
--rx_fifo_count ,
)is
begin
-----
s_axi_arready_cmb <= '0';
load_axi_data_frm_axi <= '0';
load_cmd <= '0';
s_axi_rlast_cmb <= '0';
s_axi_rvalid_cmb <= '0';
last_data <= '0';
--IO0_T_cntrl_axi <= '1';
--IO1_T_cntrl_axi <= '1';
--IO2_T_cntrl_axi <= '1';
--IO3_T_cntrl_axi <= '1';
--SCK_T_cntrl_axi <= '1';
temp_i <= '0';
case xip_sm_ps is
when IDLE => --if(XIP_cmd_error = '0') then
if(S_AXI4_ARVALID = '1') and
(XIP_trans_error = '0') and
(mst_modf_err_to_axi4_clk = '0') and
(Rx_FIFO_Full_to_axi4_clk = '0') and
(XIPSR_CPHA_CPOL_ERR_4 = '0') and
(Rx_FIFO_Empty = '1') and
(wb_hpm_done_to_axi = '1')
then
s_axi_arready_cmb <= S_AXI4_ARVALID;
load_axi_data_frm_axi <= S_AXI4_ARVALID;
load_cmd <= S_AXI4_ARVALID;
xip_sm_ns <= RD_BURST;
else
xip_sm_ns <= IDLE;
end if;
when RD_BURST =>
--if(last_data_cmb = '1') and (Rx_FIFO_rd_ack = '1') then--(rx_fifo_count = "000001") then
if (last_data_acked = '1') then
if(S_AXI4_RREADY = '1') then
temp_i <= '1';
xip_sm_ns <= IDLE;
else
xip_sm_ns <= RD_BURST;
end if;
else
xip_sm_ns <= RD_BURST;
end if;
-- coverage off
when others => xip_sm_ns <= IDLE;
-- coverage on
end case;
end process XIP_SM_P;
----------------------
-- AXI_24_BIT_ADDR_STORE_GEN: stores 24 bit axi address
AXI_24_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(23 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_24_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- AXI_32_BIT_ADDR_STORE_GEN: stores 32 bit axi address
AXI_32_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013 updated for 32 or 24 bit addressing modes
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_32_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- 24/32-bit --
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
-------------------------------------------------------------------------------
XIP_RECEIVE_FIFO_II: entity proc_common_v4_0.async_fifo_fg
generic map(
-- 3/30/2013 starts
--C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
--C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- 3/30/2013 ends
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer := 16;
C_FIFO_DEPTH => C_XIP_FIFO_DEPTH , -- : integer := 256;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT, -- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT, -- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => S_AXI4_RREADY , -- : in std_logic := '0';
Rd_clk => S_AXI4_ACLK , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => store_date_in_drr_fifo_en , --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => open, -- Rx_FIFO_wr_ack_open, -- : out std_logic;
------
Full => Rx_FIFO_Full, --Rx_FIFO_Full, -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => S_AXI4_ARESET ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => rd_error_int , -- : out std_logic;
Wr_err => open -- : out std_logic
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- from SPI clock
spiXfer_done_frm_spi_clk <= store_date_in_drr_fifo_en; --spiXfer_done_int;
mst_modf_err_frm_spi_clk <= not SPISEL_sync; -- 9/7/2013 -- MODF_strobe; -- 9/7/2013
--wrap_around_frm_spi_clk <= wrap_around;
wb_hpm_done_frm_spi_clk <= wb_hpm_done;
-- from AXI clocks
--size_length_frm_axi_clk <= size_length;
one_byte_xfer_frm_axi_clk <= one_byte_xfer;
two_byte_xfer_frm_axi_clk <= two_byte_xfer;
four_byte_xfer_frm_axi_clk <= four_byte_xfer;
load_axi_data_frm_axi_clk <= load_axi_data_frm_Axi;-- 1 bit
Transmit_Addr_frm_axi_clk <= Transmit_addr_int; -- 24 bit
load_cmd_frm_axi_clk <= load_cmd;
CPOL_frm_axi_clk <= XIPCR_1_CPOL; -- 1 bit
CPHA_frm_axi_clk <= XIPCR_0_CPHA; -- 1 bit
SS_frm_axi_clk <= SS_frm_axi; -- _reg; -- based upon C_NUM_SS_BITS
type_of_burst_frm_axi_clk <= type_of_burst; -- 1 bit signal take MSB only to differentiate WRAP and INCR burst
axi_length_frm_axi_clk <= axi_length; -- 8 bit used for WRAP transfer
dtr_length_frm_axi_clk <= dtr_length; -- 8 bit used for internbal counter
XIP_CLK_DOMAIN_SIGNALS:entity axi_quad_spi_v3_1.xip_cross_clk_sync
generic map(
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEM_ADDR_BITS => XIP_ADDR_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,
S_AXI4_ACLK => S_AXI4_ACLK ,
S_AXI4_ARESET => S_AXI4_ARESET ,
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
Rst_from_axi_cdc_to_spi => Rst_to_spi ,
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk ,
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1 ,
----------------------------
mst_modf_err_cdc_from_spi => mst_modf_err_frm_spi_clk ,
mst_modf_err_cdc_to_axi => mst_modf_err_to_axi_clk ,
mst_modf_err_cdc_to_axi4 => mst_modf_err_to_axi4_clk ,
----------------------------
one_byte_xfer_cdc_from_axi => one_byte_xfer_frm_axi_clk ,
one_byte_xfer_cdc_to_spi => one_byte_xfer_to_spi_clk ,
----------------------------
two_byte_xfer_cdc_from_axi => two_byte_xfer_frm_axi_clk ,
two_byte_xfer_cdc_to_spi => two_byte_xfer_to_spi_clk ,
----------------------------
four_byte_xfer_cdc_from_axi => four_byte_xfer_frm_axi_clk ,
four_byte_xfer_cdc_to_spi => four_byte_xfer_to_spi_clk ,
----------------------------
load_axi_data_cdc_from_axi => load_axi_data_frm_axi_clk ,
load_axi_data_cdc_to_spi => load_axi_data_to_spi_clk ,
----------------------------
Transmit_Addr_cdc_from_axi => Transmit_Addr_frm_axi_clk ,
Transmit_Addr_cdc_to_spi => Transmit_Addr_to_spi_clk ,
----------------------------
load_cmd_cdc_from_axi => load_cmd_frm_axi_clk ,
load_cmd_cdc_to_spi => load_cmd_to_spi_clk ,
----------------------------
CPOL_cdc_from_axi => CPOL_frm_axi_clk ,
CPOL_cdc_to_spi => CPOL_to_spi_clk ,
----------------------------
CPHA_cdc_from_axi => CPHA_frm_axi_clk ,
CPHA_cdc_to_spi => CPHA_to_spi_clk ,
------------------------------
SS_cdc_from_axi => SS_frm_axi_clk ,
SS_cdc_to_spi => SS_to_spi_clk ,
----------------------------
type_of_burst_cdc_from_axi => type_of_burst_frm_axi_clk ,
type_of_burst_cdc_to_spi => type_of_burst_to_spi_clk ,
----------------------------
axi_length_cdc_from_axi => axi_length_frm_axi_clk ,
axi_length_cdc_to_spi => axi_length_to_spi_clk ,
----------------------------
dtr_length_cdc_from_axi => dtr_length_frm_axi_clk ,
dtr_length_cdc_to_spi => dtr_length_to_spi_clk , --,
----------------------------
Rx_FIFO_Full_cdc_from_spi => Rx_FIFO_Full ,
Rx_FIFO_Full_cdc_to_axi => Rx_FIFO_Full_to_axi_clk ,
Rx_FIFO_Full_cdc_to_axi4 => Rx_FIFO_Full_to_axi4_clk ,
----------------------------
wb_hpm_done_cdc_from_spi => wb_hpm_done_frm_spi_clk ,
wb_hpm_done_cdc_to_axi => wb_hpm_done_to_axi
);
-------------------------------------------------------------------------------
-- STORE_NEW_TR_P: This process is used in INCR and WRAP to check for any new transaction from AXI
STORE_NEW_TR_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1') -- needed for enabling 32 bit addressing mode
or (load_wr_en = '1') -- needed for write enabling before enabling the 32 bit addressing mode
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_32_BIT_ADDR_GEN;
---------------------------------------------
STORE_NEW_TR_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1')
-- or (load_wr_en = '1')
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_24_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- STORE_INITAL_ADDR_P: The address frm AXI should be stored in the SPI environment
-- as the address generation logic will work in this domain.
STORE_24_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= "00000000" & Transmit_Addr_to_spi_clk;-- (31 downto 8);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= "00000000" & spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
-------------------------------------
end generate STORE_24_BIT_SPI_ADDR_GEN;
-----------------------------------------
STORE_32_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013
begin
-----
----------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= Transmit_Addr_to_spi_clk;-- (31 downto 0);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
----------------------------------
end generate STORE_32_BIT_SPI_ADDR_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- below signals will store the length of AXI transaction in the SPI domain
axi_len_two <= not(or_Reduce(axi_length_to_spi_clk(3 downto 1))) and
axi_length_to_spi_clk(0);
axi_len_four <= not(or_Reduce(axi_length_to_spi_clk(3 downto 2))) and
and_reduce(axi_length_to_spi_clk(1 downto 0));
axi_len_eight <= not(axi_length_to_spi_clk(3)) and
and_Reduce(axi_length_to_spi_clk(2 downto 0));
axi_len_sixteen <= and_reduce(axi_length_to_spi_clk(3 downto 0));
-------------------------------------------------------------------------------
-- below signals store the WRAP information in SPI domain
wrap_two <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_two = '1')
else
'0';
wrap_four <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_four = '1')
else
'0';
wrap_eight <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_eight = '1')
else
'0';
wrap_sixteen <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_sixteen = '1')
else
'0';
-------------------------------------------------------------------------------
-- SPI_ADDRESS_REG: This process stores the initial address coming from the AXI in
-- two registers. one register will store this address till the
-- transaction ends, while other will be updated based upon type of
-- transaction as well as at the end of each SPI transfer. this is
-- used for internal use only.
SPI_24_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(23 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(23 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(23 downto 0) <= spi_addr_int(23 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 1) <= spi_addr_i(23 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 6) <= spi_addr_i(23 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(23 downto 0) <= spi_addr_i(23 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
----------------------------------
end generate SPI_24_BIT_ADDRESS_REG_GEN;
----------------------------------------
SPI_32_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(31 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(31 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(31 downto 0) <= spi_addr_int(31 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 1) <= spi_addr_i(31 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 6) <= spi_addr_i(31 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(31 downto 0) <= spi_addr_i(31 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
end generate SPI_32_BIT_ADDRESS_REG_GEN;
----------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
SPI_24_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(23 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 1) <= spi_addr_wrap(23 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 6) <= spi_addr_wrap(23 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
end generate SPI_24_WRAP_ADDR_REG_GEN;
--------------------------------------
SPI_32_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(31 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 1) <= spi_addr_wrap(31 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 6) <= spi_addr_wrap(31 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
----------------------------------
end generate SPI_32_WRAP_ADDR_REG_GEN;
--------------------------------------
-------------------------------------------------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
LOAD_SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap_1 <= (others => '0');
else
if (wrap_around = '1') then
-- below is address generation for the WRAP mode
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + '1';
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "10";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "00010";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "100";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "000100";
else
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap_1 <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process LOAD_SPI_WRAP_ADDR_REG;
-------------------------------------------------------------------------------
-- WRAP_AROUND_GEN_P : WRAP boundary detection logic
WRAP_AROUND_GEN_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if( (Rst_to_spi = '1')
or(rst_wrap_around = '1')
) then
wrap_around <= '0';
elsif(type_of_burst_to_spi_clk = '1')then
case size_length_cntr_fixed is
when "00" => -- byte transfer
if(wrap_two = '1') and
(spi_addr_wrap(1) = '1') and
(store_date_in_drr_fifo = '1')then -- then
wrap_around <= --spi_addr_wrap(1) and
not SR_5_Tx_Empty;
elsif(wrap_four = '1') and
(spi_addr_wrap(1 downto 0) = "11") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 2 address bits
wrap_around <= --and_reduce(spi_addr_wrap(1 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_eight = '1') and
(spi_addr_wrap(2 downto 0) = "111") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 3 address bits
wrap_around <= --and_reduce(spi_addr_wrap(2 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_sixteen = '1') and
(spi_addr_wrap(3 downto 0) = "1111") and
(store_date_in_drr_fifo = '1')then -- the byte address increment will take 4 address bits for 16's wrap
wrap_around <= --and_reduce(spi_addr_wrap(3 downto 0)) and
not SR_5_Tx_Empty;
else
wrap_around <= '0';
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(1 downto 0) = "10") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_16;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(2 downto 0) = "110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_16;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(3 downto 0) = "1110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_16;
elsif(wrap_sixteen = '1') then -- and (spi_addr_wrap(4 downto 0) = "11110") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_16;
else
wrap_around <= '0';
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(2 downto 0) = "100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_32;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(3 downto 0) = "1100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_32;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(4 downto 0) = "11100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_32;
elsif(wrap_sixteen = '1') then --and (spi_addr_wrap(5 downto 0) = "111100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_32;
else
wrap_around <= '0';
end if;
-- coverage off
when others => wrap_around <= wrap_around;
-- coverage on
end case;
end if;
end if;
end process WRAP_AROUND_GEN_P;
-------------------------------------------------------------------------------
load_wrap_addr <= wrap_around;
wrp_addr_len_16_siz_32 <= '1' when (spi_addr_wrap(5 downto 0) = "111100") else '0';
wrp_addr_len_8_siz_32 <= '1' when (spi_addr_wrap(4 downto 0) = "11100") else '0';
wrp_addr_len_4_siz_32 <= '1' when (spi_addr_wrap(3 downto 0) = "1100") else '0';
wrp_addr_len_2_siz_32 <= '1' when (spi_addr_wrap(2 downto 0) = "100") else '0';
-----------------------------------------------------------------------------------
wrp_addr_len_16_siz_16 <= '1' when (spi_addr_wrap(4 downto 0) = "11110") else '0';
wrp_addr_len_8_siz_16 <= '1' when (spi_addr_wrap(3 downto 0) = "1110") else '0';
wrp_addr_len_4_siz_16 <= '1' when (spi_addr_wrap(2 downto 0) = "110") else '0';
wrp_addr_len_2_siz_16 <= '1' when (spi_addr_wrap(1 downto 0) = "10") else '0';
-----------------------------------------------------------------------------------
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytes are transferred from SPI.
LEN_CNTR_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000011";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_24_BIT_GEN;
---------------------------------
LEN_CNTR_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000000";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1') or (wr_en_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_32_BIT_GEN;
---------------------------------
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process or wr_en_under_process) and
not(or_reduce(length_cntr)) and
SPIXfer_done_int_pulse);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1') then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process
--or wr_en_under_process
)
and
not(
or_reduce(length_cntr))
and
SPIXfer_done_int_pulse
);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_24_BIT_ADDR_GEN;
-------------------------------------------
DELAY_FIFO_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty_d1 <= '1';
SR_5_Tx_Empty_d2 <= '1';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
SR_5_Tx_Empty_d2 <= SR_5_Tx_Empty_d1;
end if;
end if;
end process DELAY_FIFO_EMPTY_P;
-------------------------------------------------------------------------------
last_bt_one_data <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0);
-------------------------------------------------------------------------------
SIZE_CNTR_LD_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
size_length_cntr_fixed <= (others => '0');
size_length_cntr <= (others => '0');
elsif(
(pr_state_idle = '1') or ((SPIXfer_done_int = '1') and
(size_length_cntr = "00"))
)then
--if(one_byte_xfer_to_spi_clk = '1' )then
-- size_length_cntr_fixed <= "00";
-- size_length_cntr <= "00"; -- 1 byte
--els
if(two_byte_xfer_to_spi_clk = '1')then
size_length_cntr_fixed <= "01";
size_length_cntr <= "01"; -- half word
elsif(four_byte_xfer_to_spi_clk = '1') then
size_length_cntr_fixed <= "10";
size_length_cntr <= "11"; -- word
else
size_length_cntr_fixed <= "00";
size_length_cntr <= "00"; -- other and one_byte_xfer_to_spi_clk = '1' is merged here
end if;
elsif(SPIXfer_done_int = '1') and
(one_byte_xfer_to_spi_clk = '0')and
(cmd_addr_sent = '1') then -- (size_length_cntr /= "00") then
size_length_cntr <= size_length_cntr - "01";
end if;
end if;
end process SIZE_CNTR_LD_SPI_CLK_P;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
store_date_in_drr_fifo <= not(or_reduce(size_length_cntr)) and
SPIXfer_done_int and
cmd_addr_sent;
-------------------------------------------------------------------------------
STORE_STROBE_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
store_date_in_drr_fifo_d1 <= '0';
store_date_in_drr_fifo_d2 <= '0';
store_date_in_drr_fifo_d3 <= '0';
else
store_date_in_drr_fifo_d1 <= store_date_in_drr_fifo;
store_date_in_drr_fifo_d2 <= store_date_in_drr_fifo_d1;
store_date_in_drr_fifo_d3 <= store_date_in_drr_fifo_d2;
end if;
end if;
end process STORE_STROBE_SPI_CLK_P;
-------------------------------------------------------------------------------
MD_12_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
begin
-----
--------------------------------------------------------------------
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate WB_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate NM_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
end generate MD_12_WR_EN_TO_FIFO_GEN;
MD_0_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 0 generate
begin
-----
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate WB_FIFO_WR_EN_GEN;
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate NM_FIFO_WR_EN_GEN;
end generate MD_0_WR_EN_TO_FIFO_GEN;
-------------------------------------------------------------------------------
SHIFT_TX_REG_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
elsif(load_wr_hpm = '1') then
Tx_Data_d1(31 downto 24) <= WB_wr_hpm_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk; -- & SPI_cmd;-- (31 downto 8);
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap;--spi_addr_i & SPI_cmd;
elsif(SPIXfer_done_int = '1')then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & "11111111";
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
end generate SHIFT_TX_REG_24_BIT_GEN;
-------------------------------------------------------
SHIFT_TX_REG_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
--last_7_addr_bits <= (others => '0');
elsif(load_wr_en = '1') then
Tx_Data_d1(31 downto 24) <= "00000110"; ---nm_wr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_wr_hpm = '1')then
Tx_Data_d1(31 downto 24) <= "10110111"; ---nm_4byte_addr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk(31 downto 8); -- & SPI_cmd;-- (31 downto 8);
last_7_addr_bits <= Transmit_Addr_to_spi_clk(7 downto 0);
-- internal_count <= (others => '0');
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap(31 downto 8);--spi_addr_i & SPI_cmd;
last_7_addr_bits <= spi_addr_wrap(7 downto 0);
elsif(SPIXfer_done_int = '1') then -- and internal_count < "0101")then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & -- Transmit_Addr_to_spi_clk(7 downto 0);
-- spi_addr_wrap(7 downto 0);
last_7_addr_bits(7 downto 0);
-- internal_count <= internal_count + "0001";
--elsif(SPIXfer_done_int = '1' and internal_count = "0101") then
-- Tx_Data_d1 <= (others => '1');
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
-- STORE_INFO_P:process(EXT_SPI_CLK)is
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
-- if(Rst_to_spi = '1')then
-- data_loaded <= '0';
-- cmd_sent <= '0';
-- elsif(load_axi_data_to_spi_clk = '1' or wrap_around = '1) then
-- data_loaded <= '1';
-- elsif(data_loaded = '1' and SPIXfer_done_int = '1') then
-- cmd_sent <= '1';
-- end if;
-- end if;
-- end process STORE_INFO_P;
end generate SHIFT_TX_REG_32_BIT_GEN;
-------------------------------------------------------
-- Transmit_Data <= Tx_Data_d1(31 downto 24);
-------------------------------------------------------
-------------------------------------------------------------------------------
STD_MODE_CONTROL_GEN: if C_SPI_MODE = 0 generate
-----
begin
-----
WB_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 1 generate
-----------
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_hpm_done <= '1';
load_wr_en <= '0';-- 4/12/2013 applicable only for Numonyx memories
---- Std mode command = 0x0B - Fast Read
SPI_cmd <= "00001011"; -- FAST_READ
-- |<---- cmd error
-- WB 000 000 0100 0<-cmd error
-- NM 000 000 0100 0
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is applicable only for Winbond memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-----------------------------------------
end generate WB_MEM_STD_MD_GEN;
------------------------
--------------------------------------------------------------------------
NM_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_NM_24_BIT_GEN;
STD_SPI_CMD_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_NM_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_STD_MD_GEN;
------------------------
end generate STD_MODE_CONTROL_GEN;
-------------------------------------------------------------------------------
DUAL_MODE_CONTROL_GEN: if C_SPI_MODE = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);-----
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
WB_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 1 generate
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => --load_wr_en_cmd <= '1';
load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
-- WB 0011 000 100 0
-- NM 0011 000 100 0<-cmd error
-- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1'; -- <- '0' for DOFR, '1' for DIOFR
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate WB_MEM_DUAL_MD_GEN;
---------------=============-------------------------------------------
NM_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 2 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "111")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_DUAL_MD_GEN;
end generate DUAL_MODE_CONTROL_GEN;
QUAD_MODE_CONTROL_GEN: if C_SPI_MODE = 2 generate
-----
begin
-----
-- WB 0011 0101 00 0<-cmd error
-- NM 001100101 00 0<-cmd error
WB_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Quad mode command = 0x6B - QOFR Read
-- SPI_cmd <= "01101011";
-- 0101 000 100 0
---- Quad mode command = 0xEB - QIOFR Read
SPI_cmd <= "11101011";
-- 0101 100 100 0 -- QUAD_IO_FAST_RD
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';-- '0' for QOFR and '1' for QIOFR
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (load_axi_data_to_spi_clk = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
----------------------------
end generate WB_MEM_QUAD_MD_GEN;
-- NM 0011 0 0101 00 0<-cmd error
NM_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1000")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1001")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate NM_MEM_QUAD_MD_GEN;
--------------------------------
end generate QUAD_MODE_CONTROL_GEN;
WRAP_DELAY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
wrap_around_d1 <= '0';
wrap_around_d2 <= '0';
wrap_around_d3 <= '0';
--wrap_around_d4 <= '0';
else
wrap_around_d1 <= wrap_around;
wrap_around_d2 <= wrap_around_d1;
wrap_around_d3 <= wrap_around_d2;
--wrap_around_d4 <= wrap_around_d3;
end if;
end if;
end process WRAP_DELAY_P;
wrap_ack <= (not wrap_around_d2) and wrap_around_d1;
wrap_ack_1 <= (not wrap_around_d3) and wrap_around_d2;
start_after_wrap <= wrap_around_d2 and (not wrap_around_d1) and not SR_5_Tx_Empty;
store_last_b4_wrap <= wrap_around_d3 and (not wrap_around_d2);
--xsfer_start_aftr_wrap <= wrap_around_d4 and (not wrap_around_d3);
DELAY_START_AFTR_WRAP:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
start_after_wrap_d1 <= '0';
else
start_after_wrap_d1 <= start_after_wrap;
end if;
end if;
end process DELAY_START_AFTR_WRAP;
----------------------------------
TRANSFER_START_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1')-- or
--(wr_en_under_process_d1 = '1' and wr_en_done = '1')
then
transfer_start <= '0';
elsif (load_axi_data_to_spi_clk = '1')
or (start_after_wrap_d1 = '1')
or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_24_BIT_ADDR_GEN;
TRANSFER_START_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1') or
(wr_en_under_process_d1 = '1' and wr_en_done = '1')then
transfer_start <= '0';
elsif(load_axi_data_to_spi_clk = '1') or
(start_after_wrap_d1 = '1') or
(load_wr_hpm = '1') or
(load_wr_en = '1') then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
transfer_start_pulse <= --transfer_start and (not transfer_start_d1);
--transfer_start_d2 and (not transfer_start_d3);
transfer_start and (not(transfer_start_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
-- RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
-- begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SPIXfer_done_int <= '0';
elsif(transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- -- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- -- data register
-- --------------------------------
-- -- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- -- due to the serial input being captured on the falling edge of the PLB
-- -- clock. this is purely required for dealing with the real SPI slave memories.
-- RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_NM_GEN;
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_WB_GEN;
-----------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (transfer_start = '0') or (store_last_b4_wrap = '1') then -- (wrap_ack_1 = '1')then
Count <= (others => '0');
elsif(SPIXfer_done_int = '1')then
Count <= (others => '0');
elsif((Count(COUNT_WIDTH) = '0') and
((CPOL_to_spi_clk and CPHA_to_spi_clk) = '0')) then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
SCK_SET_RESET_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm,
load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1')then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm,
load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1') or (load_wr_en = '1') then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_32_BIT_ADDR_GEN;
-------------------------------------------
SCK_SET_RESET_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm--,
--load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm--,
--load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_24_BIT_ADDR_GEN;
-------------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (Sync_Reset = '1') or
(new_tr = '0') or (wrap_ack_1 = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '0') then -- SPIXfer_done_int_pulse_d2
if (Rst_to_spi = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d1='1') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
QSPI_NM_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 2))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 2
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_NM_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_WINBOND_MEM_DATA_CAP_GEN: if (
(C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 1
)) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_WINBOND_MEM_DATA_CAP_GEN;
------------------------------------------------------
--------------------------------
XIP_STD_DUAL_MODE_WB_MEM_GEN: if (
(C_SPI_MODE = 0 or C_SPI_MODE = 1) and
(
(C_SPI_MEMORY = 1 or C_SPI_MEMORY = 0)
)
)generate
--------------------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
) or (wrap_ack_1 = '1') then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND =>
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= '1';
if(no_slave_selected = '1') or
(wrap_around = '1')then
qspi_cntrl_ns <= IDLE;
stop_clock <= wrap_ack_1;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_NM_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 2 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_NM_MEM_GEN;
--------------------------------
--------------------------------------------------
--------------------------------------------------
XIP_QUAD_MODE_WB_MEM_GEN: if (
C_SPI_MODE = 2 and
C_SPI_MEMORY = 1
)
generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1')or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate XIP_QUAD_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 2 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
--SCK_O <= SCK_O_reg;
--SS_O <= SS_to_spi_clk;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
SS_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty_d1 = '0') and -- Length counter is not exited
(transfer_start = '1') and
(wrap_ack = '0') and -- no wrap around
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
)
else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => EXT_SPI_CLK,
D => SS_tri_state_en_control
);
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty = '0') and -- Length counter is not exited
(transfer_start = '1') and -- 4/14/2013
(wrap_ack = '0') and -- no wrap around-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => EXT_SPI_CLK,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => EXT_SPI_CLK,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif(
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
SS_O_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (SR_5_Tx_Empty ='1') then
SS_O <= (others => '1');
elsif(hpm_under_process_d1 = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_24_BIT_ADDR_GEN;
----------------------------------
SS_O_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (transfer_start = '0' and SR_5_Tx_Empty_d1='1') then
SS_O <= (others => '1');
elsif(hpm_under_process = '1') or (wr_en_under_process = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_32_BIT_ADDR_GEN;
----------------------------------
no_slave_selected <= and_reduce(SS_to_spi_clk((C_NUM_SS_BITS-1) downto 0));
-------------------------------------------------------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
--attribute IOB : string;
--attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL_to_spi_clk ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
--(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= '0'; -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => EXT_SPI_CLK, -- Clock input
CE => '1', -- Clock enable input
R => Rst_to_spi, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL_to_spi_clk ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') -- and
--(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Rst_to_spi = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0')-- or -- dont allow sck to go out when
--(Mst_N_Slv = '0')
)then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
--end generate RATIO_NOT_EQUAL_4_GENERATE;
end generate RATIO_OF_2_GENERATE;
end architecture imp;
------------------------------------------------------------------------------- | mit |
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/proc_common_v4_0/hdl/src/vhdl/common_types_pkg.vhd | 15 | 12094 | -------------------------------------------------------------------------------
-- $Id: common_types_pkg.vhd,v 1.1.4.4 2010/10/28 01:14:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- Common_Types - package and package body
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: common_types_pkg.vhd
-- Version: v1.00a
-- Description: A package with common type definition and help functions
--
--
-------------------------------------------------------------------------------
-- Structure:
-- common_types_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT (from goran's microblaze_types_pkg.vhd)
-- History:
-- BLT 6-29-2001 -- First version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 10/7/2010 v3_0_a
-- ~~~~~~
-- - Changed Get_RLOC_Name function implementation to an equivalent version
-- that addresses CR 574505.
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package Common_Types is
type RLOC_POS_TYPE is
record
X : natural;
Y : natural;
end record RLOC_POS_TYPE;
type TARGET_FAMILY_TYPE is (VIRTEX, VIRTEX2);
function log2(x : natural) return integer;
function String_To_Int(S : string) return integer;
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string;
end package Common_Types;
-------------------------------------------------------------------------------
-- Package Body section
-------------------------------------------------------------------------------
package body Common_Types is
-- log2 function returns the number of bits required to encode x choices
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
--itoa function converts integer to a text string
--this function is required since 'image doesn't work
--in synplicity
-- valid range for input to the function is -9999 to 9999
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end function itoa;
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string is
variable Col : integer;
variable Row : integer;
variable S : integer;
begin
if Target = VIRTEX then
Row := -Y;
Col := X/2;
S := 1 - (X mod 2);
return 'R' & itoa(Row) &
'C' & itoa(Col) &
".S" & itoa(S);
else -- Target = VIRTEX2
return 'X' & itoa(X) & 'Y' & itoa(Y);
end if;
end function Get_RLOC_Name;
type POS_RECORD is
record
X : natural;
Y : natural;
end record POS_RECORD;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
-----------------------------------------------------------------------------
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end function String_To_Int;
-- function Get_RLOC ( Target : TARGET_FAMILY_TYPE;
-- Module : MODULE_TYPE;
-- Index : natural) return string is
-- begin -- function Get_RLOC
-- end function Get_RLOC;
end package body Common_Types;
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/ipif_pkg.vhd | 15 | 53612 | -------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/ipif_pkg.vhd | 15 | 53612 | -------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/common/synchronizer_ff.vhd | 19 | 8637 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| mit |
frankvanbever/MIPS_processor | Xilinx_Files/toplevel_tb.vhd | 1 | 1685 | -- Vhdl test bench created from schematic /home/frank/Dropbox/Workspaces/workspace_comp_arch/MIPS_processor_2/toplevel.sch - Mon Apr 29 14:31:37 2013
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY toplevel_toplevel_sch_tb IS
END toplevel_toplevel_sch_tb;
ARCHITECTURE behavioral OF toplevel_toplevel_sch_tb IS
COMPONENT toplevel
PORT( RST : IN STD_LOGIC;
CLK : IN STD_LOGIC);
END COMPONENT;
SIGNAL RST : STD_LOGIC;
SIGNAL CLK : STD_LOGIC;
constant clk_period : time := 100 ns;
BEGIN
UUT: toplevel PORT MAP(
RST => RST,
CLK => CLK
);
-- *** Test Bench - User Defined Section ***
clk_process :process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
tb : PROCESS
BEGIN
RST<='1';
wait for 1ns;
RST<='0';
wait for 1ns;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/wr_logic.vhd | 19 | 37687 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/fifo_generator_v11_0/ramfifo/wr_logic.vhd | 19 | 37687 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/wr_logic.vhd | 19 | 37687 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd | 15 | 12529 | -------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/dynshreg_f.vhd | 15 | 15946 | -------------------------------------------------------------------------------
-- $Id: dynshreg_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v4_0.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/rd_logic.vhd | 19 | 48192 | `protect begin_protected
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd | 19 | 78408 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd | 19 | 78408 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd | 19 | 78408 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd | 19 | 78408 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8
WbsjeU4skQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304)
`protect data_block
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`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/sync_fifo_fg.vhd | 12 | 68755 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
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-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
library fifo_generator_v11_0;
--use proc_common_v4_0.coregen_comp_defs.all;
use fifo_generator_v11_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/proc_common_v4_0/hdl/src/vhdl/sync_fifo_fg.vhd | 12 | 68755 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
library fifo_generator_v11_0;
--use proc_common_v4_0.coregen_comp_defs.all;
use fifo_generator_v11_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/zpuino_serialreset.vhd | 13 | 2740 | --
-- Serial reset for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- This module causes a synchronous reset when we receive 0xFF at 300 baud.
-- Hopefully no other speed setting will cause this.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 100
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end entity zpuino_serialreset;
architecture behave of zpuino_serialreset is
constant rstcount_val: integer := ((SYSTEM_CLOCK_MHZ*1000000)/300)*8;
signal rstcount: integer;
signal rstcount_zero_q: std_logic;
begin
rstout<='1' when rstin='1' or rstcount_zero_q='1' else '0';
process(clk)
begin
if rising_edge(clk) then
if rstin='1' then
rstcount <= rstcount_val;
rstcount_zero_q <= '0';
else
if rx='1' then
rstcount <= rstcount_val;
else
if rstcount/=0 then
rstcount <= rstcount - 1;
rstcount_zero_q<='0';
else
rstcount_zero_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/bootloader.vhd | 1 | 13707 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity bootloader_dp_32 is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(11 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(11 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity bootloader_dp_32;
architecture behave of bootloader_dp_32 is
subtype RAM_WORD is STD_LOGIC_VECTOR (31 downto 0);
type RAM_TABLE is array (0 to 1023) of RAM_WORD;
shared variable RAM: RAM_TABLE := RAM_TABLE'(
x"0b0b0b98",x"c0040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b98",x"a1040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fd0608",x"72830609",x"81058205",x"832b2a83",x"ffff0652",x"04000000",x"00000000",x"00000000",x"71fd0608",x"83ffff73",x"83060981",x"05820583",x"2b2b0906",x"7383ffff",x"0b0b0b0b",x"83a70400",x"72098105",x"72057373",x"09060906",x"73097306",x"070a8106",x"53510400",x"00000000",x"00000000",x"72722473",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71737109",x"71068106",x"30720a10",x"0a720a10",x"0a31050a",x"81065151",x"53510400",x"00000000",x"72722673",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"cc040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"720a722b",x"0a535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72729f06",x"0981050b",x"0b0b88af",x"05040000",x"00000000",x"00000000",x"00000000",x"00000000",x"72722aff",x"739f062a",x"0974090a",x"8106ff05",x"06075351",x"04000000",x"00000000",x"00000000",x"71715351",x"020d0406",x"73830609",x"81058205",x"832b0b2b",x"0772fc06",x"0c515104",x"00000000",x"72098105",x"72050970",x"81050906",x"0a810653",x"51040000",x"00000000",x"00000000",x"00000000",x"72098105",x"72050970",x"81050906",x"0a098106",x"53510400",x"00000000",x"00000000",x"00000000",x"71098105",x"52040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72720981",x"05055351",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097206",x"73730906",x"07535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fc0608",x"72830609",x"81058305",x"1010102a",x"81ff0652",x"04000000",x"00000000",x"00000000",x"71fc0608",x"0b0b0b9e",x"ec738306",x"10100508",x"060b0b0b",x"88b20400",x"00000000",x"00000000",x"0b0b0b89",x"80040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"e8040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097081",x"0509060a",x"8106ff05",x"70547106",x"73097274",x"05ff0506",x"07515151",x"04000000",x"72097081",x"0509060a",x"098106ff",x"05705471",x"06730972",x"7405ff05",x"06075151",x"51040000",x"05ff0504",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"810b0b0b",x"0b9fb40c",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71810552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"02840572",x"10100552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"717105ff",x"05715351",x"020d0400",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"81dd3f96",x"ba3f0400",x"00000000",x"00000000",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101053",x"51047381",x"ff067383",x"06098105",x"83051010",x"102b0772",x"fc060c51",x"51043c04",x"72728072",x"8106ff05",x"09720605",x"71105272",x"0a100a53",x"72ed3851",x"51535104",x"88088c08",x"90087575",x"99ed2d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90087575",x"99a92d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90088dff",x"2d900c8c",x"0c880c04",x"ff3d0d0b",x"0b0b9fc4",x"335170a6",x"389fc008",x"70085252",x"70802e92",x"3884129f",x"c00c702d",x"9fc00870",x"08525270",x"f038810b",x"0b0b0b9f",x"c434833d",x"0d040480",x"3d0d0b0b",x"0b9ff008",x"802e8e38",x"0b0b0b0b",x"800b802e",x"09810685",x"38823d0d",x"040b0b0b",x"9ff0510b",x"0b0bf5f8",x"3f823d0d",x"0404ff3d",x"0d80c480",x"80845271",x"0870822a",x"70810651",x"515170f3",x"38833d0d",x"04ff3d0d",x"80c48080",x"84527108",x"70812a70",x"81065151",x"5170f338",x"7382900a",x"0c833d0d",x"04fe3d0d",x"747080dc",x"8080880c",x"7081ff06",x"ff831154",x"51537181",x"268d3880",x"fd518aa9",x"2d72a032",x"51833972",x"518aa92d",x"843d0d04",x"803d0d83",x"ffff0b83",x"d00a0c80",x"fe518aa9",x"2d823d0d",x"04ff3d0d",x"83d00a08",x"70882a52",x"528ac92d",x"7181ff06",x"518ac92d",x"80fe518a",x"a92d833d",x"0d0482f6",x"ff0b80cc",x"8080880c",x"800b80cc",x"8080840c",x"9f0b8390",x"0a0c04ff",x"3d0d7370",x"08515180",x"c8808084",x"70087084",x"80800772",x"0c525283",x"3d0d04ff",x"3d0d80c8",x"80808470",x"0870fbff",x"ff06720c",x"5252833d",x"0d04a090",x"0ba0800c",x"9fc80ba0",x"840c98d9",x"2dff3d0d",x"73518b71",x"0c901152",x"b4808072",x"0c80720c",x"700883ff",x"ff06880c",x"833d0d04",x"fa3d0d78",x"7a7dff1e",x"57575853",x"73ff2ea7",x"38805684",x"5275730c",x"72088818",x"0cff1252",x"71f33874",x"84167408",x"720cff16",x"56565273",x"ff2e0981",x"06dd3888",x"3d0d04f8",x"3d0d80c0",x"80808457",x"83d00a59",x"8be32d76",x"518c892d",x"9fc87088",x"081010b4",x"80840571",x"70840553",x"0c5656fb",x"8084a1ad",x"750c9fa4",x"0b88170c",x"8070780c",x"770c7608",x"83ffff06",x"5683ffdf",x"800b8808",x"278338ff",x"3983ffff",x"790ca080",x"54880853",x"78527651",x"8ca82d76",x"518bc72d",x"78085574",x"762e8938",x"80c3518a",x"a92dff39",x"a0840855",x"74faa090",x"ae802e89",x"3880c251",x"8aa92dff",x"39900a70",x"0870ffbf",x"06720c56",x"568a8e2d",x"8bfa2dff",x"3d0d9fd4",x"0881119f",x"d40c5183",x"900a7008",x"70feff06",x"720c5252",x"833d0d04",x"803d0d8a",x"f82d7281",x"8007518a",x"c92d8b8d",x"2d823d0d",x"04fe3d0d",x"80c08080",x"84538be3",x"2d85730c",x"80730c72",x"087081ff",x"06745351",x"528bc72d",x"71880c84",x"3d0d04fc",x"3d0d7681",x"11338212",x"33718180",x"0a297184",x"80802905",x"83143370",x"82802912",x"84163352",x"7105a080",x"05861685",x"17335752",x"53535557",x"5553ff13",x"5372ff2e",x"91387370",x"81055533",x"52717570",x"81055734",x"e9398951",x"8e9c2d86",x"3d0d04f9",x"3d0d7957",x"80c08080",x"84568be3",x"2d811733",x"82183371",x"82802905",x"53537180",x"2e943885",x"17725553",x"72708105",x"5433760c",x"ff145473",x"f3388317",x"33841833",x"71828029",x"05565280",x"54737527",x"97387358",x"77760c73",x"17760853",x"53717334",x"81145474",x"7426ed38",x"75518bc7",x"2d8af82d",x"8184518a",x"c92d7488",x"2a518ac9",x"2d74518a",x"c92d8054",x"7375278f",x"38731770",x"3352528a",x"c92d8114",x"54ee398b",x"8d2d893d",x"0d04f93d",x"0d795680",x"c0808084",x"558be32d",x"86750c74",x"518bc72d",x"8be32d81",x"ad70760c",x"81173382",x"18337182",x"80290583",x"1933780c",x"84193378",x"0c851933",x"780c5953",x"53805473",x"7727b338",x"72587380",x"2e87388b",x"e32d7775",x"0c731686",x"1133760c",x"87113376",x"0c527451",x"8bc72d8e",x"b12d8808",x"81065271",x"f6388214",x"54767426",x"d1388be3",x"2d84750c",x"74518bc7",x"2d8af82d",x"8187518a",x"c92d8b8d",x"2d893d0d",x"04fc3d0d",x"76811133",x"82123371",x"902b7188",x"2b078314",x"33707207",x"882b8416",x"33710751",x"52535757",x"54528851",x"8e9c2d81",x"ff518aa9",x"2d80c480",x"80845372",x"0870812a",x"70810651",x"515271f3",x"38738480",x"800780c4",x"8080840c",x"863d0d04",x"fe3d0d8e",x"b12d8808",x"88088106",x"535371f3",x"388af82d",x"8183518a",x"c92d7251",x"8ac92d8b",x"8d2d843d",x"0d04fe3d",x"0d800b9f",x"d40c8af8",x"2d818151",x"8ac92d9f",x"a4538f52",x"72708105",x"5433518a",x"c92dff12",x"5271ff2e",x"098106ec",x"388b8d2d",x"843d0d04",x"fe3d0d80",x"0b9fd40c",x"8af82d81",x"82518ac9",x"2d80c080",x"8084528b",x"e32d81f9",x"0a0b80c0",x"80809c0c",x"71087252",x"538bc72d",x"729fdc0c",x"72902a51",x"8ac92d9f",x"dc08882a",x"518ac92d",x"9fdc0851",x"8ac92d8e",x"b12d8808",x"518ac92d",x"8b8d2d84",x"3d0d0480",x"3d0d810b",x"9fd80c80",x"0b83900a",x"0c85518e",x"9c2d823d",x"0d04803d",x"0d800b9f",x"d80c8bae",x"2d86518e",x"9c2d823d",x"0d04fd3d",x"0d80c080",x"8084548a",x"518e9c2d",x"8be32d9f",x"c8745253",x"8c892d72",x"88081010",x"b4808405",x"71708405",x"530c52fb",x"8084a1ad",x"720c9fa4",x"0b88140c",x"73518bc7",x"2d8a8e2d",x"8bfa2dfc",x"3d0d80c0",x"80808470",x"52558bc7",x"2d8be32d",x"8b750c76",x"80c08080",x"940c8075",x"0ca08054",x"775383d0",x"0a527451",x"8ca82d74",x"518bc72d",x"8a8e2d8b",x"fa2dffab",x"3d0d800b",x"9fd80c80",x"0b9fd40c",x"800b8dff",x"0ba0800c",x"5780c480",x"80845584",x"80b3750c",x"80c88080",x"a453fbff",x"ff730870",x"7206750c",x"535480c8",x"80809470",x"08707606",x"720c5353",x"a8709aa5",x"71708405",x"530c9b82",x"710c539c",x"9b0b8812",x"0c9daa0b",x"8c120c94",x"bb0b9012",x"0c53880b",x"80d08080",x"840c80d0",x"0a538173",x"0c8bae2d",x"8288880b",x"80dc8080",x"840c81f2",x"0b900a0c",x"80c08080",x"84705252",x"8bc72d8b",x"e32d7151",x"8bc72d8b",x"e32d8472",x"0c71518b",x"c72d7677",x"7675933d",x"41415b5b",x"5b83d00a",x"5c780870",x"81065152",x"719d389f",x"d8085372",x"f0389fd4",x"085287e8",x"7227e638",x"727e0c72",x"83900a0c",x"98d12d82",x"900a0853",x"79802e81",x"b4387280",x"fe2e0981",x"0680f438",x"76802ec1",x"38807d78",x"58565a82",x"7727ffb5",x"3883ffff",x"7c0c79fe",x"18535379",x"72279838",x"80dc8080",x"88725558",x"72157033",x"790c5281",x"13537373",x"26f238ff",x"16751154",x"7505ff05",x"70337433",x"7072882b",x"077f0853",x"51555152",x"71732e09",x"8106feed",x"38743353",x"728a26fe",x"e4387210",x"109ef805",x"75527008",x"5152712d",x"fed33972",x"80fd2e09",x"81068638",x"815bfec5",x"3976829f",x"269e387a",x"802e8738",x"8073a032",x"545b80d7",x"3d7705fd",x"e0055272",x"72348117",x"57fea239",x"805afe9d",x"397280fe",x"2e098106",x"fe933879",x"5783ffff",x"7c0c8177",x"5c5afe85",x"39803d0d",x"88088c08",x"9008a080",x"0851702d",x"900c8c0c",x"8a0c810b",x"80d00a0c",x"823d0d04",x"ff3d0d98",x"fd2d8052",x"805194f2",x"2d833d0d",x"0483ffff",x"f80d8ce3",x"0483ffff",x"f80da088",x"04000000",x"00000000",x"00000000",x"00000000",x"820b80d0",x"8080900c",x"0b0b0b04",x"0083f00a",x"0b800ba0",x"80721208",x"720c8412",x"5271712e",x"ff05f238",x"028c050d",x"98f00400",x"00000000",x"00000000",x"00000000",x"00fb3d0d",x"77795555",x"80567575",x"24ab3880",x"74249d38",x"80537352",x"745180e1",x"3f880854",x"75802e85",x"38880830",x"5473880c",x"873d0d04",x"73307681",x"325754dc",x"39743055",x"81567380",x"25d238ec",x"39fa3d0d",x"787a5755",x"80577675",x"24a43875",x"9f2c5481",x"53757432",x"74315274",x"519b3f88",x"08547680",x"2e853888",x"08305473",x"880c883d",x"0d047430",x"558157d7",x"39fc3d0d",x"76785354",x"81538074",x"73265255",x"72802e98",x"3870802e",x"a9388072",x"24a43871",x"10731075",x"72265354",x"5272ea38",x"73517883",x"38745170",x"880c863d",x"0d047281",x"2a72812a",x"53537280",x"2ee63871",x"7426ef38",x"73723175",x"74077481",x"2a74812a",x"55555654",x"e539fc3d",x"0d767079",x"7b555555",x"558f7227",x"8c387275",x"07830651",x"70802ea7",x"38ff1252",x"71ff2e98",x"38727081",x"05543374",x"70810556",x"34ff1252",x"71ff2e09",x"8106ea38",x"74880c86",x"3d0d0474",x"51727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0cf01252",x"718f26c9",x"38837227",x"95387270",x"84055408",x"71708405",x"530cfc12",x"52718326",x"ed387054",x"ff8339fc",x"3d0d7679",x"71028c05",x"9f053357",x"55535583",x"72278a38",x"74830651",x"70802ea2",x"38ff1252",x"71ff2e93",x"38737370",x"81055534",x"ff125271",x"ff2e0981",x"06ef3874",x"880c863d",x"0d047474",x"882b7507",x"7071902b",x"07515451",x"8f7227a5",x"38727170",x"8405530c",x"72717084",x"05530c72",x"71708405",x"530c7271",x"70840553",x"0cf01252",x"718f26dd",x"38837227",x"90387271",x"70840553",x"0cfc1252",x"718326f2",x"387053ff",x"9039fb3d",x"0d777970",x"72078306",x"53545270",x"93387173",x"73085456",x"54717308",x"2e80c438",x"73755452",x"71337081",x"ff065254",x"70802e9d",x"38723355",x"70752e09",x"81069538",x"81128114",x"71337081",x"ff065456",x"545270e5",x"38723355",x"7381ff06",x"7581ff06",x"71713188",x"0c525287",x"3d0d0471",x"0970f7fb",x"fdff1406",x"70f88482",x"81800651",x"51517097",x"38841484",x"16710854",x"56547175",x"082edc38",x"73755452",x"ff963980",x"0b880c87",x"3d0d04ff",x"3d0d9fe4",x"0bfc0570",x"08525270",x"ff2e9138",x"702dfc12",x"70085252",x"70ff2e09",x"8106f138",x"833d0d04",x"04eac13f",x"04000000",x"00ffffff",x"ff00ffff",x"ffff00ff",x"ffffff00",x"00000946",x"00000978",x"00000920",x"000007ab",x"000009cf",x"000009e6",x"0000083e",x"000008cd",x"00000757",x"000009fa",x"01090d00",x"007fef80",x"05b8d800",x"a4041700",x"00000000",x"00000000",x"00000000",x"00000fec",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"ffffffff",x"00000000",x"ffffffff",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if WEA='1' then
RAM(conv_integer(ADDRA) ) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if WEB='1' then
RAM( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_vga_zxspectrum.vhd | 13 | 16636 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_vga_zxspectrum is
port(
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
-- Wishbone MASTER interface
mi_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
mi_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
mi_wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
mi_wb_sel_o: out std_logic_vector(3 downto 0);
mi_wb_cti_o: out std_logic_vector(2 downto 0);
mi_wb_we_o: out std_logic;
mi_wb_cyc_o: out std_logic;
mi_wb_stb_o: out std_logic;
mi_wb_ack_i: in std_logic;
-- VGA signals
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_b: out std_logic;
vga_r: out std_logic;
vga_g: out std_logic;
vga_bright: out std_logic
);
end entity;
architecture behave of VIDEO_zpuino_wb_vga_zxspectrum is
component gh_fifo_async_rrd_sr_wf is
GENERIC (add_width: INTEGER :=8; -- min value is 2 (4 memory locations)
data_width: INTEGER :=8 ); -- size of data bus
port (
clk_WR : in STD_LOGIC; -- write clock
clk_RD : in STD_LOGIC; -- read clock
rst : in STD_LOGIC; -- resets counters
srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR)
WR : in STD_LOGIC; -- write control
RD : in STD_LOGIC; -- read control
D : in STD_LOGIC_VECTOR (data_width-1 downto 0);
Q : out STD_LOGIC_VECTOR (data_width-1 downto 0);
empty : out STD_LOGIC;
qfull : out STD_LOGIC;
hfull : out STD_LOGIC;
qqqfull : out STD_LOGIC;
afull : out STD_LOGIC;
full : out STD_LOGIC);
end component;
signal fifo_full: std_logic;
signal fifo_almost_full: std_logic;
signal fifo_write_enable: std_logic;
signal fifo_quad_full: std_logic;
signal fifo_half_full: std_logic;
-- signal readclk: std_logic:='0';
signal fifo_clear: std_logic:='0';
signal read_enable: std_logic:='0';
signal fifo_write, read: std_logic_vector(3 downto 0);
signal fifo_empty: std_logic;
signal char_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal char_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal char_wb_adr_i: std_logic_vector(maxIObit downto minIObit);
signal char_wb_cyc_i: std_logic;
signal char_wb_stb_i: std_logic;
signal char_wb_ack_o: std_logic;
signal membase: std_logic_vector(wordSize-1 downto 0) := (others => '0');
signal palletebase: std_logic_vector(wordSize-1 downto 0) := (others => '0');
type state_type is (
fetch_char,
fetch_pallete,
load_char,
fill,
next_line,
sleep
);
type vgaregs_type is record
state: state_type;
chars: std_logic_vector(wordSize-1 downto 0);
pallete: std_logic_vector(wordSize-1 downto 0);
--charline: std_logic_vector(7 downto 0); -- The 8 pixels of a char row
--charpal: std_logic_vector(7 downto 0); -- Pallete for this char
hptr: integer range 0 to 79; -- horizontal counter
hoff: unsigned(4 downto 0);
voff: unsigned(4 downto 0);
memptr: unsigned(wordSize-1 downto 0);
palleteptr: unsigned(wordSize-1 downto 0);
ls_memptr: unsigned(wordSize-1 downto 0);
ls_palleteptr: unsigned(wordSize-1 downto 0);
end record;
signal r: vgaregs_type;
--# 640x480 @ 72Hz (VESA) hsync: 37.9kHz
--ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync
--# 640x480 @ 75Hz (VESA) hsync: 37.5kHz
--ModeLine "640x480" 31.5 640 656 720 840 480 481 484 500 -hsync -vsync
--# 640x480 @ 85Hz (VESA) hsync: 43.3kHz
--ModeLine "640x480" 36.0 640 696 752 832 480 481 484 509 -hsync -vsync
constant VGA_H_BORDER: integer := 64;
constant VGA_H_SYNC: integer := 40;
constant VGA_H_FRONTPORCH: integer := 24+VGA_H_BORDER;
constant VGA_H_DISPLAY: integer := 640 - (2*VGA_H_BORDER);
constant VGA_H_BACKPORCH: integer := 128+VGA_H_BORDER;
constant VGA_V_BORDER: integer := 48;
constant VGA_V_FRONTPORCH: integer := 29+VGA_V_BORDER;
constant VGA_V_SYNC: integer := 2;
constant VGA_V_DISPLAY: integer := 480 - (2*VGA_V_BORDER);
constant VGA_V_BACKPORCH: integer := 9+VGA_V_BORDER;
-- constant VGA_H_BORDER: integer := 0;
-- constant VGA_H_SYNC: integer := 2;
-- constant VGA_H_FRONTPORCH: integer := 2;
-- constant VGA_H_DISPLAY: integer := 128;
-- constant VGA_H_BACKPORCH: integer := 2;
-- constant VGA_V_BORDER: integer := 0;
-- constant VGA_V_FRONTPORCH: integer := 2;
-- constant VGA_V_SYNC: integer := 2;
-- constant VGA_V_DISPLAY: integer := 192;
-- constant VGA_V_BACKPORCH: integer := 2;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '1';
constant h_polarity: std_logic := '1';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
signal rstq1: std_logic:='1';
signal rstq2: std_logic;
signal v_display: std_logic;
signal v_display_in_wbclk: std_logic;
signal v_display_q: std_logic;
--signal v_border: std_logic;
signal cache_clear: std_logic;
signal vga_reset_q1, vga_reset_q2: std_logic;
signal rdly: std_logic;
signal hdup: std_logic := '1';
signal hflip: std_logic;
begin
-- Wishbone register access
wb_dat_o(31 downto 1) <= (others => DontCareValue);
wb_dat_o(0) <= v_display_in_wbclk;
mi_wb_dat_o <= (others => DontCareValue);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
rdly<='0';
wb_ack_o<='0';
else
if rdly='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
if wb_we_i='1' then
case wb_adr_i(3 downto 2) is
when "00" =>
membase(maxAddrBit downto 0) <= wb_dat_i(maxAddrBit downto 0);
when "01" =>
palletebase(maxAddrBit downto 0) <= wb_dat_i(maxAddrBit downto 0);
when others =>
end case;
end if;
wb_ack_o<='1';
rdly <= '1';
end if;
else
rdly <= '0';
wb_ack_o<='0';
end if;
end if;
end if;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (vcount_q < VGA_V_DISPLAY) then
v_display_in_wbclk <= '1';
else
v_display_in_wbclk <= '0';
end if;
end if;
end process;
process(wb_clk_i, wb_rst_i, r, mi_wb_ack_i, mi_wb_dat_i,membase,palletebase)
variable w: vgaregs_type;
variable current_char: std_logic_vector(7 downto 0);
variable current_pallete: std_logic_vector(7 downto 0);
variable vdisp_char: std_logic_vector(2 downto 0); -- Vertical offset in char (0 to 7)
variable pixel: std_logic_vector(3 downto 0);
variable hmax: integer range 0 to 7;
begin
mi_wb_stb_o <= '0';
mi_wb_cyc_o <= '0';
mi_wb_we_o <= '0';
mi_wb_adr_o <= (others => '0');
fifo_write_enable<='0';
char_wb_cyc_i<='0';
char_wb_stb_i<='0';
char_wb_adr_i <= (others => DontCareValue);
pixel := (others => DontCareValue);
-- vdisp_char := std_logic_vector(r.voff(3 downto 1)); -- Ignore last bit - will duplicate vertical line
--if hdup='1' then
hmax := 7; -- 8 32-bit values = 256 bits
--else
-- hmax := 79;
--end if;
w := r;
if wb_rst_i='1' or vga_reset_q1='1' then
w.state := sleep;
--w.palloff := (others => '0');
fifo_clear <='1';
w.hptr := 0;
w.hoff := (others =>'0');
w.voff := (others =>'0');
w.memptr := unsigned(membase);
w.palleteptr := unsigned(palletebase);
mi_wb_adr_o <= (others => DontCareValue);
w.ls_memptr := unsigned(membase);
w.ls_palleteptr := unsigned(palletebase);
else
fifo_clear<='0';
case r.state is
when fetch_char =>
mi_wb_stb_o <= '1';
mi_wb_cyc_o <= '1';
mi_wb_adr_o <= std_logic_vector( r.memptr(maxAddrBitIncIO downto 0) );
--w.charoff := (others => '0');
w.chars := mi_wb_dat_i;
w.hoff := (others => '0');
if mi_wb_ack_i='1' then
w.state := fill;
end if;
when fetch_pallete =>
mi_wb_stb_o <= '1';
mi_wb_cyc_o <= '1';
mi_wb_adr_o <= std_logic_vector( r.palleteptr(maxAddrBitIncIO downto 0) );
w.pallete := mi_wb_dat_i;
if mi_wb_ack_i='1' then
w.state := fetch_char;
end if;
when fill =>
-- Choose color
case r.palleteptr(1 downto 0) is
when "11" => current_pallete := r.pallete(7 downto 0);
when "10" => current_pallete := r.pallete(15 downto 8);
when "01" => current_pallete := r.pallete(23 downto 16);
when "00" => current_pallete := r.pallete(31 downto 24);
when others =>
end case;
--w.charpal := current_pallete;
case r.chars(31) is
when '1' =>
pixel := current_pallete(6) & current_pallete(2 downto 0);
when '0' =>
pixel := current_pallete(6) & current_pallete(5 downto 3);
when others =>
end case;
-- Other bits have extended attributes
if fifo_almost_full='0' then
fifo_write_enable<='1';
-- Shift r.chars
w.chars(31 downto 1) := r.chars(30 downto 0);
w.chars(0) := DontCareValue;
w.hoff := r.hoff + 1;
if r.hoff="11111" then -- Meaning we just output the 32 bits
if r.hptr=hmax then -- Finished a whole line
w.hptr := 0;
w.voff := r.voff + 1;
if r.voff(0)='1' then
-- Finished a whole character line
w.memptr := r.memptr + 4;
if r.voff(3 downto 0) /="1111" then
w.palleteptr := r.ls_palleteptr;
else
w.palleteptr := r.palleteptr + 1;
end if;
w.state := next_line;
else
w.memptr := r.ls_memptr;
w.palleteptr := r.ls_palleteptr;
w.state := sleep;
end if;
else
-- Still doing a line
w.hptr := w.hptr + 1;
w.memptr := r.memptr + 4;
w.palleteptr := r.palleteptr + 1;
--if r.palleteptr(1 downto 0)="11" then
-- Increase pointer
w.state := fetch_pallete;
--elsif r.memptr(1 downto 0)="11" then
-- Increase pointer
--else
-- w.state := fetch_char;
--end if;
--else
-- w.state := load_char;
--end if;
end if;
else
if r.hoff(2 downto 0)="111" then -- Just output 8 bits
w.palleteptr := r.palleteptr + 1;
if r.palleteptr(1 downto 0)="11" then
-- Increase pointer
w.state := fetch_pallete;
end if;
end if;
end if;
end if;
when sleep =>
w.state := fetch_pallete;
when next_line =>
if r.voff(3 downto 0)="0000" then
w.ls_palleteptr := r.palleteptr;
end if;
w.ls_memptr := r.memptr;
w.state := fetch_pallete;
when others =>
end case;
end if;
fifo_write <= pixel;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
--
--
-- VGA part
--
--
process(vgaclk, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(vgaclk) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
hcounter: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
else
hcount_q <= hcount_q + 1;
end if;
end if;
end if;
end process;
process(hcount_q, vcount_q)
begin
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end process;
process(vgaclk)
begin
if rising_edge(vgaclk) then
v_display_q <= v_display;
end if;
end process;
hsyncgen: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_FRONTPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_BACKPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
end if;
end if;
end if;
end if;
end process;
-- Cache clear.
vclear: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
cache_clear <= '1';
else
cache_clear<='0';
--if vcount_q = VGA_V_DISPLAY and h_sync_tick='1' then
-- cache_clear<='1';
--end if;
if not (vcount_q < VGA_V_DISPLAY) then
cache_clear <='1';
end if;
end if;
end if;
end process;
vsyncgen: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vga_vsync<=v_polarity;
--cache_clear <= '1';
else
--cache_clear <= '0';
if vcount_q = (VGA_V_DISPLAY + VGA_V_FRONTPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_BACKPORCH) then
vga_vsync <= v_polarity;
--cache_clear <= '1';
end if;
end if;
end if;
end process;
-- Synchronous output
process(vgaclk)
begin
if rising_edge(vgaclk) then
if v_display='0' then
vga_b <= '0';
vga_r <= '0';
vga_g <= '0';
vga_bright <= '0';
else
vga_b <= read(0);
vga_r <= read(1);
vga_g <= read(2);
vga_bright <= read(3);
end if;
end if;
end process;
process(wb_clk_i,cache_clear)
begin
if cache_clear='1' then
vga_reset_q1<='1';
vga_reset_q2<='1';
elsif rising_edge(wb_clk_i) then
vga_reset_q2<='0';
vga_reset_q1<=vga_reset_q2;
end if;
end process;
-- In order to perform H duplication, we use a trick here
process(vgaclk,v_display,v_display_q)
begin
if rising_edge(vgaclk) then
if v_display='1' and v_display_q='0' then
-- Starting an horizontal line display, reset hflip if needed
hflip <= '1';
else
if v_display='0' then
hflip <='0';
else
hflip <= hflip xor hdup;
end if;
end if;
end if;
end process;
read_enable <= v_display and not hflip;
myfifo: gh_fifo_async_rrd_sr_wf
generic map (
data_width => 4,
add_width => 4
)
port map (
clk_WR => wb_clk_i,
clk_RD => vgaclk,
rst => '0',
srst => fifo_clear,
WR => fifo_write_enable,
RD => read_enable,
D => fifo_write,
Q => read,
empty => fifo_empty,
qfull => fifo_quad_full,
hfull => fifo_half_full,
qqqfull => fifo_almost_full,
full => fifo_full
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_vga_zxspectrum.vhd | 13 | 16636 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_vga_zxspectrum is
port(
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
-- Wishbone MASTER interface
mi_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
mi_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
mi_wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
mi_wb_sel_o: out std_logic_vector(3 downto 0);
mi_wb_cti_o: out std_logic_vector(2 downto 0);
mi_wb_we_o: out std_logic;
mi_wb_cyc_o: out std_logic;
mi_wb_stb_o: out std_logic;
mi_wb_ack_i: in std_logic;
-- VGA signals
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_b: out std_logic;
vga_r: out std_logic;
vga_g: out std_logic;
vga_bright: out std_logic
);
end entity;
architecture behave of VIDEO_zpuino_wb_vga_zxspectrum is
component gh_fifo_async_rrd_sr_wf is
GENERIC (add_width: INTEGER :=8; -- min value is 2 (4 memory locations)
data_width: INTEGER :=8 ); -- size of data bus
port (
clk_WR : in STD_LOGIC; -- write clock
clk_RD : in STD_LOGIC; -- read clock
rst : in STD_LOGIC; -- resets counters
srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR)
WR : in STD_LOGIC; -- write control
RD : in STD_LOGIC; -- read control
D : in STD_LOGIC_VECTOR (data_width-1 downto 0);
Q : out STD_LOGIC_VECTOR (data_width-1 downto 0);
empty : out STD_LOGIC;
qfull : out STD_LOGIC;
hfull : out STD_LOGIC;
qqqfull : out STD_LOGIC;
afull : out STD_LOGIC;
full : out STD_LOGIC);
end component;
signal fifo_full: std_logic;
signal fifo_almost_full: std_logic;
signal fifo_write_enable: std_logic;
signal fifo_quad_full: std_logic;
signal fifo_half_full: std_logic;
-- signal readclk: std_logic:='0';
signal fifo_clear: std_logic:='0';
signal read_enable: std_logic:='0';
signal fifo_write, read: std_logic_vector(3 downto 0);
signal fifo_empty: std_logic;
signal char_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal char_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal char_wb_adr_i: std_logic_vector(maxIObit downto minIObit);
signal char_wb_cyc_i: std_logic;
signal char_wb_stb_i: std_logic;
signal char_wb_ack_o: std_logic;
signal membase: std_logic_vector(wordSize-1 downto 0) := (others => '0');
signal palletebase: std_logic_vector(wordSize-1 downto 0) := (others => '0');
type state_type is (
fetch_char,
fetch_pallete,
load_char,
fill,
next_line,
sleep
);
type vgaregs_type is record
state: state_type;
chars: std_logic_vector(wordSize-1 downto 0);
pallete: std_logic_vector(wordSize-1 downto 0);
--charline: std_logic_vector(7 downto 0); -- The 8 pixels of a char row
--charpal: std_logic_vector(7 downto 0); -- Pallete for this char
hptr: integer range 0 to 79; -- horizontal counter
hoff: unsigned(4 downto 0);
voff: unsigned(4 downto 0);
memptr: unsigned(wordSize-1 downto 0);
palleteptr: unsigned(wordSize-1 downto 0);
ls_memptr: unsigned(wordSize-1 downto 0);
ls_palleteptr: unsigned(wordSize-1 downto 0);
end record;
signal r: vgaregs_type;
--# 640x480 @ 72Hz (VESA) hsync: 37.9kHz
--ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync
--# 640x480 @ 75Hz (VESA) hsync: 37.5kHz
--ModeLine "640x480" 31.5 640 656 720 840 480 481 484 500 -hsync -vsync
--# 640x480 @ 85Hz (VESA) hsync: 43.3kHz
--ModeLine "640x480" 36.0 640 696 752 832 480 481 484 509 -hsync -vsync
constant VGA_H_BORDER: integer := 64;
constant VGA_H_SYNC: integer := 40;
constant VGA_H_FRONTPORCH: integer := 24+VGA_H_BORDER;
constant VGA_H_DISPLAY: integer := 640 - (2*VGA_H_BORDER);
constant VGA_H_BACKPORCH: integer := 128+VGA_H_BORDER;
constant VGA_V_BORDER: integer := 48;
constant VGA_V_FRONTPORCH: integer := 29+VGA_V_BORDER;
constant VGA_V_SYNC: integer := 2;
constant VGA_V_DISPLAY: integer := 480 - (2*VGA_V_BORDER);
constant VGA_V_BACKPORCH: integer := 9+VGA_V_BORDER;
-- constant VGA_H_BORDER: integer := 0;
-- constant VGA_H_SYNC: integer := 2;
-- constant VGA_H_FRONTPORCH: integer := 2;
-- constant VGA_H_DISPLAY: integer := 128;
-- constant VGA_H_BACKPORCH: integer := 2;
-- constant VGA_V_BORDER: integer := 0;
-- constant VGA_V_FRONTPORCH: integer := 2;
-- constant VGA_V_SYNC: integer := 2;
-- constant VGA_V_DISPLAY: integer := 192;
-- constant VGA_V_BACKPORCH: integer := 2;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '1';
constant h_polarity: std_logic := '1';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
signal rstq1: std_logic:='1';
signal rstq2: std_logic;
signal v_display: std_logic;
signal v_display_in_wbclk: std_logic;
signal v_display_q: std_logic;
--signal v_border: std_logic;
signal cache_clear: std_logic;
signal vga_reset_q1, vga_reset_q2: std_logic;
signal rdly: std_logic;
signal hdup: std_logic := '1';
signal hflip: std_logic;
begin
-- Wishbone register access
wb_dat_o(31 downto 1) <= (others => DontCareValue);
wb_dat_o(0) <= v_display_in_wbclk;
mi_wb_dat_o <= (others => DontCareValue);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
rdly<='0';
wb_ack_o<='0';
else
if rdly='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
if wb_we_i='1' then
case wb_adr_i(3 downto 2) is
when "00" =>
membase(maxAddrBit downto 0) <= wb_dat_i(maxAddrBit downto 0);
when "01" =>
palletebase(maxAddrBit downto 0) <= wb_dat_i(maxAddrBit downto 0);
when others =>
end case;
end if;
wb_ack_o<='1';
rdly <= '1';
end if;
else
rdly <= '0';
wb_ack_o<='0';
end if;
end if;
end if;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (vcount_q < VGA_V_DISPLAY) then
v_display_in_wbclk <= '1';
else
v_display_in_wbclk <= '0';
end if;
end if;
end process;
process(wb_clk_i, wb_rst_i, r, mi_wb_ack_i, mi_wb_dat_i,membase,palletebase)
variable w: vgaregs_type;
variable current_char: std_logic_vector(7 downto 0);
variable current_pallete: std_logic_vector(7 downto 0);
variable vdisp_char: std_logic_vector(2 downto 0); -- Vertical offset in char (0 to 7)
variable pixel: std_logic_vector(3 downto 0);
variable hmax: integer range 0 to 7;
begin
mi_wb_stb_o <= '0';
mi_wb_cyc_o <= '0';
mi_wb_we_o <= '0';
mi_wb_adr_o <= (others => '0');
fifo_write_enable<='0';
char_wb_cyc_i<='0';
char_wb_stb_i<='0';
char_wb_adr_i <= (others => DontCareValue);
pixel := (others => DontCareValue);
-- vdisp_char := std_logic_vector(r.voff(3 downto 1)); -- Ignore last bit - will duplicate vertical line
--if hdup='1' then
hmax := 7; -- 8 32-bit values = 256 bits
--else
-- hmax := 79;
--end if;
w := r;
if wb_rst_i='1' or vga_reset_q1='1' then
w.state := sleep;
--w.palloff := (others => '0');
fifo_clear <='1';
w.hptr := 0;
w.hoff := (others =>'0');
w.voff := (others =>'0');
w.memptr := unsigned(membase);
w.palleteptr := unsigned(palletebase);
mi_wb_adr_o <= (others => DontCareValue);
w.ls_memptr := unsigned(membase);
w.ls_palleteptr := unsigned(palletebase);
else
fifo_clear<='0';
case r.state is
when fetch_char =>
mi_wb_stb_o <= '1';
mi_wb_cyc_o <= '1';
mi_wb_adr_o <= std_logic_vector( r.memptr(maxAddrBitIncIO downto 0) );
--w.charoff := (others => '0');
w.chars := mi_wb_dat_i;
w.hoff := (others => '0');
if mi_wb_ack_i='1' then
w.state := fill;
end if;
when fetch_pallete =>
mi_wb_stb_o <= '1';
mi_wb_cyc_o <= '1';
mi_wb_adr_o <= std_logic_vector( r.palleteptr(maxAddrBitIncIO downto 0) );
w.pallete := mi_wb_dat_i;
if mi_wb_ack_i='1' then
w.state := fetch_char;
end if;
when fill =>
-- Choose color
case r.palleteptr(1 downto 0) is
when "11" => current_pallete := r.pallete(7 downto 0);
when "10" => current_pallete := r.pallete(15 downto 8);
when "01" => current_pallete := r.pallete(23 downto 16);
when "00" => current_pallete := r.pallete(31 downto 24);
when others =>
end case;
--w.charpal := current_pallete;
case r.chars(31) is
when '1' =>
pixel := current_pallete(6) & current_pallete(2 downto 0);
when '0' =>
pixel := current_pallete(6) & current_pallete(5 downto 3);
when others =>
end case;
-- Other bits have extended attributes
if fifo_almost_full='0' then
fifo_write_enable<='1';
-- Shift r.chars
w.chars(31 downto 1) := r.chars(30 downto 0);
w.chars(0) := DontCareValue;
w.hoff := r.hoff + 1;
if r.hoff="11111" then -- Meaning we just output the 32 bits
if r.hptr=hmax then -- Finished a whole line
w.hptr := 0;
w.voff := r.voff + 1;
if r.voff(0)='1' then
-- Finished a whole character line
w.memptr := r.memptr + 4;
if r.voff(3 downto 0) /="1111" then
w.palleteptr := r.ls_palleteptr;
else
w.palleteptr := r.palleteptr + 1;
end if;
w.state := next_line;
else
w.memptr := r.ls_memptr;
w.palleteptr := r.ls_palleteptr;
w.state := sleep;
end if;
else
-- Still doing a line
w.hptr := w.hptr + 1;
w.memptr := r.memptr + 4;
w.palleteptr := r.palleteptr + 1;
--if r.palleteptr(1 downto 0)="11" then
-- Increase pointer
w.state := fetch_pallete;
--elsif r.memptr(1 downto 0)="11" then
-- Increase pointer
--else
-- w.state := fetch_char;
--end if;
--else
-- w.state := load_char;
--end if;
end if;
else
if r.hoff(2 downto 0)="111" then -- Just output 8 bits
w.palleteptr := r.palleteptr + 1;
if r.palleteptr(1 downto 0)="11" then
-- Increase pointer
w.state := fetch_pallete;
end if;
end if;
end if;
end if;
when sleep =>
w.state := fetch_pallete;
when next_line =>
if r.voff(3 downto 0)="0000" then
w.ls_palleteptr := r.palleteptr;
end if;
w.ls_memptr := r.memptr;
w.state := fetch_pallete;
when others =>
end case;
end if;
fifo_write <= pixel;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
--
--
-- VGA part
--
--
process(vgaclk, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(vgaclk) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
hcounter: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
else
hcount_q <= hcount_q + 1;
end if;
end if;
end if;
end process;
process(hcount_q, vcount_q)
begin
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end process;
process(vgaclk)
begin
if rising_edge(vgaclk) then
v_display_q <= v_display;
end if;
end process;
hsyncgen: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_FRONTPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_BACKPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
end if;
end if;
end if;
end if;
end process;
-- Cache clear.
vclear: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
cache_clear <= '1';
else
cache_clear<='0';
--if vcount_q = VGA_V_DISPLAY and h_sync_tick='1' then
-- cache_clear<='1';
--end if;
if not (vcount_q < VGA_V_DISPLAY) then
cache_clear <='1';
end if;
end if;
end if;
end process;
vsyncgen: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vga_vsync<=v_polarity;
--cache_clear <= '1';
else
--cache_clear <= '0';
if vcount_q = (VGA_V_DISPLAY + VGA_V_FRONTPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_BACKPORCH) then
vga_vsync <= v_polarity;
--cache_clear <= '1';
end if;
end if;
end if;
end process;
-- Synchronous output
process(vgaclk)
begin
if rising_edge(vgaclk) then
if v_display='0' then
vga_b <= '0';
vga_r <= '0';
vga_g <= '0';
vga_bright <= '0';
else
vga_b <= read(0);
vga_r <= read(1);
vga_g <= read(2);
vga_bright <= read(3);
end if;
end if;
end process;
process(wb_clk_i,cache_clear)
begin
if cache_clear='1' then
vga_reset_q1<='1';
vga_reset_q2<='1';
elsif rising_edge(wb_clk_i) then
vga_reset_q2<='0';
vga_reset_q1<=vga_reset_q2;
end if;
end process;
-- In order to perform H duplication, we use a trick here
process(vgaclk,v_display,v_display_q)
begin
if rising_edge(vgaclk) then
if v_display='1' and v_display_q='0' then
-- Starting an horizontal line display, reset hflip if needed
hflip <= '1';
else
if v_display='0' then
hflip <='0';
else
hflip <= hflip xor hdup;
end if;
end if;
end if;
end process;
read_enable <= v_display and not hflip;
myfifo: gh_fifo_async_rrd_sr_wf
generic map (
data_width => 4,
add_width => 4
)
port map (
clk_WR => wb_clk_i,
clk_RD => vgaclk,
rst => '0',
srst => fifo_clear,
WR => fifo_write_enable,
RD => read_enable,
D => fifo_write,
Q => read,
empty => fifo_empty,
qfull => fifo_quad_full,
hfull => fifo_half_full,
qqqfull => fifo_almost_full,
full => fifo_full
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/zpu_config.vhd | 14 | 2691 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/zpuino_uart.vhd | 13 | 6945 | --
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end entity zpuino_uart;
architecture behave of zpuino_uart is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
begin
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/zpuino_uart.vhd | 13 | 6945 | --
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end entity zpuino_uart;
architecture behave of zpuino_uart is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
begin
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/zpuino_uart.vhd | 13 | 6945 | --
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end entity zpuino_uart;
architecture behave of zpuino_uart is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
begin
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/board_Papilio_Pro/zpuinopkg.vhd | 26 | 21269 | --
-- ZPUINO package
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuino_config.all;
package zpuinopkg is
constant num_devices: integer := (2**zpuino_number_io_select_bits);
type slot_std_logic_type is array(0 to num_devices-1) of std_logic;
subtype cpuword_type is std_logic_vector(31 downto 0);
type slot_cpuword_type is array(0 to num_devices-1) of cpuword_type;
subtype address_type is std_logic_vector(maxIObit downto minIObit);
type slot_address_type is array(0 to num_devices-1) of address_type;
component zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
-- Wishbone MASTER interface (for DMA)
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
memory_enable: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component zpuino_top_icache;
component zpuino_top is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type
);
end component zpuino_io;
component zpuino_empty_device is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_empty_device;
component zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end component zpuino_spi;
component zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end component zpuino_uart;
component zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end component zpuino_gpio;
component zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean := true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end component zpuino_timers;
component zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0);
intr_cfglvl:in std_logic_vector(INTERRUPT_LINES-1 downto 0)
);
end component zpuino_intr;
component zpuino_sigmadelta is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sync_in: in std_logic;
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0);
spp_data: out std_logic_vector(1 downto 0);
spp_en: out std_logic_vector(1 downto 0)
);
end component zpuino_sigmadelta;
component zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_crc16;
component zpuino_adc is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sample: in std_logic;
-- GPIO SPI pins
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
seln: out std_logic;
enabled: out std_logic
);
end component zpuino_adc;
component sram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
--wb_sel_i: in std_logic_vector(3 downto 0);
--wb_cti_i: in std_logic_vector(2 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
clk_we: in std_logic;
clk_wen: in std_logic;
-- SRAM signals
sram_addr: out std_logic_vector(18 downto 0);
sram_data: inout std_logic_vector(15 downto 0);
sram_ce: out std_logic;
sram_we: out std_logic;
sram_oe: out std_logic;
sram_be: out std_logic
);
end component sram_ctrl;
component zpuino_sevenseg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wbbootloadermux is
generic (
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
sel: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(11 downto 2);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic;
s1_wb_stall_i: in std_logic
);
end component wbbootloadermux;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component generic_sp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component generic_dp_ram;
component zpuino_io_YM2149 is
generic (
FREQMHZ: integer := 96
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end component;
component wb_sid6581 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end component wb_sid6581;
component zpuino_vga is
generic(
vgaclk_divider: integer := 2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
-- VGA interface
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r: out std_logic_vector(2 downto 0);
vga_g: out std_logic_vector(2 downto 0);
vga_b: out std_logic_vector(1 downto 0)
);
end component;
component simple_sigmadelta is
generic (
BITS: integer := 8
);
port (
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
data_out: out std_logic
);
end component simple_sigmadelta;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 92
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
end package zpuinopkg; | mit |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.g-ID_EX_Reg.vhd | 1 | 4383 | ---------------------------------------------------------------------------
-- ID/EX Pipeline Register
-- It propagates inputs coming from the decode stage to the ex stage
-- Note the use of the flush control signal: it used to flush the pipeline
-- register in case of control hazards(fluhs when the signal is asseted).
-- The reset is synchronous with respet to the clock, whereas the flush is
-- asynchronous.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
entity idex_reg is
port (
-- INPUTS
cw_to_ex_dec : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word directed to the ex stage (note -2 since unsigned control signal is alredy used in decode thus no need to propagate)
jump_address_dec : in std_logic_vector(31 downto 0); -- jump address extended
pc_4_dec : in std_logic_vector(31 downto 0); -- PC incremented by 4 from decode
read_data_1_dec : in std_logic_vector(31 downto 0); -- reg 1 read from decode
read_data_2_dec : in std_logic_vector(31 downto 0); -- reg 2 read from decode
immediate_ext_dec : in std_logic_vector(31 downto 0); -- immediate sign extended from decode
immediate_dec : in std_logic_vector(15 downto 0); -- immediate for lui instrucion from decode
rt_dec : in std_logic_vector(4 downto 0); -- rt address from decode
rd_dec : in std_logic_vector(4 downto 0); -- rs address from decode
rs_dec : in std_logic_vector(4 downto 0); -- rd address from decode
clk : in std_logic; -- global clock signal
rst : in std_logic; -- global reset signal
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word for ex stage
jump_address : out std_logic_vector(31 downto 0); -- jump address to ex stage
pc_4 : out std_logic_vector(31 downto 0);
read_data_1 : out std_logic_vector(31 downto 0);
read_data_2 : out std_logic_vector(31 downto 0);
immediate_ext : out std_logic_vector(31 downto 0);
immediate : out std_logic_vector(15 downto 0);
rt : out std_logic_vector(4 downto 0);
rd : out std_logic_vector(4 downto 0);
rs : out std_logic_vector(4 downto 0)
);
end idex_reg;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
architecture behavioral of idex_reg is
begin
------------------------
-- Reg Proc
-- Type: Sequiential
-- Purpose: Implement
-- the behavior of the
-- pipeline register
-- Reset is synchronous
------------------------
Reg_proc: process(clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
cw_to_ex <= (others => '0');
jump_address <= (others => '0');
pc_4 <= (others => '0');
read_data_1 <= (others => '0');
read_data_2 <= (others => '0');
immediate_ext <= (others => '0');
immediate <= (others => '0');
rt <= (others => '0');
rd <= (others => '0');
rs <= (others => '0');
else
cw_to_ex <= cw_to_ex_dec;
jump_address <= jump_address_dec;
pc_4 <= pc_4_dec;
read_data_1 <= read_data_1_dec;
read_data_2 <= read_data_2_dec;
immediate_ext <= immediate_ext_dec;
immediate <= immediate_dec;
rt <= rt_dec;
rd <= rd_dec;
rs <= rs_dec;
end if;
end if;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/Wishbone_Peripherals/sid_voice.vhd | 13 | 28809 | -------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/sid_voice.vhd | 13 | 28809 | -------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/sid_voice.vhd | 13 | 28809 | -------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/board_Papilio_One_500k/zpu_config_hyperion.vhd | 13 | 2695 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config_hyperion is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
constant Undefined: std_logic := '0';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 13;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
end zpu_config_hyperion;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/board_Papilio_One_500k/zpu_config_hyperion.vhd | 13 | 2695 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config_hyperion is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
constant Undefined: std_logic := '0';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 13;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
end zpu_config_hyperion;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/board_Papilio_One_500k/zpu_config_hyperion.vhd | 13 | 2695 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config_hyperion is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
constant Undefined: std_logic := '0';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 13;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
end zpu_config_hyperion;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_char_ram_8x8_sp.vhd | 13 | 16221 | --
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_char_ram_8x8_sp.vhd | 13 | 16221 | --
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_char_ram_8x8_sp.vhd | 13 | 16221 | --
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
| mit |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/altpll1.vhd | 1 | 16366 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll1 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END altpll1;
ARCHITECTURE SYN OF altpll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 11,
clk0_duty_cycle => 50,
clk0_multiply_by => 6,
clk0_phase_shift => "0",
clk1_divide_by => 9,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone II",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "11"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.727273"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "324.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "6"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "14.74560000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit |
hubertokf/VHDL-Fast-Adders | RCA/32bits/RCA/RCA.vhd | 1 | 1806 | -- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (31 downto 0);
SomaResult: out std_logic_vector (31 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (31 downto 1);
signal CarryInTemp: std_logic;
signal CarryOutTemp0,CarryOutTemp1: std_logic;
signal A, B, Ssoma: std_logic_vector(31 downto 0);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg32Bit
port(
valIn: in std_logic_vector(31 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(31 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>CarryInTemp
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>CarryOutTemp0,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_A: Reg32Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A
);
Reg_B: Reg32Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B
);
Reg_Ssoma: Reg32Bit PORT MAP (
valIn=>Ssoma,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
--somador--
Som0: Soma1 PORT MAP (
CarryInTemp,
A(0),
B(0),
Ssoma(0),
carry(1)
);
SOM: FOR i IN 1 TO 30 GENERATE
Som1: Soma1 PORT MAP (
carry(i),
A(i),
B(i),
Ssoma(i),
carry(i+1)
);
END GENERATE;
Som7: Soma1 PORT MAP (
carry(31),
A(31),
B(31),
Ssoma(31),
CarryOutTemp0
);
END strc_RCA ; | mit |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/uart.vhd | 1 | 22032 | --------------------------------------------------------------------------------
-- UART
-- Implements a universal asynchronous receiver transmitter with parameterisable
-- BAUD rate. Tested on a Spartan 6 LX9 connected to a Silicon Labs Cp210
-- USB-UART Bridge.
--
-- @author Peter A Bennett
-- @copyright (c) 2012 Peter A Bennett
-- @license LGPL
-- @email pab850@googlemail.com
-- @contact www.bytebash.com
--
-- Extended by
-- @author Robert Lange
-- @copyright (c) 2013 Robert Lange
-- @license LGPL
-- @home https://github.com/sd2k9/
--
-- Modified by
-- @author Kevin Johnson
-- @license LGPL
-- @email KJohnson@gatech.edu
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Math log2,ceil required to get the number of bits for our counter
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity UART is
Generic (
-- Baudrate in bps
-- The baudrate must satisify the following condition:
-- BAUD_DIVIDER := truncate(CLOCK_FREQUENCY/BAUD_RATE)
-- remainder(BAUD_DIVIDER/16) == 0
-- Why: 16 times oversampling on the receiver side
-- Also take care that the remainder(CLOCK_FREQUENCY/BAUD_RATE) is
-- small because this determines the UART baud rate error
-- See constant c_oversample_divider_val for more information
BAUD_RATE : positive := 9600;
-- Input Clock frequency in Hz
-- Actual clock for SCOMP version is 14.72MHz, but we tell the UART
-- 14.7456MHz to make the divider calculations work out. This creates
-- a 0.13% error, which is well within the acceptable range.
CLOCK_FREQUENCY : positive := 14745600
);
Port (
-- System Clock
CLOCK : in std_logic;
-- High-Active Asynchronous Reset
RESET : in std_logic;
-- The input data: 8 bit - this is the UART sender
-- Provide data on DATA_STREAM_IN and set STB to high
-- Keep the data stable until ACK is set to high which shows that
-- the data is copied into the internal buffer. Then you should
-- revoke STB and you can change IN as you want.
DATA_STREAM_IN : in std_logic_vector(7 downto 0);
DATA_STREAM_IN_STB : in std_logic;
DATA_STREAM_IN_ACK : out std_logic := '0';
-- The output data: 8 bit - this is the UART receiver
-- Data is only valid during the time the STB is high
-- Acknowledge the data with a pulse on ACK, which is confirmed by
-- revoking STB.
-- When the following start bit is received the data becomes
-- invalid and the STB is revoked. So take care about fetching the
-- data early enough, or install your own FIFO buffer
DATA_STREAM_OUT : out std_logic_vector(7 downto 0);
DATA_STREAM_OUT_STB : out std_logic;
DATA_STREAM_OUT_ACK : in std_logic;
TX : out std_logic;
RX : in std_logic -- Async Receive
);
end UART;
architecture RTL of UART is
----------------------------------------------------------------------------
-- BAUD Generation
----------------------------------------------------------------------------
-- First create the divider for the 16 times oversampled baud rate,
-- the baud rate then is derived by dividing by 16.
-- Thats why the 16 times oversampling clock must be derived without any reminder left
-- from the baud rate, to not disturb the resulting bit rate
-- You need to take care about this when selecting baud and clock frequency
-- Substract one, otherwise the reloading step is counted twice
constant c_oversample_divider_steps : natural := natural(CLOCK_FREQUENCY / (16*BAUD_RATE))-1;
-- And also how many bits do we need?
constant c_oversample_divider_bits : natural := natural(ceil(log2(real(c_oversample_divider_steps))));
-- And this is the counter type we use
subtype oversample_baud_counter_type is unsigned(c_oversample_divider_bits-1 downto 0);
-- Please only use this final value
constant c_oversample_divider_val : oversample_baud_counter_type := to_unsigned(c_oversample_divider_steps, c_oversample_divider_bits);
-- Datatype for the rx and tx counter type, must accomodate for the 8bit positions
subtype uart_rxtx_count_type is unsigned(2 downto 0);
constant c_uart_rxtx_count_reset : uart_rxtx_count_type := "000"; -- Reset value: 0
signal oversample_baud_counter : oversample_baud_counter_type := c_oversample_divider_val;
-- Tick created every counter reset
signal oversample_baud_tick : std_ulogic := '0';
-- At this moment we sample the incoming signal
signal uart_rx_sample_tick : std_ulogic := '0';
-- The baud rate itself is the oversampling tick divided by 16
subtype baud_counter_type is unsigned(3 downto 0);
signal baud_counter : baud_counter_type := ( others => '1');
signal baud_tick : std_ulogic := '0';
----------------------------------------------------------------------------
-- Transmitter Signals
----------------------------------------------------------------------------
type uart_tx_states is ( idle,
wait_for_tick,
send_start_bit,
transmit_data,
send_stop_bit);
signal uart_tx_state : uart_tx_states := idle;
signal uart_tx_data_block : std_logic_vector(7 downto 0) := (others => '0');
signal uart_tx_data : std_logic := '1';
signal uart_tx_count : uart_rxtx_count_type := c_uart_rxtx_count_reset; -- 8 states, stored in 3 bits
signal uart_rx_data_in_ack : std_logic := '0';
----------------------------------------------------------------------------
-- Receiver Signals
----------------------------------------------------------------------------
type uart_rx_states is ( rx_wait_start_synchronise -- Wait and deliver data
, rx_get_start_bit -- We are reading the start bit
, rx_get_data
, rx_get_stop_bit
);
signal uart_rx_state : uart_rx_states := rx_wait_start_synchronise;
signal uart_rx_bit : std_logic := '0';
signal uart_rx_data_block : std_logic_vector(7 downto 0) := (others => '0');
signal uart_rx_filter : unsigned(1 downto 0) := (others => '0');
signal uart_rx_count : uart_rxtx_count_type := c_uart_rxtx_count_reset; -- 8 states, stored in 3 bits
signal uart_rx_data_out_stb: std_ulogic := '0';
-- Syncing Clock to Receive Data, compared to baud_counter and creates uart_rx_sample_tick
signal uart_rx_sync_clock : baud_counter_type := (others => '0');
----------------------------------------------------------------------------
-- Helper functions
----------------------------------------------------------------------------
pure function shift_right_by_one ( -- Shift right by 1, fill with new bit
constant shift : in std_logic_vector(7 downto 0); -- Signal to shift
constant fill : in std_ulogic) -- New bit 7
return std_logic_vector is
variable ret : std_logic_vector(7 downto 0);
begin -- function shift_right_by_one
ret(7) := fill;
ret(6 downto 0) := shift (7 downto 1);
return ret;
end function shift_right_by_one;
----------------------------------------------------------------------------
-- Begin Body
----------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- Transmitter Part: Sending Data
----------------------------------------------------------------------------
TX <= uart_tx_data;
-- The input clock is CLOCK_FREQUENCY
-- For example its set to 100Mhz, then needs to be divided down to the
-- rate dictated by the BAUD_RATE. For example, if 115200 baud is selected
-- (115200 baud = 115200 bps - 115.2kbps) a tick must be generated once
-- every 1/115200
-- As explained above we use a two-step approach, so we just scale down
-- here the 16-times oversampled RX clock again
-- Use a down-counter to have a simple test for zero
-- Thats the counter part
TX_CLOCK_DIVIDER : process (CLOCK, RESET)
begin
if RESET = '1' then
baud_counter <= (others => '1');
elsif rising_edge (CLOCK) then
if oversample_baud_tick = '1' then -- Use as Clock enable
if baud_counter = 0 then
baud_counter <= (others => '1');
else
baud_counter <= baud_counter - 1;
end if;
end if;
end if;
end process TX_CLOCK_DIVIDER;
-- And thats the baud tick, which is of course only one clock long
-- So both counters should be Zero
TX_TICK: baud_tick <= '0' when RESET = '1' else
'1' when oversample_baud_tick = '1' and baud_counter = 0 else
'0';
-- Get data from DATA_STREAM_IN and send it one bit at a time
-- upon each BAUD tick. LSB first.
-- Wait 1 tick, Send Start Bit (0), Send Data 0-7, Send Stop Bit (1)
UART_SEND_DATA : process(CLOCK, RESET)
begin
if RESET = '1' then
uart_tx_data <= '1';
uart_tx_data_block <= (others => '0');
uart_tx_count <= c_uart_rxtx_count_reset;
uart_tx_state <= idle;
uart_rx_data_in_ack <= '0';
elsif rising_edge(CLOCK) then
uart_rx_data_in_ack <= '0';
case uart_tx_state is
when idle =>
if DATA_STREAM_IN_STB = '1' then
uart_tx_data_block <= DATA_STREAM_IN;
uart_rx_data_in_ack <= '1';
uart_tx_state <= wait_for_tick;
end if;
when wait_for_tick =>
if baud_tick = '1' then
uart_tx_state <= send_start_bit;
end if;
when send_start_bit =>
if baud_tick = '1' then
uart_tx_data <= '0';
uart_tx_state <= transmit_data;
end if;
when transmit_data =>
if baud_tick = '1' then
-- Send next bit
uart_tx_data <= uart_tx_data_block(0);
-- Shift for next transmit bit, filling with don't care
-- Xilinx ISE does not know srl? So just build it ourself, hehe
-- uart_tx_data_block <= uart_tx_data_block srl 1;
uart_tx_data_block <= shift_right_by_one(uart_tx_data_block, '-');
if uart_tx_count = 7 then -- binary 111
-- We're done, move to next state
uart_tx_state <= send_stop_bit;
else
-- Stay in current state
uart_tx_state <= transmit_data;
end if;
-- Always increment here, will go to zero if we're out
uart_tx_count <= uart_tx_count + 1;
end if;
when send_stop_bit =>
if baud_tick = '1' then
uart_tx_data <= '1';
uart_tx_state <= idle;
end if;
when others =>
uart_tx_data <= '1';
uart_tx_state <= idle;
end case;
end if;
end process UART_SEND_DATA;
----------------------------------------------------------------------------
-- Receiver Part: Getting Data
----------------------------------------------------------------------------
DATA_STREAM_IN_ACK <= uart_rx_data_in_ack;
DATA_STREAM_OUT <= uart_rx_data_block;
DATA_STREAM_OUT_STB <= uart_rx_data_out_stb;
-- The RX clock divider uses the 16 times oversampled clock, which we
-- create here from the input clock
-- Use a down-counter to have a simple test for zero
-- Thats for the counter and tick creation part
RX_CLOCK_DIVIDER : process (CLOCK, RESET)
begin
if RESET = '1' then
oversample_baud_counter <= c_oversample_divider_val;
oversample_baud_tick <= '0';
elsif rising_edge (CLOCK) then
if oversample_baud_counter = 0 then
oversample_baud_counter <= c_oversample_divider_val;
oversample_baud_tick <= '1';
else
oversample_baud_counter <= oversample_baud_counter - 1;
oversample_baud_tick <= '0';
end if;
end if;
end process RX_CLOCK_DIVIDER;
-- We create the sample time by syncing the oversampled tick (BAUD * 16)
-- to the received start bit by comparing then vs. the stored receive sync value
-- It's only one clock tick active
RX_SAMPLE: uart_rx_sample_tick <= '0' when RESET = '1' else
'1' when oversample_baud_tick = '1' and uart_rx_sync_clock = baud_counter else
'0';
-- Synchronise RXD and Filter to suppress spikes with a 2 bit counter
-- This is done with the 16-times oversampled clock
-- Take care, every time the receive clock is resynchronized to the next
-- start bit we can have somewhat of a jump here. But thats no problem
-- because the jump (in case it occur) is still synchronous. And we save us
-- another counter :-)
RXD_SYNC_FILTER : process(CLOCK, RESET)
begin
if RESET = '1' then
uart_rx_filter <= (others => '1');
uart_rx_bit <= '1';
elsif rising_edge(CLOCK) then
if oversample_baud_tick = '1' then
-- Filter RXD.
if RX = '1' and uart_rx_filter < 3 then
uart_rx_filter <= uart_rx_filter + 1;
elsif RX = '0' and uart_rx_filter > 0 then
uart_rx_filter <= uart_rx_filter - 1;
end if;
-- Set the RX bit.
if uart_rx_filter = 3 then
uart_rx_bit <= '1';
elsif uart_rx_filter = 0 then
uart_rx_bit <= '0';
end if;
end if;
end if;
end process RXD_SYNC_FILTER;
UART_RECEIVE_DATA : process(CLOCK, RESET)
begin
if RESET = '1' then
uart_rx_state <= rx_wait_start_synchronise;
uart_rx_data_block <= (others => '0');
uart_rx_count <= c_uart_rxtx_count_reset;
uart_rx_data_out_stb <= '0';
uart_rx_sync_clock <= (others => '0');
elsif rising_edge(CLOCK) then
case uart_rx_state is
-- Waiting for new data to come
when rx_wait_start_synchronise =>
-- With normal clock: Take care about the ACK from
-- previous received data
if DATA_STREAM_OUT_ACK = '1' then
-- Revoke strobe
uart_rx_data_out_stb <= '0';
-- No need to reset data block, it's anyway overwritten during recive
-- uart_rx_data_block <= (others => '0');
end if;
-- Only here we need to look for start with the
-- oversampled clock rate
if oversample_baud_tick = '1' and uart_rx_bit = '0' then
-- We are back in business!
uart_rx_state <= rx_get_start_bit;
-- Resynchronize the receive bit timing with the input signal
-- invert the MSB, because we need to skip half of
-- the start bit.
-- We want to sample in the MIDDLE of the bit, remember?
-- This will be used from now on as sample moment
uart_rx_sync_clock <=
(not baud_counter(3), baud_counter(2), baud_counter(1), baud_counter(0) );
end if; -- oversample_baud_tick = '1' and uart_rx_bit = '0'
when rx_get_start_bit =>
-- With normal clock: Take care about the ACK from
-- previous received data
if DATA_STREAM_OUT_ACK = '1' then
-- Revoke strobe
uart_rx_data_out_stb <= '0';
-- No need to reset data block, it's anyway overwritten during recive
-- uart_rx_data_block <= (others => '0');
end if;
if uart_rx_sample_tick = '1' then
if uart_rx_bit = '0' then
-- Everything alright, we really got a start bit
-- Please continue with data reception
uart_rx_state <= rx_get_data;
-- This is the last time we can revoke a potentially pending
-- receive strobe
-- Your fault if you didn't fetched the data until here!
uart_rx_data_out_stb <= '0';
-- But at least warn about this
-- Not for synthesis:
-- pragma translate_off
assert uart_rx_data_out_stb = '0'
report "Receive Data was not fetched by system! Losing previous data byte!"
severity warning;
-- pragma translate_on
else
-- Oh no! Corrupted Start bit! Now we're in trouble
-- Best to abort the game and issue a (simulation)
-- warning
uart_rx_state <= rx_wait_start_synchronise;
-- Not for synthesis:
-- pragma translate_off
report "We got an corrupted start bit! Something is wrong and most likely we will now fail to receive the following data. Trying to reset the receive state machine."
severity error;
-- pragma translate_on
end if;
end if;
when rx_get_data =>
if uart_rx_sample_tick = '1' then
-- Receive next bit, shift others one bit down
-- We receive lsb first, thus we're filling and shifting from msb direction
uart_rx_data_block <= shift_right_by_one(uart_rx_data_block, uart_rx_bit);
if uart_rx_count = 7 then -- binary 111
-- We're done, move to next state
uart_rx_state <= rx_get_stop_bit;
else
-- Continue in this state
uart_rx_state <= rx_get_data;
end if;
-- Always increment here, will go to zero if we're out
uart_rx_count <= uart_rx_count + 1;
end if;
when rx_get_stop_bit =>
if uart_rx_sample_tick = '1' then
if uart_rx_bit = '1' then
-- Everything alright, we really got the closing stop bit
-- Set our strobe: Data is ready!
uart_rx_data_out_stb <= '1';
else
-- Oh no! Corrupted Stop bit! Now we're in trouble
-- Best to abort the game and issue a (simulation) warning
-- Not for synthesis:
-- pragma translate_off
report "We got an corrupted stop bit! Something is wrong - throwing away this data byte"
severity error;
-- pragma translate_on
end if;
-- Anyway, go to wait for next datablock
uart_rx_state <= rx_wait_start_synchronise;
end if;
when others => -- This is an illegal state - start over
uart_rx_state <= rx_wait_start_synchronise;
end case;
end if;
end process UART_RECEIVE_DATA;
end RTL;
| mit |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/i2c_ctrl.vhd | 1 | 5379 | -- Controller for the I2C master.
-- This is mostly a state machine used to control
-- the various muxes and registers used for the I2C
-- device.
-- Author: Kevin Johnson. Last modified: 18 June 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c_ctrl is
port(
resetn : in std_logic;
clk : in std_logic;
IO_DATA : in std_logic_vector(15 downto 0);
wr_rdy : in std_logic;
wr_cmd : in std_logic;
wr_data : in std_logic;
rx_byte : in std_logic_vector(7 downto 0);
i2c_busy : in std_logic;
tx_addr : out std_logic_vector(7 downto 0);
tx_byte : out std_logic_vector(7 downto 0);
comm_en : out std_logic;
rnw : out std_logic;
data_out : out std_logic_vector(15 downto 0);
busy : out std_logic
);
end entity;
architecture main of i2c_ctrl is
-- Build an enumerated type for the state machine
type state_type is (idle, Tx2, Tx1p, Tx1, Rx2, Rx1p, Rx1);
-- Register used to hold the current state
signal state : state_type;
signal go : std_logic; -- tells state machine when to leave idle
signal running : std_logic; -- flag that communication is in progress
signal prev_busy : std_logic; -- previous value of i2c_busy
signal cmd_in : std_logic_vector(7 downto 0);
signal addr_in : std_logic_vector(7 downto 0);
signal data_in : std_logic_vector(15 downto 0);
begin
-- latches for the cmd/data from SCOMP:
latch_cmd_data : process (wr_cmd, wr_data, resetn)
begin
if (resetn = '0') then
cmd_in <= x"00";
elsif rising_edge(wr_cmd) then
cmd_in <= IO_DATA(15 downto 8);
addr_in <= IO_DATA(7 downto 0);
end if;
if (resetn = '0') then
data_in <= x"0000";
elsif rising_edge(wr_data) then
data_in <= IO_DATA;
end if;
end process;
-- This process handles the START signal, which
-- is basically a DFF that gets set by wr_rdy, and reset
-- by a signal from the other state machine. The other
-- state machine checks this to determine if it should start,
-- and resets this once it has started.
latch_rdy : process (wr_rdy, running, resetn)
begin
if (resetn = '0') OR (running = '1') then
go <= '0';
elsif rising_edge(wr_rdy) then
go <= '1';
end if;
end process;
busy <= running OR go;
-- The main state machine
state_machine : process (clk, resetn)
begin
if resetn = '0' then
state <= idle;
comm_en <= '0';
running <= '0';
elsif (rising_edge(clk)) then
prev_busy <= i2c_busy; -- used to detect transitions
case state is
when idle =>
if go = '1' then -- this is the signal to start
running <= '1';
tx_addr <= addr_in; -- set the I2C controller's address
data_out(15 downto 0) <= x"0000"; -- clear data
-- transition to the correct state according to cmd
if cmd_in(5 downto 4) = "10" then -- two to send
state <= Tx2;
tx_byte <= data_in(15 downto 8);
rnw <= '0';
elsif cmd_in(5 downto 4) = "01" then -- one to send
state <= Tx1p;
tx_byte <= data_in(7 downto 0);
rnw <= '0';
elsif cmd_in(1 downto 0) = "10" then -- two to rx
state <= Rx2;
rnw <= '1';
elsif cmd_in(1 downto 0) = "01" then -- one to rx
state <= Rx1p;
rnw <= '1';
else -- invalid command
state <= idle;
end if;
else -- not starting
state <= idle;
running <= '0'; -- no longer running
end if;
when Tx2 =>
comm_en <= '1'; -- safe to start transaction
if (prev_busy = '0') and (i2c_busy = '1') then -- busy just went high
tx_byte <= data_in(7 downto 0); -- prepare next byte
elsif (prev_busy = '1') and (i2c_busy = '0') then -- just went low
state <= Tx1;
end if;
when Tx1p =>
comm_en <= '1'; -- begin communication
state <= Tx1;
when Tx1 =>
if (prev_busy = '0') and (i2c_busy = '1') then -- busy just went high
rnw <= '1'; -- prepare to read
if cmd_in(1) = cmd_in(0) then -- probably 00 read, but also handles 11
comm_en <= '0'; -- end communication
end if;
elsif (prev_busy = '1') and (i2c_busy = '0') then -- just went low
if cmd_in(1 downto 0) = "10" then
state <= Rx2;
elsif cmd_in(1 downto 0) = "01" then
state <= Rx1;
else
state <= idle;
end if;
end if;
when Rx2 =>
comm_en <= '1'; -- safe to start transaction
if (prev_busy = '1') and (i2c_busy = '0') then -- just went low
state <= Rx1;
data_out(15 downto 8) <= rx_byte; -- store the rx'd byte
end if;
when Rx1p =>
comm_en <= '1'; -- begin communication
state <= Rx1;
when Rx1 =>
if (prev_busy = '0') and (i2c_busy = '1') then -- busy just went high
comm_en <= '0'; -- end communication
elsif (prev_busy = '1') and (i2c_busy = '0') then -- just went low
state <= idle;
data_out(7 downto 0) <= rx_byte; -- store the rx'd byte
end if;
when others =>
state <= idle;
end case;
end if;
end process;
end main;
| mit |
lfmunoz/vhdl | ip_blocks/sip_spi/sim/txt_util.vhd | 4 | 14568 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| mit |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/lpm_add_sub_db0.vhd | 1 | 4965 | -- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub_db0.vhd
-- Megafunction Name(s):
-- lpm_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub_db0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_add_sub_db0;
ARCHITECTURE SYN OF lpm_add_sub_db0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(8 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: Representation NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL dataa[8..0]
-- Retrieval info: USED_PORT: datab 0 0 9 0 INPUT NODEFVAL datab[8..0]
-- Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL result[8..0]
-- Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 datab 0 0 9 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| mit |
hubertokf/VHDL-Fast-Adders | CLAH/CLA2bits/8bits/CLAH8bits/CLAH8bits.vhd | 1 | 2889 | LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH8bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CLAH8bits;
ARCHITECTURE strc_CLAH8bits of CLAH8bits is
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL P0_sig, P1_sig, P2_sig, P3_sig: STD_LOGIC;
SIGNAL G0_sig, G1_sig, G2_sig, G3_sig: STD_LOGIC;
SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SomaT1,SomaT2,SomaT3,SomaT4:STD_LOGIC_VECTOR(1 DOWNTO 0);
Component CLA2bits
PORT (
val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
end component;
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg8Bit
PORT (
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end component;
Component CLGB
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
end component;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg8Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg8Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg8Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som1: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(1 DOWNTO 0),
val2(1 DOWNTO 0) => B_sig(1 DOWNTO 0),
CarryIn=>Cin_sig,
P=>P0_sig,
G=>G0_sig,
SomaResult=>SomaT1
);
CLGB1: CLGB PORT MAP(
P0=>P0_sig,
G0=>G0_sig,
P1=>P1_sig,
G1=>G1_sig,
Cin=>Cin_sig,
Cout1=>Cout1_temp_sig,
Cout2=>Cout2_temp_sig
);
Som2: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(3 DOWNTO 2),
val2(1 DOWNTO 0) => B_sig(3 DOWNTO 2),
CarryIn=>Cout1_temp_sig,
P=>P1_sig,
G=>G1_sig,
SomaResult=>SomaT2
);
Som3: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(5 DOWNTO 4),
val2(1 DOWNTO 0) => B_sig(5 DOWNTO 4),
CarryIn=>Cout2_temp_sig,
P=>P2_sig,
G=>G2_sig,
SomaResult=>SomaT3
);
CLGB2: CLGB PORT MAP(
P0=>P2_sig,
G0=>G2_sig,
P1=>P3_sig,
G1=>G3_sig,
Cin=>Cout2_temp_sig,
Cout1=>Cout3_temp_sig,
Cout2=>Cout_sig
);
Som4: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(7 DOWNTO 6),
val2(1 DOWNTO 0) => B_sig(7 DOWNTO 6),
CarryIn=>Cout3_temp_sig,
P=>P3_sig,
G=>G3_sig,
SomaResult=>SomaT4
);
Out_sig <= SomaT4 & SomaT3 & SomaT2 & SomaT1;
END strc_CLAH8bits; | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0_inst.vhd | 1 | 1597 | component pr_region_default_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X'; -- reset_req
address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component pr_region_default_onchip_memory2_0;
u0 : component pr_region_default_onchip_memory2_0
port map (
clk => CONNECTED_TO_clk, -- clk1.clk
reset => CONNECTED_TO_reset, -- reset1.reset
reset_req => CONNECTED_TO_reset_req, -- .reset_req
address => CONNECTED_TO_address, -- s1.address
clken => CONNECTED_TO_clken, -- .clken
chipselect => CONNECTED_TO_chipselect, -- .chipselect
write => CONNECTED_TO_write, -- .write
readdata => CONNECTED_TO_readdata, -- .readdata
writedata => CONNECTED_TO_writedata, -- .writedata
byteenable => CONNECTED_TO_byteenable -- .byteenable
);
| mit |
hubertokf/VHDL-Fast-Adders | RCA/8bits/RCA/Reg8Bit.vhd | 5 | 534 | library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg8Bit is
port(
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end Reg8Bit;
architecture strc_Reg8Bit of Reg8Bit is
signal Temp: std_logic_vector(7 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "00000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg8Bit; | mit |
lfmunoz/vhdl | ip_blocks/sip_spi/sim/std_logic_textio.vhd | 4 | 18485 | ----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk); -- but also exit on a bad read
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
if (readOk = FALSE) then
good := FALSE;
else
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk);
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
| mit |
hubertokf/VHDL-Fast-Adders | CSA/32bits/CSA32bits/Reg1Bit.vhd | 14 | 470 | library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg1Bit is
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end Reg1Bit;
architecture strc_Reg1Bit of Reg1Bit is
signal Temp: std_logic;
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= '0';
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg1Bit; | mit |
lfmunoz/vhdl | ip_blocks/sip_check_data/tb_sip_check_data.vhd | 1 | 11837 | -------------------------------------------------------------------------------------
-- FILE NAME : tb_sip_capture_x4.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : Jan 21, 2015
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Testbench for sip_capture_x4.vhd
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_sip_check_data is
end tb_sip_check_data;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_sip_check_data is
-------------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------------
component generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end component generic_host_emu;
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_10_MHZ : time := 100 ns;
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_368_MHZ : time := 2.7126 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal clk200 : std_logic := '1';
signal clk100 : std_logic := '1';
signal rst : std_logic := '1';
signal rst_delay : std_logic := '1';
signal rstn : std_logic := '0';
signal rst_rstin : std_logic_vector(31 downto 0);
signal clk_clkin : std_logic_vector(31 downto 0);
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal out_cmd_val : std_logic;
signal out_cmd : std_logic_vector(63 downto 0);
signal clk_cmd : std_logic;
signal adc0_out : std_logic_vector(63 downto 0);
signal adc0_val : std_logic;
signal adc0_stop : std_logic;
signal dac0_out : std_logic_vector(63 downto 0);
signal dac0_val : std_logic;
signal dac0_stop : std_logic;
-- data generation
signal lfsr_out : std_logic_vector(2 downto 0);
signal allow : std_logic := '0';
signal samples8bit : bus008(7 downto 0) := (others=>(others=>'0'));
signal base_cnt : std_logic_vector(7 downto 0);
signal data : std_logic_vector(63 downto 0);
signal valid : std_logic;
signal shift_data : std_logic_vector(63 downto 0);
signal shift_valid : std_logic;
signal control : std_logic_vector(31 downto 0);
signal status : std_logic_vector(31 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_125_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
clk200 <= not clk200 after CLK_167_MHZ / 2;
clk100 <= not clk100 after CLK_125_MHZ / 2;
rst <= '0' after CLK_167_MHZ * 10;
rstn <= '1' after CLK_167_MHZ * 10;
rst_delay <= '0' after CLK_167_MHZ * 40;
rst_rstin <= (0=>rst, 1 => rst, 2=> rst, others =>'0');
clk_clkin <= (13 => clk200, 14 => clk100, others=>clk);
-----------------------------------------------------------
-- Host Interface
-----------------------------------------------------------
inst0_generic_host: generic_host_emu
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"00000FF",
private_start_addr_gen => x"0000000",
private_stop_addr_gen => x"00000FF"
)
port map (
cmdclk_out_cmdclk => clk_cmd, -- out std_logic;
cmd_in_cmdin => out_cmd , -- in std_logic_vector(63 downto 0);
cmd_in_cmdin_val => out_cmd_val, -- in std_logic;
cmd_out_cmdout => in_cmd, -- out std_logic_vector(63 downto 0);
cmd_out_cmdout_val => in_cmd_val, -- out std_logic;
ifpga_rst_out_ifpga_rst => open, -- out std_logic;
clk_clkin => (others=>'0'),-- in std_logic_vector(31 downto 0);
rst_rstin => (others=>'0'),-- in std_logic_vector(31 downto 0);
sys_clk => clk, -- in std_logic;
sys_reset_n => rstn, -- in std_logic;
in_data_in_stop => adc0_stop, -- out std_logic;
in_data_in_dval => adc0_val, -- in std_logic;
in_data_in_data => adc0_out, -- in std_logic_vector(63 downto 0);
out_data_out_stop => dac0_stop, -- in std_logic;
out_data_out_dval => dac0_val, -- out std_logic;
out_data_out_data => dac0_out -- out std_logic_vector(63 downto 0)
);
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => clk200, -- 1-bit input: Reference clock input
RST => '0' -- 1-bit input: Active high reset input
);
-----------------------------------------------------------
-- Unit under test
-----------------------------------------------------------
sip_capture_x4_0:
entity xil_defaultlib.sip_capture_x4
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"0001FFF",
private_start_addr_gen => x"0000100",
private_stop_addr_gen => x"00001FF"
)
port map (
cmdclk_in_cmdclk => clk_cmd,
cmd_in_cmdin => in_cmd,
cmd_in_cmdin_val => in_cmd_val,
cmd_out_cmdout => out_cmd,
cmd_out_cmdout_val => out_cmd_val,
clk_clkin => clk_clkin,
rst_rstin => rst_rstin,
in0_in_stop => open,
in0_in_dval => shift_valid,
in0_in_data => shift_data,
in1_in_stop => open,
in1_in_dval => shift_valid,
in1_in_data => shift_data,
in2_in_stop => open,
in2_in_dval => shift_valid,
in2_in_data => shift_data,
in3_in_stop => open,
in3_in_dval => shift_valid,
in3_in_data => shift_data,
out0_out_stop => '0',
out0_out_dval => open,
out0_out_data => open,
out1_out_stop => '0',
out1_out_dval => open,
out1_out_data => open,
out2_out_stop => '0',
out2_out_dval => open,
out2_out_data => open,
out3_out_stop => '0',
out3_out_dval => open,
out3_out_data => open
);
--data_check_0:
--entity xil_defaultlib.data_check
--port map (
-- clk_in => clk200,
-- rst_in => rst,
-- data_in => generate_data,
-- valid_in => valid,
-- ctrl_in => control,
-- status_out => status
--);
-----------------------------------------------------------------------------------
-- Stimulus
-----------------------------------------------------------------------------------
process(clk200, rst_delay)
begin
if rising_edge(clk200) then
if rst_delay = '1' then
base_cnt <= (others =>'0');
valid <= '0';
allow <= '0';
else
allow <= lfsr_out(0);
if allow = '1' then
base_cnt <= base_cnt + 2;
valid <= '1';
else
valid <= '0';
end if;
end if;
end if;
end process;
samples8bit(0) <= base_cnt + 0;
samples8bit(1) <= base_cnt + 0;
samples8bit(2) <= base_cnt + 0;
samples8bit(3) <= base_cnt + 0;
samples8bit(4) <= base_cnt + 1;
samples8bit(5) <= base_cnt + 1;
samples8bit(6) <= base_cnt + 1;
samples8bit(7) <= base_cnt + 1;
data <= samples8bit(7) & samples8bit(6) & samples8bit(5) & samples8bit(4) &
samples8bit(3) & samples8bit(2) & samples8bit(1) & samples8bit(0);
shift_bytes_0:
entity work.shift_bytes
port map (
clk_in => clk200,
rst_in => rst,
data_in => data,
valid_in => valid,
data_out => shift_data,
valid_out => shift_valid,
shift_amount_in => "010"
);
-- generate sporadic data
uut: entity work.LFSR_0
generic map (
WIDTH => 3
)
port map (
clk_in => clk200,
rst_in => rst,
reg_out => lfsr_out
);
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit |
hubertokf/VHDL-Fast-Adders | RCA/16bits/RCA/RCA.vhd | 1 | 1806 | -- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (15 downto 0);
SomaResult: out std_logic_vector (15 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (15 downto 1);
signal CarryInTemp: std_logic;
signal CarryOutTemp0,CarryOutTemp1: std_logic;
signal A, B, Ssoma: std_logic_vector(15 downto 0);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg16Bit
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>CarryInTemp
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>CarryOutTemp0,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Ssoma,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
--somador--
Som0: Soma1 PORT MAP (
CarryInTemp,
A(0),
B(0),
Ssoma(0),
carry(1)
);
SOM: FOR i IN 1 TO 14 GENERATE
Som1: Soma1 PORT MAP (
carry(i),
A(i),
B(i),
Ssoma(i),
carry(i+1)
);
END GENERATE;
Som7: Soma1 PORT MAP (
carry(15),
A(15),
B(15),
Ssoma(15),
CarryOutTemp0
);
END strc_RCA ; | mit |
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