repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
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stringclasses 15
values |
|---|---|---|---|---|---|
es17m014/vhdl-counter | src/vhdl/ancode.vhd | 1 | 1112 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : ancode.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Switch coder
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
architecture rtl of ancode is
begin
process(sel_i, aen_i)
begin
ss_sel_o <= "1111";
if aen_i(conv_integer(sel_i)) = '1' then
ss_sel_o(conv_integer(sel_i)) <= '0';
end if;
end process;
end rtl; | mit |
TheMassController/VHDL_experimenting | project/deppSlave/test/depp_slave_controller_tb.vhd | 1 | 18940 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
use src.depp_pkg.all;
library tb;
use tb.depp_tb_pkg.all;
entity depp_slave_controller_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of depp_slave_controller_tb is
constant clk_period : time := 20 ns;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal depp_db : std_logic_vector(7 downto 0) := (others => '0');
signal depp_write : std_logic := '1';
signal depp_astb : std_logic := '1';
signal depp_dstb : std_logic := '1';
signal depp_wait : std_logic;
signal mst2slv : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal slv2mst : bus_slv2mst_type := BUS_SLV2MST_IDLE;
begin
clk <= not clk after (clk_period/2);
main : process
variable address : bus_address_type;
variable writeData : bus_data_type;
variable readData : bus_data_type;
variable readData_out : bus_data_type;
variable writeMask : bus_write_mask;
variable deppMode : depp_data_type;
variable deppAddr : depp_address_type;
variable expectedState : depp_slave_state_type := DEPP_SLAVE_STATE_TYPE_IDLE;
variable actualState : depp_slave_state_type := DEPP_SLAVE_STATE_TYPE_IDLE;
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Simple write") then
slv2mst <= BUS_SLV2MST_IDLE;
depp_db <= (others => 'Z');
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
wait until falling_edge(clk);
-- Start setting the output
address := std_logic_vector(to_unsigned(125, address'length));
writeData := std_logic_vector(to_unsigned(14, writeData'length));
writeMask := (others => '1');
depp_tb_bus_prepare_write(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address,
writeData => writeData,
writeMask => writeMask
);
-- Start the write
depp_tb_bus_start_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
doRead => false
);
wait for 2*clk_period;
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeData, writeData);
check_equal(mst2slv.writeMask, writeMask);
check_equal(mst2slv.writeEnable, '1');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '0');
-- Wait a while, then finish normally
wait for 26*clk_period;
wait until falling_edge(clk);
slv2mst.ack <= '1';
wait for clk_period;
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '1');
depp_tb_bus_finish_write_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait
);
expectedState.address := address;
expectedState.writeData := writeData;
expectedState.writeMask := writeMask;
depp_tb_slave_check_state (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
actualState => actualState
);
check(actualState = expectedState);
end if;
if run("Simple read") then
slv2mst <= BUS_SLV2MST_IDLE;
depp_db <= (others => 'Z');
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
wait until falling_edge(clk);
-- Start setting the output
address := std_logic_vector(to_unsigned(35, address'length));
writeData := (others => '0');
writeMask := (others => '0');
readData := std_logic_vector(to_unsigned(149, writeData'length));
depp_tb_bus_prepare_read(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address
);
-- Start the read
depp_tb_bus_start_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
doRead => true
);
wait for 2*clk_period;
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeData, writeData);
check_equal(mst2slv.writeMask, writeMask);
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '1');
check_equal(depp_wait, '0');
wait for 26*clk_period;
wait until falling_edge(clk);
slv2mst.ack <= '1';
slv2mst.readData <= readData;
wait for clk_period;
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '1');
depp_tb_bus_finish_write_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait
);
expectedState.address := address;
expectedState.writeData := writeData;
expectedState.readData := readData;
expectedState.writeMask := writeMask;
depp_tb_slave_check_state (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
actualState => actualState
);
check(actualState = expectedState);
end if;
if run("Write returns error") then
slv2mst <= BUS_SLV2MST_IDLE;
depp_db <= (others => 'Z');
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
wait until falling_edge(clk);
-- Start setting the output
address := std_logic_vector(to_unsigned(114, address'length));
writeData := std_logic_vector(to_unsigned(25, writeData'length));
readData := (others => '1');
writeMask := (others => '1');
depp_tb_bus_prepare_write(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address,
writeData => writeData,
writeMask => writeMask
);
-- Start the write
depp_tb_bus_start_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
doRead => false
);
wait for 2*clk_period;
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeData, writeData);
check_equal(mst2slv.writeMask, writeMask);
check_equal(mst2slv.writeEnable, '1');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '0');
-- Wait a while, then finish normally
wait for 26*clk_period;
wait until falling_edge(clk);
slv2mst.fault <= '1';
slv2mst.readData <= readData;
wait for clk_period;
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '1');
depp_tb_bus_finish_write_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait
);
expectedState.address := address;
expectedState.writeData := writeData;
expectedState.writeMask := writeMask;
expectedState.readData := readData;
expectedState.fault := true;
depp_tb_slave_check_state (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
actualState => actualState
);
check(actualState = expectedState);
end if;
if run("Sequential write mode") then
slv2mst <= BUS_SLV2MST_IDLE;
address := (others => '0');
writeData := (others => '0');
readData := (others => '0');
writeMask := (others => '0');
deppMode := (others => '0');
deppMode(depp_mode_fast_write_bit) := '1';
deppAddr := std_logic_vector(to_unsigned(depp2bus_mode_register_start, deppAddr'length));
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
-- Enable sequential write mode
depp_tb_depp_write_to_address(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
addr => deppAddr,
data => deppMode
);
-- Set the start address
depp_tb_bus_set_address (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address
);
deppAddr := std_logic_vector(to_unsigned(depp2bus_writeData_reg_start, deppAddr'length));
depp_tb_depp_set_address (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
addr => deppAddr
);
for i in 0 to 20 loop
writeData := std_logic_vector(to_unsigned(i, writeData'length));
address := std_logic_vector(to_unsigned(i*depp2bus_writeData_reg_len, address'length));
for j in 0 to depp2bus_writeData_reg_len - 1 loop
depp_tb_depp_set_data(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
data => writeData((j+1)*8 - 1 downto j*8),
expect_completion => (j /= depp2bus_writeData_reg_len - 1)
);
end loop;
wait until mst2slv.writeEnable = '1';
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeData, writeData);
check_equal(mst2slv.writeMask, writeMask);
check_equal(mst2slv.writeEnable, '1');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '0');
slv2mst.ack <= '1';
depp_tb_bus_finish_write_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait
);
slv2mst.ack <= '0';
end loop;
end if;
if run("Sequential read mode") then
slv2mst <= BUS_SLV2MST_IDLE;
address := (others => '0');
writeData := (others => '0');
readData := (others => '0');
writeMask := (others => '0');
deppMode := (others => '0');
deppMode(depp_mode_fast_read_bit) := '1';
deppAddr := std_logic_vector(to_unsigned(depp2bus_mode_register_start, deppAddr'length));
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
-- Enable sequential read mode
depp_tb_depp_write_to_address(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
addr => deppAddr,
data => deppMode
);
-- Set the start address
depp_tb_bus_set_address (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address
);
-- Set the depp address
deppAddr := std_logic_vector(to_unsigned(depp2bus_readData_reg_start, deppAddr'length));
depp_tb_depp_set_address (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
addr => deppAddr
);
-- Now start reading
for i in 0 to 20 loop
readData := std_logic_vector(to_unsigned(i, writeData'length));
address := std_logic_vector(to_unsigned(i*depp2bus_readData_reg_len, address'length));
depp_tb_depp_get_data(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
data => readData_out(7 downto 0),
expect_completion => false
);
wait until mst2slv.readEnable = '1';
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '1');
check_equal(depp_wait, '0');
slv2mst.readData <= readData;
slv2mst.ack <= '1';
depp_tb_bus_finish_read_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
data => readData_out(7 downto 0)
);
slv2mst.ack <= '0';
for j in 1 to depp2bus_readData_reg_len - 1 loop
depp_tb_depp_get_data(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
data => readData_out((j+1)*8 - 1 downto j*8),
expect_completion => true
);
end loop;
check_equal(readData, readData_out);
end loop;
end if;
end loop;
wait until rising_edge(clk) or falling_edge(clk);
test_runner_cleanup(runner);
wait;
end process;
test_runner_watchdog(runner, 10 ms);
controller : entity src.depp_slave_controller
port map (
rst => rst,
clk => clk,
mst2slv => mst2slv,
slv2mst => slv2mst,
USB_DB => depp_db,
USB_WRITE => depp_write,
USB_ASTB => depp_astb,
USB_DSTB => depp_dstb,
USB_WAIT => depp_wait
);
end tb;
| mit |
LucasMahieu/TP_secu | code/bench/test_core_glob.vhd | 1 | 4047 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_aes;
use lib_aes.all;
------------------------------------------------------------------------
-- This test bench is configured with two different data sets (selectable with
-- <seltest>). Each test can be run in encryption or decryption flow.
-- Then check the signals at the output of the instantiated core.
------------------------------------------------------------------------
-- Component Declaration
entity test_core is
end test_core;
--constant C_ERROR_SIGNAL_WIDTH : integer := 2;
-- Architecture of the Component
architecture a_tb of test_core is
constant RESET_ACTIVE : std_logic := '0';
constant CLK_HT : time := 16 ns;
constant ROUND_NUMBER : integer := 8;
signal go_enc : std_logic := '0';
signal go_dec : std_logic := '1';
component aes_core is port (
data_inH : in std_logic_vector( 127 downto 0 );
input_key : in std_logic_vector( 127 downto 0 );
go_cipher, go_key, enc_command : in std_logic;
data_outH : out std_logic_vector( 127 downto 0 );
data_out_ok : out std_logic;
ready_out : out std_logic;
error : out std_logic_vector( 0 downto 0 );
rst, ck : in std_logic;
fault_aes_port : in std_logic_vector( 7 downto 0)
);
end component;
signal datain : std_logic_vector( 127 downto 0 );
signal data, edata, edata1, edata2, ddata, ddata1, ddata2, kdata1, kdata2 : std_logic_vector( 127 downto 0 );
signal input_key : std_logic_vector(127 downto 0);
signal s_broken: std_logic_vector( 0 downto 0 ); -- Verify that it is C_ERROR_SIGNAL_WIDTH bit wide!
signal seltest : integer;
signal rst, ck, s_ready, s_d_ok : std_logic;
signal dout : std_logic_vector (127 downto 0);
signal s_go_crypt, s_go_key, s_command : std_logic;
-- fault attack
signal fault_sig : std_logic_vector( 7 downto 0 );
begin
-- CHANGE THE TWO LINES BELOW ACCORDING TO THE TEST YOU WANT TO EXECUTE
-- AND WHETHER YOU NEED TO TEST ENCRYPTION OR DECRYPTION:
seltest <= 2; -- 1 for "test 1" or anything else for "test 2"
s_command <= go_dec; -- "go_enc" or "go_dec"
-- Reset and clock generation:
rst <= not( RESET_ACTIVE ), RESET_ACTIVE after 50*CLK_HT, not( RESET_ACTIVE ) after 52*CLK_HT;
clk_pr : process
begin
ck <= '1';
loop
wait for CLK_HT;
ck <= not ck;
end loop;
end process;
fault : process(ck) is
variable cycle_count : natural := 7 + ROUND_NUMBER * 6;
begin
if ck'event and ck = '1' then
cycle_count := cycle_count + 1;
if s_go_crypt = '1' then
cycle_count := 0;
end if;
if cycle_count > 0 + ROUND_NUMBER * 6 and cycle_count < 7 + ROUND_NUMBER * 6 then
fault_sig <= "11111111";
else
fault_sig <= "00000000";
end if;
end if;
end process fault;
-- Input definition
edata1 <= X"3243f6a8885a308d313198a2e0370734"; edata2 <= X"00112233445566778899aabbccddeeff";
kdata1 <= X"2b7e151628aed2a6abf7158809cf4f3c"; kdata2 <= X"000102030405060708090a0b0c0d0e0f";
ddata1 <= X"3925841d02dc09fbdc118597196a0b32"; ddata2 <= X"69c4e0d86a7b0430d8cdb78070b4c55a";
input_key <= kdata1 when ( seltest=1 ) else kdata2;
edata <= edata1 when ( seltest=1 ) else edata2;
ddata <= ddata1 when ( seltest=1 ) else ddata2;
data <= edata when ( s_command=go_enc ) else ddata;
datain <= ( others=>'0' ), data after 128*CLK_HT,
( others=>'0' ) after 130*CLK_HT, data after 280*CLK_HT,
( others=>'0' ) after 282*CLK_HT;
s_go_crypt <= '0', '1' after 128*CLK_HT, '0' after 130*CLK_HT,
'1' after 280*CLK_HT, '0' after 282*CLK_HT;
s_go_key <= '0', '1' after 58*CLK_HT, '0' after 60*CLK_HT;
UUT : aes_core port map(
data_inH => datain,
input_key => input_key,
go_cipher => s_go_crypt,
go_key => s_go_key,
enc_command => s_command,
data_outH => dout,
data_out_ok => s_d_ok,
ready_out => s_ready,
error => s_broken,
rst => rst,
ck => ck,
fault_aes_port => fault_sig
);
end a_tb;
| mit |
LucasMahieu/TP_secu | code/AES/vhd/MixColumn0.vhd | 2 | 1657 |
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity mixcolumn0 is port (
in_0, in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
ctrl_dec : in T_ENCDEC;
b_out : out std_logic_vector (7 downto 0) ) ;
end mixcolumn0;
architecture a_mixcolumn0 of mixcolumn0 is
component xtime port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end component;
component x2time port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end component;
component x4time port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end component;
signal a, b, c, d, e, f, g, h, i, out_1, out_2 : std_logic_vector (7 downto 0);
begin
a <= in_0( 7 downto 0 ) xor in_1( 7 downto 0 );
c <= in_2( 7 downto 0 ) xor in_3( 7 downto 0 );
b <= c xor in_1( 7 downto 0 );
e <= in_0( 7 downto 0 ) xor in_2( 7 downto 0 );
f <= a xor c;
xt : xtime port map (a, d);
out_1 <= b xor d;
gen000e : if ( not C_INCLUDE_DECODING_LOGIC ) generate
b_out( 7 downto 0 ) <= out_1;
end generate;
gen000d : if ( C_INCLUDE_DECODING_LOGIC ) generate
x2t : x2time port map (e, g);
x4t : x4time port map (f, h);
i <= g xor h;
out_2 <= out_1 xor i; -- x4time(f) XOR x2time(e) XOR xtime(a) XOR b
b_out( 7 downto 0 ) <= out_1 when (ctrl_dec = C_ENC) else out_2; -- out_1 when encryptin, else out_2 when decrypting
end generate;
end a_mixcolumn0;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/reports/Gray_Binarization/Gray_Binarization_example.vhd | 1 | 2480 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Binarization_example is
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end entity;
architecture rtl of Gray_Binarization_example is
component Gray_Binarization
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end component;
begin
Gray_Binarization_instance :
component Gray_Binarization
port map(
Avalon_ST_Sink_data => Avalon_ST_Sink_data,
Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket,
Avalon_MM_Slave_address => Avalon_MM_Slave_address,
Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata,
Avalon_ST_Source_valid => Avalon_ST_Source_valid,
Avalon_ST_Sink_valid => Avalon_ST_Sink_valid,
Clock => Clock,
Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket,
Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket,
Avalon_MM_Slave_write => Avalon_MM_Slave_write,
aclr => aclr,
Avalon_ST_Source_ready => Avalon_ST_Source_ready,
Avalon_ST_Sink_ready => Avalon_ST_Sink_ready,
Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket,
Avalon_ST_Source_data => Avalon_ST_Source_data);
end architecture rtl;
| mit |
Nic30/hwtLib | hwtLib/examples/SimpleComentedUnit.vhd | 1 | 444 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- This is comment for SimpleComentedUnit entity, it will be rendered before entity as comment.
-- Do not forget that class inheritance does apply for docstring as well.
--
ENTITY SimpleComentedUnit IS
PORT(
a : IN STD_LOGIC;
b : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleComentedUnit IS
BEGIN
b <= a;
END ARCHITECTURE;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/altera_lnsim/common_28nm_mlab_cell_pulse_generator/_primary.vhd | 5 | 322 | library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator;
| mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_cast_GNLF52SJQ3.vhd | 4 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLF52SJQ3 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLF52SJQ3 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 8,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_cast_GNJGR7GQ2L.vhd | 8 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(17 downto 0);
output : out std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNJGR7GQ2L is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 18 + 1 ,
width_inr=> 0,
width_outl=> 8,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(17 downto 0) => input,
xin(18) => '0', yout => output
);
end architecture; | mit |
VladisM/MARK_II | VHDL/src/cpu/id.vhd | 1 | 47743 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity id is
port(
clk: in std_logic;
res: in std_logic;
instr_opcode: in std_logic_vector(7 downto 0);
flag: in std_logic;
ack: in std_logic;
int: in std_logic;
swirq: out std_logic;
we: out std_logic;
oe: out std_logic;
int_accept: out std_logic;
int_completed: out std_logic;
data_c_sel: out std_logic_vector(2 downto 0);
data_a_sel: out std_logic_vector(3 downto 0);
data_b_sel: out std_logic_vector(2 downto 0);
force_we_reg_14: out std_logic;
inc_r14: out std_logic;
inc_r15: out std_logic;
dec_r15: out std_logic;
instruction_we: out std_logic;
regfile_c_we: out std_logic
);
end entity id;
architecture id_arch of id is
type id_state_type is (
start, start_inc, start_inc_intcmp, start_dec, start_wait, start_decode, start_calli, start_call,
intrq, intrq_set, intrq_inc, intrq_inc_set, intrq_dec, intrq_dec_set, intrq_calli, intrq_call,
ret, reti, swi,
call, calli,
pop, push,
ld, ldi, st, sti,
bz_bnz_set, bzi_bnzi_set,
mvil, mvih, mvia, barrel, alu,
cmp,
div, div_w0, div_w1, div_w2, div_w3, div_w4, div_w5, div_w6, div_w7,
div_w8, div_w9, div_w10, div_w11, div_w12, div_w13, div_w14, div_done,
faddsub, faddsub_done,
fdiv, fdiv_w0, fdiv_w1, fdiv_w2, fdiv_w3, fdiv_w4, fdiv_w5, fdiv_w6, fdiv_done,
fmul, fmul_w0, fmul_done
);
signal id_state: id_state_type;
constant data_a_arg_mvia: std_logic_vector(3 downto 0) := "0000";
constant data_a_arg_branch: std_logic_vector(3 downto 0) := "0001";
constant data_a_arg_st: std_logic_vector(3 downto 0) := "0010";
constant data_a_arg_mvi: std_logic_vector(3 downto 0) := "0011";
constant data_a_int_addr: std_logic_vector(3 downto 0) := "0100";
constant data_a_pc: std_logic_vector(3 downto 0) := "0101";
constant data_a_sp: std_logic_vector(3 downto 0) := "0110";
constant data_a_sp_plus: std_logic_vector(3 downto 0) := "0111";
constant data_a_sp_minus: std_logic_vector(3 downto 0) := "1000";
constant data_a_regfile: std_logic_vector(3 downto 0) := "1001";
constant data_b_regfile: std_logic_vector(2 downto 0) := "000";
constant data_b_regfile_a: std_logic_vector(2 downto 0) := "001";
constant data_b_pc: std_logic_vector(2 downto 0) := "010";
constant data_b_arg_call: std_logic_vector(2 downto 0) := "011";
constant data_b_reg0: std_logic_vector(2 downto 0) := "100";
constant data_c_fpu: std_logic_vector(2 downto 0) := "000";
constant data_c_cmp: std_logic_vector(2 downto 0) := "001";
constant data_c_alu: std_logic_vector(2 downto 0) := "010";
constant data_c_barrel: std_logic_vector(2 downto 0) := "011";
constant data_c_miso: std_logic_vector(2 downto 0) := "100";
constant data_c_mvil: std_logic_vector(2 downto 0) := "101";
constant data_c_mvih: std_logic_vector(2 downto 0) := "110";
constant data_c_aorb: std_logic_vector(2 downto 0) := "111";
constant data_a_dontcare: std_logic_vector(3 downto 0) := "----";
constant data_b_dontcare: std_logic_vector(2 downto 0) := "---";
constant data_c_dontcare: std_logic_vector(2 downto 0) := "---";
begin
decoder: process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
id_state <= start;
else
case id_state is
when start =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_inc =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_calli =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_call =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_inc_intcmp =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_dec =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_wait =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_decode =>
case instr_opcode(7) is
when '1' =>
case instr_opcode(6 downto 4) is
when "000" => id_state <= call;
when "001" => id_state <= ld;
when "010" => id_state <= st;
when "011" =>
case flag is
when '1' => id_state <= bz_bnz_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "100" =>
case flag is
when '0' => id_state <= bz_bnz_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "101" => id_state <= mvia;
when others => id_state <= start;
end case;
when others =>
case instr_opcode(4 downto 0) is
when "00001" => id_state <= ret;
when "00010" => id_state <= reti;
when "00011" => id_state <= calli;
when "00100" => id_state <= push;
when "00101" => id_state <= pop;
when "00110" => id_state <= ldi;
when "00111" => id_state <= sti;
when "01000" =>
case flag is
when '0' => id_state <= bzi_bnzi_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "01001" =>
case flag is
when '1' => id_state <= bzi_bnzi_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "01010" => id_state <= cmp;
when "01011" => id_state <= cmp;
when "01100" => id_state <= alu;
when "01101" => id_state <= div;
when "01110" => id_state <= barrel;
when "01111" => id_state <= faddsub;
when "10000" => id_state <= fmul;
when "10001" => id_state <= fdiv;
when "10010" => id_state <= mvil;
when "10011" => id_state <= mvih;
when "10100" => id_state <= swi;
when others => id_state <= start;
end case;
end case;
when intrq =>
case ack is
when '1' => id_state <= intrq_set;
when others => id_state <= intrq;
end case;
when intrq_set =>
id_state <= start;
when intrq_calli =>
case ack is
when '1' => id_state <= intrq_set;
when others => id_state <= intrq_calli;
end case;
when intrq_call =>
case ack is
when '1' => id_state <= intrq_set;
when others => id_state <= intrq_call;
end case;
when intrq_inc =>
case ack is
when '1' => id_state <= intrq_inc_set;
when others => id_state <= intrq_inc;
end case;
when intrq_inc_set =>
id_state <= start_inc;
when intrq_dec =>
case ack is
when '1' => id_state <= intrq_dec_set;
when others => id_state <= intrq_dec;
end case;
when intrq_dec_set =>
id_state <= start;
when ret =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_inc;
when others => id_state <= start_inc;
end case;
when others => id_state <= ret;
end case;
when reti =>
case ack is
when '1' => id_state <= start_inc_intcmp;
when others => id_state <= reti;
end case;
when call =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_call;
when others => id_state <= start_call;
end case;
when others => id_state <= call;
end case;
when calli =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_calli;
when others => id_state <= start_calli;
end case;
when others => id_state <= calli;
end case;
when pop =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_inc;
when others => id_state <= start_inc;
end case;
when others => id_state <= pop;
end case;
when push =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_dec;
when others => id_state <= start_dec;
end case;
when others => id_state <= push;
end case;
when ld =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= ld;
end case;
when ldi =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= ldi;
end case;
when st =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= st;
end case;
when sti =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= sti;
end case;
when bz_bnz_set =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when bzi_bnzi_set =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when mvil =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when mvih =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when mvia =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when barrel =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when alu =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when cmp =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when div => id_state <= div_w0;
when div_w0 => id_state <= div_w1;
when div_w1 => id_state <= div_w2;
when div_w2 => id_state <= div_w3;
when div_w3 => id_state <= div_w4;
when div_w4 => id_state <= div_w5;
when div_w5 => id_state <= div_w6;
when div_w6 => id_state <= div_w7;
when div_w7 => id_state <= div_w8;
when div_w8 => id_state <= div_w9;
when div_w9 => id_state <= div_w10;
when div_w10 => id_state <= div_w11;
when div_w11 => id_state <= div_w12;
when div_w12 => id_state <= div_w13;
when div_w13 => id_state <= div_w14;
when div_w14 => id_state <= div_done;
when div_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when faddsub => id_state <= faddsub_done;
when faddsub_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when fmul => id_state <= fmul_w0;
when fmul_w0 => id_state <= fmul_done;
when fmul_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when fdiv => id_state <= fdiv_w0;
when fdiv_w0 => id_state <= fdiv_w1;
when fdiv_w1 => id_state <= fdiv_w2;
when fdiv_w2 => id_state <= fdiv_w3;
when fdiv_w3 => id_state <= fdiv_w4;
when fdiv_w4 => id_state <= fdiv_w5;
when fdiv_w5 => id_state <= fdiv_w6;
when fdiv_w6 => id_state <= fdiv_done;
when fdiv_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when swi =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
end if;
end if;
end process;
outputs: process(id_state) is begin
case id_state is
when start =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_inc =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '1'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_inc_intcmp =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '1';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '1'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_dec =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_wait =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_decode =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '1'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_dontcare;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_calli =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when start_call =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_arg_mvia;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when ret =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '0';
when reti =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '0';
when call =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when calli =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when pop =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '1';
when push =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when ld =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvia;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '1';
when ldi =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '1';
when st =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_st;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when sti =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when bz_bnz_set =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_branch;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when bzi_bnzi_set =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when mvil =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvi;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_mvil;
regfile_c_we <= '1';
when mvih =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvi;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_mvih;
regfile_c_we <= '1';
when mvia =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvia;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '1';
when barrel =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_barrel;
regfile_c_we <= '1';
when alu =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '1';
when cmp =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_cmp;
regfile_c_we <= '1';
when div =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w0 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w1 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w2 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w3 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w4 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w5 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w6 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w7 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w8 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w9 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w10 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w11 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w12 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w13 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w14 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '1';
when faddsub =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when faddsub_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '1';
when fdiv =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w0 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w1 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w2 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w3 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w4 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w5 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w6 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '1';
when fmul =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fmul_w0 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fmul_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '1';
when intrq =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_set =>
we <= '0'; oe <= '0'; int_accept <= '1'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_int_addr;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when intrq_inc =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_inc_set =>
we <= '0'; oe <= '0'; int_accept <= '1'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_int_addr;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when intrq_dec =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_minus;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_dec_set =>
we <= '0'; oe <= '0'; int_accept <= '1'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_int_addr;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when intrq_call =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_arg_call;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_calli =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_regfile_a;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when swi =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '1'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_dontcare;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
end case;
end process;
end architecture id_arch;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_bus_concat_GNIIOZRPJD.vhd | 12 | 653 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic ( widthB : natural := 8;
widthA : natural := 8);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNIIOZRPJD is
Begin
output <= a & b;
end architecture; | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_testbench_salt_GN7Z4SHGOK.vhd | 17 | 1749 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/Gray_Binarization.vhd | 2 | 2769 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Gray_Binarization;
architecture rtl of Gray_Binarization is
component Gray_Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Gray_Binarization_GN;
begin
Gray_Binarization_GN_0: if true generate
inst_Gray_Binarization_GN_0: Gray_Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
| mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_multiplexer_GNCALBUTDR.vhd | 12 | 1253 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNCALBUTDR is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 24;
pipeline : natural := 0;
number_inputs : natural := 2);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(0 downto 0);
result : out std_logic_vector(23 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(23 downto 0);
in1 : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GNCALBUTDR is
signal data_muxin : std_logic_vector(47 downto 0);
Begin
data_muxin <= in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 2,
lpm_widths => 1 ,
lpm_width => 24 ,
SelOneHot => 0 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_decoder_GNM4LOIHXZ.vhd | 14 | 901 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNM4LOIHXZ is
generic ( decode : string := "01";
pipeline : natural := 1;
width : natural := 2);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNM4LOIHXZ is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 2,
decode => "01",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_sMultAltr.vhd | 12 | 3026 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library LPM;
use LPM.LPM_COMPONENTS.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sMultAltr is
generic (
lpm_widtha : positive ;
lpm_widthb : positive ;
lpm_representation : string ;
lpm_hint : string ;
OutputMsb : natural ;
OutputLsb : natural ;
pipeline : natural
);
port (
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
datab : in std_logic_vector(lpm_widthb-1 downto 0);
result : out std_logic_vector(OutputMsb-OutputLsb downto 0)
);
end alt_dspbuilder_sMultAltr;
architecture synth of alt_dspbuilder_sMultAltr is
signal FullPrecisionResult : std_logic_vector(lpm_widtha+lpm_widthb-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gcomb: if pipeline=0 generate
U0 : lpm_mult
GENERIC MAP (
lpm_widtha => lpm_widtha,
lpm_widthb => lpm_widthb,
lpm_widthp => lpm_widtha+lpm_widthb,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => lpm_representation,
lpm_hint => lpm_hint
)
PORT MAP (
dataa => dataa,
datab => datab,
result => FullPrecisionResult
);
end generate gcomb;
greg: if pipeline>0 generate
U0 : lpm_mult
GENERIC MAP (
lpm_widtha => lpm_widtha,
lpm_widthb => lpm_widthb,
lpm_widthp => lpm_widtha+lpm_widthb,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => lpm_representation,
lpm_hint => lpm_hint,
lpm_pipeline => pipeline
)
PORT MAP (
dataa => dataa,
datab => datab,
clken=> ena,
aclr => aclr_i,
clock => clock,
result => FullPrecisionResult);
end generate greg;
g:for i in OutputLsb to OutputMsb generate
result(i-OutputLsb) <= FullPrecisionResult(i);
end generate g;
end synth;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_multiplexer.vhd | 10 | 658 | -- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
| mit |
VladisM/MARK_II | VHDL/src/cpu/qip/fp_cmp_lt/fp_cmp_lt.vhd | 1 | 5883 | -- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_cmp_lt.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_cmp_lt is
port (
clk : in std_logic := '0'; -- clk.clk
areset : in std_logic := '0'; -- areset.reset
a : in std_logic_vector(31 downto 0) := (others => '0'); -- a.a
b : in std_logic_vector(31 downto 0) := (others => '0'); -- b.b
q : out std_logic_vector(0 downto 0) -- q.q
);
end entity fp_cmp_lt;
architecture rtl of fp_cmp_lt is
component fp_cmp_lt_0002 is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(0 downto 0) -- q
);
end component fp_cmp_lt_0002;
begin
fp_cmp_lt_inst : component fp_cmp_lt_0002
port map (
clk => clk, -- clk.clk
areset => areset, -- areset.reset
a => a, -- a.a
b => b, -- b.b
q => q -- q.q
);
end architecture rtl; -- of fp_cmp_lt
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_fp_functions" version="17.0" >
-- Retrieval info: <generic name="FUNCTION_FAMILY" value="COMPARE" />
-- Retrieval info: <generic name="ARITH_function" value="ADD" />
-- Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
-- Retrieval info: <generic name="ALL_function" value="ADD" />
-- Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
-- Retrieval info: <generic name="TRIG_function" value="SIN" />
-- Retrieval info: <generic name="COMPARE_function" value="LT" />
-- Retrieval info: <generic name="ROOTS_function" value="SQRT" />
-- Retrieval info: <generic name="fp_format" value="single" />
-- Retrieval info: <generic name="fp_exp" value="8" />
-- Retrieval info: <generic name="fp_man" value="23" />
-- Retrieval info: <generic name="exponent_width" value="23" />
-- Retrieval info: <generic name="frequency_target" value="25" />
-- Retrieval info: <generic name="latency_target" value="2" />
-- Retrieval info: <generic name="performance_goal" value="frequency" />
-- Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
-- Retrieval info: <generic name="faithful_rounding" value="false" />
-- Retrieval info: <generic name="gen_enable" value="false" />
-- Retrieval info: <generic name="divide_type" value="0" />
-- Retrieval info: <generic name="select_signal_enable" value="false" />
-- Retrieval info: <generic name="scale_by_pi" value="false" />
-- Retrieval info: <generic name="number_of_inputs" value="2" />
-- Retrieval info: <generic name="trig_no_range_reduction" value="false" />
-- Retrieval info: <generic name="report_resources_to_xml" value="false" />
-- Retrieval info: <generic name="fxpt_width" value="32" />
-- Retrieval info: <generic name="fxpt_fraction" value="0" />
-- Retrieval info: <generic name="fxpt_sign" value="1" />
-- Retrieval info: <generic name="fp_out_format" value="single" />
-- Retrieval info: <generic name="fp_out_exp" value="8" />
-- Retrieval info: <generic name="fp_out_man" value="23" />
-- Retrieval info: <generic name="fp_in_format" value="single" />
-- Retrieval info: <generic name="fp_in_exp" value="8" />
-- Retrieval info: <generic name="fp_in_man" value="23" />
-- Retrieval info: <generic name="enable_hard_fp" value="true" />
-- Retrieval info: <generic name="manual_dsp_planning" value="true" />
-- Retrieval info: <generic name="forceRegisters" value="1111" />
-- Retrieval info: <generic name="selected_device_family" value="MAX 10" />
-- Retrieval info: <generic name="selected_device_speedgrade" value="6" />
-- Retrieval info: </instance>
-- IPFS_FILES : fp_cmp_lt.vho
-- RELATED_FILES: fp_cmp_lt.vhd, dspba_library_package.vhd, dspba_library.vhd, fp_cmp_lt_0002.vhd
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_port_GNOC3SGKQJ.vhd | 20 | 489 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNOC3SGKQJ is
Begin
-- Straight Bypass block
output <= input;
end architecture; | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_port_GN37ALZBS4.vhd | 20 | 449 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_port_GN37ALZBS4 is
Begin
-- Straight Bypass block
output <= input;
end architecture; | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/altera_lnsim/altera_mult_add_rtl/_primary.vhd | 5 | 43770 | library verilog;
use verilog.vl_types.all;
entity altera_mult_add_rtl is
generic(
extra_latency : integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
selected_device_family: string := "Stratix V";
lpm_type : string := "altera_mult_add";
lpm_hint : string := "UNUSED";
width_a : integer := 1;
input_register_a0: string := "UNREGISTERED";
input_aclr_a0 : string := "NONE";
input_source_a0 : string := "DATAA";
input_register_a1: string := "UNREGISTERED";
input_aclr_a1 : string := "NONE";
input_source_a1 : string := "DATAA";
input_register_a2: string := "UNREGISTERED";
input_aclr_a2 : string := "NONE";
input_source_a2 : string := "DATAA";
input_register_a3: string := "UNREGISTERED";
input_aclr_a3 : string := "NONE";
input_source_a3 : string := "DATAA";
input_a0_latency_clock: string := "UNREGISTERED";
input_a0_latency_aclr: string := "NONE";
input_a1_latency_clock: string := "UNREGISTERED";
input_a1_latency_aclr: string := "NONE";
input_a2_latency_clock: string := "UNREGISTERED";
input_a2_latency_aclr: string := "NONE";
input_a3_latency_clock: string := "UNREGISTERED";
input_a3_latency_aclr: string := "NONE";
width_b : integer := 1;
input_register_b0: string := "UNREGISTERED";
input_aclr_b0 : string := "NONE";
input_source_b0 : string := "DATAB";
input_register_b1: string := "UNREGISTERED";
input_aclr_b1 : string := "NONE";
input_source_b1 : string := "DATAB";
input_register_b2: string := "UNREGISTERED";
input_aclr_b2 : string := "NONE";
input_source_b2 : string := "DATAB";
input_register_b3: string := "UNREGISTERED";
input_aclr_b3 : string := "NONE";
input_source_b3 : string := "DATAB";
input_b0_latency_clock: string := "UNREGISTERED";
input_b0_latency_aclr: string := "NONE";
input_b1_latency_clock: string := "UNREGISTERED";
input_b1_latency_aclr: string := "NONE";
input_b2_latency_clock: string := "UNREGISTERED";
input_b2_latency_aclr: string := "NONE";
input_b3_latency_clock: string := "UNREGISTERED";
input_b3_latency_aclr: string := "NONE";
width_c : integer := 1;
input_register_c0: string := "UNREGISTERED";
input_aclr_c0 : string := "NONE";
input_register_c1: string := "UNREGISTERED";
input_aclr_c1 : string := "NONE";
input_register_c2: string := "UNREGISTERED";
input_aclr_c2 : string := "NONE";
input_register_c3: string := "UNREGISTERED";
input_aclr_c3 : string := "NONE";
input_c0_latency_clock: string := "UNREGISTERED";
input_c0_latency_aclr: string := "NONE";
input_c1_latency_clock: string := "UNREGISTERED";
input_c1_latency_aclr: string := "NONE";
input_c2_latency_clock: string := "UNREGISTERED";
input_c2_latency_aclr: string := "NONE";
input_c3_latency_clock: string := "UNREGISTERED";
input_c3_latency_aclr: string := "NONE";
width_result : integer := 34;
output_register : string := "UNREGISTERED";
output_aclr : string := "NONE";
port_signa : string := "PORT_UNUSED";
representation_a: string := "UNSIGNED";
signed_register_a: string := "UNREGISTERED";
signed_aclr_a : string := "NONE";
signed_latency_clock_a: string := "UNREGISTERED";
signed_latency_aclr_a: string := "NONE";
port_signb : string := "PORT_UNUSED";
representation_b: string := "UNSIGNED";
signed_register_b: string := "UNREGISTERED";
signed_aclr_b : string := "NONE";
signed_latency_clock_b: string := "UNREGISTERED";
signed_latency_aclr_b: string := "NONE";
number_of_multipliers: integer := 1;
multiplier1_direction: string := "NONE";
multiplier3_direction: string := "NONE";
multiplier_register0: string := "UNREGISTERED";
multiplier_aclr0: string := "NONE";
multiplier_register1: string := "UNREGISTERED";
multiplier_aclr1: string := "NONE";
multiplier_register2: string := "UNREGISTERED";
multiplier_aclr2: string := "NONE";
multiplier_register3: string := "UNREGISTERED";
multiplier_aclr3: string := "NONE";
port_addnsub1 : string := "PORT_UNUSED";
addnsub_multiplier_register1: string := "UNREGISTERED";
addnsub_multiplier_aclr1: string := "NONE";
addnsub_multiplier_latency_clock1: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr1: string := "NONE";
port_addnsub3 : string := "PORT_UNUSED";
addnsub_multiplier_register3: string := "UNREGISTERED";
addnsub_multiplier_aclr3: string := "NONE";
addnsub_multiplier_latency_clock3: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr3: string := "NONE";
adder1_rounding : string := "NO";
addnsub1_round_register: string := "UNREGISTERED";
addnsub1_round_aclr: string := "NONE";
adder3_rounding : string := "NO";
addnsub3_round_register: string := "UNREGISTERED";
addnsub3_round_aclr: string := "NONE";
multiplier01_rounding: string := "NO";
mult01_round_register: string := "UNREGISTERED";
mult01_round_aclr: string := "NONE";
multiplier23_rounding: string := "NO";
mult23_round_register: string := "UNREGISTERED";
mult23_round_aclr: string := "NONE";
width_msb : integer := 17;
output_rounding : string := "NO";
output_round_type: string := "NEAREST_INTEGER";
output_round_register: string := "UNREGISTERED";
output_round_aclr: string := "NONE";
chainout_rounding: string := "NO";
chainout_round_register: string := "UNREGISTERED";
chainout_round_aclr: string := "NONE";
chainout_round_output_register: string := "UNREGISTERED";
chainout_round_output_aclr: string := "NONE";
multiplier01_saturation: string := "NO";
mult01_saturation_register: string := "UNREGISTERED";
mult01_saturation_aclr: string := "NONE";
multiplier23_saturation: string := "NO";
mult23_saturation_register: string := "UNREGISTERED";
mult23_saturation_aclr: string := "NONE";
port_mult0_is_saturated: string := "NONE";
port_mult1_is_saturated: string := "NONE";
port_mult2_is_saturated: string := "NONE";
port_mult3_is_saturated: string := "NONE";
width_saturate_sign: integer := 1;
output_saturation: string := "NO";
port_output_is_overflow: string := "PORT_UNUSED";
output_saturate_type: string := "ASYMMETRIC";
output_saturate_register: string := "UNREGISTERED";
output_saturate_aclr: string := "NONE";
chainout_saturation: string := "NO";
port_chainout_sat_is_overflow: string := "PORT_UNUSED";
chainout_saturate_register: string := "UNREGISTERED";
chainout_saturate_aclr: string := "NONE";
chainout_saturate_output_register: string := "UNREGISTERED";
chainout_saturate_output_aclr: string := "NONE";
scanouta_register: string := "UNREGISTERED";
scanouta_aclr : string := "NONE";
width_chainin : integer := 1;
chainout_adder : string := "NO";
chainout_register: string := "UNREGISTERED";
chainout_aclr : string := "NONE";
zero_chainout_output_register: string := "UNREGISTERED";
zero_chainout_output_aclr: string := "NONE";
shift_mode : string := "NO";
rotate_register : string := "UNREGISTERED";
rotate_aclr : string := "NONE";
rotate_output_register: string := "UNREGISTERED";
rotate_output_aclr: string := "NONE";
shift_right_register: string := "UNREGISTERED";
shift_right_aclr: string := "NONE";
shift_right_output_register: string := "UNREGISTERED";
shift_right_output_aclr: string := "NONE";
zero_loopback_register: string := "UNREGISTERED";
zero_loopback_aclr: string := "NONE";
zero_loopback_output_register: string := "UNREGISTERED";
zero_loopback_output_aclr: string := "NONE";
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
use_sload_accum_port: string := "NO";
accum_sload_register: string := "UNREGISTERED";
accum_sload_aclr: string := "NONE";
accum_sload_latency_clock: string := "UNREGISTERED";
accum_sload_latency_aclr: string := "NONE";
loadconst_control_register: string := "UNREGISTERED";
loadconst_control_aclr: string := "NONE";
double_accum : string := "NO";
systolic_delay1 : string := "UNREGISTERED";
systolic_delay3 : string := "UNREGISTERED";
systolic_aclr1 : string := "NONE";
systolic_aclr3 : string := "NONE";
preadder_mode : string := "SIMPLE";
preadder_direction_0: string := "ADD";
preadder_direction_1: string := "ADD";
preadder_direction_2: string := "ADD";
preadder_direction_3: string := "ADD";
width_coef : integer := 1;
coefsel0_register: string := "UNREGISTERED";
coefsel0_aclr : string := "NONE";
coefsel1_register: string := "UNREGISTERED";
coefsel1_aclr : string := "NONE";
coefsel2_register: string := "UNREGISTERED";
coefsel2_aclr : string := "NONE";
coefsel3_register: string := "UNREGISTERED";
coefsel3_aclr : string := "NONE";
coef0_0 : integer := 0;
coef0_1 : integer := 0;
coef0_2 : integer := 0;
coef0_3 : integer := 0;
coef0_4 : integer := 0;
coef0_5 : integer := 0;
coef0_6 : integer := 0;
coef0_7 : integer := 0;
coef1_0 : integer := 0;
coef1_1 : integer := 0;
coef1_2 : integer := 0;
coef1_3 : integer := 0;
coef1_4 : integer := 0;
coef1_5 : integer := 0;
coef1_6 : integer := 0;
coef1_7 : integer := 0;
coef2_0 : integer := 0;
coef2_1 : integer := 0;
coef2_2 : integer := 0;
coef2_3 : integer := 0;
coef2_4 : integer := 0;
coef2_5 : integer := 0;
coef2_6 : integer := 0;
coef2_7 : integer := 0;
coef3_0 : integer := 0;
coef3_1 : integer := 0;
coef3_2 : integer := 0;
coef3_3 : integer := 0;
coef3_4 : integer := 0;
coef3_5 : integer := 0;
coef3_6 : integer := 0;
coef3_7 : integer := 0;
coefsel0_latency_clock: string := "UNREGISTERED";
coefsel0_latency_aclr: string := "NONE";
coefsel1_latency_clock: string := "UNREGISTERED";
coefsel1_latency_aclr: string := "NONE";
coefsel2_latency_clock: string := "UNREGISTERED";
coefsel2_latency_aclr: string := "NONE";
coefsel3_latency_clock: string := "UNREGISTERED";
coefsel3_latency_aclr: string := "NONE";
latency : integer := 0;
signed_pipeline_register_a: string := "UNREGISTERED";
signed_pipeline_aclr_a: string := "NONE";
signed_pipeline_register_b: string := "UNREGISTERED";
signed_pipeline_aclr_b: string := "NONE";
addnsub_multiplier_pipeline_register1: string := "UNREGISTERED";
addnsub_multiplier_pipeline_aclr1: string := "NONE";
addnsub_multiplier_pipeline_register3: string := "UNREGISTERED";
addnsub_multiplier_pipeline_aclr3: string := "NONE";
addnsub1_round_pipeline_register: string := "UNREGISTERED";
addnsub1_round_pipeline_aclr: string := "NONE";
addnsub3_round_pipeline_register: string := "UNREGISTERED";
addnsub3_round_pipeline_aclr: string := "NONE";
output_round_pipeline_register: string := "UNREGISTERED";
output_round_pipeline_aclr: string := "NONE";
chainout_round_pipeline_register: string := "UNREGISTERED";
chainout_round_pipeline_aclr: string := "NONE";
output_saturate_pipeline_register: string := "UNREGISTERED";
output_saturate_pipeline_aclr: string := "NONE";
chainout_saturate_pipeline_register: string := "UNREGISTERED";
chainout_saturate_pipeline_aclr: string := "NONE";
rotate_pipeline_register: string := "UNREGISTERED";
rotate_pipeline_aclr: string := "NONE";
shift_right_pipeline_register: string := "UNREGISTERED";
shift_right_pipeline_aclr: string := "NONE";
zero_loopback_pipeline_register: string := "UNREGISTERED";
zero_loopback_pipeline_aclr: string := "NONE";
accum_sload_pipeline_register: string := "UNREGISTERED";
accum_sload_pipeline_aclr: string := "NONE";
width_clock_all_wire_msb: integer := 3;
width_aclr_all_wire_msb: integer := 3;
width_ena_all_wire_msb: integer := 3;
width_a_total_msb: vl_notype;
width_a_msb : vl_notype;
width_b_total_msb: vl_notype;
width_b_msb : vl_notype;
width_c_total_msb: vl_notype;
width_c_msb : vl_notype;
width_scanina : vl_notype;
width_scanina_msb: vl_notype;
width_scaninb : vl_notype;
width_scaninb_msb: vl_notype;
width_sourcea_msb: vl_notype;
width_sourceb_msb: vl_notype;
width_scanouta_msb: vl_notype;
width_scanoutb_msb: vl_notype;
width_chainin_msb: vl_notype;
width_result_msb: vl_notype;
width_coef_msb : vl_notype;
dataa_split_ext_require: vl_notype;
dataa_port_sign : vl_notype;
width_a_ext : vl_notype;
width_a_ext_msb : vl_notype;
datab_split_ext_require: vl_notype;
datab_port_sign : vl_notype;
width_b_ext : vl_notype;
width_b_ext_msb : vl_notype;
coef_ext_require: vl_notype;
coef_port_sign : vl_notype;
width_coef_ext : vl_notype;
width_coef_ext_msb: vl_notype;
datac_split_ext_require: vl_notype;
datac_port_sign : vl_notype;
width_c_ext : vl_notype;
width_c_ext_msb : vl_notype;
width_scanchain : vl_notype;
width_scanchain_msb: vl_notype;
scanchain_port_sign: vl_notype;
preadder_representation: vl_notype;
width_preadder_input_a: vl_notype;
width_preadder_input_a_msb: vl_notype;
width_preadder_adder_result: vl_notype;
width_preadder_output_a: vl_notype;
width_preadder_output_a_msb: vl_notype;
width_preadder_output_b: vl_notype;
width_preadder_output_b_msb: vl_notype;
multiplier_input_representation_a: vl_notype;
multiplier_input_representation_b: vl_notype;
width_mult_source_a: vl_notype;
width_mult_source_a_msb: vl_notype;
width_mult_source_b: vl_notype;
width_mult_source_b_msb: vl_notype;
width_mult_result: vl_notype;
width_mult_result_msb: vl_notype;
width_adder_source: vl_notype;
width_adder_source_msb: vl_notype;
width_adder_result: vl_notype;
width_adder_result_msb: vl_notype;
width_chainin_ext: vl_notype;
width_original_result: vl_notype;
width_original_result_msb: vl_notype;
result_ext_width: vl_notype;
width_result_output: vl_notype;
width_result_output_msb: vl_notype;
width_chainout_adder_output: vl_notype
);
port(
dataa : in vl_logic_vector;
datab : in vl_logic_vector;
datac : in vl_logic_vector;
scanina : in vl_logic_vector;
scaninb : in vl_logic_vector;
sourcea : in vl_logic_vector;
sourceb : in vl_logic_vector;
clock3 : in vl_logic;
clock2 : in vl_logic;
clock1 : in vl_logic;
clock0 : in vl_logic;
aclr3 : in vl_logic;
aclr2 : in vl_logic;
aclr1 : in vl_logic;
aclr0 : in vl_logic;
ena3 : in vl_logic;
ena2 : in vl_logic;
ena1 : in vl_logic;
ena0 : in vl_logic;
signa : in vl_logic;
signb : in vl_logic;
addnsub1 : in vl_logic;
addnsub3 : in vl_logic;
result : out vl_logic_vector;
scanouta : out vl_logic_vector;
scanoutb : out vl_logic_vector;
mult01_round : in vl_logic;
mult23_round : in vl_logic;
mult01_saturation: in vl_logic;
mult23_saturation: in vl_logic;
addnsub1_round : in vl_logic;
addnsub3_round : in vl_logic;
mult0_is_saturated: out vl_logic;
mult1_is_saturated: out vl_logic;
mult2_is_saturated: out vl_logic;
mult3_is_saturated: out vl_logic;
output_round : in vl_logic;
chainout_round : in vl_logic;
output_saturate : in vl_logic;
chainout_saturate: in vl_logic;
overflow : out vl_logic;
chainout_sat_overflow: out vl_logic;
chainin : in vl_logic_vector;
zero_chainout : in vl_logic;
rotate : in vl_logic;
shift_right : in vl_logic;
zero_loopback : in vl_logic;
accum_sload : in vl_logic;
sload_accum : in vl_logic;
coefsel0 : in vl_logic_vector(2 downto 0);
coefsel1 : in vl_logic_vector(2 downto 0);
coefsel2 : in vl_logic_vector(2 downto 0);
coefsel3 : in vl_logic_vector(2 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of extra_latency : constant is 1;
attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1;
attribute mti_svvh_generic_type of dsp_block_balancing : constant is 1;
attribute mti_svvh_generic_type of selected_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of width_a : constant is 1;
attribute mti_svvh_generic_type of input_register_a0 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a0 : constant is 1;
attribute mti_svvh_generic_type of input_source_a0 : constant is 1;
attribute mti_svvh_generic_type of input_register_a1 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a1 : constant is 1;
attribute mti_svvh_generic_type of input_source_a1 : constant is 1;
attribute mti_svvh_generic_type of input_register_a2 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a2 : constant is 1;
attribute mti_svvh_generic_type of input_source_a2 : constant is 1;
attribute mti_svvh_generic_type of input_register_a3 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a3 : constant is 1;
attribute mti_svvh_generic_type of input_source_a3 : constant is 1;
attribute mti_svvh_generic_type of input_a0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_a1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_a2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_a3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_b : constant is 1;
attribute mti_svvh_generic_type of input_register_b0 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b0 : constant is 1;
attribute mti_svvh_generic_type of input_source_b0 : constant is 1;
attribute mti_svvh_generic_type of input_register_b1 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b1 : constant is 1;
attribute mti_svvh_generic_type of input_source_b1 : constant is 1;
attribute mti_svvh_generic_type of input_register_b2 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b2 : constant is 1;
attribute mti_svvh_generic_type of input_source_b2 : constant is 1;
attribute mti_svvh_generic_type of input_register_b3 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b3 : constant is 1;
attribute mti_svvh_generic_type of input_source_b3 : constant is 1;
attribute mti_svvh_generic_type of input_b0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_b1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_b2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_b3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_c : constant is 1;
attribute mti_svvh_generic_type of input_register_c0 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c0 : constant is 1;
attribute mti_svvh_generic_type of input_register_c1 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c1 : constant is 1;
attribute mti_svvh_generic_type of input_register_c2 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c2 : constant is 1;
attribute mti_svvh_generic_type of input_register_c3 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c3 : constant is 1;
attribute mti_svvh_generic_type of input_c0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_c1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_c2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_c3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_result : constant is 1;
attribute mti_svvh_generic_type of output_register : constant is 1;
attribute mti_svvh_generic_type of output_aclr : constant is 1;
attribute mti_svvh_generic_type of port_signa : constant is 1;
attribute mti_svvh_generic_type of representation_a : constant is 1;
attribute mti_svvh_generic_type of signed_register_a : constant is 1;
attribute mti_svvh_generic_type of signed_aclr_a : constant is 1;
attribute mti_svvh_generic_type of signed_latency_clock_a : constant is 1;
attribute mti_svvh_generic_type of signed_latency_aclr_a : constant is 1;
attribute mti_svvh_generic_type of port_signb : constant is 1;
attribute mti_svvh_generic_type of representation_b : constant is 1;
attribute mti_svvh_generic_type of signed_register_b : constant is 1;
attribute mti_svvh_generic_type of signed_aclr_b : constant is 1;
attribute mti_svvh_generic_type of signed_latency_clock_b : constant is 1;
attribute mti_svvh_generic_type of signed_latency_aclr_b : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of multiplier1_direction : constant is 1;
attribute mti_svvh_generic_type of multiplier3_direction : constant is 1;
attribute mti_svvh_generic_type of multiplier_register0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of port_addnsub1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr1 : constant is 1;
attribute mti_svvh_generic_type of port_addnsub3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr3 : constant is 1;
attribute mti_svvh_generic_type of adder1_rounding : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_register : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_aclr : constant is 1;
attribute mti_svvh_generic_type of adder3_rounding : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_register : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier01_rounding : constant is 1;
attribute mti_svvh_generic_type of mult01_round_register : constant is 1;
attribute mti_svvh_generic_type of mult01_round_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier23_rounding : constant is 1;
attribute mti_svvh_generic_type of mult23_round_register : constant is 1;
attribute mti_svvh_generic_type of mult23_round_aclr : constant is 1;
attribute mti_svvh_generic_type of width_msb : constant is 1;
attribute mti_svvh_generic_type of output_rounding : constant is 1;
attribute mti_svvh_generic_type of output_round_type : constant is 1;
attribute mti_svvh_generic_type of output_round_register : constant is 1;
attribute mti_svvh_generic_type of output_round_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_rounding : constant is 1;
attribute mti_svvh_generic_type of chainout_round_register : constant is 1;
attribute mti_svvh_generic_type of chainout_round_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_round_output_register : constant is 1;
attribute mti_svvh_generic_type of chainout_round_output_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier01_saturation : constant is 1;
attribute mti_svvh_generic_type of mult01_saturation_register : constant is 1;
attribute mti_svvh_generic_type of mult01_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier23_saturation : constant is 1;
attribute mti_svvh_generic_type of mult23_saturation_register : constant is 1;
attribute mti_svvh_generic_type of mult23_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of port_mult0_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_mult1_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_mult2_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_mult3_is_saturated : constant is 1;
attribute mti_svvh_generic_type of width_saturate_sign : constant is 1;
attribute mti_svvh_generic_type of output_saturation : constant is 1;
attribute mti_svvh_generic_type of port_output_is_overflow : constant is 1;
attribute mti_svvh_generic_type of output_saturate_type : constant is 1;
attribute mti_svvh_generic_type of output_saturate_register : constant is 1;
attribute mti_svvh_generic_type of output_saturate_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_saturation : constant is 1;
attribute mti_svvh_generic_type of port_chainout_sat_is_overflow : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_register : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_output_register : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_output_aclr : constant is 1;
attribute mti_svvh_generic_type of scanouta_register : constant is 1;
attribute mti_svvh_generic_type of scanouta_aclr : constant is 1;
attribute mti_svvh_generic_type of width_chainin : constant is 1;
attribute mti_svvh_generic_type of chainout_adder : constant is 1;
attribute mti_svvh_generic_type of chainout_register : constant is 1;
attribute mti_svvh_generic_type of chainout_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_chainout_output_register : constant is 1;
attribute mti_svvh_generic_type of zero_chainout_output_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_mode : constant is 1;
attribute mti_svvh_generic_type of rotate_register : constant is 1;
attribute mti_svvh_generic_type of rotate_aclr : constant is 1;
attribute mti_svvh_generic_type of rotate_output_register : constant is 1;
attribute mti_svvh_generic_type of rotate_output_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_right_register : constant is 1;
attribute mti_svvh_generic_type of shift_right_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_right_output_register : constant is 1;
attribute mti_svvh_generic_type of shift_right_output_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_register : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_output_register : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_output_aclr : constant is 1;
attribute mti_svvh_generic_type of accumulator : constant is 1;
attribute mti_svvh_generic_type of accum_direction : constant is 1;
attribute mti_svvh_generic_type of loadconst_value : constant is 1;
attribute mti_svvh_generic_type of use_sload_accum_port : constant is 1;
attribute mti_svvh_generic_type of accum_sload_register : constant is 1;
attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_clock : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_register : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_aclr : constant is 1;
attribute mti_svvh_generic_type of double_accum : constant is 1;
attribute mti_svvh_generic_type of systolic_delay1 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay3 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1;
attribute mti_svvh_generic_type of preadder_mode : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1;
attribute mti_svvh_generic_type of width_coef : constant is 1;
attribute mti_svvh_generic_type of coefsel0_register : constant is 1;
attribute mti_svvh_generic_type of coefsel0_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel1_register : constant is 1;
attribute mti_svvh_generic_type of coefsel1_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel2_register : constant is 1;
attribute mti_svvh_generic_type of coefsel2_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel3_register : constant is 1;
attribute mti_svvh_generic_type of coefsel3_aclr : constant is 1;
attribute mti_svvh_generic_type of coef0_0 : constant is 1;
attribute mti_svvh_generic_type of coef0_1 : constant is 1;
attribute mti_svvh_generic_type of coef0_2 : constant is 1;
attribute mti_svvh_generic_type of coef0_3 : constant is 1;
attribute mti_svvh_generic_type of coef0_4 : constant is 1;
attribute mti_svvh_generic_type of coef0_5 : constant is 1;
attribute mti_svvh_generic_type of coef0_6 : constant is 1;
attribute mti_svvh_generic_type of coef0_7 : constant is 1;
attribute mti_svvh_generic_type of coef1_0 : constant is 1;
attribute mti_svvh_generic_type of coef1_1 : constant is 1;
attribute mti_svvh_generic_type of coef1_2 : constant is 1;
attribute mti_svvh_generic_type of coef1_3 : constant is 1;
attribute mti_svvh_generic_type of coef1_4 : constant is 1;
attribute mti_svvh_generic_type of coef1_5 : constant is 1;
attribute mti_svvh_generic_type of coef1_6 : constant is 1;
attribute mti_svvh_generic_type of coef1_7 : constant is 1;
attribute mti_svvh_generic_type of coef2_0 : constant is 1;
attribute mti_svvh_generic_type of coef2_1 : constant is 1;
attribute mti_svvh_generic_type of coef2_2 : constant is 1;
attribute mti_svvh_generic_type of coef2_3 : constant is 1;
attribute mti_svvh_generic_type of coef2_4 : constant is 1;
attribute mti_svvh_generic_type of coef2_5 : constant is 1;
attribute mti_svvh_generic_type of coef2_6 : constant is 1;
attribute mti_svvh_generic_type of coef2_7 : constant is 1;
attribute mti_svvh_generic_type of coef3_0 : constant is 1;
attribute mti_svvh_generic_type of coef3_1 : constant is 1;
attribute mti_svvh_generic_type of coef3_2 : constant is 1;
attribute mti_svvh_generic_type of coef3_3 : constant is 1;
attribute mti_svvh_generic_type of coef3_4 : constant is 1;
attribute mti_svvh_generic_type of coef3_5 : constant is 1;
attribute mti_svvh_generic_type of coef3_6 : constant is 1;
attribute mti_svvh_generic_type of coef3_7 : constant is 1;
attribute mti_svvh_generic_type of coefsel0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_register_a : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_aclr_a : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_register_b : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_aclr_b : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr3 : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of output_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of output_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of chainout_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of output_saturate_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of output_saturate_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of rotate_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of rotate_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_right_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of shift_right_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of width_clock_all_wire_msb : constant is 1;
attribute mti_svvh_generic_type of width_aclr_all_wire_msb : constant is 1;
attribute mti_svvh_generic_type of width_ena_all_wire_msb : constant is 1;
attribute mti_svvh_generic_type of width_a_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_b_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_c_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_c_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanina : constant is 3;
attribute mti_svvh_generic_type of width_scanina_msb : constant is 3;
attribute mti_svvh_generic_type of width_scaninb : constant is 3;
attribute mti_svvh_generic_type of width_scaninb_msb : constant is 3;
attribute mti_svvh_generic_type of width_sourcea_msb : constant is 3;
attribute mti_svvh_generic_type of width_sourceb_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanouta_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanoutb_msb : constant is 3;
attribute mti_svvh_generic_type of width_chainin_msb : constant is 3;
attribute mti_svvh_generic_type of width_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_coef_msb : constant is 3;
attribute mti_svvh_generic_type of dataa_split_ext_require : constant is 3;
attribute mti_svvh_generic_type of dataa_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_a_ext : constant is 3;
attribute mti_svvh_generic_type of width_a_ext_msb : constant is 3;
attribute mti_svvh_generic_type of datab_split_ext_require : constant is 3;
attribute mti_svvh_generic_type of datab_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_b_ext : constant is 3;
attribute mti_svvh_generic_type of width_b_ext_msb : constant is 3;
attribute mti_svvh_generic_type of coef_ext_require : constant is 3;
attribute mti_svvh_generic_type of coef_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_coef_ext : constant is 3;
attribute mti_svvh_generic_type of width_coef_ext_msb : constant is 3;
attribute mti_svvh_generic_type of datac_split_ext_require : constant is 3;
attribute mti_svvh_generic_type of datac_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_c_ext : constant is 3;
attribute mti_svvh_generic_type of width_c_ext_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanchain : constant is 3;
attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3;
attribute mti_svvh_generic_type of scanchain_port_sign : constant is 3;
attribute mti_svvh_generic_type of preadder_representation : constant is 3;
attribute mti_svvh_generic_type of width_preadder_input_a : constant is 3;
attribute mti_svvh_generic_type of width_preadder_input_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_a : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_b : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_b_msb : constant is 3;
attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 3;
attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_a : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_result : constant is 3;
attribute mti_svvh_generic_type of width_mult_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_adder_source : constant is 3;
attribute mti_svvh_generic_type of width_adder_source_msb : constant is 3;
attribute mti_svvh_generic_type of width_adder_result : constant is 3;
attribute mti_svvh_generic_type of width_adder_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_chainin_ext : constant is 3;
attribute mti_svvh_generic_type of width_original_result : constant is 3;
attribute mti_svvh_generic_type of width_original_result_msb : constant is 3;
attribute mti_svvh_generic_type of result_ext_width : constant is 3;
attribute mti_svvh_generic_type of width_result_output : constant is 3;
attribute mti_svvh_generic_type of width_result_output_msb : constant is 3;
attribute mti_svvh_generic_type of width_chainout_adder_output : constant is 3;
end altera_mult_add_rtl;
| mit |
Nic30/hwtLib | hwtLib/tests/serialization/TmpVarSignCast.vhd | 1 | 1093 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TmpVarSignCast IS
PORT(
a : IN STD_LOGIC;
b : IN UNSIGNED(0 DOWNTO 0);
c : OUT UNSIGNED(0 DOWNTO 0);
d : OUT UNSIGNED(0 DOWNTO 0);
e : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
i : IN STD_LOGIC;
o : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF TmpVarSignCast IS
BEGIN
assig_process_c: PROCESS(a, b)
VARIABLE tmp_std_logic2vector_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmp_std_logic2vector_0(0) := a;
c <= UNSIGNED(tmp_std_logic2vector_0) + b;
END PROCESS;
assig_process_d: PROCESS(a, b)
VARIABLE tmp_std_logic2vector_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmp_std_logic2vector_0(0) := a;
d <= b + UNSIGNED(tmp_std_logic2vector_0);
END PROCESS;
assig_process_o: PROCESS(e, i)
VARIABLE tmp1bToUnsigned_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmp1bToUnsigned_0(0) := i;
o <= e(TO_INTEGER(UNSIGNED(tmp1bToUnsigned_0)));
END PROCESS;
END ARCHITECTURE;
| mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module.vhd | 2 | 9927 | -- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
thr : in std_logic_vector(7 downto 0) := (others => '0') -- thr.wire
);
end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module;
architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_multiplexer_GNCALBUTDR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNCALBUTDR;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNA5S4SQDN is
port (
input : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_port_GNA5S4SQDN;
component alt_dspbuilder_if_statement_GNYT6HZJI5 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(7 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNYT6HZJI5;
component alt_dspbuilder_constant_GNLMV7GZFA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLMV7GZFA;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_cast_GNKXX25S2S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKXX25S2S;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> Bus_Conversion:input
signal bus_conversion_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion:output -> If_Statement:a
signal thr_0_output_wire : std_logic_vector(7 downto 0); -- thr_0:output -> If_Statement:b
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Multiplexer1:in0
signal constant2_output_wire : std_logic_vector(23 downto 0); -- Constant2:output -> Multiplexer1:in1
signal multiplexer1_result_wire : std_logic_vector(23 downto 0); -- Multiplexer1:result -> data_out_0:input
signal if_statement_true_wire : std_logic; -- If_Statement:true -> cast0:input
signal cast0_output_wire : std_logic_vector(0 downto 0); -- cast0:output -> Multiplexer1:sel
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Multiplexer1:aclr
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Multiplexer1:clock
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => cast0_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => constant1_output_wire, -- in0.wire
in1 => constant2_output_wire -- in1.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
thr_0 : component alt_dspbuilder_port_GNA5S4SQDN
port map (
input => thr, -- input.wire
output => thr_0_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNYT6HZJI5
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 8
)
port map (
true => if_statement_true_wire, -- true.wire
a => bus_conversion_output_wire, -- a.wire
b => thr_0_output_wire -- b.wire
);
constant2 : component alt_dspbuilder_constant_GNLMV7GZFA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "111111111111111111111111",
width => 24
)
port map (
output => constant2_output_wire -- output.wire
);
constant1 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
bus_conversion : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer1_result_wire, -- input.wire
output => data_out -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => if_statement_true_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module
| mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_cast_GN7IAAYCSZ.vhd | 8 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN7IAAYCSZ is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN7IAAYCSZ is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 8 + 1 ,
width_inr=> 16,
width_outl=> 8,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_decoder.vhd | 7 | 1660 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_testbench_capture.vhd | 10 | 676 | -- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
| mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_BarrelShiftAltr.vhd | 8 | 7592 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/altera_lnsim/altera_arriav_pll/_primary.vhd | 5 | 70296 | library verilog;
use verilog.vl_types.all;
entity altera_arriav_pll is
generic(
number_of_counters: integer := 18;
number_of_fplls : integer := 1;
number_of_extclks: integer := 4;
number_of_dlls : integer := 2;
number_of_lvds : integer := 4;
pll_auto_clk_sw_en_0: string := "false";
pll_clk_loss_edge_0: string := "both_edges";
pll_clk_loss_sw_en_0: string := "false";
pll_clk_sw_dly_0: integer := 0;
pll_clkin_0_src_0: string := "clk_0";
pll_clkin_1_src_0: string := "clk_0";
pll_manu_clk_sw_en_0: string := "false";
pll_sw_refclk_src_0: string := "clk_0";
pll_auto_clk_sw_en_1: string := "false";
pll_clk_loss_edge_1: string := "both_edges";
pll_clk_loss_sw_en_1: string := "false";
pll_clk_sw_dly_1: integer := 0;
pll_clkin_0_src_1: string := "clk_1";
pll_clkin_1_src_1: string := "clk_1";
pll_manu_clk_sw_en_1: string := "false";
pll_sw_refclk_src_1: string := "clk_1";
pll_output_clock_frequency_0: string := "700.0 MHz";
reference_clock_frequency_0: string := "700.0 MHz";
mimic_fbclk_type_0: string := "gclk";
dsm_accumulator_reset_value_0: integer := 0;
forcelock_0 : string := "false";
nreset_invert_0 : string := "false";
pll_atb_0 : integer := 0;
pll_bwctrl_0 : integer := 1000;
pll_cmp_buf_dly_0: string := "0 ps";
pll_cp_comp_0 : string := "true";
pll_cp_current_0: integer := 20;
pll_ctrl_override_setting_0: string := "true";
pll_dsm_dither_0: string := "disable";
pll_dsm_out_sel_0: string := "disable";
pll_dsm_reset_0 : string := "false";
pll_ecn_bypass_0: string := "false";
pll_ecn_test_en_0: string := "false";
pll_enable_0 : string := "true";
pll_fbclk_mux_1_0: string := "fb";
pll_fbclk_mux_2_0: string := "m_cnt";
pll_fractional_carry_out_0: integer := 24;
pll_fractional_division_0: integer := 1;
pll_fractional_value_ready_0: string := "true";
pll_lf_testen_0 : string := "false";
pll_lock_fltr_cfg_0: integer := 25;
pll_lock_fltr_test_0: string := "false";
pll_m_cnt_bypass_en_0: string := "false";
pll_m_cnt_coarse_dly_0: string := "0 ps";
pll_m_cnt_fine_dly_0: string := "0 ps";
pll_m_cnt_hi_div_0: integer := 3;
pll_m_cnt_in_src_0: string := "ph_mux_clk";
pll_m_cnt_lo_div_0: integer := 3;
pll_m_cnt_odd_div_duty_en_0: string := "false";
pll_m_cnt_ph_mux_prst_0: integer := 0;
pll_m_cnt_prst_0: integer := 256;
pll_n_cnt_bypass_en_0: string := "true";
pll_n_cnt_coarse_dly_0: string := "0 ps";
pll_n_cnt_fine_dly_0: string := "0 ps";
pll_n_cnt_hi_div_0: integer := 1;
pll_n_cnt_lo_div_0: integer := 1;
pll_n_cnt_odd_div_duty_en_0: string := "false";
pll_ref_buf_dly_0: string := "0 ps";
pll_reg_boost_0 : integer := 0;
pll_regulator_bypass_0: string := "false";
pll_ripplecap_ctrl_0: integer := 0;
pll_slf_rst_0 : string := "false";
pll_tclk_mux_en_0: string := "false";
pll_tclk_sel_0 : string := "n_src";
pll_test_enable_0: string := "false";
pll_testdn_enable_0: string := "false";
pll_testup_enable_0: string := "false";
pll_unlock_fltr_cfg_0: integer := 1;
pll_vco_div_0 : integer := 0;
pll_vco_ph0_en_0: string := "true";
pll_vco_ph1_en_0: string := "true";
pll_vco_ph2_en_0: string := "true";
pll_vco_ph3_en_0: string := "true";
pll_vco_ph4_en_0: string := "true";
pll_vco_ph5_en_0: string := "true";
pll_vco_ph6_en_0: string := "true";
pll_vco_ph7_en_0: string := "true";
pll_vctrl_test_voltage_0: integer := 750;
vccd0g_atb_0 : string := "disable";
vccd0g_output_0 : integer := 0;
vccd1g_atb_0 : string := "disable";
vccd1g_output_0 : integer := 0;
vccm1g_tap_0 : integer := 2;
vccr_pd_0 : string := "false";
vcodiv_override_0: string := "false";
sim_use_fast_model_0: string := "false";
pll_output_clock_frequency_1: string := "300.0 MHz";
reference_clock_frequency_1: string := "100.0 MHz";
mimic_fbclk_type_1: string := "gclk";
dsm_accumulator_reset_value_1: integer := 0;
forcelock_1 : string := "false";
nreset_invert_1 : string := "false";
pll_atb_1 : integer := 0;
pll_bwctrl_1 : integer := 1000;
pll_cmp_buf_dly_1: string := "0 ps";
pll_cp_comp_1 : string := "true";
pll_cp_current_1: integer := 30;
pll_ctrl_override_setting_1: string := "false";
pll_dsm_dither_1: string := "disable";
pll_dsm_out_sel_1: string := "disable";
pll_dsm_reset_1 : string := "false";
pll_ecn_bypass_1: string := "false";
pll_ecn_test_en_1: string := "false";
pll_enable_1 : string := "false";
pll_fbclk_mux_1_1: string := "glb";
pll_fbclk_mux_2_1: string := "fb_1";
pll_fractional_carry_out_1: integer := 24;
pll_fractional_division_1: integer := 1;
pll_fractional_value_ready_1: string := "true";
pll_lf_testen_1 : string := "false";
pll_lock_fltr_cfg_1: integer := 25;
pll_lock_fltr_test_1: string := "false";
pll_m_cnt_bypass_en_1: string := "false";
pll_m_cnt_coarse_dly_1: string := "0 ps";
pll_m_cnt_fine_dly_1: string := "0 ps";
pll_m_cnt_hi_div_1: integer := 2;
pll_m_cnt_in_src_1: string := "ph_mux_clk";
pll_m_cnt_lo_div_1: integer := 1;
pll_m_cnt_odd_div_duty_en_1: string := "true";
pll_m_cnt_ph_mux_prst_1: integer := 0;
pll_m_cnt_prst_1: integer := 256;
pll_n_cnt_bypass_en_1: string := "true";
pll_n_cnt_coarse_dly_1: string := "0 ps";
pll_n_cnt_fine_dly_1: string := "0 ps";
pll_n_cnt_hi_div_1: integer := 256;
pll_n_cnt_lo_div_1: integer := 256;
pll_n_cnt_odd_div_duty_en_1: string := "false";
pll_ref_buf_dly_1: string := "0 ps";
pll_reg_boost_1 : integer := 0;
pll_regulator_bypass_1: string := "false";
pll_ripplecap_ctrl_1: integer := 0;
pll_slf_rst_1 : string := "false";
pll_tclk_mux_en_1: string := "false";
pll_tclk_sel_1 : string := "n_src";
pll_test_enable_1: string := "false";
pll_testdn_enable_1: string := "false";
pll_testup_enable_1: string := "false";
pll_unlock_fltr_cfg_1: integer := 2;
pll_vco_div_1 : integer := 1;
pll_vco_ph0_en_1: string := "true";
pll_vco_ph1_en_1: string := "true";
pll_vco_ph2_en_1: string := "true";
pll_vco_ph3_en_1: string := "true";
pll_vco_ph4_en_1: string := "true";
pll_vco_ph5_en_1: string := "true";
pll_vco_ph6_en_1: string := "true";
pll_vco_ph7_en_1: string := "true";
pll_vctrl_test_voltage_1: integer := 750;
vccd0g_atb_1 : string := "disable";
vccd0g_output_1 : integer := 0;
vccd1g_atb_1 : string := "disable";
vccd1g_output_1 : integer := 0;
vccm1g_tap_1 : integer := 2;
vccr_pd_1 : string := "false";
vcodiv_override_1: string := "false";
sim_use_fast_model_1: string := "false";
output_clock_frequency_0: string := "100.0 MHz";
enable_output_counter_0: string := "true";
phase_shift_0 : string := "0 ps";
duty_cycle_0 : integer := 50;
c_cnt_coarse_dly_0: string := "0 ps";
c_cnt_fine_dly_0: string := "0 ps";
c_cnt_in_src_0 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_0: integer := 0;
c_cnt_prst_0 : integer := 1;
cnt_fpll_src_0 : string := "fpll_0";
dprio0_cnt_bypass_en_0: string := "true";
dprio0_cnt_hi_div_0: integer := 3;
dprio0_cnt_lo_div_0: integer := 3;
dprio0_cnt_odd_div_even_duty_en_0: string := "false";
dprio1_cnt_bypass_en_0: vl_notype;
dprio1_cnt_hi_div_0: vl_notype;
dprio1_cnt_lo_div_0: vl_notype;
dprio1_cnt_odd_div_even_duty_en_0: vl_notype;
output_clock_frequency_1: string := "0 ps";
enable_output_counter_1: string := "true";
phase_shift_1 : string := "0 ps";
duty_cycle_1 : integer := 50;
c_cnt_coarse_dly_1: string := "0 ps";
c_cnt_fine_dly_1: string := "0 ps";
c_cnt_in_src_1 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_1: integer := 0;
c_cnt_prst_1 : integer := 1;
cnt_fpll_src_1 : string := "fpll_0";
dprio0_cnt_bypass_en_1: string := "true";
dprio0_cnt_hi_div_1: integer := 2;
dprio0_cnt_lo_div_1: integer := 1;
dprio0_cnt_odd_div_even_duty_en_1: string := "true";
dprio1_cnt_bypass_en_1: vl_notype;
dprio1_cnt_hi_div_1: vl_notype;
dprio1_cnt_lo_div_1: vl_notype;
dprio1_cnt_odd_div_even_duty_en_1: vl_notype;
output_clock_frequency_2: string := "0 ps";
enable_output_counter_2: string := "true";
phase_shift_2 : string := "0 ps";
duty_cycle_2 : integer := 50;
c_cnt_coarse_dly_2: string := "0 ps";
c_cnt_fine_dly_2: string := "0 ps";
c_cnt_in_src_2 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_2: integer := 0;
c_cnt_prst_2 : integer := 1;
cnt_fpll_src_2 : string := "fpll_0";
dprio0_cnt_bypass_en_2: string := "true";
dprio0_cnt_hi_div_2: integer := 1;
dprio0_cnt_lo_div_2: integer := 1;
dprio0_cnt_odd_div_even_duty_en_2: string := "false";
dprio1_cnt_bypass_en_2: vl_notype;
dprio1_cnt_hi_div_2: vl_notype;
dprio1_cnt_lo_div_2: vl_notype;
dprio1_cnt_odd_div_even_duty_en_2: vl_notype;
output_clock_frequency_3: string := "0 ps";
enable_output_counter_3: string := "true";
phase_shift_3 : string := "0 ps";
duty_cycle_3 : integer := 50;
c_cnt_coarse_dly_3: string := "0 ps";
c_cnt_fine_dly_3: string := "0 ps";
c_cnt_in_src_3 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_3: integer := 0;
c_cnt_prst_3 : integer := 1;
cnt_fpll_src_3 : string := "fpll_0";
dprio0_cnt_bypass_en_3: string := "false";
dprio0_cnt_hi_div_3: integer := 1;
dprio0_cnt_lo_div_3: integer := 1;
dprio0_cnt_odd_div_even_duty_en_3: string := "false";
dprio1_cnt_bypass_en_3: vl_notype;
dprio1_cnt_hi_div_3: vl_notype;
dprio1_cnt_lo_div_3: vl_notype;
dprio1_cnt_odd_div_even_duty_en_3: vl_notype;
output_clock_frequency_4: string := "0 ps";
enable_output_counter_4: string := "true";
phase_shift_4 : string := "0 ps";
duty_cycle_4 : integer := 50;
c_cnt_coarse_dly_4: string := "0 ps";
c_cnt_fine_dly_4: string := "0 ps";
c_cnt_in_src_4 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_4: integer := 0;
c_cnt_prst_4 : integer := 1;
cnt_fpll_src_4 : string := "fpll_0";
dprio0_cnt_bypass_en_4: string := "false";
dprio0_cnt_hi_div_4: integer := 1;
dprio0_cnt_lo_div_4: integer := 1;
dprio0_cnt_odd_div_even_duty_en_4: string := "false";
dprio1_cnt_bypass_en_4: vl_notype;
dprio1_cnt_hi_div_4: vl_notype;
dprio1_cnt_lo_div_4: vl_notype;
dprio1_cnt_odd_div_even_duty_en_4: vl_notype;
output_clock_frequency_5: string := "0 ps";
enable_output_counter_5: string := "true";
phase_shift_5 : string := "0 ps";
duty_cycle_5 : integer := 50;
c_cnt_coarse_dly_5: string := "0 ps";
c_cnt_fine_dly_5: string := "0 ps";
c_cnt_in_src_5 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_5: integer := 0;
c_cnt_prst_5 : integer := 1;
cnt_fpll_src_5 : string := "fpll_0";
dprio0_cnt_bypass_en_5: string := "false";
dprio0_cnt_hi_div_5: integer := 1;
dprio0_cnt_lo_div_5: integer := 1;
dprio0_cnt_odd_div_even_duty_en_5: string := "false";
dprio1_cnt_bypass_en_5: vl_notype;
dprio1_cnt_hi_div_5: vl_notype;
dprio1_cnt_lo_div_5: vl_notype;
dprio1_cnt_odd_div_even_duty_en_5: vl_notype;
output_clock_frequency_6: string := "0 ps";
enable_output_counter_6: string := "true";
phase_shift_6 : string := "0 ps";
duty_cycle_6 : integer := 50;
c_cnt_coarse_dly_6: string := "0 ps";
c_cnt_fine_dly_6: string := "0 ps";
c_cnt_in_src_6 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_6: integer := 0;
c_cnt_prst_6 : integer := 1;
cnt_fpll_src_6 : string := "fpll_0";
dprio0_cnt_bypass_en_6: string := "false";
dprio0_cnt_hi_div_6: integer := 1;
dprio0_cnt_lo_div_6: integer := 1;
dprio0_cnt_odd_div_even_duty_en_6: string := "false";
dprio1_cnt_bypass_en_6: vl_notype;
dprio1_cnt_hi_div_6: vl_notype;
dprio1_cnt_lo_div_6: vl_notype;
dprio1_cnt_odd_div_even_duty_en_6: vl_notype;
output_clock_frequency_7: string := "0 ps";
enable_output_counter_7: string := "true";
phase_shift_7 : string := "0 ps";
duty_cycle_7 : integer := 50;
c_cnt_coarse_dly_7: string := "0 ps";
c_cnt_fine_dly_7: string := "0 ps";
c_cnt_in_src_7 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_7: integer := 0;
c_cnt_prst_7 : integer := 1;
cnt_fpll_src_7 : string := "fpll_0";
dprio0_cnt_bypass_en_7: string := "false";
dprio0_cnt_hi_div_7: integer := 1;
dprio0_cnt_lo_div_7: integer := 1;
dprio0_cnt_odd_div_even_duty_en_7: string := "false";
dprio1_cnt_bypass_en_7: vl_notype;
dprio1_cnt_hi_div_7: vl_notype;
dprio1_cnt_lo_div_7: vl_notype;
dprio1_cnt_odd_div_even_duty_en_7: vl_notype;
output_clock_frequency_8: string := "0 ps";
enable_output_counter_8: string := "true";
phase_shift_8 : string := "0 ps";
duty_cycle_8 : integer := 50;
c_cnt_coarse_dly_8: string := "0 ps";
c_cnt_fine_dly_8: string := "0 ps";
c_cnt_in_src_8 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_8: integer := 0;
c_cnt_prst_8 : integer := 1;
cnt_fpll_src_8 : string := "fpll_0";
dprio0_cnt_bypass_en_8: string := "false";
dprio0_cnt_hi_div_8: integer := 1;
dprio0_cnt_lo_div_8: integer := 1;
dprio0_cnt_odd_div_even_duty_en_8: string := "false";
dprio1_cnt_bypass_en_8: vl_notype;
dprio1_cnt_hi_div_8: vl_notype;
dprio1_cnt_lo_div_8: vl_notype;
dprio1_cnt_odd_div_even_duty_en_8: vl_notype;
output_clock_frequency_9: string := "0 ps";
enable_output_counter_9: string := "true";
phase_shift_9 : string := "0 ps";
duty_cycle_9 : integer := 50;
c_cnt_coarse_dly_9: string := "0 ps";
c_cnt_fine_dly_9: string := "0 ps";
c_cnt_in_src_9 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_9: integer := 0;
c_cnt_prst_9 : integer := 1;
cnt_fpll_src_9 : string := "fpll_0";
dprio0_cnt_bypass_en_9: string := "false";
dprio0_cnt_hi_div_9: integer := 1;
dprio0_cnt_lo_div_9: integer := 1;
dprio0_cnt_odd_div_even_duty_en_9: string := "false";
dprio1_cnt_bypass_en_9: vl_notype;
dprio1_cnt_hi_div_9: vl_notype;
dprio1_cnt_lo_div_9: vl_notype;
dprio1_cnt_odd_div_even_duty_en_9: vl_notype;
output_clock_frequency_10: string := "0 ps";
enable_output_counter_10: string := "true";
phase_shift_10 : string := "0 ps";
duty_cycle_10 : integer := 50;
c_cnt_coarse_dly_10: string := "0 ps";
c_cnt_fine_dly_10: string := "0 ps";
c_cnt_in_src_10 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_10: integer := 0;
c_cnt_prst_10 : integer := 1;
cnt_fpll_src_10 : string := "fpll_0";
dprio0_cnt_bypass_en_10: string := "false";
dprio0_cnt_hi_div_10: integer := 1;
dprio0_cnt_lo_div_10: integer := 1;
dprio0_cnt_odd_div_even_duty_en_10: string := "false";
dprio1_cnt_bypass_en_10: vl_notype;
dprio1_cnt_hi_div_10: vl_notype;
dprio1_cnt_lo_div_10: vl_notype;
dprio1_cnt_odd_div_even_duty_en_10: vl_notype;
output_clock_frequency_11: string := "0 ps";
enable_output_counter_11: string := "true";
phase_shift_11 : string := "0 ps";
duty_cycle_11 : integer := 50;
c_cnt_coarse_dly_11: string := "0 ps";
c_cnt_fine_dly_11: string := "0 ps";
c_cnt_in_src_11 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_11: integer := 0;
c_cnt_prst_11 : integer := 1;
cnt_fpll_src_11 : string := "fpll_0";
dprio0_cnt_bypass_en_11: string := "false";
dprio0_cnt_hi_div_11: integer := 1;
dprio0_cnt_lo_div_11: integer := 1;
dprio0_cnt_odd_div_even_duty_en_11: string := "false";
dprio1_cnt_bypass_en_11: vl_notype;
dprio1_cnt_hi_div_11: vl_notype;
dprio1_cnt_lo_div_11: vl_notype;
dprio1_cnt_odd_div_even_duty_en_11: vl_notype;
output_clock_frequency_12: string := "0 ps";
enable_output_counter_12: string := "true";
phase_shift_12 : string := "0 ps";
duty_cycle_12 : integer := 50;
c_cnt_coarse_dly_12: string := "0 ps";
c_cnt_fine_dly_12: string := "0 ps";
c_cnt_in_src_12 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_12: integer := 0;
c_cnt_prst_12 : integer := 1;
cnt_fpll_src_12 : string := "fpll_0";
dprio0_cnt_bypass_en_12: string := "false";
dprio0_cnt_hi_div_12: integer := 1;
dprio0_cnt_lo_div_12: integer := 1;
dprio0_cnt_odd_div_even_duty_en_12: string := "false";
dprio1_cnt_bypass_en_12: vl_notype;
dprio1_cnt_hi_div_12: vl_notype;
dprio1_cnt_lo_div_12: vl_notype;
dprio1_cnt_odd_div_even_duty_en_12: vl_notype;
output_clock_frequency_13: string := "0 ps";
enable_output_counter_13: string := "true";
phase_shift_13 : string := "0 ps";
duty_cycle_13 : integer := 50;
c_cnt_coarse_dly_13: string := "0 ps";
c_cnt_fine_dly_13: string := "0 ps";
c_cnt_in_src_13 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_13: integer := 0;
c_cnt_prst_13 : integer := 1;
cnt_fpll_src_13 : string := "fpll_0";
dprio0_cnt_bypass_en_13: string := "false";
dprio0_cnt_hi_div_13: integer := 1;
dprio0_cnt_lo_div_13: integer := 1;
dprio0_cnt_odd_div_even_duty_en_13: string := "false";
dprio1_cnt_bypass_en_13: vl_notype;
dprio1_cnt_hi_div_13: vl_notype;
dprio1_cnt_lo_div_13: vl_notype;
dprio1_cnt_odd_div_even_duty_en_13: vl_notype;
output_clock_frequency_14: string := "0 ps";
enable_output_counter_14: string := "true";
phase_shift_14 : string := "0 ps";
duty_cycle_14 : integer := 50;
c_cnt_coarse_dly_14: string := "0 ps";
c_cnt_fine_dly_14: string := "0 ps";
c_cnt_in_src_14 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_14: integer := 0;
c_cnt_prst_14 : integer := 1;
cnt_fpll_src_14 : string := "fpll_0";
dprio0_cnt_bypass_en_14: string := "false";
dprio0_cnt_hi_div_14: integer := 1;
dprio0_cnt_lo_div_14: integer := 1;
dprio0_cnt_odd_div_even_duty_en_14: string := "false";
dprio1_cnt_bypass_en_14: vl_notype;
dprio1_cnt_hi_div_14: vl_notype;
dprio1_cnt_lo_div_14: vl_notype;
dprio1_cnt_odd_div_even_duty_en_14: vl_notype;
output_clock_frequency_15: string := "0 ps";
enable_output_counter_15: string := "true";
phase_shift_15 : string := "0 ps";
duty_cycle_15 : integer := 50;
c_cnt_coarse_dly_15: string := "0 ps";
c_cnt_fine_dly_15: string := "0 ps";
c_cnt_in_src_15 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_15: integer := 0;
c_cnt_prst_15 : integer := 1;
cnt_fpll_src_15 : string := "fpll_0";
dprio0_cnt_bypass_en_15: string := "false";
dprio0_cnt_hi_div_15: integer := 1;
dprio0_cnt_lo_div_15: integer := 1;
dprio0_cnt_odd_div_even_duty_en_15: string := "false";
dprio1_cnt_bypass_en_15: vl_notype;
dprio1_cnt_hi_div_15: vl_notype;
dprio1_cnt_lo_div_15: vl_notype;
dprio1_cnt_odd_div_even_duty_en_15: vl_notype;
output_clock_frequency_16: string := "0 ps";
enable_output_counter_16: string := "true";
phase_shift_16 : string := "0 ps";
duty_cycle_16 : integer := 50;
c_cnt_coarse_dly_16: string := "0 ps";
c_cnt_fine_dly_16: string := "0 ps";
c_cnt_in_src_16 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_16: integer := 0;
c_cnt_prst_16 : integer := 1;
cnt_fpll_src_16 : string := "fpll_0";
dprio0_cnt_bypass_en_16: string := "false";
dprio0_cnt_hi_div_16: integer := 1;
dprio0_cnt_lo_div_16: integer := 1;
dprio0_cnt_odd_div_even_duty_en_16: string := "false";
dprio1_cnt_bypass_en_16: vl_notype;
dprio1_cnt_hi_div_16: vl_notype;
dprio1_cnt_lo_div_16: vl_notype;
dprio1_cnt_odd_div_even_duty_en_16: vl_notype;
output_clock_frequency_17: string := "0 ps";
enable_output_counter_17: string := "true";
phase_shift_17 : string := "0 ps";
duty_cycle_17 : integer := 50;
c_cnt_coarse_dly_17: string := "0 ps";
c_cnt_fine_dly_17: string := "0 ps";
c_cnt_in_src_17 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_17: integer := 0;
c_cnt_prst_17 : integer := 1;
cnt_fpll_src_17 : string := "fpll_0";
dprio0_cnt_bypass_en_17: string := "false";
dprio0_cnt_hi_div_17: integer := 1;
dprio0_cnt_lo_div_17: integer := 1;
dprio0_cnt_odd_div_even_duty_en_17: string := "false";
dprio1_cnt_bypass_en_17: vl_notype;
dprio1_cnt_hi_div_17: vl_notype;
dprio1_cnt_lo_div_17: vl_notype;
dprio1_cnt_odd_div_even_duty_en_17: vl_notype;
dpa_output_clock_frequency_0: string := "0 ps";
pll_vcoph_div_0 : integer := 1;
dpa_output_clock_frequency_1: string := "0 ps";
pll_vcoph_div_1 : integer := 1;
enable_extclk_output_0: string := "false";
pll_extclk_cnt_src_0: string := "m0_cnt";
pll_extclk_enable_0: string := "true";
pll_extclk_invert_0: string := "false";
enable_extclk_output_1: string := "false";
pll_extclk_cnt_src_1: string := "vss";
pll_extclk_enable_1: string := "true";
pll_extclk_invert_1: string := "false";
enable_extclk_output_2: string := "false";
pll_extclk_cnt_src_2: string := "vss";
pll_extclk_enable_2: string := "true";
pll_extclk_invert_2: string := "false";
enable_extclk_output_3: string := "false";
pll_extclk_cnt_src_3: string := "vss";
pll_extclk_enable_3: string := "true";
pll_extclk_invert_3: string := "false";
enable_dll_output_0: string := "false";
pll_dll_src_value_0: string := "vss";
enable_dll_output_1: string := "false";
pll_dll_src_value_1: string := "vss";
enable_lvds_output_0: string := "false";
pll_loaden_coarse_dly_0: string := "0 ps";
pll_loaden_enable_disable_0: string := "true";
pll_loaden_fine_dly_0: string := "0 ps";
pll_lvdsclk_coarse_dly_0: string := "0 ps";
pll_lvdsclk_enable_disable_0: string := "true";
pll_lvdsclk_fine_dly_0: string := "0 ps";
enable_lvds_output_1: string := "false";
pll_loaden_coarse_dly_1: string := "0 ps";
pll_loaden_enable_disable_1: string := "true";
pll_loaden_fine_dly_1: string := "0 ps";
pll_lvdsclk_coarse_dly_1: string := "0 ps";
pll_lvdsclk_enable_disable_1: string := "true";
pll_lvdsclk_fine_dly_1: string := "0 ps";
enable_lvds_output_2: string := "false";
pll_loaden_coarse_dly_2: string := "0 ps";
pll_loaden_enable_disable_2: string := "true";
pll_loaden_fine_dly_2: string := "0 ps";
pll_lvdsclk_coarse_dly_2: string := "0 ps";
pll_lvdsclk_enable_disable_2: string := "true";
pll_lvdsclk_fine_dly_2: string := "0 ps";
enable_lvds_output_3: string := "false";
pll_loaden_coarse_dly_3: string := "0 ps";
pll_loaden_enable_disable_3: string := "true";
pll_loaden_fine_dly_3: string := "0 ps";
pll_lvdsclk_coarse_dly_3: string := "0 ps";
pll_lvdsclk_enable_disable_3: string := "true";
pll_lvdsclk_fine_dly_3: string := "0 ps"
);
port(
phout_0 : out vl_logic_vector(7 downto 0);
phout_1 : out vl_logic_vector(7 downto 0);
adjpllin : in vl_logic_vector;
cclk : in vl_logic_vector;
coreclkin : in vl_logic_vector;
extswitch : in vl_logic_vector;
iqtxrxclkin : in vl_logic_vector;
plliqclkin : in vl_logic_vector;
rxiqclkin : in vl_logic_vector;
clkin : in vl_logic_vector(3 downto 0);
refiqclk_0 : in vl_logic_vector(1 downto 0);
refiqclk_1 : in vl_logic_vector(1 downto 0);
clk0bad : out vl_logic_vector;
clk1bad : out vl_logic_vector;
pllclksel : out vl_logic_vector;
atpgmode : in vl_logic_vector;
clk : in vl_logic_vector;
fpllcsrtest : in vl_logic_vector;
iocsrclkin : in vl_logic_vector;
iocsrdatain : in vl_logic_vector;
iocsren : in vl_logic_vector;
iocsrrstn : in vl_logic_vector;
mdiodis : in vl_logic_vector;
phaseen : in vl_logic_vector;
read : in vl_logic_vector;
rstn : in vl_logic_vector;
scanen : in vl_logic_vector;
sershiftload : in vl_logic_vector;
shiftdonei : in vl_logic_vector;
updn : in vl_logic_vector;
write : in vl_logic_vector;
addr_0 : in vl_logic_vector(5 downto 0);
addr_1 : in vl_logic_vector(5 downto 0);
byteen_0 : in vl_logic_vector(1 downto 0);
byteen_1 : in vl_logic_vector(1 downto 0);
cntsel_0 : in vl_logic_vector(4 downto 0);
cntsel_1 : in vl_logic_vector(4 downto 0);
din_0 : in vl_logic_vector(15 downto 0);
din_1 : in vl_logic_vector(15 downto 0);
blockselect : out vl_logic_vector;
iocsrdataout : out vl_logic_vector;
iocsrenbuf : out vl_logic_vector;
iocsrrstnbuf : out vl_logic_vector;
phasedone : out vl_logic_vector;
dout_0 : out vl_logic_vector(15 downto 0);
dout_1 : out vl_logic_vector(15 downto 0);
dprioout_0 : out vl_logic_vector(815 downto 0);
dprioout_1 : out vl_logic_vector(815 downto 0);
fbclkfpll : in vl_logic_vector;
lvdfbin : in vl_logic_vector;
nresync : in vl_logic_vector;
pfden : in vl_logic_vector;
shiften_fpll : in vl_logic_vector;
zdb : in vl_logic_vector;
fblvdsout : out vl_logic_vector;
lock : out vl_logic_vector;
mcntout : out vl_logic_vector;
plniotribuf : out vl_logic_vector;
clken : in vl_logic_vector;
extclk : out vl_logic_vector;
dll_clkin : in vl_logic_vector;
clkout : out vl_logic_vector;
loaden : out vl_logic_vector;
lvdsclk : out vl_logic_vector;
divclk : out vl_logic_vector;
cascade_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_counters : constant is 1;
attribute mti_svvh_generic_type of number_of_fplls : constant is 1;
attribute mti_svvh_generic_type of number_of_extclks : constant is 1;
attribute mti_svvh_generic_type of number_of_dlls : constant is 1;
attribute mti_svvh_generic_type of number_of_lvds : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_0 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_0 : constant is 1;
attribute mti_svvh_generic_type of forcelock_0 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_0 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_0 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_0 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_0 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_0 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_0 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_0 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_1 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_1 : constant is 1;
attribute mti_svvh_generic_type of forcelock_1 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_1 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_1 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_1 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_1 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_1 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_1 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_1 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_0 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_1 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_2 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_2 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_2 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_3 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_3 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_3 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_4 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_4 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_4 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_5 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_5 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_5 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_6 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_6 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_6 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_7 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_7 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_7 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_8 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_8 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_8 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_9 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_9 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_9 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_9 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_9 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_10 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_10 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_10 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_10 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_10 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_11 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_11 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_11 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_11 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_11 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_12 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_12 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_12 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_12 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_12 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_13 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_13 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_13 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_13 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_13 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_14 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_14 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_14 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_14 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_14 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_15 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_15 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_15 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_15 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_15 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_16 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_16 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_16 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_16 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_16 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_17 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_17 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_17 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_17 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_17 : constant is 3;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_0 : constant is 1;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_0 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_2 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_3 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_0 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_3 : constant is 1;
end altera_arriav_pll;
| mit |
Nic30/hwtLib | hwtLib/examples/showcase0.vhd | 1 | 5141 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
--
-- .. hwt-autodoc::
--
ENTITY Showcase0 IS
PORT(
a : IN UNSIGNED(31 DOWNTO 0);
b : IN SIGNED(31 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clk : IN STD_LOGIC;
cmp_0 : OUT STD_LOGIC;
cmp_1 : OUT STD_LOGIC;
cmp_2 : OUT STD_LOGIC;
cmp_3 : OUT STD_LOGIC;
cmp_4 : OUT STD_LOGIC;
cmp_5 : OUT STD_LOGIC;
contOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
e : IN STD_LOGIC;
f : OUT STD_LOGIC;
fitted : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
g : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
h : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
j : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
k : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_0 : OUT STD_LOGIC;
output : OUT STD_LOGIC;
rst_n : IN STD_LOGIC;
sc_signal : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF Showcase0 IS
TYPE arr_t_0 IS ARRAY (3 DOWNTO 0) OF SIGNED(7 DOWNTO 0);
TYPE arr_t_1 IS ARRAY (3 DOWNTO 0) OF UNSIGNED(7 DOWNTO 0);
CONSTANT const_private_signal : UNSIGNED(31 DOWNTO 0) := UNSIGNED'(X"0000007B");
SIGNAL fallingEdgeRam : arr_t_0;
SIGNAL r : STD_LOGIC := '0';
SIGNAL r_0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
SIGNAL r_1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
SIGNAL r_next : STD_LOGIC;
SIGNAL r_next_0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL r_next_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
CONSTANT rom : arr_t_1 := (
UNSIGNED'(X"00"),
UNSIGNED'(X"01"),
UNSIGNED'(X"02"),
UNSIGNED'(X"03"));
BEGIN
assig_process_c: PROCESS(a, b)
VARIABLE tmpCastExpr_0 : UNSIGNED(31 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a + UNSIGNED(b);
c <= STD_LOGIC_VECTOR(tmpCastExpr_0);
END PROCESS;
cmp_0 <= '1' WHEN (a < UNSIGNED'(X"00000004")) ELSE '0';
cmp_1 <= '1' WHEN (a > UNSIGNED'(X"00000004")) ELSE '0';
cmp_2 <= '1' WHEN (b <= SIGNED'(X"00000004")) ELSE '0';
cmp_3 <= '1' WHEN (b >= SIGNED'(X"00000004")) ELSE '0';
cmp_4 <= '1' WHEN (b /= SIGNED'(X"00000004")) ELSE '0';
cmp_5 <= '1' WHEN (b = SIGNED'(X"00000004")) ELSE '0';
contOut <= STD_LOGIC_VECTOR(const_private_signal);
f <= r;
assig_process_fallingEdgeRam: PROCESS(clk)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
VARIABLE tmpCastExpr_2 : SIGNED(7 DOWNTO 0);
VARIABLE tmpCastExpr_1 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a(7 DOWNTO 0);
tmpCastExpr_2 := fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1)));
tmpCastExpr_1 := UNSIGNED(tmpCastExpr_2);
IF FALLING_EDGE(clk) THEN
fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1))) <= SIGNED(tmpCastExpr_0);
k <= X"000000" & STD_LOGIC_VECTOR(tmpCastExpr_1);
END IF;
END PROCESS;
assig_process_fitted: PROCESS(a)
VARIABLE tmpCastExpr_0 : UNSIGNED(15 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a(15 DOWNTO 0);
fitted <= STD_LOGIC_VECTOR(tmpCastExpr_0);
END PROCESS;
assig_process_g: PROCESS(a, b)
VARIABLE tmpCastExpr_0 : UNSIGNED(5 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a(5 DOWNTO 0);
g <= (a(1) AND b(1)) & ((a(0) XOR b(0)) OR a(1)) & STD_LOGIC_VECTOR(tmpCastExpr_0);
END PROCESS;
assig_process_h: PROCESS(a, r)
BEGIN
IF a(2) = '1' THEN
IF r = '1' THEN
h <= X"00";
ELSIF a(1) = '1' THEN
h <= X"01";
ELSE
h <= X"02";
END IF;
END IF;
END PROCESS;
assig_process_j: PROCESS(clk)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := rom(TO_INTEGER(UNSIGNED(r_1)));
IF RISING_EDGE(clk) THEN
j <= STD_LOGIC_VECTOR(tmpCastExpr_0);
END IF;
END PROCESS;
out_0 <= '0';
output <= 'X';
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r_1 <= "00";
r_0 <= "00";
r <= '0';
ELSE
r_1 <= r_next_1;
r_0 <= r_next_0;
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next_0 <= i;
r_next_1 <= r_0;
assig_process_r_next_1: PROCESS(e, r)
BEGIN
IF NOT r = '1' THEN
r_next <= e;
ELSE
r_next <= r;
END IF;
END PROCESS;
assig_process_sc_signal: PROCESS(a)
BEGIN
CASE a IS
WHEN UNSIGNED'(X"00000001") =>
sc_signal <= X"00";
WHEN UNSIGNED'(X"00000002") =>
sc_signal <= X"01";
WHEN UNSIGNED'(X"00000003") =>
sc_signal <= X"03";
WHEN OTHERS =>
sc_signal <= X"04";
END CASE;
END PROCESS;
END ARCHITECTURE;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_barrelshifter.vhd | 4 | 2271 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_barrelshifter is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
user_aclr : in std_logic;
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0);
r : out std_logic_vector(WIDTH-1 downto 0);
clock : in std_logic;
direction : in std_logic;
a : in std_logic_vector(WIDTH-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_barrelshifter;
architecture rtl of alt_dspbuilder_barrelshifter is
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18
);
port (
a : in std_logic_vector(18-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
distance : in std_logic_vector(4-1 downto 0);
ena : in std_logic;
r : out std_logic_vector(18-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
begin
alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: if ((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)) generate
inst_alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map(DISTANCE_WIDTH => 4, NDIRECTION => 1, SIGNED => 0, USE_DEDICATED_CIRCUITRY => "false", PIPELINE => 0, WIDTH => 18)
port map(a => a, aclr => aclr, clock => clock, distance => distance, ena => ena, r => r, user_aclr => user_aclr);
end generate;
assert not (((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_delay_GND2PGZRBZ.vhd | 3 | 1088 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GND2PGZRBZ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "1";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GND2PGZRBZ is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; | mit |
VladisM/MARK_II | VHDL/src/cpu/qip/fp_div/fp_div_sim/fp_div.vhd | 1 | 86872 | -- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_div
-- VHDL created on Thu Feb 15 13:09:41 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_div is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end fp_div;
architecture normal of fp_div is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstBiasM1_uid6_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal expX_uid9_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal fracX_uid10_fpDivTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal signX_uid11_fpDivTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal expY_uid12_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal fracY_uid13_fpDivTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal signY_uid14_fpDivTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal paddingY_uid15_fpDivTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal updatedY_uid16_fpDivTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal fracYZero_uid15_fpDivTest_a : STD_LOGIC_VECTOR (23 downto 0);
signal fracYZero_uid15_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracYZero_uid15_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid18_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstAllZWE_uid20_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_x_uid23_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_x_uid23_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid24_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid24_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid25_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid25_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid26_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_x_uid27_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid28_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid29_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid30_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_x_uid31_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid37_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid37_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid38_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid38_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid39_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid39_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid40_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_y_uid41_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid42_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid43_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid44_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_y_uid45_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid46_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid46_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXmY_uid47_fpDivTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expXmY_uid47_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expXmY_uid47_fpDivTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expXmY_uid47_fpDivTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal expR_uid48_fpDivTest_a : STD_LOGIC_VECTOR (10 downto 0);
signal expR_uid48_fpDivTest_b : STD_LOGIC_VECTOR (10 downto 0);
signal expR_uid48_fpDivTest_o : STD_LOGIC_VECTOR (10 downto 0);
signal expR_uid48_fpDivTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal yAddr_uid51_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal yPE_uid52_fpDivTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal fracYPostZ_uid56_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracYPostZ_uid56_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal lOAdded_uid58_fpDivTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal oFracXSE_bottomExtension_uid61_fpDivTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal oFracXSE_mergedSignalTM_uid63_fpDivTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal divValPreNormS_uid65_fpDivTest_b : STD_LOGIC_VECTOR (25 downto 0);
signal divValPreNormTrunc_uid66_fpDivTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal divValPreNormTrunc_uid66_fpDivTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal norm_uid67_fpDivTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal divValPreNormHigh_uid68_fpDivTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal divValPreNormHigh_uid68_fpDivTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal divValPreNormLow_uid69_fpDivTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal divValPreNormLow_uid69_fpDivTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal normFracRnd_uid70_fpDivTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal normFracRnd_uid70_fpDivTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal expFracRnd_uid71_fpDivTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal rndOp_uid75_fpDivTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal expFracPostRnd_uid76_fpDivTest_a : STD_LOGIC_VECTOR (35 downto 0);
signal expFracPostRnd_uid76_fpDivTest_b : STD_LOGIC_VECTOR (35 downto 0);
signal expFracPostRnd_uid76_fpDivTest_o : STD_LOGIC_VECTOR (35 downto 0);
signal expFracPostRnd_uid76_fpDivTest_q : STD_LOGIC_VECTOR (34 downto 0);
signal fracRPreExc_uid78_fpDivTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExc_uid78_fpDivTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excRPreExc_uid79_fpDivTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal excRPreExc_uid79_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expRExt_uid80_fpDivTest_b : STD_LOGIC_VECTOR (10 downto 0);
signal expUdf_uid81_fpDivTest_a : STD_LOGIC_VECTOR (12 downto 0);
signal expUdf_uid81_fpDivTest_b : STD_LOGIC_VECTOR (12 downto 0);
signal expUdf_uid81_fpDivTest_o : STD_LOGIC_VECTOR (12 downto 0);
signal expUdf_uid81_fpDivTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal expOvf_uid84_fpDivTest_a : STD_LOGIC_VECTOR (12 downto 0);
signal expOvf_uid84_fpDivTest_b : STD_LOGIC_VECTOR (12 downto 0);
signal expOvf_uid84_fpDivTest_o : STD_LOGIC_VECTOR (12 downto 0);
signal expOvf_uid84_fpDivTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal zeroOverReg_uid85_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal regOverRegWithUf_uid86_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xRegOrZero_uid87_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal regOrZeroOverInf_uid88_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid89_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRYZ_uid90_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRYROvf_uid91_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIYZ_uid92_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIYR_uid93_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid94_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZYZ_uid95_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIYI_uid96_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid97_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal concExc_uid98_fpDivTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal excREnc_uid99_fpDivTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal oneFracRPostExc2_uid100_fpDivTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracRPostExc_uid103_fpDivTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExc_uid103_fpDivTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExc_uid107_fpDivTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExc_uid107_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal invExcRNaN_uid108_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sRPostExc_uid109_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal divR_uid110_fpDivTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal os_uid114_invTables_q : STD_LOGIC_VECTOR (30 downto 0);
signal os_uid118_invTables_q : STD_LOGIC_VECTOR (20 downto 0);
signal yT1_uid126_invPolyEval_b : STD_LOGIC_VECTOR (11 downto 0);
signal rndBit_uid128_invPolyEval_q : STD_LOGIC_VECTOR (1 downto 0);
signal cIncludingRoundingBit_uid129_invPolyEval_q : STD_LOGIC_VECTOR (22 downto 0);
signal ts1_uid131_invPolyEval_a : STD_LOGIC_VECTOR (23 downto 0);
signal ts1_uid131_invPolyEval_b : STD_LOGIC_VECTOR (23 downto 0);
signal ts1_uid131_invPolyEval_o : STD_LOGIC_VECTOR (23 downto 0);
signal ts1_uid131_invPolyEval_q : STD_LOGIC_VECTOR (23 downto 0);
signal s1_uid132_invPolyEval_b : STD_LOGIC_VECTOR (22 downto 0);
signal rndBit_uid135_invPolyEval_q : STD_LOGIC_VECTOR (2 downto 0);
signal cIncludingRoundingBit_uid136_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal ts2_uid138_invPolyEval_a : STD_LOGIC_VECTOR (34 downto 0);
signal ts2_uid138_invPolyEval_b : STD_LOGIC_VECTOR (34 downto 0);
signal ts2_uid138_invPolyEval_o : STD_LOGIC_VECTOR (34 downto 0);
signal ts2_uid138_invPolyEval_q : STD_LOGIC_VECTOR (34 downto 0);
signal s2_uid139_invPolyEval_b : STD_LOGIC_VECTOR (33 downto 0);
signal topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (16 downto 0);
signal rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (14 downto 0);
signal aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal n0_uid177_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid178_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid179_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid180_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid185_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid186_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid187_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid188_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid193_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid194_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n0_uid195_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid196_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (18 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (37 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (38 downto 0);
signal osig_uid222_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (35 downto 0);
signal osig_uid222_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (12 downto 0);
signal topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (3 downto 0);
signal topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
signal topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (4 downto 0);
signal topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_a0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_b0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_s1 : STD_LOGIC_VECTOR (33 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_reset : std_logic;
signal sm0_uid247_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal osig_uid248_pT1_uid127_invPolyEval_in : STD_LOGIC_VECTOR (32 downto 0);
signal osig_uid248_pT1_uid127_invPolyEval_b : STD_LOGIC_VECTOR (13 downto 0);
signal nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (14 downto 0);
signal topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
signal topRangeY_uid266_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (16 downto 0);
signal aboveLeftX_uid272_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (7 downto 0);
signal aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (7 downto 0);
signal rightBottomX_uid283_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (6 downto 0);
signal rightBottomX_uid283_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightBottomY_uid284_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomY_uid284_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (4 downto 0);
signal n0_uid293_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid294_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid301_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid302_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (2 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_a0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_b0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_s1 : STD_LOGIC_VECTOR (33 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_reset : std_logic;
signal sm0_uid315_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_a0 : STD_LOGIC_VECTOR (7 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_s1 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_reset : std_logic;
signal sm0_uid316_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (15 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_a0 : STD_LOGIC_VECTOR (2 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_b0 : STD_LOGIC_VECTOR (2 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_s1 : STD_LOGIC_VECTOR (5 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_reset : std_logic;
signal sm0_uid317_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (5 downto 0);
signal lowRangeA_uid318_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (0 downto 0);
signal lowRangeA_uid318_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (0 downto 0);
signal highABits_uid319_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (32 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0_uid321_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (34 downto 0);
signal lowRangeA_uid322_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (2 downto 0);
signal lowRangeA_uid322_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (2 downto 0);
signal highABits_uid323_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (31 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (32 downto 0);
signal lev2_a0_uid325_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (35 downto 0);
signal osig_uid326_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (32 downto 0);
signal osig_uid326_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (24 downto 0);
signal memoryC0_uid112_invTables_lutmem_reset0 : std_logic;
signal memoryC0_uid112_invTables_lutmem_ia : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC0_uid112_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid112_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid112_invTables_lutmem_ir : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC0_uid112_invTables_lutmem_r : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC0_uid113_invTables_lutmem_reset0 : std_logic;
signal memoryC0_uid113_invTables_lutmem_ia : STD_LOGIC_VECTOR (12 downto 0);
signal memoryC0_uid113_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid113_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid113_invTables_lutmem_ir : STD_LOGIC_VECTOR (12 downto 0);
signal memoryC0_uid113_invTables_lutmem_r : STD_LOGIC_VECTOR (12 downto 0);
signal memoryC1_uid116_invTables_lutmem_reset0 : std_logic;
signal memoryC1_uid116_invTables_lutmem_ia : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC1_uid116_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid116_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid116_invTables_lutmem_ir : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC1_uid116_invTables_lutmem_r : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC1_uid117_invTables_lutmem_reset0 : std_logic;
signal memoryC1_uid117_invTables_lutmem_ia : STD_LOGIC_VECTOR (2 downto 0);
signal memoryC1_uid117_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid117_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid117_invTables_lutmem_ir : STD_LOGIC_VECTOR (2 downto 0);
signal memoryC1_uid117_invTables_lutmem_r : STD_LOGIC_VECTOR (2 downto 0);
signal memoryC2_uid120_invTables_lutmem_reset0 : std_logic;
signal memoryC2_uid120_invTables_lutmem_ia : STD_LOGIC_VECTOR (11 downto 0);
signal memoryC2_uid120_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC2_uid120_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC2_uid120_invTables_lutmem_ir : STD_LOGIC_VECTOR (11 downto 0);
signal memoryC2_uid120_invTables_lutmem_r : STD_LOGIC_VECTOR (11 downto 0);
signal invY_uid54_fpDivTest_merged_bit_select_in : STD_LOGIC_VECTOR (31 downto 0);
signal invY_uid54_fpDivTest_merged_bit_select_b : STD_LOGIC_VECTOR (25 downto 0);
signal invY_uid54_fpDivTest_merged_bit_select_c : STD_LOGIC_VECTOR (0 downto 0);
signal lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c : STD_LOGIC_VECTOR (12 downto 0);
signal lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c : STD_LOGIC_VECTOR (32 downto 0);
signal redist0_lOAdded_uid58_fpDivTest_q_2_q : STD_LOGIC_VECTOR (23 downto 0);
signal redist1_fracYPostZ_uid56_fpDivTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist2_yPE_uid52_fpDivTest_b_2_q : STD_LOGIC_VECTOR (13 downto 0);
signal redist3_yPE_uid52_fpDivTest_b_4_q : STD_LOGIC_VECTOR (13 downto 0);
signal redist4_yAddr_uid51_fpDivTest_b_2_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist5_yAddr_uid51_fpDivTest_b_4_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist6_expXmY_uid47_fpDivTest_q_8_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist7_signR_uid46_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist8_fracXIsZero_uid39_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist9_expXIsMax_uid38_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist10_excZ_y_uid37_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist11_fracXIsZero_uid25_fpDivTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist12_expXIsMax_uid24_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist13_excZ_x_uid23_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist14_fracYZero_uid15_fpDivTest_q_6_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist15_fracX_uid10_fpDivTest_b_6_q : STD_LOGIC_VECTOR (22 downto 0);
begin
-- fracY_uid13_fpDivTest(BITSELECT,12)@0
fracY_uid13_fpDivTest_b <= b(22 downto 0);
-- paddingY_uid15_fpDivTest(CONSTANT,14)
paddingY_uid15_fpDivTest_q <= "00000000000000000000000";
-- fracXIsZero_uid39_fpDivTest(LOGICAL,38)@0 + 1
fracXIsZero_uid39_fpDivTest_qi <= "1" WHEN paddingY_uid15_fpDivTest_q = fracY_uid13_fpDivTest_b ELSE "0";
fracXIsZero_uid39_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid39_fpDivTest_qi, xout => fracXIsZero_uid39_fpDivTest_q, clk => clk, aclr => areset );
-- redist8_fracXIsZero_uid39_fpDivTest_q_8(DELAY,343)
redist8_fracXIsZero_uid39_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid39_fpDivTest_q, xout => redist8_fracXIsZero_uid39_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- cstAllOWE_uid18_fpDivTest(CONSTANT,17)
cstAllOWE_uid18_fpDivTest_q <= "11111111";
-- expY_uid12_fpDivTest(BITSELECT,11)@0
expY_uid12_fpDivTest_b <= b(30 downto 23);
-- expXIsMax_uid38_fpDivTest(LOGICAL,37)@0 + 1
expXIsMax_uid38_fpDivTest_qi <= "1" WHEN expY_uid12_fpDivTest_b = cstAllOWE_uid18_fpDivTest_q ELSE "0";
expXIsMax_uid38_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid38_fpDivTest_qi, xout => expXIsMax_uid38_fpDivTest_q, clk => clk, aclr => areset );
-- redist9_expXIsMax_uid38_fpDivTest_q_8(DELAY,344)
redist9_expXIsMax_uid38_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid38_fpDivTest_q, xout => redist9_expXIsMax_uid38_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excI_y_uid41_fpDivTest(LOGICAL,40)@8
excI_y_uid41_fpDivTest_q <= redist9_expXIsMax_uid38_fpDivTest_q_8_q and redist8_fracXIsZero_uid39_fpDivTest_q_8_q;
-- fracX_uid10_fpDivTest(BITSELECT,9)@0
fracX_uid10_fpDivTest_b <= a(22 downto 0);
-- redist15_fracX_uid10_fpDivTest_b_6(DELAY,350)
redist15_fracX_uid10_fpDivTest_b_6 : dspba_delay
GENERIC MAP ( width => 23, depth => 6, reset_kind => "ASYNC" )
PORT MAP ( xin => fracX_uid10_fpDivTest_b, xout => redist15_fracX_uid10_fpDivTest_b_6_q, clk => clk, aclr => areset );
-- fracXIsZero_uid25_fpDivTest(LOGICAL,24)@6 + 1
fracXIsZero_uid25_fpDivTest_qi <= "1" WHEN paddingY_uid15_fpDivTest_q = redist15_fracX_uid10_fpDivTest_b_6_q ELSE "0";
fracXIsZero_uid25_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid25_fpDivTest_qi, xout => fracXIsZero_uid25_fpDivTest_q, clk => clk, aclr => areset );
-- redist11_fracXIsZero_uid25_fpDivTest_q_2(DELAY,346)
redist11_fracXIsZero_uid25_fpDivTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid25_fpDivTest_q, xout => redist11_fracXIsZero_uid25_fpDivTest_q_2_q, clk => clk, aclr => areset );
-- expX_uid9_fpDivTest(BITSELECT,8)@0
expX_uid9_fpDivTest_b <= a(30 downto 23);
-- expXIsMax_uid24_fpDivTest(LOGICAL,23)@0 + 1
expXIsMax_uid24_fpDivTest_qi <= "1" WHEN expX_uid9_fpDivTest_b = cstAllOWE_uid18_fpDivTest_q ELSE "0";
expXIsMax_uid24_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid24_fpDivTest_qi, xout => expXIsMax_uid24_fpDivTest_q, clk => clk, aclr => areset );
-- redist12_expXIsMax_uid24_fpDivTest_q_8(DELAY,347)
redist12_expXIsMax_uid24_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid24_fpDivTest_q, xout => redist12_expXIsMax_uid24_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excI_x_uid27_fpDivTest(LOGICAL,26)@8
excI_x_uid27_fpDivTest_q <= redist12_expXIsMax_uid24_fpDivTest_q_8_q and redist11_fracXIsZero_uid25_fpDivTest_q_2_q;
-- excXIYI_uid96_fpDivTest(LOGICAL,95)@8
excXIYI_uid96_fpDivTest_q <= excI_x_uid27_fpDivTest_q and excI_y_uid41_fpDivTest_q;
-- fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@8
fracXIsNotZero_uid40_fpDivTest_q <= not (redist8_fracXIsZero_uid39_fpDivTest_q_8_q);
-- excN_y_uid42_fpDivTest(LOGICAL,41)@8
excN_y_uid42_fpDivTest_q <= redist9_expXIsMax_uid38_fpDivTest_q_8_q and fracXIsNotZero_uid40_fpDivTest_q;
-- fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@8
fracXIsNotZero_uid26_fpDivTest_q <= not (redist11_fracXIsZero_uid25_fpDivTest_q_2_q);
-- excN_x_uid28_fpDivTest(LOGICAL,27)@8
excN_x_uid28_fpDivTest_q <= redist12_expXIsMax_uid24_fpDivTest_q_8_q and fracXIsNotZero_uid26_fpDivTest_q;
-- cstAllZWE_uid20_fpDivTest(CONSTANT,19)
cstAllZWE_uid20_fpDivTest_q <= "00000000";
-- excZ_y_uid37_fpDivTest(LOGICAL,36)@0 + 1
excZ_y_uid37_fpDivTest_qi <= "1" WHEN expY_uid12_fpDivTest_b = cstAllZWE_uid20_fpDivTest_q ELSE "0";
excZ_y_uid37_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid37_fpDivTest_qi, xout => excZ_y_uid37_fpDivTest_q, clk => clk, aclr => areset );
-- redist10_excZ_y_uid37_fpDivTest_q_8(DELAY,345)
redist10_excZ_y_uid37_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid37_fpDivTest_q, xout => redist10_excZ_y_uid37_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excZ_x_uid23_fpDivTest(LOGICAL,22)@0 + 1
excZ_x_uid23_fpDivTest_qi <= "1" WHEN expX_uid9_fpDivTest_b = cstAllZWE_uid20_fpDivTest_q ELSE "0";
excZ_x_uid23_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid23_fpDivTest_qi, xout => excZ_x_uid23_fpDivTest_q, clk => clk, aclr => areset );
-- redist13_excZ_x_uid23_fpDivTest_q_8(DELAY,348)
redist13_excZ_x_uid23_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid23_fpDivTest_q, xout => redist13_excZ_x_uid23_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excXZYZ_uid95_fpDivTest(LOGICAL,94)@8
excXZYZ_uid95_fpDivTest_q <= redist13_excZ_x_uid23_fpDivTest_q_8_q and redist10_excZ_y_uid37_fpDivTest_q_8_q;
-- excRNaN_uid97_fpDivTest(LOGICAL,96)@8
excRNaN_uid97_fpDivTest_q <= excXZYZ_uid95_fpDivTest_q or excN_x_uid28_fpDivTest_q or excN_y_uid42_fpDivTest_q or excXIYI_uid96_fpDivTest_q;
-- invExcRNaN_uid108_fpDivTest(LOGICAL,107)@8
invExcRNaN_uid108_fpDivTest_q <= not (excRNaN_uid97_fpDivTest_q);
-- signY_uid14_fpDivTest(BITSELECT,13)@0
signY_uid14_fpDivTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- signX_uid11_fpDivTest(BITSELECT,10)@0
signX_uid11_fpDivTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- signR_uid46_fpDivTest(LOGICAL,45)@0 + 1
signR_uid46_fpDivTest_qi <= signX_uid11_fpDivTest_b xor signY_uid14_fpDivTest_b;
signR_uid46_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid46_fpDivTest_qi, xout => signR_uid46_fpDivTest_q, clk => clk, aclr => areset );
-- redist7_signR_uid46_fpDivTest_q_8(DELAY,342)
redist7_signR_uid46_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid46_fpDivTest_q, xout => redist7_signR_uid46_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- sRPostExc_uid109_fpDivTest(LOGICAL,108)@8
sRPostExc_uid109_fpDivTest_q <= redist7_signR_uid46_fpDivTest_q_8_q and invExcRNaN_uid108_fpDivTest_q;
-- lOAdded_uid58_fpDivTest(BITJOIN,57)@6
lOAdded_uid58_fpDivTest_q <= VCC_q & redist15_fracX_uid10_fpDivTest_b_6_q;
-- redist0_lOAdded_uid58_fpDivTest_q_2(DELAY,335)
redist0_lOAdded_uid58_fpDivTest_q_2 : dspba_delay
GENERIC MAP ( width => 24, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => lOAdded_uid58_fpDivTest_q, xout => redist0_lOAdded_uid58_fpDivTest_q_2_q, clk => clk, aclr => areset );
-- oFracXSE_bottomExtension_uid61_fpDivTest(CONSTANT,60)
oFracXSE_bottomExtension_uid61_fpDivTest_q <= "00";
-- oFracXSE_mergedSignalTM_uid63_fpDivTest(BITJOIN,62)@8
oFracXSE_mergedSignalTM_uid63_fpDivTest_q <= redist0_lOAdded_uid58_fpDivTest_q_2_q & oFracXSE_bottomExtension_uid61_fpDivTest_q;
-- aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,170)@6
aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_in <= lOAdded_uid58_fpDivTest_q(14 downto 0);
aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_in(14 downto 10);
-- n1_uid180_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,179)@6
n1_uid180_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n1_uid188_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,187)@6
n1_uid188_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid180_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n1_uid196_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,195)@6
n1_uid196_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid188_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- yAddr_uid51_fpDivTest(BITSELECT,50)@0
yAddr_uid51_fpDivTest_b <= fracY_uid13_fpDivTest_b(22 downto 14);
-- memoryC2_uid120_invTables_lutmem(DUALMEM,331)@0 + 2
memoryC2_uid120_invTables_lutmem_aa <= yAddr_uid51_fpDivTest_b;
memoryC2_uid120_invTables_lutmem_reset0 <= areset;
memoryC2_uid120_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC2_uid120_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC2_uid120_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC2_uid120_invTables_lutmem_aa,
q_a => memoryC2_uid120_invTables_lutmem_ir
);
memoryC2_uid120_invTables_lutmem_r <= memoryC2_uid120_invTables_lutmem_ir(11 downto 0);
-- topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval(CONSTANT,242)
topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval_q <= "00000";
-- topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval(BITJOIN,244)@2
topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval_q <= memoryC2_uid120_invTables_lutmem_r & topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval_q;
-- GND(CONSTANT,0)
GND_q <= "0";
-- yPE_uid52_fpDivTest(BITSELECT,51)@0
yPE_uid52_fpDivTest_b <= b(13 downto 0);
-- redist2_yPE_uid52_fpDivTest_b_2(DELAY,337)
redist2_yPE_uid52_fpDivTest_b_2 : dspba_delay
GENERIC MAP ( width => 14, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => yPE_uid52_fpDivTest_b, xout => redist2_yPE_uid52_fpDivTest_b_2_q, clk => clk, aclr => areset );
-- yT1_uid126_invPolyEval(BITSELECT,125)@2
yT1_uid126_invPolyEval_b <= redist2_yPE_uid52_fpDivTest_b_2_q(13 downto 2);
-- nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval(BITJOIN,225)@2
nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval_q <= GND_q & yT1_uid126_invPolyEval_b;
-- topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval(CONSTANT,238)
topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval_q <= "0000";
-- topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval(BITJOIN,240)@2
topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval_q <= nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval_q & topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval_q;
-- sm0_uid247_pT1_uid127_invPolyEval(MULT,246)@2 + 2
sm0_uid247_pT1_uid127_invPolyEval_a0 <= STD_LOGIC_VECTOR(topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval_q);
sm0_uid247_pT1_uid127_invPolyEval_b0 <= STD_LOGIC_VECTOR(topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval_q);
sm0_uid247_pT1_uid127_invPolyEval_reset <= areset;
sm0_uid247_pT1_uid127_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 17,
lpm_widthb => 17,
lpm_widthp => 34,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid247_pT1_uid127_invPolyEval_a0,
datab => sm0_uid247_pT1_uid127_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid247_pT1_uid127_invPolyEval_reset,
clock => clk,
result => sm0_uid247_pT1_uid127_invPolyEval_s1
);
sm0_uid247_pT1_uid127_invPolyEval_q <= sm0_uid247_pT1_uid127_invPolyEval_s1;
-- osig_uid248_pT1_uid127_invPolyEval(BITSELECT,247)@4
osig_uid248_pT1_uid127_invPolyEval_in <= STD_LOGIC_VECTOR(sm0_uid247_pT1_uid127_invPolyEval_q(32 downto 0));
osig_uid248_pT1_uid127_invPolyEval_b <= STD_LOGIC_VECTOR(osig_uid248_pT1_uid127_invPolyEval_in(32 downto 19));
-- redist4_yAddr_uid51_fpDivTest_b_2(DELAY,339)
redist4_yAddr_uid51_fpDivTest_b_2 : dspba_delay
GENERIC MAP ( width => 9, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => yAddr_uid51_fpDivTest_b, xout => redist4_yAddr_uid51_fpDivTest_b_2_q, clk => clk, aclr => areset );
-- memoryC1_uid117_invTables_lutmem(DUALMEM,330)@2 + 2
memoryC1_uid117_invTables_lutmem_aa <= redist4_yAddr_uid51_fpDivTest_b_2_q;
memoryC1_uid117_invTables_lutmem_reset0 <= areset;
memoryC1_uid117_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 3,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC1_uid117_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC1_uid117_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC1_uid117_invTables_lutmem_aa,
q_a => memoryC1_uid117_invTables_lutmem_ir
);
memoryC1_uid117_invTables_lutmem_r <= memoryC1_uid117_invTables_lutmem_ir(2 downto 0);
-- memoryC1_uid116_invTables_lutmem(DUALMEM,329)@2 + 2
memoryC1_uid116_invTables_lutmem_aa <= redist4_yAddr_uid51_fpDivTest_b_2_q;
memoryC1_uid116_invTables_lutmem_reset0 <= areset;
memoryC1_uid116_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 18,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC1_uid116_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC1_uid116_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC1_uid116_invTables_lutmem_aa,
q_a => memoryC1_uid116_invTables_lutmem_ir
);
memoryC1_uid116_invTables_lutmem_r <= memoryC1_uid116_invTables_lutmem_ir(17 downto 0);
-- os_uid118_invTables(BITJOIN,117)@4
os_uid118_invTables_q <= memoryC1_uid117_invTables_lutmem_r & memoryC1_uid116_invTables_lutmem_r;
-- rndBit_uid128_invPolyEval(CONSTANT,127)
rndBit_uid128_invPolyEval_q <= "01";
-- cIncludingRoundingBit_uid129_invPolyEval(BITJOIN,128)@4
cIncludingRoundingBit_uid129_invPolyEval_q <= os_uid118_invTables_q & rndBit_uid128_invPolyEval_q;
-- ts1_uid131_invPolyEval(ADD,130)@4
ts1_uid131_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((23 downto 23 => cIncludingRoundingBit_uid129_invPolyEval_q(22)) & cIncludingRoundingBit_uid129_invPolyEval_q));
ts1_uid131_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((23 downto 14 => osig_uid248_pT1_uid127_invPolyEval_b(13)) & osig_uid248_pT1_uid127_invPolyEval_b));
ts1_uid131_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts1_uid131_invPolyEval_a) + SIGNED(ts1_uid131_invPolyEval_b));
ts1_uid131_invPolyEval_q <= ts1_uid131_invPolyEval_o(23 downto 0);
-- s1_uid132_invPolyEval(BITSELECT,131)@4
s1_uid132_invPolyEval_b <= STD_LOGIC_VECTOR(ts1_uid131_invPolyEval_q(23 downto 1));
-- rightBottomY_uid284_pT2_uid134_invPolyEval(BITSELECT,283)@4
rightBottomY_uid284_pT2_uid134_invPolyEval_in <= s1_uid132_invPolyEval_b(5 downto 0);
rightBottomY_uid284_pT2_uid134_invPolyEval_b <= rightBottomY_uid284_pT2_uid134_invPolyEval_in(5 downto 1);
-- n1_uid294_pT2_uid134_invPolyEval(BITSELECT,293)@4
n1_uid294_pT2_uid134_invPolyEval_b <= rightBottomY_uid284_pT2_uid134_invPolyEval_b(4 downto 1);
-- n1_uid302_pT2_uid134_invPolyEval(BITSELECT,301)@4
n1_uid302_pT2_uid134_invPolyEval_b <= n1_uid294_pT2_uid134_invPolyEval_b(3 downto 1);
-- redist3_yPE_uid52_fpDivTest_b_4(DELAY,338)
redist3_yPE_uid52_fpDivTest_b_4 : dspba_delay
GENERIC MAP ( width => 14, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => redist2_yPE_uid52_fpDivTest_b_2_q, xout => redist3_yPE_uid52_fpDivTest_b_4_q, clk => clk, aclr => areset );
-- nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval(BITJOIN,251)@4
nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q <= GND_q & redist3_yPE_uid52_fpDivTest_b_4_q;
-- rightBottomX_uid283_pT2_uid134_invPolyEval(BITSELECT,282)@4
rightBottomX_uid283_pT2_uid134_invPolyEval_in <= nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q(6 downto 0);
rightBottomX_uid283_pT2_uid134_invPolyEval_b <= rightBottomX_uid283_pT2_uid134_invPolyEval_in(6 downto 2);
-- n0_uid293_pT2_uid134_invPolyEval(BITSELECT,292)@4
n0_uid293_pT2_uid134_invPolyEval_b <= rightBottomX_uid283_pT2_uid134_invPolyEval_b(4 downto 1);
-- n0_uid301_pT2_uid134_invPolyEval(BITSELECT,300)@4
n0_uid301_pT2_uid134_invPolyEval_b <= n0_uid293_pT2_uid134_invPolyEval_b(3 downto 1);
-- sm0_uid317_pT2_uid134_invPolyEval(MULT,316)@4 + 2
sm0_uid317_pT2_uid134_invPolyEval_a0 <= n0_uid301_pT2_uid134_invPolyEval_b;
sm0_uid317_pT2_uid134_invPolyEval_b0 <= n1_uid302_pT2_uid134_invPolyEval_b;
sm0_uid317_pT2_uid134_invPolyEval_reset <= areset;
sm0_uid317_pT2_uid134_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 3,
lpm_widthb => 3,
lpm_widthp => 6,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid317_pT2_uid134_invPolyEval_a0,
datab => sm0_uid317_pT2_uid134_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid317_pT2_uid134_invPolyEval_reset,
clock => clk,
result => sm0_uid317_pT2_uid134_invPolyEval_s1
);
sm0_uid317_pT2_uid134_invPolyEval_q <= sm0_uid317_pT2_uid134_invPolyEval_s1;
-- aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval(BITSELECT,273)@4
aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_in <= STD_LOGIC_VECTOR(s1_uid132_invPolyEval_b(5 downto 0));
aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_in(5 downto 0));
-- aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval(BITJOIN,274)@4
aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval_q <= aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_b & oFracXSE_bottomExtension_uid61_fpDivTest_q;
-- aboveLeftX_uid272_pT2_uid134_invPolyEval(BITSELECT,271)@4
aboveLeftX_uid272_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q(14 downto 7));
-- sm0_uid316_pT2_uid134_invPolyEval(MULT,315)@4 + 2
sm0_uid316_pT2_uid134_invPolyEval_a0 <= STD_LOGIC_VECTOR(aboveLeftX_uid272_pT2_uid134_invPolyEval_b);
sm0_uid316_pT2_uid134_invPolyEval_b0 <= '0' & aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval_q;
sm0_uid316_pT2_uid134_invPolyEval_reset <= areset;
sm0_uid316_pT2_uid134_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 8,
lpm_widthb => 9,
lpm_widthp => 17,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid316_pT2_uid134_invPolyEval_a0,
datab => sm0_uid316_pT2_uid134_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid316_pT2_uid134_invPolyEval_reset,
clock => clk,
result => sm0_uid316_pT2_uid134_invPolyEval_s1
);
sm0_uid316_pT2_uid134_invPolyEval_q <= sm0_uid316_pT2_uid134_invPolyEval_s1(15 downto 0);
-- topRangeY_uid266_pT2_uid134_invPolyEval(BITSELECT,265)@4
topRangeY_uid266_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(s1_uid132_invPolyEval_b(22 downto 6));
-- topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval(BITJOIN,263)@4
topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval_q <= nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q & oFracXSE_bottomExtension_uid61_fpDivTest_q;
-- sm0_uid315_pT2_uid134_invPolyEval(MULT,314)@4 + 2
sm0_uid315_pT2_uid134_invPolyEval_a0 <= STD_LOGIC_VECTOR(topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval_q);
sm0_uid315_pT2_uid134_invPolyEval_b0 <= STD_LOGIC_VECTOR(topRangeY_uid266_pT2_uid134_invPolyEval_b);
sm0_uid315_pT2_uid134_invPolyEval_reset <= areset;
sm0_uid315_pT2_uid134_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 17,
lpm_widthb => 17,
lpm_widthp => 34,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid315_pT2_uid134_invPolyEval_a0,
datab => sm0_uid315_pT2_uid134_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid315_pT2_uid134_invPolyEval_reset,
clock => clk,
result => sm0_uid315_pT2_uid134_invPolyEval_s1
);
sm0_uid315_pT2_uid134_invPolyEval_q <= sm0_uid315_pT2_uid134_invPolyEval_s1;
-- highABits_uid319_pT2_uid134_invPolyEval(BITSELECT,318)@6
highABits_uid319_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(sm0_uid315_pT2_uid134_invPolyEval_q(33 downto 1));
-- lev1_a0high_uid320_pT2_uid134_invPolyEval(ADD,319)@6
lev1_a0high_uid320_pT2_uid134_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((33 downto 33 => highABits_uid319_pT2_uid134_invPolyEval_b(32)) & highABits_uid319_pT2_uid134_invPolyEval_b));
lev1_a0high_uid320_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((33 downto 16 => sm0_uid316_pT2_uid134_invPolyEval_q(15)) & sm0_uid316_pT2_uid134_invPolyEval_q));
lev1_a0high_uid320_pT2_uid134_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0high_uid320_pT2_uid134_invPolyEval_a) + SIGNED(lev1_a0high_uid320_pT2_uid134_invPolyEval_b));
lev1_a0high_uid320_pT2_uid134_invPolyEval_q <= lev1_a0high_uid320_pT2_uid134_invPolyEval_o(33 downto 0);
-- lowRangeA_uid318_pT2_uid134_invPolyEval(BITSELECT,317)@6
lowRangeA_uid318_pT2_uid134_invPolyEval_in <= sm0_uid315_pT2_uid134_invPolyEval_q(0 downto 0);
lowRangeA_uid318_pT2_uid134_invPolyEval_b <= lowRangeA_uid318_pT2_uid134_invPolyEval_in(0 downto 0);
-- lev1_a0_uid321_pT2_uid134_invPolyEval(BITJOIN,320)@6
lev1_a0_uid321_pT2_uid134_invPolyEval_q <= lev1_a0high_uid320_pT2_uid134_invPolyEval_q & lowRangeA_uid318_pT2_uid134_invPolyEval_b;
-- highABits_uid323_pT2_uid134_invPolyEval(BITSELECT,322)@6
highABits_uid323_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(lev1_a0_uid321_pT2_uid134_invPolyEval_q(34 downto 3));
-- lev2_a0high_uid324_pT2_uid134_invPolyEval(ADD,323)@6
lev2_a0high_uid324_pT2_uid134_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((33 downto 32 => highABits_uid323_pT2_uid134_invPolyEval_b(31)) & highABits_uid323_pT2_uid134_invPolyEval_b));
lev2_a0high_uid324_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "000000000000000000000000000" & sm0_uid317_pT2_uid134_invPolyEval_q));
lev2_a0high_uid324_pT2_uid134_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0high_uid324_pT2_uid134_invPolyEval_a) + SIGNED(lev2_a0high_uid324_pT2_uid134_invPolyEval_b));
lev2_a0high_uid324_pT2_uid134_invPolyEval_q <= lev2_a0high_uid324_pT2_uid134_invPolyEval_o(32 downto 0);
-- lowRangeA_uid322_pT2_uid134_invPolyEval(BITSELECT,321)@6
lowRangeA_uid322_pT2_uid134_invPolyEval_in <= lev1_a0_uid321_pT2_uid134_invPolyEval_q(2 downto 0);
lowRangeA_uid322_pT2_uid134_invPolyEval_b <= lowRangeA_uid322_pT2_uid134_invPolyEval_in(2 downto 0);
-- lev2_a0_uid325_pT2_uid134_invPolyEval(BITJOIN,324)@6
lev2_a0_uid325_pT2_uid134_invPolyEval_q <= lev2_a0high_uid324_pT2_uid134_invPolyEval_q & lowRangeA_uid322_pT2_uid134_invPolyEval_b;
-- osig_uid326_pT2_uid134_invPolyEval(BITSELECT,325)@6
osig_uid326_pT2_uid134_invPolyEval_in <= STD_LOGIC_VECTOR(lev2_a0_uid325_pT2_uid134_invPolyEval_q(32 downto 0));
osig_uid326_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(osig_uid326_pT2_uid134_invPolyEval_in(32 downto 8));
-- redist5_yAddr_uid51_fpDivTest_b_4(DELAY,340)
redist5_yAddr_uid51_fpDivTest_b_4 : dspba_delay
GENERIC MAP ( width => 9, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => redist4_yAddr_uid51_fpDivTest_b_2_q, xout => redist5_yAddr_uid51_fpDivTest_b_4_q, clk => clk, aclr => areset );
-- memoryC0_uid113_invTables_lutmem(DUALMEM,328)@4 + 2
memoryC0_uid113_invTables_lutmem_aa <= redist5_yAddr_uid51_fpDivTest_b_4_q;
memoryC0_uid113_invTables_lutmem_reset0 <= areset;
memoryC0_uid113_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 13,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC0_uid113_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC0_uid113_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC0_uid113_invTables_lutmem_aa,
q_a => memoryC0_uid113_invTables_lutmem_ir
);
memoryC0_uid113_invTables_lutmem_r <= memoryC0_uid113_invTables_lutmem_ir(12 downto 0);
-- memoryC0_uid112_invTables_lutmem(DUALMEM,327)@4 + 2
memoryC0_uid112_invTables_lutmem_aa <= redist5_yAddr_uid51_fpDivTest_b_4_q;
memoryC0_uid112_invTables_lutmem_reset0 <= areset;
memoryC0_uid112_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 18,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC0_uid112_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC0_uid112_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC0_uid112_invTables_lutmem_aa,
q_a => memoryC0_uid112_invTables_lutmem_ir
);
memoryC0_uid112_invTables_lutmem_r <= memoryC0_uid112_invTables_lutmem_ir(17 downto 0);
-- os_uid114_invTables(BITJOIN,113)@6
os_uid114_invTables_q <= memoryC0_uid113_invTables_lutmem_r & memoryC0_uid112_invTables_lutmem_r;
-- rndBit_uid135_invPolyEval(CONSTANT,134)
rndBit_uid135_invPolyEval_q <= "001";
-- cIncludingRoundingBit_uid136_invPolyEval(BITJOIN,135)@6
cIncludingRoundingBit_uid136_invPolyEval_q <= os_uid114_invTables_q & rndBit_uid135_invPolyEval_q;
-- ts2_uid138_invPolyEval(ADD,137)@6
ts2_uid138_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((34 downto 34 => cIncludingRoundingBit_uid136_invPolyEval_q(33)) & cIncludingRoundingBit_uid136_invPolyEval_q));
ts2_uid138_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((34 downto 25 => osig_uid326_pT2_uid134_invPolyEval_b(24)) & osig_uid326_pT2_uid134_invPolyEval_b));
ts2_uid138_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid138_invPolyEval_a) + SIGNED(ts2_uid138_invPolyEval_b));
ts2_uid138_invPolyEval_q <= ts2_uid138_invPolyEval_o(34 downto 0);
-- s2_uid139_invPolyEval(BITSELECT,138)@6
s2_uid139_invPolyEval_b <= STD_LOGIC_VECTOR(ts2_uid138_invPolyEval_q(34 downto 1));
-- invY_uid54_fpDivTest_merged_bit_select(BITSELECT,332)@6
invY_uid54_fpDivTest_merged_bit_select_in <= s2_uid139_invPolyEval_b(31 downto 0);
invY_uid54_fpDivTest_merged_bit_select_b <= invY_uid54_fpDivTest_merged_bit_select_in(30 downto 5);
invY_uid54_fpDivTest_merged_bit_select_c <= invY_uid54_fpDivTest_merged_bit_select_in(31 downto 31);
-- aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,169)@6
aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_in <= invY_uid54_fpDivTest_merged_bit_select_b(7 downto 0);
aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_in(7 downto 3);
-- n0_uid179_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,178)@6
n0_uid179_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n0_uid187_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,186)@6
n0_uid187_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid179_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n0_uid195_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,194)@6
n0_uid195_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid187_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- sm1_uid211_prodDivPreNormProd_uid60_fpDivTest(MULT,210)@6 + 2
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_a0 <= n0_uid195_prodDivPreNormProd_uid60_fpDivTest_b;
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_b0 <= n1_uid196_prodDivPreNormProd_uid60_fpDivTest_b;
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_q <= sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest(ADD,219)@8
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c);
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000" & sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_q);
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_b));
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_q <= lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_o(33 downto 0);
-- rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,168)@6
rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_in <= lOAdded_uid58_fpDivTest_q(5 downto 0);
rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_in(5 downto 1);
-- n1_uid178_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,177)@6
n1_uid178_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n1_uid186_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,185)@6
n1_uid186_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid178_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n1_uid194_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,193)@6
n1_uid194_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid186_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,167)@6
rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_in <= invY_uid54_fpDivTest_merged_bit_select_b(16 downto 0);
rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_in(16 downto 12);
-- n0_uid177_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,176)@6
n0_uid177_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n0_uid185_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,184)@6
n0_uid185_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid177_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n0_uid193_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,192)@6
n0_uid193_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid185_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- sm0_uid210_prodDivPreNormProd_uid60_fpDivTest(MULT,209)@6 + 2
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_a0 <= n0_uid193_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_b0 <= n1_uid194_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_q <= sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest(ADD,214)@8
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c);
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("0000000000" & sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_q);
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_b));
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_q <= lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_o(13 downto 0);
-- rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,163)@6
rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest_b <= lOAdded_uid58_fpDivTest_q(23 downto 15);
-- rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,160)@6
rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_in <= invY_uid54_fpDivTest_merged_bit_select_b(7 downto 0);
rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_in(7 downto 0);
-- rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,161)@6
rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest_q <= rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_b & GND_q;
-- sm1_uid209_prodDivPreNormProd_uid60_fpDivTest(MULT,208)@6 + 2
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_a0 <= rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest_q;
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_b0 <= rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest_b;
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q <= sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select(BITSELECT,333)@8
lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b <= sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q(4 downto 0);
lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c <= sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q(17 downto 5);
-- lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,215)@8
lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest_q <= lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_q & lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b;
-- aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,156)@6
aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_in <= lOAdded_uid58_fpDivTest_q(5 downto 0);
aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_in(5 downto 0);
-- aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest(CONSTANT,155)
aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest_q <= "000";
-- aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,157)@6
aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest_q <= aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_b & aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest_q;
-- aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,154)@6
aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest_b <= invY_uid54_fpDivTest_merged_bit_select_b(25 downto 17);
-- sm0_uid208_prodDivPreNormProd_uid60_fpDivTest(MULT,207)@6 + 2
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_a0 <= aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_b0 <= aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest_q;
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_q <= sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_s1;
-- topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,149)@6
topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest_b <= lOAdded_uid58_fpDivTest_q(23 downto 6);
-- topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,148)@6
topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest_b <= invY_uid54_fpDivTest_merged_bit_select_b(25 downto 8);
-- sm0_uid207_prodDivPreNormProd_uid60_fpDivTest(MULT,206)@6 + 2
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_a0 <= topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_b0 <= topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 36,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_q <= sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest(ADD,211)@8
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_q);
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_q);
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_b));
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_q <= lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_o(36 downto 0);
-- lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest(ADD,216)@8
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_q);
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest_q);
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_b));
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q <= lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_o(37 downto 0);
-- lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select(BITSELECT,334)@8
lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b <= lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q(4 downto 0);
lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c <= lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q(37 downto 5);
-- lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,220)@8
lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest_q <= lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_q & lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b;
-- osig_uid222_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,221)@8
osig_uid222_prodDivPreNormProd_uid60_fpDivTest_in <= lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest_q(35 downto 0);
osig_uid222_prodDivPreNormProd_uid60_fpDivTest_b <= osig_uid222_prodDivPreNormProd_uid60_fpDivTest_in(35 downto 9);
-- divValPreNormS_uid65_fpDivTest(BITSELECT,64)@8
divValPreNormS_uid65_fpDivTest_b <= osig_uid222_prodDivPreNormProd_uid60_fpDivTest_b(26 downto 1);
-- updatedY_uid16_fpDivTest(BITJOIN,15)@0
updatedY_uid16_fpDivTest_q <= GND_q & paddingY_uid15_fpDivTest_q;
-- fracYZero_uid15_fpDivTest(LOGICAL,16)@0 + 1
fracYZero_uid15_fpDivTest_a <= STD_LOGIC_VECTOR("0" & fracY_uid13_fpDivTest_b);
fracYZero_uid15_fpDivTest_qi <= "1" WHEN fracYZero_uid15_fpDivTest_a = updatedY_uid16_fpDivTest_q ELSE "0";
fracYZero_uid15_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYZero_uid15_fpDivTest_qi, xout => fracYZero_uid15_fpDivTest_q, clk => clk, aclr => areset );
-- redist14_fracYZero_uid15_fpDivTest_q_6(DELAY,349)
redist14_fracYZero_uid15_fpDivTest_q_6 : dspba_delay
GENERIC MAP ( width => 1, depth => 5, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYZero_uid15_fpDivTest_q, xout => redist14_fracYZero_uid15_fpDivTest_q_6_q, clk => clk, aclr => areset );
-- fracYPostZ_uid56_fpDivTest(LOGICAL,55)@6 + 1
fracYPostZ_uid56_fpDivTest_qi <= redist14_fracYZero_uid15_fpDivTest_q_6_q or invY_uid54_fpDivTest_merged_bit_select_c;
fracYPostZ_uid56_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYPostZ_uid56_fpDivTest_qi, xout => fracYPostZ_uid56_fpDivTest_q, clk => clk, aclr => areset );
-- redist1_fracYPostZ_uid56_fpDivTest_q_2(DELAY,336)
redist1_fracYPostZ_uid56_fpDivTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYPostZ_uid56_fpDivTest_q, xout => redist1_fracYPostZ_uid56_fpDivTest_q_2_q, clk => clk, aclr => areset );
-- divValPreNormTrunc_uid66_fpDivTest(MUX,65)@8
divValPreNormTrunc_uid66_fpDivTest_s <= redist1_fracYPostZ_uid56_fpDivTest_q_2_q;
divValPreNormTrunc_uid66_fpDivTest_combproc: PROCESS (divValPreNormTrunc_uid66_fpDivTest_s, divValPreNormS_uid65_fpDivTest_b, oFracXSE_mergedSignalTM_uid63_fpDivTest_q)
BEGIN
CASE (divValPreNormTrunc_uid66_fpDivTest_s) IS
WHEN "0" => divValPreNormTrunc_uid66_fpDivTest_q <= divValPreNormS_uid65_fpDivTest_b;
WHEN "1" => divValPreNormTrunc_uid66_fpDivTest_q <= oFracXSE_mergedSignalTM_uid63_fpDivTest_q;
WHEN OTHERS => divValPreNormTrunc_uid66_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- norm_uid67_fpDivTest(BITSELECT,66)@8
norm_uid67_fpDivTest_b <= STD_LOGIC_VECTOR(divValPreNormTrunc_uid66_fpDivTest_q(25 downto 25));
-- rndOp_uid75_fpDivTest(BITJOIN,74)@8
rndOp_uid75_fpDivTest_q <= norm_uid67_fpDivTest_b & paddingY_uid15_fpDivTest_q & VCC_q;
-- cstBiasM1_uid6_fpDivTest(CONSTANT,5)
cstBiasM1_uid6_fpDivTest_q <= "01111110";
-- expXmY_uid47_fpDivTest(SUB,46)@0 + 1
expXmY_uid47_fpDivTest_a <= STD_LOGIC_VECTOR("0" & expX_uid9_fpDivTest_b);
expXmY_uid47_fpDivTest_b <= STD_LOGIC_VECTOR("0" & expY_uid12_fpDivTest_b);
expXmY_uid47_fpDivTest_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXmY_uid47_fpDivTest_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
expXmY_uid47_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXmY_uid47_fpDivTest_a) - UNSIGNED(expXmY_uid47_fpDivTest_b));
END IF;
END PROCESS;
expXmY_uid47_fpDivTest_q <= expXmY_uid47_fpDivTest_o(8 downto 0);
-- redist6_expXmY_uid47_fpDivTest_q_8(DELAY,341)
redist6_expXmY_uid47_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 9, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => expXmY_uid47_fpDivTest_q, xout => redist6_expXmY_uid47_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- expR_uid48_fpDivTest(ADD,47)@8
expR_uid48_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist6_expXmY_uid47_fpDivTest_q_8_q(8)) & redist6_expXmY_uid47_fpDivTest_q_8_q));
expR_uid48_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00" & cstBiasM1_uid6_fpDivTest_q));
expR_uid48_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expR_uid48_fpDivTest_a) + SIGNED(expR_uid48_fpDivTest_b));
expR_uid48_fpDivTest_q <= expR_uid48_fpDivTest_o(9 downto 0);
-- divValPreNormHigh_uid68_fpDivTest(BITSELECT,67)@8
divValPreNormHigh_uid68_fpDivTest_in <= divValPreNormTrunc_uid66_fpDivTest_q(24 downto 0);
divValPreNormHigh_uid68_fpDivTest_b <= divValPreNormHigh_uid68_fpDivTest_in(24 downto 1);
-- divValPreNormLow_uid69_fpDivTest(BITSELECT,68)@8
divValPreNormLow_uid69_fpDivTest_in <= divValPreNormTrunc_uid66_fpDivTest_q(23 downto 0);
divValPreNormLow_uid69_fpDivTest_b <= divValPreNormLow_uid69_fpDivTest_in(23 downto 0);
-- normFracRnd_uid70_fpDivTest(MUX,69)@8
normFracRnd_uid70_fpDivTest_s <= norm_uid67_fpDivTest_b;
normFracRnd_uid70_fpDivTest_combproc: PROCESS (normFracRnd_uid70_fpDivTest_s, divValPreNormLow_uid69_fpDivTest_b, divValPreNormHigh_uid68_fpDivTest_b)
BEGIN
CASE (normFracRnd_uid70_fpDivTest_s) IS
WHEN "0" => normFracRnd_uid70_fpDivTest_q <= divValPreNormLow_uid69_fpDivTest_b;
WHEN "1" => normFracRnd_uid70_fpDivTest_q <= divValPreNormHigh_uid68_fpDivTest_b;
WHEN OTHERS => normFracRnd_uid70_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- expFracRnd_uid71_fpDivTest(BITJOIN,70)@8
expFracRnd_uid71_fpDivTest_q <= expR_uid48_fpDivTest_q & normFracRnd_uid70_fpDivTest_q;
-- expFracPostRnd_uid76_fpDivTest(ADD,75)@8
expFracPostRnd_uid76_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((35 downto 34 => expFracRnd_uid71_fpDivTest_q(33)) & expFracRnd_uid71_fpDivTest_q));
expFracPostRnd_uid76_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000000000" & rndOp_uid75_fpDivTest_q));
expFracPostRnd_uid76_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracPostRnd_uid76_fpDivTest_a) + SIGNED(expFracPostRnd_uid76_fpDivTest_b));
expFracPostRnd_uid76_fpDivTest_q <= expFracPostRnd_uid76_fpDivTest_o(34 downto 0);
-- excRPreExc_uid79_fpDivTest(BITSELECT,78)@8
excRPreExc_uid79_fpDivTest_in <= expFracPostRnd_uid76_fpDivTest_q(31 downto 0);
excRPreExc_uid79_fpDivTest_b <= excRPreExc_uid79_fpDivTest_in(31 downto 24);
-- invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@8
invExpXIsMax_uid43_fpDivTest_q <= not (redist9_expXIsMax_uid38_fpDivTest_q_8_q);
-- InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@8
InvExpXIsZero_uid44_fpDivTest_q <= not (redist10_excZ_y_uid37_fpDivTest_q_8_q);
-- excR_y_uid45_fpDivTest(LOGICAL,44)@8
excR_y_uid45_fpDivTest_q <= InvExpXIsZero_uid44_fpDivTest_q and invExpXIsMax_uid43_fpDivTest_q;
-- excXIYR_uid93_fpDivTest(LOGICAL,92)@8
excXIYR_uid93_fpDivTest_q <= excI_x_uid27_fpDivTest_q and excR_y_uid45_fpDivTest_q;
-- excXIYZ_uid92_fpDivTest(LOGICAL,91)@8
excXIYZ_uid92_fpDivTest_q <= excI_x_uid27_fpDivTest_q and redist10_excZ_y_uid37_fpDivTest_q_8_q;
-- expRExt_uid80_fpDivTest(BITSELECT,79)@8
expRExt_uid80_fpDivTest_b <= STD_LOGIC_VECTOR(expFracPostRnd_uid76_fpDivTest_q(34 downto 24));
-- expOvf_uid84_fpDivTest(COMPARE,83)@8
expOvf_uid84_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((12 downto 11 => expRExt_uid80_fpDivTest_b(10)) & expRExt_uid80_fpDivTest_b));
expOvf_uid84_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000" & cstAllOWE_uid18_fpDivTest_q));
expOvf_uid84_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid84_fpDivTest_a) - SIGNED(expOvf_uid84_fpDivTest_b));
expOvf_uid84_fpDivTest_n(0) <= not (expOvf_uid84_fpDivTest_o(12));
-- invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@8
invExpXIsMax_uid29_fpDivTest_q <= not (redist12_expXIsMax_uid24_fpDivTest_q_8_q);
-- InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@8
InvExpXIsZero_uid30_fpDivTest_q <= not (redist13_excZ_x_uid23_fpDivTest_q_8_q);
-- excR_x_uid31_fpDivTest(LOGICAL,30)@8
excR_x_uid31_fpDivTest_q <= InvExpXIsZero_uid30_fpDivTest_q and invExpXIsMax_uid29_fpDivTest_q;
-- excXRYROvf_uid91_fpDivTest(LOGICAL,90)@8
excXRYROvf_uid91_fpDivTest_q <= excR_x_uid31_fpDivTest_q and excR_y_uid45_fpDivTest_q and expOvf_uid84_fpDivTest_n;
-- excXRYZ_uid90_fpDivTest(LOGICAL,89)@8
excXRYZ_uid90_fpDivTest_q <= excR_x_uid31_fpDivTest_q and redist10_excZ_y_uid37_fpDivTest_q_8_q;
-- excRInf_uid94_fpDivTest(LOGICAL,93)@8
excRInf_uid94_fpDivTest_q <= excXRYZ_uid90_fpDivTest_q or excXRYROvf_uid91_fpDivTest_q or excXIYZ_uid92_fpDivTest_q or excXIYR_uid93_fpDivTest_q;
-- xRegOrZero_uid87_fpDivTest(LOGICAL,86)@8
xRegOrZero_uid87_fpDivTest_q <= excR_x_uid31_fpDivTest_q or redist13_excZ_x_uid23_fpDivTest_q_8_q;
-- regOrZeroOverInf_uid88_fpDivTest(LOGICAL,87)@8
regOrZeroOverInf_uid88_fpDivTest_q <= xRegOrZero_uid87_fpDivTest_q and excI_y_uid41_fpDivTest_q;
-- expUdf_uid81_fpDivTest(COMPARE,80)@8
expUdf_uid81_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00000000000" & GND_q));
expUdf_uid81_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((12 downto 11 => expRExt_uid80_fpDivTest_b(10)) & expRExt_uid80_fpDivTest_b));
expUdf_uid81_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid81_fpDivTest_a) - SIGNED(expUdf_uid81_fpDivTest_b));
expUdf_uid81_fpDivTest_n(0) <= not (expUdf_uid81_fpDivTest_o(12));
-- regOverRegWithUf_uid86_fpDivTest(LOGICAL,85)@8
regOverRegWithUf_uid86_fpDivTest_q <= expUdf_uid81_fpDivTest_n and excR_x_uid31_fpDivTest_q and excR_y_uid45_fpDivTest_q;
-- zeroOverReg_uid85_fpDivTest(LOGICAL,84)@8
zeroOverReg_uid85_fpDivTest_q <= redist13_excZ_x_uid23_fpDivTest_q_8_q and excR_y_uid45_fpDivTest_q;
-- excRZero_uid89_fpDivTest(LOGICAL,88)@8
excRZero_uid89_fpDivTest_q <= zeroOverReg_uid85_fpDivTest_q or regOverRegWithUf_uid86_fpDivTest_q or regOrZeroOverInf_uid88_fpDivTest_q;
-- concExc_uid98_fpDivTest(BITJOIN,97)@8
concExc_uid98_fpDivTest_q <= excRNaN_uid97_fpDivTest_q & excRInf_uid94_fpDivTest_q & excRZero_uid89_fpDivTest_q;
-- excREnc_uid99_fpDivTest(LOOKUP,98)@8
excREnc_uid99_fpDivTest_combproc: PROCESS (concExc_uid98_fpDivTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExc_uid98_fpDivTest_q) IS
WHEN "000" => excREnc_uid99_fpDivTest_q <= "01";
WHEN "001" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "010" => excREnc_uid99_fpDivTest_q <= "10";
WHEN "011" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "100" => excREnc_uid99_fpDivTest_q <= "11";
WHEN "101" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "110" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "111" => excREnc_uid99_fpDivTest_q <= "00";
WHEN OTHERS => -- unreachable
excREnc_uid99_fpDivTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExc_uid107_fpDivTest(MUX,106)@8
expRPostExc_uid107_fpDivTest_s <= excREnc_uid99_fpDivTest_q;
expRPostExc_uid107_fpDivTest_combproc: PROCESS (expRPostExc_uid107_fpDivTest_s, cstAllZWE_uid20_fpDivTest_q, excRPreExc_uid79_fpDivTest_b, cstAllOWE_uid18_fpDivTest_q)
BEGIN
CASE (expRPostExc_uid107_fpDivTest_s) IS
WHEN "00" => expRPostExc_uid107_fpDivTest_q <= cstAllZWE_uid20_fpDivTest_q;
WHEN "01" => expRPostExc_uid107_fpDivTest_q <= excRPreExc_uid79_fpDivTest_b;
WHEN "10" => expRPostExc_uid107_fpDivTest_q <= cstAllOWE_uid18_fpDivTest_q;
WHEN "11" => expRPostExc_uid107_fpDivTest_q <= cstAllOWE_uid18_fpDivTest_q;
WHEN OTHERS => expRPostExc_uid107_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid100_fpDivTest(CONSTANT,99)
oneFracRPostExc2_uid100_fpDivTest_q <= "00000000000000000000001";
-- fracRPreExc_uid78_fpDivTest(BITSELECT,77)@8
fracRPreExc_uid78_fpDivTest_in <= expFracPostRnd_uid76_fpDivTest_q(23 downto 0);
fracRPreExc_uid78_fpDivTest_b <= fracRPreExc_uid78_fpDivTest_in(23 downto 1);
-- fracRPostExc_uid103_fpDivTest(MUX,102)@8
fracRPostExc_uid103_fpDivTest_s <= excREnc_uid99_fpDivTest_q;
fracRPostExc_uid103_fpDivTest_combproc: PROCESS (fracRPostExc_uid103_fpDivTest_s, paddingY_uid15_fpDivTest_q, fracRPreExc_uid78_fpDivTest_b, oneFracRPostExc2_uid100_fpDivTest_q)
BEGIN
CASE (fracRPostExc_uid103_fpDivTest_s) IS
WHEN "00" => fracRPostExc_uid103_fpDivTest_q <= paddingY_uid15_fpDivTest_q;
WHEN "01" => fracRPostExc_uid103_fpDivTest_q <= fracRPreExc_uid78_fpDivTest_b;
WHEN "10" => fracRPostExc_uid103_fpDivTest_q <= paddingY_uid15_fpDivTest_q;
WHEN "11" => fracRPostExc_uid103_fpDivTest_q <= oneFracRPostExc2_uid100_fpDivTest_q;
WHEN OTHERS => fracRPostExc_uid103_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- divR_uid110_fpDivTest(BITJOIN,109)@8
divR_uid110_fpDivTest_q <= sRPostExc_uid109_fpDivTest_q & expRPostExc_uid107_fpDivTest_q & fracRPostExc_uid103_fpDivTest_q;
-- xOut(GPOUT,4)@8
q <= divR_uid110_fpDivTest_q;
END normal;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_sMuxAltr.vhd | 20 | 3446 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity alt_dspbuilder_sMuxAltr is
generic ( lpm_pipeline : natural:=0;
lpm_size : positive:=5;
lpm_widths : positive:=3;
lpm_width : positive:=8;
SelOneHot : natural:=0);
PORT ( clock : in std_logic ;
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
ena : in std_logic := '1';
data : in std_logic_vector (lpm_width*lpm_size-1 downto 0);
sel : in std_logic_vector (lpm_widths-1 downto 0);
result : out std_logic_vector (lpm_width-1 downto 0));
end alt_dspbuilder_sMuxAltr;
architecture synth of alt_dspbuilder_sMuxAltr is
function salive( ipp : integer; w : natural ) return std_logic_vector is
variable sxbus : std_logic_vector(w-1 downto 0);
begin
for i in 0 to w-1 loop
if ipp=i then
sxbus(i) :='1';
else
sxbus(i) :='0';
end if;
end loop;
return sxbus;
end;
signal selint : std_logic_vector(nbitnecessary(lpm_size)-1 downto 0);
signal dataa : std_logic_2d (lpm_size-1 downto 0, lpm_width-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gnoh:if SelOneHot=0 generate
selint <= sel;
end generate gnoh;
g_one_hot:if SelOneHot>0 generate
gi:for i in 0 to lpm_size-1 generate
selint <= int2ustd(i,nbitnecessary(lpm_size)) when sel = salive(i, lpm_size) else (others=>'Z');
end generate gi;
end generate g_one_hot;
g2d:for i in 1 to lpm_size generate
gw:for j in 0 to lpm_width-1 generate
dataa(i-1,j) <= data(j+(i-1)*lpm_width);
end generate gw;
end generate g2d;
gp:if lpm_pipeline>0 generate
U0 : lpm_mux generic map ( lpm_pipeline => lpm_pipeline,
lpm_size => lpm_size,
lpm_widths => nbitnecessary(lpm_size),
lpm_width => lpm_width,
lpm_type => "LPM_MUX")
port map ( sel => selint,
clken => ena,
aclr => aclr_i,
clock => clock,
data => dataa,
result => result);
end generate gp;
gc:if lpm_pipeline=0 generate
U0 : lpm_mux generic map ( lpm_size => lpm_size,
lpm_widths => nbitnecessary(lpm_size),
lpm_width => lpm_width,
lpm_type => "LPM_MUX")
port map ( sel => selint,
data => dataa,
result => result);
end generate gc;
end synth;
| mit |
VladisM/MARK_II | VHDL/src/uart/reciever.vhd | 1 | 9255 | -- Reciever
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reciever is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
rx: in std_logic;
baud16_clk_en: in std_logic;
rx_data: out unsigned(7 downto 0);
rx_done: out std_logic
);
end entity reciever;
architecture reciever_arch of reciever is
type rx_state_type is (idle, start_sync, wait_for_sync, sync, wait_b0, get_b0, wait_b1, get_b1,wait_b2, get_b2,
wait_b3, get_b3,wait_b4, get_b4,wait_b5, get_b5,wait_b6, get_b6,wait_b7, get_b7,
wait_stopbit, store_data_0, store_data_1);
signal state: rx_state_type; -- state for RX FSM
signal sipo_val: unsigned(7 downto 0);
signal rx_rec_com, res_counter, shift_sipo_reg: std_logic; -- control signals for RX FSM
signal baud_clk_en: std_logic; -- this is an baud clock
signal count: unsigned(3 downto 0); -- this is rx counter value
begin
sipo_reg:
process(res, clk, rx, shift_sipo_reg) is
variable sipo_var: unsigned(7 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
sipo_var := (others => '0');
elsif shift_sipo_reg = '1' then
sipo_var(6 downto 0) := sipo_var(7 downto 1);
sipo_var(7) := rx;
end if;
end if;
sipo_val <= sipo_var;
end process;
rx_out_reg:
process(res, clk, rx_rec_com) is
variable out_reg: unsigned(7 downto 0);
begin
if rising_edge(clk) then
if(res = '1') then
out_reg := (others => '0');
elsif rx_rec_com = '1' then
out_reg := sipo_val;
end if;
end if;
rx_data <= out_reg;
end process;
rxcounter:
process(clk, res) is
variable counter: unsigned(3 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
counter := (others => '0');
elsif res_counter = '1' then
counter := (others => '0');
elsif baud16_clk_en = '1' then
counter := counter + 1;
end if;
end if;
count <= counter;
end process;
process(count, baud16_clk_en) is
begin
if count = x"F" then
baud_clk_en <= baud16_clk_en;
else
baud_clk_en <= '0';
end if;
end process;
process(clk, res, count, baud_clk_en, rx) is
begin
if rising_edge(clk) then
if res = '1' then
state <= idle;
else
case state is
when idle =>
if ((rx = '0') and (en = '1')) then
state <= start_sync;
else
state <= idle;
end if;
when start_sync => state <= wait_for_sync;
when wait_for_sync =>
if count = "0111" then
state <= sync;
else
state <= wait_for_sync;
end if;
when sync => state <= wait_b0;
when wait_b0 =>
if baud_clk_en = '1' then
state <= get_b0;
else
state <= wait_b0;
end if;
when get_b0 => state <= wait_b1;
when wait_b1 =>
if baud_clk_en = '1' then
state <= get_b1;
else
state <= wait_b1;
end if;
when get_b1 => state <= wait_b2;
when wait_b2 =>
if baud_clk_en = '1' then
state <= get_b2;
else
state <= wait_b2;
end if;
when get_b2 => state <= wait_b3;
when wait_b3 =>
if baud_clk_en = '1' then
state <= get_b3;
else
state <= wait_b3;
end if;
when get_b3 => state <= wait_b4;
when wait_b4 =>
if baud_clk_en = '1' then
state <= get_b4;
else
state <= wait_b4;
end if;
when get_b4 => state <= wait_b5;
when wait_b5 =>
if baud_clk_en = '1' then
state <= get_b5;
else
state <= wait_b5;
end if;
when get_b5 => state <= wait_b6;
when wait_b6 =>
if baud_clk_en = '1' then
state <= get_b6;
else
state <= wait_b6;
end if;
when get_b6 => state <= wait_b7;
when wait_b7 =>
if baud_clk_en = '1' then
state <= get_b7;
else
state <= wait_b7;
end if;
when get_b7 => state <= wait_stopbit;
when wait_stopbit =>
if baud_clk_en = '1' then
state <= store_data_0;
else
state <= wait_stopbit;
end if;
when store_data_0 => state <= store_data_1;
when store_data_1 => state <= idle;
end case;
end if;
end if;
end process;
process(state) is
begin
case state is
when idle => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when start_sync => rx_rec_com <= '0'; res_counter <= '1'; shift_sipo_reg <= '0'; rx_done <= '0';
when wait_for_sync => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when sync => rx_rec_com <= '0'; res_counter <= '1'; shift_sipo_reg <= '0'; rx_done <= '0';
when wait_b0 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b0 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b2 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b2 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b3 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b3 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b4 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b4 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b5 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b5 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b6 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b6 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b7 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b7 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_stopbit => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when store_data_0 => rx_rec_com <= '1'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when store_data_1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '1';
end case;
end process;
end architecture reciever_arch;
| mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_port_GN6TDLHAW6.vhd | 13 | 487 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN6TDLHAW6 is
port(
input : in std_logic_vector(1 downto 0);
output : out std_logic_vector(1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GN6TDLHAW6 is
Begin
-- Straight Bypass block
output <= input;
end architecture; | mit |
Nic30/hwtLib | hwtLib/tests/serialization/TmpVarExample1.vhd | 1 | 661 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TmpVarExample1 IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF TmpVarExample1 IS
BEGIN
assig_process_b: PROCESS(a)
VARIABLE tmpTypeConv_0 : BOOLEAN;
VARIABLE tmpTypeConv_1 : BOOLEAN;
BEGIN
tmpTypeConv_0 := a(15 DOWNTO 0) = X"0001";
tmpTypeConv_1 := a(31 DOWNTO 16) = X"0001";
IF tmpTypeConv_0 AND tmpTypeConv_1 THEN
b <= X"00000000";
ELSE
b <= X"00000001";
END IF;
END PROCESS;
END ARCHITECTURE;
| mit |
Nic30/hwtLib | hwtLib/examples/statements/FsmExample.vhd | 1 | 1852 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY FsmExample IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
clk : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF FsmExample IS
TYPE st_t IS (a_0, b_0, aAndB);
SIGNAL st : st_t := a_0;
SIGNAL st_next : st_t;
BEGIN
assig_process_dout: PROCESS(st)
BEGIN
CASE st IS
WHEN a_0 =>
dout <= "001";
WHEN b_0 =>
dout <= "010";
WHEN OTHERS =>
dout <= "011";
END CASE;
END PROCESS;
assig_process_st: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
st <= a_0;
ELSE
st <= st_next;
END IF;
END IF;
END PROCESS;
assig_process_st_next: PROCESS(a, b, st)
BEGIN
CASE st IS
WHEN a_0 =>
IF (a AND b) = '1' THEN
st_next <= aandb;
ELSIF b = '1' THEN
st_next <= b_0;
ELSE
st_next <= st;
END IF;
WHEN b_0 =>
IF (a AND b) = '1' THEN
st_next <= aandb;
ELSIF a = '1' THEN
st_next <= a_0;
ELSE
st_next <= st;
END IF;
WHEN OTHERS =>
IF (a AND NOT b) = '1' THEN
st_next <= a_0;
ELSIF (NOT a AND b) = '1' THEN
st_next <= b_0;
ELSE
st_next <= st;
END IF;
END CASE;
END PROCESS;
END ARCHITECTURE;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_constant_GNZEH3JAKA.vhd | 20 | 592 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNZEH3JAKA is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000001111";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNZEH3JAKA is
Begin
-- Constant
output <= "000000000000000000001111";
end architecture; | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_constant_GNZEH3JAKA.vhd | 20 | 592 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNZEH3JAKA is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000001111";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNZEH3JAKA is
Begin
-- Constant
output <= "000000000000000000001111";
end architecture; | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_vecseq.vhd | 20 | 2951 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_vecseq is
generic (
SequenceLength : positive :=15;
SequenceValue : std_logic_vector := "100001110001001"
);
port (
clock : in std_logic ;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
yout : out std_logic
);
end alt_dspbuilder_vecseq;
architecture seq_SYNTH of alt_dspbuilder_vecseq is
signal clr_signal : STD_LOGIC;
signal lclr_signal : STD_LOGIC;
signal counter : std_logic_vector(ToNatural(nbitnecessary(SequenceLength)-1) downto 0);
signal yout_int : STD_LOGIC;
signal yout_comb : STD_LOGIC;
begin
u0: alt_dspbuilder_sAltrBitPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion)
port map (d => yout_int, r => yout);
fixed_constant:if SequenceLength=1 generate
yout_int <=SequenceValue(0);
end generate fixed_constant;
resetable_sequence:if SequenceLength>1 generate
process(clock, aclr)
begin
if aclr='1' then
yout_int <= '0';
counter <= (OTHERS => '0');
elsif clock'event and clock='1' then
if sclr='1' then
yout_int <= '0';
counter <= (OTHERS => '0');
elsif ena='1' then
if counter < int2ustd(SequenceLength-1 ,nbitnecessary(SequenceLength)+1) then
counter <= counter + '1';
else
counter <= (OTHERS => '0');
end if;
yout_int <= yout_comb;
end if;
end if;
end process;
gen:for i in 0 to SequenceLength-1 generate
yout_comb <= SequenceValue(i) when (counter=int2ustd(i,nbitnecessary(SequenceLength)+1)) else 'Z';
end generate;
end generate resetable_sequence;
end seq_SYNTH;
| mit |
Nic30/hwtLib | hwtLib/tests/serialization/SimpleUnitReanamedPort1.vhd | 1 | 528 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleUnitReanamedPort1 IS
PORT(
a_in_hdl_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
a_in_hdl_rd : OUT STD_LOGIC;
a_in_hdl_vld : IN STD_LOGIC;
b_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
b_rd : IN STD_LOGIC;
b_vld : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleUnitReanamedPort1 IS
BEGIN
a_in_hdl_rd <= b_rd;
b_data <= a_in_hdl_data;
b_vld <= a_in_hdl_vld;
END ARCHITECTURE;
| mit |
VladisM/MARK_II | VHDL/src/cpu/qip/fp_addsub/fp_addsub_sim/dspba_library_package.vhd | 12 | 2231 | -- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
| mit |
VladisM/MARK_II | VHDL/src/cpu/qip/fp_cmp_gt/fp_cmp_gt_sim/dspba_library.vhd | 12 | 11603 | -- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
| mit |
VladisM/MARK_II | VHDL/src/systimer/systim.vhd | 1 | 3467 | -- System timer for MARK-II
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity systim is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
intrq: out std_logic
);
end entity systim;
architecture systim_arch of systim is
signal counter: unsigned(23 downto 0);
--control register
signal control_reg: unsigned(24 downto 0);
signal top: unsigned(23 downto 0);
signal timeren: std_logic;
signal compare_match: std_logic;
--for bus interface
signal reg_sel: std_logic_vector(1 downto 0);
signal clear_from_write: std_logic; --clear the counter when value is writen to its register
begin
--this is core timer
process (clk, res, compare_match, clear_from_write)
variable cnt: unsigned(23 downto 0) := (others => '0');
begin
if(rising_edge(clk)) then
if (res = '1' or clear_from_write = '1' or compare_match = '1') then
cnt := (others => '0');
elsif(timeren = '1') then
cnt := cnt + 1;
end if;
end if;
counter <= cnt;
end process;
--comparator
process(top, counter) is begin
if(counter = top) then
compare_match <= '1';
else
compare_match <= '0';
end if;
end process;
--for interrupts
intrq <= compare_match;
--control
top <= control_reg(23 downto 0);
timeren <= control_reg(24);
-----------------
--bus interface
--chip select
process(address) is begin
if (unsigned(address) = BASE_ADDRESS) then
reg_sel <= "01"; -- control register
elsif (unsigned(address) = (BASE_ADDRESS + 1)) then
reg_sel <= "10"; -- counter
else
reg_sel <= "00";
end if;
end process;
--registers
process(clk, res, WR, data_mosi, reg_sel) is begin
if rising_edge(clk) then
if res = '1' then
control_reg <= (others => '0');
elsif (reg_sel = "01" and WR = '1') then
control_reg <= unsigned(data_mosi(24 downto 0));
end if;
end if;
end process;
--output from registers
data_miso <= "0000000" & std_logic_vector(control_reg) when (RD = '1' and reg_sel = "01") else
x"00" & std_logic_vector(counter) when (RD = '1' and reg_sel = "10") else (others => 'Z');
--generate signal when there is write acces to counter
process(WR, reg_sel) is begin
if(WR = '1' and reg_sel = "10") then
clear_from_write <= '1';
else
clear_from_write <= '0';
end if;
end process;
ack <= '1' when ((WR = '1' and reg_sel /= "00") or (RD = '1' and reg_sel /= "00")) else '0';
end architecture systim_arch;
| mit |
Nic30/hwtLib | hwtLib/tests/serialization/AssignToASliceOfReg3a.vhd | 1 | 2417 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Something not assigned by index at the end and then whole signal assigned.
--
ENTITY AssignToASliceOfReg3a IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg3a IS
SIGNAL r : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000";
SIGNAL r_next : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_23downto16 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_31downto24 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"00000000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_31downto24 & r_next_23downto16 & r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, r)
BEGIN
CASE data_in_addr IS
WHEN "00" =>
r_next_7downto0 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_31downto24 <= r(31 DOWNTO 24);
WHEN "01" =>
r_next_15downto8 <= data_in_data;
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_31downto24 <= r(31 DOWNTO 24);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN "10" =>
r_next_23downto16 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_31downto24 <= r(31 DOWNTO 24);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN OTHERS =>
r_next_7downto0 <= X"7B";
r_next_15downto8 <= X"00";
r_next_23downto16 <= X"00";
r_next_31downto24 <= X"00";
END CASE;
END PROCESS;
END ARCHITECTURE;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_delay.vhd | 1 | 4983 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_delay_GND2PGZRBZ is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "1";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GND2PGZRBZ;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(8-1 downto 0) := (others=>'0');
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNUECIBFDH_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_0: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GND2PGZRBZ_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "1") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GND2PGZRBZ_1: alt_dspbuilder_delay_GND2PGZRBZ
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "1", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNHYCSAEGT_2: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNHYCSAEGT_2: alt_dspbuilder_delay_GNHYCSAEGT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNVTJPHWYT_3: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_3: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "1") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_cast_GN6OMCQQS7.vhd | 8 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN6OMCQQS7 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN6OMCQQS7 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 16 + 1 ,
width_inr=> 8,
width_outl=> 8,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_sAltrBitPropagate.vhd | 20 | 1572 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
| mit |
capitanov/MinesweeperFPGA | src/game_cores/cl_square.vhd | 1 | 3602 | --------------------------------------------------------------------------------
--
-- Title : cl_square.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for square 8x8
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
entity cl_square is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
show_disp : in array8x8;
--data_hide : in std_logic;
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end cl_square;
architecture cl_square of cl_square is
signal data_rom : std_logic_vector(7 downto 0);
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal dataxy : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal x_z : std_logic_vector(2 downto 0);
signal y_charz : std_logic_vector(3 downto 0);
constant color : std_logic_vector(2 downto 0):="001";
begin
y_charz <= y_char(3 downto 0) when rising_edge(clk);
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
pr_select3: process(clk, reset) is
begin
if reset = '0' then
dataxy <= '0';
elsif rising_edge(clk) then
if display = '0' then
dataxy <= '0';
else
if ((xstart <= x_in) and (x_in < xend)) then
if ((ystart <= y_in) and (y_in < yend)) then
dataxy <= not show_disp(conv_integer(x_in(2 downto 0)))(conv_integer(y_in(2 downto 0)));
else
dataxy <= '0';
end if;
else
dataxy <= '0';
end if;
end if;
end if;
end process;
pr_new_box: process(clk, reset)
begin
if reset = '0' then
data_rom <= x"00";
elsif rising_edge(clk) then
if (dataxy = '1') then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"FE";
when x"1" => data_rom <= x"FE";
when x"2" => data_rom <= x"FE";
when x"3" => data_rom <= x"FE";
when x"4" => data_rom <= x"FE";
when x"5" => data_rom <= x"FE";
when x"6" => data_rom <= x"FE";
when x"7" => data_rom <= x"FE";
when x"8" => data_rom <= x"FE";
when x"9" => data_rom <= x"FE";
when x"A" => data_rom <= x"FE";
when x"B" => data_rom <= x"FE";
when x"C" => data_rom <= x"FE";
when x"D" => data_rom <= x"FE";
when x"E" => data_rom <= x"FE";
when others => data_rom <= x"00";
end case;
else
data_rom <= x"00";
end if;
end if;
end process;
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
x_z <= x_del when rising_edge(clk);
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
data <= data_rom(to_integer(unsigned(x_z)));
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_square; | mit |
Wynjones1/VHDL-Tests | simu/memory_tb.vhd | 1 | 1737 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
entity memory_tb is
end memory_tb ;
architecture rtl of memory_tb is
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal address : std_logic_vector(15 downto 0);
signal we : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_out : std_logic_vector(7 downto 0) := (others => '0');
component memory is
port( clk : in std_logic;
address : in std_logic_vector;
we : in std_logic;
data_in : in std_logic_vector;
data_out : out std_logic_vector);
end component;
begin
mem0 : memory port map (clk, address, we, data_in, data_out);
-- Generate reset signal
process begin
reset <= '1';
wait for 30 ns;
reset <= '0';
wait;
end process;
-- Generate the clock signal
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
process(clk)
variable next_address : std_logic_vector(15 downto 0);
variable state : integer := 0;
begin
if reset = '1' then
we <= '0';
data_in <= (others => '0');
address <= (others => '0');
state := 0;
elsif rising_edge(clk) then
if state = 0 then
next_address := std_logic_vector(unsigned(address) + 1);
we <= '1';
data_in <= next_address(7 downto 0);
address <= next_address;
if unsigned(next_address) = 0 then
state := 1;
end if;
else
next_address := std_logic_vector(unsigned(address) + 1);
we <= '0';
address <= next_address;
if unsigned(next_address) = 0 then
state := 0;
end if;
end if;
end if;
end process;
end rtl;
| mit |
laurivosandi/vhdl-exercise | carry_ripple_adder.vhd | 1 | 946 | library ieee;
use ieee.std_logic_1164.all;
-- This file corresponds to 4-bit carry ripple adder
entity carry_ripple_adder is
port (
a : in std_logic_vector (3 downto 0); -- First operand
b : in std_logic_vector (3 downto 0); -- Second operand
ci : in std_logic; -- Carry in
s : out std_logic_vector (3 downto 0); -- Result
co : out std_logic -- Carry out
);
end;
architecture behavioral of carry_ripple_adder is
signal c : std_logic_vector(2 downto 0);
component full_adder
port ( ci, a, b : in std_logic; s, co : out std_logic);
end component;
begin
stage0: full_adder port map ( ci, a(0), b(0), s(0), c(0));
stage1: full_adder port map (c(0), a(1), b(1), s(1), c(1));
stage2: full_adder port map (c(1), a(2), b(2), s(2), c(2));
stage3: full_adder port map (c(2), a(3), b(3), s(3), co );
end behavioral;
| mit |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_dverif.vhd | 11 | 5803 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| mit |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| mit |
Mafus1/bluetooth-receiver | source/infrastructure.vhd | 1 | 812 | -- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY infrastructure IS
PORT(
clk : IN std_logic;
reset_n : IN std_logic;
serdata_in : IN std_logic;
serdata_out : OUT std_logic
);
END infrastructure;
-- Architecture Declaration
ARCHITECTURE rtl OF infrastructure IS
-- Signals & Constants Declaration
SIGNAL q1, q2: std_logic:= '0';
-- Begin Architecture
BEGIN
-------------------------------------------
-- Process for registers (flip-flops)
-------------------------------------------
flip_flops : PROCESS(clk, reset_n, q1)
BEGIN
IF reset_n = '0' THEN
q1 <= '0';
q2 <= '0';
ELSIF rising_edge(clk) THEN
q1 <= serdata_in;
q2 <= q1;
END IF;
END PROCESS flip_flops;
serdata_out <= q2;
END rtl;
| mit |
kevintownsend/R3 | coregen/fifo_69x512_hf/simulation/fg_tb_pctrl.vhd | 20 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| mit |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_pctrl.vhd | 20 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| mit |
TMU-VHDL-team2/sqrt | components/mdr.vhd | 2 | 886 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0)
);
end mdr;
architecture BEHAVIOR of mdr is
begin
process(clock) begin
if(clock'event and clock = '1')then
if(latch = '1')then
if(sel = '0')then
data <= busC;
elsif(sel = '1')then
data <= memo;
else
null;
end if;
else
null;
end if;
else
null;
end if;
end process;
end BEHAVIOR;
| mit |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_top.vhd | 2 | 5679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 40
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/simulation/fg_tb_dverif.vhd | 35 | 5486 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| mit |
TMU-VHDL-team2/sqrt | components/old_data/pr_32.vhd | 1 | 626 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pr is
port(clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(31 downto 0);
S_PR_F : out std_logic_vector(15 downto 0));
end pr;
architecture BEHAVIOR of pr is
signal rst : std_logic_vector(15 downto 0) := "0000000010000000";
begin
S_PR_F <= rst;
process(clk) begin
if clk'event and clk = '1' then
if S_PRlat = '1' then
rst <= S_BUS_C(15 downto 0);
elsif S_s_inc = '1' then
rst <= rst + 1;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
| mit |
dugagjinll/MIPS | MIPS/registerFile.vhd | 1 | 1976 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY registerFile IS
GENERIC (
B : INTEGER := 32; --number of bits
W : INTEGER := 5 --number of address bits
);
PORT (
readRegister1 : IN std_logic_vector (W - 1 DOWNTO 0);
readRegister2 : IN std_logic_vector (W - 1 DOWNTO 0);
writeRegister : IN std_logic_vector (W - 1 DOWNTO 0);
writeData : IN std_logic_vector (B - 1 DOWNTO 0);
registerWrite : IN std_logic;
readData1 : OUT std_logic_vector (B - 1 DOWNTO 0);
readData2 : OUT std_logic_vector (B - 1 DOWNTO 0)
);
END registerFile;
ARCHITECTURE Behavioral OF registerFile IS
-- create type 2d array
TYPE reg_file_type IS ARRAY (0 TO 2 ** W - 1) OF std_logic_vector(B - 1 DOWNTO 0);
-- create 32 registers of 32 bits
SIGNAL array_reg : reg_file_type := (
x"00000000", --$zero
x"11111111", --$at
x"22222222", --$v0
x"33333333", --$v1
x"44444444", --$a0
x"55555555", --$a1
x"66666666", --$a2
x"77777777", --$a3
x"88888888", --$t0
x"99999999", --$t1
x"aaaaaaaa", --$t2
x"bbbbbbbb", --$t3
x"cccccccc", --$t4
x"dddddddd", --$t5
x"eeeeeeee", --$t6
x"ffffffff", --$t7
x"00000000", --$s0
x"11111111", --$s1
x"22222222", --$s2
x"33333333", --$s3
x"44444444", --$s4
x"55555555", --$s5
x"66666666", --$s6
x"77777777", --$s7
x"88888888", --$t8
x"99999999", --$t9
x"aaaaaaaa", --$k0
x"bbbbbbbb", --$k1
x"10008000", --$global pointer
x"7FFFF1EC", --$stack pointer
x"eeeeeeee", --$frame pointer
x"ffffffff" --$return address
);
BEGIN
PROCESS (registerWrite) -- pulse on write
BEGIN
-- writeRegister is the register which we want to write to
-- writeData is the data which we dant to save
IF (registerWrite = '1') THEN
array_reg(to_integer(unsigned(writeRegister))) <= writeData;
END IF;
END PROCESS;
-- read port
readData1 <= array_reg(to_integer(unsigned(readRegister1)));
readData2 <= array_reg(to_integer(unsigned(readRegister2)));
END Behavioral; | mit |
kevintownsend/R3 | coregen/fifo_138x16_shift/simulation/fg_tb_pkg.vhd | 1 | 11255 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_138x16_shift_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit |
kevintownsend/R3 | coregen/fifo_138x16_shift/simulation/fg_tb_synth.vhd | 1 | 9659 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 138,
C_DOUT_WIDTH => 138,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 138,
C_DIN_WIDTH => 138,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 138,
C_DIN_WIDTH => 138,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_138x16_shift_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit |
kevintownsend/R3 | coregen/fifo_138x512/example_design/fifo_138x512_top_wrapper.vhd | 1 | 19002 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_138x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_138x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(138-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(138-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_138x512_top_wrapper;
architecture xilinx of fifo_138x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_138x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_138x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit |
kevintownsend/R3 | coregen/fifo_96x512/simulation/fg_tb_dgen.vhd | 11 | 4510 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 12 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| mit |
kevintownsend/R3 | coregen/fifo_fwft_64x512/simulation/fg_tb_synth.vhd | 1 | 9294 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_fwft_64x512_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit |
kevintownsend/R3 | coregen/fifo_36x512_hf/example_design/fifo_36x512_hf_top_wrapper.vhd | 1 | 19220 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_36x512_hf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_36x512_hf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(36-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(36-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_36x512_hf_top_wrapper;
architecture xilinx of fifo_36x512_hf_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_36x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(36-1 DOWNTO 0);
DOUT : OUT std_logic_vector(36-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_36x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit |
kevintownsend/R3 | coregen/fifo_64x512_hf/example_design/fifo_64x512_hf_top_wrapper.vhd | 1 | 19220 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_64x512_hf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_64x512_hf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(64-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_64x512_hf_top_wrapper;
architecture xilinx of fifo_64x512_hf_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_64x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_64x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/simulation/fg_tb_pctrl.vhd | 10 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| mit |
TMU-VHDL-team2/sqrt | fpga/M9K_RAM.vhd | 1 | 7140 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: M9K_RAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY M9K_RAM IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
init_phase : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
input : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rden : IN STD_LOGIC := '1';
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END M9K_RAM;
ARCHITECTURE SYN OF m9k_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal a : std_logic_vector(7 downto 0);
signal d : std_logic_vector(15 downto 0);
signal w : std_logic;
BEGIN
a <= X"00" when (init_phase = X"1") else address;
d <= input when (init_phase = X"1") else data;
w <= '1' when (init_phase = X"1") else wren;
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../content.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
maximum_depth => 256,
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => a,
clock0 => clock,
data_a => d,
wren_a => w,
rden_a => rden,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256"
-- Retrieval info: PRIVATE: MIFfilename STRING "../content.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../content.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| mit |
TMU-VHDL-team2/sqrt | components/old_data/inst_32.vhd | 1 | 687 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity inst is
port(
clock : in std_logic;
busA : in std_logic_vector(31 downto 0);
latch : in std_logic;
Mlang : out std_logic_vector(15 downto 0)
);
end inst;
architecture BEHAVIOR of inst is
signal data : std_logic_vector(15 downto 0);
begin
Mlang <= data;
process(clock) begin
if(clock'event and clock = '1')then
if(latch = '1')then
data <= busA(15 downto 0);
else
null;
end if;
else
null;
end if;
end process;
end BEHAVIOR;
| mit |
TMU-VHDL-team2/sqrt | components/old_data/alu_32.vhd | 1 | 8160 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(31 downto 0);
busB : in std_logic_vector(31 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(31 downto 0)
);
end alu;
architecture BEHAVIOR of alu is
-- Definitions --
signal ans : std_logic_vector(31 downto 0);
signal atop : std_logic;
signal btop : std_logic;
signal ftop : std_logic;
signal shift_ov : std_logic;
-- Main --
begin
busC <= ans;
-- Calculate Process --
process(func, busA, busB)
variable num : integer;
variable zero : std_logic_vector(31 downto 0);
begin
case func is
when "0000" => -- select busA (not only HALT) --
ans <= busA;
when "0001" => -- select busB (not only LD1) --
ans <= busB;
when "0101" => -- ADD --
ans <= busA + busB;
when "0110" => -- SUB --
ans <= busA - busB;
when "0111" => -- SL --
case conv_integer(busB(4 downto 0)) is
when 1 to 32 =>
num := conv_integer(busB(7 downto 0));
zero := (others => '0');
shift_ov <= busA(32 - num);
ans <= busA(31 - num downto 0) & zero(num - 1 downto 0);
when others =>
shift_ov <= '0';
ans <= busA;
end case;
-- case busB(3 downto 0) is
-- when "0000" => shift_ov <= '0'; ans <= busA;
-- when "0001" => shift_ov <= busA(15); ans <= busA(14 downto 0) & '0';
-- when "0010" => shift_ov <= busA(14); ans <= busA(13 downto 0) & "00";
-- when "0011" => shift_ov <= busA(13); ans <= busA(12 downto 0) & "000";
-- when "0100" => shift_ov <= busA(12); ans <= busA(11 downto 0) & "0000";
-- when "0101" => shift_ov <= busA(11); ans <= busA(10 downto 0) & "00000";
-- when "0110" => shift_ov <= busA(10); ans <= busA( 9 downto 0) & "000000";
-- when "0111" => shift_ov <= busA( 9); ans <= busA( 8 downto 0) & "0000000";
-- when "1000" => shift_ov <= busA( 8); ans <= busA( 7 downto 0) & "00000000";
-- when "1001" => shift_ov <= busA( 7); ans <= busA( 6 downto 0) & "000000000";
-- when "1010" => shift_ov <= busA( 6); ans <= busA( 5 downto 0) & "0000000000";
-- when "1011" => shift_ov <= busA( 5); ans <= busA( 4 downto 0) & "00000000000";
-- when "1100" => shift_ov <= busA( 4); ans <= busA( 3 downto 0) & "000000000000";
-- when "1101" => shift_ov <= busA( 3); ans <= busA( 2 downto 0) & "0000000000000";
-- when "1110" => shift_ov <= busA( 2); ans <= busA( 1 downto 0) & "00000000000000";
-- when "1111" => shift_ov <= busA( 1); ans <= busA(0) & "000000000000000";
-- when others => shift_ov <= '0'; ans <= busA;
-- end case;
when "1000" => -- SR --
case conv_integer(busB(4 downto 0)) is
when 1 to 32 =>
num := conv_integer(busB(7 downto 0));
zero := (others => '0');
shift_ov <= busA(num - 1);
ans <= zero(num - 1 downto 0) & busA(31 downto num);
when others =>
shift_ov <= '0';
ans <= busA;
end case;
-- case busB(3 downto 0) is
-- when "0000" => shift_ov <= '0'; ans <= busA;
-- when "0001" => shift_ov <= busA( 0); ans <= '0' & busA(15 downto 1);
-- when "0010" => shift_ov <= busA( 1); ans <= "00" & busA(15 downto 2);
-- when "0011" => shift_ov <= busA( 2); ans <= "000" & busA(15 downto 3);
-- when "0100" => shift_ov <= busA( 3); ans <= "0000" & busA(15 downto 4);
-- when "0101" => shift_ov <= busA( 4); ans <= "00000" & busA(15 downto 5);
-- when "0110" => shift_ov <= busA( 5); ans <= "000000" & busA(15 downto 6);
-- when "0111" => shift_ov <= busA( 6); ans <= "0000000" & busA(15 downto 7);
-- when "1000" => shift_ov <= busA( 7); ans <= "00000000" & busA(15 downto 8);
-- when "1001" => shift_ov <= busA( 8); ans <= "000000000" & busA(15 downto 9);
-- when "1010" => shift_ov <= busA( 9); ans <= "0000000000" & busA(15 downto 10);
-- when "1011" => shift_ov <= busA(10); ans <= "00000000000" & busA(15 downto 11);
-- when "1100" => shift_ov <= busA(11); ans <= "000000000000" & busA(15 downto 12);
-- when "1101" => shift_ov <= busA(12); ans <= "0000000000000" & busA(15 downto 13);
-- when "1110" => shift_ov <= busA(13); ans <= "00000000000000" & busA(15 downto 14);
-- when "1111" => shift_ov <= busA(14); ans <= "000000000000000" & busA(15);
-- when others => shift_ov <= '0'; ans <= busA;
-- end case;
when "1001" => -- NAND --
ans <= busA nand busB;
when "1010" => -- JMP --
ans <= busA; --------------------------- effective address
when "1011" => -- JZE --
if(inZ = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + '1'; -- program register
end if;
when "1100" => -- JMI --
if(inS = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + '1'; -- program register
end if;
when "1101" => -- JOV --
if(inO = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + '1'; -- program register
end if;
when "1110" => -- RJMP --
ans <= busA; --------------------------- general register
when "1111" => -- DISP --
ans <= "0000000000000000000000000000" & busA(3 downto 0);
when others =>
ans <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- GetTop Process --
process(busA, busB, ans) begin
atop <= busA(31);
btop <= busB(31);
ftop <= ans(31);
if(ans = "00000000000000000000000000000000") then
outZ <= '1';
else
outZ <= '0';
end if;
end process;
-- Flag Process --
process(func, atop, btop, ftop) begin
case func is
when "0101" =>
if(((atop and btop) or (atop and not ftop) or (btop and not ftop)) = '1') then
outO <= '1';
else
outO <= '0';
end if;
when "0110" =>
if(((atop and btop) or (atop and not ftop) or (btop and not ftop)) = '1') then
outO <= '0';
else
outO <= '1';
end if;
when "0111" =>
outO <= shift_ov;
when "1000" =>
outO <= shift_ov;
when others =>
outO <= '0';
end case;
outS <= ftop;
end process;
end BEHAVIOR;
| mit |
TMU-VHDL-team2/sqrt | components/old_data/busA_32.vhd | 1 | 742 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
---SI=[MDR,GR,ADDRESS]
entity busA is
port(
clock: in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(31 downto 0);
ADDR : in std_logic_vector( 7 downto 0);
SI : in std_logic_vector( 2 downto 0);
busA_out : out std_logic_vector(31 downto 0)
);
end busA;
---architecture
architecture BEHAVIOR of busA is
begin
busA_out <= "0000000000000000" & MDR when SI = "001"
else GR when SI = "010"
else "000000000000000000000000" & ADDR when SI = "100"
else "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end BEHAVIOR;
| mit |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_pkg.vhd | 1 | 11323 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_37x512_hf_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(1-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit |
Madh93/scpu | work/mux1/_primary.vhd | 1 | 446 | library verilog;
use verilog.vl_types.all;
entity mux1 is
generic(
WIDTH : integer := 10
);
port(
d0 : in vl_logic_vector;
d1 : in vl_logic_vector;
s : in vl_logic;
y : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of WIDTH : constant is 1;
end mux1;
| mit |
alifazel/16-bit-risc | vhdl/mux2x16.vhd | 4 | 382 | library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux2x16 is
port(S : in std_logic;
X,Y : in std_logic_vector(15 downto 0);
O : out std_logic_vector(15 downto 0));
end mux2x16;
architecture Logic of mux2x16 is
begin
with S select O <= X when '0',
Y when '1',
"XXXXXXXXXXXXXXXX" when others;
end Logic; | mit |
mjl152/usmt_uarch | smt_full_adder.vhd | 1 | 1908 | -- The MIT License (MIT)
--
-- Copyright (c) 2013 Michael Lancaster
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- SMT full adder
-- Michael Lancaster <mjl152@uclive.ac.nz>
-- 4 October 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity smt_full_adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
S : out STD_LOGIC);
end smt_full_adder;
architecture Behavioral of smt_full_adder is
begin
S <= A or B or Cin;
Cout <= (A and B) or (Cin and (A or B));
end Behavioral;
| mit |
airlog/vhdl-rc4 | src/rc4_key_loader.vhd | 1 | 2542 | --
-- rc4_key_loader
-- urz¹dzenie ³aduj¹ce kolejne bajty klucza do pamiêci
--
-- TODO: opis dzialania
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.ALL;
entity rc4_key_loader is
generic (
width: integer := 8; -- ilosc bitow na wartosci
key_width: integer := 8 -- ilosc bitow na dlugosc klucza
);
port (
input: in std_logic_vector((width - 1) downto 0); -- bajt do zaszyfrowania/deszyfrowania
input_ctrl: in std_logic; -- czytaj wartosc z wejscia
input_stop: in std_logic; -- koniec nadawania klucza
go: in std_logic; -- dzialac/nie dzialac
clk: in std_logic;
key_ctrl: out std_logic; -- zapisz wartosc w pamieci
key_index: out std_logic_vector((width - 1) downto 0); -- indeks bajtu w pamieci
key_output: out std_logic_vector((width - 1) downto 0); -- perm_ctrl=1 => zapisz te wartosc
key_len_ctrl: out std_logic;
key_len_output: out std_logic_vector((key_width - 1) downto 0);
rdy: out std_logic -- gotowy do wczytywania klucza
);
end rc4_key_loader;
architecture Behavioral of rc4_key_loader is
type rc4_key_loader_state is (IDLE, ZERO_MEMORY, READING);
constant key_length : integer := 2 ** key_width;
begin
process (clk)
variable clk_ctr : integer := 0;
variable i : integer := 0;
variable state : rc4_key_loader_state := IDLE;
begin
if rising_edge(clk) then
key_ctrl <= '0';
key_len_ctrl <= '0';
rdy <= '0';
case state is
when IDLE =>
if go = '1' then
clk_ctr := 0;
i := 0;
state := ZERO_MEMORY;
end if;
when ZERO_MEMORY =>
if i >= key_length then
clk_ctr := 0;
i := 0;
state := READING;
else
key_ctrl <= '1';
key_index <= conv_std_logic_vector(i, width);
key_output <= (others => '0');
i := i + 1;
clk_ctr := clk_ctr + 1;
state := ZERO_MEMORY;
end if;
when READING =>
if input_stop = '1' then
key_len_ctrl <= '1';
key_len_output <= conv_std_logic_vector(i, key_width);
state := IDLE;
else
rdy <= '1';
if i >= key_length then
clk_ctr := 0;
rdy <= '0';
elsif input_ctrl = '1' then
key_ctrl <= '1';
key_index <= conv_std_logic_vector(i, width);
key_output <= input;
i := i + 1;
state := READING;
end if;
end if;
when others =>
end case;
end if;
end process;
end Behavioral;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/blk_mem_gen_v8_1/blk_mem_gen_v8_1.vhd | 27 | 19382 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
gQ4CxdvWgnieRLRQ2AMwpJaA+X4QUP23A7mcpTzLH1nina2JWDwyro/SbR0koY81VxQ8tVNBYSg8
3s+EjSEjvg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gPnHmBrjBHDleV2Jfu7AAgNyinLiMa4GswbueiHBD8y67DvELbF4ryETXsYzyyRC60JDgiQTY9xS
mNBL0n+tguqX8nripcl2WvUcK2rEIU4vEmrY5Xa0k52V9uCE29ruqODz0JXngqZvaosAn7R3hB73
7cI2IgLWPL6sayUHq1M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bim7wErRMWV5FSeSCuJLdGVUUYEH+U9HzwEGlgElmMU1LE1rxBL3MWBw6E1Qg5kGmxPZcrNQKg7b
PLZUD5Dv3VyvXW/HR3jI7P5DnwdmPcuCjrrkZwCh4jjzor7rIj0AM8ubprUHwkpicj6rKGNYRGRi
+lmT6hjwlretXlYwE1YClKFDSDei0UBfS9a5tRfCcNpmoCaImXf0uTOJ8unbujREQZSIp1snYBqM
Q6qvNMpDqcLoVSU7OrgHQdnonXWYqY/ILDCjdL1o02B+xcnkuGf+oGCDs8KSCPuzYvirbLqI8N91
feufkvRKEcc9+CQ7U9kVuEQ2Z+MB8XwJtiWwVA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HhRynIQ+TRImN/1ISEgCruTQGOfZ7yQ0AeSPRr1UgeSXeBV4/j+sqUVwy6KpjxjyOB8/Up1pUaXk
C62p4kvtT61bX2llnNuuYjikfaIxGUWJ2S1a+GpileS7Ui7iwtZy8qreshTy7qb9L+4SycH2S0Vs
ofqZzZCA27OgdUdAA0M=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RhnO7aE6HcfX9+ngWNOvpaRDGHOLotkXich9kwwYcDEBAwcff538vS/s9YC3iM7OnnDBzfIjK9PG
hZTnV6Wbh+heW3iD6MhhmPxC3a+3h3Xr7G6V/gV+8tP3qbjwLdyiI3Y3Tl9GXzeddtSNdvaD6764
1AS1CtRtG1cyGvfnXyGxmyDzJ91rqIOqSJbBOVjL0a+NolFyEU0BYVthKlZ39r7JI1kVtcM5XAND
LnFrRp5p6iEzVZDFdricPTs3V2FwNDnZSvZ0QADHlENUl1ofRaFRtXOEIahTDRwJJzBMRTba/K/s
3AtKBuzpWzTyvSqo+1PWwgrrClt60fAvHko0Yg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608)
`protect data_block
5fO2PrNmk6DUgNWBFaEZEwdADkRrb13p36yXhbMQkS8YOLN30xaqL+Du5W7ZZTqKopQ6y3mkdnFA
MMtYyw4viV7uGqgytEQQizhAhaf+PykQ7hkf/9hnoO1ykkN6XcwFqVXRzfWkuX+18zHcuDYsdHt4
6MR8uDqPQ7Xb1g+wRy7V8HfBE3E8F4PqqpwSFNTBQtzJe9oOwjTBtWl/LvfdymEJgvtqHhzEXvuu
brW+IgNzAukQtn2QwJCgBG5n7M2r8Wbw9CoLZlUvKXZujMRLN5LGh601f6ZJzYis0WHK7Bnq9cqK
dmkJnZjnPtFzqelobqNMoZABA0yxA+jb4we95c4WfSxcygv+8Lg70/Copt754+3/v3bHE9WMaJx4
o+I2TDl5laqhvojrdOaLURhUid1z7IXOITs6IQG1ghaaQUcXc3ZyoI/pyUpwX5NOSF74EBdPZksV
FKRxDsU5mbDWqV4AIB/cWSntq63rsDwXkk+323z9YBF8SGxf5AIfR2J3ekoSV1xU0ELhmsnO16MD
xRH2RmmZfurqPn171ddeT+iaX21PO1ZcMVs2ZiIUCTLKQJzqQMSTf2MQ2w3TP4YRRqUYKTKeAw6R
vomy4GQ/JZ7A1IWt76Cvoit+ZWO59WYZ4iPWxfPYCXL81+YLLZCZVp2/7Ew5u/1YnYaEHnnhauOz
E8GsqTEPYzfrg6oA6SGylqppd5uIwvgpO51J1RhJYDv0ZBq3NwNIR2E6cEKTtsTyqdzape4hAONT
NHZTAR9jIuVvERiyB1ZoErbB2DRKeM+TNBLOzWmWDVcj1LprKG6CE1bclU2hY3UctlZSnrvfLkxs
fxDIpShLVAcnm+jhf5sGxlf/nz9kGDHbh57NGWV1j0fMyxRv2nbz5lZefYu5/nO0PiHe7/h2RD3q
T99goCC/QUrrWyBYh87cIdpRBBH+UV+TcXXNAeY3PkhDie4mH3Uucqjsyyzi2fSsz1quFwdhswUN
Pj4+bart22H3n5uPKLORSXMkNEZ1EdSAzu2kovt5YJsr9hmgkgBR/myfN8FQlTcxp+z1fkk5dznG
SqegJFWzrefR4AeKoBtGSfHIB8IrbsiUqdOfOu3iNuQI/DlsXe2y0ltWqZZnd5lDjK0s+jSv9uac
4tpKIg8NCR3sG82QWxgSKtzdA6wrrGpQhtTWSVjBOFjYxwDli7Tm9EaEpUv7GgGRqm7wyxNy0vVo
m/rrk5ln2gG2T7su+6Cyge4lQzyYH7GrJAxjTwto/TSwTeQtIoqIu+TRTZ3MWEdQufcT6N4sYpUo
rxq59JlSfenmEYYfEyv7C+H5E/0pkDYfsTOIRakQf5/uG1Sy1jBc1KFW0YHkxg4uIhiz55goPVra
vLoJEThSE9NNs6t3FAKMbLV5L6Wm9DBJ+LdUDZ11RGLXscb+uZa/STyS+waBLHnauRtbNlKL7sp0
1rPCjqmBXjIH+MCC46OI46TWrFQKYJ95Pe7lJnLJU0yiifKY/rBvRf0JGCQ4bugwDQL0Vi3O4wbt
hHKzSL7kZet0YsrIvXVlmr6CrpSqwSPb9Eul6SYjE8eyQ9h6S/RLj9IJjcrKRHHBPW9XjtKT3Jvm
DTg1BbktNHNiOUGVQZAjSZeaER12HaMKTF6XUeBX15fX9MExZiOplL+9kuKoaM9ymgITG5+ELugA
LlQAGWaJBuQWNcugGTdKorJcSdrcqmb8/PuHFY6zzMXlZzj2K2Hwtg3dPN1o+Ao7DF6I2HCllOV2
80WtLZvSCgVi5WW0H+C7QLgk0SIx7BGFmvv+s1z1Y4WA3sG8hi9Sa7Q+kXcHKrbUrHjAFL/NxeeC
IXI4YP5CveYd+Xz0JopwTvH2NvOwKc+6QB++SV0PzAjLEVRPg2lcUbKZTsGbk+EWehJ8C+ANiZdh
/+RkSJnXnUoZuhHyL369kIzOBBaOcGcN8H1jrq4gg1oyLTsmHbiGODyWTeUfVXo3jvRKDKeO7u9c
Q9eqm2YTo9kuVdVrqSOXujb+SUaT06h6FlXGd+KCxPJWUz9LYYheyEf6xVbF8rMZgnt2x/nCml6V
nh+1BWBKXBFLqiyY8jFlarY4SD61RgrND+j4KZBVrEISZ2FxZAJ1yXMzYek62fst6amq+e7+2a45
at+UuRiBkMJcysEvmNmmbShI9ALmECXrlYi+jQmrxpFDlsE3hz5Qem/LF7MNbExfGJOSWPFnjqA3
42G79NcGS91jojpH7exT7AKO1fmRlFiVHSW861EUqlYSjnpPWM9BfDfHFCiSrkgo8gpoAcEVoheZ
VGaOUBSg+vlsX/V5LzSRyOUlWpgJ8qJT0AZKQjGAnbkFBcLwQlEMjoLdWBTToj409DMaNopCJFND
iIYdsJDpDih2Pxo8n2k9SXS6CxAQnNF0IwaRwgT85FCpkeWDKVZmahqLFXcb0VViScto5OLy3FYS
wITlxAxkLiVw0fGJNndevGiZGw5EOh6/bDhlesI/OAP1i8yPRtKn8l8LwWmj+aWZmKVGqsFvoERI
oP4woF9xMZSRwnVhV/LEmujI3VXwFjLHBsB7xcxFDOs9NlB2YPmsRzEabMOldlXSgE348ZIAS4iw
6QFcT3BS9V0Dq3zbYcx8gpm2K0gfRtowfhwlYDmugyPBWXKIAwiQUgTGxYCBk3AWhJwmR/wCvHd6
q1n35nLYHNUfcgFpPGezD1K24vLkHu4M09HojVvfnt284STcakZqV/aKBZ2lbX6jo1JhGBpDvoxP
dFHtjjaoczCOnbRgcqxVFT12I86L+dadNSOOIcYe8S2NskYJEH3969YsAz1HT1xkErISmuGxhGz/
6DBcKMn9vgF/dXJfn+YuNlvqSiONM40LEf8I67ZrlQbek0pFyOaTjzv2fgmUsOHdTdJ1MS6dUbqb
FSWJIin1fBFhpRKxs0pdNmnyjwSsXjx7H8CLUP0+m/4gQAiH4MeRtTH0ArcEniIAES2b9RnALau2
ri1Dm40Vl8ks+GWIWz7y+HzVXs6f6pfD+9b15GFI/SjCVgCan3JMW1UCo3EVMMKMAH0sp/Sf7LcG
JOcllQrL4qSWqa+VirFPTLUZchHTUihpEGp0RdFmR6fXGwRBW5b+Sn5FWjWBsxCmR0aLuITMwCGi
uKNE/dunvpkdV0ZshLOJnxxbT5M/rB7BQ8ncWOCfluOqjgeEh7OzPv7/xMyCatsErntfDhibrJmY
g2yvdDimFylMfpUlAxjx95d/PweAy0a7Xm7sI3TATeC/pJhEFowGGDd3fTyPl9u8Hos3sJykvYsu
9wstZtiC0wXBqWIIEWPEb3i81WRktS0xCdwUXW2BXzlhJb25BocZiBb6yjh7bSPu1cau4j8ZZVs2
Saa7m9HMTtNRy6sOSdGPiLL7kNR79ny0sylkb4kCG225RYUSdj42W4eiHY5i8E2Zky2TwSqt3SSi
Gfp6QCbOFNgRhXpG5CzvznAf1Ai7nxsfe/TyNXoXUzRzK8jJ2PLGu5+s/brMgFXVI0qO95SEAM2W
srYsUeO/1NSple0XfxOmNn91hk7IXEos/N7LWaqHWF6IsAByf5S9dCH6b22e8/1LTgVZfZnbkqwn
3mRlxQszif5j7b3kgBra7hkTxIL4DymX/37s+98wS3eAOgSYN3qYSYaykXU/EHqu+D6gdGsFC4cc
61O9gQIEoV0PMGt/oO5iIXyTfL8N+/zqNuVnqp/PaVq+zUtUks5drmIUe0t2xZWJCeKw5wKeqWvv
iEun2p0rrP5lQG7+9pJJsr4kJonimxnfa6SpvM/8Lib5nl2xHhQLKdezs3UtZEwzhK2SxSacVSuX
4F+awIHYUMV7W6Q8aaMTWIPcqdkMdNcGznqb773CO4c9oj+EsnrcFCDfGYttb77pOzGuTnE1DcBj
+C05OZmX+5BNLlWl3XlChqO48TNZYaRSqYhO6VbI23gb4orCUIaD9UcjhWOtyXX3Pq/IgcmxzG+b
SiDNcB4I4dT9itkLTDDQufC326lrIHTrmsC0LOSDrfB+KDgalphTIPtStuhkhDyNF+lJtRI/F+3z
e6e3VR/1dJozDnvKepRSqNFj83bSSlXwBzjjfF25H6bI61FZDkoHGiZj0K3LY9rKYCYcapIEPsb7
fR9p6CsxkDGcSmxbSNAH47pHQG7I1hqeKpolLzovuAHA4N+RZeHPLaL0s+lOejEDzf/AE/xDHFaq
tSfQ8CWKg65LLQYfJqhNmRQOUF2RF+h1+lW0g73Lbdk/ylqzq6HRD8AE035Ql2DKFOZHZ5Cur61x
m+L39c/O+tSOEjQDtOock1jRoOJteJPvn4JjN051NvWcIKf16Gvp5D57JMKZNM/01lXRo5CrDF6P
3esBFOi0P8eWRp3pHnmrkJl+AHfIcdAOoLMSReARtZE94CEEy+r36e44OY/mnqAmKXLYATUOpRn5
fSxa6OHr1iqP3TETIBwHjRdv8/YGK45hUIKGEGvRd8l0/iSwkwJzSSP04jfsGBoCCre8WFMT60oI
8rkxkxudoLP9LKUGRJGVwM8sgareov3gnijKTtvStbts4CC4sUoFEOKy44Fyv7MLj59cUvuAlo8X
vyHdtFyfAUYfHynAPc/v6HVW1dmeyMlGakwYmxC9i/gqAyyaMH7yebAtDgnLzLyVXu+OR7huQ9JK
Zyyn58QXIeV2fxOnluHP7A4m9w1F42xOvRq1Vk9CARcPoQhiv9AHjilBKrDVl6KflgE9kY/l+hIc
DIHojNDfRlJz8OGHN9TjV6v02uVeTiRrrR7f4eeyUY5gfvCPQ5GwVIGnV3eP8gI22SL50JGfw8EH
M5C8/0DTzWPV3wL22GGSeO0lqonXM7LBI27OutiYktcm2LzR6tBnowC8eWKQHgHGF/t/s3jof+8m
FJrhsefpj8LukFeE0X/CpWUWXcKpgxhq9DSR12DPLPDNwhdfKTgCnOLXyr6JI/p+rNX9H5uHuRYj
pgKnYOHF8SCnBbpyTuVjb/HVGbQb3zrU4o17Yn57pwVlfnZ4hpoZt/e91FkIh/aexvXPjT4MsJnl
AsBzCZhByXepim8JwfhVT7UH93538ECvaZGBR7UsYkJmt+ETqyY8+/8xQOfMsJEpIPBdQJKpiS7e
28lhVyZQUYjnuGKTZZjSX2b0Pg9fMA/nFr1DqLNlYJ9gXm8X+ikNfcNdBJSfBJHYVGlBdViSRyLu
oJ5eQGAANpC84jU/V9rITmwEQGRZ1rSsqhv3PlUePPuexUEEPyr3iVZn/L3O+pbCW4srvbYl/YHG
Mpjn5zRFZcbA9DtbP4WvlkPpUVBSAIYcKsHwW+TuF0JlOVN65nlvwn6bfNUUUJzlk/TnNBDFRrPo
Rz6yKR9PiWLCTXCXffkBX1XLEAh1FanbRRVAvwgOZTA7PFpzNPuxFchVyWLhl/yBkfUjjJb8YzJz
K73U+Qch4zM+W1nqs0q0689CU0JfD2Y2He5Gr7cJoigDHbVipugsY+vEqUopY+dptW4YncNZvu+1
NfAC2jDeB5FoOrwUB4ic5mNosoR2Sxn03csQkOZdJH+c2jkdyvmDMM9nqjXgr5/GUEtgrbOqFTfn
hfjK19uAl9gmucHeyZlrHSgoIQGxsMsKnY+/cWvP5yton5/bj0ezim/uSdG3HHN/jiicwflCJ80m
Tp0joxcYkkBs7tv4FEbhHo2ji9FWn+hia86yzJ35aeUHM2Vf822C5uAfEOy9vdOse+vMgj80JxQz
tqHMVQuypGEMjSIntajlFoAhfpMYTLmZMKl+3NBmrNK8VoCpLVnqJrsJyVCVjRCnrW4vcO4BP5LH
y1GPLGbTUB0qtKOWAp374Y53G3uDwrhIqvU3FAo4xJUtBiqX1TqnjRgwZ58vot/kLsRMMOStIatF
MQuzASAikq7GKKZHAJTq+pBso0Or3/0CvXCSFBfNH7A84qC3CGZE+g+j7IDVkHZeBMmAJVXGBp8e
uOiKWIJ6OUJKSaNoUyA/gK3WYGkk0dgcffM7egSE62F+ZYZ4l0tA/qHO1clfd4HWsyGkqWBmiZc8
uSwKcZstw/YSTJ7Gis6FQ68SIOjn6QdhlKYJWYaIWWxP2Z2R/diPC2tzdIgn8/hZ5vIUOnl+Gn19
/pbCAVqllczRomLfZmyrNjjgY0wsO5Crj25uqSyy8C77oVtCtn5tAYKfu+6NbjFzYq9OHkttPtKu
ySCWsc4UxnoYmk4WWxVrvW1qypB2H+Xp8Fk/ZEA2pCviskImSheZ6ItBd0gkI0KL9aCrnGqF6nF0
7vlbMlDc6wlhHRykm+x6Sl+7qjLEKC6RZ/9s9n1cWcbjkE3so7r1jy5jjl6cK4QO2oHUU8aBZ/+W
ZTkPKInn/g2VzXT8mHtodBga2VPW/o+SpoCAUdalfhibjH0+jklCMnur8/39TQdFI1Du8pKmBWwz
39FG6GQe5qZixaKx2eaozz7bSxXUqGC2TUQktVfw0fRoS5fsxwik+13W5v6aRCseZjHZgFtVuUjx
rWAhTjUu/lLuKD+wBedO56CGv3z5lNFI/2b8IrH+Dm3VesfQ4EoH3P1ZwEVOL91XEXn2sFErQgau
9YS3VZXabapgyxp1ZSEsttyU2rF1gOQq17t4dsXPky6tigx2QhlI7TdDa4oTAvng/Ft9Rcq9Ybzr
Bg3/rRA4YBE1Ezf6Y8NyN3Z0HWhh75R7CRWOVqB/wuvpvtObkJOJfbk5OuQdpgDTWL/KHvxg6J8e
c/f1hIjzaNfhg6i7wsPknnbIrRUmdxUK6DJi6d44AO6sc70Gybf41iruCXeYGcksy3LglRBZqk1r
aUohp7Dfm7VUJO1lrQ7rcdjQ98rE8KSNotz50jSqsSUhzdLzmjfd0CJhEq6zveQLdENbh89l7EuA
L60fQC1Ges+u1IX8Suv0wMONy/5Dfzigt9E0URmJ1kJu7D4s/X52NBKyAR/5cskUJzFvY6T+/rYk
Dlci24Yi8gYiP9TVlB7g8qxOq7HhEygShmCf73jQGS5kE63DhF/SGKfVZcyiGuzly24bGSbjfW7J
AetCxZmIR61AI4tOlSkoi19aLKOV0KsQw8Zd8StIYv5M4opVzeLghPsGkvxvBUI0PKTrU10QpOJM
nwZzhOc99kDTiv3sj5yAx5BYr14AMfOXTTweB8mPfYSo+yZ8KgOk4EBXCBGjU5tfUXwpf+afxo+X
8KmAuntrH1Lcmn5/+h8fCl//OLI40i1bXqlvqMKT/T6t0s9TNunPrNQEac859QhJ7HK3GYwxpaww
iG7pndyS667+Gu9japTCfmIllpuFf9Vlb6AGeu7fS70TBSxoUdjpa6uGwyCb0EMUQclSomwwJrLm
csfYXDbEtRtHeWub+dqDCUR7iiQpYCp6Ifh2lAj4cfP3uavVE7dUNvL2Pzdwz/cUg1pxVfkSFLTJ
CJj1ajGldV+Pv2hdAEfmqidx340qCmrMduUdZylTQJJ17jqDzacfkOBZ97YtY9EgftK1hBzpZRMP
pDUcRz5b+XBT+OKG7IXCrmOurjSesTT33WywPLD9jhZsIvI/Im2Ha9szFtpJyF1f43XyIpEhLZ2z
eqix4zx3gSeMTr8PBztgIhj4pxfhA0TyNo6IRVS1f+6rdp6LXnNYrenyQQLyxrkXQ9xrGBFBCB/4
Asn/OgDUbrzqz6dg3Ui0RShztu/kqt4w6xpVa5j4sNpvgucmrNza6T/HyuHEPU0B9yJzplDvEoV2
yfDzi/rmRGwbBsxqGIS2O7wp4vbpgHT9EDSln5ejgEoI44iuLnwTLfMwhJJV989sPD0ZxKF6Ythy
j3l4QzrgqShjGKaJYRdXbmeSfwuKoxw6FVBSB6873gchR0fxRTfu9ZR1rJSnmDKSXSugo0PThCv6
j8fucPTUvrO3mPe4Dh0WxZ2DkEriBNcKMYsCROa0/yFPWsKB6hPFvRqJAVhlKsyKg02sCcSZmoeP
m85dekaTPy0dTmZZrHUDi8pxMnvCMweZsIm+1m+chQy7xpn+Xid8HQxJma4fmsPHhVhkzDfAbaIx
zg9Umjpp3zHvaOaktM+NMYQu2fde6dYXdUxWoRVvqRccE99+6l+wA9eSvJ9lUBTHefbiwMi5GOkr
DHhKAHOm+sCMxUoLwhcW5rUrBYgTxxZ0jK39Jhww12tGGSlUHu+nt7pLZb38nq+3B+43L01DzP5s
JUnS6M/+C9/qQTITHtViSabjWgQmD02+XU04UFROWBJ+PB22QylYWbq4XCCl9cECXOcQtF9sOzjZ
vpSoeXTIt1dwryXVJ6o5DW1CqPAvbETjoSY1a1kcxJj9ipFgzsCsSZDkCkus+JYC+VgZX6QJYLmO
UP/kymmJ6VtZE8R1KrM4fMDsHnGm5mSyteI11smOI/htyo4Dp7Fyfqb0iAMIQnM73MVTb53O4Bx+
XpNQU/uYVwDWQszjm7avuLnQ+hphU1+ODVxzOkxrCNzuPBLALvc9eFUFheB6cphFQhKcbEqDC99c
Yj3xgBzQ53xNAcsHa11iQNgaZFc9flxgd66A8kZtksJD29r4XeP3Q+EZhyNAx/NNFITGb9bjRhdO
MJuNQfSxvSoFj+NrJrX3POpU6B5iaCVIXXl0otTLzUqBFB/xuAvVkTtC8EehBUUwS+Zr9t6Bh4yG
nw0Em6CGCaFv4eUnGK1y0FlgZTOd1tqIw1lNnFv3K0fjAApShaYC0o65h+1ocdN9dbprb9Ex+2DS
/cRziUVLlIpx3chP6vVc4Tnq+mWQJZXXG5wcAh2wBqD8/cC+eyiw1PYvB2C7d/XM0T64UTsA+HCK
jggeYmgiKsPQujrWSWLxIKCoSYZdhUAo0d1S5Ftv/kWjuuJgaaGFcMMLAhvfOmhKLYqr2/ApP/P1
EAw3ljBk1kmbPo1a2yU7C0lEgfqA104lkK4Vh+Blo/eZS33+zdy+fyleazIAOkVM9HJvfMcBHWzj
C+F/dvjV918QmJhByXuKml3d3eBEdpodMPYp5TmaU70wg7Hn7URb4SAYhoPUyUoEiZfXYs2IXxla
h7Vshlr8x4zwD746BWAYc1gC0OskUYMqDajNJA1CoRSTWJDwnj/dY7Q0+33D6UjfeQ06qLR1Ld7k
fH7DjIURGp6F3JNwtxTXH3fkspGbxo9Jma9u/Zh8SxRetwQVykOWUHeSWuDloyKQ860AWKu+ntrF
TN7wj89nYoZF3p6H9RpH1CKYftt67vRAlhQPPuaS3X2u3+NYKHPVY5qKD62aRjyMcaICIEkZC4eC
za5b/lJQrcK6r1530XrR5dr6YwtMeUuX2TArggVKKcNmUSybY5H9aLoORevcr0zhBmczV4xs6n2i
dMbyEoazLV1cHV/4MqPY+mUZwpOpDq78GZ/woflf7CLizr1kExtAhsrnUpG9fdL7RoNqhPO4lWRo
db6/WsOu0BA2GoY+spIA6DKGt4Kcge/8vXQh8K5X81KLa2pdEZMl0TEVYiviRv3fn9R+YDMdV+3y
3AwBKt0X3F3XNgelOacxDFX++19VPG6+HK6tYshKeuaEvTELsyguwiXAGnV+Qr87oQhui50e8szT
RkMgoJdOscjTxFHeTObV6eiDigjW/rTpymfl5wEPvccSrgpFxwxquk4TJ36KBws3dfOu5xRymudL
S4kK2Ac++xzg9aCQDeKc9ScLocR0QSVtntU8INTgVUvTq8FubVwphu9oVj9b7Le7KnB2w7iep1tP
WknNzFtyIeKFP2CLmk2Oc0zkg1N943sh/dGZjujxE6amzXz6wps9Jvxe7i4Ld+cW28gCuTz0ix0w
kAaxBDruWaBE/YH2nhwZMoudRqIHaLM4SR5fgkbDsfO3uaY80ppMuFO0JpQlp4aLDqKnw+25hwGI
pM7dtyHlM96TZyIloJB+9XAEsavBRsIIDXkyyd5SkHDLse6iPv+hJ3Ji4HoB8rxG0ZPyLB3dm4Aa
AgAT6PHdsjtNlZ2cHzr4insZBVUoDDQ8pRRqhmkSSKjZGQ/sFZHsVBTS3gxuSR9T9f5S8gC5sfNi
btSM9SHXzi5Eg4gIyYwoy+n2TBzmt905GlAwRRWrdPC/VU3Wph3tezTQvcurhSzf2Teba77go+ko
8ZvB2qsT5YqChYzJSz4S3xQWYxCu6ZP9U0q/AzpAV9Kda4tEItURPWkw06dfexqaCkA37aF/jWIE
8cToCfQb7eJxIM+t/kzUT13gcoEltjRl5FZ4K3IBMggaRALtx1lSTzjKJdGk8bDW11H0Q2K9koc5
Po1ZkZZCEZHLrbvE4V0Z8z0TBWQGqhQU2F2no/RoGsocZ7BWOgxM47snMPZpEelnX8ZDh2fgVNOD
reN27i1iWqhyd1/f8Ye1sIjuXsPh5AMgnzyfvv8uKae6G0qHM2dE+T+Rss0GfvsUD1oUPnKbaa8S
nvPBOPaYTytU2XrucD496pTUUGm7qa0N4agMVVlFShlsSgvKPEt70KdoAUW9Kl0qCulg8YevYUkw
WHaDCDa5/It1R8U5nOEocnwI3x1Cos5I43uYjH1oLvPWrLb6rtZtNkztT2sConWI92sgwHojzrz3
+/rL4vFjlGrWpB7HlcZl0foPV6Z6vYAtEVKtq57i0n5jJgc4S6GJ791Tzgl28ZTXU5g/AIX3TwW2
UObtu+n43Um4VpiHzxicI/X7TTKQvvVi4mTBENwSDW1Zl4uTRucD/Jhm/tL/U1T3orOpsmifmGr4
MqoLe6oWeXvbaqJbmktoH0693ZssagDrf1r+8rYovQ4IpAen65xKVNgbovSv5XEhcRy7rtMRphEp
JiEe70o2DwM8ewS7N9uYOxhPXAfViJvWiU2UhH23IEKAZE9p6PuL8bUBieUJLvp0gSwIxVcV4me4
6ZxFvR/2CrGSZXJoBjrbErwdKPvuDoiylx1lkBLvrsD4ZTSdtZu8zkqxprrDsd2QwYBHYUcvR3EP
bDkXZWd/UH5LAYP3f+SpPfiUWOeVq4I62TfLGTm50JatA3s29/ADGdGEJM6LMn+5ODH8HbgUn3ci
YB6Wi7++i4FiRFbj8SFbTQqKwsscQp5BNFLAUuesehM25F/x2PqraE2ZHBs9I+l5QMYphMcWzWjY
hl4R9cCKXcbzik7D4jbC7PCtLEFBGHUij2Chdq7FAmIcTcJWJVMLMQJLn6DbmFBf5mTUm3C0BwaN
QyeiZvyL71/xdWrE3DfCE7iymi/se0gn2TFSwFLuW2oIuZZHprhfZesE16BYmFPuSKC5G78356Km
Z5/nCVkTwW0OpMLUS+jwINkeqVy1rVKGWBqwwpPVSxo3F1zFWgiXzxhiVaTWEHRuuXAscbd6HYH5
9z83zoq1FQBByKoSbk15DFXoJUfmMp2y0rC6ZmE0U+1QdGwhCHbC6pgJn507gQhb/EGisIx7mYce
VDrv2MGcuDWWoSFrEVNHSlE+jLF5xnBYFJ64Hf+x/Is74j0NP31dk5ZpZcVDZcxgJc2f8Qz9h6PD
o28PVnjB6A+IMfdgzerMpBlS6Ic/AdnLmTTOnCTv+4JyeGGW/G8AVtPDVrmCG4NdC2790+Cf40vj
xppbt3+s0l9O8LPUv6zaW6RU7yAEHuzle3BPyAUk/+dYniDoDTfx+MvIrmoc5eQy4VRLRkRKiH7V
MCYoPF+EePrJCf3m+JhU05F1Uje4i69tjbUD/mb9EeTGaEnkeU7SNHdVEHpir8FVt/l9aRaX6uVb
wKQkIBQ1mLyuEkIVae5rdUoo50HI1vAY5Dqiwv4eJrBUWW1eqDc9hlo6X6u4rBSELaVGD4VZYsUE
yFz2BqRHehVM3LeupIKA0waKR1I7nRaokEKhn9GtovIMfmTnBwrv/oq6dfsDmRjeyplSZwuD9zHz
l0pjgT70pk2MfA5xuheJT9OjyPA+SMXb4XBLW3FB5C2kz3ddIe0UIwIDMPifsLCKhKSdCTi48hgy
hssvaVO/tJvbVbPKGzy5czxLgCA1vDWXSuGzVuPw+0/khqHLcLE0fEN9C0h2pfAMwcoTU9lcsb5+
ejKF5kPsfArwy06hIG6hNGVKib3DIifMn9bVjAZ6yI6AIkcEYk2VmCh+aF8OiQICAHv+yoV3EF2q
mlGKEFnjNxW+lcP/dluRP3LWg2Fdxayo9K3Kd7C7DSR5OEj2gLARcVWdO9Kah0CUq5Zvdo87Hllk
uJm4MdcugUlJqtRZC8MIgZ7nh7ZQeA88A1PQgUO8z6akWTpTD4tKYMdIve12/rbNzvDqRvNdQjj2
vW4P0XRt6B6O10ccchgACd9hY80B5UheMFhV8bBJVUp7HhGHHklMvPhSJ414R1XS6CK4VOyoXosJ
c74wSUXmAg31KXn8GRhJtZVVnPq5q8aQZqJuH8MqD1AgReu/BRlNzaXOXe0WKOk0DcGjZV3BI/a+
5vt0qfqKe4aZvxL04/ZXrORdORAk7MFibjp/xIKORNLSrnvLtWQ1rPdUkF/28K5Anc4K4N2Ezs+/
9WCb2R/FtEkSaZ0Gl27z5nmx+sSiwfnHxHUXe3Z3tML1zb8dBgVBN+7i61pvN9N3hBW/ek0CeMZK
Kd7LtGS42816O77M3tvzme69AwAAOnhlQcf1gMutPxVCvIvjbJeJt4u1lFKIkWW5cZHgCOna46+C
ZMtTERn5YGOfoZouNwpln1nWFzGsQluQ5Gs9yVLfSL9OnqSraRVS5Bh3j6merrsUGy+Th+J+aXPc
6QFFydfTI32EQWfPHBMaqY8qlD2zeVVJ/Vf7vBtesUpw9PLTRXRPYcnEMmN9wgS3VnFXanf5VsF1
P2MwI5wjv1oQJiZU5P+H5g7WaP2VeTuSlyJD1Mpp4t7KVYKuMXwv72627Hgoupwota5PTxyO6i29
dgSTfB2AyAJHfQx4iTjEQ7JJWWbaZHLeWzcCOBIY/OYheGjU0ERfMIACh4LaYbuPcyVhA4msr5NW
gJI9NZkDyppCPSn4iADsrcIxsk35OJdJyJjn/Ggfx5cPFrJ7n7oKk9FPMyXagVl0Q0ZWbslEjKpA
NkSjuFTEh3rtcuYyH25Suej4+/zg7mLxtkqVaOCuCQiiKLp/dEf5B3aEjOvPqP3F0o5nE+DP47K2
Jozt9dgcH/ArWey0utxbDAlSzG0TyIqt7ASWlAz3Im3heknmgGaPhda6b9FgjMq1zxVZHilpLQzT
pv37pyaLwE1ocPgHIYKxczPOb4HNNo0onOEGFNmNkx6RmE8u6qpihLPLmduSShzwLPetepyhHMTn
Vd2KKifkRqpT4lY/ZVEhbNK+hcKzwBhQpTMvd1acSVFTX88XDrtnWxM9IXlb89B41jI3ZpSvYeab
rMvD8WdaZYqkzTU7sfJ3IdPMVnXDeXhr+vlPcojFjOe7sTMz2UrLFvrefPJResonx+ZmdSEvYkRs
Onjs/aJQIsy9bw47TfJWn3I1sa8yg1L/KkZJE2dIEsjmek0Up0ym4o6K+KcDHV8LNuQxY2X0XBX8
1WoNb3tLVyfRgY++QmSFX+IomM5sx7vJ3GK7p2Tm0NBpCXOJRzqQykScJJthb/TzkXyG3ymQXGny
2N6FXnsJSj06eIsEN0HVf/0+wv8mcZ5GMPBE3DYg9qEVD8hrg4IkRhWY7/7+46lFDLsZIDEMDSYs
0dSffHQiS2mBNw4eNu+ievzLQ882FZGGWImNKgr2BQN3al9aoUoz9FY8u8Dc9B9s/p2zp1AZKD6G
Q9taTSEWv9MwpEFzzTCA6/E/o8EXzBheHDJ6KnZ+RY9mluP0+phE1T9k56q66exmUWN/xpic0R/z
m/R4T8S4wdIE4AaCXElZbL3JYMWyQDca5KjZuu62D6EK14Gtt6FXg2EzeAvPvYYEjDLpqAp/njS9
OtpcyZNQfkBbfWeFmchTNAANh5lVag7oL1fqJ0/9WYREIYyBqMrUTQDc1N5mYpOtoEeEHK8JzKLu
Sv4aqtekYGtLoke/hLHZn5srVUwqQMuje7GGTUjDvLWTZM1kLTlEcAfO74hUCmOZ1ch1YIfqAQZv
9FQaZosHQpJGv1x8AoOKt3kcz9hyjDDm4DEAud8Hi1OV7TVnRHZsAJGvI4RKgJtzj8q4xIjcphN6
z214eAo2egvvRtiMTcsDHwkA55u9d7lm2ImUOdaeX3mgxKxMsOp0jlYgcKx8FijParDzDZt79f12
EzoxIK2WRYiQEwrU6k7mUwn0u4gL+aiN6Nvd1NNjEiAaqsF0W+gkTvFgw1Ly871Y2RgxbMxJJPL+
e8BOT2OiPh9CmFB7HuVXk8J/OPkTaFvZDMac5CmX67AvDmjaQzigXy4CDnzklfDUgxiARTDkf5B6
Ep967BNVxv78TX2UkbZlKVnmQWM685pM6+M6enQhubiZhzVret6wTiMgjAhC3gcSBZOof8ZmuUnh
quhlD3DzilcLi5yIHbZOKNpIDgroBKCEl1P5WJXwKbaBk1uv7Om/LNy5N1JTg0b0JA5vtQULU/zK
DMcfD0SZMEImwX+vvZZeWxtiTRLkIbooFV32MC3n9IAU6/8rDCXBQR2oJTBYWZ5Jh2bvayQMxuEr
KGMIoc3ys8ldBvTaTR6lcIgaTugICn6f6k55eAAewWN9qWThPrjc4DNRleK38ILcBvi+JOPcMkF0
Kldi4WSj4AG/B3br8DJXzS/T1AGoqHGHu72vvwUnFgh4b/EJHxz/c0KCSS8uTswu2rgOfPE6p1Fg
7CfIbCnXVY1aKe1p+pzwAjyJg173YOcK13TPtkDKJAPNMXsbgF185F5Kd0i2qxA9KNYRJTCQQioW
C73IIZ7GrMbFPrE+FbBvkAF/WW8SRTJV/WSdj2jarGrCyUImygVeVCw35GvnNMte+CXBttSPAN+y
E2WPq4Oni+MbVdDcoDIDLvxysIdD+p6MpRznaJMeh/33S6+yWRm44mk0m4bcba+I0S8jx127N1lN
cdvWl3iaFdlBXaWa8ajl2sLiOAegJ13l4TqZPT9Ru04tCNLuNen62GSf/KGo8Ud7rhdaBbnWQyaP
Gp7KJc30aYA2ALgg1WepnBVgru+C1/6oXZ7GBLUqdcQp8gVg1YF87mCQCZ1jGwLWsFUvzVuqc8Xw
epGCXe6k0HyflmGkCsm3QUMxVIAAEpkzVhrViBXWKRVLdONrm7o3Vvl3ZslIqbOZv1OB0l7WyvEU
7qTuGKZiV///NVDymfiE76vq7JDpyJoE+KRA8JVJWm7TkN8QL3d8M1MSgJRW6EuYeYadSRVkLfzo
qRhzI3UOVhLaPmAKwCsqhnw7rRJwdmpeCVGE5J2GUpIvgh4dYP67b7NAf6p6ZuS/JZ5erJ+4fsgf
17bnHdBXpf7vCP/MZ4cHBWA1Tpso11/dHiJGTijO/6txhFAdm4YpmgJ52SOiBl1HnpUuWnCHx+EC
RuqSfn4ikoBsXmPghLRLKH6aUHnydcWzkYc8CU0vxkFEpeAbymRdZyS5YLE1dGa9zKLdB8CkJta+
YX+S2UdfIGSQsHo6KTALfDCngHajCTKwfNbRWiIXCxRmiaVlm971Fzs+q8dHM4AubzGI0wHSHDu1
Qe2dF9FCVkxxzr1i8rTWo+/uN0RkWl2T3DWW0QIE+O+wqcrBRYjXI/Dixgt6rgy73m5lkVRsJCAP
Diy6IpB6I+RUX7oUUcty77SCKYQ24wsxcSkGv9ans5cIZYjcFz1VToADzs1zwqSjq/LcS7ltJm2y
zTKRuwJZ5/g0mExv973GGahXzka3P54o6JVi3wPee8dE3XTf+S7h9Bhyh8Gpm3kGZv3XFcIJw7Bz
Xsz9Q6s3EfDTdGNxVYdIuiGM7CDVXNN0BJb+u+bOfjnHZN+YsXaJT94WOreGVgNgWNAsY94hJMkM
5wPT0mTY+ziQhRg4uvTDGtj00wT8ktEZe6Vswmli3aD2yGesAi/mQDexoZZ2y1pHtE/3m0fGAFkq
+M3DSVWcJBtCzd5C38/q32p3evG1ISOqgyyAeUpvhwetl6Srg5sLrQWfENYoAuPmMPjSCHnFjnKV
EFMv1MfduEOxOQrGERCQKQ9N7Nx19zUOZ+uxAh65+8xa6Bl/CnHFbg54vbs6TvkX6ZK0caJONj2n
2XA4PbWDggtdOIAfjxwGG/yezu40Ypr4+JRxc9fqY28/AK0xGPv1iMTM1z3NBacCddjoVN86ku3C
11870p2RFJn55QSXshGOc9f+ohC83nYRgaAL/hM9YZ/mxSqL8+7OH92d9S9hxddS2aZNxJNAld6e
fImovMseid+4TsJxSnCe2fsWbXa3ODzBDYAtMmWsc2VMJG529QjhcRNrWoPQrczjNkeCAadpatac
aJmqtwPQjroEQvAxb1MnheIGFQ5iGAy6U/49JhP7P1Vbz6R9uAijty0j9/IrX1Ioj31Xy4eyO4Nt
aLiyLtkpq9cgeHKiXyeFWVYis7uiY3cre74dvwrWrjl7ZtAAa69T1w0AVvPMNL4eGIjK0ZT+v6Hc
9/AcKyeoO5g8EUEGm9tdeImTARPSNxp7T5gUkJ3IciqOMFBCd1WBKvyfBaxl5AukgTHCC4xlwd3H
z/M+tdf4fky0pFbrvdDkAmSSTU5P5PQ4Jl62ArXaViT5wD85ks/99+0V9e9Hp92+XmCcn0tbKndu
GDE6ZUhCDiiZ7vZHAfHt5IFL1TnTKVFMmwCwvG4f0eE0zJsGIuuGmYFNW5HpnCIrvlkzKn5nsa9q
+qXu24yzr05elNBy5poAmPAhE0vIrzb2ma5/ZNXqh/fd+qoiQ8NYcEjYjZP9cVw8/AoK4alXEfDp
6maLryhr4iutgUlLSTS3TN0YdBnaBeI1NZjdc6Fh6PDkUBDcIqV0JufbvKHkPh8LWvkhj7toPOPn
bXUNzD/vKUfMaADP0wh7PDx1gVx56oLZIllCnywfdO+FjLtzN/4oCACGg3JrG/ZAiELgMuSfwlhH
zLfX6d1S0C6p2JA=
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/blk_mem_gen_v8_1/blk_mem_gen_v8_1.vhd | 27 | 19382 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
gQ4CxdvWgnieRLRQ2AMwpJaA+X4QUP23A7mcpTzLH1nina2JWDwyro/SbR0koY81VxQ8tVNBYSg8
3s+EjSEjvg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gPnHmBrjBHDleV2Jfu7AAgNyinLiMa4GswbueiHBD8y67DvELbF4ryETXsYzyyRC60JDgiQTY9xS
mNBL0n+tguqX8nripcl2WvUcK2rEIU4vEmrY5Xa0k52V9uCE29ruqODz0JXngqZvaosAn7R3hB73
7cI2IgLWPL6sayUHq1M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bim7wErRMWV5FSeSCuJLdGVUUYEH+U9HzwEGlgElmMU1LE1rxBL3MWBw6E1Qg5kGmxPZcrNQKg7b
PLZUD5Dv3VyvXW/HR3jI7P5DnwdmPcuCjrrkZwCh4jjzor7rIj0AM8ubprUHwkpicj6rKGNYRGRi
+lmT6hjwlretXlYwE1YClKFDSDei0UBfS9a5tRfCcNpmoCaImXf0uTOJ8unbujREQZSIp1snYBqM
Q6qvNMpDqcLoVSU7OrgHQdnonXWYqY/ILDCjdL1o02B+xcnkuGf+oGCDs8KSCPuzYvirbLqI8N91
feufkvRKEcc9+CQ7U9kVuEQ2Z+MB8XwJtiWwVA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HhRynIQ+TRImN/1ISEgCruTQGOfZ7yQ0AeSPRr1UgeSXeBV4/j+sqUVwy6KpjxjyOB8/Up1pUaXk
C62p4kvtT61bX2llnNuuYjikfaIxGUWJ2S1a+GpileS7Ui7iwtZy8qreshTy7qb9L+4SycH2S0Vs
ofqZzZCA27OgdUdAA0M=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RhnO7aE6HcfX9+ngWNOvpaRDGHOLotkXich9kwwYcDEBAwcff538vS/s9YC3iM7OnnDBzfIjK9PG
hZTnV6Wbh+heW3iD6MhhmPxC3a+3h3Xr7G6V/gV+8tP3qbjwLdyiI3Y3Tl9GXzeddtSNdvaD6764
1AS1CtRtG1cyGvfnXyGxmyDzJ91rqIOqSJbBOVjL0a+NolFyEU0BYVthKlZ39r7JI1kVtcM5XAND
LnFrRp5p6iEzVZDFdricPTs3V2FwNDnZSvZ0QADHlENUl1ofRaFRtXOEIahTDRwJJzBMRTba/K/s
3AtKBuzpWzTyvSqo+1PWwgrrClt60fAvHko0Yg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608)
`protect data_block
5fO2PrNmk6DUgNWBFaEZEwdADkRrb13p36yXhbMQkS8YOLN30xaqL+Du5W7ZZTqKopQ6y3mkdnFA
MMtYyw4viV7uGqgytEQQizhAhaf+PykQ7hkf/9hnoO1ykkN6XcwFqVXRzfWkuX+18zHcuDYsdHt4
6MR8uDqPQ7Xb1g+wRy7V8HfBE3E8F4PqqpwSFNTBQtzJe9oOwjTBtWl/LvfdymEJgvtqHhzEXvuu
brW+IgNzAukQtn2QwJCgBG5n7M2r8Wbw9CoLZlUvKXZujMRLN5LGh601f6ZJzYis0WHK7Bnq9cqK
dmkJnZjnPtFzqelobqNMoZABA0yxA+jb4we95c4WfSxcygv+8Lg70/Copt754+3/v3bHE9WMaJx4
o+I2TDl5laqhvojrdOaLURhUid1z7IXOITs6IQG1ghaaQUcXc3ZyoI/pyUpwX5NOSF74EBdPZksV
FKRxDsU5mbDWqV4AIB/cWSntq63rsDwXkk+323z9YBF8SGxf5AIfR2J3ekoSV1xU0ELhmsnO16MD
xRH2RmmZfurqPn171ddeT+iaX21PO1ZcMVs2ZiIUCTLKQJzqQMSTf2MQ2w3TP4YRRqUYKTKeAw6R
vomy4GQ/JZ7A1IWt76Cvoit+ZWO59WYZ4iPWxfPYCXL81+YLLZCZVp2/7Ew5u/1YnYaEHnnhauOz
E8GsqTEPYzfrg6oA6SGylqppd5uIwvgpO51J1RhJYDv0ZBq3NwNIR2E6cEKTtsTyqdzape4hAONT
NHZTAR9jIuVvERiyB1ZoErbB2DRKeM+TNBLOzWmWDVcj1LprKG6CE1bclU2hY3UctlZSnrvfLkxs
fxDIpShLVAcnm+jhf5sGxlf/nz9kGDHbh57NGWV1j0fMyxRv2nbz5lZefYu5/nO0PiHe7/h2RD3q
T99goCC/QUrrWyBYh87cIdpRBBH+UV+TcXXNAeY3PkhDie4mH3Uucqjsyyzi2fSsz1quFwdhswUN
Pj4+bart22H3n5uPKLORSXMkNEZ1EdSAzu2kovt5YJsr9hmgkgBR/myfN8FQlTcxp+z1fkk5dznG
SqegJFWzrefR4AeKoBtGSfHIB8IrbsiUqdOfOu3iNuQI/DlsXe2y0ltWqZZnd5lDjK0s+jSv9uac
4tpKIg8NCR3sG82QWxgSKtzdA6wrrGpQhtTWSVjBOFjYxwDli7Tm9EaEpUv7GgGRqm7wyxNy0vVo
m/rrk5ln2gG2T7su+6Cyge4lQzyYH7GrJAxjTwto/TSwTeQtIoqIu+TRTZ3MWEdQufcT6N4sYpUo
rxq59JlSfenmEYYfEyv7C+H5E/0pkDYfsTOIRakQf5/uG1Sy1jBc1KFW0YHkxg4uIhiz55goPVra
vLoJEThSE9NNs6t3FAKMbLV5L6Wm9DBJ+LdUDZ11RGLXscb+uZa/STyS+waBLHnauRtbNlKL7sp0
1rPCjqmBXjIH+MCC46OI46TWrFQKYJ95Pe7lJnLJU0yiifKY/rBvRf0JGCQ4bugwDQL0Vi3O4wbt
hHKzSL7kZet0YsrIvXVlmr6CrpSqwSPb9Eul6SYjE8eyQ9h6S/RLj9IJjcrKRHHBPW9XjtKT3Jvm
DTg1BbktNHNiOUGVQZAjSZeaER12HaMKTF6XUeBX15fX9MExZiOplL+9kuKoaM9ymgITG5+ELugA
LlQAGWaJBuQWNcugGTdKorJcSdrcqmb8/PuHFY6zzMXlZzj2K2Hwtg3dPN1o+Ao7DF6I2HCllOV2
80WtLZvSCgVi5WW0H+C7QLgk0SIx7BGFmvv+s1z1Y4WA3sG8hi9Sa7Q+kXcHKrbUrHjAFL/NxeeC
IXI4YP5CveYd+Xz0JopwTvH2NvOwKc+6QB++SV0PzAjLEVRPg2lcUbKZTsGbk+EWehJ8C+ANiZdh
/+RkSJnXnUoZuhHyL369kIzOBBaOcGcN8H1jrq4gg1oyLTsmHbiGODyWTeUfVXo3jvRKDKeO7u9c
Q9eqm2YTo9kuVdVrqSOXujb+SUaT06h6FlXGd+KCxPJWUz9LYYheyEf6xVbF8rMZgnt2x/nCml6V
nh+1BWBKXBFLqiyY8jFlarY4SD61RgrND+j4KZBVrEISZ2FxZAJ1yXMzYek62fst6amq+e7+2a45
at+UuRiBkMJcysEvmNmmbShI9ALmECXrlYi+jQmrxpFDlsE3hz5Qem/LF7MNbExfGJOSWPFnjqA3
42G79NcGS91jojpH7exT7AKO1fmRlFiVHSW861EUqlYSjnpPWM9BfDfHFCiSrkgo8gpoAcEVoheZ
VGaOUBSg+vlsX/V5LzSRyOUlWpgJ8qJT0AZKQjGAnbkFBcLwQlEMjoLdWBTToj409DMaNopCJFND
iIYdsJDpDih2Pxo8n2k9SXS6CxAQnNF0IwaRwgT85FCpkeWDKVZmahqLFXcb0VViScto5OLy3FYS
wITlxAxkLiVw0fGJNndevGiZGw5EOh6/bDhlesI/OAP1i8yPRtKn8l8LwWmj+aWZmKVGqsFvoERI
oP4woF9xMZSRwnVhV/LEmujI3VXwFjLHBsB7xcxFDOs9NlB2YPmsRzEabMOldlXSgE348ZIAS4iw
6QFcT3BS9V0Dq3zbYcx8gpm2K0gfRtowfhwlYDmugyPBWXKIAwiQUgTGxYCBk3AWhJwmR/wCvHd6
q1n35nLYHNUfcgFpPGezD1K24vLkHu4M09HojVvfnt284STcakZqV/aKBZ2lbX6jo1JhGBpDvoxP
dFHtjjaoczCOnbRgcqxVFT12I86L+dadNSOOIcYe8S2NskYJEH3969YsAz1HT1xkErISmuGxhGz/
6DBcKMn9vgF/dXJfn+YuNlvqSiONM40LEf8I67ZrlQbek0pFyOaTjzv2fgmUsOHdTdJ1MS6dUbqb
FSWJIin1fBFhpRKxs0pdNmnyjwSsXjx7H8CLUP0+m/4gQAiH4MeRtTH0ArcEniIAES2b9RnALau2
ri1Dm40Vl8ks+GWIWz7y+HzVXs6f6pfD+9b15GFI/SjCVgCan3JMW1UCo3EVMMKMAH0sp/Sf7LcG
JOcllQrL4qSWqa+VirFPTLUZchHTUihpEGp0RdFmR6fXGwRBW5b+Sn5FWjWBsxCmR0aLuITMwCGi
uKNE/dunvpkdV0ZshLOJnxxbT5M/rB7BQ8ncWOCfluOqjgeEh7OzPv7/xMyCatsErntfDhibrJmY
g2yvdDimFylMfpUlAxjx95d/PweAy0a7Xm7sI3TATeC/pJhEFowGGDd3fTyPl9u8Hos3sJykvYsu
9wstZtiC0wXBqWIIEWPEb3i81WRktS0xCdwUXW2BXzlhJb25BocZiBb6yjh7bSPu1cau4j8ZZVs2
Saa7m9HMTtNRy6sOSdGPiLL7kNR79ny0sylkb4kCG225RYUSdj42W4eiHY5i8E2Zky2TwSqt3SSi
Gfp6QCbOFNgRhXpG5CzvznAf1Ai7nxsfe/TyNXoXUzRzK8jJ2PLGu5+s/brMgFXVI0qO95SEAM2W
srYsUeO/1NSple0XfxOmNn91hk7IXEos/N7LWaqHWF6IsAByf5S9dCH6b22e8/1LTgVZfZnbkqwn
3mRlxQszif5j7b3kgBra7hkTxIL4DymX/37s+98wS3eAOgSYN3qYSYaykXU/EHqu+D6gdGsFC4cc
61O9gQIEoV0PMGt/oO5iIXyTfL8N+/zqNuVnqp/PaVq+zUtUks5drmIUe0t2xZWJCeKw5wKeqWvv
iEun2p0rrP5lQG7+9pJJsr4kJonimxnfa6SpvM/8Lib5nl2xHhQLKdezs3UtZEwzhK2SxSacVSuX
4F+awIHYUMV7W6Q8aaMTWIPcqdkMdNcGznqb773CO4c9oj+EsnrcFCDfGYttb77pOzGuTnE1DcBj
+C05OZmX+5BNLlWl3XlChqO48TNZYaRSqYhO6VbI23gb4orCUIaD9UcjhWOtyXX3Pq/IgcmxzG+b
SiDNcB4I4dT9itkLTDDQufC326lrIHTrmsC0LOSDrfB+KDgalphTIPtStuhkhDyNF+lJtRI/F+3z
e6e3VR/1dJozDnvKepRSqNFj83bSSlXwBzjjfF25H6bI61FZDkoHGiZj0K3LY9rKYCYcapIEPsb7
fR9p6CsxkDGcSmxbSNAH47pHQG7I1hqeKpolLzovuAHA4N+RZeHPLaL0s+lOejEDzf/AE/xDHFaq
tSfQ8CWKg65LLQYfJqhNmRQOUF2RF+h1+lW0g73Lbdk/ylqzq6HRD8AE035Ql2DKFOZHZ5Cur61x
m+L39c/O+tSOEjQDtOock1jRoOJteJPvn4JjN051NvWcIKf16Gvp5D57JMKZNM/01lXRo5CrDF6P
3esBFOi0P8eWRp3pHnmrkJl+AHfIcdAOoLMSReARtZE94CEEy+r36e44OY/mnqAmKXLYATUOpRn5
fSxa6OHr1iqP3TETIBwHjRdv8/YGK45hUIKGEGvRd8l0/iSwkwJzSSP04jfsGBoCCre8WFMT60oI
8rkxkxudoLP9LKUGRJGVwM8sgareov3gnijKTtvStbts4CC4sUoFEOKy44Fyv7MLj59cUvuAlo8X
vyHdtFyfAUYfHynAPc/v6HVW1dmeyMlGakwYmxC9i/gqAyyaMH7yebAtDgnLzLyVXu+OR7huQ9JK
Zyyn58QXIeV2fxOnluHP7A4m9w1F42xOvRq1Vk9CARcPoQhiv9AHjilBKrDVl6KflgE9kY/l+hIc
DIHojNDfRlJz8OGHN9TjV6v02uVeTiRrrR7f4eeyUY5gfvCPQ5GwVIGnV3eP8gI22SL50JGfw8EH
M5C8/0DTzWPV3wL22GGSeO0lqonXM7LBI27OutiYktcm2LzR6tBnowC8eWKQHgHGF/t/s3jof+8m
FJrhsefpj8LukFeE0X/CpWUWXcKpgxhq9DSR12DPLPDNwhdfKTgCnOLXyr6JI/p+rNX9H5uHuRYj
pgKnYOHF8SCnBbpyTuVjb/HVGbQb3zrU4o17Yn57pwVlfnZ4hpoZt/e91FkIh/aexvXPjT4MsJnl
AsBzCZhByXepim8JwfhVT7UH93538ECvaZGBR7UsYkJmt+ETqyY8+/8xQOfMsJEpIPBdQJKpiS7e
28lhVyZQUYjnuGKTZZjSX2b0Pg9fMA/nFr1DqLNlYJ9gXm8X+ikNfcNdBJSfBJHYVGlBdViSRyLu
oJ5eQGAANpC84jU/V9rITmwEQGRZ1rSsqhv3PlUePPuexUEEPyr3iVZn/L3O+pbCW4srvbYl/YHG
Mpjn5zRFZcbA9DtbP4WvlkPpUVBSAIYcKsHwW+TuF0JlOVN65nlvwn6bfNUUUJzlk/TnNBDFRrPo
Rz6yKR9PiWLCTXCXffkBX1XLEAh1FanbRRVAvwgOZTA7PFpzNPuxFchVyWLhl/yBkfUjjJb8YzJz
K73U+Qch4zM+W1nqs0q0689CU0JfD2Y2He5Gr7cJoigDHbVipugsY+vEqUopY+dptW4YncNZvu+1
NfAC2jDeB5FoOrwUB4ic5mNosoR2Sxn03csQkOZdJH+c2jkdyvmDMM9nqjXgr5/GUEtgrbOqFTfn
hfjK19uAl9gmucHeyZlrHSgoIQGxsMsKnY+/cWvP5yton5/bj0ezim/uSdG3HHN/jiicwflCJ80m
Tp0joxcYkkBs7tv4FEbhHo2ji9FWn+hia86yzJ35aeUHM2Vf822C5uAfEOy9vdOse+vMgj80JxQz
tqHMVQuypGEMjSIntajlFoAhfpMYTLmZMKl+3NBmrNK8VoCpLVnqJrsJyVCVjRCnrW4vcO4BP5LH
y1GPLGbTUB0qtKOWAp374Y53G3uDwrhIqvU3FAo4xJUtBiqX1TqnjRgwZ58vot/kLsRMMOStIatF
MQuzASAikq7GKKZHAJTq+pBso0Or3/0CvXCSFBfNH7A84qC3CGZE+g+j7IDVkHZeBMmAJVXGBp8e
uOiKWIJ6OUJKSaNoUyA/gK3WYGkk0dgcffM7egSE62F+ZYZ4l0tA/qHO1clfd4HWsyGkqWBmiZc8
uSwKcZstw/YSTJ7Gis6FQ68SIOjn6QdhlKYJWYaIWWxP2Z2R/diPC2tzdIgn8/hZ5vIUOnl+Gn19
/pbCAVqllczRomLfZmyrNjjgY0wsO5Crj25uqSyy8C77oVtCtn5tAYKfu+6NbjFzYq9OHkttPtKu
ySCWsc4UxnoYmk4WWxVrvW1qypB2H+Xp8Fk/ZEA2pCviskImSheZ6ItBd0gkI0KL9aCrnGqF6nF0
7vlbMlDc6wlhHRykm+x6Sl+7qjLEKC6RZ/9s9n1cWcbjkE3so7r1jy5jjl6cK4QO2oHUU8aBZ/+W
ZTkPKInn/g2VzXT8mHtodBga2VPW/o+SpoCAUdalfhibjH0+jklCMnur8/39TQdFI1Du8pKmBWwz
39FG6GQe5qZixaKx2eaozz7bSxXUqGC2TUQktVfw0fRoS5fsxwik+13W5v6aRCseZjHZgFtVuUjx
rWAhTjUu/lLuKD+wBedO56CGv3z5lNFI/2b8IrH+Dm3VesfQ4EoH3P1ZwEVOL91XEXn2sFErQgau
9YS3VZXabapgyxp1ZSEsttyU2rF1gOQq17t4dsXPky6tigx2QhlI7TdDa4oTAvng/Ft9Rcq9Ybzr
Bg3/rRA4YBE1Ezf6Y8NyN3Z0HWhh75R7CRWOVqB/wuvpvtObkJOJfbk5OuQdpgDTWL/KHvxg6J8e
c/f1hIjzaNfhg6i7wsPknnbIrRUmdxUK6DJi6d44AO6sc70Gybf41iruCXeYGcksy3LglRBZqk1r
aUohp7Dfm7VUJO1lrQ7rcdjQ98rE8KSNotz50jSqsSUhzdLzmjfd0CJhEq6zveQLdENbh89l7EuA
L60fQC1Ges+u1IX8Suv0wMONy/5Dfzigt9E0URmJ1kJu7D4s/X52NBKyAR/5cskUJzFvY6T+/rYk
Dlci24Yi8gYiP9TVlB7g8qxOq7HhEygShmCf73jQGS5kE63DhF/SGKfVZcyiGuzly24bGSbjfW7J
AetCxZmIR61AI4tOlSkoi19aLKOV0KsQw8Zd8StIYv5M4opVzeLghPsGkvxvBUI0PKTrU10QpOJM
nwZzhOc99kDTiv3sj5yAx5BYr14AMfOXTTweB8mPfYSo+yZ8KgOk4EBXCBGjU5tfUXwpf+afxo+X
8KmAuntrH1Lcmn5/+h8fCl//OLI40i1bXqlvqMKT/T6t0s9TNunPrNQEac859QhJ7HK3GYwxpaww
iG7pndyS667+Gu9japTCfmIllpuFf9Vlb6AGeu7fS70TBSxoUdjpa6uGwyCb0EMUQclSomwwJrLm
csfYXDbEtRtHeWub+dqDCUR7iiQpYCp6Ifh2lAj4cfP3uavVE7dUNvL2Pzdwz/cUg1pxVfkSFLTJ
CJj1ajGldV+Pv2hdAEfmqidx340qCmrMduUdZylTQJJ17jqDzacfkOBZ97YtY9EgftK1hBzpZRMP
pDUcRz5b+XBT+OKG7IXCrmOurjSesTT33WywPLD9jhZsIvI/Im2Ha9szFtpJyF1f43XyIpEhLZ2z
eqix4zx3gSeMTr8PBztgIhj4pxfhA0TyNo6IRVS1f+6rdp6LXnNYrenyQQLyxrkXQ9xrGBFBCB/4
Asn/OgDUbrzqz6dg3Ui0RShztu/kqt4w6xpVa5j4sNpvgucmrNza6T/HyuHEPU0B9yJzplDvEoV2
yfDzi/rmRGwbBsxqGIS2O7wp4vbpgHT9EDSln5ejgEoI44iuLnwTLfMwhJJV989sPD0ZxKF6Ythy
j3l4QzrgqShjGKaJYRdXbmeSfwuKoxw6FVBSB6873gchR0fxRTfu9ZR1rJSnmDKSXSugo0PThCv6
j8fucPTUvrO3mPe4Dh0WxZ2DkEriBNcKMYsCROa0/yFPWsKB6hPFvRqJAVhlKsyKg02sCcSZmoeP
m85dekaTPy0dTmZZrHUDi8pxMnvCMweZsIm+1m+chQy7xpn+Xid8HQxJma4fmsPHhVhkzDfAbaIx
zg9Umjpp3zHvaOaktM+NMYQu2fde6dYXdUxWoRVvqRccE99+6l+wA9eSvJ9lUBTHefbiwMi5GOkr
DHhKAHOm+sCMxUoLwhcW5rUrBYgTxxZ0jK39Jhww12tGGSlUHu+nt7pLZb38nq+3B+43L01DzP5s
JUnS6M/+C9/qQTITHtViSabjWgQmD02+XU04UFROWBJ+PB22QylYWbq4XCCl9cECXOcQtF9sOzjZ
vpSoeXTIt1dwryXVJ6o5DW1CqPAvbETjoSY1a1kcxJj9ipFgzsCsSZDkCkus+JYC+VgZX6QJYLmO
UP/kymmJ6VtZE8R1KrM4fMDsHnGm5mSyteI11smOI/htyo4Dp7Fyfqb0iAMIQnM73MVTb53O4Bx+
XpNQU/uYVwDWQszjm7avuLnQ+hphU1+ODVxzOkxrCNzuPBLALvc9eFUFheB6cphFQhKcbEqDC99c
Yj3xgBzQ53xNAcsHa11iQNgaZFc9flxgd66A8kZtksJD29r4XeP3Q+EZhyNAx/NNFITGb9bjRhdO
MJuNQfSxvSoFj+NrJrX3POpU6B5iaCVIXXl0otTLzUqBFB/xuAvVkTtC8EehBUUwS+Zr9t6Bh4yG
nw0Em6CGCaFv4eUnGK1y0FlgZTOd1tqIw1lNnFv3K0fjAApShaYC0o65h+1ocdN9dbprb9Ex+2DS
/cRziUVLlIpx3chP6vVc4Tnq+mWQJZXXG5wcAh2wBqD8/cC+eyiw1PYvB2C7d/XM0T64UTsA+HCK
jggeYmgiKsPQujrWSWLxIKCoSYZdhUAo0d1S5Ftv/kWjuuJgaaGFcMMLAhvfOmhKLYqr2/ApP/P1
EAw3ljBk1kmbPo1a2yU7C0lEgfqA104lkK4Vh+Blo/eZS33+zdy+fyleazIAOkVM9HJvfMcBHWzj
C+F/dvjV918QmJhByXuKml3d3eBEdpodMPYp5TmaU70wg7Hn7URb4SAYhoPUyUoEiZfXYs2IXxla
h7Vshlr8x4zwD746BWAYc1gC0OskUYMqDajNJA1CoRSTWJDwnj/dY7Q0+33D6UjfeQ06qLR1Ld7k
fH7DjIURGp6F3JNwtxTXH3fkspGbxo9Jma9u/Zh8SxRetwQVykOWUHeSWuDloyKQ860AWKu+ntrF
TN7wj89nYoZF3p6H9RpH1CKYftt67vRAlhQPPuaS3X2u3+NYKHPVY5qKD62aRjyMcaICIEkZC4eC
za5b/lJQrcK6r1530XrR5dr6YwtMeUuX2TArggVKKcNmUSybY5H9aLoORevcr0zhBmczV4xs6n2i
dMbyEoazLV1cHV/4MqPY+mUZwpOpDq78GZ/woflf7CLizr1kExtAhsrnUpG9fdL7RoNqhPO4lWRo
db6/WsOu0BA2GoY+spIA6DKGt4Kcge/8vXQh8K5X81KLa2pdEZMl0TEVYiviRv3fn9R+YDMdV+3y
3AwBKt0X3F3XNgelOacxDFX++19VPG6+HK6tYshKeuaEvTELsyguwiXAGnV+Qr87oQhui50e8szT
RkMgoJdOscjTxFHeTObV6eiDigjW/rTpymfl5wEPvccSrgpFxwxquk4TJ36KBws3dfOu5xRymudL
S4kK2Ac++xzg9aCQDeKc9ScLocR0QSVtntU8INTgVUvTq8FubVwphu9oVj9b7Le7KnB2w7iep1tP
WknNzFtyIeKFP2CLmk2Oc0zkg1N943sh/dGZjujxE6amzXz6wps9Jvxe7i4Ld+cW28gCuTz0ix0w
kAaxBDruWaBE/YH2nhwZMoudRqIHaLM4SR5fgkbDsfO3uaY80ppMuFO0JpQlp4aLDqKnw+25hwGI
pM7dtyHlM96TZyIloJB+9XAEsavBRsIIDXkyyd5SkHDLse6iPv+hJ3Ji4HoB8rxG0ZPyLB3dm4Aa
AgAT6PHdsjtNlZ2cHzr4insZBVUoDDQ8pRRqhmkSSKjZGQ/sFZHsVBTS3gxuSR9T9f5S8gC5sfNi
btSM9SHXzi5Eg4gIyYwoy+n2TBzmt905GlAwRRWrdPC/VU3Wph3tezTQvcurhSzf2Teba77go+ko
8ZvB2qsT5YqChYzJSz4S3xQWYxCu6ZP9U0q/AzpAV9Kda4tEItURPWkw06dfexqaCkA37aF/jWIE
8cToCfQb7eJxIM+t/kzUT13gcoEltjRl5FZ4K3IBMggaRALtx1lSTzjKJdGk8bDW11H0Q2K9koc5
Po1ZkZZCEZHLrbvE4V0Z8z0TBWQGqhQU2F2no/RoGsocZ7BWOgxM47snMPZpEelnX8ZDh2fgVNOD
reN27i1iWqhyd1/f8Ye1sIjuXsPh5AMgnzyfvv8uKae6G0qHM2dE+T+Rss0GfvsUD1oUPnKbaa8S
nvPBOPaYTytU2XrucD496pTUUGm7qa0N4agMVVlFShlsSgvKPEt70KdoAUW9Kl0qCulg8YevYUkw
WHaDCDa5/It1R8U5nOEocnwI3x1Cos5I43uYjH1oLvPWrLb6rtZtNkztT2sConWI92sgwHojzrz3
+/rL4vFjlGrWpB7HlcZl0foPV6Z6vYAtEVKtq57i0n5jJgc4S6GJ791Tzgl28ZTXU5g/AIX3TwW2
UObtu+n43Um4VpiHzxicI/X7TTKQvvVi4mTBENwSDW1Zl4uTRucD/Jhm/tL/U1T3orOpsmifmGr4
MqoLe6oWeXvbaqJbmktoH0693ZssagDrf1r+8rYovQ4IpAen65xKVNgbovSv5XEhcRy7rtMRphEp
JiEe70o2DwM8ewS7N9uYOxhPXAfViJvWiU2UhH23IEKAZE9p6PuL8bUBieUJLvp0gSwIxVcV4me4
6ZxFvR/2CrGSZXJoBjrbErwdKPvuDoiylx1lkBLvrsD4ZTSdtZu8zkqxprrDsd2QwYBHYUcvR3EP
bDkXZWd/UH5LAYP3f+SpPfiUWOeVq4I62TfLGTm50JatA3s29/ADGdGEJM6LMn+5ODH8HbgUn3ci
YB6Wi7++i4FiRFbj8SFbTQqKwsscQp5BNFLAUuesehM25F/x2PqraE2ZHBs9I+l5QMYphMcWzWjY
hl4R9cCKXcbzik7D4jbC7PCtLEFBGHUij2Chdq7FAmIcTcJWJVMLMQJLn6DbmFBf5mTUm3C0BwaN
QyeiZvyL71/xdWrE3DfCE7iymi/se0gn2TFSwFLuW2oIuZZHprhfZesE16BYmFPuSKC5G78356Km
Z5/nCVkTwW0OpMLUS+jwINkeqVy1rVKGWBqwwpPVSxo3F1zFWgiXzxhiVaTWEHRuuXAscbd6HYH5
9z83zoq1FQBByKoSbk15DFXoJUfmMp2y0rC6ZmE0U+1QdGwhCHbC6pgJn507gQhb/EGisIx7mYce
VDrv2MGcuDWWoSFrEVNHSlE+jLF5xnBYFJ64Hf+x/Is74j0NP31dk5ZpZcVDZcxgJc2f8Qz9h6PD
o28PVnjB6A+IMfdgzerMpBlS6Ic/AdnLmTTOnCTv+4JyeGGW/G8AVtPDVrmCG4NdC2790+Cf40vj
xppbt3+s0l9O8LPUv6zaW6RU7yAEHuzle3BPyAUk/+dYniDoDTfx+MvIrmoc5eQy4VRLRkRKiH7V
MCYoPF+EePrJCf3m+JhU05F1Uje4i69tjbUD/mb9EeTGaEnkeU7SNHdVEHpir8FVt/l9aRaX6uVb
wKQkIBQ1mLyuEkIVae5rdUoo50HI1vAY5Dqiwv4eJrBUWW1eqDc9hlo6X6u4rBSELaVGD4VZYsUE
yFz2BqRHehVM3LeupIKA0waKR1I7nRaokEKhn9GtovIMfmTnBwrv/oq6dfsDmRjeyplSZwuD9zHz
l0pjgT70pk2MfA5xuheJT9OjyPA+SMXb4XBLW3FB5C2kz3ddIe0UIwIDMPifsLCKhKSdCTi48hgy
hssvaVO/tJvbVbPKGzy5czxLgCA1vDWXSuGzVuPw+0/khqHLcLE0fEN9C0h2pfAMwcoTU9lcsb5+
ejKF5kPsfArwy06hIG6hNGVKib3DIifMn9bVjAZ6yI6AIkcEYk2VmCh+aF8OiQICAHv+yoV3EF2q
mlGKEFnjNxW+lcP/dluRP3LWg2Fdxayo9K3Kd7C7DSR5OEj2gLARcVWdO9Kah0CUq5Zvdo87Hllk
uJm4MdcugUlJqtRZC8MIgZ7nh7ZQeA88A1PQgUO8z6akWTpTD4tKYMdIve12/rbNzvDqRvNdQjj2
vW4P0XRt6B6O10ccchgACd9hY80B5UheMFhV8bBJVUp7HhGHHklMvPhSJ414R1XS6CK4VOyoXosJ
c74wSUXmAg31KXn8GRhJtZVVnPq5q8aQZqJuH8MqD1AgReu/BRlNzaXOXe0WKOk0DcGjZV3BI/a+
5vt0qfqKe4aZvxL04/ZXrORdORAk7MFibjp/xIKORNLSrnvLtWQ1rPdUkF/28K5Anc4K4N2Ezs+/
9WCb2R/FtEkSaZ0Gl27z5nmx+sSiwfnHxHUXe3Z3tML1zb8dBgVBN+7i61pvN9N3hBW/ek0CeMZK
Kd7LtGS42816O77M3tvzme69AwAAOnhlQcf1gMutPxVCvIvjbJeJt4u1lFKIkWW5cZHgCOna46+C
ZMtTERn5YGOfoZouNwpln1nWFzGsQluQ5Gs9yVLfSL9OnqSraRVS5Bh3j6merrsUGy+Th+J+aXPc
6QFFydfTI32EQWfPHBMaqY8qlD2zeVVJ/Vf7vBtesUpw9PLTRXRPYcnEMmN9wgS3VnFXanf5VsF1
P2MwI5wjv1oQJiZU5P+H5g7WaP2VeTuSlyJD1Mpp4t7KVYKuMXwv72627Hgoupwota5PTxyO6i29
dgSTfB2AyAJHfQx4iTjEQ7JJWWbaZHLeWzcCOBIY/OYheGjU0ERfMIACh4LaYbuPcyVhA4msr5NW
gJI9NZkDyppCPSn4iADsrcIxsk35OJdJyJjn/Ggfx5cPFrJ7n7oKk9FPMyXagVl0Q0ZWbslEjKpA
NkSjuFTEh3rtcuYyH25Suej4+/zg7mLxtkqVaOCuCQiiKLp/dEf5B3aEjOvPqP3F0o5nE+DP47K2
Jozt9dgcH/ArWey0utxbDAlSzG0TyIqt7ASWlAz3Im3heknmgGaPhda6b9FgjMq1zxVZHilpLQzT
pv37pyaLwE1ocPgHIYKxczPOb4HNNo0onOEGFNmNkx6RmE8u6qpihLPLmduSShzwLPetepyhHMTn
Vd2KKifkRqpT4lY/ZVEhbNK+hcKzwBhQpTMvd1acSVFTX88XDrtnWxM9IXlb89B41jI3ZpSvYeab
rMvD8WdaZYqkzTU7sfJ3IdPMVnXDeXhr+vlPcojFjOe7sTMz2UrLFvrefPJResonx+ZmdSEvYkRs
Onjs/aJQIsy9bw47TfJWn3I1sa8yg1L/KkZJE2dIEsjmek0Up0ym4o6K+KcDHV8LNuQxY2X0XBX8
1WoNb3tLVyfRgY++QmSFX+IomM5sx7vJ3GK7p2Tm0NBpCXOJRzqQykScJJthb/TzkXyG3ymQXGny
2N6FXnsJSj06eIsEN0HVf/0+wv8mcZ5GMPBE3DYg9qEVD8hrg4IkRhWY7/7+46lFDLsZIDEMDSYs
0dSffHQiS2mBNw4eNu+ievzLQ882FZGGWImNKgr2BQN3al9aoUoz9FY8u8Dc9B9s/p2zp1AZKD6G
Q9taTSEWv9MwpEFzzTCA6/E/o8EXzBheHDJ6KnZ+RY9mluP0+phE1T9k56q66exmUWN/xpic0R/z
m/R4T8S4wdIE4AaCXElZbL3JYMWyQDca5KjZuu62D6EK14Gtt6FXg2EzeAvPvYYEjDLpqAp/njS9
OtpcyZNQfkBbfWeFmchTNAANh5lVag7oL1fqJ0/9WYREIYyBqMrUTQDc1N5mYpOtoEeEHK8JzKLu
Sv4aqtekYGtLoke/hLHZn5srVUwqQMuje7GGTUjDvLWTZM1kLTlEcAfO74hUCmOZ1ch1YIfqAQZv
9FQaZosHQpJGv1x8AoOKt3kcz9hyjDDm4DEAud8Hi1OV7TVnRHZsAJGvI4RKgJtzj8q4xIjcphN6
z214eAo2egvvRtiMTcsDHwkA55u9d7lm2ImUOdaeX3mgxKxMsOp0jlYgcKx8FijParDzDZt79f12
EzoxIK2WRYiQEwrU6k7mUwn0u4gL+aiN6Nvd1NNjEiAaqsF0W+gkTvFgw1Ly871Y2RgxbMxJJPL+
e8BOT2OiPh9CmFB7HuVXk8J/OPkTaFvZDMac5CmX67AvDmjaQzigXy4CDnzklfDUgxiARTDkf5B6
Ep967BNVxv78TX2UkbZlKVnmQWM685pM6+M6enQhubiZhzVret6wTiMgjAhC3gcSBZOof8ZmuUnh
quhlD3DzilcLi5yIHbZOKNpIDgroBKCEl1P5WJXwKbaBk1uv7Om/LNy5N1JTg0b0JA5vtQULU/zK
DMcfD0SZMEImwX+vvZZeWxtiTRLkIbooFV32MC3n9IAU6/8rDCXBQR2oJTBYWZ5Jh2bvayQMxuEr
KGMIoc3ys8ldBvTaTR6lcIgaTugICn6f6k55eAAewWN9qWThPrjc4DNRleK38ILcBvi+JOPcMkF0
Kldi4WSj4AG/B3br8DJXzS/T1AGoqHGHu72vvwUnFgh4b/EJHxz/c0KCSS8uTswu2rgOfPE6p1Fg
7CfIbCnXVY1aKe1p+pzwAjyJg173YOcK13TPtkDKJAPNMXsbgF185F5Kd0i2qxA9KNYRJTCQQioW
C73IIZ7GrMbFPrE+FbBvkAF/WW8SRTJV/WSdj2jarGrCyUImygVeVCw35GvnNMte+CXBttSPAN+y
E2WPq4Oni+MbVdDcoDIDLvxysIdD+p6MpRznaJMeh/33S6+yWRm44mk0m4bcba+I0S8jx127N1lN
cdvWl3iaFdlBXaWa8ajl2sLiOAegJ13l4TqZPT9Ru04tCNLuNen62GSf/KGo8Ud7rhdaBbnWQyaP
Gp7KJc30aYA2ALgg1WepnBVgru+C1/6oXZ7GBLUqdcQp8gVg1YF87mCQCZ1jGwLWsFUvzVuqc8Xw
epGCXe6k0HyflmGkCsm3QUMxVIAAEpkzVhrViBXWKRVLdONrm7o3Vvl3ZslIqbOZv1OB0l7WyvEU
7qTuGKZiV///NVDymfiE76vq7JDpyJoE+KRA8JVJWm7TkN8QL3d8M1MSgJRW6EuYeYadSRVkLfzo
qRhzI3UOVhLaPmAKwCsqhnw7rRJwdmpeCVGE5J2GUpIvgh4dYP67b7NAf6p6ZuS/JZ5erJ+4fsgf
17bnHdBXpf7vCP/MZ4cHBWA1Tpso11/dHiJGTijO/6txhFAdm4YpmgJ52SOiBl1HnpUuWnCHx+EC
RuqSfn4ikoBsXmPghLRLKH6aUHnydcWzkYc8CU0vxkFEpeAbymRdZyS5YLE1dGa9zKLdB8CkJta+
YX+S2UdfIGSQsHo6KTALfDCngHajCTKwfNbRWiIXCxRmiaVlm971Fzs+q8dHM4AubzGI0wHSHDu1
Qe2dF9FCVkxxzr1i8rTWo+/uN0RkWl2T3DWW0QIE+O+wqcrBRYjXI/Dixgt6rgy73m5lkVRsJCAP
Diy6IpB6I+RUX7oUUcty77SCKYQ24wsxcSkGv9ans5cIZYjcFz1VToADzs1zwqSjq/LcS7ltJm2y
zTKRuwJZ5/g0mExv973GGahXzka3P54o6JVi3wPee8dE3XTf+S7h9Bhyh8Gpm3kGZv3XFcIJw7Bz
Xsz9Q6s3EfDTdGNxVYdIuiGM7CDVXNN0BJb+u+bOfjnHZN+YsXaJT94WOreGVgNgWNAsY94hJMkM
5wPT0mTY+ziQhRg4uvTDGtj00wT8ktEZe6Vswmli3aD2yGesAi/mQDexoZZ2y1pHtE/3m0fGAFkq
+M3DSVWcJBtCzd5C38/q32p3evG1ISOqgyyAeUpvhwetl6Srg5sLrQWfENYoAuPmMPjSCHnFjnKV
EFMv1MfduEOxOQrGERCQKQ9N7Nx19zUOZ+uxAh65+8xa6Bl/CnHFbg54vbs6TvkX6ZK0caJONj2n
2XA4PbWDggtdOIAfjxwGG/yezu40Ypr4+JRxc9fqY28/AK0xGPv1iMTM1z3NBacCddjoVN86ku3C
11870p2RFJn55QSXshGOc9f+ohC83nYRgaAL/hM9YZ/mxSqL8+7OH92d9S9hxddS2aZNxJNAld6e
fImovMseid+4TsJxSnCe2fsWbXa3ODzBDYAtMmWsc2VMJG529QjhcRNrWoPQrczjNkeCAadpatac
aJmqtwPQjroEQvAxb1MnheIGFQ5iGAy6U/49JhP7P1Vbz6R9uAijty0j9/IrX1Ioj31Xy4eyO4Nt
aLiyLtkpq9cgeHKiXyeFWVYis7uiY3cre74dvwrWrjl7ZtAAa69T1w0AVvPMNL4eGIjK0ZT+v6Hc
9/AcKyeoO5g8EUEGm9tdeImTARPSNxp7T5gUkJ3IciqOMFBCd1WBKvyfBaxl5AukgTHCC4xlwd3H
z/M+tdf4fky0pFbrvdDkAmSSTU5P5PQ4Jl62ArXaViT5wD85ks/99+0V9e9Hp92+XmCcn0tbKndu
GDE6ZUhCDiiZ7vZHAfHt5IFL1TnTKVFMmwCwvG4f0eE0zJsGIuuGmYFNW5HpnCIrvlkzKn5nsa9q
+qXu24yzr05elNBy5poAmPAhE0vIrzb2ma5/ZNXqh/fd+qoiQ8NYcEjYjZP9cVw8/AoK4alXEfDp
6maLryhr4iutgUlLSTS3TN0YdBnaBeI1NZjdc6Fh6PDkUBDcIqV0JufbvKHkPh8LWvkhj7toPOPn
bXUNzD/vKUfMaADP0wh7PDx1gVx56oLZIllCnywfdO+FjLtzN/4oCACGg3JrG/ZAiELgMuSfwlhH
zLfX6d1S0C6p2JA=
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/compare_vectors_f.vhd | 15 | 10255 | -------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/compare_vectors_f.vhd | 15 | 10255 | -------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/compare_vectors_f.vhd | 15 | 10255 | -------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/common/wr_pf_as.vhd | 19 | 27402 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
| mit |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/ipcore_dir/char_mem/simulation/bmg_tb_pkg.vhd | 101 | 6006 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/dynshreg_i_f.vhd | 15 | 20708 | -------------------------------------------------------------------------------
-- $Id: dynshreg_i_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: FLO
--
-- History:
-- FLO 01/03/07 First Version. Derived from dynshreg_f.
--
-- ~~~~~~
-- FLO 12/20/07
-- ^^^^^^
-- -Now using clog2 instead of log2.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_i_f is
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
--
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
function srl_init_string(i, j : natural;
w : natural;
d : positive;
bpsrl : positive;
v : bit_vector
) return bit_vector is
variable base : natural := j*bpsrl*w + i;
variable r : bit_vector(bpsrl-1 downto 0) := (others => '0');
begin
for k in 0 to min(bpsrl, d-j*bpsrl)-1 loop
r(k) := v(base+k*w);
end loop;
return r;
end srl_init_string;
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
generic map (
INIT => srl_init_string(i, j,
C_DWIDTH,
C_DEPTH,
BPSRL,
FULL_INIT_VAL)
)
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
generic map (
INIT => srl_init_string(i, j,
C_DWIDTH,
C_DEPTH,
BPSRL,
FULL_INIT_VAL)
)
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v4_0.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/common/rd_pe_ss.vhd | 19 | 28350 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Syf21YU5JnKptD7LOLtaHZM+q1VIhUFTxsmS2r0ofwQ3ushsF40KxXOCQsGAnXjGfc9kVb3Bn0ME
1qO92hlu9w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
dY69aEX8OSz52Pib+7B1y1Wvr7162ZPVuHYqEcMQ/oCfJJrpwF+oy+zQI55NVyz5aWKsTxE6uM7J
HbTWuphJFeGo7mzwyRD7dy/8IFTp8OHV9aN/fKWepd3R1nKJ/+bdmSsliOOw+inM7pfx0a3YODTn
FRAbVAMQuwe+OVuT0dQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Q+4W/1zvXVAi9QMds0GLwNMATdnR+yvz4Aqge4tYro137XvQ9NhFGdF/mXOn40o0ijOuTLANSGZq
Y1fe5IvAhv/BzIqGLvvBSGadUyLWCe23JTco14xHGh+EcGpkQzSMsD+MtFlsKB5Lh4Pk7Fki+zjY
CYS3IH1yrExDySGaxaJ/xIpVmbcDUIB29ts6Ape06rDNuWSEZkqi5ATlUPCMrVpXs0LgVRBipzor
Mr/lCisQJrroeVDmbpQGOxCT0USTTIePtqKzCRURmGOM39JzikVR3QvCxX3V9zs6LEiHJnsAr/WX
JYHo8e0tsbF+S86/2TJe/j8LJK3VvghHADCdOg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jFetHSEk8pl36rsszcvK1lxgvI24/D3eeWIqqx4SgMWK5zMch2RGKDJVjZdo+SXrQZtG4vIfoNJ/
M9NL/crW7IJ+pa4Cb2wH+GD2pA66Yo3aRE1Ld7EknU3x42o8aAXlhcPIjcxq9tmSO5RxnhMKlfjh
dMPsoD+Mezyol/EwGPo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Jgq62sziWqkTYcR9/y/ZRFUy8fWL8zR/UZTwiK9JRpmOKe++dsuUuVffmjjAGJoOkGM1fnXZqKj9
LDnUvlqAYGJAQrwT7QRdCNBN9eBMyr6WJUCOkpNRo5aWbRqVpwZihLgqtvesSbzoaKe4eDRdiEe1
xKR9vPyfNmAnPN1pwf+2YDUftVl5x4CmlqRUCO2c3iETzT+xwYzxqYKolk4Qa8DTTYe9PvjYqn2/
dj/jpAwnTcOKUqpa/3FaAU1zgLKWphnnTU+MOfKNP/ow3ZLVrmyiraKTGZlBmdJF18AzYgHb4rrc
8Z8DuRLa762hnT0qbzjf0vtKn06WBHgWqansQw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19248)
`protect data_block
73fkIQgH0nh0uGpbXVs5xsu4nDUgZgUEznyliPLuneWZg1ZmKjrPY3Wn3oHKnAwT1Xp+IJ7iq4c8
MmJabdVAZu7iLqHjux1JoZxAEFRYCvGFW9znglS7Jj0CLjKYZ/cfFCV7CcAQNj03a8inyUXlMxn+
/ZTdZQam0thxTPmhwS8NqFGOrJ4yXjbRTWC2fL4yj4vQqii4yTuWAf7HeEg6Rr1Kywfs4sA2ji3B
MRs6zsZPBaahp/J55BNHFJcbgoNwGqVSj77fj5kZ5kLF+a8cOSm6HzYoLQU07uKTw6tVRa4evgJx
z/prLUHR0iCBm6sepQaqHG3VpwpYEQQmLpH5UTZWBwWid55f6gjcqN6nfQfZd+HNobsU1scGk3hF
KvCqkZsIUcw/9ZhJCsHof1TYL9lQsvKgNFbCDXSWIvMG0oc9pMhmGNm6qeiMuxJwEn7L7suSc5pB
FaM+eEhORjIYtcxEPw8pUOKIhByYmqzgFIt0ykc+YehKBxutEUE4LYBo0eimerxb1v5LvQnyDMj4
KAxfoeWwwWnDQRUC49+GdlRJcqKjO1bPFVkDOa/zwZSFGW4aknUF6n54ZX8E2PFXKC3hOKYNG4ya
RV/FjBAPB33EHrz2lCSve+w4h+J56eSA5DGA7y1WBlMk59UQgE1XARyckV1WJB88nyN8W/vQTDRl
nsASH5grdkci609nhJSP2ZDz0gxFf4jEqvix5/r3nxiJQCTM0ZLBlisyzyvvBSL6IMBM4x/Ah5Od
4V9reUXXxnSTJ5T5fJdtus8aIV+FnZWz9EXPc8aLOcX3q/LMmPABTH/gM6wI8wUZjtbOfRNxuh4K
5Dl/jPg7JvgUUyLdgMFl7lWMkh/vWm7gq+TxlozfT681pT8zMe3TXmehE23Gm/Lc+Yp4++9a8J2E
nzChYradLs+s3Ybshiy9BCrWd2/1h7WC49Hanr7iSCSJ0Ix0tfR0uPWR8pcmVasUcEfaKHyClWt3
Nxi7vFOhiBjglECRLq9jQoQB+EYHtOGjXofjCU0Hia0Zg2aqxaElbJ2X4wW+1z/wNJinvLAkXJ9x
ZSvI1HxwQyB8mqfp05Ork3UOEkZhPytzDylvlyOQ1WnaBdv8+0AB18rkRyaSwtQfayyDV9dpDgPK
6s9i5EXkJLUx23nAfe6Fq8xDdTiQ7kkUddJuxe7WSNlSbzNu0+i4intCXkcoMyY3lTi2MQZ6JBiA
7Wqu08On96x9062uUeSZIVOvamgIGLvRJgIp5tvOYby27eILPeGSI/6lKNWLHAObd87l/AvZ6993
pEiZtI0Q9M+d3kqEgpif73Zu3hWEbg4sbX1fpfBTm6coN2ey1t+ryFo3nb/GEXU5ROSbSqIHp2ZM
0lnKPVXFmVwlRwUd02mRAe0NAWyQiUZmTgFWarpC/pjGeHa0MDjC+mpH05YnlMA1WA+7goU+2Rib
M43hqrWk1gVbAR46v8gom0jCGD9kU15PNxeFgZCLdGNaNMvyGhac7w6mE/lolgANp7iEEauXgVpr
VM2e8XV9Mv6eoddyzVq0FxqZGeVqZVAIcIWk0fRN2OuPcQgS9+EAWU114M4rrMG9g8f3osZodHfU
pVKo6S+WfkRkS/tqsfWbxykfNO1wxHS1PmktprkJ1rCHHytwT6aIwNNFVn8A0GOsw67T9yOrLOd1
cVas+T7mUXYdtEbVKbSmsjSkuT8TErTDrqQUB6s23lBnnXRXNoBx+TpU4y+j3KlTFoHN/4qqmg7j
JBzEBtFY3LVzKFovKFJ6rYH+g5Hnfh/r6iykPVemB8Fxn/S4vp+l4rpYBPE9tRTeUs7wfPQ8pJF8
cVsbrQkPfjGyv9F4jqx2aYveQzYhjH774BVk58nOa8JjpLonsQC4LeIBG5dEg1nc9d9GiBdWIAyO
PE529tlBifTnKVduk3YtiQt3OaA9Pk3Le+9WXJ2kEy5xzrUc5jThSRG7NjuEB84MC6TIyCGZyyXV
xYP+QuCqlqrHIIWsA1CSXl2aOPCn10smp3ElTFIu+GA8fEElC/UxgDwhFYurn/ZjZpCTKOJnPTqP
j3/wFyD/hk/7qvmnDiKwar1bJVDU/cIC20H1KF9aBuFNrAI+kPWwnuPLhBbZLdyjl8aVecRQelce
dt/kY6/3a0W2rx2a3L0LfCf9AeQCI562MKIwb2aBcy0Bj6tEqNZE+K4d+DbwI7YfXSjs5tDqdjr2
1QW6BN5qXAkLFOxfzmpemg9JsnQPXdHwxU4D+x1hLILGhbsETiZexdtLhjWp0WgpW3gCMTVfvKgw
WgnUlcfAK534BJdDdauhDDK/R9P00aKU4lClLO7jIvevSJc9aSXd5/t8MlmtPoWDq1Mc2qxw8D+7
XifiScc4R9VHpNOH7V5F4vq+CyPZwHw9ulClDh8c+7Rnb2P84+b62A4GfOegjf3/u3dcoH61Kz9F
DmGP+ZmfRn0+Q2lUa4NetaH05cOu2yg1dr0s9gPYWXQFEg/nIsO1nfi0PiAh2fn3d0fWbK6gCOLQ
pXJPxEh9/4LVhY9NYu2TG3kv4WralByuPaoVUEhTqZ3stIzG+AVJooZNGaE2GKsRpVxoljpTJN7q
RMwVvbi5BZjJoTcOt/Jbn9tOHgc5sbkJSXtj8ZtlGrChVflwdqPa3eWhv6F4D8drFPJYoQchN73l
v6bmA9H4bY1LSvHLShV/lds/KVkr8zeGG3vSM1rriXqGZcrp2RqGpeKLbPkZ/1arMUwFVLhlSvcd
K7RU1dc6GIRM7XKfbMl7bK6B+yBlGTmwM67RNA3kqtaNFhUqn5uTj765ds//dt9BXIN5ziSj/p8e
BR6oxTAEorrRQ5rEoUrzG8re2KoQ4oZl8fDstiaDXJTTcQNlzzMoYmyKJxo7Zzk3CssjBkgTe9Dg
tKxRNgFt2oRbEvJMYvj5EiMeUgemY+VDOO3rdj6EzrjKufXf7jMdoNlVuQ4iDE46N2JDpGXUmai1
ztJ7qjwbl4pxpKOuTmhmS9kc4LLPnZmFxXsdCFGuAXFwOhQ+Wo4Z2T5wtk4A3EeIIiArl0d1E8yy
3rcU3B38pROvmavqAHWwqlbBkj0178cOZzRhw89/U/QoYsasOUY2uHZEYZDRgKf1Y0gMk5r3YrZN
EGvh1aY2upmhLtItyRVfXnuNN2jYamasqAA1EjLPkzMuKmiWmic1NW/RvyhHZpEKikdhcjdB2P4j
yA+vaKr7EHYMoeeovd5fCt5ctL6q0EOVV/V/QGG9aIZSPA3lPKWeZJViECQSh3xvjVkNP0vURmZB
vTwfImv4L0KStahGg7CwOhTdOIZqrD/M99+6iB6cNzxfJ/mj6ccq0+jViuN5JF6r6oLnlgn428HN
jEvpGEhoQI9oSCEVw2hjgx2HcTL14tGpzhfy/g5lHMRiWaRaSxPcIuR2xXXaqSiLROr+stogy6IR
L3gMLgNqKKGyWyfZZtzjNaNCRQF1tK4BSSo9DImYnsesc+2glg54y3mQJMAvCW0ta1c4Q15eQLs3
UaIiMe4Hu94l0bSEgv4OHLKTEJcLBkHI19T+3zhzwu5+/cqcyMG9AlTZm4pvJw1OLciN3hdFc4Xz
2CKrAUktyx9o1+GFnrL0IFc6h3vcclo1gMPsFNIs56CbIFQtRggPVMP/x1w7rK+FUhvxfcdiFMRe
J5sNOLya71STlFJo0sFwwW20QXvGBKwYG+lM0ZGaBzyRBLqkJeQnsOtrsB4aHaVoaOCru0gBIAMj
tkzpQ06N68qMRFYBJvL1aG9rs0VA/sgt7SXEKbzraHey5P1n3lzmoje10T/GwTj+8Ryg59JyB4qJ
8EwPfpcc3AmZSg8jlSw7QgmQbHPvKawKrQi93bDm/wAgiERIGGDf6HT8KFbk9yYYIKIK8cmDuQSQ
OX4fakuwWqM5/BlPcCaSye22DCuirQpx2CeqnQYvzjz0vJBacwNqHxSwA10iMFVKWRSyZUav4ZUI
Nd6sfT9IQB9fVVI/qSmyj1PhF6Q+A/Y+Tx+bQhf6YgDYhXuEdmnPviyEi3ZlyUwJ8rckJ8QtObpj
iH35Nr86ubwspH19P8e468/5040jEscBLY7Dho+fapvfBlTojWx6/VbwbCsy66XLGVLFSGzYOMsh
afKWD+JJM61GJ9hLGJ9u4jpF6BcrG0jmctN6RjZflRFY813XNZY5HkyFryeDimMnWdI4S5kOFgNa
xi6HxPHvJwKIaCKKGum3G6J1CE4DlQe3ZbtsZUsexpeW3pfSmMOeqFfUZ4Wp4ZxvrEWm20Yrbj6o
COfGi72jQLxnV1dJZQkUKBH8N1K9jCFSZ64TzRO8jRM5pxIdF0I64IruucMq4kwfo2c9b0vrwtml
EccQUlJDmRecodKnkuCL0fCQ+V9Or1bNjkSxzuTn7xyg3SRYUC1aG3hjlKh9/Z47SP5iX2gqKwdQ
8H5wjLrrJpOMmAFjHaae5+F0DQe1VfsXDdCy3BAPTPvnzgKB6wP/g2ySQqAYSbI4ZyHU2McxQydf
IBjaecNH83tnY3nmrdGMSI+fMjIedgSDYYHbAMJB6tmCvp7qkykPGIie62OZt84Z+uNFTLdLz1qu
phZe85Yh0AJ9lOJGC0jL4qyBZaCQpzklyJsIZNKanaXIWDF4nClpKSE1dTGQv/h94PP0SNFex8Gr
JGu3jEVKzxPe/OCRS4hYBHKb6c1kyeQ0u/67fIQwct1mddNHOYBJbwHZOMTzCf9bQNXm9fKqHDTD
4KIaxIFC/Q6Urxe/4eb38OOrG71OmMmUf5ENnneUH4zyKrpHJKxTaGZr3CS1+DaXPn8p9PWXUFri
ODRYN2VqwjRy4CnLbmScZs3tzzhYgj0ULDV48gnFCwewLeGC5pbB18jBVB+1lhVZg4IHrElQqKT+
Kdl8cRoC66HFhuxeuLj7cCWlRQc9Qm26p64b5MLaPP1v8wJLWCeNRV9rPu3b2NVG3bJbIpYwOv+X
iI5nG56J3tM5mOeszSKZ98GQjUz7NANg0V3oTNohAobwgHG6HaQTz05sgKhkVV/txpVGHclTqhKi
Ijs4qxO795o120KDEsBEwPY2Wk2xFTpDxVuSW8sblw2D/mFRsDZqafQrNRKrrNTPVaH0rLzItgFb
Jj+Rl3kOPj/fCOzL79NhrHPKHJyanipol8twRbLl62gFUFv5IZSr53lOAMLgtMjyftTfZEpUAqvq
PMJB/6TVkrXxIKbtqy892B/bZzFCzWfjbzYYsjqzFvAomwdQ8m6iYuwdI6izyJOLB7MX3OwttM2M
BR4brdut1/hrq93Wt1UPJ6LMod8k35VHTbEOmR32f9sb7utRQqa2x3B6EtcEOW4BABIpUq/Efbe4
tbKYmPUL3bwW9tGQjHQKJo1JQxunZ/43UnfzFU1gWlfVlnjXCl0Fxs5eQvxAycabNl8TS7sKiow3
oh87CDqNnQOUtBMjEjGNsv/diT3Lu6qgU4N4eHd0Tneo8fyJizhHhNFre4l6zCN8GYdGmJhgeYze
fxOWjQXTdPXa3esjOgePjevo7xBK5JrmeBpmQoUmxTMOLUa1dBMvRQQ0hbKWErZ7jM8jLUXcu++a
GkfE70BjO/uQ7KynqeI1wVCE3PhVP4nnKuK3IsCL+ZJF6NMzNbqBDto3SlfKcfGcCm0CEyJt8jX6
3N62jdBIzkEE+eidjTLRjAG67+LvqcHXuAWfRevOKxaAdMYpOtvU8e4eiQ8oc2D7NMk6ko+4W7K7
netRGPdHxu5zXp+/Y2mShwijmalsRuvaJ9o07AGtYzCk8E6SYTMtirGSmQrkIY+sewu7Ui/5rbbH
dB7TASw40QEdAVy4XrzsTW+XVX0OCf3qXRxh7A7G79xLHKzUAw3WUWyhnku/tJVYJvI8VxcnLOyR
xufhPq73z6NxQeYcw//7cX57gapbHjeQEhd16E6BQEtK2UWUOpkl2KR7VtsUeSgxW6GWMt9rSxVF
joLa62To4LUPElUaL/ynml2ybfors1S34lNdqbW81KJh+HwEjNRcjQ7e33mLz5xrPisXXPTaEGsj
XY5nqET3avhj23SpWNP2fAOGd3A38owjcAGK+2lR/y2HZeUGgWR/yKTxSZ5CXYQkgP+2EOFUuwAM
LGCg/VjvUMYeRpZeXbjKV+85zTRK7z2KBQwVsfOmCqLzgiCf+EBDKyDfUOLpyau1GkdpKxd06ZYv
mAnXq3knQkUiKhmMSbg8ICUQ0g4/0pORuUU4s4D/aWe+U/fliWYhFp4we3G8qiGXCDJZa0U1fgr8
C4B09Hec5yKxFkdqU+3+VsmhwtTIofrEwun8C2qWTwHl7STBLRR6LvawzAqVGCh923HelsKBtfxY
U7ZjCDTdYVgVp95dV9tCd7Q8aBNEK2KyBegDGzcGDzjguvjRTOa3bHaALfRjtHxOajjxLT3/9G5n
vElTjI/hBPpz4v/MRYxKWL6yChRwVnMMx8lhjAFiMtOn2PmkUtHtt+SzitsZJR3PcE8pOYyw+G3E
WGI0J23BxFlakewNjTdQ/lH00fSnVbwZTVR+SvzT2J9x8rDowh8Phm8Pxri71+2nfLG9cMJ4WAFI
xyjI4e23a53RKiFShZ/oPSiKByW3bclOUGTbBJPR910AlXZC95zrsxTJq7XH5IzEYY8hsM2ie6C2
ObbK+dV+fY7azVzzTc0kAtxVKPYOrZ3tTGEeW+iJlF0hS3ImbvthKc8fPaHj+uZ06RQwPeUUlFNu
XJpKLiRvgnVQrGaqCTyA9umDKXJF1Fus+owmNJc4ItOWBNpdvIc2RktEOjL7cikUEIONezntI64+
MOSwFAfQDt5LMXBkYIeO9PfQ0fa3rGwbsNyFF5yrvRjDuh8aJVhHDZGZQcHMgLxK0OpAVMb4EFMG
uol6nIb3gGIn1ndimBNAUtuHICB6HAiktTz0wNeariamdQccZjzmH39GNT9PfQjQHK/Wc/WghDB5
KxPbFgFbhZZDKs+tPLm2nvqCekWTYbz8Wo2qYLQCg6ml8/JxP4Qx0WYiFsnApUlB6VufXsikhdQJ
oxmstG2yFItuzqq6lPa84liVhAJZUAAylqu0XLRrhI6q5+SAWIj2VpzzrjmVJ2GNu9E+z5Eqov3P
sh8O96B6jbVFLKLCUWt3TgFFYXvTfknmxvPpqSJoIH98fddOxTqBanuZGPYyvwnpMnry1mkoM5Pp
UHZ0F/sqdvB3XPOq2YgnyE+IF1KncLbLHaKT39eFeXV9c5xm8GGheSItWlg4yTiCLlzMaLRTnvYQ
l6exqZ+qjpTG9QTqP0VSR/Z3dnQ1XAyJa2Bc6ErpFHjU0r6E7oIsvi7FIBiHOFFSnVCSlYrDIgyi
dDePxHgECGM4tPOYSPhpFNwSxSLO/NxGU99wxj5Q8zNFohUyWDOtdUT8v7nrwYxwQgPEYTcnQJkj
tAyszcOcx0aUDdt9prpu8kUxc7EUhpaSr9rkt0lbPnM0bRiEJrVsuY+4W41jLh7HeakOe9aqlvAw
Z8QhkPhiH6wVEtAMwDT52mSTxxd7M3Uj9ZQGqlsupXY9Fnux8DXeIg1S+AIZGvNkpPnd2gcK+K06
Pm2vv9q1qPDl9d+YoBX2e2cQ+IVBL5ZQoIPK7oMKCtpYWrftgnPemLd8kxjPv9YItMMWQLJGRJBt
nNWdSJNUqQY9CbZPGK6txU49uNyVJ/4eoJbKUxeFyEleIykUshiVatlgrqaQi0xJPkelhJmoO+lQ
6p6X7dohyAYVIVJuQGHak8KePOZpAKP858Is6+KHK2SNyeBrmxLXPWlq/ObbjY3MjBb5C/PlFezL
MjI21vIVJY847tDXetIrTCDVCsal3XzTPo7d6ebUWnI0bY8mlHvlvdpkqo8Z753PrMwAyWVniGKt
5e2U5UBZtUItbKjNSaf9lWidpYSRdeYAd5IdC1IS8Z/G+BrQPNVmPH2wVvVlBkjgF0Z8Eng+tmS+
zM0xuXLqNIuLLeX8Edwv0w3kgxfDuQDscS8Uylh+d7AmcKaoXBbURCWHib2b0fcZM1xn5NYvODy2
yFUZtYl5jrZCj0yGkC026jUCkNzIieXBli8LiQjS7T/YHIWt8/QPAOuqj8oLmO9WLqhjuzqEdUMU
ZNIFshCCWd7yfoj+2a5F86qCkURevcJYbWeAp1OaMIsdSBMb2ceipWPOnXsulndlQtt5bk0/WczV
UytRGGiYUdxvV7sNb+9WNkpSdjzTr2594A74JUw+feU9fHXpBqIMhHqvzbYLFTUtsb187zaFr8Rv
IvPL7wH6d8U6MezjJfnEynsnFpfeNoE72kOgcbjoLuKikFJCGR/PrsPySAJVGCRgUV1A/gyJP805
EsJWJp8iFfC6+oKDZ5wuDExGBrJEeW6XwDJTdxDU+sbV6Rsr3t/beZvc2VGLTuAZ+1YdVOZ2r/f1
HWlC5vcRiNYoj4ap9IezfiAV/POgRjXxwCwLllma+bsMtgcR3R3xayXM+xJrWVsxUQ3WWkB8t8Nu
6K6ecbENcOPlsTaN+MwUae9je8Ilfr8sV3rZvNHLR3p1vWfjGK80gFG55iEQTrv7+pEMYj4LFWGH
TTogJ61y4IfnHspC84QWgH96WvC9tXFNi8ZVhSWiaNJfLiMY9ZlVNBvIisJT+G8iip8wKuWhHqUr
sKxDPVt2avPBgLsy19MWSAHWN7ItFZzaB6atwWG59t96c1VfeCwODe3XGvEH1nvnfKWTPfBEUXp5
o3+3NJkT5x3VwweU3GUuy41zaALCTUt8Vd+UgwMV1PrhHdKf1xtSoCAoalpU1VNosQqTDzrW15Gg
98rsMEwcE98hlo8a+U9/u6lJ9Uhiv5mdn2JH8mP62C5HjVN2XhA+hnLFLV6HG6vOPof2QP3Esqij
wyS/2GlD9Q6KkFpqkJvRYnWiXtCknVOHVDzPbR5SwcuONZfJYgxYNlfesEOCjXN593XC3jUzzKlj
2u8F2AV8r6RoiHaxSE3z/L0Vr6H5OvEFVRwoAxXv4Zz4rJnf//u4hVnV3KnWcgi6qROkEGhx8WKY
5Vu/pTkicol9o/seAVek6dI3Rbz88dG7NK8VcNQdt1syRhuEdP07mQmdixuHATjGyIxobLfp5Kpl
LDSQeZzSBQBNLaqVbDNvtVoaw5gVjHqMaFMIYGddhQRl7J6SGbHqL4mmTQL4/w2m0Squqb7+BHL4
NF6aV8JdofVv+cBBvT9wkukX/cB47XLFKNQT67SXPIhI8DVG0NWFdLv1wcz56vrZlk/nO5YKZI2+
TZRrkMNWBZu440xbHaOwDAo9uMqVqRhZziLMSKQR7ViBDm848QJ3L3FzwnCaq1EbxrJU6L7kTXuH
YWKtUJNSPCQoCL1n+rUl4T+wFrmoHvQNS5l2E+L1A8B0FTQ8SUouWeBkhfy/Fnf4fm18JPA98m7l
MiIwQgYkzP85fdcfJ4RBECC9tSQA3bMR8TZnR4vIf7p0cUn9nkfQ7k9HBo/Ju8FTvMjQBPwi6J48
wAZkDUp3J7sJIT3epkpYBNI60KYdPrMNKyfsd3gVhS1+p5FHzEwFocwzkoAYoWU45Iyh89cpLtUe
aFgc9Hkcw6BcRzJHS1NXDh5uLlBkzoc9yeXi2Z2RKPiPl6dCLqPqUwmq4izs02m7u4rfVDM53xzI
5JmBCJ2apnLgNbTPIWNjzCqDt1vfecQOQkiXngyH6GUv7zEpNJjKbw8u1McuQ2B96HkQtr5bq/SB
m29qq5eipjQrqfXgF1G3n0FH+LsiuGnhFCs7G/hI3Ag3r9byQ2OA18orXagXNHuPLRxbVnJRXSv3
Pwxt0AEYBBrePjDfCBRO0CnlW3weEBUCJUfSt4Ydj9QYanH/5f+hrkvb3Vo/YC5bpQx9bg8nB0Qd
Bhn7zcEwxOXX+7rcgnkAeZ2A5rERcgYo7EKksI5E1mBkzDiImKkkmYwqFyCCGd7m157Rs6SPQWvT
FrUU/9fyIMnMCBVE++scLQ1ZO+k0hYW4XYvcXPmcy8w5fX5mDOu3IJpHQVuWsNTSHS1buW44CUzh
H70bJ8v+kLYQLOa6+R5ym0CSvFLrFGTE7axYgCw7dMoxCoc9pkjcugfkWzCvDxuAgo58T+ypUovg
IOErTRINhNbHR+U2Kz+m4hbKgMLYwzd0XVjrTW0DziozMlIHbT/uq6RKgrxHSS9IUJfIn9CyLEni
M2GFqzrCNE4SQ+LlngWKy/ar5l+aG8forxep8Epl7hPmBh6spx7DF+Nf3XeG69OZ9mADDhFtKzCg
UfGRO4aNh4xCMno50Gblb21DwvsyUqKiZROthcIs4SAcpAhJJqDG9P/FzoxBaiYoKFDjfXJzFsBr
5HJtBUJfJ+AvSE9LnSUyRMdXJcnqdQN49jSjG1nsMpfgvplp505ReC31YpSot9o3VlFo3VWF4Cdt
8oRq5jlraW3tkT3YElMILDZmb9UMdTXlycK9W1INkfmzV66NtI/1kIWw3Z/v1f6oqeDL5Ga1AfUM
QCupdI/dUa+ULVqtONetr9Wz09uSvIXSxj2ofeTmeVri+iE4DLAsOds+ncRdGP1lOkYl/7YDzubm
aEQV2hTEdDIIQAQ1Rq0FKpNFQJIUGnQEYx71cN7MlO1CpfoujOYpj5cUVsFAfb+e4+Z0h6rXflhL
IQGPohBD448I1Vd7OozHNTbnyK3KgSmAl1byLuLXu7hdtIqBd0rnlrZ1vMbrGDWVeAQF9vYLqjku
v3EnPTpjI/Jb55aVrpFZE+Fx3Ju4SKp66HZGFaogHlYRBPowR4US5bt2D6AG0Lq+FIrS0yiJoDiB
i8JCTex4YYYAvq2cw/HGagADpk4HsxdpNduagkW+dsQZGYSEVQ20QXJ2xizZUOmQ+ojAKl1QuYvo
xBHluXlh0e4ETYhTapWaEzZw8tTgbzmpTsV3nZQH21El0KZ0AtSzB3VUcFdvZvy9yXNDLEjGFZey
cgpCYYyuYpQb01O+ugOE5DQ7/pRlbMu1L/d3P71jGI468BWuHVYvNqo5PcXI07mcOpeQ6pz7Q3U8
qzeomHMjt0+52RcTOIvJ5dNrUYeOiISucGJqHREb+Wl6MTQ/uGvW0+0M3eQlB2xWXGxUVjH5Jxb4
ap1O7esDq9oK0U9hjmKFvlQ484JBCNL3w9/CDnRIdq+4VCWrG1n/JT7y9Ba5ZB4LEDAPjYJEEuZi
dQZ4OMT2nnOSouLYz+lhR97C3tWelYwNYUzLjZ7QxJP6vSt9w6uTP2T0UpiPDxHn6crjMaAvY+ti
U6a9KY1aOLpqw4tMO88GKosc4nCDsz46XEDpPFhJywDONbi5cZLwrPoaPLciyaCwqVzYrbNMa9T/
kD+6SSn64hb+voPzk91oWZdyciwPOpOPq5HQUXdsvBiZWuRf3Fqjh2pPPZ7dQ+H5m33KyChqOy4u
UWRWGFCm25MbqxelGrCUw+tQulRDaL0T2pXh5gX91iu9dRH9pJpn6hbMon240UaXjsvTTM1iGc52
AkJIKmtw7AqN8Gz26N/A/9xDBSdXu1gsZCQWeTkYICcdT5MsSyKooeZ5fC/xZV9ECNIOrVftLe62
A2HT/NtvOS6jPwHkKP0h7nc5g1s1shnBM5nTZdLmfZBCWiyX0mWD7KWwl+sihqjemCyNoJKawE06
LDAop/LY/jemaQK7f2NoC8e9xHD2ubW/vpbsV8jckTkMKk7KftkwEu5xz4Ila39/jC1s3YI9iJWr
31RttYGNRd93FxifYjyeQ0mXXEi2nF+/dgKn0m2RnNGNDWbUIAZxK7cFQ+wPig4a6mQSCvGOtmkO
YTlML0D8wBZIGhgmDQdVq3k89HkxhuBu/eqih17+AMsvsYZLfa29hTpML5tm6xuEJ+dYn5gEZBTZ
KL/YZeErbveEUA7swM2y/mjRRf6clScgL+yDZaYwCPbUxEElvrl8kqhGONI52MA5wV1UW4KnISuh
vtQe+DZHM0iA+wPArAflXOmtcpvPdNPI09k2U5YfobXc504651V9OW52KEVBPj03Gr7Qi3AesiMK
3mgjOOL2doD6Uu6m4X2fQoNsVnqZdwoY/ZN52ZXG0VbFHD9MnY7DkRm8ji2w7F6muyX7y8lyVWUM
U0JZqs+ACJqk8H74u37lH6LSDWDErticXgsXnr3mTS6nKeo5ob4on2T4N+sKY8SopKcPcrM2O0iX
K8o5EtHeRVFuiIRDjv0+IYcex8yMEJKZT67Tt74e/E5HbCOBRL/G5XiTBNxbLKN2Z4Ee+0Er3ED1
BFKeS8WnFMjKby8qTo26n7JOhbxE6AK+pU+uFn+oks6RYEcLxYR2YiMlgtu9nAT1uNeOL9wBqbSC
LjM35vVbw0Ljw3kq2DfCjvqZZfgNkAFqB1Ny/0Q9jJ/6UiqfPl3lsZh17X4V/tBIfH3WL7ioQRn8
bq1HpZz/b4JQvpfxiVtpEUwFp56+YGpGq3CrdLl3RWykMH1N4yT94g6mkothT5kCJkzinue2sxj0
XzWFf3hUTRi/4Gwi2SZUvcde8+EFOOGCvlZUIilpuqnr60j21ZKUNML6voDKJqPhm3+FgCWVxppK
9ET1o35Fk+JDS+CYhlZCEr5XtJLfwyQkkZ7KJ9Q7u7RsTzTEcOsVzVZydl/qM7e4Zsj8/9FKZVnI
Al/cgex6ExT1lyure0YkXWbRwBVDi7+JDnN0hvSP8kncTI/XTwGSBzjlUjESZiP1I8Uy3TjTtJTB
5sGfke1WPegTOzz5AMoJbL0U6Zj0HsvcRw7l9LrJKcGZhJLQ+1De8HP/Z7TUx6jHMAUoFrpT9vAt
pDo4aovjkF7vCWsUKCmeUFDE64CjD+3gDbf2/b+KsinnXYY2HsW7xSk/5ewXi6SEShujzrpDgqX+
fNv1YOz/wtgteOvtAOjU8nak6snptQ2dBU/yy6/PM0TtZj2giDUNTqgHH8J10nBy65oXZYDpGnuB
qlo642NqecU+3x0vyedQqJxDxGGr0B1BySGIqWP6F0Uxkj62fuUwhnKwXfU4ziM2BKtJQ4hgi7lP
9Fm2ERdz5YZzxYJCwvOOBHBp9GU7xo7QoqndVhg6H+L4B67AopJUvmCEvVXJbS9jFSD2Jn2VY9l5
GTgQlJs4VFlK2JLbCBbRuasxP4sTEtNDD3vsSwBRZYcdFF7y5ZW9/I2oPzArizvXkxPESmh/UaOU
bNVGBdbbEkUr58EQ3xsuqoGsc6PMYy4y+7XOIUno8aTAWuV8Swhh1u4XMHRSpndmn2YtsQbIRY+Y
pf4vgfA7KhCwSqhVFYSnqMO72OjehsJLmqR6Zau+k0quk23pqMOvY+u4kcfurmXI+qzHYlaRWHDc
2Z1jHUdFxDP3Bn5J78YCiig0q6z+8Zwl5GyGoy1ljEzDh8z1CUSPjSbToOgOVCdbOBH0psswdydZ
1hjQYEBvfXZlJoB62AMRZ8ry9vR4fwPwZxg+bzjbVeF6QLTZNXEfnhUAPm2OmTUWmq0ZNbNsXrem
0y0YCJGgyjZ86L1VjgDGfICDng16KqtxAprGj6CAZjjpWBXkvlU2x3DT1wD9i6uv21QN1IDkDizT
cVROFt00yw3n18F+keNLGc1rxgv6urbAxToIQuFRNPnMQf2EeH94j8r6aFV0unvQbwZaRPNaufOP
qsbLhEMRrHl5sMfDhMwV78IprCJCFWtX6vMmT6kLGyLr3cYxoJB5nWLPCA84HWMDaBNaEAYzZG+M
4dnG+e+OKQP0r1UGnEmyyj7csrschd9jDYSjQ+H0XWHGmHicELxo2K6rEDMlS/dmiUvrSzSG0g3m
jx0SZyYuEP/LX+Yf3QyKh4XoWr4vDYJk9DTJ9UCpPGhWwaDVChI44ZnJ9sM9yuwmpzaYzIxEyATi
Li/5ZE8UcFgXIUJ0Rg7Tsz8zTz+sjFAe6wsyrVm+LMZhHpdLVRp2/gYPRmra6gtcc5t12r87RvBs
cMNMxB5nC6D73j/2+TjwuaYA08lwcu34uvez99/MJua+17G4/+TGy8ZZSfdfxvrJI2OwcRRNGTJK
Twfg/TvU6Bba1XA3XMPNu1+qPmX/EXKAwTFW6dzQ5qTfhZDoPXPpAg3hbPJJHqvsqtXpbIK950oH
42qpntBntLE+HfSlqTgQ1I1UZm5WMe8naUOLBskooj9PplRWTAJOnnu+MFSM3684YJbb99BBzVuJ
Nb68x582xg+xt8aM2ce+cKc7rVBQn4zrcC5Qpq3ymd0iSyO+fsEicfeseRNWzhzHkI33ff9ZxC/k
cphrme/X5agy5aIAx5NkpF9sgTs6AHEcrpPx8yIhX18fpYc8JTbvDeZkCtwJurbfpoQ+AtMShL/e
1+qq3gbxw1aeVN5SN05i5GzATogk2PDMrHFbTcwZvUnTkHEne/X+Dcz3AVINmb+fqXx3V+nGbq0G
+r4FjqARA+ewCJ7ZpDkKUQzzXxhYcQSdS3GHJoxPAfgqo2kFuwhLXY5gTa7IQK61b9jJR3l/BPal
U9G7NnIGMeRgskBAGoUqhiy6zQsCb7e7wzs8az+FVph1U9/JKDPn82e7SjsM+2GG3Q80rpe/ysCQ
cm1bEG8H0N6sXJJzU/Yh5xZnslAehllIe5rzLVjPk4TxqZUeD7S9GzoJhbjrtZsNwfxBuXgUoES6
WoBxTPrs2GQ3zfczYneXKxk05zDBtAKro+h72cLWIpVl9PxDSslqkXt1oVKg4yOk8X07CqJy9tOD
RYelPWDd16lgMICyH1HJXubO/JVBdQT5zpiLiDpf1/veV6gUbwwVtV5hdcAh86eu4iRmhbldoKdj
iNWQqqobjcmVBO9w4TOI/l2Tx2Ggu2asyIDTLGuAUoLA953riXTNMU4yUDL3kXHWLkfKsQ/vr75g
SwKKEoXgyHbZvY0YfIRpup+ssGW7YfS66kmzrrSCHeoEv0Xh+jlc0JpOa4kFbkeYsPFHxqUrxZFW
WPbB9bGWeTc/Dj+7/BXHCRvr6k3WHfl59bWBx1Ks6pUk0Hh+cEHmjWvIwQQF1UBabxrz59lUMsO+
2ga8SRZBYtNWXdnIxkbcixrpZNiKnhVB9SLsEUG9jQXngjMDCDUBvqa9TTISi6t7a4KGgX8uNfcH
SljhJD6DQ1edAJ5VEqGYxZ4pIWrTts+ZnnTc2a8TBmgHg2JTGWMMs8PthyRjSVoJNx5g3QOyOJ8n
9xc0OJoEjnWmQuGkMMAN9qJcns+Ei2OQ7u+81Tzkqblafd3hVj3rPf+5J/be0Fj0jTIHFYk/bHcs
NfH/mK9bLwm4E2B++MHLx1D3CIelRnMaKpMuJGs9agErLMHKCSrBCm3cEVYRonKgFGu/huoMWqSL
AAVbVOyf4Xxz9mlFGoIhS171xDJBU/IoJUd+2ZEAuT8y1n4IzBXJgNPOgYAAc5G47Dvv9zS6W6dn
i7ulg+07ul03pVPfaH4uDD3L2B3pL93/IR2FGNymmMKLqN8Do2GIxzGIUgHVw1x/FVZiFwgLIsff
OKws1OOZLTJsezFcUBeQoW9wNDWmOM2anw86L/vN84QVD4qTUTNW3DdTLO+jI66BHu7ozuN9Srki
8YZkkjjAjwbqBsOBIpT/CVFizwHJCIY4lRWf1iGNf7VbSz80Byldr+SeVdqabWQ4M0od5qmtTqzU
/+4OieJpV/Pj11IBMH3hm3/XUH24kezvILLbjA8AzJf7E/fvZ2amhz54Fc07Gd8t2EAjz6veBnY0
WVvnz9HfwfS0olcCgcCLFHMkQdblOYDT5aF1VivxPL7hxkf0uK/RGEQYaiN3DaA+eoFKj0bxWHHe
rGCRnQMG4V68PmB6fLf4d75Lmax4G6PYTP8vNnzuzKwiEtd69u6+noErvtdAIlymsGd/4LTpQJAf
wHJe4dbJTmqibd+qKq8q7y0iXExu2DxnN6YZiKvfitM0jnmSitleNhwM7ff+NPrhVZ14TZvvofKZ
yPOgsnD1ZT0TJmnmbElhyQGr268C9WWUWQVBcK+bfNnAeBteJB6Ihsv4qhoPviauPVMcPml/hJKG
TK40+WuQyoTZdkdiwURMVlWLMbLkywJ2BQm70a7sRt+iI4mOA6DRgIevJ9rh2VJyVSC4+8vhljmE
Gupi8r5iyvLnRAzr3j2kYbwWgtbV5euIp3bTTJuY35sXnd8dhvFSUQ6eyqRONrhbCB28Swv7qrmg
iFQJHqG+r+9w+4tz+B9tW6bPZJb8se+LVDASnTSdeK9Ezj8kY2Nuv359bn4/qcMMXnvN6SwsYCCa
qBmUiURerqnZArCRUfmWxv6akiWKFB/xAkLksjURsVV8H2GnIuKTr87R1Y6n1iBSoErVZIz7jXhm
o1xhgjfnoMqgNpvEYe06P0b1y8f6+glY/SF7LSIOYM3cjq2hGIwZdZPI9LIrGqhwfboWNjcSppGE
uN7TEgbzO6lmxHcuZK+MavRZb2p2QM/XgHavZXIuft5fqdTDAUqHuPU8hi3h6GoIXVl3NnvZ4QqL
RGlirpKbKPWvL2EbKXgIS7aXMw3/4BsXl5gu5okYkyBSnAacafvS6XFw4qj2LiEfdRqPBK+cS9r6
eK3cZ1iaxzse/l96D33io6bQgMAI7YqMhcCgtumjTgnk4DbR6YBZYupLBYqnvJKtBnsRI17eIJ15
2uhi4gfbmCW7kKlWkaTxugM7aBVFQT7dIW2s7lISdE2LPTVIuIrDWeGcN79oBEgOnY6HS92Znr8P
WeIGmA+Ggqns4HbRVjwja+oytzjUwuDS/kKP/eWfxcauh/hpduBKSq6s5qpRTyTjsdRAYVyBIQnZ
kN+1JMsEXD1EGoebh5M+B/ZdSV41ux18AEp9Ijz58RwxiVFNKfK5FcuWz/l75FT7WzLK6Itw9NL1
xMwDFNmVFWA/YDqN8v5TKXWQgIACs7BRQDZ/3ZOdAc8SIbLtXNRyewh0+JkyOQYk6V2Lm5BYmOTS
06PIppf4rNLILeDXPJ2zCCUtkwGb3bS1p8PEVV+VwGVuyySJaBheWMcb21vDWXTcnZ36iD8326V8
6aH6ww2bujW3GavSe1rOq6ok7ksUhP3NUceC3TLhqVgqwdo0TwP/yILLnoH6+AyXT6NVGbVcdN0G
setlCeyhq0+l7O2UinOsxDQiztiWT0rF+FGIGI7PWVF1rYWcsWJ6vcH9ksEaTK+oimMVayuwSfZQ
5kaoDmfglXW4w+qJQ5oK6EhMqVhkTJ7Oq6MIRP/0CfGozdX9gLLLJaLFuKppxAx5pF9aW6lorz6w
gpgdc9tGJ2/lmM4iTY1d1ctIjb1mc1rRBGuE9utQc6NCf0SqPM6rSEFZGrNUhmIapwR2i9+1e7qQ
sEgoz6oyTkNqHOkXFq5ehuoigoqr5fW998Ek0eS3nRzIpdzA7b0saQiwX/ykJ688FTBqG0aYsuxw
E2Mv6Uzk+GW79oTiNpiLgR3tK5JyBcNvaeo97U3kchKSgTJZAj1Xd97mojP7wFgYLNkvIDlDaXF8
T7EHpa9NR8ByUT/xtLUfnOBwagLPVHfZnIsSBvtijPuTSJLgSa5zHUZ8Q93oQeIsBhQWaSv3h5Rg
W6zbSknbNRBsISw9uqwUaknh7oYt8V8dC7Ln+p41nQZnjEfCGPLEh0TVRXYL1gb41TfsCIz5dQjC
35S6rbxcGSz09eP1wISK/ZC+2yCu1qMUNioL/5KhhO5jkumZFrkVp8cMxaPMDjKyBqJGIwzOLv9k
CVp2nZoxVtGV3/UyBXyjfr/nPV9bgn2p5XGyyp67/JUa0Dg4XXTMVcAeVNo/3XHrRk6xQUnwv7+c
Xh63ww4DTZwiHrnp3iZWHaGt5aFDBmfa7UuDRjK5b2SYYrvBYI2AEdj2kkiv1RmPVo2UN4MOnwq8
8Xw23fwlpdaFmIF9WGY123yneFQ0vV30TzgMHvguCYPxz9ebRX167uCGux2XctZtffq0kMEbQ3Nw
K5rejE7uqgLI0RZpzQUO5mWWGVKPnYQJHE7oAw+7LIUE6n7FlFQdlyZwD1JgrVWyj3DMDmfCMaGe
AzjqkYCz5X8VIE6C8Iup7FFooza2a311+jhIwnxgy2uZ5sMpiNgBUMtK4aD+J6gUm5REBw5Qz5On
G8iR0dN7UBdb4RPlbhCRbuUiN4jiDLS8W8aZh3wAeNrQPZj9Kr4z1vL8piBeUTt+28MI27Xft9Op
5apcl6AmB4xTM18RK67Wfku5T2zLJPcywawa1V71c57Q/ld4cU5ZLKkM45iVFzJPtrHLEyU2YulL
Sjear+PE3A2o2sgLUwTlzjb96QsbcZzaeGU+/vqI6S1w3YFE8cFrKK2PCexlpqCQCTzrWJb6knJC
N3RSdWUd4lwCPKlB2oJvg7Poo5GZH3bV0FWYDhp0YFcw1STrD9SbpzY64omiDVJdUa4gmEkkUE7E
ZamHvjwgEAgWbSr60/OJDO/ySTy5/tbgaInw8VOGzqeMzGzdkj2oWlW9nWh1+b86SkfcVIxh4vh1
umJZtI6ygFJXcytR81ku+3vg4Vb88yIhi2N+JH47OA6g98iXqLRTXoK5sUAI8Ltb1vXujHpvmuFB
en71JJdcusxU23hkAr4F7z/1ma0rzqKUvqGQ0JwJ5puAuY/biB5MfvRmSGIUtLAie35V8M+SlUZd
u1DToQeVmtSHYORy8KAm3+bqDv4UogOqvjxiKVO8rKxSKkUYfuAmvhOppWTj0u8sh5M7Pgbg0haa
OTfXf6VAUl/TJsFZ87+h6FtDqlSa4nHL3Y9Jb7znbPqvVihgoLu40Bwv3qe8FzkoIbDc89emLOiR
C9R2MI0qPPIOhS5mlXwzT2kIvBD9nDJsv2DommwhzOxrpV/u9Dw98Mb9qpMXX/b7Zw4bSqM8lvvG
rGpKaC2WMMGsbiEwroSQJyzC3ACMqssBiH88d8ZF//zHQvD1fq7ZqtQTmqF2G2V8X1Ql8lMTk4r0
W0TaPqzO2o3MVkr5LvReRKuCa0atrg1WVswLt+UqcUpslacTENXHt4Fn/8Fl1qqVHFvanHJtcSWj
54TcMGURRNldwY7AQykYyd9oNrMYOwb3OtqFZ4y1Q4Qp1rSIdUIIitdGUXkgHwGfKn4xqFWX1g+X
fLxB7u4tvJmxS7UGLfvGui9uI2/ai6n+2VVUO5+72RNennK8ltqZyf+4mEux3fexMoEpwWRIN6zy
ufXtJPlXL7/sWtbLumhOYJMwjClaVjIOSFhsYovJGSq5/5Hz0TBCqhoULdZRFz3JYrtWHVbQ/7CK
qBqXgSREDgO0d2GlYX+1GeOY1lFskSdJ1yGF04Oyyrd5BRJhUOh4trjNCCgqULS6A++AUIY48ii7
q9eD/UT8APSlcjM8jx2atRBhvPu5Oc/rJ4xpaOh4YbdhC6TNSn/k2xO5uqpf+K6nLSA5xT14YCBB
+NE1/G63J9y3sZsaqVT2pNBh4+ZTBdWs4vLEqY+ElZFZ49YHk8H6ZSPmDE2DwPzcDt9QQc7koMrN
pQ3YhDgBIhdOW415lTKnPs14bOTot89I/pzxc2lWKbqUpAPCKuN7HZJboCPRf/AC5FWi4iwL6qK+
JvO2q9YCnUzwBY1QRFyUdWMrHjtj/ILGtv+KRE9qwe+VMZReegApYFR5QtbIDbdWXn/I1uTHquYW
v80cOfRzA+taLPMZYInNpt3OZL7LeUTOBt7HDv+Kvmc1sTBPMXkPslxqxcO8ec3/rcnYSNj/JIxF
wIye3+jdXkOru+j8W9pIKeriayinp4XaOWnyfT3keVCYb597SUKcmiFUI4ldlQPxqOq1tnSR5IYW
78RdzRoiclE0w6URAtw16NXSY+Rb3C5HPCH9NQ6dh39uBPtFXmI7Qe4mAUCLPJQ+1rhutjxTHhQl
qBPYI1V7slLRn8lUWSjnCZEAKiAHw/98c1MVfaVv3qtW+9tqf6SvwJxJkK6CsqO2hjKMaSRVS5DN
zEi8KHzsxveAKOoVK09ywgakzPNg7PTxpcZAbpCb/du+Q9EMe9y5vTRMX5LpmAgfKz6qXcOio8rf
139wxbGmCQItRPyEunoJA2tmJs4sHQPwHeIDbOCKJwg7xoBPvN6LPAe7PCis6B/EqmjAMeYZsRto
/6izu2/4oja3tyHTn9CYR8OQGN29Kwm4/2wuzAqoktO1eLjU4RDrBYKJvH2psbek5Kb9GUQn1BJA
N37ZQuCeiaQJPriyQvwBw+NGG5/wWjYVE39jqmqTBMpqIYS+BKZpWLwSGbgNj0ETIdRf1GZDPgZi
X6e+mWNI/WzyivOFF9IS7vhU9kMsBAegnIA4yJax1b3hBeXRWmx0w84KyONtq2y1yO/us1spUHrV
Ba1Vine9CZTOfPU06xN0MuXYSDX+SU/QmYiZxeW6qY/9gwRyF7r0dQaOAVsUWEuRjN9/IW+WRrNA
grWeEN22z2TTpJ7OU2uFC2yeq4uTtrcqJI+2FvoN2TTR9fG+2OhUhAHmp5x7IeqwQZpKLd5T8bQm
w+aY0KV4KO4wu5188C2aYbycy2tnNlmNPMmWHaPSud0V+4XAyM6cxVCEeyYnzmKmhvLViE3//aOE
nqZH9Id35c1Fzn9ZQeuIA5FWe/h64Ol810IhaTqIbWgeJW7gRWvtx/z9PzeVgJYG4FJ75en/WXo0
GkXcb9DrQgSZJAWMp87sFLPVKGaD/IgiPtKKUfQq5pKb1FmHqh8vhB1Tn2uvS9QxZ8E9xUvCUPNu
m60L364mW9Np0OIqtsPCWY1nPLSR47j0OfrgmluwHtuHpyLe5+jN7Z+bktaF3X+Dvbjm2nIYRWbG
ERZ7ABLaxCFb7IvraJarUjfOIekXCb+t/wQjNFwP+iS8037TFCLhyxmFRQXd1FFD1kXe102pfzVO
+nPQvSlDsmTl4sFEupwAWDYwbO9OqIbnTB+G4XoWNwb0q0UG7dP5WcnblrjXwuPFCj/TuwXQWvbJ
S+EVeuDQTN/ReywPvVmQ8C+APAinofwsgqhGr6IYT+YTca351l7UIy57Sjm5t8K3YNaDEbbCJFTo
Cvzt6M8qpgSk+uK+OjtNDyw30pAHzEe4ERDr51uvQPbWJ/JU7ZQodnpmkPCPZFgbfumQaDCCzpki
wN/E5CXfkZEVijR/V0vAPW1KV3Uek4opeTYGaFVz5lqa1ncSGSYPYMQCnC55PwHD2DMtIU66IloL
Q5BgKFDzYdJPK1vajxFCBGbr2o5r0sg/J/fA8K588zJ+Sv3w8O+SHrYXEyWLATUe6JgrgmXJAiCF
SEMjN/2Tax81zF0M+C1K+nAI7Fl4u+YuVJb/e7luyIOukwBBXPBcsemsNTZagb24fjrXo5gCW0hO
71JTTNLzxZdKQcGxGU8zvkNTPh2qt8yNrbnZb7rwwsdBscEqx0P7RThTxvi/jRb66/GvlBzloxHH
/HS+JaRQwjSbc3fX/B4N+6eE1VNlwL+WUpxHU5GrhcxvE/fnYsnT/ZW1Tcbu87Y9fqHzSDVXLPo0
PTBjbwZsPBy6/OKjDdgM28JzsUASGx+4kXGJ8M5yS3GmIJu10/oLI+mnrGTen+2YPuMf2/XB05SD
oc+dAE1eY6SZXZFred++OHaPShOJpa95N+HQBGduiarKSoA2r5vu12fOA2x2vpvDvBeSSkxYYz17
RchObiSnd/elPF4Bd1D+NffS1ECN26GNQ/teRpRiCEygTKYsiwVMAd8z4OLBcH94bCMkmdseLhWF
H4SrZ54Ht8Y2yUGxlff/aCoRCGEiGqGtSpZGKdtvzq9xHiWCKcOnUiuYSgxVR58z0nkB/D40LjSG
zdR3gHQLBf67fQjHQzAcVjhJ9OJ2d/aBZ7JWF54BYXu43J3cY130xadvl26j1wA0rWLX+xG5P46t
SGHFNqPc3jYUe43vEFi+QL1dN1AwjiwwUvk+E6DAEhOW/dxGWi3ytNdOharY0+sbKebp4ir2qHyC
KAzR2SeDxGPLBIRft5wAE1R3zXJWK0PKxgFMrqtL12nATJ9BXv6w9/BqT53WR2X/u1j2lI+a3Bpm
wnIxeWg55wa2NW2GR9zT+4Qdw0aKWPsSF2bEyEgFTWXyeuNN+PFwUekrqa+JzR0E8ek5xdVIS/cF
50aW9vBvOTZ0pQT3au4Xj3mLx4b5E2wfAPaO9VD/MbcYjtPHPvEMlLLnvIiH0P8bUzK4gTr3hcw/
sCmN9NaNTkXxEXSkYl9fVaTQ5IDDHqM7z2a02wL8qr/dZsurpU2pHLqKnPF1WQSK5jByZddLlYSk
pT8iWinD497XigNTyhbAhrH8PWnKonCdFJar9zGA+QvSwbdnum435WYAiHrONmANvxVLw7YsTPyJ
HS+ISX88xtWOwQHRhvZ+5xRHlT1/TWsC743LmXLJcVa0LxXji8gWX3Esyjixq3+llENrGaaEd3at
LbGW1w29wMSCOyB9t3dDf0Q6SiDLIquQbTwucbq/G0ryOX68+NoD+1Ip4PkvObEVhtIGjc3KawQL
1jEZFFyFfe3e4ZMPn2L0k5tqDLHbmBvzPvnXe/RBTpwwgOxP478tB5TGsToPot1bGEbrF83oInP9
M+aVqKsRoMbVKGxH2BcUP2MeQv76GRCtBbWXEs3Rk16W40sM8vT5kKj3IOEkmmkHrq7lWt5VVZGh
NP7+4KwqTga0axoClBNA3dqBZA2M3dZnTQx+Lje02k8wzqv1nSThNwC9iBAVVxr27ZlwLWfnMcs8
mIZs2bHP2+ZUMcmXvC8v8js/g+EBaYlSnBQSJEw2obFkResz4zn9kTANIdLvjd4Q+K8UamSvNpjv
qU0uCFyTvoD/bgGhKGniNoAosq1/IB/JIQMFFNOHWOwHR2UbqrSwqT6DIU0B8lyyl/6kuElQiFq6
9fPhY8qeu0fnonpsZzqBSK1dmuigY1pgDtk9PKsl6VxntM6oB/hwl2xL4A20M0Eg7mTQPGSesw+B
DGcW9gORXVUro2EZLaLbh4XsGId2NGxWGO005w+wNdob26aqPqsUIZYFuNk6OSTVQzbzUOq60DwO
U8BXpgAArUWRMKKOtynm3TYIBsVhNztg2pjsGgOr1JaelqK5Ic1ZtHOik0l7W5g105qB3k2oxtJ8
7GN2vTAFNqxe9PxyUSUQ+3qlRiDqfzxIBl0RJbQk7EHhhAV9viDCGpKrEkiiPRjjuve6c7eROAVf
1zm77BfRQxxMZAex/5HUI0/BlNZlIzabrA/+e3/PLcmWj3g03mYM1Bwvg3bg9rWEbbYF/TD9FEks
KpHcCNT+O12uDCq1GfYjzx5ORZcj8c8NfNqTOR5EZgNaEiFFOeFBBKuid7AfVklaQFO+Oomzikzb
4v5HBIZ0F+7l7LBB+swkjk6LDegnY1195vNtjzHU/4TeL/cm7kGLco6XIwNYQFTEb/qBwQl76GH5
GH9ewd9q0QCw2Zs8WgCcn+P1+XRj3fTJPnJiPskrp5Ycn2SeT9s+ElnUw5VQlrsfWuNw5r2rl2oa
fH2iPUQR+mGBm9vxFajtf7WOkmwq739OvKmXPFGxf8tUkLRhaPXg2NkiaICthJ5V/OCKtsKw3kmP
FglNVI1BhKALeeD00tIL7xUA5fpVLN/RiizTgsI0Jqvcsm8L7+lUuLGlfgAMKrTVD3KDR15V37ot
uYZmlDGplTVTwgPCiJXNtU8w2vzyra5vj37Ku18xSa1kA8p8qugWqS94mfNXDiWLKCpdbkfY8iVk
5tCNBBHgCvpyjEexQlGGlUaLmDX24j/L1MRdCGXfhgzHYevw/cZJXVJ1W++F88GsSOahyhdmMPMh
XVn4kjgNkC6FglD+AKGUP+8c9Y7QGtLUyKgR5M1Nfs2dbP6bdt/Vu4gVEuJbTy67TN4iIox8eSTz
vVCE5gTfpsFmgu/8Sw8oBaR2fOYC9X9muHS+ETsMzTvx0qyYs4D5L/o5azlcBPiBjoVC97ti9tIh
4NfjPTY0a3TaXTKBQUhO3wSGoISqLxNoA7pkEtrKvJjSIjDeAKeNvjoLXFGR/AcO+2aH/gwe64Bv
09TJYxlSN38rByoJmDYD7pdiWRfz4Vb0ild80VagfQCYwoA+2gg5sj8vJY6d6Npj8HHSNhV/zr8F
hWdX0ADxgfkFb5jI+ZWYV7wmfUwZprQGZ5D/15bc1y7n9ySckEKp7FD3KqLmIDnjVxRdMUidglVg
KXX2K3+9Cq0sNAqLWtao6KUuBU2gNPjdKn5eDDEMbiqOC1jFR92tIWSDQmGjBd4lAl0Enz7zKNwM
5CoE6LD9zw64+RAuwFxlsvliwgZRINctXnnDl+/Ma2mtBISVQVzrArlSaBYPjjj/m0uPc7uWptX5
3B0iR8B8J6x58A7OEr9Abdm1w+KNkEGfOo1lK2xFnWGNk/DCsULLOLPsrfytsAb4lLKop+/kS1z0
kJjJO8tPcWRJO5bWjyhdnt3167rD11cMjBbx+sUje0SaRvb+7Jw9DxwZgVHWF2YGY1jWGqaP7KBw
skED5q3viX9mlrL5BUbP8qRXo6BeYRyxmNMfoT4Ti7y17wf2pvu4a/5ju+trLqXh5tz+kaJlO/EM
KiHNf6KAXdvRFP5V3kjBlY6KGHv5EAL0+Hq+WTo6uYAGY1Oz1r8iiyZl64P6XsVJNJzEGmsqRMO+
Y1o6lUTc3czoRzeBrVqolfL8dUFNIUAsik8MX9mNrmh51CYxiqyCXICYdugUKnZZBFhmVKZluat7
ja47U/5VcLSjpNh7yxpu9MGGLLtimLEwmeC4KMf+eTvXilTBfgOqh6m7xTyi9WmHEt/2ywcuUPGE
cKoBtv08kx7+cVGLD0+GYfOVfp1EmyYJl80hznOePIA8CwxSezzXkwgtJg/74ZsRalnF0U0Gikv1
v7gel6i1O9REJwwyMvOREqZXYxv1Jfp70O3lQhXm/Ie0UUMIkRlf3i+PBwL69JykZL6PkrOxdCzB
Y8Eb+AgL2cYhDR2WPC/lCQlGIfizJwXcYyyUBZKKrcmbX6X5FA2MIbkUHO6LER3j3a3w5TqriSAX
dgl7J+BNHLIXnKVRP6I9z1PXhm8I5hjijHsMIEUxkKF+18x/mDay/56d1mdaZojfQYvXYjXKPJR4
QBwtjRp7pJpbBE1K1+p5iFlPcrqG+etwK4EHYlA3+KBfH736VxcQbE4j7OQCvLPjpvPxkgkvZ+rZ
nVODZ2N4uvyzCiJ3Y/jJAs7A0Q4Lr3zPptAK52rBkipNz01tj8xOpQyf8SL3wPWn6kaMQD8QPCUN
aNxUGwcwFW17unANppNS/ECvlexcef3mk6orMa2cdiTa2LVYZvtAj8xgUQ8xPtru3G2yy61xVEXP
seyrVFwgNPH6WG6AjPFmX+L8Mc8q6u/GA14YQrfAaf0ovII5d9EA74cPOfnuCDvHggGS2M0ye+XR
ccOXWp20nqSqtJWLo+otuub38Jx1e20akAFtT1bBoi+WdENKLnBEM3uSPEJaYhu7NkAMKj/Jrkmy
igvcWOEmEiRNbQpXEFtlcNLaeWEGwNYu1XTED7cV+GB+3JYzh2VQk0bfcyHcaDF4s0DWjCKgdZfc
lgjTKw/81ESTPUjbTDwPKaupfQw3Kh2xo0Dgsdz+oitnWtGHhBlhvujRqgvabvj4H2Ucl8pElxFi
xU2inYx1NnOgWISSVUsbPQeoUbL++BQBarzvTEopXv/L6rqsIPQn9gPop3cvBKgJgh53Cud/Nl1E
tTQ9gqDOESykOg2rHrnqJ7dZbtWfGJeJ27fDv54uVfXIoaAPg0pi8hb2F0opRKUR+g/igj72WFqt
ue9sl2Gqc40N+dthAAuCfftolnA6bQOzGxBzZNCYrTYufFT0gpISkHHDqTnU8r8bQ9tdRTz4NZQ7
AOZLbWiVlxow9PZXrG9jDWN6wZwNVJz+eN43pgHfu35ahbdfe5Ds
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/blk_mem_gen_v8_1/blk_mem_gen_v8_1_synth.vhd | 27 | 68532 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
FAkw7gRmEwDx0cT0lLfFXgH94E+u7pXWs5ahSt/pzljIAtlVd5PhOu9ztNGUELVfoO4Gol+zPLUh
TN9yRctY4Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OsI56UKE4Z4O4++RpLw+Gr7y1Sd3eUkdDGmGZYBu0aWjoj+iDwzKGBcBG0rF5D+4LwCAgnpAGiys
xLyYTz/ObATK7L0zNe+Mx/H+/j5j5SXpNvpcXkGCWx3Mtg6EpqxneRyrD34svh6fn9QBg9AkFvdb
eTcam3dZU+Gacfm2Ivg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qc1VB803xD7sVBXVT5KuCy+daGAjeSNtMgViDKH2bpJoW4aexvjdVOFa9Cn3ZQUudsfzbRtbOfND
3qwRkfwGKGa/rWJp/b4u168LG7R497q3mKgxz4wZrw5VVWth06zATVCPkvVwwcP1aVCYV0wxe3+F
BcZo/LoE5dzRftELWM1hbxUlZMlSl/apI9c5DLD1ZPtssPXqyfH8yGBCJ6IwpqThHkCcKlxPWOFY
XBErOYYrcO+fou4DBovYWIgQB0ZKOhCR4cvN3q6rg5XOYT99xP70Y8jdZqXKRq3PuDDZEya4uwav
9zgp9xA7sRjUN5/fcIvFMcfDutvNPIc7IvkzWQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xeydwtnivo2IBZhciZFfy3r1qoKk43zuwlyfDAWr7E6QmSwqVQF5VHmc7oNu8/L6oqsi8CW2guof
n3LQZ6J8fPLN7CBNStOEImWoOU09vnECk8Bwe5gJEo2CSwnqojJJlM/jtH5jKtWnMb5YecjpsAkT
3bnS2U0oIgAvNLFItdk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QglgmN/aSMz0M17AlWb9oRKStkdBh5nVOwe4/WnjlbCHuTNXWcMIzqLlv5JcAmIdzL/13EAMS4W+
LbXaFXFMcWHAzC/5AZxX+CZbwE46qfB6uGUmUBTFEckk+Ba1aO38uKX6EDual9TqDkiz6OPrjmC5
MifvdDzh7mlaB+rYqb5sjxUWUfJCpXIOgO6lavL3535AS2e2hAYpmi1PB/ejGTuva2r1NRmDkiUk
Uq0oiyBI4sQwmU7gFF9pADJRyzpgRQuSICfI5NAGRTR3by64/5TeOArBdjuY9arezL4gMGXoOIu4
E5vrAQOLZikLF7X3/wpaihrUarYdJnuPPVXNaA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 48992)
`protect data_block
ALca4ZbZQm56On3bvuh5B0WS2btoLMeZbel4MsS/dwMbEqvPrwO6pq97L5wc4EmhtS/RA/5CtXS0
C/KdIWC7BkAWl92/ez+4/cbcWd+7u9DrpphsTFmNVafiHzkS633Xmj5EI1L5MokAFlz/7qoPK8XF
uCmJORXnRP9WqVtN5DAKcMyDjAXYfIHl2oV5D/6ENsCrGMoa9Fxl5JWlLXlVbtFdZXiNEzAO2YOs
WmhWGlxmSQcyPv31c+Xy4gkwYEF08+L2utwShGYQ5JXcipkSg6PO+U8yC52LDJazFtR+N1T5Vky/
eubJxwU6PMG2TD8v3hb1hJRn2YaZAXV1m9EibBWmTng7Ymbl3W491k2gI3wApODYTEc8/k/Knvf9
Vbp7ct6B/gjJt8UycvRJrm8l+AQILxR2gLj1w0lLMi7i9dKmp+oCsjTiNCjoE9cu92epiyx69/JU
HI2dNM7AUpjhU6KPrOnawbSUyR0MV+IPPbkVGBsPqb88VLAmG1gwh7YPx+5QePYYVl3gZmMWiJ4V
56sXjlNKYqfkB7eldyPywnd7jOY+QqR8I4OODMa4uHxACyozIiCg/7DDRYXhyCYWrRpHyDrpm8Vh
DmJRxUuMXwwYVvWNSuvAsCnCrFBdXg3ReeXO2yJw44+XgVhiIO8jRUDRlnWHAE2m1nrW+CimWYJv
Tf1b+Y3nDflswoTr82hf6JYK51yDq47R1LxQMh/5T+wIcfD7OUFYJ3zRoJ9JIsXaEBJ9KHkj9jsz
yYyo404FUOEziELp68UywAY6lDyPx6sPfgyk04upxwLP51cnLwy2QcQxKZOPT6v6ZBPDSeRbptHu
/DZ5iBy6VShj+ylN8vcURYRbjMtnH56etbifolU7n0y1dTa4C5uMdFfwWnwyhOxyaCPmYXwnq04B
cY6b1Dl2htu794iGSBo41Yw12LZSYbr+miyQUeLrQK/sVL4pxuOOZ2EDRwZFjda+Jv3Zd/zUmatx
+xAsvG9GAv3F9yqhalThADdHufEq6C+Cw+T0af/e9LszcL/b7VofxbldRy0w5V+rhSBSkTnF3I1a
ARZki3RFkt3gFCUrgzcrcb6w+/F3XnwlsN4dgrysKTtzxbFuw+dz+HKcFt3uIoguwhusiNG34VL4
vAKHJmqHA0/Vx/+7dCEQMG87aWAa70MHd1OI9md6aOFUIqe19CrUmXyhk3M4XXf/kb9Q/MF35p1C
H4i6/XObXaAdPiaJMK24+b6LKeVbapy0cRRZeGMwPMvJCGC21Mde2JPBge9FUSfCpIkL/2JjDksD
LWpzTtoLnS5fpPTjKE13OAYPIoYaS8nYmtgIw7/Nxs4FsbacqgO/2iJdXuyNugIOxpomJ6boBAo9
sYqUyiDmdymApOS1auimjrWUhcDMsWUxv1/pmmF1LrT6BN4LnyLVoTT5kpwNxY+kelNGVXSBCx5v
19eT/6TQ/te2rfhTECMhuvDd9NCpzGAjZBHB7XkRC+rvVwba+y13f8wNQAPS+Y0ypM01Tellvt5p
P7lMKTqNZFELLUeF06fXmM2vMbumbbSTtnT/IBXCW7sbOxVqoUrSCtZ2CNNtWso/RnFvf1yVFo2g
UUpykimRpicia3Wo9IoGyw9Ud63WYOiHTBG0i7aYzcUl7oNfnxtVWGa/RhJ1TGplus1NfNwpGDBk
amGmbFQaVHiLUxV8XY+fbedmbgZ9U+GEM6xeN9nRaC+j75F3LSOXyDCHN55plhIFjk5jt4ImCb2Y
/viODwcGF6jjsbEIGvlNw+BTGHQoFic51RlvqnBttmq5zs4gQywjc+Yh2PIhe1Amj5cwuVr3rJIC
s4VzAby+8LpLKMyubMqESnnEnPcGCTbmkwtjy4PhztEErC33rQ2ZxdszJ1AL8+JnHP5h1/9RfvCt
EJPpkq+2/RxUFSBhwrNcqTqnkH7VjKlj0neoLQpc7iRPJ9zllQh2fE/Em8rTUFBDbzZ2IvhE7M+h
E+yxGUNsUejNAhg0EpwwE9Ua13hDCjYFCcOxKjZzoEymXKUeCNpp4lNjQHssaO9CWPGbJ7XFqBP5
OKlnsMzaPLJ4FWgZf8RMp//3Wp1gb+tv7o3+vp3Lfk2w2AZqZRH+RvuN7sRnXlbkpWO/LFzgvyB3
FHkNHn5LtLipcr12t0/1LrpfP5F4reg6FA7orVoUL8ylaGZAj0eu0mwYwy14GmPjXqtUakr13uVg
fzO6a0KsNNr/TenRKJfFT0l62GSc8wX4QyuFaNQh3MLqHSBmehCFz7GfPMw98PGflSoA/FKXURr/
mjBhstDqfupUPTbboft4s7dETMmuEgUe2udSh3qk1+S1LOtcVLi4g1l4jl+vgvyZOKoZYXX8oa9v
+Qdl5PTLe+eQZvd/yUZXgrH2vUOV36F55ju/ma5+yRvqNgPzyv8ze9et9mxouEIyIs3pxt5bpl24
cl5lD00j+L/agM5azbf7Ph/XeHenADsv/RAiSjGUwTBlIBswOJ8k7eh99wpOe9iyV8fMnkd41RU3
H/AZyQ8PgRy5uSJvf3IPIaHd6Mk1boJirPuNuoG0a9eD815C2SlpTCXuov0sHD5XHw2z+5aXXnYN
lbt8NPrGICTSCf8R69P2JAVughLP6YAxj4j5ubQbaVHIf9pkaoaWItdWnbHj4+Zz7euXYCbMGo5Q
vzsO6rkD5QzV5yCVbf9Ovmop1cM06L8T9B5S1jqmyN/5gOtYAeokl/yHjjY/WCUSvyznCNvAGzsY
QRtJk9sJJaV0dE1f/VNj/CLlkJ98GfEu69uDtNATpVg1/u0BxE8LjSjysgimjPccsX2bin+kgcQT
Eu+PAa5OY4GyukBvZwYZ9+6BW//eDd3/r4Tln5R0g4erFQz8X2ZammT5MwCyERksLQ9po4bmn2ml
NecRqHubA/Hf8SlVLydbhqVcmi3Sjmgu36EaAi5N7NwgUbcJYo1EF1idYsyoGKyPmy2Zs1+Zv9be
HNQOFM/NNnUOWgGTyXAsUBjt3gBeSOYkc4PAjilG9fJzxrh+mNEskJ+7ItgWvwVo2HHrJa9ZL6xm
W6hEpiqtEBGtm17V5jdDZ70jMIZ+KIKk9vkrgdS9GzvXIwIJCVufMJ6dVAuHG6VQqhDw02kvuqae
hYbz+JNuDZWmE4lQNBwjdFzq9wkOFvgPKW9yUW3jZZ3NOaFYwaEemD63sTU1FQRt8GjUO63ZmOLt
BmMYZ298N3+O38N0LjFnSyCkKp/RLNjMn5zsKp549hA5eUcHWL64dimN5cu/h4kO1zCef9OaTRL8
zm0PCUpwQZ5QBKVhBIUEAgK9GwtU46Gi9fc22c4HpTya2owqZih59E6iln4Vo4gaOzwfU+a/lTEq
jZ7JWWCllgp221tXjPvXOcmCB2D+d5Pl9/KvAGlX5Rcfowtv3ilvj1lS+Mtjm0Zou8hpSBCHc+UV
rn9OChxDPft7fowtE86eu+LyfPQXQK41sUi2RKwfTIuqu1jLjVvoBFYK8exmDmWPmHp4HbKFLnnA
MjxExZ2QpfLnrQH/1rU3eFTCS1QZLdUTD6hg/HBlWcK1DR5nNro5E7r6FJ1rQdZ2QWH+YM87xYvr
qyBmdzTPqDZZtVR2Mlip0F3Vli6+KAjGVimC1qvBDR9Ckw8WqBdIeIxEa9Krm31PbNwYn3uKDhFS
WlDhlfi1IeJyHO8wOBN9wcSvRmOr+IfcWOF30q7GG4KzgkrYoXBX8sC4TnEsFTya+kV2htE8lgOy
7ZGYj7OPC/xqMp3ZAkXVlPoYIevJhhFfP1VXBYEUGaSnmznC+PbO0KcIKe6CoO6sbnz/NYgfaTaQ
jqUFSUAD6gx7YTO2/P9+soX3PvBFVhFv1fvz6gdYdt1yLb5m6HMadktuOoY7yFaghzPaCtbkkZKh
qgSlAXRbuqo4uYMmMBscddJDuGiv959DRr/w6Ge/BP/ctup7GV/JgmxbNBef9qL0U3CnVUeTDaoS
rUGRZSaPOiNl/fkNgFintu28HJDksqUcNI5rTBDg5Ri4EdUZdbAo0VXCTKzAwxZMxnUAR0E3yhqF
vuf1YlM9TR8edADnEh8UnrGKTaYem0GxrvPjoxwyFsFO1QsFaiZXJxqnmNCIQghbhzPkD1bWhz24
7oJNYn5AnQ/6VPBoCyfxYAlvLS4hW3rRPZzhDjxmdHOXhIUdusqTSdDbhTXrKbJLTgMKcPGFRS8f
JgeUioFs+lu4MvI8q5f2c4OSfY2yaQJDNxbXfQ223ypEIf69xYt5bRvjUflpxByBZ5dU7/1ky8E4
Qo36qtA+XeXGEpEEEr/dbfou+C+aYjBSAAkTgwIdhBeBXKowyftuJofN9eMYpZta0PvkHq7NAhxD
Kym0mV7kXrabt/EjGgApoIQjbucyFXpp6vVyTJNzgDCclfhBWSLKfEvejjYUn/ICjcKBbGIQm7dX
hFHwGTcXriRSYqaRE35oyGVMDYZ3F8sMwqPTTbnUROSqF9dtQ3qisGx142QAiF96AIGmAHITzLg0
KwUEmCXxiuVH1d06ApuO1JFytULrEQfJUdEsf2t0Ixo7XxYjJ4en+qCGaAAw7hOWC0rQI53ijrcs
rwvUFF2x41X6bP9m6zXOdI5WmhDebisFzDKZzVv/kMIANlvPQsTd8Pc2VkMDH8qknaQyxZstV5wU
pE2tsuMbU+CIAoBnfc4gw0zDkh5OyBwHKTtFEACCdzrWxZZ/eqRbXEeUfr/bSr2wj/PRA1YnDJpI
Y+Qrwda8TMur6e66cJzWj/oBzJRdq7YP2+X5/sPa/tN9c/yw5B3xFPSqCAWxMSTaFMC9VRK79fTZ
lvTF+YotY+PcBv21N3wqCEb6iWkf/YJcuU1KZc9QGCV8mM+40z1Ni7QPdnyoSPUuP66vD4Tn0tcF
2wBMauhQnsB2bElI9n6utOiBv7DPpzXyZgl0s0YB9+ZSfjvFHDRecO/Pjk7iLCS/kqf1TJn2ni25
jnvDpJVnX7l4eR3OwlWItGrPFMQ7R/pneuD9oa4K3lSSZs+Au24LfZDZQwgw2ew+x4SVLUp9l/s0
OOCqQY/577d2C8zjWLW4l4JFmAqdqotm/48uRqVzJXcFHwtUt94e67pBlaej/Piagpsi6fq6soP/
3jdfmgvMRo58eGMpooQReVJwxq1x0Wtnlt8OOMM6psBbJXpiyra99lfFrQUOvQtgNyioADynmrcJ
lz+cTW0421V45wrWyrPQbBCSSZLvM2tWJ5HCJjRAAPsWJGPtkHFG3v2HEUvE+mdlCTWK91o7pVH0
6z46V8MvPEPyhm/PtoN4C02AKRjpwSGP0L62TkAIWSPKW+IONeUNnlCErsbtpIbV6CFwjestqIYm
xRE3ZNeIc8lehJcvEIFRdrUJ+p3D6gqWCxYh3RDsYqy1CiXuGcg1apazd3xTyApHPD3cUTKS8OD2
XkCeK6m6JJn8tR/sznVLaYtg45bTuNd90Y2J9t5Lh+ccpnUdidpjEsP9oeHYV7c3crUaNcRBWysU
o192cqX9RH7g3cFp5UddEkXRWWLE/AASWkQ7N/Uc6aUlS1hxmSvrkaJUX6zUOO4Nv9l0+9kjr8nq
TEgoT6RS7IumOSruMcZ78upSlKp+uvVG8Qus/XSJi84zp1MI9R1sV7mLDV/GQjfFkrx+IgQHgZOR
GyEVlXRVSBaInrDCRn95gFCpmrtjkk750Ele6S9XVbu1kMiMu/rQuGHdZhw2R7qSGiqF5wz3pQ/9
gwK/1TidkxvMwLg8bItbtTFUGhRx9RN1oUe6aBq4jgbR1oMUj5b9Ak+kcNvDSBvwDuPqAKQ9ovQR
/HOHL2AsBBUgPismQ2brZnHHX9qB7xPNUaHka1+gX1zNShFlwh/lyNGHEufA1v2wTtupRFWuJ3t0
BKCoCWwu3STOuVzbqNyxk9+40w6ZEI1WlFk60ydX8ge1y8LFfPRry7gQ8eZko0S5iTV1jiZC7zmU
uT/K2IcN1+U37zwBznU7Drhan0QKUdQIyB15p8248hiz3EKlTrNtQ4KsWlUq+dmkn5lfxJiVzu28
AccVG8HngY5tC2c5PMezOQnMh/4BdPu+6eNudZNN8b/ey5Nzomc9tk+O8xTgNaKpakHO4FhmcIeX
o2GdDy6OpytDGWlmh5g3Ieke+Z0n0aqvniAoCvxqRCxd8p1HVlRqgiPzEMMFNweiyPDVypaQH+iM
84idfzIRIQnQIo0QXXbNUYbb4eIhlVvw3Mh+XXSfbfIpV3LOTGRfw7ih3J06xqvm+Pi24sA+VUx+
Trk4mIHX501MmP9Cx0TSs5NTUDt25v8uhoeLdgpkXjKRTeSeIaUoiKwm+vkSu2+dMOK4GTgZaPMm
ZqQ0tix4PuN/C+C13ZtOFWMUNv0St5fuvG86SXVpv/GDsy5nvMHq1VwbYV3SERSJaLEOtKckT+gE
myC/rXKj/TNO0noe5h5UeU1Mq6R14cTWUgATsQNAYbn6EISJZ6jLez7jij1d29Q13kfLAy4c0VqT
XRt+MCNb57aHeA0baCaaLJiqJyFjwa73hLtiDeGqdA86KuTjrNdGbtGmqbwwF6yc8fLs1j9LJID8
BMRmS2JUwsk8Ky7tVPRo37X/+Yz8+H7ewce8MMsf2qLdvXwa3TdrRnYGDSxsD65sDZ9mRMfKHMn0
16nAcXupwKII2cG2CADNkbgjyJqwALQJtJYxL7V/ACHkMFYyS/xd9hm4oEO2KUH4sRGJueeAB6RM
2YeExxhc/NzT4GyEK61gXLeaOvsDFUZt8SbfICHC8rdMxkJeO/lwatE2K++hfppI17aR1fIVCVo7
hbe+1bZLmw3zmESyKbxaR8VZzCERvC1DHoSVodxdNbkMaN+FPf2USRrfo2zQUFFtW9DBaQvm4f5K
1igfLVyIfe/OwBBN1TIVy7eMyQu3z+KqkT9wgSkAbrn1vguKIEBMmHC1BQ/SGUIcr6SqhLrlMvV5
B2BsHCvw7ucDuYF+2cvGSWZBkwn1rS5FNv7/zRvoVfeWfu+2VPzmKor7oz1TynaIotyJigDnR7nH
EQXXf2hVuIcr85h5WcsAkwYtIrwAogXD/1pGEK547VwPXp4vDXOBflF8myuo9V3ktOKfnCwU3rBl
B1ewAc3LM2OibpicdYk41gt7mSotKIHoY2KEjfYOWHDTru8Trer1gdqCcJ9MZjQHaODpegmKdlbm
wng1bMpbBiVGNlvV4ycHl3VGOGrjb8ohBLaoQfMn/0dg3LgAelRDYw+ihZfn4ARo5enQvyLeOT5C
5h9vCIhFW3xYYH5A2SUg07Ci5bmw1xHkPpdr0ex4abF5fsaseJplhnanLkCsEOiG0VIbRULPYWww
2rGYBJU9xveE2+J9YwUQpFpDWBlNKUrPBopNNuG29cQZJIgfhj0loZQedzbXBhlOqQhfCBbf8pga
s/RiGnW2RRuuJPlwI+D0TaxMnd+PMrBji/Qnh70M06tmkSFwDdYb6TL9NlAZnPdSR04+t6oHzdLR
8dxraLYBYNCuQ6phe3iRzYUs27XWKKN20avtkl3oyyFXPg2+Cihahr18Lth4MdxQVhnpLT79W/cl
Al5yVfb9UlvmF615kh8kOScVZHhdHtGNYQ6mQt47+lC9SiTLcW4NFMrlFbgd9yXqbB2OOlZkcTgJ
CCgneH91Qy54HIP8ebdULNXSpDuds0bJ/jjZ7/Z1U/nM8ty7yBY+A4BBzq1uKUfOoqhL4wZZNUP+
QUnuM8I7CQfpaVrTbKKc1RVr8EPS4SJVgD8zLwbCVYVd78IgaqpRDD57pjYNjmDLyU1sl1uh6dup
oTytFVJe6QBt2hRIAI/YMs9vbbSa3Y82WxFklhAB5xrmjrUhpbRXdWBKXhM4SYLdm8wFlDpYo/DN
U8G7M7+JZhZxGo704qDgTltPlrSQSpujqp6c990PrPpwvtZHIUTQQk22H+Xot3n2h/KiQ7fYo7XO
hdzFL4ujisXwGQQyEozKcjyVfFYoscCpjMYc1TPtAHrtbVnIbQgeodQP4cEmwMxAFVPsRaN4f7gU
+PnQSUPof+T91/82yG0B8IYHkUHhm7K/U5G9ZHkuDE0OBXchBBFRJaXesSZW2iWct1fJAu2UycS/
nRV6L4VwL13TszRfcoTWGxIUPc/g3c7G7lR/2dQRIiItHSrh7oSJhXUEDeyjSCTYhMyz328BQrSk
zXgYo25TWUgXM/fWJhKcUvPf3qhfsKKlJ9hlLJ7m5ntZ+0FyAzESD/cNvKGtbEp0jZ7asb5z71wk
ngmn5uqZ4btWVhYAZlxJhfbmphoMqj/0NF07vpvBOtUZonAZGXaNEgqXoCFjtFW9b8FSqVYG0+RZ
pyE61gSgxBHIcr/EAhX1FiUiqGQpIi3iO/WbduYQpvXT8T5vpQWPF1uLI/69Rb9zqIQIyJ1vk6Yc
Fkww+xfnbMfl/LxUx5hoac603SIJmI1v6cQLrDjZoyklvG4TfcHvaesbXiyQguFG/6BCjl3zdI57
OT7tmofymNjdV1uF1wJ+iimcaJx7QVlGUyJ0dHYk4F1w6twxYoVfd7vocR530WW0E4ytbdUHVil8
E4WSZbE59ruyPW9mRAe46p4XQvnjE9Y0u1tLiOJdxhec8cnMpjPCnA2RQ0obah1IJ3cPXdF1S7Ud
jwKOEBYfaFuFwrLjWt9K1p5hm3CKk04ge+o5LcXDnU5yyshuwu5YbKWtx8O2Hl2wdj1YnSLAFvoH
Bjwl1U30P5xaodxC6H7TUaJbrtZYRhr0IWioP+ZMWVIW/kaEhabTvL6vlQfhrcd+yTFFC5xUr1YF
g2boWR19o2Jq7TeMVBPuSC5siQFIL4KrSzDRSE4tqou2d1OQOnE+NcjclYYgpIlLvInBH9xZlscb
6KZlHa85fodCnaJBTOgLRO+hPU9P5+X6+p0s1m+1bFNluMKQmWN8el3PDSil8xggsKG7f0fJBuzn
Yf9KXYpUB9ukDWnSaYu4hGntFdUTagmY8nWI4AiAh7ervKe0Ch1njIM/En++5pLdaDOHPoZFfamr
DML9uNqj3c+voVP6Q5LSj7u30cVeIdR+vhnwNRFy2atgakfs3KJAAAVPNmUARjg4EIqFnulA16K/
O0zgX1/E4nK6Ksg80y+kJmiyPhwaV45DyNxdik7o00JUtcfgHzHCsmHZYCs5IiXDCKzmKNSZQ5xI
6WkS09vew2MBa4kDwA6Fx2sxwI6/4mQJojFu5SrfqlVCDMK64e2cjBT3JPGXPtQMKBT41Lz1E0mu
0TUmTD/6syDnP3eqvfVtTb5OaO45vh6xJIgCaROuf+2jMQM6dUCeUddIiHaSy7dW4mdP7vQPgdqL
1b0PL2RWGUgbHrk2SFEhAqUGgMz0MI0nC3QaUnpAfa4Y3f3uJgIXSZgprsHgpo9TN+TClUdosbJl
XxoMxaSq4dPw/7vePgyKf/86l8UJpAWKm3bLBNNxItqYNXFMEFww6DuCDFxAJjm6FGHtij+dh5KG
iCRvQ/w1NI8xyjKsvh7nnWnVTBmNVKzqUx0KG7gBEEUG2vq9aYgbYvLU46910VIt1rpipfwcEv+t
8oNpUI+WcYAf7GhbE2EQFFQTvK6O4u2bmW+rCO0F2V9+m0uTaSD4NTbEPIDT+4RZ8hvQYxHrpI8s
HYbhfrS4MIuz4V501uUlPHxB3ZIoRkQZcufNowWCB8HslFm9fm/6O8P1e7kLGk7JmLD63g1Kjh6m
n0+v4msBzhdvoAN+I2ESGPexXMgWRKZHcG1+0ToXmVlbKyc8lQvsmSfpoWrLpi9HogxIfUcKSafs
yat2jus3E0u5EfuOlodTIEo8O6cJh8yET3i2WJZPxbFck3LI/nbsm/7L7Kl9kE+1jI35yC+o2CJ7
0wCuOsd1Ybv0SmFPlnRmDPmETWiRalO09KxDWswAwiK9XjlGDstLDMyecccPcvqVPkA3C1cxVa44
znrZa/ccBHwvbttSbvN1XXrQINl1C113m1TelIl1agBhOvPE8G0/qAS90+1XZ0pi2pMfbkgWBDRG
qgc6f8nK/+RqvPvWrNpCynm/q4cTpDd1u2Sv63oh6HgYEN/3ZNBt9nbI32mhdlLqH3ZfmExypaI5
EWe3jO5AIbMBwPcpM+Iiw816xjFNtQvdYZZw4X3YCmM97ClRXlR8tIcXswAHpHP74L9D14bLgV1l
gqVYBxFrv0f+/g5kKPisEq2KcRxl/AvzDzuF07hwpSPQYTziJtW4mXCsWtru/0Ctnh5ywV4Sp3PM
CPoRoElJ51d6r2jl9ZhGTTn2+vmrmfuEm9S8RW/B0TRrB6XuHSPOmu6LASuzc4Or2OoLapYte1+l
vynsS+wm8Ppnwt14kvoGddjKrFJFtEDOeUXNi5RBoouVG8g+gX5Jp5ipZfS0NS06tj+2Q9g51ZCC
w4oodXycXwxbkAq1ZNP9BaaxdcLlG4jajKeZcxIWkcO0dKJThN5nq6IrQjhuaMPLsmWgaL/dal3d
gVzGndTkT+HkA3P9dbipfGNjd6eIIxNFeahhpfukUO6KRBZv6jnDfycmV33PfjyrqZt951XZJZ2u
rlm/k4qxsGUMQatyI3KXipfzFGHrLc+LTTJeL3OIyJ2Tybtvcq0BPy1BjNxhCxu64OfVw3VtP7JR
Giujk9F3uR+IjWGNFdEPdVUxcDvlUCKtIRT6liKk/5RZPOcQUErikHKmZBj2GSO8st7NuhMjrB1T
ExiLlvO8hVFMfckeBApub0FKg3KmRs75Lo8Ob5djfZdWko6zAIZLMyFgQcHXnUpYikJseym42My6
ubtFWrtAXtRhGRhsRb8MwB6uvE6Mm5I/ZlGdM/PXbXjOAbnYc5CfBTEZ96+rZW8Om3d1EVRPm2Oo
4c5oPSX+v6w4qV7MBRnMZm+JYEUSTIIwoU+WUPKxp5R+Ne5rmJn4h1HYNlWTqajHLZmhA0xMfJSJ
3JYRMX6wMPK6k3M7IAqikwboxKPKFO8462zA/cjJ3I+ig+rBaX2/kkOwUzqWO89pmwN6wR+7CBZa
xrCjeoEFrPqP1ox1WV6gMnLIvQ06WAbGlp+KuODcvaPsLinUYjH9RuuBpJAZWI3oBUkvBHXu3YH4
JZSjAZ7rjHLwLlNSS7HR8tlLNb1QKRRDHbZMJdJnEPzUstt3ZYOeT3QXN5MQsRalslzjtYM0tHE7
xHU3xyvxHKTt/Ik1s7fGTZ31Pb5rEL1ZzMq0x7cDG0C0dsCR/xezMewUmdOd516ft2YQgdeE0jOc
Ldvc3lvS83TbwSD4/mYEX3Qqy5krYiCzYKvHmJTJXDlh0FDS5+SydczCgKo/SeLxDtAgvUM/RGbd
kof6CkFXU4swFM5z2s9UmqCLnXQ17Dvvy3xBngjvZlPsNROCFecCU7fGaYp70jW8ULfvz7Deeuku
qK8918CiUuS4zkkkNX5iBLJS5FwXGBMpn1tUdMZvh90E8evKoGg9osCP5MAnh4l0AbKgVeVN02RU
eHeTTdECnLJ340I2bzVlZ5AkB2KgsBoLHS1flsShG9akJqGnncN8D5uEkVJ2yR96bFEHWYPF3Y8L
zdKRh4iXoBVOOvMQ2D8ahHs5E3EvOMHBoQ9wWhJQTKEylc44z01Xfy+S+K1Vc2ht3t57J/SgG3vY
JxgzpmqwaCsdnWjE52LkMIQByIAFAErd1JeMqPnGhyRZ/P1XAL26ZPmFgqf2jMFgJFVIXv5H9bp4
K3Mc9QWUikt7aUqfxajTpfIFRKIs+wldaYyqgfL5B1pUWqOLR4SCEGb+H7Nh0RhpPPXN80qH3t6e
QdD9/91LN27JMe9uA3GIq7wQx73bcaFCcK5OloGErQ9T4PgYv6u+IEOlYSuwoI2bUPJQW0RUBGdx
9AjPQ/LQFuKjtMIWktPRJ6G4VA7EtWr7LvE8UkcCxbBl7u9T1MQnrLXO7njSP2mdW7y0quvrtrJj
kI0c6FdnVSTeKIhwElF6z8+9KM7WDGGoxqC0U2iibLfUCXJ2s68LPWsOnQ/5TRSaTEow7XMj91ie
vIfTnKtQqyuGoXOGsPnh7s75xjd5aT/vEY0tRl3FncwNCyzVJHNXv3vXavB6xhzKh/I3E03PQVma
VYDZ5jzzuZpwg0R/hy74SxfCEtGe/9qmJW9nQRSibl3BIfmgwajKk3Mg8fxUIBCknPlsz2zZw8vi
qxmDDEtVglJSsCYP5zSnEIsEz+09F8bSlKmGwWqsf3DEiNkWmSh/FCKRZ5bve6qYjjenSBi1leFi
3sAg1usuKjFmOqcDaWu+UumVP2bQHXxB/6tLVfBazcBFrp3SegLlO9hnZeMSCfgxc08mT+a7Gn4V
PYNR+U5Cpi7ycsWQAlbbFtJIwfaOdQJE6qSYmIFAPnSOjYzZB1YviW5ktRTDPAQUOInHXsjzg8Ul
z2thAUmvjuJH5DXUPpH+cbvSNnzC8064hjEUJsx4ZI+37dLg9JiNIti5H+JvBsO1S6QOszfUeuBp
ggB4lYlXM7mK3oj3M4rfsNrP50IiehhE1EptYJYVjL/WzizZGJMU88zClEwZHEZa8SGwnwdY+IAJ
mqfTFd49lyiCyTycjw2c6SgYJ68848/QAIk06vZYkgQwTQU///8nUgSsStapxqfjLqunckyezJW+
00t3J7ic0tONwP/ZTulrRi+vrL++mMjXUfifCc/PqcPNwOXhmh3qD9US/8xWh3YNFc6S9QS8jl07
GA6ubXZVP1b2ctGotbScCffYkPKWGK8hTE4OmN43Op4Tkjx7xrMlfBQeZw9B1LnR3ZyEY/krlFLI
JNI7hw0RoH9iiSGkiaBGOMsDKDb1KADwiyfCk06tur7RNzetpmI8CFWEj54oKTJn+5IxptsmDlEz
m1MnKPfF83rb6pRXG5OX9z3+E1KzFCgpJFOGtXyGbpgtAr1wZa7k3Kit9LO2KZfpzl+iBfL21sAf
iR8V9p4XGlBKinjMfFD8xVOZEfy9APDJo42wgXHucL/CNe5573g0UGrtCetsqMFupqOZuX6gDaPK
rU9+G/3wYiXKDTA9fy2sm4dM6am2ahzb2J+xvWhcRV3nqZGkw9TE8F7P0z6y9qe8JwVoA/ZEbx+4
n6/Mh31tdOOrSD9WUwyk63LUQK5XUwMqHyZOowjPieYpIaApKLr5BLOTbBM68tcvHW2UoI4vT1rR
tV2TsezKN+rxwoI70Q5wI3vjuC+qd1ji9r2A4hxxuFPxVX6NTq3Fj/GNHrtPNMyQnDMUoc8b6r9u
XibjG/+rlGf3lywEs5RvaK34WBDk/ZIubBGP2Ry5GGuvCFw2Q3PO+nyu04ZM/gJrUqfZAjAlFSlo
Im088+W4QHO85h1AxJkQhzJTgmur1c1cDmllPc7sgQRSw4y911+x4z5XLkHrShXIaE9OWmaucQ2r
bCdoEWSwT6wGq3a8rxjL3qRlRbOWG3+GthlOqQKyqwv6li5VFGOF58r23F9JBNgchg4nKTBDw8su
6OpLtfBObd0h74IrkQJUU7xiiZG6kFaAPfc9nAMpVuFxZ3tZd5gpPLM0IOCZNVz5kD4yWmXSFYxU
j3NR0Sgoade8nUAGxHgWoeg9innMySrqu6HFgTtPoGvP1DPhh1yFyxGOUhHzxYWRPX9gQMdnQkiA
JhOtFQrzTjVFP/7DvA9zQxCFgokKWhT8GOtKaSNCJeW2MKCrwCAwBuXPbr7r/sE4uedY3KFPrAHc
V8t9c50W+qsH/2Zf4ODr+1RqBEqJRg9qh2aXhRjne2ddFPoXrCRXGNylczn8jjRU5djQ5joB8lGE
Zx2SiZxhVXHeQ1LPuBiBAyuRO6WdoloDnh3cynBiwakn4RQvWCh41IPEM/RChg2EmaApHFqfIslY
hRvHI/qBZG46EV6V38tpi9oNOA9v29uy6em8IjM6pkBxZIUWuO/VrxOIuJR3pX6ZI9pSlYPPKIUm
WErXfZqhKAq7xl/+mBCqlMoL0KzrNlCEEMyxJ4JkgO7rzROth4U6sNLjTHSeYbm9qmUfDre3eIW4
LXppa4LHUi5njqKT2lVQV+FgXEJU4HjM71t3xIfpLVDsQBa2V+qHQp+bXSIjvAzqTg9fqtvVhJc9
44NjUOzKPsIGsen2mPk2uGCi1BUDhryENgFh7LNK+p7P6QG055AwEKobnAZ68EMuJBeh8AgGaWXh
tJM0JDmdimetJXIOeA4vvhmqAAgQ0CZ2l9gHehu0bCG2E57gL3KEfnyRVMTteha6e2jrfX5b7oGi
yydScJbnVpdF2MKuHWrr7gMlxrwu+5gipYxJRYMbDOtgHk1B3P3BKLL0XBX3kV26VMznKqfnwkie
rQ/yJaYMSA0stNKHyC9iwxrS0eaYVQjUeZaM1GYrPUgpf1PLHeg8+rGZTqhLgezbz8oPGANshlHz
PGB7E+IwlQXFnB4xwMMWBxqozXw9bTLen7xkhxVWiyUerID5NHomuEVzeGKpEVLPkgPn7d/em+D0
kbgYZGG3J8vkHz29mUH0u7wln1/koYvZmtcRPf8VYbk1YVR4rd+ldH99qNcfwdxuyzTxp9r6ggy8
V5C6IYDmBHkOsgkJ9o+inHbTKOHiHPBSCkINMRqI1+XolHVf6KvyPXHfM2vUF2ocbpJyFsxgibws
zZGwNU3bj5T0TsAC7MJJrtE8HPoG08K+fIqVSMuVy+WzBh/61iAjGMStNY+KGE0IQ+HSFn19ONur
Y5z4TyVH/t6yPtn0X5APf/pHD4HiCyxqGhTiBhmgJ3kCMMev2V1+hf+51n2YPTI70wwUgncuotk/
SKeEucRMkIJO2rtOm+X0AC5RgVkVC4MDutTLQDEpnaptBwdGDs7dUdGmT5MVmDzFNXPzyANS9soX
0tTvbgoOZlULO1yWUk5egTkmPhK7MNdUpXnJDhkcnyeCMEzsKQGqfhaYB2TfSTaPTDfRVPzD+vv4
m0oDumhl6gC/rf/2pDuEF8Zv7CiZDpMqBzhlOV6cmT5tkUzQ8PmBVXbu2sFvAkEtgQ+5nCvBBTu0
5En2FFQHICbO4Sr8dss9cwd8m2mR7Jtquq5RYUoQyA0ANo37QX7s4VRLoDnugSpNs2/OSBY9f5ah
pl/4wpn0aCSSHzpgr0zq622NCvUsVcNp5Z/wFWDzzlLL381wwYRiOTPHvEJt4P3/bUV4hcfaZA2Z
AfG8pUA2vP3dR2P2vXbB0EY2+0yBtCTn9zIGlzdjSjGpOnl9plnzfQoc7uReXVKrLBK/HY4kRNb4
YLlIpMEtceXaF5lxnwFyjfu5Jz7uW73tWQi3ZyJ6ZgCUwGsNsI12q+ZpWnSS/OsHQrXgL/SYrkNx
yslviOY+Pon9KYfTbL+Pj5Ru2tXZmIWwZ1YvR8u1fn6HRWfGZi36KIpBsnp08PtsQBGGzJcG4p2V
/wkuHeWpGcBn3kUYvPfl9G9qqSRi4yhL2JaVupCmWu3S7cvAX4lE+MtffWyekGDpyNv32Nk+gtyn
nOmb2skBjQgECEE1zle3SjrEFZLB8jH44Hv8QDThx6W2WayADdugQZhFe94vMrvH2y7AZ70JxUqD
GPBQw7rn/wq6PzYfzwk0bx7yaCxVh05WR2h1bbnh0Vy5vxImOKIxNQm03H4etBQy0oGNZlE9q+eG
JqywLBR4wgUY883DK8CADYo5n66yOu8r0ScI4Xv5AjKYspfUZ14hQCLy/5FsM8HmwVhESC4ThakQ
jqHi0DPWgVFSvdmIePTlO1yG17P6o1tRvUv7a7HNG+czC2YW89eURrujgZWUDMBgpVElfg1VX4AR
W2TwaHHIHKlQCmH0IV5+6/v5NHBWEQSJP0YpdPgELky6nL22MYfCTA4lF+mrk+o5uQZfcFr7Oe/4
TfYdsPhfMXonWbxrG4tvGoNK3kMQ61/6Gti3CCShOXhyxtTJuiziYpw0n33V7l/U9F/PbXPt40Qa
BC7vtquJ5zmXudON8TZag6ZQV21hOZhbBWwZbcF2EOCk/BmQy2UwAbPsddtZXvkViBdfenf8e1P9
Sn9bH3HX9Dz5E7y0RE6qJm6aWFhFXmgt4SWyEj77gshu+xoPHJgZZu4UZF2xSbP8XwpbjSZouCTa
Hsj4ksgPHV4MGNKQBZE8wkFBwhCiwSzUDCqP+WeWzyMlPxq2EZb5SArElXPthtnQ9xFkxfXuxKj0
5VnUmQ6k0FeaUlnfFTr7OIvamxIozkq06exneASElI/gppDQPBTjNUOCP0nu23VQzAnI/of+coA6
C3yjdhaCN9eNdJt9IQ5TlzLp8yrFGXAWh7/9mdhouAgtyW3flSZX13lNG2eBIgnEtv/yhFv9zm7F
uEOpECb2doAtoRfPfWA7SSTDavto+NkdzMqcQm7D99yq3lIxb4f7NMkWONBBZ7gdlckEb4c2YBRL
lU5WS1a1NZ5fF9zlHOPkyB6YpTE3lnRnbZnSiH8f3vN3gOUafLYM7FzhC0yQSBhRXAj8igC8b7X/
BrzuRWHiAILHS9RhQyjylaSPbDc2ZUMmW0faXGqN3FKYq9JNcmnviaKAQFHepD4svApQRWfl0vZM
mvn0n5j2NxdEmhAlAXrpcanNHz9TKNFpQy1reEhVT91P1XHmUhtqASaH8Mjh7bog1WhHw9E/T1mn
DGJ9lE33KVyCqAwz5xNkP7ZH8elB9mFjygojQ+flThV6CxhY7PWg1ahpsvas4dJCRmQvD5ioxdNT
64VXX7sC1MO2ZDwxGheI1RrRJfW8XjWD6RQq8OFTQtRvQB4f9xWYXNH3cHUhbIrb0dwgIvidsbdK
drjjN9StMRvnmNabDLLrwWJnXd0fRqyfeSgMw/BF1mUsyDYQHOQpdNMzoUNPrs7YqH6qHFNUQFwj
wO4c4nubfPxW8e08A2PbGj7OuKQzKoRuprvU8McxLVBxMxqC1En4zjwrxwEOTk3cgsozDGTV3P4m
2++QR6lqai06XzUtkS57dRlbasyeJtAcELOZNZujaoWSfc3bBaOX5/U/dCdXbG9nUwuXIEl3EA5C
i03y5DgA3VNWudsaHqtNqb2JOqUKCTJenBUpZkmyY8bPIAVluosnDXQNg0ROIkugZB+C8zk0eLRt
v8CQ1LNIGKkijdke4TcDs8qL5P7y0Q9zF+dS7p89qwGxmwdftui/SLxOzgImcukxSDUVRdPQzyXG
zegBIGnuTMT10Q1qI6wr57vm7ecmIEw/zO01h/UsPP1hsd1/A43UT6kaCkQkH7gxdAGrSvJBIr8Z
DKvtoEkZvk9xT0VsmYkxRNef9e7Ap2XjyX8GEzekCtjkR8Rf6iDBOMc/6EkO+zOr7D145gUxkM8L
EFHLVTTGcWLAqpocqjwGOc9cz8mqwlecStqOXEGprkxG0LzexqMEHdJGnmtxFceKv+YGnQ+Lfmat
+ibttw6ylFptvk+XWiFXwqce3JudMIxpKhzcrp6MgH3LPAQAA8NO765b4J+655umlK22Bu2yCSvW
QX88sErkUyjng3TjHfcRedywkWJYDoxRwhvxX0UNbILWW4Dpn41o3sCGOZ9d8bJV9zcwDNm7RITF
mMQlWguLnnob5Tv9foAK0gd6BVcBmSevkYVz3978JfwlQUHre15wsGmWpKOIDg1wMLo0+lMFdJlG
/0V8S9FhaZXjOa27Yi+0O4KgkHW1aKGuZOa5VpX3pJ5Qp5Wkby78zJo4+Dyt4bGUX9MBKMykbhNu
3xBKZFeqmFJGbn8tVBJJTNgaW1IMFbXpmSgWfKN0r+6EnoKFhOwqKwIjdu3KJ0PaaqqYtxhiWASn
pwSSi72y6DP+bXBnF09EAVB8+Q0cEhqK0ZEiDYhkDgpH5DO3236QCJEGg87zkZII9yGcvghorZDa
M8yOGiO3H+45ChV7xfPlwSD8AL+WLFZvPoEpVLVhttWyv5Qsepmvbj8l3HfiJHE+Fug0nEPIOfac
SpilA5YfLjPLBGanP3grHvBjukNiH4wtaEOu3GhNaIHbmn1Jz7+BEzlgk85c0hnuTEjtEHnXBxff
5nkN6u7A1PS8NwTCOlheNDbBwevD8wueByhEREa9vvzFyd9wb+Uz9COO2yppTGKVlXiZlOA/j/1R
cCYtf1+6zfVadpNlGKqRknUmqE+NOMvatOlH87n7eKlYKI4Iq7keLS3IJxoes8j7vn45lPJCBtW3
q6y8HikNr/Vvx0+0yZDQfdHFcDzARKP8DSPQY0JAfb+Ns1mhJRzRaGeQhhtwruEMdBKhgAmDfXrB
74OnQhMkU6ia9D3LkDaU5/0sBel1vls2MB3OGbLvdV3atP5/7TQHMUucNjqZqAF7XBj6Q6CzzYDo
aQDvoK12ex4q+idihECBFPCQIizdaB62x6i39Moql6jd88zAitYKzj0jOeH3zHGvp0YkC51AX4iA
Mdt0mBcB9IKgZyiPubH9j5mXXZASKVXzRbZ7QrHH8gTl0w1rI+GPSiIXkotPVxVwVMiez1bX0dv4
53Sy9ozfB0gqUbfGjYR6P7FkTA2Sac5lwSb8ZjM2laxt5ba2Bdyzhe3EszgRbtwF8v749tX5X662
HVS7+0N/5P4kDQYuOwbY/IAs5Nl/PZivTOL77V8ccmaqQAQ+ThSHiJDz/fvCnZJFP2WGT/swE12v
wsVpcLi+nOn7KvMLtDd5USrFRJtKeI4lmn6zI4kZROGEA+VqB4B/EqP34Xw3TCdwY7AG6CFL9qdM
W4dlzEvNfiShJcwMK51jC10D3RjFTf0vV/4tMVXEKebuftjEBD3V2DFInfY7G1QkzrAcEPSpf+kM
5HF9DGd9kgzGUJCatY6GV+iUNraCs+hd2pg6loFwRbiiY3ldgznFyU3WsHO6ndcxzLlhMXfAb81F
zjiPI/NALfw4ezhiO06cn8hLfTb5o6biGWB7Ny8NbAJrx19c9hGzz7kSjLZcxIJmEDQgRww0nMOV
6tXcArmJBi66BrTarZV6on+pBdmgFMwP3oE8gfqLGf9kCSIvwrG3poeYzAotC98htUGfNLJikHDy
Wv9J1KUeptkBU9neSRzc+Ajg62greD0kB1vaOH9l7aImwnQe3cTwyTNUbpSueD+G3sLCaO3RdKqr
OgEOvJYrOY1qwJHM9WnDavm8kRSujKcDsM5NEk3o4YbOY6akcGj8UyaH28topZOTCsv+udmLuq4D
bEc23semOPMziNKOMDMGtEq1fuQW0D8fv1l7e9MQfZt8In3hmnMvnHAqu9oLm+/qCjl+G01oJk2Z
YBbkGTRg2d+zWBcxK1crqbnRBSKcGWf3htOnTfzfiK0sacQW7SQPfjq216mUOmWPA78H596HqOA8
vsb+Le5y6EnDZV6XYLW1EECa9Sfsc5e1Y7yKpxRJwvPwqn6mTPezmjsya35bEu82fORHEhyYUSrV
FPDTegzW/DAq5Wynz4MTc0EkLShXeEw2JAlHm8nK9G7TTKmAEgA4s3Yz4D+Do1KwtuFtetAz+pKp
n6T8xNJQZ/4w09jptSBHiy//WVsxqo3loLhMe9RoiiyGuU2s30Ns2lPnZd1JCzoYnSVj+afQx/+Q
B3CdBpoH3pYwWPQ9ayEvv6PkpNMH/EYxIlMrMBOXDRKDXY1Ate3nIa73c1WbWuwBa/GBQEUJ4gpf
966lBb3kw1kJfJWD7sXrgafEHqiLybgJ13Cl95W2RSzpBS9LK6TwjG0SE8Fg+e3UFudb0Nsk3O6K
zz5MH581l6/0cmlnYmKpK2vVscOS7OnRiQ7TXwxFH3/zVqcQV2wcoQKTi8CdRC4bvQv5kECM8GTV
1GJGqNJVaGTUr9SKISZc6uOzcXyOFFHlHMiW/hI7+ShJUDIPy1kXKgFXynlpk/1YEuEp7tF/Sqb1
cvE+8UixgFTp+pMtCdh72VI5PcUl9R4iaZZfQh5xps8i6ctKv9ICrfoE+wuoHMafx/IRYUqdN1WD
Ih32NhaGzaSwZ3yk1LRGsvUHrXZdNATdPONTZSkWqkFX6rl1A6b6tSglyoh973c58WWmFiGF89bJ
xVIWN8m7GR/8t3c5Mw6CL9f3HwaDGWVlYVymYylcD5MgRF0VgqlOnjVUqvsNGjmCTpWQPF21pC2W
KoNcv2qhX0P7vXriu0A6F1IYLXZqvaS6ufLNG2Iro+sSJ/rHTojySDdOLxh4krTOPSxLXygpPqHf
C5iN3sHgNue+igpnM9YfnPRcco0O9rAp1L+mVeOwUdB7oPQgiVcJUKrBGTQ9gQG88SkrwM4reAvK
F55C+H4lBtF8r61ASE4zDw2cJyx01dLeR/7PMji1ctNgA9TXtVdTB0LgTTqa7MsAfqeuNLb9rpXf
LUTu4nAseJF7E5uIB2aGRnojV4pbQdRuNMk2cbnTp0xgjSiyQ6FJVniB79t0/JpR5Iwo0xwxd/SJ
IIuu1i37uSy29DQBWXzYR1nhGdN4a9SqRz3GePemCEXxwUUFE9PH39+BGw+7yRiLlzH9h/gRvldF
HFpAXOwmSwtmyV3BMb2f+KqhaQptVzevT58Hj9DclbEGlkjUu5WL7hhVOCEKT8TDFP1J2ZgAVqjX
KJn+YwQUCn7D6344wbC5+HtApJbUMxUkB0s5sqeQOPQTlDPWFFua7kA44mSn13upFqjP6Z65bY3H
e/KSkrjN9w2mWq9RAtMTCoLbiszmBfjDmb34ilVlHa4+bj1m6G7h0vj1Rc/AftWJ988vt1aJAms4
A7btD5EZIQTUIr4Bz4l54rhOVnNRQTrfmJSZxWrwDPygJgPj0il1KjJh53c4vBlLBgyYBvYn+q5w
MOBeJnML9FMkkSUbMFENypdd9uUoRx1J57Ck/YJNUEGclVRT0Z5D5hmtV0LD+DeckXD04IhS8IvM
GbKFxc6QKHRfW8ZumNgyGymE1Ulz7Vdnxo8W8kPZnXyw5dINXUdmA0/Agl3SpecUFBRgW6EIIxwU
bf4syIQ2jlwR7oC93Y6eAYcSbSSJE3fv7UAB8ELmQDtaqZhs8+HfIWFjkNjsnA+ZUX0AsNK7iimD
28V3V/mQV0UpUwJCoe/83yow1+zXsY+du4Mu0wCvP9h6LS2MC/RlfQadguVqlHremhh5ZK9TfQsd
S9x9MV0Z4mJTOPKIpWO25FssyFBwRgQKaLfREqxV1oej5vG7JRXOeXdZUn3yU3JUYaAm1QiLpBm3
kWh8G60/1D76wAotE1DKUM2C4jAAdX6a8936rfRPWyDDBcg0ojZmrcbLuYh/daDNy6gAvoRdl/DA
0x4FIuLJ9M3GN8uywQoLTl/mMWXXaufYhKYNMfg+sZjWu8Z8K/lqjosdYGf0EGNkHh5FVAbWI5L4
fAtyr9HVUUpnqzKIf0PshpeTFxNpKm9s+TARzmsjDbhLkGi5nkqOglsfIPIhOFuPlzxasB5JxZAA
z1Bg43T8NGoE97Xd2QkYB1ox5gKVN6rEkhH9CVn9dCnBaEQs82NQc5XVcnjG/dJm5MKrwiNNupu6
r7TpRDr33xqFf1EzFo9ga2dR8QQl6l5sBQUjzfVG8NBol8t9n95vhQih5Ge+v4YZMp3cU1u24J8/
dNfVyVYkg7J2kO/FEANfjrm3aW1jphLcKqiWaPdEHLzCazkqAHC8WNfsqGkIC5aA0cSdqPDH62cx
a4/1CRoD7eS3zDrt92V4jTv3mzqNQUUuRr2wWJ1KzJs1N0c8M61bFp5b9BDbnP5QjWhdKxTdMDJu
hITPLXmhNU5BGWseuSSHFk/P0WKvzubC0KOMCGp0eEtHimpaW5z3yjIAnfSELJ50MNkE1QDCDhUy
apstgu9T/xrclLMA3Z8xJxUxduQtkUJBSbb/p8MLFwm6ds26r8Z265bsddujIC9bxkQsEq4qVjac
DavFpDz0JRYquGzC4YZbq2tMDrqIGas/BH35Hefc3TZKuKpoK7c937bW1scaq4SeG44PdlmDgd1Z
KUfljucd0Tc81J8MevYSuuzcOeFqI3dJska14R8S//mrswgXOWcPFpmEVSl+ySeTUCrPrqUOoNxE
/FjuymlLq4lqYok2K8D3H96WkuH6hDjVLh4DxKk5InDXkY93tY/IhzdM9hz8K+Qv5ywIngLBdd4n
QuKYDGkwbh2FLFtJTjCSMDN6978/ATCoUNhIE7aSKGk1A7MO9VchH6B7JkCIXF+Pz/9nm990vTmS
KCj3HFFU9o4fLbn1njiCKTyuNFwHaYs51gX1IBRNtzG5mCqCH1mwty4KH6h37ZRH+l+oGI3m/tes
WGeRP0bdrth9UXCfxvdKN66HcmQMJZd29MMxd9xe8f+6zcUmS1yQv8AT4kQL1A3+lLwYN8o4ZWDg
c4gcdaFZcwlfSy/NVSqx+7bdrSmxwELWfpHDyEnouXnNi/8+7gDK4svWwChCbqKLmnow6doAl6VO
3wfb7DtzPyZy/GgeX25QPzweTS9dE8/76ththZyiFs8cXzS4ox/J5UIjl6lAjJxhLvUlVFGNF6P4
EdVKrMoc0A7hgpA5rulEsm+vEaV/UaYJ7ClS2EAkh+gzYFoWo6Le74cH6cTrF7eXpuqOe6kwTn43
UA3hmmUvvaAqMC0nK4h9FhPXkbWCpEnmBicB0mOi6KdrmVTQ7wLaAw1Rqo2nrVhYlk1SKemCH09N
DSW6x1hmJBuVd5nACj3LJj5bMp+C1/vUNiTFr6xnN241N87Wkd2ZyZXPATIo+hsdwOXgGI1+hg47
8ba3+Q9IdTMSDn2ucjJ/7NaLT3qlyfMdofxV3sMNqOZJ57bHebpV9t4AakQrsLS6vodr3oCXEJVv
jLl5V3U+WaRec46DdnigyfkgSWeMQ+cDgxNGBlmWn4jk4XNUIJRLQ0OB6x14c40P/U3PdlCCMvWB
QUvIJv9383PfruPwZxLHcwCfFBTTMLSEx3QdoHDqqiIniWQbCm+oRuQWNcOaUvYm8sNb/pZU+cMF
P62OUuX6kUM2AWwI4fYr6rzlsc5sjSmZXh9nbcqwZEF1wTGdqcHUgetKtWSncVbM97t0KREcAWOL
WFVNrZeuHK3dSmxgCalDKvh8XlZaOhOuHgBlWZvPDpn6LvDSyJnly/aelcDFd1Z6aGGzLH0RGOOy
9nTYbXcZQe4OYssB53LVOxZVCCt1mZ4eWKlcTqlH3W59f4omRn0lFZkAVvcG7WYSen6RipXC00dY
TKwW1awWMlLY9tvJCkbEH1/NZ9V8t5jXMFLbne+h4XJoBVQucX3LWvaLr2k2rxnpbr1qoHuUBEe7
zPaBi82TSRkBYCx5vYk4kwkns/8KArizuqg8DRGrmb5sT2KT2vm6VHpCdDgrcPLh3ryasnmn4OaO
w13KFOb5WlFHZj2zX2sXSFcUVLauGkLfs+2A+7iLGTcvpMF9bbG5FCqiqcik4XEpEakyQpMe1W6w
WttQqk94E0miW6hMiOgVzEN+fwDPcnu3CrI5fFDsXXuFdE20nvtfTD2mfAkjjB2mASDGPKVOP5zX
RAfEgR4BjjeNjR0jb9f2ojbh8p5Qh7aTxXjvg1OiNBAQfjcreGmw2Xt504bFBtYqhJ886GpduCiQ
IZB5zC4/++P+AmeVOHcrSqqAPMO8C/4Ms2zDGmGp9IoxHaZsrWwBxrE8P9odGsxNjt1YSy2fA7PV
2SituzdeVND/AGSCMNYHEapFkKMDyL/UYWAO5CuVEkp5o/xBY4898Nvo2XJzdQ6EpHyI+3pIOUXj
fmkIgyf9fnG1dMQStIAlR4gmJY+mprmbAReOSe1kTrXv3ARsCglUXa39NpY1JYfuISmtun4aAylo
RXyNXnCzTRfY/RmG2Ylqxmx9n7E+MXgS5uGrNS6J3UzZex6n6dMHR62OHS8QulZlBZKBNwDcXNoB
y0dAysWLLWJA7cmEu/S54jMHt/0mIQbfVDmSSApZxQ9ZhgxWF7Kvy/ha+VVCFOYTbUyeRqOH8TAy
BCefEIPby+6i+pyiR8jeguHu9R6HulNkYnO46NdqWeNHtzyDyUbzNDuyV4p9VrFKiuRXkX8Bq37c
rB7NA01T9bXLmhJv7NIp5UwLqK4irJ2wPQt5Y83qkGhxSqmLSBAuRpkAp1dJTgeu+G3tRmSt/Nui
mRLjPjdXK0vOmbNP6VCqiAScuTzWhL+BmhQK2Ekyti4t97P2YymsIUXV9m8q6hGXgBDjHP1NdMPz
EVv9YDId+wSTyCD3nhB+FnTzqNXwwHm4gVRwgXqjbBnvKXVK9reOLOUOAgO7vte2lZ96gDAqMTFS
8B/Et2gp3trR7VBXDYOhQcIfsYxnFzkn0EJYYnOW+R64X4RkAMDlhIsDcmIZiBZf6twi793R2Z+j
FHptocMzJcqK2Awxvcp/+nMiD1qj+hhHopIQeB38wkGjb8QrW3YKwiDNn000S5iYJZWleyJyZ7dR
M8hUwVEPf11vqny/la/IQtiWZ5phG4ySVaSGnBNx50yCbXogcFkT0kzitB3Q3WrtTN75vo16kJrJ
oskkbjG8ckPHSjL3AeIWl64CTtYXhKMBPonHY0mImXYo4kaHFPEE7WfZoRQzYZ6nVILMB42gbkH0
p3cyYTO0MFITO/f0j5kgfqRmtJIyPOlpymMAV6vMd85gUGLUKyQt3IGUtdnlznXnMsYrjegYCRl6
L4lptIaW/nLUPM8dFxL34wh/PoO0z1pEc31Y04i32E+DThxgPVJzqptZMFzzTHwNSXbM3GQL+z9h
Hx+5m9yVipro/LbIskFNzD9ocdG+DF9yX1O9Vb9Sf8OHAkWwaz4YUdLB+/8BiuZ1cKiMxlxT2wUQ
rIb5oo3BdipjjTrTk6PAgW4qoyNGsxvsUOl1r5F6Ot8XX1+liJgSzkc3NRZgmbidJtPZbFM2ubOz
7ZU6+kQYR/xZ18aZKjcT2+21n4q35BUz4gnfT4JUaz9fyeuZHxGns3I0jxtfesXAy0z++AZsmiCU
dSdW/EMw7fItBsPJwZHtEXWp/GyXqHEbC1ueu6G9W1HsANIBiZM9WJKzrw1UaO7BbEhQWGRyPJOq
zvmNu+pgTX+kGju2OjrsqPb/1eLeE4ASnCYMmP8RYlO1WtLtSoylmzXVjIZ6NHYSqpbGZxSu9wmj
N7s9skSFmNl5dT6ZbgZWKpjTQQLKQcMI/Py5Gta4eo4rorolnrNkB7oFnmhI0UnWvxa2cd3G5CGU
Qx+EZfVQ7cTOKFR4DyoHmBMWQ2BujaCyEX8JkRKOPDc6cBjReLVwQ7Lrd7z90QQ0qzvyHYtU2CZ7
X1rrTn7zalN+xXVbPcWBPUZzuRoJ1AFMNK/+BHEHjMnr0lV5vubKVl665QX4mv1cw+dQRTJTNjgO
lqnksGaWawZu7pzADFd8luk6shARCO4K7DAAnN5ro+NnAq4oXjoG3HO/NFl2wxiIUJdio+y948rS
wJ9aK/qImApG7ZCP/uwhxBbc+OIQRsU2m10nwYAg6MJa7rMrNq5q4MPfi7ghpXhLcgCyDYnQsmIg
j3tUIlgFanOlY4eHADM7aYbVUcg6lkjnk/E2QyIFUv3ZddpSL8m2pg4encWS1uT7zL6XMF33Qv3M
t1LPF+8yXPjRTR9sYW+RSxk/TjIh1on+athDGCU9eInTRBwFtzPFQtYW40Dfg7qzgfpOkimPj2wC
93zufRjBxVj1rpHp5ycjVHOm8RXK9nO7UjRagiwdQfV0I3P51Db+vyCANAYfc5YR7b/Di3kvBfaw
jv/PkyZOD5dlTlWrtOaD7wHZIAvTt2EFR8ExuyA7Qa0MtpY3JM/rgErwDhhj3lIDabbVRM7sAr1Y
+08y2oOQW62MBEdEXQpT8F36XOPXNnglkPadWDLR+scmM01jajIAoj+VaF8SS/KNsG9zJBxveIK7
fq/9iHTVg32a8e3Ryd1m/oIW1T6eHIhUAn2WG/A82cgRzkYsmyj1bZcXtlrLqu98Jx7sjrfbPsTz
1cwRyE4QJ8oh2C8gciAHGUaWmH6oVhbbz/YETVxf95OhXyf1q5CtgNkLAW7WbQmRCkMAEkacgPr2
a4a4s1h1J+DwWhi2pZmUvuH/qb84jrrvih8CMB9+O2odJZ77bTybosSSVZPKxy/rcDdh2aVcUXCZ
aoBLpcXqOOP6cRcJVznJ2okFrEr3zVutrW2Y9Ra9isTWjUHU2gOj1YTVS/Psj1yo2Oi+5udbAkEy
ebqNP45OZxqZZEOA7eN8B2us/7rMZiGHDDRZxEzLZOeP47nbjJ/jZmsNg4D1pxD8PBrrLNpHWZPQ
BDO0Lns8TKmN6/VjQF7KJrXzDxfAXIIasTA3Q+AMUaCZPj/zOAMbwv0NW2/9X3nDpWwQ7t/MY7Rr
rGTG8A7eLD2bBjhMNm9TVgb+RpGBt05yC96kSbp7/A47RkmaF0VHVphnVuViilV5Ye/8nFLKac8q
Vee11mgsfzBpyxwGEXNeR7e++kMmgQRcRT6V1jmkSQekpgXZ2PqkDnOCJGM/IoRkxH08KxJfbzu1
Slw3ULYLio5S19j9tnQnruM2D/Nf6iV0O/0EAcPgjrpeVICGrApbsxZNqlH7V2Xk9ZXjvw1UwBL/
XeJRU0CAvMIS5R5OY21Kr6QV6cjnYuyfXEFXmv1XYBKCeO+/m21qq5xbVW7/Cski/vFn+TETmI9B
uN5Ma/9FV9ME3Nki8+dUDwwvONg9kugkZBrFSPgpF+JIGArzHD/I4AKWYyOfjneJorc8HSgcqgb3
06tYrHboFgjOBO7q5luMkz1jDbXBnUOnZS08fhGWsoin7Fosenb4+E+GMNndLecDplF0E1CJWtsx
MLZXm1Xf8U9LuLc6Ule448FaYcxhfU4h5l/XVn6y3td8AltcX2Be3GZ1t4I4mVuu+93ulGMOfOeT
QdsN6xxiGHZGetjH4VI99j/x4MFNrdMCZUdq6Re72/IIHTcyBeLzKhIcAM6Ido7iI3eRQerOE1i4
1lyoHA9webDMnuNOmrKXTmEiXz+IqKTXXi409CIAJrwJK41DBxDoIXRp5HbAvkMko9o925UIM3Bo
QSUNHpkPOFGoRhvfWZCBQxMtPnKqZQvZjqS0p7QWJe/iVrIK3DqC4ylsXWr48uJQjU+Pdy3EeeDb
2lBiNL+QOcvl01Dw9a6MWDHuZxgFgaDJqVffonb0TELeG6B2fbEoOG/HxJqYerbxJh+gBVOqKV27
7Fqk7c/M5y7EX3jBw1tn2pJIA8IzLmk6eECeMUKJva8NrEpqvl4Ng+dLFecS5CR1PPKdrEHITLtq
gxFYf5GGzr2gjOK1nUy6t8aN2QQESoJbrU7kBhG5IIaPHpcdaS0tytBx6kJeaORU58Yw1KPB+xN0
GyDKC+6NMEywSiNbEo7WO0jUtV9/qrgSR+dtzg70caGsBqPctEF+DY5/nBJNgpR4oX9z8zIXnv28
JnP1Cl3V1UWG25VXnEjinzT4kGySky6taJthgTJZAhthJq0CcnuvEin06S2QGliuqn8sRa+DT27n
+xI20MRpTaZXba+xd27KftlggfeTOFY6iVVBNNzy+YPUZSfNzHLqylBMRn9yPsKExGD9ONiNFueh
gowio3Bgbe46yUshMDGQ9Wu7LNK1Ss/BQOcRfV5qcJ7ZaHRz4SUDF7FX0cT6QnNTPF763NOxn0/M
L67GRRMhc80g5vh5qWpA7ItP/iXCUc4e1LfNLhqkcdp9ke049yw4qO15sDJX9ZRJiJmKbEuZ1saa
xCHn8WjkcjSc/NxjOoMw2YRNBD42s8AOziYKIDsqSUsUZJ+7/ZJ35Pm2JUxnumKEpXDiteJuHKj9
OdkLDmI1Fyy4mRMvus7ijf40XiGcG7CyGMdm7QKurWv3KiQNTWpHYpkEhlqMcyXAUb8yhQzhs3+H
rL0GGGLgxzOP43mLaMsvjPyN+WY89K3i4UkfrtDB9XXyt/dcziQlg3lzqlOYbFWLApIWpfvow5gJ
3tTHVlXIBM/Y0IerpJfpErBhd5keN6YtTJ/O4PobCF10JgIzulXblomt5hN+2cOyK8GHL8V39OLZ
dzz9I5YV5pBk/5Nw4qYfe5L7/NaNIeWFZBxL2K6p87REwbFsZ2OhrT1DvEw+v9qslw+mUSs8sR1Y
eRF2aQRIPPkeku6IQUvzx2E1VjEhk24DCGxVjXN1XIDHTR5FiIOzD+Gbl9ZFstXAPluC7hkWgKOj
EGnC4VUfEfZ5yvU71eywS5tT3zKP+JzZphVbhuBOY7KSxtlqcUWfJ833b4JpibvDKwT83mvRl8Do
iCLehSD0LRENma8jVaCAWS0RIeqoDzj/CYeJs0oMg9X1zpc/nDeshTpx9RQV2ck2dlm525JXtNrR
lWAouEv5V11N6dQ4TPe8nKcZq9nwCS+m6asWc8FVdSr/PkqsVL/PtZPuOAyzTK/LXsOhdMb+XPPq
V6pl20/a7w+OD9SDhetVOGlS+ldTVWvC/PmEcF8nNlznIklhiPbp2jTXOPeNI1pF3s0pTsbirBHR
9s/lnBqHg2j0/TybiqOlAOJeR+KHVPJQ1Y64B2tn5rTN1uCbYLqTuNnhUdD50o/MTZWpN331AJ2y
Bs3bhBsbUWOw8pshhEN+4U8+qJkMviWTeQKa5VggjslIaztN6EkwQbAe8mx5asXNnCuohZMy0YCg
IJEXKSAw8dGMdBy7Uij/wXPsIpZmWDgEa0ny6Y3aPa6hA1HQQGDdMMDNYY9qXPqnW76iBRtg8gy2
cl9/aePoqq4pj3Qq9G2GPF0dSAvilVd2jcf97mXTAt8231u9ZVJNTR5WOmNLYYEaOd/L7NuQTpJC
KDIz9MrcdiszJDJIbXg6TW3dCoGDBTSM0o6ZBxxL8d8YNp4mXGQD/jCNC45aV5Q3NpWFMWsuPdBX
tSJC82NPaxU8Dr3fkEHGSAGCVO2T0BeKy6cv3xkJko1rJ2YKPtrMRsSqmYOOrS+/yLHhKKIxEuCC
lYCX5mUUl25IQpOU9dEC0ltpBwfvy2Yen6OoRmhOF+1Wv7CS1xX0j0lCEnBF+K2v9khR9kNo5oex
0sx6MVh7CxbPQ7X1VNw+FoE5BGv0LAi3aDMlDCDxmfyElPBGyMqv4VZxOBQRU/ZAsU6708FFcahj
Ko6cSbeVOT141Zfz06IzsWX0g9BGuywmPJQt0Id2h8N6i8JSdG+u7c7WRRAVO8uU1PXzkBiucleN
sbnDlcCaMpJtLpz1+0k4qm+YYJ9P3WmQETiMZy7hAwz/tV4XgWAgbBpaNVcLIZFnUcn1j70NppIB
8uC0mK2HvXPMtwjCpesAvzpE8ujntF8spDEZkAqWUc11xxqCNPhi7Q8yyYra+9SpMO+fyw0LY2Tl
kBNPoqx+ifidQww8PcSj7Eg+3MpDegx1tDQiYSRLuWtUHKV6v9fCWM0lhuhq3/i7MXi7L3Le+toA
HBIYNO/+wPMOH4guOHo+VillbRJ71y517zOBPEk2UMmHkntfksugmZkp9/rToJlElen7GDmmZSP4
zy4VVAPlre2skuzws+W7KZ1IKEMu2n/za4uj3dcg4Gq6nCAFtJDJRzxsnjlGqaTtjfBHX0E/+Jeb
NaSKVNTBTA2rGTvF14zkvRV+lSDQB2eYII3szI/iFCfFTSVeK18VtRQlHh7McBIdx9/MMChfYKby
aj6fFFyuvrjdUxAETmqG66zfTqZqvK76yn6h0HD4x8JfkAIKTMGW8WItB/gvaVw6BmCiFFr1iU4/
UNHHolha+3rKvi7KeebNE4z0SSVKKK5WnJPWgPegKgaDqUKc8EF+9/ltLL9b6rTncJbufAvkt3G8
zywMGWG2dVJYSwecSJ/+HQ8tC5R44kdvVVqwBSGNt6F+xYmuvt0xarQFoeAG7xlA3WqiiQEkxfDI
LbDElSnhopPQ3yiEEtxUxp1YFW7jrdQUmc1WVbJk9bjMlmd7ErwUA21s6FfILND+iJGAZ0/JAdup
+nq7jq/gxe+XNray7JT1WiT7ITj333zvPVZIgMLqpzAoChFDiPVayUAqP4ySD908RG8HPxVWg8Gr
IaoNxa8Xt6vueAyB6nWhmZvwV8iPkB4PY0IwSYzZl7Ug6G+Ga1hWDFCLdauu/ugsKx4gAyafAGbb
E27HlOgyDitNIwDCL4GWK/PmE0BeUsJl7DXv21D5QwTvntQesVPJ2r+QNlxZ/jnFemBZ8f1rFKjQ
SHmDDjyGICy1o7T48VbCpcQcXi5DflnYZwCmfaen6abLtHdLIj2swfi1/QxVrlx9GQ/x8F9m59jr
NDxdLXkWIPPbHOGD40tZMlPlI+V7TwdAVaxblZjN5FrvGY1DE+Sf7juKDd5RSOvZ4HSU08hGdXIF
sHQn810iOC7g1Yz10Ue5rZntVtrH/Qi8+0v+VT5kJKDH7glBpa63z8Bj5OMV6K8VuK34L6n/zJk2
2aGbZCLou02IvJ5iiOizuA3DxnwW9lIXkAPWNT9Oz8u1wDmV4bDjc2/QfVkwYSWxASvkL4OPLVbD
sDFQF04bOUf+sM+xzQ+oE4XDolch9mHlr3BRjkA7HSsf547LQj+Psgnc/XO1yo2mP8j28DJ/EB+2
hfONzJYQYkJALt5ocRmFVGNX5eMhLTW9NcgKIFWq1K+47DmPM9WWYUtGIJvpDrr/XORgOcK+vnG4
zG/D2m6eZgfn8cUrkXzK3nxqa9Hbp30xAGhhqPCXW5kFf0TL6vgYUBOwhCyvn4wo2aF8aQwRNXpJ
rQKT/F+djK5FdVEPOai0Ra+/bScImQUpdwbHl8fgzSCnVUKQqjg9OtvwRuqPdQHt176P5Roxfd+4
CM1Vk51VVZMrj0tkhxu/lsgh6+5e3RdS4NcB6itftay6HJSt7lymhFM1Zjda2zwN4NR8jJEf/F7z
okWliksvLNwp96Zq2n7ff0Ma57ZpIh7le1rEJbEpkw1bXzUA20KMHYwrJJfUS2o/4sCeSigfmp2f
E6CNLqsy2I0un1Fg3mAKEdRAtrcA+ij+X8obk0si7YL1/QGHIheQq4Z8Zy1qsl10EXHWut8LV/Hh
1gYsPLtyiPNCdEJvrKMSzBiH6RrUStnNjvrTYIV3AFymawkOZJDPfswfnoz3TenL426ReP/9z/Ps
wvuVpisjlEvyDIzHBXrFrMuZbayBh8ON6EGb/18TyEeZdhDCWUg3Wk/zyS9sjUFo0EKuRPW2ni38
PtXzU5qrZk3sFqgDUIHX+gaTkj6vvxAzVjMrvO4TjsDWcZWr7h193xYuOxts3/yenkk/VIjb9xM8
ShCxT10B7TqsiQbxmfElFhQODTlXkB273S0eTDkKC71COs4dvijwF7fpKkaSkSuD8R/4uT1sRFYb
FRhSVp5fwbZnRiHmn+M1XTEeVXW7DVlMTKmHg+HxE7tnzLLdeAGmp7/+i4Lb5902C0KI3V/z8l4e
YaQ6EQW9tOKiGw3L6rKK3PWdqjr8LTbMhLsZGxasEL1f7ikpgA948NiQICQVEe00GEBWZ3Cz116j
OzMuLpp4cvZIfjSAu6noiCi7KCdiw2zknT5WmeYRsVZnO5kebXbJxbQ4nzWdzwcvA1VDqEqubM8g
PLa0iw4D8oHPsLVIYCL6AvirxgtnAprkChjsIVFnQuXLVuqrQZANdB2wI9mJNDUzOqnMt3dS2maC
2a1z0Ax/kZ+E3wwjfRXq1hoSxQ5AzjDD5KycwBhpyzxXP6kxvOQKlaMHRc79+odOZ633tAwahEYR
xFd4VBJDQeMgJKNYjVCozt9pxf2IQPGNOtsBJK6oipQyr0vLIQN6Nl8n1wY/QX4syrXOPBd+RNBy
KFF1xuND6O6QPHNmGClR5q3H+wS51LfHl/K3xqFBl7A316rXHCPMYluhmDR3whPSChZYWJFi/Uw4
6gEHc3Ajw7m2gzeOzYGGyKnboTGucQyxPrz9KyI6oeO4KPmnqh352mugTbDpf1Owwy8LcM13fnxn
asPAWQ9B6v22I6OT7arE8oIvqBuZDvjH+IF/wbGHT+NaItQPnDYSllAK5SwvKGPBoITrJBLoGm7c
XypPZ74Lj5bxfpidPUftQBJKNHMzlXeZpJCBVrC2glUTFBd3IjvfBYyhsKxuJ/UgHG8c6fDi0Yhg
pNv1xFRSneF4Ewo8bYylu2Gt2+RvtIYl2f7PPt11yMNnYlv0sWqXjrr11p3sxo6FW+hCH6PYqHxU
jEEo6/bdaf/txlutlrfbbYAC0d1FN17yVgmYARSvTKGxMIhxujhM82jo+0Xtrn0sXDMglJfjaxJa
S9tfsRVgDgz9rPTmBoPkJxsVNIO4Dk3+MuWV5QF0+k4FqeG/Utkx609C+e/HLXfKTwPTdShQPl5a
F5eJRfO7bhn9r0KvqfcDQupPN1xDUiwyFiDSbbRHn7LpIBqFOqbeUx+VthXoUnP+B04+hUwho3Ib
Q9JNucFuirkYBQYRpbT+d3DU7oEnIm9JEuHzw0Yxl8GZPOxPsoz7suctGvBGMWBxFGHsJmCNzL2X
NfHVZUkMkCcfnnJN6UOTR1DjDJiAJQlU2PnnHLSR7OP5p/BPTMjK3xSKLXMKCtLR5aOVqOvIWD6C
/7/YY99YuaCytdPHF6QdM3lBHvu/jNn2C4whUDVr5rQxyGybVQWldwhi2+7/1MRM5GhoRvHHHcAp
t7CP5j+k0qAgTN6n2KVIlIHqi2V+YtA9T94RILh5zScr3sjcWbet3/p5Yeq+GpKwp+5Xyct18iEw
Rh3SQtbsi9v+AlkfBbAxM/EmFx80ab8k5ycv1Puz1PA2Ykr4hNrkqlJ+wGT4GI0iHyYm5VxGDwiG
cdbuY1X2l+BYc8HrTQxJVBlC1sFt2r6/5yUaqjOXd26dK/Xu9mGmMifjgSmYYPYpbSuBlJgTiVyr
1rBxU6KUKuKKjc/wPhP9EiYXuPFJdPQ9I1AQODKlnIdmhSpQ5Qc8zr5GyhIqgRA5JJYjOmjmoslU
lwTd+aopQDgar1Q5lWHnic8dn8ZX1q3yAxtdqztSxGyRrL2E5hNGiCjhZ7wBr6ji+qyKSwc8WRnD
6sYT5Io2DumOw6ckFCaAfpZFwLeM6Yy1F1H4SgsGQbTUTz4U74oIOfA4sw9UIvq9x+6xyyl3e/ea
A1yIGTW0NdxYAwfosDS7uMx+3gSgC0l8eHzrbNcyWKiapQmcA1DnoYXrYxBpJD47AezxRkHD7X5v
nGy1BlASxTRLAZRnJ5feEtPpyWRtPVeeI11kcMqRYWOQkJAon8eLvdRRNrcU9V2FcNNmvldX89BR
oYN49JrockUiIVWGsaXXcHE8nmVr/Lb/yI/lnAaiPoLyul4sLSafxz4Rb8Yizzd8uQ+mOgp6MOu7
2Q7Rv8nLnh8iA1evqHAB+vRpN49ZEGjNnuGA0YK/COAa5MBHnr8zE8escEf8FP/UI8+xueZrcQxH
0IxOaakzdPQpJIvVz1jAFjmYn1F/rnTA0vgN8vMsMTYlF85KeHy8lGoS+hmBPQVTLRw4OJ7Q+GwI
UEBlAM/rPWSjE8F5K9RugNFwoVyUKn0vbiOvnczUN1JnbiXfH24rSlt8glWi1oGH4k46XZQl1pYc
ZoLXVxIJNzx5zsGvy9mZPvtDnYHx0nVAFXv3Qq3F8mTB7yIjgImSqwsDJhmbBzPFsyt4DKVUxdL6
Mfyuu+6gspUP3Jyv9suJ1Fxvn28mkZl/l6J3nWDhchpL67QJ0LVLOElVkNHeDR1AAQZNZUna7hfu
ILw8vVhJPNFFwcyznex72ucl5rKGbqeTQLtAczD5INfWCkVfeZgC8mH9ZOsaj4FzFXqljaTnaFfv
qcFPunS0s/8/NdmqDYKYcs0OcpULl671wESVurLdxvHXIxEnBMvOv7AkTryUEHwF/iMMobvXXaUZ
IddgDqg5ufIgmFXDQgslsa+vJuzdPBTrDm8R8NR051oWl4aahHKBq3/8TuyQRfoIv8RfK8SSNijU
OxgFdDybcMCfTBaBhfAWiVBMwHm1t7JbecB65WCxNeyPlOoZEt00UApNY/tN/Kf4lo+CrOr5FNk7
jgR/WLjFuVAd6XFUzIpRbjyHST5boh4AFw0y/+d2RCldXduL4bEcfKco8jvQvlxwYYFfSfUnOdTY
JTBCpXGAiFSvBMuWVgwPSF4cqLJn3kX36zkjz1aGHSxxdl32CHxdN94XZMq8J8+11K67uQXgsQ5j
cvSmPuz2smLwX9EyitAmoQsprteQEqKZ2IylNK6SihCEmm5RQJs15ZgQ9ZcepyjDdMvX08S0Lgyx
Sv0gV8Cio/L5YYICFFfaQkS89b7Cnf7YhnTbU43y4GK2vgPBjx4MvvWPhkBjn0JsuqnOyg6oCaU8
hIAQv1JRGXT+SvEXM2KfaoLRRx+8gbr07pt22iZmZ52QKO0KM9lPtPcvVWJ4j+CMbK4z6xXBzlQ4
uh+JRlbJlW4Ixuviqfncvs//5JeHLV4NAavtqFzl3XM8MtqJc00tfmDLRFG37kxUUF+BsuBQogya
QxnaG3c3DeDMM7swmqgx/ijqTF0A8MXxlVDGGkI5GESiBPIer2GlKtCDjgnjVSqoUtYCqqazZv9p
i5UWViKcHjPOTll/pc5dV0myP6TimhXVaUAvxnNaYytNXOwaoZbnDGI+SWGzcPXCavDBSFeaYhj4
UbqleZcnhK9FjXwPk0FKcNrWUZh8Wtcv4CREmoQ2yrX32/XHXJQS1wRfeT++1mPETDXlR9QH6A9V
yjwS7RVscN5L1Kmy7yN0Y1cScikPL3Kxl1F2rjOlUf8AUePdeEJM2QX3+013Zm39zngcQZMK3ND5
MPSEWp56YIqF9L5OFTZ/iMXMPkuOwyzoaR1loL1jcnL4pE5adCp9bQRBOgG46gyQ7A358gKNAzZO
FG5dcf8fmpLeIbVaTqwz5AnAEbeHBSogihs22749hOGbaXVJCwXSWWVNCnjD+ZtveYkl2uCM4VvY
aeGTsg2rU7BsJ1we5h6p0GIinpBheSzfAoKrPUpue1BnuQph9JW15uIljqomnC6yNqlfnxYJfEwt
aphVD28K1GaxokmRA3skfCx/VgEJ3jKTsPGDm4AlDQNKFPhnUyEd1tFFrSp9O4WwLnzA/4fRAQOX
vvZs8Zzq3suMJ0cKyvo99k1WCiaWpzgceN5GkGM8HnqSgDlTlmI7NPNpzkEqXQwOzc7pW8L9VTTE
RiXGp3w1kGygEghW/9rCW/ZVYdDoes8UXC/3gQlUGgNG14m9igeLIP4K3GMKbM8mgVGxQMaQ4eFj
7dX92oTkJOJ8F3Vw0ZTYSkLp407imNyfyeet1wD1sx0Hpxw2X2j77//9flHGGYRjjtbCunrT5ME5
CDvXzCBwfofmSEhQoFczhxk6wU7MGEO3RAiuMMAeG6AHuC9gFjzniP52vUT1gCkxPBR/kYY0eNbL
qsK+IphUvpZAcG4Dsj1cyuk8lz00+dIaflpicjyFp/XupIqk5qkD81Wdk7723ywSKfW2uwaahE5o
77Q6xHUEgOLjm9qHTwLftCEpp7cKXDPWyUuvVxvxGEb9CpuuIXo5qRTeb5Fj0argmKpNY7sjj+YL
r745NTRjofpaLtqG9Jtnbmrg9LcADdyIHLFt3FzsTHkcpNAIm30F4j56H+DVlp/Ncl0blPXcWPtM
HXz3oGpVE+j2E9W03Fhnpp/nL840UBfRBpduZtBUvNJ01UWfyOr3F+MtPaMHJCw1xHQ4HbwpbJJr
vPGUwBgL+h+ATeiXcI/0LpDPGmnRxsQ+8k7VzXW9lvP/so1eDwx1sUK9sVVR1/YP3CZaE78IDlxM
5oiCvqTcNN6v5WEUVhlA/tslfPb42VOADeCSOTDxxlWXr7qLqpmXvtz9u5QYetBcuyOyNMAGWzAP
aJErQ9i8SLfDMXl38f6mLw6ydUaSMR44lPZrBHIH2N5s0OiZLgck8edVJvafWyhpKgT2Ksx3sw4t
whHYX5emC9g3fJ98XaTX3HZi2UV6QXcPhAfkPzXC6LktQ5y3boK9Esa0I6SUanj3pyvD6Ygnn8rG
jB/VTh7zbpPJUBLjCYlwWspSPoKJS22DsOtlFEwfL7hut1FlW8fZjaGIn4bu3dzaHGeRYWBpPGa3
AqawykSOHWn5x0y0sgYP+lqeCyuFgHyxJOqHUI2hunRwjay/wouZDZ7SSB1ibpWt1zBRqGa8Y8zI
t/wHS1lrF3cxkEpJCx+yG+k5UUcEnm33Meyg1HH+hMu/Onbdmy+pCjDUq+YxK6oDNaUEHj7F0yC/
XWsJFjzzhz4kXEjkOazqe1PCjF2IrqF4ZN83bCAVwjqcwRdvFQifU+gPBK4NpPl3RnjtdUAyVVK6
8SWN/szlH/05O9vOmD2+hR6ZRERZuwgd+oWG/EHov9sufD2nQ7ENohN5nF8SoXaQbm9CEOwHMiK4
1TanDFbocVwOnWNrbrlR6o+QhYGyYcG5sXcrI4qebFilQL7o6+XBzXxpab5inLS/1Q6SdXFheCTB
B1gUD647fAGVFfwlejWRTDSQCMXcprxvTCXYcT8xlwSUNPn7qTOhuXRivjGlAxmBqo5iUu+sEfFa
avOE5udSuWuS7kQKgx5A2aFPyjhVdGEeFmLBH61+OqdBRDrrtIJHbxLjRvLRP5uizXNWV6cv4SdN
YnmnKFTIakmKTTEY5W8BWL+jNjISdNQn7SIM1xMcgiJ4+zoJWOTtd8qCY8ZoQa8iI5OJM2Z8zIuQ
TWxGA1WCWnysYAZyNdgvylRrSJfqL2hTBtIr31Hj2KwCt+HT/nDE0fxD1AYh+0nxLbChhurPKEBI
M/n3fzwbg5+Ur+UQEv9NUyRCJcRl9d9cQSLy+yIOwTo7I0LGhnXFoB8qYGNHR35nqcKOjBqLLPTr
lKW8SjPtX3/OIX26+GSDYtRMmkHQiWuKnqam+HIGFfaObbhWrNsuFreTRp/AKlUlI3g2pF4jqF6r
EoQoF7owIm/bbbrJ9/V3ZawtlWfMzkRiQlsIKCJk1AL0kyQhWFu9xDYvL6zmSZPBNLolPHPsUsbG
Crba6pXWxVmq+e6LzHWzUWtAfOep1YTM3XHbHUYZLFpIEWohtFUjrf2eLQPbvu31k0FKYJlqMr24
f/F03dBhlUrSBtaJelWWXIZHn0jwPhrfsKEXBbUI3RI7xEEkC8YiHeAxFVSTCnyw7u9+yW5/R1Xu
7YnhNpRMyDe1HOVg8Dpb9tcowJMlvSa9slxQW4gmFZhhH4sEAt205R2xiejywgFucJGpilmAxRU8
7wycBfBwJf3Qnf2EkmsOSDx3rqX0RPcVPOvSjidOzd80cV3CoOoDDAdvKrNqDkXV3yLV9h1M4RO1
03EF4JYPCLtjiY5omB+MEfvzsBf4h2LWWGhpCKvqSygiq3U+un+dEnXXVqh/QzTb4D7RVpT9G5d/
yueVJT3GG5WKdI9RjgwUCagWEaiXdjjNM1+h5jAZ0mtVfh+FoRky9IQxLqxKNFazUXil2wwdSsBg
BEnmoZC7TGFKr90629KpSt5uJy6hNmsGQoYy7Ty09tfMQyH2CXlMJ2QcNCCRTvWcxEgBIARs1+3m
rx9NXefvpR9phCoNxzTevLa+SWE+eilt1cpHRyCiasbySnDOHpG6KU1VQZQhch/NZQ7VaXui31tf
6vLDf6IhCIhU72RSGYrMMFNbOYt+62Y+Pf5y8kt68G3wcwkFvFinQn5SC8rFuoBRemj7JV/cgWnx
kNGOCB4R5MPQp+xA57nQCgotmZJ8Z4Ewz4VL9PSFrJ9GW0C3YoV51e76kD9rfhwKl6vLHJD+RKTh
0xSere6PIQfJe6b+i7rBno4/OIzYfI2FCpXZC6kLHRXlOXlJBpzcTL0U2M3hMRQxzwdgFlCGWVCf
4l+Zk1iDnizvB5NrlV7nmvkoWyw5t04z81fcPtG0gb1dRRjU6bIXeEC+bMXSpRwWBThYnVpJ7UyN
i4vkY3ggsTDWT4DUULWSwzyp9/5UfiwmdkmiAZLbYMnpecW8q3q4DTOBoWxycK4xFZ1EAAMmK/Jp
lHS9VXO/kBr5ntP8OgZdIYi4sOzPtwV7FPOhVF8mg7qeNzTC8POEU/0WpAoua8Yfc7lEDYVR6PsR
XtI/E9KK4OAMbHtVVT7GhaPqrcntXFhRZFRdDsoAXjSMzD4JnXAEfgQUnnexNCrC/GHZCtttLcrC
bJzN8zyYgjtuQGiCiH6Ml3rc9WijQfQC+rUl30r29U7OEGYDTmeKqLF8p+0Lb5L3R6YQaH4+0iJF
aiSAnOBez58lcLg7p9OIiTg9V9HnCeEc2QwEFliPix+IBLRTMnNGDnixi9J/0Cpfo0Uh15eHWC5Z
8Uu24H1yp3VcrjT0Z84Lcbecejv6kzEdKplWdfUFLrPKZUX8QdaKoJC+dE5IwHqpx0cwk23Skj+L
Z4DNYEoMWRAJBLGp/lsEXADTMAGWtNc+fqHQi9XygV/rtqCa9+TsoEpq5aDfUU6cbKjhwCoOmgN9
vRjR3/wfaEcuzRUmC3//Ij7fYeE1Wg9A8uhlk40RJWrWAIyzk/01T4fDrLF3666YIx347Lmgc/OD
ssc4lciCrSg+VUyH2xwEoSmdmvj+Xpqa9q2rNxdb2pS9rfB02gRv69xGZeWstaBdd0sxL0uk9lv1
84NG82nO5kTuKBF67uZigCptWRfvy9l1zqh/yzkLhBIkSXtBl0oTU3jxX8Q8TmFmQCuHUs+3ua86
oZOtbeYJq1mcj+F/73TYZf17yiSjvRMrByGdajqD0wYtyp3Ikqn9UO3Zd/LwsH6XdBS6J8f4hj/d
JzEogZv3alRu3SPh6rKpMZahxiwDpxgrSFcQ0bD2Enmj950cXf3kNWKiyT69fSAxiAe1yScy88uK
M44OFH2DT9n7d3NxBTDcK3U92DG/WWcJv5Z+EqJvfJd3PNWxq+GJLnentyaxpWUxH58FtMTFmyCC
vJcqfl8J0mBvegF3qJDzgNBi9aeQEU7p48h3pH66mUizkIoz6X9v8uwygwU3d8YciaSmDhS1Qu2u
fkf4t7SYS/oG+IKfAJZsNB0IwmeqdxjcAs/2kHX+SW3AzquwonUX4mMKbR8QyPC+DjBuc+hoa99D
/D1t0QJsqYzjLbJv3gmkcb/puwZUNcPiNT4S4Xn9nPA1oZK/79lYG0LpOgC3I+yEGNL8RSxAabA2
D6uJKNJi89FTssTmZq3QQDproEeM2ROS+F/vHauRLQMGEgH/HzbJY7yHTEelziicjiwNwgw+LdOe
wlZLgY4Y3Nofy1zjaCX2XKGPVTmF+yyYQRWJ81MvaZL5Ro4uc6ubeDpjvPytOWI6mDLwX8lPMU1d
hXN6KkyOQ/HT4lZ7VNKiziX6geCiqAnTcF1I5foVblfVTfPnfjb/p+e/C8LTNvdu3uD38+1Uwh3Z
ve+1rp3+6bc6BL/JVCF+IU2G6tzMobqQmSYN1dbn44GSt1TMCpEKRraw+tMfD/rifMRAsHdHotEJ
88omZry/szNEHxNK9CfsU2iKPpd2PTshNC2EyZn9esFK4PqWw1Jr+GQ5lovlSiaMw640VT23YIRj
3BVptSML3+C58QZAQ7WLCFpBjj0y8iyOSsRt0//TDygYvSVu3iKxR9wPCxdFyGtTc6qvgTbGYJIP
p/fQEJQboa/cRKP13kQXauejC7F5IYKqkEXbYYmKXogeqMANyPhLJOzMc0RmDwh/XwXS3R6Pz62s
3EejYtxFnWylz8PB8vYCSdn+v7u6LCIKIsojfHyd2CbvhMMd+pVyZI5AG+3qYMwykywwx8pC2M3V
rewmwOnTfpqxAnjcCO/izfXtfJ/bx5t4r7309IVa/EO10N94D0yXjmGCNxDeL2ELiIISQC61qfv3
/R47icBEf2Djfpz5kYFA4aVe897O5zGjZmnlQiWxpKPTX0P+F1CatrUXsOOZ0eSu33J9C50xYk5g
IAI1y4yloAGyxaCXt4MgR7Oy3dsiYMjkIm3mo0Pzh11v8iiphtUv7R8dFQAMoHea0lR8Qh3Ft5bh
UafgIA9pH6nyWyNTJ/FaRfJ8l7X0cNoYlylaegikxK6IYWCWl0CVFxiXydLztVqlDUK8wKndagm8
/Uc1jbXSI6To5vqUnKE4ftAms/d4AVPn29IgyvAzvx03pliNQ5nSX9ZVxUj18/hBiQSl7fJ+9Y//
oHII0V+aFDJx3eEJnKpOuAS7kw9lNQLt0eGPUzyVq7Q1hAzH50tBTC1rlRtlKaukqJx8d0kUEAuH
jG/wuHzln+psnZZXaAOA17YiY+Pw3e0EZMwssvDaUeHGX7SFk1dNKiqLaTlnpiAp2IGtSLb4M9Sx
bJvLE/jx0F6rojL7OQMaA1LDiAjJLGfwMt78siBSqhGL1Hh9iIOuUul29XCzTbQBLOqYOh4MG/n0
Ma3qdDR2R+rpypl4A0qc/31jJYfmc8rIZdM7x5lMgIbpExXbo4LhZJLL45vL7T4PrxvT0Zzg3VOs
2YXiZNLLZtl+EIGp903XYkUe5pq6Yrp5dRnJ0+IPssqS7+wrrJyoKGILNS+dUm4ERWJWPpl1Q6TC
erJZWUl64R7GgAhwLhoRwacl6HxJO93S2yTkTkc4UPXDD2LUp5/hfmM8yadCp6bQAlq/fm4VI0Al
ifqatMrWXgIgEVbZI99nun3xm5LwFv5JCQ85RBd0TihZVkIxYjZBv//WGcve7pCvTawZTBmvviGA
lJlf43Eadz54Nvaj4/fw04iuzCyNwWmqkKYPCZYocbu6Pu87FHgzORKrfGCV3qyVp6gwe9h2yP+X
3rfgrXNFtRJA9H92ntrl0nf4S2HEAPPtT2uz2zJYSPOgF5dxTz9lkgZuqPmVHIm+GBGVblXtUwb4
89/JM74Hnw0RgwB0JfQk33UdaBKu0zpd2OagMj8VcDYAZruTBPcNE+uvUQAwyq1Qd/Uu6QQx1Vjl
0w8xYfi36EEKSgH+IS04uCw8WXFEXsgOzWP1RO2pb3XsWtUfAwUmVGr6y+/KiHndPW6Wa1c0IjgQ
prTp+Fc2dtamYjLoO22WnmDJ0EnizSD2mQJX1TMCl7a+V5BgFxiPO0ScaJdDd2tCxHYbCAUheSM4
7HI3Hwhs2yrPLNBk1aoCLY2cVdfoR4ifzm/tCrZiZ7PaM9rU8EGeX2f1l6nvt8gJ2cxottHGS6l9
XGZJS5Azq5ZP8b2YGNyPjLS0XWWfI9464ZyM77xB2eQ/q0Go7AevoCrrOdcLbvFik3BnA3miLKtf
Hf9FTBndxiv83jz1Olv+nMxpyTaWqkfJd9TPIsRLcb9e2Sz7F37JDTW3PWS/tf3kyXsnYfeG+PVi
CRfTAJ/x2O+u+O1GlpPLshWCiSeyJdMMeTrmdltfug9KtGVqxuzLFYad6rbYCrl2cEKPivKmw12S
QnCRELmkFU5uhmSQoW6PVdAQxeFa8YD+YeFkzGj0soPV0xAPX2qFJgwKgI5v78WWG88inBFO7Lrr
SJPY76j64wvNEdzHjV5wQGdT6u0x3h0E7LsoWx0ASMUifrVJ2tFWBN14o1NuwBUCxOzNBXvJuf3D
AcijjvM+knRtFaqtXpyZgLZzkuQFlHakmlNTWp5OyuyLL5IVHllTb72SNQpxtmBS1nFS0S+MdvI2
qkkX5TsP5ImZHM3pIIRgd5dFoGOKxOPmUJFwXSDUhwQ8ZZa5Wz1IEP5GziWLWse9bAbCmdpW9Evg
PHX7HtCHxc4YUb8FoV3pPj90TvKV/SrhvaMuNe1GzL0P+Ik8oEIPdCwyLON/Rb4NRoJb1XH8glbz
TmXzJ71DWFJJj/XJKLHt/OTX4go7Zq7HC0VZDoO2mu8nrJZ6kLD2NkMMQ3TUIn+SSztjggEJqElq
nvOUW5xu10hZaReep+6tRcQQq0Afiy/mVBLSN7eWz4C3TIiWtdtTnjr8FJYppMsIC+Wn+2tC7Qvq
pcgb9hIEoD3cQJqIsL1M46afZCotIf8cS18YoUG8NMfjIyQ89DMQParWmSvjzbRWY19Frh9GY4JY
kPdi8arRuLEoCLRZGDs8iCSNxU12V3cA8XjC9e2wAUQfnfHtQkl01HnuH3oMtPI4B46G/ZTXgAwZ
zvBlt8GkpbH8od83fiUVY6Wdnf/wOro2Zl9YH/ib2dCW3YgoyaIApYdcxvIGOJWctVlXQWDWQEe9
rYnYDWI98qiA1TmRWI+vMkqMUDGH53iCZ0Unx9iFl5VnFjOQQ4t0Hid66RdnEstLDZYZmU+S8Evj
9p4a3gVCzfgcsVjIXNmpECVG8W02f2Bz2blFLKpZapp/RoJnEg1LxmxTJsN3MXMxNnYCCo8qKIE+
/kC1UXLYxyMzcxCupkKsnCiD26b8pgX/ZGG435MVqmH58clNRKdT7pVA2Lnf1AUn7KUB4mYwvjen
NUiJ/EvWZPNX3X5FCVmjIrx1bDs1rdhrK3j6aFx07cFDH0F/CAORw38sVtzNCsWc1XTEgOQmEuOs
0ZsV3S7msJePLpSeSStz4MYKshd2VTA+EC4/w8+rR0XFeagRfwUmNX9ZkhwdyIyNPoCLVbcEiku8
uCBJBraqdKtPAb/LYX8OEKMk1ook8cqrAFv6wAOs2KWggON8ymvcoAoiCmFFok+G5byPTZYv6JGt
YTG2N9SC3n/Y0QsF8F5JuNyJ2PTP0kMOdvqE5IhWGNs6o4+I4vxiKvvK/qDKKruDlRc1ec+B0wnm
mb0jJ8uPiP4+4RwNZIJK9eUNjIfMgwn00ib6VfgoL8Kyx8yzfp2GDX0GEK0pAqZyE5yIawzaeNg7
NpVpSMWArQhM/n+iajslqn8BPaainhWXArZY7zAeUzKdd46gnjQbnEw141n6JnPCT2djqz449TyH
ajqxMaPyT6P+S67TctI5nQoPKcuPQNDgNlheQ0UEMBkYx3kilzMZ1BD4aoTkEd0RyFkAsIKKpOF2
Sfdeiy1pU0NIXe6nLJVN8HI6cqyDr6VUe0nlGO7mjFT4BXZyPv/H/yVqCNDqmgFQyMRv8lE8IFJE
ap58xA/ecKONMsen7NhB1Qt1wHj7YJppXnD6CLH3yM0kauQvaHrykNHirD0bnnnkmdWb8TIfdUuX
dsXwFX28J1IV1bQBbu5JQv3WT5EzAZYgkb79jHJFWXFPUxtg3iz4liowaxpFExb6EVxpI5Km5zZA
lFQJD0TMzubbHwUIfKWQKQA2mqEQrZOO4sOEg5sBGJc2udyCaur0E4eh896kl1NK1VBY6L74J82M
pt9smL6pTlOUvmjzmNK1FikGO25Ya5sAbWSUMJ3NiDh3+SZ/DwiELfe9GX5shmWYKq1DnLx4gazL
4SlmNIJPmayJGLuWlQTFNvw0Yc4hYaFUWcQ+3khS6UQKBHFvtnnYEGHLmIkLLZ4ZGMmaf3Zz8twk
FAX3N2np6Fjf+m+y+f5EAGLmtoVEzvc6YEPJU/QzvZvyWkwETIBz+oKve6ZNT6BbZtgW5cG23eSs
+C7zglfmUoYOhvgWIe31P0CbIy2zBap2RN5GzKpg+oCkI28L/KVR97zqunRlgJuVlgNmC0WGigU0
9DUV6Jernq444RDi9eBPzAlofR0vhCDuAT3mVFtRnBQtP5Vsj9DbOpoJTK+0Svzjsq9YPjo04E1N
5XrDU1CUZ3vZZoKj5/n316Nrum3A2f26I2YLabPW8LTpDY8VFZswZw21PGGhrQ9eespfjk7U4JXY
a4jaWm0ZcZM+bIMzS8aNLXjdi/WbNMleN4YZtY0vSS10fuvBVTJC01nwA0AQZmuErlNlCmnIIWYD
5IgsKG8mFSKsS5zv/Ib07rFU2+W8V7zpy5BPx+OiCWTPu1cyu99ER15eupeHTMvSmbCwrDPfh3o4
5D2LiypycKUbWPFacWjbeVOrsPFw440MCUjrwgHuSnFrpJcBSb2TBmLiHUnCbaok5g9/eT13JYyz
4nrmu01EMGFsQmS3joG2Eqdq7tYFljRfRfjWupkhlwDvvSSHV9vBJNBW9E6F/3iwMxnHLieviiS7
MIS0vQobPVFByPLaIa2Uk5I3iMa2SOxaCI3KWztG1fa2+dZtSfy1DXroFVc8ImzBuv6sHk5lOteN
Vjy+7aaCh3FRNS0kVvpwAjZWdzIErLjZv34o21djge4XKCxyo52gHYmtukmtQPGqhB8AKpIaoDXs
nnvxB5agnCHQ6aKe9H9Rp7KpFmojI2+Ovc89ukovYIpjiycG0bOT5RJ0SroMjlZuPQRrxuW2FwKb
P7/2+ZavNCHv1KetQfFz6zf1Z4meo3OMrmY3DgaoNi0YQzeOngch9ZjzkBSCfNzGfngINEXXcWyI
uOTiPaQRzqLpNCUas68ENwMlWopjI9tZR1IU08GriorjqJIBpqlZ1qB/3s7y7Ixl0P4IkelUHb6v
rEs+payDGZe8yxTtEjYn6pp05M4rFfJ8rWYAvJGQibtgBmsJQ1fcZhIZHSWo4cvVUEkGXcMlKnjo
PKQCAq539cLFyIywh+oeagmbAwVddGdeCNTXogRAkIz2/nKHMhR9UUpqxkLTevaMkd2WGMZL/Ffn
8roothMC7GQxa6MYIDQXhm24zmocrp4YpmKbigyn3obWCI3v8pKzKVmbgXTKNpS9IAdh2aKSad+Y
ZMzDH91mDTMRIHwb9OEkVh1+q34kFW88iwAAnnX99EWf8TsCKbUqRQuztcch6m/somsKm4ohY+jy
AB9/rYgiU6tL+cf7/PpHX3U6+e0XY55AwYFekQGxxKfAGM6DuuTGs8Zqx75sDUMetlfnVwOkAjzT
tCWPGR7tyZ7oSAGJ/7vxjBtVSLAdgwIbZAT8rekrxvoSP0J6vnUZscyP/9x2ggQSU2gKwteQYwDY
oedsHa2boFjEN0taImQk7QpZ0zciuWdqF6QPO63fxun9O+VZnIYvbxkE5s5pk2m2GnrfslYCl0WB
nP9Nm6kL9lOYqHt7DKSzADD+5nEa9iGQ2DXU88inqlHKLgUUNY3JckEvRZUYrNEwQ/PckUKX010Q
YmbOPkmL2T+gc0tfxLX1EevkVLiKIx7D8cRq2dDEdl/i8gCMyuNbKEtSz9riSP50vPtqon+3iGw9
CT8CxksMCpku5cWKpc2OX/+5HXPR7OJ5ntmOfxgnh6eFsS+/DvL27mLhXzbiZa//G3F0FhSf2BLo
Hbz+fhooIZIzfC/lcDJnPb9tJHdrOBQlsHj3BgFFzSn8uj6BnHezIySKlhgUY6TQhwslMstdI64t
EonwiUhi23VXj+I5gOWY8RaY53Kolzw2MK8ZivxFUsJwkDIEj80rEMrZAbnenjdz8iQWa2SqP+Y2
ZR97+bho0/CSYHJIOkf5dx1savuFbp7Vpo8lb5zSWy8WoVX40/34ebWTIDJ8zybMtRf63DWpksEN
aJkv0Uqu3UVtP88hynNW1Kl5Z3Smm+sIpEnWEdpGKVnBAKucWlLVNE54g56oHzQeUMpz30dKnbu4
CsA8rv0fg/wSRRfVUzas13wklPS54Bq5AFEZmvYu91hy652rogWUlNo9LEv0QhNaHQGJklYBXNbW
BIZF+Au7AehriFHu9fobFdgWR2xmF6zFD1pYSd0zQTCiJnJElxNuYSFQwjkPIQHC5NNmoh8Vgur6
o8agvv4qYMW0CXhryHFvWfi2JIMwAcyfsUB3/mhbXkntJvp7u6cdZfCK2Xaj0gMiqSLPZzAfTnw0
8mUhG3JKvmKBeSC0CyLeskFp5AzUpCcr+KdyTnIUY3v2EVBQaSQbLG0+8qJZKiwjW3NJ9LMF9vrz
mmupCGSWIZPiLsLlpOWPOTIHyG0keupP4vVpL4O0s1coxn78NqEVIinWx4G68chRe+1PQ5tGfq8Z
nN3zIFkL0UcpkcYGx9p1ODzDgMcRRCpm5+LjkfogIVs/ctnnzSBSvuH6lfNLHj7L7Zfw4a74eZJ+
A8xKUDTzHuoHyXlHZMx+pfVemdobELbrzBoQaoYJkLQ2Cvm99Rr2ek+DF8NlTFL89kSwcRi0T7Hw
+SHvCwmP3Nzv+HJAsAk3jwxKKhJZqCrudcsgOACx57xvWH2PyZ9YeXg6n7VZnolRwTTm5xiwLqt7
pNwwYQJlDHIiFZ8+xVGESMdaW/uALkvy9F9qPGBSzK37lgkweyyr9OC24xoXgSmBk9sB1RLbLO9I
nVlloc2xbApjv24Lj4dZCMw9GL8pyQNnSdYkSwqz4VhpT/V9HHj/EZOWtrBWVbFhCVehy2W4mauX
42qmxN1sZWDOmXns5s9bbTzmLrzT60GfJoRwbmfaVUD6y3s8TJN39wFgPjugdkTSTbMnMVp0VzPy
S4F4xMRApjX8ftpDgvqGLBunXkTdA6R/U0Lp8krYIqN/npWv7AONIhKzkhBAsLZ4T6FlS2YDwhnd
gJllV/aeywD13MguH4hy5OR49LKHGTXt5V30pcHBH48W7BGdBBXVOu5cjOn5xG95yNpqSIvkYu+H
DGkqwcG+Uzr0fkZ4ICp15WrY7ojJBqXPAi71aFCLDKh/4jemKrK+ItcPHViI4yEkCdGklJl/m5Ly
H8U77E5XYt/eFv7y+Lt/myrkI+x3h2vhrTTi0oYKfLiDGwFBuVp8D47mqVgGDjWRyr5hlI6IqTM3
aPrsLSp7pNzI8lITGR2Fg100a4nQ57+MZU+ehlRKwnmG6VZ/Xhnqd7RI0hrqXNgQAl4UnMNo/weN
i4zDaYmXZ8nuVQz0PUymjBTNawskX3QBctZ6TkuqiQw+ZTaZfasKBiMakTf/Y26PKgvOYvRDg/5F
SV8J66wevyIwAd39cI6A0eWUGn6ucVY7yhGf5pQ1mEBgBfh59ot3ZDASKrqoxCP6w0IfVk4wSSUv
hKjZs8yTr2SCH8LvLLQMom8mq+U5fK6aIPLsFwQ0jm9J9GYZ8G8snlks/yglLA83DwglnHLVcXrM
q9rjbLOsIeIgeYPcmJxOyPT14vOuln/quohW8X+AekFTyqfjVuF4TYslhbgTkjjESUMqL5l844jH
PxbF0eIhOI2PjpGidYX0x6H8oOE/hF8HDAxoZmxAhzkz1HB6jqZhSCylghbvssDaAPlKV9qksNpB
3XJhifuiK74OwyDWlwRMakOTt3RzeFRDDtO6yHAGDR7EbXNN+0QkbBnPxj/DbxR8epz5C8Vd+mGB
Sl/OYTbQT5GIwm8o0qq6rhT8+A2bBXI8ARgZrphi5tH/e7AOXO7Ar/3HuVqF9sGjWPkplF/xEQDu
k92gBIDuAeLZr1nFyesF6bVo+Xwm2F9RV/cqFSwTMTMTvQe+S5uF484rD05ajWBysGCeDfqh7pB3
XYoNNoWhxfpb5VpoCO6upoQjr000hb/fznSau/8Rp09DimQao73jRVCu/l61w1ddjQQJ6lUMAwlW
+qLmwWIbgqA1uJPecIbNmNA3JUWs5lq03ENKoavjElTsV1dFlJyite1APmN6dRNYuvf4SUSr7EwI
x1h/gwPJjhJoJepCjD+h1Pirzsg7vg7u9z8FZSui4AZk6t+kmty7w7Oh3lhc/N96GL6XF+2LbCYO
mW1FYWXxor/apWuAIUMrKHJhabtcLgYSBmDEEyl/hXXzbzs1mCVJ2iKG5dKsp6zfQUeaHnM6f2IJ
gRw4hFlbnv5r5d5ecrtD5UIJmF6FAjhwBLBellJmDizhnJBQ5gU2zueDZSriyVgPKKXGtK2MXMvM
nix+1Suk5lv+FibKD6ZuRjDzfehoecHKXgcKw5O3LW2PUOs8vQOYjgWuv0iOHiThVXYugkGo0fvE
xmVL1/zfdh3ntDDYs/RdpkgdygHbQ3Jt7C8Q1TGrvL00sLYSLB9ArNldJvlV4Dlgyv7e09PWZr1U
y9ic86uaJd/sL+slQ7ZIktSRvrZP8t/1qYRZCtq4Xj/xrw0BJIRFLQG5Yr9cTL/WQJWZCUe4cFZ8
pbgthlHof37fb8jI0vh8Qc+hrmQHdeD0p6lLWXqH7ZSYGF5ndwGul0LHlMci14WHMxY7FnJjIa7p
HaC8vwVq0umk68n6fJQ2k+9ZUbM2OFzAxEK2Zm1R/WGELmPBJxqRwe3DFulmvzMME6CPWDck2UlS
pY/AdHHtwHTohpFhGRQPQl83aTWAgkVd7O/xa4KA0b+ZCdkJdGpawAbWi1vCbTRT8LEoevt/NLJC
zT41B1JoJRWZTj53SNn+tMOf9g0MSavd9pA9AhF1eGAebxZbjiZwJYAAN0kA8Rrwol7f/T7KjY9h
h3ml7opL+6qYgUTTCaQcLDi27uaFOk13oWxFnkJ09bnYiWGJRP4ATc1W+SQSYAodLzgmyLG2Il2v
G7t55xG7mJB1Tnj/w3ErE+g4ud3ot78sf4seRY4oMOff9wX+2WGW2/JEfHFGmS4yr9FILBqzxAfg
2+mKsET5eWurXaYPBn4cRk7oRzAtQCgm6FgX/DBag7CYp/CkBdAhauZhBE6qGjW5JCF19q7hcsrF
njSIsqWdgp/JuCvx5k7ecqh1H+wWyDgRcUuUvoiRFYnztg9ruRoJAcOI9x0T/xlXwko6ljMKqKjI
j/I+S8JJzYbh8HylrU0G0FmXmRVY70RAfzFP+Qpb1A3yIRMKacC4UWxL5xIfTzO/D6swDWwYSkd/
ld25yIZs3q1u+hsw1zWUnyRCDiL0b3Lnd9L2VsiLHkTfntJOLleJeR7B8a7ArIKuPtvCfiNV1i3t
pNu6yplRUiBMBBylrNYlZg+GbDFXSo6ctJ1J8aiAJgoUk9uKqj9E5K9jC3T0pQ9KdbVqM2EWO/jz
vYiakEQGeAskQA5K3519QDHeX5wCuKWIhXbozcF24IB7CWVAFI0Hy8EFY2rdQz/NZE3ne0udaGVE
i2p8D/Eix+y3GcrB9WW2b+ikdKLNqNL0yDU6V9FKf8Y91mx2gomrL5QMyqqBg9oIEmMTgAwGbMSI
Shx3XLcCHH2irMhMnr/JCCeavBAECtHs7tlsvX+BzuzrmjyhKx2Z2nurCn7URp6xLufscpIEEzEy
I470HkZ+iJNpn093RDFMzcpUUvwGqvdtsx3EBJaMUtxrSxDLQzXJXJkKbRS4P90KjMW3gQapDJXA
VEkohs4C5vsaTanGWGwAPOGYlsiPKnhOeB7nYXAm3Z4WQaYu/9tBaVdSC9L4g0HOsdvJDi8cJ1i8
ffbG9XhtoIel3fqqIw/RH8jRfVr91+QiL2+xgDsB37x9C8mAcNE/pDqInmCAjPlZG3LtWOC3wRv3
M/VslWHPVMPuM1dFWEotZSviiueOFeGDl98sTn0SHVS31U7se3X0dbNF//ftW7ckNAQ85nsH2Ti9
tlJ99Es9bfrCa9Jy/mMzPjjjNxDiDoLE5xe0Qlm1xtXkYysKYXNCnthw48mnFp1UTXVYbp/38Qks
km9asKgy2qFA4QoD4bUDvT4pXZLmB7HTiACuh70uE9/5JdWvJGXNrrMvF19N4vn7O4LjObt41naU
m6dR+5T8yYbTwM56b0J8vuETFueMIDXpaRDUNDaDCH2cZ/1Hx+2f9N03Zs7xQ+A3NxaDIkQWQA0X
96mM2HIuZci3Md23xpSLoaDVbSYyT2PqrIS3pFBCxUNR/S1iMyktNVjDAsRd+0pJG9dRWbQcdSK2
w+i6VrFITDuxqOshvZieLyLxw/Vvzw2K06gyBdEUD58pjXhdyshVaH4GuOKzTkVsPqqUXk68pLqw
9zw8EPQiDhVa8j5qscPhsc2h7K9HCqutGyz8tZpsvMS3LNg+1F/4Rqfu0sIoitEUtNJjcWXp0Vt1
2gOAz5YtlfI1xWHb0UbGj4a3/bixBSOKKXM2sDOY/4WwU396SiqrqNlXqC4nnBIF04/KzUHP5xQO
EwNZwEnldyOF1M9qJlHemmsZiEfMOg/eaeoQu793XJg4C4gY9jQ1jTAF0mhy8U/H74BqfU4tWb/+
MV99Oxg6N0LyKpVm+OI5H2kQxZkBJ2zdvXeW7kwNMGiBwKPbz4pT9VUzwOWD2eG5+dMkfP4G73CH
reHFPZiImaLJ7ma+BKxj7419jQ1J2ofBs+z8WmvbwV4e64N09v9gIbIGDqWQ05JCHQcMwKYuQQY9
IAajworyPvmeaG1ze0IsONKXavNxB0ZTr12Ggcztfl4ZwHg/VzFeJKnipnqqilPh3RWAw2KZVi6K
Ped44q/J1EO8mf5+AM7cZwBSQ3x6HdlJs9QpdCRx0mVgLUxuV16AdqqEt+LKH3ITx6P++SiTDbU/
/M1uKtOaRR4ZuczX5iuQo98W8viU+VTvtA1O44BjXKaHKUxaq+aMetqPjcdfgYa6wsW9MI4siHtF
HbC4R/N6M+oBq97YStSCSVKVgq5g9a+U+7EZppJX6XBc1G2jSk3pkVPZ3QsqPbjBlkDGmnjj1tXh
AkLTl4T5Smn7SCFEzWeOFE3z7b/ScL93sTdAk9o7l86kRIsnG83OUHhlZKGMZep4Gf5+3Cxpmp+V
xg6YUBgf/KK+I4nJUK/OqiKhEM9FG4GAvOeDLCl8+7r1y0defUspJwadL9rf4RJp1700v+RQXB4i
S6OyB6Ld5jhV5gMPFkgaD9xci1kYd8nZotyxVD8ZIb1TCb9ApvvjBhuX9keqtJE+dSa7DPpfZbmH
ZZ56Tk65FKfTbFvnM0h+P6VS2jmPut1Gh7f+AoRKQClLoZc42YMuQgEXSAYKw9Ac7MwaQunkj7Af
x8OKYnzDH08CmZTkJaHqqe3ofLEHmwRAFVvoqxWbtB8lDTK40NQTU7T2M4EMCFfPe9NNcEK+LB0p
bijkl18NTp2xc9LgxYeJHnc1ibFDt9yn0TYPWxX0a2sGVEfXvTpi+ryBKm/kkr5VZrCbQQS93sCn
7lqCHMPfYxWjpZ7GTuzJsL8BHjzyoX4W17BGpTSeFtJ1+iihHBJmyQ5Swii5C2DXBqWnuelagBVd
Jpe8gomt/1J58Mh5iYtu/7taCYcczZd0eprCzTv8hN4oKrPfk2nIASt6gcvXFr3Krd0EAWjJqV0Z
CtpDO+FYsKyObn6VDG9Z9IbIIyP7uiq6kw4Nu0GYQD0WRhGg7uG+YOy6vc241K1P1dy4Qdn+rZoX
RR76qInszABrY1lQARFxqDWLoGIMUVRPQV+9GtU1tbiMh99/ZHXGlqouRRJ+YhYU0iD04CziwauE
LTmilNXj28XZ2sz72vmqI6816rTISFSIrBIUZuHYEw620cVfnoQd1aIat3zYP3iA89CX36RnZ361
Ic/n9AW9WvB/N8mdCoWu6uDRg53AxaZqjFAa9NYy4JCmoI44T0bSWhvJzvk9QKF3wLWgAgX8ls22
BC6u+iErwF14ky8Ed2s8vgXeQDhN1hpd6VbVChjz7igF8y9WoF1uxJ9XOg9CFTZWyTKKs/3paLk3
f26KUnuSThBjWpgiafN+ligcdGTzM1OgqU5PTRiJrF1hnAMoFY9pSXTx/2ASLRLC419z7SrN1PUk
/TGCP8lujQCX1cNHNPOWFfCkzuCddUVIlfPWUCMaP4HeGgCC93GM309avjmBfDD6dFLNu0UdDaVS
a1pz2c/i3VaM39/ajSSnqwy6QyZhMLfA+qzK9KUfZYiIReuMYTLaZjH+7xqW/nbZU737H+2rmg/6
IB7LWfiW2ggKllFx7wslCtsdu9NHT0r0u8pJRvWa1g8o+ucfRTz31bivHZtEryVihJw6rIYrNFoE
MHa+AaMK4rKc/IzIZClOS1fCkk3aj423w+LY0uB2+2hGEy83SPZw8KHwAAmOx0BE6USbkE7bl9k9
Vzgj2C/PANZR3XRuHo5nOQFhcRsv8+RTExx/WspOu9DWGl3j56+ccFp3ApY8qT6qvnbkqbuIece0
3+86hQLQEO4CQuWiMcRN5+FoaoLYuJreTbG4fa6qBvshe8aNzo0T4r6nKt1UI2nMWDv06sKa6jgr
qqL2RRsE4rJaFB3VS4szeOcPdJUTmjh3YS0yR03rRmiA8meWZrHPPq/w+zXZrcLARuhEKZm7lB8y
aJJxOGmT6X6DhIaDkmqBplADUb+paWSoh61dEpCwbuZWSJuV38nqv6tX4owhRwVOw/OEedNDh5Sc
yNgQm2HfPft5fCDXd1Sd5XAPRLOf31lAHUO5VWqDZ5FxKfbSRM3wOhWlrKY2/av3njW8+OqoQtLh
mv+jTUpt7PavFGkUrdQDOPTaYbEz39QhoMyn9Sxp+S8SriCmIq4bM+Ajb7Dbo7ZRzjwxRgP/IsRH
gVlEB84vtuuLl3rkoPWcu4ysogu+MJtGE6H/rEG1cUz+9OWZ9+0MqP0xhxg3k4H5HZQZ10H75Itf
3wpkIT/IhFZigTND26000ck0E6DvHxhn4DhoaZ9WyNpt59PeSS+xXSGUj+Qk/1IkzC6zViKPvCnL
2f4++Q/3bzYTaLRctP9sHTXAloO2sWoHrCIeSfh4O1u8yaJjLfTG4cZqQ/kcy8AO3saaJQedSaNY
j6Cui6TUXW2xp0DRHaYZB9N5FhNQT6REUaEVYwTVib2ODyMhWPLDKzQ4EQMmf7IYZQ9HqWgZo9uj
rbSOC2PRWQGjEproCG+FDlEJgsBRaWIq+ILS7RPhsOWqIJiWuOtgrh0qFvkp+Bg1uDP6bsJFaApp
vWAYv0LASeEHsPBOeoUjRFx/LZnqOPFiFYLYjUhctgIZbYZrzbu4kAOS8XnzOOiT1S6vJU5qzZy/
aGGPpGYHin6AXwtwW4jM2YNgXNs6hvpQUKs0C8wUacSBOyv58Z+Fl654ohCFxDc9I7eEuYpzZlpT
Qvt3pEDNZykt84R0xmHw8JFOlNo0RwTRcS+rDsstZubWfJDtKVwc0pZt3TA93/C2YuzuvXBH6GW4
o43puI6r1yn78/EWrjSwxnRlSWNesn+Q1jneTEy0V3cd4e+wWCDshehmagq0YDT7vIIuJQKr+MJi
Kjw1exH3dnk1JbOd2nEhGpdg519Ru6SwI2tXnNzL/nhTEoDpRTzjnvMbG3m2wSFFrv+F39RyHjnO
9TU2MRNqtjxHMyZp1LTOxUj44mLvPqcNjfqaXLjGEHiI3jtO9i4ue/ONnYWfEAj6e0rPaM7/JBY2
4tdPH9RdeoWRidCCcPnyylt/A7xD4klzXRO2FdHBeQtWZvxV076iF602UgeVvPKOvT8k9MRfMKaO
fFrefGgy5/c2aUe+R/cfuExxX8/oktks5o9eQ5RDBJkM4sMwGJkrsGdHcBW1/AegwlS8NM325aCL
iHWNrhM+5B8DdQL70yKoPMqgYIcm8St19fIEJgDc19QS7TIxpZuCCy1hbdYI0LRwUW3nihq/sHGr
H7g0u2CUpc0LdLR8y2J17AqvY2KP9shjFw5oZrchL+UrnPA8lLHULa2AyqKC83XMzQvZUjAZoInN
MkKvbu39hqIyx7R4s7xXFC7bw6ScEYM6JOnRf3566aKDuPvAaJXkFrqyPVLTDZaVddQf3Bl95arH
PIsPIEKelJ7U/4iXpGT4SwUI30H2kI30M9d9Wsg679OwrYazxhxqM50BbsN0/GzxW6LckNLSxz54
iMo1J5PaN7hRRa+Q07Lf9GSb6UosrjOMx48ZnvCeuFBtIrpVJs4N+jbz/++WdWKh0mY4RUnRUBvd
p8OX/DSseQuP921b2bMTtAyJyjeAXm91DT8jyjWR1JdnFnIJm5aRD1LAhlPrYBtykmR/etjFgJVo
DSQB4wt1PzC8cHie5E++fvrRddUHAIAjNiLMGo4gTFbgjw03HK6mXQ/txj3r/8fjh7cVNDt0PKrN
17dZ/VoU/0XciQyoJJkcFy9iGkEfpu25LoIxCZe8/567bx/xEF62AOGLsm1QFfJrIF7MWu6tG9oH
+3WGva+n18ig7FVaHjOrmVwZt0Hr+aR4k86fZk0BbRF1ka+pSzQ6lrc/9DnextqasTMENmxJvY4s
tDlQAbT0vnx2Mbn8ZR/oHrwa/e30M0G0R57SQe1Jivi1ZcMrI1OpZp1ZGDksxk7zI2xKGumQRgkY
v5uKqlpAXrXfuLmnI0Eoim7QhXJ5yzZPKU0zGpRbiz7VykA1s9tCgxm1bfw+HodD+ykO7HaPMaIS
1W0099ovfgV1SPrCOURz94J80TnODy2tc9VAqLleH2DUEhq7BmDzCoQnJUzVesrYm3d4A1olwQsq
CooVJBKsCnEWxh3IaReFj2lUxUWIDEyU+MnRS+SzLVwplEVgMlvrban06EPc0gnR+mAweitkgSrz
73RSehwOvSAJ7i9G0AUUKGxw4Qmuj/oqfJkZDEvrpmeq4VFRGBU9zGw79WwnpD+MWcjP9HfpIrls
a7cpCJuVDBazbGJJ9TIkNuxS36a4idSZ6+jcluFK6bGNvD+yJodIIxmabvgjQITMTZvwmSoJlyhY
jlnHok3bTx5TrdX2qikdoD//nAtQklx0fzPyBJUGtydEO/nVLqJ66QRKXsQuQ0nVBzDKaEowB+26
FgcFpBnzCVKNNC7teJlrN+YRkB7fXKb9LfdwA0EylfbWqkklvVt4CzE29wXN2wdKg7aSXZ+WcQEw
vye3K6W5SN6gS+x7kcGAFn52ga/aj/AJVwHbk42fRUHSYdZVpjRTYh6i29g3OFOn4G2Zbs5KKhlU
n0jYZK6a9NsKKVF9X+rBqFw7VYdADzwq6d48MbSSy1lg5WnJPM5DN5k/LiXeBrlXNXgj1D93Ll0r
6Zo2DK08VdVci/NTg/WJ/kRwV5YvQUxekdOLdI7zFMn+eM/aBf1+MY8EIsjKDu5P3S8rwKAF9j3y
Az9a5l6G3GleGKGz263dIlo+dgaQ/7MivFTNOXQefhPDS17hpS9J6YZAJAIyTpIqQhh0e3PRQdcm
W9DiYLW6m2u1Q/6QNyVga0MYXi81OXcfS5USjtXrsE0dfHJLhNWii9I1O1FMz6cpyfmQko4peQEY
FXRY93Q8ZIos/g86oE0pgN/nFRzuGeNp6YkkfKcOUseSUjHQ/K6fsMQuhFHD5gAfaKUyN1IBsE9U
5peMY0dqoXPfNaDYawE9M7S2GUF9IXO1OnI4Ob23oWUplpFLqM5zGwFlRlodpsPnrF+LGJMvCYfy
fZB6f4Q2+N5ohNM08e2CqpvdErX7s7/V7QdxEio2/aO2wmkVyRuaP4JBod7hobaNIrxOVEaWs7CL
ZrxS5V+1AYjkyC4nfhA3zqHDYR/JQNEpfyFlLzIU1Fl68coEUv3Z9mlFYgPYKsf4Cxnbyq1EtmKU
82WJHMn09C8uul6MYjT8KoDt6QIBGUpda5UaIEUpszEvDuMG+fhX+Z1oWUbCJ+PGC/2yw8MPlHBx
5BaV9vmA+zqjOmZkiMIt5eC8th5gsDMKExcsWgWfu+j9POOqvtJ2cX/tCkM7Gv0YHtp89CKV6CC4
SuGmFTerO2lhJ13MYAyy+yAqjuOBc8SIPN368K67byp+8SObAXRZqHl/T8kAK0o3Z3DxSaKP9dGx
tL1MWRhbl6ZqQKeso9ygzzALZmE++k+SZ3FlrQsnNonevMdUkCadJt7c3v70Tn1NZu7eVjC+yWNh
5sa7QJc4587p7DdJz4PRKA2+YmzbuoUfUXjM0xseRIBPiZ1/yixBFVuDuzBWKdv2SUGf3UZ/+69Q
whgwGwUuFxMdLxQ4EHdnnD3Ag1pGIJSYuBFdoH/9h/DY2qk9mCnPA3EpIHl5G2GJtbiu+VA1HQ5o
FbFqCSVBX6sXWESVBkypmhuyiPwQchZKqD5pbCgM23EZa9yDmYME3leS83DGlynf2OecbqQqq02A
A1SbgF8aq81PIBYAb5P1bUjczZiOGWI/F3Hz8OLp+UphCUbCl0BebGPZPhq6/OLp2WlzBs6JmZjf
g1gWPnqbSJhlKoCOUQYkSmcSYNAkEPY/Lk19WgF8+VEe4zopJHRpGC/Qd10s7aR/SXNe/+Miim2c
LztmaIFN89qZl3UlbMeFQEjMl8p1QBo1iYRWPCVtha39SAMwY6rpFFgiO2KhtVBgpYOp3zOVDPlV
sKFvHe6jtw2KhFOvYCSnYrqYi7vqlChi0BrY6uNCu4hxstdmRAKDPsORHi4pREoS5XYDUK79DwlP
I1Y2y50gp7Q+75fw+dtMVxoeda+oycvG2arMB4LnUyGx5TeW4fdhDwWI1485rgXVHKXuAP5L3Wuw
TdpuGztZjG9mjgNn6/peitOMEApPgnm0MWfLSGEXD3NVPA2pFcf2sg7HPg0PeWNkU9vj5rJ+xiLT
ne7pdBbSkG9/+Z+g5L2uAVcdXo46Q1Q904rQU4SZ/S9chz/JyobE4oBJTXlHKsY5LJW+eu9bb+jR
aeoP1tEHz0m65TVK9xJOSFLWu+jn4rvr32lsZFMAVRphRe2XSO6L0vIY92rdpTMRDD3R9iCCZ47+
oCw+94ETGsoG/X+jrm52n2mhocI9mk918YXjzgFoUYJ7Z4+3R4jly7ym7mx/TOcPnt8o7Kv08hj2
FaqXSx+QBqq8947kXVzC2ObqjtyLX7Ss4QYdtX17sYtILSQWBzFXo8Lf1GkuWqcaqhWOM4N3jiq9
Sc0RzxLztFUYrWmeIO3lHW92ACrdPDT1esHB1cTbB0gNQBpLycQSeSATm9uekt05SZ5c6+KlcvMo
gAyVTyu0tdOtSaw509EkkGN77+UsMGid98lUkTOz8NZRolAyHINjd3J333KoBBXw3N2uoOjQgb16
x9cP9gQ/HMPLTyvmcFn8uYVRZ1EjSwuS0lwdQYw0nOXdYk4xchfpH00PbVjlU9MV9ctTse0HW3To
KB5oZdvDmIa/Vu4UhjXQAn5Oz8GIflXd6kilg+brWT041n1bJyk5JCFTvxXiq4mVtxKNJrJV4VXT
PhZrN95ipP9v+AOv4xbjfpXX8XEEc2gcY3IAqpRprCEcY28wZ9Vu7SNAOV//nG2WtaPbT3kCHXNN
oqAKKIQPhT4yV8NMjTA72TzI6Z0IKip9YYsbkWj1DHNysX3AMP+HtKcIBjci0VKE9vwXFnq3fj3U
MJzV96FtOllrztUoqi5kQPkh7s8H/8MA266rfpOy8RPuuJUz8bvS0YsKhpwv5bC8hVlgrpkpKSEI
c5Qp9s9t4zMPx1+W3H1jPVaQyLYMBOzSmR+dFENMNwBXPXbgqtarRnRoeX2etve4hRgK9uh1FjhS
PgCLa63zaenBzSDaX19fjpsDPpSQv6R6n7E8+ywypqinbIN65rymqXV1jnfthUGX/dAALSJBkE9a
NzL98cmWX9LykXx24mUWlr2PbNVHS/JWLAvTDmydhUvBSdE5100Zw5RIFO/vMxysXKFDefjHr70H
eE/ZF5Ln2UB7d6wtN7/icHOG0Y6y6dsYDg6y8mV8XDoqFQjcWVQ8DMcR6kflpN4hCUxtLp9k0PQ5
L0ASeiLz1u2oZi4YTqDPzU6lrK8Jbfuf4JrmvgOsZCwodmHKFgnXL8qWgBJWc3hx8hJ429b/ZHaN
3Zg5/Qr2/g3p3jtdpXeV1P3wSRBiGHO4KVhT+YG4W29ChrqOm61I+tYa3tSXS93ha9jQxzMfzP9u
qXlMTs+i7pprRmfWLcjaq/v2FI7oGDAaMDMYJ4kdibuHDDZqgmByDYEOM7gjaBaPR2NaLqUOtUEc
42K8QcT9nsQFkMjMaUBwTAHc55Kn6d/AdihnDe+AWvnknI22EdNItd5qATgxGSgLl8nWaRdwhYvC
bxqK+XNh2dpnuxtykw/SJumVjkLu7t3t53jEv0MaCG3O37wJU7JoxdpoAtMPltSPVSU/7f1CcegE
loRTmDJwWaBPLz43ZxFq4vS8NHp54+aE0G9fI93DYGXCwBn9k/CS43FQM5ah1qxd2oL7sg/woGFS
yORN6etCfe2n6gXhwqHz0Ld6n7P4SMsOPQkdDBKayxicdNFE9H4TkYrl/VHVBcP8Sp9t8d5llJxV
dNOtnAtANAUZA+/p/2gnHpkidDWnxxoMMGV3M3Ad+qydCUHNgjC30UNeEyOpV4mUbWrWF+wEzF83
5NIEnLrK+2/MwxNd6/1pDWtRqsSTFDtcdeYK+KJSYUK5gU5nw9oYV5v75eCTkJ2W/f7/ezBR1A92
iuRL9qNVVUR5xrpAJYB1HwZ5GNFuDC9HnZ5s3wwNvv4o9kAfZPsPVLoTNdF2jNI/CfnTmiZkJpKd
HAhbd4nq7TVBTApgrJCgKNH9g7P6HNNtifPwk+a7qrLMsYXb66RoNtjGqys6EqfDzuI5WoshPNQ5
ihJ1S3avCSh3ikV2gpGlZfz6JihjbEK1i/p3ULlBWelN/a+NBWrwCgzTOqxrgWYLxrcTSZ2qu+23
Ht/44EEQTzbI3bkWgkE1yvSNkRxNXdzpcaisJzoTAQ4uYwGh2gexUzaFPloRN4rDRzu69+1hcF3E
JcO+FfGmAHgCheWgx+97Q53+hClXE9LZ7VnJ4d5fvYyP7NCL8+Afq7zpQ+cvGasH3iWLiy0MEFc5
TDHcLCqImWmsxtSRexHSMDNXhtqhKUnIpZSq1hhtzPCb10QT7NDdKnJvwZwT+Iox4YDlSS5q28W3
1Ty69vTztY/bT7OLv5X0N5kDiIEtyNgjNkcOK+VjMt1OSQpU/VVG8zNoDNrkCZnPaQy7WV/f9mN0
eje7b+uWQGlTYwGIsiUK76AhKegvWQtdzDi55Ahh0Bgle4h4tWQnCkG4RE/OZ63u84EvehrTL6vw
VTpeoUDMs6Xtpz5GdzutsdjFONGH64GZWfYumzgAdxKh8b0XZAgGnSVHNaceGmMIviUDKme6lUlt
eP4ddZl1H/qnzNHDl6PWXw4A1tWo51A6+pYVrXuvA2Enx6g5D4uL0zvyHjSZ8gJMcJSQ3aU1DQP5
2s2NzKQtcoSAAmkctV/3edXU+vC83bwpCPZJKhUwRk9nVJ4B4SVylPyC/FNH4tJDdDRI62WQJ/iw
DbuP2A3CrjEP0zVW20TLT42Y9+0rS1Qpl+WGkQbCMXKKQJsx9RYuZaEKnlir1OU44B/Qqc8IoCC+
nRNLc8kIrAhDBi/XXqo213TEtez1xgr+Xy10mB2aCZCaSmW5PcDXNTKc8CZ2xtO5fk6qoTdsP0/9
J+fak4G95n4tiEycxz0C99M9XSDk9qP2fvtIlsuXfxR4ODLXyMRSjuBYmIgQ2NIMPAeFkONTs3nw
Px/eO4jaygFiI23mqt1+sY96rcMB97NdUAFPbL++dX2A7TY9zGKqmMQCrWkTJrcN8qiRtbet+R1y
gE86/fIyQhhGRhl77jMqbaB7wYRc3XsBqvJre9D/6AEf4oC9BV5oSswV6k51w1rGTIfijozcVeo4
JeeIN2bdek5hTLOohHFS8v6n7Su1RBoD5PasHIcmTXSiYMsyxKJIvJaJBnz6dmkuP8MWDeGBd3+E
IgEY65q8rk0TRWelO6Xz77l/Dimtz98Q6DhhIkPrsCkfyMCY14SNOX9VPiAcUR9Y+RRXUYCf1Tul
2jSe/T4owZnDiWye8BdcVNUYMAx4IK7LsvZaOSCk+R8FmEbyB+YFmGHgQxDnEYgD2lc1cp9YPQqZ
rKPu2MjaZ9r+z4n39pu4ZTXBevf0OwZ5hB50s+Jcad/7irKQM/ET9ILdLGuZkWv6Ftq/aSJKrWpv
sM+YlfY1tRBZSJ7+3jyErbuB4KsVi7VXJO+nrXXG1rwbzoh96cSO3l72GDoiEdGZ5FkyQkyxZHgW
6sHgQ32jpR2sc3RabyGWZS4JbFubkJ8d3+gyx60h9qMwS1iGOPXbwkDHkgkPFPDjfwWuZAvmq8ox
QEaQms6P2nNZdUHbuao7pw8Bx4qRASANwnK5cYREQx0isFCecwGZFh0lVKKxGaJmMVUfU7BWEi/I
rlmROxi3lbDt6Y7HdXjDHDUWmIsQ6E9LWo/eUf/Q6DhZ+EmOHgAvPJMMsuVv3MRtNqd2va/jDA+o
gRvqSDYnRQGj6etNGCZLcuITHeKfdnC7fC/U86VI534mlcLktbSENUB+Mf+0R2sCeTP8EXfc2YJf
vP+pJpOdql4Q/QrsNtNUgNjewq//LdUv7dk9gS3nv7y9t+GVCk0Y3Q0SmvcFBhDDTyiHbYk4ZEAu
Z7ciDFJlgWGTeNeY43+uc8XLXMSQnZYsSK8pY/edZwbV8W+iFj0D5ShKkbZcEUr2IlBJhCiXYFlT
V7xuYBmL/iR1Ve6qlDcXJiprt0GyeJqnm2T/VC6AUk0f+7ydtqRiBXsz+6WFfJzMyd8hfboy+Kpb
TCCvVerzqnUiLIaowYiM7oozAAbOZFa3A4M32s5JHwfg9enY7yhd6eJgE8p9PYByasssRnHgm9xg
YkMuCd/uX/89iy4aWGvOWLOL8QcO63fGE7js0CrUr+nCTf1sfeV4Floap3XhGiTke65VkM1Svlwl
7npIjv4YmxL83wXJeETyRhKA5HB11ZETtTmq/bvab8ILgTLxAieEp8xG3wiXGFkP5nzmeoJ6oydv
Z+ri6uYy3L019/7QYy+ISkPpYSZObcFuuX5B8vZCpk1tHyaV4yjKN041erpDyZ9ygZsb/gzp71cm
DObgbe43nVbywiWXKJpKM6E7Qd3f7CyWSzfT9CMeXpW+Jak6QirlMtOG1xxgCEV3kGzQ+gc1HXru
czVg6IkVV654EuxRQEclnJph+u9/Lh/XlO4bT1KkspbajntZPugZs+hhnwmhDAtigG62tbUJs9S7
yiHmLJ5eM1ASgOH0ImKSPa1O12TMU4Vj7zem3vMfCBPAumMHddgJhZUSmb5Vam7GzyClRhmXonDB
aaAqS6PdCUMwo/rFlOVfQljl7i334zPCYz5cIhLOolnYfrl9BvdHEZPW5yGGgAzNgFlQOg792RMs
aU+5mQhGHiLU8FhzT1zFEJH40KEwABdKJr/8L0jbNwxiRKfD2xf88SKTeZOiNc4DOMAyuB+8yf0O
WNzhqrUMgP+ALcTVXvS8EAWF450l86aWvKaqwVbmTAL7rhmjsLm3IH46hUZ3/HP9diJpJB4yEYV3
3caPJBA0rpkbgZgb4+ioCu9L1c9+fEayoxH3rKQflOJHHUhThviR+6vE8fxjrLONXHCtwtdnPaNq
ym9c2Cz3A29oTJ1jSaDgwmnwSzjJgp/H48kXPm2xIgesmoP8ZjL/xJayNXxD4Hs4Ykx+nl8bVt+K
KdQrdkd3h0mHjx5K/SvkBylQeP7d9BKTj7UnXoMeOKMjTrzkrVQG2DXQBu/O0CjTVLi0WRRUcv6p
lxVh2diz8IJg8wtyLiGXawzbwmUjfp5Pcy/SAOHq+7Cdv+mRRa28cbXxM1p+Cncb9lIDYBI0ET8B
RWGSOIaArBt/DALGFoonDl/P/mHQKBJjftJ7AF73EsHv+/DDEBh9yG4mBD6w2dZe3GBSuKOtaCbH
l6sqFvRUgy2WjDK+etYqhgnvkVUAY3P2cm7BHMpltMSmpWOU5o40mI0yQ1yClq/KQBhr4D2GXlXX
ZKu76r+PFcVT2+S1Rq3PxtGMIkkvVKoxP7/akegJjBhrGCwxErUD983Q9pZQPe9/GtKtDQfVl1no
j2PF4KXBkqPHI7jFpQEtmfWwF/X2rUuOmyaMT5A/GfDA5kzPv8OQ0zUZYBy6WHka0GQLGx3gzNDD
hLBdKjRb/dfifIla4zdAWWwmTcltXaEY61a4gUlM8Y7qe0nLGfp49nP6KBCJarlPA6rFoy3Tosvf
bi36Gd0yo9dT0JewuWPJ1OdZchoarYNV967anGs3+xrYaqZxb+a6euVT4iBw7AKxRH+Bc3Guh6Fr
7bdbEoGVlzmoVgms1nktMmSbEw9ioHhqoIV13puwZY+rJ72PW2pHiz4gFy/6C8jI8oyOjtbDJjUt
IRornPeC8PtN9itu/ooYFD7I5PEmGg5cGGQizScZZ1x0qWcKA4UNwo/okYWCApHHjwnXEP+nGY8X
rNPa8jXJyc9xzd1Ha8N46+yalaTVR3a7TrggXhe1gUz8MYIN4lOjOUj1+qmS2kZ5uC3pRhKXV+L7
hkqVmlaDfihkUT+C4StXUP9jCqmdd16sPg896qHricRaS/QXBa39PpT6C26kZ1vGDYrJBob2peEm
G5S8l3+XUAMM9yk33/7Cq/BvgjR1OEAq4ve+SHehGTMJRQRvZqQ7+Pxg5eEg+6t4tJ+XpvsHSwk+
VBLUHk4q8XADEM9+hGB9htUw4itEnN1wrwYwdJLvkpucuAf9fDQVqJMMAvsZaTQqxsBf+ywEZ5X7
o5c1GJ+USK8Z7wIZAScM4NEzS16n/yahWrSkKNU0Z4Wbj2GndewxmZwfE5TUYlUvYgFhdDbkmr5g
LOZSlyD5eYLA6eKYsFmfxhx7FEgS7ZKRwxLf+AK4iGTiMXoeZM/272jKdTY+L7rqFqIIje5RB7xo
pSGdR3dpNsLujjzbJ6qG8x+xm7ah2vyFyotJrGYUmQ4DX2ov1Mt4fz4fuo03Hi2BnSpGfkfzeNz7
uAU71J+QjnRt32xsTzDsaI8GQY5SpkjCCzBjzyAcfKPCdnAILcX5pw5M2xvewiTj4AasSrHcBNdU
d6E7eziygfRiL+hjY5TkB49c22/LpuHZbegPtp1/Fz70nX6mS3uH5aGH3LRv5KTL2XuKHb9Tpasd
dlCU23wqXaZNZuCnv4yn5ybLlMnj/rx6MdlFMeOUyQ5dwMdRLcfKzBwlNuWBPFfqvibyESclySoK
mDtXZi01Nbk4aeezthTjNecCLwRGHSNfT9BDqM99YfurSCoWQt4TBf2OQ3qNNXaDsS/adKMbAR/A
mHDy6Ay/ucK8dw8suLgnLJSM6/ICEc8/ThcvQDAy5EKmhb5fdKdlqTY8OCGp6aum5XHsIXZwK47y
VBuKo5NPRnGS4s7aXgJonKZ3jXU48G4iUwAM7WcOqRTAaUorzgJV50uuzkmlbgO67jQHWUI65JP6
KFO6AGKw/w/5R0a29RrDy5jB5gLZMsIobzWQ8Trl/tZP07M8Pa0nP0/7+4eFe9Ilq5kOi5olF80S
E7s8Cmkd5J2rC/SQZ2x9XXPTm9ExikBLtMiUJam1a5BtsVJrvwPIHid6c7KwyENP94olLVNGaWD8
BaKm3el3FA0zm/1pOCvHE3Y7XPto/UlcrMRmO1aEUzqMTRaiD4dkKKqVEkL2GKiKwO3+DOAnPhse
xESpU+Apy+b0pgCmEnBK1tjBCsc9rz4YpdMWj0IP/U7Tky7HR8F8yEKvn89W1yr5AECSDVm7pshk
+a19r+D0sEjG6TpYtFcY2A6WTOeaQJy19WSPc0wukngLwHfWyts/jKgPEpmtdr+vXBdsagC+wTJa
u2b6MkykS6Cuej18xmx8Im52sBvyrXwjvu+8Ok3ajbPWgF00g/8zDgkQeRFKEs/88zcPgPYwFvKb
77PhM0NQ8+N2COZNaIjK+YNdUZ3x6V82ozqRuQNfKwUEY5XrLAvkSFODlLq+z1wYyGlCq++xAuVp
6lADEa58CFgD5Le8fh6tOzvVKaD3fHMNRTCK7s81K44n8nvVIfR8xjqqHeP5NALfz61CEvYOBIOC
wk9Od0xjfqgbP+WvIyw5BcbxiX1iVHm1k820R3XQPkmDddpqH+AvBIVWKDzKCsePINv556Y3J2as
Sy+E3O0EO2dEkGhyKojcV8kelmts8p/CZvngOiW/S/HGGgjsjs51Aexc8kWLZK/h3RyfYVEfp1vv
vu6EASpWKXWCyRG5/0CgzfxoEi1U3PA8k21dgNS9QQOfTqBMaYFRi7oMX91XbvZeRIZFjGEVxaAw
UqDg0r32LeZMrbdQGK8SpijMtnsDNdRg7mG4+Dzgm18DNlCgqDelhdOKRf5XwrNg4TFLQNytpmVt
Wm/h5P96wuHUTocq0Fju1MMpSP6m9hz6m09rTaOGorxLaisGHajSUmZIo1PKaTBcRCiyuZcvoi39
0FuTE+gAYmWPusw6RV6osr9B7etns9HB/3QORocep2PU6MIUXxG0DHkeR7PQZq56tU/wFTN+G7+n
6ZUJxm4wHVrRkZrCUR+5pTptI3KAjxSZYOPybHQ4tR/uIPCzyIYEEv36K2rs6Vn4Whg7oGs/anaA
gFMqxbdizRhbWq/VftS0laCs4B4PujLBrNXBsmCs9Fh4ZPZFBFhovoxV2GA9VoGn6xD+rBJXi3ps
TGt3Ye+21risnE7xyHde9bpkn2kmHAL4oHgErJb17ywxnmyHvSYkR56DHWlFCQmNxkv4ETp0HE4x
yQog8SWDwUX7Or5hXbJq+Itu5t2Wfj5XFPo/UxORuO8TQ1kGSNs5pClpwOPpf8QfOvr1VYZxU0kj
JuLlkwQeXQ8RPYG8E6HibO9BcEqy2UvfEJmRFNg2VKYoc8VUB2ak8/BFWbKYO35WkW3SqXMye/R2
jvf7oMIMnZRuiYNSInV72r/aNfrPhzq0587ufs7BBSw3psz/6/tC3qEYh48HXYQvwFv3NG23DTkW
kbVKYg0Bj/WfpV+RZ+U9KtJdptrZWurwiVVc3wkNfo85j7+wPD5+88L1cTf+B4eB7AZnJFCCSIpQ
5HFVK97AnjHsG8/v2Jcs4mkFEQG9N8momOogPVcR/54bo0lXmMhLdC5WSDKbjtRGGf+SRxAGgLj5
hwiRJd5FxHUozgv4Jlm3Zka+eHaivpRYKPj9A46uMoBOAL3UHwc4vugjy7fHC1r37bOhhfIKWw3z
cmXgc0Dm611lENrEftmVYohBElGUttlH0FLujduYtg5+mds734ahIMnQUgqikpTMFaZWmTcTC/lg
iUrDFGcxGKDhnT6Ex4ONiLVxvb2j8+Olrd1iFDlTAs3PrLXUvbCMR7PgsDFDQJgcV5TD/XiOyQyl
YGSaPAcbFkalT1G5qgNxnwJbDXp3w/V60vF105LMb1tF7yxwlq6dk6qLrj1oKxHFdWx4aElDKDgG
QC17cHnwLZ1kAhSMNY5eYmQux3vx8aRfSRGId8AN6nOAiizcSXgSsWr9iiTcns45jXHIk0z7FHb2
hKl302VApT11wbBhrYWRvYVuu6r7gywnwvKIWx84MlOK2tliIdStTf3ZAOeZdEHJO9FhYQhtoUQb
/GBMbhWbGQlbfV8Q+56F2705mf++is2bfPgvz/FHUNsvNZpy/3iilOYoZgaaUwL0WDvwNRQxCLET
pHJRQTfkHXUZH7YsZL9/O22p3kPLLUT6zEWg2J/oFFysAwHzkmc2XfJyi3uWqaHfY/04SW7PrLCG
VizAoDsketh8VWQDYSOWQC8PCnBreraTD0c6EQlIb2QKFQ/FQ6eDSh3qcPTG4Z1eSoMd9c7paGzM
O9lBilGw02Nx9x0NjMWWRjWjatFA5dSe9qk9eB5xJ529hmXSPOqAX0BbMedACg7Epr+GbcnzNYHy
BVd8/V95rXaPsK9jD5fjGyltXlaRiKRRCzZhq6IfACiaH3lCI7Gd/14yLcLVYljlLot+VqasXnc8
y4LukvpIK/GVgTzKtLqMBb+FsRVnn1eIY1c23l8V1MBEE4I1mSUs1nIGHYJc6I0TvUtLtOQMnakQ
LkXbuWEhnVb7xRMGtZ4kR+PvUmAxda+sCwbaefUY9RFfFKcTaETRtdLEmdK4NBPWNrNgaXtAwsJP
NLBdjBSnsPlXg/394WGbwE5W9WqXwmGGOymrFOP0CpOy3dmWeZWSzpoRw2RYBr1eJH0uauWu5vVc
LIvAjpeAGToyvyiP1WYrElb56iiy16UkYvspwjEezbd5l5u2xM5wOGBKGrt3A7//9m+kWk8lLkpz
T+vHMtZDm8A6WylJnDIWOrIzqwC+wrd6YVovHx8fbknUQdFAJ1789nMuPdxtZAdO7oxvbzVM8glE
kUFxyYO7/AK3elVCxy+G35nikL7G2f4jq5MS9o7lsI2q1vuxDOhdIN6iEv5BLAkc7GKKOIGblBL1
9eFG6/cmtTf1oLDJSBqV2yAM1BeB60UxtGUA75nMNgyNbGTB0iM9zJoArKVOQGRMvA69nhGAHSLw
5fzcWXG5A7iyJHTyHjWJuG5r0jbIvgRaFWJx+Q4=
`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/builtin/clk_x_pntrs_builtin.vhd | 19 | 43418 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
rMj+x3ocDbJ+0HvlMPtFLLYN4V3iOWmu0i3VYcvwPU8r9dUqilqv5BoOperD1z/j12cu4ait0bNC
TvgieQY6qg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
LiFkBwHJvbvIRsrs7TuS9x+hbpgzWqPRKAN+86jD7W/DWOy2HiTI+Pr3kejl0F7PQ/wd2Tf3u0hB
l5PFI7Uciy5uXiQA7fDmYLdPcNoMNQWm9hohp6Q8wB4H3kSwMFgjlrwYcv97jBF9K/DD+f6kjMEJ
pjxxREwM6oJfyPhyhBI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mlNr/JQ7BAznEw9Lq2hOb9T0FUxDG5TxOJH6VJoPGS12EjdrVMK5Jwy/CrH7dSOtWY2eUHhpsxFO
HZJnPHkoY6pnOp56kFqNAyiHJP+z5BexlWOYCHMzTTDXl5ecpknkEs/jFqX2DjV6R1MuxPdeXOjM
JpDfpA+rd8xFCgAvhOcvKEKjw2lJmNukB/NqmGdLZU9Yd/iDC6mJcVuTrR2gzFDMoFjQUitH7TCG
r1krtYbVQjkm691WyHmxufh/qSc3KdzrpZqycBevqxjmEqCq0nMXCiMyQRHMFNk9XLymhnx09LIk
8Ck9EeU7sTUKIMhZ7oB9NRbr0Jmue7w3V7zoXw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jcrZIuGwyVPSe4eEqA3CjxEN8wKBf64m71qLvmqrllZ8mLFeyFjj3f796U4fol5LeUOSCUITklpk
5B0LZiT34IugfACCFG6eSa/KnYkpqdaiyFEJag2zBthAbQTJIoKzv4hrVDSwoJffRhWS6ZAZmMOH
9HJ1Z4KODhrBj2PMMOQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
He/hsXsp9htM4v1ezeHFxTi8NbCInK4GRCTZh00v46syUmSwf+mXhIjhLm4sHKCSUqmWt1TLUp0m
CWcpoGxiawBF6wEpl5GgUNyVTq+T/CrlV9Oykyiw8ESh1/7hqCFXSES7D6yS14KOyEm1cr2UmC+u
X/NTzDDvOd9e5R6zaiks/z3Qdqxiq6f6jnMuQiSiMBsAMCHxpq5kEezVTATURKXvDebBjGkSTomU
Wve9JRKQPSiMHuUURnaiqzi8t62PeJzIwk64jI0DQYpuyHeGDNIZt8qQokGYPimAYp9IilmsSuGG
FM6CnM5XioVenoNWDUkk1F8M0K5I/5eHgYEnkw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
`protect data_block
sy6Ib3lMvpwhxxPC+M7rwVnxAGXLfvjhwSbL9qwbP13a47pbcyAYAtiBiXbPyjK/tyIySUtf7vSa
/27KkY7mREwqrFv3FGqB88Gpqs7JFiB/I8qWsXo8R/PJNcQqQiygxZGy2G++1VltjcmVUFKc+iUv
lEZHWhwQRBs7d/5w140Her/1aydzCPG8TA3vwh4kFyhOSY/8Z2DD4Rp2CHXxckzDJfuNUp6HVuBa
A8AbDVOTOsxchTyOQRSiZmdfzqybZrGXTHJC4zYovBp3tl0VutkvVyeIF94iJ6T7abwwNkAcl8/2
RoGwAux0t5btLYN2qnqAIFKIMZRXAlZcJjaKHVglcoNCk+N+phnff6qAFFxQlMyVf17URMYPZyyM
lsRoXvydSzn7hdhaW2OvlP5l+jygneHTXx7VvZbnVHnuSyfOdAZcb90R5h7c5lGYCrzU/EHIsZPo
KX6vKCQs2vBRPiGPuvdaFTKZfLzDYpphdzPxb5tHgWA2St9MQ1mD+4aNCsnc7DoZTrM+19MPdck8
43fEcZIxkuuhCyOHtkkj6983PrOJoBxOD9YUDq0ui9lDSW+JsGxgSx2UeCcMABONkikLU8s0Xb84
DyPWiL9LWOUkr+LEQ74ZUdR56X5KSkwMbWnGcJ8AXnUJ3mXVOcemsJ9IN80r7BPF0GcCAzCgxV92
0Xpz3EhgZ/LnXHsLiuYyL3kqTxWZnKZ52HTMlp2BdLUipDlGVMpWCPWskUEN6+FOBAtecdyKhL95
1DYrnqpMd6EDi2HTpRq4ce04Sb6VqB9zEHNfSYkAt+DAqXPf0Joa0yogWUGUkgT4hhWaqwDhJNuA
OAnDBvsR4zSzeGn7p7Ir7cLQWrvQ325DbnG9iaHDiWnTdCOsmyDb7iYiV+3D8sQARCTsUeCev/+T
tgZjvYaOqGyCeWptTqX23MBZgLJaccitbRZkv99YdqPqutvlF7hHIiSaEmaqKGewVZC2AfYEsuk0
EWi84lVcjFIWJjilHZ1qY4CzJC8TBMLdqltV6HRa5DgHTWxx/ywZoIIlZrTWDn0EiGtfYmLU4vSO
e3NBJi8dsMTgmxgZxQ4QGlxrtzTeBadmAcXtt+q1Cpbq53p6kJL177TdFuLBBxgzdr9vqNR3ofum
6aZTHsIr/hY3zyHnFTU8KvBSOZHe0YxYEscT5GyTJphX8CdPctwdL9cJoWrsW3IioqCbdFrBgHQX
ghyg4RlalRtSWpH2m8iYMJD26+Yj2bLKRVYYURBVpvW0gIMsF/W6uQTbGs7znaiBlG/psMy5PjXB
EFO/XKUJ1aJRp6DnlPNL4JXqTur/mBFpa1Q3C6qwZ6mUJlII+gHNz+BlElm9KKil06oqrjZ557U2
uSfiFPB+1DMsw9I5aiVWub7CwrNCJ1GjQf2l4rhXQQk8W4PSBSU1aWps/DkoDpmxuPBxnZGzTAYM
5rRlMUJlCHeu06M5hdABQrfJis+JZvTja7DLwEyDM22foDCHGslsbTD5P79n9QqaVPTPCxQAGXap
zcHImTHEmIqNIqjhtKQdz5jsf1fzj7V3O+C6dR6l5339uy62krkKoaWxMSe23NxjpZvyIN+ZXslu
Ut14jDmDnB1yt3oDNqxw9/1jsvlGaksPQb7KAe6Y1YmdqSF6T0qUuPjTDi0bL52deji5/E6aJM97
Fj5uFMDNdmRJPA/ZClQWCKUMyU21SJE4j7LzFGHu7H5KzL0Klmi0E90Uibe7D7RG4P6UX4Tzsht7
xuAChliQpGZmPqyQI6BtpDB4Im7RIZgAP3z2oEek2SgtYwvF/4yl5a8i3D77NXZkI6fjgP4uPurU
/1++eUdayhI++MU3Cs3jF5gtst+L6y44uBT+qsMWSseXP+Wa+MLilquYht61QvheoYHhJv1QdZa3
sLdkoaL+OkAzrZt71vcfFA553xyKzTiIVVmmLlNHitWxPtIyiIM/1Y8pIhU8h4L+3r+27TSsnd0e
+UTacvz7WQBFcQwdzcm8s0Oburt58IZStDB6rNgarrFDJcYEyZ9xA4qZxzKD4yLVp0StKWMUY/LD
G/AHB+POEF5eF4WZKpyIk4b4Tzz64Z9Gpe2jaYnAIINYYi2m6tseXK44vBpznGEHAIR+/Of/l2Lq
il5B+JDVCKUhcERW5MzBo8TIZGu5ENuB7t9rbVwzst3dJN0xO21qSKRMFUyscisEFjeJDCTgV629
ZJxXsqJlmIKjw7EqP6sIbfynCO+4ImGHUDCKLVxg44of/QWZilEBY7OmGvTL3g6TIXHhgD72EMsk
0lA6//OcqHe3qVHoO5wnDhvw/ZywoJlI89+QyB+7RkB37M9Q67jr3ibcnLnsuNdDelqtB00t2Fi1
7g/3kblRjJIIJ8vMB4jj7cgbHwd0UhXOXBDw3u/TPk7sLX/A39YnhJpm9JAqcUJhdGeMhbJOjvAt
Edqg2bqLGxZBp5+qUk5KU1iwtvmrP5kehhI4XrnEEii2js5cqHTgRe7Sno8M4kvqekREvmIHzBAS
26cKGInnC7dcz8a9CENHJfq9r88vU2dRA9wK2q/dyoqzVi4rAor3DRzjb5LEOB2LglTiKspORVxf
HxK0Nc46GAiMJv35OXEifO88atf+L3QWpzkV/pDO3WTorGYdky8L7AaTuVvQ7q4zI3lhYk1hb19i
UucW5ILLIjlu21XtENc5+3YyAJnyHoG9/xGR2tiRI8u/CQtRS6Z1VjjTDVk85vg+owAdIAHjQ7Pd
NknKZPI6FKyxuamDrp9YmORb7HLI+i2oQuID8J0BDF7PLaAH5eYnK7O7F0jlDf1Ilvmw7gZXgokA
xCqQC3syydnwj7a6kFjKsg0QIy0LHmKXr5tc/ZTIurS1V9gHbTA7vuyx6L+nqEro8tNwPt+fPQ/T
SUwiARxvHXug1GEC8Of4oVY6m3w5Aefw3lp+J+v0K8p9loam/VkNm2flwYEjeSdy3WmImJUOeJ9I
4RLLSsWU9D5ZS6tKzIB8dmUZJpLOywPg/OzsBcLslVqb5FDqbpfcpE84UFPTAG9mP5kHnYDbVrXG
9TQ/fADpzBkZs9WCCWJMLXumLGFUQLnRuIUWG9sNxfd/SfZM11xMR7Nniq4ntyZat3uNTdSYFtbc
i2DvhkTD1l1jd+rjtAmgjyBqjja0zicn8321AOAymmybJi/6NQoZm4fWaSAGuBXUllmzaU2cP0HE
gGxLsntOJFvcMvQ6+9TwDahgCPabd5ajG4Zi1IsdsnaxWk0AgYlXP+QcDmQxEfb2I9O9IYjcMPLy
omff7OM8NIGL4xMUB5xEvmleb0+/LiMyOj/9FOn23+SXg6O5hzvNubqzOe2NceyMINfXxEzRXKBK
tVPanMg4T2J6bmy87lAekg+2H+nK/Cha2G6wZrIH3UlUPp+TRINnPTzUA1eF0qHpnA+KPSKMoPt/
zKE1Ogi74WYuetRLygCKLUbzWLhBoYNAMqN749NoeGNmlZ79DazehTbTfso5cegb+g6VXNJ888D2
+ZWQixeGRcam1Hwq0ZLdHNBpt+hOpTTzvX7kXi/X1QAsH7wN055lPpzZZ54ekcrcG9sbGTNvBAJs
GrJj5hORkhoNlnAy2TRThQfThUsIp39hC6tS8harbAt2mpjUex7m3nsllJocx/Yv3f6/E7kka/Z/
kLzYEmarDIHB3O+elMzn06xJTmkLE6MA0B0EFtvGVEG5oxIx0cOr2F6Umz8NV0atXTHprXlt/RL8
VvnJXDIrWxlsRqQoKlG9Q5udhmIvaa4TJlE/pj4/EA0qpf/esyRGAdcsUdGfdbja7vRHXE7oBWEm
3VB7xRrrCYSAj5nXjJbS45Ll13tr9Y9bn3EnPOXqciBgsrsbx0gDl8Nouw6eOWlRhUpnvI5BeRSZ
y7zsy0RYvkqa817nrjBsiUE4vmScNFuGbPqX6QjnXYFIDceJ5JpBf+rOkPo1ROPALqOIZI/dDOw2
g395I/e6mYLxkvWp5R8HuNtVKvn7el53h1XNXTSEUxcqzZy+SOOOYWpvQY2cUmQi4n+uN+OhTwGS
HIZcedAQwHJ9CGJaaDsyx9zo71gvE4YiTFi3+dHxjkWqzSM54N5Xh9fpzjaMcVZG59Qut+pVo1X6
V1BYdWKWKRSSL3kAbvWL7K8FIfbg0icRq/j6SghFslwQ2L32ZcjbZqWeYMix3TPFPqxB7OozI0Z+
DvEbgxswd31hUyw9PG0bI4g9PokckHUa2GcFkraG+aD5HuHJ6y1Tv7EFvPieFGjNPPVq3sFrzdfZ
cTkg7H4kMUaFF4dJ2QtuR942wnsU+QiMA4TCf8NDLO23frbtmBVohZW8vXUW05lmHjUlV3E4+wLN
6Yz/e4rV/fzp7Phv2UCF3eFN1ONxCIwiiirMp1ZR8huD28R4AFqUFH40KAH6zRqgnlaXANGJB6jE
o3D1+1c3vJMAU84tOi92pGuILR30E/a7ACIsn5VBkClyIqaBFofE6VTGpCfgDI8azDT/FgwMs4Mx
9xHh5lAFEYAwJb+QDKh636mpigmAPgxy5UR148wSw4uNXq7NAM5ltddE8qbgbgp/4dDuqjdiVIUw
Aot14HgrcMvSO7ho6IxPfUVVlLZ9aoNzeE7PjTZMHC9cHm1cJQYcMyrF5KDmby0Pd/lIC3DcCnHE
xKMFiiOMV+Tn0tcg886cpfB/NHk3jHPzE6zkzjowAzgYLAp4y2w11ahGRgk/a6Q+nlxlNtKSyAUd
1bx07c7FBJWd2PwVW5f1ZBINoJYmxRctZT8zN0Gp5CuDi5VKi0D44hOMeVN8paKrn2K8wuyRL8Kw
f602wXoZFxOZdgrdt3G1O2C5+MmEOxKpT9mdpTFPMQ6H2AJViH1JrMmAShjTLQ/4CKdCNagFkUXl
SRHwEt2G/szL4I3ewwXz2qbdp090YUajjpCex814fGPCTaVBYxxfxAjEkfi1R+1ZplCl7eT9jA0r
ZymIyty2wtVXXLz5tJatCmhgsfXuzH/ZTLwbaBZfsmYoIgJJapVUvHP+37IXef+7JrAWgt4w7lFO
0rkSDA5lpF7W/lWhTZkWPeHguuRIom6C0u+Lxf5HMiWegkpgLh6HW/Jx5VgeEi1WDr8kznGzh9WA
wEZzSIpOYBfW8dYvptNqFlA8PMZYljIJB4O8q0EyuBYk7yNWeL66QOde87O7XZ9wdRqvEoai5MLY
QyyFm3sOOQZ6/eFA5+dcf9ssE3q0rCc4AyFlF/hZ/tURIYawzf4EK5Qrj4djen09O8kXTZZ45efq
4kMcPhNcGhmYT3p1kaPWN4ddNtaB67emAeFpJf2D0hS3BUl4SEyTWlLpZ6e5AQWQiAluUQoVnR8u
wPfhC/8ryvtmpbt5WRj/ghxCL2pn1IWOVm9CzORkuTGEqYvG6hZ47zauSy3jHnl5q7Q/sscbDEmG
prhJh6n/7+nrFN9SnKz6LH/6UY8/TQgT5kWXxfiXma4BVEQF+uZhY2G95AZpLj0duWNUuW/Ywsgn
F3xPqbIRftXR7KKsJ7RHZhoDC5OETkJQCoa/L7AU/rol8tIjQKsqZXU+Nvq8C9Qxlf6zlgy0zWX7
DmqSQaqB4gMe0An982JRbUsnMwBp1WGcc2ZeIq2CEXv8cldJiSEBNx+1ZmfKzv9f85CviowFjg1s
JAsj052jpldU7BLxZPIa6FxMemzY0ZihS4ey3EleQsykHrVtp7TMWZ2z5tFbSiD6Fiwi7+8jRmD7
reSeTdhkkeCF87WfYmJdiP0fPEqoLZM73P+7cnyyBL3uec7NxXafbO+7dyqTJGfJjJuU2FJai9Rv
sdLduKyKnXodEMjJtdnd7izH+6l4+rzrWbbFUwH0abHALItnH4KhCBT1KQseNpaZAD1RoPPbtEWe
gxuOiC6jumzQTsFz2lOWWrq+l9n59illnJz3VDNz9WSAMSZiV398YN88Jfn6aV1T7Y5byEKH0uj8
iCMzjisfo7f1dLTENFBypMw0QLk4MlmcM6HWQc7ZPJWoCaddDUGGwDvl3hf1Gpqb3Mm/XuNVoyEw
p9dwH0eB30btFPEHhen27wXeOk95NLoxAX3Wc+utV2pIQTouzQF5NQUyLhZxSWitpgKN+DHHRrFN
H1/+BR6m9hIoDG3M8lbJgoJDlA72unYriKCeZ17bF9vfx2S55obGSkWAAEhBYtYTWjj1y9ymq98N
iymTmFrGocO3OmBE8a8f5wwiNLHzcXkTdjA5uFn72bKNJ6tfN1kemoK+YdAWbtk+z9ZRIdHS4N/L
MPHOvJslTrhG+8jJF2WYixeCxkMsEkDL1AZxNz+7TFHCRGecpCJag+7x1sd8jpVjX9v6p0LgXha8
qqZ4iaBMPArP6vvWkbklqsCtfX8P1FTibL5px8onMf8IDh6gU9X+vMs4ftF8EH5BoWU7C+g8mtLe
+YH1OO5XXIKDH/mWJ4Fg9qgI352gEwl1h0CALeScLKoWmCJmTiCQrmzxZQ7KrHPfYYintopwskJT
NovXXzxAsCemea5N4FzDWIL2PT0KrU1j+JyceI1t5fP4QPV0f3U+mzHxQrZW9WWqXsisr+aq+gG4
T8ubrxtUz/9V9aBDNPVwmW7y4MDky4goAFBz5sv2Vitj4xl/PdReJhivcdAiI7YpzHRgZwFxV3Ou
Rf/v8Fnc68faHvONZ4tT8GiydF4EFWARpWuv/fmoQsZA+EPJ2fn4/prghJdELo+OG95lEFPOzrXD
BL3nYE7Xblwg2NE/vNo5Ye+CNzDVcV7xl4iEJcf9MECZ3JxBnIh4+uhYFxwB//9BPjnrd72tPplk
zCczcPJBm2bOZ+nzvTnHAYd6qke3K+hdaZ81KKkoizDmxk465BTeaAm3LjFUubAlKS56j9Y3R79C
apKXFUzYdt0KGzspyEqBySdP8zmkrCWySLSbpCVUT2msz4WYityrfzLAr8lKic5g5EMd3+JZFAME
ZHFzGvLdP059vHVH+d/s9GAFOXdr2gqz6j0l7aI6AKhyYs1syXqBjk9Xj8pWnD/OTubNp0csBY2H
SrTXwnKmi8w97tOUltrnvyLPUfJctZRGmBLURGXFCnv7jvz/jx5Xcy1bF35qOn0IvTwN/fvFbxI5
Yu1uwK6cTzWYryIvcUNEPC3Om6NGjOZ9/mxr2ShEwUCANFRXYfkwgqVaNcYts6zf/QopTLRdZmi9
jnosm8ggNQ2GEoNxfRXurw82OIPzcL8YUvhAua1BseKMIB88nh8feC5G6HCypb52zcyg7+KP5Vr0
aKw5Ub4jCgonFxTdzn8aIXEVpY0j8C/l5dqEc+NhG5I5Z2pp7Kf28ak71REKuRf55sIOBmlWJyrE
K52/KOgpcgqPFN+PBkFEy3sTcalZotNacUg/FNkzv/ARL2HntCYtMHcyQl0rUpR8ScxnUmTtcwJv
9pRhM7L/Np8QmQm223DdIWOupNnT/R0kalRTJ7GZX9RIto/fzeHuSniZ3o96tjfCVChwRqgehUyD
4OwqumatX72RCOlQNflgpQPEBpZYZ6SoJrfYtgnGTY7eCwlahA14YaipRx6HyROMA3q2LaF24DhE
rnoGJ6gKWopOnZqlGAOn8aHacw5SSlZywcy2UF454lECaR8wNUzywphWn2e8ZCIbSscAx8yUa8p2
6KfkEFZ9WkNbTmiCKciAyEg7NxjCs900ocLUR7NEwFv3bjjF+MWb624JaAOVva4Ln0H6F5gXImID
bIcybftks8MZcP/hTBOO/Zdol2Nbq0OjqQW4zFjaC2zr1L5Ujjdh55qZDlpHOI8J7/9sdcs9P/lW
QP0frodz5Z1Rux07tOmdx+7BR0TeiqP9LLBUoKmdo2e3aIsSLgiGHenwE0Pmb9S7LZ+T+jbWM3mD
bk2smqvVDHEzcqmt8Zjn721DoqA72i9QllZBpnHj8TvqIa9C+GlYR9QPPWCBu2jXGc9UMnqnODpE
eJr5jEulHz12YxuP8PMLYvmQDkIxndFJ8epIEVzFxQycCTKCKOU3i5SZqougXT9jyGNl+HMjkiku
C84CbdIF5RdsBuVjPYqC2zosNGnKPCGStRcM7h4CR19lBH4QalN1dqYIWYwhXBdDLid9x5d4z8Kg
QPWR5XBc+j3VlrbcHageQOMN70hzoGonFXnNZfYlfPpgzlqFgIhb6XVJTHtKvYkMBbHUCT0fhtF2
kVMjwM0RKBCsd6zsflzJttQukVnzjfKHF5c58askvQb3XqbcgkOliSe4My3Ta925urZKxvatIk1S
BFQDbNORbtM/noLhsuJnt8QP8TPnsxOOIOAeScEIJ9mQ649he8syXlzmybCt6WO/0QYevZy7dwJr
3ky71KCBEqHnlDIwKkfow/TJ1tzH8J8FXywXeW56y8d60teGzZVya9Y+BRXAEG1+SkVkA+mCsHdi
FifKx4vqqVVuWcUgxpCF9KG5iS4EUo1IUETlnNQzegj6PsLSOtZlnJyVlC7Cker+on7jFYNVIql2
TRE7ntmPcGjqxUO2iyWX5L4ltu52wxgoxydVY3ioznkhwYhHdJdxXrE2xZWnugqXAV4EOCZjzfQo
rAoDzbGVRDJEgbcu1yUSIaxJnOxy5TtcejF/7n/HJhb4Bt2DhNX//q18jER/183bImZk1ZLHndWH
KBM2Yy6SGUUF6D9zR5hbMGh9ghTU2dviXJntp9rVm70LJOQxwte4NmOwdEp5SngJrLeYVGJofywA
4zw04/ZhT9anDQ0klNfOXuZ/plCaRKgnBw8JsjAcNNBXa6k9q1H6Pl/U9nAk34xKP4ppef0oEF5K
Jc4xGt0/qygVKGGCVeQmZ653kTE0LoUZXtLrmND1MW+SSP8qDOOX4T5GVaVQA7fa8b2mBaci7cqD
IYC3Owzt83tbATFG2L2AZPJCNzWDtOGtPpl+1zMLbiFMdx3pO+AMbOEYvl7CiPHw4fDC9b/caCeI
yafQf3ubNEHsNCkxKDaIesHnnliQXJ2WATTSAkNkFb5sP6FRX3dUQm4zXg3BFnwwxXFi60wDgaJt
KmWVv8h0PoxGk0kcTudrS9MzGMU+3AmBopSlEpp+CqbxWTjsJTprKBzbDHj018H0YDucXGznriig
wG1WuZi4PiLMpkJc4wGIddKT92lb548eic5WBcyi6sc4dPaCdgAQnbxlTxHdQmhfkckkj+YrNtGS
xFhIeVWyF9C3eFwrSwx5aKOGunk3ygFufrvnkBmR2aQPder4Kn5M+kZlZv6sOoDW4Mbqa4ZQk1gt
ys0Yxn6xfzsLXcTeKewVQ3DV6gGgkbnTRWdqVmspREXs5XJYGJZ6PjQVrjOgXa5cpxFsXTs755yA
J8LcAnZdjHMZjNnNygaYCb66nexo6Ro7bWNf9HZ0y5qeHB4cQo+XxDf0wyqo1zorOhHI5n0LSTMk
+SfhPGEiWDmzRPWJ0CFOZ5P/MbwXmrCsdNkMEQL16Acaa+BhyDNk7DtiJMKaQmWN0cmePh0PiK0t
h2Es5QDoKVBEPwv+CzB7LrTBtf5TM7op8FFP5an5RNceeMV+g1/BS2gts+eXTq/0Tvg8Y+3bEJHa
gnfxr+D+tqhcL4gMoLwFgAGI8jiglRSDWCV6sbal/H3HIGnDlSL0OSimtnBlDAq2YWa1fjfr1Jk5
NpdB9E1ACEgldYZoCuf2chhnu4kc6OEr/2HNzzgHBuZcwUjuzMlN/DHlfBKTKQ+Qn7FH32UmwCYX
rqtH5fE0CfnpMpWMlwr1LR8ay3aFWQbysZmx6hAzH91mufMuQDW0fLXtBqNuw5cJO+isgH1Z5gju
0Ggj7wXivPTAeNXqvsmijOejrHDpGzqEA/rjY0wySYu/VcN6vqHduJUi3tuVAZNRUYc0EKXV3vO7
ht07QN4FS4XWomgJae4bA/8/iqWCz6xzCTUSRoKBRc/s6ypfCO0/50juEszKhgSs9zY3JPny8ts9
MwGDI/WLAo2s3EJsvyKgPbKrAaj0MFPvJ2mlV9ZIUoGbhgIWaWhx5bAY4V3GUZfMjv2KSKUQLdC6
NeMcvAQJyBx7ZcN32QZZ8VCNkksPFP/sxgHgBJTYzYSueb8xF9f9uMsIP7/6vee9UJk19bmOPH7b
68NWK/NXNNzufpLrBSzT/swf9PYqKhdbSR48RdrzlaW09ijRz+lnh442FIaCBBip9+NfLtHpyYLS
qHYL76Me/Gf1I+GGl0ciAsD/rfbSghZdFOubt9CG/2R31XOs32rBFiXBY6tH95Vlp4uJ2HpsVDmI
xDjyOxlaZ9ZFvAVt/yaLs6iy78aK4kdpPMx/4L0nvA43cECp1EyKDW4RUKSCkIcFrQlJCbC5duZG
nsY8BIfcoYlAcE3mp603YVlt4Wex0oYzVcQBTB0nE5gmW20VaWgztGdDubBoLo7ZtaP0ZGCrJyDV
DvMhBpqXjG6pC6PDM5i+rEe88scZuzXBBgE2T4hAKO+2u6QMwtBqLhwCjqOWkZogfg89yOhGUU6J
H3/a+Z1QcvdhSdtlTNQ57SRw+XYGAVSbcObjFM7EPFo/ceOmeAG65AI23C9xvHcQIt4nuAUwKK9F
XjkLLyURaZQM18p6ZQZ8ZalIckQNMZMfhMgqV6a16Mmebv9B+PB0uWLNWwPneYCkFRYUz9Xjl1AQ
ksoplG3Ilt0dOxel6I85e3zkuAgyR7o/pAEa0B6InCSCd1XpiJ44P3Mle6Gow7LnKr+M0yVoptL6
l/E5/7J+ceHDubaQ0/PR/usD3nkJq4UdDsvVu2qk7hiF7YoOInfWEO8w3AGG7+pajTmGO9rsoV1r
nPCVZiqnlmRC90qIMIbuZTiv1UBfTqAZcU/HtV8Pe4wc/W/+z23p5LwDq2yTwWZwFPclmD3eRTee
XMPTgK3m0CxEPOZQxXRP1x9BvwZoKrqJ53qjlMtVl82TwmD7dMJwM0bsIQVJicwAbjizCtY1pVfK
QOVbF/VEKMm8foHQ35BseR2gpfU7y5ttwbPmUX/TQrWYr64wXj59OoAq+p6WKjaqdBkXG1kN4sGv
VvO9eIVhUek2Fk0CXkK4Q3wpI8hRxncoJ+220EirYbliVrAhPir09dMC4dMGIBr/LYDNFIpLqBKQ
tx7JU34NDKZ6uircQ3vcMtNLFaP+sHsUmO+i1rafm6/kusho5rLMG+0ed1KXfmA97NiopPTB9zdF
lw0rl062eivaMcQFS2C14T7aYqZRdkyTvA7FDYcx/u6THKSVBcVIikcmP0c18fEkQOilnY7ImpDt
xLufM/k5F91G5HCyUrMCM6qIpE2ukVkkz6ZukQA+fw9ZxSooI9F7qMVrWcp5bAgyOaObR/xXZmX2
Ey9m7gPuZp/aoo9EZvXzU8ry4WKZn8kvkVDNIpH0ePbhRLDgbRc8N8QNPVpwDoXCl69gxliT1lwP
USv+GeSkt1GKNL4YRqb1k3tBCw7ylqwO/21AUa9PIMkdipwdOsvWvgfKdDhd6CiHPlWprsQ/VBsi
xIbnwRFyww94hzBineYibTKartxI2HkP502xt/f9h83FnpWx5z0HmGFVEJINaxbto7GQHiOnC5FL
JlZMDuUv+cMnwzk7e6x4NvFq2aj+Iy9BE65sq8KRpupU0QAdBODcexvkXlJxTnmA5jBii2TcBDGX
41IUYnhVDHBEuNZInHv7FS0PIzgPeGipBjyVAv86cOtnf2d8rpghbxRmghuBouuLCXEjsSDu3AF4
VrrgOB63nzh0HRGcoxmFkws750l+Il0SDEmw5kMpfwhzD437SdB7hCfVTdKlEvmzRh8SL2etkNvp
jby57mWeqq0d0uzT/t1K/snk/WOZIkVfXYT8jDndtJapK/B2ApMk5vIzWgYK/jW2EZF940g6rlIG
X3igGQH/285rAFGqk3PqR+pPkiG7+v9V9TJxfWOf+yJo5rtEDZXLLVmRpou4YORYdAS1/+vBCoF4
Q9MsyUmh8kD3lH5FL8EpcMnnBJgIpDZMYFCjrTO1VyFMG6OH7IPGNElHXTCvVOwgyX7vR6eV+U1f
IPPo7XLy+C9E445XRM4HDAbfS7VbHVvVHvPvM2Oc5i2gmXbNEPYa70g7w3y1AYf+Nx3YNJ2H9jh7
KWe7d+JNmd1Av+uPViG79M3t8pBWeGzGtK956UCsy3y1gPv1lCxYEuwSJBqgta0MR+ALPLPoHTyD
RwSrXtShGrQYeCc6y2nIoRZBUhk3CK+UkQ3OyW+WiiuyslIkSIDZsxwoX4cwHH+VnY151F8ZybCa
zx0fOsZqSBqIn4VCLBdnqqvI0q4UAFjLuxhT5oKu+BffEXjbx2R3FOagqErsW3cnV0iRZjYXHm03
5A9d6m2tvoMiUMA82DdwL20lQsinF7r32nD+jbnNRctrF6Ru20Y4rYw2qDd1kpumSAp6IiUVbsOl
n/Wf3k0BS7mCbo1m4I37e0HhN7ye9WrqDm/jDSiOeinZ46fU98RVz58tkUZRnlzZpi5Zc7Non9c5
FhxqPPKRTfUzij9XPfcXz3L/PrXyX15TJz71+MY7G4Fj5qvvVuHjxxsRVb83gLZbK2KP9UgAjPMK
zfW0IBsMq9oSaglDcOnbbYxQ4nLoOZwLD98AgTxjrXdwZwerkKcuWHXggt4gUzSKq7I+mRjZUtZ0
3QthQb2B7CB2FqS73QhmSn3Z/V2qIQlCx4Z5NnBRjRErJkyRH5VCI+74kK2j6gXGv0A79XJZ5Cx3
dAGXxi11/26OI+xi+hgTgE1oYkfF8uTUCMhkyko2YLLdrVK+rzFlcIuduLq5BI4xZ+QFBV+W42GN
27ztBqlLQRmg7UfJuYAAz5SQc5eejW429pGSDpDin+AYo+SP8WHc9RtZffxB/bxcolsXN63/89Q4
x8gy0Eh60WjYySPkSNBdYaLgK7hkiyv3XlgHSfnHc06UaVjGj7TNnEbbBnL7ZV8F+DIIJ1upcqkl
480ieVz5Vco/YMrnGO0MaGYpm7ESKhlvtc7IscBiwH8/FpLzYMjDeZmRq65Y+d2OrUYwKVVlVASW
bvm4MWaR5kkqbYVIsS3mhvGODo04YaV/HjxLLz1OCQbQf7TwcuK2aYS+xQ00mzwBTDhbr/5vw2Z9
5sgU2WNhqyQEBipu6V5TH1Zis5d3/aylMdIUyP817CGVAuOdZ/BHxmGHfvLZanuFNW68Fwwuz3Bz
iLV1KoUTbklFMMwU2iuhTNSyDh8ByP/4GSo0r4DgYrERXTcrubGOpPCsvePlC5JqKjTXE3kLFAwd
Kq1qpiS9yPz9hCQ8PXLSvTrkabJUSMwV6KbHJkba+vdH7QxSMbqMO6UAuqdwgQrRjlIl7tSa8xCe
T+6BoJM0Vx0nWDD6qbWdaCs7hkBfUbPJVT3wWSv5+1L4/4wR4OUNQ1A5JTSl216hXzVvxhNdPiq6
IEg4CezQ613VbCqRCa2/2E4BGPiPlM9SG/rvNBe+LQGfSvUd9eW7MapWtjqgwvCJWNEwpNIHa6fe
Es7MBN1mH9R3YGDwnOXvkyc0vxFM1RCwsmy2d8Gm23aK3HmXaz3pCXkNuJpYpgksqvEJcxVb07B7
Oc4XYPCG1ag0L6LcCu58WT6eksHVZF5dueiqQsFk2vzk3UiJFyvFHvbeDhV2Ts2zXHc+/SgjFkxO
CALprrHv5WVMp8W9fH4sB33ruVLLLMvW3p0z/TS6tFFoojyG1wICawDxHm/SCBRItADae/7ffAdg
EOhu7h0c9X0HQbnvP/Pswq4wrkY4oeGhe+J/bWgAnFBo9uDNs4vCJCP2FoKou4XHX1nphRq4WEWW
0YxXGEG8MGBB10lu4kup0TG4DynVbm9pw8aSzmZ8ZNrJAIVJ/RFyGfsRf8AkS3+fry3G9j3hORm5
VQHdYRsNVWAJ2/cy34iLvLHcAf2zaOUXgv8EQhAn5/g7xJR5f2aDhvoT1BszusitUGTXj7zChTCX
jrCusaXYcvC7EeHhrDpdH/3gljX85ZdLTtIJxoVqW8e9SobsrRvSVmG49Htq9c3W1uCzMTxiO7Fw
DiYjEvmnbC1UiD3LvV+tR/+Db5DmXyTfiOqiUy6yNszpevfdIA8OnlpgBPIQS1ct5wgfcamA6xf1
KjX4xO3gY26oCWQ6f2ebFRaLz98IONxDhbOdTY7I2Do0zuzXBW66xkCVkmotzw5c3JJ7Xeg6jX/y
dSO5COljT1T0+l5r1sW+4F7/4mx+yMxpywi8vLzaMLO8qXT1St/9iS8zK9m5YKbU9p/m6Oow0XC5
qfO+G1IhhD/sHfheOHg0+cE5t4hdWh5HSPZvJN6dG25QwOk+KqMwQI9mmJFxAR8ozc6qNGJMtiH9
Ql0OKhO5HuD99v5PiN4WClz4IuVzHZvouKgBe9T6dk8g5JLcQ2a688/TOgluMJM3+bcn/irP9/uT
PwYg0zCnVRrupajt+TC0tRSBdcOF1EhJ3hgKUdonlwXnJUofc5rGqUO98GtVCb/WXqXSfgbjjjMe
gOIFbUnpPygDBK7QMl5M7DNorJofzBLNJUs7csZ/PFdjSmC+sBlN5WYuh4XCQtY3AxOIhPR4FFcX
Kir1xGPhsoAb9A8XHw36RA9YqiXMBDoyhPonBgLc+ZQ/vPtJSmahCURphpi5RyFqqPJMwdmp6n2g
0fzD32zURpmuc3gmBn4+6403ZbSRolGlp/0B1GC/ZElVUJmSP/QmJnuxPiNOsE4eRSCOAoQDBd7X
0fDXo//uXe2tpGZnfnmu0/3miQTp/Gxm2cSckdgKzkAThEQnr27ZTnU1qHLHWtOoFVm8/t7rxU7r
GogsK9q+UPrExrvSoI4bRc2/Jj09LI8eUek1eLorfjll9Umk+CvIhv+aRFshGtvBA3ZpgNjk9ONQ
NPznxpIu5iTH+KN6CTsqJSFcLvIzZqb1f2Lb83OkhVYza9vHlFkzg4rD9gL7glLt6QW6b2gogJWS
X739ArheZ3BDkXZTohdepc3fMFrtgg8aO2deEsDsZjFnIypVtYe5xawOOGdRcbTEDHzcWZX6V7HR
yf/b1q0hSRLnvTjZW52okdNJ8Rv+EcMCsntm1S6sFyuGao87DCWL8lA2lETq/aQLwY3YZGObxscY
surXEWcrxkHn7Dps32ebyBU+QdL7B4rtw4VnJoYvWgBl6zo0225VWb4LsBkKAriqsT1rdde3lui+
1VBYSlvr6OG/wfgB+v/Z2iAIcv+31g38xvu2L0Br1Yc4byuVgtQEqjGwSDeH954Pw+O1+Lh2SbQV
4Ul+rCjRfZjeJEZf6GlMHSe73nPT+4qriZUWAXIBPB41qKFq/c63TJeqlNLySgv0ZXdX3A7Zr8+3
pWhxUAND6dp00BpL1C7Fb+zKXhiTmhV+MoybTN/XxXMBGflyAqi0nuFDDyegQtkSAo87tAplJJlE
rxuCZINBHxdyhXb3wBOZRgMBDtWutOudx575HAToIUDlY9xnaaUq/ezzNU3b+J0TgEd26aEMfp6I
gXSC2fNBWL0yuyGOvNwizfywmx06WTAE2kXJP71HG+IT8ZWmBMYxQLTKJ9d/sfg3FSf8ZEdNEuVS
ADDf7Et5bOBKqotEE3o0R5siqXWi6ySxx0Tt7W7JnQO2W+X3MVLxMCr+N9FXOK8eC30/sQZLsAHv
iKQlI02Ei72q1t7EN0+i6HABIdWPsMZWyO4bQ9JkLLseOWM9mUzlmqmhD5rBei5j6jBl0RRAGDsu
vpCbzG2zL97NqXOtfEfd2LvZtzGHwiiyllctjuWiCzRJigiR8ELIOE0Zs9QW2ofZcJ31XvFk8NXx
0HMi8SR5bwjxnGTlDRqhnYkXZxXIDntHaVbKDgWg/fm5qeNTb9uGFfDxDQp26bCybZ4YDa0y3ry1
KYAlB0EVVXUwj9NXAmDeoNtfFgcg+QQPIhLn5TUFUlVlzLTT2mcsKNZW4ASciC09g7e0GK/Wjsoo
cVHpn5iKQzVRFbawFLexCF0c52wzxRLAoECoupK4tldE7wwqtXB4Z/KjAJR5s3ZAxOo2G2Yt5tXw
QJsQlF/QmaIOiEe/ugoQwTRZu+bTB2zNXuzTqFtCUq5drkH06625bgYvSB689RNxY2QeMWEi9SAy
GaymLRUz9ZyN2uqJKW93MierGFO/+O2+XaarEvQjav6H6ThiF0nf9hgoDK4OoMo5b6+1LGBsWUWA
dd6AjAgXOC2SSyjrnLJ4mNNNzhKZm9tgtO5n1UMsB66VH7jhcVTz3kk8HeXnk3uwe5/3mWZznIP5
iCR1i9Q3HxEbVI6MaDK/RxiUcN3IRvZ6nUoVifDF9hsSc/AD/nNmkjtyOln5QH60gNTSsNVDQXKm
RB8GaVVV8E8Ndyn/Jwx5ypO1mqfEqPGu7PFGJvJpWrQ2C15RwER6cUEHwIFOz4bgVfLpKmiQxhG9
KYYsEgeBXMxx1siu9dlyC8vyZOKkza3IuJYHTFGPanxPaLh4QrpvKi00Cq+IkqultyC32HUTZOZK
Zlh58h26jSbq50FWACRU9foKNGc3jlV/YLMeBtP6wjFZhVokh1eoStwhnQpvXzmJ4fqPPHeOeJ0C
/uzcn5+wYA1v4xwL6BC9qj207HBdBY2/3awnZMVpP/WFEy7nTD7RgRFcG8kMj++YYD5xPx4/OvvG
t+y5hVbUzmhwTXzQa9yLt5+ATDs9wzb0bcud1GeasY+pQK1wH41vFap6OSzoApPmtuXnKQE6elgR
pPpXfMRy5LBP49ql0DzY73sLGhtxeKE1VEwquSuViduMde7sBloiyF5/wc0x7iyB7Suq4dnz7NmC
eHxCcHOo2rexeyYHNcxMcs5UTFj1UN+Pn3mFfY2wa0NrCny+aUYnNXk+fk2UwWTtntpNlLtcGbRl
t7xOOBSfSpUtGAvAy0SXS/Bud3nQG38Tjj+WGwYKTsNNKc1iVxVXMmKiHrfk0nvQ5UWHr5BWUptg
f2J6f3prw+kRnIVFubc/271F9uOlQqNHxP0W30bHtH43iaNYmGT0sf1dGzeJM8l5MGzUu6Un1Y65
Hu2Fecg7fnqZ7AjhdBqamiPcRrKSGV6PXTvUbO9n30hsMigZQpWWWQtQ2Y77Yg+727ZgyRaEW+wH
1Lh4EwzWApALBjguZ+6OcUVgG0kNW8FMK9rg7eJYcnwvOz8Drpqcl8wWSPSObFMhDZ81Py5A25mM
oAF4YdnqkRte+B2yNZEWObeIXtcrQaaOcrUHQ1PYYxLfv9DlhIbJWFC24TsCl8QJ2FQwviLBCMiq
+zYTM+FW5X9Wf5J5mOdk8uxF2VDDlCqQbIHFR9dOG/oddqxZOfHNC20kvh5nz1ULbaSF3Hxxcmtn
p19miSL+MTWePjuBU8zR67i4wtbhE7TJynORZlCOOOdws/axGk1EsaKt0VoHzt4RcbWCkgoddXZ0
G+9+ZUgmbGuXgUO1hMlcVrbW8RPi7lZ5bE2IEGv/R/I8Z3ZAr/xC8ETj64g0F769Zm2OoOL4c6go
GvuygiVYTXxoMfLgbH3Fj2ZkCRUhe7VN4TjtjtMA3QsU6X/Q3YB/K1qGNuRFzQciEHgYF0oosJRF
WmWaqfuixGmPZ+JbVHTMBd40MpCw9Fl9MtKoJ20PMtbH/aTNJ2b/dV8B6GX1tXBLND96DaQMwvwM
YWBbpplGUw6mRU4j8zwRXKlpOOOt3cIb04v7GdhjMTxxhbFrVovFFwG56jsmVuyj2PzAMgfwX0J4
fAh2RUupSJj83GfC0saLvjcSQ5SBcJ2rEK3R35AL+X6u9Rpby038/7pahStiCcf9HyanpgIKSA5H
Zm/ALcwR+DhxoCkjhDGkaYl67RlReaBFItsucP1dJyvzMm7+jdyFzdv8O8r8t+i1pfd0H0O9jd1K
37fnshWs7pE9KiW5fLjwQe/EJv9qM+Nem6j6srHoVSRa8PDFdrtkefdUfBbaMiasYZwg/622+loZ
soPrF+r7pvNd7fjiD5Oq36fv6/cweZ1Cb0oqipHas5UtXpkpXh5STuxzc8+SqdWgVKEytLhlJ4e7
5T6PW0JGDy5a0ZffrAQ+8EbnMUYGQwRgqKIXRGpYY8Tnb3/mC9kXB+tWwXBPp8lytm0B2B747lEt
h7A9B7RmlKNf9GftTQDO/2j0qjUdeph4EPamrGjeyZRzZJnbevgu8MRv/KCpK//3u99ASVgc4qDl
3Ou34J40islEiS6Mee6cZZ0cRLMarJuTyneyqNpQKY1G/YlZ4itxm79b5sqnnpHWodr46SDcRDKK
3y739IZ2HYEPWuZ+djtEdlQIRKHiz2Xxq4IKata9+dLPhQqsanTJ6YI/9xn0T2NqRBx5Fi+ICzF/
8jgqQFM+0lIMTTTsBfEfRMXDKcZzSAodnmbrvVqA4zIAIjEofsZN1zsSnqIu8wHqOzzRBVtqKayU
S146eox3rirB6m8A1/a6XhC877L8e8cIi28yvE3MpZz7d5tjrbtGmZTZXnG4VdhNOmzCDEHYA1D3
dpfnalVc7JewMzP9YJm55H4TVfPlWitC1JIOT0j1JRP6FednCtvpPhKXTZukB3k5exOd/8qA1Gx6
yxLxK3s0fUDoK7Z+oXZqSYHocWImXRM87vmAEIlLxER0Edp3PrKh/aSCEOhXImAIwmzYF/xVtBFI
T3g61lCKMMx64UygNl+a636hnM4nxON4b0gtjpjLRnt2fEamo/tHxaesxmPtowRWibvbr9zJbB23
Uua75xdFglnF2Uvgbirc3f8cNagfT6pmCdcA55tY+Bqi0ZKK/0aBcQsLsqHWsPTS4Ggk0MmCVCH0
rHMh0TztOtHBy7cvO9nz7EQE4GVC/2HTMjP4MvuGJpFzrAMcFPNVzndDMY+AhWWt8XWaQiY+6Hn9
5/702v4+DEuHxDvTWhK8EMX+xpVY6iJwUSbJirC74WQAwD2KD2fIdB8TyiH9/sFQQqFoXV6QWy/u
jOdHcsvy30X3/LLwiu0lQglzE/TvEA5t8dYKaq9feEsIPxZin1BJhkDPAaV7aN4uAMnwDlycmhi8
2cZhI7C27oKEP+X6NpJ1sBxXKOVxTpHCHKj0ZmID0xi3hF4LsuTnvaPXzvyCGCY/twQn3SwJkQ7U
lRbcqLji915c5kHjGecrue1u2CEkoPlj/RWr1/Pbir/xvDlQaWXPGADimnuNv9S6rISwuygPnMV8
zFUfHG3Yo+Z19TRR6LrsFcYD8hu6pHvSr2QN9EFeIJvSligyg2IKPfMafVxXyYMz/rS53fKWx8BB
YghlSg5MXUj1PEt77b7M/oEKAhJ/cO2VB6X6Y/WTD2/0oKuaodyQGoZYw/rSP8fxTVAZ6OiuXxdP
JSHRz8szcijztOCP5UgfuqViYycQR3BalWZr4tFcXEpUrTlh/SFjCFd/GV53wGdh4M5IUypwzIZC
leqssjbLxP08i+XZVCX8SIqGK3rSzYNK2Ab7wRNKie8naqiMEmkiv7ivqrSNZYG8FHq2BqwAJbqj
P8fmMYwxCqmiyAXhYs7SPnZ26Cyyktdz6cbPjKVaSLBaIErAzUJQDtAS5c6kzxNXz3NpZ0Lx+Dyd
QVr/u4LYRiWc8vFKWvcgezhXQB7Xxo2q2sCXn1bXlGbzpFUfNz9lTHGq7ZkjPltq905zB4eWC8hq
zMAG0ABbargpAEr1frkjZU3+rirU7GpvSi9USNM01tjthkTbeUTOr8Bcbcai95gnEJBK+wWegK1M
/zeZTYjQ79Wy5lR4ENh1KwDSXbUXQMUZM82S9p1N8evT//OMc6BHbsgTs/xVlBLTvNcxHnzH3n7l
0LOQL05D6vI/49tnjB6mns5sAhIIwRO+WRKjgM+mKIN/LFSzHN4UOOpNrGlVLK/AEhpmRJ5Rej0d
uDGP+EagcoQXy9y6VlFjAj6y9dJd46eR2DISNyhNahjyjA3YQQYACkTPqbt/NvdHd1C/gr95vEb2
tRKObd0WHUBmIRs52P4EHZw0ct98lFVSHHDHWA42Wb0FHkgPzyIuVlq3x+YakEaF2hroq9MeHMbS
DX8noEkmY4ySW6xhNv2naK8sEmEj2h/fyfxA2LbLsSIx1+nlym9hx7yB12e3KOihzaS/RPbdM6sU
TZAxNVRELG03/rciZel0pvUcD2Wu17f8qQZJtFgfvSiQjCQ8hoZOG9/CWB5bIMtiDNaU+zucmnv4
Ux0xK4drhnlgPPabU5pWLjBCooxqUAwTUNJi/oAMai4vtAEhW1I9op+QWEjVYKj0Qry9piFImO+d
GUGliLb+ntcGC103gEmc+n6VW0HYu+G5T8bmhpQRcvtDL347NK8EoDPEwurOPqr9K02kj/14iH+7
56BjuEcBWhvwiVSGFQompwdeCgVgDDqf7QjuztXG5aiTfW6AofxQd6xeC7RregjtKVAqQnN+rt0p
6WophOwQRrIcUV9o6V3sBGN9CluPdgdcAwTj80oIqSodi/YQHSlt42qPoyMjOKbhGtmU9/oUrUMi
UhjQ3qNpCx1hKwxqHyr6V6gsYJrxW+ZQF7IztQvQrIgW7JFjpu2Q7AQUNpT/3+fdg5IlnsKw81Ne
4kB/bf5TBeroz1I60IZbm9zilR150sYg5OZnBnzk23eZO5JojN/ZlhK7IVvs29dGHtXZNS9YTSA3
pLXSh6GggrZofdgTS07SpeUAZ+YXbnTx5QYkl+JAJZFvgpXLE6FzzUTgkRdNBjFCYVaRPIh+MvZO
dfl54TtOaebC88bs7v72+7hX4c9OTTJ8bCFLrTaEAsyJjt5vJmCz+ISxNbmBIwzCzMZkEvUP7ec0
SqKp/3xt2pWEdQQNPkLItFZ/uKeQhIDzGH7eNaA4EvmMeheC/p6IrSmbKPmwI84hAcYmYfS9s6R7
k5UDULWf5cva1R6zww/6nUUgfprtVdRLZjOx8NbUPAnSI8V95wZ/bmWgf1Gxqi5nee1SfwAMQYXp
hTG4tQvjFsvfG3acb6nK2J5SPYc9AvcqGPCX6IlZvgGw7Bp57EcfufA8WqvfyzzPX6QeS1uNcZU2
yDfWvD887OihJSKVPoa8UTlv95YR+PE4hjSq2hqkcc+Sw0DZB0Zlo1+EfjmFdpc1yVvZG7D+DD1R
nUJ9M2DKGyNeB/Da6fJEhMJcwfGN1Mvlo3bpGncIK5P2q49Lbqr/YJZ4FKhbAeqWiohVCEhQGD8e
ByyAVtnxRH40AFLjr61uwFeeR77xToyVRxyOoy93Bn35hAQucmmlSqzFKZZocGO1pxHBBzu8i/YX
PrT94Uf2Gc3lJAZIxMnCa9E/YRsHe05MlvTdT2hwYfu8sbJqWdT32TJBLETTzfBBtDNKoegDK4Jh
5qQ7coqmTBeuqouF0scswbD8P2sjz1HD43rPNumvoHqq8LIHFGCM7fyBMoSN8BaKVQ7KYWpgUvq5
zlui9VNSv8jG/q+vDy+Dhez7u2u0bMU6U35eq2VIBfNsGr8ClT/fuCiZ3/aBkqycSk1Ad9V8ABVr
clqtaOegcnVHy8yUyQLwov9yIpINW7W7RorqjmpQHHUTWddClf1zz8y/teNo7FWGaHLe038L8Rgi
Eb4NO9aFcRObfTEBBRDJ8nPPTQZVYmWddAeRsc7PHd+mygRAhVxn5D32fwokkL8rDtTUMvmcE0Uy
VwrAz9nPnZkjPNYYZhFA+D0dzIMhO1cNqeU+tT0OtgWv6pVwN3tr0lkJnsw6bpanQ3dGx874N6GV
M0X9RKvurPPCdYmiGiK9XeOKUH3HoLjqq0S1n7EhptSxaYY5y5UacIZmUtjAaI+dPBeq+V7TDMT5
o/QpoG2QlSD+AE6OuQYlNwgqFn8lBQw8Z+iB3aIFN1evaYKGyGjh7TA1iYxWC86z2YdZ82cJ3f1L
DhLvxswHmSJBle+blT6hv+ZEAGolPq8GULtJrGej/w2TXwMfstbxjsRkYbxjgCj/FfLl03i9FcTW
THe6z3zTal97nBfZLIsAQMCALMXQIZtYavv8YXloFRdIFEb32I3UdTOQhasYC0ldJAW2VX9Z5QlK
EZHUu2lNYw4Y2EqxqtOyqBpdwmSPgynQ1eD+whLxLFlO1oUBlqgKokFF19wtqlwIHSiLFBrnD/63
dzslMSdesFjnmaUwJLBq8LSqKElN8JhGJ1X2RIXFOIOgBrQCa48ZaNshebs06PGlr9ibdMH1LyIk
g3UdrxA0tdRKJXM/lMX9g/U34shQQNHkxDr7qWsh+oX6Acf5ceg3EbRmasYHmLfHT8Bwnc3qviyN
+fBEz8DLSt7kAHtGA829EiR3iTgAioivz8GRslgffYlAwUnn6tnJvehtfl7l5PRfej6R+qlXl3Fn
eZBPe9YpYF5CsGfNRtnYoM+xeKTL7uOFLobwooEXK1Wy4DdL5qi7kwY/RQOGxX+M+h/wIQkmQPzW
DZsoPQPjMud8m9n4MfHDlN4rhsrsr+wsa2lzFyAIuRoVa+qSY/DUoEzV6uGF6ausds3cjMS+md6g
3qK2MMkk0l7xE29HH2nk/XtAWJ29GEZAj5OsPT1gGV5eoFgCDuDtgeSaW897xiYuUyHZYOcZi6NB
YNRXQObQtNUAhdxjKsg+kDkFSPEeoZXeyLFNh06wnvY0l5Aw/w/Gp0kQoa1PIa3CL3Kmatp0WUzc
GpC0Q7p1HxdF1XT+lHAtc08fCWjW9FqtMUUBoZNz/Uj94foUugjUcnD4ZKwlLIRRmoLw/YKPQe2r
vX1gmiS16/tOARMdT+eBRwfou+mgipV9OVlA6E3xdLG3veIvFBJznkWHQKIRzq4EJpVbkwk6h9HW
esOoYmb1rgwKG4ReK0B9blIURRf5/+62ATh9RYPeWnJOgID/i85Idqrx2sOLjjBk1oqIyHsGUdAL
re04z5B51er1UBG76zZvdZytSFftLicNm+WWZYBoD2R1944m+sS28i+A7SA7gVkSebtSZnYhHc4p
YVkAo9cJr6nSMh7qPFYc6ha4EQHftf1R5F/rKLH0J5Ag0hj/p0AKMT2H43fR7XptL2afoUP5A7WT
jSxTpepxMF+tWzi5s5RJaN1z+H78uvmlopZlh2cSXwSEV5Nk2Jp+SyzYJb67jx7tNcnB1nF3F1YZ
1KUP50rUcJvY4IXGy4KG/ViYzfSFybNuTYHCDVrEedPd312S3QXcNodfoK2dVm8bbDqatnmZ7sV3
FpIgRZ/fDjB00sFZL/WzL3O52mb9KCgdH0jdf8AxF7Wu2r9eSs/UdFWbsD0MtDBz7I9x4JNsGjGo
o9XGOhF3qdTeDqq/cds24otIPFvOp0LUZO0N3ZpuWULlfjV00vZolyJZjHpjJA4AFTYs5rga8Pyy
MMft/1jqjvhnsp9scxSSM/i9bX730KBzwihDQLP1/IyZMBOD6CYmAPi7VbAQu1g1ocBqR2oUn3Bi
CTqchBC9BT44RvnKIN6hO5NegMkBAynWaew9jB6CRQzCLJafDnWHqY4NHmv561fY175c+s0stZ2f
zfwXSI1dOWtzRyWcW5PnpAgLtmsHMReEFKdSu+pVD3pQ8ooxeFQDtQpD2o++SZpeE6FVXeQpPa43
K5NubarCo4XzElG8a0llVWH02CdekF0jD1kGN5YDG7nyxe127XA7g9uR5w5OhTBVJZA7lKq/bqH7
lkMKAxFD1fChLGN0uRFaY3n7x8KO0Ca+05OFBgqAMQk14qidA89X6sNVTcX/e9YiYQOm83eQCWjB
ULT3/oBGhKlz4xADw5vqB1odMtabzEccnlapq9QF3gpiwjcxJiyFJqp72tTR7DSKcNq9qd0WaZDH
e7fFe8+qbzr+CwPc2VH1m+aVLAGFnq0lkAGMKPm+NEyfWhLWZHoLFPj7whnRBKgTrEB6izvpfdTS
ka/KkjAP7fRqjw4EpUXZN0rSZ23rC3mzJeJhaZsFI0A0uqdvfG0kJvlmIULK0eDsu3PeuT3+Oymz
FbeyI79zG7gDE0AsHiirbEzTy32oF+9rlV00lAB5rlbKKBnbaYiD/zO69f4/8e1qeUwcY8eNbMXv
9vhm6Oh0n/BFB1+OlpUAe2yOdaOkbBfiuJGlW9POdQf8hFl0Pgt76c8sEGrIu9DJjGyZU4hYa6Ar
jXCDN5jPIMnrUMINC2fLU2x7ynwq4jSgQ6xgmmQE/f4zwSJ0jSOuVdAMKm/Kbhg8BbnoHYEo9YPL
9fdM+dcxRwZ4Optxanu20lCMlfzsRaDK2gbvfNnbKqBHh4GQeR8m8IsVjfCQYMq+ua626Of4MmRm
Vzbf0B0EsfSx0pXXJdR7L6SUhjhSbIeuFi/Odz8jNhN237ailF4hdEZWVnE7O/zmlyOEUh/NyPtS
a+d6hBJ8lYN01Xju2IV13aWrNREyw807be0jKrcFNs+QZt7bAERb0YLbtXF3L/ZFXEgNyI8WiQ/C
kU+EBOiqQU2iqcn08PaDo+UP0qR+aUMadC2yWDwkqYvWlFOGQ4l30Lbe1SSdv/zhpvn5LMKGKx5u
HoWQEWmlzMVHbGNcbE7yaXRDW2VOALhO9NGF58+bx8EJdPtTmtsuMbPHZFobIpnIlByqwPljCrjP
pYX5uJtAGEJGvVtOXo8XK278/raZZkOiVfERgsTWM9J2e3MfUyoCPD7sI+Ao6ybHHy2UZmMC0gkO
thoT1yaMI0jZpleWlZbXeu7xUEGmgH/yHxqxG+YENLz1BBKG1JjoSo69puWQHgEK7fBtM08emmiI
HbBtvZBgQwxCT/YxhXmH8Bzr18ZC6GWZ6lLV+Vhx2lYBTCxIaktlJ9Njqz6y1rRLAQ8NO8VI6R2m
AdG6o3bEMdQKxxQVl6KQSPmCLx201zdJ/tuYiB2iH1uyhrlPdjk7jQcnyElDQmgUR46+Xq8QhdJV
c5b4mWPyulIHD9EnmBiXpLePCE6YwCeLA/K8JX/bvKrgX8ou6kjkmEMwuyYN8snFmoFl93NUSzuG
zrOWpWXv1+sUx2NaAbjss2OrfTOIyQ2dzdpJcfmJbvPwG3teuK950j7vzODVg3ltQ33HBkT7/20v
gXLEaMYgDatjKuDE9kzPaNs6J2ZiHsek29LxUwB4JHS8FDvW9vtZCJLMeq0OGBlJDE4W9tebimi4
btlQInwdpCjMtGvQdsxoqfCyHK1I8Flzzl2fvHMGuxS/NqVwS2ZtHY4jvsVmRMQ0Pl6Wun7350pB
NrUMh7iqKZZ7T9xqTRZMKNR75swucg7uCSm3U/eZQsHbvO8P/4Rh/O3vP44kMBl6odPGWxQJGCKL
pzY5kKmCz+Bh6QPaygOj3J26j1c6cuSe3qwFrXcV8/WwwCyK476kq+bCQfZepO+fikZVwrWwW5Ck
Vb4OS5JY7As4RXySPzFILL9wWGif1Bw0M11YdTORmOAWFrCQv6SaLOg5/OT0CjSL7oB2QJhKSY7n
ehnC6ENhjuX7P7Uotfz51vLu5blvqwvE3b20JnQmeXUhVeEW/ruhcdEyZM/Lton3rxjnL/J1cBdZ
Q5Ht+hnEMlKA48hYIvRy7i58Uo0Vpowy21ttCw4ikWYdwkOETnnLK7rAa+H8sleSDinJjA5s8YQX
M2ulKJX8sYzy7/sqG1FRaZtJ/QH2gkAiqAgMDP/tuGjfiPo06MFmgpf3zKL1M38d9smavuaVaHXV
mTyfK62XldfTcA5PNLOh0NF9Bb+9pMWYWl5AppqPcMM63pppMWeqwY7LDDHWaEs3AFNqswh4njY5
tat6zmsh0JgEPJ3C5qPM/PyUyu3cX8snOkfSJ9ePQkHJRFObSjno9XdIsmt2aPuTTZPdKDUYclXo
5AI0V6E+DyKICzbXddGN+7e0XPzyeyrpANCJL9O3UybwmWVW6p+/8a7Pg9WoWjOXCSrN6Id/4nAh
o6KvZE9nRqBeDtYMNBviMS3w5UwunxCAKBwGUs5rZ3BN/g5MMF8gJih5tA3C8Wi658Be6BLXb5sF
I7I9EU722tzR/fQBVg8OoRrqCcN1lc97LlJHBAOq9l/4o0w6+4Zi+N0Fpk2MknfAYeaQqxDnCjk/
+vuh2ofTJcNC+8eTTlewzkXRf/sR3ULdxzMgg4QwHqjfJg37W4xMTUh8Ceb56Tww0I6xM8Ksbcm2
PjKgDOD5AWmnYN8db+Vj/yqnOlOF03v0En0aduwLZMsVHWpvCBpRY0vifPZrlAGwHfoQzTBx9k4r
tujcoYkwTrKslcygEIR/CJYH9/9aE/+z+hl++m8LCjmBM/2DLm+Mazot1T+T8FYeIvgpqkQ853E1
Tf1D5bOxoAEeFGu3/bDMRFnEP3ocN48JZagxh2hm+flijrzAE3oAdaZm47sOhteoyMCzo0RR4nLO
trULMHyOg3P1ZN2Pu/P8IVVxVfVgpJ/mpEucPmbee0KRCMHgGxNGg2JIHMCvRIxnaiyLPLxTkbsW
wP73sjhpZAOoRe0pr2feIFJ+NwG7rk3B8PRm5jNSvRQhaX1q36gnqBJoRsDeL++s52PjxaIhJf+Y
7Uu39eiBiLvCE5/aNj4MNdY8AWoo2l0roeOVu//bfuA2WAablanE7CqLYOT8TlEJaRquDpjx8LNG
ed4n+FR+Ejh0AIuv/QuOLO8F/7M29eUQ8N2IfKDzjvJTDdGLPqizDS9ktfNTX8pKWyboLEU3Hg45
L3aHunGAYqqPwqqgDlV0yLiaxmXAeqSVuLH3HfSULyYO7Hh76kixijCxrfHTvq6o/0HbUQGb8KIh
DlIQ6atwAtmzlK2xDctpeDxaUcyI0BbC2OA1clXj+hj+pugbJNl1+X7cOFo3SQ6JyIQ1jZ/Q68j7
OGg3Tn9RPivOcU2XUlw/j+2wa7dw6xRXXu4FKG0fI2FJSOpShxACcRQOh7oXW7tothQPDT8eNRKk
yeVc72+SqBNoh2UuAzF+3+Mn8ysGQXxo+s3/84WgzTX8y6x45LlPmzXVbdIYP5BJjcPGPKpGZv+Z
8ZxsbfqKFuHF6uMzqCcQACf7HCKnl21Mj3LeXClkwnKHbbNalamhmDjULyV5tSLHb3r0ljQrtJgy
U8LeWTTPR4DBSsBTlgx+z7JzSDTzHblnc0jSHxTPxfc6Kg1zoxzSSIfa+RZ/XI+1mpeoFDEh1Dxt
Byt4JlFdyUtVfsj6bfKED8kEIJPJsLf0Jfzqcwf0/ancNkpTQlxylaD8CLNICEbbIDZLWrPMV1j0
tbT65WVp6cBiIiB1K/6Ng7s/5mGIVc1BM6RIMIYuQXRVwHeTLOM/w6uxITkBbqSmP7ivA7r3g0ya
ZJY4YyqJZerfH5nGN4igHvpPYRQ44Ihm3ESrYeZUR9qt8z/lQHhQg+9E9IUxWsMm/9uBhaFqvYuX
I2rGM9bOwok+6SsvipNN/n3tzXi31ECHhVyUh51GtH6fV04rR1PZt79AYsuAqEYxXRHdAY/S1KTC
mv5SnskM50rG6Yj/Ki2GXftTj7H+VqSvldVYpkMx5XrHz7w/hatpcEaqVqsezCQLs+ag4PdDgs/5
b+ibDuZEV5UkKORpP4Fpp7RvvA4t85S3j8p18EKBAjZ2JxX+L7t0oueygR6qyouDqM0i+TKbBxeO
Ovle/DoyHFYJznToH52oxMa5Z1NrC1kq+mQX9s3sfdQJWUoS8ycLAnpafnEfcOxTB5MGVKRi5mRV
EOEDiRJjkeB4Bcl17QS2N+760rHGsHksO4oAG8CZqZaVPbVvv7dv3uDBCw2NR9KdCaqM6KQdT0WC
5FSDPdrLUQpwQPOIcqQWdQfxbVKKH5DvKQsI/wYQar2PRtWTr57U0vDSihbcV6xjlp48VeMBXVYL
Eb+Nt7NojEM2XVnjcynPaBF76yMaazNRKOmt0TOCm/776HLxifUKe/ZNqxqNqGMHe5FJZXyB8Bwp
r1Xq9m3Cttv/DITfASf0gq8khBZANIVbYRM7lc4IPBNbYC4elTkOA45RRKAYnS/SZXqt/h25S/1O
L6mrKr91QtcvhrGr6WQjvfswzd5rkQ8rYV/ysBN3Bz5Xf9F2uSXOgMMdwDL1m/ivjopm17waVoyC
XNumK88vTYVVqJGeXyqYZPR7Gq+c3Bzp8zzlXUaeBEmlLQcE49IU0ZZjAK3A6c0W9iygjLUnucGp
B8iEPyUtB8DaIlzqP+9IaZChlPwiFhVAjTaqJTLbgZX+a4439qYfBinnHVvt3EIJIfwe2piIlLOn
pac8sB8NbXOdWGQJX9erawa0lHxaXIQndcTtlL8QD5qPNWKCdXm2Si3frDt5mVq/hNvfp/mgC+kq
29TjsgiE4sxv62kGlZi4NwnYRc/XwVMjRcVhOQZMIJg9luDzmvMRpDciMhO38yJ0S7LWgH2RTImj
nccCTVQpPFb4ALKRQpLF+k57WAs+nxCFmHco3CrCxZJ2MAc28yGTHBBiW5EDFCSVGx3AVB7Y93eW
CG5BS+Jn9hc551zpenS4I2JI6f0IXUV4SAIW29ooqV5FL0zMkAsMdgvb9Vu2ajo7bWpSLmjqZY+F
/VIGoQJ6DSdLyLTxyPmoRe+fUTipSXnQfwC2wRIYNtbCyXuuApiIgROfzqAGvxnozvJ8lHwV5ohE
B3rrd4YMXO+uLXjUWb3Ojw2JjmilwZdsZPJV7iiAOinYXMSK2TAx43hJDfJeFnNo3XAPuniP/Lq5
OEjHUpCGwACY/hrl5u4v3LyG1g2ssOfxjBaxWUkdzetS97Jc7lz7++RrtLHqGP8cLDdmRPzg1Wnk
5zpXWR2pRedaB1yen32mCKCQYTOrT7PEcKylIAisKU+82cv2+xiebGQQsTimZLYPLtVI5oxbpjWd
xVPMx8D+FgOOrXruAix5gWCG4nPeYCY9FGTWU8lJytjsr2lC+FdJ9r2qLifKcxgGSVOqEU7OuPOd
iQ/V9cgycp2dWbwIDpAymthA2OD+TrnFA4JPZdsrQ4EK5BGhxpOqDO31iKIt8TXHgq27Nma2u8Mo
sS4o4YdEQJchbdVq5pOk528vL/xb/gpAaC9i9uRJKh+FNz4foFRUKNp8fC8ttOvFGLC2dIaJD68i
Qj5901WGky8d7Qram9ejMUmkpZEz5bL9ABZBwM4+3M+BTqZxUcL1bu/oIqBmySl6M89qYn0OfLLC
FiZxCS5zYbkUmKAfuZeZkFBHOXR+d/iEkncd5dd6Rkjj7qQ2OjoSXcBiEg0WYmbV5zmS7PwBLTJE
g5eTdvYI+D15L7wJa9eXDEh1xhc7ZJyP51uBNV1F3BM5wXhtK9B40bEbk2sCZLPwRVR9nrRldSKA
0xJL3Vh3CIHJU0xYfEdf7SdZmNaznJjm4llgwWZkRMyZoOFzCVzJg/w0qtdRHRJdU9mXVQewCRRb
UBTwv3HaXwtaZ+0+/1utz2FSKBvUY45Uyg2s45ZY5mxwit7wCZ55UMaMkR/oxRvnBIDqwJA4kdip
lQqSb8s1LdTtmm7JDJPqXqPhhd6v/9MKbgGE/qLYXoYV9AhXm0ftmirXEkWi+puH04Bc+Sa6h1CO
rWLIjkznLoIC72lQ9ZjELo0SyERqchlzM9zsz1osVn3VLNc76H86WzGhu/WiCIxi2OAXf0MU1OKk
qSVVRoT7fhgMNjbxJP3pGBdjb0jdEIJt1EoVebERZ3yb2Oj6HZCZ5OwegEmMRGaajZmvUx8AnZei
0obYWhaMpbbvF6HtNo5wL4UphDulL0JfVSSJ3p/wmER3uAyOw+dTvLAAxry2Sh49+E55H1XERJuJ
bWRdrUcsQstbb2aqpHHLqKjX2gcH3tZjoIWEGKTR8G64/+u+uY3a+jdo0c/QwhUOIPmELRhR2LgN
qE420Af7W6L2AQ51HQM6br+iwm/yuKcnZ5SnTJ642KleE+JIGT2cdCNBoN/taXxxFu2RP5I3VwdK
Sz1Ax8WNAduddLLx2co7NaCVRowtePFm7RYtznU0BMB1tMYe0uxV2Bn0I80KOSo+Nl++f4kZEHBs
CVjJo3skd0a3+s+p0QaD63nAziq3xIzdC7H6D8HBO3xgR/hASFiIhzTWX/U3zGk3RsKmLD+svWF1
QgPPLonhRw2OHDUVhzjXAySv3Vrw/X4G+nJwdH7enPKm33UqCqDhKuN3Chvp6O6nyvg5GW/PWqv6
VR5tLk2daRZ6g/XFWm3v6tfpPQtukzpjgdTmPcVDUBtKicXIWgfHeqzElpue0Fd8l+pWa9G9n3ne
TjLVKPbHzYemQh17LuxxiiIvNkv9DIkMV7Jj8SBHlhKigEpwrF4i8fu1j9X9yqXhvkY18+bRN3Gw
uBrWNIS/1YF/gR7o/NosY+ROwaE7uJQxDXqoR/3ywlM8/tK/1Z9GbSiFkiUxX8bnPplo16SV3lh2
XH0snq29jaQWwy7SciTxQsWStVeUsznA90FhQWU33nGJWMuqOG5WqqMgo+C6G3pZF4BLuwI9k9AB
liqgP7U7H6gz7rudcR+xahXCp9J2EUXowHkro8lZ3ERFVURAKeF+30bCV5u34g9WBX5I/qE1IEct
ay1jcqOe0Tz6SRW7oBAqpfxqGPSpA5A9y6i3senHEBxYP8KUoXrpb/Zj48WsZ+MvFi38nXstbuv7
p18fnck9aNHrl6RZZuah7PBpi0HiJoOuXJLN647VD7qytEYof995f3yNj0VMXvc0AxyxtsuHGLYc
M58qVYW2xIikXw7mzF95DXCqsXiMNxrCzIOAZqH6YsVwqnjri9g8niYjg1OPC2Xaru6+ohWMpUc9
KVtqvP01nbemece7CqFVPFyWiFutDrUT4kbsRS5Jx4YM9aTHxi/TmZ9+fZ9MhgJIKREpRmGSgd9m
oO56bEQLz13CFArbz9WRUAaWftwV1czyw3i2ptn3pUbKeizZRX0C1n/VXqxGCMPJYQ5nm78qYC2W
wGQBEzWp22ny9RFpL++0gG0SxMSrYKvlWxxsN9NQW0kalYEH7v7ec+bl2XRUOm6cieRd2Y9Xd2rT
3T+vvTY6NqmZJQWBwGYmndMUfAM2Mq13Ni0nwPO3QvuCgC+1GKVcFHNjSdN0l95ZGVmTKP93rxW/
rRPE6QHwJRW2mnBYyenu4SApjNBfeQ6rD/PKTmebRpOeoa6UNNKeqNYtRL2B2FfFYFb9jZprNZAZ
BC6yx1tYUtBIZRaCIpGeFljllm/Vw4QkhBG2OPeV8JwAgegm5l2tZAipbHFPxw2ixORWXxxr8EJb
V7f4thcC1g6zSrZ6Ik63JKo3HzQxfakBxO0JOh9iHkmYSblMhfX03RBytZu8ngmwdU1IkxJlMlbC
WO7gxkxF9Q32lyBfoyXFkYD/PesPFZV97DYasNwDchz+SSNavsXR7j33WRuo0w+05xwTMW1k4TFS
A/m1QPMZWJTU+sggkYQIZNHob9rHBVZi8C2FSQHfe4hNLacUlfrbSc4r5yHE5lquOsJyA8VUhXkM
Gkccf2p+3xlKm85mIZ10NwqWdgb11fUt9JXc13iomYC/eW7rv6wFDB2jx9FfNRtj6tx0rusY4bf9
o9S+mah73qudHPHxJWSOcROhu2cxMC52HCaMbrKiuy4QJcd6qUBikFNCpvqDzyLxaLgRksb5hsN8
US7r0ofmOflKSfUSgl9Uvxw7ThS9T0adWfBBXE72krbW9MKZlRGkWTKK5JmlLTBUUqqtuW3/fgc5
kU3dKpVuV/fEKt91bRp6QTPnJMal904FkGSwDopaxhdvDlVhR26SueGJDQvTTeIe9qgtZ1FD7BdR
MDbjGNzPrFBN5nMheR3m3dfDJ2hx3vog0ct+n+O22ZJjM+3Z8svqWX28nRw+Vn0HPF35j2EK4YC8
MuyOqF1AbJ+pzaM/59sfGZ5jmf7XPMcqFV6PmbSvWHUoOPT/I0HZelXnW9CFcX9DPeeMNyrThbFB
Fqk1DnEUmCswazX0XvrlB6y66Fvpii/lo8vQyvx6rWwWbpZl1RPC8+511MebOhBPnciClMUxS1iP
MO2t/zfD+VXdFk2/55h2QXuxdvY2TM9ZbbCkjnf0jmFlj5KhJX7uSEjzpkUOAVzXMSdtYhxZkz4A
g8YHq4BlrVWNdnr4IxQZkle5Klof0dHVN4BYVG9X3Ife2wPhbv+Jc1UFoss8OF5j6X2gIsnsyb11
uzSwmK89B+VGwcd0gz4NN9vjxbZyuYyFCp6WwX/IOVqZ5YYOcGkm4DRGvxTJ1CaMXm4C12vvWzkB
jOSPrxhzXgpBDoUm3jHfsKfpy7O1v1gHgnCVBN/IvMVmNDyF7YTorXSw5gHfDC9aP3xq6+P17mc4
K783Q85qSaveVfkKeGzVPwr8tSXXQ60ws6YKc63PQmNQMysOMq2FpqExvByVrHF8+CCLkQzunUiG
vWvIfTfXgEansf4C7QMYMwwin6EN2x148yX2ZfbA+ls4TtKXlZ0WQ13GmidlGxjQ3LoJmvxkI/gI
vLfTeXNNqJesBABzJqcQxXJFNXR8M7Ry/OwQx0bXgrinBPtH8AibILgE41d4u7f2Rt2J1Zr7zyoB
2tz5wwrfkRoCBW/Jf6wvHJaIKFEYDx/IcWmuEuIJ14kyRreaZNDsxjFFeHsYS9M3SbnkSrrjmcWg
huCG74N5ZI+k3yNSr/lENYpWLpMg13g6RLSGaNaRQ72+hWnzgu1F5Rz+i683kN8vAJmVsUGWRDKQ
mzF6zXLgPCLraHJD65Aov+fd/ovktuP4w65zndGShx7Q36wScrvI47xBP0XvYgyu/l1TAjXJxD0P
LqRn0pKbapwO2GgpIBjWeL3oqYq9Mq6/fXSvSPJVsbpzZrnvSBD21fbHFo0fsT1i8DLF0wWChTXt
6CJKKN8XecO7znQpq3FduC5kuMOLq50lC3PE0A3DDxjgbfpr1UI/QDpVWsyQFh9d1mP+kJMLJgmu
6T6sKZiS1nIn16vu8uBRSGk6sFJP9Von6KN50oSMKBoHasyInB14W2CA4s1VWCucqWScOps49J/g
X8JZ0ZEMAlQqhSJW/WAtDlYZ1bOHS0cG4uKM6bfJGTIGXoPj7okSlRSdNZAZ6dqCN/f3WHgXRY09
0W2TNtbpJGdvvNicA3kChoYmesXlU58v3GJMy4cw+eZLwJ75IOgRvfkThReTX7VI1XRcNbagslFD
PGICbcJYbpuOEVgaug7KKOSF3OrPM5vleOVlEsnA2oYFh735ddf0LskmdG2Wn9ifuhq3GuQ3ULyV
i4kw1jw1cA23zG92tWSilEigd+VMlSARMZ+awwq6mfgi8IZromCIajraOGpsk9bEhzsojTQnaTb3
Xn8xuiE3lMvUWZnmnAs1GSKUkAwbUzgn2QvDVi7ulpJP62AMmvURkIBBw7icIO4btzcfXmnjZUj2
/ynwFOjLXQEL2vbtVi98aC2zxVmTqqTncClTU5s/Sxjc0WOUJXPY6ygZToGi6iymg2VoT2jFpg7M
ys7JYsNnjb/Cr9DQvLczaUl4+puwVXBJbXlkUCSXm3FJkedasUBWlV6KKA339Te4jKemmCDGcbN0
Jh2YbxxSQdxY32lZm8ccwvIWiSQoXOLlWodnOl6r1YmMsbAJbpRRNGd7yIcjp/lAqXyf8ZYejnqP
rlM++HSuyTCw9wWDsI79zFdGTfA8G2HagCh4y38zekbplznA8EpZZ7UQccXWrLcq5c4UiSHaNu7Q
JpcFnJpHo3CCby/c4Pau2A8Zg4THSBQlEB8M/jjTxnYIakHqKuiYSDyJis+fV1zJ+xZBDg1aSRlO
u4wNJuyubGcS8DcOZ6KFPyr6X96KZvoQ+wUPfZ/onnkFWKdbx7ejr4r3PXyL8XjuZ22dJR65+8p9
FFDtYurSVCBw3RUNqMkE4cRDhHXdQYqINuLayi/zAQB/C8fGx3/AY3RUTs96XMswAmTY7IUFjBbJ
YLK+6iwZ7qwoKwsnV5HF3ThcrjidNJdAYfMmd8vSa5lCCMyEj1WSrcLf80Y9CvygziJoxIK4EnGw
j91eSyuXSA3hVXqoJjj98GxvInjjhIq5hdzLE1OQJHjzZ8e65EFj84arO0/ojfJgZBg7Tr5wCmE6
eiNhzKDJN/0Cl+y4xJBV9v8qukSGzkg38GuQs4DpL9gxPrrvIYqPIO9RBoK9l+vvBjmyUJzxJGpz
3RJn5GS6s5KwYWWrcx1ErNVpayfDPJyzIQV8YoLc+dOkKN8MP7RtmFyYjBiC1T0z8xG4HumMkQRg
onsP1kCDh899VBx4QqGaW88b3BCJrsmDtW5ZzA0N8bRofgBN2/26McWN1Wl4CJypbgfk+oWDHEN+
Ko2PmfdiVWMz4tHJ31ieh8JXG8idLrRUa33YYPI7HLgfRvV1bCjcdl+hblqajNw272Ce0eT8bx3E
xWA68LXkgMnVDNCgLqbJXKBBkBKWG3/o0SlI0Jxkk22ccmQWjctO1TmIiP+4Tgg57QO69gz35nFR
GhmtTMx0bSvA5fnUkQkRkJLuL0roxP8cPh6zNNwsLozC6jUyvAopA/1o6Lt37j3/1jLdVK/d4XxU
alfz1qlHWSEjVX0lEt0EGmwXf4loDOO7uzf/IBRwJX4dld7lgMkoaAFiVUpjxh/69HCYCoGlP8Dv
1KsVf9b+EaqoQgthLFOZdk4papxTq+KQJwDB5EhZiRRUqD6e1sO9NeCWFVQt5CJGkUrn/JgYnEsw
IlDGRmREHoT7h3+JmmsV2G8HxAillxusbVfRpJGmgjctI+5UJeioPmEyFi0j2NkGCmV9ABBpZVLT
IMs5R6SNpEQeGv1DaaUYedpHl3iRlh71F4BwH/XTtCzCQx9DfLWpLCTmzDj7x0LA9m9QE20JugZK
xB2gYAW3BcstAWjwqwzzVpiOsVNtLvMo1bR1nyxPjAUIrgSQPM4ITHZWdtPlRN9DCQsSUg5Kyo2k
BZsydI9S5404JL4LigYKj7cLHrLHZKG0/Q2GdQ+FJTTe4euOVvjxW0Cd637BFZHDdzN8l/ll5Ghs
B80kbSYmZpmiFLbb6b7paKzRBE+AkZHzjCTFwopYj7I4FY0B9bA5gdBI/vV0neEf0mhhzGkxx1OP
mM+7/gJA11zJTU8EsiOKO7hG90YQuo0IrwmEUdFuFtPdGLp+br5jfJocP+fA8pViOnroQoN/fL/j
d7TDb19P9+nzs/3ij1UiaTsgELG6TrEiXy2DMJ2W8/sY8n8QQnUBt/F/RHmAEzLON0oCKz5rFl0a
9a6rmGfmjhnFl7yKVvkSvQ6kl4/ouJ8IGNZDaJ63DAWeXZoO03WrKfxk0p8nunfzXRlaPR2w95Cq
1GOwpgT72I8Kq6fRop9Hyn50yunI+yO33fXTdO2vJPoMC4tsYEyiJDnM3Zs9VmEWpJm68r83HQ6+
frRKzng4bgWy32JlZL4UBHEmRTh9m7QCoUwy1jBWDVIrbav14f/VhFEVeqPPzyjQMeCwiEB+Ws8K
KReWOMK+DhvyR0fS7+rYtzIc+V4jk0QFKh5seQrimBUO2OoZqF20HeUiYeOygiQKtM6vj1SYiGs6
TelQ5JoYqcrBPcKfPDIvO/UcER6qX0j81mSz4QrbijToMxD+NstKPEzGn2MyOwIx5LdBXhEsc8vq
+G9zIcXxko3/VVD+BiM6lopCN+vpdEVttFg7yTCCKzO8SEw0f007xr0DGFk/1KxDuxmhNBdnBk3f
bR3Z1DmnetZ+LbrWsWfOigAb0S1rzcDvgfMzWtz4UAdiSllo7usgACFJlwxi38r12oLVY2m7Vk4w
U8Zb4U7SdY3LDVVvy7nKnnA5Nc9IBI1najXesq9fkeXDheZ6qzj+8Bq9s/2WqsTJXYnkiMsek0JX
yE1dUkvC227Qt+hvqUwZgWPkwLZp9mL02X7I9Leh3gH2AMLYAdIbb0KegIbN+N6dlVJyjcZXfOuX
jT6rvA11GSV8i6F7TwDufziMvtFtNVf5Pv/dzw7uxSf6AramZ1zTW4Nc3nPvc+y4nAzEcDBsSV4K
Kd6wnm2JxT1+lthtctVKi457dxKmwbxGx1Evydn3h8WPsWFGYDHloosdKLQRo4ICMS6rxCyDjuzY
9PcVVW/k4tj8JO1gvSKhIewm+EsJ5oAz206zIQa44mmPiBs2I7kaRKSl+254KQ/XPVLRkokn3ya4
T+wbY7DNqENAxFzjeImQeomJ6Z9lGDZRmHLzGigbLmg5YJe5TcbBBJKWBW8m/1MbVN6ulG9/tlDL
XWsXnKCBPh8X5p7ThoyoBeuBadi0B4Ru0ABASvVJJD+tp76WSDpEQktbK89tSBS12jVHbYzkCqZ9
2A9ssaQZU640AUef9VmgGCglUxmph1v3Bqs+KXDBWw/lndxTuJFxK6XRwzqi64q/wPi0yWaNYNPE
WYFzpO/zTstKq2lO2lN6MFzXAhzIGUbOTOyv4mDI2bXKDnJtCgTZEcF66wV9Ngb0505/sUNpzOz1
S9PNHUf+qPzeZgTI0ydOsDr2BMXQ/oU+KU9q3DsM5fisjCIZaeeVyvERE/kcOUVaGTvjtjruaVw2
3ZG6CIji/MhTtTV9P6rNq71ficMct/ksX0uv8DspX27LlCMBjkuP6UgNJdfAVPu1R3yiBtLSEfgQ
LIxZK3jqRgqBXJ9JzTz80/iBoXkqeBqLVZLOwQKgr2ZtWa8YahS3ZRDX2R7Bjww6LM/7PCjdP5iI
BKU0GXWxmHZdnVeSqQpKREy5CYLbNfVgpmeLe4g0RElkq1bhSAau665iX7Ohj79S6n4SARptGO2V
FB8aVLDyFzpQqkoLxmIP3MyYug0a8RlBtVtJQwYPQ/o2L1TY/1UeJTujxVwVN24m3qLs+Xw2Ettb
yfxyKgPxJnSY61kE3lnkM81+piZ5vuDLMimhNWOaxOiMgW5kQkeZMMUBCLcRVuWGVK314yvnudED
9IcCsn2QPbtjmF58s6I2CUPOLTRgntor7UaonUSe9/xzgj1pi9MI2OcbQIzhrLEEK/MKvlAf1xPD
yUl9Yj9wFzOqXaENqMrK8ASsM3lfrjIPm632WCesRFCnKsxQlDC00DQJoXKtN1DZUAqd9PB2KT5U
DEVziOLstIomHJTM9lywRMta5zQTX1GXwd9YHTeok5QS3t0+auLTsmpaZPxdwllemJxR0j/PM0so
ANyuuxr60yl8r7ApQGdk3yYEMeDLWvSkfeVqlEZWG5TlA4xygoK1V5G1zv1vEBQ5l6y2YXlgHvin
92txFNqNirxmMV6h0Xtl5+T97J8FoeQS2KJiwOALelTZtaBTBkLTBNh0ixR8bsiYo3bEgjBDb7tg
9xEjOX5ZhekjUyFtW6ltunjJLB2Ds3iT7Ua+Y8EmH4Tr5DdvWrrjN6nKaZmwIxyvDlDSvX5qFGRR
udMHDrlFAcBL/lDwfAg0may9ZfF4rk7N2v3dGrr4uxYXHUeU6JUzjHVnO96XoBVOMEVOYn2YL5H/
Hdb/Jx7R4Ff0Kw930WwvqU0bWX4bRWlBoZAYPIuYhvZNJGcXxwDIv2dabuakDzLF2oL23Apluoi9
J1tSEb6H8VHfQeU9dtTlDVzkFUDqunbUAmpQ1VvV4lLaJbUREzPTj400JYP5QA6RAVABnF6EvZS5
kpUD/pYuY/fn4eW3cPNj8t1Eyed2FdaSpySRKAEuUmrrrC+Upu5p4ZzTSKHCBO/AlFv2Br080IbA
QVEIgWGhTmkFTqbSQ3kecT/wbK8YE3x4o8X66qmA+HxuvsNoRg0AbeDWlMWWe2EyiJ+XWJGfMP/r
ZppS9TtVoDkpdWY40oCOSzXI5Opmrvi5+qZUX+lSKcITt4Thki75QlOreBkVI4ZprQATK26R7Upv
N4qNHZegb14Lc1UH4L7HksvMHpfFpk5a5f5BCP2ohA2DcuAJ2KopebjZ4HFuEJAYT0iMQHuaafJK
J7PLB2J4E2bhYW+Hv5Ww+GcovPIyQVPq0kX/IFBPgI/VoyBIC+rGJZsoXPqbIYBKZtsl9GCTMyFp
qAsFenm1Erc97GEHWuiTVobu9S9XMkTAAyZN36i0hERNyUsG2jPMqsS1JLMfw5whPDRc0+eZSf2x
1GelOi8OZWIH/ZVKZdvTiKmdaMLH3lzNMSdtpnsltxKSbzD1CgjLiuutEAjRbH3o70Qivtfyv/Nd
g5kPro2JkDLxhRN+3eFcr+UmdZNKrHNk2lZ0qUMIGWAaeWZmFPzokxv3wtKSmCQ5NUeWka352nEO
irhRFsaiEcBBR5jUXRzU6Kx6Jrgrn1q4YqrA+KAz5ASvoXB7lM2Wwbfzwp4JxV6qTEClEBo7AziP
62IFnZxhvRYUyg/FFepRq3ZpC7M8SbX/68sEIDiu0LwkXgzFtfGm1R+LVT9eFgNZNGpJaPag5WIV
Qgsj56n052xNmxDV+0CfG0DA1JShEvCoHNm2Fnr/738vwGt5/expl1+vIoioVGj6Vbf3KZJ5HGMS
/bFwK6H8Xs2oY4SDg5xSCYPeiEIU1U8s5ZOkfR8RYF5rAVX46jYUO9zAwVPNQqUt+LDs4W8rdNoB
b1gp9BWtiSFxTnOpRREiwVDAS8X4AjbP6ARvRjWeZPTfW58RfpglcQpAOxmTbaO1t6bEm/qffN7R
XQqL1YV4+37vwSpZ5LryMCdM7xkUAAFycSQyutIgNgHgCzmjOwCmFJU4Cujg7Bz8qFqMr+09WHac
XzxtFkPAhbHI0W/mTrLS24r7V3bFF0l2WzTuDsqFhOeXI+zwTcoPUz6sjWJdtRYQADPB1XnU3UkS
VhSADMxpSN6xM9xvTzzzm0Zw91w4mfrQLy7pVUxDgJJo5OjcGUhAmEer3rQlpGL1ZcYFctSqyOoV
iT4DfWRKyVkq+AMPOoHQ3lCB+OtlAvHbe54l68zOoftGoTsQ25hzlL9k3jG0L572aQY3qGm3uCDY
5R5xnc1BpwlGVJQX+O9Oi6/Mz1VGqxBayKgXUXd1xj7hLNVbx6abbGM9u+lpOni7EzJ3UY0XJm7c
B7M8siajJlXJl6hGL+dsOiNtNYrMiWOzZ8zn/zyGkeg6TL2XllX9NlbStyyDwgTB7AuH16EpQVT3
EPzuac23gNbKKJusE70p3KMVb5lDbTPQY6Z19pRmcDzVHMOcaI7AQ0M5nqL82G8Uf+/l5TNiqSrP
5F72zHreyr/frFXRQ9FAV6YDILEvW+8KlHQIrFZmLBXRKqjzOiLZ3Ollom8OS1e9Ip1tNOlknzKT
IG8cAzzM30MmwOfPhT85kRQGkHBNAo7Yz1hndJo3UJd+9sZ9XhWZVRwEGKVHfZA/qU6q0cXfuWsV
7WkGJfe8OnibPdxQYTbaZhYwQnvdZYLsECXZHGQh4tYWxP+MZnAcYA4OOLGghytdzQCjLfWj/SkX
z419aj6r9QBsE9ajZLetsTPqOMcBotorNe+c65BGydjhJTFZlAqigxlEczX4ZQ8xUCPDBwuufAe5
eK/Mb5j0cvK6TL4u3TdlU6pidVOeCM26I8aE5ENvncDm3bNKDoeuTt8qULw55hkYlcAhpnSgmcMy
w47l85NQVno2UchYm3UhYa6rclghrsCkcVYaDJdFbc1gxMACYMytsE4lDIr5/IDBeiom84wHj6yA
knjHvKkH275+8Pmqx9vsItvsdYFnLi6cOzaEQKvlaNZkFMkCmOMh9oJ/us3626bA6uEDHzaLv/Hm
XbMnG4mayxI2Aj67EduyYBla7dCBNzeM/Wfm54C3i5/SllIP5yo0XHLVS7Fev0TfNT92gEg+SGPZ
5qf5qNsxQ2TG+EIxeHEQTHjoAG0IApj9RtmEQaFtpkDVYhUfptQ+4BaT4I0piMG5NxbMfpO9v+Jg
Swi0RWHjgAqxBcRTzuqnZUWRLPwCoDlem6zdLit84QVvN5eeKZ+GP7bQOC6uCCUZIgiLKX75y2sh
bNal9Hvjzg1Bk/3sgbuU2DA1DyAWEV6Kv5E916JkKnxzMcmbhgmaK9zAlBSUskxt812t5/c6ZE2t
d4TW4m89nhBxnh/ykgV3Sfl1nPCEBWpmX0mWfbb07NdUZ7wsaSW3aP3i/fgRpS80f6VrJiWAXR82
vTrWzeEfrDgEHcaPl+cIpcOW6k3bNeTxoXkhpUTR58W3wFnzF9dCMeaQHmkfGgnk4Jeo0rRWw55u
VUwzwQ5gYRt28KQoJcAh3cR6Hhw6XnveUb5esFfVOlTmlbk6EBKUg79E1lZ8aPZGqJ8G2ov5OVyr
4b9xVVulBEOPa26lcuAnEao69wdEO9slq1k0ftZv3AWi54RY8tkog/Y7MDSb09c5JZls0Qa96P8/
Gd/wzdhxBjPxWE2LaRNdY9hWUK9wJToDPEZ/bnU0/YAd18j+RVAjUBazgdQNB4fOO2BsRupzTMh9
E5JFgEPZ43AFoOSCm93RK3IvhCygUggqFs1PA/yX0qAztpXdaHAMelIbq8bSk6sOi0OMFzIPcDv2
6tf5cNEP/s5PaTb7V2LZCDQzQGhdGAOUckJlIut5h/QNN3O001kBr6DH+kg8ugEJfBqoilzb3VlY
TBPnAEE70F1h2ibfkmcrajUbVyWlF0c4frIm8XyiOxfijh2AkgOqzRbMLWCGzE/AmoriXWnZVziW
HT5tXZ5FdfwUtJhJ1xK38uoQZi+kMN+9U5Ccc+ptnYniW5pWQu6F9KzJarfbW+lDPMzyjObbIz7e
Cie/5OXEMii3S+m/HENB13/J1WFNfvLmVXw8baoqy9nuGZ67ryvWPf0gSVPTxaGWawAOywJAlv0Y
6Dp9wazRdnfWFLFgdErVjWoOk0LCrHUytoLpaMoBn5bDxx5A3WROxt6dUESG6iu7EnFeWVs5e0+y
vGnoQXZT9nT+mk8DvtL4KVNJqiFRC7V17/fxaxb5yyrOjCFskS9aqsLLZgafAyKbNKfuYcilElja
DubR+Egrnmqkml01vDwnIClaQIsiB/c95M2Pb6lzPneDkRBiM4/CreZfwICBGzEBEJ9YP91zA5Fz
sTPNBPZwYABinQXZU/fSRYlBxA==
`protect end_protected
| mit |
bgottschall/reloc | zedboard_example/zedboard_example.srcs/sources_1/bd/BD_PR_3/hdl/BD_PR_3_wrapper.vhd | 1 | 8354 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Aug 5 18:37:52 2017
--Host : knuff running 64-bit Debian GNU/Linux 9.0 (stretch)
--Command : generate_target BD_PR_3_wrapper.bd
--Design : BD_PR_3_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BD_PR_3_wrapper is
port (
AXIS_CLK : out STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
m_axis_data_0_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_0_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_data_0_tlast : out STD_LOGIC;
m_axis_data_0_tready : in STD_LOGIC;
m_axis_data_0_tvalid : out STD_LOGIC;
m_axis_data_1_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_1_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_data_1_tlast : out STD_LOGIC;
m_axis_data_1_tready : in STD_LOGIC;
m_axis_data_1_tvalid : out STD_LOGIC;
m_axis_data_2_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_2_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_data_2_tlast : out STD_LOGIC;
m_axis_data_2_tready : in STD_LOGIC;
m_axis_data_2_tvalid : out STD_LOGIC;
s_axis_data_0_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_data_0_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_data_0_tlast : in STD_LOGIC;
s_axis_data_0_tready : out STD_LOGIC;
s_axis_data_0_tvalid : in STD_LOGIC;
s_axis_data_1_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_data_1_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_data_1_tlast : in STD_LOGIC;
s_axis_data_1_tready : out STD_LOGIC;
s_axis_data_1_tvalid : in STD_LOGIC;
s_axis_data_2_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_data_2_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_data_2_tlast : in STD_LOGIC;
s_axis_data_2_tready : out STD_LOGIC;
s_axis_data_2_tvalid : in STD_LOGIC
);
end BD_PR_3_wrapper;
architecture STRUCTURE of BD_PR_3_wrapper is
component BD_PR_3 is
port (
m_axis_data_0_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_0_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_data_0_tlast : out STD_LOGIC;
m_axis_data_0_tready : in STD_LOGIC;
m_axis_data_0_tvalid : out STD_LOGIC;
m_axis_data_1_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_1_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_data_1_tlast : out STD_LOGIC;
m_axis_data_1_tready : in STD_LOGIC;
m_axis_data_1_tvalid : out STD_LOGIC;
m_axis_data_2_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_2_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_data_2_tlast : out STD_LOGIC;
m_axis_data_2_tready : in STD_LOGIC;
m_axis_data_2_tvalid : out STD_LOGIC;
s_axis_data_0_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_data_0_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_data_0_tlast : in STD_LOGIC;
s_axis_data_0_tready : out STD_LOGIC;
s_axis_data_0_tvalid : in STD_LOGIC;
s_axis_data_1_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_data_1_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_data_1_tlast : in STD_LOGIC;
s_axis_data_1_tready : out STD_LOGIC;
s_axis_data_1_tvalid : in STD_LOGIC;
s_axis_data_2_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_data_2_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_data_2_tlast : in STD_LOGIC;
s_axis_data_2_tready : out STD_LOGIC;
s_axis_data_2_tvalid : in STD_LOGIC;
AXIS_CLK : out STD_LOGIC;
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component BD_PR_3;
begin
BD_PR_3_i: component BD_PR_3
port map (
AXIS_CLK => AXIS_CLK,
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
m_axis_data_0_tdata(31 downto 0) => m_axis_data_0_tdata(31 downto 0),
m_axis_data_0_tkeep(3 downto 0) => m_axis_data_0_tkeep(3 downto 0),
m_axis_data_0_tlast => m_axis_data_0_tlast,
m_axis_data_0_tready => m_axis_data_0_tready,
m_axis_data_0_tvalid => m_axis_data_0_tvalid,
m_axis_data_1_tdata(31 downto 0) => m_axis_data_1_tdata(31 downto 0),
m_axis_data_1_tkeep(3 downto 0) => m_axis_data_1_tkeep(3 downto 0),
m_axis_data_1_tlast => m_axis_data_1_tlast,
m_axis_data_1_tready => m_axis_data_1_tready,
m_axis_data_1_tvalid => m_axis_data_1_tvalid,
m_axis_data_2_tdata(31 downto 0) => m_axis_data_2_tdata(31 downto 0),
m_axis_data_2_tkeep(3 downto 0) => m_axis_data_2_tkeep(3 downto 0),
m_axis_data_2_tlast => m_axis_data_2_tlast,
m_axis_data_2_tready => m_axis_data_2_tready,
m_axis_data_2_tvalid => m_axis_data_2_tvalid,
s_axis_data_0_tdata(31 downto 0) => s_axis_data_0_tdata(31 downto 0),
s_axis_data_0_tkeep(3 downto 0) => s_axis_data_0_tkeep(3 downto 0),
s_axis_data_0_tlast => s_axis_data_0_tlast,
s_axis_data_0_tready => s_axis_data_0_tready,
s_axis_data_0_tvalid => s_axis_data_0_tvalid,
s_axis_data_1_tdata(31 downto 0) => s_axis_data_1_tdata(31 downto 0),
s_axis_data_1_tkeep(3 downto 0) => s_axis_data_1_tkeep(3 downto 0),
s_axis_data_1_tlast => s_axis_data_1_tlast,
s_axis_data_1_tready => s_axis_data_1_tready,
s_axis_data_1_tvalid => s_axis_data_1_tvalid,
s_axis_data_2_tdata(31 downto 0) => s_axis_data_2_tdata(31 downto 0),
s_axis_data_2_tkeep(3 downto 0) => s_axis_data_2_tkeep(3 downto 0),
s_axis_data_2_tlast => s_axis_data_2_tlast,
s_axis_data_2_tready => s_axis_data_2_tready,
s_axis_data_2_tvalid => s_axis_data_2_tvalid
);
end STRUCTURE;
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/rd_dc_fwft_ext_as.vhd | 19 | 12811 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
SPpb0sHtYr+7D0Z/NdHkBGKHFj6bPnAk4zCT9Qd9jSi/NZdzqHWXjKwgFh3NrYG/AQMVJcT4R9KU
T1kWm6bsuw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
PM0w38wqoKZTqxD5ZMv+He7u+x4mAKOhS9vNWqYsLtlMu2ni98hkp4Js0D7iFCQdcFCu3Jaj2Vqe
E0m1H+UGB6We+zPa+TnTKUC9+mxtEW7xpi8i+GVKfIfe89n3euEibIBIS0WLtZypuPRjuzr2TWw/
TpBFYS1oUTQ1qwWguI8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OIEbVz6QJBHT228fhImFLc7Q94gbSg/QOSgeKpAp1zRCxot1azeNL0EHN3pwZU9Qs6kuTNEAn7+w
agqdilWN9rl3uQlRBfW5KbIj2khza90rK/4UYrbcPGQyMxF8l/LBS9RaSzH8pqlJgQ4YfgwGNaq6
EHHkNL7CBEprP8VBO3A9geAIYBWstNirz3P/01jzH8PT87csZHkt/KV+1ancvBdl8zy3Pi5RrOtK
WdR5qLkbXJ6m4DjaubrW8HdK/fqusuCVkVGxmajuQw899iRpx5AiTEwKYKOor3msJGxdK7STL4ZT
S1m+Ec1GdsxDwYBgiKT0A3c1/unIYBS6y17V2A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Y9qoE+tEhAFEsAZgxeFxNUflksEoY80RYly6rjz4X/QwncMYkOdY5w8AxmW4IYZfWprQfyfkxMrN
8JuXogLHC84iIPhEFIhJ/+RivFHW4gCUIf9NTOGEkQza7hd31B0/7LZttbZHcfTR5stmYGMhB9xi
VCriwe4C9iR9zFvOJxk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eCcOM7HngIZB2JCDRQ//SPPOptJbtDQ6WJM03A6xR3t8OhM7+MFavTdB4aR11UrppwUsYiZCHTBc
4AdaSSNbTEcILhRaZMNZ85hgqiNgFb3YTJu8ZIWifM+Ad5U1zkzbH1xsVssRl/Sl+cf+TCDh9Psd
UOpjIzWfsyGgyfaSSbczC/DMklBqFcyspqzOP0YGdgI4It3e5xnwDvYeewRqIZggj0RyjkJH8PxJ
o1XlyTZFQZIIFN0x8sDbcPdsUekU3pOCvI9JK89jigNzKmLJRotLEgZQt0B8gMiz/gm5u0+k01OA
f/7Xo9TSexSaZ5evmswsNTBQhg4v8j39bgkh9Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7744)
`protect data_block
5c14H3XnHn6oO1IeyUW2iFvZzZ9cCnGgzIUu3xjh8e5xy/i+86IXlWbx5i2mlzzGRsVALU6t0f5I
QeLGf6AbkZ3hlwUCPMwVm2NmJK02qmRODGZiQlWi86n7suSZCs63ZjJ8pPnlCAQn8FaAgD+sgU+U
LVJSO14ZQJdmeB9GkCpHLzCfmtn8G9pebF+4tvm+oH1Uj6EAIKVfWPjUewpmjHF89f+d8S2xkvls
d6F1pZhG0Miog0UYG98SqUR6cD8feORy/6KXrmhEBqlx5N1uGyRpBmcg4JnW7T4/l28UxSeLzrgI
4U4PONALlPBLOVnyVaJS2p9a6dmHqVwxrzpygh4ePWkz8aQCV23fCBCRex9yZdPwsXD5KBoAtTOV
e8m6hpUgMopGSCe/ZgYGMJb5h5Ug1v77eD5d6E5Tec6ZV1BBzld41Me5gj4RFU/7nM7Zeqx65sQv
2QrqR8YAmfROrLQk6fvAiDvNCn81ulN/k0mUUx77ADvCzqU2vNzog4QhdiTvV6BwSiQyVhLExOAT
RP9xun9p56pDh5dbI507yrklnIOT+S+ZwHcpBNEswTZsn9Tz5O8Izrk0z1HfI7y5064+Phb4LNAg
iJ52UgStrHi6fIcPLqF+nI0q4L80u2nS4VwuaD880mWYCx0rB89Q8U47GVQFUwE+Et3pto+6HnDR
zBJPxRBs0/nBwZrTyibxOTfQlrVttYxiXEEQrBs75MmUf5VUnPUcvumnaaBLLy3CnPHGFqUV9hyB
7QfbtWxmBfEcFZpLIJ3DEEd6LBdklewU8RePNbtw6eSxJIzz2qg8Z9nC538q0h3Tl4QrcEO/Mk3V
/EdZ3Uk2f+62flnxW7FfOJYVt97Spa9FVTDxZ5Wgshd+IBYPh7nUc7xSe2mzU7VJxE/GLzavxO75
I3XoeiB1XDWZm3TCQE94c2E6WW0IaO1MptHx1atHjIn4irTOMQHFpngzfn5J6Boyhh4/Yr9VB2NK
a9HBu8cqZODx9oW+/jH9/7EEKhTeQebSHO79mjsqRG6LZdS/sk7qo+rEyAYv7YZohW/cVu8bGZIq
k1cXJS1QBCudOnZzIJh+TaMtrVAtxdlqxUsTxCA5vuyf6weMiYdFIzna751iKfkRRDLJ83dAyHmz
9iv/fXQGP90Xi85xe8AC2gyzrDQGCJW5G/x2uLokQiKUu7NzqoPvLWQsLIXCjPOaHkjtcS3ncdiA
vDhbCIys7eWECB3nTAr9CFCaXWi9Sia5MQ57SGoaRP731iJrqdQwPrXG+2fczOptpWA5jjtHEO9S
H2SuBg5ZHOgBHnmqNE68npxq5dX2BGoYV77/gOJjNMT8maS0ZPmDN/OHFuqWL4uWGbI1xogG+exe
WQygKkUbkqedsoeKd0mwWsxUenSMqmILUkjYEoxz41pevqFRkKbHuX/mO+ZxaBzzZ0ScsYPKGDGU
p8+i4m2c07sQ8f7PmgkR5x3zbQNNNysim8a85mNC4KYxHMXTFc3dALcIbUpu31cLczOpb2Q5u2SE
Snl0l8Hd0YWglpJrBg8NpKyzXFnTtK/1fU1x6HhObOe3WE4kKXLv4iFvAHWxRyMUTeDOTa0mdI6C
Pqo+ZITRzKpyG7k9pSp8gN95su3ofhmm37L7jWqEilb3qXor09HAuJTld34C7obfC2OWRTaj85L/
SE46aTHHxfb4MQx2DcVYtaqeMi9cBx5z0BgvqwNcIQxuYt59WgWH8QV3zi79EDB8bhwTuZxNSdGX
FfcnCFvq7ntDqOqUoy7PRPo0zTeywPqzDWQe0LCSW9qQMSkCbjSP2JKi9bVsPW+V8avobRCE1Tgd
jxTEFRYiJWrNXgo961FaMuyrxs8215iMEN5QTdpeqxTbdU2MtMmMHEiEqvjlBrhDiWLw8GYS90dM
sb/IK53ooAF8QVxjWp9tJpodQigYKNwEuMl0inrhMAgU+SRXPPWiavciUPCb5drTK6BboVdcXHil
PNmBSF3HniyDVT3iDkPmsgMseJewzXdJnkrlT3mNfLKeNP1SSEjQVbbUwU/iS6vuupbU1YPjmb5G
QUmJ0sX9O4xS8VkkcUSMGtPtzqXlulgXV8CM1VKzZrNa/C2uFyU3y3xuaVkz9br/Tf4O8sNIz3t2
9wtU0zkoC4RuJbnhn42zJmTQU3OZtyX0tiPQhBC9lPA9bUjqUVj5epeOdamKSe9dzb5vw1iHIDS6
kLRuRSbCuOCOtzarozdpmpZIMu2vkiWJQ8ns69jgiiMctt0nH6dZjc78GcXZj2eUG7ELRJMw2oXH
IWGGL7X13RNv+/ih1RDuJ7SfPtb+vHooCWwmH3vZsGb/oITNg70+PpuXZU/Wi0Gv6Vrqr868Qv0/
n8O7U1ki146Rgd5tv98JSv0g7eucYuENzW1UbfAeuexUD/tOMbifJMg4fdm0A5ugrRJqt3V1qRRa
y5YHSOvhbVQYQtpU8qeLw12NSwedrQrKbT3EB4bfVsDHeFDBSrIGO/RrmNg/2ni9g3MI4ExruoKL
+GmlIPivWj/RWL4zjOErkN8paHTpER5QFduI+OoQP96NLOBEZeeUjEWjq5afJSCGv+O3NIDsYLWr
PcCZu2iHkLXwLC/JP2KeBnbWpAbouXFuZOIELIb2R3EwoafsvDq7gY+mNJH8VpzbG5Ie/j6UTXHC
/ZbMIz1vnQ4maU0hAoXs7Keen5bx/D28sS1RsYPHq+szPSGdzPNhGaqeQ4UjSYyeVo1nh7+Gr7z0
CdRzzwQSHUo9PWG/0IQ4VgTk5mQ67AcMGSiW2734tpMPS/GKsMe05uXX60mQdEkMBQFWgKKwKiKt
xs747yhJUtH2HtFEZ7THRs6rOUdOC8QWNhFJ9TAhMRKzAUziNvq7Biek9IN61T6+xDQiPennQyTq
p9S9lZmXx5wtHgyR84+5m+dLUaJMaK0o0gqYgrfzyr5J9uHaTYN8EkJOOCwWD9yv2UIcuWkrWvth
bwQCq0hb8yj79Yf94p9eeMjvjAyYHgWN4xiXAyc6KXa+nOlreuZTGxQKrsuaEuw4flmPxy3ndyJn
Vdka7+vsnvYL0Fo3Ne4rTXkzRK7XbYa9UR7P9U7H+hnnpoXPTxA14SqYsRnIt3pFysdd2VtVaJw5
T+WVzWUH78db5By9zm7zlv0p90DwecdXN6rFnVuwMmpm3Nq3NiGvGSPzIe58UlQ2ZIJy2J0dIJvT
XdHQMiEJ1vCkE5i7hYBs1pl9TlsBVwKH8XhL8XRmJTojX2MU3HUbgjdF+09nMGaXbr1oHSgwXUwC
xe6PpkChpsha7EKQrdeu7C8B+VxStvT/oRGbDVTiATcTaSE5B7Dk44VFki9JzQ03wKJBzjjOyIQH
6N2zoejjGs2v51NwsTILZm1EAqK4esOEvcIlrpTUMISMhFDfNNm/2LAsiX2HG0YKJdZbJeMoS/XY
RCEk4nH8MUOyr3ZcJ9tVeoxuza+OazXeGObr+ayKHrYCOwVtFVhBwtyFRQYoKt1qKHe3Kp9jvoIA
0mrKlB8ZyPqCVO16d8Mr3UP4T7t1EBUwLRcXbSVaQdYqkAoMvpShdBA3hLLwRl3NYWD+T2LuK6Iv
rLO7SLqf8Licd/wWToT5nZ7azrfVoZMgLaR6fx2dBGBNZoqtjolgQVWRZPzTIWjV5YAWQby39A4V
T8p+BROI4pHZ/hLe55oA8L9ofrSU9vvkADrSnecLx+rRiZeV5DBmF++OLvpga0X9y+v2HWnt5PpH
S5TVI8sAQjG3MEWcXLVRkOGFbd6fR7T6UhNe7j6391Jv/igk/jVWZUlmtAwp0XEf/cPbCLS+Fczh
vJvNIGhvduxCogdW035A5riPJPvBlFXrSnrAPJIgKVVk0YOyn1pG4SCGZLmSb2R6xmvzjYyvGmmf
OhU6PK/PeY18z9DGhXm3lj/+Aj3ek6GY17iPxD6d6uEIzcczThaC2t4p/TClmeOqsj+Axuo17y1C
FKPtpHrELNbVNf5ZCt3b6syz9V3TFjvhpWd+GUYaSVae1pNAElo94JoeG1v7daAvFp+FtW4lq8/u
yCqiTUl/YtiAfmdj86vqnQ7XEEyeXewk3zOudWei8krlH/QLvfjBkZe7iHnuDP4dfZgmzCMo6sXu
O8lj3ESK9E/WQU9R3NSDj3KSysqSv9NuylPipDkvTtkX2vqJbDBA4pTn/c8mgzTI1eJwssImF43H
zjyX0HrZMR9R58AJIlbRxdVxG4buA8K7Cc7R9fZqflL24G2y6CElejZbM6QsgAO7S3vCm2sfL9pz
w/KHPZeRai7ETCVBHtxiXTt9uDreie2HTU26WpMuzhlI3s2mErCDKqm2sz5g6HHfPmUsyPvHOsSJ
Te6k0AW4N6afrKTwFKQPRPlN032D2wgecoUE8cGnnnXPWO3g5pb6bTb7SuMy7rMX6EqDT86LY4RL
bXYZx1kjuuup8IbmcNSp4QQIvq4oekb08RFlrChM7KDB9825jLf3ZG2WJJdBT6FO3E8S3tIgopTC
nA2UR7hUsYz8wb1ZrKLtAz9gSS8bCVSLYixuYQerLQV/khG6d1L8BEqg+BRwaXjQsT0htuVAxiH5
CjoC0vJOtc3N0xu+6o14vOSXxuYqXjpHFHRjFmLtPn9AtsIrhHmo2uDAgj3sVRYUTYcwUQv6wvXP
8CWcQkmflKhjZsZFZ5ANpgpZW9vh5mnCf4kN18VP6YT/QQycckDVOiVIfhC4lQ5SrwLlzS69J4q1
Y4UExQ/7aGCQwYsF52EluNq4rK0tYNpLEE3e1oZwbnSYePh/vXnbp0z+OfGeP9jucbIrBdHJIpuq
zia6W244IruLuxZs1rWMU82qmq07mAqLHXy3fYHczahoT98piGVU5ORBYwEJHuDAiXdFCfjpQeo0
GGK1bEngb/fBTda+6wtnUfVZRwidU8B1QbRTkpOiGOcZlODOvxxcg9sO3aHhhQkKyYQ+0kvUMSIX
ePXgoOIoSDcSDPwpmrS3YTE7hAV8FzeJuNN3JEdjnmTIyKwBmmZKj/Kcfxmn6nILMYkl95rFKIlx
ucixorWznlAqkiGWaw3MAe+khdZAMba4j9uDqR8jY/BK6LCer81zay20OQi5XjmyYJXkxad/tpij
O0g6qPuSGF76Dq+wy8SmYWJ8AiAYbW1UHQHRWWRR5L2qMt8w1B+g3LKilAr412mWzRe3FQo+zZve
PJw4k6mj4A723Hm8c+A/sj65++XedC57rOS7i7GOozhWW7H8KFIV0CWkwXmCp3mHFn7SNgaCAp2I
35RTFhim73iHVHUot3YkQRA+Ut+Mc1HDjOjYAbmuE5pyjK+Y9/5dUnw4jamPxC3RhE0n0b3xD4kI
Lc/sz6PM6y7NxmItSDysysgYZMp5WTKOg26zz+GTiGIQg1r3bcSjO5+huKjxTosw9N652zNOStXa
+M443r1syNPbCyYPN8xh9XHQiUkllgL2WCzebcOt5NqPtjkavdYLfFnyZ3WGpxfvRKD117/NiiBn
EpjkaAA7NV2gcRaPHt8iE8xFSVVZdGXl98kIIi4NCTe0yvIoeuGSmKS9kZSdB7QNj1X/WUVmNy4V
wKwOcBEoPl2o3AOhOXo0/pp1SuDEdCxhYvk45E8rpEYgD0NStdtllE9gQxyW5XnOJUuYPQinDYwZ
VVpuNiLPQeZhKGNp/UoCY6xQCvMnFgyeghOJjFFXSY8wM/W2YC0na1JRqByolrALKxAR+To+OyWl
oaS2rOGB2Zk2okxrF0o66GZimJRFfyuAebNPTQQ6le8EsXUFzCBIdKJFKYO8rz5v36h4RraDjQE0
wx3FjQkZE1ce9HZkqXNSRfa5Z/kmvFbz7+RZ0AGAWV5NU71CLyAB3FiLbDQ/4U6AGaurqxfiDYrB
neRSmthA/Eoga7cBwEFolCDn9JnCMjq6pvXrhXnaQGbfzPUJcMW7DmAVa8Jr0bJzHdjXUTv+Yg0S
OYwFAGpUc+41XHT5fNc2y5suN4XpfJigB13UkyIyPkKB9WSZsomMjWkb2xeJ0gAymkHt2sRaYkFg
uzE/t8Roam2aucumMnM6UfMxWyB7F9gQ1Gzxsz7z26ps5hv7S3kGJ+AvbVMmeXmsrVTTqDAuriIZ
P/DFlRyCmQkvQUU6+sphav4OqOjRqyrgTEMTN0qNjmdnNJ0ZZtowQ7i84GqL6XSWl3hHzXO5PLKx
IVgRh5/Z8cJjrbisoKBzGTXSRobRK7yHMnFaxWL6N+5sgttCYe3JUFMyQo2IHijaob583vYVpFa/
diSJyyaIczwPWodU9ym/+zJwiA6tAZSqPNhFjKxna5Ev1KmWDx/ZQ21xbF/C0fzr4gAljeYZW9RD
OTCqo6LC+gS5x9Kl5yiL5E2nK9pk/SEToMDBA51dAMr7eiZOdi/2xITDyYNSLhm3wk0n+354fPS9
L9HQ21eVgCbemWhcC8n8OIJCrCSwdeO811qkD5SC7wCUZdY11nM1SVwf7eVLbwPrsIDgJg87H5WD
iYQIXJEchoUMJycrnaRPsxjoU3GiGvtu/GuajAj+pN28G/2Jd6w2pGpAqEgWFOPZWDftfs4SdlwS
nUOO9vZhp4Aj8NF2/fQ3lPlTvb+ADgVMQoaxApv3Q3/6+X2LfyMq6FEHEy2ffniUc3fgTKYxrbAA
vqyANbkKRbugnfQ164Q+z6GQDIaByEwG55YnblJbgNWmFt2kBgEfvrFNj0RuTMxFFXK/uzG+4Hea
wFT0F6wX5mf7zMXOOL5yyfbERfFzQgJbfaI3LlzPzJOhfWINxT+lS33HP8KveDoVEhnyySCrSsi2
Ek+vrluOEQSi3nwTKhTZKDPKJHxt2J20Y+XlRYA6Euc9zMnghzUUg0mEnAaUyrzKF6lWAdoGWscR
KMgD323NyqdjTJfR8cR0VOZm13XDnC/TXocrGbcoLxMFmeRBcVcQIyq2qmFk19ebEecb8xR6kOWf
WgKFqvW9e8H2wH8xu/IHXKc3wkygcYnUAoLs6WmsLQOCS1DpOb4jEsKDlpqTQAjxCklm2nkxHxa4
07v/IHSzgDXKEAW8qfgespZFAkrHcw8NdQZyGvG7uZoz/Ob5kyn5lXktenwRNcOSe4IKL9D07nmm
wSqlxALhQusodxjwBkb+Kbp0V8zdYCQ46gfja9Q/rPlTyS3yhLXE/9zjkF5fMkYHmW+bVUM5h+uh
2YjU2+0Y/6l2pbUPeEex8PSnQ8L5VrNtLoZbbO9ZPKtZ6AW+m0t4C2RLVt5vtTYFv9vUKuhA1xAE
0xOepgSWrcfP5xzZg86bAlCIKjm3DA3ixk/r2cCnVLTfU53lsNZ74yG2SuOfIc9XTt7EIh/l1VXn
6K21wJonLoQ4bDGuN58O6ilwD43jGh4aHoVwwRsHTJObaIH0QRPBXiwHkOks8cAanwr6tkbJJrwo
vmpbdIZIG/qjhYjCHRWIFxjMr+WOCZbX0MYrwdjIqBlVtBqOmLqJF/8qgEaLttJ/Ir9WJOVaRj0/
gPnOReiNZYtXVbNeLVqqK4B/+zKgwTGwwA2x0ipsQAlq7urGUv/vVgrN7J4i62dIH+FaZWN2xqNG
ddzu5skm10AQenGFziR+e+afKugv3alwWotxsFMcKgAMqu4epdqoozWU9KXVQHdMRXR82VfzYMjG
1qbPuNdtqgXbZzifl5gqcEVy1p9NntD32Q2toFeK8bHHsGVfNE4Sx+9UphoUtqy++OT6t4SE4x+w
PA963tWa38nzJxvRUds+0htKdnn7qzO4oyQ7JOqm231H8noezbmelvFVxrLwvIgWnZUVyPDFELj5
9+1YL3R/w/O2G5jnQk3ePSwcWaR3hA4GN5hjdq4qUzwy4LUANroHaF/Oi2rQv75yVjrnL99pr8WQ
TSuo8G0kpYFW0gPF2ztU0sL0MtWxdMaAgqh+9TgGke6pkZ3r+tt7nGhzUXiWYg5BRvSDt8QYEKfA
XhAqm1D+xlrx5vPTui1Z3JjI9bwEdj1pS6nQEIrOZuXj7jf8UHsAgUmAdOB/Xf2LhLdFLwVgk8U2
Y3tNX3u38ZY81Z6QvjH3kSBZ2SMJgMMaqvolD4B6I8hMwn1GsymtNP/ztKbEqZyctJ4aub+ZKcE1
SidTHKQsUd8ACNsDRv5ygo3vyA2Kjc86L9C+NJanh02douvEB1iYpf7dmpQ46mjQ0kbgRzFKNUrR
ExrKWpbnn6b9+texHWPgW8vtFievGdhW2Bq0ltyiekerkAWQTYzKmY+KIWQQuZup8c4HSGmR5qaC
lamEsx//IDD+fpfEFI9/1XiOnk6TgJAbjJAjLoVQulr/YvlawYkBvnX3Q9wvwNE7ERpS3QQdoLr0
OnYuTWiSiAR2NtQyEAar9Q9ePLABvE8ImNxVm7Df9zJx5qk6AJOyVJO7Tvqfhy6Aj3nuKjSMLUvf
BySS0RJUS0P828vxO5wHEiB3jSUNwRG31StFVoBavXKUUVCVAc+jeFJO4xbRe0O1IomVZm+mjy+u
DW6eRqHJTziKi7j3OieKePHAZRsoy8sBeZlTOMBzdER2rtxxUgEljuwSyaZt0/Hvya2H4zBqAG3J
5Smmq1GpXOq7lFbGO35WH9BNS4xo0japSsNT1Qiw7D5/JsbSPvgu8zCpqYc7LMp1ElhGUSzGHaFA
WYq1YMKlQW9QYzICkPZLT2x/RjNWMtRlVKxKl9eb6oc/qAfrWpUpVJrp9Y7HY+/GATCQgWZlQ5GA
JFvyxR0MdEnG66pRtW/iMQDX2H2vzkuT1NwfUgHa0KJsVRAaFBMce//VaGHAV+HwcfNxNJS/86vf
n71ykGC8q1G87IFrHd9BE93XBjDEprUsXIYecX1NiRHFn38GP8UBgdy6cwn1ffrJbowBIRs/bgI1
+dd89/eRHILUI9d46RLu/ke9TCY4aNSvSkfcIJ55nzjHt1k1zvoWAwkZ8VcdKh/pA7zC2OWOQbiF
cE64XodqJigiCiTKObeuk63qVU2Z5W+0iW2i8raDj3WhEWMP8xQBwMnzDywUaybHqKgUUv6ON1/j
PjKxpFPWH+y39Czmw2EoUVAfX6tuO5nexLW/iVzVNh3b+8V1UlgPJW9l3KQ8Ry0CC4nz/x4+3WxB
0RwLM5FfS07rOoZQI5nyvb74DXBpaMChGmqOhODl6L6GVmXpYNZOWvtZhSXGhz0pJ6Dq5abBzlDN
JwbfFI/ukXxp4EZ7XMmfaZPHVFnmI15mSvY36flMTWhMQxMz/EupfEO1Xzw0TCAdbSzBQiuGC89r
Igh/23m2t0JjHqRUddahArwhvSvcKqBczPVBhO67QuCKM3FGDsdI53bHD+Kq9VvouyBfeC+SYs4r
GNa/Q8lBjLxZsp+BHNmyZ+UNvNhEKYPeRhc5PAw234qgzeNu7gYd0Dbb1JgJNiJtX9lqyUeLdNdw
FIN3ZK2RiYzIHLplUwgBR356mBdRaVnDI+SLC9T5p/VpB+etSBEtCUU085KuCIhgWmzKgutEWKz6
ewAXirM8ZUQJrGiZzvHd6ElWfyAIlZ7rJ05hDyhEvspiESruAU73qPoZIiL5i5MgQ5msVNe5JkWg
0aJIqviCKY95tR2hq6NbgU1YoUZWAfkkBth7TSGrvLjdsM1XTAAAENQ9ssd239uosyPbIVd0dC3/
A3bkHFm6rRBxmLVpC4puGDGbvT5HW5Cve2F7rxa8Xx5qLCXcseKEuoNWigur1qhS0i1p8k0YsW64
el1HNn8TtM/rIx5W4VCVDfvHE684/4RmgeVB8PNKJG2W3HfDJti2rWJcWN0sPvWjAp8xNUYW9+Bg
1ic4JUzewiWIS+UerL9SbTWhlQE0An+JEZj4Qq44almoIAdi9C+7Nkaa87vzcz8XImzeEGz79LR6
q2631nl2OPLNpolhQHSt99L8RSccocA9dQRJxgRsLH8Z1phXT28i7LOVIyh0Aw+GnvY2s86LpAkF
wp7rSALP9nRbIf7NZdaQE/mKhBqF8C9d4s0yrcpRVs6uprjJoHjD9lm4z4EYghJJ/lrxdy/P9wdQ
HqRIykK1pThCk8TjzZ3Lxhw1RfNCMBRQHu3bmfTC1VkdjA1EZH4wy1wmfKEUFjZnUwK7UGTUAK9x
hYChfrPX13ou98LwmQquzbZX0ddQMUGatu60lsciXydQ1rU6P/1c2Wfmx4SUDMPtdwr2NCFC8KV2
lwrn+TYRv+9xUsZdJs3fNcNDfVcwKVyJHZo6c7qhc3s5hY6JusdJAidO0EpynCy0YH7Y/OX0bsfu
E1dgD0HkYKQn+mQ1tvrLGxNh38s/WkAGsQMjN1/sHKYW89ADUEw9+fP1U1F7Ufe2RRgFW+douUSM
YZrAvEhoXTH5UOOqTXVnLR+h01PD5fNtDnNoGM7liWqFB+4FlzVU2aKfjopHoKZ09g==
`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/rd_dc_fwft_ext_as.vhd | 19 | 12811 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
SPpb0sHtYr+7D0Z/NdHkBGKHFj6bPnAk4zCT9Qd9jSi/NZdzqHWXjKwgFh3NrYG/AQMVJcT4R9KU
T1kWm6bsuw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
PM0w38wqoKZTqxD5ZMv+He7u+x4mAKOhS9vNWqYsLtlMu2ni98hkp4Js0D7iFCQdcFCu3Jaj2Vqe
E0m1H+UGB6We+zPa+TnTKUC9+mxtEW7xpi8i+GVKfIfe89n3euEibIBIS0WLtZypuPRjuzr2TWw/
TpBFYS1oUTQ1qwWguI8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OIEbVz6QJBHT228fhImFLc7Q94gbSg/QOSgeKpAp1zRCxot1azeNL0EHN3pwZU9Qs6kuTNEAn7+w
agqdilWN9rl3uQlRBfW5KbIj2khza90rK/4UYrbcPGQyMxF8l/LBS9RaSzH8pqlJgQ4YfgwGNaq6
EHHkNL7CBEprP8VBO3A9geAIYBWstNirz3P/01jzH8PT87csZHkt/KV+1ancvBdl8zy3Pi5RrOtK
WdR5qLkbXJ6m4DjaubrW8HdK/fqusuCVkVGxmajuQw899iRpx5AiTEwKYKOor3msJGxdK7STL4ZT
S1m+Ec1GdsxDwYBgiKT0A3c1/unIYBS6y17V2A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Y9qoE+tEhAFEsAZgxeFxNUflksEoY80RYly6rjz4X/QwncMYkOdY5w8AxmW4IYZfWprQfyfkxMrN
8JuXogLHC84iIPhEFIhJ/+RivFHW4gCUIf9NTOGEkQza7hd31B0/7LZttbZHcfTR5stmYGMhB9xi
VCriwe4C9iR9zFvOJxk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eCcOM7HngIZB2JCDRQ//SPPOptJbtDQ6WJM03A6xR3t8OhM7+MFavTdB4aR11UrppwUsYiZCHTBc
4AdaSSNbTEcILhRaZMNZ85hgqiNgFb3YTJu8ZIWifM+Ad5U1zkzbH1xsVssRl/Sl+cf+TCDh9Psd
UOpjIzWfsyGgyfaSSbczC/DMklBqFcyspqzOP0YGdgI4It3e5xnwDvYeewRqIZggj0RyjkJH8PxJ
o1XlyTZFQZIIFN0x8sDbcPdsUekU3pOCvI9JK89jigNzKmLJRotLEgZQt0B8gMiz/gm5u0+k01OA
f/7Xo9TSexSaZ5evmswsNTBQhg4v8j39bgkh9Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7744)
`protect data_block
5c14H3XnHn6oO1IeyUW2iFvZzZ9cCnGgzIUu3xjh8e5xy/i+86IXlWbx5i2mlzzGRsVALU6t0f5I
QeLGf6AbkZ3hlwUCPMwVm2NmJK02qmRODGZiQlWi86n7suSZCs63ZjJ8pPnlCAQn8FaAgD+sgU+U
LVJSO14ZQJdmeB9GkCpHLzCfmtn8G9pebF+4tvm+oH1Uj6EAIKVfWPjUewpmjHF89f+d8S2xkvls
d6F1pZhG0Miog0UYG98SqUR6cD8feORy/6KXrmhEBqlx5N1uGyRpBmcg4JnW7T4/l28UxSeLzrgI
4U4PONALlPBLOVnyVaJS2p9a6dmHqVwxrzpygh4ePWkz8aQCV23fCBCRex9yZdPwsXD5KBoAtTOV
e8m6hpUgMopGSCe/ZgYGMJb5h5Ug1v77eD5d6E5Tec6ZV1BBzld41Me5gj4RFU/7nM7Zeqx65sQv
2QrqR8YAmfROrLQk6fvAiDvNCn81ulN/k0mUUx77ADvCzqU2vNzog4QhdiTvV6BwSiQyVhLExOAT
RP9xun9p56pDh5dbI507yrklnIOT+S+ZwHcpBNEswTZsn9Tz5O8Izrk0z1HfI7y5064+Phb4LNAg
iJ52UgStrHi6fIcPLqF+nI0q4L80u2nS4VwuaD880mWYCx0rB89Q8U47GVQFUwE+Et3pto+6HnDR
zBJPxRBs0/nBwZrTyibxOTfQlrVttYxiXEEQrBs75MmUf5VUnPUcvumnaaBLLy3CnPHGFqUV9hyB
7QfbtWxmBfEcFZpLIJ3DEEd6LBdklewU8RePNbtw6eSxJIzz2qg8Z9nC538q0h3Tl4QrcEO/Mk3V
/EdZ3Uk2f+62flnxW7FfOJYVt97Spa9FVTDxZ5Wgshd+IBYPh7nUc7xSe2mzU7VJxE/GLzavxO75
I3XoeiB1XDWZm3TCQE94c2E6WW0IaO1MptHx1atHjIn4irTOMQHFpngzfn5J6Boyhh4/Yr9VB2NK
a9HBu8cqZODx9oW+/jH9/7EEKhTeQebSHO79mjsqRG6LZdS/sk7qo+rEyAYv7YZohW/cVu8bGZIq
k1cXJS1QBCudOnZzIJh+TaMtrVAtxdlqxUsTxCA5vuyf6weMiYdFIzna751iKfkRRDLJ83dAyHmz
9iv/fXQGP90Xi85xe8AC2gyzrDQGCJW5G/x2uLokQiKUu7NzqoPvLWQsLIXCjPOaHkjtcS3ncdiA
vDhbCIys7eWECB3nTAr9CFCaXWi9Sia5MQ57SGoaRP731iJrqdQwPrXG+2fczOptpWA5jjtHEO9S
H2SuBg5ZHOgBHnmqNE68npxq5dX2BGoYV77/gOJjNMT8maS0ZPmDN/OHFuqWL4uWGbI1xogG+exe
WQygKkUbkqedsoeKd0mwWsxUenSMqmILUkjYEoxz41pevqFRkKbHuX/mO+ZxaBzzZ0ScsYPKGDGU
p8+i4m2c07sQ8f7PmgkR5x3zbQNNNysim8a85mNC4KYxHMXTFc3dALcIbUpu31cLczOpb2Q5u2SE
Snl0l8Hd0YWglpJrBg8NpKyzXFnTtK/1fU1x6HhObOe3WE4kKXLv4iFvAHWxRyMUTeDOTa0mdI6C
Pqo+ZITRzKpyG7k9pSp8gN95su3ofhmm37L7jWqEilb3qXor09HAuJTld34C7obfC2OWRTaj85L/
SE46aTHHxfb4MQx2DcVYtaqeMi9cBx5z0BgvqwNcIQxuYt59WgWH8QV3zi79EDB8bhwTuZxNSdGX
FfcnCFvq7ntDqOqUoy7PRPo0zTeywPqzDWQe0LCSW9qQMSkCbjSP2JKi9bVsPW+V8avobRCE1Tgd
jxTEFRYiJWrNXgo961FaMuyrxs8215iMEN5QTdpeqxTbdU2MtMmMHEiEqvjlBrhDiWLw8GYS90dM
sb/IK53ooAF8QVxjWp9tJpodQigYKNwEuMl0inrhMAgU+SRXPPWiavciUPCb5drTK6BboVdcXHil
PNmBSF3HniyDVT3iDkPmsgMseJewzXdJnkrlT3mNfLKeNP1SSEjQVbbUwU/iS6vuupbU1YPjmb5G
QUmJ0sX9O4xS8VkkcUSMGtPtzqXlulgXV8CM1VKzZrNa/C2uFyU3y3xuaVkz9br/Tf4O8sNIz3t2
9wtU0zkoC4RuJbnhn42zJmTQU3OZtyX0tiPQhBC9lPA9bUjqUVj5epeOdamKSe9dzb5vw1iHIDS6
kLRuRSbCuOCOtzarozdpmpZIMu2vkiWJQ8ns69jgiiMctt0nH6dZjc78GcXZj2eUG7ELRJMw2oXH
IWGGL7X13RNv+/ih1RDuJ7SfPtb+vHooCWwmH3vZsGb/oITNg70+PpuXZU/Wi0Gv6Vrqr868Qv0/
n8O7U1ki146Rgd5tv98JSv0g7eucYuENzW1UbfAeuexUD/tOMbifJMg4fdm0A5ugrRJqt3V1qRRa
y5YHSOvhbVQYQtpU8qeLw12NSwedrQrKbT3EB4bfVsDHeFDBSrIGO/RrmNg/2ni9g3MI4ExruoKL
+GmlIPivWj/RWL4zjOErkN8paHTpER5QFduI+OoQP96NLOBEZeeUjEWjq5afJSCGv+O3NIDsYLWr
PcCZu2iHkLXwLC/JP2KeBnbWpAbouXFuZOIELIb2R3EwoafsvDq7gY+mNJH8VpzbG5Ie/j6UTXHC
/ZbMIz1vnQ4maU0hAoXs7Keen5bx/D28sS1RsYPHq+szPSGdzPNhGaqeQ4UjSYyeVo1nh7+Gr7z0
CdRzzwQSHUo9PWG/0IQ4VgTk5mQ67AcMGSiW2734tpMPS/GKsMe05uXX60mQdEkMBQFWgKKwKiKt
xs747yhJUtH2HtFEZ7THRs6rOUdOC8QWNhFJ9TAhMRKzAUziNvq7Biek9IN61T6+xDQiPennQyTq
p9S9lZmXx5wtHgyR84+5m+dLUaJMaK0o0gqYgrfzyr5J9uHaTYN8EkJOOCwWD9yv2UIcuWkrWvth
bwQCq0hb8yj79Yf94p9eeMjvjAyYHgWN4xiXAyc6KXa+nOlreuZTGxQKrsuaEuw4flmPxy3ndyJn
Vdka7+vsnvYL0Fo3Ne4rTXkzRK7XbYa9UR7P9U7H+hnnpoXPTxA14SqYsRnIt3pFysdd2VtVaJw5
T+WVzWUH78db5By9zm7zlv0p90DwecdXN6rFnVuwMmpm3Nq3NiGvGSPzIe58UlQ2ZIJy2J0dIJvT
XdHQMiEJ1vCkE5i7hYBs1pl9TlsBVwKH8XhL8XRmJTojX2MU3HUbgjdF+09nMGaXbr1oHSgwXUwC
xe6PpkChpsha7EKQrdeu7C8B+VxStvT/oRGbDVTiATcTaSE5B7Dk44VFki9JzQ03wKJBzjjOyIQH
6N2zoejjGs2v51NwsTILZm1EAqK4esOEvcIlrpTUMISMhFDfNNm/2LAsiX2HG0YKJdZbJeMoS/XY
RCEk4nH8MUOyr3ZcJ9tVeoxuza+OazXeGObr+ayKHrYCOwVtFVhBwtyFRQYoKt1qKHe3Kp9jvoIA
0mrKlB8ZyPqCVO16d8Mr3UP4T7t1EBUwLRcXbSVaQdYqkAoMvpShdBA3hLLwRl3NYWD+T2LuK6Iv
rLO7SLqf8Licd/wWToT5nZ7azrfVoZMgLaR6fx2dBGBNZoqtjolgQVWRZPzTIWjV5YAWQby39A4V
T8p+BROI4pHZ/hLe55oA8L9ofrSU9vvkADrSnecLx+rRiZeV5DBmF++OLvpga0X9y+v2HWnt5PpH
S5TVI8sAQjG3MEWcXLVRkOGFbd6fR7T6UhNe7j6391Jv/igk/jVWZUlmtAwp0XEf/cPbCLS+Fczh
vJvNIGhvduxCogdW035A5riPJPvBlFXrSnrAPJIgKVVk0YOyn1pG4SCGZLmSb2R6xmvzjYyvGmmf
OhU6PK/PeY18z9DGhXm3lj/+Aj3ek6GY17iPxD6d6uEIzcczThaC2t4p/TClmeOqsj+Axuo17y1C
FKPtpHrELNbVNf5ZCt3b6syz9V3TFjvhpWd+GUYaSVae1pNAElo94JoeG1v7daAvFp+FtW4lq8/u
yCqiTUl/YtiAfmdj86vqnQ7XEEyeXewk3zOudWei8krlH/QLvfjBkZe7iHnuDP4dfZgmzCMo6sXu
O8lj3ESK9E/WQU9R3NSDj3KSysqSv9NuylPipDkvTtkX2vqJbDBA4pTn/c8mgzTI1eJwssImF43H
zjyX0HrZMR9R58AJIlbRxdVxG4buA8K7Cc7R9fZqflL24G2y6CElejZbM6QsgAO7S3vCm2sfL9pz
w/KHPZeRai7ETCVBHtxiXTt9uDreie2HTU26WpMuzhlI3s2mErCDKqm2sz5g6HHfPmUsyPvHOsSJ
Te6k0AW4N6afrKTwFKQPRPlN032D2wgecoUE8cGnnnXPWO3g5pb6bTb7SuMy7rMX6EqDT86LY4RL
bXYZx1kjuuup8IbmcNSp4QQIvq4oekb08RFlrChM7KDB9825jLf3ZG2WJJdBT6FO3E8S3tIgopTC
nA2UR7hUsYz8wb1ZrKLtAz9gSS8bCVSLYixuYQerLQV/khG6d1L8BEqg+BRwaXjQsT0htuVAxiH5
CjoC0vJOtc3N0xu+6o14vOSXxuYqXjpHFHRjFmLtPn9AtsIrhHmo2uDAgj3sVRYUTYcwUQv6wvXP
8CWcQkmflKhjZsZFZ5ANpgpZW9vh5mnCf4kN18VP6YT/QQycckDVOiVIfhC4lQ5SrwLlzS69J4q1
Y4UExQ/7aGCQwYsF52EluNq4rK0tYNpLEE3e1oZwbnSYePh/vXnbp0z+OfGeP9jucbIrBdHJIpuq
zia6W244IruLuxZs1rWMU82qmq07mAqLHXy3fYHczahoT98piGVU5ORBYwEJHuDAiXdFCfjpQeo0
GGK1bEngb/fBTda+6wtnUfVZRwidU8B1QbRTkpOiGOcZlODOvxxcg9sO3aHhhQkKyYQ+0kvUMSIX
ePXgoOIoSDcSDPwpmrS3YTE7hAV8FzeJuNN3JEdjnmTIyKwBmmZKj/Kcfxmn6nILMYkl95rFKIlx
ucixorWznlAqkiGWaw3MAe+khdZAMba4j9uDqR8jY/BK6LCer81zay20OQi5XjmyYJXkxad/tpij
O0g6qPuSGF76Dq+wy8SmYWJ8AiAYbW1UHQHRWWRR5L2qMt8w1B+g3LKilAr412mWzRe3FQo+zZve
PJw4k6mj4A723Hm8c+A/sj65++XedC57rOS7i7GOozhWW7H8KFIV0CWkwXmCp3mHFn7SNgaCAp2I
35RTFhim73iHVHUot3YkQRA+Ut+Mc1HDjOjYAbmuE5pyjK+Y9/5dUnw4jamPxC3RhE0n0b3xD4kI
Lc/sz6PM6y7NxmItSDysysgYZMp5WTKOg26zz+GTiGIQg1r3bcSjO5+huKjxTosw9N652zNOStXa
+M443r1syNPbCyYPN8xh9XHQiUkllgL2WCzebcOt5NqPtjkavdYLfFnyZ3WGpxfvRKD117/NiiBn
EpjkaAA7NV2gcRaPHt8iE8xFSVVZdGXl98kIIi4NCTe0yvIoeuGSmKS9kZSdB7QNj1X/WUVmNy4V
wKwOcBEoPl2o3AOhOXo0/pp1SuDEdCxhYvk45E8rpEYgD0NStdtllE9gQxyW5XnOJUuYPQinDYwZ
VVpuNiLPQeZhKGNp/UoCY6xQCvMnFgyeghOJjFFXSY8wM/W2YC0na1JRqByolrALKxAR+To+OyWl
oaS2rOGB2Zk2okxrF0o66GZimJRFfyuAebNPTQQ6le8EsXUFzCBIdKJFKYO8rz5v36h4RraDjQE0
wx3FjQkZE1ce9HZkqXNSRfa5Z/kmvFbz7+RZ0AGAWV5NU71CLyAB3FiLbDQ/4U6AGaurqxfiDYrB
neRSmthA/Eoga7cBwEFolCDn9JnCMjq6pvXrhXnaQGbfzPUJcMW7DmAVa8Jr0bJzHdjXUTv+Yg0S
OYwFAGpUc+41XHT5fNc2y5suN4XpfJigB13UkyIyPkKB9WSZsomMjWkb2xeJ0gAymkHt2sRaYkFg
uzE/t8Roam2aucumMnM6UfMxWyB7F9gQ1Gzxsz7z26ps5hv7S3kGJ+AvbVMmeXmsrVTTqDAuriIZ
P/DFlRyCmQkvQUU6+sphav4OqOjRqyrgTEMTN0qNjmdnNJ0ZZtowQ7i84GqL6XSWl3hHzXO5PLKx
IVgRh5/Z8cJjrbisoKBzGTXSRobRK7yHMnFaxWL6N+5sgttCYe3JUFMyQo2IHijaob583vYVpFa/
diSJyyaIczwPWodU9ym/+zJwiA6tAZSqPNhFjKxna5Ev1KmWDx/ZQ21xbF/C0fzr4gAljeYZW9RD
OTCqo6LC+gS5x9Kl5yiL5E2nK9pk/SEToMDBA51dAMr7eiZOdi/2xITDyYNSLhm3wk0n+354fPS9
L9HQ21eVgCbemWhcC8n8OIJCrCSwdeO811qkD5SC7wCUZdY11nM1SVwf7eVLbwPrsIDgJg87H5WD
iYQIXJEchoUMJycrnaRPsxjoU3GiGvtu/GuajAj+pN28G/2Jd6w2pGpAqEgWFOPZWDftfs4SdlwS
nUOO9vZhp4Aj8NF2/fQ3lPlTvb+ADgVMQoaxApv3Q3/6+X2LfyMq6FEHEy2ffniUc3fgTKYxrbAA
vqyANbkKRbugnfQ164Q+z6GQDIaByEwG55YnblJbgNWmFt2kBgEfvrFNj0RuTMxFFXK/uzG+4Hea
wFT0F6wX5mf7zMXOOL5yyfbERfFzQgJbfaI3LlzPzJOhfWINxT+lS33HP8KveDoVEhnyySCrSsi2
Ek+vrluOEQSi3nwTKhTZKDPKJHxt2J20Y+XlRYA6Euc9zMnghzUUg0mEnAaUyrzKF6lWAdoGWscR
KMgD323NyqdjTJfR8cR0VOZm13XDnC/TXocrGbcoLxMFmeRBcVcQIyq2qmFk19ebEecb8xR6kOWf
WgKFqvW9e8H2wH8xu/IHXKc3wkygcYnUAoLs6WmsLQOCS1DpOb4jEsKDlpqTQAjxCklm2nkxHxa4
07v/IHSzgDXKEAW8qfgespZFAkrHcw8NdQZyGvG7uZoz/Ob5kyn5lXktenwRNcOSe4IKL9D07nmm
wSqlxALhQusodxjwBkb+Kbp0V8zdYCQ46gfja9Q/rPlTyS3yhLXE/9zjkF5fMkYHmW+bVUM5h+uh
2YjU2+0Y/6l2pbUPeEex8PSnQ8L5VrNtLoZbbO9ZPKtZ6AW+m0t4C2RLVt5vtTYFv9vUKuhA1xAE
0xOepgSWrcfP5xzZg86bAlCIKjm3DA3ixk/r2cCnVLTfU53lsNZ74yG2SuOfIc9XTt7EIh/l1VXn
6K21wJonLoQ4bDGuN58O6ilwD43jGh4aHoVwwRsHTJObaIH0QRPBXiwHkOks8cAanwr6tkbJJrwo
vmpbdIZIG/qjhYjCHRWIFxjMr+WOCZbX0MYrwdjIqBlVtBqOmLqJF/8qgEaLttJ/Ir9WJOVaRj0/
gPnOReiNZYtXVbNeLVqqK4B/+zKgwTGwwA2x0ipsQAlq7urGUv/vVgrN7J4i62dIH+FaZWN2xqNG
ddzu5skm10AQenGFziR+e+afKugv3alwWotxsFMcKgAMqu4epdqoozWU9KXVQHdMRXR82VfzYMjG
1qbPuNdtqgXbZzifl5gqcEVy1p9NntD32Q2toFeK8bHHsGVfNE4Sx+9UphoUtqy++OT6t4SE4x+w
PA963tWa38nzJxvRUds+0htKdnn7qzO4oyQ7JOqm231H8noezbmelvFVxrLwvIgWnZUVyPDFELj5
9+1YL3R/w/O2G5jnQk3ePSwcWaR3hA4GN5hjdq4qUzwy4LUANroHaF/Oi2rQv75yVjrnL99pr8WQ
TSuo8G0kpYFW0gPF2ztU0sL0MtWxdMaAgqh+9TgGke6pkZ3r+tt7nGhzUXiWYg5BRvSDt8QYEKfA
XhAqm1D+xlrx5vPTui1Z3JjI9bwEdj1pS6nQEIrOZuXj7jf8UHsAgUmAdOB/Xf2LhLdFLwVgk8U2
Y3tNX3u38ZY81Z6QvjH3kSBZ2SMJgMMaqvolD4B6I8hMwn1GsymtNP/ztKbEqZyctJ4aub+ZKcE1
SidTHKQsUd8ACNsDRv5ygo3vyA2Kjc86L9C+NJanh02douvEB1iYpf7dmpQ46mjQ0kbgRzFKNUrR
ExrKWpbnn6b9+texHWPgW8vtFievGdhW2Bq0ltyiekerkAWQTYzKmY+KIWQQuZup8c4HSGmR5qaC
lamEsx//IDD+fpfEFI9/1XiOnk6TgJAbjJAjLoVQulr/YvlawYkBvnX3Q9wvwNE7ERpS3QQdoLr0
OnYuTWiSiAR2NtQyEAar9Q9ePLABvE8ImNxVm7Df9zJx5qk6AJOyVJO7Tvqfhy6Aj3nuKjSMLUvf
BySS0RJUS0P828vxO5wHEiB3jSUNwRG31StFVoBavXKUUVCVAc+jeFJO4xbRe0O1IomVZm+mjy+u
DW6eRqHJTziKi7j3OieKePHAZRsoy8sBeZlTOMBzdER2rtxxUgEljuwSyaZt0/Hvya2H4zBqAG3J
5Smmq1GpXOq7lFbGO35WH9BNS4xo0japSsNT1Qiw7D5/JsbSPvgu8zCpqYc7LMp1ElhGUSzGHaFA
WYq1YMKlQW9QYzICkPZLT2x/RjNWMtRlVKxKl9eb6oc/qAfrWpUpVJrp9Y7HY+/GATCQgWZlQ5GA
JFvyxR0MdEnG66pRtW/iMQDX2H2vzkuT1NwfUgHa0KJsVRAaFBMce//VaGHAV+HwcfNxNJS/86vf
n71ykGC8q1G87IFrHd9BE93XBjDEprUsXIYecX1NiRHFn38GP8UBgdy6cwn1ffrJbowBIRs/bgI1
+dd89/eRHILUI9d46RLu/ke9TCY4aNSvSkfcIJ55nzjHt1k1zvoWAwkZ8VcdKh/pA7zC2OWOQbiF
cE64XodqJigiCiTKObeuk63qVU2Z5W+0iW2i8raDj3WhEWMP8xQBwMnzDywUaybHqKgUUv6ON1/j
PjKxpFPWH+y39Czmw2EoUVAfX6tuO5nexLW/iVzVNh3b+8V1UlgPJW9l3KQ8Ry0CC4nz/x4+3WxB
0RwLM5FfS07rOoZQI5nyvb74DXBpaMChGmqOhODl6L6GVmXpYNZOWvtZhSXGhz0pJ6Dq5abBzlDN
JwbfFI/ukXxp4EZ7XMmfaZPHVFnmI15mSvY36flMTWhMQxMz/EupfEO1Xzw0TCAdbSzBQiuGC89r
Igh/23m2t0JjHqRUddahArwhvSvcKqBczPVBhO67QuCKM3FGDsdI53bHD+Kq9VvouyBfeC+SYs4r
GNa/Q8lBjLxZsp+BHNmyZ+UNvNhEKYPeRhc5PAw234qgzeNu7gYd0Dbb1JgJNiJtX9lqyUeLdNdw
FIN3ZK2RiYzIHLplUwgBR356mBdRaVnDI+SLC9T5p/VpB+etSBEtCUU085KuCIhgWmzKgutEWKz6
ewAXirM8ZUQJrGiZzvHd6ElWfyAIlZ7rJ05hDyhEvspiESruAU73qPoZIiL5i5MgQ5msVNe5JkWg
0aJIqviCKY95tR2hq6NbgU1YoUZWAfkkBth7TSGrvLjdsM1XTAAAENQ9ssd239uosyPbIVd0dC3/
A3bkHFm6rRBxmLVpC4puGDGbvT5HW5Cve2F7rxa8Xx5qLCXcseKEuoNWigur1qhS0i1p8k0YsW64
el1HNn8TtM/rIx5W4VCVDfvHE684/4RmgeVB8PNKJG2W3HfDJti2rWJcWN0sPvWjAp8xNUYW9+Bg
1ic4JUzewiWIS+UerL9SbTWhlQE0An+JEZj4Qq44almoIAdi9C+7Nkaa87vzcz8XImzeEGz79LR6
q2631nl2OPLNpolhQHSt99L8RSccocA9dQRJxgRsLH8Z1phXT28i7LOVIyh0Aw+GnvY2s86LpAkF
wp7rSALP9nRbIf7NZdaQE/mKhBqF8C9d4s0yrcpRVs6uprjJoHjD9lm4z4EYghJJ/lrxdy/P9wdQ
HqRIykK1pThCk8TjzZ3Lxhw1RfNCMBRQHu3bmfTC1VkdjA1EZH4wy1wmfKEUFjZnUwK7UGTUAK9x
hYChfrPX13ou98LwmQquzbZX0ddQMUGatu60lsciXydQ1rU6P/1c2Wfmx4SUDMPtdwr2NCFC8KV2
lwrn+TYRv+9xUsZdJs3fNcNDfVcwKVyJHZo6c7qhc3s5hY6JusdJAidO0EpynCy0YH7Y/OX0bsfu
E1dgD0HkYKQn+mQ1tvrLGxNh38s/WkAGsQMjN1/sHKYW89ADUEw9+fP1U1F7Ufe2RRgFW+douUSM
YZrAvEhoXTH5UOOqTXVnLR+h01PD5fNtDnNoGM7liWqFB+4FlzVU2aKfjopHoKZ09g==
`protect end_protected
| mit |
bgottschall/reloc | zedboard_example/zedboard_example.srcs/sources_1/imports/sources_1/imports/new/wrapper.vhd | 1 | 19020 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity wrapper is
generic (
DATAWIDTH : integer := 32
);
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end wrapper;
architecture rtl of wrapper is
component BD_PR_3 is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
m_axis_data_0_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
m_axis_data_0_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
m_axis_data_0_tlast : inout STD_LOGIC;
m_axis_data_0_tready : inout STD_LOGIC;
m_axis_data_0_tvalid : inout STD_LOGIC;
s_axis_data_0_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
s_axis_data_0_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
s_axis_data_0_tlast : inout STD_LOGIC;
s_axis_data_0_tready : inout STD_LOGIC;
s_axis_data_0_tvalid : inout STD_LOGIC;
m_axis_data_1_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
m_axis_data_1_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
m_axis_data_1_tlast : inout STD_LOGIC;
m_axis_data_1_tready : inout STD_LOGIC;
m_axis_data_1_tvalid : inout STD_LOGIC;
s_axis_data_1_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
s_axis_data_1_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
s_axis_data_1_tlast : inout STD_LOGIC;
s_axis_data_1_tready : inout STD_LOGIC;
s_axis_data_1_tvalid : inout STD_LOGIC;
m_axis_data_2_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
m_axis_data_2_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
m_axis_data_2_tlast : inout STD_LOGIC;
m_axis_data_2_tready : inout STD_LOGIC;
m_axis_data_2_tvalid : inout STD_LOGIC;
s_axis_data_2_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
s_axis_data_2_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
s_axis_data_2_tlast : inout STD_LOGIC;
s_axis_data_2_tready : inout STD_LOGIC;
s_axis_data_2_tvalid : inout STD_LOGIC;
AXIS_CLK : buffer STD_LOGIC
);
end component;
component pr_axis_buffer is
generic (
DATAWIDTH : integer := DATAWIDTH
);
port (
static_m_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
static_m_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
static_m_axis_data_tready : out std_logic;
static_m_axis_data_tlast : in std_logic;
static_m_axis_data_tvalid : in std_logic;
pr_m_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
pr_m_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
pr_m_axis_data_tready : out std_logic;
pr_m_axis_data_tlast : in std_logic;
pr_m_axis_data_tvalid : in std_logic;
static_s_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
static_s_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
static_s_axis_data_tready : in std_logic;
static_s_axis_data_tlast : out std_logic;
static_s_axis_data_tvalid : out std_logic;
pr_s_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
pr_s_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
pr_s_axis_data_tready : in std_logic;
pr_s_axis_data_tlast : out std_logic;
pr_s_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
component pr_axis is
generic (
DATAWIDTH : integer := DATAWIDTH
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
signal static_m_axis_data_0_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_m_axis_data_0_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_m_axis_data_0_tlast : STD_LOGIC;
signal static_m_axis_data_0_tready : STD_LOGIC;
signal static_m_axis_data_0_tvalid : STD_LOGIC;
signal static_s_axis_data_0_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_s_axis_data_0_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_s_axis_data_0_tlast : STD_LOGIC;
signal static_s_axis_data_0_tready : STD_LOGIC;
signal static_s_axis_data_0_tvalid : STD_LOGIC;
signal pr_m_axis_data_0_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_m_axis_data_0_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_m_axis_data_0_tlast : STD_LOGIC;
signal pr_m_axis_data_0_tready : STD_LOGIC;
signal pr_m_axis_data_0_tvalid : STD_LOGIC;
signal pr_s_axis_data_0_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_s_axis_data_0_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_s_axis_data_0_tlast : STD_LOGIC;
signal pr_s_axis_data_0_tready : STD_LOGIC;
signal pr_s_axis_data_0_tvalid : STD_LOGIC;
signal static_m_axis_data_1_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_m_axis_data_1_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_m_axis_data_1_tlast : STD_LOGIC;
signal static_m_axis_data_1_tready : STD_LOGIC;
signal static_m_axis_data_1_tvalid : STD_LOGIC;
signal static_s_axis_data_1_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_s_axis_data_1_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_s_axis_data_1_tlast : STD_LOGIC;
signal static_s_axis_data_1_tready : STD_LOGIC;
signal static_s_axis_data_1_tvalid : STD_LOGIC;
signal pr_m_axis_data_1_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_m_axis_data_1_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_m_axis_data_1_tlast : STD_LOGIC;
signal pr_m_axis_data_1_tready : STD_LOGIC;
signal pr_m_axis_data_1_tvalid : STD_LOGIC;
signal pr_s_axis_data_1_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_s_axis_data_1_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_s_axis_data_1_tlast : STD_LOGIC;
signal pr_s_axis_data_1_tready : STD_LOGIC;
signal pr_s_axis_data_1_tvalid : STD_LOGIC;
signal static_m_axis_data_2_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_m_axis_data_2_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_m_axis_data_2_tlast : STD_LOGIC;
signal static_m_axis_data_2_tready : STD_LOGIC;
signal static_m_axis_data_2_tvalid : STD_LOGIC;
signal static_s_axis_data_2_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_s_axis_data_2_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_s_axis_data_2_tlast : STD_LOGIC;
signal static_s_axis_data_2_tready : STD_LOGIC;
signal static_s_axis_data_2_tvalid : STD_LOGIC;
signal pr_m_axis_data_2_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_m_axis_data_2_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_m_axis_data_2_tlast : STD_LOGIC;
signal pr_m_axis_data_2_tready : STD_LOGIC;
signal pr_m_axis_data_2_tvalid : STD_LOGIC;
signal pr_s_axis_data_2_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_s_axis_data_2_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_s_axis_data_2_tlast : STD_LOGIC;
signal pr_s_axis_data_2_tready : STD_LOGIC;
signal pr_s_axis_data_2_tvalid : STD_LOGIC;
signal clk : STD_LOGIC;
begin
block_design: component BD_PR_3
port map(
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
m_axis_data_0_tdata => static_m_axis_data_0_tdata,
m_axis_data_0_tkeep => static_m_axis_data_0_tkeep,
m_axis_data_0_tlast => static_m_axis_data_0_tlast,
m_axis_data_0_tready => static_m_axis_data_0_tready,
m_axis_data_0_tvalid => static_m_axis_data_0_tvalid,
s_axis_data_0_tdata => static_s_axis_data_0_tdata,
s_axis_data_0_tkeep => static_s_axis_data_0_tkeep,
s_axis_data_0_tlast => static_s_axis_data_0_tlast,
s_axis_data_0_tready => static_s_axis_data_0_tready,
s_axis_data_0_tvalid => static_s_axis_data_0_tvalid,
m_axis_data_1_tdata => static_m_axis_data_1_tdata,
m_axis_data_1_tkeep => static_m_axis_data_1_tkeep,
m_axis_data_1_tlast => static_m_axis_data_1_tlast,
m_axis_data_1_tready => static_m_axis_data_1_tready,
m_axis_data_1_tvalid => static_m_axis_data_1_tvalid,
s_axis_data_1_tdata => static_s_axis_data_1_tdata,
s_axis_data_1_tkeep => static_s_axis_data_1_tkeep,
s_axis_data_1_tlast => static_s_axis_data_1_tlast,
s_axis_data_1_tready => static_s_axis_data_1_tready,
s_axis_data_1_tvalid => static_s_axis_data_1_tvalid,
m_axis_data_2_tdata => static_m_axis_data_2_tdata,
m_axis_data_2_tkeep => static_m_axis_data_2_tkeep,
m_axis_data_2_tlast => static_m_axis_data_2_tlast,
m_axis_data_2_tready => static_m_axis_data_2_tready,
m_axis_data_2_tvalid => static_m_axis_data_2_tvalid,
s_axis_data_2_tdata => static_s_axis_data_2_tdata,
s_axis_data_2_tkeep => static_s_axis_data_2_tkeep,
s_axis_data_2_tlast => static_s_axis_data_2_tlast,
s_axis_data_2_tready => static_s_axis_data_2_tready,
s_axis_data_2_tvalid => static_s_axis_data_2_tvalid,
AXIS_CLK => clk
);
pr_0_buffer: component pr_axis_buffer
port map (
static_m_axis_data_tdata => static_m_axis_data_0_tdata,
static_m_axis_data_tkeep => static_m_axis_data_0_tkeep,
static_m_axis_data_tready => static_m_axis_data_0_tready,
static_m_axis_data_tlast => static_m_axis_data_0_tlast,
static_m_axis_data_tvalid => static_m_axis_data_0_tvalid,
pr_m_axis_data_tdata => pr_m_axis_data_0_tdata,
pr_m_axis_data_tkeep => pr_m_axis_data_0_tkeep,
pr_m_axis_data_tready => pr_m_axis_data_0_tready,
pr_m_axis_data_tlast => pr_m_axis_data_0_tlast,
pr_m_axis_data_tvalid => pr_m_axis_data_0_tvalid,
static_s_axis_data_tdata => static_s_axis_data_0_tdata,
static_s_axis_data_tkeep => static_s_axis_data_0_tkeep,
static_s_axis_data_tready => static_s_axis_data_0_tready,
static_s_axis_data_tlast => static_s_axis_data_0_tlast,
static_s_axis_data_tvalid => static_s_axis_data_0_tvalid,
pr_s_axis_data_tdata => pr_s_axis_data_0_tdata,
pr_s_axis_data_tkeep => pr_s_axis_data_0_tkeep,
pr_s_axis_data_tready => pr_s_axis_data_0_tready,
pr_s_axis_data_tlast => pr_s_axis_data_0_tlast,
pr_s_axis_data_tvalid => pr_s_axis_data_0_tvalid,
clk => clk
);
pr_1_buffer: component pr_axis_buffer
port map (
static_m_axis_data_tdata => static_m_axis_data_1_tdata,
static_m_axis_data_tkeep => static_m_axis_data_1_tkeep,
static_m_axis_data_tready => static_m_axis_data_1_tready,
static_m_axis_data_tlast => static_m_axis_data_1_tlast,
static_m_axis_data_tvalid => static_m_axis_data_1_tvalid,
pr_m_axis_data_tdata => pr_m_axis_data_1_tdata,
pr_m_axis_data_tkeep => pr_m_axis_data_1_tkeep,
pr_m_axis_data_tready => pr_m_axis_data_1_tready,
pr_m_axis_data_tlast => pr_m_axis_data_1_tlast,
pr_m_axis_data_tvalid => pr_m_axis_data_1_tvalid,
static_s_axis_data_tdata => static_s_axis_data_1_tdata,
static_s_axis_data_tkeep => static_s_axis_data_1_tkeep,
static_s_axis_data_tready => static_s_axis_data_1_tready,
static_s_axis_data_tlast => static_s_axis_data_1_tlast,
static_s_axis_data_tvalid => static_s_axis_data_1_tvalid,
pr_s_axis_data_tdata => pr_s_axis_data_1_tdata,
pr_s_axis_data_tkeep => pr_s_axis_data_1_tkeep,
pr_s_axis_data_tready => pr_s_axis_data_1_tready,
pr_s_axis_data_tlast => pr_s_axis_data_1_tlast,
pr_s_axis_data_tvalid => pr_s_axis_data_1_tvalid,
clk => clk
);
pr_2_buffer: component pr_axis_buffer
port map (
static_m_axis_data_tdata => static_m_axis_data_2_tdata,
static_m_axis_data_tkeep => static_m_axis_data_2_tkeep,
static_m_axis_data_tready => static_m_axis_data_2_tready,
static_m_axis_data_tlast => static_m_axis_data_2_tlast,
static_m_axis_data_tvalid => static_m_axis_data_2_tvalid,
pr_m_axis_data_tdata => pr_m_axis_data_2_tdata,
pr_m_axis_data_tkeep => pr_m_axis_data_2_tkeep,
pr_m_axis_data_tready => pr_m_axis_data_2_tready,
pr_m_axis_data_tlast => pr_m_axis_data_2_tlast,
pr_m_axis_data_tvalid => pr_m_axis_data_2_tvalid,
static_s_axis_data_tdata => static_s_axis_data_2_tdata,
static_s_axis_data_tkeep => static_s_axis_data_2_tkeep,
static_s_axis_data_tready => static_s_axis_data_2_tready,
static_s_axis_data_tlast => static_s_axis_data_2_tlast,
static_s_axis_data_tvalid => static_s_axis_data_2_tvalid,
pr_s_axis_data_tdata => pr_s_axis_data_2_tdata,
pr_s_axis_data_tkeep => pr_s_axis_data_2_tkeep,
pr_s_axis_data_tready => pr_s_axis_data_2_tready,
pr_s_axis_data_tlast => pr_s_axis_data_2_tlast,
pr_s_axis_data_tvalid => pr_s_axis_data_2_tvalid,
clk => clk
);
pr_0 : component pr_axis
port map (
s_axis_data_tdata => pr_s_axis_data_0_tdata,
s_axis_data_tkeep => pr_s_axis_data_0_tkeep,
s_axis_data_tready => pr_s_axis_data_0_tready,
s_axis_data_tlast => pr_s_axis_data_0_tlast,
s_axis_data_tvalid => pr_s_axis_data_0_tvalid,
m_axis_data_tdata => pr_m_axis_data_0_tdata,
m_axis_data_tkeep => pr_m_axis_data_0_tkeep,
m_axis_data_tready => pr_m_axis_data_0_tready,
m_axis_data_tlast => pr_m_axis_data_0_tlast,
m_axis_data_tvalid => pr_m_axis_data_0_tvalid,
clk => clk
);
pr_1 : component pr_axis
port map (
s_axis_data_tdata => pr_s_axis_data_1_tdata,
s_axis_data_tkeep => pr_s_axis_data_1_tkeep,
s_axis_data_tready => pr_s_axis_data_1_tready,
s_axis_data_tlast => pr_s_axis_data_1_tlast,
s_axis_data_tvalid => pr_s_axis_data_1_tvalid,
m_axis_data_tdata => pr_m_axis_data_1_tdata,
m_axis_data_tkeep => pr_m_axis_data_1_tkeep,
m_axis_data_tready => pr_m_axis_data_1_tready,
m_axis_data_tlast => pr_m_axis_data_1_tlast,
m_axis_data_tvalid => pr_m_axis_data_1_tvalid,
clk => clk
);
pr_2 : component pr_axis
port map (
s_axis_data_tdata => pr_s_axis_data_2_tdata,
s_axis_data_tkeep => pr_s_axis_data_2_tkeep,
s_axis_data_tready => pr_s_axis_data_2_tready,
s_axis_data_tlast => pr_s_axis_data_2_tlast,
s_axis_data_tvalid => pr_s_axis_data_2_tvalid,
m_axis_data_tdata => pr_m_axis_data_2_tdata,
m_axis_data_tkeep => pr_m_axis_data_2_tkeep,
m_axis_data_tready => pr_m_axis_data_2_tready,
m_axis_data_tlast => pr_m_axis_data_2_tlast,
m_axis_data_tvalid => pr_m_axis_data_2_tvalid,
clk => clk
);
end architecture rtl; | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/async_fifo_fg.vhd | 12 | 121997 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v11_0;
use fifo_generator_v11_0.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
--use proc_common_v4_0.coregen_comp_defs.all;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
FAMILY_IS_SUPPORTED;
Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
FAMILY_IS_SUPPORTED;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising wr clock edge to issue assertion
Wait until Wr_clk = '1';
wait until Wr_clk = '0';
Wait until Wr_clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait; -- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Almost_full <= '0' ; -- : out std_logic;
Almost_empty <= '0' ; -- : out std_logic;
Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => Full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full, -- : OUT std_logic;
almost_full => Almost_full, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/rd_pe_sshft.vhd | 19 | 17676 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
SOOYAbmSVdMSmEhVcX6OANZAlRBhIeIgp+j8aWie5qMiZZfkKWRKGFlDj4dOK2MxGgpLi60kolAl
iwo8CvQQmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XO8hvx7ayNrMYNs+QowHbS9oiS1GjnY7XWvxUBWvS8S0pBwgguPJgxI5Jawjx75IEBra9z6gur8D
+8bJ3wjB5uOzP0Op4TufbsYZTMy5/IRaR1m1haAiZDNWpnRaJY0iGIl1ZfXnFFB/FNm2d6rg/H7b
+K1wV2KmxNsYmhxGeUs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qrXPktUjITPZaeyYovMGSvjyrwEeWSEPCoXArB49zu0J+taotc50izauZkw4BvtuT10+TUqV3pWu
H2Y4+wBhbI0avNdhBTQ6WysNgxNkl4xSoIMSUDeWLPrThpvXqf5EM2xFWnYEsoSt1fOlTzsbNp4Z
xTF0/8eRzGcTqQK8goNirFS4li1yNxnvMyocM7UB0Hgwd4r1WhVfwqexmsE2F2aKD0WceDfUKvzW
BkaD/pggzoFKe9ZBj4krjm5QO6MJe6tmyETtklCe5Tp5KFVAoUG5SSUacYfOW5JRRQQN1B29KV6+
B/PXOjnEprmrDoW2/GvnZUOJ8iICUgvcDDx9Gw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RfdpJMuL5lneUspdc3THLHWNRfMy7ZKvo7MAlgXNSeMyJ16shj6csIbQx7zWlYY0s5cmQ5qBeuky
S0nRybRR8cWMHwN/9rEo4V+uesao4mJ5GbtqRFTH0pGXUIW0hSA/qLXBAZCtANiThLFmTTovXGQx
QWChhP7QcQZsZBRuEUY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KfAPtRUOpYg8KaNj0Wxd1r4Bcs5Lt64mregrxrObBeYBNNIje2iGcuv2d5+PQzzomKwP4NoGlbzx
CSYz6XLlhFat5X0Kad65Lvso8ilyZLrxVgz/cQQVMyGtqJsflyi+jbqMWdWQzDlLboEzDolIGqLM
T16l7bjdTv+UHoBJFQNNpgCUB8RCwZwGjuOrDkNOQRBxFbXP4ewZBD1TITGRJ+9yag2oeIszJxFS
OnxOibAvqbpn5K7zetHoNiQFD0HLxODP6ACT7OZWy2QVwDRr6smLhIBBF+7E8S7up2WgvZZ778OW
7Swo175PkHbmEfmpa+y5XkNQNOq7GC6XNCURkg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11344)
`protect data_block
XeolcEv1XcxF/7A6Cf/Dp/bpAs8ntvHlmi5MxmmgThFenKkDUOe0vGxkk6+KPD+i0agVeShdlmul
lMhEPVzitkHiQwmsXhdtyH0Dng6XgzNj4avaL5TqEPpu9Xajl+B2bCTGRPcjUMiPxZNI4MMFHqO6
tDdxK9pjDipsCZOeCNolfFGko1pVMwWAFlRIR4D50wi9T/+J0yVYS4CYGj5qYhO7+7TTQK1thbKn
kM62L9XgNsvCbmrircZTugxc9SuDEHzFq0r9tcze3bIUqrFd3nyvLpXbgCHhtRBAl6j/kabk+9Gx
QKoms8bbim1d1wcIsXw5LhAgHKy3qF9LgDygsJkSclgn1Hh6VJ/2MyQRpWIR/D40H/ryvbLbElnr
zrPnbwPob8ezkMHZK//tJHJjmU7iRaV+2fOQJsYFrZJ7X3cpnfOyp/3zUqc7vYCJ1UkXucgyDvuI
IUxc83x65pJIfaLA1JJ3goouXc3JI5g4tbZs+FTPJvStbhrPkLPtwgWJVP3iHPvcKOA9RmniO/l4
ROT1kH/TQFBlDTq5ImEP0Kf4hwSSN4yI/VaHNlSLX9ZT7S5ujkM24mLDX5Td8mv7pxK3BgEwKQqA
pbyEagqVnZ+R4ngF1w0yvzosvrABbvmIPD8mf/hier8WUNmvV/IzzWEWNjp4aQjEPnFQCkDMEgjO
BaL9mwiZcqyOO+GGEHzVLrWSKloFI6QUmdI+MYhnaF0pKmEcgrbBagOP9AplMKUEIkasT7DHZ+ux
Ns0LsSPZNF4XEhx9aOjh3zgTyFStvoTncRMjayJBXgui1tBZJv8Sd2LzSfICoo4tHBKmeiP8KGXL
9J3yZ+bH1zd3DX1UmO2pkelXNoUcdl7Q9qDq81oS71Hpex3QjIX4fEp4r7iYsWpaxN9MtKdMbo2u
6W40lf9UE9zYWHpzc0CDjMFWxHr1r9skErL0ekCBsi/+gzLShTn0NRkD+I+jG+jXuIgxklh7N/Uo
70KyXFWaNj1b+I5leANORV3xOZqog3EaG4+pMn7ybhVGEP8WJsTsnZ68FhBFI3J87nbUeT1r98h3
rLOUWMa9XYTNKczQeDItxeh8soTh14w7eGcWc9rPQWsQXxLfzEbBVeXMVE9Dg3HiwljH/hATwhXW
df6Yo3FnoT/PxrVTsvQKy6tZrSiym/INej40rpFYW1YS7fQtsXSaWE2och0I6Su8pMHoVeK9Hzow
buchIUa1iw2I2gm7VrtusU32HEnH8pAjmUR/PKDJ8Lb6R4wrrGODW4wSpZoQk7Z633Y8oiUULEkl
wO16HKTMY6Mc6d6qpaXvwzK+JyrdOZPCdCtiSWd6+CIBPcIV576A8CVlyhg6Lm/DpPDsfLC+ZKJ1
wuCqt6MH42MFe0u00v7OD+mPxXxe+hI5TlEsHArXkPwpCR0r0jLlzA1/B3qIgeww1V6wz4bryJue
7CoB8T13mmzje5npARdb37cYxH7Vmm9xy+lybrBrhLuzMle+Ba0MuSvxYBLCA7H517od4+Jj7SoB
o3xTvbV8ySynOhqPOScu6CfZkjqHuzF3kbM4xdtCWMwCcB0qOpE2kGqJj3aixx5SyC9aGsP6irww
4Oc1vaKeOPr1ZaCyhmLlZ8ABseCPB26qPGbUOqs1aEQcd4nnVOdNTsstuCI9iTNouOdt0GNbPgFo
hejT2gCPFeAYKu8rAJ3xRgtH5qngZtFxuNiudWRQWftoxXkr1ZnwVl3sni3+joorOEaeeO1D/Jm8
t4gFEdTYq4QH70SJoGaVyJLrD3WmwBZhW7lNjSgfO6OdgL/6YEElNABCS7HYa5bCuZdqcemfdvIY
5huyHnsUOIVAdy6NLNWGjc1nnMSbV7uZxVxktikifGkMb3awY4LI6wr4Cy/f61AM7A0fLwCifTET
h6nF3W++aXIzlamMzNS4SFj4L7CvA8RWMb8jGp0rMvA7DF5sbabIMNL34K91OUrWUyIjkprqrY8h
PawFRfjDAM9rNt3WqCiC2Q7QztJ50v2hsFqO0nX/Uxg9dPShUtF/3MJWYCjdy89l5CBmwBVt6T8t
wvBSigwKP374L28g1dfd0I6qEU1yfx/Qfb0RwNPCCY46Eq39FqAL5yNl+PMCk7LtCni40uq4cBex
90wz5QuXl7a9a8U2B/N464DCm/1JIg+HD8yDLtTQ/CByhEt8Add9wLeaQrHT0+YHcb4GuXBW0CmJ
iOoO53OTF65OEu3DJ7Lbfb/MBeja0milR13Ph3ouzJxpIFwvGPJ5kMRxDSKgvP36bf/RmDeG+H9c
jLjPaSYm4VPgYvR3iDAr7xtZz7UPbQisL8mW21Vl/OT1J8bJ6S/FUytOqfxUoIB435IYYfUS7Yeq
baVhVSBm+r2vMcvSyLejKkyqdds9e7Yw4lQ1hJ1U/qayBgyvgQAnANln2DPZkUF+N4sxsDXC3SEp
1qnRysP0Ys19PErcjFlh+jLqOUGerKRUC6jDqujo9fC20NTor2ekDTNU6wJcEKZzVXWyfBZ6dT5p
zz5LoBeGAnpRN+Pj7kiRKfs0g4vE5SMq7YY+Z38/DSUfPsfoEr6J0IERQKr7f9loUSXK/GRzMWke
XoTHzeYzQI7xij0RFU1Ua2IW5RW9dkDhyd1V/HWIjQkXEeCybNWMtcwoDA1OtZpqG5uGoKhvBj/P
gH3oG+m7tPEtOl9s6pMWAAZv5QRkCQGeDzz/nzoWhygMaXfMsKUveoE0Cc0XB6rk3LrYOMfdYurz
RER0/iJVWaI5Sx5iGqWgjsMJGUqnOKvmacuCihTCAv0J9LlhRGv4LZaowff/t8iLh1BkPGWhjI6K
ffyqYz+p38eIUJbL0bA4AR3O5670We76LGJbtVLXYa8tlKDTZFkxmw9RHqTjLVoheH9dchJQlGAv
rz5xaCtScpQw+bb1bpOpE7eI0nRzYlPMkmX1DWpmtJ3O8OA9m5Q9OrLtld7dMAUvb86uJVJqEgUf
4apH/QJgWWs+ncSl7kp94zDEX6c8wgjf5dyTBDB6OObzhnewcBtuz88bZ+CfyFL1iKYzCjnIOpdQ
vrplaPXcAQ35Z7JsAXI7yN5YhURXqaNNEk6YZ0Y9zxqB9ctseJsiegyTZ4SGxZwfJueLGZJNiYuf
I9pI8qfeOA9UiWtePLInJBHOa1Vp7QVBTGP95Vh3rdF7gqffkyx1amQvMD/c/De+qLSlWAQtmcBo
fBpIvOICxQaHJUf/p6fqMJW2dyguDoCPWAJtwoAz4AtG27wVB3yHNQuoT8iJW1TLVIWh3tg3gD4s
yzbRMl288A9SUVhNKw2P/UQGPCsRoMk+6SSyvxm/2xN1e+UOe31kgSUyeyIXn5qM4t7Wr3jQJQT6
JLOdoRe8omx6RzarvpUJN2i09PRM/IBqugWKkk5rnDO0qSxvtMqNYNEnboq+1wyOHN8kLSQFCCtR
KTRkvvocmo/nk0c443rLCB0IB5/RH0yzsuZT+nT3qgHs/BOCp2nVW+1rN5rxriOyB6YiyMgV9grX
6gQpTxBaB+CZzu/MWszLT7Hxljb03bjpbc2OHmv+Az89XbYvHhCX9F0grKoVFaHF6MA1R1mCUF8Z
QOGYkS+sqyTnV+0JtTdRqn9L3wbbTX25uXUY5DrSgDLkFFCLoY+C5Ahw0hwpXv/TllHND8jiapFC
Fg7jFcg83cR1RvwCMwB/GJkGreQMYCassYgnH4SAbTueUad5o+yPvwTGiumWF82+nVK9ADa9CKNt
cNjER4C+LIxbHbUaFfFv9ThTZkyEjrNpQRGOvGw0W85Uo1yIUtWBhFP+BNc0Jfuo/2lzvWeMiWFO
69J3jRmhBB1uB9lDI8OIHH2Y6Ic8vf5b/+bmbUKU8xHgiuGgUprj+4VLCHfaNBHzqkoWpDiY5wkF
AHFkfr6UeKfIqlm9utGfcmnS9Trbb/bgpMAiL34E14VPCw83tegYsUVhu4fdxD4XGbPaqvqEw7fv
6+SUSP8mZM5hFnE0BfnhIzHk2gbWR9FRTg+ZFVs8vzv0nc0HDzh9d3fODHlDjKjlWvZz+cdsgaJd
bvB83ciIv1EKYtWb72pReFwpD7tLkPzoIz4FA8uCAh47z6ItGXBBgTDcNiY7vw196io+45HllCL1
lDO8JJmB945/NciIkVekN4S16ah767SVrYdyXNtqi/Ifs1XBZZJLD1zIoNy0MHZyJbXpTC0FP1Vf
bd/6e2yKdSTDSomrZv0YBvj/gasF+pPKJX6kjnQopmxG08iHB4IA3xTnOiMDzo9XhiKNdfys6kd3
9ba+lRtW7/IhegCkQ6EG5PGFHkHwOaBAfP2DzD4up+tVyP8ZUsf1cX+100p5yPFQHdRiPAYnC52x
kGxqIellkIvmDwaUgaT3OrrN0EPm56qkFHgfzpn7arjUyOMlhRmZC1QOr8tiadZHeSn4jobU3vS+
8XhoQ6Tu0h+zdu/IhyH5V2Jl4d2k6rWmB+CaCj4jWV6GXWKZu9r+r7XxAS+21RyzsL8NINaW3Vtm
US1TdBewsXWdte4t1fkFGsF24y3hnYxbnapPqlk0OH1Sf+CZFh/qoXatH91kmlKHtk87lXabIrYD
dAD7xfRR0vXFxamBqxJO023EV/DFc/6uYTkgwMjVAFimb3gVhvZd6ednrIzBS1VoB6J+Hd3ZqKE+
wbLWOXZy6hqP2gU9ZCp1ExvcrVfpaJ8jCFvpF+eTDnAdQXZkQqJOO953JgQ0vzQEEf/c9QVdSaJX
BClFYFLqijEQMe7SZeun3SSt5rFxByBjtNk8V4gWy5VJnPwycZemfwDH2tkiMRCo96PdOZCWB4a3
GhStAn/E8WOYjaAcV+aMC5jPKrDhCGogbDfLWW9tij8Dz4So/opIlrDy2bnotKwSR2XHpKNS3eLs
Mvf33ce1T2V598uEpEypAItLaq7z2kf4ITyJaktmmlT5FBvXtZiUegOetSbJ5xPKeN0R/3RQW40k
gFfN46ka23xHVwxjy5g9+H6dbKygqyowkhcikSxnM9zQD+4/td9IVWfkGdv1iuQPGfXqWXDBRL+j
DwOxJM+BoFjOU/D6wrTVjdkLkALiDiwWrqIo6ToVoj85eqXufNKhE9uZ4BRxULb/mfNAIWSxdXh0
a7J1nY7JatgW34QbxFKJQaNEMgsvg4iUhIj0sSyNvERXGC+LOAnBGPif1js9GOJHXWtBMQpg8J0v
lndKa62tIv+WwyMQHashAbfi9cxahuv6ZLmMXdjSAZtyOCbjYpQwTt8GJNiT/oM/7wSvxIIrTgWj
2qRy3v6ykY5cAsCUcspGptZhCd2rEKwCJnpHSyb4OKObfvFbSiBkTypBaJjNXIwpXtHKWyD9xi0N
pai4AFlvanFVznWWGqYZbN/VuZMwhtfxAFxcVrMcsW8GLiAzg/kOPof6mXniiRuVpIZl6c65mswE
4PUQG/jbkZng+IUWQara6ftVZx2WlYHJoJXIWtjzVrdXnjmqA0zzisnTmDHxuISxzLU0eKrJiP82
b7i1TtXdbpAYBXkBklxH0NKfAp/PXPCLziy026Zi+fX0lMvncFaABgw04tLuexYxRySydPZA2ppJ
U2pK1m2cCKYSUW4IBSo9bd+MG4HCie6R8s/6lq7vlTnocyewlxSFP15NLtHCXo0GthZHdgVV0zHM
jIaABAP088jiWtIAaL5jXPbM05ihY2u6KC4P0GcjzZ6cl2iMen+pF1iRO1VcNlH/95JvmATuh4Nk
Uj6R4/BWapkmi3l1Oa9IE5jfi5ymOuMTsfPjzw+JeS01clSXCciw+nmpLmLZscXkFZ/J0LD77F1h
wzkIHCv41nntqMUyQX1jm3GGhUdXxq+XqQh6Z85lTdgpRSGmMRQyuR+YoAkzSPZuWRJ7Rw3MpAI1
RpyAOCHczfRTuEyh1H7Gw7HOXqYFX4ZitSBdnVvnzzu1XKN4p7v+zL8e1CPi9nYQQ6P0v1C9A2Su
UEiPTBPGqraj5daUnuXXlgNudYpJLcC+oTxXLH7Trel1gfojQXTughC/H/elqybGtE1fyOisiVWi
0Pqu++rZ5kLwiYc3tie3DU7SvTCgwtmnjqHuzUIcfB49TtpPO6eMsZSH8xdX2J3sYSgGilAWyVq0
SrPowjYUqwBHH96xvhRJ2ly3LljsWB3i1xe+/hxi7mCcUz2sIEaa9rjga71y4EiusptYQiNxD0SH
w2gcO2+yUDmJhRNA9RHTlC2WSeHWSI4kpvKswljP+HuhxttCy+Uskww/gDlm1I3nVPNGFxgwBsPA
jcVr+bOrqj//xtR0/rQTTVyWXrrPEaVa7ByGtfT+cHEvAUEIHn9/Esmt9Oddyyw+oUCStLIBiYKL
MGIrs1DcRNHUaNTk2EK6gTX6gL+gT0YtQS+0Y04/T14le2x2YJqT2ocxltSJ5FAKerdVfaGT/ztK
CLk53UtdPUczBV3HOKOAhNPFZeyKYrDMXm6YKO2IKQ3DaZN77d1Mi04fTjUuoQuuROEdhXg3iaLC
FBfHnZP8lqzqRAf8E1J4paacrnXbGF1KzsPlvIdTn7HROC8dvslm7LIn+iH7EoJRt/9EmN+EN5BU
l15L/NONU3Cp7NgGhg1cM+VIu6Q1xZpiaLBba8PV4t0x5RExJEztZBUkbAPi76mYdDGQo43CvkJO
pJSdcmZKMRE6tQLG4Y6sTrPsn2+kFX0ZUJXPnCyhQ4ROgQ4EVxk/s85mYSnUH29jXS4tew9Q2vyC
6Co3vN2T0NeiLG9APuS9uOPBXSRAu88wyCPOzyO/wgqMPAf3HwpllASTVjIHvts9aQfBPLDTGNon
9n2OPyq6us7v/iRY2EJPYXjPakBgVb8wx5wVIv+wDoFO7URMYHlAvMSJf/pPX/FkYlXMO8tKpCKY
NrDFbbEEsR8kQIkdlT12/OF86qNmsE6pxYzMrRuhfFJs3c2UbjoP7eipL0VHrm2qBY2riJxUZuOD
o/5MQgOHM9F+t1aAPkQLZn+HJUhZ3aYfkIWc/VgHwKTNIQrBDslJOearNSXT/SamX0S3c7a22WMm
41MZzGDS8kqrrcWORJ8J/lD0LDYiH4fFnfdQn3x9xsaJPAJmr+Xv9QulJZ79WCw1G3PaYfhWtOBc
w1bkE7qMB0XDoKUt3aegQUoOLlG9rCe2CczWjji8tk/YNxLy9thSvif2SQ1U+BDBov6y31hvhqWL
ZBysvpWErkL92wpEVekICY5HZwWoz1FV4u+COOFG+paORI2dnOvDRy6EZCds281fNe0ALnOeWQ1b
W0eaZYAK8sR1rh95+/g3Eb2kBwATByMa9+1KT8DAaKitNVrA+7MOdIaY5QiBXWZ0jkXlRdOYTloZ
UT5n3YrMJaxQvPL/eVwhg2+8kueevo8BlkYRxIJ9Fvjd5g9LRSpM3LAO+5d7awoFtb47sQ/EKC6m
kKlMkCerRo+0865ZoJJdCIRQUSotypil71QED+QBqxOHgfyOsPIPxI4x9n49a7KpKjHqOxGI3oTh
nNWpyCSu+EZOSp6bupnDob8J4KdbMtYjKsqL5hZzaxRcMNZ1B6Gw+6ZgFD3ktdoxhoXDse2qB4so
YxoRgqdbYsEwPxXlQ6ceipdFvOah57o6UAuwiEfatvm7Rcbu6YDw8W2JWVY4NrfM9h2KnjWPUUt+
s1AQoilEnLjjrxwPvU4aqI79rE6BSzfhzdNyqnSu6mfCoscB3a7GHmfIqIiol8pDVvncwwlSPMd4
kGUT43DMlW3dbCozFFTVy/eooW7m+ojIZftIHwaarSC9/N+CfFZz0hnTXa34dn2avrDPb/FpK8aV
ktRFPb8j/OlFnliRnCxxHAlCUeNWICUxk4nN9iQOsj6ldHB0n1Yn9ZqlQlz3ps+4EnrJJkcEhxXx
nlYz/S+dUSxL+/cSou05eY5+ElN1EvRo7j6fdekD9xX1vPfV5zbwX6YM9YNOX2PUt+iaQEgMEcoi
p36amET95sNQMdBTfNG1KHpEDoM5P5GfcAaDIUrxsglJwwZ+it/Fzz+bW3MSU5+TieROr2JhypVK
grLmPkyOhjc/m2seMPRgjKndZ3MfFj6WD+PZE0YCEJ+kT4zof1gBelDaTDCByCkKa1kEL28UiNbM
tfY0b+quh2wFHCVL8/wv/HSGr015myjkjE6vxdmoXT6llbXvu9IPYzMWC9c2SbliEOQJvIlIcB4G
lOf+3JQn6njyv7HKOZYYQurSsErv7owht4FvgNxoV6KsX42+ew50VUwRFeT3tpM8Nnx8Js9x0sHP
Kkmk3QDuf4dCmItOxbVr7veLWSZnl9zCGspiA0Boxms+H37uf6Zwtzxbkk8jbLlKxeCmFDSludcv
e2Iarou8Fk6jughFnYf8SZdAJQ/WxiZOzS5H/fqOOUMB9fc8wd2vmzwFN77x+uPTfYMxcbU1ubzi
iT9cDAb5n6Mfrc58+2Drkh862VSngQN19Z4OTpRj0QtvEkJN5ro1qOIrUj0ApMHo4YmpBXp6P+i4
V2H7LMVuh5Wi6eI9q+VEz8Z+GUErD60CL97IAesFTfvKfNXBPDXSxGf6SwZGnehseLuTGsVHmvVI
3RuKx/UgPC3zOZFZnGzKJ472H66DQX+2TNmmaq//VQnXQJ3nOV04WqUHgZUXbWDhAhwJzDtriSbJ
ZBumiBmBgcQhXY7ToKXug65BFS2k5AGgzGfUo36KC20TBbPGjf7/MyS+9LIqGVRga7Rs+qNuHNgS
a0SelVoSE4/4fcfwe5/LIdi6haCuO47j2wkLorGnWpv6nM9r6gu88shdTZX+UJm0Y3SL/LJGURao
Vol+iEG6sjx2ePkh5zGKlM2sPlPTuxdcOpWcWQ3AcWGdDUEzhTfiDF3HgLUyi7itDNl/nkFO1Mv2
IOasuYfF0S6qMKgZLEuvEOIVwTFANbZT9vGsNjZhdr9iFgj0aRDwm70CXxmJ/TNzS0sZs/N6GKDn
CgbiYSTIKNracrppaehUM/8pVWA6XlcURKrzJW22K4ntPUonRIIKG5IjmuZqn6i5NoqI5hsD15c6
qPLkWvSaZenYhCKQkJmqNsZ64HQSMtT0QkEScIVoIChSxrq8e/FbXzXSZeDO4bFo9ioGH5cKn4DI
5IH/s6kQZLNOMdnNg1NZSu6+hHffFSFJMNYsK68sxvf5meb3wlGsxq1yNJ+aHXn44omlcxZajMUr
s/DVoVAAJEejuLIbaWyRAGDy+quFF9sHIwfq7KKw1UdkOq8Uy2A3dPKW1ErkN+zVGO6VMV6c7izt
/TYLq6Ky1sikViIPoI4DWYHCTJJHJuegV5yKV331520notITENCTpwoKyA3eZeI+0CecNpHYnUKw
RIf757tBB4AVFghHBbDP7hG52jsD5fUHvTC1wmVKTTCvEQwinIgj6hVVASWc6WjG+dAnVbr+vBl3
LZcGRkIP+55ZLp2L7F42pimj8bu2VExoIb3G7ciU4JH5lU3nlzx/BB6GpGq9k+r0IWjgPcjEKB/i
NZzgK1t1kGTS2UrXdA0VGRYVYk6fo6K1lcA000Kvjewo37GS7mU+w6wuwsnPUTG2luop4p+rt3P9
9XNh+C9CWttjppNnCCrpl5hDMnALxUm2Tqupj73KYs7+Se0d5IMX05WVX6qVVPpV7Le1cjZQyxvj
RSGol6ooZiB67LSgQiunUG5XT5mq70vFSqiKyBXWnCg3DG0XlJPOwWw3sl/dY62kPjz5js9F8e7/
JduEnSs2uxrlYWdB2e/OlpCqNwm2Hj84jY8XQErFqr3GTD4OQXo11AEWZ1J0n7yMqZgM2G8qYDdG
+IWrTS+sOF9D10zdEYAfu/tXekpwTRp5Jns4Q0zksqhG+wpesq1kbvD96uesZsZZpbEb7hXwFtDj
3hgXmhmhPduax26KFMdOVGpJlnH72iGZAQfN+nV+OKTWMBxJK0PuGOzkY+sYnn9BZk2BPXS9MGC6
bb+yzU3Fta+zW/DxWOvtjaQ86cdjc10S8ljriCC2L2JpnGhbRBHmU6LbtU2+Q3Qpg7rwRBs876b5
0gfDz9HkIBpzuMkXSNMuHszTqlLxhvM49eVx7orF3XidqD030a2R+QnnqClCHFJtSk/ug/9I5VoT
HFsV8WqqiGIlIcyjfjAHf85pYSUIbkmOWPxqOkIg8JoYqLmhNsrdaKNNtRkNnplLDTJninucxPgE
ryVVP+Ol0qcy2KKoDZW71K4x2ZOFReI7oT/bRfpLoaT6mPV7+jfeO8xHp+Oc9Ez7bC7vhnmg5Gb0
MvdfOBziuFjrI58IlJdj0bcOCMmrYGLjdS6XUTEyhD/1JQGo2EJdyiA3nVwfVyYtwFg/8o9V3TwV
GyPgnvV8hlNsHbtstAK2Sq/G4rA6EM5j1+Ti5BlTKhabNK4nnwuXu2OCt5tok8efCJa2X9YQwpQD
uDmGBwCwD3NAH9cPDHWBt2OgLHZAnYG19E5NhdWzpadnzwb3erlfefi7pe2SX7+SwXYw/OYBv5AO
ZmFm2pVBOjrlgdzraDb4ZMI0WlffK8xPBqJAn2s+54wvZ9ALVCBEoVGueEzSAPo+UINSxgprQA4/
YyB23dXoLhdMsTZLkqxX1YksdWsCeI6NTMYQRZXLf6dngrLjzcy3yNfYF7YiGVi3mvuFyuYpKVoP
BZecaMEuxzkc2GXCLUcwSsDjeF01w/r1GShaGoNnUOK3LvZGZUScdLBZtDrv3c5XtzkeieCDopfi
lzchLt2GQ/SjnJ1Gkhl6eUBEk/bwmnMnQbD+LYgwtDdCMfidkWybKMBU0rK9v8I1oYZDZYmcN8XH
nHUpg6/0PSZyO4Ibt9ySgRE55eeUBhESBx2dL0xoQFMgKWGqM2TWz711ALe1VV/Vwv8JiOFjJOyV
hScwCnJ6KfFOhUvGs84Gr2d2KGgN1VYw6PWl3S2/ZTTi/rK0adNuci7vV3h7BdBue1SVvzOnhWm5
fxPUxj2TH5tpGA77XqnmlW0LWZgpFkUzta8RTT6cB8ML7RRDWhySWCEyen0ZiqlgzG+adLMakmT/
7GP18HYN1S0/kpYr4XVV53qgyATmxq1+KpLPlWUwpjQ77GGGjyiQz8y/xG6zpW9p/syAxuZRcP4D
s+6qmSRm668T6lWs98HQar2qykvi6PfBrHXX12vDvUz+g30vPVZ63T7V5qwJRyBb46DMXDmXnBD7
97twYlSqjuMzqu7kQmemeWg6CLxNPGI5sQreS9QTDCCHM2c/SZyTTsK/13kd0Nu7vWBS/Nl4A3RK
LAfYAp8OoAgWAib1HnIApjXUa/v9pWseM8jFgSH4VXub+7yh8y4q4sTKwwwNi91Dm9IRt0b4iASp
Z1YdLDhs/ZrTP0CN9bTRdS9fe6mhIr0YL1ngQmRFwzAvwN/rZTlTDzKJdcY5R6vnZ7EAGnnFtPFg
Nz1L0fiegQQLrzyqes1xXCD2ar9WVVa38lN9ZoC5IIK+3rxIKb0MZ+gwbQkeV2/cgHB1eUU5hLTH
Ro7QjLRjnuML09RT89r8ACPqBse0elXhO8QTRLrHNNUJ5sdINiIYkLRSeXQtU1I3TM/lFw4vzx48
ToG9X49Y8YK+1mL5M5sesr2hwXVrLEIpdEvNRHjDSjZNuldyq4D05LdxlKHDXO9Wt0okOvebwtie
RUyJcNyWLUSDtwL0zFLWQZ01d6c4fmmYYL2iaBMuUdM4Due1pheE+KKDKkubZieKEK8J+VuTwtoN
eWfIoZmahDvIxcvciNtadMjfcMjAH9D3J3BVvHX1WbfYLZndcd4ChJYEcSnbgxLf4J+ulgflvydA
uKM1Qy4FE5XSvZjOLikW7ZXsLbJwSKZb7xgQ6Vp5gvPFgF+MroyTW/frpA8rBq1r04XVU+tTIeJZ
102jsjKCB+Gx87TSwLkYimH7MX+OWCg+Q35TnyhOv6lIBTSan6hAMC75rE5eQ//R4UF+G5JWb0YF
zafeNEsPgiqOQekdvPB1+IokNY5/ghAPwrUiEvv7aU6L0Pnwsmkuowfb+utShi9yPvNa21HscW7t
9/SLwMeu139kNtN+v6tj4Nq9dK8eWzlU+Qv7fCAwUSB090fOTSboHhzi+lqy/RvxM05XCYpUg/BJ
ikLO0Wl0yG//BWZLT5BipOTlk/fWBwwhQpXTed5ovGNWiUzlZpoCimSJ/yNUmv6EjJ8bK/RCLDz3
CF/RehrMikd9VLL9DdxTEoTVa3N7sIrXBgu3ppXYKo9fP4+OC1qx6JClcMKit7zWwNyX29oqNGMW
lN8gJJZF7oH7YMllfRtmWz76K8CgRgPlGPhelT1HiaL4s4LrvL49GvxWz2ms1dYRcG8OfnDbQQ9l
AirrCWSdQcN+TBMmQgWc6m6ipyWJK+XcsM40OnV4s5s24d6geM1FJm2/yX2lL7m8W7umwSU1V+HG
zKGuiYbVVnhfvoZFsuIItmzsMb76NhDbKvhmGC+8FRUkMKvVdezgIcrFdQ1WuorsudnlZAO6OnTx
G6XthRrfkEWoNeYxyVBW29V1qQuyAxwbXdZazJeDTcfQUjYg+9y6cH3apF5Azq5VrDf2VgnStjGu
hwK5ls/YWMZEjTx3cDnHJCbQT/QMBzd3de4T7v9UxpwIYaQQ47/NdoUVVDXsl/7PMuxuKoNhTeaC
3Awge9XAI12Aq4OtQXYXBuRzQbK777YCPx/xdMxVC0t/4pDpi3LLeB8awY8YnftMVU0RND0DOKtG
LFd8Vag1tsBLWLmL/TGNu+Pk4rG00KWYhaXtKBI1HcsrriGvTWKRHu/R/b4+Oh8P/zNEQa7N2bj7
bZpR2ALSHlHky1qQnZBdXQWcvrAGHtj6KbRvlEjHZx7GdyS5MfTVmToawMTrLbuv3o15BFC+aeGP
kPF1AYs0J5ccxLd0dBvu0+hjj7Ah9coR2f/o6E9B5A8sLIwRSfUgvPtg/W8c8sl501003CE0ufTC
Od1RQD72gvditdONgBdgS2uWpeYFHfHPSO8RB8SP+aim5JBd1/7Vqspgu+UQkmxGagZFCLRCI688
a2HWoF1oQ8WsjACX006LS/gYvBl0zqPVV36yNnx46CCUB3TCwsEFsUg1sup/3nuQ/oOv271FHEc/
8bpPNh4ZJgzXcaNB/+vjc7cswYwAAKg4KktO15YwG5qIP9liGt6/qXXZSuCDzCw3bg4QDmuDJxTj
fQsBl+ttV4ju5zDoIUyfbyELesJ2rjGK+JhFSgi/aFqt04qHgakT4Q91ineF7Vj47YfFWoxVcg+b
Hu1Vz+HPp8FaGFpIZqAtoODpqHX+yTkf0Rx/biYfON7imVMPmNKr7Sa6ZzYkPSXfX8liMBxlOE4H
8XIz4fZQEO/7nGQgBMWLeJQjapYsQVysLOu3NtNX3jAy1gZ1ZSy0Y2jwgQCCaZMwu++3z0eEZtOQ
0JcDQXsBKp1jkOAf10I8i42A8nsM9FCUZrkLD2A2wSEJoNTlivNMEYMrXcElLMAJWvqhPskPF6+y
5h/Ui0SicXgpJABqGYXTuQqLky/0kGg6siCMK7yMFFtruXeZceFZLelXffxS+IhK+4OZWc10YP/R
IaXesT6UqkqJooPDONlW2EVeyOr0cI+ZnxAiJECsWYPD/AY1Hn4iLkx1mhfdKsX4czzu1DFC0Xbx
jYt+S1EUW1UkDW9YNmdcMYSxj2Jb/CJcG5dproxphBjHwvgUAB4OBM6jr9Iqw+TGiD72mGI9HVaD
CnPbn0NLSnBZNsb95D9bd7QRh05/ZO97Rpn8RPJMDjPRJgWkbmqUb859kvLXaMIsyX1BYtG1hfOz
OEx7/h9qsAXssWNuk914XGmi7IWIGLpPJa598m3Z8KreIcThwQrPvWyT4BCZMe87OK2Da1bnt98B
0kgyZyIXZJ7Xw1huLb7lrpcme0tktSnddll0Po2qcFfgbY87q62mwaxijaj9kJo9FCiD6V6IRry5
mNTxK2pS+faayARwOB3e5mVZmHVqUiGKEgS6x2vDmgQQq2xBZJw0TwzsICwNJ9BrvTPbvf94W1ws
yVGYfXnEJConZonHbqVOtAK1+KDILocnZs1z3wsbUYAk12sWEakmaaS2sdbw/DXe1CHnoPliILPa
o6au+zwwMJ5YBrYiKn5fBGaj2jj4SbgvHI73OUlkm99y874D/Z5ZlihOVcd4YOMm32jYi0LXwKMV
mSh8VNgli5ihIv5+MVc/Utyqqgf1tfuenzSgUdVY2cJBJMJMjCeuDztLfODv3LRAm7KJdlPNpbsW
c8gJbx1EBiCSc/7jF6TFonQ5otJ/sazFuoAsm/Dm/5ybHCitzpXI2EpUET1LbhDuOFO8CUQXSDo4
UnotPRpgpuBhkwcQckQQ2I3Q/3xWo7SOSg6fE29Ysvm52ZUAi1FDaLT4aZDL+xGJx3QbZN8dTZ/1
n8O4EaG6umNaIWCZHlmSf4f04cemADlq3Eqj+KZQW0tO9g70eiaG43jGwBclwR6OEQ2St68flRhd
lusqHkKKb77+62DamdGCuJxqL6dIvT21VHjJ8qkMlbQ4yd23pGgrfdACQ+9o85macB7K+rGkoOFO
es3nGn/HPiPOq+4x330RU9DzfgmSxAijmMBBM/dTDYTovHZMpHEw9U90tVT40yIx+XGgkyLP1zBZ
+iau5msgIWmrbQRM6yFaQBRTfCOI165rZIgX+wcrkttl8rNuD/zFq+jq2nMUmM5rtgA/N4YwZxTB
+2qqLVF4IFRAtuYLqoMREPYoFm2CEDqGwp24f+79r9eCBKvtWZDxehoBjf15aMDwoJJlaEfc9lyw
GFKNOuTT3co2DrWnMC9fRoy2NsC3wfKv6h1pUagpsVMsBvVUtAsj8iegV8Ju4j8ZqTNvbCoM5RXI
ahddM3TSJ4yt6pRTtnS/hWOVL1wV3961ZYTRncV/VGv8Rm7cGWO40E5uya3qhUuJFR1C1FMFUW4H
9jHMcHOHUQ6kr837W4yBM3P+LXsWJIc/bwigAC/XFDbLCJAgWN7R5bGGgZPSUH7tjrG0a+Y6d73R
q+wg3m5IWPSRfx02YouE6QcAnnBaqV2Po0wvqOUHGw2T3MROeHWqIj00sshA7cnzhJx61zl+bZvZ
sNrASJqfzyYvhqe+4qUOdk1glzr8VkXJLdQj8gA7RpL5ynBIUlm49Lp7ETteXbm1HSU+RNxrljFb
7E5q8ox79n63hE9h9EsxmJRgO0bPaaewqqRHnhNwEGXOkk5h7jGrmuNKumL189w2kTwhwfJxOvbj
6g==
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/builtin/builtin_prim_v6.vhd | 19 | 37128 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cIiYfk3Xy6N5OP4pq3GmqGiiVNUZ6H5+UojetFJBvbKolIu21jc4BnJQVK6clVlXeOqxCwUuMeWy
2HOHrYFv+g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lIziGPDmnLk8lYYpZIaDaMbL8fBzq4Pr1Jhh0ulXet+pjCJLyV5jakxS1oSptZ+tHYCT5i9DwoXk
484l0YBwGxIV/F50kQ4mY5SmovR5v/32XWyGw8Sob1+z/rA/iYbfy53jpQjBFTMhONxMl2jPMKOr
8b4lWHN3CKPgzR7gpH0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
htRzDc7r6AHMWLJSZlCSE/9tAboPhTxPArTqmJzMnfBntgIxMOX2YAPT8iZ7gZlglNlT/Bmc3ZIa
nj4bYkmP/Ed/Ze8J5Af7OuS/hLPfbdPEIMVOJrAzPKtgRUGYzZFakpIpDVbTLnXVCXGbnWwhbHOl
N+MoLyC3ep/1xGkMFlPyLgKVegokAfOd/5ePZ6yal5L+KR1ET32v4t5eGaONowzpG0O9uY8LtLQU
iVJDGAf4BzpePmtzOyeo5v68FfUFTjm1d6csF3e9pbQ9fEwJazksjJfyX2XYuUZH1eu5bhyJMU/O
c9/o5sfORhKXoxNo0FDKepouEYzneEXI8uuD0A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
FHtFxX6m7YezwdeWAQ6jmWMHTTCQ3ATyb5990cCrfHVNkzUwGdq1shf9GRL+uR3C20sVQ7v4/+tb
aJQn0JjlSYvQTO2Q6FVyjXNHAr7wpM4t4p6I4KuMXkNXuNp6PVpERQgKViWQe974sEr/n8wacl6w
0ZeeyAlvAxPvOHeW8Sc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WrHRD4nLu8DRRwrUtiyMH2ZN6Vs3L2kgyFgp5P9DMlNKTdIDDQa1yTQPpciIt64OlniyoYCatBqg
Wt8N5KlawExwntwLmfujXap7EAFuw40uyJX+yki/gczIgekz/25Q1+NPVfIAzqSReCro4UUW45VQ
4oIxLBIF53PvEJm3CGD200yoSxIl9Szkkq1FCyNtIufy0im7xj9CnEg/iFEwxzn8s8Ge79lV+lhg
fO4H7eA/Qsx28fzoVv2RYnMwC/Ln7iTt2527VU0KjrPDX1WGbNCJ5ny6IM/daMbuTMvJb5fz48+S
KUNyOcNxuhu15WGxxGlN6mcj5zB0r8XxgsnOfQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25744)
`protect data_block
EufbohqYXYXdSKgd2wid85QAz6nmZQlgwpxyaOJ6iU5HCwy5KcUzMU5Vk0eG7GRTWbqqwaELdsbR
eWwJt26/naD594YSUwZsF363lEqCh7g7mw2Tjh5wKmzg21ncivZ5TADtxkHoaKrLrtNTQmfg6Y7K
fch1+Fcv73dUCyijN6KfpAOQXPtfIF7QWZrdJ6k4NDCetzr7iK7HUssjfCYfK51WEKNfZRQiVWaW
z+RFZaWjJJe6UlE/0bL9T5/97oJa6aRIEz//oQnCMqhki8uMEuXo9dWSlqaHm5Gtqq3dVScF3nVU
IryEMtjK1gA0odj5PDQuJ57gNpNrrbvt7AKvlimUbzRJPzEcNWeVvl8a0iEBuJgWOmnAWZzrxZmn
3ya869WW/KAp+p3jtqrqtCcadMac1lWbKWYNJ8Q+zd2HMOetPxJGCuQiEc9sAD+oQoePJsmFI5nd
Myx43TgaFr4PoR+lcjEVvhf6vwQRxrVf+SedzLBPi4HLXn4EPxdZX4nLhkivAY/Mvf9G1DraNrLm
wqtLse9/LqIGOlRgnmrddSSjtJA+J1DJQGo+70iEFiliVIQjBThbm4oK8G3lT0bVcQcaXPKJB5tt
HuYsa42fkZpvQzPFZ9ef/S91298m4ZyCBiOM2RSb8lUtwT9DaIsDPcS+TIMnpfO+CA0eibRUsmwG
UnKmkQMjgOvBMqu2nhIPVPHtUwD45SDrPQDVCL+hJTQwWzL6Q3i1tnS68VRNtWTy75p0BgIZVAw+
d5KINDwwT77oX3MxIE7rTWsSDi9w9QAlmHf2bUA/fHxsuOxVhCCaTBntGjd9ZFGObkoPd8JDkPN1
AGb+rcl8iWOTlfiaApc/dL3/WKx5PsaKnAPa8wm1+6b1vgkrhLqPOJ5b1099jh9nitFbjmxRONfz
itpzL1PMEaLmpwiSVShcWG2MhoIdI0plXu/rO68ia37tVbb3xyarB+8V2jUBaHh+yquKJdU/egPc
P3rMVXqFBbWhhb8mXxO6bAYHgTHKAhTvBoxWvsKl9Uw96apSUF1dSdq7tt/AUfO9PL/bsIBZGwfl
vCKf5pq1UG2iWInMBJ7hod7Y/wg9xx19xqkFcvHubFHjHo4eN3mJx7f7Rr5fht7Bbf/het+kVbW7
kBZoCqNjehW2PjqUPNw2EyCLwl3mAp0eLNYcVNxqGbSex0XdefPpw0xRlP52d2tUabAmitkITope
Kpwyd28XQKmXS7Bug9S0XPb9r8OcMkdN96J1RaNlP4VlKEqLOUAfrP04e/csu/SawPSDFJQIjwih
7K/HKz3FCSHnxCBT/9KMbdM6qcIaYOU/ud4lCBg2jh9YCyjWHtDt1bEaf/lBuZUXthZIpCK+l9Kt
wSZdMHwnkSthvygcbC2g515wUoCaPuhRVeqg6m3oXzS6Wi7qvxJtA5RZoP0hlHr9n/TAVEhzVrkN
RjT8VkJWyDN8OKBzKijilyL72famQUekMyTE4gaujs4a1y9Vdn0Ll+tQKURFFaxFI0IZ3k7rGqTl
k4NlqS/mMydRScIAOVlUpZwKJudejPOzCHijyM9MEDZ1SyLJ+Hx4f6inrINpcC/Jwq3dGT+EeYfh
/0XMhfq2c6iYAVvOUyEvoJ3zlSEOPzWJabBKv2Qzoo5LQzcdq2dgLyIYTC9WsXqzxAU+hinta3CK
4nYoKsYZgYJVf2ruiJEpkb+gaa2ywKaRxd4TywuQsNgtdsg0yO2MrWVZe61smBZ8ptdpxYyGSvDe
VTFE5D/a5inntknJkiINU+hb8qDoxaVUkFb7WEsmj7TZ2G+8kj2R0qxQW82fdrOjQ08o9HSTHCKG
AnTABQ7zLVSJ3aBCXZmhVgUiZLZQS4HRFkOr+CxVhHLaLSpvvOVoJpNU0owVXwPsBbivWgDQJjzM
D+zsmzCD7qd1n6a8rENnADJx2o7qq0YPJTtu33FTvsOGOU9K1xXyf/rFEeoXUA6IG5CoY4v0sIo9
BtYnnIqNmFHBvwsno9vtRxvRy9oeiPVwM3GRu0TJidKdzBlzaY8N1y8VK1A8lsdYCClXBz8Vh3OH
YHMULtOPbLwBlBUjTtNIP3wLJX0QoKLuWjbnGl8cAhkLkcYONB7nVHEe+5EhU0OjQ2yn7/oNFJoM
arfnv1SAjAHzHeCa/ZnMkYMu0Oq7sMYh6CioIJHe6TYV7GjBef/WP8xL+KzDexcR1pHl8dLcAZiY
yy31/tGt1YcSDZsIB9xxi38eUlV4TUq07L160GoNEGTmX0EsChtLYYnBuI/TRULkd7ane059AbZw
OGG3NSO8O5sVeO4ogf50PNpU/Tcq3AVih8LfzKaJjrX1E5QeR7Yy8W2wBqzjB2R1Mv//TsfViE+i
9sHJS5GxEjIWMaFrTXgY0HS01360hR6LXsSHr8YqQerKUV5f/G8ozWyjayQ7pTwsNCZ2TGo/NzgQ
vriPyBXwfwus0Dz0HgCe9Jqr0sUVDBi4JZ6oywkSbhkXxRmKVTC4/arRMqyH5QVgp6YdrSfJdqCR
bnorb6nQ9kmR4xagorBZhRVzg6jySLqVwuYBe1tbZtpqkzb4Qhv1U/XtbSVi1QPufu0utw7qcuH6
gvFHJfxigK26sE2TAGI76t6ggD5k0yq/VYHnLIHDY7WElDwgtsdjEOTylRxt/EDezvdW7j6+iamk
tBNrlJaum2/f8D3QFqVlOZrAhrMhIWHsyqfsOQQL0wid2Ycu/ncgfZJ6lAcmuMkiw3PS5A69Fig5
woiZcu8O3rRsgMY2XDR8EwoxJBE3VDad/Qd8HCsP5+Cxv9eauUeBxYqaGirlY2DdA1LKznFjNNNZ
+wRBtTRFO3EWJkA2B2ADqIn6JcV1dQGN/pqhaFGla4R2OFno5EMZdUNUSBlScOl+DfE889NCEol6
2SJpmjjSMJkgw5dM6h3YgatJ2jracP4AP8kg1iZepUmPYvAM+BfY4O2/FUOGII/sIwnuSK4ES85i
JB0o9QFi0nxij7e3xzrxNN9A/VVe5v4ZcUGA12qX0F+Nk77yvteQxXpthfJd1SQ4Ekr1Yi7P995D
lBq9hkwqeN/+m/StFNjjL1LAWXEueLA/eAwa9gcgssvqVFVyKwLx6svVNnkLP/3wHhEANeVv6Feo
yqHPsW6Tf1OKu3skd7r6oynfBNSOEQALsDLzlK2bcTK07Fk05ET1xxMNWvQNOiyK2cSzQKeulG8c
U7GkBD+aMjAtYC0B9OPNj2c3a7UM1Bi00qI7y8AGRz99BZYHd9BAyTHes5LUZHtGzCSdGCkXnUG1
LoEezNxelj37f4K7jexsYqH49gLHwPR4avS3cDkVn2ghaAE22n0iTWu+ax0R+JB4Jt/RGEgPWxBa
0LqkNPKZ8zOT6hsS25jnhFwAIckbjs8qkDQcw0ary37mPLWvCadjxs7jKlDHWGS+D4VyIKmUaO5v
wL+NVS1xU5iP5EMM3uttLPJfoYYpCCHshnNT6UZwzS7djU/wChNpoKRiv4n+uD3LgWR8akMq2OTV
t4eV7DfQd2TA/CU4KOR2cWjB9Ao5XA6Jp7RgQj51ZT5gL4GmBQYVkwSQNamaG9F+EctTe9FRsvhZ
79L6K1jrldewaWDPPCbuO0wMqZp1alAXcs12pvqSxQhRPeTO31LhSVUWW4KhXGSnQ0ObJcZL2XHh
FMQ04dOjxvXU92l7OCjDlFsZxPNJzb7+yywM2bLM1AGBm7dNSmu0WRdIFeTN6iWt0bWv/yzZs2+B
iRnLuSwT80ON1foAZJiVoEb05jF/kyOIp71LTd8GvNeo11DTFhXOokgnZHEC7RA/ybqJRcSHpGox
uXbZGiuyGkmTFMsZd++uh+do+xX6vnYw7UHT3Qk9aCrdvw7PC1a1S3YIMTYe7JhEWvEdoG+SU8Xl
McEa92GatgEkfRQjGicEwoC4Rp0GhtWqdaiiPhKZYKAWaf8U/PyUhpox2QD+vcnm4T4wjzsZIQzZ
jj+3wq09qH0ioygYki9NGiBefzfzxUuCq4s7jlbEE0xUeWHOLEpFkBLbYjoJrsY5KjePUOkY6K85
53zzfQO/UFuba3dJGUOB9RBXHXV9WyTAGRbYwUE8vSUXQ0m6MSI7vfxFMPwWz3+z77/7qTIgiax5
0crPX1+lraifiN9UMEqmGLkW8qxTrLyNwW0LzVq/OurQcNuKmAgR8VX2j5fBafP26VihfXj+w5HZ
t/bOXPQcUtFa4MQaLgZ+Mb+nHEc2ilOn2yWMXyP6chLMuguB37vZEeoU1xNeJCe7bSWbd4jqZZeS
ced0jXLo29W01GyKGvwmF03HBfgSY9cA7oOaoUt9P+1u9N2Ah+6ptjaEzvE3W/7T7nX2B9tMZZOp
+v0KkGEF/BvXlboS2DR1xzWbSdQO3y9U5yM+JQayqDlhNW29lF8eGmMTtxITby8CRgHqsyoeYTRK
T1KHE/3gM9l9dEUPri7H1Emqne/yRNWDG0Zs0kVGetEXKzDOAPLGZxk8ggDjnBJ2hs2ymqOubxHp
JZK3xVsbMQ30y3/suX0+pE1zv9/EInsqM1hgpTzQzEtZf6RqnJEpGx9skThs32tVvy/ofR0yBmIa
3XpdR5oHyuUAkNAT/2Sv1Ma9bFL6P2PfP0Fnv6KBiJUPbJzyvkHEwoUK0V3bBoKimaZaAPBqWHyw
4VcozHz4PtERSXsszXoi6ok/VqE1z75jz92VlCtFiu0nYuUP1hEtLmD032kQt4bAhSn2jk1Du3IC
TaLdcM8aYCQchVFGPkrEEINjQYcfUCRdymuNUQyAQBHnbaF2H1RaRn8fUP7dEIq1SIt/uQeJEdY9
lDO67omDl8A3+QTwvqUINrYsd+OmnQb7WOHd0QKb3SxnJX83SESyHrRxtNJs0XPJeOlR8FBBB/MN
CYz5Nz5t0sV7MSreZrWMNG5BAkD6Pa0Q0h+VAa4sufjsJBEzHrHcSNUGNy5UDVn0Qos/jBPbhu+m
pEA2LANA3oerkkua+hpNLl7mcQqn7dceFPJgZr8VkxrxG6cXpIlq3NuL3AsdVJ9jMhh/C/NUPwaO
No83RPXpDQBlMeklHcEerRAnajGU/DS47egHhXv51d/KffXGh3DsX4V7c9AqZZEj+o1etIOvYLh4
PhRrbR1QBT4oWdte4BQtInpB7dnXkmtGo0SpWbK/YYqz5c0hgJbqqO+nRS6yoD7adzhR4aRrANmS
a6Y3fpqHFMD0Ij3V96cheB2c+TFKrxmLdFR+mDyP8pNfhWM9uNi2bwCnoFPBZJaIRO1k6Behq00f
WFabdiE87uZD5aLz/Cx9OarwkRVj/wc2zSzJXzMG7sljuU2GI9EaStWEx4jWrgx/nQZfi+xL0+KJ
doelEKtWvFwnUwY1Ur4eumm4cdEKqtArFuYOuy0oEqfa/K1xSsErPiDVyaQeeZcWklTspPB5RO8t
FtUUl7YOqrULKy1Sb91X9SyeS45Gl2pWUNJK4y+29/5MjPchJR/2l50HbBxt3inFMPePIsQaXrtj
MYWI9nYFrg51GnAgzTC/5L+WnBUo3sEuw3Y34mwK0aHrG99UtKgUz5ynNuXQTSEf7ppPRyDgWK3A
59Aukovejs2T6X4fksqzfa7u3W0WIncqhXy8Fp4pTKwEqD+bFNCsgnJJXftg9mMBqncXa5bUMvHG
nHciTm+rfByUQKQYOCQ3pxPop1SzkM6hC3UEfBdW31MMPNVn6pYj96AkPtKvdIGwaXFxpkdgWf1m
JjiwzCWUh5NTEDchCFxp7DPruXGz2ByR/pkaejHu79sRNDFnDqF3RD8NeykQtYiCMhPQp/1lU9nw
Fkz9NN7p6jQ+DK30HMQPUaSofKFpHmVA9l23F46OhZWRGW/nPu1t1q6QhkioYA6NZrefiGe9YmAu
/rboi0qfX6J06ZcJnM5U5q5IN5Vq/YTe9NtGQ2u4liD44gRyLyuV/GrosTXndlHCjHly3J0Ld5rR
QPR5FoUUwofQzL3e79Z1KTJI1mbgqbf/To3gHW3boF7V28XNB1foklTM/jvMcm7K4Fweoy9veKKH
H222yRfYvq0qn4afD6lF20e2Qt34qgRptytfYDDaWVBgJnnGXm+FUt5COJX0ULAVPwHNWS2vJfou
1nB7Wf+pF6YNUx/uKWJgp72LkYtOUZrReqXsJBBHsqRRW+/Icr169ak+0mTG2zJQ19W9GR7th3FB
DhRB0Zq+naCPRNXqE1/uFkIqyQPpWnx2dvMI4sErYPUHlw1dc8BXkZgJjiw+Iqi4dwx0V4UPZH45
vdp+lJULOuBXR1ZuMB1z9bOUDHX5jkMPu7rDB7+hhLPGf1y41GIK+LKGRZYpjako3hAqsx+6WcY4
2SyvOjrceAUT2TMnEi6FfLEdaQStEag6B+HMS1UQGW7kgziOUCs/+/pUw0RYNHRdZehA65slmQ+i
Wbnrm4mxo5u2nGqu1uqFLhhgC7dnwn7yYZ4AnCJhLv4MpoDlB3DhPui7Wunp6/vUXVAlqhk1CNMR
C3mIX3soJnKSW7SNAnSmjE8DJnW+FIq3zWd0o0UGsl2wxSMYIjx8FjapoShV1wG97ni80AAwG5Tk
9aduEhPCphvr5b8PD7ZWWoCT5NDwcL4zrCgKXoroE9uYMW8oVwhyJWKMnM3Y2+uFGd02Mz1qRUQa
yECfWufKo1NJL9RK8YigUqJZrMF0R95Se7JKOcQBtsQmJ3+cZoI2WCY0oZmMIiEcE0uj1bbXJm7S
y+cL4hJ66ThHizfWBk5G2Fjg2NFoHNydV6Gn5dlejq64RPRGS9SmjS6fqAfB25Ro8SoVlnYByDT0
hxtFEzvGLhFkcpcOTOsG0RI05UIeHE6+vD8uNPYTXq9kvgs+a61uVjauepnqtYJuDrDPhVm74pMs
10CJWZ+PUOdpZN8usJYVtspWXDtch7rN2hsojrNr0vN5/DZsdpCtIa0weggEOui+II4fjdWC+D1Z
BUnhor+RztGV7GLExfNGGhfDsziEE2WA1wpNjpJgw/yL0Q7TlWPO7c1xhYQRp2cKYpxBIgPYegGa
MCRbt2vSdGQpY48kAJjI8t0+VQvxsLfffQFxlNn5TWvE930KpSFH/g9feuUln0WytvmxURDfgnYO
joLsq2qKM42HaX11SeYfBkFvJurvT1nh0M6ZEE2KBjBoxXf0+GJy4EjXKwQtrfDFSTtvzkFmnkxG
DHsoRMTPdALEGEiZ8Bi84IXB0WfgRYtC6aR09VHuL/FGaPCrfFTD4jrspajjoVg0ty1VbudZ+3Fa
7uyPni/enGHLSKL203X8sx2EKaRaBZAYg+pMZzjGjHLXU7xXFvzyPkRuWibEj7jDjAgIMQgzkSMN
WZi0dEGh/HvEDuGNzXAAYSwNGKQQvQyBInvbEOebMXJgJq7b6CWLcRhwGQXeLIfiOqzzkxuzD9Qs
26WDvm4NBnDfeUM1IsvT0jX1c5xF283FrtVSLKtdhkFdWi9j4fk+7DLQ5mOqG9I27ncWOjZgYW4/
CdPJb3x+5fMugeQiA9rgbTVz1Hob2ebqdncFET5U94ZmN6nJouZN2B/bvqv53zTbz5qqQn+nbIqm
7u4BXAlXD4W2sU4DvhFob7Nr0/d1l8LRagjeuwFd1cMTB0s7AWconPm+BSUjgtLcsujyGUaQgRK1
QoDDV9nOs+xPCBoKcJugwM3thkeqHKqiL35/IYTyxekUxwFuIe/gKUf8G3GHvv1k6Ri8EL1ze/bO
y1iRdrPYTs/W3TJD2yZE4EOI98i4PMfsxJR5MLPihnj7AowKt62yiYaZdgHISG7MsAjkVQUfI0rx
A1rVINhUXiWC//LCzuv44sXWEySmSgFYvsQPA/QCfFDeK9qBPZo3Zu/Y40dJeT3hfgSezkvvPMm1
zTB10hTxErze7xJhQhLKcj94E+n4IGLxKS/1FyXaOMIWdjI7lgnRk91xr7tHf0YOqcAXkWVXer0u
ly/nkx7J8/xf6WUz4UkKBo7UBQA/0t6/Vq/psIU0uxA5pq+bZuzc/jVhvi22z1iFJbN23WcHenSJ
cCdRlKe8tH1ja2tTLkgm9QqcMzNBOiZZCFzXnw5wodDwJLcK8EvlAukJK/oWX0nztxilJ44LLl2x
yerHNm1ILPDBHZfGHjjtZOKk+y6u+LB47D01ERah2hRSL90NuyzHfnZx4HXPgsKOUnPh5fenEpiW
Vl8bH3Jwe6SmqY/tK74ySVyTxG3/ZBE7zZZttu/0FbtPrufw3+ZF7P91PMu3djQaFOxBk3PSIhw0
vlWpFObJSgCqWqgGi4lfj1VQkGKlrP3M8qBdPlii1de4jTwpzriaA7S4/5jXDYezCSZRK05aMcIn
ybDGwvRKFeDm0tw6M327XmVFlXcQeJqR3Lcdg6PLpdwO/G3RYxIfL00GHQl8DWow+6xL5Vft3ihp
G0+zVcp9icWK+Cr6lhqDL0bRT1WnjzZxvaMNdo22HlwMu8SSy+ZHgs9Mh4blUJY3MImbuJL7q5kr
xjolMeik4R9M5ETpdt8M4j9TWymcFum4UFRF8g7kXyyrnSLCa1iQ+8NuMHMfAf+qprxrBEvOTsj+
JteDWyz6illjV3s0UjdH5qMGxmWSqbRgTvaUZUKzARhuLtyyD+2zj8yuSo4dfhnFph/h1fOBKKvA
D8dN0CKOQsY4mth0kIFTCgN02QNN8PhvDH/NNL3wJ7FUnDrmbebgEt+ahsasQNUQcRWCSni0bQvo
N3mhs+3RRX4txqFEeLLHdWCcsTlsPSEXPK9k9pf8U83OEpbyJGkuiRfxtf6/FYNMrHT8MNWnjuW1
t0l1QrO3Jbi7wD3N8iyo3V4k5W05eOPuAtiSDQ7O7dqbPKgT07pIp2Xl1garDsv1xFdN1m3cQMa6
+Gzar39KHTJ6Gx2vFBfCXB/68WRV7lziE7n0BZCPK1AJ5aWhzzUF27caTzKkgCUww5/D2y4d+fX5
V65As3sqG/1uEh+wKiuJr8P962C1O+/tgceS+587oe7+b5//yNmwhYgX24NiwqQ3LJWAmPMU02LL
IS3nOj5qceZIXYNs87OUjQhK0KvZC7TRVsWLr0hr0ZdwHhGJhqaJrJPjMcCBhLBfBeBhP3Ji4ffD
qDq51Fr9Ksf+DYQV8fOsZq1WD2EFtayQkLtBLTJ8OvewdCTC9f52JadCvzkm6YYuPkxf8/XetKLY
KXHIQ/o9iaNNVstVrl0j2WVs0NZc/1w5AwbFygl9ztRfSoHmV/x2CKsM6qNIjMCf8RyflqQt9+j5
BeEDcAuq859NHHs3ljzqka0Zd7HjjdNE6I9gHb8JR82sUqOGdqVW6H4Xm9MibeK08IyhKKYhzCN/
jKundD6sCnX7L6Iixq9rhh1S5oQAjiLTvPcapp+FJMsagyO5jnfTWakK794XLXZ1E13EtnB3gcRZ
IwYYmzd92cUh32y6uN3iy9Slt7wBA/tePPJvF6E507+coiBOTVnheVlNyOAh8GQM4Gk7mXg8oSHj
bJtAWshNm2z4pQAKEe4NT9JBWXSuOlhkwlLdKbGTwA21Ju/fE0WMa+9Ao9mPc+DHqO82UPX9KJRn
wv3kjH+iwnBnQ/vAoUM92JFH1w8wb6OF1/xPrMJVNRtOQXSUudgCDqc+gJxF54dGQjGER+LIoG4E
UHAY0aQjpFwozqbpLvPpO/WKr4LGz1ZUldkbjJrBzxePyfbW47janAd8wxiZz0oxByP0SQe6JhrX
EW/eVuI3n8kcD0l/dSPBRseoXg3B75SgJpnK4pENmu1WyrA/ntLGl02KxvXL5TlReaTKzkF5brOL
EGCZA8yADZdOZoUqhjqUR0rkwiXiLTPhyocnrkFLKYmlOd5+fhjAPmrdepx/2mwOex2PF7PJvURH
yeqNh28TvmwheQccNqp+AxBgGA4XCoBK1wJcres6SLxxaoFNb3W3PVon/OPMBWx1cy/d3B0em5CF
rrBurq1tBhg3S5tBjtqVo97rn/OHit8jL+wEZKhdy6rvw6TssQHByQ0eNJTjHIqVEaNbA4xPWEaC
pXeMfJrbDsNzDAkv+d0fgwLTgpWzty7SzVyf8hLFdzo7/+A6Bi2KstH/cYG6I/Bs+Kk2QmDDgtff
L0rdCLtxVu9sGil6Dk/2HoOuu/f3d9thE2/M8fELlVOwT9Buqv81GOIdR1eudfbb1//neebIolpl
xOmN+jYCT84g0UcBcXJsY3nCb7D1pLGeYbeytdVEU40dE5rpzQyiDJ5v5x35Z0ylkE+Q1+iIrkHY
rxTwh6ifz1XrQDQe9BVDl1KloGoi/I23J6iakqLCiQKGHed7+odIoPWRKv//4GoKfxosGLEoOPhS
cNbaRn1TohVC6tMglmehn+WQgobiAxvCB1t0gsYdNgUdPGlp096Kii21zfMU9ergkfKCXYZGj0o2
P2/4iiOfMoxORz9G0gsgSLhHl6bFYExAi2kmL051u9bhNA/+kg+BR9lppHbpjhZaw/bqBgrYcSuU
e66G042G9i7/VfWSQQyLaimNz1uMBv/GF3PUMuvG44Iv/7yTIVxUJcDYMVvRSJr/FZ0c50wxCTjl
yBjHpcjV9VVG+oVb7to+JhghUoMTByNQZfRrNoQp/0XGwXFrEv/LQTSY4A9gvUGo6kX1pTs1os+L
3HrO1bflk85x0ZiDE4GCWyGOYspc+L2ikxau91sPrHZbGsAjPshX+34GH1JMU5hhYaR9Jj017bQR
watNo++FItAs1R5coRtNCyD8rwyBIpEpV/0T0+Ouvefyn/RUcH7Y0+c92ngXjJEACUJ3cn7oZQLF
laVlqOh3MQvqC1TVQAdjOXEllqXJptict/h+TNdBTDpBWq/WHRc3VsN/qABHG/NtiAjTPSgC+3Vu
3zovaSurCo6eZ+Rr6qS9WBT1d1HlfgDDHLxSKWsNjgZ1knM5aTzidzil9dVSbrSYVQDhRbhdgBPo
QISSR61NgJTal4MDVj3yE+aXh+Z8oL1HQY9vHr5b1xoaLEda1IQGAFo/yDEQf1ZfDRT/0V7DtwH8
YRIuawd7vZb54cBvFzBYSJMUIyNmsWbzI/WEmlW8bz4oEjAgf5y1DxNb7ccp2dl5aukPmQUO3iwl
3PAcWTjVEMGsQ1JR/9ZT/DRYvL+cy/CfUYGN0KRcTtzsixqO2A0A57omtSIYTSC7hJxdYhlB+XC2
Hnmfc4Aa/iPTc+c9Ri7Ngj2/lpz1DGXbxYjYjhs+wQD/nsfFB8I6sfNNOpb84W7PRYQeWgjA8FW7
Ix76EH3FIJU6+cL7bqwEjq0S5L94cTsuYNTYmUyuMkeGOVWtQZQmyY6xra6J/jSjzJkQVb0PpPlH
SwhzLiiizsnbMVo1RyfsjzdyoB4fa78QVRpZA9FNhPglf0ce26Vyl5pM++jpvLQF0j+NjwpSQOEt
Rh4SE6KUK6nVtIRtqEsGHT7qWu1zp8scw230ZD8cPThDP/kPhHHDTXcF6BvgJoIGHIMsHLwQjBHe
Dy/f9K/Oka7imaxplO77ixV1VdxEtPA6RK3SOVGCyB0K8jJRSinGq+gGL4Jj6CjRJBBKYovUh7Rv
Gzbsad7OvrrmXtZuaOYOTRtkwlVYwZDrAbDwhr2azxL0I06pkmwO90QB/a2RVKyealGY84IT232z
E4t7X9klOAM6FpI5leFrBSt6RVAKgI27JLmMmIFLq8SmeYMoEOp+Raf8/M65wED+HzW4OYBc4WkF
q/90CjNjh8pApVsV2ZJvPTMa99mKg+yiuz/hL3WSRyjR6apAm61YmVWZhpmOG52JFGo+Ow0Dn8Iz
jA5PUreWAo7S4WFC6vOej2fOWIcQ1Q3OsvML1thHmJGyskAXZeUGbNzEJP3WHy0gXRdrslI6ph2X
M9sNZBjYh30qes84AJ4V5skYt/aCVvQYWXqzar57tVAd7NTojtp96KRGOIk8tSfLakwcwFDitsxI
zWUWGS+Ms8C4oTgOvX1uVmmfbrhDrWbi+A6JnCFk7XR/DSu7YTAHtOWKeReCWQia07OBwfi2O50V
p8JlADtBKFieyLJhfOioEjjuZi4YqO4KcGdc79As0OY4Vg7G7oT4HfT6EqSffqUHjITBXqi5wO6E
vgD86WSa+eYOe7/EjPpO9cOuyb6FDASdBPqo5WcY2eofv1cQ1z6bAAQ7VS9kQnf95WxaYBdyG+HB
1Y2RzIXRKKpPg5xLWN5WFVJNCEtF8y4YdH6e34yByEy9Kelq+etx4226q5w6w3bSi10pSoygtURv
OXvlRY3BBUINfiIZwbbIH713Azr/bS84Y9IFUmf+J7jzVUouzaqMw8QRlVOle4fsS+7Hu/gDGnJh
1/QYzUPH9j+2ZR3CLAOA6KtViehg6kd14f4xdJSg7UEmoN5OohE4054xXNyHNYCipwa9Odz5p2ju
xNtyhYNdEkxy5Ww8N1nZUwbdGjjt/DDrtmkBd1cMWXHJ4hxUEHH4PFLde4rk/Dev37RDZBBut0BW
K1tYDqf1L+Pecmw4ldf/ckx7Z5mBfa/F4hV+TQlgir/CEb3vh2VRlKqyhIM+T+z4Th4GjD7F0gsF
PIFi7X8a5nRqGXFKpCqddenWkgujisRdqabaUbq25dwdhVHiBFuYjL64FKYJkwqhcNnW6pGGlFTh
Kg2O8fFG5hqjRTmanGkhtUsWr6yp+oRyXLaeHMlbgsN+VMY0EQ/tjnWbYDzfVthJxdYu80vJV54u
SWCDKRU4cBwQcSw+mskB/J9QnTMJQ03Jp+DjOXbAsmYcVRX4lSaj6E1cgk0I4xB0F3qcAgryR9iV
+Trxpn64GLc+Lzgk4N06vJeQLUw/urW6GoDiilWJpYr8qDImBTgjw36yT5UtpzjC6s65dN96YXKb
Uu8sA5Feq4xkXKMfv5hmb5+JlkkJihdt4IO/lgH8YJ1o2Wit1xKp2XjKjZ+Kow8H8vSw/116jUbY
wXBioA9Rigizi+yx1/aZ14fpTMnAfN6t6KdBJWN12bUJaoeZ/AfKF5os+g5cb8LyE0ySTvWorPkr
wjjhYda7w9cIN+RpNoAyeMd8Or4olm9AqNAXHsegAC8ZAQnDxB5aBuFh198xiFcxbpoEi8C6EWei
It6d0XflDCNku2cs5uPLfWyIuH+yCgBaJkkCWSPgHjmdLHXZgSGzCat7tjNVQ/WPgmKc5M1Wc3Dh
9NxoHJ5/TakqFLeBOYyK3b8rOTbCAjIeE6Bvz10j0Bp6xpGNJuOviL60KW3N4STusQrYxwejsVoy
b5R9fM2sqS0oDOT6ohGJxnkEKASrTNinyzxFdaq5ubP4v4v1J8X7jgVZZi62WWJBewadI1GTX03a
fVXqPtNhdnUCXFiBMkYeCZPOFlRu84wlQ5b+7yKbVcn4hWH4TPfsJghPOBjmx5wVhP3cx4eSQtMs
BafqcWMbsJVtCgG34c5ghS9Q0cmtivfjsdAhaWc2osYy319v28OSr7BBXXaYo3uScTmFU074Xjc9
zYMajRLSvdznyxKGGBahVYjMb4q2+hDW/dMk5TsSs8YL02ezleUkVsoMOIq4GXyXD47YssfBN1Uw
1zjLXUJAGqQdE5q3DimuW/EVhnGHGgJFSKAqWsWMu/D64gfW5vpLlJUbXKSVlfGsCdpikhDvsaCF
DIaR6HC14TYL1WgQViz3zuUfBLntiedRv+kkixxXASPHuRKfwirBObSCEbgn2xFmycuK2xCOyWWb
0UQo5wvqIU7ZtQKTth0sW5j/yNXE1xvuGMAt2AMmm24O73dpUXqMQnHVZROWAllphy3mTh8TtvjQ
JSFt240jW22skHAVV4XbCfR+1Wim88vjWSAM3K4DujsRF4AgT117tvkuEAb9GjOvKzEx8Z9MxNoE
C+OmbakxOg0mq8sh487GIJOG7OW31eZo/4dfKOJfG1QxAgro6HpoaOUTmcJz2eg5Hn2ZmJ+c2Di2
gALfxK/aXLa/JaW/Tw5ygMKNgxVmzFx6CNP1FrbLjMR1QbRuzAC8z+ieBAmK7JHWfoJo/dBSIHM9
OEAOZ5w1WXveTRcWseaJhw5W2EBeoqdUBmbYajn4cb1TnoumQB+eNMA/GfS7+ZuJifnlp+RCJrFd
VZwt/HF7+NAVoRfUF8hxf4TTTJksH+YBs6NFYIZDocNTmNHeMUplHADkvDzM+anBzNBVR6ffX0L9
qWw4hDQGUZFyGwWQIVu8xHjw3tMPx8R+38BPPzVLR8XL/EQb08OrWWdjPw+q7gK9p5xoz8zkH8Uq
sXgoq5t0tc4/HbeCzV5hmrQqQDNb2gmUjTLyIY5R5p6HK7rECHXi684EoJ/GC7dfGprGWwrqah+g
3qM8CjyQyN2oWgRddYhWXU8obNzG0U9/4bhXak+BEzi8SR0qsCsmG+PQ5hc7N0LvMHWkKSw9YYtF
ZCUMICUNEMGeIoS5M17V5fyQJs8jFCP1XLHr3jQWHg5a9jI4Me5p7oC0VDytmPOWruKPeYeZAYTz
Kqle6AHOmuuHzimy9N5YmPZcIe/y+MJtqsky4f7rk17IIYdfKPLfivQUIyChkKvi2CZA874nIVOX
ue2BEwhjYOiKv+Xqj0ZXNdwdRAh17OEGlfKnnQy2c7YSMSgSugsiRe6rHi9fZ44gI3xe20OCvTiv
yLLLyLxMI8bU9rokOFxmCNowPLRiYeSYcqkW5DvKudqklTjW8mQXZcHQsO9Ce5yuPcOz5yk0zyxp
630x8AzS2tUfHfuiZ1RaXCe3gvkQ0r9hTLv4olzAE/stq8nmLdwwQAHGYHOy29SRRwchV1fWBA8b
wWaPf9A0d9l05U1ekG3iW3gMMyj6rbDDyeMFcf76LhAMdZt4JegiRFTmUMfzXOB7LKr3E1KtxyQr
Fq3mQiyrdJck9+3AqI4IpziNQtn70Jl8t5S52jT8vyCu2yBHlw4JYMdQqWZZwoNW4MYiQnIQiur3
0ZrT8yMbRkiZCg0l5ypAbW3q2JmoJLDJwp/hSMx9DPYQu949ZyXLP3eyjizYVD+Zy41t4ueFQo9v
h/Y2JPbOcZ3k9QJLyilQ5EUZBCbFmaknZnH9t6+qJSLH9lhZrvTuczh5/1BFA2zd2EJAOzlBZlVw
G856lLk630RhZ+XGRO0d428yGyh1UGJJkruGd9rUHwsQqfiFgY78IKMWner/3RX+fql21RZXjWWW
xcEWGMlb7IFoN/5YoivjmeYd0jumvBgovFtEAe2Typ4R/gx/p/HZ39bPOdmrGouOKfJhLGIBRFJR
RKV+9j5P/fGGmb8YzoJa2xa45WLFhiyqzWuzIijN7SS5ofnA8lYRVx3HIe+el5H4XbLJqyZNSfHD
0XDQWWuyLYXlnu/juRfuWFo2R7yQXVY62A4SIikcEQDSf+Id8cEXl/IctdXLY6M1SOQH1yZAb1qQ
v01muPTJFbDCggkZsSTZG890oD4I2RJt5ugt8NXh2waMhn263qg5xiTEhZKYcfp7qrqqk0UN55SH
IBq4NSOUo4PUQZYkdP5NjpekOa6rdrIQ23KgKil3uAqiHKD2xz3G+2xf8eO1rXOBwIdFS+DZTVib
wESriOIpfiF31VhaV+/cFxK57/CEueloRECrbAOgha5ePzztVES2Gdcl2DwQHznzVAFcyG3FF6ug
6twRXTsB7zCWyNMkS3vc1HUKscG1XP+tLvqdhdJnrn/xzGxnR/RCd4HwdW+GazEsT9Q0CGLzBHGA
rEAn6mE0pAEUf15GEzQVlh6g58hjkVxh6gV+88liBx/kfVi3Lrgb9cdkTmSx4UKkURO4KskSaxVa
Ss+VeM/OFkrRnxa2Qr7A2Oh9x8bxbhsniza+PFMR62cSh/1Z+axpYL/gpdhgfgFIf/wVlSMHyU5N
J5ERF41M6VHqylKDi7dbguElqpI8B8egtewT+XK6Y9cG5cyZkbRRlIqAT99sBpDx9nZe/DLLoVNs
7x4r+r6LqOLLrO6gTv5xNFmW8g/8Z1Ruwq2uKvUGmcBWgxyequhMBL8chFfImnS1Ga8ud0JeUqFW
yYRuzfLWdVM1IGhbaeRQ25hcyd/MrNuBaAabSydrdxy8k1QFCDp/mtgr8EBnpUw9b1TgTEbm0i4C
4TN/1m9fyuqJxwZHMXNPAcIsBFqRZ5a5ow6dQQUThYaeC5/hK5305sTAvRKgzQXCzPPzjNhkC/R+
22PdzVU3s6ehXg4HTZWO+PVJk28leRtpHIPRYefw9UPl5T5I8OLxEOkIm3Um9c5OW+LeSTbqlQsG
Y8N0nCSExZftuLGQPc2kt3D3CIVUe3QEQm7rSMBryP9nJ6WhzU5x9pYvs+DI8nzsblrwS2KbxzEc
eEHsOgTYFRimid5MtOoZIetxWqClMLfvF4K0/bl9q+UmY5+7VuiY4sO/J/V+H+C3rU9EvGva0a9Z
D8TDYO5UYnZ4MlVl8h4zZcnmOlpvSVjhpLualxqi+zE0c509uZY6696sC0PHd/cC+rcN/Wk/RLO4
IG8eXqdfyA+ysdDNH31rvUQDENcxbVWB+ulYciLA20/xrQNIM8ItpZyAL4kV6YKGFWq9us0eVYWg
LiIDkBI6w5ZwLUDJByzm2lfb0WomTOXWxkG/4s4XiKuawBaZDOxm4XhWC1JxGrgaoYejKrfp7X3v
zPsWGkb6/P0h8CEzwkZ41+JBs3fhcyv+BTOdJq9VHy9m8/sGQvp93cYTkUKVQhlyw9GT0kvfUtZW
anY+mQEew2gd+5zOTzRiUeJSVYmUZy5P9SMW5vt4EXCPn83ZA4i85YUN+h2QWzzjS4/ptSTMga+0
/7FMz4YdQOYHGcfmA5DJAMZemsYH+rWfp1UV/Uk8mwv0IL0rrJmew9HpnXFsbx8l/qldGJpmVIfp
XRwycA50UXgOb1zmAMSFKOeGspYgNp7qHJasPcZN4m7JVRf3ngiBJrb9eNqX/YyYMOnafRfookan
V5ywMR2rGEiFqFEWAGs/vOQi5zccb6h16GfVsCGFCvx/gDJ59nZt98jxbWsCMF6ApgCbDxcHZ2CW
JNARVyrgMPOn3i81x96HPgGoohrgw+81bU6pxsu3V5WrZD3KVZu/WdkmN7FLipC0fu30GSKjNaH0
5+ATEkl8D0v41uocIUh1x0O99mz5lM0SNBtZBakVChmJlI32UzeJAKk/IqEQlaJHl74JmKIVWKWP
MshDlUwLvEW2uxW6nGU/4eV1Ep4JZ24p3NQnKH587epHlsBSrLQE6K19br6fTLFhDCT4SGVTOWMz
n0BMcCbHojKPITrHA+o6U/F5smir+6W1UFpoeFoSQF+qvuQ5Ymc55h2Et3AUFf3ZspAwID4PiXaB
jCYUL3PIKq4XYSRxOwlnPAHdArkPrvMjFofEaxJIB/1IeEYwW4HuVdhk1RndGkGGE2GsLL/hhFc6
4BPE9DneGG/Ge1xc+dkGrYGRVDlDD1SXPRzv9kP8b5qXzI8HspPrYYBPBeTHdao5Cw5eWZFaD9sy
YQHsLb0UzcVYYI2jvi/73GOFqgaUDPeX/+uGP/MyxooUAvBaRN5pAI2cqYQnUQfOGWTjwLoCxGDK
DyCQlBJvOfoQEwBrrnZLLOT/bww8WS/RQannROZ9dfwsnQdp73VIe6JqT/tjbmazVA1BtaLWiFwc
3YHBF1baQgftOjAC03SW6Wi+ZpuOXvO788sdYVkPDb5DLz2bDRpWFoCKNyu37EqqQAsAA373Jy/+
GFjXNTqf/SjPtXshsyNPzD2pKbcyC2M+nqP9DiSgLxoMKHrmVIlOiczgfCbHw8KbgG0jgYXtOzEL
8NhhtWHM1tUzAU7YLIreoCKYsS2Tc03g4vY4B/xPgBOLiJy9FtE014SRq/AidTIy1mv3M9IG+CTo
dLAmaLpXNhK+hV79YINmWoSDe8kvpPLtwmQAme8866yy/iAR04GvV54FYRVEcwEucPAPE2ICftFU
AyBeNuaMr5uZ7YKJ/0NnG5G8g491rBJUedKBy7NyYVj4sjAezbf45TNoTVScrBVI2FNdfRt/7fHj
+49T7u/kRhgKOdDfuMIsLjXBJFACjR4RnT8C1iH5rThsrFCy4a2icXBMyYl5j9UZhVIsmn5Regwf
DvHdBKvS0//Gy+6j3d3haxyP8XgvQRReXRUxHOeO2esZzUNAXHCT4IW6ote/HbcDLrNiYAhOyd02
Hxfl/40al2ldzOzsqRvt/pOxlbpJ5k0B51+92aJGUgYNb/Ib1nVIIXlobXTxP6v41roH8u49y1r4
paiys+hHOOKENbUKbdQAzaV/19J6NTkt+5hfqSYIGdp8Lt5zrKYg85vBXeu0Lry9YlexkVUl0Ntr
KpfA4VCF1JzirKYpQ5blPnJcej2xo/tXwI2dnxfNBPx6IaDdYgchsf6uv/GJNXJl9SMCHkNb5Nm7
B4wkN3ZiW30mUhnWHA9lWBTJfP2uPI0xJtejQ3+y6DHcpuL5KjvjmKP0WplSEJEYMxtAFdcZA73l
CUqgnrfWCMNkgqPUPK8qgTkDxSusAEQUQg4HfNWimRRsMuBkISgIC6a+DRDZQNMeORs70ZH5mNAC
dcDVkFf/hl9XUNLGfMTaqzfxqUyvfS5HJarmdhLIBgKJeWafCRSUEjdY1y+ekyfq3uMfipGDeFL5
FFBZvGhyU9xKxjyj8FizZZkUbLPXEDHAa98tltn8JJG5xYBShbwcBJ4WIUU47xbvm3kwVKWWQXOJ
FuG4Mbx5mQG3xbSxk7ZZVa0PiCKA8ozI8zTGOl2TUYydTAap2x8CPR+lWu4jl2fUfexKWGzZOC9C
1hDryMtICGcbbiUGMZCINsTWEEcnyoe3Mc7oWvHiSiGvqSGa7wdTFiOPAt9aT86QZ7KhO7PMAxcA
iXXxJ5mxNWx/6IUGy+JCznZ0NjrFIUbatewkPSvjfEqd5CvWpzeoPQLzZxui1asFBHeOPpnRingg
PD035lTCKUXMGCh6VSg3G0va987857ELRITmWyGMqoRA5OIJxRENl6iSxrx5AamSVnO4y47JlqdD
jM1uzsP9Xw3HqpvshAnmKS1tXSGmo/Vl2GfO3Cc8o/5SV+qIy8HODbM0Vmm+6LS2FsbGkTd0UNDG
nKJu7fNyvHrXgZh+CMZgX+3Uft/K8eSnCEsR0VOIifNJMmNE3VqzhN3NKcov1QYwMC9ecASHkybX
0IYSVFrTdo3FUiqtEFUs5nxBlJ4+8783yZzKDO1V4bqs2w52P6rOkXFpAUJfekiIs6fW31DMBOrC
UctdestckjL/lTL9qRa9bWCh86TnK6vMEBL4FFqwl6BaSjC0DoxXsdLz+CSSRvqmj5KfhL1p1WqI
YshW8vi3B6VLbWutmZAPLCP4nURO3iVvb0buRO8ipwswYEtegrvuVUfOh+S49KEFQE5pcFU5vali
JqX3Q0OUEPurV2BQHyWPXq+UBvH4PC7ImdJzMNr6LLqQ9Bvj299QVhcU60y2yPUPSmP2B6iQbshl
oe/b+p8G+u1L08qMfm7AbX/iMSGyzhRpfDfWvZ59RMgqOUqn1sogCQ+PzgfuX2FJWsmbONgqtTed
LV90dQBvwbDshPcFw9Ns7G5C+ix4BGAnw9LN8XlZZPnA6IxSObXuDr8YBeP5I82Wgq4ypV2nrcWd
f3HWS4x/CCKh5nHh7HAdad21mPIIgO9HZZrkUwnwLmru8IkXMzS/OP2iuxQ/FAAqL2Ifs+Cp6eYX
OyP+aGxa4+/mj4aENIFWIc1xiz7DWM86KlVzu9/dT/m2A/kyUiR2Im2YCy9btoya5w6fakwzQFdL
UU6XubYaoB7W7Sd9+H+HbCai+X0c4IuAnGN6UBTDFOsPazc9HIfyqwo8Sy6Nk79gRNyhI2M6Sx3G
CQPAYMrPGQYRW9jizixpXkSwz6T2rUQYDzqohPnvRF3GWhpypRqF1eUT0n0Aqv1Aq/+JVLTYkLc0
o7WY8vmbyVLVCO5I0q8vpMFwzvmAgaCgueRytncdlQIKM36lakkFxBVrfepmsVJxx7RkJ7+X8U7D
GZlOSZnoPXdZ12P0p7g/of36BDJyyMu8TQqhyQimpu2MqxtcuweCP//J1W159VNUf9nY2kIf5WnD
FlOKmU8fgEtSOYWvisRYN1eSi9G1wZzmBm/V9q5jxToijWQgCZ4kDPFUze9HaJ+eq5sybHe2aZBF
JQiz5CNKp9t4XZbP4Uwhv6FEuKUZouXhuVBcFvej19MRdildKXguoBQbM7RvVs/CHU4Jd3jEYddQ
dzCIOQzZjc17GxQcYmt1BTa+hNPsdnQQbE6LbPC8BgjcPVeLpFqBkf+qV6EcQsoWg2a3Xwtyfbki
+PPX3DFyvQ0+MmmBvMuH2Hhcq3lVPIy6KmyLbXGJYFiF13DzLUXzysfSV2f0UfKoMMohTDEvRFJW
j9s7MVio0WPCb9i4drg8VcGmbB5BcsgqFCHayIag/u58dd6AYHREiUO6UYblam906/gK02Gy1hL9
eKa212YLT7c6g5WXQrOfDly9GgIk4jMaEY80zH+owR1CSH0dUb6IqJrOqZuLLFFMitUSdP4j0sjA
jvGyLJ7t4XIFVgBQf5BKLRG3beILvl9IQ/qx7GtyvwwOxO4Csj/prBVWcZeZfjr//7WbxjnulhnT
PRHbZ0r+4VOl7Cp7YV5jbYlGgkZohsj8PDsGQ22/jxlQvdEnPcWXSBPRqKrX3J0SPn62EhQeM1KZ
m6PqvnDMa/YhY7+iSp5Io3Mj1g8AtVG40wigf9MzH7Msy08oDeNmpKkITRR91l+q/MUf5gTPuPv8
zW1X39ToAr9AbN3yZisJtGWeKHopAS6cAU4bCDYSgU/g/NK+SSSxMAlmJ9eL0L+YqrSnEhH48eDm
GMYmM3JM6wvmy9W7XAWliiZ+eRCk8FenOkD/TkM0pkiDpqKPDT6N3BHe1Mj8xFnHjBL+Tynvnffi
AHM0dmHkqCVg7stf1eGzxtULWczeASEfWQjRa0FvD5XR+AIob8+4h0XWEpsTtzWQIQ5fY5FKKcFa
ptgzsBvGfvc5gRl5teoFHOLyUWJrPn3wyzIKmxufk9wmIRx6zxO4uWfni8pOGbEEJ1sVV8SbLUgg
QwfsQ6Kb/ZVt0O8Bt1CQ77rKcYH0O4nfSc9FzOetGdgFNwnehKni6ENZ4N63gFhb0jPAakcZ+L4s
UIntg7AiWG9qpPdpmAsAnZkk49SH58jztCsBU0y9+2xlVZ2RDjl4U022V8OR4YQKpToYdBQjhGUJ
5XvlGeV90KUXVqp6kwDA3pFThaFkoFExO4mFNoDd9YPJ8NueP+zcjVVUV+1q/ebZCx+8FyMyoSUV
A7MAhB/hdVnfAvVY9/LEgKKAUIVn9wxG0jZUQUK03ViJyEp/BAZYXbYfIABr3l1T+kA6vLVFTZhK
kXQoDlPUVBMSo35awNWfwJutimS+UHMWcE+WjZTY8BBcRSqlBscZcs5NSeYvRuUARlcbQ0Y98xBs
zkiCdsvKZsZB1vv1iIoh+wibcvjqOhItHQzr4vJ5NgWON2/qa3Q/MVbrLx8r+T2O1PXw+VVHn+fE
2966FSDxHbq/44Mm+cfQRZJ/ObaBAJJ+WpmbAXyjrUSu9rnYGsYSAboxTWbF2mY5uCtMVNkdJ7mj
+94YTe/EWsLCjPVLb5iJWPHNK88FJqXwj8ttz9DI5h2I+FJq2CgW13C/HgSdlcLMP6BOji8poXfw
JWX1LhlxqWL8Yv7s2neTvhPMkHN3a13HYL/QR/iR8n6dZhmjp+tqCZcjE6r2EQhNbE3Br1t7KGQa
FWpM7eNehADIKGGowKPSpteBAhvkykyj4OudxPm21moeJOfK1lTB7a+Q6AntSVANbskg3sNztcCi
Z/KeQKpa78FMvrJBusRLFoh1i3RuFObnLUSeLoeYawKYIWy/ci3QYwPN2wiVHx4LZGd523G/IU51
I6to1MjQVD7ceNPMIoo443+OqUQoiNGkxa63+uuSvGAbNGutHvjjOtQ9F+xO3aWqiSixcgc7VLGY
xrpghYMhy22zAXPF5cP+RhkLUEfgwQQD5TaKq4H9DSVsowbUo6+0emIS86ZlkJAunzgs/vcchqIJ
v6qpphwbcX/U2LBlBEbKinoVSCqC4imEDfQY1Q2bgFB4Lk3p8Ce8ga5uBZGhRCp6aFDfM+r9syDA
gRKwwtQ1wWYYZA9VwOXpOM9VLIi3+onlSzqchfrMSzsRcPKr8fQ2JZxLfgtmwfAJ/itjYWtTN//0
yQ+6GSsScJsTnqyNXGW8GQ2SdGhXcnBBi/WPx1SGMt/ZA5g9Hp2toHhgPJl8blkPLn9Z7LD0AvJg
lrl1iyq/mC5GnsuxKm0pG0wuHh1F9r1UccoU/C8yTh2h91sNNGKMYCwT2Vq6Gh4Ny9nwIIKl1RGi
aNIuFHocMgDzXmPlpuBfrQDh72efVDzM1y/hhXQ5XzdCs2zzvxbPda2QnkvnsdND8riNRge4GbGg
EOcHSAXndvAxGJ2KBCktVsQdbcKt+F/fSVoi8HfAS34gMHi/GXi9rg8u2mj+9HzpDEzE0DKg4HRf
PHf8Pl6H8Ct133PxAaTb9xJwzqwdqMWdSfHNz04VKnELxt6eawj6/pzmoT1DrEW/pI3Y5HojUo1T
nCe3wHXo0E4JUj4/8HQJYWlC5LERDxSyO/jSVOFOM38/zPeCR+inSBOt6O5Eed9CI/WwXdHCnVzV
Ky9pzB4j5l8IWip8iBjG5YK71Xg/4eauRncYcWLLJXGxXSViw9FOT26IwFFYlzVSNS+cIFJtLGqr
4n80fEKHQncCR/pI71iy/0gO1G8S6MLFBkfWEdT4i604lG19mu5hVkO0ic0jJprRyKWfLvpHvxMh
w+Uf21v5SG2QPRd7b2xDJe0Rla6klsNyLM7tuIZd0E2vynU+0iYiOQX24OQup8vMparqoo0DwK3m
O+zAhuSNuyInF+6EWSz1ZT9MXlXF8n1rpWCw1Jtx8pty7rqjqUbYXoQABTUZc1avfBlGdCnxiYIC
4f0rMYaVUr65IKHwJ8A+iksDSVcA/KWQLQwJgT9C8YGYeSd/cVu9CGEnbmOYySFvMVZdfKHfC0Vs
pgCVjpgviM/fp85PE+mVD40a200+mBt04rr987n5xcd/2jvQD8CH/aQrkLSVj8Tzjp0RiN+cnqlp
FkSmleG93FxwOUuWG5Tx7O1hkAsamXyuDAvf2ADRVupYIj/GxhgQUi8pwx+/PCy1yai2avHv8Z/R
Y4VsW1ZzpVXhTiHCDUD7BhKHkZzLrJMp82ziuw5kr6Gs72E/3XQU6XT+3t00ss5F353EJULGIME3
jcVGNVq+4/3GOEf48j2AUVEEy/GaudPgtYedG/wKdqaMhJEic35y/QsnnRS8c1ZIxI8wBLfVrgeD
iy2QThZvgTnG5T1I9uZA7Zb2Ac8a5dRlkKrXr/aR/SPiUwVULRojBYqN/Luav658prV340AlcnOm
HNvuJfdUnO1UElhoIU9sQw+JcZ1+jPAKl+l+zDVAIwhjnK3qG8JYhNpqMp9by8DHB2XeLEWbcpNI
cBt5V01birZjJ5/B+/+AfNYzSXFXc37chmiZuxpPJ1VK+LLgau50rC5AqvUvxVMOiw1v/lmXq3c5
ozJZP3hNQe0ECPh58ddQt80SoW4x9xKH15Ht7fYU1LOCmrhPDxJUGCzuEyOkyDXJlmUpabMD51A+
6PFwKpedodpoTS5eBzuL0BvKD3MF/EzdLKmTu6PX0M53Ir1aptQhXU5CETB++nMDFsY164+PyVk8
bcRhFWIo86xIfI3qQqVsapCDqJKnB8aNQGJoXI3hmHylDC+Fzatj8HoH6juf19Ruac5j7XuTjJcz
f+O/rSCwNw4Dg9XBT7dbI39fh7XNABvqkQXvOCPjU2s3G/fjDQpgd6BNKogY/yNNVcWNpzhOlmCx
nM1yXd0AMz+uwIfQHoSUuyyeKnBF49j0clcmndDXgw4vTo1xoQgOEOarRKpn2AuuZ51Xq2A++jy8
WYXkiE9+2yijLpEYSFJ+/UaJRF9K29ZgVcoPHWoVzp7Z9eE4HTIqBSC4H7JLVDNDBK66xUxingmd
ag7ao5ErS1QRwSOOtjs2KF9ibUf7PKAd2tMZOeRd7Yha76uQrA0NsmBCZ236JutQ6kMcLOy/pguP
c+cPsXdP0n9qk8tFFd7wt40tr5Shu51Z88ubLeF5OyLxeay0Ov/94LGLfyYiX8MyNYzslVjzC9qD
0ED3x6/LaUTl6HHf9ld4UjBWbesMIXviaRKpBsp2dsU8ckDAUILm1I3V+XUq/mhYwsLWRvVuXOO5
/8TiRv6ejQ5ldsCJAk406e46yVJNJJUR2X2PDQxpvxrhJq6Fjh/wQCDqogkJ2u5A3ZYDfOdHsdCx
83aVGM9SH1VwiSF3MdzNSb+dNeNOcAp3Yod6GdKalF61CjvezHY8DG4ba4n38g5e5/7S1LVDY6jR
oXW7rpoOZgtmWpJlNtUnKpe6g1pjx2lzlVlrIdlgN5w8E0q0MymH7iPvhibFD8GlPL2AYFAtM75R
qiKXcD7QghANT0xaTJPLacVI/08GyUCwqELHejbX8t86opKcs9ljvBqVgBIEZvvNjPkzUs3a6m1D
WkT3FryPemen90NEGRfsTzOuskW3e6ApyA2qeCLz2Ezf5vUEhlgz58NujiujMdpIsux2UlACrSmD
TZrZAUuE5S2sA/OqF5FijCL7GMdcvZ1eU8Sc0OVnRPQKFktK0MNVLhIKrrO2e+APCYdHc7CwoqN5
ciHPbaqGjQPrBIS7ccqJFda2euT/6OkfCDSbVcThoMO71EM2ylFCTmz6MeimBOnK4qa83po3q9Kn
9GEw+x3UIBPglUEsublg5dJw5HZwDmNGsydVz07oYhBmgQHyAduWhwjzEz5cTLYtQDS6xIZY/q0e
//+ygppAmRKd6RvDJZQ/sa2MFobCLJYHjSAmsacAs36eZN9oW6jgTlINk7ieTSC6Zm98HyqS6mEc
yLaJMf+k4b23f6CE87PEJTiobRVBoM2ZtwUavGD1Uv6Vwdj29ZpzW6yKUUw7HmfhGGPXnWgzhCuY
+JivV5BnhdnFtIkIj/d2Sbav9jHwdqktnIDr4w+ABlsJSJWSItNfn93uIr1JplVk8KT/wzEcZxkj
M1grILlWs3KLE1A9gBnCaKLmrtIzMnuT67biDDOLZZU9cnsOia246SVe4WWFdDGFV2MAHC2v63ev
chOZDoCh37OuIxb5pbcE4Re7E+FAsihmdmTzjk2e0DFvdd0VlM2eOcejHqgVpxezy3Uk2MFwOPij
ZuCdDo2aRUELYLXj2MNEW1tDacpMzibsqHxS5m2WMj+hfQRXEztbsCROl0cD5GlEhKB1iQ34JJvE
Vv8C9oyGbs/BWk/sphMvpP/j3eyzgCgSwL2QzEscNJh3CN+JbTtnwfWv3JbF38XmIdv51jk52nyK
g/OWBCzc12ASjD2ZBb3SYNPU2CNoTfk082VbwnBP1mTbbP2WUAbUtXlbRlD4McpWW5oYvUWwcQDt
nCFiIZpFCETASoQNsRwR3pOigLUtjOE3iwXuFQ7uCRhV/mKlMuvcLJda/s1h2fRCp0U1PqK38k4q
kRADDwO1zsNXr/2bEF7bhdyktjLgxE+PEOOdb1oGDtSWitUFnJR0/qzXmfpa3O4XZeat3eU5oeJt
K/RTiK4KiSRd57KTqRF4nqsV1vbSx94tQsOsP46ChokQaeoFKDVRMujEmTGdOUthvHScxLstMBVE
8fV9mgOaOqkw1quhTsuAkhrfxau6YnsL+z2iPVJCgMtJGC8ixbhlW5qMPFUnZ1QqBu0V/5VleyEY
NIxw03ANjSOejVl5GHJydwxdMGZliKfLQyoR4jV/cqvShybV3WwTbwedbLq+osMYK4deQmSmTICg
6xl5y45ggj8ciSKR2BAnDXSR1KLQVyz/5A9fYUJdLEQSXSmNAFMqV8LZg3/bYSvOGZO9/r8QPyQL
ivoYkSHV7VH4OT42PSacg7qUoRlu+pMEzFTfjqRxMZR28dIAqbbVAL+h/PgbZEvs3dxld9OZzNcp
oXLtEKESOXqSt8Lu3K4L9JoxCDEfp8uRZkpZrbPVH4Y8VUaw9LxJsT6Cabcm8ULvCliqH+1yHO6H
Rl9jL8WF62cNQxoRYuezlmiudV90UMyq/us1rcGAneCFXqOF5DPvPf6ldgSjHzCfxYbxrLV/9rIt
/3bUt5xhTEeVIi1TC4s7oxFb/PMOpLWqy702FGOlEbbcwCwarmC9cSR6W8wULFGIZ0XyJw7P1qFu
rte+5ecj41RBYDN27OxmUWVJ4ccjJDTHxd52uecwJUGpsXfxe6gVx6hNSJwTEChy/MWZ2AS/35WI
nzU1PKSnaC31G36Iw8gglU90/KvESwy3ML2vzGxNy5Vh7SfcKCWg8zf7iM6YhoN7PpH/BWY0cFkI
bTWnoKXxYNlpDt/i9+kFoNh8UiWlaEOroQcokkuob3i9al0uVchawZGtFJVctVfhlV53JjVJSg1S
sVkj5JpyygwBqtS9/WMgOz07KSKAcuAZvs8KK+mpTdo4RD+VNH7y8QghVefR74nZ+MzLezCeM9gJ
+VrffljCsDq6M6ga+55rywzq0de/8FW4KbO30b7Ld1U36PsN9VFWYyheYIT8A+RQwGz5E753r1g8
2/eFrPxbmNvsEs45138Fvt53pa4QCIxO0j004plei2xCjz+/eUVovk04+xT5hy3qE0bl+xN1qQGP
12FZAGjhQQ9tAwmjTVAP1/F1A41Q9fBM+JrzOiY87i5sdWwO6Ilrn/xvDRyAMd7PXQTq+YgLlM7x
Gi8bN6MW2T2vkr6aXa0V+6e+IBJ1cJc0eU/Vmo5E63LvNZts9G/x/6uPmuVEb7ijh+v4TCXVfzmJ
4MWdL9KcoS+3rRBN+AdWPBRbnWFRe0hCTZCzyJt2vnQvUnCwE0J3OJlCnBbV3lASrG+wgBin1ofB
fLj0+8b8zOT7fHqL9QovZwcI7sYZBIO/kKzr9PhkALlEEUpu4E+B0Sa2/8CMlPXfPYYJuUUETsFF
Ps+BDoPVWh6VZH+dtHuf6bsT+IFzCPzHG6Ri+JBUnV2g+uADAtcEqRYn3sqIMLq9RCxVxIVjEcdF
0Y/Oz5/H4n7/eeJX53spXG5MedpxJZpcnW6fJUQGIaIsitpoaaEPJODoOlY8xupgYwRz7tG+Hkas
pFxiDfHYQdNt5xSIQqPfpyVQ57bdoA6UW9Bo0VFkzxM28st3KcVPpNLENzNZmKvK+OYXRSGdcQKq
H3owHc4iHxd/DVI486ANKzOS5iPIWGcvyzKLg62t5bV29ZRc4HiCc27xAV/a33EBQMhF/m/6r4Cc
TTE4fsUOoxyyC14didlzm3F1iygQUklHZsQJEa7vFi9390wnAetAcXqdIM5BAgzEwjk8SbhNg51I
BPDOVzoSYXAIrgmEVm6gjnvc9VPDYxEIv82R5sRwuunY+OfCg5XzrTF4EE6yZtyWhv9bnaiJXIDb
1GzofcHH7INJBi7d1VA39fXYvM5UnM29lBrFYClcGNrdZcn9sXVSK6I47e4a92dUjWj29O8B11VC
P/p0GQtNyrk98vIOkVy2u/GMuTOy1JohlxUEZTM9rR9zl3bzO23ayQBPLHxpUaLwMaN3JUbRH1Df
MdOfDCf3ueBkYyl9SppPIzJnOWVc/nOneqqECp2wPHtRIhWfyA4/lWM+aFU4O/1Vf1npZySbFLtW
JhuFWrURsT9b6v6K7OEZe1c+Ev7Ga4z/B6EHbYWLVWbvgyL/VJzr8sVOYyxjVTIjHALLk3aXv8N1
hM2vldJxH310aFCPJz2Md5MDR/Mgqy8g0ChnTMFrrpau4GMOwgTM0LdPKZbfil4lU42a9fl/wuoh
hGflwWkWQk88Lt0vXh74I6s9YQiJ+nX89bnwjzf+mt7mjxnGQNfMXntsPEfX2Hn4xMQnjjeYP9vT
PoAexj4cKrICw3dhN4WHHmxawv+Mf+96/l6QCnxn3dWxshVkzHr9Hcbx3bon3M2pIp0IWO3GvIsX
dRiywEd/Wd07OvsTWfhYwTgSGqg/qq1Q08iTPIQrcamWH7UjuojIlwAvM6GCRFKaQ9ieKhIdLWcY
B+CMpb2JXCNnT6i96rdkl2L8hZkFXHYv5IGbU3a1/fgtpeL5V+y3/lXrt1XhE48ZnlvzWMU6FM12
yDK4lu6NIc3GNnFQIWD5UtQVTR6dAK11PMfb2DUroM9lx+I+yyY2rY+TyYhfaM9QZ0KiSec6r/VY
I3RFqqTD2o5oftLnoPB1pAMLfT/pye3wf4PxCcuFED3WGiKXcRWgpR0BAy/gpE7U81MlMVWVxt0P
sj+Cy2GWJQ59TioxR4/r69egUjvqxzv3jXF+n8WOnCcPyf/5iBKEX9gUs3QTAA2utRojnMAS4hWx
WzfW7t7UZ0HpoGBn6uf9PxIBNYgPGOdg9bUDTgXXe0DEB/TRpIeHlEi02UMOxWoAFSem7rAPFyhS
y+wZai2tN3NfozI3uWz5YfyqaRnN7AHezlkUVrx7qfPrqy01uzAQ9bdb6D2kr/lAq420r6f+YD2N
tbAlV0gyaTE/LgpbI1Y9T83r2gZ3wM+jPVyH8o/VTZRzCVMR2uY41gVGtlMbnkBZyFnSggwuohZd
wG/lnYOYa/PL1LUpv20IQmkJcWSU9e9YZmWuBjyU9FddNg3drpABHZ2Onx7XED912M/s3A2Z3ilt
PzF37CoGoKIQmde5tNLz9Vr16z1h9zE/viINVnXxCwpsb0k+JjEyhQtwJGaps0EGej5WdNyuXvQI
hU5xWBb0ct2HO3au4r1UlIJyu1AUmj+IfU9kjxgm9RWviWE8JjXWEum2p++3AQNqvIWYZtEksJy/
CBZZAyHou3pORCTVq6ApvxXsIj6On2CAYmT1z/wFNG11oLx8VQ0kEgNjwlzvGRKTdGiHy4nOvRb+
Nh1RwA4bYoetIHh+9aa333eRsboo/h7jRAJn9aaNGrqEvdL1FZlK6N/eggeTWwDTK2mMmFaIabPb
xSU2YHbk08iJxXfXBWMBjy/JpX8PVaTdQJWh/L6Uo3240gUMEHOdnnFqlqborVSB/OD/u3tTLJRD
Vwbixi5AEONF8uWF+EwDxEdcW1l/j6GaPHVDkMFskO07UjJaGsZBwarNS6hUDgoUw8l3FDblQTxL
advhFcq3DZQTxMntCqdVMXtcH8qB3F2mNWUkI4IM2h31yKPvhQDHSQkhv1aSZ9zta2W4q22GMwS6
UkiyYd58pvN5GNidSIrumVLQiIZRMYesAEyJH3rUq+ErEPTnZJGsxsLTndd8LZRcVGvcjJYTIlJh
HAGoYnBSAntNVqnYIYe3V4meGSJWbms/dL+FSaBnTW14vUJicU7B/1REYH37U6SePLB5LtKSm2wl
gwS+NKPAOASSxIo3w4RLHchWzoAvaTdS+RNPMuUOQ41q6HmoNjaeAeCsnrnzr+yUKg8Y6feQfMRq
vhPJ05z2uwxIiG+IAnnF/ormWE7Bt8TXij4BSw+knUkm1fJ/ZE2wq8o8FB34HuXquhame4f7LwQ+
kk3VFZYZrg6JVuXSpDQUjAbJfk28OytJgN7MMhIyxHCJ3ApilWmtoms5rRWZrpHNYprEGwoaTppH
+75Wtd59ZPy67SQvAFgJ6/4yS1v/IocmLB+TJ675pZkM9nqNwVP2tH4PBztWktCZ75vcyIxH0Ya6
YZY3bYU9iy0FLguC3YPlBO6Ov0e/e0DjvWxcuzZEbyEjvGJ8pNhL1OCM+ROptosmeE7h7m97Xhhr
eWYj3R+3cvgTuq384C5XfE50DD1SGqayqyq2locdZg6FuOUJNZCB0om4NGY/9KJYgmE+wZB77l1c
4zoFOcGd+S7KGwgW8z/0ilpKF0OWA4+xmcBRZ6OTfRd0/A+0zyl+kL3lZ99doF9mTBr4s4XVZt+p
vT4beshl6ww9QKamJDNGl9leI1NvMDcRWCHeO+1OqnoJFok75eYAY5XFhIRLL85bUGKAHnGOJQLL
svi99CKVzzvmahp3cLXKQdKxO+3udSXarJ5wz/a/7W5hUCowbsWlsc22I9hcOUceduAtvF86KGXp
GYk0l8g6ODfV9QMROFycg/xqNe3ukgGuvvw7P8we8cl2S4Bx8GKJyK2bBqM79c4i8QKX8sEvRvqM
wXs7qWFRaSJhn2TwuyttfheyOZ/oQmCS9sVZqyx8O5ItQRvgoEc4K703ctuBPPq6ouzjlzloxC2w
B/OStInnAclFyZRdvgpz50rn5eCXiF5j/AGBJ1FFG0jshcwtwVVXZ2YEtl8yiuWyc2boWXgO2F2Q
/tn0P5VJFfNs0oZib2WlysUPrpGOQ2PqWRmKEbkdabAYsunL03P7jyBvdEw22cvH0TunhRsGGdx8
llYwL+iw0kS7pqdnTQwOu5rSChvdNwRUZGndb1y7d7jQKJbbUS54vyKuow6g/AEjsoFoLeAs35EE
fXCljRNG32vc9FWfAwLspDo4jhBwf+VlNJiTcIrz1gUZFt0VdkaGrMuBfgGOSAZ6FXlI3JeUWnMY
CLsGyHM4P1UccMN0HiS/3nOxEFaiei3owz112u6dhEBjy0FDoruUB+I7qQWgiylxKgwHeQSRJgW4
U1lI+sKfpMA/vmYU1K1A/lG+N79youkqIIY6IFq49C6o/FsoZB76Q3zHqS6zcGPrZiZX1nPNDXKs
jTkeSbxVDX7jNyH7QoKnvzWmk58qqLR5ish1ENidEJsFP0w3uvTLmtHcrifKtOpw9AE4+vZA8BmI
IBzJHdgN0n80iYdyocXBqCGWg3xGuroqtqwm/9UfK9xO8w9JXcbsyYN2Wvidwsxl/ufQtfaj8yPg
QP7Rq/HhEqhSnUclXbInD2zFbY2brb6g85sYRati3wutNKyenp/3RD2ENMZYqaX4OLUvTr8OXo3s
FngrGNxZUg/kTp/NWeHmGTvIhmhDvkt+xOw34TrlQ9DBHaR4h0+N1rFzmgT9Djb87cXEAtqUCf2O
Tjkr2O5vopPkkAhhMr8x4K7tXfv3yprh+h1qAYEXQqitk387WxOAuXOCKo4w34lMHCbj7FcN8DRq
34nkgPymDHALbCL0MNhmrP+juObR9vATFUMI9FGBVbYqaTyIelQmd/RjfKw8MqcSpqvUQpSGdm/Q
LFmZFR6rKpO414OD22wP9qIk5lApfC5HgvBe91aVWH/sPylHeugiG5f2zZcRGW3ClvUmg0BtRbM1
2N30hSsqVfXI7rilpQ3vaQJDd0JbXm5cFSipOTs2MoBjLm1LiydRlmxVCxwhF7WoF8XZNq8kcqiD
HMbFPCLxbX8zCLQJPTdZTr0i4MGfkU6vyiEksYuozDPx7WYuTR+aiazK22dTK43pA3xr4NR9Vb/B
q28vYjogyVFQHHBqWlqHKRgAHuD3l9+Ci/XEEeNGnQ9AHxzkiIqxfXejiuqWe3PL0FYkwP43E23r
ggjsJfIc93l1MCBfPiFCc76wxTALbNzn1QuaBDbYDU0m6c9/0dzniI15hJ/fXiOTVwI9S9C8ikhc
oGv6moLvbv/Lm+/5avbJ5r0lE4pw8qjnC4CbafuXAi7bHenonFAkjii+YbODGHyhapQPg+z69PYw
Tj6WOKzE1QEyoVcmn9b2uDtQPohlPyUuP5e/9l/E3PvY6AnmZ8Xu0tHNtv7GVzrjQ9lcPWUVjpm6
15W/EJsEs/5FOoiUSnYnbs8d74yRjfVFfPIfaCp0JwUPdImYb8WtIa1wnBUS/JgajJad6BsNXO1b
f4omnEBmHunu5GxzMdzAgPfv7gtyhAfEkXNKBwE7uoNgXgNhkhsVwrc19Q+trvJ4PwtxKWOwRuB4
CogMsOLKSr71e5NxHIaCz9vJnKvGJsjgKg+o2jJrMMDpL7yKXvqXs5/SzuzahywpoZzscRcqDS+7
qQido9yCeOPwjfW+r1lMuHw/ScECn8ELSMO6bTBA3jUs5gB/bq0w4+xBRN5gWBjNseEGqn55nHjn
4MVDifffX+rDTlpmj/GMkTWeYApZVPOmnwVWfsN+ubL95//RhAvnDokTKsRVmSR7yFD/kTb+09CU
yOpE3FE3n1RvyN8sGSL9rxPbQwOhwojYwV+SChXRZ/dUDXTewgUfyXtWxyrbBAhfzSPEWD6nubv/
Bi5qqj9umY6XWovDxYj2G5RjU2H9liGn6jg0PqeqVc+6Yu29R/XgXI06TpAfJM3Dv4u/d+AkuHpb
SmDQ1eQWuMIfdT/YG1hOG22LegD2RgBXDMXH0CgWtaltnbgZs4ejcRmzeNpW/+mgixqg6eRkVhXG
4wcnvLQECMGmNX2yC1TCqhqx7JtRA5z6JgW1LDDBkXZfxcLaitJkPT0DPqxw8vClaI2gyIP2zA7f
MDghDLxgzViDXUc1LLUMwiLaXHH36h53xSLx/U8W3/LaYVQrDAW/Utu5E2zxl9DryrB2SYqfzD50
pYCvLDqSyu7mS6f86hbmQ2x3XCpJkYRwx1PAB8QEuJhe4PP/01LDfalCUXr/VRSZHvq/HoBIuJ8I
XA8alusRUOaCZmkIIkjrH+GdAdr4vKhD12d5/bYw7NXx3+x3QH0UNSQntiB+V8Cjb/N1A4tBOLkL
ta/r9cIZAQ0r5GU7koEWfLbFZDJWLb+gHL47QzpKVAB+vqiK4mvOpjqmgU72vYXK3KQRpWFzleGE
+5SsiqWBWLvbESVhf7wIT9TXZB9eQoHAITUvmQmaXuKSmNaa0+TP1wWOSmt/qZwA05p8be7IXh+5
L3mCbBg9QdXaZeDxcI3iC381UEeWUXTzn5a8LSkAyBUbHSIAkQ5Qsg3VZdUgxUFN0s769YevIYFn
JAfG6nxOfa0eD+/8U1FuC2pk+A/Pvg0vn2Z0nOtP01lyRqcRklYBqyqginrGrfHuFaJKVx8YrZt3
W7BwPRu5G2vovQU406IZsG9+XLN2DPYUk1ssbotS875JQiVqVH1BHYC5A/9FU/scty0Xs5tShoqj
BLFfMW6ImWMyoG3mXNVh3vERYOIFJeSKbLhx+C1AyaRQGCFYW9MaCEatg4WH0lyaQmT4IIcMEg42
q9tWVyM1yPvSWJCzOqB7lFwlh13uOXbU82X5j4KWKWr+HQrUGblqoNSa9d5MX54QV1xCxMiq/0ha
u6q6x8WZyFgJP9XOmpQvHk/7IBCxbYA56nTFLVU+RdCH1USdAw/4zCs7eP7aMAjNpNXJby/u1qac
onSIVvcEU07Ym+clgXO+jbdZzYU3AbxOYLfKqYye+o8v1fSxRBgnwq4pISuzkwLJ8wigWlmrDZM/
fX1lD3ASgnH3kah+efAZkBQbM6mfvFYd8UROlRY40u1D4SKAHr5QEF2DFA/x2Gms3q5q9mC7DcKj
Ed1/MvfxZnGMytM4cKn6CLgFhYchXk5vwpD9o/CV9ElPZEm/klwGc5A1I7zq0ClfuspX3Du1Go1h
Kg9J18aeroc7l1RL5DysLeBRfAilaP9Bb2PotEnrpHOUg95dWsqf28cBTH1TKXupcAkAFGhCbt/X
M1VqCmhttBxlaYm7r+JxdYNPs7Shb1GuJ2qwfwzxljMN3SYUgiIljkDHIwf3IMGScUAS5koj5E/o
It0Mj7qc/cf/wS1hBiMq7GK9I4D+KWdytDol8Cq8IkVKUCc+qsnxza8OI22NJT1c0GbUHOSwKTgF
yZy8GpTtzxDWjbo8cM/kh477blDmaLePsu8/c8WcajKCGQv05VgmQbCJhq6/55xuXcPua7U2KoL2
w/Z9ccgcPTTSpGwdPNHWy3Ig4nbZV2aFLJN+GTQUrMchyD6NT5Afuiv0gWMjiBb8pPMGenmfuJv8
cWZFypBZLOmlVGQqZS7RXkOx5JRHEtYbUF0Q7++rISZ0MDtG83+1z6madoF/jDdtrasETn4p2Qz3
53kJ2CFB5a3i5NIwr0v/gzNmk8ZOHiyuXVzX25Y0x9b9YTDmn8ksM7zi5JP2fD7HisLGkGhgzdtL
030Vefi+4sajB2+76RsfL7DNz8h8qVnhFEr5DkIcqNSLplgoXlx+ATPZhBw7ysBVr5hl5+gg7xgc
F9UIO5ukjSgcn2q32bGjw6/qwANBaoatxZ+ajVsgqzGdvOQ1fCO0eUK1om/V1oJqqxzF3uwXAb6D
or7I16kT3J53hjGWdTLWPaVxdYdzViMiRM9NKMGmdE4OzfsEK1UW/o8efnEVmcxVWokXSlSnf/NT
pHdrB44xsg+HJzaa3+PsBi+waM4nuC9xGQnBlQDMUTKX7cQ05da9gBdeZ7PJnBNAO1BD3Vv1KPHk
oJH/8T4ylPsV6gu2K+bGezjdb+/H2kfJIs2/OsK7HyBJfcqnrJ+gKUpflK4LWvJ4cZ/u2ll+7zYt
YMn6HOkEjQQsUhcdZ1cqpkdiaEKQSmDHsd9V58tEiQAn9Ncj9uGC21Ie4EcBUuHnLivki3ic6rfy
tuVoeoBn178COMzSXDtAtfyHTEAuY2yJac0xfcBOjvojipAGR1j1QZspo+524G/DcWLkIIUc66/U
z4C0BE+omvysDjlBpvm5Ym1g0Xy0I/IXAC5PB4xQswi8EujYmg==
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/fifo_generator_v11_0/builtin/builtin_prim_v6.vhd | 19 | 37128 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cIiYfk3Xy6N5OP4pq3GmqGiiVNUZ6H5+UojetFJBvbKolIu21jc4BnJQVK6clVlXeOqxCwUuMeWy
2HOHrYFv+g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lIziGPDmnLk8lYYpZIaDaMbL8fBzq4Pr1Jhh0ulXet+pjCJLyV5jakxS1oSptZ+tHYCT5i9DwoXk
484l0YBwGxIV/F50kQ4mY5SmovR5v/32XWyGw8Sob1+z/rA/iYbfy53jpQjBFTMhONxMl2jPMKOr
8b4lWHN3CKPgzR7gpH0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
htRzDc7r6AHMWLJSZlCSE/9tAboPhTxPArTqmJzMnfBntgIxMOX2YAPT8iZ7gZlglNlT/Bmc3ZIa
nj4bYkmP/Ed/Ze8J5Af7OuS/hLPfbdPEIMVOJrAzPKtgRUGYzZFakpIpDVbTLnXVCXGbnWwhbHOl
N+MoLyC3ep/1xGkMFlPyLgKVegokAfOd/5ePZ6yal5L+KR1ET32v4t5eGaONowzpG0O9uY8LtLQU
iVJDGAf4BzpePmtzOyeo5v68FfUFTjm1d6csF3e9pbQ9fEwJazksjJfyX2XYuUZH1eu5bhyJMU/O
c9/o5sfORhKXoxNo0FDKepouEYzneEXI8uuD0A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
FHtFxX6m7YezwdeWAQ6jmWMHTTCQ3ATyb5990cCrfHVNkzUwGdq1shf9GRL+uR3C20sVQ7v4/+tb
aJQn0JjlSYvQTO2Q6FVyjXNHAr7wpM4t4p6I4KuMXkNXuNp6PVpERQgKViWQe974sEr/n8wacl6w
0ZeeyAlvAxPvOHeW8Sc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WrHRD4nLu8DRRwrUtiyMH2ZN6Vs3L2kgyFgp5P9DMlNKTdIDDQa1yTQPpciIt64OlniyoYCatBqg
Wt8N5KlawExwntwLmfujXap7EAFuw40uyJX+yki/gczIgekz/25Q1+NPVfIAzqSReCro4UUW45VQ
4oIxLBIF53PvEJm3CGD200yoSxIl9Szkkq1FCyNtIufy0im7xj9CnEg/iFEwxzn8s8Ge79lV+lhg
fO4H7eA/Qsx28fzoVv2RYnMwC/Ln7iTt2527VU0KjrPDX1WGbNCJ5ny6IM/daMbuTMvJb5fz48+S
KUNyOcNxuhu15WGxxGlN6mcj5zB0r8XxgsnOfQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25744)
`protect data_block
EufbohqYXYXdSKgd2wid85QAz6nmZQlgwpxyaOJ6iU5HCwy5KcUzMU5Vk0eG7GRTWbqqwaELdsbR
eWwJt26/naD594YSUwZsF363lEqCh7g7mw2Tjh5wKmzg21ncivZ5TADtxkHoaKrLrtNTQmfg6Y7K
fch1+Fcv73dUCyijN6KfpAOQXPtfIF7QWZrdJ6k4NDCetzr7iK7HUssjfCYfK51WEKNfZRQiVWaW
z+RFZaWjJJe6UlE/0bL9T5/97oJa6aRIEz//oQnCMqhki8uMEuXo9dWSlqaHm5Gtqq3dVScF3nVU
IryEMtjK1gA0odj5PDQuJ57gNpNrrbvt7AKvlimUbzRJPzEcNWeVvl8a0iEBuJgWOmnAWZzrxZmn
3ya869WW/KAp+p3jtqrqtCcadMac1lWbKWYNJ8Q+zd2HMOetPxJGCuQiEc9sAD+oQoePJsmFI5nd
Myx43TgaFr4PoR+lcjEVvhf6vwQRxrVf+SedzLBPi4HLXn4EPxdZX4nLhkivAY/Mvf9G1DraNrLm
wqtLse9/LqIGOlRgnmrddSSjtJA+J1DJQGo+70iEFiliVIQjBThbm4oK8G3lT0bVcQcaXPKJB5tt
HuYsa42fkZpvQzPFZ9ef/S91298m4ZyCBiOM2RSb8lUtwT9DaIsDPcS+TIMnpfO+CA0eibRUsmwG
UnKmkQMjgOvBMqu2nhIPVPHtUwD45SDrPQDVCL+hJTQwWzL6Q3i1tnS68VRNtWTy75p0BgIZVAw+
d5KINDwwT77oX3MxIE7rTWsSDi9w9QAlmHf2bUA/fHxsuOxVhCCaTBntGjd9ZFGObkoPd8JDkPN1
AGb+rcl8iWOTlfiaApc/dL3/WKx5PsaKnAPa8wm1+6b1vgkrhLqPOJ5b1099jh9nitFbjmxRONfz
itpzL1PMEaLmpwiSVShcWG2MhoIdI0plXu/rO68ia37tVbb3xyarB+8V2jUBaHh+yquKJdU/egPc
P3rMVXqFBbWhhb8mXxO6bAYHgTHKAhTvBoxWvsKl9Uw96apSUF1dSdq7tt/AUfO9PL/bsIBZGwfl
vCKf5pq1UG2iWInMBJ7hod7Y/wg9xx19xqkFcvHubFHjHo4eN3mJx7f7Rr5fht7Bbf/het+kVbW7
kBZoCqNjehW2PjqUPNw2EyCLwl3mAp0eLNYcVNxqGbSex0XdefPpw0xRlP52d2tUabAmitkITope
Kpwyd28XQKmXS7Bug9S0XPb9r8OcMkdN96J1RaNlP4VlKEqLOUAfrP04e/csu/SawPSDFJQIjwih
7K/HKz3FCSHnxCBT/9KMbdM6qcIaYOU/ud4lCBg2jh9YCyjWHtDt1bEaf/lBuZUXthZIpCK+l9Kt
wSZdMHwnkSthvygcbC2g515wUoCaPuhRVeqg6m3oXzS6Wi7qvxJtA5RZoP0hlHr9n/TAVEhzVrkN
RjT8VkJWyDN8OKBzKijilyL72famQUekMyTE4gaujs4a1y9Vdn0Ll+tQKURFFaxFI0IZ3k7rGqTl
k4NlqS/mMydRScIAOVlUpZwKJudejPOzCHijyM9MEDZ1SyLJ+Hx4f6inrINpcC/Jwq3dGT+EeYfh
/0XMhfq2c6iYAVvOUyEvoJ3zlSEOPzWJabBKv2Qzoo5LQzcdq2dgLyIYTC9WsXqzxAU+hinta3CK
4nYoKsYZgYJVf2ruiJEpkb+gaa2ywKaRxd4TywuQsNgtdsg0yO2MrWVZe61smBZ8ptdpxYyGSvDe
VTFE5D/a5inntknJkiINU+hb8qDoxaVUkFb7WEsmj7TZ2G+8kj2R0qxQW82fdrOjQ08o9HSTHCKG
AnTABQ7zLVSJ3aBCXZmhVgUiZLZQS4HRFkOr+CxVhHLaLSpvvOVoJpNU0owVXwPsBbivWgDQJjzM
D+zsmzCD7qd1n6a8rENnADJx2o7qq0YPJTtu33FTvsOGOU9K1xXyf/rFEeoXUA6IG5CoY4v0sIo9
BtYnnIqNmFHBvwsno9vtRxvRy9oeiPVwM3GRu0TJidKdzBlzaY8N1y8VK1A8lsdYCClXBz8Vh3OH
YHMULtOPbLwBlBUjTtNIP3wLJX0QoKLuWjbnGl8cAhkLkcYONB7nVHEe+5EhU0OjQ2yn7/oNFJoM
arfnv1SAjAHzHeCa/ZnMkYMu0Oq7sMYh6CioIJHe6TYV7GjBef/WP8xL+KzDexcR1pHl8dLcAZiY
yy31/tGt1YcSDZsIB9xxi38eUlV4TUq07L160GoNEGTmX0EsChtLYYnBuI/TRULkd7ane059AbZw
OGG3NSO8O5sVeO4ogf50PNpU/Tcq3AVih8LfzKaJjrX1E5QeR7Yy8W2wBqzjB2R1Mv//TsfViE+i
9sHJS5GxEjIWMaFrTXgY0HS01360hR6LXsSHr8YqQerKUV5f/G8ozWyjayQ7pTwsNCZ2TGo/NzgQ
vriPyBXwfwus0Dz0HgCe9Jqr0sUVDBi4JZ6oywkSbhkXxRmKVTC4/arRMqyH5QVgp6YdrSfJdqCR
bnorb6nQ9kmR4xagorBZhRVzg6jySLqVwuYBe1tbZtpqkzb4Qhv1U/XtbSVi1QPufu0utw7qcuH6
gvFHJfxigK26sE2TAGI76t6ggD5k0yq/VYHnLIHDY7WElDwgtsdjEOTylRxt/EDezvdW7j6+iamk
tBNrlJaum2/f8D3QFqVlOZrAhrMhIWHsyqfsOQQL0wid2Ycu/ncgfZJ6lAcmuMkiw3PS5A69Fig5
woiZcu8O3rRsgMY2XDR8EwoxJBE3VDad/Qd8HCsP5+Cxv9eauUeBxYqaGirlY2DdA1LKznFjNNNZ
+wRBtTRFO3EWJkA2B2ADqIn6JcV1dQGN/pqhaFGla4R2OFno5EMZdUNUSBlScOl+DfE889NCEol6
2SJpmjjSMJkgw5dM6h3YgatJ2jracP4AP8kg1iZepUmPYvAM+BfY4O2/FUOGII/sIwnuSK4ES85i
JB0o9QFi0nxij7e3xzrxNN9A/VVe5v4ZcUGA12qX0F+Nk77yvteQxXpthfJd1SQ4Ekr1Yi7P995D
lBq9hkwqeN/+m/StFNjjL1LAWXEueLA/eAwa9gcgssvqVFVyKwLx6svVNnkLP/3wHhEANeVv6Feo
yqHPsW6Tf1OKu3skd7r6oynfBNSOEQALsDLzlK2bcTK07Fk05ET1xxMNWvQNOiyK2cSzQKeulG8c
U7GkBD+aMjAtYC0B9OPNj2c3a7UM1Bi00qI7y8AGRz99BZYHd9BAyTHes5LUZHtGzCSdGCkXnUG1
LoEezNxelj37f4K7jexsYqH49gLHwPR4avS3cDkVn2ghaAE22n0iTWu+ax0R+JB4Jt/RGEgPWxBa
0LqkNPKZ8zOT6hsS25jnhFwAIckbjs8qkDQcw0ary37mPLWvCadjxs7jKlDHWGS+D4VyIKmUaO5v
wL+NVS1xU5iP5EMM3uttLPJfoYYpCCHshnNT6UZwzS7djU/wChNpoKRiv4n+uD3LgWR8akMq2OTV
t4eV7DfQd2TA/CU4KOR2cWjB9Ao5XA6Jp7RgQj51ZT5gL4GmBQYVkwSQNamaG9F+EctTe9FRsvhZ
79L6K1jrldewaWDPPCbuO0wMqZp1alAXcs12pvqSxQhRPeTO31LhSVUWW4KhXGSnQ0ObJcZL2XHh
FMQ04dOjxvXU92l7OCjDlFsZxPNJzb7+yywM2bLM1AGBm7dNSmu0WRdIFeTN6iWt0bWv/yzZs2+B
iRnLuSwT80ON1foAZJiVoEb05jF/kyOIp71LTd8GvNeo11DTFhXOokgnZHEC7RA/ybqJRcSHpGox
uXbZGiuyGkmTFMsZd++uh+do+xX6vnYw7UHT3Qk9aCrdvw7PC1a1S3YIMTYe7JhEWvEdoG+SU8Xl
McEa92GatgEkfRQjGicEwoC4Rp0GhtWqdaiiPhKZYKAWaf8U/PyUhpox2QD+vcnm4T4wjzsZIQzZ
jj+3wq09qH0ioygYki9NGiBefzfzxUuCq4s7jlbEE0xUeWHOLEpFkBLbYjoJrsY5KjePUOkY6K85
53zzfQO/UFuba3dJGUOB9RBXHXV9WyTAGRbYwUE8vSUXQ0m6MSI7vfxFMPwWz3+z77/7qTIgiax5
0crPX1+lraifiN9UMEqmGLkW8qxTrLyNwW0LzVq/OurQcNuKmAgR8VX2j5fBafP26VihfXj+w5HZ
t/bOXPQcUtFa4MQaLgZ+Mb+nHEc2ilOn2yWMXyP6chLMuguB37vZEeoU1xNeJCe7bSWbd4jqZZeS
ced0jXLo29W01GyKGvwmF03HBfgSY9cA7oOaoUt9P+1u9N2Ah+6ptjaEzvE3W/7T7nX2B9tMZZOp
+v0KkGEF/BvXlboS2DR1xzWbSdQO3y9U5yM+JQayqDlhNW29lF8eGmMTtxITby8CRgHqsyoeYTRK
T1KHE/3gM9l9dEUPri7H1Emqne/yRNWDG0Zs0kVGetEXKzDOAPLGZxk8ggDjnBJ2hs2ymqOubxHp
JZK3xVsbMQ30y3/suX0+pE1zv9/EInsqM1hgpTzQzEtZf6RqnJEpGx9skThs32tVvy/ofR0yBmIa
3XpdR5oHyuUAkNAT/2Sv1Ma9bFL6P2PfP0Fnv6KBiJUPbJzyvkHEwoUK0V3bBoKimaZaAPBqWHyw
4VcozHz4PtERSXsszXoi6ok/VqE1z75jz92VlCtFiu0nYuUP1hEtLmD032kQt4bAhSn2jk1Du3IC
TaLdcM8aYCQchVFGPkrEEINjQYcfUCRdymuNUQyAQBHnbaF2H1RaRn8fUP7dEIq1SIt/uQeJEdY9
lDO67omDl8A3+QTwvqUINrYsd+OmnQb7WOHd0QKb3SxnJX83SESyHrRxtNJs0XPJeOlR8FBBB/MN
CYz5Nz5t0sV7MSreZrWMNG5BAkD6Pa0Q0h+VAa4sufjsJBEzHrHcSNUGNy5UDVn0Qos/jBPbhu+m
pEA2LANA3oerkkua+hpNLl7mcQqn7dceFPJgZr8VkxrxG6cXpIlq3NuL3AsdVJ9jMhh/C/NUPwaO
No83RPXpDQBlMeklHcEerRAnajGU/DS47egHhXv51d/KffXGh3DsX4V7c9AqZZEj+o1etIOvYLh4
PhRrbR1QBT4oWdte4BQtInpB7dnXkmtGo0SpWbK/YYqz5c0hgJbqqO+nRS6yoD7adzhR4aRrANmS
a6Y3fpqHFMD0Ij3V96cheB2c+TFKrxmLdFR+mDyP8pNfhWM9uNi2bwCnoFPBZJaIRO1k6Behq00f
WFabdiE87uZD5aLz/Cx9OarwkRVj/wc2zSzJXzMG7sljuU2GI9EaStWEx4jWrgx/nQZfi+xL0+KJ
doelEKtWvFwnUwY1Ur4eumm4cdEKqtArFuYOuy0oEqfa/K1xSsErPiDVyaQeeZcWklTspPB5RO8t
FtUUl7YOqrULKy1Sb91X9SyeS45Gl2pWUNJK4y+29/5MjPchJR/2l50HbBxt3inFMPePIsQaXrtj
MYWI9nYFrg51GnAgzTC/5L+WnBUo3sEuw3Y34mwK0aHrG99UtKgUz5ynNuXQTSEf7ppPRyDgWK3A
59Aukovejs2T6X4fksqzfa7u3W0WIncqhXy8Fp4pTKwEqD+bFNCsgnJJXftg9mMBqncXa5bUMvHG
nHciTm+rfByUQKQYOCQ3pxPop1SzkM6hC3UEfBdW31MMPNVn6pYj96AkPtKvdIGwaXFxpkdgWf1m
JjiwzCWUh5NTEDchCFxp7DPruXGz2ByR/pkaejHu79sRNDFnDqF3RD8NeykQtYiCMhPQp/1lU9nw
Fkz9NN7p6jQ+DK30HMQPUaSofKFpHmVA9l23F46OhZWRGW/nPu1t1q6QhkioYA6NZrefiGe9YmAu
/rboi0qfX6J06ZcJnM5U5q5IN5Vq/YTe9NtGQ2u4liD44gRyLyuV/GrosTXndlHCjHly3J0Ld5rR
QPR5FoUUwofQzL3e79Z1KTJI1mbgqbf/To3gHW3boF7V28XNB1foklTM/jvMcm7K4Fweoy9veKKH
H222yRfYvq0qn4afD6lF20e2Qt34qgRptytfYDDaWVBgJnnGXm+FUt5COJX0ULAVPwHNWS2vJfou
1nB7Wf+pF6YNUx/uKWJgp72LkYtOUZrReqXsJBBHsqRRW+/Icr169ak+0mTG2zJQ19W9GR7th3FB
DhRB0Zq+naCPRNXqE1/uFkIqyQPpWnx2dvMI4sErYPUHlw1dc8BXkZgJjiw+Iqi4dwx0V4UPZH45
vdp+lJULOuBXR1ZuMB1z9bOUDHX5jkMPu7rDB7+hhLPGf1y41GIK+LKGRZYpjako3hAqsx+6WcY4
2SyvOjrceAUT2TMnEi6FfLEdaQStEag6B+HMS1UQGW7kgziOUCs/+/pUw0RYNHRdZehA65slmQ+i
Wbnrm4mxo5u2nGqu1uqFLhhgC7dnwn7yYZ4AnCJhLv4MpoDlB3DhPui7Wunp6/vUXVAlqhk1CNMR
C3mIX3soJnKSW7SNAnSmjE8DJnW+FIq3zWd0o0UGsl2wxSMYIjx8FjapoShV1wG97ni80AAwG5Tk
9aduEhPCphvr5b8PD7ZWWoCT5NDwcL4zrCgKXoroE9uYMW8oVwhyJWKMnM3Y2+uFGd02Mz1qRUQa
yECfWufKo1NJL9RK8YigUqJZrMF0R95Se7JKOcQBtsQmJ3+cZoI2WCY0oZmMIiEcE0uj1bbXJm7S
y+cL4hJ66ThHizfWBk5G2Fjg2NFoHNydV6Gn5dlejq64RPRGS9SmjS6fqAfB25Ro8SoVlnYByDT0
hxtFEzvGLhFkcpcOTOsG0RI05UIeHE6+vD8uNPYTXq9kvgs+a61uVjauepnqtYJuDrDPhVm74pMs
10CJWZ+PUOdpZN8usJYVtspWXDtch7rN2hsojrNr0vN5/DZsdpCtIa0weggEOui+II4fjdWC+D1Z
BUnhor+RztGV7GLExfNGGhfDsziEE2WA1wpNjpJgw/yL0Q7TlWPO7c1xhYQRp2cKYpxBIgPYegGa
MCRbt2vSdGQpY48kAJjI8t0+VQvxsLfffQFxlNn5TWvE930KpSFH/g9feuUln0WytvmxURDfgnYO
joLsq2qKM42HaX11SeYfBkFvJurvT1nh0M6ZEE2KBjBoxXf0+GJy4EjXKwQtrfDFSTtvzkFmnkxG
DHsoRMTPdALEGEiZ8Bi84IXB0WfgRYtC6aR09VHuL/FGaPCrfFTD4jrspajjoVg0ty1VbudZ+3Fa
7uyPni/enGHLSKL203X8sx2EKaRaBZAYg+pMZzjGjHLXU7xXFvzyPkRuWibEj7jDjAgIMQgzkSMN
WZi0dEGh/HvEDuGNzXAAYSwNGKQQvQyBInvbEOebMXJgJq7b6CWLcRhwGQXeLIfiOqzzkxuzD9Qs
26WDvm4NBnDfeUM1IsvT0jX1c5xF283FrtVSLKtdhkFdWi9j4fk+7DLQ5mOqG9I27ncWOjZgYW4/
CdPJb3x+5fMugeQiA9rgbTVz1Hob2ebqdncFET5U94ZmN6nJouZN2B/bvqv53zTbz5qqQn+nbIqm
7u4BXAlXD4W2sU4DvhFob7Nr0/d1l8LRagjeuwFd1cMTB0s7AWconPm+BSUjgtLcsujyGUaQgRK1
QoDDV9nOs+xPCBoKcJugwM3thkeqHKqiL35/IYTyxekUxwFuIe/gKUf8G3GHvv1k6Ri8EL1ze/bO
y1iRdrPYTs/W3TJD2yZE4EOI98i4PMfsxJR5MLPihnj7AowKt62yiYaZdgHISG7MsAjkVQUfI0rx
A1rVINhUXiWC//LCzuv44sXWEySmSgFYvsQPA/QCfFDeK9qBPZo3Zu/Y40dJeT3hfgSezkvvPMm1
zTB10hTxErze7xJhQhLKcj94E+n4IGLxKS/1FyXaOMIWdjI7lgnRk91xr7tHf0YOqcAXkWVXer0u
ly/nkx7J8/xf6WUz4UkKBo7UBQA/0t6/Vq/psIU0uxA5pq+bZuzc/jVhvi22z1iFJbN23WcHenSJ
cCdRlKe8tH1ja2tTLkgm9QqcMzNBOiZZCFzXnw5wodDwJLcK8EvlAukJK/oWX0nztxilJ44LLl2x
yerHNm1ILPDBHZfGHjjtZOKk+y6u+LB47D01ERah2hRSL90NuyzHfnZx4HXPgsKOUnPh5fenEpiW
Vl8bH3Jwe6SmqY/tK74ySVyTxG3/ZBE7zZZttu/0FbtPrufw3+ZF7P91PMu3djQaFOxBk3PSIhw0
vlWpFObJSgCqWqgGi4lfj1VQkGKlrP3M8qBdPlii1de4jTwpzriaA7S4/5jXDYezCSZRK05aMcIn
ybDGwvRKFeDm0tw6M327XmVFlXcQeJqR3Lcdg6PLpdwO/G3RYxIfL00GHQl8DWow+6xL5Vft3ihp
G0+zVcp9icWK+Cr6lhqDL0bRT1WnjzZxvaMNdo22HlwMu8SSy+ZHgs9Mh4blUJY3MImbuJL7q5kr
xjolMeik4R9M5ETpdt8M4j9TWymcFum4UFRF8g7kXyyrnSLCa1iQ+8NuMHMfAf+qprxrBEvOTsj+
JteDWyz6illjV3s0UjdH5qMGxmWSqbRgTvaUZUKzARhuLtyyD+2zj8yuSo4dfhnFph/h1fOBKKvA
D8dN0CKOQsY4mth0kIFTCgN02QNN8PhvDH/NNL3wJ7FUnDrmbebgEt+ahsasQNUQcRWCSni0bQvo
N3mhs+3RRX4txqFEeLLHdWCcsTlsPSEXPK9k9pf8U83OEpbyJGkuiRfxtf6/FYNMrHT8MNWnjuW1
t0l1QrO3Jbi7wD3N8iyo3V4k5W05eOPuAtiSDQ7O7dqbPKgT07pIp2Xl1garDsv1xFdN1m3cQMa6
+Gzar39KHTJ6Gx2vFBfCXB/68WRV7lziE7n0BZCPK1AJ5aWhzzUF27caTzKkgCUww5/D2y4d+fX5
V65As3sqG/1uEh+wKiuJr8P962C1O+/tgceS+587oe7+b5//yNmwhYgX24NiwqQ3LJWAmPMU02LL
IS3nOj5qceZIXYNs87OUjQhK0KvZC7TRVsWLr0hr0ZdwHhGJhqaJrJPjMcCBhLBfBeBhP3Ji4ffD
qDq51Fr9Ksf+DYQV8fOsZq1WD2EFtayQkLtBLTJ8OvewdCTC9f52JadCvzkm6YYuPkxf8/XetKLY
KXHIQ/o9iaNNVstVrl0j2WVs0NZc/1w5AwbFygl9ztRfSoHmV/x2CKsM6qNIjMCf8RyflqQt9+j5
BeEDcAuq859NHHs3ljzqka0Zd7HjjdNE6I9gHb8JR82sUqOGdqVW6H4Xm9MibeK08IyhKKYhzCN/
jKundD6sCnX7L6Iixq9rhh1S5oQAjiLTvPcapp+FJMsagyO5jnfTWakK794XLXZ1E13EtnB3gcRZ
IwYYmzd92cUh32y6uN3iy9Slt7wBA/tePPJvF6E507+coiBOTVnheVlNyOAh8GQM4Gk7mXg8oSHj
bJtAWshNm2z4pQAKEe4NT9JBWXSuOlhkwlLdKbGTwA21Ju/fE0WMa+9Ao9mPc+DHqO82UPX9KJRn
wv3kjH+iwnBnQ/vAoUM92JFH1w8wb6OF1/xPrMJVNRtOQXSUudgCDqc+gJxF54dGQjGER+LIoG4E
UHAY0aQjpFwozqbpLvPpO/WKr4LGz1ZUldkbjJrBzxePyfbW47janAd8wxiZz0oxByP0SQe6JhrX
EW/eVuI3n8kcD0l/dSPBRseoXg3B75SgJpnK4pENmu1WyrA/ntLGl02KxvXL5TlReaTKzkF5brOL
EGCZA8yADZdOZoUqhjqUR0rkwiXiLTPhyocnrkFLKYmlOd5+fhjAPmrdepx/2mwOex2PF7PJvURH
yeqNh28TvmwheQccNqp+AxBgGA4XCoBK1wJcres6SLxxaoFNb3W3PVon/OPMBWx1cy/d3B0em5CF
rrBurq1tBhg3S5tBjtqVo97rn/OHit8jL+wEZKhdy6rvw6TssQHByQ0eNJTjHIqVEaNbA4xPWEaC
pXeMfJrbDsNzDAkv+d0fgwLTgpWzty7SzVyf8hLFdzo7/+A6Bi2KstH/cYG6I/Bs+Kk2QmDDgtff
L0rdCLtxVu9sGil6Dk/2HoOuu/f3d9thE2/M8fELlVOwT9Buqv81GOIdR1eudfbb1//neebIolpl
xOmN+jYCT84g0UcBcXJsY3nCb7D1pLGeYbeytdVEU40dE5rpzQyiDJ5v5x35Z0ylkE+Q1+iIrkHY
rxTwh6ifz1XrQDQe9BVDl1KloGoi/I23J6iakqLCiQKGHed7+odIoPWRKv//4GoKfxosGLEoOPhS
cNbaRn1TohVC6tMglmehn+WQgobiAxvCB1t0gsYdNgUdPGlp096Kii21zfMU9ergkfKCXYZGj0o2
P2/4iiOfMoxORz9G0gsgSLhHl6bFYExAi2kmL051u9bhNA/+kg+BR9lppHbpjhZaw/bqBgrYcSuU
e66G042G9i7/VfWSQQyLaimNz1uMBv/GF3PUMuvG44Iv/7yTIVxUJcDYMVvRSJr/FZ0c50wxCTjl
yBjHpcjV9VVG+oVb7to+JhghUoMTByNQZfRrNoQp/0XGwXFrEv/LQTSY4A9gvUGo6kX1pTs1os+L
3HrO1bflk85x0ZiDE4GCWyGOYspc+L2ikxau91sPrHZbGsAjPshX+34GH1JMU5hhYaR9Jj017bQR
watNo++FItAs1R5coRtNCyD8rwyBIpEpV/0T0+Ouvefyn/RUcH7Y0+c92ngXjJEACUJ3cn7oZQLF
laVlqOh3MQvqC1TVQAdjOXEllqXJptict/h+TNdBTDpBWq/WHRc3VsN/qABHG/NtiAjTPSgC+3Vu
3zovaSurCo6eZ+Rr6qS9WBT1d1HlfgDDHLxSKWsNjgZ1knM5aTzidzil9dVSbrSYVQDhRbhdgBPo
QISSR61NgJTal4MDVj3yE+aXh+Z8oL1HQY9vHr5b1xoaLEda1IQGAFo/yDEQf1ZfDRT/0V7DtwH8
YRIuawd7vZb54cBvFzBYSJMUIyNmsWbzI/WEmlW8bz4oEjAgf5y1DxNb7ccp2dl5aukPmQUO3iwl
3PAcWTjVEMGsQ1JR/9ZT/DRYvL+cy/CfUYGN0KRcTtzsixqO2A0A57omtSIYTSC7hJxdYhlB+XC2
Hnmfc4Aa/iPTc+c9Ri7Ngj2/lpz1DGXbxYjYjhs+wQD/nsfFB8I6sfNNOpb84W7PRYQeWgjA8FW7
Ix76EH3FIJU6+cL7bqwEjq0S5L94cTsuYNTYmUyuMkeGOVWtQZQmyY6xra6J/jSjzJkQVb0PpPlH
SwhzLiiizsnbMVo1RyfsjzdyoB4fa78QVRpZA9FNhPglf0ce26Vyl5pM++jpvLQF0j+NjwpSQOEt
Rh4SE6KUK6nVtIRtqEsGHT7qWu1zp8scw230ZD8cPThDP/kPhHHDTXcF6BvgJoIGHIMsHLwQjBHe
Dy/f9K/Oka7imaxplO77ixV1VdxEtPA6RK3SOVGCyB0K8jJRSinGq+gGL4Jj6CjRJBBKYovUh7Rv
Gzbsad7OvrrmXtZuaOYOTRtkwlVYwZDrAbDwhr2azxL0I06pkmwO90QB/a2RVKyealGY84IT232z
E4t7X9klOAM6FpI5leFrBSt6RVAKgI27JLmMmIFLq8SmeYMoEOp+Raf8/M65wED+HzW4OYBc4WkF
q/90CjNjh8pApVsV2ZJvPTMa99mKg+yiuz/hL3WSRyjR6apAm61YmVWZhpmOG52JFGo+Ow0Dn8Iz
jA5PUreWAo7S4WFC6vOej2fOWIcQ1Q3OsvML1thHmJGyskAXZeUGbNzEJP3WHy0gXRdrslI6ph2X
M9sNZBjYh30qes84AJ4V5skYt/aCVvQYWXqzar57tVAd7NTojtp96KRGOIk8tSfLakwcwFDitsxI
zWUWGS+Ms8C4oTgOvX1uVmmfbrhDrWbi+A6JnCFk7XR/DSu7YTAHtOWKeReCWQia07OBwfi2O50V
p8JlADtBKFieyLJhfOioEjjuZi4YqO4KcGdc79As0OY4Vg7G7oT4HfT6EqSffqUHjITBXqi5wO6E
vgD86WSa+eYOe7/EjPpO9cOuyb6FDASdBPqo5WcY2eofv1cQ1z6bAAQ7VS9kQnf95WxaYBdyG+HB
1Y2RzIXRKKpPg5xLWN5WFVJNCEtF8y4YdH6e34yByEy9Kelq+etx4226q5w6w3bSi10pSoygtURv
OXvlRY3BBUINfiIZwbbIH713Azr/bS84Y9IFUmf+J7jzVUouzaqMw8QRlVOle4fsS+7Hu/gDGnJh
1/QYzUPH9j+2ZR3CLAOA6KtViehg6kd14f4xdJSg7UEmoN5OohE4054xXNyHNYCipwa9Odz5p2ju
xNtyhYNdEkxy5Ww8N1nZUwbdGjjt/DDrtmkBd1cMWXHJ4hxUEHH4PFLde4rk/Dev37RDZBBut0BW
K1tYDqf1L+Pecmw4ldf/ckx7Z5mBfa/F4hV+TQlgir/CEb3vh2VRlKqyhIM+T+z4Th4GjD7F0gsF
PIFi7X8a5nRqGXFKpCqddenWkgujisRdqabaUbq25dwdhVHiBFuYjL64FKYJkwqhcNnW6pGGlFTh
Kg2O8fFG5hqjRTmanGkhtUsWr6yp+oRyXLaeHMlbgsN+VMY0EQ/tjnWbYDzfVthJxdYu80vJV54u
SWCDKRU4cBwQcSw+mskB/J9QnTMJQ03Jp+DjOXbAsmYcVRX4lSaj6E1cgk0I4xB0F3qcAgryR9iV
+Trxpn64GLc+Lzgk4N06vJeQLUw/urW6GoDiilWJpYr8qDImBTgjw36yT5UtpzjC6s65dN96YXKb
Uu8sA5Feq4xkXKMfv5hmb5+JlkkJihdt4IO/lgH8YJ1o2Wit1xKp2XjKjZ+Kow8H8vSw/116jUbY
wXBioA9Rigizi+yx1/aZ14fpTMnAfN6t6KdBJWN12bUJaoeZ/AfKF5os+g5cb8LyE0ySTvWorPkr
wjjhYda7w9cIN+RpNoAyeMd8Or4olm9AqNAXHsegAC8ZAQnDxB5aBuFh198xiFcxbpoEi8C6EWei
It6d0XflDCNku2cs5uPLfWyIuH+yCgBaJkkCWSPgHjmdLHXZgSGzCat7tjNVQ/WPgmKc5M1Wc3Dh
9NxoHJ5/TakqFLeBOYyK3b8rOTbCAjIeE6Bvz10j0Bp6xpGNJuOviL60KW3N4STusQrYxwejsVoy
b5R9fM2sqS0oDOT6ohGJxnkEKASrTNinyzxFdaq5ubP4v4v1J8X7jgVZZi62WWJBewadI1GTX03a
fVXqPtNhdnUCXFiBMkYeCZPOFlRu84wlQ5b+7yKbVcn4hWH4TPfsJghPOBjmx5wVhP3cx4eSQtMs
BafqcWMbsJVtCgG34c5ghS9Q0cmtivfjsdAhaWc2osYy319v28OSr7BBXXaYo3uScTmFU074Xjc9
zYMajRLSvdznyxKGGBahVYjMb4q2+hDW/dMk5TsSs8YL02ezleUkVsoMOIq4GXyXD47YssfBN1Uw
1zjLXUJAGqQdE5q3DimuW/EVhnGHGgJFSKAqWsWMu/D64gfW5vpLlJUbXKSVlfGsCdpikhDvsaCF
DIaR6HC14TYL1WgQViz3zuUfBLntiedRv+kkixxXASPHuRKfwirBObSCEbgn2xFmycuK2xCOyWWb
0UQo5wvqIU7ZtQKTth0sW5j/yNXE1xvuGMAt2AMmm24O73dpUXqMQnHVZROWAllphy3mTh8TtvjQ
JSFt240jW22skHAVV4XbCfR+1Wim88vjWSAM3K4DujsRF4AgT117tvkuEAb9GjOvKzEx8Z9MxNoE
C+OmbakxOg0mq8sh487GIJOG7OW31eZo/4dfKOJfG1QxAgro6HpoaOUTmcJz2eg5Hn2ZmJ+c2Di2
gALfxK/aXLa/JaW/Tw5ygMKNgxVmzFx6CNP1FrbLjMR1QbRuzAC8z+ieBAmK7JHWfoJo/dBSIHM9
OEAOZ5w1WXveTRcWseaJhw5W2EBeoqdUBmbYajn4cb1TnoumQB+eNMA/GfS7+ZuJifnlp+RCJrFd
VZwt/HF7+NAVoRfUF8hxf4TTTJksH+YBs6NFYIZDocNTmNHeMUplHADkvDzM+anBzNBVR6ffX0L9
qWw4hDQGUZFyGwWQIVu8xHjw3tMPx8R+38BPPzVLR8XL/EQb08OrWWdjPw+q7gK9p5xoz8zkH8Uq
sXgoq5t0tc4/HbeCzV5hmrQqQDNb2gmUjTLyIY5R5p6HK7rECHXi684EoJ/GC7dfGprGWwrqah+g
3qM8CjyQyN2oWgRddYhWXU8obNzG0U9/4bhXak+BEzi8SR0qsCsmG+PQ5hc7N0LvMHWkKSw9YYtF
ZCUMICUNEMGeIoS5M17V5fyQJs8jFCP1XLHr3jQWHg5a9jI4Me5p7oC0VDytmPOWruKPeYeZAYTz
Kqle6AHOmuuHzimy9N5YmPZcIe/y+MJtqsky4f7rk17IIYdfKPLfivQUIyChkKvi2CZA874nIVOX
ue2BEwhjYOiKv+Xqj0ZXNdwdRAh17OEGlfKnnQy2c7YSMSgSugsiRe6rHi9fZ44gI3xe20OCvTiv
yLLLyLxMI8bU9rokOFxmCNowPLRiYeSYcqkW5DvKudqklTjW8mQXZcHQsO9Ce5yuPcOz5yk0zyxp
630x8AzS2tUfHfuiZ1RaXCe3gvkQ0r9hTLv4olzAE/stq8nmLdwwQAHGYHOy29SRRwchV1fWBA8b
wWaPf9A0d9l05U1ekG3iW3gMMyj6rbDDyeMFcf76LhAMdZt4JegiRFTmUMfzXOB7LKr3E1KtxyQr
Fq3mQiyrdJck9+3AqI4IpziNQtn70Jl8t5S52jT8vyCu2yBHlw4JYMdQqWZZwoNW4MYiQnIQiur3
0ZrT8yMbRkiZCg0l5ypAbW3q2JmoJLDJwp/hSMx9DPYQu949ZyXLP3eyjizYVD+Zy41t4ueFQo9v
h/Y2JPbOcZ3k9QJLyilQ5EUZBCbFmaknZnH9t6+qJSLH9lhZrvTuczh5/1BFA2zd2EJAOzlBZlVw
G856lLk630RhZ+XGRO0d428yGyh1UGJJkruGd9rUHwsQqfiFgY78IKMWner/3RX+fql21RZXjWWW
xcEWGMlb7IFoN/5YoivjmeYd0jumvBgovFtEAe2Typ4R/gx/p/HZ39bPOdmrGouOKfJhLGIBRFJR
RKV+9j5P/fGGmb8YzoJa2xa45WLFhiyqzWuzIijN7SS5ofnA8lYRVx3HIe+el5H4XbLJqyZNSfHD
0XDQWWuyLYXlnu/juRfuWFo2R7yQXVY62A4SIikcEQDSf+Id8cEXl/IctdXLY6M1SOQH1yZAb1qQ
v01muPTJFbDCggkZsSTZG890oD4I2RJt5ugt8NXh2waMhn263qg5xiTEhZKYcfp7qrqqk0UN55SH
IBq4NSOUo4PUQZYkdP5NjpekOa6rdrIQ23KgKil3uAqiHKD2xz3G+2xf8eO1rXOBwIdFS+DZTVib
wESriOIpfiF31VhaV+/cFxK57/CEueloRECrbAOgha5ePzztVES2Gdcl2DwQHznzVAFcyG3FF6ug
6twRXTsB7zCWyNMkS3vc1HUKscG1XP+tLvqdhdJnrn/xzGxnR/RCd4HwdW+GazEsT9Q0CGLzBHGA
rEAn6mE0pAEUf15GEzQVlh6g58hjkVxh6gV+88liBx/kfVi3Lrgb9cdkTmSx4UKkURO4KskSaxVa
Ss+VeM/OFkrRnxa2Qr7A2Oh9x8bxbhsniza+PFMR62cSh/1Z+axpYL/gpdhgfgFIf/wVlSMHyU5N
J5ERF41M6VHqylKDi7dbguElqpI8B8egtewT+XK6Y9cG5cyZkbRRlIqAT99sBpDx9nZe/DLLoVNs
7x4r+r6LqOLLrO6gTv5xNFmW8g/8Z1Ruwq2uKvUGmcBWgxyequhMBL8chFfImnS1Ga8ud0JeUqFW
yYRuzfLWdVM1IGhbaeRQ25hcyd/MrNuBaAabSydrdxy8k1QFCDp/mtgr8EBnpUw9b1TgTEbm0i4C
4TN/1m9fyuqJxwZHMXNPAcIsBFqRZ5a5ow6dQQUThYaeC5/hK5305sTAvRKgzQXCzPPzjNhkC/R+
22PdzVU3s6ehXg4HTZWO+PVJk28leRtpHIPRYefw9UPl5T5I8OLxEOkIm3Um9c5OW+LeSTbqlQsG
Y8N0nCSExZftuLGQPc2kt3D3CIVUe3QEQm7rSMBryP9nJ6WhzU5x9pYvs+DI8nzsblrwS2KbxzEc
eEHsOgTYFRimid5MtOoZIetxWqClMLfvF4K0/bl9q+UmY5+7VuiY4sO/J/V+H+C3rU9EvGva0a9Z
D8TDYO5UYnZ4MlVl8h4zZcnmOlpvSVjhpLualxqi+zE0c509uZY6696sC0PHd/cC+rcN/Wk/RLO4
IG8eXqdfyA+ysdDNH31rvUQDENcxbVWB+ulYciLA20/xrQNIM8ItpZyAL4kV6YKGFWq9us0eVYWg
LiIDkBI6w5ZwLUDJByzm2lfb0WomTOXWxkG/4s4XiKuawBaZDOxm4XhWC1JxGrgaoYejKrfp7X3v
zPsWGkb6/P0h8CEzwkZ41+JBs3fhcyv+BTOdJq9VHy9m8/sGQvp93cYTkUKVQhlyw9GT0kvfUtZW
anY+mQEew2gd+5zOTzRiUeJSVYmUZy5P9SMW5vt4EXCPn83ZA4i85YUN+h2QWzzjS4/ptSTMga+0
/7FMz4YdQOYHGcfmA5DJAMZemsYH+rWfp1UV/Uk8mwv0IL0rrJmew9HpnXFsbx8l/qldGJpmVIfp
XRwycA50UXgOb1zmAMSFKOeGspYgNp7qHJasPcZN4m7JVRf3ngiBJrb9eNqX/YyYMOnafRfookan
V5ywMR2rGEiFqFEWAGs/vOQi5zccb6h16GfVsCGFCvx/gDJ59nZt98jxbWsCMF6ApgCbDxcHZ2CW
JNARVyrgMPOn3i81x96HPgGoohrgw+81bU6pxsu3V5WrZD3KVZu/WdkmN7FLipC0fu30GSKjNaH0
5+ATEkl8D0v41uocIUh1x0O99mz5lM0SNBtZBakVChmJlI32UzeJAKk/IqEQlaJHl74JmKIVWKWP
MshDlUwLvEW2uxW6nGU/4eV1Ep4JZ24p3NQnKH587epHlsBSrLQE6K19br6fTLFhDCT4SGVTOWMz
n0BMcCbHojKPITrHA+o6U/F5smir+6W1UFpoeFoSQF+qvuQ5Ymc55h2Et3AUFf3ZspAwID4PiXaB
jCYUL3PIKq4XYSRxOwlnPAHdArkPrvMjFofEaxJIB/1IeEYwW4HuVdhk1RndGkGGE2GsLL/hhFc6
4BPE9DneGG/Ge1xc+dkGrYGRVDlDD1SXPRzv9kP8b5qXzI8HspPrYYBPBeTHdao5Cw5eWZFaD9sy
YQHsLb0UzcVYYI2jvi/73GOFqgaUDPeX/+uGP/MyxooUAvBaRN5pAI2cqYQnUQfOGWTjwLoCxGDK
DyCQlBJvOfoQEwBrrnZLLOT/bww8WS/RQannROZ9dfwsnQdp73VIe6JqT/tjbmazVA1BtaLWiFwc
3YHBF1baQgftOjAC03SW6Wi+ZpuOXvO788sdYVkPDb5DLz2bDRpWFoCKNyu37EqqQAsAA373Jy/+
GFjXNTqf/SjPtXshsyNPzD2pKbcyC2M+nqP9DiSgLxoMKHrmVIlOiczgfCbHw8KbgG0jgYXtOzEL
8NhhtWHM1tUzAU7YLIreoCKYsS2Tc03g4vY4B/xPgBOLiJy9FtE014SRq/AidTIy1mv3M9IG+CTo
dLAmaLpXNhK+hV79YINmWoSDe8kvpPLtwmQAme8866yy/iAR04GvV54FYRVEcwEucPAPE2ICftFU
AyBeNuaMr5uZ7YKJ/0NnG5G8g491rBJUedKBy7NyYVj4sjAezbf45TNoTVScrBVI2FNdfRt/7fHj
+49T7u/kRhgKOdDfuMIsLjXBJFACjR4RnT8C1iH5rThsrFCy4a2icXBMyYl5j9UZhVIsmn5Regwf
DvHdBKvS0//Gy+6j3d3haxyP8XgvQRReXRUxHOeO2esZzUNAXHCT4IW6ote/HbcDLrNiYAhOyd02
Hxfl/40al2ldzOzsqRvt/pOxlbpJ5k0B51+92aJGUgYNb/Ib1nVIIXlobXTxP6v41roH8u49y1r4
paiys+hHOOKENbUKbdQAzaV/19J6NTkt+5hfqSYIGdp8Lt5zrKYg85vBXeu0Lry9YlexkVUl0Ntr
KpfA4VCF1JzirKYpQ5blPnJcej2xo/tXwI2dnxfNBPx6IaDdYgchsf6uv/GJNXJl9SMCHkNb5Nm7
B4wkN3ZiW30mUhnWHA9lWBTJfP2uPI0xJtejQ3+y6DHcpuL5KjvjmKP0WplSEJEYMxtAFdcZA73l
CUqgnrfWCMNkgqPUPK8qgTkDxSusAEQUQg4HfNWimRRsMuBkISgIC6a+DRDZQNMeORs70ZH5mNAC
dcDVkFf/hl9XUNLGfMTaqzfxqUyvfS5HJarmdhLIBgKJeWafCRSUEjdY1y+ekyfq3uMfipGDeFL5
FFBZvGhyU9xKxjyj8FizZZkUbLPXEDHAa98tltn8JJG5xYBShbwcBJ4WIUU47xbvm3kwVKWWQXOJ
FuG4Mbx5mQG3xbSxk7ZZVa0PiCKA8ozI8zTGOl2TUYydTAap2x8CPR+lWu4jl2fUfexKWGzZOC9C
1hDryMtICGcbbiUGMZCINsTWEEcnyoe3Mc7oWvHiSiGvqSGa7wdTFiOPAt9aT86QZ7KhO7PMAxcA
iXXxJ5mxNWx/6IUGy+JCznZ0NjrFIUbatewkPSvjfEqd5CvWpzeoPQLzZxui1asFBHeOPpnRingg
PD035lTCKUXMGCh6VSg3G0va987857ELRITmWyGMqoRA5OIJxRENl6iSxrx5AamSVnO4y47JlqdD
jM1uzsP9Xw3HqpvshAnmKS1tXSGmo/Vl2GfO3Cc8o/5SV+qIy8HODbM0Vmm+6LS2FsbGkTd0UNDG
nKJu7fNyvHrXgZh+CMZgX+3Uft/K8eSnCEsR0VOIifNJMmNE3VqzhN3NKcov1QYwMC9ecASHkybX
0IYSVFrTdo3FUiqtEFUs5nxBlJ4+8783yZzKDO1V4bqs2w52P6rOkXFpAUJfekiIs6fW31DMBOrC
UctdestckjL/lTL9qRa9bWCh86TnK6vMEBL4FFqwl6BaSjC0DoxXsdLz+CSSRvqmj5KfhL1p1WqI
YshW8vi3B6VLbWutmZAPLCP4nURO3iVvb0buRO8ipwswYEtegrvuVUfOh+S49KEFQE5pcFU5vali
JqX3Q0OUEPurV2BQHyWPXq+UBvH4PC7ImdJzMNr6LLqQ9Bvj299QVhcU60y2yPUPSmP2B6iQbshl
oe/b+p8G+u1L08qMfm7AbX/iMSGyzhRpfDfWvZ59RMgqOUqn1sogCQ+PzgfuX2FJWsmbONgqtTed
LV90dQBvwbDshPcFw9Ns7G5C+ix4BGAnw9LN8XlZZPnA6IxSObXuDr8YBeP5I82Wgq4ypV2nrcWd
f3HWS4x/CCKh5nHh7HAdad21mPIIgO9HZZrkUwnwLmru8IkXMzS/OP2iuxQ/FAAqL2Ifs+Cp6eYX
OyP+aGxa4+/mj4aENIFWIc1xiz7DWM86KlVzu9/dT/m2A/kyUiR2Im2YCy9btoya5w6fakwzQFdL
UU6XubYaoB7W7Sd9+H+HbCai+X0c4IuAnGN6UBTDFOsPazc9HIfyqwo8Sy6Nk79gRNyhI2M6Sx3G
CQPAYMrPGQYRW9jizixpXkSwz6T2rUQYDzqohPnvRF3GWhpypRqF1eUT0n0Aqv1Aq/+JVLTYkLc0
o7WY8vmbyVLVCO5I0q8vpMFwzvmAgaCgueRytncdlQIKM36lakkFxBVrfepmsVJxx7RkJ7+X8U7D
GZlOSZnoPXdZ12P0p7g/of36BDJyyMu8TQqhyQimpu2MqxtcuweCP//J1W159VNUf9nY2kIf5WnD
FlOKmU8fgEtSOYWvisRYN1eSi9G1wZzmBm/V9q5jxToijWQgCZ4kDPFUze9HaJ+eq5sybHe2aZBF
JQiz5CNKp9t4XZbP4Uwhv6FEuKUZouXhuVBcFvej19MRdildKXguoBQbM7RvVs/CHU4Jd3jEYddQ
dzCIOQzZjc17GxQcYmt1BTa+hNPsdnQQbE6LbPC8BgjcPVeLpFqBkf+qV6EcQsoWg2a3Xwtyfbki
+PPX3DFyvQ0+MmmBvMuH2Hhcq3lVPIy6KmyLbXGJYFiF13DzLUXzysfSV2f0UfKoMMohTDEvRFJW
j9s7MVio0WPCb9i4drg8VcGmbB5BcsgqFCHayIag/u58dd6AYHREiUO6UYblam906/gK02Gy1hL9
eKa212YLT7c6g5WXQrOfDly9GgIk4jMaEY80zH+owR1CSH0dUb6IqJrOqZuLLFFMitUSdP4j0sjA
jvGyLJ7t4XIFVgBQf5BKLRG3beILvl9IQ/qx7GtyvwwOxO4Csj/prBVWcZeZfjr//7WbxjnulhnT
PRHbZ0r+4VOl7Cp7YV5jbYlGgkZohsj8PDsGQ22/jxlQvdEnPcWXSBPRqKrX3J0SPn62EhQeM1KZ
m6PqvnDMa/YhY7+iSp5Io3Mj1g8AtVG40wigf9MzH7Msy08oDeNmpKkITRR91l+q/MUf5gTPuPv8
zW1X39ToAr9AbN3yZisJtGWeKHopAS6cAU4bCDYSgU/g/NK+SSSxMAlmJ9eL0L+YqrSnEhH48eDm
GMYmM3JM6wvmy9W7XAWliiZ+eRCk8FenOkD/TkM0pkiDpqKPDT6N3BHe1Mj8xFnHjBL+Tynvnffi
AHM0dmHkqCVg7stf1eGzxtULWczeASEfWQjRa0FvD5XR+AIob8+4h0XWEpsTtzWQIQ5fY5FKKcFa
ptgzsBvGfvc5gRl5teoFHOLyUWJrPn3wyzIKmxufk9wmIRx6zxO4uWfni8pOGbEEJ1sVV8SbLUgg
QwfsQ6Kb/ZVt0O8Bt1CQ77rKcYH0O4nfSc9FzOetGdgFNwnehKni6ENZ4N63gFhb0jPAakcZ+L4s
UIntg7AiWG9qpPdpmAsAnZkk49SH58jztCsBU0y9+2xlVZ2RDjl4U022V8OR4YQKpToYdBQjhGUJ
5XvlGeV90KUXVqp6kwDA3pFThaFkoFExO4mFNoDd9YPJ8NueP+zcjVVUV+1q/ebZCx+8FyMyoSUV
A7MAhB/hdVnfAvVY9/LEgKKAUIVn9wxG0jZUQUK03ViJyEp/BAZYXbYfIABr3l1T+kA6vLVFTZhK
kXQoDlPUVBMSo35awNWfwJutimS+UHMWcE+WjZTY8BBcRSqlBscZcs5NSeYvRuUARlcbQ0Y98xBs
zkiCdsvKZsZB1vv1iIoh+wibcvjqOhItHQzr4vJ5NgWON2/qa3Q/MVbrLx8r+T2O1PXw+VVHn+fE
2966FSDxHbq/44Mm+cfQRZJ/ObaBAJJ+WpmbAXyjrUSu9rnYGsYSAboxTWbF2mY5uCtMVNkdJ7mj
+94YTe/EWsLCjPVLb5iJWPHNK88FJqXwj8ttz9DI5h2I+FJq2CgW13C/HgSdlcLMP6BOji8poXfw
JWX1LhlxqWL8Yv7s2neTvhPMkHN3a13HYL/QR/iR8n6dZhmjp+tqCZcjE6r2EQhNbE3Br1t7KGQa
FWpM7eNehADIKGGowKPSpteBAhvkykyj4OudxPm21moeJOfK1lTB7a+Q6AntSVANbskg3sNztcCi
Z/KeQKpa78FMvrJBusRLFoh1i3RuFObnLUSeLoeYawKYIWy/ci3QYwPN2wiVHx4LZGd523G/IU51
I6to1MjQVD7ceNPMIoo443+OqUQoiNGkxa63+uuSvGAbNGutHvjjOtQ9F+xO3aWqiSixcgc7VLGY
xrpghYMhy22zAXPF5cP+RhkLUEfgwQQD5TaKq4H9DSVsowbUo6+0emIS86ZlkJAunzgs/vcchqIJ
v6qpphwbcX/U2LBlBEbKinoVSCqC4imEDfQY1Q2bgFB4Lk3p8Ce8ga5uBZGhRCp6aFDfM+r9syDA
gRKwwtQ1wWYYZA9VwOXpOM9VLIi3+onlSzqchfrMSzsRcPKr8fQ2JZxLfgtmwfAJ/itjYWtTN//0
yQ+6GSsScJsTnqyNXGW8GQ2SdGhXcnBBi/WPx1SGMt/ZA5g9Hp2toHhgPJl8blkPLn9Z7LD0AvJg
lrl1iyq/mC5GnsuxKm0pG0wuHh1F9r1UccoU/C8yTh2h91sNNGKMYCwT2Vq6Gh4Ny9nwIIKl1RGi
aNIuFHocMgDzXmPlpuBfrQDh72efVDzM1y/hhXQ5XzdCs2zzvxbPda2QnkvnsdND8riNRge4GbGg
EOcHSAXndvAxGJ2KBCktVsQdbcKt+F/fSVoi8HfAS34gMHi/GXi9rg8u2mj+9HzpDEzE0DKg4HRf
PHf8Pl6H8Ct133PxAaTb9xJwzqwdqMWdSfHNz04VKnELxt6eawj6/pzmoT1DrEW/pI3Y5HojUo1T
nCe3wHXo0E4JUj4/8HQJYWlC5LERDxSyO/jSVOFOM38/zPeCR+inSBOt6O5Eed9CI/WwXdHCnVzV
Ky9pzB4j5l8IWip8iBjG5YK71Xg/4eauRncYcWLLJXGxXSViw9FOT26IwFFYlzVSNS+cIFJtLGqr
4n80fEKHQncCR/pI71iy/0gO1G8S6MLFBkfWEdT4i604lG19mu5hVkO0ic0jJprRyKWfLvpHvxMh
w+Uf21v5SG2QPRd7b2xDJe0Rla6klsNyLM7tuIZd0E2vynU+0iYiOQX24OQup8vMparqoo0DwK3m
O+zAhuSNuyInF+6EWSz1ZT9MXlXF8n1rpWCw1Jtx8pty7rqjqUbYXoQABTUZc1avfBlGdCnxiYIC
4f0rMYaVUr65IKHwJ8A+iksDSVcA/KWQLQwJgT9C8YGYeSd/cVu9CGEnbmOYySFvMVZdfKHfC0Vs
pgCVjpgviM/fp85PE+mVD40a200+mBt04rr987n5xcd/2jvQD8CH/aQrkLSVj8Tzjp0RiN+cnqlp
FkSmleG93FxwOUuWG5Tx7O1hkAsamXyuDAvf2ADRVupYIj/GxhgQUi8pwx+/PCy1yai2avHv8Z/R
Y4VsW1ZzpVXhTiHCDUD7BhKHkZzLrJMp82ziuw5kr6Gs72E/3XQU6XT+3t00ss5F353EJULGIME3
jcVGNVq+4/3GOEf48j2AUVEEy/GaudPgtYedG/wKdqaMhJEic35y/QsnnRS8c1ZIxI8wBLfVrgeD
iy2QThZvgTnG5T1I9uZA7Zb2Ac8a5dRlkKrXr/aR/SPiUwVULRojBYqN/Luav658prV340AlcnOm
HNvuJfdUnO1UElhoIU9sQw+JcZ1+jPAKl+l+zDVAIwhjnK3qG8JYhNpqMp9by8DHB2XeLEWbcpNI
cBt5V01birZjJ5/B+/+AfNYzSXFXc37chmiZuxpPJ1VK+LLgau50rC5AqvUvxVMOiw1v/lmXq3c5
ozJZP3hNQe0ECPh58ddQt80SoW4x9xKH15Ht7fYU1LOCmrhPDxJUGCzuEyOkyDXJlmUpabMD51A+
6PFwKpedodpoTS5eBzuL0BvKD3MF/EzdLKmTu6PX0M53Ir1aptQhXU5CETB++nMDFsY164+PyVk8
bcRhFWIo86xIfI3qQqVsapCDqJKnB8aNQGJoXI3hmHylDC+Fzatj8HoH6juf19Ruac5j7XuTjJcz
f+O/rSCwNw4Dg9XBT7dbI39fh7XNABvqkQXvOCPjU2s3G/fjDQpgd6BNKogY/yNNVcWNpzhOlmCx
nM1yXd0AMz+uwIfQHoSUuyyeKnBF49j0clcmndDXgw4vTo1xoQgOEOarRKpn2AuuZ51Xq2A++jy8
WYXkiE9+2yijLpEYSFJ+/UaJRF9K29ZgVcoPHWoVzp7Z9eE4HTIqBSC4H7JLVDNDBK66xUxingmd
ag7ao5ErS1QRwSOOtjs2KF9ibUf7PKAd2tMZOeRd7Yha76uQrA0NsmBCZ236JutQ6kMcLOy/pguP
c+cPsXdP0n9qk8tFFd7wt40tr5Shu51Z88ubLeF5OyLxeay0Ov/94LGLfyYiX8MyNYzslVjzC9qD
0ED3x6/LaUTl6HHf9ld4UjBWbesMIXviaRKpBsp2dsU8ckDAUILm1I3V+XUq/mhYwsLWRvVuXOO5
/8TiRv6ejQ5ldsCJAk406e46yVJNJJUR2X2PDQxpvxrhJq6Fjh/wQCDqogkJ2u5A3ZYDfOdHsdCx
83aVGM9SH1VwiSF3MdzNSb+dNeNOcAp3Yod6GdKalF61CjvezHY8DG4ba4n38g5e5/7S1LVDY6jR
oXW7rpoOZgtmWpJlNtUnKpe6g1pjx2lzlVlrIdlgN5w8E0q0MymH7iPvhibFD8GlPL2AYFAtM75R
qiKXcD7QghANT0xaTJPLacVI/08GyUCwqELHejbX8t86opKcs9ljvBqVgBIEZvvNjPkzUs3a6m1D
WkT3FryPemen90NEGRfsTzOuskW3e6ApyA2qeCLz2Ezf5vUEhlgz58NujiujMdpIsux2UlACrSmD
TZrZAUuE5S2sA/OqF5FijCL7GMdcvZ1eU8Sc0OVnRPQKFktK0MNVLhIKrrO2e+APCYdHc7CwoqN5
ciHPbaqGjQPrBIS7ccqJFda2euT/6OkfCDSbVcThoMO71EM2ylFCTmz6MeimBOnK4qa83po3q9Kn
9GEw+x3UIBPglUEsublg5dJw5HZwDmNGsydVz07oYhBmgQHyAduWhwjzEz5cTLYtQDS6xIZY/q0e
//+ygppAmRKd6RvDJZQ/sa2MFobCLJYHjSAmsacAs36eZN9oW6jgTlINk7ieTSC6Zm98HyqS6mEc
yLaJMf+k4b23f6CE87PEJTiobRVBoM2ZtwUavGD1Uv6Vwdj29ZpzW6yKUUw7HmfhGGPXnWgzhCuY
+JivV5BnhdnFtIkIj/d2Sbav9jHwdqktnIDr4w+ABlsJSJWSItNfn93uIr1JplVk8KT/wzEcZxkj
M1grILlWs3KLE1A9gBnCaKLmrtIzMnuT67biDDOLZZU9cnsOia246SVe4WWFdDGFV2MAHC2v63ev
chOZDoCh37OuIxb5pbcE4Re7E+FAsihmdmTzjk2e0DFvdd0VlM2eOcejHqgVpxezy3Uk2MFwOPij
ZuCdDo2aRUELYLXj2MNEW1tDacpMzibsqHxS5m2WMj+hfQRXEztbsCROl0cD5GlEhKB1iQ34JJvE
Vv8C9oyGbs/BWk/sphMvpP/j3eyzgCgSwL2QzEscNJh3CN+JbTtnwfWv3JbF38XmIdv51jk52nyK
g/OWBCzc12ASjD2ZBb3SYNPU2CNoTfk082VbwnBP1mTbbP2WUAbUtXlbRlD4McpWW5oYvUWwcQDt
nCFiIZpFCETASoQNsRwR3pOigLUtjOE3iwXuFQ7uCRhV/mKlMuvcLJda/s1h2fRCp0U1PqK38k4q
kRADDwO1zsNXr/2bEF7bhdyktjLgxE+PEOOdb1oGDtSWitUFnJR0/qzXmfpa3O4XZeat3eU5oeJt
K/RTiK4KiSRd57KTqRF4nqsV1vbSx94tQsOsP46ChokQaeoFKDVRMujEmTGdOUthvHScxLstMBVE
8fV9mgOaOqkw1quhTsuAkhrfxau6YnsL+z2iPVJCgMtJGC8ixbhlW5qMPFUnZ1QqBu0V/5VleyEY
NIxw03ANjSOejVl5GHJydwxdMGZliKfLQyoR4jV/cqvShybV3WwTbwedbLq+osMYK4deQmSmTICg
6xl5y45ggj8ciSKR2BAnDXSR1KLQVyz/5A9fYUJdLEQSXSmNAFMqV8LZg3/bYSvOGZO9/r8QPyQL
ivoYkSHV7VH4OT42PSacg7qUoRlu+pMEzFTfjqRxMZR28dIAqbbVAL+h/PgbZEvs3dxld9OZzNcp
oXLtEKESOXqSt8Lu3K4L9JoxCDEfp8uRZkpZrbPVH4Y8VUaw9LxJsT6Cabcm8ULvCliqH+1yHO6H
Rl9jL8WF62cNQxoRYuezlmiudV90UMyq/us1rcGAneCFXqOF5DPvPf6ldgSjHzCfxYbxrLV/9rIt
/3bUt5xhTEeVIi1TC4s7oxFb/PMOpLWqy702FGOlEbbcwCwarmC9cSR6W8wULFGIZ0XyJw7P1qFu
rte+5ecj41RBYDN27OxmUWVJ4ccjJDTHxd52uecwJUGpsXfxe6gVx6hNSJwTEChy/MWZ2AS/35WI
nzU1PKSnaC31G36Iw8gglU90/KvESwy3ML2vzGxNy5Vh7SfcKCWg8zf7iM6YhoN7PpH/BWY0cFkI
bTWnoKXxYNlpDt/i9+kFoNh8UiWlaEOroQcokkuob3i9al0uVchawZGtFJVctVfhlV53JjVJSg1S
sVkj5JpyygwBqtS9/WMgOz07KSKAcuAZvs8KK+mpTdo4RD+VNH7y8QghVefR74nZ+MzLezCeM9gJ
+VrffljCsDq6M6ga+55rywzq0de/8FW4KbO30b7Ld1U36PsN9VFWYyheYIT8A+RQwGz5E753r1g8
2/eFrPxbmNvsEs45138Fvt53pa4QCIxO0j004plei2xCjz+/eUVovk04+xT5hy3qE0bl+xN1qQGP
12FZAGjhQQ9tAwmjTVAP1/F1A41Q9fBM+JrzOiY87i5sdWwO6Ilrn/xvDRyAMd7PXQTq+YgLlM7x
Gi8bN6MW2T2vkr6aXa0V+6e+IBJ1cJc0eU/Vmo5E63LvNZts9G/x/6uPmuVEb7ijh+v4TCXVfzmJ
4MWdL9KcoS+3rRBN+AdWPBRbnWFRe0hCTZCzyJt2vnQvUnCwE0J3OJlCnBbV3lASrG+wgBin1ofB
fLj0+8b8zOT7fHqL9QovZwcI7sYZBIO/kKzr9PhkALlEEUpu4E+B0Sa2/8CMlPXfPYYJuUUETsFF
Ps+BDoPVWh6VZH+dtHuf6bsT+IFzCPzHG6Ri+JBUnV2g+uADAtcEqRYn3sqIMLq9RCxVxIVjEcdF
0Y/Oz5/H4n7/eeJX53spXG5MedpxJZpcnW6fJUQGIaIsitpoaaEPJODoOlY8xupgYwRz7tG+Hkas
pFxiDfHYQdNt5xSIQqPfpyVQ57bdoA6UW9Bo0VFkzxM28st3KcVPpNLENzNZmKvK+OYXRSGdcQKq
H3owHc4iHxd/DVI486ANKzOS5iPIWGcvyzKLg62t5bV29ZRc4HiCc27xAV/a33EBQMhF/m/6r4Cc
TTE4fsUOoxyyC14didlzm3F1iygQUklHZsQJEa7vFi9390wnAetAcXqdIM5BAgzEwjk8SbhNg51I
BPDOVzoSYXAIrgmEVm6gjnvc9VPDYxEIv82R5sRwuunY+OfCg5XzrTF4EE6yZtyWhv9bnaiJXIDb
1GzofcHH7INJBi7d1VA39fXYvM5UnM29lBrFYClcGNrdZcn9sXVSK6I47e4a92dUjWj29O8B11VC
P/p0GQtNyrk98vIOkVy2u/GMuTOy1JohlxUEZTM9rR9zl3bzO23ayQBPLHxpUaLwMaN3JUbRH1Df
MdOfDCf3ueBkYyl9SppPIzJnOWVc/nOneqqECp2wPHtRIhWfyA4/lWM+aFU4O/1Vf1npZySbFLtW
JhuFWrURsT9b6v6K7OEZe1c+Ev7Ga4z/B6EHbYWLVWbvgyL/VJzr8sVOYyxjVTIjHALLk3aXv8N1
hM2vldJxH310aFCPJz2Md5MDR/Mgqy8g0ChnTMFrrpau4GMOwgTM0LdPKZbfil4lU42a9fl/wuoh
hGflwWkWQk88Lt0vXh74I6s9YQiJ+nX89bnwjzf+mt7mjxnGQNfMXntsPEfX2Hn4xMQnjjeYP9vT
PoAexj4cKrICw3dhN4WHHmxawv+Mf+96/l6QCnxn3dWxshVkzHr9Hcbx3bon3M2pIp0IWO3GvIsX
dRiywEd/Wd07OvsTWfhYwTgSGqg/qq1Q08iTPIQrcamWH7UjuojIlwAvM6GCRFKaQ9ieKhIdLWcY
B+CMpb2JXCNnT6i96rdkl2L8hZkFXHYv5IGbU3a1/fgtpeL5V+y3/lXrt1XhE48ZnlvzWMU6FM12
yDK4lu6NIc3GNnFQIWD5UtQVTR6dAK11PMfb2DUroM9lx+I+yyY2rY+TyYhfaM9QZ0KiSec6r/VY
I3RFqqTD2o5oftLnoPB1pAMLfT/pye3wf4PxCcuFED3WGiKXcRWgpR0BAy/gpE7U81MlMVWVxt0P
sj+Cy2GWJQ59TioxR4/r69egUjvqxzv3jXF+n8WOnCcPyf/5iBKEX9gUs3QTAA2utRojnMAS4hWx
WzfW7t7UZ0HpoGBn6uf9PxIBNYgPGOdg9bUDTgXXe0DEB/TRpIeHlEi02UMOxWoAFSem7rAPFyhS
y+wZai2tN3NfozI3uWz5YfyqaRnN7AHezlkUVrx7qfPrqy01uzAQ9bdb6D2kr/lAq420r6f+YD2N
tbAlV0gyaTE/LgpbI1Y9T83r2gZ3wM+jPVyH8o/VTZRzCVMR2uY41gVGtlMbnkBZyFnSggwuohZd
wG/lnYOYa/PL1LUpv20IQmkJcWSU9e9YZmWuBjyU9FddNg3drpABHZ2Onx7XED912M/s3A2Z3ilt
PzF37CoGoKIQmde5tNLz9Vr16z1h9zE/viINVnXxCwpsb0k+JjEyhQtwJGaps0EGej5WdNyuXvQI
hU5xWBb0ct2HO3au4r1UlIJyu1AUmj+IfU9kjxgm9RWviWE8JjXWEum2p++3AQNqvIWYZtEksJy/
CBZZAyHou3pORCTVq6ApvxXsIj6On2CAYmT1z/wFNG11oLx8VQ0kEgNjwlzvGRKTdGiHy4nOvRb+
Nh1RwA4bYoetIHh+9aa333eRsboo/h7jRAJn9aaNGrqEvdL1FZlK6N/eggeTWwDTK2mMmFaIabPb
xSU2YHbk08iJxXfXBWMBjy/JpX8PVaTdQJWh/L6Uo3240gUMEHOdnnFqlqborVSB/OD/u3tTLJRD
Vwbixi5AEONF8uWF+EwDxEdcW1l/j6GaPHVDkMFskO07UjJaGsZBwarNS6hUDgoUw8l3FDblQTxL
advhFcq3DZQTxMntCqdVMXtcH8qB3F2mNWUkI4IM2h31yKPvhQDHSQkhv1aSZ9zta2W4q22GMwS6
UkiyYd58pvN5GNidSIrumVLQiIZRMYesAEyJH3rUq+ErEPTnZJGsxsLTndd8LZRcVGvcjJYTIlJh
HAGoYnBSAntNVqnYIYe3V4meGSJWbms/dL+FSaBnTW14vUJicU7B/1REYH37U6SePLB5LtKSm2wl
gwS+NKPAOASSxIo3w4RLHchWzoAvaTdS+RNPMuUOQ41q6HmoNjaeAeCsnrnzr+yUKg8Y6feQfMRq
vhPJ05z2uwxIiG+IAnnF/ormWE7Bt8TXij4BSw+knUkm1fJ/ZE2wq8o8FB34HuXquhame4f7LwQ+
kk3VFZYZrg6JVuXSpDQUjAbJfk28OytJgN7MMhIyxHCJ3ApilWmtoms5rRWZrpHNYprEGwoaTppH
+75Wtd59ZPy67SQvAFgJ6/4yS1v/IocmLB+TJ675pZkM9nqNwVP2tH4PBztWktCZ75vcyIxH0Ya6
YZY3bYU9iy0FLguC3YPlBO6Ov0e/e0DjvWxcuzZEbyEjvGJ8pNhL1OCM+ROptosmeE7h7m97Xhhr
eWYj3R+3cvgTuq384C5XfE50DD1SGqayqyq2locdZg6FuOUJNZCB0om4NGY/9KJYgmE+wZB77l1c
4zoFOcGd+S7KGwgW8z/0ilpKF0OWA4+xmcBRZ6OTfRd0/A+0zyl+kL3lZ99doF9mTBr4s4XVZt+p
vT4beshl6ww9QKamJDNGl9leI1NvMDcRWCHeO+1OqnoJFok75eYAY5XFhIRLL85bUGKAHnGOJQLL
svi99CKVzzvmahp3cLXKQdKxO+3udSXarJ5wz/a/7W5hUCowbsWlsc22I9hcOUceduAtvF86KGXp
GYk0l8g6ODfV9QMROFycg/xqNe3ukgGuvvw7P8we8cl2S4Bx8GKJyK2bBqM79c4i8QKX8sEvRvqM
wXs7qWFRaSJhn2TwuyttfheyOZ/oQmCS9sVZqyx8O5ItQRvgoEc4K703ctuBPPq6ouzjlzloxC2w
B/OStInnAclFyZRdvgpz50rn5eCXiF5j/AGBJ1FFG0jshcwtwVVXZ2YEtl8yiuWyc2boWXgO2F2Q
/tn0P5VJFfNs0oZib2WlysUPrpGOQ2PqWRmKEbkdabAYsunL03P7jyBvdEw22cvH0TunhRsGGdx8
llYwL+iw0kS7pqdnTQwOu5rSChvdNwRUZGndb1y7d7jQKJbbUS54vyKuow6g/AEjsoFoLeAs35EE
fXCljRNG32vc9FWfAwLspDo4jhBwf+VlNJiTcIrz1gUZFt0VdkaGrMuBfgGOSAZ6FXlI3JeUWnMY
CLsGyHM4P1UccMN0HiS/3nOxEFaiei3owz112u6dhEBjy0FDoruUB+I7qQWgiylxKgwHeQSRJgW4
U1lI+sKfpMA/vmYU1K1A/lG+N79youkqIIY6IFq49C6o/FsoZB76Q3zHqS6zcGPrZiZX1nPNDXKs
jTkeSbxVDX7jNyH7QoKnvzWmk58qqLR5ish1ENidEJsFP0w3uvTLmtHcrifKtOpw9AE4+vZA8BmI
IBzJHdgN0n80iYdyocXBqCGWg3xGuroqtqwm/9UfK9xO8w9JXcbsyYN2Wvidwsxl/ufQtfaj8yPg
QP7Rq/HhEqhSnUclXbInD2zFbY2brb6g85sYRati3wutNKyenp/3RD2ENMZYqaX4OLUvTr8OXo3s
FngrGNxZUg/kTp/NWeHmGTvIhmhDvkt+xOw34TrlQ9DBHaR4h0+N1rFzmgT9Djb87cXEAtqUCf2O
Tjkr2O5vopPkkAhhMr8x4K7tXfv3yprh+h1qAYEXQqitk387WxOAuXOCKo4w34lMHCbj7FcN8DRq
34nkgPymDHALbCL0MNhmrP+juObR9vATFUMI9FGBVbYqaTyIelQmd/RjfKw8MqcSpqvUQpSGdm/Q
LFmZFR6rKpO414OD22wP9qIk5lApfC5HgvBe91aVWH/sPylHeugiG5f2zZcRGW3ClvUmg0BtRbM1
2N30hSsqVfXI7rilpQ3vaQJDd0JbXm5cFSipOTs2MoBjLm1LiydRlmxVCxwhF7WoF8XZNq8kcqiD
HMbFPCLxbX8zCLQJPTdZTr0i4MGfkU6vyiEksYuozDPx7WYuTR+aiazK22dTK43pA3xr4NR9Vb/B
q28vYjogyVFQHHBqWlqHKRgAHuD3l9+Ci/XEEeNGnQ9AHxzkiIqxfXejiuqWe3PL0FYkwP43E23r
ggjsJfIc93l1MCBfPiFCc76wxTALbNzn1QuaBDbYDU0m6c9/0dzniI15hJ/fXiOTVwI9S9C8ikhc
oGv6moLvbv/Lm+/5avbJ5r0lE4pw8qjnC4CbafuXAi7bHenonFAkjii+YbODGHyhapQPg+z69PYw
Tj6WOKzE1QEyoVcmn9b2uDtQPohlPyUuP5e/9l/E3PvY6AnmZ8Xu0tHNtv7GVzrjQ9lcPWUVjpm6
15W/EJsEs/5FOoiUSnYnbs8d74yRjfVFfPIfaCp0JwUPdImYb8WtIa1wnBUS/JgajJad6BsNXO1b
f4omnEBmHunu5GxzMdzAgPfv7gtyhAfEkXNKBwE7uoNgXgNhkhsVwrc19Q+trvJ4PwtxKWOwRuB4
CogMsOLKSr71e5NxHIaCz9vJnKvGJsjgKg+o2jJrMMDpL7yKXvqXs5/SzuzahywpoZzscRcqDS+7
qQido9yCeOPwjfW+r1lMuHw/ScECn8ELSMO6bTBA3jUs5gB/bq0w4+xBRN5gWBjNseEGqn55nHjn
4MVDifffX+rDTlpmj/GMkTWeYApZVPOmnwVWfsN+ubL95//RhAvnDokTKsRVmSR7yFD/kTb+09CU
yOpE3FE3n1RvyN8sGSL9rxPbQwOhwojYwV+SChXRZ/dUDXTewgUfyXtWxyrbBAhfzSPEWD6nubv/
Bi5qqj9umY6XWovDxYj2G5RjU2H9liGn6jg0PqeqVc+6Yu29R/XgXI06TpAfJM3Dv4u/d+AkuHpb
SmDQ1eQWuMIfdT/YG1hOG22LegD2RgBXDMXH0CgWtaltnbgZs4ejcRmzeNpW/+mgixqg6eRkVhXG
4wcnvLQECMGmNX2yC1TCqhqx7JtRA5z6JgW1LDDBkXZfxcLaitJkPT0DPqxw8vClaI2gyIP2zA7f
MDghDLxgzViDXUc1LLUMwiLaXHH36h53xSLx/U8W3/LaYVQrDAW/Utu5E2zxl9DryrB2SYqfzD50
pYCvLDqSyu7mS6f86hbmQ2x3XCpJkYRwx1PAB8QEuJhe4PP/01LDfalCUXr/VRSZHvq/HoBIuJ8I
XA8alusRUOaCZmkIIkjrH+GdAdr4vKhD12d5/bYw7NXx3+x3QH0UNSQntiB+V8Cjb/N1A4tBOLkL
ta/r9cIZAQ0r5GU7koEWfLbFZDJWLb+gHL47QzpKVAB+vqiK4mvOpjqmgU72vYXK3KQRpWFzleGE
+5SsiqWBWLvbESVhf7wIT9TXZB9eQoHAITUvmQmaXuKSmNaa0+TP1wWOSmt/qZwA05p8be7IXh+5
L3mCbBg9QdXaZeDxcI3iC381UEeWUXTzn5a8LSkAyBUbHSIAkQ5Qsg3VZdUgxUFN0s769YevIYFn
JAfG6nxOfa0eD+/8U1FuC2pk+A/Pvg0vn2Z0nOtP01lyRqcRklYBqyqginrGrfHuFaJKVx8YrZt3
W7BwPRu5G2vovQU406IZsG9+XLN2DPYUk1ssbotS875JQiVqVH1BHYC5A/9FU/scty0Xs5tShoqj
BLFfMW6ImWMyoG3mXNVh3vERYOIFJeSKbLhx+C1AyaRQGCFYW9MaCEatg4WH0lyaQmT4IIcMEg42
q9tWVyM1yPvSWJCzOqB7lFwlh13uOXbU82X5j4KWKWr+HQrUGblqoNSa9d5MX54QV1xCxMiq/0ha
u6q6x8WZyFgJP9XOmpQvHk/7IBCxbYA56nTFLVU+RdCH1USdAw/4zCs7eP7aMAjNpNXJby/u1qac
onSIVvcEU07Ym+clgXO+jbdZzYU3AbxOYLfKqYye+o8v1fSxRBgnwq4pISuzkwLJ8wigWlmrDZM/
fX1lD3ASgnH3kah+efAZkBQbM6mfvFYd8UROlRY40u1D4SKAHr5QEF2DFA/x2Gms3q5q9mC7DcKj
Ed1/MvfxZnGMytM4cKn6CLgFhYchXk5vwpD9o/CV9ElPZEm/klwGc5A1I7zq0ClfuspX3Du1Go1h
Kg9J18aeroc7l1RL5DysLeBRfAilaP9Bb2PotEnrpHOUg95dWsqf28cBTH1TKXupcAkAFGhCbt/X
M1VqCmhttBxlaYm7r+JxdYNPs7Shb1GuJ2qwfwzxljMN3SYUgiIljkDHIwf3IMGScUAS5koj5E/o
It0Mj7qc/cf/wS1hBiMq7GK9I4D+KWdytDol8Cq8IkVKUCc+qsnxza8OI22NJT1c0GbUHOSwKTgF
yZy8GpTtzxDWjbo8cM/kh477blDmaLePsu8/c8WcajKCGQv05VgmQbCJhq6/55xuXcPua7U2KoL2
w/Z9ccgcPTTSpGwdPNHWy3Ig4nbZV2aFLJN+GTQUrMchyD6NT5Afuiv0gWMjiBb8pPMGenmfuJv8
cWZFypBZLOmlVGQqZS7RXkOx5JRHEtYbUF0Q7++rISZ0MDtG83+1z6madoF/jDdtrasETn4p2Qz3
53kJ2CFB5a3i5NIwr0v/gzNmk8ZOHiyuXVzX25Y0x9b9YTDmn8ksM7zi5JP2fD7HisLGkGhgzdtL
030Vefi+4sajB2+76RsfL7DNz8h8qVnhFEr5DkIcqNSLplgoXlx+ATPZhBw7ysBVr5hl5+gg7xgc
F9UIO5ukjSgcn2q32bGjw6/qwANBaoatxZ+ajVsgqzGdvOQ1fCO0eUK1om/V1oJqqxzF3uwXAb6D
or7I16kT3J53hjGWdTLWPaVxdYdzViMiRM9NKMGmdE4OzfsEK1UW/o8efnEVmcxVWokXSlSnf/NT
pHdrB44xsg+HJzaa3+PsBi+waM4nuC9xGQnBlQDMUTKX7cQ05da9gBdeZ7PJnBNAO1BD3Vv1KPHk
oJH/8T4ylPsV6gu2K+bGezjdb+/H2kfJIs2/OsK7HyBJfcqnrJ+gKUpflK4LWvJ4cZ/u2ll+7zYt
YMn6HOkEjQQsUhcdZ1cqpkdiaEKQSmDHsd9V58tEiQAn9Ncj9uGC21Ie4EcBUuHnLivki3ic6rfy
tuVoeoBn178COMzSXDtAtfyHTEAuY2yJac0xfcBOjvojipAGR1j1QZspo+524G/DcWLkIIUc66/U
z4C0BE+omvysDjlBpvm5Ym1g0Xy0I/IXAC5PB4xQswi8EujYmg==
`protect end_protected
| mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/wr_pf_sshft.vhd | 19 | 20160 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YdpNuWNv5ANxG6sesr+pii9y21Kx+NVDp0WoJ8gKKxKHNSppxy07GkwBsVP2aDgHIw9l2ULLZTNZ
WthaAb5amQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kEIsWLqGmgOl8w9T2kPb2uPP5XenCQ9kpxljFoCEGisg/vUEuVE5EQlDS3+mxviS53p6zH5m8hA5
bszDfKwHD76EbEoDDpJWL09MvEqH4hbAV7G0A9Qe7ZciYDi8os/DYZvhR8zjbLils1MINgQgL32T
+DXtGPXNuzJTAMDKzws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NxGGOrhc83L0V7+Qmwb6+Gi21+qsbQ+hA/5/9jysqY4QYAqiXfCrWB3N0NrVsGWuuTvZXoFNcxot
Izvlkgh5KOucyz0ezFvnhsYziU+FkvqQYf1g82Syrsz8zvyVWXqii6aXcF/WSMwXtiDjm4MiGpFm
yTcu8CcJgBMXYGVZx6nj+IgO08YgHCC4sfTqmgIgkxkmBrOsiH76g2hPxvXPgVWaBlJF0bS/hLIS
Glmsy0cU+pqQlcfbTEV79W+sXQ5Q3KPQFXj7AhMrHHD9esRm2Isg/tuzcRVk1cq3LsMUN//vGrfM
OKoYOozZxl1/IflxrtIzbjclaBUaFr5bvZYMTQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
dIJ+Oh/ID0KokdCrmxnp1QfFJ5QZBtIG4FQx5Pan4DTwhUxDWY/BQobSBBDXzWh1TT07UPg0V7Ui
zobKMfHgBNkMD8/PoD0AIDWLDLeXLvIJje8mGtE07uncec5mJ2eGa/WSy5sFj4M/Vdtk7C/Ab9LC
9qAaWZZ72ZUoEHuysZg=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
VglxNkzPd+guDL8DGRWVtgWGTdJbzbKKn0hBXJRIK4IuLrtOeezNwjLTIb0FIMSJGqYYwUrPN3z3
TVnjDJDaG+HA47egpMvivRkbnfO2/EAJtU7n0hK18OztWFzW+yXOUsOuQnFS20EGjEAN6HCMCAXS
ralqFAJsvMtY2y3dJNuE6ytT3WYkXmZUpTrJPPJOu2l9mCOnHkBU0dRG7RNYXf1tEMPaZrHSYyvp
XKWW5CTowIM6jJQxDVSVfwprGmWFUVJFtAmp+65D3ADXiHMcwre5cI/ty7nYS3euq41mrkrZyEF4
iH4/gU0xN9mM3aF9hBPzu3xQrdML35ONnUZTzw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13184)
`protect data_block
4EcGi+I9uDBqUSattxTQKwAQGdhGAEtr1/eJ8OL5AsVmCd5EltTDJEmL7/IPTETIu8mU+GNOOhu2
LJOtTFmvNo/itTBifA1YH9tRr0aZn/HO17uzdnUDfyLoFjA16ICglRMMIRMG30hdns2uzlILoQjR
wPJZEvfg7NHOgHqXh7nEF504wuABjiXjvxD2FGWm1WchsHZC+WmajMCtN9h8PV1g6I/25OL+dDQV
hlY0knO9sPHQhZoh0mXCMli4Taku4EBb1DyqZjCU6ffy5tgcVX5jPPrc6Z18Tz1QUTmxzmS1nNCi
mdvxhyVoHzghvdrIK89q8a0A3smTUp12z/lkdhwyiIq5lrheaBYbxbtJRbdlaS5ox/n+HU9BAOxh
OPZ9UyB8esiquBz03no+GZIeyaUNePDm1wS2osSgVI19SKGOuJVS9AtSfgZaKQF8WC9R2MWxrt5u
sxfLT4lB/yNa7GOXuGE29sXBK7XxrBiqU7FZ3yyHrrhSOwlQhKiz8/1+u0fp0AqwMxjRY7kdxOnf
b63Xe/ittLXUs8QJdpINWjiKAhty+yel3ovMnXvOodS95Isx9w3o6k/zm9rz0pbXXDnkLGuvSnRw
CQUY2UWx1C5ow3zq2+P1jbyXXO9lXIZFzuQCacqtAuN3FElSpyq5+X8uy5zoIcE3gHUk1VMuPMue
OVj8PXh46ZNcOJZKWbPwpfwlXsfNi03fv3FZoqMSOcTgOQedKETXT5ZujTcfiGexzXV7TvKCtaeg
/uvZIleZovXC9c8C2rVPEjsEZXtXt2d8uEHajypGT6jKdNhHSxRkh/H3ujGXn0sT7vzuK41vrj3i
bcygYfyENPzLNr1o9ncZder7vmXjKlGuF/lXkf8pPoMHH32RxMNIF7/nKrjwExipMnomJpc+RLts
6jJ1MVUbqxi6jsK55oSoEEhvp6SqP/IuufD0AlKSDybfJD1u71rEqMQ8DQOrQKlaimmP50gJ6mzB
tTqbUvl6WlZKyk2+xq46KOKYeTyfSn5QNw2ctfHWx0hK+digWvQIXYr7syclrysp1ypo+BTwyV+I
8pWtu7mPVh8ogqIT53ur+oZ1z7oFMNAbmO6WfBHrq6KShp6UTWPVaz+4CQtDaJYoQPh9ia2Uu57j
K4YccLgBhmbiztH29U3AyoP4A0KiTtNPZPNtxiDBTPF9T8rnu0+s9q0MEpY4dBN5Y7bNFSUbkvwa
OugzPcy/Ay3yipWExu3P6uSGc8h0cE3cVE0stu8zHZ4KCVaQ6rkzX1O6CAZ0eWzgkPH14AJIlWo2
X/2+9LJz7qvA3FR/wQmx9/3MWv9tGLjzIS6BJwDS5nf7QFSh2ch/esC847sLVeS9WrQnJN8rRcJo
vQ85POYFBwR/pUZzrBxBal8SufZzrdSRb9Ur/Ms/Rvd4BNfHe7ChnG8RYavUKn8tovAvNVHqkOmW
39+xCFHke7uvdOzi08rFcEq4hzbha4eWXJPJZ20brNPne3NgFWhehM+wdefhmTM/rbTHR5deD1oq
y5j514b7pCtK61QFKevOjx30vWyfqgaiDyplLwhX2sKUKNBjD9Ch6FJBA3YB51tHnzoyPMEENeUE
+gGYwGmcYOnJW0nujBuvBHqMVex/OqR3z/bWFaZzxEk1HCuSf+qmpOp4d6Xb1Qx0w0w/VfBO5mY4
ox1EyGara3m+T8dFSB8cGgmJ0v7E1neZv3Pl+3I4G8xvRgtVtvuQJC1+OvSF2xfc37wUqryU2rkI
aQsVmjOVaPXbv3ga39qZ5Z5moZlAz1JKsKEi1IP3u6bTEefwWY8G8IOSKb52cqD/KaFbW9m1xWXS
3Tspfk2PRczf4RU4XCtBCfszwewITB8rzBrUZVeNqqwwIXx56fRadzCv17teLvaMGNRIz/9kirgs
ehagNrskDDupY4sRMwrlNLzUvlphgRTLRyvn9BP7lxBnTh4EeK35ZafjJ4tHuRDG3LQR1H8yQGIs
Msp83J/7pCuvT1vqDuNO3EZ7rEJiVtyUpoUouC8sXgCs3ZeBFxq8q5iJi/hbsIw3GKiGmMC8hkTP
ySqdU2dOZto9CXh1pg6r+KNzbBjJBYfePvVehvfeQiN4XGXhjrNxbb3CEFHdswT+gUuHVO9jsbej
Rizvx9O8pW+osrCFl3vNoYGjgPYT5By9vd7WOoWyTLcZzuEJFeeEO2mci42xdxS18z7dwzazdmN0
L7tRSEd5UIRPLeJ8NofWQJovlMDC0djykut1Dsp0XggHIEjqrz/k3jTBeBRVhNeO7FpiAu0FEaoz
wpHjrF/MiTFBPGIgni29fw3ACncIE/Te/snZnmjlxt+uJJAdKHDncCuTvCWF7HCVe16DsGJYaKpU
m4GzYiVeXfkkEPaLRwmPSyTKdrVybgTpBBUhkj8tYIDcQ4LqmjkkcCrpjTAu++kzP9tNssKd7BIU
ti1Zfh01qQ6ugT5kyADGxqW5hPUaQ4b0HoK1WC1WtnIRRRksyVBQTm4bnRbcr8HmH04b9NVynB6b
PN62xJ8qNQxn4qotYmNZJ/y5odrrAqR44vH9LzSLbN4ysx1KGRbPxseJMzpROZGrMoKhAvODw77p
jKZ4PiogGfKHXh5rEgE6ugyF4Nc/xHv/oUnFN8Owu3QQrwuZgZGNfb1+VkCeZqL/tLhiboZagF1P
7mX3l7v9L8hbHhVAwb3LeAAey0cPvOfpmeHHEuC+IjZZQd66NGQ8LhAmO3RkGEYnUk54WcC8scQC
97WP9zHHUsN74BbrPs9daX9Wd/YZFaizq9qgVhNDfT/4CR/RHGU7IOHZF5AIshp7ay1ZDPAzGCbH
L6Zl/8aZy2vbFmQC8sK0mL2EX284jcF+ejRTfoF4rMGxJ9uda6TkvAFVHOizDe7rZlU9P6ngfcor
oyIc2DosvfheFJuHaI9EXJf5gRUnsdP7t+ZVZxS7rbCy+CMFHvlVtch16cGb/ea7CCIuvDpEHQlx
WNwOMjw5MUIGcqsd19lsZKDdLoZwE2FWO3MzRq+KCI8TRiLqFNzcJ9lENnF8WuWkgdAI7tbkF4sU
3SG8qattjrD3mhWxFx0oX8NraF72cqSSr32CgT5gL3c12x7vCVgLnY0BRCcFL3TbO+DL46tVgfkL
CNp1RxU+nnL22TPBV+OB0tyHf2bQugkf6212Cv6njz7Jc7EuMf5LZdXjbIsDdKnDwnAEKzLUO5fD
XeE/Ba6QrerO7fVZrvi+qNaEpwgMsHoKg/eoKYBTpBJ1jKEyOctuBlrGuDwjoBlZg7J5JtBVRJXJ
ikdzJAKepAzJdhZ9FjayIUzOL+Les7rRK0g6WXVl3lvsLEihBeFHZT4ts++CgqKWalUKtg6bBzN4
AHGXHAx4Kr7N410001RHLc2dG0PPLENd2OZRHM/ClGzLZA08nYo1BkTthel01S506YAYasfEY8Av
fo0LnAkO+wwzSPPAN+QBNNSmnD0pCcuggsZ65uKUYfXBJYo7a/U4f59PoWZkQsmMslheblgU85SZ
QH6GBpkKfLpQQTTnnbULczL2KyXa5t2Er7MVJbq7TTq0zS1xxzw8j3IAB9Ma30iKZPLLJDU0azxc
dTJNAwsQ8rrNT2SSM7cbuf717l/33suq3Xq/aYCqxVrMcayRvV7yVsudpUP/itan/iWjqJuAwUP8
YyyzuIeQKVT8dk3aA2w5/56r4ZJfiLcdZmyiKFITEw/sXnHSY7E0dPZKmVGg4qgBKk9ZmNzydG/4
AfemVZMJRAp2oorl/vBe/NAVVcpmLhiCGxEQWYPwdXgwAtY7s/UpdQuoue5Owsj1SmUGJrvkv6lX
vdIPSdXV2L5+hOkkq0O/lbdA8l1/IkrlJGuw7dl+JbVR8zVh1s5UfUe2BKrWkIWCx2AZNrNKHu7w
fq6nfxGZMwICsGfx+Nfnqm9OSZPrjQIGM17STSiM7J6jKWtRkF07K07fEgo1Mb5g5JZCOukrlWCZ
lSZBZxQJ1b9FrmqEsaNi05azsrTaEaKZElX6EGz2ZTBJQkEp+x6BwFZZ1/kd7DX2y4xYL5UMggcA
jGKgSB0kfMJxG72Krw63Lm1pAUVRvy/Nd+CD2u1wfcU1A02VBUJt2w+WJ3TvXdHw6x8N01LOPf7k
favkLWjng2RgkFrVRBisKI4RBS+NGngKr+Ww0Y022avy+xILty5W8iFOmbELD7m8tuzCstjh/9My
D3YdDxWikvTe5XURjFlc4xbNpY03RZrOcA0EawSthAR1jyEnKru2lpMTUMlLI6bcrQurZHevTcIZ
nMe1TUL0K5/mOYao5mwIVgJc7WVUjrtWGyWg8ROXRlxMzxgjhvYfpHiEJtCC/Q1joe99x84jmrEs
6tsAC0ZSvAGdXTcHsLInnsyFxL3ggMWLWEf8XvAhMYokGav3AnYbwLUoUFIa/AS4FYaXB8fD6y6L
dyaUAnDqgaLmRLyDQE5O2HsSLo50e67Xe4pvHjCnZLL9rTES6OWj0wIl8xVFVS1DMFbrC7Cu2I2n
NmIDSAEJ0W5FtIwJtvSGp9O10MyXRqzH/o2+xpK5/eWVarHjqT7ZnNcQbFVC5tcrQWTu/7gDMWVF
HHO6SDT37gZQsOUJRZBi5owcj+JZIg9bnMeG4h2w0aIdnW+g4aKCuTpSvUDYz2JhQ0EmjyaPXM2G
r5vQV6bv6v9g+1zE2Tqm5/jNapToc1F0tTw8Zhva90ukcrVeeB3mYBJJ431jtDW4aFnFw2Oqh8Pd
uipgdimK7X5W3m4iqj5H09FT+q8IV0ebihJ0sw9BDoauG6zAk+08qOyfVjGhvFqsMELn/G0InaeN
RRk+TmdJtn4fUYn9ZKvScaAhVBJRIudVwLqycPOvHJgssYQ4tJgeO/s/N4uSDs9pRfq2juA3pSLR
V+BF8zY2nGiLv0ey63D+RTK7GW56fjDwBfjiAB2fyJpyq1og6VDu5ZG2/4qaZz3EqlA+MJpQogWx
itejs0nbimPZOai9mKl7iFfUUgsmF2Kp+VGJZT0/UeLf/6I5l1c9QO6YZJfL2gCWhC+JbYfNll8V
xoIvfjTfOMc+118Zv7IFJPiytQn/70uyIYuM5Y24M65Oc06w8+upDBlSRuGQsQ8NURyfIt/yhXII
DdO3cmGq9Y6j23XrH7cOSx/xrYR2zMo9oZJPdwI2SbTse8gJYRmYYuLzYwHSXdJa03iSMXx/nZxa
VzigqlhAcHYpgyjeGuN13ZYvTPXmN72HgwaygkyNZTxxhhc65QCzx65LALnYh/BV1Ah3S2UxzQ49
tA6XnM7DffK35bl+bBVSdUrOqper70CteDxToEfcbdXBfCls53TUU5QCWPRyVAHLXwz4XH08lg5X
GTYXrQ8/Ed5G1rHau8CTDyxOAv6Sz6yP9QvfOmaok/97MwMoFzKsMobg2hNowdLlSeFpcjarei+1
hUoqqIjqGYFAh7rpxkfQxIQzwHkX9sUX2PPbNAV/OC2B/pOUp5EEilut6+1YFyDowN6hyMpFO9mc
a677IzYBxd3/OBoGPiNVm8oKH0flVaDz0VoBsx8pKj6qpUzA4MMorrjtLKLxuDaMdrCZErPTmdoc
HTNJIZ33JOI5AOJAqQsWaVHqz+kjwerHecrlsZkqwThiMhs442bcZnSS2mmye9Ir7eJQcHL9i+Sg
MiaVJDbEWJ0ttHLvBn97x3e4qFheOb4xgVy48hEz+av/Da1wqf4RPDZH9qShEXjFw7x0iQ1VnvFf
lddPnc2u4wAQL4s0n10v5qJVvgBcidfZxYJLcS1GUZieCBemLARD5eTbZxjrbFkUkPCn5CB4wPRR
qCEDTVKhn3Rbzqwac+e7r2XZfodl0lxzv5TD9/cEBjUpwF/4MN3RaXHkm7H8pg3Qmabr1fj/zT8B
pkAvfTlc+V2BgxZWEkEFmpIFPx3uuqWB+TAdddQUh3mEIRH5ZQ3Ntgk2QUC6eHka9fCOxTj0RZaJ
8Jd0ahPnukQAVxAE5Hb/zb38RZihQLdwd/mN/6iF3IMOL7EDkCwtLLsdBjQ+QVmz46VmlSlbpfwN
O+/jBkB+F0dfRDeaEvGRhYscvZcG/zIrYlbN2s8LxhAf6123QAcZHub7i+NIl2e/GoWm47ntF/vM
WMHRfAxMjMDw+Ggo9FKBEan2753JbVpYePj2o3BQb4IUfK0c5HCzOf3zkNjlOvQbKOSYhmbnFO9x
2Iaao7ZXJe/FbfytIzG6M3rsfZXhHm+adKAFS4xqZjZiX3/WBcQkEe8Yg2+TREgjVOfJD098DR5c
/lbJgOM5+EkzLNyy/IoXTZpWVz9RA82HgXxqbDFW37ue3bEXx6YF3Kn11SV4OK7+pu68pYbcBzGo
dwTl4XHIMsSZbDZVzmV0DBjUZ8h/6px6u2IqUemMynA07qyXmCDYXTe9jEpxGsQ0we0Wf0+BUQkX
po3urt2Cie1Weby6Odgw1P2Y4slmRFd3v63KMTvQwS1wydvA76bN4VIlOMYuMk6T8b+b9lXJrLiF
RVvALmZ7w4PlQYpEtM3KKHxibPkwQZgWb/EYo1LBCt12GguqsavhEbZE7TP6YLBE/Y855yKyWkYX
Vf6DKVtVkUvoMViCPEWgTNTuog+Mf8PwyMQbSpD1FA3AmkkTxbkIZ1lGjhy19cq1RNjIPGsYWUCA
oc2fTQv8dpu9Yufus/zgiGJRKqpP0Sikek1nj9R/JfxPI8FYQSCoL65kFVi4oF4YYBGVbT6r4En3
6c5yIaEzp6Ph3RS/DRDzdOS7lsBDR/rL/QbI+SZQVoRvf+nmPFSKYZLnjHKK89pJXTCvgn0L/V5b
yJ/Bw5rHpiwAPo3sEUwB+5ao6zZx9L22EWuUn2uqmSuO6D7TYBMp3BFtd+IA4c5+vIbNunFh+Uyo
hu/6uGYMg+V1qM021VGIeGwCv9BwzoN/gB2gv56/Dau3TCG8x6CXB3Iye93If0Al/y/PlklYfbGP
lR8mG1ZsiolgMf/t4rwzVbb+KR3v8DD8OiCOfQvGVaWv3hVHCVaEEC0WivW7YZXBroykFxRCQG9a
5+5iVUbUiZ6L2HKzHjlSZwCkIzeNhnzpWewS2X5cVF8lQhglTAwhKZzdsLIEj+2l4eIdLUpT1MCJ
6EuzMTUf/WKH0chqKtwZWAUABOYA88u7aHOPbjoOzhBXRJDfhUcTZrgJ7nt/dvgUzIADMsGzOyGO
EIoUrjEDtGgUyfdhXBEnAdNKFxNI7nlhfy4VhypWcZ1qxIUxNQwwWfJ+Y0Tuma6Vjfz5dz1kSPtZ
C4TjTyCsFSFtIqPEsoE+oTsqL8jFqpbj7ULi2xJH13OZOoH4KQzepE7XyWpYIwqCmXZlRsXtOwtt
8TAIa/g4Q3uixDU9E/+6BSmHnsEJzz+ASjVJ2TqRq76vP+YlRINNBm9p2NfMvoHgkjdC1DjVPDvX
pvRat2CR3sBB3FZYSuCWmjL0IMkczkGRb+rysnXqCb/uhlDF5/jDV59fgnWCEV95ME3gHojT4QZT
nMFtROUrkUcG3U2nyP3Lp6e2jLG4bVcfNImiUZrZk4+8/4wuHEABYwG47DSGGa0yHWf6+SzN8RE+
mqDLWY/xwQvR5zhKCjMfC2l4nRR9Mgv1O0DjYHntLCjpo/xAo0PU2CcOnz9h8C4WOgbmsxfjYxKp
zx1JCK6DDqkvNlEyBkrnJK0q8aRSlK5uVaFYPsrvdlRJCa7VNhOMhaHi8SPNVWGJbIUtMhYjuVJK
HosMt5HkVYhkUuO53dKRsA4x/nQT4dLuezOfVWevMgCnKLEfBykQEi75Dw8COMdn0MfAAkh5iInI
xjmT7MOk5hXSLsi9wVl1NlJtGIU4YxH0PwRx1xw9hHm0nfnjR3l13b3BWrhjqHpTVOT82Vklhcvf
queIdUTFTplY2ZA9xsjXc7E7ApItDsz3ysB2ytG+IC8WJ3BA848UwvEmjkgxVev3satSXtqdGcn9
pll04wmd7HgoztJKU53wn2t+EkVaM9JuS6JeV7payAMQdbGPRm+zQYOB7bNG20obCHJogFlX98z/
wNB5uxoP187Rza5ae9UH65GX6VbLnEXGw2+6LpUG+hfeigQuiozHj2rP4SbNZlNBQs1W5lWQxKfJ
HMJ6MQ0P2MAFuNHxQN2hhPfwJslAvPZjw3J4Ms45FloU4pStm1krb1B7v5SZAkmMy5440s5fi76G
wlT86dmenJpJtpyotCATz3P68mtD/DK9/WF+MSSyF71btL6t2xAflLX6DTk6PjItiNOJxeKzmfhG
VLFzVqs55hZm+N2b8nTwMctNvQP/H9n4bvHmHr5eMB5vcL2CsQba5ygi+uS3xfj5DNrSmcSXc98j
N7NZPuZ9xjpxbX1PJYhgEu95ZxDE5rbx/f6q8uRAeW4lnu6kz8pKfYYLwgY5CpZfQsfUa+SKkYXg
cxOTbdzWDYKGfv2XE0kOwPoU5dUDAdf4uN6/5NCH1SJQngsTYfABtAgF2aIgllV+dQnvetm6JYAC
smTtjudlPYbzsHGu8vVfQojX95krEprHTA5/H/cc+nTOBLbr0sYUCtlyrgrmCBPtztnnjYW3xT5L
9xdH7TgNovfQpCfavsW8zfmycUKDq6rfIfuT8nt6EPwNjEdyO5QTxMJLNQZjV2uOjnkztNREb7PG
uMZ1KvJrXx8bfa6GhIS2XNRYP5gY1i8gPUZ4TVZdD0gETs4No29tdWjZMWqdU+KNKcSUCs8QPUhE
1tnIPABBBik5d0wOWEw8kn7y+EGei6jjqViP3xeDrjvEfeE6P65ux90P8WK5/tvwD72wc7YA4bQV
tbCZzTejk07gR0stOneTFVs+Obkw/B00eQf2T3MD46OkiZr0i95NFxOphBi/byVQHi85Nv0GLU2Q
q2RNLrJm8vp1hVFw4eMQn9pj4WqlVuOeHtKvEzrOM1WE15RsnWJcI+kxpMMxx9ZvqAevKeJBA501
8UobKte5QPB+aI2MFHThkrnaIuf3/2NIX9rGbXoip4NrH5ahnpLYWSiXHpEcQbtBz8/W9U8tAukp
JWu9B5OYK/OAkeG6K225GsTg1Z5uOvf31VW575Rl6oebX3QjxcUit5w764WLTv6Bdi19yFeoUliZ
bCR+2SF0Tu9UEUz9KfjfGdHwuQO5Z1jKqETkWxEQUCjYMKNOoJRxjOGzs3P2JT0XxsCvxEvGyEH/
muhe46K7fI8QzWA8Q5d57/TVhX7WqcW7pd0WENBF0C3BBLs1BVgEWoh9K2gx2rF1v4dw7g9hgNlm
gp8jdgQeH4pfv9TCIkjlqjF/0BN2Dpuk9MzIlCeEcMYUlQm2xiD9bq/nRMcfjItsQ3Th36QIcDXd
sx3RSNL0J4ymLvk17/IuD7YYQR7yZwdNSCZl2shBUeyXM0H7ErEankcVFX+nktu4Og+4S5pWL2vZ
D7vC9wQVQBaaZjY/cJ3+2A8RVs/0CV3Oq4KQFnjPEj28yYozVxctGkyNL1RPMVrrGpcB2zrIG8w9
dQ/X3fcOPbLP/oNTnzSdVKrvlgE0wQCKM/mjG73U6V9oiatSwsWO1xX716tcUvZz443yaojcrTBa
gx956tTmtsscFNQTcUBkquCW0CB+qu4JxbAdKW6Ee3TPcMwAo3mUtbC/jaQJfaG4uelx3ZfJSbrz
x8UclhQrkU5mmjrDJgHWLpdTb5n6tmHYM2VfK0ShWUEW1kYpDa8vSFXQgbbVJmDndKgK0RYEStck
4pKDKDnQkujoHHNORrYPTc/v+jn99keTsmWirZvfYhPkI6TTtt0BIm1rRaUwFRYJZTMFP5wNXWju
lHhEFigCb8ZokUNNlbQBRsV8dWPskSLfx+Z9iHJ3oLYqcpIq2QKQRJuo/J4yXE2JdfHMlknRm+m1
/+DxeCyip8Am7cq5TsekoVGUiqCdt7qerYP/cM+kMEx2B829k/KIuziEYEJQHc6bcBU0yNuN1jpx
lNyRlXD3NybYmJob/7z5TSfcchdOsoSFBlWP4aHi6H6cStmrLZvxnHKR0HYoO3InYkJhUprx/ZOT
lCmMnCcqRGMP2zrn9I4k+EZ2yhpTEO2swIIFWtP/kzDBVBYjtZge676opJcvXz/6txDY4VxOYK+1
nUYA6gqXvPFK0pEaUVx20natVbRkVab6povbsvrwnyYTYH2ux1+6Y5WK+Hw1fBH3j4qTJgH2U0zK
TkDTWilko8IUv/5asxUaj9IJhOQ0foORKV25P1XRl8jCW7vX1NlBcgvl2HkAvL/dPWDeW9kJFLTB
US2Ch3cqTAisRJju7wCPl2x7IJEgnLot9QFydMNXtXtC6bzv6bNM1XFjYO0pphg4P8G5p4MJ4no5
cZwlQLHYQ3KTi4/RM9Z+yqKLRj4+koQ1AkuTYrGPehlzDYda4rMk70pAV96okZk7gYToe50XVc7Y
ZjTciT3pkJCuIr2Ews2GB8mKn62tp2Xd6jQdXB1ErTOWL6JUPD1eRw39DlQz8UuHgwA8jlB2UOxa
76z+Q6Vqmi/2N4uBVNiVLLh6A970jXPc9RoswTgrdLw+z96t1Z9Dn9R3WBXfQ+TF91COaBrdwD3a
cczeiT5yioDQfifG1Xv7Om2pNgJ48z3dd5GbF88M0Iq+1K1jnLkk8XgFB0VD+e830ZrcqTnEMz7D
hFQreZYC5A4jXS/X5gjzJlbW/cXr+R/dAqEzxG7qUxWdv6YUybVS+xz5SdBs9V/D2Qlqz2dVZ9A6
aFB9Z0R/PSRvmzgXesi5Mkz2bjDi7oHoNMMI+lA/F1tGCi60PXujeVks58sPZPPFFtXwwabK4JvL
ML9in9N0cufax4DaE6fhddIcaMXH9UL21WGa0gfW5MsQ5bRsFx/xB3b+zFdVzwiT5xoCB1BIK0sD
4WjDFToLaqh2m+BmHnwmSIuilg342CluKxwKL3YYFO3b/RM+9Wwc3kfkjyuMFfproa4X7hbTHrmq
MaHhb8ehj2XXUGlfIFNNkaurI3mNBJjRnsTIdod/9Eb2DAznVv3yd8A22B/djqAIbamlbHZPDzaA
uSF6zeOm9PZHFImn/amvA2cQbyWZpI/qSdsjAaG9x+SvDPfhIl4+bJ2qZsvNLWKMVtWJE0AsBp2G
0MfTo10eD0ImMbg4TXiiSqC7hcRS25bt7MGu+itL7V10/p9CJFrw+uE6b5VBwgvSXiT//PSy/q2F
afVe4prU2noFd9bqngJ0jnYlhW7CtGf9RDqI8IFqkQHBcxjC784BxyhVjDK2bN5HIIz0lJDEzIhe
8jC8kZWijY0/ZKhcKCFe0Vzp7vl1SgRl+hQ3ixKCXvTosyR8E/BkvduQsK2+OroDB6KFLOXKu2vu
mq4TO5YKrnu3iHxFhkIu17SJajKg28CIlSovYlnEkWYu9DultmByVsUZzWeV0S0OnJTNqXztDmAX
l1Bkfmut+GQI0+eGInTXErNodN5QvjDMplI/lYeLOosALM7BtkC1kD50pBUktnkSI25SqFyzxJ4f
9Or7FWIS6Ja1lIVaQeVeVI73GAwPCksKCC4+DYoaPS9yNAqTnBUjn1sOUzLNfd9caiutRz1gbYW9
MZavQc36BgsTG7rb00vcI/R7nBvVpN0Ffm+0eGahmteS0ES8f6NSwSLztM3Yi54tEMQWc7lGljI1
9gDlA8Y54J6PwajYVT/ssBoFGiRTFOphwURhjNSewu2Ae8oJsDAR9qZ38rgZ0sQaXOyf1N2UOO6o
bxkn0lUudk7Rl9eIbRlf3ysUqJ+nqcuSuKkfenjJAip+940UhbS4joQ//KqjH4fTHDgnEkavQ9UX
JU5t3LN4udOqRKYGFVg/4m0gIj8HSpTkUTZIlejfCrqToqdAQKlFgoFrBUse6FQHJ/Y+IhlkHLGI
UExa/YaTNaWE3QwO1imNeqAiB+Mf+fIe3JlaSMVIBqTiZ7fzgWCbkNQuHcuThQuceGgbbaBxkVGG
Mgrc/GyB9BH1QbcOtQHvqmmjUWUUugR6kBTvuhyJXFXtco7gYX3a/EnJTsgCLj0+HF16GiMTe1Rk
LZ4dgJ+kWv4vFEHY7niD9EKKHo00lbuLSjbi3nwfapVcv8BGup4dwwE+wm299NmUTK50p8B1WerH
bDgRojo/fEZ8MSIprx7RlSnnoY2+pjxx3a00tEzNDBdLFDh+Bf0/rgGpoiRJi5ZjZEtZ54flRbEg
HJk5k+ZX+SM0dBT9/g+8Q5qFbKzTv9/e/lrxd0UVGBmVWbm+rvDmz0N/TcwnJqjcp/uiLi7jKaU0
38F8ro04xf0etIvyodUiPcLhO/mn3i7x/sEFj15Oe6jAJ9gagoT5z8CjOeYgv3Nfkbc403HG2BiF
soTzD/QefiIOrZJpOXgWDrE12FN97UjN5NAUN5tx4gR4tPPHyRd9WdxPXWONqW9epXUHvfpgcMg5
NiPP+vm5LcThUkOrZU0aSNXAK5kadhchOTa700TG02EDBlePPzWSi9vzFgLV7wFd6JfiW14NzW6b
qkwX8RvACT+QD6hne/e5cX9nMjWm0/I7kX93lQhObsXnHpucncn8A9uoFfZoYVJU7q6hGJrFRhm8
f/7yKAxeO9pst1Xrx3fPrJU0YS+Knpc3jXNsy66yF6pDvPRZ//8i3OStlcXyEXbF92ICeQbsxdBf
s8zXAfxGY9dEoyMXR9RJMXhrk3M/ST/0ap8JKjpASNXOulzO+3tl30+PzF7UFsMQUmsuZ7IDND9r
FAV310wSNkg4wLBQBXi752tXaFqr1tdizMxZZMR8K12J6vizFO3ffUeGxPkP016ri6uDOXAl1KNe
8UohvOFdgVhptZOmUwaV0WwgLKHjraTtE3wWNm78hUavSZ1ZEUIzCJqDK3opOkrydF67dLQ2AcUX
oNI2+KNQ8ISut/aylwho6vtGhUA6kif6V3KNnCYgvnArsFN00b8XhXRuTdaFlzE33GGc7eOJpqFk
xyYBcjqeEtpdadK029i5MAdp6FqCGMs4s0nx7lMLQBzcSLUTeFqVVc/UUvuJkgzsiVMTeZ0ITCRs
ZUcUqhSSifJwOvoN/g+YaTp6WNfYUJlSSChsDw7KbcNtpCjzqzgREzBiqaV4tYerxK89Jp6w6Xs3
1WFv7zvSsOmBa29UhHpaqNM8aiOhOOsZrdCukPzxltF5oShR081Cf9J9ksBzBUPS34RGq+CtbuBV
oRDpqMm2ZV21Gl+ZqB5eGx98w1rSSASImmGE2/L3dajphtakTITRSZrpwv6bRu0q69jXX3DNnEcY
izmsUQZA5fAnSMPG5kLw6tTwue7pcNycQ2iOEkaQDMSqWxdHKPMNfVqIuQEeYDbFfu7LQ6KDI05u
Er6+8H+gApDW2VpIscZR2LpEM5ktQaeLorYWxsmP26whcXM0hQYxtrycSXMNM1yKvnBQ1FBXQt1k
KEPWq1H8gJk5WBsBYNyY1AuDZxBKQfpxMMa3Qk9NyzUBO3rDdt1MxywOujmQKnIz77skoh+GbDlM
bIGGvPmWBeJ/PTneuKAPPpHOCjGrN22WX38T2/lcWMB4qcW6mV0xH0euHRYQL1AfG+hVJ4eBCl4o
uQUo2eouRuKYjUqefqz7ZVn/7gudIMDkIIJCYP9MxuAccPnHXNOXmGNpgXtOAn5yELDvREAkgJoX
43H0NGpDSrwxqdXEsEpSmM6ydzw5iDMAMdiC/vIGnH/L5jIHbcCh6U6pCiEP25xiqvrDwieG5xZB
itemqpnnJfJGp4aRVN/SwCVfLhO7OWSEoSyo3EvoxmuUVFw0jEVP07Z0TWbur/AxY1g5mof/urMc
zfhz9I627Uk+iiBxRMIEsnufYb9X1fl9QQwaPF4YUd+uLh6Kse5P4RTusrjF/JtTA1wcnBdr7EiW
+0WoABmp/KeNEp6E671CAD0o1RmJcKvPv4cHCKae+AsOti3nIYfFrrVRkIAOG0Q2OSNCtd0J5DJT
SiqGnUVW4z2B2pPv5imkn2Kd08cqrx2M2Uo72H1WiOUVcl+xPjVQ5l3UR1DugCSYjbnTHbQs1dyh
G2aOAf2KQ5/f2/fhqEM+YuxtxyEqVb+LveTXFdG/BcLyQoHRxuPvhB9pyJVVjVHfbzIjphPWWa3s
cXKH23B0F/geQ5nkfr1gWmYByzQ4gOElHtWAED1EzIlErNMHET2zScPtvVCXk5XfZOMtNCtAE8En
SBY5JKYoEEUqE9+c8I39jxfk1IGRnjGBR6lQsA+foRAEe98nQmtD2aqVvyDelDkjKq0GgEPywEYf
8PzNHwPEavrWvOCSuZQNMh1pac2rI1Xp1SuFV48Ng2TDYQc5zU8Raf/a6VvKd6TXnRo/NszHcejS
a4wKcVQZnFki6u3j67zeqw2QeEcHyUBjEvOaeGQdvlKPyj7W+NPWGtRn0J5ow7TTmoSeLiHOHp31
Y+eRuj4SfbWJTTR3eLzcBS89nhqkLXrckzTl+oapj+A/PA4CBRuBHUWtJGIOa5bXN9l44ZMNQiCm
snWu5V82FHMAoEHIVtXpgG/E490/1CS5uvy7dkaBjMqKYuC8pKxh7ycjpNnFmBraRiwGYzcAzWDi
G6i/zIgzchMPfzOcCKT+qUtzJx6oLeH5PpxNLeN4nOTdfC93wGvX2lGTfl3g8DPv22Y1YQo1ACkg
Iit8hDPXFzWJ4SjPjMfpq3X/+k/bq1vZl1VrtJDMzOVAM+ozbY4F8Kgm54Gqz6wKSMxF21eGb+Yf
GLD4HvlDsBn1oqBUR0SDqdotn7cEli2hIWUX4TBp4Ge40+dsc7XyOUK59Vk+1wcx7HYblmmqr7uY
bIm0njy5cmsR4sqRCB+b27mDeoP2s3HHQFI8TmTK64/QFGj0FkrnIF7gXlWXYyfpIV5XfxDlsRN8
3d1shsZLeD6JXaSN2cKUydVhY9kM7xJGUriqKv2OaXUCZtqzoF0HYPcDCsF1xHhtxKuunfMtNVBh
3ZV5ghWvLqrZOHkLUKRNSkOxGfilauCUfSUy5H++apUifWRLPa0dchJRgl2ZmJ3BsipCs72EpRRZ
ndEW6D/U1SuY8AxQUqRmCRTYCIIPnkd0PT/sqLtWmQOfVfQtl162X8oNyQsPbB2nepESYzV5b9i3
6F5jJ2wKfkTXaroVmgQyOLaEMSKHTorEAjhCOnH4CGOyycqF+We4ak7bfghGofniLpbnmQZHavy1
36tgguhAvbT74IbCnu30plwxwHyzs0o6e4Be5gZA+8HRrX1rTzRjSPPaE7RHKQHSR8BtKd/6uwU4
+hWsUpwW2Yu7sL6eHIlvgE7eYxXtlmsEGD08N6bXwzMNhLDUHzh5b9q3mseKpIsWH4tazU/NtrIm
ME9M6O5Kz3L4I2vrNfxUfMfbWNST3/FKaK6jNwwTKceslAFZ4rHZUqbJdK7UML7dY1M9WAP576xC
chQS8Ez3ER3hj8bAkg0HuWs2tudaeHCE5tH1ZmvCzIo7m4Crj7xeNMDY/p6dHZD36qf/BOxJiaGj
fVsU5+8O5AIXjjT1zTPu6sidjuTmqWHcbFCsUeg4W16r8+cu2c/6+dcS0sCBb+M5CV9PZoYhfVXb
Nn8iUOQCtYClazb2CTmtyBX67i5OEeRKseg3M2SbTcjGrtkkO4UC0P2xFqQrYPuiakWfqXY1foG9
2y29VFDqa55LU2s5zrp7JxrZmxbXKTCmt7AXFbG5e4CaedcOSCDXGH/LRMwboDNoqCY9rphdxO/Q
KxpQ4auo98r1F+wgST6NBbsk+B1BhGxBCBVibPxg1dgFMOApIAHEdhDq3Sdh8kddctEm5ezhPupb
q9tCSknYlL25VhwZiJnKY/sOjp66RB3+9w3nBwTz36BlkTBDd+rgjy7Kh3TJ/+9uyyRW6XPb26gD
K29E6zxDZC3E2iJvIsv1yj5IOtXwi0B17SBwhujJk6ycZiIfAL1JyKOkIeIzPS6OkvCV1wrqH+sa
d05EdXfMaMNmHHxBtIUiR4r6EfBrZWbFWX+draYChUBzMZfn6+PdBMZvysVCW3347t8Q+X5HqA3F
DbGdqSpijfpuSR1P8u+RSc7dNrJ1uBz7MUPMrn6UqSzPZF8fF2p/SDbmStAAdp73qdt3i4sd0lkO
54MzaaBLAUPeKumFxu9x0qdMGMufM+ecuocA6Wa1WnECgUfAHeblt0On/QOBpOqTADoQo7cD7ANX
tYMnMHTE6J7KqGYa6UWQblnZJ/iCujUWlOz9rWT4kfn+P49rmZKGFmB8JkPf3giA8eJRvJdBWRsi
o989qY923CGf6LDjKoBRJFRlb+sT5w5XFwOoySxZsDZlaxtUd67drF7qECBEU9Obr+g72Xooa1kJ
Wdt7bdNqO4B2dmzknI0w6mx0DUjyGeGojDmSgBVMp9wm0B0nmz6jQdYBn7k5+89YFh30aRN0eAmV
g8IGwrnSTE9AqJWBZiDCjjda/NAT49Igtp1Fq47PRhJeui54Md8mgEnlX5qZhl/KKYpElKfDIyh/
Vvex0OvqiZ2cyzO2jKolYCDyPv37a3EtAznoVCndaAWYS8zH1Eoo0jcqDYl5KZNApPuXXyu03a3v
RS/VyOmKBDRV0Q/UJ1QM+NjMlil/jEDEfEZNZYjsyYaSkvxmaM/3wO8RR5BDeUwWQTwV/8B6KX1w
TG6PPwPIJpw4s8KByf+b5HPMF1Tbk4I7Urn8gra2k9MxWl0bbiwsitsxFv1I+Y6nGscVVYf3OpvX
i9zb867a6vjcCeEBZQ+UpXnZ6dcyRLFLrcmE4iIMA6+YAYJWcY11tPwCdZj54AjYWKeeItmsFsnX
gGrAifA16FvY3hdeiWT1iwumXnEBZ9zr8t4QEtvda+fkEaZPAV9SRbCkNuizD/UXFLIYiSi9hKN9
JsbJuLTLKthuQ4JS1khFZ6BjWgV0ubvRgPU84blPbL7rz8xUQjz275azl7xyxBpXE3oixnQP45+E
q3+HGaXZXVWehFOt0Fa/osH74/0pUC13x9xJHU9RFQFS6l938Hlv9KhNv8tepSp/pFe5VX+Y5fi5
y5qHq3zZWqfvhWJkXmoxWvsLm0PC7Wuq5mRoYFktgYiVFLZKmVngPxLtlj2JwF3/o6V2+DL10naU
F9zhy31lYoQ4HUO6XlEv//tejAokVLY9kkX/DPaausSlzwIE0CvN1KxMoby5EkJh3UyLRatP7G40
mHYBPvKetKjrOrOY+WaMyJv4kU06umpGzTlZnXXk+1k0Z89J8p6V6FCiQIyDAwAZckDTT6b2B7ji
YmmzEWs3+KtwExns9A5e8kSrQkfo0Yit1okOFC4HXhigNkxwqNs99ep1nlhD6ALeR9xpwrPjA8Sv
XPpIr0te4c1cBJaIThG7fcHuhd/2+aXCk9P5Y/owNNW7LnHsm9MJo9pIhudehTeIsYW+YZiJ7gKV
D20id6kpCNnNndcrF9VuTdX1iHM3lIn12gZL9sQztGP9WFC09SRzpanGWQ3mZ+J0GXjByfUXdkG7
+pVdIMpd6KmSgkwBdzhbd9P3++7jwOvI2tHdsMk9btvhv68AnzOOiXtoK+42BoZ03XYbSWaalNdI
1h9lVguC8kJ0mf8eAfYX4m3yUebBJGPb1DAae8CJPvJ4VdGum3nCNn7CtuPGcq09NsRRmnkpe45i
v5KHEpkf2FdcH/6VYzzNyDStxXg26QJOxb/7fN9J8TMum/a9DUDOL+7WvwbehmNnhJnNGSgMSKrj
fEuVRkmJsV/qtyTWQAKmv0s=
`protect end_protected
| mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/rd_fwft.vhd | 19 | 38466 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PpoeUczC12+YQ6zcBW/hk7KVg+x7UTioMUTG7QSkaE8DKLm5OzMFnRnSP2RdM8C+WL55mLvLDYfA
5lOC4Ruqpw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
K3yZ7/h8XZC4VnxKqSX+X1dWQEKELq4EziAIjvSKKzex+MM5ch0NyAGabLWybM0VZcnyA2IuBQRw
LXtEZmU52Vw900CqGAC8j1ob1JJokunlfDgROKOp9VekmhrNu0zlywHl+eh6CQ/t5W76EWfCnLXS
TKcvUxKzMPqBkiVg3Y8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NSAGB2MTAPfuv2AfQtQrWIP89UNTneL4Bk6/B2TdOO+6mmG5j3iveazvIvg7qIHwAqHfCGACbbAp
fGS79Be+x6ilLMPgwgbPlwYl5oARsjb29GILZJJbq65kaBdWWJCFrRmIDIFHXq65c5qChGV/7EF5
BRY2p2sjUe67cd7MFOLVO0mKHurU5wiieT+wdpbGs9uEgt/pGFeQKlj4ch2XzN03R8Lg3KmqOC6w
j6pa6lYe8j+sQMdh+WMN3EmYurAN2aA01NOtdnD7EoaLrP3ByXrwCKFB06hQfAMKudCun+42nXbW
17uiY727vjm9PIB2xOmQazUdPEZbwz2Eeua7KQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NPiHNhu2YI6wz7attBCDx15tEqFL81ie9/7cRUJzlr+aO842fU7+GGF/JOlqWsuQg2RB92onmIR9
gKmj6xIVPN77wRnezyej9aQsYy3bBfOSvbf7a7d2lZQT1pTZcYMfp3xveVQ5gTGk/1BN6rnnT8J4
QRALHC2oqPHhQZ427wg=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aHttOHUQP+m+tZmSEhqIMk3Jbc86fWQ1/2LKPbbHBoOHb+XyETCjDqnDo9IWfpo+m+LC80obW4Zd
cXgM5NoQ9F1AYdG2ggcdGNXeaparpheOz+XWEe8nirOAN+Ks5VYo+yRWYwO3R0Y+0V6Yw8r7cd48
CXttfKVhu2QOlKTiKegYDKMRGhVyrdNkx/KDldRFk70rkBceBbiSjdBniOrozyhG2imBoMkKkCmI
8TwlLhPf5Ra+r8wceN6j4BjOnyQ3EtzJgw91ujnHo20MZFiaPiqLQIavDgBT1y7leXT7TIK9Z2uu
L3Oj5XHzPc1v3FMsMkjnu8xWqC9pP05Ha8xR1w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26736)
`protect data_block
Lw3ntSlrCokmfZtclotQk75wzvGS8NAVbfW40Ny0M3qGBUgwlKBkocOK4usgGsCHzLcvJEWmwBj1
3wfmeMovQ6E1L9p0zv5fHQAI3pbG1yrQ5Pb1RchCkOLmGsOWkL4hI8Ky5pymEJV1Gy/67VFKPPHp
STpFio7hukOaG6yOfVLFz3BjqWEdbVfaa9tRGugyO+5FcqZfTxEa4Si03udjzcqO/H35KmceoELJ
CVHDK/c/EMXh6yS70PdLGd7LXJrWz9BaflTPsqg0SsBoypFIhqc0Akrc6Kfn7npE84ChKUB4GlGU
vUH+XOAK6WZPYMBbzSFb2EyB4R0MDSlk6yQ7bouMsCbdpYezi8JoXVkuvdBh8eAVMDcTUpO+zHOG
cOhyf2+W/j2t4Rh6DPo6Z7SQW+ZD5XKHwTANc3xKbL5GImmKo65uLWHhs8yeUBgjO7ez9gSK9ImO
TXfAwYByaTC96hkCbSVgknq1RpqhWgk7oqBSVuVVqqhPaXvMQT5WlE9ztefbtuw8ZR+KnU+Uqy5O
JJkSpS8ZMay7i5oG3XwXhDgjmrvEnj8zjpyY32Xi3vfWU6pKwGxia+3B95RJhTv9ClBA54bT8zyn
U6mU0a8h6xBr8FxQ9eJysWb9Nv5iWvzi8gdfy2MV6utnvncbYWX8Fk2rhNw2f/AktfVi8tMpALIt
bxb8I2ZUMW0W+WltnNR87F5nSLBowjwjsMwTWxfpUuY/YP5S0670UjEkm1+47MHIZBqku1kyACFP
k9BkHGzAiMYJRg99p2SRFHgz7hT1RjKIV63TDKmuGyNxCxNCkr2Cwr3bbvBfiG8OszPfP+ysR3Q4
TFS1vrC00M1tevsr3RKo5v+s/ovLj6NHEk6qwKfHxuRCcwZkzF7cIeSEHQnxikAkVdqFsfC2B+YC
vcJ8p/3cu3a9TGi1sRbsSy66u1WDHPtO5BiRYtsSsgomPsPCrD5QSVQFy196L/XxJiJoQgvyrJxJ
VoM5Eu4fLnoDPTJQlWEm8ZFxKYOWGilL0jBLq+2A2HRn6DfPTbzzYQ5gPbuhOcoXKhgj836wPGQF
LYoKMxERfnDJPDheayMnhe1OG/yb0VfkicRPAqDZ/LQtZ/aqSAJzt6wVQSEU+y/45UM+sfJ1C/ax
E0sgloo0mQjB3Ge2WPuZBXkL8NC7fqBaaDAznRlwPR8e+E5S9ShyZNxXvOqFUCyRYQqPJAn+qxfb
rdaHg5saIk3JlY0bKk3AQR86bCmRQUw0UtJDcI6LPYVXSp9Z67HTWKCeT0Z1bEb2jJnj3DFzG9aK
1mP6KXkgXiGamu1TZlDfezhuHNc7vZufwldz6XmnipHBg4sZIxcJbNqP1GIquwbz4hpCK58WsSla
JYl464gMCafm22GcbZ+fhcPqzjM5NytZOkhaeGsZU9LLxcBxs50J76MuNbI3BW+n2nlJiHDNrHJk
1GY00lltSVFIe/BeK/m7GHHH/WSloyiLGSTX7DqndwaltYCkLSvtam+prvHLOrmkZg+Nh9XDR0y7
xzXHbjq4DSC0FGKJSsb1AmbqNDlcHyLaCxhWlYEWUPrVyqEozMKlFmf+PSz385P9HAbbOdqMFoz5
qJLPdc42fgT/S49tB4mn5iX9jC0flJ4VfoT3HRu6EN93FreG4iqGIIjf0caLMMhxn9aBJFdygvCZ
jCviqiwiDLMsbAqzezwNRcpMrbv1cb5LuQCzOFJOckCv+HI7kRsZSa68sfVe7FyWS2gc4DCJCB00
JEUoMtzJVvGKYd08xQS4c3B4GTvKhdUY7mYIT/HWri+psziRwLykLQP/O9ajxz0Qt+9eeJAEERaW
/nQFXhuXiaWgBMVlusuhvkE7RNk0N6dvFXQazYsCDbPk6UbKS0W319a4zh4brl5bEa5d7WbLHG6H
8ut/H8gJG7GvYleoc39l7tExXA7K1jc5SbOsey7ZqwtffKnm5L6ZnKMCnWXMxRcbajQfpuyEVry7
I2VkzhoI/A7fMaGK3fTMQ1PHeurlQ8JIFKRnc+IxGcUjlzdk3UV18Ym8NasQe5mah8YpL/YvEdTc
+jXmBOOcfk8iXefsTsy9pYy512a8G67Q5AMRi7yszcz4V6O/CiRieoyMS6FRljneBOF9Q6e1R3Ch
Rvh3hANMssokfb+YDaU/rTn0G+CGzMo6jY8HbH+xzJcYozxBqw+AfNmEefSJmpWcE7hkRtptmyEB
VlJKtTwZYOtDLat1vyzp+ED91waawyn06GO76JUuogC4FuNpr4vFQQMmcn+A/S06UzHmRS2ao0yw
mHgOKp1mVXg75qdKYRXkPqV2wcfDB4/XDp/D+fCIRFE2DZ5TxIAwVM2fdQ6PtID+ddt2Q2Q6flFv
P6vpj/r6Gm/O5U/JpHuCqeLLLdIbQmQKWYKfPaYHPlLTjcLXjuFgdS6hhTtgoaUWOR6MNBBkdcNT
MZPBu+NZPt6E2alYtBmRE33wKFznrtKa6thViDReJiHfqdZjU15OdG98JXO1stHbdfN/hqpwQFvA
Jx5vInTvHLhfMTDybDsT+ACrnKGOOOXGGB2Ri3HRwELiPoWlGpjXEPTcfvwz3714B4x79nRMyNSw
zey2GPL2cEbYmATOXXTAKAqW86h1yqqV/kGJ6eN42IlOBgK2jXw/l3ieazFfa5Hosw6IyvLPkaDK
Zaq0eR/ok9uzGU/3NxLo7wKxjLxcxU2ZK/4ECTJrcded8Lnw4yEJjUxQ4jGOJ2TjnjIFD9MvimB3
wDSN0kUsnwqd6HVX3pa804dFSm3TZWdfUh4iOzK/BAuVt8ZYfqpTiS44DSvcRAfxmQEjlsMH0RUI
/mMU6i4GND5Z/SXqDywA21y5ODYfFIMT9sDgv+PRyym22+CMVnxZh2kXlQAlBnN/dXKo4AKAjiQ9
E8X67Y7OkJmw2Em/7QmPTkg24nsx7mEewtZ1B56MdwFXNFs3ZrA2b8BqLeJHswdRsTlthGYcZkAT
uZaW9B9eDy0UbL4/bqv0N0JqHBD/ndg4Z6ceZXJRykGEm0GU3dYJxCdw4CO6ca5scsyNtCB8ovQR
KB8wyIuexIfPvxTxqF5PDuWQEi0CWipY8UHu7ZT3S+TCB3cusDj9X1zeR1HQpiaWK1GQeyPSsMu9
QNM5z9qbNfqADWdgWrH6+fIm5UD3sGD38lDVceO2TjiGpnqlfS3W5BltJ1rtm3sANUNl7HNkZvrY
fJqDp9j4pcDWOBbDsGZe0crIkERuFXNPmfWHYc7vFvLrNxPDWOC3DckbiNb34RSQnYFDTVFJWZs0
KNmXnwFGigPbNYuyexyWQ+D427YtA3CT9l7DsGvLZbu3NMfB0PoH2xslyp/uhf940tyOekpWdAPN
9qtZI5jmyRt4JT2Hz1O9Jrfdqbd3rXyRh71k6bmNVQpK1vQVQirsDi5z2n3MZOx7PfZpBxWsgIOo
PrckF6FUdeE4dRFrNo2eNTOH+DtZ1KOB3UhD1tMu2PoZTLy/wT3arR62+eDmdG2mvfUC9+B/IHxF
K0HZXFJ7UVC83T1u+iBh/3/ggH2tttccOCC/tnxqnc9yIJ9eGkUgjUs4UcP3lL+FTn6/QNxdEccr
EFJcLEZ8c+lCjG1By+omLwkI7pp7dS6b9YH4thdSuXCCGQErgeq4oLNj5jMUtz9mJOtGGtbrv0vH
W8IrAhVEM+VtJEQSW6U/4K6a6GMM8f3wK0zk/U7SD52ioV6lmHZ0jb8vTN/ProLgEuoudfyd38cI
1mD5ljwoaYHdXz3uZ8iIG411D+7lHjZ/WETTu4zWM4XbF4JUlKPpgqgvJhFRo/glaciAQICq4LoT
KA63mC4AlH+bh4Y3Sw6/V7Fa4nWfobUqZOXBaHpGZ1OZ3YAN+7jZqfHjYIyTCq5ugV6dX5787TkF
HGJizTdNtlQfPoxBjTQNRLu+mCLJaMaylv7GFIPDRBO/5V9KHQvKGFoG5HDjF+J3z/FIUr3jguCu
9yWUoqz8pEz2yC+pr9vWblKM544Q5No9kWQkc6wmP/mPrx9V08O3KX4YtlusbUiTIC4RpQADjrNC
7rMCq3mnt9kzCX/8HGEcrCh+0LVEf1PlGzCVrxC7JovzEeoqcu4ioeftuYrRhRfTSWVTebZUwXqp
Ur9lzR5L6f7sT0n7Bu3sDC0eHZ2C5fr8KmrXKuDTrjlPtpFk+AW//Y0+wY4feCNFZwMeKvRXZ7p1
GQH4n1j9J8ROPfWVvnpqP6eDuMA2hLgjKFeL4mCWk+iQC36hmKFU6E3nyNfazdoH3as8ufwNQDNQ
qtqiUytBNkcieqcyh+fuKZ7tmSmldj0ZPqCC5SwmxHMwhtE7/6T1uMUr9kFyXFAeJnlQRiBuQE8Y
Lw9BkAlhhH2QeFHaw4m73iN8EZAxqvjrf4obRT3xuwoOvgedGAhdztlHfedlyOCPITMYJNa63JTL
NvdNVYd7bIjKs8uK3r/LgPE82b+pgr0IEDPdKWHnqYtuKhN27KFEYPZ6NTFzi9Bltupvaeh6GnYH
QAJ+KaA/OWfVyFfMMUZbDAoFuEUp2CCyyltaeVVv6rxTHvlO4cliqBLmzSG+UD5m16eoNc9vsvGX
pfQlCGfvX43mjbL7YD9NQmaIJC5kMAF0NrLEEi0LfrO/F9ju12O0bq56igJSsLestY7cEqxWJCcM
WgcEs/DYbdTQFjBhBSp58ZbUH8awJYgVc+dBmlFT5nbuxKaDCY69FN3okAoZSAzoNa6djAnhtcc0
gC5bI3gYwkX4QdJGYTAY0+kCzlyynES44iJBfc+aFlyOhBsCQfXMFH569pKknjvRb4So4hbrnc9I
3e/0C4b/XdlrOsooZt1N3Be4H93+MADHdwR6cvVYXRbQ7ThSZx7jo/FzoUXPLTyLRK/8HW8M9quy
mvOWzJOcn36uHbrSm3Er8aA1aGToYtXXyw29HTFcUvGsk2/7IDtJ2k/h4SANe6cTpbXbyFUBdif2
4hX9/5hOaPRU2eoxiKExILa2O7x13CWZ2OAcAWjf/KZ0X8kMEJks8WFEVdflHLkLn/Z7OIWpXjO1
rc7x95D98U/2dNX5604RRqSEnsbKVASNF04dYsiQL6ijON6rVKC6WyMHLTVIwwpAGnmYHLYCdJAF
SV/cdCTP/CeXFs9T4HP3JiSpjeCtWzyd2scUM2TYSaaqQ4mutitqrtqUtLawz7DxfkIUwShpXlLf
1v6CLFAnzn32J/LobO4q1w7qFjBUfny4CPn0qlhxyp2l1wRxyDQZ2J0+jctygeAVv9cOlaWUYjsM
MrKvYc5urUnJPNmLfH5+cVHa9NHpowUv85QOT4nYSFrRinaJuG9V9WCrXMFJyIXx/0rI2oO+Ikqo
7GUHPV63fC32gzPNDiIap007yeb2lfxU39RWTMYwpkuoBqGR2y45sBgHR+jNqnEPuDCoZFQlCKq9
gWRH97PBdNdRHEuwzaiOQ1Wu8xeFtJnCuqS2TcaVZEKtffmRc1mA9reUBEhxl7hPhMTW75k2pL4k
wNK/NFVIfMcjNP3QDuoblGYqNI6PC3EUmTM/DqeOIp904HMAn/Ke2pLUgCladI4dVKUeEtbsgWp8
xQGvn95RAZazqo9C/xeVeboyPhzUszpbA2NBduuKb5usRw9VM8K+LTqzipUecNvxjP/OQtqwkvna
kM32DH9/Ej19uVZuHb3tzJmJvsjWA5O9ZQYrZlwpvK0uHNi3upfdo7DkCJvn/1LYHMBVupLUGfyt
/dGLEug1PP1yiwREeV3lrytLAy6OKwY/XT5Ov8tBIpO/kNbTIQ79KOKVm46yuvBWoDvy8kHtiCWz
/i/cAQZQslWd+2rFt0uSk+t5PdIDxMkpz0FWaxZZ2Qf5JzBQ1P1q96HD3V6FQwc3Xl8KtIFUkRQU
hpSGgSTxSc/J2PsT+1z/sRFbALESLAu8InYOUstooK0gUCOlUpU3w4Q9xrzEuY1Z0Uxq0IPFOe4+
mhESdybX1xpq9kEZXniPBFiIeKyN66/eFeZaiAra4wQLjfDhytle+j8F/B1dCFeGt/0bTaUvae1Y
wlxdRrkLTdkKby9CjZBKUX9TIgcS3D0GYjixUKtIWo3Axk7ZTGEvU5pBrXaB/iGnd9HYdW6mWzz8
H22hWbJ0YctA5dedBGvfyPA5DAhSdTlYk0iYcnY9aIjvQwPZSQ4LxeOJCMpgLeUVM0Lm/o+avmwT
I8c4s081KdkH8wHD1etb4hnx5Pz/SszlXMMjFhC+vFQg8bEhXmib67GtCSPbe6mk9NQ6bOIlnn2L
JoN2Lbgdp/KVSFwIyQs63o6GIQiiylU+Oq+LkFIjqtutzIaH2aG32bRcdAiAQ18fitq8YXmdz1po
0N7gFYNzXjTRnnRx+7uvgW4cMsovSTSivavYsJOH8imKLHeYqNs7CmQWxnIMDrtX36XPjK2IcJG1
EJ7Q9UeKwUvk3kVLUo545OJvf2shAv+e8/kwHwAXiiGpHt7ekEgR9wydPBpS3D4xRSrDz9ecqGTZ
XCoAiN+cGi82aAwoVCG9PssXL73n8amozvxEVDEIntMma3UMtzVrXAseC14SjgK5fi+Nf0weLidc
/iSRc+CWDYpFb5tOVjXWZVk/swW0yZ2NK0gbJJLPRVpGlqLeeJenXF/G6R15m1yIgWFwXjdCIHr7
KCgiayIQqC51JKL3Mj1I7FmsotXuX69+esp1qo55s3DnfF7vvbud5Sjgesb0nsYpJlcfRVx2lvb1
SK29UPVa1em+lTPmZioE+R8hChU7ZAH80XNP5XdUjDmE0r3qf16x+lHDcB3TyDwvxmlR5nGnHC/4
eseu22nWxUj1r2aecSY0PIldYjDq97E7CG7/FDxuFm08hgL3/oMiBxff1KzGOvJlsSLbMtesg5sQ
4dAZp+2uNJu0WU5PuKBVRsxRpY6fYGhqdGsHUzJPylsM0+dRP46L+DSPmniHSrY/yyW3mc/1Q5NJ
mu9KcRfexlWwbj1V2yjVSKkuNEFOYbr2IkBNTP8fKW5sFiPVYGywYMhCDwcfyRK+f6ZEf3ijQnpO
P2AxHwIRfj2tzD2Ub+FBtOBB0OrOsJHL5rF1070YFaDdCqNyiU0oObZkzDz3SfsOrEeTm5Xz2zni
48uZWqRUGLFYaSsY0mo6K3Fki+36Buqqq69X67ghss6+XCeH2Zz5xOxUt2o624SU/L8WplBkVZ51
XqUsmshngRZxXEJw/S2wsoVprmXtByLf2UwilMp4NF6wfP+xfd+OKvwflceHaASKA6seNn5bsw8j
32kPAHChGF4HyHBUH8CIwOTNHtq47WPEJ2HciS69bV33HCBsd72DZqSuG90dFPRVsdnVK5ulxS2G
qZyQhSeP5uAJA4Bd4phbyCaaO3FTR+ySim38emCA4sbK3/47tBsA/N5gRUP6pezpPflLUpbanIeQ
ZpCDzSV9RYgoY4H/sGl17eBl4q9G6FNm9eOvz5zk8OOz/VSItbiAymMPtkPlKPaMHUTHLb85Ubw+
K6BNYgZmfjJMeMlpaK756Ik1WPM6n5lwjStREKYJ5f0fuSFBORfMYfFZzgDkn9eZPVrsXT0y6HDG
bAe8Ov8ZU2boLIaQj7iLaAmYOVSauhihKocfIAXq2llCxX5uFFy/uEsi7Hrdzu/4gC/HPOlnRmjN
kzH3ckFwEiaKQXwcshIjlQy5hfSE3Ubz1OlD04/pyIN3lypzK/CM6qSx7JJZPPMhzuk+QnxY62WR
62xlz8YDTuXadJHWFr22kwNnKpkFRr/Yy0HXZ/16idN5UmBu3c9bjq3LuxJoolpf9dG8srziMxkZ
xgti3rTYaRZmrG1EUNvjbQCPdS8LDkPJAox+lkIMuHzAMd+/2KiqcZwpSNJRQo0N6Pa2MmkUWOj9
jN5Dj+mRDWz/CNQplmX3TBTlhKJ1CuTeQeyRZk5VgSZpf6GKvjQ48+6/bu4jRrVxK6Bm3GBaji4s
qMB4c7yxy5C3gGN8A2IhiseGtywpg3DHOF4fd0f7QEuZid037zqZmLCIgteIKGneq5XSUpKiadVm
gXEhD2/Y/Lq6YNr0CB92TUoEf2SRavepT/kSXqTpZJRiUTS/wHPkiys7KCjDOYpvuZerwIPePFAn
jsZpk8cOxhveIG3QevMoDm3OEWMy9NJJkCBzvhuFRieqnz4dzyAOf8BWCpcJ7byxU79+3hyWXODI
wBaDr6SSUgxBqej5BofbG2a9ztxWQLPnxBvoIj+56mR1HRgjPlke9KtQSlRkwottVs22CzcoXmg7
cI/QKF9v4kBM6iZ9ZHE2a4ayvon8yzFAb+N8bnQn5kLgZj1KKuYul2zxw56iHepRUs2G8vGBS1gf
8kgow14QTBaPh8qBgairIrtkuB12qg3daoBdvH96MySHZVM/VexuhRbTlNual4a4ch6Ee1tfaiVh
2qsyLRlGsdz5UfGdElwBcgsmgPyF6wDaEprDcyo/eW5pGv6/m0N5fUDJ8swXvJtTT5ew0bc4XWG9
c+S9S3+y4QxWVvA2PWAgUUhqt1sYInAlwhSkl6XkesHLD9M1YplPvJDmov2O70sRQt8pO/FjIHh4
mGSWz5S9tq0b5yrPX/UruWCfIP4zt7p0W9Iiu6E4Vc+q9wZiVMEBuD7hOVSbltZDn0cb5ol+a+S4
mBKxx21M6Ak1qjNbc+bw8WAZdx6u8gs6E/fTAVEn90Z+Kr5VfIubb/HBOrfL4760Jk/IPaWtebED
6STx/YTc+u003dYWEP+2QdRTSXF8JdXcPf8p3kpxx14B2AZjoP5U6ZOT3CVmEJI69iGESwiupftz
KZK5bByE1TGqnFOTeoGvfn4KPxAIKgjVRBgDR7uFQjUFrr8f7x3QGwWMacytQMw1eeza0ha32K9b
DM26nybZuU0by51DX/Ji6mooALTWVqc7NYqXVoU03PjkrAW5zzlHULbuJTbET0awZoB1jIQ4wyNs
Btr4fjF+1tLTsj4vY2R1PphD9XxpJ+S0odaotskCVC0HP/FcnsYa+O04BQSHwVww3fxJ6dHN3xxt
mINi0RogqeD9qti6BJfsYMBLR3gUrh1+KY0bP5EIQyPZlvybTI0HhZgSbOTWo8DpHQCVQDcqZS0x
mbB+HQlJwUxvXVRSNj/3pdvkG96tRU+qznfLRUJe9j79aBuksDEcEPNwx0VAE4xD9LwPh9VdW9jC
SRbbhYHcX2OVQ2AZSSJEhf5BvNPrzDglNlHcVeqQVtzs8PogzJ++vr8PF+TlzNP7CxRIPjd4yQjG
8MXz97wzr5xto2W6mnCg7XFkhK+Tyx2+UJrZnQ2Bw5t0GcJikn8kLnjVwEQl2ByjFO5msIpbmGtf
1c2qjEQNcGuCNocSVCVFcY5o6CqZ16w4iTIn2pcnBVW6likUMK7hjj2m6+oIHfMT31V3X+5xYKWb
47Yt8e2GaePgLGShMsuuxkaeKlO76rGa20Xn4zlvf0yG8kDsufPt+OZgSxQEnMAynrnUqAISov9a
fKk8u0f/lizi0jKvuYP/mMXVNmexwMbY5YEXcG4CBjt9SFrmnQmQWUOgKBWmDi/JdZMfp2FXGDXD
vOtfWhcTjRF7/cEgaPRAGRP63yap0KUG3ThtG8mUPAk5akGwTHdAGL8tiVaR83duT/AXDJLnetMW
yJgk6FZqQpPDKgHuWclrWGJiom7o+1Q6CYsxQFcgQEtbWpPktba2pgGJoBxBbOHYlgiFC+g5HoII
i86DH6rDJ6d2uHBfqffXCqomigEmpDkPkL3hRjHajorvfS39lvuc/s9VLBq0AnDPFz9m9xEX1I2Y
1KnSGdWaxDOVHf/050U8NMDz7abagg44SCSTOyTR8YJub0vWfmYyy1NZF9c466njfN+sEk8KCSeZ
RvX42SC4U4MJAanFOQSzun6hF8jniTbkHYVmzj2dX0NS4ayGjODaFJPfywT3Dkj2QPZbKuTprAbL
WjsgiSnPgwRftXywPU7PuU4x299CUz6ywyn5TDmSl9N8jSdd062TtZ84PATISVVZ9kEAigO861tk
sgsyrCPWvkCKr9poZZTciL/uP+EINRQuf3uG0J4IOS+SvAC6EvYd9dpwqUqOr7SKbtx4CEwC7JYQ
8VABySrRmoatZ8vb9r3CZ/8Vx0soTEwwJroNlT1fBc752xwFNAkxr+xEJe0Kl1Iu1KUljT7Q287o
V0sfNvtYMgWg3q1tbscV/tp59qzCD3qJdxIR4uv/IeRlDJkq2qR7VZtGgNr3iJSvS+8naM1slJJk
Z0uhhPD5oy03fQ/TJbZkVj/Dxpn/KqN4S1iHK+8NhH+s+S+5LlmiyLM5B9smSyWwQHS0FPHCsCBm
IC3UToAEWw6UMf3kcSjAMLgN1IspxJCVAGVVkKb9o8suiYq0RwhN/efH0gUDyxXV/Nifa0JEDn6m
ZyY2nvIofZpq0FBueDZDbismkwoWRtD8Wqz+rPOcXjgHWWRUcI6rvNtOV25a+SgkpZmZW14Z9xed
Q+LTNpdwZcIS0SipIRl5/cCFxn4cYnlCzHEo+jVSMQUT7/v8+bRxhuVb7CHMI/WC8o1itIPbvpxy
Oml7Juy3vdKpWEmqW/zzBI3eIxhSzZgTugYoStSSY9HQP3l1Hva/c+KC9LQyC9F8NSBiD2bMvkDC
8ZDmWofngPiu+N3C1nbwndEHphdrc6GtgYyCsx3ma3h85hrmfDqdLjMJW4lcIcxJKhA3SiV+5+me
Ek8xb9PV5RuXgKfhUK3MUa63LcWV2z5wb53XbEPRvtp408TyG+blePGJTya0kvoFq017UivioHZ1
fSuK55Gqhr7UogaAm+nwS9UL1IZyNmPDvmthUmclG/fcntqK58A4ObS9s4VZDzLqenaI/4Mm2iJS
JDrdizUsIR9wwqx/coTaRR1gOH7Pa19cjNgWctfA7+wRsT4cluSPz1d1ygleVuiF2nz7+e/274ql
s/FzOhbLORmGe1u7ifPEcmfR2FX/5y8XkfzaQjzpd+bc2tWRhyQ1HIQMNIfRM95GQt8kr68bmSwX
0RhwndVfsERpwFJo7R8uxNyYdGCVno+UZc6nTsBZi4RDi6dx5jOKtD86DT2oQQOiaGkHWfTzutct
BzAkw1sN4d8AKEux8YlSIgqoqGFvghTn8H2F4y4nfquDDKPIsiuGmtw9JMG0pciXw3x223gCFadh
ZCx5fk5Oy4LuvR3EseBwROWwYCs41AhyQEOkNaDtp23I/GZqGsRbgK78PMyb8TV/n4f1o681x0yA
DtFeRT+b29Xej3TzbpIxW4JI5EpFKRlG5XUi2wz76NI7HWv6HKj+q0nr67uPihhOy7KpHfHiJk12
MuVL6kOZ0tKd+bcS2iLuc9vpQG5QOiRi++SPzkWCj9OTPJVKzBU77Tr3MPk2ybbiQQCGPTYVTsWx
h1nKC3He1IDtOzYBm7xkHbSWlsKoymAGgezUHlxNbzin96sEtlqA+eBGqyeqUKbE2+n5WnXwzf2+
OBZ0Wo30CsKFKDceV/izLfLXGVNaqGos1nImVEfy8j1Q2pvlW1K0nRjhm3Q+T1yDaH+JDSPg+MRl
QY9cZWurmrmw0bTcGA3GFtk+kYZ1dsQT41epNYh96eN9XitKlhOSiV4bmpd0q2iRflqxsrpjzO+U
dScO/PsEnSY2f0LqOcHGKPtYK74GXXwtVBY8JWC5L62+Azou2zkckYRtKV638hWYm/WJ81MUUMac
EIWG6pRHiE53G7weZwv+jrazsL+Jz1LziMHiMtKYWNW5pKCfmYE4/7SBX/ZjaP6D/NvhKe0jbPPN
yjKS8cLtOH4Z1z7D5zE1o6NR6ORxgBaCSgmX294sFYObYsrQTRW9ZzKCX13Xka4sdTaitoDgcMYR
2Ax6CYbp3a8MTsNRglw6/Z2tGThN1NGQJhtHeLTU5YwNbt27cqru5AfhHMml/7bRWxVT8CvL3dqY
KkdGlH0xeZ1zxvuy6pgpKUmWJ5J9G+VUgpxa4f0CeHmuIo8M8c8g0mZ3C/vf/SNNJ78hpXQm18Rz
4rXZE/OLzRBbKTV8o4KN/iQcLOAPjF99N5ElhShQHeTOcfe+Utt8A9HVHXdlCNMPZqZXA8eZ6/lT
Lbv+4bCUoZ+HFjG/jnez/2sSbpKp2QhN1AER89mdQbLI4kCi1lQKK04sMJr9iTo3anPg9YQzaHR8
1+kRHEg5h7U1uExMxcVyiiY2rWQLc3mDp37Cfzs9YCpsQAQ8VbnhaC3uef33svl0UW74/fAKyhda
PSq8bGE6grAlKon3odOzoVLoRIO0i37F8biDmhwfe/w7AcK0JNaN7aRS3eekDy4w9Pp6G6u7C0E+
xdq++l/TbwLhpOWj2Ogt9sjuqMD3L1yZCUIcf9EEh5YTlHX4GNzeOGKbypzQItopPZl7LceF7Vqw
Qq7601wLQy6kmJCIfZjVusZ98brePrFjx/qy+cnwIzmPf4QofyefPYoD/tK0JBaK/9QzTKtCwtG7
z7CHiz3rxfeC05KTnIzYtsNZZjrWEKNYPm6TeLUoKUIJ5ypUlO9fdlMXh9OKfGebrBev0HedgN2F
qDIswDYhJAXwS3CySlUK0tSNgkv0Wxcmg2fgzYJV0DIIemhuwOlZl5nDv7gINtpehHCbz1Vy4tA6
1bXARXo6qKtFhkI0og4Qnz8hLdoOCmTwDZF+QizHhAssp48cwZAg68xKuYIXLr1KjEhGKtw9YvaB
ebLYNbScUydoZbOBM3Xl/q6DVWW7nQfvxdpcv7DvVHIRBvtxrEbaH8APBrhKiTE1jSenWi3dQTk6
8WWtqF2kFNPixzFgeYrCDQhBMEW30l7g8YzWpkM+basAkEGuQXdHyWDH/Zyyy8lqzmTN+Owd77xY
/icgU9j0gf4K8a2tVAiE7jEZHPuyGRje63RygWHy7DOmrlMHcO9JBwVNoU9LOHMxbTwxbo7iCMnn
En9ys2zgvOfgLNwqW7pYmLY0rIeB/Laek67DEwPPW6V1bNb4OxCjrxQqwejdLdS2nWM42DcgNqen
Pcjka+qTlEFNOzY1ZvxUX6IEb8tbJ6wsbtuawwnFX6pxbOIx7Sb1ywczKh07+b0BRNWys3zCXJN/
Oug9iWdV5knBmTnh5U6pJemVj9jftQGRNCmgkkFrV93F+g8UHCVEpJ7/9T2NN8xzK26gF6BtDXzs
zmOMZZbrN/q6atj++AyM6OKlNPc8iUpV8550duLbcEemAoPOnu094W6uPAumLRUUvrlsyj8fdHz4
N6GPc7O53tfI2u3bvQJ26Lu+6hkkkagH88Kq5DjqrPwmrwIGacerIyiURruYx8frWiAss7jnAoN/
PuId8nI352XK5b2WOpvX2yEbRvrC8NPfvkTTypHMgm+cwEjDGHAz9D6BFTfwD0Q5jfzE3KnjXQjY
mHWFD1wl64k6TNY4Be9yYIFWE4x6Q2WLg0e8Mp+ZdUhIkDvNL/m6ZMmcNknKhFTMWisMdF0b7oLm
EEmTzpMd3qj4Oaw/G3+Oacm3a1WlIepMA+ev9aZIFIOvPoncpF8hjbPW5JP8CupXOgyXiIKgyu/M
X+I9yEuA/+TxSdFWYUyvzusOoBGQKWPcn97R/tKGLRDpb2tTE2ZA0X/zjtaWZ6BicRZ7CzSJX4Ct
bCQ11l3g8kwpNwWNMw4jNpGCebwk85fXpFdqGyqTDY1dp3Em0783k4rv7giYVFhpa+qyAOqakpvR
lz0OmQV76yygXG3EwO2E/7lXUdhsNSO0CzYvNsjryW2Cd/7hg6XQR4NIOezyxYmM7rvBrrF3hJrn
tr7AA8+Ye8xiljZ+8XEIZESKE4Jrq+qXDkmpb9rMEZHEZ73qTtPU7FrGrnZzdp1ZPG5myK8CE94O
VfTe3Dxs7ECFt+DGMhWSkSVql3j9mrlqUIj6HPNu0NkyysFIiGke7Ef6kIIJQWJaVZj0R8Kfcl65
CvsNxLh5+bBJOJQx5gnR3gBNczxxmu9NuSDXmVXc4sohECHYndGulH9U02n7I/Awk2yHOsmyN+vb
az6yKn6jz1zDtqq0Q4+aln5tTJNYQ+ArYAUG5dhOR50XYMNY4VMNln9dDknE53E10pGGTPEvt7G0
GsoTKAK46bv/MuAzXsUshDSUsn6yWsn2Vam9btjkgmWHCSxVmR4RQsiu5rZhthFY5WW3U1zhliiJ
aT4+ZuADWNz/cZVdmS4lxaT6JxugAs7VBMCbT4FA0WcmqmptiWEDgYfTAHOLVStHDU52KWdbER7+
JDU2d9+Pk1wjnDW/jCgVNQ8wM7MEVYDJIVT7WbzLemlA/zbjNRLjZo3zePVwFi00FKFsYP8hIU8e
ta2RK5vqED5cLXd1VolQsJUzkw65EsUlHMo2hAsub3UuxdIk5aBlocu2OWlERafcpmlZeb95+9+Y
z6In4Ob1sl9L80c8zRmdSARiEpw0Z4cWojpjjseJ5fRtwIU704i93egLSdIfBwUIePrjwWeO8Hk5
GsKriQHbEzDmhwEktQKDyLjTyY5ia6GaaYtg62LiX7016m9jYqZ1xVm2JkKj1UR5d9WXF6Ehu7a6
DyginRrF42CfuqJSw+JxVeL50KfC++9Pl8TA55qxsXFq94rJtOphAeAGG771B9946w0Qk5DUfj4f
w60KSj9zXIlubH37uOyLLwgn3c9TVMkIoy7Ue7tAXbXR16rc8/F7Y4I7ry+7tU9KUAbGpTOlJxR4
azdC06e9VKNDK2YFI/8xnZmRwEmOsFGneDPCnq02s61y73Bgh1AiFwzrPg4YcuYBAAdkWups7Jf0
+mpALaacmO6uYI+LHCjfeOR4rsR/t45Pi4wUJWrL/EYHojENJWlTF06TtlcUbyQvzr7jGMfbx1DM
IaFgeg1hcgp0XuIwTcEjdw+W7yt8MUn2zFi7VX2+PIfzY+XJKynsX2g2e9guZ2vj6A4OAPMDxmxo
k+S0Mt1zp4sAMKWiXZcgGnJqOl+EkyymKh7j+A3+gyQUlfhquIq1ljZEemFQ+DZkTE4drZ01gG93
VmJEuaf4zYljOqu0+BUZEQOE4pUriU4/7+VKqTGxXW6DHG6M726yL28nbulOPRKLcqV/x4UzX815
4hAnfFxU5L+IOnN5Xm70K1Ui4R2u9XPnMwHVI4h1nW2zUEgyGDMcWRc16ry4TaDxlGNQ26VpO1V7
1ikwqqNSWcpmc4u9L/CPX/bR084u+lUUzYhgPeVfP8F8VcbhmT23m1ENv2X55VAk+pp1KrJI1VDa
XtJtUjC013WRv0iNOiTuHzG8SXYK7h9uvf1vP/LUzuF2n1awWpoAQHorYO9zVcN+e2SV2F0mKlH7
2uhjk71xcqzID9HSBRutAJMTjgU0RGGp10sKN3a9ynkE5Q01MIrp0dRKuD5ro3hQtQdkdPrXKZgi
JWe8QBPM08mOWeXjy1AACqkFt1THu+7MjClxdopu39k9oG9HCALL2HAmq7qnsbVVobhbUcyx6lD0
SI12AOmB3g27fJcgzdlUQw6w7dRIH0YzK43cYyHLnC9sbbRqe5eG/2p3l4lHWpsohoqmDeBDuJ4R
vBeJspUxgW342DZ5bk4FFOv2XFZtPnlEPdcl485Wxy7oIKB8bHPPyd0QofuyKSU7x5AJLwIsB9aT
jqdb1FGFIyNJ2N5ucEHCUaTfRO0PgFTO3mYwXqe7di6gRFHxZtLD0ogBxfaQ8/jFdqQCMLFmETvP
HSl1WFzDTl3RiE8zwbhMvtbt0l1Eqeht4caJbrYHeLXIUrAaAktjEqal5rVVwlxhXc8K3n5Kraxi
O2s+6GWkR8v5MHKj4cp8+y574HfBHTAxTQDPqcpOTFkFxE8XLLXaudd2vmPaQauoeJPnJAjQwFXG
bDq3d+ockHiB6tJatYio9nP+1zK2JzVza2V37H9Qbk+04+EbOxPEouQ6qmmdGY0HoeP0h4w6GLa+
Ae36r6hm3w1En5d2AKm4CL7Ir08/aqnY9iFB8QGBEsupGYAZHwRBEvvfhaQ+Y9n4TQop2jvDy7SH
2Dwa39L4EywRCNsrcMQKPreJcA9T6bJfxrdmW9pe9XJ0GmPEr49v6oCXiJuY21/sDzAUd6ca1zJB
uyr7QZ80xjG6rOznLtDhPggSS+jz5wickB1tKHorBLCAM+2pnbhxQw/gm73+KozL7LcdeQKCfrdb
F+L3CScadTF2ndkL7pcbDpWTS8mFCf5mT4+UQpq5AtPKDp/ImfrjhmnKaBTxj/T0NBNpkttzZn+P
I/NqBx9kEIAAMJW/ID7km3v3QOhO8H/I5SKikOD3UO1FMg5vMdi0R+r8NiSrZ7XzBko3rmOFJUMP
JEDPmktp7TVLsYxp9qfkOhkQPcVWWomTkTPaR3PHGp1iW47Pw97DIMCyPPWXoJrZSkjp9wvNTJqw
CocPAhRffkfu1XVQ74GOw8NOYq7R8CBG9Ps0ETWvprDOJ9y7jUxz7rmpAOewDmfSsktOWs+rTr9i
wvQfNp39JW1+C75INnTQjslFKjpwlIqbfmbXmVU/Vf0BEENllYzjMtryaVNADObEnf3zA0gwDPjt
yWkfeWsEYiLZKyIcjSy1HITc6PCZ0+9aBUlAg6sk2cs31D5BJu+MYOxaqC/iDirFTbLU1cfAsSpz
mX1gO+1FAducj9nwRfQBn1RfqLiIody8juZqTwo7w/Nq+hZ6J5YFP8oamw0Sxn0TiNeIn0esvIv9
q266ZMHylQC5qeSQHALej3AJqmDwbMEa7ZcMc6js+KSiDAW2QCqyewvjLKIfHCdkdlNDdgBrmC8E
1i7dDcopUP7RZ86w3A5kcG3p8EZEENkJ8SIQKlCyVbBCMQK4LWD0lITGhAOdKQGTAmehyGapyu22
/0FHGcpLlqE2GPeAaNRXUsUik5RqcleyuhVMiO5nHWV/vsUutd2Qob71+k/9wnGlKCDvGoUqNBv8
SQ38FhNSF3lCwizFHKpPeZFK2Ms5Ir5VM9snWEXvNwMmXcu+/9bVfFAMeuYAQc6YpekFDpt7CfCO
jbGKRowMsNT1KkhoGXz/L9LWwUblkXPDgKmBU4YA/8ceatLV0I86CBq4QQFtvX2UWH/YK9aCk07C
jvnvTRoDqReDPxXlLGIW/DcXlyPldzKM20xt/ko10FY7kIokwZ4n9HC4+C35p989KJvzwUoMnoBb
BcUERTrNUh6hLbc5/hPTlrdUGhMEf5W1KTs6L9xBG1c8Kvlp3O9iDt30H8SXnS7pCrCtg6Pc0cxr
Am63Cfv+IT2BXqUz/elv7Su53fsci3mjo+fmWU2SWOksvGYgAwJ+ff+r6Vv4+U3XI0qWP7mWEqcY
wT8B/Ei9RABEPKsT6MSxiGCY2LrCb9l+fZhoDBJVH0lBg/Aad2A5DoLgysG3WpC0a97pyIz5gUR8
udP/Ro0yWKln4iBdlkcIkBe9zjxhWtKWmPxavC9Nn6Cof20qsjNSQY2EM4IA7xM4Kok073BQWF5l
ldVSAGw+fk55ugzeO6KLlrE904XQLcyRUf/ZRrnCfBNz5ENaFno0dPduobYBo6sXT3jvNla2vaiF
E5bU9/6OqtgYjDQewGcy2Kx1IsVQTeg8tmIoKRv9BXIdP2QzN4Z1oONaZeLrrR8JeO3iuEjObI7A
CxevMZmLG7eNG1Q3WSB3eI3iiH8JfDQb6EnQ5/N/asi4E4HOHS4gC/Aor+gTZe7Dr9sXkhtBl0Dk
+tSEFKWgDwkF0kSv26oE46KxEwTMUh1dh32H0SE/7XBZ05HdLFpzWKmWOcx9c6BR+ByQaJpRt1yQ
cgTzqDNvDE98Olf6zgVTyTH8NizzlIjueqgZh7OG90/poTrqE2kMuG41sOaHQxj4T1jHmhvQwgSw
EW5I5Nh5r0hulXj09EiKzRfDmmqJVV7V9QRhePx8kCZ6vMx8H+CRTKRjcBCKyMY/oLt0mh/5nNW7
Q1H36JpvacFMvDK8fTfQF5nt/fyv53+dCmDHbW4VSYc/ov5h9YPxPcO/jtaNl1JJRmp9N32kawEg
9/Tc8DteuPrrHcWcyerl6fQzDrw9txx+6Cf+5+gUx6vdQ+O02zfAYRUVul126FCNEjHBy5MBAGBP
f8N/u1LC8VU+CM1Mm3e5RE7YkqgDmV/AguocCkPWPxzLfpghTWLU7nANahYrl9MluatM3Pb/sRVZ
s8AgHnSZ58wGG91EE6D7zil7f4ovyaBlgg02TufpQKvuwOFXCpF1kmwsmdvSMQ3j1dS2UN4neKJ8
gNf9LefbfIG61dYHQisKSP8dsYfJyA+KL6cKUh7ENY1fVHxKKAvXGy3S3tK8l00u1Fyi3nNnY3gk
5CMy49b3cBg8qDjmsIbr6YEtWPN3z0Zo8jxrCL/7JXo0Rx5l4KvrK9INza1bOhpaBtIfHwYFDBlE
IleY2I/LvYeYF6H0NpAypkTks+kH9aKhK9R+HumfL3WdbNi5NRqYzlg8Q1E/pmO20e+vra9unF5b
vDGjjtb42nTx1emnnvqXqHK0wOpdxMyiux3PWAQafouDru1ctOQOX8h6y5jMNrP2Et5jCUagfuEB
/gs1heduLisb+fWvwEy0oD6UhO8TggkaFynCzinI8xV9zItGMQCCb3tLDlmWKTL9KMPY83xPOXG3
j0HddnRhGRGKRa6jbtLnDzoNburhltzdeeth+sBOqFX1gZz21Ks6NIOJm9I31HtRbGmRJ54kwfz5
ZtI45Qef0jruvjruXalCOtRL/WDMx86xh5qRipO/9K0nzryUbPjDl0FXqlRYUV5vr3IF5nvt9E1T
ofZvQi/djdlmxnEfwIxOmNcNitnv7Jb8XSGwsstdvB7P6ChFMZ5QIqSpIfnxHD14Ed/X500HWWRP
hh7quDb8cedxvPGjSAM58sfQ7BSJGTKRlJEB3RvhpZfQbZNlHilKyjsbAdN/ctcdqhOQldFUgQaK
NzxEIO7xOi+22kRyGcCbEmPZENw98bB8FC0AajvyN4ev5+9yJRACfK+huayLcT0I9ZvZkQ2FlinK
WurXR9WJ1L/YNsptbiX60ivgqk/dZzpbIDf1/bAB9bmBaDN/37qSHDkW4u2XtSEFhZ9BHzi/gYh5
gNzCzV24RIjA88pTHZguyChCrA6Ma9fJWPAZCI55+7dd2P3El8+jXodANbfkVRH1TVZ7T/cnUt8G
/Ke9v4X8aUQToW+G2dlKZsnqyVjqa/EduWrWcOKTy3IqnHiZ9NRXFo4dSQoJzadVzu01+rx6pSJz
1Jk/d/2RbuLaRLNzWxBjEPbsgeW/kLwIABsGJX+i2thVRYly+215ITYz+PSbHDodP0JCgJGOwDVu
woiBZPRyJ0oC8UqnJ+pnD2MEUNk2lZjmz9zzQZ3s3eLoh5Ur/Ymszb9qzFzZl0PcgN3bGX9+Dapk
erN0KFM4ORIoXBa8R71i7lZL8ZeRuoiIrCQhhdlfzTwwaEv0kxZAnMWPHXJe2SXV3K/kqR61sv4f
kpaw9R6WL0BBQuNiE1GunO8zYqUXX18g6h8c+VrkZOlJnhoTyMr4J22lKvDHlhjAEXA25EQ0E5lv
ZD5zk2/QdbWTo+OYo8uGQ0MBeXRW/8A00ZrWMivosQWM1Vtc0DsjVEa0HC9krTWvJeGutNeXfb3C
Yo4Iv5k7BwcZCRVhGuXrUHhBOx7+c2X8dBewOXEWiLeYGQ4lEqU9l/SmZHjWpqYDUe0OjWNhyZtd
apv05T66JhzNXf3tatFazZojaqGwpax5EopQGkc7GtFXf6SNV7U+r5ZCF5xjzXwnUJQ9uW9s/YEJ
kD3lsiUoofZW7IGyS5V5xT0Vq6a5M8NipcL8AcJXP8UMVHYvkSIv6Fw9mfAHTxG7j/I0eBa3fXyk
yBHqTefw0GT1lUyBWcmrlrduEopz5ff3x1bDhEj4IWE0fv8VEdIA3u+8sMmPbMvcMzQFQMAmColG
KntcvVhAkrGNFu/wz9glT9hDOz/YOL1nN4twkUqH2D5n/+CyGfYRGzC91YETD3wRprsChCBNOIIK
LeoCgrJv4XwCWuOk5b9h4W1m41svN+VHtrxCRmUuH8JXAMgMgtwNoqynQy3edWwj85MB4WCK9/fj
UsU3/AnznjxNB4kyge621o4qO7+/dnnxaIcxKEqyj5FPAQ+lIO0r2pmeNyIajX9FyC7sjV2Jk/pF
aZqR7x5THuRgXiPvoI93Gn/OYiU3oCzSDMsRrZczAGtkFGEndj00IvLRMm9CIbvrD16d/Y3CtNjM
MDG45/J1uj6lEaWn0lEzIvCQM7PJM7uliYv2O7MR7Ljult9FYakBMlLUg8sj+CCyj4l12Z5KibN/
uehUtKRgpDkEWJy7hZWnRl3iydzZSVJjRXpjlcgd862Atw4lel1oYL0dvqi7nUDgbhZ/CQsxbzuP
VgssNZXQ74fQXNFA32ES1mtU7m/ItcuNXw40WbE8PuIx623lOqdugn106FQZN6R6/+gtTdQxM3Lq
7eA122Ur4I2bfkbfLCMBjDPaG9jCDzuDJdacOVYKiiSLEzabZGUKsEo6wvIfjuIZVQ9YIlg76RFL
KRlQDtotRHGkdG0/GcpqVQrEkAbXFpios4yh+mAvJc1u8V7FFRtsJBZRnoR6a+0OsL3rcLxoxeZU
8YUiaFxhW0Lujd0bbmOd+efFzvVDznhcVUNcSOWw/oMwJakna/GtvmLxYvmV77xlua+l2yVLLUVT
AToQsU62zFAqVklDTIaXhvSS0FuwqWJb6A/PBo2nOIF9hhrsaveo6WtdKDdYmpKOJscgBb3sgWoe
9q8u5EbIh9sKNMxjRKjnirHi2E/NY1Xlt790SAMweLS85glL8qtoMG/aZwEgnids8a3JdeV6Wg2i
dto5EAQ2nTQVA4qk/ZxL4BmMUlpKOWnjd4NRZYgWtQGk2pQPT5QKDA/KqVhKmoX7X4Did6e7wtPN
yhJBYglsDAzNCD72iKoBpzjIrPfLqvr5t7PmK++mmkqiPkMkRdW2XmdwVn46MPmnA7jn5azmtuLY
MGLBZyzov2KHih9KqDGfEhyfpmdXS7ouflITOdT0IVdCE4gdfnUuxuJ0bPN7/p4UdAbmfdaYjO5T
x+9AC1E1VOGeRy1rFJw4w6oGyqe1N6KNtTapQpawYJx8QKG1JrNz/+sp9cXKhU7crsidJztp+DVA
YRbxT1izS7518NWbIU8t6dbMQ0UFpUpQmscJY/OC2yafL0RGGrp8JTe9g5kkURrNcSbkMharcgDO
Dl0T/k6o2cFiHhVqiAoTSICbDIEQex+HNf/JqGGcL5D5Wr/XCQiFarhSQtjbuO4D0XZ0qipOUfoh
2ZU8y4iH9Q190hIbB/CHyUrT1TaqJpb6ZM+6fVhU7O0EHGWqAr7pfG/iKCQvFSRYcBVizTrBsJ8C
zvvRKnaT9az155sVXsA5v700rntM4nIJKf9MkjrGVXx+/pIDM6kD9CN32wl0FXT8mGluMNaJRN6o
iu0MvyP/gO/tBCxMNvG9q8ZJh8clRrt300QN5j0GdZx6/3JN/CRrquhhau+zQguAYiLkuKbuQf6G
mfhHjUAikhW40EgEVk6V9JxgQWOufISgpkLwjYuePEaBKBupJVuiF24bD+XSof+G7UC41LCpWkGV
jxYoG1ltW92ew94Qmc+ausrMDVjCL+IP1XDB9K+LmjMSDa8KdkKcg77rLZZQTw1xP6g4SvELaQvI
f5S8M/W8ae8aoS/JzdswDi0IFm6TDdYa6TZWXBX+bFxb56pSycxAVCHJL4QdZv/E1glFTm/DEKFU
FCAYx2h0K2h/nYYcKP2sM+61dhxU3ouhR5LnWWfkD+RXEZu0fVgqNroMKbZNIkGbjdvgJCcU9o4Y
1pbv7xjub7F9/znZblZNE1Q9C+b+u2gQI1zhf+RNXYWOHQhGMi1o9AFABhknmTRi9FEqJXUaDh94
Srk+KRHwRRB2tY7hLZAny2kOlkZQu+Fw1HU5Wxxjc2zh3x4oFma7aqWmy4MKpSNRbex6dqvxwjHU
313wbC78Cq39qSHHDHod/ARjhBScK5vUvae/ft1JXkpvMF+s4VPpZ+WnwP8xQAeqig+eyKA3gmAH
8S3deXf8GmToM65erw9ixbpH2iE2m72Q87Yl1l5Qp5YPffbedw+kdRdEP+guXxTzr5zMdxkXDJ+2
n27Prio5yKTdvMPEy/6vNwlM1+Nd06M2QiDnP31ng0ZLAGkMc0rVlzkGjTwmvp4kkRa8y+9Ljb/U
31AB2isWMCpWDXuX+WVfFLpTjBuek+KvrLnAP2i1LLE9SBVo88EMEAhE6F/4cM7nD+Vq0OBIXiXs
E2TU0OyN3q1LATBJqRlEmeG/w+Dk6hjg4SQWr2qWuGppaGENEmOuKOkAMQ5Bu7+WUzNtrYbGknht
u9MJc6vc2a2blZPi+8GYnhdMNICvfPs+SqmxE+zusSl9f36hFsB1YjbZogYIw3f1pFl5ygdTvzMl
GXfPBlfF2u55zpDe3Rq+d1Ci6zK2dfuXm04gLDFGszAKMW/dVV7Dp3UYedmIkVP/5p115BUx/4/k
aC3HqFiPVpMR5vOy1h3DmtAlCjVsgtp9WQHNIanH21pPZksPdR4Nw8c/1ZYGCiGReqG4m2OvU751
k3hT2dyCcurh6WkAcOJ3PYvg/Oc6uC7WYgd6xfi5cqEBTRtaQcsByzNeyjsCClA6OFSoyhlj96C/
oRqGynUW5mbM20i9fq+XGjObKNyM0tLHmCeUZcotKX2PEXDf2v702gMmoi8YnPpN0NV5FxMUvf2o
hwyC/AX4q2ScU1ph3/exI2BnBOj3keIqjX+jNxst4YdC6KJ2ewbKIdyi5qIlaD5oLvn9j281sZrm
fyk/gnjIX5H3Hw2MZG8B8AOhD/BBmCm9MMvk32ozWuhq2EtyVzQ40PpK5M5Q/zxuWiGENmH+/1Cf
zuph6ViLg55M1ofmF3zlPQLmMRMAd45dr6qj1/+mw+FDpQgxBZoniRamR0RKQUzXJ/mpXwANrGLg
nR+iLFYUPk/9gPoXcRsl5juw/AoGEHAUFhYFOGH2VSz2bKWVRFlOJ/yEMuWd5XbX+DN4KKLMgHfq
ngCSEXuOhTpLszK5b41DSTEwyf85Sz9WoHC6z4UTjY38uz0/rGyLkxETSVxzN9B8tgCcKkmuj/rF
U71Uqk3PJl2E53HZTLemaw2s4erXZd+TZ/s+abTi1H19gHKCxXGwmhsFZm/ke8m1Vaz7feQibx0F
J5/v0ucrcV1pvSr49CHBdkhC6NzgpHPab1ts/TXPziVgmAV5VWi6Q63O+2SjSR6YOE/1QGB8BdyB
xZRiCNjWWRDq8cw32d3j0q4sXcXTKt6rj0zwvT0YgsIx2jJOR7b+x6E5HdWscONR7GKpaool0lnx
zUdNNl38OXypp3q3ktT5wpVsGpdNL6sl/Ebix0PlepT6XbsOlaqzIi5RAro8auFcL8Mh1ulQHYBr
G1iozRUcVVG0fjLL/U/bJGkwYxNLBlFOt3NtNvcufPJh0HfDdFRrJWxKUmkgL4N77ig4gmVywORz
j53MojfAR6B5GAuALgvh3LR+gtI6dC26SKJdTu7rOQZWYLZJDbq6j/x5nu7YuFze82ENn/QSM1Qn
bJ7Mrcx8CbtWwA64jsUgofdAF+HCcew8u/HTL1ibZFNbHTWVTOOl0luq3ebtTTcEtd26OoFwnUQz
4uOVlsK2WN4QpyuULabU40I+2pTC/kfEbSEVVNN7CHOagRW1mYXH+uEOK6k50sm9YSg2a40fazC6
ij48T/PMobr3w7hIm+78Nq99dzRxBsMFZZASknBqK393yllm6ynUO/XOT9kezsd1meIZxVEI2SJY
I4J/Zclj8Q1ejJ4tfr+MhbuQ8UmpJDSGDdG+k7ytGCVsTSSFqUJxxCnp/BMnu218aL9Ij1x0Y0kO
boaMM+zlLYPs6poVQZZ0URHoU03+hx0/N/mlk78fYVNQ3oPRBu40TLqNDZGJM7PEcVU+e7G07XgR
FoNwjepkKZTzW009KYiMoBemv64X/oCKwYhDVq3OGIzsqdT6ZDyadYNecTX9Q3D5Yei80G+VFht7
9NJR/c2RBXjVVG/WEOknfMVxfMvYx3aiyMdNHz7wxudgOgcjKDtTGnxJcEFwJp6ZmZeARwhj05FO
3xj7Bsg+8OAHwODqwI7XGdOGVGDq2HDJpQe8k3dXSodQ06NmNULUOteX+gzuB/m5CSO9Fu9i5mCh
Hgkc3ttEN/xmAdUKfRpgCuq7DDvkVbMP+mwK3FVL8Qzs/nNpWbij8c3PKnki5RQRKEIbYbBIS8OV
OjqZ+iXaVRGkrfriTnSjdqtPErJCuZksvI4XGWgo1sGiw7AF6fIDOqSN7yX1u3eg/B4Zch3ojhP7
GithoxFaFoEeFXg9z63oySD8F8VxFjJFvDWJ55oUDJl3FirxDZGh1byjA2o78SoCxtv21wn2JnZc
WlGpfkED1vlm/tBZrG4Rty9B6pDu88iN1dGuTqF25p4X0uSLWbvVh6O41jUSeBsyDz/ZIJ9xfw4J
aBMVOB9Z+fqatUra2QiyDHMOzHHa8H5PBFZWjbLp1C/rlljvusYo3qBOGnyJbspe2hCvp1uMM/Ci
1GbGQNGQk9ZxvJT5qX93/CQi3Ds1PFpIDCE5mqmwLzdH4BKzs+n04B2fa2BRfTx5a8hmp9sga4W7
iP4zkvq13b6dPnUtGyTX+Qb8yfZHSkB/L1yDrszWtCCam6Aeu4nPbsLAHvsK/Qn/gzHRvp9VoHOr
YyKQTzXroB2XPY+KSO+n7t+se7oNzv36bnRG1g/dw0Rl9JHPIZRgBm1mWrzs2gYeQibhnnqNIJG8
kPqn447JmLAkeOr8RipEo4E198O3qmG+0box7Chm6kv4+K1v6CoFp3Cq58dqO6pFqN69cmrNrMm2
0HpYOkC0ZS/fxjKgoXT+j7kUiNew0bjdyBGThdcac2aQJEyztqe+sdzWkol2cb2Xe3gdqFdtFuHP
8p4LJwWzhds5tDl23wgMItt+GY3rlOds+SKBvlE0VSuueoqx1I10YXjasBDIgrpqldE5sG8F9JRK
DX/7Ub7Qnxr372ytvHGd8J9jGPAymCdZKSEm29bIfZ1FjNUVp10wlbYkRr2QIjoT4MmhIC7LvTSp
GWbxdtCBNYtj1ovTOXgpvefZAFSuPeO/8e+JI4j/aj8p6YlH0daBD7MEW0lZCa47g0q/08UDxtaG
HJKIfA7qEg3/MyyxQ76bnOIhEyWcWSZB7gxm4D1NXlzogQTkThlNKYx26BCDdfbDaOIw5Epq0lMH
ZKZWbKb7l2bAyTkhFdnse3uRF7h3/70MG6iBZ9Cow2dk0gpx6lwbH8N1UHVk7WgDxCKYONkMlVHm
SbUwFq7NQHdgg7Z0H2eQGGHRZE3VIplXav22dCX9K8js0gZGWolDjbIxbfRQK+6sg8Yx5XYhDuor
2OkB31WSvN2bXpuOHd6vUcWPRXZhx3hkyMiSMjXVIXtr3LtZryiD15TTV5HMt/w8vKhnUTB8MmRI
SPIlpE/Y1uQBKDlkXCH9IofoDST1wgFIWwKLsY1Lmna2BxKFeUFx5kEJUSJIRMGCRenakP8SpAll
oDOA61YWnhCOP93mVxOPwaIcMUDPXlM+166Hl/HM1eraDy47iEaEuHVbitS1aVvzKlFnvteZEMUJ
VJV5+RuahPljAxNQTgTs4E2MsbrcQfeM47Q0nETMp/KkftU9dRab8TUFZL72/GUAPLDqjNmE/1Ny
IdZwM8bzCon3XdM+gTDIINzlRKStuJMGmJdboCm5ELDsMFpt6/lkBmByYAGDNvoqeobBvAPBymU9
zSqo0Er4KUPA5NVlHcVroZoaMjO3F6sUf21LIkSTFTcftFSlpeugRFgFpQ7rfGrjkKqAiFhEAh+9
1U6eeda5kwlsx3kmki8478c/VHHEN87VUo3KSGwdGEopey9YKruBRdMJgsesUVAyrmXX1uTj8+5Y
Ea/psoJJYj2kVdSaEOQOVLwlAGR379U0zAvDme66IINbbBxqxiYSjFceeOXezs9rST02zfB2HQa0
HUojaFiWKsGSaquR/pXCSahRqkYls1ikXBeSl8OV2nTb6CplBoBhXAVSaMBtJc4ayUfpJwpxfxzz
U9L+PQSOIuYx1GgbSc9gxadPLJGcklDs7rbVrn8mPXRK8bNBd8VRVlVuIkenrumMR4qztNQpQ0Ft
53EArDuZRTGPYNhlaJqhpvpKn35evmrjClMEd9TMPnCTFtQpUbBrZSAEgc4EBWqPodYKy/3NkuYZ
5X07iyzxb50y8Gjd8UsBKK/nokqSfD7Xi4NCst/GvjPjUX12N6gb2ck+1NGaW4+4jNnoWpQR0Olz
+17TZcUen9/S6kf6NSMnkot/EzpRzBG7rzo/3rREk3hJoz39mUd/dT013Ii2+L4qOoT/mQsUkobJ
ExvyAh5Gs/VubpSaq5COFC1LtUN9TpLLNhuPV7hiTPlMcexJFS4D4iHwloDVMR2famqGDa4SvmHQ
xN2ziPbNxG6fobXpK/9bqTwn58D/FgX7l0bc23eN9X7xiSYhYtllxVbQ6Ya9SPDN3U5xTiV8e9r0
FGMWVFJh50vGW/Ug6dPK417UP3d2GNmZW4MLeUWxSBngDwbo06iTNTMdwH8IAm7R1Vvz2Yep3gwh
EFCNWAIfCj8B9Zi1kpbfodKH2DlNw7LcmLIUoKm/TYHlt3TooymCb10x8by5eB8rbI4wiZZidyFI
6uU+9MBAlFb/bFESiMUGlNmXkdWiTaNkrqKJnfHuZCD5YhJ/2GxFJUduuntsdUef1RN4fT5Tk5mt
8SlCloFh1mtYX20IGvhSRJzCDytLd5ydJMVzruw6RVgt6cmi9BOM3sqSsIuiQPYBJVHQgd4aR3uv
DC8gVE0apAsmn6ZN1nlZEVv+dYg60+X7JrebhIxbQ2QCIZku90ebw+xobP+oldvQpHJLxpIMApC1
CGZn4WY1uPXeQbIBrhANIz6XZW0Q+G4xxxRkCkxcPihrz+j3hkmsclgEG07knCfbNFOysULlh310
TrNzXMdWrNaL/I0OdM52LKUcT268Vc5m7f8IuyX/YmNHfM6I+/ZM8C2dCuh0f6dySwUj3iNtIwGs
macxgIJqTiaMxDVyLOZbYieh4y8Om5WVRuBPuPK7W9lGU+ja9sBB5wEdRzEI7AkmeKWvFLg9KMw7
BwapDp0AiQZsLEFrvVsLkDuLU7v7d+/To0EAb1jtHAQm3znZ0/dDnyZJd70Lm7aZ8qMrMotBbQ6G
nxQ+IdeQQZXX9fau3I+SjDuazCn6xhaDv/DaFmSWyze/KZJCLSvTbnV+MGs4nevfCv598apEE3Po
90zaQMHGaOlowo+p/yEMyjFFGX1xinWYiRKyjK6k7cYozskd0RvVi4sPA+qhCmhc0Z0DVuVhz/wH
ImPWEnP3PQMAt6ZTmaQbpDseZ9sJEzhm3hITuewI6/fzG0i9TPNvAkQuUnWrBwe60AAHbOo9qt9C
PT5SZXk5u/1iwkGeUEiC2fw71zKxjksSx+GUg21SaOZTriudJeCka0h8Y6Up0L4pZv8MdqpEyCxH
wB6ZKDpYfgiiwn/zpCbzHD+SIkG4DoCaITSyY1KXJuEtyLfzjEa8VI0+xCg78pCtsXtYf6D2b+or
5n/qPtF5wZVNOpVySTfJEDQpstROCCGGf5O9NobHPWenLDxZFzBGKZZuvHKnBGkrL8BZrzoJFBi6
BdwHfElG4jH8jRWITn7AYIpPhJgC731WnqG7drW0+XXNnzRfMOPYb+MeAIgm3dNP00sE/2jwfRoo
+POx1GBWnQWXr504efi5Si9czzAZo9B3cOxCaoWy0RQ4XmBr3e+XvstBGFnlqNPQqKBDPE8KFy9C
oEQ38qwFFJ5V9GpDXG4XoAd3IcEgqNzzuGNc8drpfHXn5IjeszwSqGu08n022LdGfKQp1QgPchTy
ZgNFr5cUjmErZmykm46ltTXPQ1D0gcjskh6djbdwrjuohJCyl8GZcYoeOpjJRSf9zb3QZRfrmvpp
jc0uVraPEE/HNfctOtRu528NQoKHf+2ElD3FAhwQ1HZArT5s/qrm/4BClcWfjsSgmgNos+JmTP9U
4EUq+F80PhOElSgChm2s4O2I2vwSuP43iMPu1OD8x2TJlooCUVUeUgTTQakIbKX+NfN7fwMawgGU
XJgvnLWyIPF5R/1g6SvmAVI5L/rsGuIJdXluR1dxah434NO7flgGEuh8yRbsxKtxdKVv5RDOK95A
FuDFsonXSXfTuNMaEJ2YNg7h3vcOzeLVZWTxu0NElfjqYCZ5QqYOKLVMhfTTWdDG3LacOymcTJS8
3e0rkp9jq139qWlVxaoGu2vh+8N6/+W/NyTS+/L/z/KXGphN5u0RuvPGIZZeY6jK1ert6IOQ28N8
yH9Mz70yfe+CRdCJgIYFRaUEDU4eIX92aVXbD2Vrhc1+FYJXHdjoIts110FKy86XI+zyAQxhTI9p
v2r0vfzgRCkkUoK6Czg43aJCFyEE+RIzXhlR+jiUJOMq1jyk+XX6Oj+pSy6Rp2WBDVHqkZAp9Sns
AkApXG/ajA85sgBLg94J94AzJJEtBW0uUlkPHIh9ZfXByNFF6MN3Zs54D17VaKn9G273UrR9rCyz
UFpsyr4s6sCpLgL+xsWTcMqoxva/NhguzXhfP8ERJqlSvkBt4R8GMUpDCzqlpAlMsQaE4tdTIA9e
P101Yy9qa/Uo0CB6infhmSH3ODBw9G0/0tWgqbr3EytEVcDhYAMt/E2vpHJZv7aVnq+z34eN78HS
NN9aAxuvz3eLBVzn0sRK/PdvZ20ApAA4uXH+c3zOIhzNF1W1K7EqzAlYkNaghx3rgLGw8cIdeE05
5BJXKPTX66x4oHP2+rrkUDw9FDHvbaLvlxYg0AdouEE2ZSStoASF+jWrpJv4EmedHxGCPtFumC1M
+/XEmM/oF9gr1giJSzm6k0HqP4Q+eBb/6hgQShOujLpSAnBwvK1j7RhJp+ExkrNMxqsZCJ0wmSzh
tHWscF+HqD7sMeemopvghBQ3uJfL7F6ELWc8Axjfx3yoR+RikJ5RvTwaDZLdHzy1hF9SaKDqwL69
vqfFDMnlIUp3gCH9nhhFOpecppt95dVGL1QXvcnni4AEjfejLNmwXk/N0UvUw+oHOxp7EEK6NyVI
D+xIGzq2hYSbLh6NSr8XMDeDq9nyK4FhpLV7b7LA0bsscN4n0lFRcgM6a5nH9YZOxC2JOs2p+IeE
ux5N4byAXShNtJiAr8TRetlmY4Ppe2DBr2Wi1MLKJ91Wkx5gEqewI2mk0tQCckvM4hWE5cocalZt
dXZo3wxg3lhsCH6jsxDK5jfCacDtlfxNjFs8rhXaMEUUDhB1tHxxTt54wnYL7pLBLcKBJ63kgSUf
qLCmpmBgUlMRLaPJ8gOjf9MhZqBlQt367FUJ00unk84llHm6zm1+H7oCSby8j75vwQICU9QhZKZI
1dfmLXL9fxQSI5zfVnJj1HEomw1p6JcE2lT3z0SgMh9nKa2p9AxZA0yhNVfXIqIMwCFTb6ReG997
B1eImeW2/iFskmEETYJVA5mTCi/OwOZkjp1RJ+QiMrg3Z6y0Fq47TcFhKDzTtGOE82koI6lsL/Ww
oEUwFQVCXbNGMjv2sFVK9SQ2S+y7uSJnqUBIuSFm/rt4dkrAiixiNZ+cCis+Zrn90EG3SzWXKRRM
lrUNuYIlX0onfVpQ6RI+fBlnjuCuoSKrOesvDXh+kgjOezTHztoXD6wwZvF/GFTB/Bvl3ebBmHel
NlKZqSEryVCgezgdbnHRrXD3fr8T0EjRKM0fWUhDnrlCuqgaNfZla+7upFivwtqYAnAFTjR9gWtD
fGKMUoAbDqyTaqMWouVEbcJ1xxuOICs2CS9VL65qUcmhKV9aZMil7PeMnyxH1QIPBbKjLeZDeOzB
QSzVxKu0m64+FklhvC7DUCqSxC2iHcuYbiE+XAfsB3lcsD26kAoACSJYcaoT8o59WakNoQ2XHMCf
3XnVUbuOHqK7bSUSMCFxi6PyEehvTN6Aajk2EKJTv706GxPUqHArw7f+bhVQFkBKFL9LJVh0xJFj
LR8WCCZMi/4bEUIkwKdKPAk1q4e8LT8foxPVYv5r3K8DjetzX1bCAtzugmaIlFJhVJcuhdXQ1fw5
twEz6GbYOjtDMsW1Ls33S+fk7RguUrumYxKnLfBNBrmz0f0BAD8vHHCv7FQD3c/LgfpirWp1gUUn
XYMSqc52XkSLuJr1KsopMSNFYNsojiYJbSdvPRxRli/DtV2gyFcorWiOhzdg2Dm0YLhbDoKjBPyx
w2cap7upbIjZBMj0Oa4etRJR4ZZQxAaCnJ8bxabaLZSlVQ6tssiIjb/NfkgqiiA8WsPBwr4/eKMT
j5XRvikDCA7jTGwnl9pVutABhU9SoSg6ufQZeHjKXxINANygDYtXQ3P/1zZhgmz/jkpzOsHMht5N
xW22bGnsF8jmBU111J4MchpsOUSCmd3lVXrYMAOW5Ji6+Adn62dQJK6YIVHnFCAL1iefyjmiU4zb
aC3zoTuP9JSMAU7s+/6IKpumN/NcjlLkfFyIiZJXkSzk38syUZPPY+uH4LbPhaUFHpymY5J6tfvQ
0fLk6elsLsxHQVbq4zMg9QdOs185UV3u08fZAXxe9NthmUseVdySQdii2kcJh4oVZxmGIHCj8fz5
n4FYUDUQOzsxl6WlZCKO1Dj9kOmswbYhbQMwi44LFTmBmzp1Fp1dOR/LSxc1CPN6oMJHgHql2soY
nG/AtmUsJOHgofh/FRQMEwJuk8bDfbFHQDVRLOWLq8Eu+fDvJw61jjDpAfxqD1WrDN7q/itL1RR6
bfSVBFrWXBgcXNexlCYAFdjLkGj0Hp9TbiyNmTf8obKxnOqxtI+EXAoTysxIgWK2DPIohyxkNeiO
1TxX3XKcTk4rsJwcRE80vR1CQ39f3S15akzm3HyhxH1lrIdsF2FaFe1fosUla4+YccU1/UeEaZRe
eMe2jTXKTKahtJVQfKIePRQPVvMVr2JU4e21N7cSXUdrhbDoODc/MhbrlDz+IyGN/n37kIeEwsVf
b+eEIRGo22fRCkcG18BxACsaKoLefDBRJMq+N+mAK6E1KaBumuG5ZmkZPPocyHtw+irOEUQwqM2e
iCKoE32oe4kBTNJ3S6dg/aOFs44kNazih0cF1QDt/LQ5FNbZMYGN7vaV5lPyAdOeOxvWssEkI6i+
Wyns9LejizpZsTEG2f4jZXKaHOlBkCNJ9hBneUZZBDyKht8CQdYNjEq4E409YLGUVLXKaqi0oF7w
DO3g51YM4CaYy9RhbC0HaQ3P24pCY5IR5k9fRIJXpfpuf/3V7cSjN2AzdE6hwI9NJY+AtBEH5UqP
Y0NVlFfPKt8WDY5oEw1XXZSaCoJPdwt7Ccdkk5q1XZmNRglIYGi/CSXMkym2Wakx/5eRufH3yAbV
mdyWphPj5r/F365iCVhZkSVR3vz9O3Ajn4IEJZLIHjZwP3FQMAtykL80lgJxe0Kj4SNPEhD6Zd5C
CCWYE7qvt6rEHjHwZF7SISkvtAUV7OoqvRisAWhyVNfcrahDUPZfXgkRXPxsWTTVs4oYFXUMjjeE
pdCvBo/A+mbi9vGnAkvR7Y3w2QzKpyLAb/CLhdpNB5r11BZaNt+/qTemWRZ2K4mVwypE6eGGr81c
tGTyar8qarmeL2vKZ/6dRom256TFgStoCrC+UE/colUxvOaPNE0aj6M/yw4vxkGxzrT08scJvkbQ
IC8OniPI81pg/CtfUmKS9PThK+kuHpp8lWeil6fNvWWE/RbemHmQPKt7/w0oIjkaa6KI/HmcXuhc
NFyQIeHJiyatYLbq5MGL3BHYDJPCdp+pOUqnSQWlIapQ2L2B2DhUHtmkhaIQOf6uenSqdPuFqqhA
+i6HJzjmzPNpOfr44cWXhNTcffWSGGUTerT6/8R0PUDHMQaWOaUM+O8x3bXskaglxou2HkV7o1wy
mSOriigVK2y/ar4rp6ULcGCXD3yooZRMlY+/JzYkCKa3IydmXJSm0JKntAA5jnbrsgsM2l1XY1MZ
h4U+wq+kjY87cR6C17weiHKZ4kQR4cQwNwkHg2aBiEhTSus7hE0KBQAmoIv8oLzvyTWAVL5BJ4vy
eGLy4QNgs5It6PHm+upmCjBDo6vklaSAmhED+gYTe2AWnnZlHKdCU/l6YyAxD2LobU+9ChUT+6MH
YMbmgib8SggIukwtFkI+iqPhFY3NJoZ6QX7BDq2nER6bii7AUh92hLwXY3G7hUYWwIxJu2tIkEyj
RemT/Yh9nJ5SRI90LXP9/C8KS6clYvKqj+8rofpP5bvHwImbDfYsrh0dLmHthQBJqBVPSnMXKtYT
qt6wBb597Dy460ghzeeV8AvV23p/zAVHhMvqzZZntnNBhlrNFvdzkrBdxU2DMzefHKcgjL3rAJ8G
MTi4C7XTX8oWdjpIIZJS0UW3kAiVlW+4cYO0U1RtY5t/vjMhHuuPEx/v3xufCidvc7mBA/X7Ec/5
f8mXEvXvBnEMwJqKrGy3SbdZUKFbk2IB8JsLFFHT7f1woObMQBFryV1PUzK1eNHhfoU5j93ESHTP
zfwwawc7/zfg6mte0Hg7j6dKmVsuQ5uyaAgbmfmUCDwkZm6USPaVSssctEEQyMffYl3TxjY+5LtZ
EpNUfw84eglQvW7G1n3c9vSnk4Vmax2fezp7NQh4MwBP32jA7/cFntC9o4BJoPjXW/YLQhzGd7WH
mCq1yVyEEzi4vEIGQTeYIbM6V5ss0YTlaEaSymJTaPrpNgvEUQ/DsKoSv/1Ti7lsh9MYoD/CN9LY
PajB7kN3Ga7pRs069WK5aDoOW7KuIv0rpgOzQ2MQl9yBbn+9WxuzT5P4GkF6FmlEiX/MCj47qtz9
atFkgXiWsU4xyQLQSG7WaQosNBeE4kR1BmXv8B9C3E+izjV5kYZ0065m64IUniFy16tW0xXop+/l
Ikx4QjXEnzSDJ08ar1+o+8ak32Bt4QC+974DUz0Xn5wPN94qUhFehNX8U/KbTJTI0Mde1d9sWclq
RDGq8yIF4cX3lvH6wYtYFcailL9QWioaINjMRF90wYwD6dDub+8feqpSGTiYDTUaqgtw9+wqtpAd
Wzy9zPfD0dQpZb6v1Tl7sL8kZVYxBbn1pjNsP2Oz9W9PxW1Kf7RB3hjjiPsyudZoTCGpJqZrTBy2
tehA+autgvMmi06UHE4gEJ8HWHFdrhjBZCmLzRdTi7V9NuO2X5OUCE8cw2RVJ9screAOrJez1z3c
UhjBn4ILycbI/IATR/g6K3SS1SRp+Gd5VtwnckgmWo6eZQctkRp4EsDfVLM3tilMOnLg3qRrd0o2
gvnAZ1yKkINYw6QjdC0F02U188McHDXnok5OOkYcofFfPv7yvx3AlgiScpYQje6WTlBwKFHSvp1n
gvA1Qs4QzPbriV1TowrglhpgUUgM8dxtlAFqgL5iKM8t0KZpi+a1Bo8KQmmpOfsXETfbKV95rhf1
sjdQlHHplEO3V+WfI/hPVyNi4nuB16EBOw6fVD4PqM6K7TmOwPUf49gNUyYH7Tq36LEn7xjD1Aps
5PQeBKjWPYhOcNBLipoia3+0Mi6SHSTN2ryOPn4+77FcjTHRXI9JhtUZZKRtTipgSCiuPGUwgCrv
05XnGfUAQCq6eUdL1MeFfQQe5WZj5rVJl1hp5jEpj7Qr0eohUGdSpa8o2Ue27R1S0tCTM8nhDRD3
S5G/uG+7dL56L+kQUe2t6+OGtV42ZCYn4OHcp8LAvQt6JyIzJisYBHTR5Gu75QlRzhU9oRiVLnOu
AutOCQ7C9N7sr73DMcbfqds7vw8jFZBfgwf+vlrpVDHwMdMLixecEXP2dMwMDNr7qSU3eXpU1d+3
rg9PtoABuuLyf5h7gLTUr1EvkKI9KxPzuU3NC9vZQrvad8oeQ2DfKKg8pdaZR6XteZSHfvluWUhw
2NL14LGH/Holc7q1s6ZZb2aEvUADCesf1+SdxQC2LigEbBEAxC9P8c64qE3TVH8+dI1QifMP6kaC
IUCDW4QNeLp4+6XIj4O18QE2GfMxK96VOk+U1TRjD8SO1YVZwP42TScGNfxw0Wnz8CzTiygN4cFw
Y5fGmtn6337DBtUJXHG5GEmKZBwQe5MuH4rvlMgaea6ldFcF9N2RQMzM79YHIxKvlpu54Y5LPA6K
nhO2W1TMfxxxF/Fun/R9aIs47CIzbYr45DrCFh9BY5sokSE9/JO4GSn7EJ++7BhL7pskZCu1ClxX
vgGYcqoZyhMWTVGyqdI9ViDVjMDFbDicQ2va4KOyDI6qeNk8l0E9vOr/2FlTunSelN/z/pDXt5hf
JcT9aW58I2vil42qQbh0sDwbjyK8VZ6TwCb5hzbm+cFNdILl9vwOnFwSZmFqmVT0j0fcNlER8sBh
a+9XorUGbZSyyss7KdlHHcLEDfViS8cJ9diZX95RdRA0IcOb8ReZAC/firfS/RrNOGU/X63+huYM
XY4Zo5SaSjYKiWQVabdeSSWKt4N3ujMDRBQiuBszerhzYqIGUjTemWTM7GtqfNNX1SpIbtMIUoN3
6nawiL19A4qdOcsA8htVmk4xxBwOistAuZlLbliVXofJTS89fs9i02EgcZMWj829NC9GAjzAq9+F
a/cihxWO2OPul2TKFsQ+7xlIZ5KFFSRnnYGlxLfIq+TAY3fpf3QUBLGNSLFV3wlsAM3NOieRsBsv
GujtiO6vcqo9B+V5nYeeBR6/n+5p+0xSUoscusRQNKSOYTgESDQ/I9MvT+xYsTYMF+347Dp9BIWI
OxZvjfhjYz5+DShWHtNM7+Y/fswy4l1Ec6qtWH4FJPJKJXNkyGbIaMdi0clPVCy9/c2cgEJNNsnU
Xt+Byxjrs4Yt+ORhcN6iPQvY98tFq56EL6yYD8S9ZhqSIJ2Ix+A8n9emyzhEFJzrhiajTj0vIEmE
eJ1j2r853a4PTTcssrBiR2FHN4MAZS0oD5EyxfMi3TAbNelYY5gDeYyRLhVixopcndnKmNzMT94g
IWDQ/BiXF4HBpQ/22aYyDaI8JZDlCq4FJAOdH7CfdcVxqmP/06SnlrUGCbySpk4WbC6JiU/GLTnr
MISlLVan9YKNhSQUaSaT9/z+gi96oVyyLCOg5J8LHUqpAuDkUAUpIjAQ+Gy2LX0KiCTCBkunAkQQ
qSrOlBRwm1NG3L91YM4icqJ7LyCRTqo9NXoLVlgrI+VoWRuOcOczU9tYx/3SkiG+8eubizBiw0qP
07Jb98P+SPWI388Qwl2KsIKOlXRcznpVvNEY6kap552Ex7a/WvpBeQwXTasoi0PV3AZUfYIF7hAg
6vg/+kklM3bnYo4b/H4b2aYA3Sj+zBCVtawCMX+5YLitqVOl4uWgH5gYnPg+mGURoN2dq8Lh/fTA
Q5VaYf9LZ1nqNtb80vtCbSSbi1Ob6KQbZDlGCGN0OKKLtyWbMAGpTarbcx1nIR/VSTE9HunN0vwd
jwxJCw4qLbeU9eJqqxuN2DSWSeaaGaPfTKZ6+ywJ9NFNuueJdy1NRF0wZ4hsc+c3a/wuN2sMeNgp
vBsvH7o17wS82JNQok6IGCCfbrIdOkhnuEdtbIEq7VHjoLwEgtgzsPZ4TsZ7GINnEC8c6R4RxNmm
Dl09wAUBehCU3Yw1KLqZNqDkvUemvUeyX3QCuLEYLhEaK/NbqJRNJbl+yFVmm3nR9+waBiVbeWpY
5taWNCkJh16EkuACDkmc4aeM7MowLkC11omcJdNumaZXZ8QOHVe+i7WYDi0jZy+nIPHzd/Jr2VQx
b1sRRHGgYWw9vHfk/JTJIx26x0QIdzP2VHY3lVl0ZIiLBeiViNPE8d0LOKBTk5mCwkk8iL/xqoOF
dfAy
`protect end_protected
| mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/rd_dc_as.vhd | 19 | 10777 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
EHhlU67zSXzve/de+KpY85nXXvMNuZL7tYgf9fn2xs2MMX6KZ+NkxxVYV7RC95SlNzgUt4DfQ4/9
3ul1mLnDjQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UlAZFSxNoqgvPPKliBxVt5c0coSpd2sh9B8mE9L64FOLOsIE10QbDZBGLO1c2gEWIwuQ23M7QvQA
5NLCK/AU93Cer6u3Y5Kw85Zu7Q3cTJ6gtsPScNo+F/wtG37D/TBvZy9QIxLBvCRLOZx77GL+Y61M
X3HQ3kaL5tpBN9LRA7Y=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BhywTGDm5IJZmP+63CSoL/TDCpGJVG3VkCIbV3f5gGTJ6iLDPwvtFhhY8681GBR+EoOyUSMbP3AZ
DMFHBgscpLa8vafzBYp5kDkIAp6zpVke5p8WT0T374mfT86d/rJV4lUvVArJtTXZ7Qb2BRu+oMwW
4NXsxCdhgqbldJw6uUCqk28aEPgcbivrgwKY8foWfBnTw+EKHyn/oWDvwghTokcxfEnmhIMsR0T3
yD/98FKNKviERlHfn1BhQ/aqkW51Vp/q5U9qrKs/+lZwoRMsy8lRZRggDQnNmQrFO+0t1Oq/DlpL
Pzgpskdyam5KjVkaaUDiD9LunE1mnunv1fkvkQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
M0G+I4o5qs/wY3cBNkJHuC5SdvD7yJrXn6vr03zDaDrjCzuSM2xSWnhAroxnc+rs8YiB5XG+kxRS
nfrpZghhDmt8SYAMsT5eb/ToWHwFcmxPkOwf0TCRf7UHox/rcVr0f6gppZYuBp8i/HMdTy7/9hVi
Jazk/jJ0qiENaXH3lhU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
II8O6ksX/NQP2v4t19inJMyzBruYXofFp7EnZduWuRh3lmwU4/uZj2tsoMzEFI9GURJGr6OGMrIR
LHPoTtEBaHFBnPNcL2m+mOF2hh90g7CmgF4J8nr08oNvCPZORB5fd/Cj4ujbrC4saBHdapCX/nOt
W3mratI2AGAl+T3t7Q0k1PLokEpC1hOrn+eLqLqV9hKaNBlW7DfM0Swj9M60AbHp0kL8sQjj6PfO
zKNcq6Xvq1JnJLzZ115Py+hhtw8g3az1/vAI3s/sf20/ggZ0t1s4m7+wPif6Tf6IZJCySXPmKW47
LjAxEb+MGgXZe5eFDZ4nbVPt5Q03mtQWzOAzTQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6240)
`protect data_block
KjU9w7W+EMycYBwWubdK4cdo2TVOg7IXnsAenMl8Ozs+YPsIVEz9JLFHnXtP+EnrqLSP6JpsfCDv
c5EY5IiZohLLsnigtGQoAbw3xJrNfW7odSYx5OD4rGw1worABRCGX65sm+Dz/Wupvrnmbf1sWTzb
I1Yb+4MVfrIKHdMbYrS9PLjZ7K2J3YbboHo5MI6h5AlOz/+wGnMsAEaQbMYvqJbaN2FCbAce2hhV
fy/iMb+u44tGRUobF7EBOM25t3AN6z0qAN8B8tt70gHhP7G2dr/q/u0VygxQRtQ4Qwop7a1Y+Y/Y
vKnqlKUJJW1lNtGrDOjKvANBtviInxNmIJJuTt9TX6ORbWBArIhf4J6Swg7TRMm+PSivJewPvN7T
YlACXXW8PSBf7kQxUv1GmNucJA2TdwxipfmPsgFE9jFxlJzGdnUSgScm1bb+uhyB4SFKWJtjiUfk
ChVZ1dA71YVoQibyJENp2WllpAlhr57uOo5B3OboE31a8NK0MnpKkDvAFfCKtRNWChM61a50DzPs
x1ya5DsBYVEJE0yQqZaMTKjONm1Q2quPFAsNFlIParq8YIf+YJI1h2iCp3VNOolk3dXcZ5+dFf9A
5lFIch83dsv7U9xkziK3ZOXOGSAKe7ZuKMduaZS/faR4T7ZaQ8Dnr6BOjylOmEwycfepVvnpgQkU
P2jdhLwiosu6YGAjUzolNsxAZE+sMJ80VQSxu+dfjyT7buiY0oLLoZrCeLdIHrJAIBSBkt9PUppT
rEvWd3qEWeh+cRk0qVqy8k41MvEg2jAtAcZwP06/lVrGvtQRiB44kWdpJUC73xqVc5F2sDuWVYfX
ItM4rOxLGOjc+JhvqhFPqYLepDQFcz23kjWAaIp5z4Wa6AAYrhw0t+0FrnsRp/vvhdQb9wVWj5SR
9IPA+3c2CP2uDvkHbm4qfXQpOUplq7T5+r17VfKonq8y3TepvMT2CJyp1Et2UGI5paOFkMGQfb6j
KgH+9hqhTaCeKynmIF/WVAwvmw4MK5K3mIyBgTu67u1VlOIiT7jyCVc6UM+8YKnMW0bGA5Owy4o4
bH0qDAUvCp25DSbPUfVvg6qUSpHuepCIxnVO4fcrknYmhLSPF1oeNQCJsVkX8OqLwTa6Y66Nn12C
yJ06vsMa4TLKWHzIp5FhBIFCTVHFV6DqNVBBEty81GRMwHIQKnJsziUfTQunlfoTTe09MT4VYem1
JR9qHh8Xq9h2Mmd6kAoNyP10G34oyVKq5WUkaTmHuDZEzONtfQ9eYbyiCvLbx/rwenhiGuaIjFA8
qUpm7XmYDatnG5yhquyKCEYoNpe8yJBUaShg9Gldmnxo9vwa0Q2JtqA741aspVRtIx+ebh9d8me5
o6VAeWToXdA3tEzz7lT/7u4OTR6OzjIDVlOMDGJty45RUN9219if9lcBbxEvwDXV6YgAG+wZebE3
wuE83MwN7As9EDPxC3boQMqzDvVgKZSr70o/08jjb9dB/p3vjw+nwuYd4xzPLI+ZB9s6k6xNf4HB
Ck1RrL5Qo+56iyJC2smH4sKP6Y+W2QcYA9ZCvCnzsSJZqgwKuGNbtMwAi9TYd3KlyRcSZ+kXdLcu
J++NMX2z6jAn73e+iRBQ1HnxRp3OV5Ow8LnVLUD9kkfGuRMmxREgNHdH/Q4JJRQL/Kbn+JKttwzj
3NnV/Q3Rvv25dflq+WytAtxKz6x8J/iShR+b/PFS3nLI0as7Wc08d0XcTgivltF8gXAFME38kEhz
LWd3xy7WO9pp9kVQ2mBQcFM0IFS1fIFdlia+lz2ahyZ2GlMA5hx0CoVNEgX/Y0zndSpyVUb5W4zW
hLWph1aw3YTJQ5ae2ZI+BkzaapyF9d1cn4iId6yN4jotmC6btlrlvNCCXIkmQIUswF3mrXc5rEbW
PSV9t0/hho6lE3+B17Cu/NOIQq5gaUinTfCC89mKYwaVN+0/q3JJvOIeHc9LrOJcBpxKx7hfMZSk
a5KPoDp2JWpXxFGDnteZ5sCm9Z1/n/BB6v7WirmQrzd3VckoX6bh1+OVF8eq0SQ4ewiJDcYQRvl5
vGRTaQnEUxQ3dY+CD8d5vfU1ttwQZyV/t8kuUn3wtmN6q5O6qeEDCc69Vs01v/K20/2qRkpemzi4
vHzYf0UWqtCkZBmNZhuAe6T2uSP8aD4swtzxVlIgjenx618ljrBfxMBUNu5zlkkO//eppVOZZ3eQ
3ZQ+gKF61Yb485fHH5K0N0+69hMjt+c8mHTgxq1r9lIstt4GVIOk7t6hYEIj5zAB9Cr7jB9dhZJH
W6+bNSs2ND5fs34wXhV7QfCSw/lqkqAoWRjMXI/QaDHltstQR1SWTkGmIi51DZhWyVamFnXXVDTn
HGjS7OfRJ2uOreyQhYkTgF/6wt0/pz26j3JWShhGauXx4QPBAKbmFNlNG4BUMWBJqT6PQzqPrJ/F
zkC1JHRwlJzPanaZKUkNwSQbb9jSQFo88u8qOMRwLACi0QaMyEDzjDhUKBTFhtkNv+PE473gNVTu
dsh00VAJs9qI3Hn71rRiHCOVBTlsmSgR93k3nWX1XnVUEFd2w8RYacOI4FzVNmfVdB8CFXW8x1MI
XNkWyeCIfPtZXI9nIHQjU8O+SMIFQxNCDVv3OK/hDvTlABDMnorSePsakt7H+S29pO27i7tlBluH
IibyZMBi4ZCOVtbw0gJAQTqBunz6xI3f+jYU8LWkw5JUUv3qa1MPzBi9dGDkx8cCsUyPeNfMzvZq
qXu+q54Ph4x4N4TYy9kUR+faW99xbXYMtwCT1rIegoAFsH17fj0chu8s2IpZBzVLPrtOYbWFCLys
D4v5twypLkZUMfyO0o/QuQkHJVLms6Tmue2s8fKAM9CRturZt21W2rMkVPQk93mlcE9esvJvzYp6
0zl9OMmTiX+14q0pVSiTgMk0n387MXfY+lNk3w6ufLZ5bVEthiktsRZfI2m3YpVy+Bb+JJi0ZrTN
3qPzechDhnxe08dNumoKP8C0N9qCUSwwAjAgVxWsePL51iNn8W2ny1vslQBVKss4X6VNV93bzN7Y
pTzexLphfNpq5ylQ8m23Gn1cFhII5SzJvxdtrZ/aw5GefPFKHq8DUlkDi/o13opwW1Rudh1/7e6i
QGThg51wgrH3lhgGKsRV2ZPRowf303ZguR2y9Cb6g7WXWuT4hfzHnreW2MCTy2v5vTN9s3RH8rw6
T0SNO53iN3FLiTX08m+lHto2cZiRbsfJtC7q4ueY7rMofv5Qtcl5/IyuoC/3cQ903bEId59UKzMY
umv695NMs84zzX8csSPDhWT+7Tgsvb6w0OK4tsUipFScSUYXO2qWUZAyURWFHNUpI6MyCPUVtyxR
6w6QLfIsISkvQ1Qgsr60Eu/tFlvu5y8Gw3YwVZe5gsekdIqIKo+StixkAg7sFZDu+DKh8CqjpUzG
FSbT4O66nnBTo+FV9PM1oHTKb+mbC20KpeH59wqWOA6P80vAwi30okV0T+GfgTCrXmDN9A6inzbj
tXkhBd81pgRkHSH6NG+2iSgpl4ArLZDP/SgiIFfopv3GGevpKW6mBOGTj7L1ay8ecl441bPadA4w
ly1qyjVk13dRWAF/Q6r5foqht1VxP99OY+WyYuK39t+cyUbbPaHXJoV7p+EzpLyDlWi4f7o7XJ95
G/vCQ9WDlBLg9ySIyVPRyEs9UBE4770bLaLEQ8LPmRzOEvKU01Z2njPkITN4qi5Y7hwuCea95Hz6
nfVMlN9nvZea5nlaVYU7OcWlTcGqfnqF1jUmel7Vzu5t43tqS/SY3fhJlOveToOUwG5ZvUEGZ8Vl
yvsIZPgTpQNpsjd3G/+XdjlqFH4Bn1E7rpNJ3Do3vGcA0n4BGpbyy1XVBMJWm4ISLKC2T7v1mQgk
YXf1goSB2GgWsn7zo120p1WfzA5uqIfRVPdYDNkt1tvuxseRPyI2G7sRaI+U4b4Mr8vnAK/xQ/ZQ
bhKCmy7hHe+5b+TAs7cN+PFwFfTjboS8ob0gRtlwDRhuNx9vARvnyTKf/v2FlhqYnmLO7OygE6NM
MvWQjcHRlQ7U1mbmMJLupQM0xU2z8x0EYh9ZwLvfPe2+s5y7+ZJIiUT1ZJfte99H/UUfcjvRcMxu
K5WNcSVFY4Wwbyoc6c33aoyPL1hKB7MuaXjdpwXPnoytM0Bmefl5y6zJVDhn9f6EgVm9vwldGzpJ
Rcv1MZ5o+Xz6ewQZPnfqW/IFdVa4hKIYiGsJa88rqTpnRWVlxw9wh3aKL0CNpR3YgNpJITrqN0NY
LNor1+ITn95qrsU1f56R5P7pjpyIQU2+oHFSewnCsdOu3BMbGh20EFIGyzUIbDnFnjAr9BAvtrJi
ECSswhcR5GcntzjfbdkiZdF1VlhVXPvTcuzmlu0s5NaHBxa5UL7dCOEjD31YFJumOz0HZOBuprDV
zwYpzI1Rn6DXuVWncio9rog6qk+gSTTLsYhXgJt179BcqMMfy6iwia46hioq58+WgIHx85l8PNIc
J8Wqqvtqrz51OpeHn9RL6CDT9WM0kBq/S8ZqtCaZRlhMLR2uSWc3+Ajsv2lNh82Ft3xGf17pCFdc
v4dMZD1kHYdyLsyh5wZZIqwniillJDKGt2SHfkZEs357oP/58CiGR7HqqxlIMuX/FPdjMvtUnY3k
9GtabkoYXsw6yyuYj3vW0wcaGlpRmJPy7Cwfcu+NrioQB45ZRgJ+QKBrKcXMWyMDq7u3St+cikUz
sLavLUyILtCX/g1/Vi0eUg6L+Ucae0AIHJfDyGQLeM/7LKEE7HDoSRCTOpRvskTmATZ6HRiDqDVi
i5ajpg9IC27m/mzhvhaUcqae1sZY6RjDCKoV9ZYJFlHl2Pj++Na2wBBBhSN8Zyd4N5vwn/dcK22A
9RlOhqY6eLE1RKF4/L3UK/Xo03TxT1H+qX4uZ/sjvadrip22KLIFkazxHxoNW4OFEaGfagi98BSZ
HfFyv4+i3R6ElzL4pJotn/RY6nQ/RRqmiRKMqBpqR/zmisLHCYIwsVOaI7UjJoadoSkPrwRP3/s4
FMJGHD/xgZOOzDHySq/rwoVLOEDg2wsLxZLBF+MeXlDrf5ErQ6e8Df5FpcHX96E9VlvWoWHIyLZf
PjmMwsqSilfSSDdjyN3+HjPVBWdH3NOG8ftg/VCat/kLbVNILhjbRXlMbnYv0hXMELTYqDME0agq
MQR3/V+OD8ayhGnvwgnjaR0KSVolk16J3xYG6WWPjxyK5ZfesItCG5J7h70/lr+6mhz35z9B+Oe7
gH+b3q88UfE5i2fJgimvv+k4qxy5PuPnQnS/wSibTI1CMOHB/RVEptCmrmbmtehzkgJYfLJ/HV2K
fq0FfBRHgfchpZczvxl6kwo/IBmkorYvHAT6UyCH/S9lx+ZVlhHT9RhTGC8schH2WK/3NGBk3YN0
hqXu2lPsYmnuylISAeZINjVZBMOcdYOPojd+qwJ8lMmdszi4y/Rd5T4fcNL8RPlC4Zis81kYrOrq
1bXONdnD2Zkdpt69NklwEDjEBTpvChAlShyoDes1EnRCS5g/PbIe0Sr1EoahHzhgBR8nR8xpfoQa
A2ELvnuj44fZEVKNdmrXdk76Rx7CnkqnLZcw5CLT8e2/1d4n9Le18lAjOBhVjSNPqYxqVGdOv+90
z/EeVaHTMpZopWqO+urdTiOgFYkUdW4cycOsPIGqc25QtlPaHbl+kkI+8Ja43ohgHSulzqD7rg19
e441QqOh8cVzOXKQ7KR1NUbTWKxbWXPzrPe8pcXQNO+ZM0aTjAgmO1pg0wvzzrzE3zHiDzzDiLw7
LcPnZrLgxl4uRF/Amvgc57aQsKX+xZ1DoeopcoBkTFFtRIXRxbebWJBJXvHETQYBrK/PPQK1/0dj
2LgyOvwScij1T6S+AXwZ/E/96/PjsbFtRzB1RYhI2USIxTFC9VzNzy4QweJJccLVX1ngrWJZwNG4
0s5BVlvSDhXvcUxLPs5JgGrrDNeZkBUHC6qChGSLZ4iy5SUAq851+llkJjtGNh7aQe5yfNUvZGXi
Poq4aupTbfQ2VZe3L4c3ZHX+hM349R2pUr7mFiosmG/k5QUF8KvDCUVQeWRw9zZ71cLjYF24+cDS
hcdR2p48A6uJtHrx25jxiYvlULgN3wsJl4VxsacJ6iLYE2JsEVZH5HsIm9lCRRweYJGA1rkXrX9V
W966Fh+8QPzTh+OJcjIOwK55ziN1OewT5udp/kseHK1upjRH63mw1C6+NTFVTW0zddpmnm4MsfXN
xCiOUbE/u8woN0L3f/bUoLoBb+JLo97+Qi7TCEXgiQScFGMkl90SaoOe4f5r+1hyze8bF+pwSMoE
t5vH3k+xIYqH+EMyt6Tv031CZEcuyJsWA/BTBCcWie2M1s5VkzV1vVKh+JLd/PgHM6prq+PgdVpa
KP9Y3Xj2ThNzOb9wdU4EHKiLooW+qSv0Ucyb9sn9PXFQKhWd9CuaOevHurHShyHGPfLTCwM8JzzA
Q5WHHtD6RRo0dH2NC6YKbemtXRyUWY5chnNgGKy/tbC/GPQV1XH22nBt8dmq5+Kr/A6nj+rPmoLp
+28uOLkhmiWed1Fa5x3okuUeRTZDDcVozRmeHXAE6aRWnKe+Xp/kELYNT58781JmyF6QMsE9+f8e
fPebURfrIFGdHW1EHd+sq1dArvUf3MNP2l7OacdRXuN3CwWj981u3cC7l/WgP7qEzJgAmr6IebEq
XGxWldGXS1AhBU8dIEWsLRRQH0X6FaKTMQKyGnQkX9nIXKTMkIWoqtgJLEoUHXDqDl9+CaB0pqBj
5PmpneFM+t4DxlnWwLPKEMakAugbg2XJXFSIzDR/U+C7Y2YCXAoZiL1AcKXMyRHp9xB8Nya/9QRe
4VoLms5Bq3GSp1zU1sCofg3x6grhWXFdVj4ISfTztjWNfQ31zEFx1/Lqsn8utwHkDLzzYvaqSBv5
v0R+WdwAFrd5IXXmWewka4CscS7Weq61tW1/Ueg5MMCqQJ+SZPLtCQQNiGS9msr6vTcX0m2Nc8Kq
+WRd41/K09XWVV5vG7GDRcgDeABBbZT/5lRZne9OJhWEJh2Pd4jKXyRtj3XefzpY4RHpENgchHBI
CZq1eUU64j1zMI2MWlK8tvJeQOCJ/zgvuS9H4VjyOttYO/88EOpUrJH1MYp0JHbxZoNX9y/BqREw
vAX9U7E+1K3EF0oyFS4z8TdxLt0Osr/8TB0lhKt907mqp4vDKO2Amz8dU0S7DLa256p2KtFxP84g
yTEWYJHzw5QVbhC85j5zbmsMyTiME5+pu1SnJjflcwMnq1krNk8Y1JWBmlBe2uSsmkZjIRrysIs1
DW1whU2fBSdiMRESHY33H8wPHGA81hQ17pF4wCGFSG6mNtNwUb+NA6bXZorDmEMmLf6BfgGQfx6q
2xT9YXuw/KEC0Qb4/8TXIYtMeObaFAPMwPM1ueH/q2GRBJuBLDQYHOOvOyCGXxgYxj9LZ+9U64rr
yaqrYtCQy/AtPyGW1xaMiLw5FeEoEQrt66kwqIkuUXZftATG4TDIVO239uMumZFgHWUksN3bLoCq
QcmAM7+Zb9SlUc7QWkD2p179PcRjDBRxvi66jJiWtm9EGGZ/i3R+JNQEZKfzppHwsACRetKhmFAa
4IpYOATGHTlPWaRfAmZyFCEe7Zp27x7FLOK1pnoEmfuBCuTtX+03L/QsLKEjELAccXBDD++PWcJ4
yR+Xzcw19BqvUsEOSduJk1aDRUxHKVAIrmB1XEPsQW0oaBVp0ju2+IcfQ30Nc9JqM4MW+VsJy9JL
4Ib2mfkizlZyb86Jv43u1NYdCnx9uioKSPNJoabHF4DFdax9d0uISC5KDT+JHQOZjWtIq1YMBOiw
hY9W4iZ3SPFboYzsOMjkZPmBtfuMpfGjVc3h0pWQk03S2vx6FTVTnZaKUrB2LUh7qrHt2OUA/9Ew
y7qbQDe59drGmedYTvjYiSFJewzHBN8C6jEd1GDMN7B1hPGK1r+0gAQsTDbKnNmqcB6h4rQZqVHl
pPB5v+ZDRLUPYqY8dHofgZCXjeJUbAdd1ZQ8xMJP0Uamm0jChwad3bcNGiihLvwrhB+72V3jnhcg
BcDmVPfM2+vgzpiBEE2LfWEgA9OuA15/hI1VbSN44ga+R6Gp6Ss8F5PLAgvx1DNkjrnjvDOlrzea
tV47ZAFdv2JD81L9UxFeXHN/+NBrqHj04HxCX0Mo6QiFUWBivOjzuJMo6y+VyEC+4L9EllJARzLQ
DE911LdeTdqyTWxBrTlQ8wrGcPiZgVsTmedJidbagT19F8bs/+xgDmVOo2ewxfV9syoGjlMwVmmg
Ul4iJv6lX4gQUMP6uU2Hcb5Rv7AZL4lkOzek
`protect end_protected
| mit |
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