repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
cnplab/blockmon | fw-combo/src/generator/comp/pseudorand_length_gen.vhd | 1 | 7738 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- pseudorand_length_gen.vhd : LFSR based pseudorandom generator module
-- Copyright (C) 2009 CESNET
-- Author(s): Pavol Korcek <korcek@liberouter.org>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: pseudorand_length_gen.vhd 12090 2009-11-24 13:57:11Z korcek $
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.lfsr_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity pseudorand_length_gen is
generic (
TAPS_1024 : LFSR_TAPS :=(10, 7);
TAPS_256 : LFSR_TAPS :=(8,6,5,4);
TAPS_128 : LFSR_TAPS :=(7,6);
TAPS_64 : LFSR_TAPS :=(6,5)
);
port (
RESET : in std_logic; -- reset
CLK : in std_logic; -- clock signal
S_EN : in std_logic; -- shift enable
F_EN : in std_logic; -- fill enable
DIN : in std_logic_vector(10 downto 0); -- seed
DOUT : out std_logic_vector(10 downto 0) -- data out
);
end entity pseudorand_length_gen;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture beh of pseudorand_length_gen is
-- pseudorandom output registers
signal reg_1024 : std_logic_vector(9 downto 0); -- 0 - 1023
signal reg_256 : std_logic_vector(7 downto 0); -- 0 - 255
signal reg_1024_and_256 : std_logic_vector(10 downto 0); -- 0 - 1278
signal reg_128 : std_logic_vector(6 downto 0); -- 0 - 127
signal reg_64 : std_logic_vector(5 downto 0); -- 0 - 63
signal reg_128_and_64 : std_logic_vector(7 downto 0); -- 0 - 190
signal reg_last : std_logic_vector(10 downto 0); -- 0 - 1468
signal reg_add : std_logic_vector(10 downto 0); -- 64 - 1532
-- init vectors
signal init_1024 : std_logic_vector(9 downto 0);
signal init_256 : std_logic_vector(7 downto 0);
signal init_128 : std_logic_vector(6 downto 0);
signal init_64 : std_logic_vector(5 downto 0);
begin
-- -------------------------------------------------------------------------
inst1024_u: entity work.lfsr_parallel
generic map(
LFSR_LENGTH => 10,
TAPS => TAPS_1024
)
port map(
CLK => CLK,
S_EN => S_EN,
F_EN => F_EN,
DIN => init_1024,
DOUT => reg_1024
);
init_1024 <= DIN(0) & DIN(2) & DIN(9) & DIN(8) & DIN(0) & DIN(1) & DIN(7) & DIN(5) & DIN(3) & DIN(3);
-- -------------------------------------------------------------------------
inst256_u: entity work.lfsr_parallel
generic map(
LFSR_LENGTH => 8,
TAPS => TAPS_256
)
port map(
CLK => CLK,
S_EN => S_EN,
F_EN => F_EN,
DIN => init_256,
DOUT => reg_256
);
init_256 <= DIN(7) & DIN(7) & DIN(6) & DIN(5) & DIN(1) & DIN(2) & DIN(2) & DIN(4);
-- -------------------------------------------------------------------------
inst128_u: entity work.lfsr_parallel
generic map(
LFSR_LENGTH => 7,
TAPS => TAPS_128
)
port map(
CLK => CLK,
S_EN => S_EN,
F_EN => F_EN,
DIN => init_128,
DOUT => reg_128
);
init_128 <= DIN(6) & DIN(2) & DIN(3) & DIN(3) & DIN(3) & DIN(5) & DIN(9);
-- -------------------------------------------------------------------------
inst64_u: entity work.lfsr_parallel
generic map(
LFSR_LENGTH => 6,
TAPS => TAPS_64
)
port map(
CLK => CLK,
S_EN => S_EN,
F_EN => F_EN,
DIN => init_64,
DOUT => reg_64
);
init_64 <= DIN(7) & DIN(8) & DIN(9) & DIN(9) & DIN(0) & DIN(4);
-- register ------------------------------------------------------
reg_1024_and_256p: process(RESET, CLK)
begin
if(CLK'event and CLK = '1') then
if (RESET = '1') then
reg_1024_and_256 <= (others => '1');
elsif (S_EN = '1' OR F_EN = '1') then
reg_1024_and_256 <= ( '0' & reg_1024) + ( "000" & reg_256);
end if;
end if;
end process;
-- register ------------------------------------------------------
reg_128_and_64p: process(RESET, CLK)
begin
if(CLK'event and CLK = '1') then
if (RESET = '1') then
reg_128_and_64 <= (others => '1');
elsif (S_EN = '1' OR F_EN = '1') then
reg_128_and_64 <= ( '0' & reg_128) + ( "00" & reg_64);
end if;
end if;
end process;
-- register ------------------------------------------------------
reg_lastp: process(RESET, CLK)
begin
if(CLK'event and CLK = '1') then
if (RESET = '1') then
reg_last <= (others => '0');
elsif (S_EN = '1' OR F_EN = '1') then
reg_last <= (reg_1024_and_256) + ( "000" & reg_128_and_64);
end if;
end if;
end process;
-- register ------------------------------------------------------
reg_add_64p: process(RESET, CLK)
begin
if(CLK'event and CLK = '1') then
if (RESET = '1') then
reg_add <= (others => '0');
elsif (S_EN = '1' OR F_EN = '1') then
reg_add <= reg_last + conv_std_logic_vector(56, reg_last'length);
end if;
end if;
end process;
DOUT <= reg_add;
end architecture beh;
| bsd-3-clause |
cnplab/blockmon | fw-combo/src/netcope-sim/models/ib_bfm_pkg.vhd | 1 | 36491 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- storage_init_pkg.vhd: Storage Init PKG
-- Copyright (C) 2006 CESNET
-- Author(s): Petr Kobiersky <xkobie00@stud.fit.vutbr.cz>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: ib_bfm_pkg.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use std.textio.all;
-- ----------------------------------------------------------------------------
-- Internal Bus BFM Package
-- ----------------------------------------------------------------------------
PACKAGE ib_bfm_pkg IS
CONSTANT MAX_TRANS_LENGTH : integer := 4095;
CONSTANT MAX_WRITE_LENGTH : integer := 4096;
CONSTANT MAX_INIT_DATA : integer := 4096;
-----------------------------------------------------------------------------
-- DATA TYPES
-----------------------------------------------------------------------------
-- Internal Bus Operation Type
TYPE IbOpType IS (LocalRead, LocalWrite, Completition, G2LR, L2GW, FileLogging, TranscriptLogging,
InitMemory, InitMemoryFromAddr, ShowMemory);
-- File Name Type
TYPE FileNameType IS RECORD
Len : integer;
Arr : string(1 to 256);
END RECORD;
TYPE DataType IS ARRAY (0 TO MAX_INIT_DATA/8) of std_logic_vector(63 downto 0);
-- Operation parameters
TYPE DiCmdType IS RECORD
SrcAddr : std_logic_vector(31 downto 0); -- Source Address
DstAddr : std_logic_vector(31 downto 0); -- Destination Address
LocalAddr : std_logic_vector(31 downto 0); -- Local Address (for GlobalTransactions)
GlobalAddr : std_logic_vector(63 downto 0); -- Global Address (for GlobalTransactions)
Length : integer; -- Length
Tag : integer; -- Tag
Data : DataType; -- Data
LastFlag : std_logic; -- Completition Last Flag
Enable : boolean;
FileName : FileNameType;
MemAddr : integer;
END RECORD;
-- Command record
TYPE IbCmdVType IS
RECORD
CmdOp : IbOpType; -- Operation
Di : DiCmdType; -- Operation input parameters
END RECORD;
-- Command REQ/ACK record
TYPE IbCmdType IS
RECORD
Req : std_logic;
ReqAck : std_logic;
Ack : std_logic;
END RECORD;
----------------------------------------------------------------------------
-- SIGNAL FOR SETTINGS BFM REQUESTS
----------------------------------------------------------------------------
SIGNAL IbCmd : IbCmdType := ('0', 'Z', 'Z');
----------------------------------------------------------------------------
-- BFM FUNCTIONS
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Functions is called by IB BFM model to obtain command parameters
PROCEDURE ReadIbCmdV (VARIABLE LclIbCmdV : OUT IbCmdVType);
----------------------------------------------------------------------------
-- Functions is called by IB BFM model to return results
PROCEDURE WriteIbCmdV (VARIABLE LclIbCmdV : IN IbCmdVType);
-----------------------------------------------------------------------------
-- Converts string type into the FileNameType
FUNCTION ConvFileName(FileName : string) RETURN FileNameType;
-----------------------------------------------------------------------------
-- Converts FileNameType into the string
FUNCTION ConvFileName(FileName : FileNameType) return string;
----------------------------------------------------------------------------
-- USER FUNCTIONS
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Local Read Transaction
PROCEDURE IBLocalRead (
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- Address from where are data readed
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination address of completition transaction
CONSTANT Length : IN integer; -- Number of bytes to be readed
CONSTANT Tag : IN integer; -- Transaction Tag
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Local Write Transaction
PROCEDURE IBLocalWrite (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Local Write Transaction with Data from File
PROCEDURE IBLocalWriteFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Local Write Transaction
PROCEDURE IBLocalWrite32 (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(31 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Local Write Transaction with Data from File
PROCEDURE IBLocalWriteFile32 (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (32 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Completition Transaction
PROCEDURE IBCompletition (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Completition Transaction with Data from File
PROCEDURE IBCompletitionFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Not Last Completition Transaction (op_done is not generated)
PROCEDURE IBNotLastCompletition (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Not Last Completition Transaction with Data from File (op_done is not generated)
PROCEDURE IBNotLastCompletitionFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Enable Transcript Logging
PROCEDURE SetTranscriptLogging (
CONSTANT Enable : IN boolean; -- Enable/Disable
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Enable File Logging
PROCEDURE SetFileLogging (
CONSTANT Enable : IN boolean; -- Enable/Disable
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Init HostPC Memory
PROCEDURE InitMemory (
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Init HostPC Memory Starting From Given Address
PROCEDURE InitMemoryFromAddr (
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Address : IN integer; -- Where to write data
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Show content of Memory
PROCEDURE ShowMemory (
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
END ib_bfm_pkg;
-- ----------------------------------------------------------------------------
-- Internal Bus BFM Package BODY
-- ----------------------------------------------------------------------------
PACKAGE BODY ib_bfm_pkg IS
-----------------------------------------------------------------------------
-- Command shared variable
SHARED VARIABLE IbCmdV : IbCmdVType;
-----------------------------------------------------------------------------
-- Functions is called by IB BFM model to obtain command parameters
PROCEDURE ReadIbCmdV (VARIABLE LclIbCmdV : OUT IbCmdVType) IS
BEGIN
LclIbCmdV := IbCmdV;
END;
-----------------------------------------------------------------------------
-- Functions is called by IB BFM model to return results
PROCEDURE WriteIbCmdV (VARIABLE LclIbCmdV : IN IbCmdVType) IS
BEGIN
IbCmdV := LclIbCmdV;
END;
-----------------------------------------------------------------------------
-- Converts string type into the FileNameType
FUNCTION ConvFileName(FileName : string) RETURN FileNameType IS
VARIABLE result : FileNameType;
BEGIN
result.Len := FileName'length;
result.Arr(1 to result.len) := FileName;
RETURN result;
END;
-----------------------------------------------------------------------------
-- Converts FileNameType into the string
FUNCTION ConvFileName(FileName : FileNameType) return string is
BEGIN
RETURN FileName.arr(1 to FileName.len);
END;
-- ----------------------------------------------------------------
-- Count Number of lines in file
FUNCTION FileLineCount(FileName : IN string) RETURN integer IS
FILE in_file : text;
VARIABLE in_line : line;
VARIABLE readFlag : boolean;
VARIABLE data : std_logic_vector(63 downto 0);
VARIABLE i : integer;
BEGIN
i:=0;
file_open(in_file, FileName, READ_MODE);
while not (endfile(in_file)) loop
readline(in_file, in_line);
i:=i+1;
end loop;
file_close(in_file);
RETURN i;
END;
-----------------------------------------------------------------------------
-- Local Read Transaction
PROCEDURE IBLocalRead (
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- Address from where are data readed
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination address of completition transaction
CONSTANT Length : IN integer; -- Number of bytes to be readed
CONSTANT Tag : IN integer; -- Transaction Tag
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := LocalRead;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------------
-- Local Write Transaction
PROCEDURE IBLocalWrite (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.Data(0) := Data;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------------
-- Local Write File Transaction
PROCEDURE IBLocalWriteFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
variable j : integer;
variable split_cnt : integer;
variable split_len : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
if (len <= MAX_WRITE_LENGTH) then
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := len;
IbCmdV.Di.Tag := Tag;
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(i/8), readFlag);
assert readFlag report "IBLocalWriteFile read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
else -- Split transactions
file_open(in_file, FileName, READ_MODE);
split_cnt := (len / MAX_WRITE_LENGTH);
if (len > (MAX_WRITE_LENGTH*split_cnt)) then
split_cnt := split_cnt+1;
end if;
i:=0;
WHILE (split_cnt > 0) loop
if (len > MAX_WRITE_LENGTH) then
split_len := MAX_WRITE_LENGTH;
else
split_len := len;
end if;
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr+(i*MAX_WRITE_LENGTH);
IbCmdV.Di.Length := split_len;
IbCmdV.Di.Tag := Tag;
j:=0;
while (j < split_len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(j/8), readFlag);
assert readFlag report "IBLocalWriteFile read error" severity ERROR;
j:=j+8;
end loop;
i:=i+1;
split_cnt:=split_cnt-1;
len:=len-MAX_WRITE_LENGTH;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END LOOP;
file_close(in_file);
END IF;
END;
-----------------------------------------------------------------------------
-- Local Write Transaction
PROCEDURE IBLocalWrite32 (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(31 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.Data(0) := X"00000000" & Data;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------------
-- Local Write File Transaction
PROCEDURE IBLocalWriteFile32 (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (32 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable data32a : std_logic_vector(31 downto 0);
variable data32b : std_logic_vector(31 downto 0);
variable readFlag : boolean;
variable len : integer;
variable i : integer;
variable j : integer;
variable split_cnt : integer;
variable split_len : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*4;
else
len := Length;
end if;
if (len <= MAX_WRITE_LENGTH) then
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Len;
IbCmdV.Di.Tag := Tag;
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, data32a, readFlag);
assert readFlag report "IBLocalWriteFile32 read error" severity ERROR;
if ((i + 4) < len) then
readline(in_file, in_line);
hread(in_line, data32b, readFlag);
assert readFlag report "IBLocalWriteFile32 read error" severity ERROR;
else
data32b:=X"00000000";
end if;
IbCmdV.Di.Data(i/8):= data32b&data32a;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
else
file_open(in_file, FileName, READ_MODE);
split_cnt := (len / MAX_WRITE_LENGTH);
if (len > (MAX_WRITE_LENGTH*split_cnt)) then
split_cnt := split_cnt+1;
end if;
i:=0;
WHILE (split_cnt > 0) loop
if (len > MAX_WRITE_LENGTH) then
split_len := MAX_WRITE_LENGTH;
else
split_len := len;
end if;
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr+(i*MAX_WRITE_LENGTH);
IbCmdV.Di.Length := split_len;
IbCmdV.Di.Tag := Tag;
j := 0;
while (j < split_len) loop
readline(in_file, in_line);
hread(in_line, data32a, readFlag);
assert readFlag report "IBLocalWriteFile32 read error" severity ERROR;
if ((j + 4) < len) then
readline(in_file, in_line);
hread(in_line, data32b, readFlag);
assert readFlag report "IBLocalWriteFile32 read error" severity ERROR;
else
data32b:=X"00000000";
end if;
IbCmdV.Di.Data(j/8):= data32b&data32a;
j:=j+8;
end loop;
i:=i+1;
split_cnt:=split_cnt-1;
len:=len-MAX_WRITE_LENGTH;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END LOOP;
file_close(in_file);
end if;
END;
-----------------------------------------------------------------------
-- Completition Transaction
PROCEDURE IBCompletition (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := Completition;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.Data(0) := Data;
IbCmdV.Di.LastFlag := '1';
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Completition Transaction with Data from File
PROCEDURE IBCompletitionFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
assert (len <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := Completition;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := len;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.LastFlag := '1';
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(i/8), readFlag);
assert readFlag report "IBCompletitionFile read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Not Last Completition Transaction (op_done is not generated)
PROCEDURE IBNotLastCompletition (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := Completition;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.Data(0) := Data;
IbCmdV.Di.LastFlag := '0';
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Not Last Completition Transaction with Data from File (op_done is not generated)
PROCEDURE IBNotLastCompletitionFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
assert (len <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := Completition;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := len;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.LastFlag := '0';
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(i/8), readFlag);
assert readFlag report "IBNotLastCompletitionFile read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Enable Transcript Logging
PROCEDURE SetTranscriptLogging (
CONSTANT Enable : IN boolean; -- Enable/Disable
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
IbCmdV.CmdOp := TranscriptLogging;
IbCmdV.Di.Enable := Enable;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Enable File Logging
PROCEDURE SetFileLogging (
CONSTANT Enable : IN boolean; -- Enable/Disable
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
IbCmdV.CmdOp := FileLogging;
IbCmdV.Di.Enable := Enable;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Init HostPC Memory
PROCEDURE InitMemory (
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
assert (len <= MAX_INIT_DATA) report "Transaction length exceed 4096 bytes memory init limit" severity ERROR;
IbCmdV.CmdOp := InitMemory;
IbCmdV.Di.Length := Length;
IbCmdV.Di.MemAddr := 0;
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(i/8), readFlag);
assert readFlag report "InitMemory read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Init HostPC Memory Starting From Given Address
PROCEDURE InitMemoryFromAddr (
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Address : IN integer; -- Where to write data
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
assert (len <= MAX_INIT_DATA) report "Transaction length exceed 4096 bytes memory init limit" severity ERROR;
IbCmdV.CmdOp := InitMemoryFromAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.MemAddr := Address;
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data((i)/8), readFlag);
assert readFlag report "InitMemoryFromAddr read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Show content of Memory
PROCEDURE ShowMemory (
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
IbCmdV.CmdOp := ShowMemory;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
END ib_bfm_pkg;
| bsd-3-clause |
cnplab/blockmon | fw-combo/src/netcope-sim/models/mi_bfm_pkg.vhd | 1 | 5784 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- fl_bfm_pkg.vhd: Support package for bfm_sim
-- Copyright (C) 2007 CESNET
-- Author(s): Vlastimil Kosar <xkosar02@stud.fit.vutbr.cz>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mi_bfm_pkg.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use std.textio.all;
-- ----------------------------------------------------------------------------
-- MI SIM Package
-- ----------------------------------------------------------------------------
package mi_bfm_pkg is
type TTransactionDirection is (READ, WRITE);
type TTransaction is record
DATA : std_logic_vector(31 downto 0);
ADDR : std_logic_vector(31 downto 0);
BE : std_logic_vector(3 downto 0);
DIRECTION : TTransactionDirection;
end record;
type TCommandStatus is record
BUSY : std_logic;
REQ_ACK : std_logic;
REQ : std_logic;
end record;
signal status : TCommandStatus := ('0', '0', '0');
-- internaly used to synchronize model
procedure WriteTransaction(variable trans : in TTransaction);
procedure ReadTransaction(variable trans : out TTransaction);
-- write data on address addr with byte enables be. status_cnt have to be status(x) and mi_sim_id have to be x
procedure MI32Write(constant addr : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant be : in std_logic_vector(3 downto 0);
signal status : inout TCommandStatus);
-- read data from address addr with byte enables be. status_cnt have to be status(x) and mi_sim_id have to be x
procedure MI32Read(constant addr : in std_logic_vector(31 downto 0);
variable data : inout std_logic_vector(31 downto 0);
constant be : in std_logic_vector(3 downto 0);
signal status : inout TCommandStatus);
end mi_bfm_pkg;
-- ----------------------------------------------------------------------------
-- MI SIM PKG BODY
-- ----------------------------------------------------------------------------
package body mi_bfm_pkg is
shared variable transaction : TTransaction;
procedure ReadTransaction(variable trans : out TTransaction) is
begin
trans := transaction;
end procedure;
procedure WriteTransaction(variable trans : in TTransaction) is
begin
transaction := trans;
end procedure;
procedure MI32Write(constant addr : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant be : in std_logic_vector(3 downto 0);
signal status : inout TCommandStatus) is
begin
transaction.ADDR := addr;
transaction.DATA := data;
transaction.BE := be;
transaction.DIRECTION := WRITE;
status.REQ <= '1';
wait on status.REQ_ACK;
status.REQ <= '0';
wait until status.BUSY = '0';
end procedure;
procedure MI32Read(constant addr : in std_logic_vector(31 downto 0);
variable data : inout std_logic_vector(31 downto 0);
constant be : in std_logic_vector(3 downto 0);
signal status : inout TCommandStatus) is
begin
transaction.ADDR := addr;
transaction.BE := be;
transaction.DIRECTION := READ;
status.REQ <= '1';
wait on status.REQ_ACK;
status.REQ <= '0';
wait until status.BUSY = '0';
data := transaction.data;
end procedure;
end mi_bfm_pkg;
| bsd-3-clause |
cnplab/blockmon | fw-combo/src/common/simple_fifo.vhd | 1 | 3260 | -- -----------------------------------------------------------------
-- Simple synchronous FIFO
-- -----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity SIMPLE_FIFO is
generic (
DATA_WIDTH : integer := 64;
DEPTH : integer := 512
);
port (
-- global FPGA clock
CLK : in std_logic;
-- global synchronous reset
RESET : in std_logic;
-- Write interface
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
WRITE_EN : in std_logic;
-- Read interface
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
READ_EN : in std_logic;
-- Control
STATE_FULL : out std_logic;
STATE_EMPTY : out std_logic
);
end entity SIMPLE_FIFO;
architecture behavioral of SIMPLE_FIFO is
-- -----------------------------------------------------------------
-- Signals
-- -----------------------------------------------------------------
type ram_type is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal fifo : ram_type;
signal read_ptr : integer range 0 to DEPTH-1;
signal write_ptr : integer range 0 to DEPTH-1;
signal depth_cur : integer range 0 to DEPTH;
begin
-- -----------------------------------------------------------------
-- Logic
-- -----------------------------------------------------------------
-- FIFO read and write
process(CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
write_ptr <= 0;
read_ptr <= 0;
DATA_OUT <= (others => '0');
else
-- Read in the FIFO
if (read_en = '1') then
data_out <= fifo(read_ptr);
-- Increment the pointer
if (read_ptr < DEPTH - 1) then
read_ptr <= read_ptr + 1;
else
read_ptr <= 0;
end if;
end if;
-- Write in the FIFO
if (write_en = '1') then
fifo(write_ptr) <= data_in;
-- Increment the pointer
if (write_ptr < DEPTH - 1) then
write_ptr <= write_ptr + 1;
else
write_ptr <= 0;
end if;
end if;
end if;
end if;
end process;
-- FIFO depth management
process(CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
depth_cur <= 0;
else
if (write_en = '1' and read_en = '0') then
depth_cur <= depth_cur + 1;
elsif (write_en = '0' and read_en = '1') then
depth_cur <= depth_cur - 1;
end if;
end if;
end if;
end process;
-- FIFO full/empty
STATE_FULL <= '1' when (depth_cur >= DEPTH) else '0';
STATE_EMPTY <= '1' when (depth_cur <= 0) else '0';
end;
| bsd-3-clause |
cnplab/blockmon | fw-combo/src/IPFIX/comp/barrel_bit_shifter.vhd | 1 | 3942 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- barrel_bit_shifter.vhd: Barrel shifter with generic data width
-- Copyright (C) 2010 CESNET
-- Author(s): Viktor Pus <pus@liberouter.org>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: barrel_bit_shifter.vhd 13189 2010-03-10 15:07:35Z pus $
--
-- TODO:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- ENTITY DECLARATION -- Barrel shifter --
-- ----------------------------------------------------------------------------
entity BARREL_BIT_SHIFTER is
generic (
DATA_WIDTH : integer := 8;
-- set true to shift left, false to shift right
SHIFT_LEFT : boolean := true
);
port (
-- Input interface ------------------------------------------------------
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
SEL : in std_logic_vector(log2(DATA_WIDTH)-1 downto 0)
);
end BARREL_BIT_SHIFTER;
-- ----------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION --
-- ----------------------------------------------------------------------------
architecture barrel_bit_shifter_arch of BARREL_BIT_SHIFTER is
begin
multiplexors: for i in 0 to DATA_WIDTH-1 generate
process (DATA_IN, SEL)
variable sel_aux: integer;
begin
if (SHIFT_LEFT) then
sel_aux := conv_integer('0'&SEL);
else
sel_aux := conv_integer('0'&(0-SEL));
end if;
DATA_OUT(i) <= DATA_IN((DATA_WIDTH-sel_aux+i) mod (DATA_WIDTH));
end process;
end generate;
end barrel_bit_shifter_arch;
| bsd-3-clause |
cnplab/blockmon | fw-combo/src/netcope-sim/models/fl_bfm_rdy_pkg.vhd | 1 | 4573 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- fl_bfm_rdy_pkg.vhd: RDY signal functions package for sim and monitor
-- Copyright (C) 2007 CESNET
-- Author(s): Vlastimil Kosar <xkosar02@stud.fit.vutbr.cz>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: fl_bfm_rdy_pkg.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
-- ----------------------------------------------------------------------------
-- RDY functions package
-- ----------------------------------------------------------------------------
PACKAGE fl_bfm_rdy_pkg IS
TYPE RDYSignalDriver IS (EVER, ONOFF, RND);
PROCEDURE DriveRdyN50_50(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic);
PROCEDURE DriveRdyNAll(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic);
PROCEDURE DriveRdyNRnd(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic);
PROCEDURE SetSeed(Seed : in integer);
END fl_bfm_rdy_pkg;
-- ----------------------------------------------------------------------------
-- FrameLink Bus BFM Package BODY
-- ----------------------------------------------------------------------------
PACKAGE BODY fl_bfm_rdy_pkg IS
SHARED VARIABLE number: integer := 399751;
PROCEDURE SetSeed(Seed : in integer) IS
BEGIN
number := Seed;
END;
PROCEDURE Random(RND : out integer) IS
BEGIN
number := number * 69069 + 1;
RND := (number rem 7);
END;
PROCEDURE DriveRdyN50_50(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic) IS
BEGIN
RDY_N <= '0';
wait until (CLK'event and CLK='1');
RDY_N <= '1';
wait until (CLK'event and CLK='1');
END;
PROCEDURE DriveRdyNAll(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic) IS
BEGIN
RDY_N <= '0';
wait until (CLK'event and CLK='1');
END;
PROCEDURE DriveRdyNRnd(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic) IS
VARIABLE RNDVAL: integer;
VARIABLE VALUE: std_logic;
BEGIN
Random(RNDVAL);
if (RNDVAL rem 2 = 0) then
VALUE := '0';
else
VALUE := '1';
end if;
Random(RNDVAL);
for i in 1 to RNDVAL loop
RDY_N <= VALUE;
wait until (CLK'event and CLK='1');
end loop;
END;
END fl_bfm_rdy_pkg;
| bsd-3-clause |
cnplab/blockmon | fw-combo/src/IPFIX/comp/mi32_async_arch_norec.vhd | 1 | 6971 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- mi32_async_arch_norec.vhd: Architecture of mi32_async component without
-- records
-- Copyright (C) 2006 CESNET
-- Author(s): Viktor Pus <pus@liberouter.org>
-- Jiri Matousek <xmatou06@stud.fit.vutbr.cz>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mi32_async_arch_norec.vhd 6111 2008-10-26 22:49:39Z xmatou06 $
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture full of MI32_ASYNC_NOREC is
-- Asynchronous signals
signal req : std_logic;
signal regasync_req_fall : std_logic;
signal regasync_req_rise : std_logic;
signal ack : std_logic;
signal regasync_ack_fall : std_logic;
signal regasync_ack_rise : std_logic;
-- Control signals
signal slave_en : std_logic;
signal done : std_logic;
signal mi_m_ardy2 : std_logic;
signal mi_s_drdy2 : std_logic;
-- Delayed signals in simulation
signal s_drdy_d : std_logic;
signal s_drd_d : std_logic_vector(31 downto 0);
-- Reigsters in direction Master -> Slave
signal reg_dwr : std_logic_vector(31 downto 0);
signal reg_addr : std_logic_vector(31 downto 0);
signal reg_rd : std_logic;
signal reg_wr : std_logic;
signal reg_be : std_logic_vector(3 downto 0);
-- Registers in direction Slave -> Master
signal reg_drd : std_logic_vector(31 downto 0);
signal reg_drdy : std_logic;
begin
-- regasync_req_fall register
process(RESET, CLK_S)
begin
if (RESET = '1') then
regasync_req_fall <= '0';
elsif (CLK_S'event AND CLK_S = '0') then
regasync_req_fall <= req;
end if;
end process;
-- regasync_req_rise register
process(RESET, CLK_S)
begin
if (RESET = '1') then
regasync_req_rise <= '0';
elsif (CLK_S'event AND CLK_S = '1') then
regasync_req_rise <= regasync_req_fall;
end if;
end process;
-- regasync_ack_fall register
process(RESET, CLK_M)
begin
if (RESET = '1') then
regasync_ack_fall <= '0';
elsif (CLK_M'event AND CLK_M = '0') then
regasync_ack_fall <= ack;
end if;
end process;
-- regasync_ack_rise register
process(RESET, CLK_M)
begin
if (RESET = '1') then
regasync_ack_rise <= '0';
elsif (CLK_M'event AND CLK_M = '1') then
regasync_ack_rise <= regasync_ack_fall;
end if;
end process;
fsm_master : entity work.MI32_ASYNC_FSMM
port map(
RESET => RESET,
CLK => CLK_M,
RD => MI_M_RD,
WR => MI_M_WR,
ACK => regasync_ack_rise,
REQ => req,
ARDY => mi_m_ardy2,
DONE => done
);
fsm_slave : entity work.MI32_ASYNC_FSMS
port map(
RESET => RESET,
CLK => CLK_S,
REQ => regasync_req_rise,
DRDY => mi_s_drdy2,
ARDY => MI_S_ARDY,
ACK => ack,
EN => slave_en
);
-- process(CLK_S)
-- begin
-- if reg_wr = '1' then
-- mi_s_drdy2 <= '1';
-- else
-- mi_s_drdy2 <= MI_S.DRDY;
-- end if;
-- end process;
mi_s_drdy2 <= '1' when reg_wr = '1' else
MI_S_DRDY;
s_drdy_d <= MI_S_DRDY
-- pragma translate off
after 1 ns
-- pragma translate on
;
s_drd_d <= MI_S_DRD
-- pragma translate off
after 1 ns
-- pragma translate on
;
reg_master_to_slave : process(CLK_M, RESET)
begin
if RESET = '1' then
reg_dwr <= (others => '0');
reg_addr <= (others => '0');
reg_rd <= '0';
reg_wr <= '0';
reg_be <= (others => '0');
elsif CLK_M'event and CLK_M = '1' then
if mi_m_ardy2 = '1' and (MI_M_RD = '1' or MI_M_WR = '1') then
reg_dwr <= MI_M_DWR;
reg_addr <= MI_M_ADDR;
reg_rd <= MI_M_RD;
reg_wr <= MI_M_WR;
reg_be <= MI_M_BE;
end if;
end if;
end process;
reg_slave_to_master : process(CLK_S, RESET)
begin
if RESET = '1' then
reg_drd <= (others => '0');
elsif CLK_S'event and CLK_S = '1' then
if mi_s_drdy2 = '1' then
reg_drd <= s_drd_d;
end if;
end if;
end process;
reg_drdy_slave_to_master : process(CLK_S, RESET)
begin
if RESET = '1' then
reg_drdy <= '0';
elsif CLK_S'event and CLK_S = '1' then
if mi_s_drdy2 = '1' then
reg_drdy <= s_drdy_d;
end if;
end if;
end process;
-- Port mapping
MI_M_ARDY <= mi_m_ardy2 and (MI_M_RD or MI_M_WR);
MI_M_DRDY <= reg_drdy when done = '1' else
'0';
MI_M_DRD <= reg_drd;
MI_S_DWR <= reg_dwr;
MI_S_ADDR <= reg_addr;
MI_S_RD <= reg_rd when slave_en = '1' else
'0';
MI_S_WR <= reg_wr when slave_en = '1' else
'0';
MI_S_BE <= reg_be;
end architecture full;
| bsd-3-clause |
creationix/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
zephyrer/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/xps_icapi_v1_01_a/hdl/vhdl/icap_wrapper.vhd | 3 | 10911 | -------------------------------------------------------------------------------
-- icap_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESIM -- Parameter is TRUE for ReSim-based simulation
-- C_FAMILY -- target FPGA family
-------------------------------------------------------------------------------
-- --inputs
--
-- Icap_clk -- ICAP clock
-- Icap_ce -- ICAP chip enable
-- Icap_we -- ICAP write enable
-- Icap_datain -- ICAP configuration data in
--
-- --outputs
--
-- Icap_busy -- ICAP busy qualifier
-- Icap_dataout -- ICAP configuration readback data out
-------------------------------------------------------------------------------
entity icap_wrapper is
generic(
C_RESIM : integer := 1;
C_GEN_BITSWAP : integer := 1;
C_FAMILY : string := "virtex5"
);
port(
Icap_clk : in std_logic;
Icap_ce : in std_logic;
Icap_we : in std_logic;
Icap_datain : in std_logic_vector(31 downto 0);
Icap_busy : out std_logic;
Icap_dataout : out std_logic_vector(31 downto 0)
);
attribute KEEP : string;
attribute KEEP of Icap_ce : signal is "TRUE";
attribute KEEP of Icap_we : signal is "TRUE";
attribute KEEP of Icap_datain : signal is "TRUE";
attribute KEEP of Icap_dataout : signal is "TRUE";
attribute KEEP of Icap_busy : signal is "TRUE";
end icap_wrapper;
architecture imp of icap_wrapper is
component ICAP_VIRTEX4 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX5 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX6 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CSB : in std_logic;
RDWRB : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX4_WRAPPER is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX5_WRAPPER is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX6_WRAPPER is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CSB : in std_logic;
RDWRB : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
signal Icap_datain_bs : std_logic_vector(31 downto 0);
signal Icap_dataout_bs : std_logic_vector(31 downto 0);
begin -- architecture imp
-----------------------------------------------------------------------------
-- GEN_UNISIM
-----------------------------------------------------------------------------
-- Implement using ICAP instance on chip
-- Simulate using unisim model (black box)
GEN_UNISIM : if C_RESIM = 0 generate
GEN_VIRTEX4 : if (C_FAMILY="virtex4") generate
ICAP_VERTEX4_I : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X32")
port map (
CLK => Icap_clk,
CE => Icap_ce,
WRITE => Icap_we,
I => Icap_datain_bs,
BUSY => Icap_busy,
O => Icap_dataout_bs
);
end generate GEN_VIRTEX4;
GEN_VIRTEX5 : if (C_FAMILY="virtex5") generate
ICAP_VERTEX5_I : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => "X32")
port map (
CLK => icap_clk,
CE => icap_ce,
WRITE => icap_we,
I => icap_datain_bs,
BUSY => icap_busy,
O => icap_dataout_bs
);
end generate GEN_VIRTEX5;
GEN_VIRTEX6 : if (C_FAMILY="virtex6") generate
ICAP_VERTEX6_I : ICAP_VIRTEX6
generic map (
ICAP_WIDTH => "X32")
port map (
CLK => icap_clk,
CSB => icap_ce,
RDWRB => icap_we,
I => icap_datain_bs,
BUSY => icap_busy,
O => icap_dataout_bs
);
end generate GEN_VIRTEX6;
end generate GEN_UNISIM;
-----------------------------------------------------------------------------
-- GEN_RESIM:
-----------------------------------------------------------------------------
-- Implement using ICAP instance on chip
-- Simulate using ReSim model
GEN_RESIM : if C_RESIM = 1 generate
GEN_VIRTEX4 : if (C_FAMILY="virtex4") generate
ICAP_VIRTEX4_I : ICAP_VIRTEX4_WRAPPER
generic map (
ICAP_WIDTH => "X32"
)
port map (
CLK => icap_clk, -- I: clock
CE => icap_ce, -- I: clock enable
WRITE => icap_we, -- I: write enable
I => icap_datain_bs, -- I: configuration data
BUSY => icap_busy, -- O: busy
O => icap_dataout_bs -- O: configuration readback data
);
end generate GEN_VIRTEX4;
GEN_VIRTEX5 : if (C_FAMILY="virtex5") generate
ICAP_VIRTEX5_I : ICAP_VIRTEX5_WRAPPER
generic map (
ICAP_WIDTH => "X32"
)
port map (
CLK => icap_clk, -- I: clock
CE => icap_ce, -- I: clock enable
WRITE => icap_we, -- I: write enable
I => icap_datain_bs, -- I: configuration data
BUSY => icap_busy, -- O: busy
O => icap_dataout_bs -- O: configuration readback data
);
end generate GEN_VIRTEX5;
GEN_VIRTEX6 : if (C_FAMILY="virtex6") generate
ICAP_VIRTEX6_I : ICAP_VIRTEX6_WRAPPER
generic map (
ICAP_WIDTH => "X32"
)
port map (
CLK => icap_clk, -- I: clock
CSB => icap_ce, -- I: clock enable
RDWRB => icap_we, -- I: write enable
I => icap_datain_bs, -- I: configuration data
BUSY => icap_busy, -- O: busy
O => icap_dataout_bs -- O: configuration readback data
);
end generate GEN_VIRTEX6;
end generate GEN_RESIM;
-----------------------------------------------------------------------------
-- GEN_BITSWAP:
-----------------------------------------------------------------------------
----SystemVerilog Syntax
----
----generate begin : gen_i_bitswap
---- genvar j;
---- for (j = 0; j <= 3; j = j + 1) begin : mirror_j
---- genvar i;
---- for (i = 0; i <= 7; i = i + 1) begin : mirror_i
---- assign I_bs[j * 8 + i] = I[j * 8 + 7 - i];
---- end
---- end
----end endgenerate
----
----generate begin : gen_o_bitswap
---- genvar j;
---- for (j = 0; j <= 3; j = j + 1) begin : mirror_j
---- genvar i;
---- for (i = 0; i <= 7; i = i + 1) begin : mirror_i
---- assign O[j * 8 + i] = O_bs[j * 8 + 7 - i];
---- end
---- end
----end endgenerate
GEN_NO_BITSWAP : if ((C_FAMILY = "virtex4") or (C_GEN_BITSWAP = 0)) generate
Icap_datain_bs <= Icap_datain;
Icap_dataout <= Icap_dataout_bs;
end generate GEN_NO_BITSWAP;
GEN_VERITEX5_BS : if ((C_FAMILY = "virtex5") and (C_GEN_BITSWAP = 1)) generate
process(Icap_datain) begin
for j in 0 to 3 loop
for i in 0 to 7 loop
Icap_datain_bs(j * 8 + i) <= Icap_datain(j * 8 + 7 - i);
end loop;
end loop;
end process;
process(Icap_dataout_bs) begin
for j in 0 to 3 loop
for i in 0 to 7 loop
Icap_dataout(j * 8 + i) <= Icap_dataout_bs(j * 8 + 7 - i);
end loop;
end loop;
end process;
end generate GEN_VERITEX5_BS;
GEN_VERITEX6_BS : if ((C_FAMILY = "virtex6") and (C_GEN_BITSWAP = 1)) generate
process(Icap_datain) begin
for j in 0 to 3 loop
for i in 0 to 7 loop
Icap_datain_bs(j * 8 + i) <= Icap_datain(j * 8 + 7 - i);
end loop;
end loop;
end process;
process(Icap_dataout_bs) begin
for j in 0 to 3 loop
for i in 0 to 7 loop
Icap_dataout(j * 8 + i) <= Icap_dataout_bs(j * 8 + 7 - i);
end loop;
end loop;
end process;
end generate GEN_VERITEX6_BS;
end architecture imp;
| bsd-3-clause |
zephyrer/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/xps_icapi_v1_01_a/hdl/vhdl/icap_virtex_wrapper.vhd | 6 | 4458 |
---------------------------------------------------------------------
--
-- ICAP_VIRTEX4_WRAPPER
--
-- Description: Instantiating ICAP_VIRTEX4
-- Simulation/Synthesis: Synthesis
-- Reference: $XILINX_HOME/vhdl/src/unisims/primitive/ICAP_VIRTEX4.vhd
--
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ICAP_VIRTEX4_WRAPPER is
generic(
ICAP_WIDTH: string := "X8" -- "X8" or "X32"
);
port(
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0);
CE : in std_logic;
CLK : in std_logic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_logic
);
end ICAP_VIRTEX4_WRAPPER;
architecture synth of ICAP_VIRTEX4_WRAPPER is
component ICAP_VIRTEX4 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
begin
i_ICAP_VIRTEX4 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => ICAP_WIDTH
)
port map (
BUSY => BUSY,
O => O,
CE => CE,
CLK => CLK,
I => I,
WRITE => WRITE
);
end synth;
---------------------------------------------------------------------
--
-- ICAP_VIRTEX5_WRAPPER
--
-- Description: Instantiating ICAP_VIRTEX5
-- Simulation/Synthesis: Synthesis
-- Reference: $XILINX_HOME/vhdl/src/unisims/primitive/ICAP_VIRTEX5.vhd
--
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ICAP_VIRTEX5_WRAPPER is
generic(
ICAP_WIDTH: string := "X8" -- "X8", "X16" or "X32"
);
port(
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0);
CE : in std_logic;
CLK : in std_logic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_logic
);
end ICAP_VIRTEX5_WRAPPER;
architecture synth of ICAP_VIRTEX5_WRAPPER is
component ICAP_VIRTEX5 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
begin
i_ICAP_VIRTEX5 : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => ICAP_WIDTH
)
port map (
BUSY => BUSY,
O => O,
CE => CE,
CLK => CLK,
I => I,
WRITE => WRITE
);
end synth;
---------------------------------------------------------------------
--
-- ICAP_VIRTEX6_WRAPPER
--
-- Description: Instantiating ICAP_VIRTEX6
-- Simulation/Synthesis: Synthesis
-- Reference: $XILINX_HOME/vhdl/src/unisims/primitive/ICAP_VIRTEX6.vhd
--
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ICAP_VIRTEX6_WRAPPER is
generic(
DEVICE_ID : bit_vector := X"04244093";
ICAP_WIDTH : string := "X8"; -- "X8", "X16" or "X32"
SIM_CFG_FILE_NAME : string := "NONE"
);
port(
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0);
CSB : in std_logic;
CLK : in std_logic;
I : in std_logic_vector(31 downto 0);
RDWRB : in std_logic
);
end ICAP_VIRTEX6_WRAPPER;
architecture synth of ICAP_VIRTEX6_WRAPPER is
component ICAP_VIRTEX6 is
generic(
DEVICE_ID : bit_vector := X"04244093";
ICAP_WIDTH : string := "X8";
SIM_CFG_FILE_NAME : string := "NONE"
);
port(
CLK : in std_logic;
CSB : in std_logic;
RDWRB : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
begin
i_ICAP_VIRTEX6 : ICAP_VIRTEX6
generic map (
DEVICE_ID => DEVICE_ID,
ICAP_WIDTH => ICAP_WIDTH,
SIM_CFG_FILE_NAME => SIM_CFG_FILE_NAME
)
port map (
BUSY => BUSY,
O => O,
CSB => CSB,
CLK => CLK,
I => I,
RDWRB => RDWRB
);
end synth;
| bsd-3-clause |
zephyrer/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/xps_math_v1_01_a/hdl/vhdl/xps_math.vhd | 3 | 24271 | ------------------------------------------------------------------------------
-- xps_math.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library xps_math_v1_01_a;
use xps_math_v1_01_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity xps_math is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity xps_math;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of xps_math is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant CLK_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200";
constant CLK_HIGHADDR : std_logic_vector := C_BASEADDR or X"000002FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address
ZERO_ADDR_PAD & CLK_BASEADDR, -- soft clock space base address
ZERO_ADDR_PAD & CLK_HIGHADDR -- soft clock space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_REG : integer := 2;
constant RST_NUM_REG : integer := 1;
constant CLK_NUM_REG : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_REG), -- number of ce for user logic slave space
1 => pad_power2(RST_NUM_REG), -- number of ce for soft reset space
2 => pad_power2(CLK_NUM_REG) -- number of ce for soft clock space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_CS_INDEX : integer := 0;
constant USER_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant CLK_CS_INDEX : integer := 2;
constant CLK_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, CLK_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal clk_Bus2IP_Clk : std_logic;
signal clk_IP2Bus_WrAck : std_logic;
signal clk_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
------------------------------------------
-- Component declarations
------------------------------------------
component soft_reset
generic
(
C_SIPIF_DWIDTH : integer := 32;
C_RESET_WIDTH : integer := 4
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end component;
component soft_clock
generic
(
C_SIPIF_DWIDTH : integer := 32
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Clock Output
Clk2IP_Clk : out std_logic;
-- Status Reply Outputs to the Bus
Clk2Bus_WrAck : out std_logic;
Clk2Bus_Error : out std_logic;
Clk2Bus_ToutSup : out std_logic
);
end component;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate soft_clock
------------------------------------------
SOFT_CLOCK_I : soft_clock
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(CLK_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Clk2IP_Clk => clk_Bus2IP_Clk,
Clk2Bus_WrAck => clk_IP2Bus_WrAck,
Clk2Bus_Error => clk_IP2Bus_Error,
Clk2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity xps_math_v1_01_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => clk_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "100" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck or clk_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error or clk_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| bsd-3-clause |
zephyrer/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/ipif_v1_00_a/hdl/vhdl/plbv46_master_burst_wrapper_128.vhd | 3 | 19674 | ------------------------------------------------------------------------------
-- plbv46_master_burst_wrapper.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_master_burst_v1_01_a;
use plbv46_master_burst_v1_01_a.plbv46_master_burst;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plbv46_master_burst_wrapper is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 128;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_INHIBIT_CC_BLE_INCLUSION : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER GENERICS BELOW THIS LINE ---------------
-- ADD USER GENERICS ABOVE THIS LINE ---------------
);
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
MPLB_Clk : in std_logic ;
MPLB_Rst : in std_logic ;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8) - 1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_abort : out std_logic;
M_lockErr : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_UABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER PORTS BELOW THIS LINE ------------------
Bus2IP_Mst_Clk : out std_logic;
Bus2IP_Mst_Reset : out std_logic;
IP2Bus_MstRd_Req : in std_logic;
IP2Bus_MstWr_Req : in std_logic;
IP2Bus_Mst_Addr : in std_logic_vector(0 to C_MPLB_AWIDTH-1);
IP2Bus_Mst_Length : in std_logic_vector(0 to 11);
IP2Bus_Mst_BE : in std_logic_vector(0 to 128/8 -1);
IP2Bus_Mst_Type : in std_logic;
IP2Bus_Mst_Lock : in std_logic;
IP2Bus_Mst_Reset : in std_logic;
Bus2IP_Mst_CmdAck : out std_logic;
Bus2IP_Mst_Cmplt : out std_logic;
Bus2IP_Mst_Error : out std_logic;
Bus2IP_Mst_Rearbitrate : out std_logic;
Bus2IP_Mst_Cmd_Timeout : out std_logic;
Bus2IP_MstRd_d : out std_logic_vector(0 to 128-1);
Bus2IP_MstRd_rem : out std_logic_vector(0 to 128/8-1);
Bus2IP_MstRd_sof_n : out std_logic;
Bus2IP_MstRd_eof_n : out std_logic;
Bus2IP_MstRd_src_rdy_n : out std_logic;
Bus2IP_MstRd_src_dsc_n : out std_logic;
IP2Bus_MstRd_dst_rdy_n : in std_logic;
IP2Bus_MstRd_dst_dsc_n : in std_logic;
IP2Bus_MstWr_d : in std_logic_vector(0 to 128-1);
IP2Bus_MstWr_rem : in std_logic_vector(0 to 128/8-1);
IP2Bus_MstWr_sof_n : in std_logic;
IP2Bus_MstWr_eof_n : in std_logic;
IP2Bus_MstWr_src_rdy_n : in std_logic;
IP2Bus_MstWr_src_dsc_n : in std_logic;
Bus2IP_MstWr_dst_rdy_n : out std_logic;
Bus2IP_MstWr_dst_dsc_n : out std_logic
-- ADD USER PORTS ABOVE THIS LINE ------------------
);
end entity plbv46_master_burst_wrapper;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plbv46_master_burst_wrapper is
constant PADDING_ZEROS : std_logic_vector(0 to 127) := (others => '0');
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
-- NOT USED: signal ipif_IP2Bus_MstRd_Req : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_Req : std_logic;
-- NOT USED: signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
-- NOT USED: signal ipif_IP2Bus_Mst_Length : std_logic_vector(0 to 11);
-- NOT USED: signal ipif_IP2Bus_Mst_Type : std_logic;
-- NOT USED: signal ipif_IP2Bus_Mst_Lock : std_logic;
-- NOT USED: signal ipif_IP2Bus_Mst_Reset : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_CmdAck : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Cmplt : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Error : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_sof_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_eof_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_src_dsc_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstRd_dst_rdy_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstRd_dst_dsc_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_sof_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_eof_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_src_rdy_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_src_dsc_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstWr_dst_dsc_n : std_logic;
--
-- BITWIDTH ADAPTION:
--
-- Bitwidth of plbv46_master_burst is variable depending on the C_SPLB_DWIDTH/C_SPLB_NATIVE_DWIDTH
-- Bitwidth of plbv46_master_burst_wrapper_128 is tuned for 128bit systemc modules
--
-- The following signals may have different bitwidth between
-- plbv46_master_burst and plbv46_master_burst_wrapper_128. And MSBs of them may not be connected
--
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_IP2Bus_MstWr_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
begin
------------------------------------------
-- instantiate plbv46_master_burst
------------------------------------------
PLBV46_MASTER_BURST_I : entity plbv46_master_burst_v1_01_a.plbv46_master_burst
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_INHIBIT_CC_BLE_INCLUSION => C_INHIBIT_CC_BLE_INCLUSION,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr,
IP2Bus_Mst_Length => IP2Bus_Mst_Length,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE, ---- FOR BITWIDTH ADAPTION
IP2Bus_Mst_Type => IP2Bus_Mst_Type,
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d, ---- FOR BITWIDTH ADAPTION
Bus2IP_MstRd_rem => ipif_Bus2IP_MstRd_rem, ---- FOR BITWIDTH ADAPTION
Bus2IP_MstRd_sof_n => Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d, ---- FOR BITWIDTH ADAPTION
IP2Bus_MstWr_rem => ipif_IP2Bus_MstWr_rem, ---- FOR BITWIDTH ADAPTION
IP2Bus_MstWr_sof_n => IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2IP_MstWr_dst_dsc_n
);
ipif_IP2Bus_Mst_BE <= IP2Bus_Mst_BE(128/8-C_MPLB_NATIVE_DWIDTH/8 to 128/8-1);
ipif_IP2Bus_MstWr_d <= IP2Bus_MstWr_d(128-C_MPLB_NATIVE_DWIDTH to 128-1);
ipif_IP2Bus_MstWr_rem <= IP2Bus_MstWr_rem(128/8-C_MPLB_NATIVE_DWIDTH/8 to 128/8-1);
Bus2IP_MstRd_d <= PADDING_ZEROS(C_MPLB_NATIVE_DWIDTH to 128-1) & ipif_Bus2IP_MstRd_d;
Bus2IP_MstRd_rem <= PADDING_ZEROS(C_MPLB_NATIVE_DWIDTH/8 to 16-1) & ipif_Bus2IP_MstRd_rem;
Bus2IP_Mst_Clk <= MPLB_Clk;
Bus2IP_Mst_Reset <= MPLB_Rst;
end IMP;
| bsd-3-clause |
Elemnir/astral_cornucopia | ECE351_final_project/interface.vhd | 1 | 8923 | ----------------------------------------------------------------------------------
--
-- Author: Adam Howard - ahowar31@utk.edu, Ben Olson - molson5@utk.edu
-- ECE-351: Course Project - Greenhouse Monitor
-- Notes: Main interface controller
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity interface is
Port (
rst : in std_logic;
clk : in std_logic;
btn_bus : in std_logic_vector (3 downto 0);
t_data : in std_logic_vector (7 downto 0);
l_data : in std_logic_vector (7 downto 0);
seg_bus : out std_logic_vector (0 to 7);
digi_bus : out std_logic_vector (0 to 3);
led_bus : out std_logic_vector (7 downto 0)
);
end interface;
architecture interface_arch of interface is
type DISPLAY_STATE is (t_cur, t_low, t_high, l_cur, l_low, l_high);
signal disp : DISPLAY_STATE := t_cur;
signal tl_set, ll_set : integer := 0; --default low temp and light settings
signal th_set, lh_set : integer := 255; --default high temp and light settings
signal alert : integer := 0; --if !=0, show system state on display
component clk_divider is
Port (
rst: in std_logic;
clk_in : in std_logic;
clk_out : out std_logic;
const : in INTEGER
);
end component clk_divider;
signal clk_digi : std_logic := '0';
signal digi_val : std_logic_vector(3 downto 0) := "1110";
begin
digi_bus <= digi_val;
DIG_DIV: clk_divider port map(
rst => rst,
clk_in => clk,
clk_out => clk_digi,
const => 10000
);
-- 7-segment display driver
DISP_DRIVER: process(clk_digi, rst, digi_val) is
variable digi_temp : std_logic_vector(3 downto 0);
variable temp_int, t : integer;
begin
digi_temp := digi_val;
if (rst = '1') then
digi_val <= "1110";
seg_bus <= "00000000";
elsif rising_edge(clk_digi) then
digi_temp := digi_temp(2 downto 0) & digi_temp(3);
-- Show 1st digit on display
if (digi_temp(3) = '0') then
if (disp = t_cur or disp = t_low or disp = t_high) then
seg_bus <= "11001110";
else
seg_bus <= "11000111";
end if;
-- Show 2nd digit on display
elsif (digi_temp(2) = '0') then
if alert /= 0 then
seg_bus <= "11111111";
else
if disp = t_cur then
temp_int := conv_integer(t_data);
elsif disp = t_low then
temp_int := tl_set;
elsif disp = t_high then
temp_int := th_set;
elsif disp = l_cur then
temp_int := conv_integer(l_data);
elsif disp = l_low then
temp_int := ll_set;
else
temp_int := lh_set;
end if;
if (temp_int < 200 and temp_int > 99) then
seg_bus <= "11111001";
elsif (temp_int < 300 and temp_int > 199) then
seg_bus <= "10100100";
else
seg_bus <= "11111111";
end if;
end if;
-- Show 3rd digit on display
elsif (digi_temp(1) = '0') then
if alert /= 0 then
if (disp = t_cur or disp = l_cur) then
seg_bus <= "11000110";
elsif (disp = t_low or disp = l_low) then
seg_bus <= "11000111";
else
seg_bus <= "10001001";
end if;
else
if disp = t_cur then
temp_int := conv_integer(t_data);
elsif disp = t_low then
temp_int := tl_set;
elsif disp = t_high then
temp_int := th_set;
elsif disp = l_cur then
temp_int := conv_integer(l_data);
elsif disp = l_low then
temp_int := ll_set;
else
temp_int := lh_set;
end if;
--temp_int := temp_int mod 100;
if (temp_int > 200) then
temp_int := temp_int - 200;
elsif (temp_int > 100) then
temp_int := temp_int - 100;
end if;
if (temp_int < 20 and temp_int > 9) then
seg_bus <= "11111001";
elsif (temp_int < 30 and temp_int > 19) then
seg_bus <= "10100100";
elsif (temp_int < 40 and temp_int > 29) then
seg_bus <= "10110000";
elsif (temp_int < 50 and temp_int > 39) then
seg_bus <= "10011001";
elsif (temp_int < 60 and temp_int > 49) then
seg_bus <= "10010010";
elsif (temp_int < 70 and temp_int > 59) then
seg_bus <= "10000010";
elsif (temp_int < 80 and temp_int > 69) then
seg_bus <= "11111000";
elsif (temp_int < 90 and temp_int > 79) then
seg_bus <= "10000000";
elsif (temp_int < 100 and temp_int > 89) then
seg_bus <= "10010000";
else
seg_bus <= "11000000";
end if;
end if;
-- Show 4th digit on display
elsif (digi_temp(0) = '0') then
if alert /= 0 then
if (disp = t_cur or disp = l_cur) then
seg_bus <= "11000001";
elsif (disp = t_low or disp = l_low) then
seg_bus <= "11000000";
else
seg_bus <= "11001111";
end if;
else
if disp = t_cur then
temp_int := conv_integer(t_data);
elsif disp = t_low then
temp_int := tl_set;
elsif disp = t_high then
temp_int := th_set;
elsif disp = l_cur then
temp_int := conv_integer(l_data);
elsif disp = l_low then
temp_int := ll_set;
else
temp_int := lh_set;
end if;
--temp_int := temp_int mod 10;
if (temp_int > 200) then
temp_int := temp_int - 200;
elsif (temp_int > 100) then
temp_int := temp_int - 100;
end if;
if (temp_int > 90) then
temp_int := temp_int - 90;
elsif (temp_int > 80) then
temp_int := temp_int - 80;
elsif (temp_int > 70) then
temp_int := temp_int - 70;
elsif (temp_int > 60) then
temp_int := temp_int - 60;
elsif (temp_int > 50) then
temp_int := temp_int - 50;
elsif (temp_int > 40) then
temp_int := temp_int - 40;
elsif (temp_int > 30) then
temp_int := temp_int - 30;
elsif (temp_int > 20) then
temp_int := temp_int - 20;
elsif (temp_int > 10) then
temp_int := temp_int - 10;
end if;
if (temp_int = 1) then
seg_bus <= "11111001";
elsif (temp_int = 2) then
seg_bus <= "10100100";
elsif (temp_int = 3) then
seg_bus <= "10110000";
elsif (temp_int = 4) then
seg_bus <= "10011001";
elsif (temp_int = 5) then
seg_bus <= "10010010";
elsif (temp_int = 6) then
seg_bus <= "10000010";
elsif (temp_int = 7) then
seg_bus <= "11111000";
elsif (temp_int = 8) then
seg_bus <= "10000000";
elsif (temp_int = 9) then
seg_bus <= "10010000";
else
seg_bus <= "11000000";
end if;
end if;
end if;
digi_val <= digi_temp;
end if;
end process DISP_DRIVER;
-- Controls state changes and modifies system settings based on BTN input
BTN_LOGIC: process(clk, rst) is
begin
if (rst = '1') then
disp <= t_cur;
alert <= 0;
lh_set <= 255;
th_set <= 255;
ll_set <= 0;
tl_set <= 0;
elsif rising_edge(clk) then
if alert /= 0 then
alert <= alert - 1;
end if;
if btn_bus(3) = '1' then --switch from light read out to temp read out
if (disp = t_cur or disp = t_low or disp = t_high) then
disp <= l_cur;
else
disp <= t_cur;
end if;
alert <= 50000000;
elsif btn_bus(2) = '1' then --switch between current, low, and, high readouts
case (disp) is
when t_cur => disp <= t_low;
when t_low => disp <= t_high;
when t_high => disp <= t_cur;
when l_cur => disp <= l_low;
when l_low => disp <= l_high;
when l_high => disp <= l_cur;
end case;
alert <= 50000000;
elsif btn_bus(1) = '1' then --increment the current setting
if disp = t_low and tl_set < th_set-1 then
tl_set <= tl_set + 1;
elsif disp = t_high and th_set < 255 then
th_set <= th_set + 1;
elsif disp = l_low and ll_set < lh_set-1 then
ll_set <= ll_set + 1;
elsif disp = l_high and lh_set < 255 then
lh_set <= lh_set + 1;
end if;
elsif btn_bus(0) = '1' then --decrement the current setting
if disp = t_low and tl_set > 0 then
tl_set <= tl_set - 1;
elsif disp = t_high and th_set > tl_set + 1 then
th_set <= th_set - 1;
elsif disp = l_low and ll_set > 0 then
ll_set <= ll_set - 1;
elsif disp = l_high and lh_set > ll_set + 1 then
lh_set <= lh_set - 1;
end if;
end if;
end if;
end process BTN_LOGIC;
-- Activate LEDs if the light or temp data exceeds the set limits
ALARM: process(clk, rst) is
variable ttemp, ltemp : integer;
begin
ttemp := conv_integer(t_data);
ltemp := conv_integer(l_data);
if (rst = '1') then
led_bus <= "00000000";
elsif rising_edge(clk) then
if (tl_set > ttemp) or (th_set < ttemp) then
led_bus(0) <= '1';
else
led_bus(0) <= '0';
end if;
if (ll_set > ltemp) or (lh_set < ltemp) then
led_bus(1) <= '1';
else
led_bus(1) <= '0';
end if;
end if;
end process ALARM;
end interface_arch;
| bsd-3-clause |
tectronics/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/xps_icapi_v1_01_a/hdl/vhdl/xps_icapi.vhd | 3 | 203 | ------------------------------------------------------------------------------
-- THIS FILE IS EMPTY BUT CAN NOT BE DELETED
------------------------------------------------------------------------------
| bsd-3-clause |
Elemnir/astral_cornucopia | ECE351_final_project/clk_divider.vhd | 1 | 1029 | ----------------------------------------------------------------------------------
--
-- Author: Adam Howard - ahowar31@utk.edu, Ben Olson - molson5@utk.edu
-- ECE-351: Course Project - Greenhouse Monitor
-- Notes: Clock divider
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity clk_divider is
Port (
rst: in std_logic;
clk_in : in std_logic;
clk_out : out std_logic;
const : in INTEGER
);
end clk_divider;
architecture clk_divider_arch of clk_divider is
signal counter : integer := 0;
signal clk_tp : std_logic := '0';
begin
clk_out <= clk_tp;
DIVIDER: process(clk_in, rst) is
begin
if (rst = '1') then
counter <= 0;
clk_tp <= '0';
elsif (rising_edge(clk_in)) then
if counter = const then
counter <= 0;
clk_tp <= not clk_tp;
else
counter <= counter + 1;
end if;
end if;
end process DIVIDER;
end clk_divider_arch;
| bsd-3-clause |
yunqu/PYNQ | boards/ip/dvi2rgb_v1_7/src/SyncAsync.vhd | 34 | 3727 | -------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
| bsd-3-clause |
yunqu/PYNQ | boards/ip/audio_codec_ctrl_v1.0/src/iis_ser.vhd | 4 | 4342 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:20:51 08/06/2012
-- Design Name:
-- Module Name: iis_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity iis_ser is
Port ( CLK_100MHZ : in STD_LOGIC; --gbuf clock
SCLK : in STD_LOGIC; --logic (not used as clk)
LRCLK : in STD_LOGIC; --logic (not used as clk)
SDATA : out STD_LOGIC;
EN : in STD_LOGIC;
LDATA : in STD_LOGIC_VECTOR (23 downto 0);
RDATA : in STD_LOGIC_VECTOR (23 downto 0));
end iis_ser;
architecture Behavioral of iis_ser is
--bit cntr counts to 25 (not 24) so that it can set sdata to zero after
--the 24th bit has been sent to the receiver
constant bit_cntr_max : std_logic_vector(4 downto 0) := "11001";--25
type IIS_STATE_TYPE is (RESET, WAIT_LEFT, WRITE_LEFT, WAIT_RIGHT, WRITE_RIGHT);
signal start_left : std_logic;
signal start_right : std_logic;
signal write_bit : std_logic;
signal sclk_d1 : std_logic := '0';
signal lrclk_d1 : std_logic := '0';
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal ldata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal rdata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal sdata_reg : std_logic := '0';
signal iis_state : IIS_STATE_TYPE := RESET;
begin
process(CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
sclk_d1 <= SCLK;
lrclk_d1 <= LRCLK;
end if;
end process;
--Detect falling edge on LRCLK
start_left <= (lrclk_d1 and not(LRCLK));
--Detect rising edge on LRCLK
start_right <= (not(lrclk_d1) and LRCLK);
--Detect falling edge on SCLK
write_bit <= (sclk_d1 and not(SCLK));
--Next state logic
next_iis_state_process : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
case iis_state is
when RESET =>
if (EN = '1') then
iis_state <= WAIT_LEFT;
end if;
when WAIT_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_left = '1') then
iis_state <= WRITE_LEFT;
end if;
when WRITE_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_RIGHT;
end if;
when WAIT_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_right = '1') then
iis_state <= WRITE_RIGHT;
end if;
when WRITE_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_LEFT;
end if;
when others=> --should never be reached
iis_state <= RESET;
end case;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = WRITE_RIGHT or iis_state = WRITE_LEFT) then
if (write_bit = '1') then
bit_cntr <= bit_cntr + 1;
end if;
else
bit_cntr <= (others => '0');
end if;
end if;
end process;
data_shift_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
ldata_reg <= (others => '0');
rdata_reg <= (others => '0');
elsif ((iis_state = WAIT_LEFT) and (start_left = '1')) then
ldata_reg <= LDATA;
rdata_reg <= RDATA;
else
if (iis_state = WRITE_LEFT and write_bit = '1') then
ldata_reg(23 downto 1) <= ldata_reg(22 downto 0);
ldata_reg(0) <= '0';
end if;
if (iis_state = WRITE_RIGHT and write_bit = '1') then
rdata_reg(23 downto 1) <= rdata_reg(22 downto 0);
rdata_reg(0) <= '0';
end if;
end if;
end if;
end process data_shift_proc;
sdata_update_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
sdata_reg <= '0';
elsif (iis_state = WRITE_LEFT and write_bit = '1') then
sdata_reg <= ldata_reg(23);
elsif (iis_state = WRITE_RIGHT and write_bit = '1') then
sdata_reg <= rdata_reg(23);
end if;
end if;
end process sdata_update_proc;
SDATA <= sdata_reg;
end Behavioral;
| bsd-3-clause |
yunqu/PYNQ | boards/ip/audio_codec_ctrl_v1.0/src/axi_lite_ipif.vhd | 4 | 13991 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v1.01.a
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity work.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
| bsd-3-clause |
yunqu/PYNQ | boards/ip/audio_codec_ctrl_v1.0/src/pselect_f.vhd | 4 | 12490 | -------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.common_types.all;
use work.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
| bsd-3-clause |
jsloan256/ecp3-versa | wiggle/wiggle.vhd | 1 | 436 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY wiggle IS
PORT(
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
gpio : OUT INTEGER RANGE 0 TO 128
);
END wiggle;
ARCHITECTURE wiggle_arch OF wiggle IS
SIGNAL count : INTEGER RANGE 0 TO 128;
BEGIN
PROCESS (clk, rstn)
BEGIN
IF rstn = '0' THEN
count <= 0;
ELSIF (clk'EVENT AND clk = '1') THEN
count <= count + 1;
END IF;
END PROCESS;
gpio <= count;
END wiggle_arch;
| bsd-3-clause |
microcom/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
mohamed/fsl_perf_counter | hw/perf_counter_v1_00_a/hdl/vhdl/perf_counter_tb.vhd | 1 | 3433 | -- Testbench of Performance Counter for MicroBlaze
-- Author: Mohamed A. Bamakhrama <m.a.m.bamakhrama@liacs.leidenuniv.nl>
-- Copyrights (c) 2010 by Universiteit Leiden
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity perf_counter_tb is
end perf_counter_tb;
architecture sim of perf_counter_tb is
constant clock_frequency : natural := 100_000_000;
constant clock_period : time := 1000 ms /clock_frequency;
signal clock : std_logic := '0';
signal rst : std_logic := '1'; --active high reset
signal tb_FSL_Clk : std_logic;
signal tb_FSL_Rst : std_logic;
signal tb_FSL_S_Clk : std_logic;
signal tb_FSL_S_Read : std_logic;
signal tb_FSL_S_Data : std_logic_vector(0 to 31);
signal tb_FSL_S_Control : std_logic;
signal tb_FSL_S_Exists : std_logic;
signal tb_FSL_M_Clk : std_logic;
signal tb_FSL_M_Write : std_logic;
signal tb_FSL_M_Data : std_logic_vector(0 to 31);
signal tb_FSL_M_Control : std_logic;
signal tb_FSL_M_Full : std_logic;
component perf_counter
generic
(
C_NUM_OF_COUNTERS : integer := 4;
C_LOG2_NUM_OF_COUNTERS : integer := 2;
C_EXT_RESET_HIGH : integer := 1
);
port
(
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
);
end component;
begin
clock <= not clock after clock_period/2;
tb_FSL_Clk <= clock;
tb_FSL_Rst <= rst;
dut: perf_counter
port map (
FSL_Clk => tb_FSL_Clk,
FSL_Rst => tb_FSL_Rst,
FSL_S_Clk => open,
FSL_S_Read => tb_FSL_S_Read,
FSL_S_Control => tb_FSL_S_Control,
FSL_S_Data => tb_FSL_S_Data,
FSL_S_Exists => tb_FSL_S_Exists,
FSL_M_Clk => open,
FSL_M_Write => tb_FSL_M_Write,
FSL_M_Data => tb_FSL_M_Data,
FSL_M_Control => tb_FSL_M_Control,
FSL_M_Full => tb_FSL_M_Full
);
stim: process
begin
rst <= '0';
wait for clock_period;
rst <= '1';
wait for clock_period;
rst <= '0';
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"00000000";
wait for clock_period;
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"00000001";
wait for clock_period;
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"0000000A";
wait for clock_period;
tb_FSL_S_Exists <= '0';
tb_FSL_S_Data <= X"00000000";
wait for 10*clock_period;
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"0000000B";
wait for clock_period;
tb_FSL_S_Exists <= '0';
tb_FSL_S_Data <= X"00000000";
wait for 10*clock_period;
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"0000000C";
wait for clock_period;
tb_FSL_S_Exists <= '0';
tb_FSL_S_Data <= X"00000000";
wait for 10*clock_period;
assert false report "Testbench terminated successfully!" severity note;
assert false report "Simulation stopped" severity failure;
end process;
end sim;
| bsd-3-clause |
mohamed/fsl_perf_counter | hw/perf_counter_v1_00_a/hdl/vhdl/perf_counter.vhd | 1 | 4213 | -- Performance Counter for MicroBlaze
-- Author: Mohamed A. Bamakhrama <m.a.m.bamakhrama@liacs.leidenuniv.nl>
-- Copyrights (c) 2010 by Universiteit Leiden
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity perf_counter is
generic
(
C_NUM_OF_COUNTERS : integer := 4;
C_LOG2_NUM_OF_COUNTERS : integer := 2;
C_EXT_RESET_HIGH : integer := 1
);
port
(
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
);
end perf_counter;
architecture rtl of perf_counter is
constant MSB_OP : integer := 31;
constant LSB_OP : integer := 29;
constant MSB_ID : integer := 28;
constant LSB_ID : integer := 28-C_LOG2_NUM_OF_COUNTERS+1;
constant RST_ALL : std_logic_vector(0 to 2) := "000";
constant RST_ID : std_logic_vector(0 to 2) := "001";
constant START_ID : std_logic_vector(0 to 2) := "010";
constant STOP_ID : std_logic_vector(0 to 2) := "011";
constant READ_ID : std_logic_vector(0 to 2) := "100";
-- 64-bit counter @ 100MHz = > 5800 years
-- This eliminates the need for handling overflows
type counter_t is array(1 to C_NUM_OF_COUNTERS) of std_logic_vector(0 to 63);
signal counter : counter_t;
type op_t is (idle, running, reset, rd);
type op_array_t is array(1 to C_NUM_OF_COUNTERS) of op_t;
signal op_r : op_array_t;
signal op_i : op_array_t;
subtype id_int_t is integer range 0 to C_NUM_OF_COUNTERS;
signal rd_id_r : id_int_t;
signal rd_id_i : id_int_t;
signal rst : std_logic;
begin
rst <= FSL_Rst when (C_EXT_RESET_HIGH = 1) else not FSL_Rst;
FSL_M_Control <= '0';
FSL_M_Clk <= FSL_Clk;
FSL_S_Clk <= FSL_Clk;
registers: process(FSL_Clk)
begin
if rising_edge(FSL_Clk) then
if (rst = '1') then
counter <= (others => (others => '0'));
op_r <= (others => idle);
rd_id_r <= 0;
else
op_r <= op_i;
rd_id_r <= rd_id_i;
for i in 1 to C_NUM_OF_COUNTERS loop
case (op_i(i)) is
when idle =>
counter(i) <= counter(i);
when running =>
counter(i) <= std_logic_vector(unsigned(counter(i))+1);
when reset =>
counter(i) <= (others => '0');
when rd =>
counter(i) <= counter(i);
when others =>
null;
end case;
end loop;
end if;
end if;
end process;
fsm: process(FSL_S_Exists, FSL_S_Data, op_r, counter, rd_id_r)
variable id : integer;
begin
-- Default assignments
id := 0;
op_i <= op_r;
FSL_M_Data <= (others => '0');
FSL_M_Write <= '0';
FSL_S_Read <= '0';
rd_id_i <= 0;
if (FSL_S_Exists = '1' and rd_id_r = 0) then
id := to_integer(unsigned(FSL_S_Data(LSB_ID to MSB_ID))) + 1;
case(FSL_S_Data(LSB_OP to MSB_OP)) is
when RST_ALL =>
op_i <= (others => reset);
FSL_S_Read <= '1';
when RST_ID =>
op_i(id) <= reset;
FSL_S_Read <= '1';
when STOP_ID =>
op_i(id) <= idle;
FSL_S_Read <= '1';
when START_ID =>
op_i(id) <= running;
FSL_S_Read <= '1';
when READ_ID =>
op_i(id) <= rd;
rd_id_i <= id;
FSL_S_Read <= '1';
FSL_M_Data <= counter(id)(32 to 63);
FSL_M_Write <= '1';
when others =>
null;
end case;
end if;
if (rd_id_r /= 0) then
op_i(rd_id_r) <= running;
FSL_S_Read <= '0';
FSL_M_Data <= counter(rd_id_r)(0 to 31);
FSL_M_Write <= '1';
rd_id_i <= 0;
end if;
end process;
end architecture rtl;
| bsd-3-clause |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC/pll_sys.vhd | 2 | 16741 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll_sys.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.1.1 Build 200 11/30/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2016 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll_sys IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll_sys;
ARCHITECTURE SYN OF pll_sys IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
locked <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "1500",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll_sys",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "10.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "54.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_sys.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "1500"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| bsd-3-clause |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC_MOORE/PacketProcessor/packetprocessor_testbench.vhdl | 2 | 1478 | -- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessor_types.all;
entity packetprocessor_testbench is
port(done : out boolean);
end;
architecture structural of packetprocessor_testbench is
signal finished : boolean;
signal system1000 : std_logic;
signal system1000_rstn : std_logic;
signal i : packetprocessor_types.tup2;
signal case_alt : packetprocessor_types.tup3;
begin
done <= finished;
-- pragma translate_off
process is
begin
system1000 <= '0';
wait for 3 ns;
while (not finished) loop
system1000 <= not system1000;
wait for 500 ns;
system1000 <= not system1000;
wait for 500 ns;
end loop;
wait;
end process;
-- pragma translate_on
-- pragma translate_off
system1000_rstn <= '0',
'1' after 2 ns;
-- pragma translate_on
totest : entity packetprocessor_topentity_0
port map
(system1000 => system1000
,system1000_rstn => system1000_rstn
,i => i
,case_alt => case_alt);
i <= packetprocessor_types.tup2'(std_logic_vector'(0 to 11 => 'X'),true);
finished <=
-- pragma translate_off
false,
-- pragma translate_on
true
-- pragma translate_off
after 100 ns
-- pragma translate_on
;
end;
| bsd-3-clause |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC_MOORE/PacketProcessorDF/packetprocessordf_cnt_j.vhdl | 2 | 1751 | -- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_cnt_j is
port(pts : in packetprocessordf_types.array_of_tup3(0 to 3);
pts_0 : in unsigned(10 downto 0);
pts_1 : in unsigned(7 downto 0);
result : out boolean);
end;
architecture structural of packetprocessordf_cnt_j is
signal app_arg : unsigned(7 downto 0);
signal case_scrut : boolean;
signal case_scrut_0 : boolean;
signal case_alt : boolean;
signal cnt_j_j1out : boolean;
signal result_0 : boolean;
signal case_scrut_1 : packetprocessordf_types.tup3;
signal a1 : unsigned(10 downto 0);
signal m1 : unsigned(7 downto 0);
signal p1 : unsigned(7 downto 0);
begin
app_arg <= pts_1 and m1;
case_scrut <= app_arg = p1;
case_scrut_0 <= pts_0 /= a1;
case_alt <= true when case_scrut else
cnt_j_j1out;
packetprocessordf_cnt_j_j1_cnt_j_j1out : entity packetprocessordf_cnt_j_j1
port map
(result => cnt_j_j1out
,pts => pts
,pts_0 => pts_0
,pts_1 => pts_1);
result_0 <= cnt_j_j1out when case_scrut_0 else
case_alt;
-- index begin
indexvec : block
signal vec_index : integer range 0 to 4-1;
begin
vec_index <= to_integer(to_signed(1,64))
-- pragma translate_off
mod 4
-- pragma translate_on
;
case_scrut_1 <= pts(vec_index);
end block;
-- index end
a1 <= case_scrut_1.tup3_sel0;
m1 <= case_scrut_1.tup3_sel1;
p1 <= case_scrut_1.tup3_sel2;
result <= result_0;
end;
| bsd-3-clause |
Rogiel/BananaCore | Source/Instruction/InstructionController.vhd | 1 | 72449 | --
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library BananaCore;
use BananaCore.Instruction.DecodedInstruction;
use BananaCore.InstructionDecoder;
use BananaCore.Instruction.all;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
use BananaCore.LoadInstructionExecutor;
use BananaCore.StoreInstructionExecutor;
use BananaCore.WriteIoInstructionExecutor;
use BananaCore.ReadIoInstructionExecutor;
use BananaCore.AddInstructionExecutor;
use BananaCore.SubtractInstructionExecutor;
use BananaCore.MultiplyInstructionExecutor;
use BananaCore.DivideInstructionExecutor;
use BananaCore.BitwiseAndInstructionExecutor;
use BananaCore.BitwiseOrInstructionExecutor;
use BananaCore.BitwiseNandInstructionExecutor;
use BananaCore.BitwiseNorInstructionExecutor;
use BananaCore.BitwiseXorInstructionExecutor;
use BananaCore.BitwiseNotInstructionExecutor;
use BananaCore.GreaterThanInstructionExecutor;
use BananaCore.GreaterOrEqualThanInstructionExecutor;
use BananaCore.LessThanInstructionExecutor;
use BananaCore.LessOrEqualThanInstructionExecutor;
use BananaCore.EqualInstructionExecutor;
use BananaCore.NotEqualInstructionExecutor;
use BananaCore.JumpInstructionExecutor;
use BananaCore.JumpIfCarryInstructionExecutor;
use BananaCore.HaltInstructionExecutor;
use BananaCore.ResetInstructionExecutor;
-- Decodes a instruction bit stream into a organized and easy to use instruction record
entity InstructionController is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress;
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData;
-- the operation to perform on the memory
memory_operation: out MemoryOperation;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic;
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor memory address bus
register_address: out RegisterAddress;
-- the processor memory data bus
register_data_read: in RegisterData;
-- the processor memory data bus
register_data_write: out RegisterData;
-- the processor memory operation signal
register_operation: out RegisterOperation;
-- the processor memory operation signal
register_enable: out std_logic;
-- a flag indicating if a register operation has completed
register_ready: in std_logic;
------------------------------------------
-- IO PORTS
------------------------------------------
-- io port: port0
port0: in IOPortData;
-- io port: port1
port1: out IOPortData
);
end InstructionController;
architecture InstructionControllerImpl of InstructionController is
signal instruction_data: std_logic_vector(0 to 31);
signal current_instruction: DecodedInstruction;
signal program_counter: MemoryAddress := integer_to_memory_address(0);
type state_type is (
read_memory0,
wait_memory0,
read_memory1,
wait_memory1,
read_memory2,
wait_memory2,
read_memory3,
wait_memory3,
decode_instruction,
-- wait_decode_instruction,
execute,
wait_execute
);
signal state: state_type := read_memory0;
signal instruction_enabler: std_logic_vector(0 to 255);
signal instruction_ready: std_logic_vector(0 to 255);
signal memory_address_local: MemoryAddress;
signal memory_data_write_local: MemoryData;
signal memory_operation_local: MemoryOperation;
signal memory_enable_local: std_logic;
signal memory_ready_local: std_logic;
signal register_address_local: RegisterAddress;
signal register_data_local: RegisterData;
signal register_operation_local: RegisterOperation;
signal register_enable_local: std_logic;
attribute keep: boolean;
attribute keep of instruction_ready: signal is true;
attribute keep of instruction_data: signal is true;
attribute keep of current_instruction: signal is true;
attribute keep of state: signal is true;
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--for line in content:
-- cog.outl("signal memory_address_{0}: MemoryAddress;".format(line.lower()))
-- cog.outl("signal memory_enable_{0}: std_logic;".format(line.lower()))
-- cog.outl("signal memory_data_write_{0}: MemoryData;".format(line.lower()))
-- cog.outl("signal memory_operation_{0}: MemoryOperation;".format(line.lower()))
-- cog.outl("signal register_address_{0}: RegisterAddress;".format(line.lower()))
-- cog.outl("signal register_data_write_{0}: RegisterData;".format(line.lower()))
-- cog.outl("signal register_operation_{0}: RegisterOperation := OP_REG_DISABLED;".format(line.lower()))
-- cog.outl("signal register_enable_{0}: std_logic;".format(line.lower()))
-- cog.outl();
--]]]
signal memory_address_load: MemoryAddress;
signal memory_enable_load: std_logic;
signal memory_data_write_load: MemoryData;
signal memory_operation_load: MemoryOperation;
signal register_address_load: RegisterAddress;
signal register_data_write_load: RegisterData;
signal register_operation_load: RegisterOperation := OP_REG_DISABLED;
signal register_enable_load: std_logic;
signal port1_load: MemoryData;
signal memory_address_store: MemoryAddress;
signal memory_enable_store: std_logic;
signal memory_data_write_store: MemoryData;
signal memory_operation_store: MemoryOperation;
signal register_address_store: RegisterAddress;
signal register_data_write_store: RegisterData;
signal register_operation_store: RegisterOperation := OP_REG_DISABLED;
signal register_enable_store: std_logic;
signal port1_store: MemoryData;
signal memory_address_writeio: MemoryAddress;
signal memory_enable_writeio: std_logic;
signal memory_data_write_writeio: MemoryData;
signal memory_operation_writeio: MemoryOperation;
signal register_address_writeio: RegisterAddress;
signal register_data_write_writeio: RegisterData;
signal register_operation_writeio: RegisterOperation := OP_REG_DISABLED;
signal register_enable_writeio: std_logic;
signal port1_writeio: MemoryData;
signal memory_address_readio: MemoryAddress;
signal memory_enable_readio: std_logic;
signal memory_data_write_readio: MemoryData;
signal memory_operation_readio: MemoryOperation;
signal register_address_readio: RegisterAddress;
signal register_data_write_readio: RegisterData;
signal register_operation_readio: RegisterOperation := OP_REG_DISABLED;
signal register_enable_readio: std_logic;
signal port1_readio: MemoryData;
signal memory_address_add: MemoryAddress;
signal memory_enable_add: std_logic;
signal memory_data_write_add: MemoryData;
signal memory_operation_add: MemoryOperation;
signal register_address_add: RegisterAddress;
signal register_data_write_add: RegisterData;
signal register_operation_add: RegisterOperation := OP_REG_DISABLED;
signal register_enable_add: std_logic;
signal port1_add: MemoryData;
signal memory_address_subtract: MemoryAddress;
signal memory_enable_subtract: std_logic;
signal memory_data_write_subtract: MemoryData;
signal memory_operation_subtract: MemoryOperation;
signal register_address_subtract: RegisterAddress;
signal register_data_write_subtract: RegisterData;
signal register_operation_subtract: RegisterOperation := OP_REG_DISABLED;
signal register_enable_subtract: std_logic;
signal port1_subtract: MemoryData;
signal memory_address_multiply: MemoryAddress;
signal memory_enable_multiply: std_logic;
signal memory_data_write_multiply: MemoryData;
signal memory_operation_multiply: MemoryOperation;
signal register_address_multiply: RegisterAddress;
signal register_data_write_multiply: RegisterData;
signal register_operation_multiply: RegisterOperation := OP_REG_DISABLED;
signal register_enable_multiply: std_logic;
signal port1_multiply: MemoryData;
signal memory_address_divide: MemoryAddress;
signal memory_enable_divide: std_logic;
signal memory_data_write_divide: MemoryData;
signal memory_operation_divide: MemoryOperation;
signal register_address_divide: RegisterAddress;
signal register_data_write_divide: RegisterData;
signal register_operation_divide: RegisterOperation := OP_REG_DISABLED;
signal register_enable_divide: std_logic;
signal port1_divide: MemoryData;
signal memory_address_bitwiseand: MemoryAddress;
signal memory_enable_bitwiseand: std_logic;
signal memory_data_write_bitwiseand: MemoryData;
signal memory_operation_bitwiseand: MemoryOperation;
signal register_address_bitwiseand: RegisterAddress;
signal register_data_write_bitwiseand: RegisterData;
signal register_operation_bitwiseand: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwiseand: std_logic;
signal port1_bitwiseand: MemoryData;
signal memory_address_bitwiseor: MemoryAddress;
signal memory_enable_bitwiseor: std_logic;
signal memory_data_write_bitwiseor: MemoryData;
signal memory_operation_bitwiseor: MemoryOperation;
signal register_address_bitwiseor: RegisterAddress;
signal register_data_write_bitwiseor: RegisterData;
signal register_operation_bitwiseor: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwiseor: std_logic;
signal port1_bitwiseor: MemoryData;
signal memory_address_bitwisenand: MemoryAddress;
signal memory_enable_bitwisenand: std_logic;
signal memory_data_write_bitwisenand: MemoryData;
signal memory_operation_bitwisenand: MemoryOperation;
signal register_address_bitwisenand: RegisterAddress;
signal register_data_write_bitwisenand: RegisterData;
signal register_operation_bitwisenand: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwisenand: std_logic;
signal port1_bitwisenand: MemoryData;
signal memory_address_bitwisenor: MemoryAddress;
signal memory_enable_bitwisenor: std_logic;
signal memory_data_write_bitwisenor: MemoryData;
signal memory_operation_bitwisenor: MemoryOperation;
signal register_address_bitwisenor: RegisterAddress;
signal register_data_write_bitwisenor: RegisterData;
signal register_operation_bitwisenor: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwisenor: std_logic;
signal port1_bitwisenor: MemoryData;
signal memory_address_bitwisexor: MemoryAddress;
signal memory_enable_bitwisexor: std_logic;
signal memory_data_write_bitwisexor: MemoryData;
signal memory_operation_bitwisexor: MemoryOperation;
signal register_address_bitwisexor: RegisterAddress;
signal register_data_write_bitwisexor: RegisterData;
signal register_operation_bitwisexor: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwisexor: std_logic;
signal port1_bitwisexor: MemoryData;
signal memory_address_bitwisenot: MemoryAddress;
signal memory_enable_bitwisenot: std_logic;
signal memory_data_write_bitwisenot: MemoryData;
signal memory_operation_bitwisenot: MemoryOperation;
signal register_address_bitwisenot: RegisterAddress;
signal register_data_write_bitwisenot: RegisterData;
signal register_operation_bitwisenot: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwisenot: std_logic;
signal port1_bitwisenot: MemoryData;
signal memory_address_greaterthan: MemoryAddress;
signal memory_enable_greaterthan: std_logic;
signal memory_data_write_greaterthan: MemoryData;
signal memory_operation_greaterthan: MemoryOperation;
signal register_address_greaterthan: RegisterAddress;
signal register_data_write_greaterthan: RegisterData;
signal register_operation_greaterthan: RegisterOperation := OP_REG_DISABLED;
signal register_enable_greaterthan: std_logic;
signal port1_greaterthan: MemoryData;
signal memory_address_greaterorequalthan: MemoryAddress;
signal memory_enable_greaterorequalthan: std_logic;
signal memory_data_write_greaterorequalthan: MemoryData;
signal memory_operation_greaterorequalthan: MemoryOperation;
signal register_address_greaterorequalthan: RegisterAddress;
signal register_data_write_greaterorequalthan: RegisterData;
signal register_operation_greaterorequalthan: RegisterOperation := OP_REG_DISABLED;
signal register_enable_greaterorequalthan: std_logic;
signal port1_greaterorequalthan: MemoryData;
signal memory_address_lessthan: MemoryAddress;
signal memory_enable_lessthan: std_logic;
signal memory_data_write_lessthan: MemoryData;
signal memory_operation_lessthan: MemoryOperation;
signal register_address_lessthan: RegisterAddress;
signal register_data_write_lessthan: RegisterData;
signal register_operation_lessthan: RegisterOperation := OP_REG_DISABLED;
signal register_enable_lessthan: std_logic;
signal port1_lessthan: MemoryData;
signal memory_address_lessorequalthan: MemoryAddress;
signal memory_enable_lessorequalthan: std_logic;
signal memory_data_write_lessorequalthan: MemoryData;
signal memory_operation_lessorequalthan: MemoryOperation;
signal register_address_lessorequalthan: RegisterAddress;
signal register_data_write_lessorequalthan: RegisterData;
signal register_operation_lessorequalthan: RegisterOperation := OP_REG_DISABLED;
signal register_enable_lessorequalthan: std_logic;
signal port1_lessorequalthan: MemoryData;
signal memory_address_equal: MemoryAddress;
signal memory_enable_equal: std_logic;
signal memory_data_write_equal: MemoryData;
signal memory_operation_equal: MemoryOperation;
signal register_address_equal: RegisterAddress;
signal register_data_write_equal: RegisterData;
signal register_operation_equal: RegisterOperation := OP_REG_DISABLED;
signal register_enable_equal: std_logic;
signal port1_equal: MemoryData;
signal memory_address_notequal: MemoryAddress;
signal memory_enable_notequal: std_logic;
signal memory_data_write_notequal: MemoryData;
signal memory_operation_notequal: MemoryOperation;
signal register_address_notequal: RegisterAddress;
signal register_data_write_notequal: RegisterData;
signal register_operation_notequal: RegisterOperation := OP_REG_DISABLED;
signal register_enable_notequal: std_logic;
signal port1_notequal: MemoryData;
signal memory_address_jump: MemoryAddress;
signal memory_enable_jump: std_logic;
signal memory_data_write_jump: MemoryData;
signal memory_operation_jump: MemoryOperation;
signal register_address_jump: RegisterAddress;
signal register_data_write_jump: RegisterData;
signal register_operation_jump: RegisterOperation := OP_REG_DISABLED;
signal register_enable_jump: std_logic;
signal port1_jump: MemoryData;
signal memory_address_jumpifcarry: MemoryAddress;
signal memory_enable_jumpifcarry: std_logic;
signal memory_data_write_jumpifcarry: MemoryData;
signal memory_operation_jumpifcarry: MemoryOperation;
signal register_address_jumpifcarry: RegisterAddress;
signal register_data_write_jumpifcarry: RegisterData;
signal register_operation_jumpifcarry: RegisterOperation := OP_REG_DISABLED;
signal register_enable_jumpifcarry: std_logic;
signal port1_jumpifcarry: MemoryData;
signal memory_address_halt: MemoryAddress;
signal memory_enable_halt: std_logic;
signal memory_data_write_halt: MemoryData;
signal memory_operation_halt: MemoryOperation;
signal register_address_halt: RegisterAddress;
signal register_data_write_halt: RegisterData;
signal register_operation_halt: RegisterOperation := OP_REG_DISABLED;
signal register_enable_halt: std_logic;
signal port1_halt: MemoryData;
signal memory_address_reset: MemoryAddress;
signal memory_enable_reset: std_logic;
signal memory_data_write_reset: MemoryData;
signal memory_operation_reset: MemoryOperation;
signal register_address_reset: RegisterAddress;
signal register_data_write_reset: RegisterData;
signal register_operation_reset: RegisterOperation := OP_REG_DISABLED;
signal register_enable_reset: std_logic;
signal port1_reset: MemoryData;
-- [[[end]]]
signal mux_disabled : std_logic := '1';
signal jump_program_counter : MemoryAddress;
signal jump_program_counter_set : std_logic;
signal jump_if_carry_program_counter : MemoryAddress;
signal jump_if_carry_program_counter_set : std_logic;
begin
-- IMPLEMENTATION NOTE: here, we could very easily (and handly) implement a pipeline.
-- While the instruction is being executed we could already start loading the next memory addresses.
-- Though we have to be sure that no other instruction is accessing the memory bus at the same time.
memory_address <=
memory_address_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tmemory_address_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tmemory_address_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
memory_address_load when instruction_enabler(0) = '1' else
memory_address_store when instruction_enabler(1) = '1' else
memory_address_writeio when instruction_enabler(2) = '1' else
memory_address_readio when instruction_enabler(3) = '1' else
memory_address_add when instruction_enabler(4) = '1' else
memory_address_subtract when instruction_enabler(5) = '1' else
memory_address_multiply when instruction_enabler(6) = '1' else
memory_address_divide when instruction_enabler(7) = '1' else
memory_address_bitwiseand when instruction_enabler(8) = '1' else
memory_address_bitwiseor when instruction_enabler(9) = '1' else
memory_address_bitwisenand when instruction_enabler(10) = '1' else
memory_address_bitwisenor when instruction_enabler(11) = '1' else
memory_address_bitwisexor when instruction_enabler(12) = '1' else
memory_address_bitwisenot when instruction_enabler(13) = '1' else
memory_address_greaterthan when instruction_enabler(14) = '1' else
memory_address_greaterorequalthan when instruction_enabler(15) = '1' else
memory_address_lessthan when instruction_enabler(16) = '1' else
memory_address_lessorequalthan when instruction_enabler(17) = '1' else
memory_address_equal when instruction_enabler(18) = '1' else
memory_address_notequal when instruction_enabler(19) = '1' else
memory_address_jump when instruction_enabler(20) = '1' else
memory_address_jumpifcarry when instruction_enabler(21) = '1' else
memory_address_halt when instruction_enabler(22) = '1' else
memory_address_reset when instruction_enabler(23) = '1';
-- [[[end]]]
memory_data_write <=
memory_data_write_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tmemory_data_write_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tmemory_data_write_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
memory_data_write_load when instruction_enabler(0) = '1' else
memory_data_write_store when instruction_enabler(1) = '1' else
memory_data_write_writeio when instruction_enabler(2) = '1' else
memory_data_write_readio when instruction_enabler(3) = '1' else
memory_data_write_add when instruction_enabler(4) = '1' else
memory_data_write_subtract when instruction_enabler(5) = '1' else
memory_data_write_multiply when instruction_enabler(6) = '1' else
memory_data_write_divide when instruction_enabler(7) = '1' else
memory_data_write_bitwiseand when instruction_enabler(8) = '1' else
memory_data_write_bitwiseor when instruction_enabler(9) = '1' else
memory_data_write_bitwisenand when instruction_enabler(10) = '1' else
memory_data_write_bitwisenor when instruction_enabler(11) = '1' else
memory_data_write_bitwisexor when instruction_enabler(12) = '1' else
memory_data_write_bitwisenot when instruction_enabler(13) = '1' else
memory_data_write_greaterthan when instruction_enabler(14) = '1' else
memory_data_write_greaterorequalthan when instruction_enabler(15) = '1' else
memory_data_write_lessthan when instruction_enabler(16) = '1' else
memory_data_write_lessorequalthan when instruction_enabler(17) = '1' else
memory_data_write_equal when instruction_enabler(18) = '1' else
memory_data_write_notequal when instruction_enabler(19) = '1' else
memory_data_write_jump when instruction_enabler(20) = '1' else
memory_data_write_jumpifcarry when instruction_enabler(21) = '1' else
memory_data_write_halt when instruction_enabler(22) = '1' else
memory_data_write_reset when instruction_enabler(23) = '1';
-- [[[end]]]
memory_operation <=
memory_operation_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tmemory_operation_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tmemory_operation_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
memory_operation_load when instruction_enabler(0) = '1' else
memory_operation_store when instruction_enabler(1) = '1' else
memory_operation_writeio when instruction_enabler(2) = '1' else
memory_operation_readio when instruction_enabler(3) = '1' else
memory_operation_add when instruction_enabler(4) = '1' else
memory_operation_subtract when instruction_enabler(5) = '1' else
memory_operation_multiply when instruction_enabler(6) = '1' else
memory_operation_divide when instruction_enabler(7) = '1' else
memory_operation_bitwiseand when instruction_enabler(8) = '1' else
memory_operation_bitwiseor when instruction_enabler(9) = '1' else
memory_operation_bitwisenand when instruction_enabler(10) = '1' else
memory_operation_bitwisenor when instruction_enabler(11) = '1' else
memory_operation_bitwisexor when instruction_enabler(12) = '1' else
memory_operation_bitwisenot when instruction_enabler(13) = '1' else
memory_operation_greaterthan when instruction_enabler(14) = '1' else
memory_operation_greaterorequalthan when instruction_enabler(15) = '1' else
memory_operation_lessthan when instruction_enabler(16) = '1' else
memory_operation_lessorequalthan when instruction_enabler(17) = '1' else
memory_operation_equal when instruction_enabler(18) = '1' else
memory_operation_notequal when instruction_enabler(19) = '1' else
memory_operation_jump when instruction_enabler(20) = '1' else
memory_operation_jumpifcarry when instruction_enabler(21) = '1' else
memory_operation_halt when instruction_enabler(22) = '1' else
memory_operation_reset when instruction_enabler(23) = '1';
-- [[[end]]]
memory_enable <=
memory_enable_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tmemory_enable_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tmemory_enable_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
memory_enable_load when instruction_enabler(0) = '1' else
memory_enable_store when instruction_enabler(1) = '1' else
memory_enable_writeio when instruction_enabler(2) = '1' else
memory_enable_readio when instruction_enabler(3) = '1' else
memory_enable_add when instruction_enabler(4) = '1' else
memory_enable_subtract when instruction_enabler(5) = '1' else
memory_enable_multiply when instruction_enabler(6) = '1' else
memory_enable_divide when instruction_enabler(7) = '1' else
memory_enable_bitwiseand when instruction_enabler(8) = '1' else
memory_enable_bitwiseor when instruction_enabler(9) = '1' else
memory_enable_bitwisenand when instruction_enabler(10) = '1' else
memory_enable_bitwisenor when instruction_enabler(11) = '1' else
memory_enable_bitwisexor when instruction_enabler(12) = '1' else
memory_enable_bitwisenot when instruction_enabler(13) = '1' else
memory_enable_greaterthan when instruction_enabler(14) = '1' else
memory_enable_greaterorequalthan when instruction_enabler(15) = '1' else
memory_enable_lessthan when instruction_enabler(16) = '1' else
memory_enable_lessorequalthan when instruction_enabler(17) = '1' else
memory_enable_equal when instruction_enabler(18) = '1' else
memory_enable_notequal when instruction_enabler(19) = '1' else
memory_enable_jump when instruction_enabler(20) = '1' else
memory_enable_jumpifcarry when instruction_enabler(21) = '1' else
memory_enable_halt when instruction_enabler(22) = '1' else
memory_enable_reset when instruction_enabler(23) = '1';
-- [[[end]]]
register_data_write <=
register_data_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tregister_data_write_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tregister_data_write_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
register_data_write_load when instruction_enabler(0) = '1' else
register_data_write_store when instruction_enabler(1) = '1' else
register_data_write_writeio when instruction_enabler(2) = '1' else
register_data_write_readio when instruction_enabler(3) = '1' else
register_data_write_add when instruction_enabler(4) = '1' else
register_data_write_subtract when instruction_enabler(5) = '1' else
register_data_write_multiply when instruction_enabler(6) = '1' else
register_data_write_divide when instruction_enabler(7) = '1' else
register_data_write_bitwiseand when instruction_enabler(8) = '1' else
register_data_write_bitwiseor when instruction_enabler(9) = '1' else
register_data_write_bitwisenand when instruction_enabler(10) = '1' else
register_data_write_bitwisenor when instruction_enabler(11) = '1' else
register_data_write_bitwisexor when instruction_enabler(12) = '1' else
register_data_write_bitwisenot when instruction_enabler(13) = '1' else
register_data_write_greaterthan when instruction_enabler(14) = '1' else
register_data_write_greaterorequalthan when instruction_enabler(15) = '1' else
register_data_write_lessthan when instruction_enabler(16) = '1' else
register_data_write_lessorequalthan when instruction_enabler(17) = '1' else
register_data_write_equal when instruction_enabler(18) = '1' else
register_data_write_notequal when instruction_enabler(19) = '1' else
register_data_write_jump when instruction_enabler(20) = '1' else
register_data_write_jumpifcarry when instruction_enabler(21) = '1' else
register_data_write_halt when instruction_enabler(22) = '1' else
register_data_write_reset when instruction_enabler(23) = '1';
-- [[[end]]]
register_operation <=
register_operation_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tregister_operation_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tregister_operation_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
register_operation_load when instruction_enabler(0) = '1' else
register_operation_store when instruction_enabler(1) = '1' else
register_operation_writeio when instruction_enabler(2) = '1' else
register_operation_readio when instruction_enabler(3) = '1' else
register_operation_add when instruction_enabler(4) = '1' else
register_operation_subtract when instruction_enabler(5) = '1' else
register_operation_multiply when instruction_enabler(6) = '1' else
register_operation_divide when instruction_enabler(7) = '1' else
register_operation_bitwiseand when instruction_enabler(8) = '1' else
register_operation_bitwiseor when instruction_enabler(9) = '1' else
register_operation_bitwisenand when instruction_enabler(10) = '1' else
register_operation_bitwisenor when instruction_enabler(11) = '1' else
register_operation_bitwisexor when instruction_enabler(12) = '1' else
register_operation_bitwisenot when instruction_enabler(13) = '1' else
register_operation_greaterthan when instruction_enabler(14) = '1' else
register_operation_greaterorequalthan when instruction_enabler(15) = '1' else
register_operation_lessthan when instruction_enabler(16) = '1' else
register_operation_lessorequalthan when instruction_enabler(17) = '1' else
register_operation_equal when instruction_enabler(18) = '1' else
register_operation_notequal when instruction_enabler(19) = '1' else
register_operation_jump when instruction_enabler(20) = '1' else
register_operation_jumpifcarry when instruction_enabler(21) = '1' else
register_operation_halt when instruction_enabler(22) = '1' else
register_operation_reset when instruction_enabler(23) = '1';
-- [[[end]]]
register_enable <=
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tregister_enable_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tregister_enable_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
register_enable_load when instruction_enabler(0) = '1' else
register_enable_store when instruction_enabler(1) = '1' else
register_enable_writeio when instruction_enabler(2) = '1' else
register_enable_readio when instruction_enabler(3) = '1' else
register_enable_add when instruction_enabler(4) = '1' else
register_enable_subtract when instruction_enabler(5) = '1' else
register_enable_multiply when instruction_enabler(6) = '1' else
register_enable_divide when instruction_enabler(7) = '1' else
register_enable_bitwiseand when instruction_enabler(8) = '1' else
register_enable_bitwiseor when instruction_enabler(9) = '1' else
register_enable_bitwisenand when instruction_enabler(10) = '1' else
register_enable_bitwisenor when instruction_enabler(11) = '1' else
register_enable_bitwisexor when instruction_enabler(12) = '1' else
register_enable_bitwisenot when instruction_enabler(13) = '1' else
register_enable_greaterthan when instruction_enabler(14) = '1' else
register_enable_greaterorequalthan when instruction_enabler(15) = '1' else
register_enable_lessthan when instruction_enabler(16) = '1' else
register_enable_lessorequalthan when instruction_enabler(17) = '1' else
register_enable_equal when instruction_enabler(18) = '1' else
register_enable_notequal when instruction_enabler(19) = '1' else
register_enable_jump when instruction_enabler(20) = '1' else
register_enable_jumpifcarry when instruction_enabler(21) = '1' else
register_enable_halt when instruction_enabler(22) = '1' else
register_enable_reset when instruction_enabler(23) = '1' else
-- [[[end]]]
'0';
register_address <=
register_address_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tregister_address_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tregister_address_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
register_address_load when instruction_enabler(0) = '1' else
register_address_store when instruction_enabler(1) = '1' else
register_address_writeio when instruction_enabler(2) = '1' else
register_address_readio when instruction_enabler(3) = '1' else
register_address_add when instruction_enabler(4) = '1' else
register_address_subtract when instruction_enabler(5) = '1' else
register_address_multiply when instruction_enabler(6) = '1' else
register_address_divide when instruction_enabler(7) = '1' else
register_address_bitwiseand when instruction_enabler(8) = '1' else
register_address_bitwiseor when instruction_enabler(9) = '1' else
register_address_bitwisenand when instruction_enabler(10) = '1' else
register_address_bitwisenor when instruction_enabler(11) = '1' else
register_address_bitwisexor when instruction_enabler(12) = '1' else
register_address_bitwisenot when instruction_enabler(13) = '1' else
register_address_greaterthan when instruction_enabler(14) = '1' else
register_address_greaterorequalthan when instruction_enabler(15) = '1' else
register_address_lessthan when instruction_enabler(16) = '1' else
register_address_lessorequalthan when instruction_enabler(17) = '1' else
register_address_equal when instruction_enabler(18) = '1' else
register_address_notequal when instruction_enabler(19) = '1' else
register_address_jump when instruction_enabler(20) = '1' else
register_address_jumpifcarry when instruction_enabler(21) = '1' else
register_address_halt when instruction_enabler(22) = '1' else
register_address_reset when instruction_enabler(23) = '1';
-- [[[end]]]
-- [[--[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content:
-- template_vars = {
-- 'LowerName': line.lower(),
-- 'Name': line,
-- 'Index': counter
-- }
-- cog.outl("{LowerName}_instruction_executor: {Name}InstructionExecutor port map(".format(**template_vars))
-- cog.outl("\tclock => clock,".format(**template_vars))
-- cog.outl("\tenable => instruction_enabler({Index}),".format(**template_vars))
-- cog.outl("\targ0_address => current_instruction.reg0,".format(**template_vars))
-- cog.outl("\targ1_address => current_instruction.reg1,".format(**template_vars))
-- cog.outl("\tinstruction_ready => instruction_ready({Index}),".format(**template_vars))
-- cog.outl("\tmemory_address => memory_address_{LowerName},".format(**template_vars))
-- cog.outl("\tmemory_data_read => memory_data_read,".format(**template_vars))
-- cog.outl("\tmemory_data_write => memory_data_write_{LowerName},".format(**template_vars))
-- cog.outl("\tmemory_operation => memory_operation_{LowerName},".format(**template_vars))
-- cog.outl("\tmemory_enable => memory_enable_{LowerName},".format(**template_vars))
-- cog.outl("\tmemory_ready => memory_ready,".format(**template_vars))
-- cog.outl("\tregister_address => register_address_{LowerName},".format(**template_vars))
-- cog.outl("\tregister_operation => register_operation_{LowerName},".format(**template_vars))
-- cog.outl("\tregister_data_read => register_data_read,".format(**template_vars))
-- cog.outl("\tregister_data_write => register_data_write_{LowerName},".format(**template_vars))
-- cog.outl("\tregister_enable => register_enable_{LowerName},".format(**template_vars))
-- cog.outl("\tport0 => port0,".format(**template_vars))
-- cog.outl("\tport1 => port1_{LowerName}".format(**template_vars))
-- cog.outl(");".format(**template_vars))
-- cog.outl()
-- counter = counter + 1
--]]--]
load_instruction_executor: LoadInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(0),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
arg2_address => current_instruction.address,
instruction_ready => instruction_ready(0),
memory_address => memory_address_load,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_load,
memory_operation => memory_operation_load,
memory_enable => memory_enable_load,
memory_ready => memory_ready,
register_address => register_address_load,
register_operation => register_operation_load,
register_data_read => register_data_read,
register_data_write => register_data_write_load,
register_enable => register_enable_load,
register_ready => register_ready
);
store_instruction_executor: StoreInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(1),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
arg2_address => current_instruction.address,
instruction_ready => instruction_ready(1),
memory_address => memory_address_store,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_store,
memory_operation => memory_operation_store,
memory_enable => memory_enable_store,
memory_ready => memory_ready,
register_address => register_address_store,
register_operation => register_operation_store,
register_data_read => register_data_read,
register_data_write => register_data_write_store,
register_enable => register_enable_store,
register_ready => register_ready
);
writeio_instruction_executor: WriteIoInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(2),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(2),
memory_address => memory_address_writeio,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_writeio,
memory_operation => memory_operation_writeio,
memory_enable => memory_enable_writeio,
memory_ready => memory_ready,
register_address => register_address_writeio,
register_operation => register_operation_writeio,
register_data_read => register_data_read,
register_data_write => register_data_write_writeio,
register_enable => register_enable_writeio,
register_ready => register_ready,
port1 => port1
);
readio_instruction_executor: ReadIoInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(3),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(3),
memory_address => memory_address_readio,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_readio,
memory_operation => memory_operation_readio,
memory_enable => memory_enable_readio,
memory_ready => memory_ready,
register_address => register_address_readio,
register_operation => register_operation_readio,
register_data_read => register_data_read,
register_data_write => register_data_write_readio,
register_enable => register_enable_readio,
register_ready => register_ready,
port0 => port0
);
add_instruction_executor: AddInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(4),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(4),
memory_address => memory_address_add,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_add,
memory_operation => memory_operation_add,
memory_enable => memory_enable_add,
memory_ready => memory_ready,
register_address => register_address_add,
register_operation => register_operation_add,
register_data_read => register_data_read,
register_data_write => register_data_write_add,
register_enable => register_enable_add,
register_ready => register_ready
);
subtract_instruction_executor: SubtractInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(5),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(5),
memory_address => memory_address_subtract,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_subtract,
memory_operation => memory_operation_subtract,
memory_enable => memory_enable_subtract,
memory_ready => memory_ready,
register_address => register_address_subtract,
register_operation => register_operation_subtract,
register_data_read => register_data_read,
register_data_write => register_data_write_subtract,
register_enable => register_enable_subtract,
register_ready => register_ready
);
multiply_instruction_executor: MultiplyInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(6),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(6),
memory_address => memory_address_multiply,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_multiply,
memory_operation => memory_operation_multiply,
memory_enable => memory_enable_multiply,
memory_ready => memory_ready,
register_address => register_address_multiply,
register_operation => register_operation_multiply,
register_data_read => register_data_read,
register_data_write => register_data_write_multiply,
register_enable => register_enable_multiply,
register_ready => register_ready
);
divide_instruction_executor: DivideInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(7),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(7),
memory_address => memory_address_divide,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_divide,
memory_operation => memory_operation_divide,
memory_enable => memory_enable_divide,
memory_ready => memory_ready,
register_address => register_address_divide,
register_operation => register_operation_divide,
register_data_read => register_data_read,
register_data_write => register_data_write_divide,
register_enable => register_enable_divide,
register_ready => register_ready
);
bitwiseand_instruction_executor: BitwiseAndInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(8),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(8),
memory_address => memory_address_bitwiseand,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwiseand,
memory_operation => memory_operation_bitwiseand,
memory_enable => memory_enable_bitwiseand,
memory_ready => memory_ready,
register_address => register_address_bitwiseand,
register_operation => register_operation_bitwiseand,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwiseand,
register_enable => register_enable_bitwiseand,
register_ready => register_ready
);
bitwiseor_instruction_executor: BitwiseOrInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(9),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(9),
memory_address => memory_address_bitwiseor,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwiseor,
memory_operation => memory_operation_bitwiseor,
memory_enable => memory_enable_bitwiseor,
memory_ready => memory_ready,
register_address => register_address_bitwiseor,
register_operation => register_operation_bitwiseor,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwiseor,
register_enable => register_enable_bitwiseor,
register_ready => register_ready
);
bitwisenand_instruction_executor: BitwiseNandInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(10),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(10),
memory_address => memory_address_bitwisenand,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwisenand,
memory_operation => memory_operation_bitwisenand,
memory_enable => memory_enable_bitwisenand,
memory_ready => memory_ready,
register_address => register_address_bitwisenand,
register_operation => register_operation_bitwisenand,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwisenand,
register_enable => register_enable_bitwisenand,
register_ready => register_ready
);
bitwisenor_instruction_executor: BitwiseNorInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(11),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(11),
memory_address => memory_address_bitwisenor,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwisenor,
memory_operation => memory_operation_bitwisenor,
memory_enable => memory_enable_bitwisenor,
memory_ready => memory_ready,
register_address => register_address_bitwisenor,
register_operation => register_operation_bitwisenor,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwisenor,
register_enable => register_enable_bitwisenor,
register_ready => register_ready
);
bitwisexor_instruction_executor: BitwiseXorInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(12),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(12),
memory_address => memory_address_bitwisexor,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwisexor,
memory_operation => memory_operation_bitwisexor,
memory_enable => memory_enable_bitwisexor,
memory_ready => memory_ready,
register_address => register_address_bitwisexor,
register_operation => register_operation_bitwisexor,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwisexor,
register_enable => register_enable_bitwisexor,
register_ready => register_ready
);
bitwisenot_instruction_executor: BitwiseNotInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(13),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(13),
memory_address => memory_address_bitwisenot,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwisenot,
memory_operation => memory_operation_bitwisenot,
memory_enable => memory_enable_bitwisenot,
memory_ready => memory_ready,
register_address => register_address_bitwisenot,
register_operation => register_operation_bitwisenot,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwisenot,
register_enable => register_enable_bitwisenot,
register_ready => register_ready
);
greaterthan_instruction_executor: GreaterThanInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(14),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(14),
memory_address => memory_address_greaterthan,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_greaterthan,
memory_operation => memory_operation_greaterthan,
memory_enable => memory_enable_greaterthan,
memory_ready => memory_ready,
register_address => register_address_greaterthan,
register_operation => register_operation_greaterthan,
register_data_read => register_data_read,
register_data_write => register_data_write_greaterthan,
register_enable => register_enable_greaterthan,
register_ready => register_ready
);
greaterorequalthan_instruction_executor: GreaterOrEqualThanInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(15),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(15),
memory_address => memory_address_greaterorequalthan,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_greaterorequalthan,
memory_operation => memory_operation_greaterorequalthan,
memory_enable => memory_enable_greaterorequalthan,
memory_ready => memory_ready,
register_address => register_address_greaterorequalthan,
register_operation => register_operation_greaterorequalthan,
register_data_read => register_data_read,
register_data_write => register_data_write_greaterorequalthan,
register_enable => register_enable_greaterorequalthan,
register_ready => register_ready
);
lessthan_instruction_executor: LessThanInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(16),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(16),
memory_address => memory_address_lessthan,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_lessthan,
memory_operation => memory_operation_lessthan,
memory_enable => memory_enable_lessthan,
memory_ready => memory_ready,
register_address => register_address_lessthan,
register_operation => register_operation_lessthan,
register_data_read => register_data_read,
register_data_write => register_data_write_lessthan,
register_enable => register_enable_lessthan,
register_ready => register_ready
);
lessorequalthan_instruction_executor: LessOrEqualThanInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(17),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(17),
memory_address => memory_address_lessorequalthan,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_lessorequalthan,
memory_operation => memory_operation_lessorequalthan,
memory_enable => memory_enable_lessorequalthan,
memory_ready => memory_ready,
register_address => register_address_lessorequalthan,
register_operation => register_operation_lessorequalthan,
register_data_read => register_data_read,
register_data_write => register_data_write_lessorequalthan,
register_enable => register_enable_lessorequalthan,
register_ready => register_ready
);
equal_instruction_executor: EqualInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(18),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(18),
memory_address => memory_address_equal,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_equal,
memory_operation => memory_operation_equal,
memory_enable => memory_enable_equal,
memory_ready => memory_ready,
register_address => register_address_equal,
register_operation => register_operation_equal,
register_data_read => register_data_read,
register_data_write => register_data_write_equal,
register_enable => register_enable_equal,
register_ready => register_ready
);
notequal_instruction_executor: NotEqualInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(19),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(19),
memory_address => memory_address_notequal,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_notequal,
memory_operation => memory_operation_notequal,
memory_enable => memory_enable_notequal,
memory_ready => memory_ready,
register_address => register_address_notequal,
register_operation => register_operation_notequal,
register_data_read => register_data_read,
register_data_write => register_data_write_notequal,
register_enable => register_enable_notequal,
register_ready => register_ready
);
jump_instruction_executor: JumpInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(20),
arg0_address => current_instruction.address,
instruction_ready => instruction_ready(20),
memory_address => memory_address_jump,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_jump,
memory_operation => memory_operation_jump,
memory_enable => memory_enable_jump,
memory_ready => memory_ready,
register_address => register_address_jump,
register_operation => register_operation_jump,
register_data_read => register_data_read,
register_data_write => register_data_write_jump,
register_enable => register_enable_jump,
program_counter => jump_program_counter,
program_counter_set => jump_program_counter_set,
register_ready => register_ready
);
jumpifcarry_instruction_executor: JumpIfCarryInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(21),
arg0_address => current_instruction.address,
instruction_ready => instruction_ready(21),
memory_address => memory_address_jumpifcarry,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_jumpifcarry,
memory_operation => memory_operation_jumpifcarry,
memory_enable => memory_enable_jumpifcarry,
memory_ready => memory_ready,
register_address => register_address_jumpifcarry,
register_operation => register_operation_jumpifcarry,
register_data_read => register_data_read,
register_data_write => register_data_write_jumpifcarry,
register_enable => register_enable_jumpifcarry,
register_ready => register_ready,
program_counter => jump_if_carry_program_counter,
program_counter_set => jump_if_carry_program_counter_set
);
halt_instruction_executor: HaltInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(22),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(22),
memory_address => memory_address_halt,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_halt,
memory_operation => memory_operation_halt,
memory_enable => memory_enable_halt,
memory_ready => memory_ready,
register_address => register_address_halt,
register_operation => register_operation_halt,
register_data_read => register_data_read,
register_data_write => register_data_write_halt,
register_enable => register_enable_halt,
register_ready => register_ready
);
reset_instruction_executor: ResetInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(23),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(23),
memory_address => memory_address_reset,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_reset,
memory_operation => memory_operation_reset,
memory_enable => memory_enable_reset,
memory_ready => memory_ready,
register_address => register_address_reset,
register_operation => register_operation_reset,
register_data_read => register_data_read,
register_data_write => register_data_write_reset,
register_enable => register_enable_reset,
register_ready => register_ready
);
-- [[[--end]]]
process(clock) begin
if clock'event and clock = '1' then
case state is
when read_memory0 =>
mux_disabled <= '1';
memory_address_local <= program_counter;
memory_operation_local <= MEMORY_OP_READ;
memory_enable_local <= '1';
state <= wait_memory0;
when wait_memory0 =>
mux_disabled <= '1';
if memory_ready = '1' then
instruction_data(0 to 7) <= memory_data_read;
memory_enable_local <= '0';
state <= read_memory1;
else
state <= wait_memory0;
end if;
when read_memory1 =>
mux_disabled <= '1';
memory_address_local <= program_counter + 1;
memory_operation_local <= MEMORY_OP_READ;
memory_enable_local <= '1';
state <= wait_memory1;
when wait_memory1 =>
mux_disabled <= '1';
if memory_ready = '1' then
instruction_data(8 to 15) <= memory_data_read;
memory_enable_local <= '0';
state <= read_memory2;
else
state <= wait_memory1;
end if;
when read_memory2 =>
mux_disabled <= '1';
memory_address_local <= program_counter + 2;
memory_operation_local <= MEMORY_OP_READ;
memory_enable_local <= '1';
state <= wait_memory2;
when wait_memory2 =>
mux_disabled <= '1';
if memory_ready = '1' then
instruction_data(16 to 23) <= memory_data_read;
memory_enable_local <= '0';
state <= read_memory3;
else
state <= wait_memory2;
end if;
when read_memory3 =>
mux_disabled <= '1';
memory_address_local <= program_counter + 3;
memory_operation_local <= MEMORY_OP_READ;
memory_enable_local <= '1';
state <= wait_memory3;
when wait_memory3 =>
mux_disabled <= '1';
if memory_ready = '1' then
instruction_data(24 to 31) <= memory_data_read;
memory_enable_local <= '0';
state <= decode_instruction;
else
state <= wait_memory3;
end if;
when decode_instruction =>
mux_disabled <= '0';
memory_enable_local <= '0';
case instruction_data(0 to 7) is
when "00000000" =>
current_instruction.opcode <= LOAD;
current_instruction.reg0 <= unsigned(instruction_data(8 to 11));
current_instruction.reg1 <= unsigned(instruction_data(12 to 15));
current_instruction.address <= unsigned(instruction_data(16 to 31));
if unsigned(instruction_data(8 to 11)) = 0 then
current_instruction.size <= 3;
elsif unsigned(instruction_data(8 to 11)) = 1 then
current_instruction.size <= 4;
elsif unsigned(instruction_data(8 to 11)) = 2 then
current_instruction.size <= 4;
end if;
when "00000001" =>
current_instruction.opcode <= STORE;
current_instruction.size <= 4;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
current_instruction.address <= unsigned(instruction_data(16 to 31));
when "00000010" =>
current_instruction.opcode <= WRITE_IO;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00000011" =>
current_instruction.opcode <= READ_IO;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00010000" =>
current_instruction.opcode <= ADD;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00010001" =>
current_instruction.opcode <= SUBTRACT;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00010010" =>
current_instruction.opcode <= MULTIPLY;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00010011" =>
current_instruction.opcode <= DIVIDE;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000000" =>
current_instruction.opcode <= BITWISE_AND;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000001" =>
current_instruction.opcode <= BITWISE_OR;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000010" =>
current_instruction.opcode <= BITWISE_NAND;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000011" =>
current_instruction.opcode <= BITWISE_NOR;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000100" =>
current_instruction.opcode <= BITWISE_XOR;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000101" =>
current_instruction.opcode <= BITWISE_NOT;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110000" =>
current_instruction.opcode <= GREATER_THAN;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110001" =>
current_instruction.opcode <= GREATER_OR_EQUAL_THAN;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110010" =>
current_instruction.opcode <= LESS_THAN;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110011" =>
current_instruction.opcode <= LESS_OR_EQUAL_THAN;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110100" =>
current_instruction.opcode <= EQUAL;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110101" =>
current_instruction.opcode <= NOT_EQUAL;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00100000" =>
current_instruction.opcode <= JUMP;
current_instruction.size <= 3;
current_instruction.address <= bits_to_memory_address(instruction_data(8 to 23));
when "00100010" =>
current_instruction.opcode <= JUMP_IF_CARRY;
current_instruction.size <= 3;
current_instruction.address <= bits_to_memory_address(instruction_data(8 to 23));
when others =>
current_instruction.opcode <= HALT;
current_instruction.size <= 1;
end case;
state <= execute;
when execute =>
mux_disabled <= '0';
program_counter <= program_counter + current_instruction.size;
case current_instruction.opcode is
-- [[[cog
--import re
--
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content:
-- cog.outl("when {0} => instruction_enabler <= ({1} => '1', others => '0');".format(re.sub('([a-z0-9])([A-Z])', r'\1_\2', re.sub('(.)([A-Z][a-z]+)', r'\1_\2', line)).upper(), counter))
-- counter = counter + 1
--]]]
when LOAD => instruction_enabler <= (0 => '1', others => '0');
when STORE => instruction_enabler <= (1 => '1', others => '0');
when WRITE_IO => instruction_enabler <= (2 => '1', others => '0');
when READ_IO => instruction_enabler <= (3 => '1', others => '0');
when ADD => instruction_enabler <= (4 => '1', others => '0');
when SUBTRACT => instruction_enabler <= (5 => '1', others => '0');
when MULTIPLY => instruction_enabler <= (6 => '1', others => '0');
when DIVIDE => instruction_enabler <= (7 => '1', others => '0');
when BITWISE_AND => instruction_enabler <= (8 => '1', others => '0');
when BITWISE_OR => instruction_enabler <= (9 => '1', others => '0');
when BITWISE_NAND => instruction_enabler <= (10 => '1', others => '0');
when BITWISE_NOR => instruction_enabler <= (11 => '1', others => '0');
when BITWISE_XOR => instruction_enabler <= (12 => '1', others => '0');
when BITWISE_NOT => instruction_enabler <= (13 => '1', others => '0');
when GREATER_THAN => instruction_enabler <= (14 => '1', others => '0');
when GREATER_OR_EQUAL_THAN => instruction_enabler <= (15 => '1', others => '0');
when LESS_THAN => instruction_enabler <= (16 => '1', others => '0');
when LESS_OR_EQUAL_THAN => instruction_enabler <= (17 => '1', others => '0');
when EQUAL => instruction_enabler <= (18 => '1', others => '0');
when NOT_EQUAL => instruction_enabler <= (19 => '1', others => '0');
when JUMP => instruction_enabler <= (20 => '1', others => '0');
when JUMP_IF_CARRY => instruction_enabler <= (21 => '1', others => '0');
when HALT => instruction_enabler <= (22 => '1', others => '0');
when RESET => instruction_enabler <= (23 => '1', others => '0');
-- [[[end]]]
when others =>
instruction_enabler <= (others => '0');
end case;
state <= wait_execute;
when wait_execute =>
-- program_counter <=
-- jump_program_counter when jump_program_counter_set = '1' else
-- jump_if_carry_program_counter when jump_if_carry_program_counter_set = '1' else
-- program_counter;
if jump_program_counter_set = '1' then
program_counter <= jump_program_counter;
elsif jump_if_carry_program_counter_set = '1' then
program_counter <= jump_if_carry_program_counter;
else
program_counter <= program_counter;
end if;
case current_instruction.opcode is
-- [[[cog
--import re
--
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content:
-- cog.outl("when {0} => ".format(re.sub('([a-z0-9])([A-Z])', r'\1_\2', re.sub('(.)([A-Z][a-z]+)', r'\1_\2', line)).upper(), counter))
-- cog.outl("\tif instruction_ready({0}) = '1' then".format(counter))
-- cog.outl("\t\tinstruction_enabler <= (others => '0');")
-- cog.outl("\t\tmux_disabled <= '1';")
-- cog.outl("\t\tstate <= read_memory0;")
-- cog.outl("\telse")
-- cog.outl("\t\tstate <= wait_execute;")
-- cog.outl("\tend if;")
-- counter = counter + 1
--]]]
when LOAD =>
if instruction_ready(0) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when STORE =>
if instruction_ready(1) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when WRITE_IO =>
if instruction_ready(2) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when READ_IO =>
if instruction_ready(3) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when ADD =>
if instruction_ready(4) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when SUBTRACT =>
if instruction_ready(5) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when MULTIPLY =>
if instruction_ready(6) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when DIVIDE =>
if instruction_ready(7) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_AND =>
if instruction_ready(8) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_OR =>
if instruction_ready(9) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_NAND =>
if instruction_ready(10) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_NOR =>
if instruction_ready(11) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_XOR =>
if instruction_ready(12) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_NOT =>
if instruction_ready(13) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when GREATER_THAN =>
if instruction_ready(14) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when GREATER_OR_EQUAL_THAN =>
if instruction_ready(15) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when LESS_THAN =>
if instruction_ready(16) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when LESS_OR_EQUAL_THAN =>
if instruction_ready(17) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when EQUAL =>
if instruction_ready(18) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when NOT_EQUAL =>
if instruction_ready(19) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when JUMP =>
if instruction_ready(20) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when JUMP_IF_CARRY =>
if instruction_ready(21) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when HALT =>
if instruction_ready(22) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when RESET =>
if instruction_ready(23) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
-- [[[end]]]
end case;
end case;
end if;
end process;
end InstructionControllerImpl;
| bsd-3-clause |
Rogiel/BananaCore | Source/Instruction/Executor/BitwiseAndInstructionExecutor.vhd | 1 | 3970 | --
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The BitwiseAndInstructionExecutor entity
entity BitwiseAndInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic;
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic
);
end BitwiseAndInstructionExecutor;
architecture BitwiseAndInstructionExecutorImpl of BitwiseAndInstructionExecutor is
type state_type is (
fetch_arg0,
store_arg0,
fetch_arg1,
store_arg1,
execute,
store_result,
complete
);
signal state: state_type := fetch_arg0;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_arg0 =>
instruction_ready <= '0';
register_address <= arg0_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg0;
when store_arg0 =>
if register_ready = '1' then
arg0 <= register_data_read;
register_enable <= '0';
state <= fetch_arg1;
else
state <= store_arg0;
end if;
when fetch_arg1 =>
register_address <= arg1_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg1;
when store_arg1 =>
if register_ready = '1' then
arg1 <= register_data_read;
register_enable <= '0';
state <= execute;
else
state <= store_arg1;
end if;
when execute =>
result <= arg0 and arg1;
state <= store_result;
when store_result =>
register_address <= AccumulatorRegister;
register_operation <= OP_REG_SET;
register_data_write <= result;
register_enable <= '1';
instruction_ready <= '1';
state <= complete;
when complete =>
state <= complete;
end case;
else
instruction_ready <= '0';
state <= fetch_arg0;
end if;
end if;
end process;
end BitwiseAndInstructionExecutorImpl;
| bsd-3-clause |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC/Top.vhd | 1 | 8544 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity de0_nano_system is
port
( CLOCK_50 : in std_logic
; GPIO_0 : inout std_logic_vector(33 downto 0)
; GPIO_1 : inout std_logic_vector(33 downto 0)
-- Removed for logic analyser GPIO_2 : inout std_logic_vector(12 downto 0);
; GPIO_0_IN : in std_logic_vector(1 downto 0)
; GPIO_1_IN : in std_logic_vector(1 downto 0)
; GPIO_2_IN : in std_logic_vector(2 downto 0)
-- SDRAM IS42S16160B (143MHz@CL-3) is used.
; DRAM_CLK : out std_logic
; DRAM_CKE : out std_logic
; DRAM_CS_N : out std_logic
; DRAM_RAS_N : out std_logic
; DRAM_CAS_N : out std_logic
; DRAM_WE_N : out std_logic
; DRAM_DQ : inout std_logic_vector(15 downto 0)
; DRAM_DQM : out std_logic_vector(1 downto 0)
; DRAM_ADDR : out std_logic_vector(12 downto 0)
; DRAM_BA : out std_logic_vector(1 downto 0)
; EPCS_DCLK : out std_logic
; EPCS_NCSO : out std_logic
; EPCS_ASDO : out std_logic
; EPCS_DATA0 : in std_logic
; LED : out std_logic_vector(7 downto 0)
; KEY : in std_logic_vector(1 downto 0)
; SW : in std_logic_vector(3 downto 0)
; ADC_SDAT : in std_logic
; ADC_SADDR : out std_logic
; ADC_SCLK : out std_logic
; ADC_CS_N : out std_logic
; G_SENSOR_INT : in std_logic
; G_SENSOR_CS_N : out std_logic
-- EEPROM
; I2C_SDAT : in std_logic
; I2C_SCLK : out std_logic
);
end entity de0_nano_system;
architecture syn of de0_nano_system is
component pll_sys
port
( inclk0 : in std_logic := '0'
; c0 : out std_logic
; c1 : out std_logic
; locked : out std_logic
);
end component pll_sys;
component jtagtestrw is
port
( tdi : out std_logic
; tdo : in std_logic := '0'
; ir_in : out std_logic_vector(2 downto 0)
; ir_out : in std_logic_vector(2 downto 0) := (others => '0')
; virtual_state_cdr : out std_logic
; virtual_state_sdr : out std_logic
; virtual_state_e1dr : out std_logic
; virtual_state_pdr : out std_logic
; virtual_state_e2dr : out std_logic
; virtual_state_udr : out std_logic
; virtual_state_cir : out std_logic
; virtual_state_uir : out std_logic
; tck : out std_logic
);
end component jtagtestrw;
component clckctrl is
port
( inclk : in std_logic := 'X' -- inclk
; ena : in std_logic := 'X' -- ena
; outclk : out std_logic -- outclk
);
end component clckctrl;
signal sys_clk : std_logic;
signal clk_10 : std_logic;
signal pll_locked : std_logic;
signal tdi : std_logic;
signal tdo : std_logic;
signal tck : std_logic;
signal ir_in : std_logic_vector(2 downto 0);
signal sdr : std_logic;
signal udr : std_logic;
signal cdr : std_logic;
signal vdr_out : std_logic_vector(11 downto 0);
signal vdr_out_rdy : std_logic;
signal vdr_in : std_logic_vector(11 downto 0);
signal pp2_vdr_out : std_logic_vector(28 downto 0);
signal dbg_data : std_logic_vector(15 downto 0);
signal dbg_clk : std_logic;
signal dbg_trg : std_logic;
signal dbg_rst_in : std_logic;
signal pp_reset : std_logic;
signal pp_rst_in : std_logic;
function to_stdulogic( V: Boolean ) return std_ulogic is
begin
if V then
return '1';
else
return '0';
end if;
end to_stdulogic;
function to_Boolean( V: std_ulogic ) return Boolean is
begin
if V = '1' then
return True;
else
return False;
end if;
end to_Boolean;
begin
inst_pll_sys : pll_sys
port map
( inclk0 => CLOCK_50
, c0 => sys_clk
, c1 => clk_10
, locked => pll_locked
);
inst_heartbeat : counter_div
generic map
( OFFSET => 21
, BIT_WIDTH => 1
)
port map
( clk => clk_10
, counter_out => LED(0 downto 0)
);
-- IR WIDTH must be 3 at the moment.
-- For addressing VIR and sizing data for the virtual JTAG you can observe the
-- Compilation Report/Analysis and Synthesis/Debug settings summary/Virtual JTAG settings
-- Which give parameters that are used in JtagRW.hs (#nastyhack for now)
-- virAddrLen <= "User DR1 Length"
-- virAddrLen <= " Address"
-- and likely the 0xE, 0xC - TBC
-- Can also get those parameters via TCL
-- open_device -hardware_name {USB-Blaster [1-1]} -device_name {@1: EP3C25/EP4CE22 (0x020F30DD)}
-- device_lock -timeout 10000
-- device_virtual_ir_shift -instance_index 0 -ir_value 1 -show_equivalent_device_ir_dr_shift
--
--Info (16701): device_ir_shift -ir_value 14
--Info (16701): device_dr_shift -length 12 -dr_value 00B -value_in_hex
--Info (16701): device_dr_shift -length 12 -dr_value 401 -value_in_hex
-- These can be interogated from the FPGA - problem for later.
-- These change parameters as more JTAG components are added/removed
-- Such as:
-- * virtual JTAG
-- * extractable RAM
-- * Signal II analyser
-- Note: the clash generated RAM can not be made readable as is already dual port.
inst_jtagtest : jtagtestrw
port map
( tdi => tdi
, tdo => tdo
, ir_in => ir_in
, virtual_state_sdr => sdr
, virtual_state_udr => udr
, virtual_state_cdr => cdr
, tck => tck
);
inst_jtag_if : jtagif2
generic map
( DR_BITS => 12 )
port map
( aclr => '0'
, tck => tck
, tdi => tdi
, tdo => tdo
, sdr => sdr
, udr => udr
, cdr => cdr
, ir_in => ir_in
, vdr_out => vdr_out
, vdr_out_rdy => vdr_out_rdy
, vdr_in => vdr_in
-- , vdr_in_rdy
);
-- synchroniser on the pll_locked
inst_pp_clk : clckctrl
port map
( inclk => tck
, ena => pll_locked
, outclk => pp_rst_in
);
inst_pp_reset : counter_hold
generic map
( HOLD_FOR => 4 )
port map
( clk => pp_rst_in
, hold_out => pp_reset
);
inst_pkt_proc : packetprocessor_topentity
port map
( input_0_0 => vdr_out
, input_0_1 => to_Boolean(vdr_out_rdy)
-- clock
, system1000 => tck
-- asynchronous reset: active low
, system1000_rstn => pp_reset
, std_logic_vector(output_0_0) => vdr_in(11 downto 3)
, to_stdulogic(output_0_1) => vdr_in(2)
, to_stdulogic(output_0_2) => vdr_in(1)
);
inst_pkt_proc2 : packetprocessordf_topentity
port map
( input_0_0 => pp2_vdr_out
, input_0_1 => to_Boolean(vdr_out_rdy)
-- clock
, system1000 => tck
-- asynchronous reset: active low
, system1000_rstn => pp_reset
--, std_logic_vector(output_0_0) => dbg_data(15 downto 5)
, std_logic_vector(output_0_1) => dbg_data(15 downto 5)
, std_logic_vector(output_0_2) => dbg_data(4 downto 1)
--, std_logic_vector(output_0_3) => dbg_data(1)
, to_stdulogic(output_0_8) => dbg_data(0)
);
pp2_vdr_out <= vdr_out & "00000000000000000";
-- Since we can't actively use the Signal2 logic analyser whilst using
-- Jtag for data we can capture some events here and extract when the
-- Jtag is done. Not pretty but works OK. See runMemGet.sh at top level.
-- tcl:
-- begin_memory_edit -hardware_name "USB-Blaster \[1-1\]" -device_name "@1: EP3C25/EP4CE22 (0x020F30DD)"
-- puts [read_content_from_memory -instance_index 0 -start_address 0 -word_count 8192 -content_in_hex]
-- end_memory_edit
inst_ds_clk : clckctrl
port map
( inclk => sys_clk
, ena => pll_locked
, outclk => dbg_clk
);
inst_dbgsnap : dbgsnap
port map
( clk => dbg_clk
, tr => dbg_trg
, dbg_in => dbg_data
);
-- Just for testing...
-- dbg_data <= vdr_out & tck & sdr & cdr & udr;
dbg_trg <= udr;
LED(7 downto 1) <= vdr_in(10 downto 4);
vdr_in(0 downto 0) <= "0";
end architecture syn;
-- *** EOF *** | bsd-3-clause |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC_MOORE/PacketProcessor/packetprocessor_blockram.vhdl | 2 | 2845 | -- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessor_types.all;
entity packetprocessor_blockram is
port(rd : in unsigned(10 downto 0);
wrm : in std_logic_vector(19 downto 0);
-- clock
system1000 : in std_logic;
result : out unsigned(7 downto 0));
end;
architecture structural of packetprocessor_blockram is
signal x2 : unsigned(10 downto 0);
signal wild2_app_arg : signed(63 downto 0);
signal y : unsigned(7 downto 0);
signal wild2 : signed(63 downto 0);
signal x1 : packetprocessor_types.tup2_0;
signal result_0 : signed(63 downto 0);
signal wild_app_arg : signed(63 downto 0);
signal case_alt : unsigned(7 downto 0);
signal case_alt_0 : signed(63 downto 0);
signal wild : signed(63 downto 0);
signal app_arg : unsigned(7 downto 0);
signal app_arg_0 : signed(63 downto 0);
signal app_arg_1 : boolean;
signal result_1 : signed(63 downto 0);
begin
-- blockRam begin
packetprocessor_blockram_blockram : block
signal ram : packetprocessor_types.array_of_unsigned_8(0 to 2047) := (packetprocessor_types.array_of_unsigned_8'(0 to 2048-1 => to_unsigned(0,8) ));
signal dout : unsigned(7 downto 0);
signal rd_0 : integer range 0 to 2048 - 1;
signal wr : integer range 0 to 2048 - 1;
begin
rd_0 <= to_integer(result_1)
-- pragma translate_off
mod 2048
-- pragma translate_on
;
wr <= to_integer(app_arg_0)
-- pragma translate_off
mod 2048
-- pragma translate_on
;
blockram_sync : process(system1000)
begin
if rising_edge(system1000) then
if app_arg_1 then
ram(wr) <= app_arg;
end if;
dout <= ram(rd_0);
end if;
end process;
result <= dout;
end block;
-- blockRam end
x2 <= x1.tup2_0_sel0;
wild2_app_arg <= signed(std_logic_vector(resize(x2,64)));
y <= x1.tup2_0_sel1;
wild2 <= wild2_app_arg;
x1 <= (tup2_0_sel0 => unsigned(wrm(18 downto 8))
,tup2_0_sel1 => unsigned(wrm(7 downto 0)));
result_0 <= wild2;
wild_app_arg <= signed(std_logic_vector(resize(rd,64)));
case_alt <= y;
case_alt_0 <= result_0;
wild <= wild_app_arg;
with (wrm(19 downto 19)) select
app_arg <= unsigned'(0 to 7 => 'X') when "0",
case_alt when others;
with (wrm(19 downto 19)) select
app_arg_0 <= signed'(0 to 63 => 'X') when "0",
case_alt_0 when others;
with (wrm(19 downto 19)) select
app_arg_1 <= false when "0",
true when others;
result_1 <= wild;
end;
| bsd-3-clause |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC_MOORE/clckctrl/synthesis/unnamed.vhd | 4 | 856 | -- unnamed.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity unnamed is
port (
inclk : in std_logic := '0'; -- altclkctrl_input.inclk
ena : in std_logic := '0'; -- .ena
outclk : out std_logic -- altclkctrl_output.outclk
);
end entity unnamed;
architecture rtl of unnamed is
component unnamed_altclkctrl_0 is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component unnamed_altclkctrl_0;
begin
altclkctrl_0 : component unnamed_altclkctrl_0
port map (
inclk => inclk, -- altclkctrl_input.inclk
ena => ena, -- .ena
outclk => outclk -- altclkctrl_output.outclk
);
end architecture rtl; -- of unnamed
| bsd-3-clause |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC_MOORE/pll_sys_inst.vhd | 2 | 121 | pll_sys_inst : pll_sys PORT MAP (
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig,
locked => locked_sig
);
| bsd-3-clause |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC_MOORE/test/test_dbgsnap.vhd | 2 | 1630 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.dbgsnap;
entity dbgsnap_testbench is
port(done : out boolean);
end;
architecture structural of dbgsnap_testbench is
signal finished : boolean;
signal clk : boolean;
signal tr : std_logic;
signal dbg_in : unsigned(15 downto 0):= to_unsigned(0,16);
function to_stdulogic( V: Boolean ) return std_ulogic is
begin
if V then
return '1';
else
return '0';
end if;
end to_stdulogic;
begin
done <= finished;
-- pragma translate_off
process is
begin
clk <= false;
wait for 3 ns;
while (not finished) loop
clk <= not clk;
wait for 500 ns;
clk <= not clk;
wait for 500 ns;
end loop;
wait;
end process;
process is
begin
wait for 3 ns;
while (not finished) loop
dbg_in <= dbg_in + 1;
wait for 1000 ns;
end loop;
wait;
end process;
-- pragma translate_on
-- pragma translate_off
-- pragma translate_on
totest : entity dbgsnap
port map
( clk => to_stdulogic(clk)
, tr => tr
, dbg_in => std_logic_vector(dbg_in)
);
tr <=
-- pragma translate_off
'0',
-- pragma translate_on
'1'
-- pragma translate_off
after 1000 ns
-- pragma translate_on
;
finished <=
-- pragma translate_off
false,
-- pragma translate_on
true
-- pragma translate_off
after 8200000 ns
-- pragma translate_on
;
end;
| bsd-3-clause |
Rogiel/BananaCore | Source/Instruction/Executor/LessThanInstructionExecutor.vhd | 1 | 4032 | --
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The LessThanInstructionExecutor entity
entity LessThanInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic := '0';
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic
);
end LessThanInstructionExecutor;
architecture LessThanInstructionExecutorImpl of LessThanInstructionExecutor is
type state_type is (
fetch_arg0,
store_arg0,
fetch_arg1,
store_arg1,
execute,
store_result,
complete
);
signal state: state_type := fetch_arg0;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: std_logic;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_arg0 =>
instruction_ready <= '0';
register_address <= arg0_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg0;
when store_arg0 =>
if register_ready = '1' then
arg0 <= register_data_read;
register_enable <= '0';
state <= fetch_arg1;
else
state <= store_arg0;
end if;
when fetch_arg1 =>
register_address <= arg1_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg1;
when store_arg1 =>
if register_ready = '1' then
arg1 <= register_data_read;
register_enable <= '0';
state <= execute;
else
state <= store_arg1;
end if;
when execute =>
if arg0 < arg1 then
result <= '1';
else
result <= '0';
end if;
state <= store_result;
when store_result =>
register_address <= SpecialRegister;
register_operation <= OP_REG_SET;
register_data_write(CarryBit) <= result;
register_enable <= '1';
instruction_ready <= '1';
state <= complete;
when complete =>
state <= complete;
end case;
else
instruction_ready <= '0';
state <= fetch_arg0;
end if;
end if;
end process;
end LessThanInstructionExecutorImpl;
| bsd-3-clause |
Rogiel/BananaCore | Source/Instruction/Executor/BitwiseNotInstructionExecutor.vhd | 1 | 3970 | --
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The BitwiseNotInstructionExecutor entity
entity BitwiseNotInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic;
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic
);
end BitwiseNotInstructionExecutor;
architecture BitwiseNotInstructionExecutorImpl of BitwiseNotInstructionExecutor is
type state_type is (
fetch_arg0,
store_arg0,
fetch_arg1,
store_arg1,
execute,
store_result,
complete
);
signal state: state_type := fetch_arg0;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_arg0 =>
instruction_ready <= '0';
register_address <= arg0_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg0;
when store_arg0 =>
if register_ready = '1' then
arg0 <= register_data_read;
register_enable <= '0';
state <= fetch_arg1;
else
state <= store_arg0;
end if;
when fetch_arg1 =>
register_address <= arg1_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg1;
when store_arg1 =>
if register_ready = '1' then
arg1 <= register_data_read;
register_enable <= '0';
state <= execute;
else
state <= store_arg1;
end if;
when execute =>
result <= not arg0;
state <= store_result;
when store_result =>
register_address <= AccumulatorRegister;
register_operation <= OP_REG_SET;
register_data_write <= result;
register_enable <= '1';
instruction_ready <= '1';
state <= complete;
when complete =>
state <= complete;
end case;
else
instruction_ready <= '0';
state <= fetch_arg0;
end if;
end if;
end process;
end BitwiseNotInstructionExecutorImpl;
| bsd-3-clause |
plessl/zippy | vhdl/tb_arch/tstfir4/tb_tstfir4.vhd | 1 | 10561 | ------------------------------------------------------------------------------
-- Testbench for the tstfir4 function of the zunit
--
-- Project :
-- File : tb_tstfir4.vhd
-- Author : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/15
-- $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
-- $Id: tb_tstfir4.vhd 217 2005-01-13 16:52:03Z plessl $
------------------------------------------------------------------------------
-- This testbench tests the tstfir4 function of the zunit.
--
-- The primary goals of this testbench are:
-- test extension of cell to support 3 inputs (operands)
-- test ternary operators (mux is a ternary operator)
-- test the alu_mux function
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-28 CP created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTFIR4.all;
entity tb_tstfir4 is
end tb_tstfir4;
architecture arch of tb_tstfir4 is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- test vector and expected response
constant COEFS : coeff4array := (1,2,3,1);
constant NDATA : integer := 20; -- nr. of data elements
constant NRUNCYCLES : integer := NDATA+2; -- nr. of run cycles
type fifo_array is array (0 to NDATA-1) of natural;
constant TESTV : fifo_array :=
(1,0,0,1,2,0,0,2,3,0,0,3,1,0,0,1,0,0,0,0);
-- (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
constant EXPRESP : fifo_array :=
(1,2,3,2,4,7,7,4,7,12,11,6,7,11,6,2,2,3,1,0);
-- (1,2,3,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
-- configuration stuff
signal Cfg : engineConfigRec := tstfir4cfg(COEFS);
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstfir4_cfg.h";
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable expectedresponse : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-------------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(DATAWIDTH-1 downto 0) <= std_logic_vector(to_unsigned(TESTV(i), DATAWIDTH));
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-------------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-------------------------------------------------
-- computation running
-------------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO0:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
expectedresponse := std_logic_vector(to_unsigned(EXPRESP(i),DATAWIDTH));
response := DataOutxD(DATAWIDTH-1 downto 0);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity note;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause |
rhalstea/cidr_15_fpga_join | build_engine/vhdl/generic_fifo.vhd | 2 | 2632 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Fall Through FIFO
entity generic_fifo is
generic (
DATA_WIDTH : natural := 8;
DATA_DEPTH : natural := 32;
AFULL_POS : natural := 24
);
port (
clk : in std_logic;
rst : in std_logic;
afull_out : out std_logic;
write_en_in : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
empty_out : out std_logic;
read_en_in : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end generic_fifo;
architecture Behavioral of generic_fifo is
type FIFO_T is array (DATA_DEPTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory_s : FIFO_T;
signal push_pointer_s : natural;
signal pop_pointer_s : natural;
signal afull_s : std_logic;
signal empty_s : std_logic;
begin
-- Push element onto the FIFO
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
push_pointer_s <= 0;
elsif write_en_in = '1' then
memory_s(push_pointer_s) <= data_in;
if push_pointer_s >= DATA_DEPTH-1 then
push_pointer_s <= 0;
else
push_pointer_s <= push_pointer_s + 1;
end if;
end if;
end if;
end process;
-- Pop element from the FIFO
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
pop_pointer_s <= 0;
elsif read_en_in = '1' and empty_s = '0' then
if pop_pointer_s >= DATA_DEPTH-1 then
pop_pointer_s <= 0;
else
pop_pointer_s <= pop_pointer_s + 1;
end if;
end if;
end if;
end process;
empty_s <= '1' when push_pointer_s = pop_pointer_s else '0';
afull_s <= '1' when ((push_pointer_s > pop_pointer_s) and (push_pointer_s - pop_pointer_s > AFULL_POS)) or
((push_pointer_s < pop_pointer_s) and (DATA_DEPTH-1 - pop_pointer_s + push_pointer_s > AFULL_POS))
else '0';
empty_out <= empty_s;
afull_out <= afull_s;
data_out <= memory_s(pop_pointer_s);
end Behavioral;
| bsd-3-clause |
plessl/zippy | vhdl/ioportctrl.vhd | 1 | 5388 | ------------------------------------------------------------------------------
-- I/O port controller of ZIPPY engine
--
-- Project :
-- File : $URL: svn+ssh://plessl@yosemite.ethz.ch/home/plessl/SVN/simzippy/trunk/vhdl/ioportctrl.vhd $
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/20
-- $Id: ioportctrl.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
-- I/O port controller controls the read/write enables of the FIFOs. Each IO
-- port controller features a 4LUT that computes any boolean function of the
-- following 4 signals:
-- LUT(0) : bit 0 of the cycle counter (up counter)
-- LUT(1) : bit 1 of the cycle counter (up counter)
-- LUT(2) : result 0 of cycle up/dwn counter greater/equal constant Cmp0
-- LUT(3) : result 1 of cycle up/dwn counter greater/equal constant Cmp1
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- compare unit
------------------------------------------------------------------------------
-- 2 modi: greater than (GT), equal (EQ)
library ieee;
use ieee.std_logic_1164.all;
entity IOP_Compare is
generic (
OPWIDTH : integer);
port (
ConfigxS : in std_logic;
Op0xDI : in std_logic_vector(OPWIDTH-1 downto 0);
Op1xDI : in std_logic_vector(OPWIDTH-1 downto 0);
CmpxDO : out std_logic);
end IOP_Compare;
architecture simple of IOP_Compare is
begin -- simple
Compare : process (ConfigxS, Op0xDI, Op1xDI)
begin
if (ConfigxS = '0') then -- GT modus
if (Op0xDI > Op1xDI) then
CmpxDO <= '1';
else
CmpxDO <= '0';
end if;
else -- EQ modus
if (Op0xDI = Op1xDI) then
CmpxDO <= '1';
else
CmpxDO <= '0';
end if;
end if;
end process Compare;
end simple;
------------------------------------------------------------------------------
-- 4-LUT
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LookUpTable4to1 is
port (
ConfigxDI : in std_logic_vector(15 downto 0);
In0xDI : in std_logic;
In1xDI : in std_logic;
In2xDI : in std_logic;
In3xDI : in std_logic;
OutxDO : out std_logic);
end LookUpTable4to1;
architecture simple of LookUpTable4to1 is
signal AddrxD : std_logic_vector(3 downto 0);
begin -- simple
AddrxD <= In3xDI & In2xDI & In1xDI & In0xDI;
OutxDO <= ConfigxDI(to_integer(unsigned(AddrxD)));
end simple;
------------------------------------------------------------------------------
-- IO port controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
entity IOPortCtrl is
generic (
CCNTWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ConfigxI : in ioportConfigRec;
CycleDnCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
PortxEO : out std_logic);
end IOPortCtrl;
architecture simple of IOPortCtrl is
component IOP_Compare
generic (
OPWIDTH : integer);
port (
ConfigxS : in std_logic;
Op0xDI : in std_logic_vector(OPWIDTH-1 downto 0);
Op1xDI : in std_logic_vector(OPWIDTH-1 downto 0);
CmpxDO : out std_logic);
end component;
component LookUpTable4to1
port (
ConfigxDI : in std_logic_vector(15 downto 0);
In0xDI : in std_logic;
In1xDI : in std_logic;
In2xDI : in std_logic;
In3xDI : in std_logic;
OutxDO : out std_logic);
end component;
signal Cmp0InxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal Cmp1InxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal Cmp0OutxD : std_logic;
signal Cmp1OutxD : std_logic;
begin -- simple
Cmp0Mux : Mux2to1
generic map (
WIDTH => CCNTWIDTH)
port map (
SelxSI => ConfigxI.Cmp0MuxS,
In0xDI => CycleUpCntxDI,
In1xDI => CycleDnCntxDI,
OutxDO => Cmp0InxD);
Cmp0 : IOP_Compare
generic map (
OPWIDTH => CCNTWIDTH)
port map (
ConfigxS => ConfigxI.Cmp0ModusxS,
Op0xDI => Cmp0InxD,
Op1xDI => ConfigxI.Cmp0ConstxD,
CmpxDO => Cmp0OutxD);
Cmp1Mux : Mux2to1
generic map (
WIDTH => CCNTWIDTH)
port map (
SelxSI => ConfigxI.Cmp1MuxS,
In0xDI => CycleUpCntxDI,
In1xDI => CycleDnCntxDI,
OutxDO => Cmp1InxD);
Cmp1 : IOP_Compare
generic map (
OPWIDTH => CCNTWIDTH)
port map (
ConfigxS => ConfigxI.Cmp1ModusxS,
Op0xDI => Cmp1InxD,
Op1xDI => ConfigxI.Cmp1ConstxD,
CmpxDO => Cmp1OutxD);
Lut4 : LookUpTable4to1
port map (
ConfigxDI => ConfigxI.LUT4FunctxD,
In0xDI => CycleUpCntxDI(0),
In1xDI => CycleUpCntxDI(1),
In2xDI => Cmp0OutxD,
In3xDI => Cmp1OutxD,
OutxDO => PortxEO);
end simple;
| bsd-3-clause |
alexandruradovici/ace-builds | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
plessl/zippy | vhdl/tb_arch/tstfir8_virt/tb_tstfir8_virt.vhd | 1 | 12604 | ------------------------------------------------------------------------------
-- Testbench for zunit.vhd: configures an 8-tap FIR
--
-- Project :
-- File : tb_zunit-fir8.vhd
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/28
-- Last changed: $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- testbench for the fir8 case study. Used for standalone simulation and for
-- generating the configuration header file for system co-simulation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_FIR.all;
entity tb_tstfir8_virt is
end tb_tstfir8_virt;
architecture fir8 of tb_tstfir8_virt is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (tbstart, idle, done, rst,
push_data, inlevel, wr_ncycl, rd_ncycl, running,
outlevel, pop_data,
set_cntxt, wr_context0, wr_context1);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- contexts
signal Context0 : engineConfigRec :=
fir8mult( ( 1, 2, 1, 2, 2, 1, 2, 1));
signal Context1 : engineConfigRec :=
fir8mult_b(( 1, -1, 1, -1, -1, 1, -1, 1));
signal Context2 : engineConfigRec :=
fir8mult( ( 0, 1, 0, 1, 1, 0, 1, 0));
signal Context3 : engineConfigRec :=
fir8mult_b((-1, -2, 1, 2, 2, 1, -2, -1));
signal Context4 : engineConfigRec :=
fir8mult( ( 1, 2, -2, -2, -2, -2, 2, 1));
signal Context5 : engineConfigRec :=
fir8mult_b(( 3, 2, 1, 0, 0, 1, 2, 3));
signal Context6 : engineConfigRec :=
fir8mult( (-2, -1, 0, 1, 1, 0, -1, -2));
signal Context7 : engineConfigRec :=
fir8mult_b(( 1, 0, -2, -1, -1, -2, 0, 1));
signal Context0xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context0);
signal Context1xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context1);
signal Context2xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context2);
signal Context3xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context3);
signal Context4xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context4);
signal Context5xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context5);
signal Context6xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context6);
signal Context7xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context7);
signal Context0Prt : cfgPartArray := partition_config(Context0xD);
signal Context1Prt : cfgPartArray := partition_config(Context1xD);
signal Context2Prt : cfgPartArray := partition_config(Context2xD);
signal Context3Prt : cfgPartArray := partition_config(Context3xD);
signal Context4Prt : cfgPartArray := partition_config(Context4xD);
signal Context5Prt : cfgPartArray := partition_config(Context5xD);
signal Context6Prt : cfgPartArray := partition_config(Context6xD);
signal Context7Prt : cfgPartArray := partition_config(Context7xD);
-- aux. stuff
file HFILE : text open write_mode is "tstfir8_virt_cfg.h";
begin -- fir8
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
variable contextArr : contextPartArray;
begin -- process hFileGen
contextArr(0) := Context0Prt;
contextArr(1) := Context1Prt;
contextArr(2) := Context2Prt;
contextArr(3) := Context3Prt;
contextArr(4) := Context4Prt;
contextArr(5) := Context5Prt;
contextArr(6) := Context6Prt;
contextArr(7) := Context7Prt;
gen_contexthfile2(HFILE, contextArr);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
constant NDATA : integer := 20; -- nr. of data elements
constant NRUNCYCLES : integer := NDATA+1; -- nr. of run cycles
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- -----------------------------------------------
-- reset (ZREG_RST:W)
-- -----------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 0 (ZREG_CFGMEM0:W)
-- -----------------------------------------------
tbStatus <= wr_context0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in Context0Prt'low to Context0Prt'high loop
DataInxD <= Context0Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 1 (ZREG_CFGMEM1:W)
-- -----------------------------------------------
tbStatus <= wr_context1;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM1, IFWIDTH));
for i in Context1Prt'low to Context1Prt'high loop
DataInxD <= Context1Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- push data into FIFO 0 (ZREG_FIFO0:W)
-- -----------------------------------------------
tbStatus <= push_data;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
-- wait for CLK_PERIOD;
-- for i in 12 to NDATA loop
for i in 1 to NDATA loop
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- set context select register (ZREG_CONTEXTSEL:W)
-- -----------------------------------------------
tbStatus <= set_cntxt;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CONTEXTSEL, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-- -----------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-- -----------------------------------------------
-- computation running
-- -----------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 0 to NRUNCYCLES-1 loop
wait for CLK_PERIOD;
end loop; -- i
-- -----------------------------------------------
-- pop data from FIFO 1 (ZREG_FIFO1:R)
-- -----------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
for i in 1 to NDATA loop
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- done; stop simulation
-- -----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "ROGER; stimuli processed; sim. terminated after " &
str(ccount) & " cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end fir8;
| bsd-3-clause |
plessl/zippy | vhdl/tb_arch/tstadpcm/tb_tstadpcm.vhd | 1 | 12152 | ------------------------------------------------------------------------------
-- Testbench for the ADPCM configuration for the zippy array
--
-- Project :
-- File : $Id: $
-- Author : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/15
-- Changed : $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
-- This testbnech tests the ADPCM configuration for the zunit
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTADPCM.all;
entity tb_tstadpcm is
end tb_tstadpcm;
architecture arch of tb_tstadpcm is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant DELAY : integer := 2; -- processing delay of circuit,
-- due to pipelining
signal NDATA : integer := 0; -- nr. of data elements
signal NRUNCYCLES : integer := 0; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration stuff
signal Cfg : engineConfigRec := tstadpcmcfg;
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstadpcm_cfg.h";
file TVFILE : text open read_mode is "test.adpcm.txt"; -- adpcm encoded
-- input file
file ERFILE : text open read_mode is "test.pcm.txt"; -- decoded file in
-- PCM format
--------------------------------------------------------------------
-- test vectors
-- out = c(0) ? a : b
--
-- The testbench feeds input a also to the mux input, i.e. the output of the
-- multiplexer is alway determined by the LSB of input A
--------------------------------------------------------------------
begin -- arch
assert (N_ROWS = 7) report "configuration needs N_ROWS=7" severity failure;
assert (N_COLS = 7) report "configuration needs N_COLS=7" severity failure;
assert (N_HBUSN >= 2) report "configuration needs N_HBUSN>=2" severity failure;
assert (N_HBUSS >= 2) report "configuration needs N_HBUSS>=2" severity failure;
assert (N_VBUSE >= 1) report "configuration needs N_VBUSE>=1" severity failure;
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable expectedresponse : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable l : line;
variable tv : std_logic_vector(3 downto 0);
variable tvstring : string(tv'range);
variable expr : std_logic_vector(15 downto 0);
variable exprstring : string(expr'range);
variable tvcount : integer := 0;
begin -- process stimuliTb
-- while not endfile(TVFILE) loop
--
-- readline(TVFILE, l);
-- read(l, tvstring);
-- tv := to_std_logic_vector(tvstring); -- from txt_util
--
-- readline(ERFILE, l);
-- read(l, exprstring);
-- expr := to_std_logic_vector(exprstring);
--
-- assert false
-- report "tv=" & str(tv) & " expr= " & str(expr)
-- severity note;
-- end loop;
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-------------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
while not endfile(TVFILE) loop
readline(TVFILE, l);
read(l, tvstring);
tv := to_std_logic_vector(tvstring); -- defined in txt_util
DataInxD <= (others => '0');
DataInxD(3 downto 0) <= tv;
tvcount := tvcount + 1;
wait for CLK_PERIOD;
end loop;
-- determine length of data from input file
NDATA <= tvcount;
NRUNCYCLES <= tvcount + DELAY;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-------------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-------------------------------------------------
-- computation running
-------------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
-------------------------------------------------
-- pop 2 words from out buffer (ZREG_FIFO1:R)
-- delay of circuit due to registers (pipelining)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
wait for DELAY*CLK_PERIOD;
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO1:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
if not endfile(ERFILE) then
readline(ERFILE, l);
read(l, exprstring);
expr := to_std_logic_vector(exprstring);
else
expr := (others => '0');
end if;
expectedresponse := std_logic_vector(resize(signed(expr), DATAWIDTH));
response := DataOutxD(DATAWIDTH-1 downto 0);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause |
plessl/zippy | vhdl/testbenches/tb_SchedulerTemporalPartitioning.vhd | 1 | 3644 | -------------------------------------------------------------------------------
-- Title : Testbench for design "SchedulerTemporalPartitioning"
-- Project :
-------------------------------------------------------------------------------
-- File : SchedulerTemporalPartitioning_tb.vhd
-- Author : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Computer Engineering Lab, ETH Zurich
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
-------------------------------------------------------------------------------
entity SchedulerTemporalPartitioning_tb is
end SchedulerTemporalPartitioning_tb;
-------------------------------------------------------------------------------
architecture arch of SchedulerTemporalPartitioning_tb is
component SchedulerTemporalPartitioning
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ScheduleStartxEI : in std_logic;
ScheduleDonexSO : out std_logic;
NoTpContextsxSI : in unsigned(CNTXTWIDTH-1 downto 0);
NoTpUserCyclesxSI : in unsigned(CCNTWIDTH-1 downto 0);
CExEO : out std_logic;
ClrContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEO : out std_logic;
ContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0));
end component;
-- component ports
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
signal ScheduleStartxE : std_logic;
signal ScheduleDonexS : std_logic;
signal NoTpContextsxS : unsigned(CNTXTWIDTH-1 downto 0);
signal NoTpUserCyclesxS : unsigned(CCNTWIDTH-1 downto 0);
signal CExE : std_logic;
signal ClrContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0);
signal ClrContextxE : std_logic;
signal ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0);
signal CycleDnCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal CycleUpCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
begin -- arch
-- component instantiation
DUT : SchedulerTemporalPartitioning
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ScheduleStartxEI => ScheduleStartxE,
ScheduleDonexSO => ScheduleDonexS,
NoTpContextsxSI => NoTpContextsxS,
NoTpUserCyclesxSI => NoTpUserCyclesxS,
CExEO => CExE,
ClrContextxSO => ClrContextxS,
ClrContextxEO => ClrContextxE,
ContextxSO => ContextxS,
CycleDnCntxDO => CycleDnCntxD,
CycleUpCntxDO => CycleUpCntxD);
-- clock generation
ClkxC <= not ClkxC after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until ClkxC = '1';
NoTpUserCyclesxS <= to_unsigned(20, NoTpUserCyclesxS'length);
NoTpContextsxS <= to_unsigned(3, NoTpContextsxS'length);
RstxRB <= '0';
wait for 20 ns;
RstxRB <= '1';
ScheduleStartxE <= '1';
wait for 20 ns;
ScheduleStartxE <= '0';
wait for 1300 ns;
assert false report "simulation terminated" severity failure;
end process WaveGen_Proc;
end arch;
| bsd-3-clause |
plessl/zippy | vhdl/testbenches/tb_ioportctrl.vhd | 1 | 14247 | ------------------------------------------------------------------------------
-- Testbench for ioportctrl.vhd
--
-- Project :
-- File : tb_ioportctrl.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/20
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComponentsPkg.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
entity tb_IOPortCtrl is
end tb_IOPortCtrl;
architecture arch of tb_IOPortCtrl is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, exp1, exp2, exp3, exp4, exp5, exp6,
exp7, exp8);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT I/O signals
signal ConfigxI : ioportConfigRec;
signal CycleDnCntxDI : std_logic_vector(CCNTWIDTH-1 downto 0);
signal CycleUpCntxDI : std_logic_vector(CCNTWIDTH-1 downto 0);
signal PortxEO : std_logic;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : IOPortCtrl
generic map (
CCNTWIDTH => CCNTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ConfigxI => ConfigxI,
CycleDnCntxDI => CycleDnCntxDI,
CycleUpCntxDI => CycleUpCntxDI,
PortxEO => PortxEO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal ConfigxI : out ioportConfigRec;
signal CycleDnCntxDI : out std_logic_vector(CCNTWIDTH-1 downto 0);
signal CycleUpCntxDI : out std_logic_vector(CCNTWIDTH-1 downto 0)) is
begin
ConfigxI <= init_ioportConfig;
CycleDnCntxDI <= (others => '0');
CycleUpCntxDI <= (others => '0');
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
--------------------------------------------------------------------------
-- Experiment 1: always "1"
--------------------------------------------------------------------------
tbStatus <= exp1;
ConfigxI.LUT4FunctxD <= X"FFFF";
CycleDnCntxDI <= std_logic_vector(to_unsigned(7, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(6, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(4, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(2, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(1, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(0, CCNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- Experiment 2: "CycleDnCnt=3 => 1"
--------------------------------------------------------------------------
tbStatus <= exp2;
ConfigxI.Cmp0MuxS <= '1'; -- compare down counter
ConfigxI.Cmp0ModusxS <= '1'; -- modus "="
ConfigxI.Cmp0ConstxD <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
ConfigxI.LUT4FunctxD <= X"F0F0";
CycleDnCntxDI <= std_logic_vector(to_unsigned(7, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(6, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(4, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(2, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(1, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(0, CCNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- Experiment 3: "CycleDnCnt>3 => 1"
--------------------------------------------------------------------------
tbStatus <= exp3;
ConfigxI.Cmp0MuxS <= '1'; -- compare down counter
ConfigxI.Cmp0ModusxS <= '0'; -- modus ">"
ConfigxI.Cmp0ConstxD <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
ConfigxI.LUT4FunctxD <= X"F0F0";
CycleDnCntxDI <= std_logic_vector(to_unsigned(7, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(6, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(4, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(2, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(1, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(0, CCNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- Experiment 4: "CycleDnCnt<3 => 1" (NOTE: ^= NOT>2)
--------------------------------------------------------------------------
tbStatus <= exp4;
ConfigxI.Cmp0MuxS <= '1'; -- compare down counter
ConfigxI.Cmp0ModusxS <= '0'; -- modus ">"
ConfigxI.Cmp0ConstxD <= std_logic_vector(to_unsigned(2, CCNTWIDTH));
ConfigxI.LUT4FunctxD <= X"0F0F";
CycleDnCntxDI <= std_logic_vector(to_unsigned(7, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(6, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(4, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(2, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(1, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(0, CCNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- Experiment 5: "3<CycleDnCnt<6 => 1"
--------------------------------------------------------------------------
tbStatus <= exp5;
ConfigxI.Cmp0MuxS <= '1'; -- compare down counter
ConfigxI.Cmp0ModusxS <= '0'; -- modus ">"
ConfigxI.Cmp0ConstxD <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
ConfigxI.Cmp1MuxS <= '1'; -- compare down counter
ConfigxI.Cmp1ModusxS <= '0'; -- modus ">"
ConfigxI.Cmp1ConstxD <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
ConfigxI.LUT4FunctxD <= X"00F0";
CycleDnCntxDI <= std_logic_vector(to_unsigned(7, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(6, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(4, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(2, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(1, CCNTWIDTH));
wait for CLK_PERIOD;
CycleDnCntxDI <= std_logic_vector(to_unsigned(0, CCNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- Experiment 6: "CycleUpCnt(0)"
--------------------------------------------------------------------------
tbStatus <= exp6;
ConfigxI.LUT4FunctxD <= X"AAAA";
CycleUpCntxDI <= std_logic_vector(to_unsigned(0, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(1, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(2, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(4, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(6, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(7, CCNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- Experiment 7: "CycleUpCnt(1)"
--------------------------------------------------------------------------
tbStatus <= exp7;
ConfigxI.LUT4FunctxD <= X"CCCC";
CycleUpCntxDI <= std_logic_vector(to_unsigned(0, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(1, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(2, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(4, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(6, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(7, CCNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- Experiment 8: "3<CycleUpCnt<6 => 1"
--------------------------------------------------------------------------
tbStatus <= exp8;
ConfigxI.Cmp0MuxS <= '0'; -- compare up counter
ConfigxI.Cmp0ModusxS <= '0'; -- modus ">"
ConfigxI.Cmp0ConstxD <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
ConfigxI.Cmp1MuxS <= '0'; -- compare up counter
ConfigxI.Cmp1ModusxS <= '0'; -- modus ">"
ConfigxI.Cmp1ConstxD <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
ConfigxI.LUT4FunctxD <= X"00F0";
CycleUpCntxDI <= std_logic_vector(to_unsigned(0, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(1, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(2, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(3, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(4, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(5, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(6, CCNTWIDTH));
wait for CLK_PERIOD;
CycleUpCntxDI <= std_logic_vector(to_unsigned(7, CCNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait for CLK_PERIOD;
tbStatus <= done;
init_stimuli(ConfigxI, CycleDnCntxDI, CycleupCntxDI);
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause |
plessl/zippy | vhdl/componentsPkg.vhd | 1 | 16216 | -- Component declarations
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
use work.AuxPkg.all;
package ComponentsPkg is
component ZUnit
generic (
IFWIDTH : integer;
DATAWIDTH : integer;
CCNTWIDTH : integer;
FIFODEPTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
RExEI : in std_logic;
AddrxDI : in std_logic_vector(IFWIDTH-1 downto 0);
DataxDI : in std_logic_vector(IFWIDTH-1 downto 0);
DataxDO : out std_logic_vector(IFWIDTH-1 downto 0));
end component;
component Scheduler is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
SchedulerSelectxSI : in std_logic;
SchedContextSequencerxDI : in EngineScheduleControlType;
SchedTemporalPartitioningxDI : in EngineScheduleControlType;
EngineScheduleControlxEO : out EngineScheduleControlType
);
end component;
component SchedulerTemporalPartitioning is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
--
ScheduleStartxEI : in std_logic;
ScheduleDonexSO : out std_logic;
-- number of temporal contexts used in temporal partition
NoTpContextsxSI : in unsigned(CNTXTWIDTH-1 downto 0);
-- number of user clock-cycles to run
NoTpUserCyclesxSI : in unsigned(CCNTWIDTH-1 downto 0);
-- signals to engine
CExEO : out std_logic;
ClrContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEO : out std_logic;
ContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0)
);
end component;
component ScheduleStore
generic (
WRDWIDTH : integer;
CONWIDTH : integer;
CYCWIDTH : integer;
ADRWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
IAddrxDI : in std_logic_vector(ADRWIDTH-1 downto 0);
IWordxDI : in std_logic_vector(WRDWIDTH-1 downto 0);
SPCclrxEI : in std_logic;
SPCloadxEI : in std_logic;
ContextxDO : out std_logic_vector(CONWIDTH-1 downto 0);
CyclesxDO : out std_logic_vector(CYCWIDTH-1 downto 0);
LastxSO : out std_logic);
end component;
component ScheduleCtrl
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
StartxEI : in std_logic;
RunningxSI : in std_logic;
LastxSI : in std_logic;
SwitchxEO : out std_logic;
BusyxSO : out std_logic);
end component;
component ConfigMem
generic (
CFGWIDTH : integer;
PTRWIDTH : integer;
SLCWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
CfgSlicexDI : in std_logic_vector(SLCWIDTH-1 downto 0);
LoadSlicePtrxEI : in std_logic;
SlicePtrxDI : in std_logic_vector(PTRWIDTH-1 downto 0);
ConfigWordxDO : out std_logic_vector(CFGWIDTH-1 downto 0));
end component;
component ContextMux
generic (
NINP : integer);
port (
SelxSI : in std_logic_vector(log2(NINP)-1 downto 0);
InpxI : in contextArray;
OutxDO : out contextType);
end component;
component ContextSelCtrl
port (
DecEnxEI : in std_logic;
SchedEnxEI : in std_logic;
SchedBusyxSI : in std_logic;
CSREnxEO : out std_logic;
CSRMuxSO : out std_logic);
end component;
component Decoder
generic (
REGWIDTH : integer);
port (
RstxRB : in std_logic;
WrReqxEI : in std_logic;
RdReqxEI : in std_logic;
RegNrxDI : in std_logic_vector(REGWIDTH-1 downto 0);
SystRstxRBO : out std_logic;
CCloadxEO : out std_logic;
VirtContextNoxEO : out std_logic;
ContextSchedulerSelectxEO : out std_logic;
Fifo0WExEO : out std_logic;
Fifo0RExEO : out std_logic;
Fifo1WExEO : out std_logic;
Fifo1RExEO : out std_logic;
CMWExEO : out std_logic_vector(N_CONTEXTS-1 downto 0);
CMLoadPtrxEO : out std_logic_vector(N_CONTEXTS-1 downto 0);
CSRxEO : out std_logic;
EngClrCntxtxEO : out std_logic;
SSWExEO : out std_logic;
SSIAddrxDO : out std_logic_vector(SIW_ADRWIDTH-1 downto 0);
ScheduleStartxE : out std_logic;
DoutMuxSO : out std_logic_vector(2 downto 0));
end component;
component FifoCtrl
port (
RunningxSI : in std_logic;
EngInPortxEI : in std_logic;
EngOutPortxEI : in std_logic;
DecFifoWExEI : in std_logic;
DecFifoRExEI : in std_logic;
FifoMuxSO : out std_logic;
FifoWExEO : out std_logic;
FifoRExEO : out std_logic);
end component;
component CycleDnCntr
generic (
CNTWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CinxDI : in std_logic_vector(CNTWIDTH-1 downto 0);
OnxSO : out std_logic;
CoutxDO : out std_logic_vector(CNTWIDTH-1 downto 0));
end component;
component CycleCntCtrl
port (
DecLoadxEI : in std_logic;
SchedLoadxEI : in std_logic;
SchedBusyxSI : in std_logic;
CCLoadxEO : out std_logic;
CCMuxSO : out std_logic);
end component;
component Engine -- computation engine
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in engineConfigRec;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
InPortxDI : in engineInoutDataType;
OutPortxDO : out engineInoutDataType;
InPortxEO : out std_logic_vector(N_IOP-1 downto 0);
OutPortxEO : out std_logic_vector(N_IOP-1 downto 0));
end component;
component EngClearCtrl
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
DecEngClrxEI : in std_logic;
SchedStartxEI : in std_logic;
SchedSwitchxEI : in std_logic;
SchedBusyxSI : in std_logic;
SchedEngClrxSI : in std_logic;
EngClrxEO : out std_logic);
end component;
component IOPortCtrl -- I/O port controller
generic (
CCNTWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ConfigxI : in ioportConfigRec;
CycleDnCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
PortxEO : out std_logic);
end component;
component Row -- row of cells
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in rowConfigArray;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
InpxI : in rowInputArray;
OutxO : out rowOutputArray;
MemDataxDI : in data_vector(N_COLS-1 downto 0);
MemAddrxDO : out data_vector(N_COLS-1 downto 0);
MemDataxDO : out data_vector(N_COLS-1 downto 0);
MemCtrlxSO : out data_vector(N_COLS-1 downto 0)
);
end component;
component Cell -- cell (routing + proc. element)
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in cellConfigRec;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
-- data io signals
InputxDI : in cellInputRec;
OutputxZO : out CellOutputRec;
-- memory signals
MemDataxDI : in data_word;
MemAddrxDO : out data_word;
MemDataxDO : out data_word;
MemCtrlxSO : out data_word
);
end component;
component ProcEl -- processing element
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in procConfigRec;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
-- data io signals
InxDI : in procelInputArray;
OutxDO : out data_word;
-- memory signals
MemDataxDI : in data_word;
MemAddrxDO : out data_word;
MemDataxDO : out data_word;
MemCtrlxSO : out data_word
);
end component;
component RoutEl -- routing element
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ConfigxI : in routConfigRec;
InputxDI : in cellInputRec;
OutputxZO : out CellOutputRec;
ProcElInxDO : out procelInputArray;
ProcElOutxDI : in data_word
);
end component;
component CClkGating
port (
EnxEI : in std_logic;
MClockxCI : in std_logic;
CClockxCO : out std_logic);
end component;
component Fifo
generic (
WIDTH : integer;
DEPTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
RExEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0);
EmptyxSO : out std_logic;
FullxSO : out std_logic;
FillLevelxDO : out std_logic_vector(log2(DEPTH) downto 0));
end component;
component UpDownCounter
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CExEI : in std_logic;
ModexSI : in std_logic;
CinxDI : in std_logic_vector(WIDTH-1 downto 0);
CoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component FlipFlop
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic;
DoutxDO : out std_logic);
end component;
component FlipFlop_Clr
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxEI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic;
DoutxDO : out std_logic);
end component;
component Reg_En
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Reg_Clr_En
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxEI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Reg_AClr_En
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxABI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Rom is
generic (
DEPTH : integer
);
port (
ConfigxI : in data_vector(DEPTH-1 downto 0);
RdAddrxDI : in data_word;
RdDataxDO : out data_word
);
end component Rom;
component ContextRegFile
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
EnxEI : in std_logic;
DinxDI : in data_word;
DoutxDO : out data_word);
end component;
component Mux2to1
generic (
WIDTH : integer);
port (
SelxSI : in std_logic;
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Mux4to1
generic (
WIDTH : integer);
port (
SelxSI : in std_logic_vector(1 downto 0);
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
In2xDI : in std_logic_vector(WIDTH-1 downto 0);
In3xDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Mux8to1
generic (
WIDTH : integer);
port (
SelxSI : in std_logic_vector(2 downto 0);
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
In2xDI : in std_logic_vector(WIDTH-1 downto 0);
In3xDI : in std_logic_vector(WIDTH-1 downto 0);
In4xDI : in std_logic_vector(WIDTH-1 downto 0);
In5xDI : in std_logic_vector(WIDTH-1 downto 0);
In6xDI : in std_logic_vector(WIDTH-1 downto 0);
In7xDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Mux16to1
generic (
WIDTH : integer);
port (
SelxSI : in std_logic_vector(3 downto 0);
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
In2xDI : in std_logic_vector(WIDTH-1 downto 0);
In3xDI : in std_logic_vector(WIDTH-1 downto 0);
In4xDI : in std_logic_vector(WIDTH-1 downto 0);
In5xDI : in std_logic_vector(WIDTH-1 downto 0);
In6xDI : in std_logic_vector(WIDTH-1 downto 0);
In7xDI : in std_logic_vector(WIDTH-1 downto 0);
In8xDI : in std_logic_vector(WIDTH-1 downto 0);
In9xDI : in std_logic_vector(WIDTH-1 downto 0);
InAxDI : in std_logic_vector(WIDTH-1 downto 0);
InBxDI : in std_logic_vector(WIDTH-1 downto 0);
InCxDI : in std_logic_vector(WIDTH-1 downto 0);
InDxDI : in std_logic_vector(WIDTH-1 downto 0);
InExDI : in std_logic_vector(WIDTH-1 downto 0);
InFxDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component TristateBuf
generic (
WIDTH : integer);
port (
InxDI : in std_logic_vector(WIDTH-1 downto 0);
OExEI : in std_logic;
OutxZO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component PullBus
generic (
WIDTH : integer);
port (
ModexSI : in std_logic;
BusxZO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Pull
port (
ModexSI : in std_logic;
WirexZO : out std_logic);
end component;
end ComponentsPkg;
| bsd-3-clause |
plessl/zippy | vhdl/tb_arch/tstadpcm_virt/vtest/adpcm_p1.vhd | 1 | 5514 | -- c_0_0 opt232
cfg.gridConf(0)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(0)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(0).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- c_0_1 op13
cfg.gridConf(0)(1).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(0)(1).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(0)(1).routConf.i(1).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_NOREG;
-- c_0_2 op14
cfg.gridConf(0)(2).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(0)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(0)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(1).LocalxE(LOCAL_W) := '1';
-- i.2
cfg.gridConf(0)(2).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(2).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(0)(2).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(2).routConf.o.VBusExE(1) := '1';
-- c_0_3 op6
cfg.gridConf(0)(3).procConf.AluOpxS := alu_and;
-- i.0
cfg.gridConf(0)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(3).routConf.i(0).HBusNxE(1) := '1';
-- i.1
cfg.gridConf(0)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(3).procConf.ConstOpxD := i2cfgconst(7);
-- o.0
cfg.gridConf(0)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(3).routConf.o.HBusNxE(0) := '1';
-- c_1_0 opt230
cfg.gridConf(1)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(1)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(0).routConf.i(0).LocalxE(LOCAL_SE) := '1';
-- c_1_1 op8
cfg.gridConf(1)(1).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(1).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(1)(1).procConf.OutMuxS := O_NOREG;
cfg.gridConf(1)(1).routConf.o.HBusNxE(0) := '1';
-- c_1_2 op15
cfg.gridConf(1)(2).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(1).LocalxE(LOCAL_S) := '1';
-- o.0
cfg.gridConf(1)(2).procConf.OutMuxS := O_NOREG;
-- c_1_3 op9
cfg.gridConf(1)(3).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(3).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(1)(3).procConf.OutMuxS := O_NOREG;
-- c_2_0 opt231
cfg.gridConf(2)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(2)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(0).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- c_2_1 op17
cfg.gridConf(2)(1).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(0).HBusSxE(0) := '1';
-- i.1
cfg.gridConf(2)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(1).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(2)(1).procConf.OutMuxS := O_NOREG;
-- c_2_2 op11
cfg.gridConf(2)(2).procConf.AluOpxS := alu_srl;
-- i.0
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(2)(2).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- i.1
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(2).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(2)(2).procConf.OutMuxS := O_NOREG;
-- c_2_3 op16
cfg.gridConf(2)(3).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(0).VBusExE(1) := '1';
-- i.1
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(1).LocalxE(LOCAL_NW) := '1';
-- i.2
cfg.gridConf(2)(3).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(2).HBusNxE(0) := '1';
-- o.0
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(2)(3).routConf.o.HBusSxE(0) := '1';
-- c_3_0 op10
cfg.gridConf(3)(0).procConf.AluOpxS := alu_srl;
-- i.0
cfg.gridConf(3)(0).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(3)(0).routConf.i(0).LocalxE(LOCAL_E) := '1';
-- i.1
cfg.gridConf(3)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(0).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(3)(0).procConf.OutMuxS := O_NOREG;
-- c_3_1 opt120
cfg.gridConf(3)(1).procConf.AluOpxS := alu_pass0;
-- o.0
cfg.gridConf(3)(1).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(3)(1).procConf.OutCtxRegSelxS := i2ctx(0);
cfg.gridConf(3)(1).routConf.o.HBusSxE(1) := '1';
-- c_3_2 op7
cfg.gridConf(3)(2).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(3)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(0).LocalxE(LOCAL_SE) := '1';
-- i.1
cfg.gridConf(3)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(2).procConf.ConstOpxD := i2cfgconst(4);
-- o.0
cfg.gridConf(3)(2).procConf.OutMuxS := O_NOREG;
-- c_3_3 op12
cfg.gridConf(3)(3).procConf.AluOpxS := alu_srl;
-- i.0
cfg.gridConf(3)(3).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(3)(3).routConf.i(0).HBusSxE(1) := '1';
-- i.1
cfg.gridConf(3)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(3).procConf.ConstOpxD := i2cfgconst(3);
-- o.0
cfg.gridConf(3)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(3)(3).routConf.o.HBusNxE(0) := '1';
-- input drivers
cfg.inputDriverConf(0)(0)(1) := '1';
-- output drivers
| bsd-3-clause |
plessl/zippy | vhdl/configmem.vhd | 1 | 3386 | ------------------------------------------------------------------------------
-- ZIPPY configuration memory (consisting of slices of equal width)
--
-- Project :
-- File : configmem.vhd
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/09
-- Last changed: $LastChangedDate: 2004-10-07 11:06:32 +0200 (Thu, 07 Oct 2004) $
------------------------------------------------------------------------------
-- Configuration memory for one single context
--
-- The configuration memory is written in some sort of DMA mode, i.e.
-- the configuration data is divided into slices of equal width which
-- are transfered one after the other. The start address can be
-- configured by setting the slice pointer. After a slice has been
-- written, the slice pointer is incremented automatically. This feature
-- can be used for efficient partial reconfiguration.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-06 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ZArchPkg.all;
entity ConfigMem is
generic (
CFGWIDTH : integer;
PTRWIDTH : integer;
SLCWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
CfgSlicexDI : in std_logic_vector(SLCWIDTH-1 downto 0);
LoadSlicePtrxEI : in std_logic;
SlicePtrxDI : in std_logic_vector(PTRWIDTH-1 downto 0);
ConfigWordxDO : out std_logic_vector(CFGWIDTH-1 downto 0));
end ConfigMem;
architecture simple of ConfigMem is
constant NSLICES : integer := (CFGWIDTH-1)/SLCWIDTH+1;
constant MEMWIDTH : integer := NSLICES*SLCWIDTH;
signal CfgWordxD : std_logic_vector(MEMWIDTH-1 downto 0);
signal SlcPtrxD : unsigned(PTRWIDTH-1 downto 0);
signal HiPtr, LoPtr : integer;
signal LastxS : std_logic;
begin -- simple
LoPtr <= (to_integer(SlcPtrxD))*SLCWIDTH;
HiPtr <= LoPtr+SLCWIDTH-1;
ConfigReg : process (ClkxC, RstxRB)
begin -- process ConfigReg
if RstxRB = '0' then -- asynchronous reset (active low)
CfgWordxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if WExEI = '1' then
CfgWordxD(HiPtr downto LoPtr) <= CfgSlicexDI;
end if;
end if;
end process ConfigReg;
PtrCnt : process (ClkxC, RstxRB)
begin -- process PtrCnt
if RstxRB = '0' then -- asynchronous reset (active low)
SlcPtrxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if LoadSlicePtrxEI = '1' then
SlcPtrxD <= unsigned(SlicePtrxDI);
elsif WExEI = '1' then
if LastxS = '1' then
SlcPtrxD <= (others => '0');
else
SlcPtrxD <= SlcPtrxD+1;
end if;
end if;
end if;
end process PtrCnt;
DetectLast : process (SlcPtrxD)
begin -- process DetectLast
if SlcPtrxD < NSLICES-1 then
LastxS <= '0';
else
LastxS <= '1';
end if;
end process DetectLast;
ConfigWordxDO <= CfgWordxD(CFGWIDTH-1 downto 0);
end simple;
| bsd-3-clause |
plessl/zippy | vhdl/archConfigPkg.vhd | 1 | 2270 | ------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
-- These are the default architecture parameters. A configuration is
-- expected to provide its own configuration for these parameters. As VHDL
-- does not support overriding of constants (or something similar) each
-- testbench in tb_arch provides its own modified copy of this file, and
-- the architecture is compiled from scratch within the tb_arch/xx
-- directory.
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
| bsd-3-clause |
plessl/zippy | vhdl/testbenches/tb_schedulestore.vhd | 1 | 7415 | ------------------------------------------------------------------------------
-- Testbench for schedulestore.vhd
--
-- Project :
-- File : tb_schedulestore.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-16
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_ScheduleStore is
end tb_ScheduleStore;
architecture arch of tb_ScheduleStore is
constant WRDWIDTH : integer := 32;
constant CONWIDTH : integer := 8;
constant CYCWIDTH : integer := 8;
constant ADRWIDTH : integer := 6;
constant FILLWIDTH : integer := WRDWIDTH-(CONWIDTH+CYCWIDTH+ADRWIDTH+1);
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, progSchedule, loadSPC, resetSPC);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal SPCclrxEI : std_logic;
signal SPCloadxEI : std_logic;
signal WExEI : std_logic;
signal IAddrxDI : std_logic_vector(ADRWIDTH-1 downto 0);
signal IWordxDI : std_logic_vector(WRDWIDTH-1 downto 0);
signal ContextxDO : std_logic_vector(CONWIDTH-1 downto 0);
signal CyclesxDO : std_logic_vector(CYCWIDTH-1 downto 0);
signal LastxSO : std_logic;
-- testbench signals
signal IContextxD : std_logic_vector(CONWIDTH-1 downto 0);
signal ICyclesxD : std_logic_vector(CYCWIDTH-1 downto 0);
signal INextAdrxD : std_logic_vector(ADRWIDTH-1 downto 0);
signal ILastxD : std_logic;
signal IFillxD : std_logic_vector(FILLWIDTH-1 downto 0) := (others => '0');
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ScheduleStore
generic map (
WRDWIDTH => WRDWIDTH,
CONWIDTH => CONWIDTH,
CYCWIDTH => CYCWIDTH,
ADRWIDTH => ADRWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExEI,
IAddrxDI => IAddrxDI,
IWordxDI => IWordxDI,
SPCclrxEI => SPCclrxEI,
SPCloadxEI => SPCloadxEI,
ContextxDO => ContextxDO,
CyclesxDO => CyclesxDO,
LastxSO => LastxSO);
----------------------------------------------------------------------------
-- instruction word encoding
----------------------------------------------------------------------------
IWordxDI <= IFillxD & IContextxD & ICyclesxD & INextAdrxD & ILastxD;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal WExEI : out std_logic;
signal IAddrxDI : out std_logic_vector(ADRWIDTH-1 downto 0);
signal IContextxD : out std_logic_vector(CONWIDTH-1 downto 0);
signal ICyclesxD : out std_logic_vector(CYCWIDTH-1 downto 0);
signal INextAdrxD : out std_logic_vector(ADRWIDTH-1 downto 0);
signal ILastxD : out std_logic;
signal SPCclrxEI : out std_logic;
signal SPCloadxEI : out std_logic) is
begin
WExEI <= '0';
IAddrxDI <= (others => '0');
IContextxD <= (others => '0');
ICyclesxD <= (others => '0');
INextAdrxD <= (others => '0');
ILastxD <= '0';
SPCclrxEI <= '0';
SPCloadxEI <= '0';
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait for CLK_PERIOD;
--
-- program schedule into schedule store
--
tbStatus <= progSchedule;
IAddrxDI <= std_logic_vector(to_unsigned(0, ADRWIDTH));
IContextxD <= std_logic_vector(to_unsigned(10, CONWIDTH));
ICyclesxD <= std_logic_vector(to_unsigned(100, CYCWIDTH));
INextAdrxD <= std_logic_vector(to_unsigned(1, ADRWIDTH));
ILastxD <= '0';
WExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= progSchedule;
IAddrxDI <= std_logic_vector(to_unsigned(1, ADRWIDTH));
IContextxD <= std_logic_vector(to_unsigned(11, CONWIDTH));
ICyclesxD <= std_logic_vector(to_unsigned(101, CYCWIDTH));
INextAdrxD <= std_logic_vector(to_unsigned(2, ADRWIDTH));
ILastxD <= '0';
WExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= progSchedule;
IAddrxDI <= std_logic_vector(to_unsigned(2, ADRWIDTH));
IContextxD <= std_logic_vector(to_unsigned(12, CONWIDTH));
ICyclesxD <= std_logic_vector(to_unsigned(102, CYCWIDTH));
INextAdrxD <= std_logic_vector(to_unsigned(3, ADRWIDTH));
ILastxD <= '0';
WExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= progSchedule;
IAddrxDI <= std_logic_vector(to_unsigned(3, ADRWIDTH));
IContextxD <= std_logic_vector(to_unsigned(13, CONWIDTH));
ICyclesxD <= std_logic_vector(to_unsigned(103, CYCWIDTH));
INextAdrxD <= std_logic_vector(to_unsigned(4, ADRWIDTH));
ILastxD <= '0';
WExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait for CLK_PERIOD;
wait for CLK_PERIOD;
--
-- load schedule PC n times
--
for i in 0 to 3 loop
tbStatus <= loadSPC;
SPCloadxEI <= '1';
wait for CLK_PERIOD;
end loop; -- i
--
-- reset schedule PC (points to store address 0)
--
tbStatus <= idle;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait for CLK_PERIOD;
tbStatus <= resetSPC;
SPCclrxEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause |
plessl/zippy | vhdl/testbenches/tb_row.vhd | 1 | 5096 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
entity tb_Row is
end tb_Row;
architecture arch of tb_Row is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, cell0_sll, cell1_sll, cell2_sll,
cell3_sll);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrxAB : std_logic := '1';
signal CExE : std_logic := '1';
signal Cfg : rowConfigArray;
signal ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0) := (others => '0');
signal Input : rowInputArray;
signal Output : rowOutputArray;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Row
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxABI => ClrxAB,
CExEI => CExE,
ConfigxI => Cfg,
ContextxSI => ContextxS,
InpxI => Input,
OutxO => Output);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
-- cell0: shift (SSL) by constant operator (=3)
tbStatus <= cell0_sll;
Cfg(0).procConf.AluOpxS <= alu_sll;
Cfg(0).procConf.Op1MuxS <= "10";
Cfg(0).procConf.ConstOpxD <= std_logic_vector(to_unsigned(3, DATAWIDTH));
Cfg(0).routConf.Tri0OExE <= '1';
Cfg(0).routConf.Tri1OExE <= '1';
Cfg(0).routConf.Tri2OExE <= '1';
Input(0).In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait for CLK_PERIOD;
-- cell1: shift (SSL) by constant operator (=4)
tbStatus <= cell1_sll;
Cfg(1).procConf.AluOpxS <= alu_sll;
Cfg(1).procConf.Op1MuxS <= "10";
Cfg(1).procConf.ConstOpxD <= std_logic_vector(to_unsigned(4, DATAWIDTH));
Cfg(1).routConf.Tri0OExE <= '1';
Cfg(1).routConf.Tri1OExE <= '1';
Cfg(1).routConf.Tri2OExE <= '1';
Input(1).In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait for CLK_PERIOD;
-- cell2: shift (SSL) by constant operator (=5)
tbStatus <= cell2_sll;
Cfg(2).procConf.AluOpxS <= alu_sll;
Cfg(2).procConf.Op1MuxS <= "10";
Cfg(2).procConf.ConstOpxD <= std_logic_vector(to_unsigned(5, DATAWIDTH));
Cfg(2).routConf.Tri0OExE <= '1';
Cfg(2).routConf.Tri1OExE <= '1';
Cfg(2).routConf.Tri2OExE <= '1';
Input(2).In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait for CLK_PERIOD;
-- cell3: shift (SSL) by constant operator (=6)
tbStatus <= cell3_sll;
Cfg(3).procConf.AluOpxS <= alu_sll;
Cfg(3).procConf.Op1MuxS <= "10";
Cfg(3).procConf.ConstOpxD <= std_logic_vector(to_unsigned(6, DATAWIDTH));
Cfg(3).routConf.Tri0OExE <= '1';
Cfg(3).routConf.Tri1OExE <= '1';
Cfg(3).routConf.Tri2OExE <= '1';
Input(3).In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause |
plessl/zippy | vhdl/cycledncntr.vhd | 1 | 2170 | ------------------------------------------------------------------------------
-- Cycles Down Counter
--
-- Project :
-- File : cycledncntr.vhd
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2004-10-07 11:06:32 +0200 (Thu, 07 Oct 2004) $
------------------------------------------------------------------------------
-- Loadable cycle counter that controls the execution of the
-- array. The counter value is decreased until it reaches zero. It
-- cannot be loaded while counting down.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-05 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CycleDnCntr is
generic (
CNTWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CinxDI : in std_logic_vector(CNTWIDTH-1 downto 0);
OnxSO : out std_logic;
CoutxDO : out std_logic_vector(CNTWIDTH-1 downto 0));
end CycleDnCntr;
architecture simple of CycleDnCntr is
signal CountxD : unsigned(CNTWIDTH-1 downto 0);
signal NotZeroxS : std_logic;
begin -- simple
Comparator : process (CountxD)
begin -- process Comparator
if CountxD > 0 then
NotZeroxS <= '1';
else
NotZeroxS <= '0';
end if;
end process Comparator;
Counter : process (ClkxC, RstxRB)
begin -- process Counter
if RstxRB = '0' then -- asynchronous reset (active low)
CountxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if NotZeroxS = '1' then
CountxD <= CountxD - 1;
elsif LoadxEI = '1' then -- only loadable if count > 0
CountxD <= unsigned(CinxDI);
end if;
end if;
end process Counter;
CoutxDO <= std_logic_vector(CountxD);
OnxSO <= NotZeroxS;
end simple;
| bsd-3-clause |
plessl/zippy | vhdl/tb_arch/tstfir4/tstfir4_archConfigPkg.vhd | 9 | 1871 | ------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
| bsd-3-clause |
stuarthodgson/cocotb | examples/functionality/hdl/sample_module.vhdl | 3 | 2758 | -------------------------------------------------------------------------------
-- Copyright (c) 2014 Potential Ventures Ltd
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of Potential Ventures Ltd,
-- Copyright (c) 2013 SolarFlare Communications Inc nor the
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sample_module is
port (
clk : in std_ulogic;
stream_in_data : in std_ulogic_vector(7 downto 0);
stream_in_data_wide : in std_ulogic_vector(63 downto 0);
stream_in_valid : in std_ulogic;
stream_in_ready : out std_ulogic;
stream_out_data_comb : out std_ulogic_vector(7 downto 0);
stream_out_data_registered : out std_ulogic_vector(7 downto 0);
stream_out_ready : in std_ulogic
);
end;
architecture impl of sample_module is
begin
process (clk) begin
if rising_edge(clk) then
stream_out_data_registered <= stream_in_data;
end if;
end process;
stream_out_data_comb <= stream_in_data;
stream_in_ready <= stream_out_ready;
end architecture; | bsd-3-clause |
pkerling/ethernet_mac | ethernet_types.vhd | 1 | 1184 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
library ieee;
use ieee.std_logic_1164.all;
package ethernet_types is
-- One Ethernet interface byte
subtype t_ethernet_data is std_ulogic_vector(7 downto 0);
-- Ethernet speed, values defined below
subtype t_ethernet_speed is std_ulogic_vector(1 downto 0);
-- Ethernet MAC layer address
constant MAC_ADDRESS_BYTES : positive := 6;
subtype t_mac_address is std_ulogic_vector((MAC_ADDRESS_BYTES * 8 - 1) downto 0);
-- Use utility.reverse_bytes to convert from the canoncial form to the internal representation
-- Example: signal m : t_mac_address := reverse_bytes(x"04AA19BCDE10");
-- m then represents the canoncial address 04-AA-19-BC-DE-10
-- Broadcast address
constant BROADCAST_MAC_ADDRESS : t_mac_address := x"FFFFFFFFFFFF";
-- Speed constants
constant SPEED_1000MBPS : t_ethernet_speed := "10";
constant SPEED_100MBPS : t_ethernet_speed := "01";
constant SPEED_10MBPS : t_ethernet_speed := "00";
constant SPEED_UNSPECIFIED : t_ethernet_speed := "11";
end package; | bsd-3-clause |
32bitmicro/Malinki | fabric/rio/rtl/vhdl/RioPacketBuffer.vhd | 2 | 33275 | -------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Containing RapidIO packet buffering functionallity. Two different entities
-- are implemented, one with transmission window support and one without.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, magro732@opencores.org
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RioPacketBuffer
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for RioPacketBuffer.
--
-- Generic variables
-- -----------------
-- SIZE_ADDRESS_WIDTH - The number of frames in powers of two.
-- CONTENT_ADDRESS_WIDTH - The total number of entries in the memory that can
-- be used to store packet data.
-- CONTENT_WIDTH - The width of the data to store as packet content in the memory.
-- MAX_PACKET_SIZE - The number of entries that must be available for a new
-- complete full sized packet to be received. This option is present to ensure
-- that it is always possible to move a packet to the storage without being
-- surprised that the storage is suddenly empty.
-------------------------------------------------------------------------------
entity RioPacketBuffer is
generic(
SIZE_ADDRESS_WIDTH : natural := 6;
CONTENT_ADDRESS_WIDTH : natural := 8;
CONTENT_WIDTH : natural := 32;
MAX_PACKET_SIZE : natural := 69);
port(
clk : in std_logic;
areset_n : in std_logic;
inboundWriteFrameFull_o : out std_logic;
inboundWriteFrame_i : in std_logic;
inboundWriteFrameAbort_i : in std_logic;
inboundWriteContent_i : in std_logic;
inboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
inboundReadFrameEmpty_o : out std_logic;
inboundReadFrame_i : in std_logic;
inboundReadFrameRestart_i : in std_logic;
inboundReadFrameAborted_o : out std_logic;
inboundReadFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
inboundReadContentEmpty_o : out std_logic;
inboundReadContent_i : in std_logic;
inboundReadContentEnd_o : out std_logic;
inboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0);
outboundWriteFrameFull_o : out std_logic;
outboundWriteFrame_i : in std_logic;
outboundWriteFrameAbort_i : in std_logic;
outboundWriteContent_i : in std_logic;
outboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
outboundReadFrameEmpty_o : out std_logic;
outboundReadFrame_i : in std_logic;
outboundReadFrameRestart_i : in std_logic;
outboundReadFrameAborted_o : out std_logic;
outboundReadFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
outboundReadContentEmpty_o : out std_logic;
outboundReadContent_i : in std_logic;
outboundReadContentEnd_o : out std_logic;
outboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioPacketBuffer.
-------------------------------------------------------------------------------
architecture RioPacketBufferImpl of RioPacketBuffer is
component PacketBufferContinous is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end component;
begin
-----------------------------------------------------------------------------
-- Outbound frame buffers.
-----------------------------------------------------------------------------
OutboundPacketBuffer: PacketBufferContinous
generic map(
SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
CONTENT_WIDTH=>CONTENT_WIDTH,
MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
port map(
clk=>clk,
areset_n=>areset_n,
writeFrameFull_o=>outboundWriteFrameFull_o,
writeFrame_i=>outboundWriteFrame_i, writeFrameAbort_i=>outboundWriteFrameAbort_i,
writeContent_i=>outboundWriteContent_i, writeContentData_i=>outboundWriteContentData_i,
readFrameEmpty_o=>outboundReadFrameEmpty_o,
readFrame_i=>outboundReadFrame_i, readFrameRestart_i=>outboundReadFrameRestart_i,
readFrameAborted_o=>outboundReadFrameAborted_o,
readFrameSize_o=>outboundReadFrameSize_o,
readContentEmpty_o=>outboundReadContentEmpty_o,
readContent_i=>outboundReadContent_i, readContentEnd_o=>outboundReadContentEnd_o,
readContentData_o=>outboundReadContentData_o);
-----------------------------------------------------------------------------
-- Inbound frame buffers.
-----------------------------------------------------------------------------
InboundPacketBuffer: PacketBufferContinous
generic map(
SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
CONTENT_WIDTH=>CONTENT_WIDTH,
MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
port map(
clk=>clk,
areset_n=>areset_n,
writeFrameFull_o=>inboundWriteFrameFull_o,
writeFrame_i=>inboundWriteFrame_i, writeFrameAbort_i=>inboundWriteFrameAbort_i,
writeContent_i=>inboundWriteContent_i, writeContentData_i=>inboundWriteContentData_i,
readFrameEmpty_o=>inboundReadFrameEmpty_o,
readFrame_i=>inboundReadFrame_i, readFrameRestart_i=>inboundReadFrameRestart_i,
readFrameAborted_o=>inboundReadFrameAborted_o,
readFrameSize_o=>inboundReadFrameSize_o,
readContentEmpty_o=>inboundReadContentEmpty_o,
readContent_i=>inboundReadContent_i, readContentEnd_o=>inboundReadContentEnd_o,
readContentData_o=>inboundReadContentData_o);
end architecture;
-------------------------------------------------------------------------------
-- RioPacketBufferWindow
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for RioPacketBufferWindow.
-------------------------------------------------------------------------------
entity RioPacketBufferWindow is
generic(
SIZE_ADDRESS_WIDTH : natural := 6;
CONTENT_ADDRESS_WIDTH : natural := 8;
CONTENT_WIDTH : natural := 32;
MAX_PACKET_SIZE : natural := 69);
port(
clk : in std_logic;
areset_n : in std_logic;
inboundWriteFrameFull_o : out std_logic;
inboundWriteFrame_i : in std_logic;
inboundWriteFrameAbort_i : in std_logic;
inboundWriteContent_i : in std_logic;
inboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
inboundReadFrameEmpty_o : out std_logic;
inboundReadFrame_i : in std_logic;
inboundReadFrameRestart_i : in std_logic;
inboundReadFrameAborted_o : out std_logic;
inboundReadContentEmpty_o : out std_logic;
inboundReadContent_i : in std_logic;
inboundReadContentEnd_o : out std_logic;
inboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0);
outboundWriteFrameFull_o : out std_logic;
outboundWriteFrame_i : in std_logic;
outboundWriteFrameAbort_i : in std_logic;
outboundWriteContent_i : in std_logic;
outboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
outboundReadFrameEmpty_o : out std_logic;
outboundReadFrame_i : in std_logic;
outboundReadFrameRestart_i : in std_logic;
outboundReadFrameAborted_o : out std_logic;
outboundReadWindowEmpty_o : out std_logic;
outboundReadWindowReset_i : in std_logic;
outboundReadWindowNext_i : in std_logic;
outboundReadContentEmpty_o : out std_logic;
outboundReadContent_i : in std_logic;
outboundReadContentEnd_o : out std_logic;
outboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioPacketBufferWindow.
-------------------------------------------------------------------------------
architecture RioPacketBufferWindowImpl of RioPacketBufferWindow is
component PacketBufferContinous is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end component;
component PacketBufferContinousWindow is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readWindowEmpty_o : out std_logic;
readWindowReset_i : in std_logic;
readWindowNext_i : in std_logic;
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end component;
begin
-----------------------------------------------------------------------------
-- Outbound frame buffers.
-----------------------------------------------------------------------------
OutboundPacketBuffer: PacketBufferContinousWindow
generic map(
SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
CONTENT_WIDTH=>CONTENT_WIDTH,
MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
port map(
clk=>clk,
areset_n=>areset_n,
writeFrameFull_o=>outboundWriteFrameFull_o,
writeFrame_i=>outboundWriteFrame_i, writeFrameAbort_i=>outboundWriteFrameAbort_i,
writeContent_i=>outboundWriteContent_i, writeContentData_i=>outboundWriteContentData_i,
readFrameEmpty_o=>outboundReadFrameEmpty_o,
readFrame_i=>outboundReadFrame_i, readFrameRestart_i=>outboundReadFrameRestart_i,
readFrameAborted_o=>outboundReadFrameAborted_o,
readWindowEmpty_o=>outboundReadWindowEmpty_o,
readWindowReset_i=>outboundReadWindowReset_i,
readWindowNext_i=>outboundReadWindowNext_i,
readContentEmpty_o=>outboundReadContentEmpty_o,
readContent_i=>outboundReadContent_i, readContentEnd_o=>outboundReadContentEnd_o,
readContentData_o=>outboundReadContentData_o);
-----------------------------------------------------------------------------
-- Inbound frame buffers.
-----------------------------------------------------------------------------
InboundPacketBuffer: PacketBufferContinous
generic map(
SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
CONTENT_WIDTH=>CONTENT_WIDTH,
MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
port map(
clk=>clk,
areset_n=>areset_n,
writeFrameFull_o=>inboundWriteFrameFull_o,
writeFrame_i=>inboundWriteFrame_i, writeFrameAbort_i=>inboundWriteFrameAbort_i,
writeContent_i=>inboundWriteContent_i, writeContentData_i=>inboundWriteContentData_i,
readFrameEmpty_o=>inboundReadFrameEmpty_o,
readFrame_i=>inboundReadFrame_i, readFrameRestart_i=>inboundReadFrameRestart_i,
readFrameAborted_o=>inboundReadFrameAborted_o,
readFrameSize_o=>open,
readContentEmpty_o=>inboundReadContentEmpty_o,
readContent_i=>inboundReadContent_i, readContentEnd_o=>inboundReadContentEnd_o,
readContentData_o=>inboundReadContentData_o);
end architecture;
-------------------------------------------------------------------------------
-- PacketBufferContinous
-- This component stores data in chuncks and stores the size of them. The full
-- memory can be used, except for one word, or a specified (using generic)
-- maximum number of frames.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for PacketBufferContinous.
-------------------------------------------------------------------------------
entity PacketBufferContinous is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for PacketBufferContinous.
-------------------------------------------------------------------------------
architecture PacketBufferContinousImpl of PacketBufferContinous is
component MemorySimpleDualPortAsync is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
component MemorySimpleDualPort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
clkB_i : in std_logic;
enableB_i : in std_logic;
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
-- The number of available word positions left in the memory.
signal available : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The position to place new frames.
signal backIndex, backIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The position to remove old frames.
signal frontIndex, frontIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The size of the current frame.
signal readFrameEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The start of unread content.
signal memoryStart_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The current reading position.
signal memoryRead_p, memoryReadNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The end of unread content.
signal memoryEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The current writing position.
signal memoryWrite_p, memoryWriteNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- Memory output signal containing the position of a frame.
signal framePositionReadData : std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
begin
-----------------------------------------------------------------------------
-- Internal signal assignments.
-----------------------------------------------------------------------------
available <= not (memoryEnd_p - memoryStart_p);
backIndexNext <= backIndex + 1;
frontIndexNext <= frontIndex + 1;
memoryWriteNext_p <= memoryWrite_p + 1;
memoryReadNext_p <= memoryRead_p + 1;
-----------------------------------------------------------------------------
-- Writer logic.
-----------------------------------------------------------------------------
writeFrameFull_o <= '1' when ((backIndexNext = frontIndex) or
(available < MAX_PACKET_SIZE)) else '0';
Writer: process(clk, areset_n)
begin
if (areset_n = '0') then
backIndex <= (others=>'0');
memoryEnd_p <= (others=>'0');
memoryWrite_p <= (others=>'0');
elsif (clk'event and clk = '1') then
if (writeFrameAbort_i = '1') then
memoryWrite_p <= memoryEnd_p;
elsif (writeContent_i = '1') then
memoryWrite_p <= memoryWriteNext_p;
end if;
if(writeFrame_i = '1') then
memoryEnd_p <= memoryWrite_p;
backIndex <= backIndexNext;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Frame cancellation logic.
-----------------------------------------------------------------------------
process(clk, areset_n)
begin
if (areset_n = '0') then
readFrameAborted_o <= '0';
elsif (clk'event and clk = '1') then
if ((frontIndex = backIndex) and
((writeFrameAbort_i = '1') and (readFrameRestart_i = '0'))) then
readFrameAborted_o <= '1';
elsif ((writeFrameAbort_i = '0') and (readFrameRestart_i = '1')) then
readFrameAborted_o <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Reader logic.
-----------------------------------------------------------------------------
readFrameEmpty_o <= '1' when (frontIndex = backIndex) else '0';
readContentEmpty_o <= '1' when ((frontIndex = backIndex) and
(memoryWrite_p = memoryRead_p)) else '0';
readFrameSize_o <= std_logic_vector(readFrameEnd_p - memoryStart_p);
Reader: process(clk, areset_n)
begin
if (areset_n = '0') then
frontIndex <= (others=>'0');
memoryStart_p <= (others=>'0');
memoryRead_p <= (others=>'0');
readContentEnd_o <= '0';
elsif (clk'event and clk = '1') then
-- REMARK: Break apart into registers to avoid priority ladder???
if(readFrameRestart_i = '1') then
memoryRead_p <= memoryStart_p;
elsif(readContent_i = '1') then
if(memoryRead_p = readFrameEnd_p) then
readContentEnd_o <= '1';
else
readContentEnd_o <= '0';
memoryRead_p <= memoryReadNext_p;
end if;
elsif(readFrame_i = '1') then
memoryStart_p <= readFrameEnd_p;
frontIndex <= frontIndexNext;
memoryRead_p <= readFrameEnd_p;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Frame positioning memory signals.
-----------------------------------------------------------------------------
readFrameEnd_p <= unsigned(framePositionReadData);
-- Memory to keep frame starting/ending positions in.
FramePosition: MemorySimpleDualPortAsync
generic map(ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_ADDRESS_WIDTH)
port map(
clkA_i=>clk, enableA_i=>writeFrame_i,
addressA_i=>std_logic_vector(backIndex), dataA_i=>std_logic_vector(memoryWrite_p),
addressB_i=>std_logic_vector(frontIndex), dataB_o=>framePositionReadData);
-----------------------------------------------------------------------------
-- Frame content memory signals.
-----------------------------------------------------------------------------
-- Memory to keep frame content in.
-- REMARK: Use paritybits here as well to make sure the frame data does not
-- become corrupt???
FrameContent: MemorySimpleDualPort
generic map(ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_WIDTH)
port map(
clkA_i=>clk, enableA_i=>writeContent_i,
addressA_i=>std_logic_vector(memoryWrite_p), dataA_i=>writeContentData_i,
clkB_i=>clk, enableB_i=>readContent_i,
addressB_i=>std_logic_vector(memoryRead_p), dataB_o=>readContentData_o);
end architecture;
-------------------------------------------------------------------------------
-- PacketBufferContinousWindow
-- This component stores data in chuncks and stores the size of them. The full
-- memory can be used, except for one word, or a specified (using generic)
-- maximum number of frames.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for PacketBufferContinousWindow.
-------------------------------------------------------------------------------
entity PacketBufferContinousWindow is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readWindowEmpty_o : out std_logic;
readWindowReset_i : in std_logic;
readWindowNext_i : in std_logic;
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for PacketBufferContinousWindow.
-------------------------------------------------------------------------------
architecture PacketBufferContinousWindowImpl of PacketBufferContinousWindow is
component MemorySimpleDualPortAsync is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
component MemorySimpleDualPort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
clkB_i : in std_logic;
enableB_i : in std_logic;
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
-- The number of available word positions left in the memory.
signal available : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal backIndex, backIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal frontIndex, frontIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal windowIndex, windowIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The size of the current frame.
signal readFrameEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The start of unread content.
signal memoryStart_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The start of unread window content.
signal memoryStartWindow_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The current reading position.
signal memoryRead_p, memoryReadNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The end of unread content.
signal memoryEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The current writing position.
signal memoryWrite_p, memoryWriteNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal framePositionReadAddress : std_logic_vector(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal framePositionReadData : std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
begin
-----------------------------------------------------------------------------
-- Internal signal assignments.
-----------------------------------------------------------------------------
available <= not (memoryEnd_p - memoryStart_p);
backIndexNext <= backIndex + 1;
frontIndexNext <= frontIndex + 1;
windowIndexNext <= windowIndex + 1;
memoryWriteNext_p <= memoryWrite_p + 1;
memoryReadNext_p <= memoryRead_p + 1;
-----------------------------------------------------------------------------
-- Writer logic.
-----------------------------------------------------------------------------
writeFrameFull_o <= '1' when ((backIndexNext = frontIndex) or
(available < MAX_PACKET_SIZE)) else '0';
Writer: process(clk, areset_n)
begin
if (areset_n = '0') then
backIndex <= (others=>'0');
memoryEnd_p <= (others=>'0');
memoryWrite_p <= (others=>'0');
elsif (clk'event and clk = '1') then
if (writeFrameAbort_i = '1') then
memoryWrite_p <= memoryEnd_p;
elsif (writeContent_i = '1') then
memoryWrite_p <= memoryWriteNext_p;
end if;
if(writeFrame_i = '1') then
memoryEnd_p <= memoryWrite_p;
backIndex <= backIndexNext;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Frame cancellation logic.
-----------------------------------------------------------------------------
process(clk, areset_n)
begin
if (areset_n = '0') then
readFrameAborted_o <= '0';
elsif (clk'event and clk = '1') then
if ((windowIndex = backIndex) and
((writeFrameAbort_i = '1') and (readFrameRestart_i = '0'))) then
readFrameAborted_o <= '1';
elsif ((writeFrameAbort_i = '0') and (readFrameRestart_i = '1')) then
readFrameAborted_o <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Reader logic.
-----------------------------------------------------------------------------
readFrameEmpty_o <= '1' when (frontIndex = backIndex) else '0';
readWindowEmpty_o <= '1' when (windowIndex = backIndex) else '0';
readContentEmpty_o <= '1' when ((windowIndex = backIndex) and
(memoryWrite_p = memoryRead_p)) else '0';
Reader: process(clk, areset_n)
begin
if (areset_n = '0') then
frontIndex <= (others=>'0');
windowIndex <= (others=>'0');
memoryStart_p <= (others=>'0');
memoryStartWindow_p <= (others=>'0');
memoryRead_p <= (others=>'0');
readContentEnd_o <= '0';
elsif (clk'event and clk = '1') then
-- REMARK: Break apart into registers to avoid priority ladder???
if(readFrameRestart_i = '1') then
memoryRead_p <= memoryStartWindow_p;
elsif(readContent_i = '1') then
if(memoryRead_p = readFrameEnd_p) then
readContentEnd_o <= '1';
else
readContentEnd_o <= '0';
memoryRead_p <= memoryReadNext_p;
end if;
elsif(readFrame_i = '1') then
memoryStart_p <= readFrameEnd_p;
frontIndex <= frontIndexNext;
elsif(readWindowReset_i = '1') then
memoryStartWindow_p <= memoryStart_p;
windowIndex <= frontIndex;
memoryRead_p <= memoryStart_p;
elsif(readWindowNext_i = '1') then
memoryStartWindow_p <= readFrameEnd_p;
windowIndex <= windowIndexNext;
memoryRead_p <= readFrameEnd_p;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Frame positioning memory signals.
-----------------------------------------------------------------------------
-- Assign the address from both frontIndex and windowIndex to be able to
-- share the memory between the two different types of accesses. This assumes
-- that the window is not accessed at the same time as the other signal.
framePositionReadAddress <= std_logic_vector(frontIndex) when (readFrame_i = '1') else
std_logic_vector(windowIndex);
readFrameEnd_p <= unsigned(framePositionReadData);
-- Memory to keep frame starting/ending positions in.
FramePosition: MemorySimpleDualPortAsync
generic map(ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_ADDRESS_WIDTH)
port map(
clkA_i=>clk, enableA_i=>writeFrame_i,
addressA_i=>std_logic_vector(backIndex), dataA_i=>std_logic_vector(memoryWrite_p),
addressB_i=>framePositionReadAddress, dataB_o=>framePositionReadData);
-----------------------------------------------------------------------------
-- Frame content memory signals.
-----------------------------------------------------------------------------
-- Memory to keep frame content in.
-- REMARK: Use paritybits here as well to make sure the frame data does not
-- become corrupt???
FrameContent: MemorySimpleDualPort
generic map(ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_WIDTH)
port map(
clkA_i=>clk, enableA_i=>writeContent_i,
addressA_i=>std_logic_vector(memoryWrite_p), dataA_i=>writeContentData_i,
clkB_i=>clk, enableB_i=>readContent_i,
addressB_i=>std_logic_vector(memoryRead_p), dataB_o=>readContentData_o);
end architecture;
| bsd-3-clause |
pkerling/ethernet_mac | xilinx/input_buffer.vhd | 1 | 1844 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Configurable input buffer forced into the IO block
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity input_buffer is
generic(
-- If TRUE, fixed_input_delay is inserted between the pad and the flip-flop
HAS_DELAY : boolean := FALSE;
IDELAY_VALUE : natural range 0 to 255 := 0
);
port(
-- Connect to pad or IBUF
pad_i : in std_ulogic;
-- Connect to user logic
buffer_o : out std_ulogic;
-- Capture clock
clock_i : in std_ulogic
);
end entity;
architecture spartan_6 of input_buffer is
signal delayed : std_ulogic := '0';
-- Force putting input Flip-Flop into IOB so it doesn't end up in a normal logic tile
-- which would ruin the timing.
attribute iob : string;
attribute iob of FDRE_inst : label is "FORCE";
begin
-- When delay activated: Instantiate IODELAY2 and then capture its output
delay_gen : if HAS_DELAY = TRUE generate
fixed_input_delay_inst : entity work.fixed_input_delay
generic map(
IDELAY_VALUE => IDELAY_VALUE
)
port map(
pad_i => pad_i,
delayed_o => delayed
);
end generate;
-- When delay deactivated: Directly capture the signal
no_delay_gen : if HAS_DELAY = FALSE generate
delayed <= pad_i;
end generate;
FDRE_inst : FDRE
generic map(
INIT => '0') -- Initial value of register ('0' or '1')
port map(
Q => buffer_o, -- Data output
C => clock_i, -- Clock input
CE => '1', -- Clock enable input
R => '0', -- Synchronous reset input
D => delayed -- Data input
);
end architecture;
| bsd-3-clause |
32bitmicro/Malinki | fabric/rio/rtl/vhdl/RioCommon.vhd | 2 | 45114 | -------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Contains commonly used types, functions, procedures and entities used in
-- the RapidIO IP library project.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, magro732@opencores.org
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RioCommon library.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- RioCommon package description.
-------------------------------------------------------------------------------
package rio_common is
-----------------------------------------------------------------------------
-- Commonly used types.
-----------------------------------------------------------------------------
type Array1 is array (natural range <>) of
std_logic;
type Array2 is array (natural range <>) of
std_logic_vector(1 downto 0);
type Array3 is array (natural range <>) of
std_logic_vector(2 downto 0);
type Array4 is array (natural range <>) of
std_logic_vector(3 downto 0);
type Array5 is array (natural range <>) of
std_logic_vector(4 downto 0);
type Array8 is array (natural range <>) of
std_logic_vector(7 downto 0);
type Array9 is array (natural range <>) of
std_logic_vector(8 downto 0);
type Array10 is array (natural range <>) of
std_logic_vector(9 downto 0);
type Array16 is array (natural range <>) of
std_logic_vector(15 downto 0);
type Array32 is array (natural range <>) of
std_logic_vector(31 downto 0);
type Array34 is array (natural range <>) of
std_logic_vector(33 downto 0);
-----------------------------------------------------------------------------
-- Commonly used constants.
-----------------------------------------------------------------------------
-- Symbol types between the serial and the PCS layer.
constant SYMBOL_IDLE : std_logic_vector(1 downto 0) := "00";
constant SYMBOL_CONTROL : std_logic_vector(1 downto 0) := "01";
constant SYMBOL_ERROR : std_logic_vector(1 downto 0) := "10";
constant SYMBOL_DATA : std_logic_vector(1 downto 0) := "11";
-- STYPE0 constants.
constant STYPE0_PACKET_ACCEPTED : std_logic_vector(2 downto 0) := "000";
constant STYPE0_PACKET_RETRY : std_logic_vector(2 downto 0) := "001";
constant STYPE0_PACKET_NOT_ACCEPTED : std_logic_vector(2 downto 0) := "010";
constant STYPE0_RESERVED : std_logic_vector(2 downto 0) := "011";
constant STYPE0_STATUS : std_logic_vector(2 downto 0) := "100";
constant STYPE0_VC_STATUS : std_logic_vector(2 downto 0) := "101";
constant STYPE0_LINK_RESPONSE : std_logic_vector(2 downto 0) := "110";
constant STYPE0_IMPLEMENTATION_DEFINED : std_logic_vector(2 downto 0) := "111";
-- STYPE1 constants.
constant STYPE1_START_OF_PACKET : std_logic_vector(2 downto 0) := "000";
constant STYPE1_STOMP : std_logic_vector(2 downto 0) := "001";
constant STYPE1_END_OF_PACKET : std_logic_vector(2 downto 0) := "010";
constant STYPE1_RESTART_FROM_RETRY : std_logic_vector(2 downto 0) := "011";
constant STYPE1_LINK_REQUEST : std_logic_vector(2 downto 0) := "100";
constant STYPE1_MULTICAST_EVENT : std_logic_vector(2 downto 0) := "101";
constant STYPE1_RESERVED : std_logic_vector(2 downto 0) := "110";
constant STYPE1_NOP : std_logic_vector(2 downto 0) := "111";
-- FTYPE constants.
constant FTYPE_REQUEST_CLASS : std_logic_vector(3 downto 0) := "0010";
constant FTYPE_WRITE_CLASS : std_logic_vector(3 downto 0) := "0101";
constant FTYPE_STREAMING_WRITE_CLASS : std_logic_vector(3 downto 0) := "0110";
constant FTYPE_MAINTENANCE_CLASS : std_logic_vector(3 downto 0) := "1000";
constant FTYPE_RESPONSE_CLASS : std_logic_vector(3 downto 0) := "1101";
constant FTYPE_DOORBELL_CLASS : std_logic_vector(3 downto 0) := "1010";
constant FTYPE_MESSAGE_CLASS : std_logic_vector(3 downto 0) := "0010";
-- TTYPE Constants
constant TTYPE_MAINTENANCE_READ_REQUEST : std_logic_vector(3 downto 0) := "0000";
constant TTYPE_MAINTENANCE_WRITE_REQUEST : std_logic_vector(3 downto 0) := "0001";
constant TTYPE_MAINTENANCE_READ_RESPONSE : std_logic_vector(3 downto 0) := "0010";
constant TTYPE_MAINTENANCE_WRITE_RESPONSE : std_logic_vector(3 downto 0) := "0011";
constant TTYPE_NREAD_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
constant TTYPE_NWRITE_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
constant LINK_REQUEST_CMD_RESET_DEVICE : std_logic_vector(2 downto 0) := "011";
constant LINK_REQUEST_CMD_INPUT_STATUS : std_logic_vector(2 downto 0) := "100";
constant PACKET_NOT_ACCEPTED_CAUSE_UNEXPECTED_ACKID : std_logic_vector(4 downto 0) := "00001";
constant PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC : std_logic_vector(4 downto 0) := "00010";
constant PACKET_NOT_ACCEPTED_CAUSE_NON_MAINTENANCE_STOPPED : std_logic_vector(4 downto 0) := "00011";
constant PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC : std_logic_vector(4 downto 0) := "00100";
constant PACKET_NOT_ACCEPTED_CAUSE_INVALID_CHARACTER : std_logic_vector(4 downto 0) := "00101";
constant PACKET_NOT_ACCEPTED_CAUSE_NO_RESOURCES : std_logic_vector(4 downto 0) := "00110";
constant PACKET_NOT_ACCEPTED_CAUSE_LOSS_DESCRAMBLER : std_logic_vector(4 downto 0) := "00111";
constant PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR : std_logic_vector(4 downto 0) := "11111";
-----------------------------------------------------------------------------
-- Types used in simulations.
-----------------------------------------------------------------------------
type ByteArray is array (natural range <>) of
std_logic_vector(7 downto 0);
type HalfwordArray is array (natural range <>) of
std_logic_vector(15 downto 0);
type WordArray is array (natural range <>) of
std_logic_vector(31 downto 0);
type DoublewordArray is array (natural range <>) of
std_logic_vector(63 downto 0);
-- Type defining a RapidIO frame.
type RioFrame is record
length : natural range 0 to 69;
payload : WordArray(0 to 68);
end record;
type RioFrameArray is array (natural range <>) of RioFrame;
-- Type defining a RapidIO payload.
type RioPayload is record
length : natural range 0 to 133;
data : HalfwordArray(0 to 132);
end record;
-----------------------------------------------------------------------------
-- Crc5 calculation function.
-- ITU, polynom=0x15.
-----------------------------------------------------------------------------
function Crc5(constant data : in std_logic_vector(18 downto 0);
constant crc : in std_logic_vector(4 downto 0))
return std_logic_vector;
---------------------------------------------------------------------------
-- Create a RapidIO physical layer control symbol.
---------------------------------------------------------------------------
function RioControlSymbolCreate(
constant stype0 : in std_logic_vector(2 downto 0);
constant parameter0 : in std_logic_vector(4 downto 0);
constant parameter1 : in std_logic_vector(4 downto 0);
constant stype1 : in std_logic_vector(2 downto 0);
constant cmd : in std_logic_vector(2 downto 0))
return std_logic_vector;
-----------------------------------------------------------------------------
-- Crc16 calculation function.
-- CITT, polynom=0x1021.
-----------------------------------------------------------------------------
function Crc16(constant data : in std_logic_vector(15 downto 0);
constant crc : in std_logic_vector(15 downto 0))
return std_logic_vector;
---------------------------------------------------------------------------
-- Create a randomly initialized data array.
---------------------------------------------------------------------------
procedure CreateRandomPayload(
variable payload : out HalfwordArray(0 to 132);
variable seed1 : inout positive;
variable seed2 : inout positive);
procedure CreateRandomPayload(
variable payload : out DoublewordArray(0 to 31);
variable seed1 : inout positive;
variable seed2 : inout positive);
---------------------------------------------------------------------------
-- Create a generic RapidIO frame.
---------------------------------------------------------------------------
function RioFrameCreate(
constant ackId : in std_logic_vector(4 downto 0);
constant vc : in std_logic;
constant crf : in std_logic;
constant prio : in std_logic_vector(1 downto 0);
constant tt : in std_logic_vector(1 downto 0);
constant ftype : in std_logic_vector(3 downto 0);
constant sourceId : in std_logic_vector(15 downto 0);
constant destId : in std_logic_vector(15 downto 0);
constant payload : in RioPayload)
return RioFrame;
---------------------------------------------------------------------------
-- Create a NWRITE RapidIO frame.
---------------------------------------------------------------------------
function RioNwrite(
constant wrsize : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant address : in std_logic_vector(28 downto 0);
constant wdptr : in std_logic;
constant xamsbs : in std_logic_vector(1 downto 0);
constant dataLength : in natural range 1 to 32;
constant data : in DoublewordArray(0 to 31))
return RioPayload;
---------------------------------------------------------------------------
-- Create a NREAD RapidIO frame.
---------------------------------------------------------------------------
function RioNread(
constant rdsize : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant address : in std_logic_vector(28 downto 0);
constant wdptr : in std_logic;
constant xamsbs : in std_logic_vector(1 downto 0))
return RioPayload;
---------------------------------------------------------------------------
-- Create a RESPONSE RapidIO frame.
---------------------------------------------------------------------------
function RioResponse(
constant status : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant dataLength : in natural range 0 to 32;
constant data : in DoublewordArray(0 to 31))
return RioPayload;
---------------------------------------------------------------------------
-- Create a Maintenance RapidIO frame.
---------------------------------------------------------------------------
function RioMaintenance(
constant transaction : in std_logic_vector(3 downto 0);
constant size : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant hopCount : in std_logic_vector(7 downto 0);
constant configOffset : in std_logic_vector(20 downto 0);
constant wdptr : in std_logic;
constant dataLength : in natural range 0 to 8;
constant data : in DoublewordArray(0 to 7))
return RioPayload;
-----------------------------------------------------------------------------
-- Function to convert a std_logic_vector to a string.
-----------------------------------------------------------------------------
function byteToString(constant byte : std_logic_vector(7 downto 0))
return string;
---------------------------------------------------------------------------
-- Procedure to print to report file and output
---------------------------------------------------------------------------
procedure PrintR( constant str : string );
---------------------------------------------------------------------------
-- Procedure to print to spec file
---------------------------------------------------------------------------
procedure PrintS( constant str : string );
---------------------------------------------------------------------------
-- Procedure to Assert Expression
---------------------------------------------------------------------------
procedure AssertE( constant exp: boolean; constant str : string );
---------------------------------------------------------------------------
-- Procedure to Print Error
---------------------------------------------------------------------------
procedure PrintE( constant str : string );
---------------------------------------------------------------------------
-- Procedure to end a test.
---------------------------------------------------------------------------
procedure TestEnd;
end package;
-------------------------------------------------------------------------------
-- RioCommon package body description.
-------------------------------------------------------------------------------
package body rio_common is
-----------------------------------------------------------------------------
-- Crc5 calculation function.
-- ITU, polynom=0x15.
-----------------------------------------------------------------------------
function Crc5(constant data : in std_logic_vector(18 downto 0);
constant crc : in std_logic_vector(4 downto 0))
return std_logic_vector is
type crcTableType is array (0 to 31) of std_logic_vector(7 downto 0);
constant crcTable : crcTableType := (
x"00", x"15", x"1f", x"0a", x"0b", x"1e", x"14", x"01",
x"16", x"03", x"09", x"1c", x"1d", x"08", x"02", x"17",
x"19", x"0c", x"06", x"13", x"12", x"07", x"0d", x"18",
x"0f", x"1a", x"10", x"05", x"04", x"11", x"1b", x"0e" );
variable index : natural range 0 to 31;
variable result : std_logic_vector(4 downto 0);
begin
result := crc;
index := to_integer(unsigned(data(18 downto 14) xor result));
result := crcTable(index)(4 downto 0);
index := to_integer(unsigned(data(13 downto 9) xor result));
result := crcTable(index)(4 downto 0);
index := to_integer(unsigned(data(8 downto 4) xor result));
result := crcTable(index)(4 downto 0);
index := to_integer(unsigned((data(3 downto 0) & '0') xor result));
return crcTable(index)(4 downto 0);
end Crc5;
---------------------------------------------------------------------------
-- Create a RapidIO physical layer control symbol.
---------------------------------------------------------------------------
function RioControlSymbolCreate(
constant stype0 : in std_logic_vector(2 downto 0);
constant parameter0 : in std_logic_vector(4 downto 0);
constant parameter1 : in std_logic_vector(4 downto 0);
constant stype1 : in std_logic_vector(2 downto 0);
constant cmd : in std_logic_vector(2 downto 0))
return std_logic_vector is
variable returnValue : std_logic_vector(31 downto 0);
variable symbolData : std_logic_vector(18 downto 0);
begin
symbolData(18 downto 16) := stype0;
symbolData(15 downto 11) := parameter0;
symbolData(10 downto 6) := parameter1;
symbolData(5 downto 3) := stype1;
symbolData(2 downto 0) := cmd;
returnValue(31 downto 13) := symbolData;
returnValue(12 downto 8) := Crc5(symbolData, "11111");
returnValue(7 downto 0) := x"00";
return returnValue;
end function;
-----------------------------------------------------------------------------
-- Crc16 calculation function.
-- CITT, polynom=0x1021.
-----------------------------------------------------------------------------
function Crc16(constant data : in std_logic_vector(15 downto 0);
constant crc : in std_logic_vector(15 downto 0))
return std_logic_vector is
type crcTableType is array (0 to 255) of std_logic_vector(15 downto 0);
constant crcTable : crcTableType := (
x"0000", x"1021", x"2042", x"3063", x"4084", x"50a5", x"60c6", x"70e7",
x"8108", x"9129", x"a14a", x"b16b", x"c18c", x"d1ad", x"e1ce", x"f1ef",
x"1231", x"0210", x"3273", x"2252", x"52b5", x"4294", x"72f7", x"62d6",
x"9339", x"8318", x"b37b", x"a35a", x"d3bd", x"c39c", x"f3ff", x"e3de",
x"2462", x"3443", x"0420", x"1401", x"64e6", x"74c7", x"44a4", x"5485",
x"a56a", x"b54b", x"8528", x"9509", x"e5ee", x"f5cf", x"c5ac", x"d58d",
x"3653", x"2672", x"1611", x"0630", x"76d7", x"66f6", x"5695", x"46b4",
x"b75b", x"a77a", x"9719", x"8738", x"f7df", x"e7fe", x"d79d", x"c7bc",
x"48c4", x"58e5", x"6886", x"78a7", x"0840", x"1861", x"2802", x"3823",
x"c9cc", x"d9ed", x"e98e", x"f9af", x"8948", x"9969", x"a90a", x"b92b",
x"5af5", x"4ad4", x"7ab7", x"6a96", x"1a71", x"0a50", x"3a33", x"2a12",
x"dbfd", x"cbdc", x"fbbf", x"eb9e", x"9b79", x"8b58", x"bb3b", x"ab1a",
x"6ca6", x"7c87", x"4ce4", x"5cc5", x"2c22", x"3c03", x"0c60", x"1c41",
x"edae", x"fd8f", x"cdec", x"ddcd", x"ad2a", x"bd0b", x"8d68", x"9d49",
x"7e97", x"6eb6", x"5ed5", x"4ef4", x"3e13", x"2e32", x"1e51", x"0e70",
x"ff9f", x"efbe", x"dfdd", x"cffc", x"bf1b", x"af3a", x"9f59", x"8f78",
x"9188", x"81a9", x"b1ca", x"a1eb", x"d10c", x"c12d", x"f14e", x"e16f",
x"1080", x"00a1", x"30c2", x"20e3", x"5004", x"4025", x"7046", x"6067",
x"83b9", x"9398", x"a3fb", x"b3da", x"c33d", x"d31c", x"e37f", x"f35e",
x"02b1", x"1290", x"22f3", x"32d2", x"4235", x"5214", x"6277", x"7256",
x"b5ea", x"a5cb", x"95a8", x"8589", x"f56e", x"e54f", x"d52c", x"c50d",
x"34e2", x"24c3", x"14a0", x"0481", x"7466", x"6447", x"5424", x"4405",
x"a7db", x"b7fa", x"8799", x"97b8", x"e75f", x"f77e", x"c71d", x"d73c",
x"26d3", x"36f2", x"0691", x"16b0", x"6657", x"7676", x"4615", x"5634",
x"d94c", x"c96d", x"f90e", x"e92f", x"99c8", x"89e9", x"b98a", x"a9ab",
x"5844", x"4865", x"7806", x"6827", x"18c0", x"08e1", x"3882", x"28a3",
x"cb7d", x"db5c", x"eb3f", x"fb1e", x"8bf9", x"9bd8", x"abbb", x"bb9a",
x"4a75", x"5a54", x"6a37", x"7a16", x"0af1", x"1ad0", x"2ab3", x"3a92",
x"fd2e", x"ed0f", x"dd6c", x"cd4d", x"bdaa", x"ad8b", x"9de8", x"8dc9",
x"7c26", x"6c07", x"5c64", x"4c45", x"3ca2", x"2c83", x"1ce0", x"0cc1",
x"ef1f", x"ff3e", x"cf5d", x"df7c", x"af9b", x"bfba", x"8fd9", x"9ff8",
x"6e17", x"7e36", x"4e55", x"5e74", x"2e93", x"3eb2", x"0ed1", x"1ef0" );
variable index : natural range 0 to 255;
variable result : std_logic_vector(15 downto 0);
begin
result := crc;
index := to_integer(unsigned(data(15 downto 8) xor result(15 downto 8)));
result := crcTable(index) xor (result(7 downto 0) & x"00");
index := to_integer(unsigned(data(7 downto 0) xor result(15 downto 8)));
result := crcTable(index) xor (result(7 downto 0) & x"00");
return result;
end Crc16;
---------------------------------------------------------------------------
-- Create a randomly initialized data array.
---------------------------------------------------------------------------
procedure CreateRandomPayload(
variable payload : out HalfwordArray(0 to 132);
variable seed1 : inout positive;
variable seed2 : inout positive) is
variable rand: real;
variable int_rand: integer;
variable stim: std_logic_vector(7 downto 0);
begin
for i in payload'range loop
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
end loop;
end procedure;
procedure CreateRandomPayload(
variable payload : out DoublewordArray(0 to 31);
variable seed1 : inout positive;
variable seed2 : inout positive) is
variable rand: real;
variable int_rand: integer;
variable stim: std_logic_vector(7 downto 0);
begin
for i in payload'range loop
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(23 downto 16) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(31 downto 24) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(39 downto 32) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(47 downto 40) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(55 downto 48) := std_logic_vector(to_unsigned(int_rand, 8));
uniform(seed1, seed2, rand);
int_rand := integer(trunc(rand*256.0));
payload(i)(63 downto 56) := std_logic_vector(to_unsigned(int_rand, 8));
end loop;
end procedure;
---------------------------------------------------------------------------
-- Create a generic RapidIO frame.
---------------------------------------------------------------------------
function RioFrameCreate(
constant ackId : in std_logic_vector(4 downto 0);
constant vc : in std_logic;
constant crf : in std_logic;
constant prio : in std_logic_vector(1 downto 0);
constant tt : in std_logic_vector(1 downto 0);
constant ftype : in std_logic_vector(3 downto 0);
constant sourceId : in std_logic_vector(15 downto 0);
constant destId : in std_logic_vector(15 downto 0);
constant payload : in RioPayload) return RioFrame is
variable frame : RioFrame;
variable result : HalfwordArray(0 to 137);
variable crc : std_logic_vector(15 downto 0) := x"ffff";
begin
-- Add the header and addresses.
result(0) := ackId & "0" & vc & crf & prio & tt & ftype;
result(1) := destId;
result(2) := sourceId;
-- Update the calculated CRC with the header contents.
crc := Crc16("00000" & result(0)(10 downto 0), crc);
crc := Crc16(result(1), crc);
crc := Crc16(result(2), crc);
-- Check if a single CRC should be added or two.
if (payload.length <= 37) then
-- Single CRC.
for i in 0 to payload.length-1 loop
result(i+3) := payload.data(i);
crc := Crc16(payload.data(i), crc);
end loop;
result(payload.length+3) := crc;
-- Check if paddning is needed to make the payload even 32-bit.
if ((payload.length mod 2) = 1) then
result(payload.length+4) := x"0000";
frame.length := (payload.length+5) / 2;
else
frame.length := (payload.length+4) / 2;
end if;
else
-- Double CRC.
for i in 0 to 36 loop
result(i+3) := payload.data(i);
crc := Crc16(payload.data(i), crc);
end loop;
-- Add in-the-middle crc.
result(40) := crc;
crc := Crc16(crc, crc);
for i in 37 to payload.length-1 loop
result(i+4) := payload.data(i);
crc := Crc16(payload.data(i), crc);
end loop;
result(payload.length+4) := crc;
-- Check if paddning is needed to make the payload even 32-bit.
if ((payload.length mod 2) = 0) then
result(payload.length+5) := x"0000";
frame.length := (payload.length+6) / 2;
else
frame.length := (payload.length+5) / 2;
end if;
end if;
-- Update the result length.
for i in 0 to frame.length-1 loop
frame.payload(i) := result(2*i) & result(2*i+1);
end loop;
return frame;
end function;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
function RioNwrite(
constant wrsize : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant address : in std_logic_vector(28 downto 0);
constant wdptr : in std_logic;
constant xamsbs : in std_logic_vector(1 downto 0);
constant dataLength : in natural range 1 to 32;
constant data : in DoublewordArray(0 to 31))
return RioPayload is
variable payload : RioPayload;
begin
payload.data(0)(15 downto 12) := "0100";
payload.data(0)(11 downto 8) := wrsize;
payload.data(0)(7 downto 0) := tid;
payload.data(1) := address(28 downto 13);
payload.data(2)(15 downto 3) := address(12 downto 0);
payload.data(2)(2) := wdptr;
payload.data(2)(1 downto 0) := xamsbs;
for i in 0 to dataLength-1 loop
payload.data(3+4*i) := data(i)(63 downto 48);
payload.data(4+4*i) := data(i)(47 downto 32);
payload.data(5+4*i) := data(i)(31 downto 16);
payload.data(6+4*i) := data(i)(15 downto 0);
end loop;
payload.length := 3 + 4*dataLength;
return payload;
end function;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
function RioNread(
constant rdsize : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant address : in std_logic_vector(28 downto 0);
constant wdptr : in std_logic;
constant xamsbs : in std_logic_vector(1 downto 0))
return RioPayload is
variable payload : RioPayload;
begin
payload.data(0)(15 downto 12) := "0100";
payload.data(0)(11 downto 8) := rdsize;
payload.data(0)(7 downto 0) := tid;
payload.data(1) := address(28 downto 13);
payload.data(2)(15 downto 3) := address(12 downto 0);
payload.data(2)(2) := wdptr;
payload.data(2)(1 downto 0) := xamsbs;
payload.length := 3;
return payload;
end function;
---------------------------------------------------------------------------
-- Create a RESPONSE RapidIO frame.
---------------------------------------------------------------------------
function RioResponse(
constant status : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant dataLength : in natural range 0 to 32;
constant data : in DoublewordArray(0 to 31))
return RioPayload is
variable payload : RioPayload;
begin
payload.data(0)(11 downto 8) := status;
payload.data(0)(7 downto 0) := tid;
if (dataLength = 0) then
payload.data(0)(15 downto 12) := "0000";
payload.length := 1;
else
payload.data(0)(15 downto 12) := "1000";
for i in 0 to dataLength-1 loop
payload.data(1+4*i) := data(i)(63 downto 48);
payload.data(2+4*i) := data(i)(47 downto 32);
payload.data(3+4*i) := data(i)(31 downto 16);
payload.data(4+4*i) := data(i)(15 downto 0);
end loop;
payload.length := 1 + 4*dataLength;
end if;
return payload;
end function;
---------------------------------------------------------------------------
-- Create a Maintenance RapidIO frame.
---------------------------------------------------------------------------
function RioMaintenance(
constant transaction : in std_logic_vector(3 downto 0);
constant size : in std_logic_vector(3 downto 0);
constant tid : in std_logic_vector(7 downto 0);
constant hopCount : in std_logic_vector(7 downto 0);
constant configOffset : in std_logic_vector(20 downto 0);
constant wdptr : in std_logic;
constant dataLength : in natural range 0 to 8;
constant data : in DoublewordArray(0 to 7))
return RioPayload is
variable payload : RioPayload;
begin
payload.data(0)(15 downto 12) := transaction;
payload.data(0)(11 downto 8) := size;
payload.data(0)(7 downto 0) := tid;
payload.data(1)(15 downto 8) := hopCount;
payload.data(1)(7 downto 0) := configOffset(20 downto 13);
payload.data(2)(15 downto 3) := configOffset(12 downto 0);
payload.data(2)(2) := wdptr;
payload.data(2)(1 downto 0) := "00";
if (dataLength = 0) then
payload.length := 3;
else
for i in 0 to dataLength-1 loop
payload.data(3+4*i) := data(i)(63 downto 48);
payload.data(4+4*i) := data(i)(47 downto 32);
payload.data(5+4*i) := data(i)(31 downto 16);
payload.data(6+4*i) := data(i)(15 downto 0);
end loop;
payload.length := 3 + 4*dataLength;
end if;
return payload;
end function;
-----------------------------------------------------------------------------
-- Function to convert a std_logic_vector to a string.
-----------------------------------------------------------------------------
function byteToString(constant byte : std_logic_vector(7 downto 0))
return string is
constant table : string(1 to 16) := "0123456789abcdef";
variable returnValue : string(1 to 2);
begin
returnValue(1) := table(to_integer(unsigned(byte(7 downto 4))) + 1);
returnValue(2) := table(to_integer(unsigned(byte(3 downto 0))) + 1);
return returnValue;
end function;
---------------------------------------------------------------------------
-- Procedure to print test report
---------------------------------------------------------------------------
procedure PrintR( constant str : string ) is
file reportFile : text;
variable reportLine, outputLine : line;
variable fStatus: FILE_OPEN_STATUS;
begin
--Write report note to wave/transcript window
report str severity NOTE;
end PrintR;
---------------------------------------------------------------------------
-- Procedure to print test spec
---------------------------------------------------------------------------
procedure PrintS( constant str : string ) is
file specFile : text;
variable specLine, outputLine : line;
variable fStatus: FILE_OPEN_STATUS;
begin
--Write to spec file
file_open(fStatus, specFile, "testspec.txt", append_mode);
write(specLine, string'(str));
writeline (specFile, specLine);
file_close(specFile);
end PrintS;
---------------------------------------------------------------------------
-- Procedure to Assert Expression
---------------------------------------------------------------------------
procedure AssertE( constant exp: boolean; constant str : string ) is
file reportFile : text;
variable reportLine, outputLine : line;
variable fStatus: FILE_OPEN_STATUS;
begin
if (not exp) then
--Write to STD_OUTPUT
report(str) severity error;
else
PrintR("Status: Passed");
PrintS("Status: Passed");
end if;
end AssertE;
---------------------------------------------------------------------------
-- Procedure to Print Error
---------------------------------------------------------------------------
procedure PrintE( constant str : string ) is
file reportFile : text;
variable reportLine, outputLine : line;
variable fStatus: FILE_OPEN_STATUS;
begin
--Write to STD_OUTPUT
report str severity error;
end PrintE;
---------------------------------------------------------------------------
-- Procedure to end a test.
---------------------------------------------------------------------------
procedure TestEnd is
begin
assert false report "Test complete." severity failure;
wait;
end TestEnd;
end rio_common;
-------------------------------------------------------------------------------
-- Crc16CITT
-- A CRC-16 calculator following the implementation proposed in the 2.2
-- standard.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity for Crc16CITT.
-------------------------------------------------------------------------------
entity Crc16CITT is
port(
d_i : in std_logic_vector(15 downto 0);
crc_i : in std_logic_vector(15 downto 0);
crc_o : out std_logic_vector(15 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for Crc16CITT.
-------------------------------------------------------------------------------
architecture Crc16Impl of Crc16CITT is
signal d : std_logic_vector(0 to 15);
signal c : std_logic_vector(0 to 15);
signal e : std_logic_vector(0 to 15);
signal cc : std_logic_vector(0 to 15);
begin
-- Reverse the bit vector indexes to make them the same as in the standard.
d(15) <= d_i(0); d(14) <= d_i(1); d(13) <= d_i(2); d(12) <= d_i(3);
d(11) <= d_i(4); d(10) <= d_i(5); d(9) <= d_i(6); d(8) <= d_i(7);
d(7) <= d_i(8); d(6) <= d_i(9); d(5) <= d_i(10); d(4) <= d_i(11);
d(3) <= d_i(12); d(2) <= d_i(13); d(1) <= d_i(14); d(0) <= d_i(15);
-- Reverse the bit vector indexes to make them the same as in the standard.
c(15) <= crc_i(0); c(14) <= crc_i(1); c(13) <= crc_i(2); c(12) <= crc_i(3);
c(11) <= crc_i(4); c(10) <= crc_i(5); c(9) <= crc_i(6); c(8) <= crc_i(7);
c(7) <= crc_i(8); c(6) <= crc_i(9); c(5) <= crc_i(10); c(4) <= crc_i(11);
c(3) <= crc_i(12); c(2) <= crc_i(13); c(1) <= crc_i(14); c(0) <= crc_i(15);
-- Calculate the resulting crc.
e <= c xor d;
cc(0) <= e(4) xor e(5) xor e(8) xor e(12);
cc(1) <= e(5) xor e(6) xor e(9) xor e(13);
cc(2) <= e(6) xor e(7) xor e(10) xor e(14);
cc(3) <= e(0) xor e(7) xor e(8) xor e(11) xor e(15);
cc(4) <= e(0) xor e(1) xor e(4) xor e(5) xor e(9);
cc(5) <= e(1) xor e(2) xor e(5) xor e(6) xor e(10);
cc(6) <= e(0) xor e(2) xor e(3) xor e(6) xor e(7) xor e(11);
cc(7) <= e(0) xor e(1) xor e(3) xor e(4) xor e(7) xor e(8) xor e(12);
cc(8) <= e(0) xor e(1) xor e(2) xor e(4) xor e(5) xor e(8) xor e(9) xor e(13);
cc(9) <= e(1) xor e(2) xor e(3) xor e(5) xor e(6) xor e(9) xor e(10) xor e(14);
cc(10) <= e(2) xor e(3) xor e(4) xor e(6) xor e(7) xor e(10) xor e(11) xor e(15);
cc(11) <= e(0) xor e(3) xor e(7) xor e(11);
cc(12) <= e(0) xor e(1) xor e(4) xor e(8) xor e(12);
cc(13) <= e(1) xor e(2) xor e(5) xor e(9) xor e(13);
cc(14) <= e(2) xor e(3) xor e(6) xor e(10) xor e(14);
cc(15) <= e(3) xor e(4) xor e(7) xor e(11) xor e(15);
-- Reverse the bit vector indexes to make them the same as in the standard.
crc_o(15) <= cc(0); crc_o(14) <= cc(1); crc_o(13) <= cc(2); crc_o(12) <= cc(3);
crc_o(11) <= cc(4); crc_o(10) <= cc(5); crc_o(9) <= cc(6); crc_o(8) <= cc(7);
crc_o(7) <= cc(8); crc_o(6) <= cc(9); crc_o(5) <= cc(10); crc_o(4) <= cc(11);
crc_o(3) <= cc(12); crc_o(2) <= cc(13); crc_o(1) <= cc(14); crc_o(0) <= cc(15);
end architecture;
-------------------------------------------------------------------------------
-- MemoryDualPort
-- Generic synchronous memory with one read/write port and one read port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for MemoryDualPort.
-------------------------------------------------------------------------------
entity MemoryDualPort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
writeEnableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
clkB_i : in std_logic;
enableB_i : in std_logic;
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for MemoryDualPort.
-------------------------------------------------------------------------------
architecture MemoryDualPortImpl of MemoryDualPort is
type MemoryType is array (natural range <>) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
begin
process(clkA_i)
begin
if (clkA_i'event and clkA_i = '1') then
if (enableA_i = '1') then
if (writeEnableA_i = '1') then
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
end if;
dataA_o <= memory(to_integer(unsigned(addressA_i)));
end if;
end if;
end process;
process(clkB_i)
begin
if (clkB_i'event and clkB_i = '1') then
if (enableB_i = '1') then
dataB_o <= memory(to_integer(unsigned(addressB_i)));
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
-- MemorySimpleDualPort
-- Generic synchronous memory with one write port and one read port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for MemorySimpleDualPort.
-------------------------------------------------------------------------------
entity MemorySimpleDualPort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
clkB_i : in std_logic;
enableB_i : in std_logic;
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for MemorySimpleDualPort.
-------------------------------------------------------------------------------
architecture MemorySimpleDualPortImpl of MemorySimpleDualPort is
type MemoryType is array (natural range <>) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
begin
process(clkA_i)
begin
if (clkA_i'event and clkA_i = '1') then
if (enableA_i = '1') then
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
end if;
end if;
end process;
process(clkB_i)
begin
if (clkB_i'event and clkB_i = '1') then
if (enableB_i = '1') then
dataB_o <= memory(to_integer(unsigned(addressB_i)));
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
-- MemorySinglePort
-- Generic synchronous memory with one read/write port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for MemorySinglePort.
-------------------------------------------------------------------------------
entity MemorySinglePort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clk_i : in std_logic;
enable_i : in std_logic;
writeEnable_i : in std_logic;
address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for MemorySinglePort.
-------------------------------------------------------------------------------
architecture MemorySinglePortImpl of MemorySinglePort is
type MemoryType is array (natural range <>) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (enable_i = '1') then
if (writeEnable_i = '1') then
memory(to_integer(unsigned(address_i))) <= data_i;
end if;
data_o <= memory(to_integer(unsigned(address_i)));
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
-- MemorySimpleDualPortAsync
-- Generic memory with one synchronous write port and one asynchronous read port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for MemorySimpleDualPortAsync.
-------------------------------------------------------------------------------
entity MemorySimpleDualPortAsync is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1;
INIT_VALUE : std_logic := 'U');
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for MemorySimpleDualPortAsync.
-------------------------------------------------------------------------------
architecture MemorySimpleDualPortAsyncImpl of MemorySimpleDualPortAsync is
type MemoryType is array (natural range <>) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1) := (others=>(others=>INIT_VALUE));
begin
process(clkA_i)
begin
if (clkA_i'event and clkA_i = '1') then
if (enableA_i = '1') then
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
end if;
end if;
end process;
dataB_o <= memory(to_integer(unsigned(addressB_i)));
end architecture;
-------------------------------------------------------------------------------
-- RioFifo1
-- Simple fifo which is one entry deep.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity for RioFifo1.
-------------------------------------------------------------------------------
entity RioFifo1 is
generic(
WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
empty_o : out std_logic;
read_i : in std_logic;
data_o : out std_logic_vector(WIDTH-1 downto 0);
full_o : out std_logic;
write_i : in std_logic;
data_i : in std_logic_vector(WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioFifo1.
-------------------------------------------------------------------------------
architecture RioFifo1Impl of RioFifo1 is
signal empty : std_logic;
signal full : std_logic;
begin
empty_o <= empty;
full_o <= full;
process(areset_n, clk)
begin
if (areset_n = '0') then
empty <= '1';
full <= '0';
data_o <= (others => '0');
elsif (clk'event and clk = '1') then
if (empty = '1') then
if (write_i = '1') then
empty <= '0';
full <= '1';
data_o <= data_i;
end if;
else
if (read_i = '1') then
empty <= '1';
full <= '0';
end if;
end if;
end if;
end process;
end architecture;
| bsd-3-clause |
pkerling/ethernet_mac | generic/single_signal_synchronizer_simple.vhd | 1 | 608 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Simple two-FF synchronizer
library ieee;
use ieee.std_logic_1164.all;
architecture simple of single_signal_synchronizer is
signal signal_tmp : std_ulogic := '0';
begin
process(clock_target_i, preset_i)
begin
if preset_i = '1' then
signal_tmp <= '1';
signal_o <= '1';
elsif rising_edge(clock_target_i) then
signal_tmp <= signal_i;
signal_o <= signal_tmp;
end if;
end process;
end architecture;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Video_PR_1.0/hdl/Video_Box.vhd | 1 | 2555 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/10/2017 11:07:04 AM
-- Design Name:
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
architecture Behavioral of Video_Box is
attribute BLACK_BOX : string;
attribute BLACK_BOX of Behavioral: architecture is "TRUE";
begin
end Behavioral;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/rgb2dvi/src/OutputSERDES.vhd | 11 | 8366 | -------------------------------------------------------------------------------
--
-- File: OutputSERDES.vhd
-- Author: Elod Gyorgy, Mihaita Nagy
-- Original Project: HDMI output on 7-series Xilinx FPGA
-- Date: 28 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity OutputSERDES is
Generic (
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in STD_LOGIC; --TMDS clock x1 (CLKDIV)
SerialClk : in STD_LOGIC; --TMDS clock x5 (CLK)
--Encoded serial data
sDataOut_p : out STD_LOGIC;
sDataOut_n : out STD_LOGIC;
--Encoded parallel data (raw)
pDataOut : in STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
aRst : in STD_LOGIC);
end OutputSERDES;
architecture Behavioral of OutputSERDES is
signal sDataOut, ocascade1, ocascade2 : std_logic;
signal pDataOut_q : std_logic_vector(13 downto 0);
begin
-- Differential output buffer for TMDS I/O standard
OutputBuffer: OBUFDS
generic map (
IOSTANDARD => "TMDS_33")
port map (
O => sDataOut_p,
OB => sDataOut_n,
I => sDataOut);
-- Serializer, 10:1 (5:1 DDR), master-slave cascaded
SerializerMaster: OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => kParallelWidth,
TRISTATE_WIDTH => 1,
TBYTE_CTL => "FALSE",
TBYTE_SRC => "FALSE",
SERDES_MODE => "MASTER")
port map (
OFB => open, -- 1-bit output: Feedback path for data
OQ => sDataOut, -- 1-bit output: Data path output
-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TBYTEOUT => open, -- 1-bit output: Byte group tristate
TFB => open, -- 1-bit output: 3-state control
TQ => open, -- 1-bit output: 3-state control
CLK => SerialClk, -- 1-bit input: High speed clock
CLKDIV => PixelClk, -- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => pDataOut_q(13),
D2 => pDataOut_q(12),
D3 => pDataOut_q(11),
D4 => pDataOut_q(10),
D5 => pDataOut_q(9),
D6 => pDataOut_q(8),
D7 => pDataOut_q(7),
D8 => pDataOut_q(6),
OCE => '1', -- 1-bit input: Output data clock enable
RST => aRst, -- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => ocascade1,
SHIFTIN2 => ocascade2,
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' -- 1-bit input: 3-state clock enable
);
SerializerSlave: OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => kParallelWidth,
TRISTATE_WIDTH => 1,
TBYTE_CTL => "FALSE",
TBYTE_SRC => "FALSE",
SERDES_MODE => "SLAVE")
port map (
OFB => open, -- 1-bit output: Feedback path for data
OQ => open, -- 1-bit output: Data path output
-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT1 => ocascade1,
SHIFTOUT2 => ocascade2,
TBYTEOUT => open, -- 1-bit output: Byte group tristate
TFB => open, -- 1-bit output: 3-state control
TQ => open, -- 1-bit output: 3-state control
CLK => SerialClk, -- 1-bit input: High speed clock
CLKDIV => PixelClk, -- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => '0',
D2 => '0',
D3 => pDataOut_q(5),
D4 => pDataOut_q(4),
D5 => pDataOut_q(3),
D6 => pDataOut_q(2),
D7 => pDataOut_q(1),
D8 => pDataOut_q(0),
OCE => '1', -- 1-bit input: Output data clock enable
RST => aRst, -- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' -- 1-bit input: 3-state clock enable
);
-------------------------------------------------------------
-- Concatenate the serdes inputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceOSERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
--OSERDESE2 sends D1 bit first
pDataOut_q(14-slice_count-1) <= pDataOut(slice_count);
end generate SliceOSERDES_q;
end Behavioral;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/usb2device_v1_0/src/HS_Negotiation.vhd | 2 | 24545 | -------------------------------------------------------------------------------
--
-- File: HS_Negotiation.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles the USB speed negociatian, reset and suspend protocols
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity HS_Negotiation is
Port (
u_Reset : in STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
--command signals used to initiate register read/write,
--NOPID frameworks of the ULPI state machine
u_Send_NOPID_CMD : out STD_LOGIC;
u_Send_EXTW_CMD : out STD_LOGIC;
u_Send_REGW_CMD : out STD_LOGIC;
u_Send_EXTR_CMD : out STD_LOGIC;
u_Send_REGR_CMD : out STD_LOGIC;
u_Send_STP_CMD : out STD_LOGIC;
u_Send_Last : out STD_LOGIC;
u_Remote_Wake : in STD_LOGIC;
--NOPID data, register data, register address used for
--attachment signaling and for chirping
u_Tx_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Regw_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Reg_Addr : out STD_LOGIC_VECTOR (7 downto 0);
--inputs from ULPI state machine
u_Rx_Cmd_Received : in STD_LOGIC;
u_Tx_Cmd_Done : in STD_LOGIC;
--UTMI+ signals
u_LineState : in STD_LOGIC_VECTOR (1 downto 0);
u_Vbus : in STD_LOGIC_VECTOR (1 downto 0);
-- Negotiation outputs
u_USB_Mode : out STD_LOGIC;
u_Not_Connected : OUT std_logic;
u_Set_Mode_HS : OUT std_logic;
u_Set_Mode_FS : OUT std_logic;
u_Wake : OUT std_logic;
u_USBCMD_RS : in std_logic;
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0);
u_Negociation_Done : out STD_LOGIC
);
end HS_Negotiation;
architecture Behavioral of HS_Negotiation is
constant Const_10Ms : STD_LOGIC_VECTOR (10 downto 0) := "00001100100"; --100
constant Const_20Ms : STD_LOGIC_VECTOR (10 downto 0) := "00011001000"; --200
constant Const_50Ms : STD_LOGIC_VECTOR (10 downto 0) := "00111110100"; --500
constant Const_1_2Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000001100"; --12
constant Const_2_5Us : STD_LOGIC_VECTOR (12 downto 0) := "0000010010110"; --150 * Ulpi_Clk_period = 2.5Us
constant Const_2_5Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000011001"; --25Const_3Ms
constant Const_3Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000011110"; --30
constant Const_200Us : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; --2
type state_type is (IDLE, REGR, EXTR_W, EXTR_R, DISCONNECTED, WAIT_ATTACH, WRITE_FCR, ATTACH, WAIT_RESET, PULL_UP_ID, NORMAL,RST_RES_SUSP, SUSPEND, HS_SUSPEND, FS_SUSPEND, SUSP_RES, RESET, ERROR, SEND_CHIRP_K, WAIT_CHIRP_J, WAIT_CHIRP_K, SEND_CHIRP_K_LAST, WAIT_CHIRP_SE0, SET_FS, SET_HS, SWITCH_FS, FS_WAIT_SE0, FS_WAIT_J, RESUME_REQ_WAIT, WAIT_HSEOP, CLEAR_SUSPEND, SIGNAL_WAKE); -- CLEAR_SUSPEND_COMPLETE
signal u_Negociation_State, u_Negociation_Next_State : state_type;
signal u_RX_J : STD_LOGIC;
signal u_RX_K : STD_LOGIC;
signal u_RX_SE0 : STD_LOGIC;
signal u_RX_Idle : STD_LOGIC;
signal u_Set_Mode_HS_Loc : STD_LOGIC;
signal u_Mode : STD_LOGIC; --1 when the device is in High Speed mode, 0 otherwise
signal u_Negociation_Done_Rst : STD_LOGIC;
signal u_Negociation_Done_Set : STD_LOGIC;
signal u_LineState_q : STD_LOGIC_VECTOR(1 downto 0);
signal u_LineState_Change : STD_LOGIC;
signal u_Cnt1_Us : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt1_Ms : STD_LOGIC_VECTOR(10 downto 0);
signal u_Cnt2_Us : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt1_Ms_Presc : STD_LOGIC;
signal u_Cnt1_Rst_Ms : STD_LOGIC;-- initial 100ms, chirp_k
signal u_Cnt2_Rst_Ms : STD_LOGIC;
signal u_Cnt_Chirp : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal u_Cnt_Chirp_CE : STD_LOGIC;
signal u_Cnt_Chirp_Rst : STD_LOGIC;
--degug
signal u_Cnt1_Ms_debug : STD_LOGIC_VECTOR(10 downto 0);
attribute mark_debug : string;
attribute keep : string;
--attribute mark_debug of state_ind_hs_r : signal is "true";
--attribute keep of state_ind_hs_r : signal is "true";
--attribute mark_debug of rst : signal is "true";
--attribute keep of rst : signal is "true";
--attribute mark_debug of u_LineState : signal is "true";
--attribute keep of u_LineState : signal is "true";
--attribute mark_debug of u_Cnt1_Us : signal is "true";
--attribute keep of u_Cnt1_Us : signal is "true";
--attribute mark_debug of u_Cnt1_Ms : signal is "true";
--attribute keep of u_Cnt1_Ms : signal is "true";
--attribute mark_debug of u_RX_Idle : signal is "true";
--attribute keep of u_RX_Idle : signal is "true";
--attribute mark_debug of u_Cnt1_Rst_Ms : signal is "true";
--attribute keep of u_Cnt1_Rst_Ms : signal is "true";
--attribute mark_debug of u_Mode : signal is "true";
--attribute keep of u_Mode : signal is "true";
--attribute mark_debug of u_Cnt1_Ms_debug : signal is "true";
--attribute keep of u_Cnt1_Ms_debug : signal is "true";
begin
u_USB_Mode <= u_Mode;
u_Set_Mode_HS <= u_Set_Mode_HS_Loc;
u_RX_SE0 <= '1' when u_LineState = "00"
else '0';
u_RX_K <= '1' when u_LineState = "10"
else '0';
u_RX_J <= '1' when u_LineState = "01"
else '0';
u_RX_Idle <= u_RX_SE0 when u_Mode = '1'
else u_RX_J;
--debug purposes
delay_cnt: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
u_Cnt1_Ms_debug <= u_Cnt1_Ms;
end if;
end process;
--detect state machine changes
STATE_CHANGE: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
u_LineState_q <= u_LineState;
if (u_LineState_q = u_LineState) then
u_LineState_Change <= '0';
else
u_LineState_Change <= '1';
end if;
end if;
end process;
--u_Mode encodes the negotiated speed
MODEHS : process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0') then
u_Mode <= '0';
else
if (u_Set_Mode_HS_Loc = '1') then
u_Mode <= '1';
end if;
end if;
end if;
end process;
NEG_DONE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0' or u_Negociation_Done_Rst = '0') then
u_Negociation_Done <= '0';
else
if (u_Negociation_Done_Set = '1') then
u_Negociation_Done <= '1';
end if;
end if;
end if;
end process;
--Counters/Timers used to monitor Reset, Suspend, Resume, High Speed Negotiation characteristic intervals
US_COUNTER1: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if ((u_Cnt1_Rst_Ms = '1') or (u_Reset = '0')) then
u_Cnt1_Us <= (others => '0');
u_Cnt1_Ms_Presc <= '0';
else
u_Cnt1_Us <= u_Cnt1_Us + '1';
if (u_Cnt1_Us = 6000) then -- u_Cnt1_Ms_Presc = 100us
u_Cnt1_Ms_Presc <= '1';
u_Cnt1_Us <= (others => '0');
else
u_Cnt1_Ms_Presc <= '0';
end if;
end if;
end if;
end process;
MS_COUNTER1: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt1_Rst_Ms = '1' or (u_Reset = '0')) then
u_Cnt1_Ms <= (others => '0');
else
if (u_Cnt1_Ms_Presc = '1') then
u_Cnt1_Ms <= u_Cnt1_Ms + '1';
end if;
end if;
end if;
end process;
US_COUNTER2: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt2_Rst_Ms = '1' or (u_Reset = '0')) then
u_Cnt2_Us <= (others => '0');
else
u_Cnt2_Us <= u_Cnt2_Us + '1';
if (u_Cnt2_Us = 6000) then
u_Cnt2_Us <= (others => '0');
end if;
end if;
end if;
end process;
CHIRP_COUNTER: process (u_Cnt_Chirp_CE, Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt_Chirp_Rst = '1' or (u_Reset = '0')) then
u_Cnt_Chirp <= (others => '0');
elsif (u_Cnt_Chirp_CE = '1') then
u_Cnt_Chirp <= u_Cnt_Chirp + '1';
end if;
end if;
end process;
--High Speed Negotiation State Machine
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0') then
u_Negociation_State <= IDLE;
else
u_Negociation_State <= u_Negociation_Next_State;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (u_Negociation_State, u_Vbus, u_Rx_Cmd_Received, u_USBCMD_RS, u_LineState, u_LineState_Change, u_Tx_Cmd_Done, u_RX_J, u_RX_K, u_RX_Idle, u_RX_SE0, u_Cnt_Chirp, u_Remote_Wake, u_Mode)
begin
u_Negociation_Next_State <= u_Negociation_State;
state_ind_hs <= "00000";
u_Tx_Data <= (others => '0');
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Cnt_Chirp_CE <= '0';
u_Cnt_Chirp_Rst <= '1';
u_Set_Mode_HS_Loc <= '0';
u_Negociation_Done_Rst <= '1';
u_Negociation_Done_Set <= '0';
u_Send_REGW_CMD <= '0';
u_Send_NOPID_CMD <= '0';
u_Send_Last <= '0';
u_Tx_Regw_Data <= (others => '0');
u_Tx_Reg_Addr <= (others => '0');
u_Send_REGR_CMD <= '0';
u_Send_EXTW_CMD <= '0';
u_Send_EXTR_CMD <= '0';
u_Send_STP_CMD <= '0';
u_Not_Connected <= '0';
u_Set_Mode_FS <= '0';
u_Wake <= '0';
case (u_Negociation_State) is
when IDLE =>
if (u_USBCMD_RS = '1') then --Waits for user interaction (USBCMD-> RS bit : Run/Stop) to start negociation
u_Negociation_Next_State <= DISCONNECTED;
end if;
when DISCONNECTED =>
state_ind_hs <= "00001";
u_Negociation_Done_Rst <= '0';
u_Not_Connected <= '1';
if (u_Vbus = "11") then
u_Negociation_Next_State <= WAIT_ATTACH;
end if;
when WAIT_ATTACH =>
state_ind_hs <= "00010";
u_Not_Connected <= '1';
u_Cnt1_Rst_Ms <= '0';
if ( u_Cnt1_Ms = Const_50Ms) then -- Debounce interval. Not required by specifications
if (u_Vbus = "11") then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= PULL_UP_ID;
else
u_Negociation_Next_State <= DISCONNECTED;
end if;
end if;
when PULL_UP_ID =>
state_ind_hs <= "00011";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "001010"; --u_Tx_Data (6 downto 0) = OTG control reg write addr
u_Tx_Regw_Data <= "00000001";
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= WRITE_FCR;
end if;
when WRITE_FCR =>
state_ind_hs <= "00100";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --Select peripheral Full Speed driver: opmode = 00, xcvrselect = 01, termselect = 1; the pull-up resistor on D+ will be attached
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= ATTACH;
end if;
when ATTACH =>
state_ind_hs <= "00101";
if (u_LineState = "01") then
u_Negociation_Next_State <= WAIT_RESET;
end if;
when WAIT_RESET => --the host should detect the pull-up resistor and should place the bus in SE0 state
state_ind_hs <= "00110";
u_Cnt1_Rst_Ms <= '0';
if (u_LineState = "00") then
u_Negociation_Next_State <= NORMAL;
end if;
when NORMAL => -- this is the state corresponding to normal operation. The state machine monitors SUSPEND(IDLE) and RESET conditions
state_ind_hs <= "11111";
if ( u_LineState_Change = '0') then
if (u_RX_Idle = '1') then -- if the device is in high speed mode it can not distinguish between IDLE and SE0 at this point
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_3Ms) then
u_Negociation_Next_State <= RST_RES_SUSP;
end if;
elsif ((u_RX_SE0 = '1') and (u_Mode = '0')) then --If the device is being reset from a non-suspended full-speed state, then the device begins a high-speed
--detection handshake after the detection of SE0 for no less than 2.5 ?s and no more than 3.0 ms
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
else
u_Cnt1_Rst_Ms <= '1';
end if;
else
u_Cnt1_Rst_Ms <= '1';
end if;
when RST_RES_SUSP =>
state_ind_hs <= "00111";
if (u_Mode = '0') then
u_Negociation_Next_State <= SUSPEND;
elsif (u_Mode = '1') then
u_Negociation_Next_State <= SWITCH_FS;
end if;
--RESET sequence
when RESET => --Enter High-speed Detection Handshake. Select peripheral chirp by writing to the PHY FCR
state_ind_hs <= "01000";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01010100"; --opmode = 10, xcvrselect = 00, termselect = 1
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SEND_CHIRP_K;
end if;
when SEND_CHIRP_K =>
state_ind_hs <= "01001";
u_Cnt1_Rst_Ms <= '0';
u_Send_NOPID_CMD <= '1'; --This will instruct the ULPI state machine to send NOPID_CMD with transmit data which is by default 00h (drive current into D-)
if (u_Cnt1_Ms = Const_1_2Ms) then --The device chirp must last no less than 1.0 ms (TUCH) and must end no more than 7.0 ms (TUCHEND) high-speed Reset time T0.
u_Cnt1_Rst_Ms <= '1';
u_Send_Last <= '1';
u_Negociation_Next_State <= SEND_CHIRP_K_LAST;
end if;
when SEND_CHIRP_K_LAST =>
state_ind_hs <= "01010";
--u_Tx_Data <= (others => '0');
u_Cnt1_Rst_Ms <= '1';
if (u_Rx_Cmd_Received = '1') then
if (u_RX_SE0 = '1') then
u_Negociation_Next_State <= WAIT_CHIRP_SE0;
end if;
end if;
--------------------------------------------------------------
when WAIT_CHIRP_SE0 =>
state_ind_hs <= "01011";
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
u_Negociation_Next_State <= WAIT_CHIRP_K;
elsif (u_Cnt1_Ms = Const_2_5Ms) then
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
--------------------------------------------------------------
when WAIT_CHIRP_K =>
state_ind_hs <= "01100";
u_Cnt_Chirp_Rst <= '0';
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
if (u_RX_K = '1') then
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
if (u_Cnt2_Us = Const_2_5Us) then
if(u_Cnt_Chirp > 5) then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Cnt_Chirp_Rst <= '1';
u_Cnt_Chirp_CE <= '0';
u_Negociation_Next_State <= SET_HS;
else
u_Cnt_Chirp_CE <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Negociation_Next_State <= WAIT_CHIRP_J;
end if;
end if;
elsif (u_Cnt1_Ms = Const_2_5Ms or u_RX_SE0 = '1') then
u_Send_REGW_CMD <= '1';
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
when WAIT_CHIRP_J =>
state_ind_hs <= "01101";
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
u_Cnt_Chirp_Rst <= '0';
if (u_RX_J = '1') then
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
if (u_Cnt2_Us = Const_2_5Us) then
if(u_Cnt_Chirp > 5) then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Cnt_Chirp_Rst <= '1';
u_Cnt_Chirp_CE <= '0';
u_Negociation_Next_State <= SET_HS;
else
u_Cnt2_Rst_Ms <= '1';
u_Cnt_Chirp_CE <= '1';
u_Negociation_Next_State <= WAIT_CHIRP_K;
end if;
end if;
elsif (u_Cnt1_Ms = Const_2_5Ms or u_RX_SE0 = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "00000101"; --opmode = 00, xcvrselect = 00, termselect = 1
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
when SET_FS =>
state_ind_hs <= "01110";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --opmode = 00, xcvrselect = 01, termselect = 1
u_Send_REGW_CMD <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Done_Set <= '1';
u_Negociation_Next_State <= NORMAL;
end if;
when SET_HS =>
state_ind_hs <= "01111";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000000"; --opmode = 00, xcvrselect = 00, termselect = 0
u_Set_Mode_HS_Loc <= '1';
u_Send_REGW_CMD <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Done_Set <= '1';
u_Negociation_Next_State <= NORMAL;
end if;
---SUSPEND/RESUME -- Not Tested!
when SWITCH_FS => -- Select peripherla Full Speed by writing to FCR
u_Negociation_Done_Rst <= '0';
state_ind_hs <= "10000";
u_Cnt1_Rst_Ms <= '0';
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --opmode = 00, xcvrselect = 01, termselect = 1
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SUSP_RES;
end if;
when SUSP_RES =>
state_ind_hs <= "10001";
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_200Us) then --The device samples the bus state, and checks for SE0 (reset as opposed to suspend), no less than 100 �s and no more than 875 �s (TWTRSTHS) after starting reversion to full-speed.
if( u_RX_SE0 = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
elsif (u_RX_J = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= SUSPEND;
else
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= DISCONNECTED;
end if;
end if;
when SUSPEND =>
state_ind_hs <= "10010";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg set addr
u_Tx_Regw_Data <= "00010101"; --set suspendM
if (u_Tx_Cmd_Done = '1') then
if (u_Mode = '1') then
u_Negociation_Next_State <= HS_SUSPEND;
else
u_Negociation_Next_State <= FS_SUSPEND;
end if;
end if;
when FS_SUSPEND =>
state_ind_hs <= "10011";
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_20Ms) then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= FS_WAIT_SE0;
end if;
elsif (u_RX_SE0 = '1')then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
elsif (u_Remote_Wake = '1') then -- 3ms to enter suspend + 2ms
u_Send_STP_CMD <= '1';
u_Negociation_Next_State <= CLEAR_SUSPEND;
else
u_Cnt1_Rst_Ms <= '1';
end if;
when HS_SUSPEND =>
state_ind_hs <= "10100";
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
state_ind_hs <= "11110";
if (u_Cnt1_Ms = Const_20Ms) then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= WAIT_HSEOP;
end if;
elsif (u_RX_SE0 = '1')then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
state_ind_hs <= "11101";
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
elsif (u_Remote_Wake = '1') then -- 3ms to enter suspend + 2ms
u_Send_STP_CMD <= '1';
u_Negociation_Next_State <= CLEAR_SUSPEND;
else
state_ind_hs <= "11100";
u_Cnt1_Rst_Ms <= '1';
end if;
when FS_WAIT_SE0 =>
state_ind_hs <= "10101";
if (u_RX_SE0 = '1') then
u_Negociation_Next_State <= FS_WAIT_J;
end if;
when FS_WAIT_J =>
state_ind_hs <= "10110";
if (u_RX_J = '1') then
u_Send_REGW_CMD <= '1';
u_Set_Mode_FS <= '1';
u_Wake <= '1';
u_Negociation_Next_State <= SET_FS;
else
u_Negociation_Next_State <= ERROR;
end if;
when WAIT_HSEOP =>
state_ind_hs <= "10111";
if (u_RX_SE0 = '1') then
u_Send_REGW_CMD <= '1';
u_Wake <= '1';
u_Negociation_Next_State <= SET_HS;
end if;
when CLEAR_SUSPEND =>
state_ind_hs <= "11001";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100";
u_Tx_Regw_Data <= "01010101";
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SIGNAL_WAKE;
end if;
when SIGNAL_WAKE =>
state_ind_hs <= "11010";
u_Send_NOPID_CMD <= '1';
u_Tx_Data <= "11111111";
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_10Ms) then
u_Send_Last <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= RESUME_REQ_WAIT;
end if;
end if;
when RESUME_REQ_WAIT =>
state_ind_hs <= "11011";
u_Cnt1_Rst_Ms <= '0';
if (u_RX_K = '1') then
u_Negociation_Next_State <= WAIT_HSEOP;
end if;
when others =>
u_Negociation_Next_State <= DISCONNECTED;
end case;
end process;
end Behavioral;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd | 28 | 10116 | -- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/xip_status_reg.vhd | 2 | 11243 | -------------------------------------------------------------------------------
-- SPI Status Register Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2011] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xip_status_reg.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus. The file defines the logic for
-- status register in XIP mode.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.log2;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-- C_S_AXI_DATA_WIDTH -- Native data bus width 32 bits only
-- C_NUM_SS_BITS -- Number of bits in slave select
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- STATUS REGISTER RELATED SIGNALS
--================================
-- REGISTER/FIFO INTERFACE
-- Bus2IP_SPISR_RdCE -- Status register Read Chip Enable
-- IP2Bus_SPISR_Data -- Status register data to PLB based on PLB read
-- SR_3_modf -- Mode fault error status flag
-- SR_4_Tx_Full -- Transmit register full status flag
-- SR_5_Tx_Empty -- Transmit register empty status flag
-- SR_6_Rx_Full -- Receive register full status flag
-- SR_7_Rx_Empty -- Receive register empty stauts flag
-- ModeFault_Strobe -- Mode fault strobe
-- SLAVE REGISTER RELATED SIGNALS
--===============================
-- Bus2IP_SPISSR_WrCE -- slave select register write chip enable
-- Bus2IP_SPISSR_RdCE -- slave select register read chip enable
-- Bus2IP_SPISSR_Data -- slave register data from PLB Bus
-- IP2Bus_SPISSR_Data -- Data from slave select register during PLB rd
-- SPISSR_Data_reg_op -- Data to SPI Module
-- Wr_ce_reduce_ack_gen -- commaon write ack generation signal
-- Rd_ce_reduce_ack_gen -- commaon read ack generation signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity xip_status_reg is
generic
(
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
------------------------
C_XIP_SPISR_REG_WIDTH : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
--------------------------
XIPSR_AXI_TR_ERR : in std_logic; -- bit 4 of XIPSR
XIPSR_CPHA_CPOL_ERR : in std_logic; -- bit 3 of XIPSR
XIPSR_MST_MODF_ERR : in std_logic; -- bit 2 of XIPSR
XIPSR_AXI_RX_FULL : in std_logic; -- bit 1 of XIPSR
XIPSR_AXI_RX_EMPTY : in std_logic; -- bit 0 of XIPSR
--------------------------
Bus2IP_XIPSR_WrCE : in std_logic;
Bus2IP_XIPSR_RdCE : in std_logic;
--------------------------
--IP2Bus_XIPSR_RdAck : out std_logic;
--IP2Bus_XIPSR_WrAck : out std_logic;
IP2Bus_XIPSR_Data : out std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0);
ip2Bus_RdAck : in std_logic
);
end xip_status_reg;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of xip_status_reg is
----------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal XIPSR_data_int : std_logic_vector(C_XIP_SPISR_REG_WIDTH-1 downto 0);
--signal ip2Bus_RdAck_core_reg : std_logic;
--signal ip2Bus_RdAck_core_reg_d1 : std_logic;
--signal ip2Bus_WrAck_core_reg : std_logic;
--signal ip2Bus_WrAck_core_reg_d1 : std_logic;
----------------------
begin
-----
-- XIPSR - 31 -- -- 5 4 3 2 1 0
-- <-- NA --> AXI CPOL_CPHA MODF Rx Rx
-- Transaction Error Error Error Full Empty
-- Default 0 0 0 0 0
-------------------------------------------------------------------------------
--XIPSR_CMD_ERR <= '0';
---------------------------------------
XIPSR_DATA_STORE_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)<= (others => '0');
elsif(ip2Bus_RdAck = '1') then
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)<= (others => '0');
else
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)
<= XIPSR_AXI_TR_ERR & -- bit 4
XIPSR_CPHA_CPOL_ERR &
XIPSR_MST_MODF_ERR &
XIPSR_AXI_RX_FULL &
XIPSR_AXI_RX_EMPTY ; -- bit 0
end if;
end if;
end process XIPSR_DATA_STORE_P;
--------------------------------------------------
XIPSR_REG_RD_GENERATE: for i in C_XIP_SPISR_REG_WIDTH-1 downto 0 generate
-----
begin
-----
IP2Bus_XIPSR_Data(i) <= XIPSR_data_int(i) and Bus2IP_XIPSR_RdCE ; --and ip2Bus_RdAck_core_reg;
end generate XIPSR_REG_RD_GENERATE;
-----------------------------------
---------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/axi_i2s_adi_1.2/hdl/fifo_synchronizer.vhd | 7 | 3877 | -- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity fifo_synchronizer is
generic (
DEPTH : integer := 4;
WIDTH : integer := 2
);
port (
resetn : in std_logic;
in_clk : in std_logic;
in_data : in std_logic_vector(WIDTH - 1 downto 0);
in_tick : in std_logic;
out_clk : in std_logic;
out_data : out std_logic_vector(WIDTH - 1 downto 0);
out_tick : out std_logic
);
end fifo_synchronizer;
architecture impl of fifo_synchronizer is
type DATA_SYNC_FIFO_TYPE is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
signal fifo: DATA_SYNC_FIFO_TYPE;
signal rd_addr : natural range 0 to DEPTH - 1;
signal wr_addr : natural range 0 to DEPTH - 1;
signal tick : std_logic;
signal tick_d1 : std_logic;
signal tick_d2 : std_logic;
begin
process (in_clk)
begin
if rising_edge(in_clk) then
if resetn = '0' then
wr_addr <= 0;
tick <= '0';
else
if in_tick = '1' then
fifo(wr_addr) <= in_data;
wr_addr <= (wr_addr + 1) mod DEPTH;
tick <= not tick;
end if;
end if;
end if;
end process;
process (out_clk)
begin
if rising_edge(out_clk) then
if resetn = '0' then
rd_addr <= 0;
tick_d1 <= '0';
tick_d2 <= '0';
else
tick_d1 <= tick;
tick_d2 <= tick_d1;
out_tick <= tick_d1 xor tick_d2;
if (tick_d1 xor tick_d2) = '1' then
rd_addr <= (rd_addr + 1) mod DEPTH;
out_data <= fifo(rd_addr);
end if;
end if;
end if;
end process;
end;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_sg_v4_1_2/hdl/src/vhdl/axi_sg_updt_q_mngr.vhd | 7 | 39579 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_q_mngr.vhd
-- Description: This entity is the descriptor update queue manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Control **-- --
--***********************************-- --
ch1_updt_curdesc_wren : out std_logic ; --
ch1_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_active : in std_logic ; --
ch1_updt_queue_empty : out std_logic ; --
ch1_updt_ioc : out std_logic ; --
ch1_updt_ioc_irq_set : in std_logic ; --
--
ch1_dma_interr : out std_logic ; --
ch1_dma_slverr : out std_logic ; --
ch1_dma_decerr : out std_logic ; --
ch1_dma_interr_set : in std_logic ; --
ch1_dma_slverr_set : in std_logic ; --
ch1_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Control **-- --
--***********************************-- --
ch2_updt_active : in std_logic ; --
-- ch2_updt_curdesc_wren : out std_logic ; --
-- ch2_updt_curdesc : out std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_queue_empty : out std_logic ; --
ch2_updt_ioc : out std_logic ; --
ch2_updt_ioc_irq_set : in std_logic ; --
--
ch2_dma_interr : out std_logic ; --
ch2_dma_slverr : out std_logic ; --
ch2_dma_decerr : out std_logic ; --
ch2_dma_interr_set : in std_logic ; --
ch2_dma_slverr_set : in std_logic ; --
ch2_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Update Interface In **-- --
--***********************************-- --
s_axis_ch1_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Update Interface In **-- --
--***********************************-- --
s_axis_ch2_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--***************************************-- --
--** Update Interface to AXI DataMover **-- --
--***************************************-- --
-- S2MM Stream Out To DataMover --
s_axis_s2mm_tdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_tlast : out std_logic ; --
s_axis_s2mm_tvalid : out std_logic ; --
s_axis_s2mm_tready : in std_logic --
);
end axi_sg_updt_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch1_updt_tlast : std_logic := '0';
signal m_axis_ch1_updt_tvalid : std_logic := '0';
signal m_axis_ch1_updt_tready : std_logic := '0';
signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch2_updt_tlast : std_logic := '0';
signal m_axis_ch2_updt_tvalid : std_logic := '0';
signal m_axis_ch2_updt_tready : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** CHANNEL 1 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 1 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
-------------------------------------------------------------------------------
I_UPDT_DESC_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_INCLUDE_MM2S => C_INCLUDE_CH1 ,
C_INCLUDE_S2MM => C_INCLUDE_CH2 ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch1_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
-- updt2_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt2_curdesc => ch2_updt_curdesc ,
updt2_active => ch2_updt_active ,
updt2_queue_empty => ch2_updt_queue_empty ,
updt2_ioc => ch2_updt_ioc ,
updt2_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma2_interr => ch2_dma_interr ,
dma2_slverr => ch2_dma_slverr ,
dma2_decerr => ch2_dma_decerr ,
dma2_interr_set => ch2_dma_interr_set ,
dma2_slverr_set => ch2_dma_slverr_set ,
dma2_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Update Pointer Stream
s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready ,
-- m_axis2_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis2_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis2_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_QUEUE;
--*****************************************************************************
--** CHANNEL 1 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
begin
I_NO_UPDT_DESC_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
updt2_active => ch2_updt_active ,
updt2_queue_empty => ch2_updt_queue_empty ,
updt2_ioc => ch2_updt_ioc ,
updt2_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma2_interr => ch2_dma_interr ,
dma2_slverr => ch2_dma_slverr ,
dma2_decerr => ch2_dma_decerr ,
dma2_interr_set => ch2_dma_interr_set ,
dma2_slverr_set => ch2_dma_slverr_set ,
dma2_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Update Pointer Stream
s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready ,
-- m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch1_updt_tready ,
-- S2MM Stream Out To DataMover
-- m_axis2_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis2_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis2_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_NO_QUEUE;
-- Channel 1 NOT included therefore tie ch1 outputs off
--GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate
--begin
-- ch1_updt_curdesc_wren <= '0';
-- ch1_updt_curdesc <= (others => '0');
-- ch1_updt_queue_empty <= '1';
-- ch1_updt_ioc <= '0';
-- ch1_dma_interr <= '0';
-- ch1_dma_slverr <= '0';
-- ch1_dma_decerr <= '0';
-- m_axis_ch1_updt_tdata <= (others => '0');
-- m_axis_ch1_updt_tlast <= '0';
-- m_axis_ch1_updt_tvalid <= '0';
-- s_axis_ch1_updtptr_tready <= '0';
-- s_axis_ch1_updtsts_tready <= '0';
--end generate GEN_NO_CH1_UPDATE_Q_IF;
--*****************************************************************************
--** CHANNEL 2 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 2 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
--GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate
--
--begin
--
-- --*************************************************************************
-- --** CHANNEL 2 - DESCRIPTOR QUEUE **
-- --*************************************************************************
-- -- If Descriptor Update queueing enabled then instantiate Queue Logic
-- GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
-- begin
-- ---------------------------------------------------------------------------
-- I_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_queue
-- generic map(
-- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
-- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
-- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
-- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
-- C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
-- C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- ---------------------------------------------------------------
-- -- AXI Scatter Gather Interface
-- ---------------------------------------------------------------
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- s_axis_updt_aclk => s_axis_ch2_updt_aclk ,
--
-- --********************************--
-- --** Control and Status **--
-- --********************************--
-- updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt_curdesc => ch2_updt_curdesc ,
-- updt_active => ch2_updt_active ,
-- updt_queue_empty => ch2_updt_queue_empty ,
-- updt_ioc => ch2_updt_ioc ,
-- updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
--
-- dma_interr => ch2_dma_interr ,
-- dma_slverr => ch2_dma_slverr ,
-- dma_decerr => ch2_dma_decerr ,
-- dma_interr_set => ch2_dma_interr_set ,
-- dma_slverr_set => ch2_dma_slverr_set ,
-- dma_decerr_set => ch2_dma_decerr_set ,
--
-- --********************************--
-- --** Update Interfaces In **--
-- --********************************--
-- -- Update Pointer Stream
-- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
-- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
-- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
-- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
--
-- -- Update Status Stream
-- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
-- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
-- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
-- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--
-- --********************************--
-- --** Update Interfaces Out **--
-- --********************************--
-- -- S2MM Stream Out To DataMover
-- m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch2_updt_tready
-- );
--
-- end generate GEN_CH2_QUEUE;
--
--
-- --*****************************************************************************
-- --** CHANNEL 2 - NO DESCRIPTOR QUEUE **
-- --*****************************************************************************
--
-- -- No update queue enabled, therefore map internal stream logic
-- -- directly to channel port.
-- GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
-- I_NO_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_noqueue
-- generic map(
-- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
-- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
-- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
-- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
-- )
-- port map(
-- ---------------------------------------------------------------
-- -- AXI Scatter Gather Interface
-- ---------------------------------------------------------------
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- --********************************--
-- --** Control and Status **--
-- --********************************--
-- updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt_curdesc => ch2_updt_curdesc ,
-- updt_active => ch2_updt_active ,
-- updt_queue_empty => ch2_updt_queue_empty ,
-- updt_ioc => ch2_updt_ioc ,
-- updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
--
-- dma_interr => ch2_dma_interr ,
-- dma_slverr => ch2_dma_slverr ,
-- dma_decerr => ch2_dma_decerr ,
-- dma_interr_set => ch2_dma_interr_set ,
-- dma_slverr_set => ch2_dma_slverr_set ,
-- dma_decerr_set => ch2_dma_decerr_set ,
--
-- --********************************--
-- --** Update Interfaces In **--
-- --********************************--
-- -- Update Pointer Stream
-- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
-- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
-- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
-- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
--
-- -- Update Status Stream
-- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
-- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
-- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
-- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--
-- --********************************--
-- --** Update Interfaces Out **--
-- --********************************--
-- -- S2MM Stream Out To DataMover
-- m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch2_updt_tready
-- );
--
-- end generate GEN_CH2_NO_QUEUE;
--
--end generate GEN_CH2_UPDATE_Q_IF;
--
---- Channel 2 NOT included therefore tie ch2 outputs off
--GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate
--begin
-- ch2_updt_curdesc_wren <= '0';
-- ch2_updt_curdesc <= (others => '0');
-- ch2_updt_queue_empty <= '1';
--
-- ch2_updt_ioc <= '0';
-- ch2_dma_interr <= '0';
-- ch2_dma_slverr <= '0';
-- ch2_dma_decerr <= '0';
--
-- m_axis_ch2_updt_tdata <= (others => '0');
-- m_axis_ch2_updt_tlast <= '0';
-- m_axis_ch2_updt_tvalid <= '0';
--
-- s_axis_ch2_updtptr_tready <= '0';
-- s_axis_ch2_updtsts_tready <= '0';
--
--end generate GEN_NO_CH2_UPDATE_Q_IF;
-------------------------------------------------------------------------------
-- MUX For DataMover
-------------------------------------------------------------------------------
--TO_DATAMVR_MUX : process(ch1_updt_active,
-- ch2_updt_active,
-- m_axis_ch1_updt_tdata,
-- m_axis_ch1_updt_tlast,
-- m_axis_ch1_updt_tvalid,
-- m_axis_ch2_updt_tdata,
-- m_axis_ch2_updt_tlast,
-- m_axis_ch2_updt_tvalid)
-- begin
-- if(ch1_updt_active = '1')then
-- s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata;
-- s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast;
-- s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid;
-- elsif(ch2_updt_active = '1')then
-- s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata;
-- s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast;
-- s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid;
-- else
-- s_axis_s2mm_tdata <= (others => '0');
-- s_axis_s2mm_tlast <= '0';
-- s_axis_s2mm_tvalid <= '0';
-- end if;
-- end process TO_DATAMVR_MUX;
--
--m_axis_ch1_updt_tready <= s_axis_s2mm_tready;
--m_axis_ch2_updt_tready <= s_axis_s2mm_tready;
--
end implementation;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/dvi2rgb_v1_6/src/EEPROM_8b.vhd | 15 | 8403 | -------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module emulates a generic I2C EEPROM. It is byte-addressable, with
-- a customizable address width (and thus capacity). It can be made writable
-- from I2C or not, in which case all writes are ignored.
-- Providing a file name accessible by the synthesizer will initialize the
-- EEPROM with the default values from the file.
-- An example use case for this module would be a DDC EEPROM, storing EDID
-- (Extended display identification data). The I2C bus bus is compatible
-- with both standard and fast mode.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EEPROM_8b is
Generic (
kSampleClkFreqInMHz : natural := 100;
kSlaveAddress : std_logic_vector(7 downto 1) := "1010000";
kAddrBits : natural range 1 to 8 := 8; -- 2**kAddrBits byte EEPROM capacity
kWritable : boolean := true; -- is it writable from I2C?
kInitFileName : string := ""); -- name of file containing init values, leave empty to init with zero
Port (
SampleClk : in STD_LOGIC; --at least fSCL*10
sRst : in std_logic;
-- two-wire interface
aSDA_I : in STD_LOGIC;
aSDA_O : out STD_LOGIC;
aSDA_T : out STD_LOGIC;
aSCL_I : in STD_LOGIC;
aSCL_O : out STD_LOGIC;
aSCL_T : out STD_LOGIC);
end EEPROM_8b;
architecture Behavioral of EEPROM_8b is
constant kRAM_Width : integer := 8;
type eeprom_t is array (0 to 2**kAddrBits - 1) of std_logic_vector(kRAM_Width-1 downto 0);
impure function InitRamFromFile (ramfilename : in string) return eeprom_t is
file ramfile : text is in ramfilename;
variable ramfileline : line;
variable ram_name : eeprom_t;
variable bitvec : bit_vector(kRAM_Width-1 downto 0);
variable good : boolean;
begin
assert good report "Reading EDID data from file " & ramfilename & "." severity NOTE;
for i in eeprom_t'range loop
readline (ramfile, ramfileline);
read (ramfileline, bitvec, good);
assert good report "Failed to parse EEPROM_8b init file " & ramfilename & "at line " & integer'image(i+1) & "." severity FAILURE;
ram_name(i) := to_stdlogicvector(bitvec);
end loop;
return ram_name;
end function;
impure function init_from_file_or_zeroes(ramfile : string) return eeprom_t is
begin
if ramfile = "" then
return (others => (others => '0'));
else
return InitRamFromFile(ramfile);
end if;
end;
signal eeprom : eeprom_t := init_from_file_or_zeroes(kInitFileName);
signal aEeprom_out : std_logic_vector(kRAM_Width-1 downto 0);
signal sAddr : natural range 0 to 2**kAddrBits - 1;
type state_type is (stIdle, stRead, stWrite, stRegAddress);
signal sState, sNstate : state_type;
signal sI2C_DataIn, sI2C_DataOut : std_logic_vector(7 downto 0);
signal sI2C_Stb, sI2C_Done, sI2C_End, sI2C_RdWrn, sWe : std_logic;
begin
-- Instantiate the I2C Slave Transmitter
I2C_SlaveController: entity work.TWI_SlaveCtl
generic map (
SLAVE_ADDRESS => kSlaveAddress & '0',
kSampleClkFreqInMHz => kSampleClkFreqInMHz)
port map (
D_I => sI2C_DataOut,
D_O => sI2C_DataIn,
RD_WRN_O => sI2C_RdWrn,
END_O => sI2C_End,
DONE_O => sI2C_Done,
STB_I => sI2C_Stb,
SampleClk => SampleClk,
SRST => sRst,
--two-wire interface
SDA_I => aSDA_I,
SDA_O => aSDA_O,
SDA_T => aSDA_T,
SCL_I => aSCL_I,
SCL_O => aSCL_O,
SCL_T => aSCL_T);
-- RAM
Writable: if kWritable generate
EEPROM_RAM: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sWe = '1') then
eeprom(sAddr) <= sI2C_DataIn;
end if;
end if;
end process EEPROM_RAM;
end generate Writable;
-- ROM/RAM sync output
RegisteredOutput: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
sI2C_DataOut <= eeprom(sAddr);
end if;
end process RegisteredOutput;
RegisterAddress: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sI2C_Done = '1') then
if (sState = stRegAddress) then
sAddr <= to_integer(resize(unsigned(sI2C_DataIn), kAddrBits));
elsif (sState = stRead) then
sAddr <= sAddr + 1;
end if;
end if;
end if;
end process RegisterAddress;
--Insert the following in the architecture after the begin keyword
SyncProc: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sRst = '1') then
sState <= stIdle;
else
sState <= sNstate;
end if;
end if;
end process SyncProc;
--MOORE State-Machine - Outputs based on state only
sI2C_Stb <= '1' when (sState = stRegAddress or sState = stRead or sState = stWrite) else '0';
sWe <= '1' when (sState = stWrite) else '0';
NextStateDecode: process (sState, sI2C_Done, sI2C_End, sI2C_RdWrn)
begin
--declare default state for next_state to avoid latches
sNstate <= sState;
case (sState) is
when stIdle =>
if (sI2C_Done = '1') then
if (sI2C_RdWrn = '1') then
sNstate <= stRead;
else
sNstate <= stRegAddress;
end if;
end if;
when stRegAddress =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stWrite;
end if;
when stWrite =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stWrite;
end if;
when stRead =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stRead;
end if;
when others =>
sNstate <= stIdle;
end case;
end process NextStateDecode;
end Behavioral;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/axi_qspi_enhanced_mode.vhd | 2 | 39164 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_qspi_enhanced_mode.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- enhanced mode with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.log2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library interrupt_control_v3_1_4;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
entity axi_qspi_enhanced_mode is
generic (
-- General Parameters
C_FAMILY : string := "virtex7";
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_AXI4_CLK_PS : integer := 10000;--AXI clock period
C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_FIFO_DEPTH : integer := 16;-- allowed 0,16,256.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode,
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer range 24 to 24 := 24;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c";
C_SPI_MEM_ADDR_BITS : integer -- newly added
);
port (
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
S_AXI4_ARESETN : in std_logic;
-------------------------------
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
Bus2IP_Clk : out std_logic;
Bus2IP_Reset : out std_logic;
--Bus2IP_Addr : out std_logic_vector
-- (C_S_AXI4_ADDR_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI4_DATA_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI4_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI4_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic;
---------------------------------
burst_tr : out std_logic;
rready : out std_logic
);
end entity axi_qspi_enhanced_mode;
architecture imp of axi_qspi_enhanced_mode is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
constant ACTIVE_LOW_RESET : std_logic := '0';
-- local type declarations
type STATE_TYPE is (
IDLE,
AXI_SINGLE_RD,
AXI_RD,
AXI_SINGLE_WR,
AXI_WR,
CHECK_AXI_LENGTH_ERROR,
AX_WRONG_BURST_TYPE,
WR_RESP_1,
WR_RESP_2,
RD_RESP_1,RD_LAST,
RD_RESP_2,
ERROR_RESP,
RD_ERROR_RESP
);
-- Signal Declaration
-----------------------------
signal axi_full_sm_ps : STATE_TYPE;
signal axi_full_sm_ns : STATE_TYPE;
-- function declaration
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
-- code coverage -- function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
-- code coverage -- variable i : integer := 0;
-- code coverage -- begin
-- code coverage -- for i in 31 downto 0 loop
-- code coverage -- if y(i)='1' then
-- code coverage -- return (i);
-- code coverage -- end if;
-- code coverage -- end loop;
-- code coverage -- return -1;
-- code coverage -- end function Get_Addr_Bits;
-- constant declaration
constant C_ADDR_DECODE_BITS : integer := 6; -- Get_Addr_Bits(C_S_AXI_SPI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector(31 downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-- type decode_bit_array_type is Array(natural range 0 to (
-- (C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
-- integer;
-- type short_addr_array_type is Array(natural range 0 to
-- C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
-- std_logic_vector(0 to(C_ADDR_DECODE_BITS-1));
-- signal declaration
signal axi_size_reg : std_logic_vector(2 downto 0);
signal axi_size_cmb : std_logic_vector(2 downto 0);
signal bus2ip_rnw_i : std_logic;
signal bus2ip_addr_i : std_logic_vector(31 downto 0); -- (31 downto 0); -- 8/18/2013
signal wr_transaction : std_logic;
signal wr_addr_transaction : std_logic;
signal arready_i : std_logic;
signal awready_i, s_axi_wready_i : std_logic;
signal S_AXI4_RID_reg : std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
signal S_AXI4_BID_reg : std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
signal s_axi_mem_bresp_reg : std_logic_vector(2 downto 0);
signal axi_full_sm_ps_IDLE_cmb : std_logic;
signal s_axi_mem_bvalid_reg : std_logic;
signal bus2ip_BE_reg : std_logic_vector(((C_S_AXI4_DATA_WIDTH/8) - 1) downto 0);
signal axi_length_cmb : std_logic_vector(7 downto 0);
signal axi_length_reg : std_logic_vector(7 downto 0);
signal burst_transfer_cmb : std_logic;
signal burst_transfer_reg : std_logic;
signal axi_burst_cmb : std_logic_vector(1 downto 0);
signal axi_burst_reg : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(7 downto 0);
signal last_data_cmb : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal pr_state_idle : std_logic;
signal length_error : std_logic;
signal rnw_reg, rnw_cmb : std_logic;
signal arready_cmb : std_logic;
signal awready_cmb : std_logic;
signal wready_cmb : std_logic;
signal store_axi_signal_cmb : std_logic;
signal combine_ack, start, temp_i, response : std_logic;
signal s_axi4_rdata_i : std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
signal s_axi4_rresp_i : std_logic_vector(1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal S_AXI4_BRESP_i : std_logic_vector(1 downto 0);
signal s_axi_bvalid_i : std_logic;
signal pr_state_length_chk : std_logic;
signal axi_full_sm_ns_IDLE_cmb : std_logic;
signal last_data_reg: std_logic;
signal rst_en : std_logic;
signal s_axi_rvalid_cmb, last_data, burst_tr_i,rready_i, store_data : std_logic;
signal Bus2IP_Reset_i : std_logic;
-----
begin
-----
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
-- REGISTERING_RESET_P: Invert the reset coming from AXI4
-----------------------
REGISTERING_RESET_P : process (S_AXI4_ACLK) is
-----
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
Bus2IP_Reset_i <= not S_AXI4_ARESETN;
end if;
end process REGISTERING_RESET_P;
Bus2IP_Reset <= Bus2IP_Reset_i;
Bus2IP_Clk <= S_AXI4_ACLK;
--Bus2IP_Resetn <= S_AXI4_ARESETN;
--bus2ip_rnw_i <= rnw_reg;-- '1' when S_AXI4_ARVALID='1' else '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_Data <= S_AXI4_WDATA;
--Bus2IP_Addr <= bus2ip_addr_i;
wr_transaction <= S_AXI4_AWVALID and (S_AXI4_WVALID);
bus2ip_addr_i <= ZEROS & S_AXI4_ARADDR(C_ADDR_DECODE_BITS downto 0) when (S_AXI4_ARVALID='1')
else
ZEROS & S_AXI4_AWADDR(C_ADDR_DECODE_BITS downto 0);
--S_AXI4_ARADDR(C_ADDR_DECODE_BITS+1 downto 0) when (S_AXI4_ARVALID='1')
--else
--S_AXI4_AWADDR(C_ADDR_DECODE_BITS+1 downto 0);
-- read and write transactions should be separate
-- preferencec of read over write
-- only narrow transfer of 8-bit are supported
-- for 16-bit and 32-bit transactions error should be generated - dont provide these signals to internal logic
--wr_transaction <= S_AXI4_AWVALID and (S_AXI4_WVALID);
--wr_addr_transaction <= S_AXI4_AWVALID and (not S_AXI4_WVALID);
-------------------------------------------------------------------------------
AXI_ARREADY_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
arready_i <='0';
else
arready_i <= arready_cmb;
end if;
end if;
end process AXI_ARREADY_P;
--------------------------
S_AXI4_ARREADY <= arready_i; -- arready_i;--IP2Bus_RdAck; --arready_i;
--------------------------
AXI_AWREADY_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
awready_i <='0';
else
awready_i <= awready_cmb;
end if;
end if;
end process AXI_AWREADY_P;
--------------------------
S_AXI4_AWREADY <= awready_i;
--------------------------
S_AXI4_BRESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (axi_full_sm_ps = IDLE) then
S_AXI4_BRESP_i <= (others => '0');
elsif (axi_full_sm_ps = AXI_WR) or (axi_full_sm_ps = AXI_SINGLE_WR) then
S_AXI4_BRESP_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI4_BRESP_P;
---------------------------
S_AXI4_BRESP <= S_AXI4_BRESP_i;
-------------------------------
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if S_AXI4_ARESETN = '0' then
s_axi_bvalid_i <= '0';
elsif(axi_full_sm_ps = WR_RESP_1)then
s_axi_bvalid_i <= '1';
elsif(S_AXI4_BREADY = '1')then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------
S_AXI4_BVALID <= s_axi_bvalid_i;
--------------------------------
----S_AXI_WREADY_I_P: below process provides logic for valid write response signal
---------------------
S_AXI_WREADY_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if S_AXI4_ARESETN = '0' then
s_axi_wready_i <= '0';
else
s_axi_wready_i <= wready_cmb;
end if;
end if;
end process S_AXI_WREADY_I_P;
-------------------------------
S_AXI4_WREADY <= s_axi_wready_i;
--------------------------------
-------------------------------------------------------------------------------
-- REG_BID_P,REG_RID_P: Below process makes the RID and BID '0' at POR and
-- : generate proper values based upon read/write
-- transaction
-----------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESETN = '0') then
S_AXI4_RID_reg <= (others=> '0');
elsif(store_axi_signal_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_RID_reg;
-----------------------------
REG_BID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
S_AXI4_BID_reg <= (others=> '0');
elsif(store_axi_signal_cmb = '1')then
S_AXI4_BID_reg <= S_AXI4_AWID;-- and pr_state_length_chk;
end if;
end if;
end process REG_BID_P;
-----------------------
S_AXI4_BID <= S_AXI4_BID_reg;
------------------------------
------------------------
-- BUS2IP_BE_P:Register Bus2IP_BE for write strobe during write mode else '1'.
------------------------
BUS2IP_BE_P: process (S_AXI4_ACLK) is
------------
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if ((Bus2IP_Reset_i = RESET_ACTIVE)) then
bus2ip_BE_reg <= (others => '0');
else
if (rnw_cmb = '0'-- and
--(wready_cmb = '1')
) then
bus2ip_BE_reg <= S_AXI4_WSTRB;
else -- if(rnw_cmb = '1') then
bus2ip_BE_reg <= (others => '1');
end if;
end if;
end if;
end process BUS2IP_BE_P;
------------------------
Bus2IP_BE <= bus2ip_BE_reg;
axi_length_cmb <= S_AXI4_ARLEN when (rnw_cmb = '1')
else
S_AXI4_AWLEN;
burst_transfer_cmb <= (or_reduce(axi_length_cmb));
BURST_LENGTH_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
axi_length_reg <= (others => '0');
burst_transfer_reg <= '0';
elsif((store_axi_signal_cmb = '1'))then
axi_length_reg <= axi_length_cmb;
burst_transfer_reg <= burst_transfer_cmb;
end if;
end if;
end process BURST_LENGTH_REG_P;
-----------------------
burst_tr_i <= burst_transfer_reg;
burst_tr <= burst_tr_i;
-------------------------------------------------------------------------------
axi_size_cmb <= S_AXI4_ARSIZE(2 downto 0) when (rnw_cmb = '1')
else
S_AXI4_AWSIZE(2 downto 0);
SIZE_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
axi_size_reg <= (others => '0');
elsif((store_axi_signal_cmb = '1'))then
axi_size_reg <= axi_size_cmb;
end if;
end if;
end process SIZE_REG_P;
-----------------------
axi_burst_cmb <= S_AXI4_ARBURST when (rnw_cmb = '1')
else
S_AXI4_AWBURST;
BURST_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN = ACTIVE_LOW_RESET) then
axi_burst_reg <= (others => '0');
elsif(store_axi_signal_cmb = '1')then
axi_burst_reg <= axi_burst_cmb;
end if;
end if;
end process BURST_REG_P;
-----------------------
combine_ack <= IP2Bus_WrAck or IP2Bus_RdAck;
--------------------------------------------
LENGTH_CNTR_P:process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN = ACTIVE_LOW_RESET) then
length_cntr <= (others => '0');
elsif((store_axi_signal_cmb = '1'))then
length_cntr <= axi_length_cmb;
elsif (wready_cmb = '1' and S_AXI4_WVALID = '1') or
(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then -- burst length error
length_cntr <= length_cntr - '1';
end if;
end if;
end process LENGTH_CNTR_P;
--------------------------
--last_data_cmb <= or_reduce(length_cntr(7 downto 1)) and length_cntr(1);
rready <= rready_i;
last_bt_one_data_cmb <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0) and S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(length_cntr(7 downto 0)));
--temp_i <= (combine_ack and last_data_reg)or rst_en;
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(axi_full_sm_ps_IDLE_cmb = '1') then
last_data_acked <= '0';
elsif(burst_tr_i = '0')then
if(S_AXI4_RREADY = '1' and last_data_acked = '1')then
last_data_acked <= '0';
else
last_data_acked <= last_data_cmb and s_axi_rvalid_cmb;
end if;
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then
last_data_acked <= '1';
else
last_data_acked <= last_data and s_axi_rvalid_i and S_AXI4_RREADY;
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= last_data_acked;
--------------------------------
-- S_AXI4_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESETN = '0') then
S_AXI4_RRESP_i <= (others => '0');
S_AXI4_RDATA_i <= (others => '0');
elsif(S_AXI4_RREADY = '1' )or(store_data = '1') then --if --((axi_full_sm_ps = AXI_SINGLE_RD) or (axi_full_sm_ps = AXI_BURST_RD)) then
S_AXI4_RRESP_i <= (IP2Bus_Error) & '0';
S_AXI4_RDATA_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
S_AXI4_RRESP <= S_AXI4_RRESP_i;
S_AXI4_RDATA <= S_AXI4_RDATA_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (axi_full_sm_ps = IDLE) then
s_axi_rvalid_i <= '0';
elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
s_axi_rvalid_i <= s_axi_rvalid_i;
else
s_axi_rvalid_i <= s_axi_rvalid_cmb;
end if;
end if;
end process S_AXI_RVALID_I_P;
-----------------------------
S_AXI4_RVALID <= s_axi_rvalid_i;
-- -----------------------------
-- Addr_int <= S_AXI_ARADDR when(rnw_cmb_dup = '1')
-- else
-- S_AXI_AWADDR;
axi_full_sm_ns_IDLE_cmb <= '1' when (axi_full_sm_ns = IDLE) else '0';
axi_full_sm_ps_IDLE_cmb <= '1' when (axi_full_sm_ps = IDLE) else '0';
pr_state_idle <= '1' when axi_full_sm_ps = IDLE else '0';
pr_state_length_chk <= '1' when axi_full_sm_ps = CHECK_AXI_LENGTH_ERROR
else
'0';
REGISTER_LOWER_ADDR_BITS_P:process(S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (axi_full_sm_ps_IDLE_cmb = '1') then
length_error <= '0';
elsif(burst_transfer_cmb = '1')then -- means its a burst
--if (bus2ip_addr_i (7 downto 3) = "01101")then
if (bus2ip_addr_i (6 downto 3) = "1101")then
length_error <= '0';
else
length_error <= '1';
end if;
end if;
end if;
end process REGISTER_LOWER_ADDR_BITS_P;
---------------------------------------
-- length_error <= '0';
---------------------------
REG_P: process (S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
axi_full_sm_ps <= IDLE;
last_data_reg <= '0';
else
axi_full_sm_ps <= axi_full_sm_ns;
last_data_reg <= last_data_cmb;
end if;
end if;
end process REG_P;
-------------------------------------------------------
STORE_SIGNALS_P: process (S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
rnw_reg <= '0';
else-- if(store_axi_signal_cmb = '1')then
rnw_reg <= rnw_cmb;
end if;
end if;
end process STORE_SIGNALS_P;
-------------------------------------------------------
AXI_FULL_STATE_MACHINE_P:process(
axi_full_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_AWVALID ,
S_AXI4_WVALID ,
S_AXI4_BREADY ,
S_AXI4_RREADY ,
wr_transaction ,
wr_addr_transaction ,
length_error ,
IP2Bus_WrAck ,
last_data_cmb ,
IP2Bus_RdAck ,
IP2Bus_Error ,
burst_transfer_cmb ,
last_bt_one_data_cmb ,
rnw_reg ,
length_cntr
)is
-----
begin
-----
arready_cmb <= '0';
awready_cmb <= '0';
wready_cmb <= '0';
start <= '0';
rst_en <= '0';
temp_i <= '0';
store_axi_signal_cmb <= '0';
s_axi_rvalid_cmb <= '0';
rready_i <= '0';
rnw_cmb <= '0';
last_data <= '0';
store_data <= '0';
case axi_full_sm_ps is
when IDLE => if(S_AXI4_ARVALID = '1') then
start <= '1';
store_axi_signal_cmb <= '1';
arready_cmb <= '1';
if(burst_transfer_cmb = '1') then
axi_full_sm_ns <= AXI_RD;
else
axi_full_sm_ns <= AXI_SINGLE_RD;
end if;
elsif(wr_transaction = '1')then
start <= '1';
store_axi_signal_cmb <= '1';
if(burst_transfer_cmb = '1') then
awready_cmb <= '1';
wready_cmb <= '1';
axi_full_sm_ns <= AXI_WR;
else
axi_full_sm_ns <= AXI_SINGLE_WR;
end if;
else
axi_full_sm_ns <= IDLE;
end if;
rnw_cmb <= S_AXI4_ARVALID and (not S_AXI4_AWVALID);
------------------------------
when CHECK_AXI_LENGTH_ERROR => if (length_error = '0') then
if(rnw_reg = '1')then
arready_cmb <= '1';
axi_full_sm_ns <= AXI_RD;
else
awready_cmb <= '1';
axi_full_sm_ns <= AXI_WR;
end if;
start <= '1';
else
axi_full_sm_ns <= ERROR_RESP;
end if;
---------------------------------------------------------
when AXI_SINGLE_RD => --arready_cmb <= IP2Bus_RdAck;
s_axi_rvalid_cmb <= IP2Bus_RdAck or IP2Bus_Error;
temp_i <= IP2Bus_RdAck or IP2Bus_Error;
rready_i <= '1';
if(IP2Bus_RdAck = '1')or (IP2Bus_Error = '1') then
store_data <= not S_AXI4_RREADY;
axi_full_sm_ns <= RD_LAST;
else
axi_full_sm_ns <= AXI_SINGLE_RD;
end if;
rnw_cmb <= rnw_reg;
when AXI_RD =>
rready_i <= S_AXI4_RREADY and not last_data_cmb;
last_data <= last_bt_one_data_cmb;
if(last_data_cmb = '1') then
if(S_AXI4_RREADY = '1')then
temp_i <= '1';--IP2Bus_RdAck;--IP2Bus_WrAck;
rst_en <= '1';--IP2Bus_RdAck;--IP2Bus_WrAck;
axi_full_sm_ns <= IDLE;
else
s_axi_rvalid_cmb <= not S_AXI4_RREADY;
last_data <= not S_AXI4_RREADY;
temp_i <= '1';
axi_full_sm_ns <= RD_LAST;
end if;
else
s_axi_rvalid_cmb <= IP2Bus_RdAck or IP2Bus_Error; -- not last_data_cmb;
axi_full_sm_ns <= AXI_RD;
end if;
rnw_cmb <= rnw_reg;
----------------------------------------------------------
when AXI_SINGLE_WR => awready_cmb <= IP2Bus_WrAck or IP2Bus_Error;
wready_cmb <= IP2Bus_WrAck or IP2Bus_Error;
temp_i <= IP2Bus_WrAck or IP2Bus_Error;
if(IP2Bus_WrAck = '1')or (IP2Bus_Error = '1')then
axi_full_sm_ns <= WR_RESP_1;
else
axi_full_sm_ns <= AXI_SINGLE_WR;
end if;
rnw_cmb <= rnw_reg;
when AXI_WR => --if(IP2Bus_WrAck = '1')then
wready_cmb <= '1';--IP2Bus_WrAck;
if(last_data_cmb = '1') then
wready_cmb <= '0';
temp_i <= '1';--IP2Bus_WrAck;
rst_en <= '1';--IP2Bus_WrAck;
axi_full_sm_ns <= WR_RESP_1;
else
axi_full_sm_ns <= AXI_WR;
end if;
rnw_cmb <= rnw_reg;
-----------------------------------------------------------
when WR_RESP_1 => --if(S_AXI4_BREADY = '1') then
-- axi_full_sm_ns <= IDLE;
--else
axi_full_sm_ns <= WR_RESP_2;
-- end if;
-----------------------------------------------------------
when WR_RESP_2 => if(S_AXI4_BREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= WR_RESP_2;
end if;
-----------------------------------------------------------
when RD_LAST => if(S_AXI4_RREADY = '1') then -- and (TX_FIFO_Empty = '1') then
last_data <= not S_AXI4_RREADY;
axi_full_sm_ns <= IDLE;
else
last_data <= not S_AXI4_RREADY;
s_axi_rvalid_cmb <= not S_AXI4_RREADY;
axi_full_sm_ns <= RD_LAST;
temp_i <= '1';
end if;
-----------------------------------------------------------
when RD_RESP_2 => if(S_AXI4_RREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= RD_RESP_2;
end if;
-----------------------------------------------------------
when ERROR_RESP => if(length_cntr = "00000000") and
(S_AXI4_BREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= ERROR_RESP;
end if;
response <= '1';
when others => axi_full_sm_ns <= IDLE;
end case;
end process AXI_FULL_STATE_MACHINE_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
I_DECODER : entity axi_quad_spi_v3_2_8.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK,
Bus_rst => S_AXI4_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0), -- (C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI4_ARVALID,
Bus_RNW_Erly => S_AXI4_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
end architecture imp;
------------------------------------------------------------------------------
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_gpio_v2_0/hdl/src/vhdl/gpio_core.vhd | 8 | 35419 | -------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_gpio_v2_0/hdl/src/vhdl/gpio_core.vhd | 8 | 35419 | -------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/Partial_Designs/Source/Invert.vhd | 1 | 4258 | ----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 01/30/2017 10:24:00 AM
-- Design Name: Invert Filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter inverts the image passing through the filter. This is
-- done by taking the make RGB value and subtracting the actual from
-- the max, creating the inverse of the RGB value.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin Invert Architecture Design
architecture Behavioral of Video_Box is
--Complete RGB value
signal full_const : unsigned(7 downto 0):= "11111111";
--Inverted signals for the red, green, and blue values
signal red_i,green_i,blue_i : unsigned(7 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
begin
--Take the max value and subtract away the RGB values to invert the image
red_i <= full_const - unsigned(RGB_IN_reg(23 downto 16));
green_i <= full_const - unsigned(RGB_IN_reg(15 downto 8));
blue_i <= full_const - unsigned(RGB_IN_reg(7 downto 0));
--Concatenate the inverted Red, Green, and Blue values together
--Route the inverted RGB values out
USER_LOGIC <= std_logic_vector(red_i&green_i&blue_i);
--Pass all the other signals through the region
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
end Behavioral;
--End Invert Architecture Design | bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_scc.vhd | 18 | 47911 | -------------------------------------------------------------------------------
-- axi_datamover_scc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4
-- Sets the width of the Tag field in the input command
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_scc;
architecture implementation of axi_datamover_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when 16 =>
temp_slice_width := 5;
when 8 =>
temp_slice_width := 4;
when 4 =>
temp_slice_width := 3;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 2;
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
when 64 =>
temp_btt_ls_unused := 3;
when 32 =>
temp_btt_ls_unused := 2;
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_input_eof_reg : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= sig_input_eof_reg; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty and
sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_input_eof_reg <= '0';
sig_cmd_burst_reg <= "00";
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
if (C_MICRO_DMA = 1) then
sig_input_eof_reg <= cmd2mstr_command(CMD_EOF_INDEX);
else
sig_input_eof_reg <= '1';
end if;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SCC_SM_COMB
--
-- Process Description:
-- Implements combinational portion of state machine
--
-------------------------------------------------------------
SCC_SM_COMB : process (sm_scc_state,
cmd2mstr_cmd_valid,
sig_addr_data_rdy_pending,
sig_cmd_reg_full,
sig_btt_is_zero_reg
)
begin
-- Set default State machine outputs
sm_pop_input_cmd_ns <= '0';
sm_set_push2axi_ns <= '0';
sm_scc_state_ns <= sm_scc_state;
sm_set_error_ns <= '0';
sm_scc_sm_ready_ns <= '1';
case sm_scc_state is
----------------------------------------------------
when INIT =>
-- if (sig_addr_data_rdy4cmd = '1') then
if (cmd2mstr_cmd_valid = '1') then -- wait for first cmd valid after reset
sm_scc_state_ns <= GET_NXT_CMD; -- jump to get command
else
sm_scc_sm_ready_ns <= '0';
sm_scc_state_ns <= INIT; -- Stay in Init
End if;
----------------------------------------------------
when POP_RECOVER =>
sm_scc_state_ns <= GET_NXT_CMD; -- jump to next state
----------------------------------------------------
when GET_NXT_CMD =>
if (sig_cmd_reg_full = '1') then
sm_scc_state_ns <= CHK_AND_CALC; -- jump to next state
else
sm_scc_state_ns <= GET_NXT_CMD; -- stay in this state
end if;
----------------------------------------------------
when CHK_AND_CALC =>
sm_set_push2axi_ns <= '1'; -- Push the command to ADDR and DATA
if (sig_btt_is_zero_reg = '1') then
sm_scc_state_ns <= ERROR_TRAP; -- jump to error trap
sm_set_error_ns <= '1'; -- Set internal error flag
else
sm_scc_state_ns <= PUSH_TO_AXI;
end if;
----------------------------------------------------
when PUSH_TO_AXI =>
if (sig_addr_data_rdy_pending = '1') then
sm_scc_state_ns <= PUSH_TO_AXI; -- stay in this state
-- until both Addr and Data have taken commands
else
sm_pop_input_cmd_ns <= '1';
sm_scc_state_ns <= POP_RECOVER; -- jump back to fetch new cmd input
end if;
----------------------------------------------------
when ERROR_TRAP =>
sm_scc_state_ns <= ERROR_TRAP; -- stay in this state
sm_set_error_ns <= '1';
----------------------------------------------------
when others =>
sm_scc_state_ns <= INIT; -- error so always jump to init state
end case;
end process SCC_SM_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sm_scc_state <= INIT;
sm_pop_input_cmd <= '0' ;
sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
sm_scc_sm_ready <= '0' ;
else
sm_scc_state <= sm_scc_state_ns ;
sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= sm_set_error_ns ;
sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
end if;
end if;
end process SCC_SM_REG;
end implementation;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/Partial_Designs/Source/sobel_filter/pixel_buffer.vhd | 1 | 4592 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/14/2017 03:01:40 PM
-- Design Name:
-- Module Name: pixel_buffer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library work;
use work.filter_lib.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pixel_buffer is
generic (
WIDTH : natural := 3;
HEIGHT : natural := 3;
LINE_LENGTH : natural := 2048
);
port (
-- Clock
CLK : in std_logic;
-- Inputs
data_in : in pixel_t;
vde_in : in std_logic; -- Active video Flag (optional)
hs_in : in std_logic; -- Horizontal sync signal (optional)
vs_in : in std_logic; -- Veritcal sync signal (optional)
-- Outputs
data_out : out pixel2d_t(WIDTH - 1 downto 0, HEIGHT - 1 downto 0);
vde_out : out std_logic; -- Active video Flag (optional)
hs_out : out std_logic; -- Horizontal sync signal (optional)
vs_out : out std_logic -- Veritcal sync signal (optional)
);
end pixel_buffer;
architecture Behavioral of pixel_buffer is
signal to_window : pixel_t;
-- Indeces for the line buffers
signal line_buffer_index, line_buffer_index_next : unsigned(log2ceil(LINE_LENGTH) - 1 downto 0);
-- Window of pixels to be sent out
signal window_reg, window_next : pixel2d_t(WIDTH - 1 downto 0, HEIGHT - 1 downto 0);
-- Used to control shifting in the linebuffer
signal new_line, vde_prev, shift : std_logic;
begin
-- To guarantee zero padding
to_window <= data_in when vde_in = '1' else
(others=>'0');
-- Control logic for shifting stuff
shift <= vde_in;
-- Falling-edge detector for the vde signal
process(CLK)
begin
if (rising_edge(CLK)) then
vde_prev <= vde_in;
end if;
end process;
new_line <= '1' when (vde_prev = '1') and (vde_in = '0') else '0';
-- Counter for line_buffer_index
process(CLK)
begin
if (rising_edge(CLK)) then
line_buffer_index <= line_buffer_index_next;
window_reg <= window_next;
end if;
end process;
-- Increment when shift is asserted, zero otherwise
line_buffer_index_next <= (others=>'0') when (new_line = '1') else
(line_buffer_index + 1) when (shift = '1') else
line_buffer_index;
-- LINEBUFFERS and WINDOW
-- Generate linebuffers, and do reads/writes to the window
if_linebuffers:
if (HEIGHT > 1) generate -- Verify if this is necessary or not
for_linebuffers:
for row in 1 to HEIGHT - 1 generate
line_x : entity work.line_buffer(inferred)
generic map (
LENGTH => 2048
)
port map (
CLK => CLK,
en => shift,
index => std_logic_vector(line_buffer_index),
d_in => window_next(0, row - 1),
d_out => window_next(0, row)
);
end generate;
end generate;
-- Shift pixels around in the window
window_next(0,0) <= to_window when (shift = '1') else
window_reg(0, 0);
rows:
for row in 0 to (HEIGHT - 1) generate
columns:
for column in 0 to (WIDTH - 1) generate
-- If not last column
not_last_col:
if column < (WIDTH - 1) generate
-- Feed each pixel to the next reg in the row
window_next(column + 1, row) <= window_reg(column, row) when (shift = '1') else
window_reg(column + 1, row);
end generate; -- if not last col
end generate; -- for cols
end generate; -- for rows
-- Outputs
data_out <= window_reg;
-- TODO: Delay these by an appropriate amount
vde_out <= vde_in;
hs_out <= hs_in;
vs_out <= vs_in;
end Behavioral;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_sg_v4_1_2/hdl/src/vhdl/axi_sg_ftch_q_mngr.vhd | 7 | 49985 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
--
-- Channel 1 Control --
ch1_desc_flush : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_ftch_active : in std_logic ; --
ch1_nxtdesc_wren : out std_logic ; --
ch1_ftch_queue_empty : out std_logic ; --
ch1_ftch_queue_full : out std_logic ; --
ch1_ftch_pause : out std_logic ; --
--
-- Channel 2 Control --
ch2_desc_flush : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_ftch_active : in std_logic ; --
ch2_nxtdesc_wren : out std_logic ; --
ch2_ftch_queue_empty : out std_logic ; --
ch2_ftch_queue_full : out std_logic ; --
ch2_ftch_pause : out std_logic ; --
nxtdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : out std_logic ; --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tkeep : in std_logic_vector --
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ;
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Determine the maximum word count for use in setting the word counter width
-- Set bit width on max num words to fetch
constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH
,C_SG_CH2_WORDS_TO_FETCH);
-- LOG2 to get width of counter
constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT);
-- Zero value for counter
constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= (others => '0');
-- One value for counter
constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH));
-- Seven value for counter
constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH));
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_mm2s_tready_i : std_logic := '0';
signal ch1_ftch_tready : std_logic := '0';
signal ch2_ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal fetch_word_count : std_logic_vector
(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0');
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal lsbnxtdesc_tready : std_logic := '0';
signal msbnxtdesc_tready : std_logic := '0';
signal nxtdesc_tready : std_logic := '0';
signal ch1_writing_curdesc : std_logic := '0';
signal ch2_writing_curdesc : std_logic := '0';
signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0';
-- KAPIL
signal ch_desc_flush : std_logic := '0';
signal m_axis_ch_ftch_tready : std_logic := '0';
signal ch_ftch_queue_empty : std_logic := '0';
signal ch_ftch_queue_full : std_logic := '0';
signal ch_ftch_pause : std_logic := '0';
signal ch_writing_curdesc : std_logic := '0';
signal ch_ftch_tready : std_logic := '0';
signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch_ftch_tvalid : std_logic := '0';
signal m_axis_ch_ftch_tlast : std_logic := '0';
signal data_concat : std_logic_vector (95 downto 0) := (others => '0');
signal data_concat_64 : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_64_cdma : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0');
signal next_bd : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_valid, tvalid_new : std_logic;
signal data_concat_tlast, tlast_new : std_logic;
signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0);
signal sof_ftch_desc : std_logic;
signal nxtdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal cyclic_enable : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else
ch2_cyclic;
nxtdesc <= nxtdesc_int;
TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate
-- TLAST is generated when 8th beat is received
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
SOF_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then
sof_ftch_desc <= '0';
elsif(counter (6) = '1'
and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tvalid = '1'
and m_axis_mm2s_tdata(27) = '1' )then
sof_ftch_desc <= '1';
end if;
end if;
end process SOF_CHECK;
end generate TLAST_GEN;
NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate
sof_ftch_desc <= '0';
CDMA : if C_ENABLE_CDMA = 1 generate
-- For CDMA TLAST is generated when 7th beat is received
-- because last one is not needed
tlast_new <= counter (6) and m_axis_mm2s_tvalid;
tvalid_new <=counter (6) and m_axis_mm2s_tvalid;
end generate CDMA;
NOCDMA : if C_ENABLE_CDMA = 0 generate
-- For DMA tlast is generated with 8th beat
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
end generate NOCDMA;
end generate NOTLAST_GEN;
-- Following shift register keeps track of number of data beats
-- of BD that is being read
DATA_BEAT_REG : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then
counter (0) <= '1';
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0');
Elsif (m_axis_mm2s_tvalid = '1') then
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0);
counter (0) <= '0';
end if;
end if;
end process DATA_BEAT_REG;
-- Registering the Buffer address from BD, 3rd beat
-- Common for DMA, CDMA
DATA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (31 downto 0) <= (others => '0');
Elsif (counter (2) = '1') then
data_concat (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1;
ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (31 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1_64;
end generate ADDR_64BIT;
ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG1_64;
data_concat_64 (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate ADDR_64BIT2;
DMA_REG2 : if C_ENABLE_CDMA = 0 generate
begin
-- For DMA, the 7th beat has the control information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (6) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
end generate DMA_REG2;
CDMA_REG2 : if C_ENABLE_CDMA = 1 generate
begin
-- For CDMA, the 5th beat has the DA information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
CDMA_ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (31 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2_64;
end generate CDMA_ADDR_64BIT;
CDMA_ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG2_64;
data_concat_64_cdma (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate CDMA_ADDR_64BIT2;
end generate CDMA_REG2;
NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate
begin
-- Last beat is directly concatenated and passed to FIFO
-- Masking the CMPLT bit with cyclic_enable
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end generate NOFLOP_FOR_QUEUE;
-- In absence of queuing option the last beat needs to be floped
FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate
begin
NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95 downto 64) <= (others => '0');
Elsif (counter (7) = '1') then
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
end if;
end if;
end process DATA_REG3;
end generate NO_FETCH_Q;
FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95) <= '0';
Elsif (counter (7) = '1') then
data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable);
end if;
end if;
end process DATA_REG3;
data_concat (94 downto 64) <= (others => '0');
end generate FETCH_Q;
DATA_CNTRL : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_valid <= '0';
data_concat_tlast <= '0';
Else
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end if;
end if;
end process DATA_CNTRL;
end generate FLOP_FOR_NOQUEUE;
-- Since the McDMA BD has two more fields to be captured
-- following procedures are needed
NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
data_concat_mcdma <= (others => '0');
end generate NOMCDMA_FTECH;
MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
DATA_MCDMA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (31 downto 0) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG1;
DATA_MCDMA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (63 downto 32) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG2;
end generate MCDMA_BD_FETCH;
---------------------------------------------------------------------------
-- For 32-bit SG addresses then drive zero on msb
---------------------------------------------------------------------------
GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
msb_curdesc <= (others => '0');
end generate GEN_CURDESC_32;
---------------------------------------------------------------------------
-- For 64-bit SG addresses then capture upper order adder to msb
---------------------------------------------------------------------------
GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CAPTURE_CURADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
msb_curdesc <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ C_M_AXI_SG_ADDR_WIDTH
downto DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT + 1);
end if;
end if;
end process CAPTURE_CURADDR;
end generate GEN_CURDESC_64;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(31 downto 0) <= (others => '0');
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then
nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6);
-- BD addresses are always 16 word 32-bit aligned
nxtdesc_int(5 downto 0) <= (others => '0');
end if;
end if;
end process REG_LSB_NXTPNTR;
lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (0) = '1' --etch_word_count = WORD_ZERO
else '0';
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_NXTDESC : if C_ACTUAL_ADDR = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(63 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata;
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC;
GEN_UPPER_MSB_NXTDESC2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
nxtdesc_int (63 downto C_ACTUAL_ADDR) <= (others => '0');
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC2;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Throw away second word but drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_NO_UPR_MSB_NXTDESC;
-- Drive ready to DataMover for ether lsb or msb capture
nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready;
-- Generate logic for checking stale descriptor
GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
---------------------------------------------------------------------------
-- Examine Completed BIT to determine if stale descriptor fetched
---------------------------------------------------------------------------
CMPLTD_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ftch_stale_desc <= '0';
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN
and m_axis_mm2s_tready_i = '1'
and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then
ftch_stale_desc <= '1' and (not cyclic_enable);
else
ftch_stale_desc <= '0';
end if;
end if;
end process CMPLTD_CHECK;
end generate GEN_STALE_DESC_CHECK;
-- No needed logic for checking stale descriptor
GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ftch_stale_desc <= '0';
end generate GEN_NO_STALE_CHECK;
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_sg_v4_1_2.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_INCLUDE_MM2S => C_INCLUDE_CH1,
C_INCLUDE_S2MM => C_INCLUDE_CH2,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => '0' ,
-- Channel Control
desc1_flush => ch1_desc_flush ,
desc2_flush => ch2_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch1_active => ch1_ftch_active ,
ftch2_active => ch2_ftch_active ,
ftch1_queue_empty => ch1_ftch_queue_empty ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch1_queue_full => ch1_ftch_queue_full ,
ftch2_queue_full => ch2_ftch_queue_full ,
ftch1_pause => ch1_ftch_pause ,
ftch2_pause => ch2_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing1_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat_64_cdma => data_concat_64_cdma,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
m_axis1_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk ,
m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch1_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch2_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0');
end generate GEN_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_sg_v4_1_2.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_CH1 => C_INCLUDE_CH1
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
desc2_flush => ch2_desc_flush ,
ftch2_active => ch2_ftch_active ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch2_queue_full => ch2_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch_desc_available => m_axis_ftch1_desc_available ,
m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis2_ftch_desc_available => m_axis_ftch2_desc_available ,
m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
ch1_ftch_pause <= '0';
ch2_ftch_pause <= '0';
end generate GEN_NO_QUEUE;
-------------------------------------------------------------------------------
-- DataMover TREADY MUX
-------------------------------------------------------------------------------
writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr;
TREADY_MUX : process(writing_curdesc,
fetch_word_count,
nxtdesc_tready,
-- channel 1 signals
ch1_ftch_active,
ch1_desc_flush,
ch1_ftch_tready,
-- channel 2 signals
ch2_ftch_active,
ch2_desc_flush,
counter(0),
counter(1),
ch2_ftch_tready)
begin
-- If commmanded to flush descriptor then assert ready
-- to datamover until active de-asserts. this allows
-- any commanded fetches to complete.
if( (ch1_desc_flush = '1' and ch1_ftch_active = '1')
or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then
m_axis_mm2s_tready_i <= '1';
-- NOT ready if cmnd being written because
-- curdesc gets written to queue
elsif(writing_curdesc = '1')then
m_axis_mm2s_tready_i <= '0';
-- First two words drive ready from internal logic
elsif(counter(0) = '1' or counter(1)='1')then
m_axis_mm2s_tready_i <= nxtdesc_tready;
-- Remainder stream words drive ready from channel input
else
m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready)
or (ch2_ftch_active and ch2_ftch_tready);
end if;
end process TREADY_MUX;
m_axis_mm2s_tready <= m_axis_mm2s_tready_i;
end implementation;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/rgb2dvi/src/SyncAsync.vhd | 34 | 3727 | -------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_skid_buf.vhd | 12 | 16812 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/address_decoder.vhd | 4 | 22452 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_4.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_4.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd | 4 | 33322 | -------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_11 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_11 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_4;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_11 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_11;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_11.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_sg_v4_1_2/hdl/src/vhdl/axi_sg_sfifo_autord.vhd | 7 | 20294 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_mm2s_basic_wrap.vhd | 4 | 44262 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_reset;
use axi_datamover_v5_1_9.axi_datamover_cmd_status;
use axi_datamover_v5_1_9.axi_datamover_scc;
use axi_datamover_v5_1_9.axi_datamover_addr_cntl;
use axi_datamover_v5_1_9.axi_datamover_rddata_cntl;
use axi_datamover_v5_1_9.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1_9.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32));
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_9.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_9.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1_9.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_9.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_9.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1_9.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/slave_attachment.vhd | 4 | 24073 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_4.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
| bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_input_buffer/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd | 15 | 465879 | -------------------------------------------------------------------------------
--
-- FIFO Generator - VHDL Behavioral Model
--
-------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Filename: fifo_generator_vhdl_beh.vhd
--
-- Author : Xilinx
--
-------------------------------------------------------------------------------
-- Structure:
--
-- fifo_generator_vhdl_beh.vhd
-- |
-- +-fifo_generator_v13_0_1_conv
-- |
-- +-fifo_generator_v13_0_1_bhv_as
-- |
-- +-fifo_generator_v13_0_1_bhv_ss
-- |
-- +-fifo_generator_v13_0_1_bhv_preload0
--
-------------------------------------------------------------------------------
-- Description:
--
-- The VHDL behavioral model for the FIFO Generator.
--
-- The behavioral model has three parts:
-- - The behavioral model for independent clocks FIFOs (_as)
-- - The behavioral model for common clock FIFOs (_ss)
-- - The "preload logic" block which implements First-word Fall-through
--
-------------------------------------------------------------------------------
--#############################################################################
--#############################################################################
-- Independent Clocks FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
-- Independent Clocks Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_bhv_as IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2
);
PORT(
---------------------------------------------------------------------------
-- Input and Output Declarations
---------------------------------------------------------------------------
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VALID : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_bhv_as;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_as IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH - 1;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION div_roundup
-- Returns data_value / divisor, with the result rounded-up (if fractional)
-------------------------------------------------------------------------------
FUNCTION divroundup (
data_value : integer;
divisor : integer)
RETURN integer IS
VARIABLE div : integer;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- Derived Constants
-----------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_FIFO_RD_DEPTH : integer
:= actual_fifo_depth(C_RD_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_SMALLER_DATA_WIDTH : integer
:= get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
-- "Extra Words" is the number of write words which fit into the two
-- first-word fall-through output register stages (if using FWFT).
-- For ratios of 1:4 and 1:8, the fractional result is rounded up to 1.
-- This value is used to calculate the adjusted PROG_FULL threshold
-- value for FWFT.
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
CONSTANT EXTRA_WORDS : integer := divroundup(2 * C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD);
-- "Extra words dc" is used for calculating the adjusted WR_DATA_COUNT
-- value for the core when using FWFT.
-- extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
-- -----------------|------------------|-----------------|---------------
-- 1 | 8 | C_RD_PNTR_WIDTH | 2
-- 1 | 4 | C_RD_PNTR_WIDTH | 2
-- 1 | 2 | C_RD_PNTR_WIDTH | 2
-- 1 | 1 | C_WR_PNTR_WIDTH | 2
-- 2 | 1 | C_WR_PNTR_WIDTH | 4
-- 4 | 1 | C_WR_PNTR_WIDTH | 8
-- 8 | 1 | C_WR_PNTR_WIDTH | 16
CONSTANT EXTRA_WORDS_DC : integer
:= if_then_else ((C_DEPTH_RATIO_WR = 1),2,
(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT C_PE_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PE_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL); --NO FWFT
CONSTANT C_PE_THR_ASSERT_VAL_I : integer := C_PE_THR_ASSERT_ADJUSTED;
CONSTANT C_PE_THR_NEGATE_VAL_I : integer := C_PE_THR_NEGATE_ADJUSTED;
CONSTANT C_PF_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PF_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); --NO FWFT
-- NO_ERR_INJECTION will be 1 if ECC is OFF or ECC is ON but no error
-- injection is selected.
CONSTANT NO_ERR_INJECTION : integer
:= if_then_else(C_USE_ECC = 0,1,
if_then_else(C_ERROR_INJECTION_TYPE = 0,1,0));
-- SBIT_ERR_INJECTION will be 1 if ECC is ON and single bit error injection
-- is selected.
CONSTANT SBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 1),1,0);
-- DBIT_ERR_INJECTION will be 1 if ECC is ON and double bit error injection
-- is selected.
CONSTANT DBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 2),1,0);
-- BOTH_ERR_INJECTION will be 1 if ECC is ON and both single and double bit
-- error injection are selected.
CONSTANT BOTH_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 3),1,0);
CONSTANT C_DATA_WIDTH : integer := if_then_else(NO_ERR_INJECTION = 1, C_DIN_WIDTH, C_DIN_WIDTH+2);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
TYPE wr_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
TYPE rd_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pntr_q : wr_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL rd_pntr_q : rd_sync_array := (OTHERS => (OTHERS => '0'));
-------------------------------------------------------------------------------
-- Signals Declaration
-------------------------------------------------------------------------------
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_rst_i : std_logic := '0';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL wr_rst_d1 : std_logic := '0';
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL valid_out : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL width_gt1 : std_logic := '0';
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL empty_int : boolean := TRUE;
SIGNAL empty_comb : std_logic := '1';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL empty_comb_d1 : std_logic := '1';
SIGNAL almost_empty_int : boolean := TRUE;
SIGNAL full_int : boolean := FALSE;
SIGNAL full_comb : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL ram_wr_en : std_logic := '0';
SIGNAL almost_full_int : boolean := FALSE;
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
SIGNAL diff_pntr_wr : integer := 0;
SIGNAL diff_pntr_rd : integer := 0;
SIGNAL pf_input_thr_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL pf_input_thr_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE inj_err(1 DOWNTO 0) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------------
-- Asynchronous FIFO
-------------------------------------------------------------------------------
gnll_afifo: IF (C_FIFO_TYPE /= 3) GENERATE
wr_pntr <= conv_std_logic_vector(wr_point,C_WR_PNTR_WIDTH);
rd_pntr <= conv_std_logic_vector(rd_point,C_RD_PNTR_WIDTH);
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
-------------------------------------------------------------------------------
-- calculate number of words in wr and rd domain according to the deepest port
--
-- These steps circumvent the linked-list data structure and keep track of
-- wr_point and rd_point pointers much like the core itself does. The behavioral
-- model uses these to calculate WR_DATA_COUNT and RD_DATA_COUNT. This was done
-- because the sizeof() function always returns the exact number of words in
-- the linked list, and can not account for delays when crossing clock domains.
-------------------------------------------------------------------------------
adj_wr_point <= wr_point * C_DEPTH_RATIO_RD;
adj_rd_point <= rd_point * C_DEPTH_RATIO_WR;
adj_wr_point_d1<= wr_point_d1 * C_DEPTH_RATIO_RD;
adj_rd_point_d1<= rd_point_d1 * C_DEPTH_RATIO_WR;
width_gt1 <= '1' WHEN (C_DIN_WIDTH = 2) ELSE '0';
PROCESS (adj_wr_point, adj_wr_point_d1, adj_rd_point, adj_rd_point_d1)
BEGIN
IF (adj_wr_point >= adj_rd_point_d1) THEN
num_wr_words <= adj_wr_point - adj_rd_point_d1;
ELSE
num_wr_words <= C_WR_DEPTH*C_DEPTH_RATIO_RD + adj_wr_point - adj_rd_point_d1;
END IF;
IF (adj_wr_point_d1 >= adj_rd_point) THEN
num_rd_words <= adj_wr_point_d1 - adj_rd_point;
ELSE
num_rd_words <= C_RD_DEPTH*C_DEPTH_RATIO_WR + adj_wr_point_d1 - adj_rd_point;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_VALID_LOW
-------------------------------------------------------------------------------
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_out;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_out;
END GENERATE gnvh;
-------------------------------------------------------------------------------
--Calculate UNDERFLOW based on C_UNDERFLOW_LOW
-------------------------------------------------------------------------------
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
-------------------------------------------------------------------------------
--Assign PROG_FULL and PROG_EMPTY
-------------------------------------------------------------------------------
PROG_FULL <= prog_full_reg;
PROG_EMPTY <= prog_empty_reg;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1) GENERATE
grdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rdc_fwft_ext_as(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE grdc_fwft_ext;
gnrdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE gnrdc_fwft_ext;
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1) GENERATE
gwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wdc_fwft_ext_as(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gwdc_fwft_ext;
gnwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gnwdc_fwft_ext;
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Write data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
wdc_fwft_ext: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
CONSTANT C_PNTR_WIDTH : integer
:= if_then_else ((C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH),
C_WR_PNTR_WIDTH, C_RD_PNTR_WIDTH);
SIGNAL adjusted_wr_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL adjusted_rd_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
CONSTANT EXTRA_WORDS : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(
if_then_else ((C_DEPTH_RATIO_WR=1),2
,(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD))
,C_PNTR_WIDTH+1);
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_data_count_i : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
BEGIN
-----------------------------------------------------------------------------
--Adjust write and read pointer to the deepest port width
-----------------------------------------------------------------------------
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH
gpadr: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adjusted_rd_pntr(C_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
END GENERATE gpadr;
--C_PNTR_WIDTH=C_RD_PNTR_WIDTH
gpadw: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adjusted_wr_pntr(C_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE gpadw;
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH=C_RD_PNTR_WIDTH
ngpad: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE ngpad;
-----------------------------------------------------------------------------
--Calculate words in write domain
-----------------------------------------------------------------------------
--Subtract the pointers to get the number of words in the RAM, *THEN* pad
--the result
diff_wr_rd_tmp <= adjusted_wr_pntr - adjusted_rd_pntr;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
pwdc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_i <= (OTHERS=>'0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_i <= diff_wr_rd + extra_words;
END IF;
END PROCESS pwdc;
gdc0: IF (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO 0);
END GENERATE gdc0;
gdc1: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gdc1;
END GENERATE wdc_fwft_ext;
-------------------------------------------------------------------------------
-- Read data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
rdc_fwft_ext: IF (C_HAS_RD_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL zero : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL one : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(1, C_RD_PNTR_WIDTH+1);
SIGNAL two : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(2, C_RD_PNTR_WIDTH+1);
SIGNAL adjusted_wr_pntr_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
BEGIN
----------------------------------------------------------------------------
-- If write depth is smaller than read depth, pad write pointer.
-- If write depth is bigger than read depth, trim write pointer.
----------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= WR_PNTR_RD;
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r
<= WR_PNTR_RD(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-----------------------------------------------------------------------------
-- This accounts for preload 0 by explicitly handling the preload states
-- which do not have both output stages filled. As a result, the rd_data_count
-- produced will always accurately reflect the number of READABLE words at
-- a given time.
-----------------------------------------------------------------------------
diff_wr_rd_tmp <= adjusted_wr_pntr_r - RD_PNTR;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
prdc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rdc_fwft_ext_as <= zero;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (stage2_valid = '0') THEN
rdc_fwft_ext_as <= zero;
ELSIF (stage2_valid = '1' AND stage1_valid = '0') THEN
rdc_fwft_ext_as <= one;
ELSE
rdc_fwft_ext_as <= diff_wr_rd + two;
END IF;
END IF;
END PROCESS prdc;
END GENERATE rdc_fwft_ext;
-------------------------------------------------------------------------------
-- Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
-------------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr_rd;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr_rd(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-------------------------------------------------------------------------------
-- Generate Empty
-------------------------------------------------------------------------------
-- ram_rd_en used to determine EMPTY should depend on the EMPTY.
ram_rd_en <= RD_EN AND (NOT empty_comb);
empty_int <= ((adj_wr_pntr_rd = rd_pntr) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Empty
-------------------------------------------------------------------------------
almost_empty_int <= ((adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+2),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Empty & Almost Empty
-- Generate read data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
empty_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_comb <= '1' AFTER C_TCQ;
empty_comb_d1 <= '1' AFTER C_TCQ;
ALMOST_EMPTY <= '1' AFTER C_TCQ;
rd_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_data_count_int <= ((adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO 0) -
rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
empty_comb_d1 <= empty_comb AFTER C_TCQ;
IF (empty_int) THEN
empty_comb <= '1' AFTER C_TCQ;
ELSE
empty_comb <= '0' AFTER C_TCQ;
END IF;
IF (empty_comb = '0') THEN
IF (almost_empty_int) THEN
ALMOST_EMPTY <= '1' AFTER C_TCQ;
ELSE
ALMOST_EMPTY <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Read pointer adjustment based on pointers width for FULL/ALMOST_FULL generation
-------------------------------------------------------------------------------
gfpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gfpad;
gftrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
<= rd_pntr_wr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gftrim;
-------------------------------------------------------------------------------
-- Generate Full
-------------------------------------------------------------------------------
-- ram_wr_en used to determine FULL should depend on the FULL.
ram_wr_en <= WR_EN AND (NOT full_comb);
full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+1),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Full
-------------------------------------------------------------------------------
almost_full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+3),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Full & Almost Full
-- Generate write data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
full_proc : PROCESS (WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_comb <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ALMOST_FULL <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (full_int) THEN
full_comb <= '1' AFTER C_TCQ;
ELSE
full_comb <= '0' AFTER C_TCQ;
END IF;
IF (RST_FULL_GEN = '1') THEN
ALMOST_FULL <= '0' AFTER C_TCQ;
ELSIF (full_comb = '0') THEN
IF (almost_full_int) THEN
ALMOST_FULL <= '1' AFTER C_TCQ;
ELSE
ALMOST_FULL <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS full_proc;
wdci_proc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_int <= ((wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO 0) -
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
END IF;
END PROCESS wdci_proc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
user_empty_fb_d1 <= USER_EMPTY_FB;
IF (user_empty_fb_d1 = '0' AND USER_EMPTY_FB = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_comb = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_comb = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_comb = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
gnrd_fwft: IF (C_PRELOAD_LATENCY > 0) GENERATE
rd_fwft_cnt <= X"2";
END GENERATE gnrd_fwft;
-------------------------------------------------------------------------------
-- Assign FULL, EMPTY, ALMOST_FULL and ALMOST_EMPTY
-------------------------------------------------------------------------------
FULL <= full_comb;
EMPTY <= empty_comb;
-------------------------------------------------------------------------------
-- Asynchronous FIFO using linked lists
-------------------------------------------------------------------------------
FIFO_PROC : PROCESS (WR_CLK, RD_CLK, rd_rst_i, wr_rst_i)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF wr_rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
rd_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
rd_pntr_q <= rd_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & rd_pntr_wr_d1;
-- Delay the write pointer before passing to RD_CLK domain to accommodate
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
rd_pntr_wr <= rd_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --WR_CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF rd_rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
wr_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
-- DRAM resets asynchronously
IF (C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- BRAM resets synchronously
IF (C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
wr_pntr_q <= wr_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & wr_pntr_rd1;
-- Delay the read pointer before passing to WR_CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
wr_pntr_rd <= wr_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (ram_rd_en = '1') THEN
IF empty_comb /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --RD_CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
-----------------------------------------------------------------------------
-- Programmable FULL flags
-----------------------------------------------------------------------------
proc_pf_input: PROCESS(PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT,PROG_FULL_THRESH_NEGATE)
BEGIN
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH - conv_integer(EXTRA_WORDS_DC);
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
END IF;
ELSE -- STD
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH;
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT;
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE;
END IF;
END IF;
END PROCESS proc_pf_input;
proc_wdc: PROCESS(WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
diff_pntr_wr <= 0;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (ram_wr_en = '0') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) after C_TCQ;
ELSIF (ram_wr_en = '1') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) + 1 after C_TCQ;
END IF;
END IF; -- WR_CLK
END PROCESS proc_wdc;
proc_pf: PROCESS(WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_reg <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_reg <= '0' after C_TCQ;
ELSIF (C_PROG_FULL_TYPE = 1) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 2) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < C_PF_THR_NEGATE_ADJUSTED) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 3) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 4) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < conv_integer(pf_input_thr_negate_val)) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
END IF; --C_PROG_FULL_TYPE
END IF; -- WR_CLK
END PROCESS proc_pf;
---------------------------------------------------------------------------
-- Programmable EMPTY Flags
---------------------------------------------------------------------------
proc_pe: PROCESS(RD_CLK, rd_rst_i)
VARIABLE pe_thr_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE pe_thr_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF (rd_rst_i = '1') THEN
diff_pntr_rd <= 0;
prog_empty_reg <= '1';
pe_thr_assert_val := (OTHERS => '0');
pe_thr_negate_val := (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (ram_rd_en = '0') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) after C_TCQ;
ELSIF (ram_rd_en = '1') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) - 1 after C_TCQ;
ELSE
diff_pntr_rd <= diff_pntr_rd after C_TCQ;
END IF;
IF (C_PROG_EMPTY_TYPE = 1) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 2) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > C_PE_THR_NEGATE_VAL_I) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 3) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= pe_thr_assert_val) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 4) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT - "10";
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT;
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= conv_integer(pe_thr_assert_val)) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > conv_integer(pe_thr_negate_val)) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
END IF; --C_PROG_EMPTY_TYPE
END IF; -- RD_CLK
END PROCESS proc_pe;
-----------------------------------------------------------------------------
-- overflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
g7s_ovflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
overflow_i <= full_comb AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g7s_ovflw;
g8s_ovflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
--overflow_i <= (wr_rst_i OR full_comb) AND WR_EN after C_TCQ;
overflow_i <= (full_comb) AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g8s_ovflw;
END GENERATE govflw;
-----------------------------------------------------------------------------
-- underflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
g7s_unflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
underflow_i <= empty_comb and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g7s_unflw;
g8s_unflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
--underflow_i <= (rd_rst_i OR empty_comb) and RD_EN after C_TCQ;
underflow_i <= (empty_comb) and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g8s_unflw;
END GENERATE gunflw;
-----------------------------------------------------------------------------
-- wr_ack_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF wr_rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
----------------------------------------------------------------------------
-- valid_i generation: Asynchronous FIFO
----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_comb /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------
-- Delay valid_d1
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1
-----------------------------------------------------------------
gv0_as: IF (C_USE_EMBEDDED_REG>0
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_d1 <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_d1 <= valid_i after C_TCQ;
END IF;
END PROCESS;
END GENERATE gv0_as;
gv1_as: IF NOT (C_USE_EMBEDDED_REG>0
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
valid_d1 <= valid_i;
END GENERATE gv1_as;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Use delayed Valid AND DOUT if we have a LATENCY=2 configurations
-- ( if C_MEMORY_TYPE=0 or 1, C_PRELOAD_REGS=0, C_USE_EMBEDDED_REG=1 )
--Otherwise, connect the valid and DOUT values up directly, with no
--additional latency.
-----------------------------------------------------------------------------
gv0: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)AND C_EN_SAFETY_CKT =0) GENERATE
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF (rd_rst_i = '1') THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv0_safety: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT =1) GENERATE
SIGNAL dout_rst_val_d1 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dout_rst_val_d2 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS ( RD_CLK )
BEGIN
rst_delayed_sft1 <= rd_rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
PROCESS (rst_delayed_sft4 ,rd_rst_i, RD_CLK )
BEGIN
IF (rst_delayed_sft4 = '1' OR rd_rst_i = '1') THEN
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_delayed_sft4 , RD_CLK )
BEGIN
IF (rst_delayed_sft4 = '1' ) THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
--ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0_safety;
gv1_nsafety: IF (NOT (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) ) GENERATE
gv2a: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_i;
END GENERATE gv2a;
DOUT <= dout_i;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END GENERATE gv1_nsafety;
END GENERATE gnll_afifo;
-------------------------------------------------------------------------------
-- Low Latency Asynchronous FIFO
-------------------------------------------------------------------------------
gll_afifo: IF (C_FIFO_TYPE = 3) GENERATE
TYPE mem_array IS ARRAY (0 TO C_WR_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL wr_pntr_ll_afifo : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo_q : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL ll_afifo_full : std_logic := '0';
SIGNAL ll_afifo_empty : std_logic := '1';
SIGNAL wr_pntr_eq_rd_pntr : std_logic := '0';
SIGNAL wr_pntr_eq_rd_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus2 : std_logic := '0';
BEGIN
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
write_allow <= WR_EN AND (NOT ll_afifo_full);
read_allow <= RD_EN AND (NOT ll_afifo_empty);
wrptr_proc : PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_pntr_ll_afifo <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
wr_pntr_ll_afifo <= wr_pntr_ll_afifo + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
-------------------------------------------------------------------------------
-- Fill the Memory
-------------------------------------------------------------------------------
wr_mem : PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr_ll_afifo)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
rdptr_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_pntr_ll_afifo_q <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_pntr_ll_afifo_q <= rd_pntr_ll_afifo AFTER C_TCQ;
END IF;
END PROCESS rdptr_proc;
rd_pntr_ll_afifo <= rd_pntr_ll_afifo_q + "1" WHEN (read_allow = '1') ELSE rd_pntr_ll_afifo_q;
-------------------------------------------------------------------------------
-- Generate DOUT for DRAM
-------------------------------------------------------------------------------
rd_mem : PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK = '1') THEN
DOUT <= memory(conv_integer(rd_pntr_ll_afifo)) AFTER C_TCQ;
END IF;
END PROCESS rd_mem;
-------------------------------------------------------------------------------
-- Generate EMPTY
-------------------------------------------------------------------------------
wr_pntr_eq_rd_pntr <= '1' WHEN (wr_pntr_ll_afifo = rd_pntr_ll_afifo_q) ELSE '0';
wr_pntr_eq_rd_pntr_plus1 <= '1' WHEN (wr_pntr_ll_afifo = conv_std_logic_vector(
(conv_integer(rd_pntr_ll_afifo_q)+1),
C_RD_PNTR_WIDTH)) ELSE '0';
proc_empty : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
ll_afifo_empty <= '1';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
ll_afifo_empty <= wr_pntr_eq_rd_pntr OR (read_allow AND wr_pntr_eq_rd_pntr_plus1) AFTER C_TCQ;
END IF;
END PROCESS proc_empty;
-------------------------------------------------------------------------------
-- Generate FULL
-------------------------------------------------------------------------------
rd_pntr_eq_wr_pntr_plus1 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+1),
C_WR_PNTR_WIDTH)) ELSE '0';
rd_pntr_eq_wr_pntr_plus2 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+2),
C_WR_PNTR_WIDTH)) ELSE '0';
proc_full : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
ll_afifo_full <= '1';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
ll_afifo_full <= rd_pntr_eq_wr_pntr_plus1 OR (write_allow AND rd_pntr_eq_wr_pntr_plus2) AFTER C_TCQ;
END IF;
END PROCESS proc_full;
EMPTY <= ll_afifo_empty;
FULL <= ll_afifo_full;
END GENERATE gll_afifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Common Clock FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_misc.ALL;
-------------------------------------------------------------------------------
-- Common-Clock Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_bhv_ss IS
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_EN : IN std_logic := '0';
RD_EN_USER : IN std_logic;
WR_EN : IN std_logic := '0';
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_RST_BUSY : IN std_logic := '0';
RD_RST_BUSY : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_bhv_ss;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_ss IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer;
C_COMMON_CLOCK : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic_vector;
false_case : std_logic_vector)
RETURN std_logic_vector IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
running_result := conv_std_logic_vector(value,bitwidth);
RETURN running_result;
END int_2_std_logic_vector;
--------------------------------------------------------------------------------
-- Constant Declaration
--------------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY, 1);
CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_FIFO_DEPTH : integer := C_WR_DEPTH;
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
CONSTANT C_DATA_WIDTH : integer := if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0),
C_DIN_WIDTH+2, C_DIN_WIDTH);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
CONSTANT DO_ALL_ZERO : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT RST_VAL : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
CONSTANT RST_VALUE : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= if_then_else(C_USE_DOUT_RST = 1, RST_VAL, DO_ALL_ZERO);
CONSTANT IS_ASYMMETRY : integer :=if_then_else((C_WR_PNTR_WIDTH /= C_RD_PNTR_WIDTH),1,0);
CONSTANT C_GRTR_PNTR_WIDTH : integer :=if_then_else((C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH),C_WR_PNTR_WIDTH,C_RD_PNTR_WIDTH);
CONSTANT LESSER_WIDTH : integer
:=if_then_else((C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH),
C_WR_PNTR_WIDTH,
C_RD_PNTR_WIDTH);
CONSTANT DIFF_MAX_RD : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
CONSTANT DIFF_MAX_WR : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
TYPE mem_array IS ARRAY (0 TO C_FIFO_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- Internal Signals
-------------------------------------------------------------------------------
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL read_allow_dc : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_full_i : std_logic := '0';
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
SIGNAL rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
SIGNAL srst_wrst_busy : std_logic := '0';
SIGNAL srst_rrst_busy : std_logic := '0';
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
--The delayed reset is used to deassert prog_full
SIGNAL rst_q : std_logic := '0';
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_full_noreg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL prog_empty_noreg: std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := RST_VALUE;
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL mem_pntr : integer := 0;
SIGNAL ram_wr_en_i : std_logic := '0';
SIGNAL ram_rd_en_i : std_logic := '0';
SIGNAL comp1 : std_logic := '0';
SIGNAL comp0 : std_logic := '0';
SIGNAL going_full : std_logic := '0';
SIGNAL leaving_full : std_logic := '0';
SIGNAL ram_full_comb : std_logic := '0';
SIGNAL ecomp1 : std_logic := '0';
SIGNAL ecomp0 : std_logic := '0';
SIGNAL going_empty : std_logic := '0';
SIGNAL leaving_empty : std_logic := '0';
SIGNAL ram_empty_comb : std_logic := '0';
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL wr_point_d2 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_pntr_temp : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL width_gt1 : std_logic := '0';
-------------------------------------------------------------------------------
--Used in computing AE and AF
-------------------------------------------------------------------------------
SIGNAL fcomp2 : std_logic := '0';
SIGNAL going_afull : std_logic := '0';
SIGNAL leaving_afull : std_logic := '0';
SIGNAL ram_afull_comb : std_logic := '0';
SIGNAL ecomp2 : std_logic := '0';
SIGNAL going_aempty : std_logic := '0';
SIGNAL leaving_aempty : std_logic := '0';
SIGNAL ram_aempty_comb : std_logic := '1';
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
-------------------------------------------------------------------------------
--Used in computing RD_DATA_COUNT WR_DATA_COUNT
-------------------------------------------------------------------------------
SIGNAL count_dc : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0) := int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
SIGNAL one : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0);
SIGNAL ratio : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0);
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE inj_err(1 DOWNTO 0) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
--gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
rst_i <= RST;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST;
srst_rrst_busy <= SRST OR RD_RST_BUSY;
srst_wrst_busy <= SRST OR WR_RST_BUSY;
END GENERATE gsrst;
--No SRST
nosrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
srst_rrst_busy <= '0';
srst_wrst_busy <= '0';
END GENERATE nosrst;
gdc : IF (C_HAS_DATA_COUNT = 1) GENERATE
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
diff_count <= wr_pntr - rd_pntr;
gdcb : IF (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT(C_RD_PNTR_WIDTH-1 DOWNTO 0) <= diff_count;
DATA_COUNT(C_DATA_COUNT_WIDTH-1) <= '0' ;
END GENERATE;
gdcs : IF (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT <=
diff_count(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH);
END GENERATE;
END GENERATE gdc;
gndc : IF (C_HAS_DATA_COUNT = 0) GENERATE
DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_PRELOAD_LATENCY and C_VALID_LOW settings
-------------------------------------------------------------------------------
gvlat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_d1;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_d1;
END GENERATE gnvh;
END GENERATE gvlat1;
-------------------------------------------------------------------------------
-- Calculate UNDERFLOW based on C_PRELOAD_LATENCY and C_UNDERFLOW_LOW settings
-------------------------------------------------------------------------------
guflat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
END GENERATE guflat1;
FULL <= full_i;
gaf_ss: IF (C_HAS_ALMOST_FULL = 1 OR C_PROG_FULL_TYPE > 2 OR C_PROG_EMPTY_TYPE > 2) GENERATE
BEGIN
ALMOST_FULL <= almost_full_i;
END GENERATE gaf_ss;
gafn_ss: IF (C_HAS_ALMOST_FULL = 0 AND C_PROG_FULL_TYPE <= 2 AND C_PROG_EMPTY_TYPE <= 2) GENERATE
BEGIN
ALMOST_FULL <= '0';
END GENERATE gafn_ss;
EMPTY <= empty_i;
gae_ss: IF (C_HAS_ALMOST_EMPTY = 1) GENERATE
BEGIN
ALMOST_EMPTY <= almost_empty_i;
END GENERATE gae_ss;
gaen_ss: IF (C_HAS_ALMOST_EMPTY = 0) GENERATE
BEGIN
ALMOST_EMPTY <= '0';
END GENERATE gaen_ss;
write_allow <= WR_EN AND (NOT full_i);
read_allow <= RD_EN AND (NOT empty_i);
gen_read_allow_for_dc_fwft: IF(C_PRELOAD_REGS =1 AND C_PRELOAD_LATENCY =0) GENERATE
read_allow_dc <= RD_EN_USER AND (NOT USER_EMPTY_FB);
END GENERATE gen_read_allow_for_dc_fwft;
gen_read_allow_for_dc_std: IF(NOT(C_PRELOAD_REGS =1 AND C_PRELOAD_LATENCY =0)) GENERATE
read_allow_dc <= read_allow;
END GENERATE gen_read_allow_for_dc_std;
wrptr_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
wr_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
wr_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (write_allow = '1') THEN
wr_pntr <= wr_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
gecc_mem: IF (C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= INJECTDBITERR & INJECTSBITERR & DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gecc_mem;
gnecc_mem: IF NOT (C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gnecc_mem;
rdptr_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
rd_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
rd_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (read_allow = '1') THEN
rd_pntr <= rd_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS rdptr_proc;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (CLK'event AND CLK = '1') THEN
-- user_empty_fb_d1 <= USER_EMPTY_FB;
user_empty_fb_d1 <= empty_i;
IF (user_empty_fb_d1 = '0' AND empty_i = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_i = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_i = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_i = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_i = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_i = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_i = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_i = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
-------------------------------------------------------------------------------
-- Generate DOUT for common clock low latency FIFO
-------------------------------------------------------------------------------
gll_dout: IF(C_FIFO_TYPE = 2) GENERATE
SIGNAL dout_q : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
dout_i <= memory(conv_integer(rd_pntr)) when (read_allow = '1') else dout_q;
dout_reg : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
dout_q <= dout_i AFTER C_TCQ;
END IF;
END PROCESS dout_reg;
END GENERATE gll_dout;
-------------------------------------------------------------------------------
-- Generate FULL flag
-------------------------------------------------------------------------------
gpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr (C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH) <= rd_pntr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr <= rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gtrim;
comp1 <= '1' WHEN (adj_rd_pntr_wr = (wr_pntr + "1")) ELSE '0';
comp0 <= '1' WHEN (adj_rd_pntr_wr = wr_pntr) ELSE '0';
gf_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
END GENERATE gf_wp_eq_rp;
-- Write data width is bigger than read data width
-- Write depth is smaller than read depth
-- One write could be equal to 2 or 4 or 8 reads
gf_asym: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_full <= comp1 AND write_allow AND (NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))));
leaving_full <= (comp0 AND read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))) OR RST_FULL_GEN;
END GENERATE gf_asym;
gf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
END GENERATE gf_wp_gt_rp;
ram_full_comb <= going_full OR (NOT leaving_full AND full_i);
full_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
full_i <= ram_full_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS full_proc;
-------------------------------------------------------------------------------
-- Generate ALMOST_FULL flag
-------------------------------------------------------------------------------
fcomp2 <= '1' WHEN (adj_rd_pntr_wr = (wr_pntr + "10")) ELSE '0';
gaf_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= (comp1 AND read_allow AND NOT write_allow) OR RST_FULL_GEN;
END GENERATE gaf_wp_eq_rp;
gaf_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_afull <= fcomp2 AND write_allow AND (NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))));
leaving_afull <= (comp1 AND (NOT write_allow) AND read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))) OR RST_FULL_GEN;
END GENERATE gaf_wp_lt_rp;
gaf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= ((comp0 OR comp1 OR fcomp2) AND read_allow) OR RST_FULL_GEN;
END GENERATE gaf_wp_gt_rp;
ram_afull_comb <= going_afull OR (NOT leaving_afull AND almost_full_i);
af_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
almost_full_i <= ram_afull_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS af_proc;
-------------------------------------------------------------------------------
-- Generate EMPTY flag
-------------------------------------------------------------------------------
pad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE pad;
trim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE trim;
ecomp1 <= '1' WHEN (adj_wr_pntr_rd = (rd_pntr + "1")) ELSE '0';
ecomp0 <= '1' WHEN (adj_wr_pntr_rd = rd_pntr) ELSE '0';
ge_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_empty <= (ecomp1 AND (NOT write_allow) AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
END GENERATE ge_wp_eq_rp;
ge_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_empty <= (ecomp1 AND (NOT write_allow) AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
END GENERATE ge_wp_lt_rp;
ge_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_empty <= ecomp1 AND read_allow AND (NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0))));
leaving_empty <= ecomp0 AND write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0));
END GENERATE ge_wp_gt_rp;
ram_empty_comb <= going_empty OR (NOT leaving_empty AND empty_i);
empty_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
empty_i <= '1' AFTER C_TCQ;
ELSE
empty_i <= ram_empty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Generate data_count_int flags for RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rd_depth_gt_wr: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
SIGNAL decr_by_one : std_logic := '0';
SIGNAL incr_by_ratio : std_logic := '0';
BEGIN
ratio <= int_2_std_logic_vector(if_then_else(C_DEPTH_RATIO_RD > C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD, C_DEPTH_RATIO_WR), C_GRTR_PNTR_WIDTH+1);
one <= int_2_std_logic_vector(1, C_GRTR_PNTR_WIDTH+1);
decr_by_one <= read_allow_dc;
incr_by_ratio <= write_allow;
cntr: PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_wrst_busy = '1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1)
AFTER C_TCQ;
ELSE
IF decr_by_one = '1' THEN
IF incr_by_ratio = '0' THEN
count_dc <= count_dc - one AFTER C_TCQ;
ELSE
count_dc <= count_dc - one + ratio AFTER C_TCQ;
END IF;
ELSE
IF incr_by_ratio = '0' THEN
count_dc <= count_dc AFTER C_TCQ;
ELSE
count_dc <= count_dc + ratio AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS cntr;
rd_data_count_int <= count_dc;
wr_data_count_int <= count_dc(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE rd_depth_gt_wr;
wr_depth_gt_rd: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
SIGNAL incr_by_one : std_logic := '0';
SIGNAL decr_by_ratio : std_logic := '0';
BEGIN
ratio <= int_2_std_logic_vector(if_then_else(C_DEPTH_RATIO_RD > C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD, C_DEPTH_RATIO_WR), C_GRTR_PNTR_WIDTH+1);
one <= int_2_std_logic_vector(1, C_GRTR_PNTR_WIDTH+1);
incr_by_one <= write_allow;
decr_by_ratio <= read_allow_dc;
cntr: PROCESS (CLK, RST)
BEGIN
IF (rst_i = '1' ) THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_wrst_busy='1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1)
AFTER C_TCQ;
ELSE
IF incr_by_one = '1' THEN
IF decr_by_ratio = '0' THEN
count_dc <= count_dc + one AFTER C_TCQ;
ELSE
count_dc <= count_dc + one - ratio AFTER C_TCQ;
END IF;
ELSE
IF decr_by_ratio = '0' THEN
count_dc <= count_dc AFTER C_TCQ;
ELSE
count_dc <= count_dc - ratio AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS cntr;
wr_data_count_int <= count_dc;
rd_data_count_int <= count_dc(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE wr_depth_gt_rd;
-------------------------------------------------------------------------------
-- Generate ALMOST_EMPTY flag
-------------------------------------------------------------------------------
ecomp2 <= '1' WHEN (adj_wr_pntr_rd = (rd_pntr + "10")) ELSE '0';
gae_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_aempty <= (ecomp2 AND (NOT write_allow) AND read_allow);
leaving_aempty <= (ecomp1 AND write_allow AND (NOT read_allow));
END GENERATE gae_wp_eq_rp;
gae_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_aempty <= (ecomp2 AND (NOT write_allow) AND read_allow);
leaving_aempty <= ((ecomp0 OR ecomp1 OR ecomp2) AND write_allow);
END GENERATE gae_wp_lt_rp;
gae_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_aempty <= ecomp2 AND read_allow AND (NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0))));
leaving_aempty <= ecomp1 AND (NOT read_allow) AND write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0));
END GENERATE gae_wp_gt_rp;
ram_aempty_comb <= going_aempty OR (NOT leaving_aempty AND almost_empty_i);
ae_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
almost_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
almost_empty_i <= '1' AFTER C_TCQ;
ELSE
almost_empty_i <= ram_aempty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS ae_proc;
-------------------------------------------------------------------------------
-- synchronous FIFO using linked lists
-------------------------------------------------------------------------------
gnll_cc_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
FIFO_PROC : PROCESS (CLK, rst_i, wr_pntr)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_point_d2 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF CLK'event AND CLK = '1' THEN
IF srst_wrst_busy = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_point_d2 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
ELSE
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
rd_pntr_wr <= rd_pntr_wr_d1 after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
wr_point_d2 <= wr_point_d1 after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_i /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --srst
END IF; --CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF (C_FIFO_TYPE < 2 AND C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
IF (rst_i = '1' OR srst_rrst_busy = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
END IF;
IF rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
-- DRAM resets asynchronously
IF (C_FIFO_TYPE < 2 AND (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3 )AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF CLK'event AND CLK = '1' THEN
-- ELSE
IF (srst_rrst_busy= '1') THEN
IF (C_FIFO_TYPE < 2 AND (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3 ) AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
IF srst_rrst_busy = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
-- DRAM resets asynchronously
IF (C_FIFO_TYPE < 2 AND C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSE
-- Delay the read pointer before passing to CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
wr_pntr_rd <= wr_pntr_rd1 after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (RD_EN = '1') THEN
IF empty_i /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --srst
END IF; --CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
END GENERATE gnll_cc_fifo;
-------------------------------------------------------------------------------
-- Generate PROG_FULL and PROG_EMPTY flags
-------------------------------------------------------------------------------
gpf_pe: IF (C_PROG_FULL_TYPE /= 0 OR C_PROG_EMPTY_TYPE /= 0) GENERATE
SIGNAL diff_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_max : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_wr_pntr_rd_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_max : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_reg1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_reg1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_reg2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_reg2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow_q : std_logic := '0';
SIGNAL read_allow_q : std_logic := '0';
SIGNAL write_only : std_logic := '0';
SIGNAL write_only_q : std_logic := '0';
SIGNAL read_only : std_logic := '0';
SIGNAL read_only_q : std_logic := '0';
SIGNAL prog_full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL prog_empty_i : std_logic := '1';
SIGNAL full_reg : std_logic := '0';
SIGNAL rst_full_ff_reg1 : std_logic := '0';
SIGNAL rst_full_ff_reg2 : std_logic := '0';
SIGNAL carry : std_logic := '0';
CONSTANT WR_RD_RATIO_I_PF : integer := if_then_else((C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH), (C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH), 0);
CONSTANT WR_RD_RATIO_PF : integer := 2**WR_RD_RATIO_I_PF;
-- CONSTANT WR_RD_RATIO_I_PE : integer := if_then_else((C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH), (C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH), 0);
-- CONSTANT WR_RD_RATIO_PE : integer := 2**WR_RD_RATIO_I_PE;
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
--CONSTANT EXTRA_WORDS : integer := if_then_else ((C_DEPTH_RATIO_WR = 1),2,
-- (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT EXTRA_WORDS_PF : integer := 2*WR_RD_RATIO_PF;
--CONSTANT EXTRA_WORDS_PE : integer := 2*WR_RD_RATIO_PE;
CONSTANT C_PF_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF, -- FWFT
C_PROG_FULL_THRESH_ASSERT_VAL); -- STD
CONSTANT C_PF_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF, -- FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); -- STD
CONSTANT C_PE_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2,
C_PROG_EMPTY_THRESH_ASSERT_VAL);
CONSTANT C_PE_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL);
BEGIN
diff_pntr_pe_max <= DIFF_MAX_RD;
dif_pntr_sym: IF (IS_ASYMMETRY = 0) GENERATE
write_only <= write_allow AND NOT read_allow;
read_only <= read_allow AND NOT write_allow;
END GENERATE dif_pntr_sym;
dif_pntr_asym: IF (IS_ASYMMETRY = 1) GENERATE
gpf_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
read_only <= read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)) AND NOT(write_allow);
write_only <= write_allow AND NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)));
END GENERATE gpf_wp_lt_rp;
gpf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
read_only <= read_allow AND NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)));
write_only<= write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)) AND NOT(read_allow);
END GENERATE gpf_wp_gt_rp;
END GENERATE dif_pntr_asym;
dif_cal_pntr_sym: IF (IS_ASYMMETRY = 0) GENERATE
wr_rd_q_proc : PROCESS (CLK)
BEGIN
IF (rst_i = '1') THEN
write_only_q <= '0';
read_only_q <= '0';
diff_pntr_reg1 <= (OTHERS => '0');
diff_pntr_pe_reg1 <= (OTHERS => '0');
diff_pntr_reg2 <= (OTHERS => '0');
diff_pntr_pe_reg2 <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_rrst_busy = '1' OR srst_wrst_busy = '1' ) THEN
IF (srst_rrst_busy = '1') THEN
read_only_q <= '0' AFTER C_TCQ;
diff_pntr_pe_reg1 <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_pe_reg2 <= (OTHERS => '0');
END IF;
IF (srst_wrst_busy = '1') THEN
write_only_q <= '0' AFTER C_TCQ;
diff_pntr_reg1 <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_reg2 <= (OTHERS => '0');
END IF;
ELSE
write_only_q <= write_only AFTER C_TCQ;
read_only_q <= read_only AFTER C_TCQ;
diff_pntr_reg2 <= diff_pntr_reg1 AFTER C_TCQ;
diff_pntr_pe_reg2 <= diff_pntr_pe_reg1 AFTER C_TCQ;
-- Add 1 to the difference pointer value when only write happens.
IF (write_only = '1') THEN
diff_pntr_reg1 <= wr_pntr - adj_rd_pntr_wr + "1" AFTER C_TCQ;
ELSE
diff_pntr_reg1 <= wr_pntr - adj_rd_pntr_wr AFTER C_TCQ;
END IF;
-- Add 1 to the difference pointer value when write or both write & read or no write & read happen.
IF (read_only = '1') THEN
diff_pntr_pe_reg1 <= adj_wr_pntr_rd - rd_pntr - "1" AFTER C_TCQ;
ELSE
diff_pntr_pe_reg1 <= adj_wr_pntr_rd - rd_pntr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
diff_pntr <= diff_pntr_reg1(C_WR_PNTR_WIDTH-1 downto 0);
diff_pntr_pe <= diff_pntr_pe_reg1(C_RD_PNTR_WIDTH-1 downto 0);
END GENERATE dif_cal_pntr_sym;
dif_cal_pntr_asym: IF (IS_ASYMMETRY = 1) GENERATE
adj_wr_pntr_rd_asym(C_RD_PNTR_WIDTH downto 1) <= adj_wr_pntr_rd;
adj_wr_pntr_rd_asym(0) <= '1';
rd_pntr_asym(C_RD_PNTR_WIDTH downto 1) <= not(rd_pntr);
rd_pntr_asym(0) <= '1';
wr_rd_q_proc : PROCESS (CLK)
BEGIN
IF (rst_i = '1') THEN
diff_pntr_pe_asym <= (OTHERS => '0');
full_reg <= '0';
rst_full_ff_reg1 <= '1';
rst_full_ff_reg2 <= '1';
diff_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_rrst_busy = '1' OR srst_wrst_busy = '1' ) THEN
IF (srst_rrst_busy = '1') THEN
rst_full_ff_reg1 <= '1' AFTER C_TCQ;
rst_full_ff_reg2 <= '1' AFTER C_TCQ;
full_reg <= '0' AFTER C_TCQ;
diff_pntr_pe_asym <= (OTHERS => '0') AFTER C_TCQ;
END IF;
IF (srst_wrst_busy = '1') THEN
diff_pntr <= (OTHERS => '0') AFTER C_TCQ;
END IF;
ELSE
write_only_q <= write_only AFTER C_TCQ;
read_only_q <= read_only AFTER C_TCQ;
diff_pntr_reg2 <= diff_pntr_reg1 AFTER C_TCQ;
diff_pntr_pe_reg2 <= diff_pntr_pe_reg1 AFTER C_TCQ;
rst_full_ff_reg1 <= RST_FULL_FF AFTER C_TCQ;
rst_full_ff_reg2 <= rst_full_ff_reg1 AFTER C_TCQ;
full_reg <= full_i AFTER C_TCQ;
diff_pntr_pe_asym <= adj_wr_pntr_rd_asym + rd_pntr_asym AFTER C_TCQ;
IF (full_i = '0') THEN
diff_pntr <= wr_pntr - adj_rd_pntr_wr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
carry <= (NOT(OR_REDUCE(diff_pntr_pe_asym (C_RD_PNTR_WIDTH downto 1))));
diff_pntr_pe <= diff_pntr_pe_max when (full_reg = '1' AND rst_full_ff_reg2 = '0' AND carry = '1' ) else diff_pntr_pe_asym (C_RD_PNTR_WIDTH downto 1);
END GENERATE dif_cal_pntr_asym;
-------------------------------------------------------------------------------
-- Generate PROG_FULL flag
-------------------------------------------------------------------------------
gpf: IF (C_PROG_FULL_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold constant
-------------------------------------------------------------------------------
gpf1: IF (C_PROG_FULL_TYPE = 1) GENERATE
pf1_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '0') THEN
IF ((diff_pntr) >= C_PF_ASSERT_VAL ) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((diff_pntr) < C_PF_ASSERT_VAL ) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf1_proc;
END GENERATE gpf1;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpf2: IF (C_PROG_FULL_TYPE = 2) GENERATE
pf2_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1' AND C_HAS_RST = 1) THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_NEGATE_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (RST_FULL_GEN='0') THEN
IF (conv_integer(diff_pntr) >= C_PF_ASSERT_VAL ) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) < C_PF_NEGATE_VAL) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf2_proc;
END GENERATE gpf2;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold input port
-------------------------------------------------------------------------------
gpf3: IF (C_PROG_FULL_TYPE = 3) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH)WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH;
pf3_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) > pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) = pf_assert_val) THEN
IF (read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (full_i='0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) < pf_assert_val) THEN
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf3_proc;
END GENERATE gpf3;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpf4: IF (C_PROG_FULL_TYPE = 4) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pf_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH_ASSERT -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH) WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_ASSERT;
pf_negate_val <= PROG_FULL_THRESH_NEGATE -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH) WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_NEGATE;
pf4_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr) = pf_negate_val) AND read_only_q = '1') OR
(conv_integer(diff_pntr) < pf_negate_val)) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (full_i='0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF(conv_integer(diff_pntr) < pf_negate_val) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf4_proc;
END GENERATE gpf4;
PROG_FULL <= prog_full_i;
END GENERATE gpf;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY flag
-------------------------------------------------------------------------------
gpe: IF (C_PROG_EMPTY_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold constant
-------------------------------------------------------------------------------
gpe1: IF (C_PROG_EMPTY_TYPE = 1) GENERATE
pe1_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSE
IF (IS_ASYMMETRY = 0) THEN
IF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (rst_i = '0') THEN
IF (diff_pntr_pe <= (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (diff_pntr_pe > (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS pe1_proc;
END GENERATE gpe1;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpe2: IF (C_PROG_EMPTY_TYPE = 2) GENERATE
pe2_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSE
IF (IS_ASYMMETRY = 0) THEN
IF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_NEGATE_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (rst_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > (C_PE_NEGATE_VAL) ) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS pe2_proc;
END GENERATE gpe2;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold input port
-------------------------------------------------------------------------------
gpe3: IF (C_PROG_EMPTY_TYPE = 3) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH;
pe3_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) < pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) = pe_assert_val) THEN
IF (write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > pe_assert_val) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pe3_proc;
END GENERATE gpe3;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpe4: IF (C_PROG_EMPTY_TYPE = 4) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pe_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_ASSERT;
pe_negate_val <= PROG_EMPTY_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_NEGATE;
pe4_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr_pe) = pe_negate_val) AND write_only_q = '1') OR
(conv_integer(diff_pntr_pe) > pe_negate_val)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (conv_integer(diff_pntr_pe) <= (pe_assert_val)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > pe_negate_val) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pe4_proc;
END GENERATE gpe4;
PROG_EMPTY <= prog_empty_i;
END GENERATE gpe;
END GENERATE gpf_pe;
-------------------------------------------------------------------------------
-- overflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
g7s_ovflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= full_i AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g7s_ovflw;
g8s_ovflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= (WR_RST_BUSY OR full_i) AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g8s_ovflw;
END GENERATE govflw;
-------------------------------------------------------------------------------
-- underflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
g7s_unflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= empty_i and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g7s_unflw;
g8s_unflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= (RD_RST_BUSY OR empty_i) and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g8s_unflw;
END GENERATE gunflw;
-------------------------------------------------------------------------------
-- wr_ack_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (CLK,rst_i)
BEGIN
IF rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF srst_wrst_busy = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_EN = '1' THEN
IF full_i /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
-----------------------------------------------------------------------------
-- valid_i generation: Synchronous FIFO
-----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF srst_rrst_busy = '1' THEN
valid_i <= '0' after C_TCQ;
ELSE --srst_i=0
-- Setup default value for underflow and valid
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_i /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Delay Valid AND DOUT
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1, STD
-----------------------------------------------------------------------------
gnll_fifo1: IF (C_FIFO_TYPE < 2) GENERATE
gv0: IF (C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT = 0) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF (rst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
valid_d1 <= valid_i after C_TCQ;
IF (srst_rrst_busy = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv1: IF (C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT = 1) GENERATE
SIGNAL dout_rst_val_d2 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dout_rst_val_d1 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN
PROCESS ( CLK )
BEGIN
rst_delayed_sft1 <= rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
PROCESS (rst_delayed_sft4 ,rst_i, CLK )
BEGIN
IF (rst_delayed_sft4 = '1' OR rst_i = '1') THEN
valid_d1 <= '0' after C_TCQ;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
valid_d1 <= valid_i after C_TCQ;
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_delayed_sft4 , CLK )
BEGIN
IF (rst_delayed_sft4 = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
--valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
--ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
--valid_d1 <= valid_i after C_TCQ;
IF (srst_rrst_busy = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
--valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv1;
END GENERATE gnll_fifo1;
gv1: IF (C_FIFO_TYPE = 2 OR (NOT(C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)))) GENERATE
valid_d1 <= valid_i;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
END GENERATE gv1;
--END GENERATE gnll_fifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Preload Latency 0 (First-Word Fall-Through) Module
--#############################################################################
--#############################################################################
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fifo_generator_v13_0_1_bhv_preload0 IS
GENERIC (
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
WR_RST_BUSY : IN std_logic;
RD_RST_BUSY : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic := '0';
USERDBITERR : OUT std_logic := '0';
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0) := (OTHERS => '0')
);
END fifo_generator_v13_0_1_bhv_preload0;
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_preload0 IS
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
SIGNAL USERDATA_int : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
SIGNAL preloadstage1 : std_logic := '0';
SIGNAL preloadstage2 : std_logic := '0';
SIGNAL ram_valid_i : std_logic := '0';
SIGNAL read_data_valid_i : std_logic := '0';
SIGNAL ram_regout_en : std_logic := '0';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL empty_q : std_logic := '1';
SIGNAL rd_en_q : std_logic := '0';
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_empty_q : std_logic := '1';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
BEGIN -- behavioral
grst: IF (C_HAS_RST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE
rd_rst_i <= RD_RST;
end generate grst;
ngrst: IF (C_HAS_RST = 0 AND C_ENABLE_RST_SYNC = 1) GENERATE
rd_rst_i <= '0';
END GENERATE ngrst;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST OR WR_RST_BUSY OR RD_RST_BUSY;
END GENERATE gsrst;
--SRST
ngsrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
END GENERATE ngsrst;
gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
CONSTANT INVALID : std_logic_vector (1 downto 0) := "00";
CONSTANT STAGE1_VALID : std_logic_vector (1 downto 0) := "10";
CONSTANT STAGE2_VALID : std_logic_vector (1 downto 0) := "01";
CONSTANT BOTH_STAGES_VALID : std_logic_vector (1 downto 0) := "11";
SIGNAL curr_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
SIGNAL next_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
BEGIN
proc_fwft_fsm : PROCESS ( curr_fwft_state, RD_EN, FIFOEMPTY)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
IF (FIFOEMPTY = '0') THEN
next_fwft_state <= STAGE1_VALID;
ELSE --FIFOEMPTY = '1'
next_fwft_state <= INVALID;
END IF;
WHEN STAGE1_VALID =>
IF (FIFOEMPTY = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSE -- FIFOEMPTY = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN STAGE2_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= INVALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= STAGE1_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '0') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- FIFOEMPTY = '1' AND RD_EN = '0'
next_fwft_state <= STAGE2_VALID;
END IF;
WHEN BOTH_STAGES_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- RD_EN = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN OTHERS =>
next_fwft_state <= INVALID;
END CASE;
END PROCESS proc_fwft_fsm;
proc_fsm_reg: PROCESS (rd_rst_i, RD_CLK)
BEGIN
IF (rd_rst_i = '1') THEN
curr_fwft_state <= INVALID;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
curr_fwft_state <= INVALID AFTER C_TCQ;
ELSE
curr_fwft_state <= next_fwft_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_fsm_reg;
proc_regen: PROCESS (curr_fwft_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
STAGE2_REG_EN <= '0';
WHEN STAGE1_VALID =>
STAGE2_REG_EN <= '1';
WHEN STAGE2_VALID =>
STAGE2_REG_EN <= '0';
WHEN BOTH_STAGES_VALID =>
IF (RD_EN = '1') THEN
STAGE2_REG_EN <= '1';
ELSE
STAGE2_REG_EN <= '0';
END IF;
WHEN OTHERS =>
STAGE2_REG_EN <= '0';
END CASE;
END PROCESS proc_regen;
VALID_STAGES <= curr_fwft_state;
--------------------------------------------------------------------------------
-- preloadstage2 indicates that stage2 needs to be updated. This is true
-- whenever read_data_valid is false, and RAM_valid is true.
--------------------------------------------------------------------------------
preloadstage2 <= ram_valid_i AND (NOT read_data_valid_i OR RD_EN);
--------------------------------------------------------------------------------
-- preloadstage1 indicates that stage1 needs to be updated. This is true
-- whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
-- false (indicating that Stage1 needs updating), or preloadstage2 is active
-- (indicating that Stage2 is going to update, so Stage1, therefore, must
-- also be updated to keep it valid.
--------------------------------------------------------------------------------
preloadstage1 <= (((NOT ram_valid_i) OR preloadstage2) AND (NOT FIFOEMPTY));
--------------------------------------------------------------------------------
-- Calculate RAM_REGOUT_EN
-- The output registers are controlled by the ram_regout_en signal.
-- These registers should be updated either when the output in Stage2 is
-- invalid (preloadstage2), OR when the user is reading, in which case the
-- Stage2 value will go invalid unless it is replenished.
--------------------------------------------------------------------------------
ram_regout_en <= preloadstage2;
--------------------------------------------------------------------------------
-- Calculate RAM_RD_EN
-- RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
-- update the value in Stage1.
-- One case when this happens is when preloadstage1=true, which indicates
-- that the data in Stage1 or Stage2 is invalid, and needs to automatically
-- be updated.
-- The other case is when the user is reading from the FIFO, which guarantees
-- that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is
-- replinished by data from the memory. So, as long as the RAM has data in it,
-- a read of the RAM should occur.
--------------------------------------------------------------------------------
ram_rd_en <= (RD_EN AND NOT FIFOEMPTY) OR preloadstage1;
END GENERATE gnll_fifo;
gll_fifo: IF (C_FIFO_TYPE = 2) GENERATE
SIGNAL empty_d1 : STD_LOGIC := '1';
SIGNAL fe_of_empty : STD_LOGIC := '0';
SIGNAL curr_state : STD_LOGIC := '0';
SIGNAL next_state : STD_LOGIC := '0';
SIGNAL leaving_empty_fwft : STD_LOGIC := '0';
SIGNAL going_empty_fwft : STD_LOGIC := '0';
BEGIN
fsm_proc: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
next_state <= '1';
ELSE
next_state <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_state <= '0';
ELSE
next_state <= '1';
END IF;
WHEN OTHERS =>
next_state <= '0';
END CASE;
END PROCESS fsm_proc;
empty_reg: PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_d1 <= '1';
empty_i <= '1';
ram_valid_i <= '0';
curr_state <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
empty_d1 <= '1' AFTER C_TCQ;
empty_i <= '1' AFTER C_TCQ;
ram_valid_i <= '0' AFTER C_TCQ;
curr_state <= '0' AFTER C_TCQ;
ELSE
empty_d1 <= FIFOEMPTY AFTER C_TCQ;
curr_state <= next_state AFTER C_TCQ;
empty_i <= going_empty_fwft OR (NOT leaving_empty_fwft AND empty_i) AFTER C_TCQ;
ram_valid_i <= next_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_reg;
fe_of_empty <= empty_d1 AND (NOT FIFOEMPTY);
prege: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN OTHERS =>
ram_regout_en <= '0';
ram_rd_en <= '0';
END CASE;
END PROCESS prege;
ple: PROCESS (curr_state, fe_of_empty) -- Leaving Empty
BEGIN
CASE curr_state IS
WHEN '0' =>
leaving_empty_fwft <= fe_of_empty;
WHEN '1' =>
leaving_empty_fwft <= '1';
WHEN OTHERS =>
leaving_empty_fwft <= '0';
END CASE;
END PROCESS ple;
pge: PROCESS (curr_state, FIFOEMPTY, RD_EN) -- Going Empty
BEGIN
CASE curr_state IS
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
going_empty_fwft <= '1';
ELSE
going_empty_fwft <= '0';
END IF;
WHEN OTHERS =>
going_empty_fwft <= '0';
END CASE;
END PROCESS pge;
END GENERATE gll_fifo;
--------------------------------------------------------------------------------
-- Calculate ram_valid
-- ram_valid indicates that the data in Stage1 is valid.
--
-- If the RAM is being read from on this clock cycle (ram_rd_en=1), then
-- ram_valid is certainly going to be true.
-- If the RAM is not being read from, but the output registers are being
-- updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
-- therefore causing ram_valid to be false.
-- Otherwise, ram_valid will remain unchanged.
--------------------------------------------------------------------------------
gvalid: IF (C_FIFO_TYPE < 2) GENERATE
regout_valid: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_valid
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSE
IF ram_rd_en = '1' THEN
ram_valid_i <= '1' after C_TCQ;
ELSE
IF ram_regout_en = '1' THEN
ram_valid_i <= '0' after C_TCQ;
ELSE
ram_valid_i <= ram_valid_i after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS regout_valid;
END GENERATE gvalid;
--------------------------------------------------------------------------------
-- Calculate READ_DATA_VALID
-- READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
-- Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1,
-- such that the data in Stage1 is propogated into Stage2.
--------------------------------------------------------------------------------
regout_dvalid : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSE
read_data_valid_i <= ram_valid_i OR (read_data_valid_i AND NOT RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_dvalid;
-------------------------------------------------------------------------------
-- Calculate EMPTY
-- Defined as the inverse of READ_DATA_VALID
--
-- Description:
--
-- If read_data_valid_i indicates that the output is not valid,
-- and there is no valid data on the output of the ram to preload it
-- with, then we will report empty.
--
-- If there is no valid data on the output of the ram and we are
-- reading, then the FIFO will go empty.
--
-------------------------------------------------------------------------------
gempty: IF (C_FIFO_TYPE < 2) GENERATE
regout_empty : PROCESS (RD_CLK, rd_rst_i) --This is equivalent to (NOT read_data_valid_i)
BEGIN
IF (rd_rst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSE
empty_i <= (NOT ram_valid_i AND NOT read_data_valid_i) OR (NOT ram_valid_i AND RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_empty;
END GENERATE gempty;
regout_empty_q: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN --
empty_q <= empty_i after C_TCQ;
END IF;
END PROCESS regout_empty_q;
regout_rd_en: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
rd_en_q <= RD_EN after C_TCQ;
END IF;
END PROCESS regout_rd_en;
-------------------------------------------------------------------------------
-- Calculate user_almost_empty
-- user_almost_empty is defined such that, unless more words are written
-- to the FIFO, the next read will cause the FIFO to go EMPTY.
--
-- In most cases, whenever the output registers are updated (due to a user
-- read or a preload condition), then user_almost_empty will update to
-- whatever RAM_EMPTY is.
--
-- The exception is when the output is valid, the user is not reading, and
-- Stage1 is not empty. In this condition, Stage1 will be preloaded from the
-- memory, so we need to make sure user_almost_empty deasserts properly under
-- this condition.
-------------------------------------------------------------------------------
regout_aempty: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_empty
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSE
IF ((ram_regout_en = '1') OR (FIFOEMPTY = '0' AND read_data_valid_i = '1' AND RD_EN='0')) THEN
almost_empty_i <= FIFOEMPTY after C_TCQ;
END IF;
almost_empty_q <= almost_empty_i after C_TCQ;
END IF;
END IF;
END PROCESS regout_aempty;
USEREMPTY <= empty_i;
USERALMOSTEMPTY <= almost_empty_i;
FIFORDEN <= ram_rd_en;
RAMVALID <= ram_valid_i;
guvh: IF C_USERVALID_LOW=0 GENERATE
USERVALID <= read_data_valid_i;
END GENERATE guvh;
guvl: if C_USERVALID_LOW=1 GENERATE
USERVALID <= NOT read_data_valid_i;
END GENERATE guvl;
gufh: IF C_USERUNDERFLOW_LOW=0 GENERATE
USERUNDERFLOW <= empty_q AND rd_en_q;
END GENERATE gufh;
gufl: if C_USERUNDERFLOW_LOW=1 GENERATE
USERUNDERFLOW <= NOT (empty_q AND rd_en_q);
END GENERATE gufl;
glat0_nsafety: if C_EN_SAFETY_CKT=0 GENERATE
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END GENERATE glat0_nsafety;
glat0_safety: if C_EN_SAFETY_CKT=1 GENERATE
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN -- PROCESS regout_lat0
PROCESS ( RD_CLK )
BEGIN
rst_delayed_sft1 <= rd_rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2 ) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2 AND rst_delayed_sft4 = '1') THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1' and rd_rst_i = '0') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END GENERATE glat0_safety;
END behavioral;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for Conventional FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_bhv_as;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_bhv_ss;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the conventional
-- FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_INTERFACE_TYPE : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
WR_RST_I_OUT : OUT std_logic := '0';
RD_RST_I_OUT : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_conv;
-------------------------------------------------------------------------------
-- Definition of Parameters
-------------------------------------------------------------------------------
-- C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
-- C_COUNT_TYPE : --not used
-- C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
-- C_DEFAULT_VALUE : --not used
-- C_DIN_WIDTH : Width of DIN bus
-- C_DOUT_RST_VAL : Reset value of DOUT
-- C_DOUT_WIDTH : Width of DOUT bus
-- C_ENABLE_RLOCS : --not used
-- C_FAMILY : not used in bhv model
-- C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
-- C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
-- C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
-- C_HAS_BACKUP : --not used
-- C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
-- C_HAS_INT_CLK : not used in bhv model
-- C_HAS_MEMINIT_FILE : --not used
-- C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
-- C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
-- C_HAS_RD_RST : --not used
-- C_HAS_RST : 1=Core has Async Rst
-- C_HAS_SRST : 1=Core has Sync Rst
-- C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
-- C_HAS_VALID : 1=Core has VALID flag
-- C_HAS_WR_ACK : 1=Core has WR_ACK flag
-- C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
-- C_HAS_WR_RST : --not used
-- C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
-- 1=Common-Clock ShiftRam
-- 2=Indep. Clocks Bram/Dram
-- 3=Virtex-4 Built-in
-- 4=Virtex-5 Built-in
-- C_INIT_WR_PNTR_VAL : --not used
-- C_MEMORY_TYPE : 1=Block RAM
-- 2=Distributed RAM
-- 3=Shift RAM
-- 4=Built-in FIFO
-- C_MIF_FILE_NAME : --not used
-- C_OPTIMIZATION_MODE : --not used
-- C_OVERFLOW_LOW : 1=OVERFLOW active low
-- C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
-- C_PRELOAD_REGS : 1=Use output registers
-- C_PRIM_FIFO_TYPE : not used in bhv model
-- C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
-- C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
-- C_PROG_EMPTY_TYPE : 0=No programmable empty
-- 1=Single prog empty thresh constant
-- 2=Multiple prog empty thresh constants
-- 3=Single prog empty thresh input
-- 4=Multiple prog empty thresh inputs
-- C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
-- C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
-- C_PROG_FULL_TYPE : 0=No prog full
-- 1=Single prog full thresh constant
-- 2=Multiple prog full thresh constants
-- 3=Single prog full thresh input
-- 4=Multiple prog full thresh inputs
-- C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
-- C_RD_DEPTH : Depth of read interface (2^N)
-- C_RD_FREQ : not used in bhv model
-- C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
-- C_UNDERFLOW_LOW : 1=UNDERFLOW active low
-- C_USE_DOUT_RST : 1=Resets DOUT on RST
-- C_USE_ECC : not used in bhv model
-- C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
-- C_USE_FIFO16_FLAGS : not used in bhv model
-- C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
-- C_VALID_LOW : 1=VALID active low
-- C_WR_ACK_LOW : 1=WR_ACK active low
-- C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
-- C_WR_DEPTH : Depth of write interface (2^N)
-- C_WR_FREQ : not used in bhv model
-- C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
-- C_WR_RESPONSE_LATENCY : --not used
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- BACKUP : Not used
-- BACKUP_MARKER: Not used
-- CLK : Clock
-- DIN : Input data bus
-- PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
-- PROG_FULL_THRESH : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
-- RD_CLK : Read Domain Clock
-- RD_EN : Read enable
-- RD_RST : Not used
-- RST : Asynchronous Reset
-- SRST : Synchronous Reset
-- WR_CLK : Write Domain Clock
-- WR_EN : Write enable
-- WR_RST : Not used
-- INT_CLK : Internal Clock
-- ALMOST_EMPTY : One word remaining in FIFO
-- ALMOST_FULL : One empty space remaining in FIFO
-- DATA_COUNT : Number of data words in fifo( synchronous to CLK)
-- DOUT : Output data bus
-- EMPTY : Empty flag
-- FULL : Full flag
-- OVERFLOW : Last write rejected
-- PROG_EMPTY : Programmable Empty Flag
-- PROG_FULL : Programmable Full Flag
-- RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
-- UNDERFLOW : Last read rejected
-- VALID : Last read acknowledged, DOUT bus VALID
-- WR_ACK : Last write acknowledged
-- WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
-- SBITERR : Single Bit ECC Error Detected
-- DBITERR : Double Bit ECC Error Detected
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_conv IS
-----------------------------------------------------------------------------
-- FUNCTION two_comp
-- Returns a 2's complement value
-------------------------------------------------------------------------------
FUNCTION two_comp(
vect : std_logic_vector)
RETURN std_logic_vector IS
VARIABLE local_vect : std_logic_vector(vect'high DOWNTO 0);
VARIABLE toggle : integer := 0;
BEGIN
FOR i IN 0 TO vect'high LOOP
IF (toggle = 1) THEN
IF (vect(i) = '0') THEN
local_vect(i) := '1';
ELSE
local_vect(i) := '0';
END IF;
ELSE
local_vect(i) := vect(i);
IF (vect(i) = '1') THEN
toggle := 1;
END IF;
END IF;
END LOOP;
RETURN local_vect;
END two_comp;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic_vector
-- Returns a std_logic_vector for an integer value for a given width.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
IF (value < 0) THEN
running_value := -1 * value;
END IF;
FOR i IN 0 TO bitwidth-1 LOOP
IF running_value MOD 2 = 0 THEN
running_result(i) := '0';
ELSE
running_result(i) := '1';
END IF;
running_value := running_value/2;
END LOOP;
IF (value < 0) THEN -- find the 2s complement
RETURN two_comp(running_result);
ELSE
RETURN running_result;
END IF;
END int_2_std_logic_vector;
COMPONENT fifo_generator_v13_0_1_bhv_as
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_bhv_ss
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
RD_EN_USER : IN std_logic;
RST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
WR_RST_BUSY : IN std_logic := '0';
RD_RST_BUSY : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_ACK : OUT std_logic;
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_bhv_preload0
GENERIC (
C_DOUT_RST_VAL : string;
C_DOUT_WIDTH : integer;
C_HAS_RST : integer;
C_HAS_SRST : integer;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
WR_RST_BUSY : IN std_logic;
RD_RST_BUSY : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic;
USERDBITERR : OUT std_logic;
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
-- Constant to have clock to register delay
CONSTANT C_TCQ : time := 100 ps;
SIGNAL zero : std_logic := '0';
SIGNAL CLK_INT : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals for delayed input signals
-- All the input signals except Clock are delayed by 100 ps and then given to
-- the models.
-----------------------------------------------------------------------------
SIGNAL rst_delayed : std_logic := '0';
SIGNAL srst_delayed : std_logic := '0';
SIGNAL wr_rst_delayed : std_logic := '0';
SIGNAL rd_rst_delayed : std_logic := '0';
SIGNAL din_delayed : std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_en_delayed : std_logic := '0';
SIGNAL rd_en_delayed : std_logic := '0';
SIGNAL prog_empty_thresh_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_assert_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_negate_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_assert_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_negate_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL injectdbiterr_delayed : std_logic := '0';
SIGNAL injectsbiterr_delayed : std_logic := '0';
SIGNAL wr_rst_busy_i : std_logic := '0';
SIGNAL rd_rst_busy_i : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
SIGNAL rd_en_fifo_in : std_logic;
SIGNAL dout_fifo_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fifo_out : std_logic;
SIGNAL almost_empty_fifo_out : std_logic;
SIGNAL valid_fifo_out : std_logic;
SIGNAL underflow_fifo_out : std_logic;
SIGNAL rd_data_count_fifo_out : std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL wr_data_count_fifo_out : std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL data_count_fifo_out : std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL DATA_COUNT_FWFT : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL SS_FWFT_RD : std_logic := '0' ;
SIGNAL SS_FWFT_WR : std_logic := '0' ;
SIGNAL FULL_int : std_logic ;
SIGNAL almost_full_i : std_logic ;
SIGNAL prog_full_i : std_logic ;
SIGNAL dout_p0_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
signal valid_p0_out : std_logic;
signal empty_p0_out : std_logic;
signal underflow_p0_out : std_logic;
signal almost_empty_p0_out : std_logic;
signal empty_p0_out_q : std_logic;
signal almost_empty_p0_out_q : std_logic;
SIGNAL ram_valid : std_logic; --Internal signal used to monitor the
--ram_valid state
signal rst_fwft : std_logic;
signal sbiterr_fifo_out : std_logic;
signal dbiterr_fifo_out : std_logic;
signal wr_rst_i : std_logic := '0';
signal rd_rst_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal rst_full_gen_i : std_logic := '0';
signal rst_full_ff_i : std_logic := '0';
signal rst_2_sync : std_logic := '0';
signal rst_2_sync_safety : std_logic := '0';
signal clk_2_sync : std_logic := '0';
signal clk_2_sync_safety : std_logic := '0';
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION log2roundup
-- Returns a log2 of the input value
-----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
CONSTANT FULL_FLAGS_RST_VAL : integer := if_then_else((C_HAS_SRST = 1),0,C_FULL_FLAGS_RST_VAL);
CONSTANT IS_WR_PNTR_WIDTH_CORRECT : integer := if_then_else((C_WR_PNTR_WIDTH = log2roundup(C_WR_DEPTH)),1,0);
CONSTANT IS_RD_PNTR_WIDTH_CORRECT : integer := if_then_else((C_RD_PNTR_WIDTH = log2roundup(C_RD_DEPTH)),1,0);
BEGIN
rst_delayed <= RST AFTER C_TCQ;
srst_delayed <= SRST AFTER C_TCQ;
wr_rst_delayed <= WR_RST AFTER C_TCQ;
rd_rst_delayed <= RD_RST AFTER C_TCQ;
din_delayed <= DIN AFTER C_TCQ;
wr_en_delayed <= WR_EN AFTER C_TCQ;
rd_en_delayed <= RD_EN AFTER C_TCQ;
prog_empty_thresh_delayed <= PROG_EMPTY_THRESH AFTER C_TCQ;
prog_empty_thresh_assert_delayed <= PROG_EMPTY_THRESH_ASSERT AFTER C_TCQ;
prog_empty_thresh_negate_delayed <= PROG_EMPTY_THRESH_NEGATE AFTER C_TCQ;
prog_full_thresh_delayed <= PROG_FULL_THRESH AFTER C_TCQ;
prog_full_thresh_assert_delayed <= PROG_FULL_THRESH_ASSERT AFTER C_TCQ;
prog_full_thresh_negate_delayed <= PROG_FULL_THRESH_NEGATE AFTER C_TCQ;
injectdbiterr_delayed <= INJECTDBITERR AFTER C_TCQ;
injectsbiterr_delayed <= INJECTSBITERR AFTER C_TCQ;
--Assign Ground Signal
zero <= '0';
ASSERT (C_MEMORY_TYPE /= 4) REPORT "FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado." SEVERITY FAILURE;
--
ASSERT (C_IMPLEMENTATION_TYPE /= 2) REPORT "WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information." SEVERITY NOTE;
ASSERT (IS_WR_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH." SEVERITY FAILURE;
ASSERT (IS_RD_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH." SEVERITY FAILURE;
gen_ss : IF ((C_IMPLEMENTATION_TYPE = 0) OR (C_IMPLEMENTATION_TYPE = 1) OR (C_MEMORY_TYPE = 4)) GENERATE
fgss : fifo_generator_v13_0_1_bhv_ss
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => if_then_else(C_MEMORY_TYPE = 4, 1, C_MEMORY_TYPE),
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
CLK => CLK,
DIN => din_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
RD_EN => rd_en_fifo_in,
RD_EN_USER => rd_en_delayed,
RST => rst_i,
SRST => srst_delayed,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_EN => wr_en_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
ALMOST_EMPTY => almost_empty_fifo_out,
ALMOST_FULL => almost_full_i,
DATA_COUNT => data_count_fifo_out,
DOUT => dout_fifo_out,
EMPTY => empty_fifo_out,
FULL => FULL_int,
OVERFLOW => OVERFLOW,
PROG_EMPTY => PROG_EMPTY,
PROG_FULL => prog_full_i,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
VALID => valid_fifo_out,
WR_ACK => WR_ACK,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_ss;
gen_as : IF (C_IMPLEMENTATION_TYPE = 2 OR C_FIFO_TYPE = 3) GENERATE
fgas : fifo_generator_v13_0_1_bhv_as
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
WR_CLK => WR_CLK,
RD_CLK => RD_CLK,
RST => rst_i,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_RST => wr_rst_i,
RD_RST => rd_rst_i,
DIN => din_delayed,
RD_EN => rd_en_fifo_in,
WR_EN => wr_en_delayed,
RD_EN_USER => rd_en_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
DOUT => dout_fifo_out,
FULL => FULL_int,
ALMOST_FULL => almost_full_i,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_fifo_out,
ALMOST_EMPTY => almost_empty_fifo_out,
VALID => valid_fifo_out,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
PROG_FULL => prog_full_i,
PROG_EMPTY => PROG_EMPTY,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_as;
ALMOST_FULL <= almost_full_i;
PROG_FULL <= prog_full_i;
WR_RST_I_OUT <= wr_rst_i;
RD_RST_I_OUT <= rd_rst_i;
-------------------------------------------------------------------------
-- Connect internal clock used for FWFT logic based on C_COMMON_CLOCK ---
-------------------------------------------------------------------------
clock_fwft_common: IF (C_COMMON_CLOCK=1 ) GENERATE
CLK_INT <= CLK;
END GENERATE clock_fwft_common;
clock_fwft: IF (C_COMMON_CLOCK= 0 ) GENERATE
CLK_INT <= RD_CLK;
END GENERATE clock_fwft;
-----------------------------------------------------------------------------
-- Connect Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
latnrm: IF (C_PRELOAD_LATENCY=1 OR C_PRELOAD_LATENCY=2 OR C_FIFO_TYPE = 3) GENERATE
rd_en_fifo_in <= rd_en_delayed;
DOUT <= dout_fifo_out;
VALID <= valid_fifo_out;
EMPTY <= empty_fifo_out;
ALMOST_EMPTY <= almost_empty_fifo_out;
UNDERFLOW <= underflow_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
WR_DATA_COUNT <= wr_data_count_fifo_out;
SBITERR <= sbiterr_fifo_out;
DBITERR <= dbiterr_fifo_out;
END GENERATE latnrm;
lat0: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND C_FIFO_TYPE /= 3) GENERATE
SIGNAL sbiterr_fwft : STD_LOGIC := '0';
SIGNAL dbiterr_fwft : STD_LOGIC := '0';
SIGNAL rd_en_to_fwft_fifo : STD_LOGIC := '0';
SIGNAL dout_fwft : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fwft : STD_LOGIC := '0';
SIGNAL valid_stages_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL stage2_reg_en_i : STD_LOGIC := '0';
BEGIN
rst_fwft <= rd_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
lat0logic : fifo_generator_v13_0_1_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
RD_EN => rd_en_to_fwft_fifo,
FIFOEMPTY => empty_fifo_out,
FIFODATA => dout_fifo_out,
FIFOSBITERR => sbiterr_fifo_out,
FIFODBITERR => dbiterr_fifo_out,
USERDATA => dout_fwft,
USERVALID => valid_p0_out,
USEREMPTY => empty_fwft,
USERALMOSTEMPTY => almost_empty_p0_out,
USERUNDERFLOW => underflow_p0_out,
RAMVALID => ram_valid, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_fifo_in,
USERSBITERR => sbiterr_fwft,
USERDBITERR => dbiterr_fwft,
STAGE2_REG_EN => stage2_reg_en_i,
VALID_STAGES => valid_stages_i
);
gberr_non_pkt_fifo: IF (C_FIFO_TYPE /= 1) GENERATE
VALID <= valid_p0_out;
ALMOST_EMPTY <= almost_empty_p0_out;
UNDERFLOW <= underflow_p0_out;
SBITERR <= sbiterr_fwft;
DBITERR <= dbiterr_fwft;
dout_p0_out <= dout_fwft;
rd_en_to_fwft_fifo <= rd_en_delayed;
empty_p0_out <= empty_fwft;
END GENERATE gberr_non_pkt_fifo;
rdcg: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND C_COMMON_CLOCK = 0) GENERATE
eclk: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk;
rcsproc: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(1, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc;
END GENERATE rdcg;
rdcg1: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND C_COMMON_CLOCK = 0) GENERATE
eclk1: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk1;
rcsproc1: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc1;
END GENERATE rdcg1;
nrdcg: IF (C_USE_FWFT_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= rd_data_count_fifo_out;
END GENERATE nrdcg;
WR_DATA_COUNT <= wr_data_count_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
---------------------------------------------------
-- logics for common-clock data count with fwft
-- For common-clock FIFOs with FWFT, data count
-- is calculated as an up-down counter to maintain
-- accuracy.
---------------------------------------------------
grd_en_npkt: IF (C_FIFO_TYPE /= 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= rd_en_delayed AND NOT valid_p0_out ;
END GENERATE ngfwft_rd;
END GENERATE grd_en_npkt;
grd_en_pkt: IF (C_FIFO_TYPE = 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND (NOT valid_p0_out);
END GENERATE ngfwft_rd;
END GENERATE grd_en_pkt;
SS_FWFT_WR <= wr_en_delayed AND (NOT FULL_int) ;
cc_data_cnt: IF (C_HAS_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
count_fwft: PROCESS (CLK, rst_fwft)
BEGIN
IF (rst_fwft = '1' AND C_HAS_RST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF ((srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') AND C_HAS_SRST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSE
IF (SS_FWFT_WR = '0' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
ELSIF (SS_FWFT_WR = '0' and SS_FWFT_RD ='1') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 after C_TCQ;
ELSIF (SS_FWFT_WR = '1' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 after C_TCQ;
ELSE
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
END IF ;
END IF;
END IF;
END PROCESS count_fwft;
END GENERATE cc_data_cnt;
----------------------------------------------
DOUT <= dout_p0_out;
EMPTY <= empty_p0_out;
gpkt_fifo_fwft: IF (C_FIFO_TYPE = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_plus1 : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_reg : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL eop_at_stage2 : STD_LOGIC := '0';
SIGNAL ram_pkt_empty : STD_LOGIC := '0';
SIGNAL ram_pkt_empty_d1 : STD_LOGIC := '0';
SIGNAL pkt_ready_to_read : STD_LOGIC := '0';
SIGNAL fwft_stage1_valid : STD_LOGIC := '0';
SIGNAL fwft_stage2_valid : STD_LOGIC := '0';
SIGNAL rd_en_2_stage2 : STD_LOGIC := '0';
SIGNAL ram_wr_en_pkt_fifo : STD_LOGIC := '0';
SIGNAL wr_eop : STD_LOGIC := '0';
SIGNAL dummy_wr_eop : STD_LOGIC := '0';
SIGNAL ram_rd_en_compare : STD_LOGIC := '0';
SIGNAL partial_packet : STD_LOGIC := '0';
SIGNAL wr_rst_fwft_pkt_fifo : STD_LOGIC := '0';
SIGNAL stage1_eop : STD_LOGIC := '0';
SIGNAL stage1_eop_d1 : STD_LOGIC := '0';
SIGNAL rd_en_fifo_in_d1 : STD_LOGIC := '0';
BEGIN
wr_rst_fwft_pkt_fifo <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
-- Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
-- When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
-- When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
-- write packet count
gdummy_wr_eop: IF (C_AXI_TYPE = 0) GENERATE
SIGNAL packet_empty_wr : std_logic := '1';
BEGIN
proc_dummy_wr_eop: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
partial_packet <= '0';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed = '1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
partial_packet <= '0' AFTER C_TCQ;
ELSE
IF (almost_full_i = '1' AND ram_wr_en_pkt_fifo = '1' AND packet_empty_wr = '1' AND din_delayed(0) = '0') THEN
partial_packet <= '1' AFTER C_TCQ;
ELSE
IF (partial_packet = '1' AND din_delayed(0) = '1' AND ram_wr_en_pkt_fifo = '1') THEN
partial_packet <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS proc_dummy_wr_eop;
dummy_wr_eop <= almost_full_i AND ram_wr_en_pkt_fifo AND packet_empty_wr AND (NOT din_delayed(0)) AND (NOT partial_packet);
-- Synchronize the packet EMPTY in WR clock domain to generate the dummy WR_EOP
gpkt_empty_sync: IF (C_COMMON_CLOCK = 0) GENERATE
TYPE pkt_empty_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE-1) OF STD_LOGIC;
SIGNAL pkt_empty_sync : pkt_empty_array := (OTHERS => '1');
BEGIN
proc_empty_sync: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
pkt_empty_sync <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
pkt_empty_sync <= pkt_empty_sync(1 to C_SYNCHRONIZER_STAGE-1) & empty_p0_out AFTER C_TCQ;
END IF;
END PROCESS proc_empty_sync;
packet_empty_wr <= pkt_empty_sync(0);
END GENERATE gpkt_empty_sync;
gnpkt_empty_sync: IF (C_COMMON_CLOCK = 1) GENERATE
packet_empty_wr <= empty_p0_out;
END GENERATE gnpkt_empty_sync;
END GENERATE gdummy_wr_eop;
proc_stage1_eop: PROCESS (rst_fwft, CLK_INT)
BEGIN
IF (rst_fwft = '1') THEN
stage1_eop_d1 <= '0';
rd_en_fifo_in_d1 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed = '1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
stage1_eop_d1 <= '0' AFTER C_TCQ;
rd_en_fifo_in_d1 <= '0' AFTER C_TCQ;
ELSE
stage1_eop_d1 <= stage1_eop AFTER C_TCQ;
rd_en_fifo_in_d1 <= rd_en_fifo_in AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_stage1_eop;
stage1_eop <= dout_fifo_out(0) WHEN (rd_en_fifo_in_d1 = '1') ELSE stage1_eop_d1;
ram_wr_en_pkt_fifo <= wr_en_delayed AND (NOT FULL_int);
wr_eop <= ram_wr_en_pkt_fifo AND ((din_delayed(0) AND (NOT partial_packet)) OR dummy_wr_eop);
ram_rd_en_compare <= stage2_reg_en_i AND stage1_eop;
pkt_fifo_fwft : fifo_generator_v13_0_1_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => 2 -- Enable low latency fwft logic
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
RD_EN => rd_en_delayed,
FIFOEMPTY => pkt_ready_to_read,
FIFODATA => dout_fwft,
FIFOSBITERR => sbiterr_fwft,
FIFODBITERR => dbiterr_fwft,
USERDATA => dout_p0_out,
USERVALID => OPEN,
USEREMPTY => empty_p0_out,
USERALMOSTEMPTY => OPEN,
USERUNDERFLOW => OPEN,
RAMVALID => OPEN, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_2_stage2,
USERSBITERR => SBITERR,
USERDBITERR => DBITERR,
STAGE2_REG_EN => OPEN,
VALID_STAGES => OPEN
);
pkt_ready_to_read <= NOT ((ram_pkt_empty NOR empty_fwft) AND ((valid_stages_i(0) AND valid_stages_i(1)) OR eop_at_stage2));
rd_en_to_fwft_fifo <= NOT empty_fwft AND rd_en_2_stage2;
pregsm : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
eop_at_stage2 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (stage2_reg_en_i = '1') THEN
eop_at_stage2 <= stage1_eop AFTER C_TCQ;
END IF;
END IF;
END PROCESS pregsm;
-----------------------------------------------------------------------------
-- Write and Read Packet Count
-----------------------------------------------------------------------------
proc_wr_pkt_cnt: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
wr_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (wr_eop = '1') THEN
wr_pkt_count <= wr_pkt_count + int_2_std_logic_vector(1,C_WR_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_wr_pkt_cnt;
grss_pkt_cnt : IF C_COMMON_CLOCK = 1 GENERATE
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count <= (OTHERS => '0');
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH);
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
rd_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
ELSIF (stage2_reg_en_i = '1' AND stage1_eop = '1') THEN
rd_pkt_count <= rd_pkt_count + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
rd_pkt_count_plus1 <= rd_pkt_count_plus1 + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (SRST='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
ELSE
IF ((rd_pkt_count = wr_pkt_count) AND wr_eop = '1') THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count_plus1 = wr_pkt_count) AND wr_eop = '0' AND almost_full_i = '0' AND ram_rd_en_compare = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS proc_pkt_empty;
END GENERATE grss_pkt_cnt;
gras_pkt_cnt : IF C_COMMON_CLOCK = 0 GENERATE
TYPE wr_pkt_cnt_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pkt_count_q : wr_pkt_cnt_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pkt_count_b2g : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_pkt_count_rd : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
proc_wr_pkt_cnt_b2g: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_b2g <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_pkt_count_b2g <= wr_pkt_count AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_b2g;
-- Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
proc_wr_pkt_cnt_rd: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_q <= (OTHERS => (OTHERS => '0'));
wr_pkt_count_rd <= (OTHERS => '0');
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
wr_pkt_count_q <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-2 DOWNTO 0) & wr_pkt_count_b2g AFTER C_TCQ;
wr_pkt_count_rd <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-1) AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_rd;
rd_pkt_count <= rd_pkt_count_reg + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH)
WHEN (stage1_eop = '1') ELSE rd_pkt_count_reg;
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count_reg <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (rd_en_fifo_in = '1') THEN
rd_pkt_count_reg <= rd_pkt_count AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty_as : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (rd_pkt_count /= wr_pkt_count_rd) THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count = wr_pkt_count_rd) AND stage2_reg_en_i = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_pkt_empty_as;
END GENERATE gras_pkt_cnt;
END GENERATE gpkt_fifo_fwft;
END GENERATE lat0;
gdc_fwft: IF (C_HAS_DATA_COUNT = 1) GENERATE
begin
ss_count: IF ((NOT ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0)) ) OR
(C_USE_FWFT_DATA_COUNT = 0) )GENERATE
begin
DATA_COUNT <= data_count_fifo_out ;
end generate ss_count ;
ss_count_fwft1: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1) ) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO 0) ;
end generate ss_count_fwft1 ;
ss_count_fwft2: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1)) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1) ;
end generate ss_count_fwft2 ;
end generate gdc_fwft;
FULL <= FULL_int;
-------------------------------------------------------------------------------
-- If there is a reset input, generate internal reset signals
-- The latency of reset will match the core behavior
-------------------------------------------------------------------------------
--Single RST
grst_sync : IF (C_ENABLE_RST_SYNC = 1 OR C_FIFO_TYPE = 3) GENERATE
grst : IF (C_HAS_RST = 1) GENERATE
gic_rst : IF (C_COMMON_CLOCK = 0 OR C_FIFO_TYPE = 3) GENERATE
SIGNAL rd_rst_asreg : std_logic:= '0';
SIGNAL rd_rst_asreg_d1 : std_logic:= '0';
SIGNAL rd_rst_asreg_d2 : std_logic:= '0';
SIGNAL rd_rst_comb : std_logic:= '0';
SIGNAL rd_rst_reg : std_logic:= '0';
SIGNAL wr_rst_asreg : std_logic:= '0';
SIGNAL wr_rst_asreg_d1 : std_logic:= '0';
SIGNAL wr_rst_asreg_d2 : std_logic:= '0';
SIGNAL wr_rst_comb : std_logic:= '0';
SIGNAL wr_rst_reg : std_logic:= '0';
SIGNAL rst_active : STD_LOGIC := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
BEGIN
PROCESS (WR_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
wr_rst_asreg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
IF (wr_rst_asreg_d1 = '1') THEN
wr_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_asreg_d1 <= wr_rst_asreg after C_TCQ;
wr_rst_asreg_d2 <= wr_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (wr_rst_asreg, wr_rst_asreg_d2)
BEGIN
wr_rst_comb <= NOT wr_rst_asreg_d2 AND wr_rst_asreg;
END PROCESS;
PROCESS (WR_CLK, wr_rst_comb)
BEGIN
IF (wr_rst_comb = '1') THEN
wr_rst_reg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event and WR_CLK = '1') THEN
rst_delayed_d1 <= rst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (wr_rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= rst_active after C_TCQ;
END IF;
END IF;
END PROCESS;
PROCESS (RD_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rd_rst_asreg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
IF (rd_rst_asreg_d1 = '1') THEN
rd_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_asreg_d1 <= rd_rst_asreg after C_TCQ;
rd_rst_asreg_d2 <= rd_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rd_rst_asreg, rd_rst_asreg_d2)
BEGIN
rd_rst_comb <= NOT rd_rst_asreg_d2 AND rd_rst_asreg;
END PROCESS;
PROCESS (RD_CLK, rd_rst_comb)
BEGIN
IF (rd_rst_comb = '1') THEN
rd_rst_reg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
wr_rst_i <= wr_rst_reg;
rd_rst_i <= rd_rst_reg;
wr_rst_busy <= '0';
wr_rst_busy_i <= '0';
rd_rst_busy <= '0';
rd_rst_busy_i <= '0';
END GENERATE gic_rst;
gcc_rst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
PROCESS (CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rst_asreg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
IF (rst_asreg_d1 = '1') THEN
rst_asreg <= '0' after C_TCQ;
ELSE
rst_asreg <= rst_asreg after C_TCQ;
END IF;
END IF;
IF (CLK'event and CLK = '1') THEN
rst_asreg_d1 <= rst_asreg after C_TCQ;
rst_asreg_d2 <= rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_asreg, rst_asreg_d2)
BEGIN
rst_comb <= NOT rst_asreg_d2 AND rst_asreg;
END PROCESS;
PROCESS (CLK, rst_comb)
BEGIN
IF (rst_comb = '1') THEN
rst_reg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
rst_i <= rst_reg;
wr_rst_busy <= '0';
wr_rst_busy_i <= '0';
rd_rst_busy <= '0';
rd_rst_busy_i <= '0';
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK = '1') THEN
rst_delayed_d1 <= rst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= rst_reg after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gcc_rst;
END GENERATE grst;
gnrst : IF (C_HAS_RST = 0) GENERATE
wr_rst_i <= '0';
rd_rst_i <= '0';
rst_i <= '0';
END GENERATE gnrst;
gsrst : IF (C_HAS_SRST = 1) GENERATE
gcc_srst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
g8s_cc_srst: IF (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus") GENERATE
SIGNAL wr_rst_reg : STD_LOGIC := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
BEGIN
prst: PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (wr_rst_reg = '0' AND srst_delayed = '1') THEN
wr_rst_reg <= '1';
ELSE
IF (wr_rst_reg = '1') THEN
wr_rst_reg <= '0';
ELSE
wr_rst_reg <= wr_rst_reg;
END IF;
END IF;
END IF;
END PROCESS;
rst_i <= wr_rst_reg;
rd_rst_busy <= wr_rst_reg;
rd_rst_busy_i <= wr_rst_reg;
wr_rst_busy <= wr_rst_reg WHEN (C_MEMORY_TYPE /= 4) ELSE rst_active_i;
wr_rst_busy_i <= wr_rst_reg WHEN (C_MEMORY_TYPE /= 4) ELSE rst_active_i;
rst_full_ff_i <= wr_rst_reg;
rst_full_gen_i <= rst_active_i WHEN (C_FULL_FLAGS_RST_VAL = 1) ELSE '0';
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK = '1') THEN
rst_delayed_d1 <= srst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (wr_rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= wr_rst_reg after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE g8s_cc_srst;
END GENERATE gcc_srst;
END GENERATE gsrst;
END GENERATE grst_sync;
gnrst_sync : IF (C_ENABLE_RST_SYNC = 0) GENERATE
wr_rst_i <= wr_rst_delayed;
rd_rst_i <= rd_rst_delayed;
rst_i <= '0';
END GENERATE gnrst_sync;
rst_2_sync <= rst_delayed WHEN (C_ENABLE_RST_SYNC = 1) ELSE wr_rst_delayed;
rst_2_sync_safety <= RST WHEN (C_ENABLE_RST_SYNC = 1) ELSE RD_RST;
clk_2_sync <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE WR_CLK;
clk_2_sync_safety <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE RD_CLK;
grst_safety_ckt: IF (C_EN_SAFETY_CKT = 1 AND C_INTERFACE_TYPE = 0) GENERATE
SIGNAL rst_d1_safety : STD_LOGIC := '1';
SIGNAL rst_d2_safety : STD_LOGIC := '1';
SIGNAL rst_d3_safety : STD_LOGIC := '1';
SIGNAL rst_d4_safety : STD_LOGIC := '1';
SIGNAL rst_d5_safety : STD_LOGIC := '1';
SIGNAL rst_d6_safety : STD_LOGIC := '1';
SIGNAL rst_d7_safety : STD_LOGIC := '1';
BEGIN
prst: PROCESS (rst_2_sync_safety, clk_2_sync_safety)
BEGIN
IF (rst_2_sync_safety = '1') THEN
rst_d1_safety <= '1';
rst_d2_safety <= '1';
rst_d3_safety <= '1';
rst_d4_safety <= '1';
rst_d5_safety <= '1';
rst_d6_safety <= '1';
rst_d7_safety <= '1';
ELSIF (clk_2_sync_safety'event AND clk_2_sync_safety = '1') THEN
rst_d1_safety <= '0' AFTER C_TCQ;
rst_d2_safety <= rst_d1_safety AFTER C_TCQ;
rst_d3_safety <= rst_d2_safety AFTER C_TCQ;
rst_d4_safety <= rst_d3_safety AFTER C_TCQ;
rst_d5_safety <= rst_d4_safety AFTER C_TCQ;
rst_d6_safety <= rst_d5_safety AFTER C_TCQ;
rst_d7_safety <= rst_d6_safety AFTER C_TCQ;
END IF;
END PROCESS prst;
assert_safety: PROCESS (rst_d7_safety, wr_en)
BEGIN
IF(rst_d7_safety = '1' AND wr_en = '1') THEN
assert false
report "A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled"
severity warning;
END IF;
END PROCESS assert_safety;
END GENERATE grst_safety_ckt;
grstd1 : IF ((C_HAS_RST = 1 OR C_HAS_SRST = 1 OR C_ENABLE_RST_SYNC = 0)) GENERATE
-- RST_FULL_GEN replaces the reset falling edge detection used to de-assert
-- FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
-- RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
-- PROG_FULL
grst_full: IF (C_FULL_FLAGS_RST_VAL = 1) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
SIGNAL rst_d3 : STD_LOGIC := '1';
SIGNAL rst_d4 : STD_LOGIC := '1';
SIGNAL rst_d5 : STD_LOGIC := '1';
BEGIN
grst_f: IF (C_HAS_SRST = 0) GENERATE
prst: PROCESS (rst_2_sync, clk_2_sync)
BEGIN
IF (rst_2_sync = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
rst_d3 <= '1';
rst_d4 <= '1';
rst_d5 <= '1';
ELSIF (clk_2_sync'event AND clk_2_sync = '1') THEN
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_d4 <= rst_d3 AFTER C_TCQ;
rst_d5 <= rst_d4 AFTER C_TCQ;
END IF;
END PROCESS prst;
g_nsafety_ckt: IF ((C_EN_SAFETY_CKT = 0) ) GENERATE
rst_full_gen_i <= rst_d3;
END GENERATE g_nsafety_ckt;
g_safety_ckt: IF (C_EN_SAFETY_CKT = 1 ) GENERATE
rst_full_gen_i <= rst_d5;
END GENERATE g_safety_ckt;
rst_full_ff_i <= rst_d2;
END GENERATE grst_f;
ngrst_f: IF (C_HAS_SRST = 1) GENERATE
prst: PROCESS (clk_2_sync)
BEGIN
IF (clk_2_sync'event AND clk_2_sync = '1') THEN
IF (srst_delayed = '1') THEN
rst_d1 <= '1' AFTER C_TCQ;
rst_d2 <= '1' AFTER C_TCQ;
rst_d3 <= '1' AFTER C_TCQ;
rst_full_gen_i <= '0' AFTER C_TCQ;
ELSE
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_full_gen_i <= rst_d3 AFTER C_TCQ;
END IF;
END IF;
END PROCESS prst;
rst_full_ff_i <= '0';
END GENERATE ngrst_f;
END GENERATE grst_full;
gnrst_full: IF (C_FULL_FLAGS_RST_VAL = 0) GENERATE
rst_full_gen_i <= '0';
rst_full_ff_i <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i;
END GENERATE gnrst_full;
END GENERATE grstd1;
END behavioral;
-------------------------------------------------------------------------------
--
-- Register Slice
-- Register one AXI channel on forward and/or reverse signal path
--
----------------------------------------------------------------------------
--
-- Structure:
-- reg_slice
--
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fifo_generator_v13_0_1_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END fifo_generator_v13_0_1_axic_reg_slice;
ARCHITECTURE xilinx OF fifo_generator_v13_0_1_axic_reg_slice IS
SIGNAL storage_data1 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_ready_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL m_valid_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL areset_d1 : STD_LOGIC := '0'; -- Reset delay register
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
-- Constant to have clock to register delay
CONSTANT TFF : time := 100 ps;
BEGIN
--------------------------------------------------------------------
--
-- Both FWD and REV mode
--
--------------------------------------------------------------------
gfwd_rev: IF (C_REG_CONFIG = 0) GENERATE
CONSTANT ZERO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT ONE : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
CONSTANT TWO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
SIGNAL state : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL storage_data2 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL load_s1 : STD_LOGIC;
SIGNAL load_s2 : STD_LOGIC;
SIGNAL load_s1_from_s2 : BOOLEAN;
BEGIN
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with either slave side data or from storage2
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s1 = '1') THEN
IF (load_s1_from_s2) THEN
storage_data1 <= storage_data2 AFTER TFF;
ELSE
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Load storage2 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s2 = '1') THEN
storage_data2 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
-- Always load s2 on a valid transaction even if it's unnecessary
load_s2 <= S_VALID AND s_ready_i;
-- Loading s1
PROCESS(state,S_VALID,M_READY)
BEGIN
IF ((state = ZERO AND S_VALID = '1') OR -- Load when empty on slave transaction
-- Load when ONE if we both have read and write at the same time
(state = ONE AND S_VALID = '1' AND M_READY = '1') OR
-- Load when TWO and we have a transaction on Master side
(state = TWO AND M_READY = '1')) THEN
load_s1 <= '1';
ELSE
load_s1 <= '0';
END IF;
END PROCESS;
load_s1_from_s2 <= (state = TWO);
-- State Machine for handling output signals
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
state <= ZERO AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSE
CASE state IS
WHEN ZERO => -- No transaction stored locally
IF (S_VALID = '1') THEN -- Got one so move to ONE
state <= ONE AFTER TFF;
END IF;
WHEN ONE => -- One transaction stored locally
IF (M_READY = '1' AND S_VALID = '0') THEN -- Read out one so move to ZERO
state <= ZERO AFTER TFF;
END IF;
IF (M_READY = '0' AND S_VALID = '1') THEN -- Got another one so move to TWO
state <= TWO AFTER TFF;
s_ready_i <= '0' AFTER TFF;
END IF;
WHEN TWO => -- TWO transaction stored locally
IF (M_READY = '1') THEN -- Read out one so move to ONE
state <= ONE AFTER TFF;
s_ready_i <= '1' AFTER TFF;
END IF;
WHEN OTHERS =>
state <= state AFTER TFF;
END CASE;
END IF;
END IF;
END PROCESS;
m_valid_i <= state(0);
END GENERATE gfwd_rev;
--------------------------------------------------------------------
--
-- C_REG_CONFIG = 1
-- Light-weight mode.
-- 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
-- Operates same as 1-deep FIFO
--
--------------------------------------------------------------------
gfwd_rev_pipeline1: IF (C_REG_CONFIG = 1) GENERATE
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSIF (m_valid_i = '1' AND M_READY = '1') THEN
s_ready_i <= '1' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (S_VALID = '1' AND s_ready_i = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '1' AFTER TFF;
END IF;
IF (m_valid_i = '0') THEN
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
END GENERATE gfwd_rev_pipeline1;
end xilinx;-- reg_slice
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for AXI
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_misc.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_conv;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the AXI FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_vhdl_beh IS
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "virtex7";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_PIPELINE_REG : integer := 0;
C_POWER_SAVING_MODE : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_AXI_LEN_WIDTH : integer := 8;
C_AXI_LOCK_WIDTH : integer := 2;
C_HAS_AXI_ID : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 1;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8;
C_AXIS_TDEST_WIDTH : integer := 4;
C_AXIS_TUSER_WIDTH : integer := 4;
C_AXIS_TSTRB_WIDTH : integer := 4;
C_AXIS_TKEEP_WIDTH : integer := 4;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 5 = Common Clock Built-in FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- AXI Built-in FIFO Primitive Type
-- 512x36, 1kx18, 2kx9, 4kx4, etc
C_PRIM_FIFO_TYPE_WACH : string := "512x36";
C_PRIM_FIFO_TYPE_WDCH : string := "512x36";
C_PRIM_FIFO_TYPE_WRCH : string := "512x36";
C_PRIM_FIFO_TYPE_RACH : string := "512x36";
C_PRIM_FIFO_TYPE_RDCH : string := "512x36";
C_PRIM_FIFO_TYPE_AXIS : string := "512x36";
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
-- 0: No Programmable FULL
-- 1: Single Programmable FULL Threshold Constant
-- 3: Single Programmable FULL Threshold Input Port
C_PROG_FULL_TYPE_WACH : integer := 5;
C_PROG_FULL_TYPE_WDCH : integer := 5;
C_PROG_FULL_TYPE_WRCH : integer := 5;
C_PROG_FULL_TYPE_RACH : integer := 5;
C_PROG_FULL_TYPE_RDCH : integer := 5;
C_PROG_FULL_TYPE_AXIS : integer := 5;
-- Single Programmable FULL Threshold Constant Assert Value
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
-- 0: No Programmable EMPTY
-- 1: Single Programmable EMPTY Threshold Constant
-- 3: Single Programmable EMPTY Threshold Input Port
C_PROG_EMPTY_TYPE_WACH : integer := 5;
C_PROG_EMPTY_TYPE_WDCH : integer := 5;
C_PROG_EMPTY_TYPE_WRCH : integer := 5;
C_PROG_EMPTY_TYPE_RACH : integer := 5;
C_PROG_EMPTY_TYPE_RDCH : integer := 5;
C_PROG_EMPTY_TYPE_AXIS : integer := 5;
-- Single Programmable EMPTY Threshold Constant Assert Value
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
SLEEP : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
FULL : OUT std_logic := '0';
ALMOST_FULL : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
EMPTY : OUT std_logic := '1';
ALMOST_EMPTY : OUT std_logic := '1';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '1'; -- Active low reset, default value set to 1
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT std_logic := '0';
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT std_logic := '0';
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT std_logic := '0';
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic := '0';
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic := '0';
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RLAST : OUT std_logic := '0';
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RVALID : OUT std_logic := '0';
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT std_logic := '0';
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic := '0';
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic := '0';
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic := '0';
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT std_logic := '0';
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_SBITERR : OUT std_logic := '0';
AXI_AW_DBITERR : OUT std_logic := '0';
AXI_AW_OVERFLOW : OUT std_logic := '0';
AXI_AW_UNDERFLOW : OUT std_logic := '0';
AXI_AW_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_SBITERR : OUT std_logic := '0';
AXI_W_DBITERR : OUT std_logic := '0';
AXI_W_OVERFLOW : OUT std_logic := '0';
AXI_W_UNDERFLOW : OUT std_logic := '0';
AXI_W_PROG_FULL : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_SBITERR : OUT std_logic := '0';
AXI_B_DBITERR : OUT std_logic := '0';
AXI_B_OVERFLOW : OUT std_logic := '0';
AXI_B_UNDERFLOW : OUT std_logic := '0';
AXI_B_PROG_FULL : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_SBITERR : OUT std_logic := '0';
AXI_AR_DBITERR : OUT std_logic := '0';
AXI_AR_OVERFLOW : OUT std_logic := '0';
AXI_AR_UNDERFLOW : OUT std_logic := '0';
AXI_AR_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_SBITERR : OUT std_logic := '0';
AXI_R_DBITERR : OUT std_logic := '0';
AXI_R_OVERFLOW : OUT std_logic := '0';
AXI_R_UNDERFLOW : OUT std_logic := '0';
AXI_R_PROG_FULL : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_SBITERR : OUT std_logic := '0';
AXIS_DBITERR : OUT std_logic := '0';
AXIS_OVERFLOW : OUT std_logic := '0';
AXIS_UNDERFLOW : OUT std_logic := '0';
AXIS_PROG_FULL : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY : OUT STD_LOGIC := '1'
);
END fifo_generator_vhdl_beh;
ARCHITECTURE behavioral OF fifo_generator_vhdl_beh IS
COMPONENT fifo_generator_v13_0_1_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_INTERFACE_TYPE : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
WR_RST_I_OUT : OUT std_logic := '0';
RD_RST_I_OUT : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END COMPONENT;
-- CONSTANT C_AXI_LEN_WIDTH : integer := 8;
CONSTANT C_AXI_SIZE_WIDTH : integer := 3;
CONSTANT C_AXI_BURST_WIDTH : integer := 2;
-- CONSTANT C_AXI_LOCK_WIDTH : integer := 2;
CONSTANT C_AXI_CACHE_WIDTH : integer := 4;
CONSTANT C_AXI_PROT_WIDTH : integer := 3;
CONSTANT C_AXI_QOS_WIDTH : integer := 4;
CONSTANT C_AXI_REGION_WIDTH : integer := 4;
CONSTANT C_AXI_BRESP_WIDTH : integer := 2;
CONSTANT C_AXI_RRESP_WIDTH : integer := 2;
CONSTANT TFF : time := 100 ps;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed and returns string.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : string;
false_case : string)
RETURN string IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
---------------------------------------------------------------------------
-- FUNCTION : log2roundup
---------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
CONSTANT lower_limit : integer := 1;
CONSTANT upper_limit : integer := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : bin2gray
-----------------------------------------------------------------------------
-- This function receives a binary value, and returns the associated
-- graycoded value.
FUNCTION bin2gray (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := indata(I) XOR indata(I+1);
END LOOP;
RETURN tmp_value;
END bin2gray;
-----------------------------------------------------------------------------
-- FUNCTION : gray2bin
-----------------------------------------------------------------------------
-- This function receives a gray-coded value, and returns the associated
-- binary value.
FUNCTION gray2bin (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := XOR_REDUCE(indata(length-1 DOWNTO I));
END LOOP;
RETURN tmp_value;
END gray2bin;
--------------------------------------------------------
-- FUNCION : map_ready_valid
-- Returns the READY signal that is mapped out of FULL or ALMOST_FULL or PROG_FULL
-- Returns the VALID signal that is mapped out of EMPTY or ALMOST_EMPTY or PROG_EMPTY
--------------------------------------------------------
FUNCTION map_ready_valid(
pf_pe_type : integer;
full_empty : std_logic;
af_ae : std_logic;
pf_pe : std_logic)
RETURN std_logic IS
BEGIN
IF (pf_pe_type = 5) THEN
RETURN NOT full_empty;
ELSIF (pf_pe_type = 6) THEN
RETURN NOT af_ae;
ELSE
RETURN NOT pf_pe;
END IF;
END map_ready_valid;
SIGNAL inverted_reset : std_logic := '0';
SIGNAL axi_rs_rst : std_logic := '0';
CONSTANT IS_V8 : INTEGER := if_then_else((C_FAMILY = "virtexu"),1,0);
CONSTANT IS_K8 : INTEGER := if_then_else((C_FAMILY = "kintexu"),1,0);
CONSTANT IS_A8 : INTEGER := if_then_else((C_FAMILY = "artixu"),1,0);
CONSTANT IS_VM : INTEGER := if_then_else((C_FAMILY = "virtexuplus"),1,0);
CONSTANT IS_KM : INTEGER := if_then_else((C_FAMILY = "kintexuplus"),1,0);
CONSTANT IS_ZNQU : INTEGER := if_then_else((C_FAMILY = "zynquplus"),1,0);
CONSTANT IS_8SERIES : INTEGER := if_then_else((IS_V8 = 1 OR IS_K8 = 1 OR IS_A8 = 1 OR IS_VM = 1 OR IS_ZNQU = 1 OR IS_KM = 1),1,0);
BEGIN
inverted_reset <= NOT S_ARESETN;
gaxi_rs_rst: IF (C_INTERFACE_TYPE > 0 AND (C_AXIS_TYPE = 1 OR C_WACH_TYPE = 1 OR
C_WDCH_TYPE = 1 OR C_WRCH_TYPE = 1 OR C_RACH_TYPE = 1 OR C_RDCH_TYPE = 1)) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
BEGIN
prst: PROCESS (inverted_reset, S_ACLK)
BEGIN
IF (inverted_reset = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
rst_d1 <= '0' AFTER TFF;
rst_d2 <= rst_d1 AFTER TFF;
END IF;
END PROCESS prst;
axi_rs_rst <= rst_d2;
END GENERATE gaxi_rs_rst;
---------------------------------------------------------------------------
-- Top level instance for Conventional FIFO.
---------------------------------------------------------------------------
gconvfifo: IF (C_INTERFACE_TYPE = 0) GENERATE
SIGNAL wr_data_count_in : std_logic_vector (C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
signal full_i : std_logic := '0';
signal empty_i : std_logic := '0';
signal WR_RST_INT : std_logic := '0';
signal RD_RST_INT : std_logic := '0';
begin
inst_conv_fifo: fifo_generator_v13_0_1_conv
GENERIC map(
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => if_then_else(C_USE_DOUT_RST = 1, C_DOUT_RST_VAL, "0"),
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RD_RST => C_HAS_RD_RST,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_HAS_WR_RST => C_HAS_WR_RST,
C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_FREQ => C_RD_FREQ,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_FREQ => C_WR_FREQ,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
CLK => CLK,
RST => RST,
SRST => SRST,
WR_CLK => WR_CLK,
WR_RST => WR_RST,
RD_CLK => RD_CLK,
RD_RST => RD_RST,
DIN => DIN,
WR_EN => WR_EN,
RD_EN => RD_EN,
PROG_EMPTY_THRESH => PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => PROG_EMPTY_THRESH_ASSERT,
PROG_EMPTY_THRESH_NEGATE => PROG_EMPTY_THRESH_NEGATE,
PROG_FULL_THRESH => PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => PROG_FULL_THRESH_ASSERT,
PROG_FULL_THRESH_NEGATE => PROG_FULL_THRESH_NEGATE,
INT_CLK => INT_CLK,
INJECTDBITERR => INJECTDBITERR,
INJECTSBITERR => INJECTSBITERR,
--Outputs
DOUT => DOUT,
FULL => full_i,
ALMOST_FULL => ALMOST_FULL,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_i,
ALMOST_EMPTY => ALMOST_EMPTY,
VALID => VALID,
UNDERFLOW => UNDERFLOW,
DATA_COUNT => DATA_COUNT,
RD_DATA_COUNT => RD_DATA_COUNT,
WR_DATA_COUNT => wr_data_count_in,
PROG_FULL => PROG_FULL,
PROG_EMPTY => PROG_EMPTY,
SBITERR => SBITERR,
DBITERR => DBITERR,
WR_RST_BUSY => WR_RST_BUSY,
RD_RST_BUSY => RD_RST_BUSY,
WR_RST_I_OUT => WR_RST_INT,
RD_RST_I_OUT => RD_RST_INT
);
FULL <= full_i;
EMPTY <= empty_i;
fifo_ic_adapter: IF (C_HAS_DATA_COUNTS_AXIS = 3) GENERATE
SIGNAL wr_eop : STD_LOGIC := '0';
SIGNAL rd_eop : STD_LOGIC := '0';
SIGNAL data_read : STD_LOGIC := '0';
SIGNAL w_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL r_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_gc : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_gc_asreg_last : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_rd : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
--SIGNAL axis_wr_rst : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
--SIGNAL axis_rd_rst : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL d_cnt : std_logic_vector(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL d_cnt_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_w_cnt_rd_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (others => '0');
SIGNAL r_inv_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (others => '0');
-- Defined to connect data output of one FIFO to data input of another
TYPE w_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(log2roundup(C_WR_DEPTH)-1 DOWNTO 0);
SIGNAL w_q : w_sync_array := (OTHERS => (OTHERS => '0'));
TYPE axis_af_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(0 DOWNTO 0);
BEGIN
wr_eop <= WR_EN AND not(full_i);
rd_eop <= RD_EN AND not(empty_i);
-- Write Packet count logic
proc_w_cnt: PROCESS (WR_CLK, WR_RST_INT)
BEGIN
IF (WR_RST_INT = '1') THEN
w_cnt <= (OTHERS => '0');
ELSIF (WR_CLK = '1' AND WR_CLK'EVENT) THEN
IF (wr_eop = '1') THEN
w_cnt <= w_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_w_cnt;
-- Convert Write Packet count to Grey
pw_gc : PROCESS (WR_CLK, WR_RST_INT)
BEGIN
if (WR_RST_INT = '1') then
w_cnt_gc <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
w_cnt_gc <= bin2gray(w_cnt, log2roundup(C_WR_DEPTH)) AFTER TFF;
END IF;
END PROCESS pw_gc;
-- Synchronize the Write Packet count in read domain
-- Synchronize the axis_almost_full in read domain
gpkt_cnt_sync_stage: FOR I IN 1 TO C_SYNCHRONIZER_STAGE GENERATE
BEGIN
-- pkt_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => log2roundup(C_WR_DEPTH_AXIS)
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => wpkt_q(i-1),
-- Q => wpkt_q(i)
-- );
PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1' AND C_HAS_RST = 1) THEN
w_q(i) <= (OTHERS => '0');
ELSIF RD_CLK'EVENT AND RD_CLK = '1' THEN
w_q(i) <= w_q(i-1) AFTER TFF;
END IF;
END PROCESS;
END GENERATE gpkt_cnt_sync_stage;
w_q(0) <= w_cnt_gc;
w_cnt_gc_asreg_last <= w_q(C_SYNCHRONIZER_STAGE);
-- Convert synchronized Write Packet count grey value to binay
pw_rd_bin : PROCESS (RD_CLK, RD_RST_INT)
BEGIN
if (RD_RST_INT = '1') then
w_cnt_rd <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last, log2roundup(C_WR_DEPTH)) AFTER TFF;
END IF;
END PROCESS pw_rd_bin;
-- Read Packet count logic
proc_r_cnt: PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1') THEN
r_cnt <= (OTHERS => '0');
ELSIF (RD_CLK = '1' AND RD_CLK'EVENT) THEN
IF (rd_eop = '1') THEN
r_cnt <= r_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_r_cnt;
-- Take the difference of write and read packet count
-- Logic is similar to rd_pe_as
adj_w_cnt_rd_pad(log2roundup(C_WR_DEPTH) DOWNTO 1) <= w_cnt_rd;
r_inv_pad(log2roundup(C_WR_DEPTH) DOWNTO 1) <= not r_cnt;
p_cry: PROCESS (rd_eop)
BEGIN
IF (rd_eop = '0') THEN
adj_w_cnt_rd_pad(0) <= '1';
r_inv_pad(0) <= '1';
ELSE
adj_w_cnt_rd_pad(0) <= '0';
r_inv_pad(0) <= '0';
END IF;
END PROCESS p_cry;
p_sub: PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1') THEN
d_cnt_pad <= (OTHERS=>'0');
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad AFTER TFF;
END IF;
END PROCESS p_sub;
d_cnt <= d_cnt_pad(log2roundup(C_WR_DEPTH) DOWNTO 1);
WR_DATA_COUNT <= d_cnt;
END GENERATE fifo_ic_adapter;
fifo_icn_adapter: IF (C_HAS_DATA_COUNTS_AXIS /= 3) GENERATE
WR_DATA_COUNT <= wr_data_count_in;
END GENERATE fifo_icn_adapter;
END GENERATE gconvfifo; -- End of conventional FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Top level instance for ramfifo in AXI Streaming FIFO core. It implements:
-- * BRAM based FIFO
-- * Dist RAM based FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxis_fifo: IF ((C_INTERFACE_TYPE = 1) AND (C_AXIS_TYPE < 2)) GENERATE
SIGNAL axis_din : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_dout : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_full : std_logic := '0';
SIGNAL axis_almost_full : std_logic := '0';
SIGNAL axis_empty : std_logic := '0';
SIGNAL axis_s_axis_tready : std_logic := '0';
SIGNAL axis_m_axis_tvalid : std_logic := '0';
SIGNAL axis_wr_en : std_logic := '0';
SIGNAL axis_rd_en : std_logic := '0';
SIGNAL axis_dc : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_rst_busy_axis : STD_LOGIC := '0';
SIGNAL rd_rst_busy_axis : STD_LOGIC := '0';
CONSTANT TDATA_OFFSET : integer := if_then_else(C_HAS_AXIS_TDATA = 1,C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH,C_DIN_WIDTH_AXIS);
CONSTANT TSTRB_OFFSET : integer := if_then_else(C_HAS_AXIS_TSTRB = 1,TDATA_OFFSET-C_AXIS_TSTRB_WIDTH,TDATA_OFFSET);
CONSTANT TKEEP_OFFSET : integer := if_then_else(C_HAS_AXIS_TKEEP = 1,TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH,TSTRB_OFFSET);
CONSTANT TID_OFFSET : integer := if_then_else(C_HAS_AXIS_TID = 1,TKEEP_OFFSET-C_AXIS_TID_WIDTH,TKEEP_OFFSET);
CONSTANT TDEST_OFFSET : integer := if_then_else(C_HAS_AXIS_TDEST = 1,TID_OFFSET-C_AXIS_TDEST_WIDTH,TID_OFFSET);
CONSTANT TUSER_OFFSET : integer := if_then_else(C_HAS_AXIS_TUSER = 1,TDEST_OFFSET-C_AXIS_TUSER_WIDTH,TDEST_OFFSET);
BEGIN
-- Generate the DIN to FIFO by concatinating the AXIS optional ports
gdin1: IF (C_HAS_AXIS_TDATA = 1) GENERATE
axis_din(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET) <= S_AXIS_TDATA;
M_AXIS_TDATA <= axis_dout(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET);
END GENERATE gdin1;
gdin2: IF (C_HAS_AXIS_TSTRB = 1) GENERATE
axis_din(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET) <= S_AXIS_TSTRB;
M_AXIS_TSTRB <= axis_dout(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET);
END GENERATE gdin2;
gdin3: IF (C_HAS_AXIS_TKEEP = 1) GENERATE
axis_din(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET) <= S_AXIS_TKEEP;
M_AXIS_TKEEP <= axis_dout(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET);
END GENERATE gdin3;
gdin4: IF (C_HAS_AXIS_TID = 1) GENERATE
axis_din(TKEEP_OFFSET-1 DOWNTO TID_OFFSET) <= S_AXIS_TID;
M_AXIS_TID <= axis_dout(TKEEP_OFFSET-1 DOWNTO TID_OFFSET);
END GENERATE gdin4;
gdin5: IF (C_HAS_AXIS_TDEST = 1) GENERATE
axis_din(TID_OFFSET-1 DOWNTO TDEST_OFFSET) <= S_AXIS_TDEST;
M_AXIS_TDEST <= axis_dout(TID_OFFSET-1 DOWNTO TDEST_OFFSET);
END GENERATE gdin5;
gdin6: IF (C_HAS_AXIS_TUSER = 1) GENERATE
axis_din(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET) <= S_AXIS_TUSER;
M_AXIS_TUSER <= axis_dout(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET);
END GENERATE gdin6;
gdin7: IF (C_HAS_AXIS_TLAST = 1) GENERATE
axis_din(0) <= S_AXIS_TLAST;
M_AXIS_TLAST <= axis_dout(0);
END GENERATE gdin7;
-- Write protection
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gaxis_wr_en1: IF (C_PROG_FULL_TYPE_AXIS = 0) GENERATE
gwe_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_wr_en <= S_AXIS_TVALID AND axis_s_axis_tready;
END GENERATE gwe_pkt;
gwe: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_wr_en <= S_AXIS_TVALID;
END GENERATE gwe;
END GENERATE gaxis_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gaxis_wr_en2: IF (C_PROG_FULL_TYPE_AXIS /= 0) GENERATE
axis_wr_en <= axis_s_axis_tready AND S_AXIS_TVALID;
END GENERATE gaxis_wr_en2;
-- Read protection
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gaxis_rd_en1: IF (C_PROG_EMPTY_TYPE_AXIS = 0) GENERATE
gre_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_rd_en <= M_AXIS_TREADY AND axis_m_axis_tvalid;
END GENERATE gre_pkt;
gre_npkt: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_rd_en <= M_AXIS_TREADY;
END GENERATE gre_npkt;
END GENERATE gaxis_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gaxis_rd_en2: IF (C_PROG_EMPTY_TYPE_AXIS /= 0) GENERATE
axis_rd_en <= axis_m_axis_tvalid AND M_AXIS_TREADY;
END GENERATE gaxis_rd_en2;
gaxisf: IF (C_AXIS_TYPE = 0) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
SIGNAL axis_wr_rst : STD_LOGIC := '0';
SIGNAL axis_rd_rst : STD_LOGIC := '0';
BEGIN
axis_we <= axis_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE axis_wr_en AND S_ACLK_EN;
axis_re <= axis_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE axis_rd_en AND M_ACLK_EN;
axisf : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 2 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 11 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_AXIS,
C_WR_DEPTH => C_WR_DEPTH_AXIS,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_DOUT_WIDTH => C_DIN_WIDTH_AXIS,
C_RD_DEPTH => C_WR_DEPTH_AXIS,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_AXIS,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_AXIS,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_AXIS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS,
C_USE_ECC => C_USE_ECC_AXIS,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_AXIS,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => if_then_else(C_APPLICATION_TYPE_AXIS = 1,1,0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else(C_APPLICATION_TYPE_AXIS = 1,0,C_APPLICATION_TYPE_AXIS),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => 0,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => axis_we,
RD_EN => axis_re,
PROG_FULL_THRESH => AXIS_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXIS_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXIS_INJECTDBITERR,
INJECTSBITERR => AXIS_INJECTSBITERR,
DIN => axis_din,
DOUT => axis_dout,
FULL => axis_full,
EMPTY => axis_empty,
ALMOST_FULL => axis_almost_full,
PROG_FULL => AXIS_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXIS_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => AXIS_OVERFLOW,
VALID => OPEN,
UNDERFLOW => AXIS_UNDERFLOW,
DATA_COUNT => axis_dc,
RD_DATA_COUNT => AXIS_RD_DATA_COUNT,
WR_DATA_COUNT => AXIS_WR_DATA_COUNT,
SBITERR => AXIS_SBITERR,
DBITERR => AXIS_DBITERR,
WR_RST_BUSY => wr_rst_busy_axis,
RD_RST_BUSY => rd_rst_busy_axis,
WR_RST_I_OUT => axis_wr_rst,
RD_RST_I_OUT => axis_rd_rst
);
g8s_axis_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_axis_rdy: IF (C_IMPLEMENTATION_TYPE_AXIS = 5 OR C_IMPLEMENTATION_TYPE_AXIS = 13) GENERATE
axis_s_axis_tready <= NOT (axis_full OR wr_rst_busy_axis);
END GENERATE g8s_bi_axis_rdy;
g8s_nbi_axis_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_AXIS = 5 OR C_IMPLEMENTATION_TYPE_AXIS = 13)) GENERATE
axis_s_axis_tready <= NOT (axis_full);
END GENERATE g8s_nbi_axis_rdy;
END GENERATE g8s_axis_rdy;
g7s_axis_rdy: IF (IS_8SERIES = 0) GENERATE
axis_s_axis_tready <= NOT (axis_full);
END GENERATE g7s_axis_rdy;
--axis_m_axis_tvalid <= NOT axis_empty WHEN (C_APPLICATION_TYPE_AXIS /= 1) ELSE NOT axis_empty AND axis_pkt_read;
gnaxis_pkt_fifo: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_m_axis_tvalid <= NOT axis_empty;
END GENERATE gnaxis_pkt_fifo;
S_AXIS_TREADY <= axis_s_axis_tready;
M_AXIS_TVALID <= axis_m_axis_tvalid;
gaxis_pkt_fifo_cc: IF (C_APPLICATION_TYPE_AXIS = 1 AND C_COMMON_CLOCK = 1) GENERATE
SIGNAL axis_wr_eop : STD_LOGIC := '0';
SIGNAL axis_wr_eop_d1 : STD_LOGIC := '0';
SIGNAL axis_rd_eop : STD_LOGIC := '0';
SIGNAL axis_pkt_cnt : INTEGER := 0;
SIGNAL axis_pkt_read : STD_LOGIC := '0';
BEGIN
axis_m_axis_tvalid <= NOT axis_empty AND axis_pkt_read;
axis_wr_eop <= axis_we AND S_AXIS_TLAST;
axis_rd_eop <= axis_re AND axis_dout(0);
-- Packet Read Generation logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_read <= '0';
axis_wr_eop_d1 <= '0';
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
axis_wr_eop_d1 <= axis_wr_eop;
IF (axis_rd_eop = '1' AND (axis_pkt_cnt = 1) AND axis_wr_eop_d1 = '0') THEN
axis_pkt_read <= '0' AFTER TFF;
ELSIF ((axis_pkt_cnt > 0) OR (axis_almost_full = '1' AND axis_empty = '0')) THEN
axis_pkt_read <= '1' AFTER TFF;
END IF;
END IF;
END PROCESS;
-- Packet count logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_cnt <= 0;
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_wr_eop_d1 = '1' AND axis_rd_eop = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt + 1 AFTER TFF;
ELSIF (axis_rd_eop = '1' AND axis_wr_eop_d1 = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt - 1 AFTER TFF;
END IF;
END IF;
END PROCESS;
END GENERATE gaxis_pkt_fifo_cc;
gaxis_pkt_fifo_ic: IF (C_APPLICATION_TYPE_AXIS = 1 AND C_COMMON_CLOCK = 0) GENERATE
SIGNAL axis_wr_eop : STD_LOGIC := '0';
SIGNAL axis_rd_eop : STD_LOGIC := '0';
SIGNAL axis_pkt_read : STD_LOGIC := '0';
SIGNAL axis_wpkt_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_rpkt_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_gc : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_gc_asreg_last : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_rd : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pkt_cnt : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pkt_cnt_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_axis_wpkt_cnt_rd_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (others => '0');
SIGNAL rpkt_inv_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (others => '0');
-- Defined to connect data output of one FIFO to data input of another
TYPE wpkt_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0);
SIGNAL wpkt_q : wpkt_sync_array := (OTHERS => (OTHERS => '0'));
TYPE axis_af_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(0 DOWNTO 0);
SIGNAL axis_af_q : axis_af_array := (OTHERS => (OTHERS => '0'));
SIGNAL axis_af_rd : std_logic_vector(0 DOWNTO 0) := (others => '0');
BEGIN
axis_wr_eop <= axis_we AND S_AXIS_TLAST;
axis_rd_eop <= axis_re AND axis_dout(0);
-- Packet Read Generation logic
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
axis_pkt_read <= '0';
ELSIF (M_ACLK = '1' AND M_ACLK'EVENT) THEN
IF (axis_rd_eop = '1' AND (conv_integer(diff_pkt_cnt) = 1)) THEN
axis_pkt_read <= '0' AFTER TFF;
-- Asserting packet read at the same time when the packet is written is not considered because it causes
-- packet FIFO handshake violation when the packet size is just 2 data beat and each write is separated
-- by more than 2 clocks. This causes the first data to come out at the FWFT stage making the actual FIFO
-- empty and leaving the first stage FWFT stage with no data, and when the last data is written, it
-- actually makes the valid to be high for a clock and de-asserts immediately as the written data will
-- take two clocks to appear at the FWFT output. This situation is a violation of packet FIFO, where
-- TVALID should not get de-asserted in between the packet transfer.
ELSIF ((conv_integer(diff_pkt_cnt) > 0) OR (axis_af_rd(0) = '1' AND axis_empty = '0')) THEN
axis_pkt_read <= '1' AFTER TFF;
END IF;
END IF;
END PROCESS;
axis_m_axis_tvalid <= (NOT axis_empty) AND axis_pkt_read;
-- Write Packet count logic
proc_wpkt_cnt: PROCESS (S_ACLK, axis_wr_rst)
BEGIN
IF (axis_wr_rst = '1') THEN
axis_wpkt_cnt <= (OTHERS => '0');
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_wr_eop = '1') THEN
axis_wpkt_cnt <= axis_wpkt_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_wpkt_cnt;
-- Convert Write Packet count to Grey
pwpkt_gc : PROCESS (S_ACLK, axis_wr_rst)
BEGIN
if (axis_wr_rst = '1') then
axis_wpkt_cnt_gc <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt, log2roundup(C_WR_DEPTH_AXIS)) AFTER TFF;
END IF;
END PROCESS pwpkt_gc;
-- Synchronize the Write Packet count in read domain
-- Synchronize the axis_almost_full in read domain
gpkt_cnt_sync_stage: FOR I IN 1 TO C_SYNCHRONIZER_STAGE GENERATE
BEGIN
-- pkt_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => log2roundup(C_WR_DEPTH_AXIS)
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => wpkt_q(i-1),
-- Q => wpkt_q(i)
-- );
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1' AND C_HAS_RST = 1) THEN
wpkt_q(i) <= (OTHERS => '0');
ELSIF M_ACLK'EVENT AND M_ACLK = '1' THEN
wpkt_q(i) <= wpkt_q(i-1) AFTER TFF;
END IF;
END PROCESS;
-- af_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => 1
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => axis_af_q(i-1),
-- Q => axis_af_q(i)
-- );
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1' AND C_HAS_RST = 1) THEN
axis_af_q(i) <= (OTHERS => '0');
ELSIF M_ACLK'EVENT AND M_ACLK = '1' THEN
axis_af_q(i) <= axis_af_q(i-1) AFTER TFF;
END IF;
END PROCESS;
END GENERATE gpkt_cnt_sync_stage;
wpkt_q(0) <= axis_wpkt_cnt_gc;
axis_wpkt_cnt_gc_asreg_last <= wpkt_q(C_SYNCHRONIZER_STAGE);
axis_af_q(0)(0) <= axis_almost_full;
axis_af_rd <= axis_af_q(C_SYNCHRONIZER_STAGE);
-- Convert synchronized Write Packet count grey value to binay
pwpkt_rd_bin : PROCESS (M_ACLK, axis_rd_rst)
BEGIN
if (axis_rd_rst = '1') then
axis_wpkt_cnt_rd <= (OTHERS => '0');
ELSIF (M_ACLK'event AND M_ACLK = '1') THEN
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last, log2roundup(C_WR_DEPTH_AXIS)) AFTER TFF;
END IF;
END PROCESS pwpkt_rd_bin;
-- Read Packet count logic
proc_rpkt_cnt: PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
axis_rpkt_cnt <= (OTHERS => '0');
ELSIF (M_ACLK = '1' AND M_ACLK'EVENT) THEN
IF (axis_rd_eop = '1') THEN
axis_rpkt_cnt <= axis_rpkt_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_rpkt_cnt;
-- Take the difference of write and read packet count
-- Logic is similar to rd_pe_as
adj_axis_wpkt_cnt_rd_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1) <= axis_wpkt_cnt_rd;
rpkt_inv_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1) <= not axis_rpkt_cnt;
pkt_cry: PROCESS (axis_rd_eop)
BEGIN
IF (axis_rd_eop = '0') THEN
adj_axis_wpkt_cnt_rd_pad(0) <= '1';
rpkt_inv_pad(0) <= '1';
ELSE
adj_axis_wpkt_cnt_rd_pad(0) <= '0';
rpkt_inv_pad(0) <= '0';
END IF;
END PROCESS pkt_cry;
pkt_sub: PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
diff_pkt_cnt_pad <= (OTHERS=>'0');
ELSIF M_ACLK'event AND M_ACLK = '1' THEN
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad AFTER TFF;
END IF;
END PROCESS pkt_sub;
diff_pkt_cnt <= diff_pkt_cnt_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1);
END GENERATE gaxis_pkt_fifo_ic;
gdc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 1 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
SIGNAL axis_dc_pkt_fifo : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_dc_pkt_fifo <= (OTHERS => '0');
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_we = '1' AND axis_re = '0') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo + "1" AFTER TFF;
ELSIF (axis_we = '0' AND axis_re = '1') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo - "1" AFTER TFF;
END IF;
END IF;
END PROCESS;
AXIS_DATA_COUNT <= axis_dc_pkt_fifo;
END GENERATE gdc_pkt;
gndc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 0 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
AXIS_DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc_pkt;
gdc: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
AXIS_DATA_COUNT <= axis_dc;
END GENERATE gdc;
END GENERATE gaxisf;
-- Register Slice for AXI Streaming
gaxis_reg_slice: IF (C_AXIS_TYPE = 1) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
BEGIN
axis_we <= S_AXIS_TVALID WHEN (C_HAS_SLAVE_CE = 0) ELSE S_AXIS_TVALID AND S_ACLK_EN;
axis_re <= M_AXIS_TREADY WHEN (C_HAS_MASTER_CE = 0) ELSE M_AXIS_TREADY AND M_ACLK_EN;
axis_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_AXIS,
C_REG_CONFIG => C_REG_SLICE_MODE_AXIS
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => axis_din,
S_VALID => axis_we,
S_READY => S_AXIS_TREADY,
-- Master side
M_PAYLOAD_DATA => axis_dout,
M_VALID => M_AXIS_TVALID,
M_READY => axis_re
);
END GENERATE gaxis_reg_slice;
END GENERATE gaxis_fifo;
gaxifull: IF (C_INTERFACE_TYPE = 2) GENERATE
SIGNAL axi_rd_underflow_i : std_logic := '0';
SIGNAL axi_rd_overflow_i : std_logic := '0';
SIGNAL axi_wr_underflow_i : std_logic := '0';
SIGNAL axi_wr_overflow_i : std_logic := '0';
BEGIN
gwrch: IF (C_HAS_AXI_WR_CHANNEL = 1) GENERATE
SIGNAL wach_din : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout_pkt : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_full : std_logic := '0';
SIGNAL wach_almost_full : std_logic := '0';
SIGNAL wach_prog_full : std_logic := '0';
SIGNAL wach_empty : std_logic := '0';
SIGNAL wach_almost_empty : std_logic := '0';
SIGNAL wach_prog_empty : std_logic := '0';
SIGNAL wdch_din : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_dout : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_full : std_logic := '0';
SIGNAL wdch_almost_full : std_logic := '0';
SIGNAL wdch_prog_full : std_logic := '0';
SIGNAL wdch_empty : std_logic := '0';
SIGNAL wdch_almost_empty : std_logic := '0';
SIGNAL wdch_prog_empty : std_logic := '0';
SIGNAL wrch_din : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_dout : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_full : std_logic := '0';
SIGNAL wrch_almost_full : std_logic := '0';
SIGNAL wrch_prog_full : std_logic := '0';
SIGNAL wrch_empty : std_logic := '0';
SIGNAL wrch_almost_empty : std_logic := '0';
SIGNAL wrch_prog_empty : std_logic := '0';
SIGNAL axi_aw_underflow_i : std_logic := '0';
SIGNAL axi_w_underflow_i : std_logic := '0';
SIGNAL axi_b_underflow_i : std_logic := '0';
SIGNAL axi_aw_overflow_i : std_logic := '0';
SIGNAL axi_w_overflow_i : std_logic := '0';
SIGNAL axi_b_overflow_i : std_logic := '0';
SIGNAL wach_s_axi_awready : std_logic := '0';
SIGNAL wach_m_axi_awvalid : std_logic := '0';
SIGNAL wach_wr_en : std_logic := '0';
SIGNAL wach_rd_en : std_logic := '0';
SIGNAL wdch_s_axi_wready : std_logic := '0';
SIGNAL wdch_m_axi_wvalid : std_logic := '0';
SIGNAL wdch_wr_en : std_logic := '0';
SIGNAL wdch_rd_en : std_logic := '0';
SIGNAL wrch_s_axi_bvalid : std_logic := '0';
SIGNAL wrch_m_axi_bready : std_logic := '0';
SIGNAL wrch_wr_en : std_logic := '0';
SIGNAL wrch_rd_en : std_logic := '0';
SIGNAL awvalid_en : std_logic := '0';
SIGNAL awready_pkt : std_logic := '0';
SIGNAL wdch_we : STD_LOGIC := '0';
SIGNAL wr_rst_busy_wach : std_logic := '0';
SIGNAL wr_rst_busy_wdch : std_logic := '0';
SIGNAL wr_rst_busy_wrch : std_logic := '0';
SIGNAL rd_rst_busy_wach : std_logic := '0';
SIGNAL rd_rst_busy_wdch : std_logic := '0';
SIGNAL rd_rst_busy_wrch : std_logic := '0';
CONSTANT AWID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WACH);
CONSTANT AWADDR_OFFSET : integer := AWID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT AWLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWADDR_OFFSET - C_AXI_LEN_WIDTH,AWADDR_OFFSET);
CONSTANT AWSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLEN_OFFSET - C_AXI_SIZE_WIDTH,AWLEN_OFFSET);
CONSTANT AWBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWSIZE_OFFSET - C_AXI_BURST_WIDTH,AWSIZE_OFFSET);
CONSTANT AWLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWBURST_OFFSET - C_AXI_LOCK_WIDTH,AWBURST_OFFSET);
CONSTANT AWCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLOCK_OFFSET - C_AXI_CACHE_WIDTH,AWLOCK_OFFSET);
CONSTANT AWPROT_OFFSET : integer := AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT AWQOS_OFFSET : integer := AWPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT AWREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWQOS_OFFSET - C_AXI_REGION_WIDTH, AWQOS_OFFSET);
CONSTANT AWUSER_OFFSET : integer := if_then_else(C_HAS_AXI_AWUSER = 1,AWREGION_OFFSET-C_AXI_AWUSER_WIDTH,AWREGION_OFFSET);
CONSTANT WID_OFFSET : integer := if_then_else(C_AXI_TYPE = 3 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WDCH);
CONSTANT WDATA_OFFSET : integer := WID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT WSTRB_OFFSET : integer := WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
CONSTANT WUSER_OFFSET : integer := if_then_else(C_HAS_AXI_WUSER = 1,WSTRB_OFFSET-C_AXI_WUSER_WIDTH,WSTRB_OFFSET);
CONSTANT BID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WRCH);
CONSTANT BRESP_OFFSET : integer := BID_OFFSET - C_AXI_BRESP_WIDTH;
CONSTANT BUSER_OFFSET : integer := if_then_else(C_HAS_AXI_BUSER = 1,BRESP_OFFSET-C_AXI_BUSER_WIDTH,BRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_wr_ch: IF (C_AXI_TYPE /= 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
gwach_din1: IF (C_HAS_AXI_AWUSER = 1) GENERATE
wach_din(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET) <= S_AXI_AWUSER;
M_AXI_AWUSER <= wach_dout(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET);
END GENERATE gwach_din1;
gwach_din2: IF (C_HAS_AXI_AWUSER = 0) GENERATE
M_AXI_AWUSER <= (OTHERS => '0');
END GENERATE gwach_din2;
gwach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wach_din(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET) <= S_AXI_AWID;
M_AXI_AWID <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET);
END GENERATE gwach_din3;
gwach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_AWID <= (OTHERS => '0');
END GENERATE gwach_din4;
gwach_din5: IF (C_AXI_TYPE = 1) GENERATE
wach_din(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET) <= S_AXI_AWREGION;
M_AXI_AWREGION <= wach_dout(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET);
END GENERATE gwach_din5;
gwach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_AWREGION <= (OTHERS => '0');
END GENERATE gwach_din6;
wach_din(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET) <= S_AXI_AWADDR;
wach_din(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET) <= S_AXI_AWLEN;
wach_din(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET) <= S_AXI_AWSIZE;
wach_din(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET) <= S_AXI_AWBURST;
wach_din(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET) <= S_AXI_AWLOCK;
wach_din(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET) <= S_AXI_AWCACHE;
wach_din(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET) <= S_AXI_AWPROT;
wach_din(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET) <= S_AXI_AWQOS;
M_AXI_AWADDR <= wach_dout(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWLEN <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET);
M_AXI_AWSIZE <= wach_dout(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET);
M_AXI_AWBURST <= wach_dout(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET);
M_AXI_AWLOCK <= wach_dout(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET);
M_AXI_AWCACHE <= wach_dout(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET);
M_AXI_AWPROT <= wach_dout(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET);
M_AXI_AWQOS <= wach_dout(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET);
END GENERATE gwach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
gwdch_din1: IF (C_HAS_AXI_WUSER = 1) GENERATE
wdch_din(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET) <= S_AXI_WUSER;
M_AXI_WUSER <= wdch_dout(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET);
END GENERATE gwdch_din1;
gwdch_din2: IF (C_HAS_AXI_WUSER = 0) GENERATE
M_AXI_WUSER <= (OTHERS => '0');
END GENERATE gwdch_din2;
gwdch_din3: IF (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
wdch_din(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET) <= S_AXI_WID;
M_AXI_WID <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET);
END GENERATE gwdch_din3;
gwdch_din4: IF NOT (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
M_AXI_WID <= (OTHERS => '0');
END GENERATE gwdch_din4;
wdch_din(WID_OFFSET-1 DOWNTO WDATA_OFFSET) <= S_AXI_WDATA;
wdch_din(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET) <= S_AXI_WSTRB;
wdch_din(0) <= S_AXI_WLAST;
M_AXI_WDATA <= wdch_dout(WID_OFFSET-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
M_AXI_WLAST <= wdch_dout(0);
END GENERATE gwdch1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Response Channel optional ports
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
gwrch_din1: IF (C_HAS_AXI_BUSER = 1) GENERATE
wrch_din(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET) <= M_AXI_BUSER;
S_AXI_BUSER <= wrch_dout(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET);
END GENERATE gwrch_din1;
gwrch_din2: IF (C_HAS_AXI_BUSER = 0) GENERATE
S_AXI_BUSER <= (OTHERS => '0');
END GENERATE gwrch_din2;
gwrch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wrch_din(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET) <= M_AXI_BID;
S_AXI_BID <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET);
END GENERATE gwrch_din3;
gwrch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_BID <= (OTHERS => '0');
END GENERATE gwrch_din4;
wrch_din(BID_OFFSET-1 DOWNTO BRESP_OFFSET) <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(BID_OFFSET-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_full_din_wr_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Write Address Channel optional ports
axi_lite_din_wr_ch: IF (C_AXI_TYPE = 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
wach_din <= S_AXI_AWADDR & S_AXI_AWPROT;
M_AXI_AWADDR <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWPROT <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWPROT_OFFSET);
END GENERATE gwach1;
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
wdch_din <= S_AXI_WDATA & S_AXI_WSTRB;
M_AXI_WDATA <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
END GENERATE gwdch1;
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
wrch_din <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_lite_din_wr_ch;
-- Write protection for Write Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwach_wr_en1: IF (C_PROG_FULL_TYPE_WACH = 0) GENERATE
wach_wr_en <= S_AXI_AWVALID;
END GENERATE gwach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwach_wr_en2: IF (C_PROG_FULL_TYPE_WACH /= 0) GENERATE
wach_wr_en <= wach_s_axi_awready AND S_AXI_AWVALID;
END GENERATE gwach_wr_en2;
-- Write protection for Write Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwdch_wr_en1: IF (C_PROG_FULL_TYPE_WDCH = 0) GENERATE
wdch_wr_en <= S_AXI_WVALID;
END GENERATE gwdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwdch_wr_en2: IF (C_PROG_FULL_TYPE_WDCH /= 0) GENERATE
wdch_wr_en <= wdch_s_axi_wready AND S_AXI_WVALID;
END GENERATE gwdch_wr_en2;
-- Write protection for Write Response Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwrch_wr_en1: IF (C_PROG_FULL_TYPE_WRCH = 0) GENERATE
wrch_wr_en <= M_AXI_BVALID;
END GENERATE gwrch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwrch_wr_en2: IF (C_PROG_FULL_TYPE_WRCH /= 0) GENERATE
wrch_wr_en <= wrch_m_axi_bready AND M_AXI_BVALID;
END GENERATE gwrch_wr_en2;
-- Read protection for Write Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwach_rd_en1: IF (C_PROG_EMPTY_TYPE_WACH = 0) GENERATE
gpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= awready_pkt AND awvalid_en;
END GENERATE;
gnpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= M_AXI_AWREADY;
END GENERATE;
END GENERATE gwach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwach_rd_en2: IF (C_PROG_EMPTY_TYPE_WACH /= 0) GENERATE
gaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
END GENERATE gaxi_mm_wach_rd_en2;
gnaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND M_AXI_AWREADY;
END GENERATE gnaxi_mm_wach_rd_en2;
END GENERATE gwach_rd_en2;
-- Read protection for Write Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwdch_rd_en1: IF (C_PROG_EMPTY_TYPE_WDCH = 0) GENERATE
wdch_rd_en <= M_AXI_WREADY;
END GENERATE gwdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwdch_rd_en2: IF (C_PROG_EMPTY_TYPE_WDCH /= 0) GENERATE
wdch_rd_en <= wdch_m_axi_wvalid AND M_AXI_WREADY;
END GENERATE gwdch_rd_en2;
-- Read protection for Write Response Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwrch_rd_en1: IF (C_PROG_EMPTY_TYPE_WRCH = 0) GENERATE
wrch_rd_en <= S_AXI_BREADY;
END GENERATE gwrch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwrch_rd_en2: IF (C_PROG_EMPTY_TYPE_WRCH /= 0) GENERATE
wrch_rd_en <= wrch_s_axi_bvalid AND S_AXI_BREADY;
END GENERATE gwrch_rd_en2;
gwach2: IF (C_WACH_TYPE = 0) GENERATE
SIGNAL wach_we : STD_LOGIC := '0';
SIGNAL wach_re : STD_LOGIC := '0';
BEGIN
wach_we <= wach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wach_wr_en AND S_ACLK_EN;
wach_re <= wach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wach_rd_en AND M_ACLK_EN;
axi_wach : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WACH = 2 OR C_IMPLEMENTATION_TYPE_WACH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WACH = 11 OR C_IMPLEMENTATION_TYPE_WACH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WACH,
C_WR_DEPTH => C_WR_DEPTH_WACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_DOUT_WIDTH => C_DIN_WIDTH_WACH,
C_RD_DEPTH => C_WR_DEPTH_WACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH,
C_USE_ECC => C_USE_ECC_WACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_WACH = 1),0,C_APPLICATION_TYPE_WACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wach_we,
RD_EN => wach_re,
PROG_FULL_THRESH => AXI_AW_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AW_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AW_INJECTDBITERR,
INJECTSBITERR => AXI_AW_INJECTSBITERR,
DIN => wach_din,
DOUT => wach_dout_pkt,
FULL => wach_full,
EMPTY => wach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AW_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AW_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_aw_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_aw_underflow_i,
DATA_COUNT => AXI_AW_DATA_COUNT,
RD_DATA_COUNT => AXI_AW_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AW_WR_DATA_COUNT,
SBITERR => AXI_AW_SBITERR,
DBITERR => AXI_AW_DBITERR,
WR_RST_BUSY => wr_rst_busy_wach,
RD_RST_BUSY => rd_rst_busy_wach,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_wach_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wach_rdy: IF (C_IMPLEMENTATION_TYPE_WACH = 5 OR C_IMPLEMENTATION_TYPE_WACH = 13) GENERATE
wach_s_axi_awready <= NOT (wach_full OR wr_rst_busy_wach);
END GENERATE g8s_bi_wach_rdy;
g8s_nbi_wach_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WACH = 5 OR C_IMPLEMENTATION_TYPE_WACH = 13)) GENERATE
wach_s_axi_awready <= NOT (wach_full);
END GENERATE g8s_nbi_wach_rdy;
END GENERATE g8s_wach_rdy;
g7s_wach_rdy: IF (IS_8SERIES = 0) GENERATE
wach_s_axi_awready <= NOT (wach_full);
END GENERATE g7s_wach_rdy;
wach_m_axi_awvalid <= NOT wach_empty;
S_AXI_AWREADY <= wach_s_axi_awready;
gawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL awvalid_pkt : STD_LOGIC := '0';
BEGIN
awvalid_pkt <= wach_m_axi_awvalid AND awvalid_en;
wach_pkt_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => wach_dout_pkt,
S_VALID => awvalid_pkt,
S_READY => awready_pkt,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gawvld_pkt_fifo;
gnawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
M_AXI_AWVALID <= wach_m_axi_awvalid;
wach_dout <= wach_dout_pkt;
END GENERATE gnawvld_pkt_fifo;
gaxi_wr_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AW_UNDERFLOW <= axi_aw_underflow_i;
END GENERATE gaxi_wr_ch_uf1;
gaxi_wr_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AW_OVERFLOW <= axi_aw_overflow_i;
END GENERATE gaxi_wr_ch_of1;
END GENERATE gwach2;
-- Register Slice for Write Address Channel
gwach_reg_slice: IF (C_WACH_TYPE = 1) GENERATE
wach_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => C_REG_SLICE_MODE_WACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wach_din,
S_VALID => S_AXI_AWVALID,
S_READY => S_AXI_AWREADY,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gwach_reg_slice;
gwdch2: IF (C_WDCH_TYPE = 0) GENERATE
SIGNAL wdch_re : STD_LOGIC := '0';
BEGIN
wdch_we <= wdch_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wdch_wr_en AND S_ACLK_EN;
wdch_re <= wdch_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wdch_rd_en AND M_ACLK_EN;
axi_wdch : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 2 OR C_IMPLEMENTATION_TYPE_WDCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 11 OR C_IMPLEMENTATION_TYPE_WDCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WDCH,
C_WR_DEPTH => C_WR_DEPTH_WDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WDCH,
C_RD_DEPTH => C_WR_DEPTH_WDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH,
C_USE_ECC => C_USE_ECC_WDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wdch_we,
RD_EN => wdch_re,
PROG_FULL_THRESH => AXI_W_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_W_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_W_INJECTDBITERR,
INJECTSBITERR => AXI_W_INJECTSBITERR,
DIN => wdch_din,
DOUT => wdch_dout,
FULL => wdch_full,
EMPTY => wdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_W_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_W_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_w_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_w_underflow_i,
DATA_COUNT => AXI_W_DATA_COUNT,
RD_DATA_COUNT => AXI_W_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_W_WR_DATA_COUNT,
SBITERR => AXI_W_SBITERR,
DBITERR => AXI_W_DBITERR,
WR_RST_BUSY => wr_rst_busy_wdch,
RD_RST_BUSY => rd_rst_busy_wdch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_wdch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wdch_rdy: IF (C_IMPLEMENTATION_TYPE_WDCH = 5 OR C_IMPLEMENTATION_TYPE_WDCH = 13) GENERATE
wdch_s_axi_wready <= NOT (wdch_full OR wr_rst_busy_wdch);
END GENERATE g8s_bi_wdch_rdy;
g8s_nbi_wdch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WDCH = 5 OR C_IMPLEMENTATION_TYPE_WDCH = 13)) GENERATE
wdch_s_axi_wready <= NOT (wdch_full);
END GENERATE g8s_nbi_wdch_rdy;
END GENERATE g8s_wdch_rdy;
g7s_wdch_rdy: IF (IS_8SERIES = 0) GENERATE
wdch_s_axi_wready <= NOT (wdch_full);
END GENERATE g7s_wdch_rdy;
wdch_m_axi_wvalid <= NOT wdch_empty;
S_AXI_WREADY <= wdch_s_axi_wready;
M_AXI_WVALID <= wdch_m_axi_wvalid;
gaxi_wr_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_W_UNDERFLOW <= axi_w_underflow_i;
END GENERATE gaxi_wr_ch_uf2;
gaxi_wr_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_W_OVERFLOW <= axi_w_overflow_i;
END GENERATE gaxi_wr_ch_of2;
END GENERATE gwdch2;
-- Register Slice for Write Data Channel
gwdch_reg_slice: IF (C_WDCH_TYPE = 1) GENERATE
wdch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wdch_din,
S_VALID => S_AXI_WVALID,
S_READY => S_AXI_WREADY,
-- Master side
M_PAYLOAD_DATA => wdch_dout,
M_VALID => M_AXI_WVALID,
M_READY => M_AXI_WREADY
);
END GENERATE gwdch_reg_slice;
gwrch2: IF (C_WRCH_TYPE = 0) GENERATE
SIGNAL wrch_we : STD_LOGIC := '0';
SIGNAL wrch_re : STD_LOGIC := '0';
BEGIN
wrch_we <= wrch_wr_en WHEN (C_HAS_MASTER_CE = 0) ELSE wrch_wr_en AND M_ACLK_EN;
wrch_re <= wrch_rd_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wrch_rd_en AND S_ACLK_EN;
axi_wrch : fifo_generator_v13_0_1_conv -- Write Response Channel
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 2 OR C_IMPLEMENTATION_TYPE_WRCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 11 OR C_IMPLEMENTATION_TYPE_WRCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WRCH,
C_WR_DEPTH => C_WR_DEPTH_WRCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WRCH,
C_RD_DEPTH => C_WR_DEPTH_WRCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WRCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WRCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WRCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH,
C_USE_ECC => C_USE_ECC_WRCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WRCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WRCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wrch_we,
RD_EN => wrch_re,
PROG_FULL_THRESH => AXI_B_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_B_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_B_INJECTDBITERR,
INJECTSBITERR => AXI_B_INJECTSBITERR,
DIN => wrch_din,
DOUT => wrch_dout,
FULL => wrch_full,
EMPTY => wrch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_B_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_B_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_b_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_b_underflow_i,
DATA_COUNT => AXI_B_DATA_COUNT,
RD_DATA_COUNT => AXI_B_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_B_WR_DATA_COUNT,
SBITERR => AXI_B_SBITERR,
DBITERR => AXI_B_DBITERR,
WR_RST_BUSY => wr_rst_busy_wrch,
RD_RST_BUSY => rd_rst_busy_wrch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
wrch_s_axi_bvalid <= NOT wrch_empty;
g8s_wrch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wrch_rdy: IF (C_IMPLEMENTATION_TYPE_WRCH = 5 OR C_IMPLEMENTATION_TYPE_WRCH = 13) GENERATE
wrch_m_axi_bready <= NOT (wrch_full OR wr_rst_busy_wrch);
END GENERATE g8s_bi_wrch_rdy;
g8s_nbi_wrch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WRCH = 5 OR C_IMPLEMENTATION_TYPE_WRCH = 13)) GENERATE
wrch_m_axi_bready <= NOT (wrch_full);
END GENERATE g8s_nbi_wrch_rdy;
END GENERATE g8s_wrch_rdy;
g7s_wrch_rdy: IF (IS_8SERIES = 0) GENERATE
wrch_m_axi_bready <= NOT (wrch_full);
END GENERATE g7s_wrch_rdy;
S_AXI_BVALID <= wrch_s_axi_bvalid;
M_AXI_BREADY <= wrch_m_axi_bready;
gaxi_wr_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_B_UNDERFLOW <= axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf3;
gaxi_wr_ch_of3: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_B_OVERFLOW <= axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of3;
END GENERATE gwrch2;
-- Register Slice for Write Response Channel
gwrch_reg_slice: IF (C_WRCH_TYPE = 1) GENERATE
wrch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WRCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WRCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wrch_din,
S_VALID => M_AXI_BVALID,
S_READY => M_AXI_BREADY,
-- Master side
M_PAYLOAD_DATA => wrch_dout,
M_VALID => S_AXI_BVALID,
M_READY => S_AXI_BREADY
);
END GENERATE gwrch_reg_slice;
gaxi_wr_ch_uf4: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_wr_underflow_i <= axi_aw_underflow_i OR axi_w_underflow_i OR axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf4;
gaxi_wr_ch_of4: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_wr_overflow_i <= axi_aw_overflow_i OR axi_w_overflow_i OR axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of4;
gaxi_pkt_fifo_wr: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
BEGIN
txn_count_en_up <= wdch_s_axi_wready AND wdch_we AND wdch_din(0);
txn_count_en_down <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
gaxi_mm_cc_pkt_wr: IF (C_COMMON_CLOCK = 1) GENERATE
proc_wr_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (txn_count_en_up = '1' AND txn_count_en_down = '0') THEN
wr_pkt_count <= wr_pkt_count + conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
ELSIF (txn_count_en_down = '1' AND txn_count_en_up = '0') THEN
wr_pkt_count <= wr_pkt_count - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
END IF;
END IF;
END PROCESS proc_wr_txn_cnt;
awvalid_en <= '1' WHEN (wr_pkt_count > conv_std_logic_vector(0,C_WR_PNTR_WIDTH_WDCH)) ELSE '0';
END GENERATE gaxi_mm_cc_pkt_wr;
END GENERATE gaxi_pkt_fifo_wr;
END GENERATE gwrch;
grdch: IF (C_HAS_AXI_RD_CHANNEL = 1) GENERATE
SIGNAL rach_din : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout_pkt : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_full : std_logic := '0';
SIGNAL rach_almost_full : std_logic := '0';
SIGNAL rach_prog_full : std_logic := '0';
SIGNAL rach_empty : std_logic := '0';
SIGNAL rach_almost_empty : std_logic := '0';
SIGNAL rach_prog_empty : std_logic := '0';
SIGNAL rdch_din : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_dout : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_full : std_logic := '0';
SIGNAL rdch_almost_full : std_logic := '0';
SIGNAL rdch_prog_full : std_logic := '0';
SIGNAL rdch_empty : std_logic := '0';
SIGNAL rdch_almost_empty : std_logic := '0';
SIGNAL rdch_prog_empty : std_logic := '0';
SIGNAL axi_ar_underflow_i : std_logic := '0';
SIGNAL axi_ar_overflow_i : std_logic := '0';
SIGNAL axi_r_underflow_i : std_logic := '0';
SIGNAL axi_r_overflow_i : std_logic := '0';
SIGNAL rach_s_axi_arready : std_logic := '0';
SIGNAL rach_m_axi_arvalid : std_logic := '0';
SIGNAL rach_wr_en : std_logic := '0';
SIGNAL rach_rd_en : std_logic := '0';
SIGNAL rdch_m_axi_rready : std_logic := '0';
SIGNAL rdch_s_axi_rvalid : std_logic := '0';
SIGNAL rdch_wr_en : std_logic := '0';
SIGNAL rdch_rd_en : std_logic := '0';
SIGNAL arvalid_en : std_logic := '0';
SIGNAL arready_pkt : std_logic := '0';
SIGNAL rdch_re : STD_LOGIC := '0';
SIGNAL wr_rst_busy_rach : STD_LOGIC := '0';
SIGNAL wr_rst_busy_rdch : STD_LOGIC := '0';
SIGNAL rd_rst_busy_rach : STD_LOGIC := '0';
SIGNAL rd_rst_busy_rdch : STD_LOGIC := '0';
CONSTANT ARID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RACH);
CONSTANT ARADDR_OFFSET : integer := ARID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT ARLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARADDR_OFFSET - C_AXI_LEN_WIDTH,ARADDR_OFFSET);
CONSTANT ARSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLEN_OFFSET - C_AXI_SIZE_WIDTH,ARLEN_OFFSET);
CONSTANT ARBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARSIZE_OFFSET - C_AXI_BURST_WIDTH,ARSIZE_OFFSET);
CONSTANT ARLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARBURST_OFFSET - C_AXI_LOCK_WIDTH,ARBURST_OFFSET);
CONSTANT ARCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLOCK_OFFSET - C_AXI_CACHE_WIDTH,ARLOCK_OFFSET);
CONSTANT ARPROT_OFFSET : integer := ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT ARQOS_OFFSET : integer := ARPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT ARREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARQOS_OFFSET - C_AXI_REGION_WIDTH,ARQOS_OFFSET);
CONSTANT ARUSER_OFFSET : integer := if_then_else(C_HAS_AXI_ARUSER = 1,ARREGION_OFFSET-C_AXI_ARUSER_WIDTH,ARREGION_OFFSET);
CONSTANT RID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RDCH);
CONSTANT RDATA_OFFSET : integer := RID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT RRESP_OFFSET : integer := RDATA_OFFSET - C_AXI_RRESP_WIDTH;
CONSTANT RUSER_OFFSET : integer := if_then_else(C_HAS_AXI_RUSER = 1,RRESP_OFFSET-C_AXI_RUSER_WIDTH,RRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_rd_ch: IF (C_AXI_TYPE /= 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
grach_din1: IF (C_HAS_AXI_ARUSER = 1) GENERATE
rach_din(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET) <= S_AXI_ARUSER;
M_AXI_ARUSER <= rach_dout(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET);
END GENERATE grach_din1;
grach_din2: IF (C_HAS_AXI_ARUSER = 0) GENERATE
M_AXI_ARUSER <= (OTHERS => '0');
END GENERATE grach_din2;
grach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rach_din(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET) <= S_AXI_ARID;
M_AXI_ARID <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET);
END GENERATE grach_din3;
grach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_ARID <= (OTHERS => '0');
END GENERATE grach_din4;
grach_din5: IF (C_AXI_TYPE = 1) GENERATE
rach_din(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET) <= S_AXI_ARREGION;
M_AXI_ARREGION <= rach_dout(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET);
END GENERATE grach_din5;
grach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_ARREGION <= (OTHERS => '0');
END GENERATE grach_din6;
rach_din(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET) <= S_AXI_ARADDR;
rach_din(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET) <= S_AXI_ARLEN;
rach_din(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET) <= S_AXI_ARSIZE;
rach_din(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET) <= S_AXI_ARBURST;
rach_din(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET) <= S_AXI_ARLOCK;
rach_din(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET) <= S_AXI_ARCACHE;
rach_din(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET) <= S_AXI_ARPROT;
rach_din(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET) <= S_AXI_ARQOS;
M_AXI_ARADDR <= rach_dout(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARLEN <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET);
M_AXI_ARSIZE <= rach_dout(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET);
M_AXI_ARBURST <= rach_dout(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET);
M_AXI_ARLOCK <= rach_dout(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET);
M_AXI_ARCACHE <= rach_dout(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET);
M_AXI_ARPROT <= rach_dout(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET);
M_AXI_ARQOS <= rach_dout(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET);
END GENERATE grach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
grdch_din1: IF (C_HAS_AXI_RUSER = 1) GENERATE
rdch_din(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET) <= M_AXI_RUSER;
S_AXI_RUSER <= rdch_dout(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET);
END GENERATE grdch_din1;
grdch_din2: IF (C_HAS_AXI_RUSER = 0) GENERATE
S_AXI_RUSER <= (OTHERS => '0');
END GENERATE grdch_din2;
grdch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rdch_din(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET) <= M_AXI_RID;
S_AXI_RID <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET);
END GENERATE grdch_din3;
grdch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_RID <= (OTHERS => '0');
END GENERATE grdch_din4;
rdch_din(RID_OFFSET-1 DOWNTO RDATA_OFFSET) <= M_AXI_RDATA;
rdch_din(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET) <= M_AXI_RRESP;
rdch_din(0) <= M_AXI_RLAST;
S_AXI_RDATA <= rdch_dout(RID_OFFSET-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
S_AXI_RLAST <= rdch_dout(0);
END GENERATE grdch1;
END GENERATE axi_full_din_rd_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Read Address Channel optional ports
axi_lite_din_rd_ch: IF (C_AXI_TYPE = 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
rach_din <= S_AXI_ARADDR & S_AXI_ARPROT;
M_AXI_ARADDR <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARPROT <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARPROT_OFFSET);
END GENERATE grach1;
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
rdch_din <= M_AXI_RDATA & M_AXI_RRESP;
S_AXI_RDATA <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
END GENERATE grdch1;
END GENERATE axi_lite_din_rd_ch;
-- Write protection for Read Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grach_wr_en1: IF (C_PROG_FULL_TYPE_RACH = 0) GENERATE
rach_wr_en <= S_AXI_ARVALID;
END GENERATE grach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grach_wr_en2: IF (C_PROG_FULL_TYPE_RACH /= 0) GENERATE
rach_wr_en <= rach_s_axi_arready AND S_AXI_ARVALID;
END GENERATE grach_wr_en2;
-- Write protection for Read Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grdch_wr_en1: IF (C_PROG_FULL_TYPE_RDCH = 0) GENERATE
rdch_wr_en <= M_AXI_RVALID;
END GENERATE grdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grdch_wr_en2: IF (C_PROG_FULL_TYPE_RDCH /= 0) GENERATE
rdch_wr_en <= rdch_m_axi_rready AND M_AXI_RVALID;
END GENERATE grdch_wr_en2;
-- Read protection for Read Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grach_rd_en1: IF (C_PROG_EMPTY_TYPE_RACH = 0) GENERATE
gpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= arready_pkt AND arvalid_en;
END GENERATE;
gnpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= M_AXI_ARREADY;
END GENERATE;
END GENERATE grach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grach_rd_en2: IF (C_PROG_EMPTY_TYPE_RACH /= 0) GENERATE
gaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
END GENERATE gaxi_mm_rach_rd_en2;
gnaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND M_AXI_ARREADY;
END GENERATE gnaxi_mm_rach_rd_en2;
END GENERATE grach_rd_en2;
-- Read protection for Read Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grdch_rd_en1: IF (C_PROG_EMPTY_TYPE_RDCH = 0) GENERATE
rdch_rd_en <= S_AXI_RREADY;
END GENERATE grdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grdch_rd_en2: IF (C_PROG_EMPTY_TYPE_RDCH /= 0) GENERATE
rdch_rd_en <= rdch_s_axi_rvalid AND S_AXI_RREADY;
END GENERATE grdch_rd_en2;
grach2: IF (C_RACH_TYPE = 0) GENERATE
SIGNAL rach_we : STD_LOGIC := '0';
SIGNAL rach_re : STD_LOGIC := '0';
BEGIN
rach_we <= rach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rach_wr_en AND S_ACLK_EN;
rach_re <= rach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE rach_rd_en AND M_ACLK_EN;
axi_rach : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_RACH = 2 OR C_IMPLEMENTATION_TYPE_RACH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_RACH = 11 OR C_IMPLEMENTATION_TYPE_RACH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RACH,
C_WR_DEPTH => C_WR_DEPTH_RACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_DOUT_WIDTH => C_DIN_WIDTH_RACH,
C_RD_DEPTH => C_WR_DEPTH_RACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH,
C_USE_ECC => C_USE_ECC_RACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_RACH = 1),0,C_APPLICATION_TYPE_RACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rach_we,
RD_EN => rach_re,
PROG_FULL_THRESH => AXI_AR_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AR_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AR_INJECTDBITERR,
INJECTSBITERR => AXI_AR_INJECTSBITERR,
DIN => rach_din,
DOUT => rach_dout_pkt,
FULL => rach_full,
EMPTY => rach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AR_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AR_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_ar_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_ar_underflow_i,
DATA_COUNT => AXI_AR_DATA_COUNT,
RD_DATA_COUNT => AXI_AR_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AR_WR_DATA_COUNT,
SBITERR => AXI_AR_SBITERR,
DBITERR => AXI_AR_DBITERR,
WR_RST_BUSY => wr_rst_busy_rach,
RD_RST_BUSY => rd_rst_busy_rach,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_rach_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_rach_rdy: IF (C_IMPLEMENTATION_TYPE_RACH = 5 OR C_IMPLEMENTATION_TYPE_RACH = 13) GENERATE
rach_s_axi_arready <= NOT (rach_full OR wr_rst_busy_rach);
END GENERATE g8s_bi_rach_rdy;
g8s_nbi_rach_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_RACH = 5 OR C_IMPLEMENTATION_TYPE_RACH = 13)) GENERATE
rach_s_axi_arready <= NOT (rach_full);
END GENERATE g8s_nbi_rach_rdy;
END GENERATE g8s_rach_rdy;
g7s_rach_rdy: IF (IS_8SERIES = 0) GENERATE
rach_s_axi_arready <= NOT (rach_full);
END GENERATE g7s_rach_rdy;
rach_m_axi_arvalid <= NOT rach_empty;
S_AXI_ARREADY <= rach_s_axi_arready;
gaxi_arvld: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL arvalid_pkt : STD_LOGIC := '0';
BEGIN
arvalid_pkt <= rach_m_axi_arvalid AND arvalid_en;
rach_pkt_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => rach_dout_pkt,
S_VALID => arvalid_pkt,
S_READY => arready_pkt,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE gaxi_arvld;
gnaxi_arvld: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
M_AXI_ARVALID <= rach_m_axi_arvalid;
rach_dout <= rach_dout_pkt;
END GENERATE gnaxi_arvld;
gaxi_rd_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AR_UNDERFLOW <= axi_ar_underflow_i;
END GENERATE gaxi_rd_ch_uf1;
gaxi_rd_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AR_OVERFLOW <= axi_ar_overflow_i;
END GENERATE gaxi_rd_ch_of1;
END GENERATE grach2;
-- Register Slice for Read Address Channel
grach_reg_slice: IF (C_RACH_TYPE = 1) GENERATE
rach_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => C_REG_SLICE_MODE_RACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rach_din,
S_VALID => S_AXI_ARVALID,
S_READY => S_AXI_ARREADY,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE grach_reg_slice;
grdch2: IF (C_RDCH_TYPE = 0) GENERATE
SIGNAL rdch_we : STD_LOGIC := '0';
BEGIN
rdch_we <= rdch_wr_en WHEN (C_HAS_MASTER_CE = 0) ELSE rdch_wr_en AND M_ACLK_EN;
rdch_re <= rdch_rd_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rdch_rd_en AND S_ACLK_EN;
axi_rdch : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 2 OR C_IMPLEMENTATION_TYPE_RDCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 11 OR C_IMPLEMENTATION_TYPE_RDCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RDCH,
C_WR_DEPTH => C_WR_DEPTH_RDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_RDCH,
C_RD_DEPTH => C_WR_DEPTH_RDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH,
C_USE_ECC => C_USE_ECC_RDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_RDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rdch_we,
RD_EN => rdch_re,
PROG_FULL_THRESH => AXI_R_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_R_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_R_INJECTDBITERR,
INJECTSBITERR => AXI_R_INJECTSBITERR,
DIN => rdch_din,
DOUT => rdch_dout,
FULL => rdch_full,
EMPTY => rdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_R_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_R_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_r_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_r_underflow_i,
DATA_COUNT => AXI_R_DATA_COUNT,
RD_DATA_COUNT => AXI_R_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_R_WR_DATA_COUNT,
SBITERR => AXI_R_SBITERR,
DBITERR => AXI_R_DBITERR,
WR_RST_BUSY => wr_rst_busy_rdch,
RD_RST_BUSY => rd_rst_busy_rdch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
rdch_s_axi_rvalid <= NOT rdch_empty;
g8s_rdch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_rdch_rdy: IF (C_IMPLEMENTATION_TYPE_RDCH = 5 OR C_IMPLEMENTATION_TYPE_RDCH = 13) GENERATE
rdch_m_axi_rready <= NOT (rdch_full OR wr_rst_busy_rdch);
END GENERATE g8s_bi_rdch_rdy;
g8s_nbi_rdch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_RDCH = 5 OR C_IMPLEMENTATION_TYPE_RDCH = 13)) GENERATE
rdch_m_axi_rready <= NOT (rdch_full);
END GENERATE g8s_nbi_rdch_rdy;
END GENERATE g8s_rdch_rdy;
g7s_rdch_rdy: IF (IS_8SERIES = 0) GENERATE
rdch_m_axi_rready <= NOT (rdch_full);
END GENERATE g7s_rdch_rdy;
S_AXI_RVALID <= rdch_s_axi_rvalid;
M_AXI_RREADY <= rdch_m_axi_rready;
gaxi_rd_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_R_UNDERFLOW <= axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf2;
gaxi_rd_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_R_OVERFLOW <= axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of2;
END GENERATE grdch2;
-- Register Slice for Read Data Channel
grdch_reg_slice: IF (C_RDCH_TYPE = 1) GENERATE
rdch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_RDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rdch_din,
S_VALID => M_AXI_RVALID,
S_READY => M_AXI_RREADY,
-- Master side
M_PAYLOAD_DATA => rdch_dout,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY
);
END GENERATE grdch_reg_slice;
gaxi_rd_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_rd_underflow_i <= axi_ar_underflow_i OR axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf3;
gaxi_rd_ch_of3: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_rd_overflow_i <= axi_ar_overflow_i OR axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of3;
gaxi_pkt_fifo_rd: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL rd_burst_length : STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_free_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_committed_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
SIGNAL rdch_rd_ok : STD_LOGIC := '0';
SIGNAL accept_next_pkt : STD_LOGIC := '0';
SIGNAL decrement_val : INTEGER := 0;
BEGIN
rd_burst_length <= ('0' & rach_dout_pkt(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET)) + conv_std_logic_vector(1,9);
accept_next_pkt <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
rdch_rd_ok <= rdch_re AND rdch_s_axi_rvalid;
arvalid_en <= '1' WHEN (rd_fifo_free_space >= rd_burst_length) ELSE '0';
gaxi_mm_cc_pkt_rd: IF (C_COMMON_CLOCK = 1) GENERATE
rd_fifo_free_space <= conv_std_logic_vector(C_WR_DEPTH_RDCH-conv_integer(rd_fifo_committed_space),C_WR_PNTR_WIDTH_RDCH+1);
decrement_val <= 1 WHEN (rdch_rd_ok = '1') ELSE 0;
proc_rd_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
rd_fifo_committed_space <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (accept_next_pkt = '1') THEN
-- Subtract 1 if read happens on read data FIFO while adding ARLEN
rd_fifo_committed_space <= rd_fifo_committed_space + conv_std_logic_vector((conv_integer(rd_burst_length) - decrement_val), C_WR_PNTR_WIDTH_RDCH+1);
ELSIF (rdch_rd_ok = '1') THEN
-- Subtract 1 whenever read happens on read data FIFO
rd_fifo_committed_space <= rd_fifo_committed_space - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_RDCH+1);
END IF;
END IF;
END PROCESS proc_rd_txn_cnt;
END GENERATE gaxi_mm_cc_pkt_rd;
END GENERATE gaxi_pkt_fifo_rd;
END GENERATE grdch;
gaxi_comm_uf: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
grdwr_uf1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_wr_underflow_i OR axi_rd_underflow_i;
END GENERATE grdwr_uf1;
grdwr_uf2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
UNDERFLOW <= axi_wr_underflow_i;
END GENERATE grdwr_uf2;
grdwr_uf3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_rd_underflow_i;
END GENERATE grdwr_uf3;
END GENERATE gaxi_comm_uf;
gaxi_comm_of: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
grdwr_of1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_wr_overflow_i OR axi_rd_overflow_i;
END GENERATE grdwr_of1;
grdwr_of2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
OVERFLOW <= axi_wr_overflow_i;
END GENERATE grdwr_of2;
grdwr_of3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_rd_overflow_i;
END GENERATE grdwr_of3;
END GENERATE gaxi_comm_of;
END GENERATE gaxifull;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Pass Through Logic or Wiring Logic
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxi_pass_through: IF (C_WACH_TYPE = 2 OR C_WDCH_TYPE = 2 OR C_WRCH_TYPE = 2 OR
C_RACH_TYPE = 2 OR C_RDCH_TYPE = 2 OR C_AXIS_TYPE = 2) GENERATE
gwach_pass_through: IF (C_WACH_TYPE = 2) GENERATE -- Wiring logic for Write Address Channel
M_AXI_AWID <= S_AXI_AWID;
M_AXI_AWADDR <= S_AXI_AWADDR;
M_AXI_AWLEN <= S_AXI_AWLEN;
M_AXI_AWSIZE <= S_AXI_AWSIZE;
M_AXI_AWBURST <= S_AXI_AWBURST;
M_AXI_AWLOCK <= S_AXI_AWLOCK;
M_AXI_AWCACHE <= S_AXI_AWCACHE;
M_AXI_AWPROT <= S_AXI_AWPROT;
M_AXI_AWQOS <= S_AXI_AWQOS;
M_AXI_AWREGION <= S_AXI_AWREGION;
M_AXI_AWUSER <= S_AXI_AWUSER;
S_AXI_AWREADY <= M_AXI_AWREADY;
M_AXI_AWVALID <= S_AXI_AWVALID;
END GENERATE gwach_pass_through;
-- Wiring logic for Write Data Channel
gwdch_pass_through: IF (C_WDCH_TYPE = 2) GENERATE
M_AXI_WID <= S_AXI_WID;
M_AXI_WDATA <= S_AXI_WDATA;
M_AXI_WSTRB <= S_AXI_WSTRB;
M_AXI_WLAST <= S_AXI_WLAST;
M_AXI_WUSER <= S_AXI_WUSER;
S_AXI_WREADY <= M_AXI_WREADY;
M_AXI_WVALID <= S_AXI_WVALID;
END GENERATE gwdch_pass_through;
-- Wiring logic for Write Response Channel
gwrch_pass_through: IF (C_WRCH_TYPE = 2) GENERATE
S_AXI_BID <= M_AXI_BID;
S_AXI_BRESP <= M_AXI_BRESP;
S_AXI_BUSER <= M_AXI_BUSER;
M_AXI_BREADY <= S_AXI_BREADY;
S_AXI_BVALID <= M_AXI_BVALID;
END GENERATE gwrch_pass_through;
-- Pass Through Logic for Read Channel
grach_pass_through: IF (C_RACH_TYPE = 2) GENERATE -- Wiring logic for Read Address Channel
M_AXI_ARID <= S_AXI_ARID;
M_AXI_ARADDR <= S_AXI_ARADDR;
M_AXI_ARLEN <= S_AXI_ARLEN;
M_AXI_ARSIZE <= S_AXI_ARSIZE;
M_AXI_ARBURST <= S_AXI_ARBURST;
M_AXI_ARLOCK <= S_AXI_ARLOCK;
M_AXI_ARCACHE <= S_AXI_ARCACHE;
M_AXI_ARPROT <= S_AXI_ARPROT;
M_AXI_ARQOS <= S_AXI_ARQOS;
M_AXI_ARREGION <= S_AXI_ARREGION;
M_AXI_ARUSER <= S_AXI_ARUSER;
S_AXI_ARREADY <= M_AXI_ARREADY;
M_AXI_ARVALID <= S_AXI_ARVALID;
END GENERATE grach_pass_through;
grdch_pass_through: IF (C_RDCH_TYPE = 2) GENERATE -- Wiring logic for Read Data Channel
S_AXI_RID <= M_AXI_RID;
S_AXI_RLAST <= M_AXI_RLAST;
S_AXI_RUSER <= M_AXI_RUSER;
S_AXI_RDATA <= M_AXI_RDATA;
S_AXI_RRESP <= M_AXI_RRESP;
S_AXI_RVALID <= M_AXI_RVALID;
M_AXI_RREADY <= S_AXI_RREADY;
END GENERATE grdch_pass_through;
gaxis_pass_through: IF (C_AXIS_TYPE = 2) GENERATE -- Wiring logic for AXI Streaming
M_AXIS_TDATA <= S_AXIS_TDATA;
M_AXIS_TSTRB <= S_AXIS_TSTRB;
M_AXIS_TKEEP <= S_AXIS_TKEEP;
M_AXIS_TID <= S_AXIS_TID;
M_AXIS_TDEST <= S_AXIS_TDEST;
M_AXIS_TUSER <= S_AXIS_TUSER;
M_AXIS_TLAST <= S_AXIS_TLAST;
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TVALID <= S_AXIS_TVALID;
END GENERATE gaxis_pass_through;
END GENERATE gaxi_pass_through;
END behavioral;
| bsd-3-clause |
cintiamh/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
ymei/TMSPlane | Firmware/test_bench/shiftreg_drive_tb.vhd | 2 | 6005 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:39:52 01/07/2015
-- Design Name: shiftreg_drive_tb
-- Module Name:
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: shiftreg_drive
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE IEEE.NUMERIC_STD.ALL;
ENTITY shiftreg_drive_tb IS
END shiftreg_drive_tb;
ARCHITECTURE behavior OF shiftreg_drive_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shiftreg_drive
GENERIC (
DATA_WIDTH : positive := 32; -- parallel data width
CLK_DIV_WIDTH : positive := 16;
DELAY_AFTER_SYNCn : natural := 0; -- number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL : std_logic := '0'; -- High or Low for SCLK when not switching
DOUT_DRIVE_EDGE : std_logic := '1'; -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE : std_logic := '0' -- 1/0 rising/falling edge of SCLK captures new DIN bit
);
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
CLK_DIV : IN std_logic_vector(CLK_DIV_WIDTH-1 DOWNTO 0); -- SCLK freq is CLK / 2**(CLK_DIV)
DATAIN : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
START : IN std_logic;
BUSY : OUT std_logic;
DATAOUT : OUT std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
SCLK : OUT std_logic;
DOUT : OUT std_logic;
SYNCn : OUT std_logic;
DIN : IN std_logic
);
END COMPONENT;
COMPONENT edge_sync
GENERIC (
EDGE : std_logic := '1' -- '1' : rising edge, '0' falling edge
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
EI : IN std_logic;
SO : OUT std_logic
);
END COMPONENT;
COMPONENT fifo16to32
PORT (
RST : IN std_logic;
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
DIN : IN std_logic_vector(15 DOWNTO 0);
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DOUT : OUT std_logic_vector(31 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL CLK : std_logic := '0';
SIGNAL CLK_DIV : std_logic_vector(15 DOWNTO 0) := x"0003";
SIGNAL RESET : std_logic := '0';
SIGNAL DATAIN : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL START : std_logic := '0';
SIGNAL DIN : std_logic;
--Outputs
SIGNAL DATAOUT : std_logic_vector(31 DOWNTO 0);
SIGNAL BUSY : std_logic;
SIGNAL SCLK : std_logic;
SIGNAL DOUT : std_logic;
SIGNAL SYNCn : std_logic;
-- internals
SIGNAL wr_start : std_logic := '0';
SIGNAL fifo_din : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL fifo_wr_en : std_logic;
SIGNAL fifo_rd_en : std_logic;
SIGNAL fifo_full : std_logic;
SIGNAL fifo_empty : std_logic;
-- Clock period definitions
CONSTANT CLK_period : time := 10 ns;
CONSTANT SCLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : shiftreg_drive PORT MAP (
CLK => CLK,
CLK_DIV => CLK_DIV,
RESET => RESET,
DATAIN => DATAIN,
START => START,
BUSY => BUSY,
DATAOUT => DATAOUT,
SCLK => SCLK,
DOUT => DOUT,
SYNCn => SYNCn,
DIN => DIN
);
DIN <= DOUT;
fifo : fifo16to32
PORT MAP (
RST => RESET,
WR_CLK => CLK,
RD_CLK => CLK,
DIN => fifo_din,
WR_EN => fifo_wr_en,
RD_EN => fifo_rd_en,
DOUT => DATAIN,
FULL => fifo_full,
EMPTY => fifo_empty
);
START <= NOT fifo_empty;
-- rising edge of busy
rd_es : edge_sync
GENERIC MAP (
EDGE => '1' -- '1' : rising edge, '0' falling edge
)
PORT MAP (
RESET => RESET,
CLK => CLK,
EI => BUSY,
SO => fifo_rd_en
);
wr_es : edge_sync
GENERIC MAP (
EDGE => '1' -- '1' : rising edge, '0' falling edge
)
PORT MAP (
RESET => RESET,
CLK => CLK,
EI => wr_start,
SO => fifo_wr_en
);
-- Clock process definitions
CLK_process : PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_period/2;
CLK <= '1';
WAIT FOR CLK_period/2;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
WAIT FOR 25ns;
-- hold reset state for 80 ns.
RESET <= '1';
WAIT FOR 80 ns;
RESET <= '0';
WAIT FOR CLK_period*12;
-- insert stimulus here
WAIT FOR 10ps;
fifo_din <= x"505a";
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
fifo_din <= x"a505";
WAIT FOR CLK_period;
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
WAIT FOR 20ns;
fifo_din <= x"abcd";
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
fifo_din <= x"1234";
WAIT FOR CLK_period;
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
WAIT FOR 1100ns;
fifo_din <= x"4321";
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
fifo_din <= x"dcba";
WAIT FOR CLK_period;
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
WAIT;
END PROCESS;
END;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/gig_eth/KC705/fifo/tri_mode_ethernet_mac_0_tx_client_fifo.vhd | 4 | 67415 | --------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_tx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a transmitter side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is built around an Inferred Dual Port RAM,
-- giving a total memory capacity of 4096 bytes.
--
-- Valid frame data received from the user interface is written
-- into the Block RAM on the tx_fifo_aclkk. The FIFO will store
-- frames up to 4kbytes in length. If larger frames are written
-- to the FIFO, the AxiStream interface will accept the rest of the
-- frame, but that frame will be dropped by the FIFO and the
-- overflow signal will be asserted.
--
-- The FIFO is designed to work with a minimum frame length of 14
-- bytes.
--
-- When there is at least one complete frame in the FIFO, the MAC
-- transmitter AxiStream interface will be driven to request frame
-- transmission by placing the first byte of the frame onto
-- tx_axis_mac_tdata and by asserting tx_axis_mac_tvalid. The MAC will later
-- respond by asserting tx_axis_mac_tready. At this point the remaining
-- frame data is read out of the FIFO subject to tx_axis_mac_tready.
-- Data is read out of the FIFO on the tx_mac_aclk.
--
-- If the generic FULL_DUPLEX_ONLY is set to false, the FIFO will
-- requeue and retransmit frames as requested by the MAC. Once a
-- frame has been transmitted by the FIFO it is stored until the
-- possible retransmit window for that frame has expired.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The minimum write clock
-- frequency is the read clock frequency divided by 2.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- Entity declaration for the Transmitter FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_tx_client_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end tri_mode_ethernet_mac_0_tx_client_fifo;
architecture RTL of tri_mode_ethernet_mac_0_tx_client_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the block RAM
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_bram_tdp
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 12
);
port (
-- Port A
a_clk : in std_logic;
a_rst : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
-- Encoded read state machine states.
type rd_state_typ is (IDLE_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
START_DATA1_s,
DATA_PRELOAD1_s,
DATA_PRELOAD2_s,
WAIT_HANDSHAKE_s,
FRAME_s,
HANDSHAKE_s,
FINISH_s,
DROP_ERR_s,
DROP_s,
RETRANSMIT_ERR_s,
RETRANSMIT_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states,
type wr_state_typ is (WAIT_s,
DATA_s,
EOF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe is array (0 to 1) of std_logic;
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_sof_pipe : cntl_pipe;
signal wr_eof_pipe : cntl_pipe;
signal wr_accept_pipe : cntl_pipe;
signal wr_accept_bram : std_logic;
signal wr_sof_int : std_logic;
signal wr_eof_bram : std_logic_vector(0 downto 0);
signal wr_eof_reg : std_logic;
signal wr_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0) := (others => '0');
signal wr_fifo_full : std_logic;
signal wr_en : std_logic;
signal wr_ovflow_dst_rdy : std_logic;
signal tx_axis_fifo_tready_int_n : std_logic;
signal data_count : unsigned(3 downto 0) := (others => '0');
signal frame_in_fifo : std_logic;
signal frames_in_fifo : std_logic;
signal frame_in_fifo_valid : std_logic;
signal frame_in_fifo_valid_tog : std_logic := '0';
signal frame_in_fifo_valid_sync : std_logic;
signal frame_in_fifo_valid_delay : std_logic;
signal rd_eof : std_logic;
signal rd_eof_pipe : std_logic;
signal rd_eof_reg : std_logic;
signal rd_addr : unsigned(11 downto 0) := (others => '0');
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_eof_data_bram : std_logic_vector(8 downto 0);
signal rd_data_bram : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_delay : std_logic_vector(7 downto 0) := (others => '0');
signal rd_eof_bram : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_tran_frame_tog : std_logic := '0';
signal wr_tran_frame_sync : std_logic;
signal wr_tran_frame_delay : std_logic := '0';
signal rd_retran_frame_tog : std_logic := '0';
signal wr_retran_frame_sync : std_logic;
signal wr_retran_frame_delay : std_logic := '0';
signal wr_store_frame : std_logic;
signal wr_eof_state : std_logic;
signal wr_eof_state_reg : std_logic;
signal wr_transmit_frame : std_logic;
signal wr_transmit_frame_delay : std_logic;
signal wr_retransmit_frame : std_logic;
signal wr_frames : unsigned(8 downto 0) := (others => '0');
signal wr_frame_in_fifo : std_logic;
signal wr_frames_in_fifo : std_logic;
signal rd_16_count : unsigned(3 downto 0) := (others => '0');
signal rd_txfer_en : std_logic;
signal rd_addr_txfer : unsigned(11 downto 0) := (others => '0');
signal rd_txfer_tog : std_logic := '0';
signal wr_txfer_tog_sync : std_logic;
signal wr_txfer_tog_delay : std_logic := '0';
signal wr_txfer_en : std_logic;
signal wr_rd_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_diff : unsigned(11 downto 0) := (others => '0');
signal wr_fifo_status : unsigned(3 downto 0) := (others => '0');
signal rd_drop_frame : std_logic;
signal rd_retransmit : std_logic;
signal rd_start_addr : unsigned(11 downto 0) := (others => '0');
signal rd_start_addr_load : std_logic;
signal rd_start_addr_reload : std_logic;
signal rd_dec_addr : unsigned(11 downto 0) := (others => '0');
signal rd_transmit_frame : std_logic;
signal rd_retransmit_frame : std_logic;
signal rd_col_window_expire : std_logic;
signal rd_col_window_pipe : cntl_pipe;
signal wr_col_window_pipe : cntl_pipe;
signal wr_fifo_overflow : std_logic;
signal rd_slot_timer : unsigned(9 downto 0) := (others => '0');
signal wr_col_window_expire : std_logic;
signal rd_idle_state : std_logic;
signal tx_axis_mac_tdata_int_frame : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int_handshake : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal tx_axis_mac_tvalid_int_finish : std_logic;
signal tx_axis_mac_tvalid_int_droperr : std_logic;
signal tx_axis_mac_tvalid_int_retransmiterr : std_logic;
signal tx_axis_mac_tlast_int_frame_handshake : std_logic;
signal tx_axis_mac_tlast_int_finish : std_logic;
signal tx_axis_mac_tlast_int_droperr : std_logic;
signal tx_axis_mac_tlast_int_retransmiterr : std_logic;
signal tx_axis_mac_tuser_int_droperr : std_logic;
signal tx_axis_mac_tuser_int_retransmit : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_mac_reset : std_logic;
-- Small delay for simulation purposes.
constant dly : time := 1 ps;
------------------------------------------------------------------------------
-- Attributes for FIFO simulation and synthesis
------------------------------------------------------------------------------
-- ASYNC_REG attributes added to simulate actual behaviour under
-- asynchronous operating conditions.
attribute ASYNC_REG : string;
attribute ASYNC_REG of wr_rd_addr : signal is "TRUE";
attribute ASYNC_REG of wr_col_window_pipe : signal is "TRUE";
------------------------------------------------------------------------------
-- Begin FIFO architecture
------------------------------------------------------------------------------
begin
-- invert reset sense as architecture is optimised for active high resets
tx_fifo_reset <= not tx_fifo_resetn;
tx_mac_reset <= not tx_mac_resetn;
------------------------------------------------------------------------------
-- Write state machine and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are WAIT, DATA, EOF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_state <= WAIT_s after dly;
else
wr_state <= wr_nxt_state after dly;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinitorial.
next_wrs_p : process(wr_state, wr_sof_pipe(1), wr_eof_pipe(0), wr_eof_pipe(1),
wr_eof_bram(0), wr_fifo_overflow, data_count)
begin
case wr_state is
when WAIT_s =>
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
else
wr_nxt_state <= WAIT_s;
end if;
when DATA_s =>
-- Wait for the end of frame to be detected.
if wr_fifo_overflow = '1' and wr_eof_pipe(0) = '0'
and wr_eof_pipe(1) = '0' then
wr_nxt_state <= OVFLOW_s;
elsif wr_eof_pipe(1) = '1' then
if data_count(3 downto 2) /= "11" then
wr_nxt_state <= OVFLOW_s;
else
wr_nxt_state <= EOF_s;
end if;
else
wr_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- If the start of frame is already in the pipe, a back-to-back frame
-- transmission has occured. Move straight back to frame state.
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
elsif wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= EOF_s;
end if;
when OVFLOW_s =>
-- Wait until the end of frame is reached before clearing the overflow.
if wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= WAIT_s;
end case;
end process;
-- small frame count - frames smaller than 10 bytes are problematic as the frame_in_fifo cannot
-- react quickly enough - empty detect could be used in the read domain but this doesn't fully cover all cases
-- the cleanest fix is to simply ignore frames smaller than 10 bytes
-- generate a counter which is cleaered on an sof and counts in data
data_count_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
data_count <= (others => '0') after dly;
else
if wr_sof_pipe(1) = '1' then
data_count <= (others => '0') after dly;
else
if data_count(3 downto 2) /= "11" then
data_count <= data_count + "0001" after dly;
end if;
end if;
end if;
end if;
end process data_count_p;
-- Decode output signals, combinatorial.
-- wr_en is used to enable the BRAM write and the address to increment.
wr_en <= '0' when wr_state = OVFLOW_s else wr_accept_bram;
wr_addr_inc <= wr_en;
wr_addr_reload <= '1' when wr_state = OVFLOW_s else '0';
wr_start_addr_load <= '1' when wr_state = EOF_s and wr_nxt_state = WAIT_s
else
'1' when wr_state = EOF_s and wr_nxt_state = DATA_s
else '0';
-- Pause the AxiStream handshake when the FIFO is full.
tx_axis_fifo_tready_int_n <= wr_ovflow_dst_rdy when wr_state = OVFLOW_s
else wr_fifo_full;
tx_axis_fifo_tready <= not tx_axis_fifo_tready_int_n;
-- Generate user overflow indicator.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
-- When in overflow and have captured ovflow EOF, set tx_axis_fifo_tready again.
p_ovflow_dst_rdy : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_ovflow_dst_rdy <= '0' after dly;
else
if wr_fifo_overflow = '1' and wr_state = DATA_s then
wr_ovflow_dst_rdy <= '0' after dly;
elsif tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tlast = '1' then
wr_ovflow_dst_rdy <= '1' after dly;
end if;
end if;
end if;
end process;
-- EOF signals for use in overflow logic.
wr_eof_state <= '1' when wr_state = EOF_s else '0';
p_reg_eof_st : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_eof_state_reg <= '0' after dly;
else
wr_eof_state_reg <= wr_eof_state after dly;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Read state machine and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are IDLE, QUEUE1, QUEUE2, QUEUE3, QUEUE_ACK, WAIT_ACK, FRAME,
-- HANDSHAKE, FINISH, DROP_ERR, DROP, RETRANSMIT_ERR, RETRANSMIT.
-- Clock state to next state.
clock_rds_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_state <= IDLE_s after dly;
else
rd_state <= rd_nxt_state after dly;
end if;
end if;
end process clock_rds_p;
------------------------------------------------------------------------------
-- Full duplex-only state machine.
gen_fd_sm : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, frames_in_fifo, frame_in_fifo_valid, rd_eof, rd_eof_reg, tx_axis_mac_tready)
begin
case rd_state is
when IDLE_s =>
-- If there is a frame in the FIFO, start to queue the new frame
-- to the output.
if (frame_in_fifo = '1' and frame_in_fifo_valid = '1') or frames_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= START_DATA1_s;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_PRELOAD1_s;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when FRAME_s =>
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
if tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_fd_sm;
------------------------------------------------------------------------------
-- Full and half duplex state machine.
gen_hd_sm : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Decode the next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, frames_in_fifo, frame_in_fifo_valid, rd_eof_reg, tx_axis_mac_tready,
rd_drop_frame, rd_retransmit)
begin
case rd_state is
when IDLE_s =>
-- If a retransmit request is detected then prepare to retransmit.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- If there is a frame in the FIFO, then queue the new frame to
-- the output.
elsif (frame_in_fifo = '1' and frame_in_fifo_valid = '1') or frames_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE2_s;
end if;
when QUEUE2_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE3_s;
end if;
when QUEUE3_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= START_DATA1_s;
end if;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= DATA_PRELOAD2_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD2_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= WAIT_HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= DATA_PRELOAD2_s;
end if;
when WAIT_HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_HANDSHAKE_s;
end if;
when FRAME_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If a collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when DROP_ERR_s =>
-- FIFO is ready to drop the frame. Assure that the MAC has
-- accepted the final byte and err signal before dropping.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= DROP_s;
else
rd_nxt_state <= DROP_ERR_s;
end if;
when DROP_s =>
-- Wait until rest of frame has been cleared.
if rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= DROP_s;
end if;
when RETRANSMIT_ERR_s =>
-- FIFO is ready to retransmit the frame. Assure that the MAC has
-- accepted the final byte and err signal before retransmitting.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= RETRANSMIT_ERR_s;
end if;
when RETRANSMIT_s =>
-- Reload the data pipeline from the start of the frame.
rd_nxt_state <= QUEUE1_s;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_hd_sm;
-- Combinatorially select tdata candidates.
tx_axis_mac_tdata_int_frame <= tx_axis_mac_tdata_int when rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s
else rd_data_pipe;
tx_axis_mac_tdata_int_handshake <= rd_data_pipe when rd_nxt_state = FINISH_s
else tx_axis_mac_tdata_int;
tx_axis_mac_tdata <= tx_axis_mac_tdata_int;
-- Decode output tdata based on current and next read state.
rd_data_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_frame after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_handshake after dly;
when others =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
end case;
end if;
end if;
end process rd_data_decode_p;
-- Combinatorially select tvalid candidates.
tx_axis_mac_tvalid_int_finish <= '0' when rd_nxt_state = IDLE_s
else '1';
tx_axis_mac_tvalid_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tvalid_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tvalid based on current and next read state.
rd_dv_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tvalid <= '1' after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tvalid <= '1' after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when DATA_PRELOAD1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tvalid <= '1' after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FINISH_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_retransmiterr after dly;
when others =>
tx_axis_mac_tvalid <= '0' after dly;
end case;
end if;
end if;
end process rd_dv_decode_p;
-- Combinatorially select tlast candidates.
tx_axis_mac_tlast_int_frame_handshake <= rd_eof_reg when rd_nxt_state = FINISH_s
else '0';
tx_axis_mac_tlast_int_finish <= '0' when rd_nxt_state = IDLE_s
else rd_eof_reg;
tx_axis_mac_tlast_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tlast_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tlast based on current and next read state.
rd_last_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tlast <= rd_eof after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tlast <= '1' after dly;
else
case rd_state is
when DATA_PRELOAD1_s =>
tx_axis_mac_tlast <= rd_eof after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when FINISH_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_retransmiterr after dly;
when others =>
tx_axis_mac_tlast <= '0' after dly;
end case;
end if;
end if;
end process rd_last_decode_p;
-- Combinatorially select tuser candidates.
tx_axis_mac_tuser_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tuser_int_retransmit <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tuser based on current and next read state.
rd_user_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tuser <= '1' after dly;
else
case rd_state is
when DROP_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_retransmit after dly;
when others =>
tx_axis_mac_tuser <= '0' after dly;
end case;
end if;
end if;
end process rd_user_decode_p;
------------------------------------------------------------------------------
-- Decode full duplex-only control signals.
gen_fd_decode : if (FULL_DUPLEX_ONLY = TRUE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'1' when rd_nxt_state = FRAME_s else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when rd_nxt_state = HANDSHAKE_s else
'0' when rd_state = FINISH_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = FINISH_s and rd_nxt_state =IDLE_s
else '0';
-- Unused for full duplex only.
rd_start_addr_reload <= '0';
rd_start_addr_load <= '0';
rd_retransmit_frame <= '0';
end generate gen_fd_decode;
------------------------------------------------------------------------------
-- Decode full and half duplex control signals.
gen_hd_decode : if (FULL_DUPLEX_ONLY = FALSE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'0' when rd_nxt_state = DROP_ERR_s else
'0' when (rd_nxt_state = DROP_s and rd_eof = '1') else
'1' when rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s else
'0' when (rd_state = DATA_PRELOAD2_s and rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when (rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when rd_state = FINISH_s else
'0' when rd_state = RETRANSMIT_ERR_s else
'0' when rd_state = RETRANSMIT_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else
'1' when rd_state = DROP_s and rd_nxt_state = IDLE_s
else '0';
-- Assertion indicates that the starting address must be reloaded to enable
-- the current frame to be retransmitted.
rd_start_addr_reload <= '1' when rd_state = RETRANSMIT_s else '0';
rd_start_addr_load <= '1' when rd_state= WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else
'1' when rd_col_window_expire = '1' else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = FINISH_s and rd_nxt_state =IDLE_s
else '0';
-- Retransmit frame pulse must never be more frequent than once per 16 clocks
-- to allow toggle to cross clock domain.
rd_retransmit_frame <= '1' when rd_state = RETRANSMIT_s else '0';
end generate gen_hd_decode; -- half duplex control signals
------------------------------------------------------------------------------
-- Frame count
-- We need to maintain a count of frames in the FIFO, so that we know when a
-- frame is available for transmission. The counter must be held on the write
-- clock domain as this is the faster clock if they differ.
------------------------------------------------------------------------------
-- A frame has been written to the FIFO.
wr_store_frame <= '1' when wr_state = EOF_s and wr_nxt_state /= EOF_s
else '0';
-- Generate a toggle to indicate when a frame has been transmitted by the FIFO.
p_rd_trans_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_transmit_frame = '1' then
rd_tran_frame_tog <= not rd_tran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read transmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_tran_frame_tog,
data_out => wr_tran_frame_sync
);
-- Edge-detect of the resynchronized transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_tran_frame_delay <= wr_tran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_transmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_tran_frame_delay xor wr_tran_frame_sync) = '1' then
wr_transmit_frame <= '1' after dly;
else
wr_transmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
------------------------------------------------------------------------------
-- Full duplex-only frame count.
gen_fd_count : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock if they differ.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (not wr_store_frame and wr_transmit_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_fd_count;
------------------------------------------------------------------------------
-- Full and half duplex frame count.
gen_hd_count : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Generate a toggle to indicate when a frame has been retransmitted from
-- the FIFO.
p_rd_retran_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_retransmit_frame = '1' then
rd_retran_frame_tog <= not rd_retran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read retransmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_retran_frame_tog,
data_out => wr_retran_frame_sync
);
-- Edge detect of the resynchronized read transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_retran_frame_delay <= wr_retran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_retransmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_retran_frame_delay xor wr_retran_frame_sync) = '1' then
wr_retransmit_frame <= '1' after dly;
else
wr_retransmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored or retransmitted and decremented when a frame is
-- transmitted. Need to keep the counter on the write clock as this is the
-- fastest clock if they differ. Logic assumes transmit and retransmit cannot
-- happen at same time.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and wr_retransmit_frame) = '1' then
wr_frames <= wr_frames + 2 after dly;
elsif ((wr_store_frame or wr_retransmit_frame)
and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (wr_transmit_frame and not wr_store_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_hd_count;
-- send wr_transmit_frame back to read domain to ensure it waits until the frame_in_fifo logic has been updated
p_delay_wr_transmit : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_transmit_frame_delay <= '0' after dly;
else
wr_transmit_frame_delay <= wr_transmit_frame after dly;
end if;
end if;
end process p_delay_wr_transmit;
p_wr_tx : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if wr_transmit_frame_delay = '1' then
frame_in_fifo_valid_tog <= not frame_in_fifo_valid_tog after dly;
end if;
end if;
end process p_wr_tx;
-- Generate a frame in FIFO signal for use in control logic.
p_wr_avail : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frame_in_fifo <= '0' after dly;
else
if wr_frames /= (wr_frames'range => '0') then
wr_frame_in_fifo <= '1' after dly;
else
wr_frame_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_wr_avail;
-- Generate a multiple frames in FIFO signal for use in control logic.
p_mult_wr_avail : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames_in_fifo <= '0' after dly;
else
if wr_frames >= "000000010" then
wr_frames_in_fifo <= '1' after dly;
else
wr_frames_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_mult_wr_avail;
-- Synchronize it back onto read domain for use in the read logic.
resync_wr_frame_in_fifo : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_mac_aclk,
data_in => wr_frame_in_fifo,
data_out => frame_in_fifo
);
-- Synchronize it back onto read domain for use in the read logic.
resync_wr_frames_in_fifo : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_mac_aclk,
data_in => wr_frames_in_fifo,
data_out => frames_in_fifo
);
-- in he case where only one frame is in the fifo we have to be careful about the faling edge of
-- the frame in fifo signal as for short frames this could occur after the state machine completes
resync_fif_valid_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_mac_aclk,
data_in => frame_in_fifo_valid_tog,
data_out => frame_in_fifo_valid_sync
);
-- Edge detect of the re-resynchronized read transmit frame signal.
p_delay_fif_valid : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
frame_in_fifo_valid_delay <= frame_in_fifo_valid_sync after dly;
end if;
end process p_delay_fif_valid;
p_sync_fif_valid : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
frame_in_fifo_valid <= '1' after dly;
else
-- Edge detector
if (frame_in_fifo_valid_delay xor frame_in_fifo_valid_sync) = '1' then
frame_in_fifo_valid <= '1' after dly;
elsif rd_transmit_frame = '1' then
frame_in_fifo_valid <= '0' after dly;
end if;
end if;
end if;
end process p_sync_fif_valid;
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when write enable signal has been asserted
wr_addr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_addr <= (others => '0') after dly;
elsif wr_addr_reload = '1' then
wr_addr <= wr_start_addr after dly;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_addr_p;
-- Store the start address in case the address must be reset.
wr_staddr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_start_addr <= (others => '0') after dly;
elsif wr_start_addr_load = '1' then
wr_start_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_staddr_p;
------------------------------------------------------------------------------
-- Half duplex-only read address counters.
gen_fd_addr : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
-- Do not need to keep a start address, but the address is needed to
-- calculate FIFO occupancy.
rd_start_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
rd_start_addr <= rd_addr after dly;
end if;
end if;
end process rd_start_p;
end generate gen_fd_addr;
------------------------------------------------------------------------------
-- Full and half duplex read address counters
gen_hd_addr : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_start_addr_reload = '1' then
rd_addr <= rd_start_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
rd_staddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
if rd_start_addr_load = '1' then
rd_start_addr <= rd_addr - 6 after dly;
end if;
end if;
end if;
end process rd_staddr_p;
-- Collision window expires after MAC has been transmitting for required slot
-- time. This is 512 clock cycles at 1Gbps. Also if the end of frame has fully
-- been transmitted by the MAC then a collision cannot occur. This collision
-- expiration signal goes high at 768 cycles from the start of the frame.
-- This is inefficient for short frames, however it should be enough to
-- prevent the FIFO from locking up.
rd_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_col_window_expire <= '0' after dly;
else
if rd_transmit_frame = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_slot_timer(9 downto 7) = "110" then
rd_col_window_expire <= '1' after dly;
end if;
end if;
end if;
end process;
rd_idle_state <= '1' when rd_state = IDLE_s else '0';
rd_colreg_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_col_window_pipe(0) <= rd_col_window_expire
and rd_idle_state after dly;
if rd_txfer_en = '1' then
rd_col_window_pipe(1) <= rd_col_window_pipe(0) after dly;
end if;
end if;
end process;
rd_slot_time_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
-- Will not count until after the first frame is sent.
if tx_mac_reset = '1' then
rd_slot_timer <= "1111111111" after dly;
else
-- Reset counter.
if rd_transmit_frame = '1' then
rd_slot_timer <= (others => '0') after dly;
-- Do not allow counter to roll over, and
-- only count when frame is being transmitted.
elsif rd_slot_timer /= "1111111111" then
rd_slot_timer <= rd_slot_timer + 1 after dly;
end if;
end if;
end if;
end process;
end generate gen_hd_addr;
-- Read address generation
rd_decaddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_dec_addr <= (others => '0') after dly;
else
if rd_addr_inc = '1' then
rd_dec_addr <= rd_addr - 1 after dly;
end if;
end if;
end if;
end process rd_decaddr_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_data_pipe(0) <= tx_axis_fifo_tdata after dly;
if wr_accept_pipe(0) = '1' then
wr_data_pipe(1) <= wr_data_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_data_bram <= wr_data_pipe(1) after dly;
end if;
end if;
end process reg_din_p;
-- Start of frame set when tvalid is asserted and previous frame has ended.
wr_sof_int <= tx_axis_fifo_tvalid and wr_eof_reg;
-- Set end of frame flag when tlast and tvalid are asserted together.
-- Reset to logic 1 to enable first frame's start of frame flag.
reg_eofreg_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_eof_reg <= '1';
else
if tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tready_int_n = '0' then
wr_eof_reg <= tx_axis_fifo_tlast;
end if;
end if;
end if;
end process reg_eofreg_p;
-- Pipeline the start of frame flag when the pipe is enabled.
reg_sof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_sof_pipe(0) <= wr_sof_int and not tx_axis_fifo_tlast after dly;
if wr_accept_pipe(0) = '1' then
wr_sof_pipe(1) <= wr_sof_pipe(0) after dly;
end if;
end if;
end process reg_sof_p;
-- Pipeline the pipeline enable signal, which is derived from simultaneous
-- assertion of tvalid and tready.
reg_acc_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if (tx_fifo_reset = '1') then
wr_accept_pipe(0) <= '0' after dly;
wr_accept_pipe(1) <= '0' after dly;
wr_accept_bram <= '0' after dly;
else
wr_accept_pipe(0) <= tx_axis_fifo_tvalid and (not tx_axis_fifo_tready_int_n) and
not (tx_axis_fifo_tlast and wr_sof_int) after dly;
wr_accept_pipe(1) <= wr_accept_pipe(0) after dly;
wr_accept_bram <= wr_accept_pipe(1) after dly;
end if;
end if;
end process reg_acc_p;
-- Pipeline the end of frame flag when the pipe is enabled.
reg_eof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_eof_pipe(0) <= tx_axis_fifo_tvalid and tx_axis_fifo_tlast and not wr_sof_int after dly;
if wr_accept_pipe(0) = '1' then
wr_eof_pipe(1) <= wr_eof_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_eof_bram(0) <= wr_eof_pipe(1) after dly;
end if;
end if;
end process reg_eof_p;
-- Register data outputs from BRAM.
-- No resets to allow SRL16 target.
reg_dout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
rd_data_delay <= rd_data_bram after dly;
rd_data_pipe <= rd_data_delay after dly;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
rd_eof_pipe <= rd_eof_bram(0) after dly;
rd_eof <= rd_eof_pipe after dly;
rd_eof_reg <= rd_eof or rd_eof_pipe after dly;
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Half duplex-only drop and retransmission controls.
gen_hd_input : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Register the collision without retransmit signal, which is a pulse that
-- causes the FIFO to drop the frame.
reg_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_drop_frame <= tx_collision and (not tx_retransmit) after dly;
end if;
end process reg_col_p;
-- Register the collision with retransmit signal, which is a pulse that
-- causes the FIFO to retransmit the frame.
reg_retr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_retransmit <= tx_collision and tx_retransmit after dly;
end if;
end process reg_retr_p;
end generate gen_hd_input;
------------------------------------------------------------------------------
-- FIFO full functionality
------------------------------------------------------------------------------
-- Full functionality is the difference between read and write addresses.
-- We cannot use gray code this time as the read address and read start
-- addresses jump by more than 1.
-- We generate an enable pulse for the read side every 16 read clocks. This
-- provides for the worst-case situation where the write clock is 20MHz and
-- read clock is 125MHz.
p_rd_16_pulse : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_16_count <= (others => '0') after dly;
else
rd_16_count <= rd_16_count + 1 after dly;
end if;
end if;
end process;
rd_txfer_en <= '1' when rd_16_count = "1111" else '0';
-- Register the start address on the enable pulse.
p_rd_addr_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_addr_txfer <= (others => '0') after dly;
else
if rd_txfer_en = '1' then
rd_addr_txfer <= rd_start_addr after dly;
end if;
end if;
end if;
end process;
-- Generate a toggle to indicate that the address has been loaded.
p_rd_tog_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_txfer_en = '1' then
rd_txfer_tog <= not rd_txfer_tog after dly;
end if;
end if;
end process;
-- Synchronize the toggle to the write side.
resync_rd_txfer_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_txfer_tog,
data_out => wr_txfer_tog_sync
);
-- Delay the synchronized toggle by one cycle.
p_wr_tog_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_txfer_tog_delay <= wr_txfer_tog_sync after dly;
end if;
end process;
-- Generate an enable pulse from the toggle. The address should have been
-- steady on the wr clock input for at least one clock.
wr_txfer_en <= wr_txfer_tog_delay xor wr_txfer_tog_sync;
-- Capture the address on the write clock when the enable pulse is high.
p_wr_addr_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_rd_addr <= (others => '0') after dly;
elsif wr_txfer_en = '1' then
wr_rd_addr <= rd_addr_txfer after dly;
end if;
end if;
end process;
-- Obtain the difference between write and read pointers
p_wr_addr_diff : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_addr_diff <= (others => '0') after dly;
else
wr_addr_diff <= wr_rd_addr - wr_addr after dly;
end if;
end if;
end process;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_full <= '0' after dly;
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1' after dly;
else
wr_fifo_full <= '0' after dly;
end if;
end if;
end if;
end process p_wr_full;
-- Memory overflow occurs when the FIFO is full and there are no frames
-- available in the FIFO for transmission. If the collision window has
-- expired and there are no frames in the FIFO and the FIFO is full, then the
-- FIFO is in an overflow state. We must accept the rest of the incoming
-- frame in overflow condition.
gen_fd_ovflow : if (FULL_DUPLEX_ONLY = TRUE) generate
-- In full duplex mode, the FIFO memory can only overflow if the FIFO goes
-- full but there is no frame available to be retranmsitted. Therefore,
-- prevent signal from being asserted when store_frame signal is high, as
-- frame count is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
else '0';
-- Tie off unused half-duplex signals
wr_col_window_pipe(0) <= '0' after dly;
wr_col_window_pipe(1) <= '0' after dly;
end generate gen_fd_ovflow;
gen_hd_ovflow : if (FULL_DUPLEX_ONLY = FALSE) generate
-- In half duplex mode, register write collision window to give address
-- counter sufficient time to update. This will prevent the signal from
-- being asserted when the store_frame signal is high, as the frame count
-- is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
and wr_col_window_expire = '1'
else '0';
-- Register rd_col_window signal.
-- This signal is long, and will remain high until overflow functionality
-- has finished, so save just to register the once.
p_wr_col_expire : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_col_window_pipe(0) <= '0' after dly;
wr_col_window_pipe(1) <= '0' after dly;
wr_col_window_expire <= '0' after dly;
else
if wr_txfer_en = '1' then
wr_col_window_pipe(0) <= rd_col_window_pipe(1) after dly;
end if;
wr_col_window_pipe(1) <= wr_col_window_pipe(0) after dly;
wr_col_window_expire <= wr_col_window_pipe(1) after dly;
end if;
end if;
end process;
end generate gen_hd_ovflow;
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_fifo_status : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_status <= "0000" after dly;
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000" after dly;
else
wr_fifo_status(3) <= not wr_addr_diff(11) after dly;
wr_fifo_status(2) <= not wr_addr_diff(10) after dly;
wr_fifo_status(1) <= not wr_addr_diff(9) after dly;
wr_fifo_status(0) <= not wr_addr_diff(8) after dly;
end if;
end if;
end if;
end process p_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram(0);
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
rd_eof_bram(0) <= rd_eof_data_bram(8);
rd_data_bram <= rd_eof_data_bram(7 downto 0);
tx_ramgen_i : tri_mode_ethernet_mac_0_bram_tdp
generic map (
DATA_WIDTH => 9,
ADDR_WIDTH => 12
)
port map (
b_dout => rd_eof_data_bram,
a_addr => std_logic_vector(wr_addr(11 downto 0)),
b_addr => std_logic_vector(rd_addr(11 downto 0)),
a_clk => tx_fifo_aclk,
b_clk => tx_mac_aclk,
a_din => wr_eof_data_bram,
b_en => rd_en,
a_rst => tx_fifo_reset,
b_rst => tx_mac_reset,
a_wr => wr_en
);
end RTL;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/i2c/i2c_master.vhd | 1 | 11099 | --------------------------------------------------------------------------------
--! @file i2c_master
--! @brief As master, read/write up to 2/3 bytes on th i2c bus.
--! @author Dong Wang, 20161009
--! Yuan Mei, 20170817
--! Read/write is initiated by a pulse on START
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY i2c_master IS
GENERIC (
INPUT_CLK_FREQENCY : integer := 100_000_000;
-- BUS CLK freqency should be divided by multiples of 4 from input frequency
BUS_CLK_FREQUENCY : integer := 100_000
);
PORT (
CLK : IN std_logic; -- system clock 50Mhz
RESET : IN std_logic; -- active high reset
START : IN std_logic; -- rising edge triggers r/w; synchronous to CLK
MODE : IN std_logic_vector(1 DOWNTO 0); -- "00" : 1 bytes read or write, "01" : 2 bytes r/w, "10" : 3 bytes write only;
SL_RW : IN std_logic; -- '0' is write, '1' is read
SL_ADDR : IN std_logic_vector(6 DOWNTO 0); -- slave addr
REG_ADDR : IN std_logic_vector(7 DOWNTO 0); -- slave internal reg addr for read and write
WR_DATA0 : IN std_logic_vector(7 DOWNTO 0); -- first data byte to write
WR_DATA1 : IN std_logic_vector(7 DOWNTO 0); -- second data byte to write
RD_DATA0 : OUT std_logic_vector(7 DOWNTO 0); -- first data byte read
RD_DATA1 : OUT std_logic_vector(7 DOWNTO 0); -- second data byte read
BUSY : OUT std_logic; -- indicates transaction in progress
ACK_ERROR : OUT std_logic; -- i2c has unexpected ack
SDA_in : IN std_logic; -- serial data input from i2c bus
SDA_out : OUT std_logic; -- serial data output to i2c bus
SDA_t : OUT std_logic; -- serial data direction to/from i2c bus, '1' is read-in
SCL : OUT std_logic -- serial clock output to i2c bus
);
END i2c_master;
ARCHITECTURE arch OF i2c_master IS
COMPONENT i2c_master_core IS
GENERIC (
INPUT_CLK_FREQENCY : integer;
BUS_CLK_FREQUENCY : integer
);
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
ENA : IN std_logic;
ADDR : IN std_logic_vector(6 DOWNTO 0);
RW : IN std_logic;
DATA_WR : IN std_logic_vector(7 DOWNTO 0);
BUSY : OUT std_logic;
DATA_RD : OUT std_logic_vector(7 DOWNTO 0);
ACK_ERROR : OUT std_logic;
SDA_in : IN std_logic;
SDA_out : OUT std_logic;
SDA_t : OUT std_logic;
SCL : OUT std_logic
);
END COMPONENT i2c_master_core;
SIGNAL sI2C_enable : std_logic;
SIGNAL sI2C_data_wr : std_logic_vector(7 DOWNTO 0);
SIGNAL sI2C_data_rd : std_logic_vector(7 DOWNTO 0);
SIGNAL sI2C_busy : std_logic;
SIGNAL sBusyCnt : std_logic_vector(2 DOWNTO 0);
SIGNAL sBusy_d1 : std_logic;
SIGNAL sBusy_d2 : std_logic;
SIGNAL rd_data0_buf : std_logic_vector(7 DOWNTO 0);
SIGNAL rd_data1_buf : std_logic_vector(7 DOWNTO 0);
TYPE machine_type IS (StWaitStart,
StWr1,
StWr2,
StWr3,
StRd1,
StRd2
); -- needed states
SIGNAL state : machine_type; -- state machine
BEGIN
i2c_master_core_inst : i2c_master_core
GENERIC MAP (
INPUT_CLK_FREQENCY => INPUT_CLK_FREQENCY,
BUS_CLK_FREQUENCY => BUS_CLK_FREQUENCY
)
PORT MAP (
CLK => CLK,
RESET => RESET,
ENA => sI2C_enable,
ADDR => SL_ADDR,
RW => SL_RW,
DATA_WR => sI2C_data_wr,
BUSY => sI2C_busy,
DATA_RD => sI2C_data_rd,
ACK_ERROR => ACK_ERROR,
SDA_in => SDA_in,
SDA_out => SDA_out,
SDA_t => SDA_t,
SCL => SCL
);
--busy counter
busy_d : PROCESS (CLK) IS
BEGIN
IF rising_edge(CLK) THEN
sBusy_d1 <= sI2C_busy;
sBusy_d2 <= sBusy_d1;
END IF;
END PROCESS busy_d;
busy_counter : PROCESS (CLK, RESET) IS
BEGIN
IF RESET = '1' THEN -- asynchronous reset (active high)
sBusyCnt <= "000";
ELSIF rising_edge(CLK) THEN
IF state = StWaitStart THEN
sBusyCnt <= "000";
ELSIF sBusy_d2 = '0' and sBusy_d1 = '1' THEN
sBusyCnt <= std_logic_vector(unsigned(sBusyCnt) + 1);
ELSE
sBusyCnt <= sBusyCnt;
END IF;
END IF;
END PROCESS busy_counter;
state_machine : PROCESS (CLK, RESET) IS
BEGIN
IF RESET = '1' THEN -- asynchronous reset (active high)
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
BUSY <= '0';
rd_data0_buf <= (OTHERS => '0');
rd_data1_buf <= (OTHERS => '0');
state <= StWaitStart;
ELSIF rising_edge(CLK) THEN -- rising clock edge
CASE state IS
-- //// Wait for signal to start I2C transaction
WHEN StWaitStart =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
BUSY <= '0';
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
IF START = '1' THEN
BUSY <= '1';
IF SL_RW = '0' THEN -- write
IF MODE = "00" THEN -- 1 byte write (no payload)
state <= StWr1;
ELSIF MODE = "01" THEN -- 2 bytes write (1 byte payload)
state <= StWr2;
ELSIF MODE = "10" THEN -- 3 bytes write (2 byte payload)
state <= StWr3;
ELSE
state <= StWaitStart;
END IF;
ELSE
IF MODE = "00" THEN -- 1 byte read
state <= StRd1;
ELSIF MODE = "01" THEN -- 2 bytes read
state <= StRd2;
ELSE
state <= StWaitStart;
END IF;
END IF;
ELSE
state <= StWaitStart;
END IF;
-- 1 byte write
WHEN StWr1 =>
BUSY <= '1';
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
sI2C_data_wr <= REG_ADDR;
state <= StWr1;
WHEN "001" =>
sI2C_enable <= '0';
sI2C_data_wr <= REG_ADDR;
IF sI2C_busy = '0' THEN
state <= StWaitStart;
ELSE
state <= StWr1;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
state <= StWaitStart;
END CASE;
-- 2 bytes write
WHEN StWr2 =>
BUSY <= '1';
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
sI2C_data_wr <= REG_ADDR;
state <= StWr2;
WHEN "001" =>
sI2C_enable <= '1';
sI2C_data_wr <= WR_DATA0;
state <= StWr2;
WHEN "010" =>
sI2C_enable <= '0';
sI2C_data_wr <= WR_DATA0;
IF sI2C_busy = '0' THEN
state <= StWaitStart;
ELSE
state <= StWr2;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
state <= StWaitStart;
END CASE;
-- 3 bytes write
WHEN StWr3 =>
BUSY <= '1';
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
sI2C_data_wr <= REG_ADDR;
state <= StWr3;
WHEN "001" =>
sI2C_enable <= '1';
sI2C_data_wr <= WR_DATA0;
state <= StWr3;
WHEN "010" =>
sI2C_enable <= '1';
sI2C_data_wr <= WR_DATA1;
state <= StWr3;
WHEN "011" =>
sI2C_enable <= '0';
sI2C_data_wr <= WR_DATA1;
IF sI2C_busy = '0' THEN
state <= StWaitStart;
ELSE
state <= StWr3;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
state <= StWaitStart;
END CASE;
-- 1 byte read
WHEN StRd1 =>
BUSY <= '1';
rd_data1_buf <= rd_data1_buf;
sI2C_data_wr <= (OTHERS => '0');
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
rd_data0_buf <= rd_data0_buf;
state <= StRd1;
WHEN "001" =>
sI2C_enable <= '0';
IF sI2C_busy = '0' THEN
state <= StWaitStart;
rd_data0_buf <= sI2C_data_rd;
ELSE
state <= StRd1;
rd_data0_buf <= rd_data0_buf;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
rd_data0_buf <= rd_data0_buf;
state <= StWaitStart;
END CASE;
-- 2 bytes read
WHEN StRd2 =>
BUSY <= '1';
sI2C_data_wr <= (OTHERS => '0');
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
state <= StRd2;
WHEN "001" =>
sI2C_enable <= '1';
IF sI2C_busy = '0' THEN
state <= StRd2;
rd_data0_buf <= sI2C_data_rd;
rd_data1_buf <= rd_data1_buf;
ELSE
state <= StRd2;
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
END IF;
WHEN "010" =>
sI2C_enable <= '0';
IF sI2C_busy = '0' THEN
state <= StWaitStart;
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= sI2C_data_rd;
ELSE
state <= StRd2;
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
state <= StWaitStart;
END CASE;
-- //// shouldn't happen
WHEN OTHERS =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
BUSY <= '0';
rd_data0_buf <= (OTHERS => '0');
rd_data1_buf <= (OTHERS => '0');
state <= StWaitStart;
END CASE;
END IF;
END PROCESS state_machine;
RD_DATA0 <= rd_data0_buf;
RD_DATA1 <= rd_data1_buf;
END arch;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/utility_pkg.vhd | 1 | 6389 | --------------------------------------------------------------------------------
--! @file utility.vhd
--! @brief Package of utility modules and functions.
--! @author Yuan Mei
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;
PACKAGE utility IS
COMPONENT uartio
GENERIC (
-- tick repetition frequency is (input freq) / (2**COUNTER_WIDTH / DIVISOR)
COUNTER_WIDTH : positive;
DIVISOR : positive
);
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
RX_DATA : OUT std_logic_vector(7 DOWNTO 0);
RX_RDY : OUT std_logic;
TX_DATA : IN std_logic_vector(7 DOWNTO 0);
TX_EN : IN std_logic;
TX_RDY : OUT std_logic;
-- serial lines
RX_PIN : IN std_logic;
TX_PIN : OUT std_logic
);
END COMPONENT;
COMPONENT byte2cmd
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
-- byte in
RX_DATA : IN std_logic_vector(7 DOWNTO 0);
RX_RDY : IN std_logic;
-- cmd out
CMD_FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); --! command fifo data out port
CMD_FIFO_EMPTY : OUT std_logic; --! command fifo "emtpy" SIGNAL
CMD_FIFO_RDCLK : IN std_logic;
CMD_FIFO_RDREQ : IN std_logic --! command fifo read request
);
END COMPONENT;
COMPONENT channel_sel
GENERIC (
CHANNEL_WIDTH : positive := 16;
INDATA_WIDTH : positive := 256;
OUTDATA_WIDTH : positive := 256
);
PORT (
CLK : IN std_logic; --! fifo wrclk
RESET : IN std_logic;
SEL : IN std_logic_vector(7 DOWNTO 0);
--
DATA_FIFO_RESET : IN std_logic;
--
INDATA_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
DATA_FIFO_WREN : IN std_logic;
DATA_FIFO_FULL : OUT std_logic;
--
OUTDATA_FIFO_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0);
DATA_FIFO_RDEN : IN std_logic;
DATA_FIFO_EMPTY : OUT std_logic
);
END COMPONENT;
COMPONENT channel_avg
GENERIC (
NCH : positive := 16;
OUTCH_WIDTH : positive := 16;
INTERNAL_WIDTH : positive := 32;
INDATA_WIDTH : positive := 256;
OUTDATA_WIDTH : positive := 256
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
-- high 4-bit is offset, 2**(low 4-bit) is number of points to average
CONFIG : IN std_logic_vector(7 DOWNTO 0);
TRIG : IN std_logic;
INDATA_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
OUTVALID : OUT std_logic;
OUTDATA_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT pulse2pulse
PORT (
IN_CLK : IN std_logic;
OUT_CLK : IN std_logic;
RST : IN std_logic;
PULSEIN : IN std_logic;
INBUSY : OUT std_logic;
PULSEOUT : OUT std_logic
);
END COMPONENT;
COMPONENT edge_sync IS
GENERIC (
EDGE : std_logic := '1' --! '1' : rising edge, '0' falling edge
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
EI : IN std_logic;
SO : OUT std_logic
);
END COMPONENT;
COMPONENT width_pulse_sync IS
GENERIC (
DATA_WIDTH : positive := 8;
MODE : natural := 0 -- 0: output one pulse of duration PW
-- 1: a train of 1-clk wide pulses (of number PW)
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
PW : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
START : IN std_logic; -- should be synchronous to CLK, of any width
BUSY : OUT std_logic;
CLKO : IN std_logic;
RSTO : OUT std_logic;
PO : OUT std_logic
);
END COMPONENT;
COMPONENT clk_div IS
GENERIC (
WIDTH : positive := 16;
PBITS : positive := 4 --! log2(WIDTH)
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
DIV : IN std_logic_vector(PBITS-1 DOWNTO 0);
CLK_DIV : OUT std_logic
);
END COMPONENT;
COMPONENT clk_fwd
GENERIC (
INV : boolean := false;
SLEW : string := "SLOW"
);
PORT (
R : IN std_logic;
I : IN std_logic;
O : OUT std_logic;
O_P : OUT std_logic;
O_N : OUT std_logic
);
END COMPONENT;
IMPURE FUNCTION version_from_file(filename : IN string) RETURN std_logic_vector;
FUNCTION reverse_vector(a : IN std_logic_vector) RETURN std_logic_vector;
END PACKAGE utility;
PACKAGE BODY utility IS
IMPURE FUNCTION version_from_file(filename : IN string) RETURN std_logic_vector IS
-- FILE foo : text IS IN filename;
FILE foo : text OPEN read_mode IS filename;
VARIABLE xline : line;
VARIABLE inStr : string(1 TO 100);
VARIABLE i : integer RANGE 1 TO 100;
VARIABLE x : integer := 0;
VARIABLE done : boolean := false;
VARIABLE good : boolean;
VARIABLE smudge : std_logic_vector(1 DOWNTO 0) := "00";
BEGIN
readline(foo, xline);
-- FOR i IN 1 TO xline'length LOOP
FOR i IN inStr'range LOOP
read(xline, inStr(i), good);
IF NOT good THEN
EXIT;
ELSIF inStr(i) = ':' THEN -- mark if a range of revisions
x := 0; -- and report the later one
smudge(0) := '1';
ELSIF inStr(i) = 'M' THEN -- mark if anything is modified from repository
done := true; -- if we see this, it's also the end of the number!
smudge(1) := '1';
ELSIF NOT done THEN
x := 10*x + character'pos(inStr(i))-character'pos('0');
END IF;
END LOOP;
ASSERT false REPORT "version="&inStr SEVERITY note;
RETURN smudge & std_logic_vector(to_unsigned(x, 14));
END FUNCTION;
FUNCTION reverse_vector(a : IN std_logic_vector)
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(a'range);
ALIAS aa : std_logic_vector(a'reverse_range) IS a;
BEGIN
FOR i IN aa'range LOOP
result(i) := aa(i);
END LOOP;
RETURN result;
END; -- function reverse_vector
END PACKAGE BODY utility;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/global_clock_reset.vhd | 1 | 3334 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Yuan Mei
--
-- Create Date: 12/13/2013 07:56:40 PM
-- Design Name:
-- Module Name: global_clock_reset - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- This module encapsulates the main clock generation and its proepr resetting.
-- It also provides a global reset signal output upon stable clock's pll lock.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY global_clock_reset IS
PORT (
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
FORCE_RST : IN std_logic;
-- output
GLOBAL_RST : OUT std_logic;
SYS_CLK : OUT std_logic;
LOCKED : OUT std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic;
CLK_OUT3 : OUT std_logic;
CLK_OUT4 : OUT std_logic
);
END global_clock_reset;
ARCHITECTURE Behavioral OF global_clock_reset IS
COMPONENT clockwiz
PORT (
-- Clock in ports
clk_in1 : IN std_logic;
-- Clock out ports
clk_out1 : OUT std_logic;
clk_out2 : OUT std_logic;
clk_out3 : OUT std_logic;
clk_out4 : OUT std_logic;
-- Status and control signals
reset : IN std_logic;
locked : OUT std_logic
);
END COMPONENT;
COMPONENT GlobalResetter
PORT (
FORCE_RST : IN std_logic;
CLK : IN std_logic; -- system clock
DCM_LOCKED : IN std_logic;
CLK_RST : OUT std_logic;
GLOBAL_RST : OUT std_logic
);
END COMPONENT;
-- Signals
SIGNAL sys_clk_i : std_logic;
SIGNAL dcm_locked : std_logic;
SIGNAL dcm_reset : std_logic;
BEGIN
IBUFDS_inst : IBUFDS
GENERIC MAP (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
PORT MAP (
O => sys_clk_i, -- Buffer output
I => SYS_CLK_P, -- Diff_p buffer input (connect directly to top-level port)
IB => SYS_CLK_N -- Diff_n buffer input (connect directly to top-level port)
);
BUFG_inst : BUFG
PORT MAP (
I => sys_clk_i,
O => sys_clk
);
--sys_clk <= sys_clk_i;
clockwiz_inst : clockwiz
PORT MAP (
-- Clock in ports
clk_in1 => sys_clk_i,
-- Clock out ports
clk_out1 => CLK_OUT1,
clk_out2 => CLK_OUT2,
clk_out3 => CLK_OUT3,
clk_out4 => CLK_OUT4,
-- Status and control signals
reset => dcm_reset,
locked => dcm_locked
);
globalresetter_inst : GlobalResetter
PORT MAP (
FORCE_RST => FORCE_RST,
CLK => sys_clk_i,
DCM_LOCKED => dcm_locked,
CLK_RST => dcm_reset,
GLOBAL_RST => GLOBAL_RST
);
LOCKED <= dcm_locked;
END Behavioral;
| bsd-3-clause |
ymei/TMSPlane | Firmware/test_bench/channel_avg_tb.vhd | 1 | 2988 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/29/2014 07:39:31 PM
-- Design Name:
-- Module Name: channel_avg_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY channel_avg_tb IS
END channel_avg_tb;
ARCHITECTURE Behavioral OF channel_avg_tb IS
COMPONENT channel_avg IS
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
CONFIG : IN std_logic_vector(7 DOWNTO 0);
TRIG : IN std_logic;
INDATA_Q : IN std_logic_vector(256-1 DOWNTO 0);
OUTVALID : OUT std_logic;
OUTDATA_Q : OUT std_logic_vector(256-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL RESET : std_logic := '0';
SIGNAL CLK : std_logic := '0';
--
SIGNAL CONFIG : std_logic_vector(7 DOWNTO 0) := x"94";
SIGNAL TRIG : std_logic := '0';
SIGNAL INDATA_Q : std_logic_vector(256-1 DOWNTO 0);
SIGNAL OUTVALID : std_logic;
SIGNAL OUTDATA_Q : std_logic_vector(256-1 DOWNTO 0);
--
SIGNAL ch_val : signed(13 DOWNTO 0) := (OTHERS => '0');
-- Clock period definitions
CONSTANT CLK_period : time := 10 ns;
CONSTANT CLKOUT_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : channel_avg
PORT MAP (
RESET => RESET,
CLK => CLK,
CONFIG => CONFIG,
TRIG => TRIG,
INDATA_Q => INDATA_Q,
OUTVALID => OUTVALID,
OUTDATA_Q => OUTDATA_Q
);
-- Clock process definitions
CLK_process : PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_period/2;
CLK <= '1';
WAIT FOR CLK_period/2;
END PROCESS;
PROCESS (CLK, RESET) IS
VARIABLE i : integer;
BEGIN
IF RESET = '1' THEN
ch_val <= to_signed(-128, ch_val'length);
ELSIF rising_edge(CLK) THEN
ch_val <= ch_val + 1;
END IF;
FOR i IN 0 TO 15 LOOP
INDATA_Q(i*16+15 DOWNTO i*16+2) <= std_logic_vector(ch_val);
INDATA_Q(i*16+1 DOWNTO i*16) <= "00";
END LOOP;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- hold reset state
RESET <= '0';
WAIT FOR 15 ns;
RESET <= '1';
WAIT FOR CLK_period*3;
RESET <= '0';
WAIT FOR CLK_period*5.3;
TRIG <= '1';
WAIT FOR CLK_period*5.7;
TRIG <= '0';
--
--
WAIT;
END PROCESS;
END Behavioral;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/ten_gig_eth/TE07412C1/pcs_pma/ten_gig_eth_pcs_pma_wrapper.vhd | 3 | 10440 | -------------------------------------------------------------------------------
-- Title : Example Design level wrapper
-- Project : 10GBASE-R
-------------------------------------------------------------------------------
-- File : ten_gig_eth_pcs_pma_0_example_design.vhd
-------------------------------------------------------------------------------
-- Description: This file is a wrapper for the 10GBASE-R core; it contains the
-- core support level and a few registers, including a DDR output register
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
entity ten_gig_eth_pcs_pma_wrapper is
port (
refclk_p : in std_logic;
refclk_n : in std_logic;
-- ymei dclk : in std_logic;
coreclk_out : out std_logic;
reset : in std_logic;
qpll_locked : out std_logic; -- ymei
sim_speedup_control: in std_logic := '0';
xgmii_txd : in std_logic_vector(63 downto 0);
xgmii_txc : in std_logic_vector(7 downto 0);
xgmii_rxd : out std_logic_vector(63 downto 0) := x"0000000000000000";
xgmii_rxc : out std_logic_vector(7 downto 0) := x"00";
xgmii_rx_clk : out std_logic;
txp : out std_logic;
txn : out std_logic;
rxp : in std_logic;
rxn : in std_logic;
mdc : in std_logic;
mdio_in : in std_logic;
mdio_out : out std_logic := '0';
mdio_tri : out std_logic := '0';
prtad : in std_logic_vector(4 downto 0);
core_status : out std_logic_vector(7 downto 0);
resetdone : out std_logic;
signal_detect : in std_logic;
tx_fault : in std_logic;
tx_disable : out std_logic);
end ten_gig_eth_pcs_pma_wrapper;
library ieee;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
architecture wrapper of ten_gig_eth_pcs_pma_wrapper is
----------------------------------------------------------------------------
-- Component Declaration for the 10GBASE-R block level.
----------------------------------------------------------------------------
component ten_gig_eth_pcs_pma_0_support is
port (
refclk_p : in std_logic;
refclk_n : in std_logic;
dclk_out : out std_logic; -- ymei
coreclk_out : out std_logic;
reset : in std_logic;
sim_speedup_control : in std_logic := '0';
qplloutclk_out : out std_logic;
qplloutrefclk_out : out std_logic;
qplllock_out : out std_logic;
rxrecclk_out : out std_logic;
txusrclk_out : out std_logic;
txusrclk2_out : out std_logic;
gttxreset_out : out std_logic;
gtrxreset_out : out std_logic;
txuserrdy_out : out std_logic;
areset_datapathclk_out : out std_logic;
reset_counter_done_out : out std_logic;
xgmii_txd : in std_logic_vector(63 downto 0);
xgmii_txc : in std_logic_vector(7 downto 0);
xgmii_rxd : out std_logic_vector(63 downto 0);
xgmii_rxc : out std_logic_vector(7 downto 0);
txp : out std_logic;
txn : out std_logic;
rxp : in std_logic;
rxn : in std_logic;
resetdone_out : out std_logic;
signal_detect : in std_logic;
tx_fault : in std_logic;
tx_disable : out std_logic;
mdc : in std_logic;
mdio_in : in std_logic;
mdio_out : out std_logic := '0';
mdio_tri : out std_logic := '0';
prtad : in std_logic_vector(4 downto 0);
pma_pmd_type : in std_logic_vector(2 downto 0);
core_status : out std_logic_vector(7 downto 0));
end component;
----------------------------------------------------------------------------
-- Signal declarations.
----------------------------------------------------------------------------
signal coreclk : std_logic;
signal resetdone_int : std_logic;
signal qplloutclk_out : std_logic;
signal qplloutrefclk_out : std_logic;
signal qplllock_out : std_logic;
signal dclk_buf : std_logic;
signal txusrclk_out : std_logic;
signal txusrclk2_out : std_logic;
signal gttxreset_out : std_logic;
signal gtrxreset_out : std_logic;
signal txuserrdy_out : std_logic;
signal areset_datapathclk_out : std_logic;
signal reset_counter_done_out : std_logic;
signal xgmii_txd_reg : std_logic_vector(63 downto 0) := x"0000000000000000";
signal xgmii_txc_reg : std_logic_vector(7 downto 0) := x"00";
signal xgmii_rxd_int : std_logic_vector(63 downto 0);
signal xgmii_rxc_int : std_logic_vector(7 downto 0);
signal mdio_out_int : std_logic;
signal mdio_tri_int : std_logic;
signal mdc_reg : std_logic := '0';
signal mdio_in_reg : std_logic := '0';
begin
resetdone <= resetdone_int;
-- Add a pipeline to the xmgii_tx inputs, to aid timing closure
tx_reg_proc : process(coreclk)
begin
if(coreclk'event and coreclk = '1') then
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
end if;
end process;
-- Add a pipeline to the xmgii_rx outputs, to aid timing closure
rx_reg_proc : process(coreclk)
begin
if(coreclk'event and coreclk = '1') then
xgmii_rxd <= xgmii_rxd_int;
xgmii_rxc <= xgmii_rxc_int;
end if;
end process;
-- Add a pipeline to the mdio in/outputs, to aid timing closure
-- This is safe since the mdio clk is running so slowly.
mdio_outtri_reg_proc : process(coreclk)
begin
if(coreclk'event and coreclk = '1') then
mdio_tri <= mdio_tri_int;
mdio_out <= mdio_out_int;
mdc_reg <= mdc;
mdio_in_reg <= mdio_in;
end if;
end process;
-- ymei
-- dclk_bufg_i : BUFG
-- port map
-- (
-- I => dclk,
-- O => dclk_buf
-- );
-- Instance the 10GBASE-KR Core Support layer
ten_gig_eth_pcs_pma_core_support_layer_i : ten_gig_eth_pcs_pma_0_support
port map (
refclk_p => refclk_p,
refclk_n => refclk_n,
dclk_out => dclk_buf, -- ymei
coreclk_out => coreclk,
reset => reset,
sim_speedup_control => sim_speedup_control,
qplloutclk_out => qplloutclk_out,
qplloutrefclk_out => qplloutrefclk_out,
qplllock_out => qplllock_out,
rxrecclk_out => open,
txusrclk_out => txusrclk_out,
txusrclk2_out => txusrclk2_out,
gttxreset_out => gttxreset_out,
gtrxreset_out => gtrxreset_out,
txuserrdy_out => txuserrdy_out,
areset_datapathclk_out => areset_datapathclk_out,
reset_counter_done_out => reset_counter_done_out,
xgmii_txd => xgmii_txd_reg,
xgmii_txc => xgmii_txc_reg,
xgmii_rxd => xgmii_rxd_int,
xgmii_rxc => xgmii_rxc_int,
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
resetdone_out => resetdone_int,
signal_detect => signal_detect,
tx_fault => tx_fault,
tx_disable => tx_disable,
mdc => mdc_reg,
mdio_in => mdio_in_reg,
mdio_out => mdio_out_int,
mdio_tri => mdio_tri_int,
prtad => prtad,
pma_pmd_type => "101",
core_status => core_status);
qpll_locked <= qplllock_out; -- ymei
coreclk_out <= coreclk;
rx_clk_ddr : ODDR
generic map (
SRTYPE => "ASYNC",
DDR_CLK_EDGE => "SAME_EDGE")
port map (
Q => xgmii_rx_clk,
D1 => '0',
D2 => '1',
C => coreclk,
CE => '1',
R => '0',
S => '0');
end wrapper;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/width_pulse_sync.vhd | 1 | 3550 | --------------------------------------------------------------------------------
--! @file width_pulse_sync.vhd
--! @brief Produce a pulse of specified width in a different clock domain.
--! @author Yuan Mei
--!
--! Produce a pulse of specified width in a different clock domain
--! following a 1-CLKO wide reset pulse.
--! Ideally suited to change iodelay taps and iserdes bitslip
--! MODE := 0 output one pulse of duration PW
--! := 1 a train of 1-clk wide pulses (of number PW)
--! PW = 0 will still generate RSTO but no PO.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY width_pulse_sync IS
GENERIC (
DATA_WIDTH : positive := 8;
MODE : natural := 0 -- 0: output one pulse of duration PW
-- 1: a train of 1-clk wide pulses (of number PW)
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
PW : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
START : IN std_logic; -- should be synchronous to CLK, of any width
BUSY : OUT std_logic;
--
CLKO : IN std_logic;
RSTO : OUT std_logic;
PO : OUT std_logic
);
END width_pulse_sync;
ARCHITECTURE Behavioral OF width_pulse_sync IS
SIGNAL prev : std_logic;
SIGNAL prevb : std_logic;
SIGNAL prevb1 : std_logic;
SIGNAL prevo : std_logic;
SIGNAL prevo1 : std_logic;
SIGNAL busy_buf : std_logic;
SIGNAL busy_bufo : std_logic;
SIGNAL pw_buf : std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
SIGNAL po_buf : std_logic;
BEGIN
PROCESS (CLK, RESET) IS
BEGIN
IF RESET = '1' THEN
prev <= '0';
busy_buf <= '0';
pw_buf <= (OTHERS => '0');
prevb <= '0';
prevb1 <= '0';
ELSIF rising_edge(CLK) THEN
prev <= START;
-- Capture the rising edge of START, which is synchronous to CLK, of any width
IF (prev = '0' AND START = '1' AND prevb1 = '0') THEN
busy_buf <= '1';
pw_buf <= PW;
END IF;
prevb <= busy_bufo;
prevb1 <= prevb;
-- Capture the falling edge of busy_bufo
IF (prevb = '0' AND prevb1 = '1') THEN
busy_buf <= '0';
END IF;
END IF;
END PROCESS;
BUSY <= busy_buf;
-- output clock domain
PROCESS (CLKO) IS
VARIABLE counter : unsigned(DATA_WIDTH DOWNTO 0);
BEGIN
IF rising_edge(CLKO) THEN
prevo <= busy_buf;
prevo1 <= prevo;
busy_bufo <= '0';
po_buf <= '0';
RSTO <= '0';
-- Capture the rising edge of busy_buf
IF (prevo1 = '0' AND prevo = '1') THEN
busy_bufo <= '1';
counter := (OTHERS => '0');
RSTO <= '1';
ELSIF counter = 0 THEN
busy_bufo <= '1';
counter := counter + 1;
ELSIF counter <= unsigned(pw_buf) THEN
busy_bufo <= '1';
IF MODE = 0 THEN
counter := counter + 1;
po_buf <= '1';
ELSIF MODE = 1 THEN
IF po_buf = '0' THEN
counter := counter + 1;
END IF;
po_buf <= NOT po_buf;
END IF;
END IF;
END IF;
END PROCESS;
PO <= po_buf;
END Behavioral;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/ten_gig_eth/TE07412C1/fifo/ten_gig_eth_mac_0_xgmac_fifo.vhd | 3 | 10927 | -------------------------------------------------------------------------------
-- Title : XG MAC Tx/Rx FIFO Wrapper
-- Project : 10 Gig Ethernet MAC Core
-------------------------------------------------------------------------------
-- File : ten_gig_eth_mac_0_xgmac_fifo.vhd
-- Author : Xilinx Inc.
-------------------------------------------------------------------------------
-- Description:
-- This module is the top level entity for the 10 Gig Ethernet MAC FIFO
-- This top level connects together the lower hierarchial
-- entities which create this design. This is illustrated below.
-------------------------------------------------------------------------------
--
-- .---------------------------------------------.
-- | |
-- | .----------------------------. |
-- | | TRANSMIT_FIFO | |
-- ---------|------>| |--------|-------> MAC Tx
-- | | | | Interface
-- | '----------------------------' |
-- | |
-- | |
-- | |
-- External | |
-- AXI-S | |
-- Interface | |
-- | |
-- | .----------------------------. |
-- | | RECEIVE_FIFO | |
-- <--------|-------| |<-------|-------- MAC Rx Interface
-- | | | |
-- | '----------------------------' |
-- | |
-- | |
-- | |
-- | |
-- | |
-- '---------------------------------------------'
--
-------------------------------------------------------------------------------
-- Functionality:
--
-- 1. TRANSMIT_FIFO accepts 64-bit data from the client and writes
-- this into the Transmitter FIFO. The logic will then extract this from
-- the FIFO and write this data to the MAC Transmitter in 64-bit words.
--
-- 2. RECEIVE_FIFO accepts 64-bit data from the MAC Receiver and
-- writes this into the Receiver FIFO. The client inferface can then
-- read 64-bit words from this FIFO.
--
-------------------------------------------------------------------------------
-- (c) Copyright 2001-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.xgmac_fifo_pack.all;
entity ten_gig_eth_mac_0_xgmac_fifo is
generic (
TX_FIFO_SIZE : integer := 512; -- valid fifo sizes: 512, 1024, 2048, 4096, 8192, 16384 words.
RX_FIFO_SIZE : integer := 512); -- valid fifo sizes: 512, 1024, 2048, 4096, 8192, 16384 words.
port (
----------------------------------------------------------------
-- client interface --
----------------------------------------------------------------
-- tx_wr_clk domain
tx_axis_fifo_aresetn : in std_logic; -- the transmit client clock.
tx_axis_fifo_aclk : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(63 downto 0);
tx_axis_fifo_tkeep : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_fifo_full : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
--rx_rd_clk domain
rx_axis_fifo_aresetn : in std_logic;
rx_axis_fifo_aclk : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(63 downto 0);
rx_axis_fifo_tkeep : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
---------------------------------------------------------------------------
-- mac transmitter interface --
---------------------------------------------------------------------------
tx_axis_mac_aresetn : in std_logic;
tx_axis_mac_aclk : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(63 downto 0);
tx_axis_mac_tkeep : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
---------------------------------------------------------------------------
-- mac receiver interface --
---------------------------------------------------------------------------
rx_axis_mac_aresetn : in std_logic;
rx_axis_mac_aclk : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(63 downto 0);
rx_axis_mac_tkeep : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_full : out std_logic
);
end ten_gig_eth_mac_0_xgmac_fifo;
architecture rtl of ten_gig_eth_mac_0_xgmac_fifo is
component ten_gig_eth_mac_0_axi_fifo is
generic (
FIFO_SIZE : integer := 512;
WR_FLOW_CTRL : boolean := false);
port (
-- FIFO write domain
wr_axis_aresetn : in std_logic;
wr_axis_aclk : in std_logic;
wr_axis_tdata : in std_logic_vector(63 downto 0);
wr_axis_tkeep : in std_logic_vector(7 downto 0);
wr_axis_tvalid : in std_logic;
wr_axis_tlast : in std_logic;
wr_axis_tready : out std_logic;
wr_axis_tuser : in std_logic;
-- FIFO read domain
rd_axis_aresetn : in std_logic;
rd_axis_aclk : in std_logic;
rd_axis_tdata : out std_logic_vector(63 downto 0);
rd_axis_tkeep : out std_logic_vector(7 downto 0);
rd_axis_tvalid : out std_logic;
rd_axis_tlast : out std_logic;
rd_axis_tready : in std_logic;
-- FIFO Status Signals
fifo_status : out std_logic_vector(3 downto 0);
fifo_full : out std_logic );
end component;
begin
--Instance the transmit fifo.
i_tx_fifo : ten_gig_eth_mac_0_axi_fifo
generic map(
FIFO_SIZE => TX_FIFO_SIZE,
WR_FLOW_CTRL => true)
port map (
wr_axis_aresetn => tx_axis_fifo_aresetn,
wr_axis_aclk => tx_axis_fifo_aclk,
wr_axis_tdata => tx_axis_fifo_tdata,
wr_axis_tkeep => tx_axis_fifo_tkeep,
wr_axis_tvalid => tx_axis_fifo_tvalid,
wr_axis_tlast => tx_axis_fifo_tlast,
wr_axis_tready => tx_axis_fifo_tready,
wr_axis_tuser => tx_axis_fifo_tlast,
rd_axis_aresetn => tx_axis_mac_aresetn,
rd_axis_aclk => tx_axis_mac_aclk,
rd_axis_tdata => tx_axis_mac_tdata,
rd_axis_tkeep => tx_axis_mac_tkeep,
rd_axis_tvalid => tx_axis_mac_tvalid,
rd_axis_tlast => tx_axis_mac_tlast,
rd_axis_tready => tx_axis_mac_tready,
fifo_status => tx_fifo_status,
fifo_full => tx_fifo_full);
--Instance the receive fifo
rx_fifo_inst : ten_gig_eth_mac_0_axi_fifo
generic map (
FIFO_SIZE => RX_FIFO_SIZE,
WR_FLOW_CTRL => false)
port map (
wr_axis_aresetn => rx_axis_mac_aresetn,
wr_axis_aclk => rx_axis_mac_aclk,
wr_axis_tdata => rx_axis_mac_tdata,
wr_axis_tkeep => rx_axis_mac_tkeep,
wr_axis_tvalid => rx_axis_mac_tvalid,
wr_axis_tlast => rx_axis_mac_tlast,
wr_axis_tready => open,
wr_axis_tuser => rx_axis_mac_tuser,
rd_axis_aresetn => rx_axis_fifo_aresetn,
rd_axis_aclk => rx_axis_fifo_aclk,
rd_axis_tdata => rx_axis_fifo_tdata,
rd_axis_tkeep => rx_axis_fifo_tkeep,
rd_axis_tvalid => rx_axis_fifo_tvalid,
rd_axis_tlast => rx_axis_fifo_tlast,
rd_axis_tready => rx_axis_fifo_tready,
fifo_status => rx_fifo_status,
fifo_full => rx_fifo_full);
end rtl;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/gig_eth/KC705/common/tri_mode_ethernet_mac_0_sync_block.vhd | 5 | 5676 | --------------------------------------------------------------------------------
-- Title : CDC Sync Block
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_sync_block.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Used on signals crossing from one clock domain to another, this
-- is a multiple flip-flop pipeline, with all flops placed together
-- into the same slice. Thus the routing delay between the two is
-- minimum to safe-guard against metastability issues.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_sync_block is
generic (
INITIALISE : bit := '0';
DEPTH : integer := 5
);
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
attribute dont_touch : string;
attribute dont_touch of tri_mode_ethernet_mac_0_sync_block : entity is "yes";
end tri_mode_ethernet_mac_0_sync_block;
architecture structural of tri_mode_ethernet_mac_0_sync_block is
-- Internal Signals
signal data_sync0 : std_logic;
signal data_sync1 : std_logic;
signal data_sync2 : std_logic;
signal data_sync3 : std_logic;
signal data_sync4 : std_logic;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute async_reg : string;
attribute async_reg of data_sync_reg0 : label is "true";
attribute async_reg of data_sync_reg1 : label is "true";
attribute async_reg of data_sync_reg2 : label is "true";
attribute async_reg of data_sync_reg3 : label is "true";
attribute async_reg of data_sync_reg4 : label is "true";
attribute shreg_extract : string;
attribute shreg_extract of data_sync_reg0 : label is "no";
attribute shreg_extract of data_sync_reg1 : label is "no";
attribute shreg_extract of data_sync_reg2 : label is "no";
attribute shreg_extract of data_sync_reg3 : label is "no";
attribute shreg_extract of data_sync_reg4 : label is "no";
begin
data_sync_reg0 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_in,
Q => data_sync0,
CE => '1',
R => '0'
);
data_sync_reg1 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync0,
Q => data_sync1,
CE => '1',
R => '0'
);
data_sync_reg2 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync1,
Q => data_sync2,
CE => '1',
R => '0'
);
data_sync_reg3 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync2,
Q => data_sync3,
CE => '1',
R => '0'
);
data_sync_reg4 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync3,
Q => data_sync4,
CE => '1',
R => '0'
);
data_out <= data_sync4;
end structural;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/gig_eth/KC705/fifo/tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.vhd | 5 | 9650 | --------------------------------------------------------------------------------
-- Title : 10/100/1G Ethernet FIFO
-- Version : 1.2
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
-- The top level wrapper consists of individual FIFOs on the
-- transmitter path and on the receiver path.
--
-- Each path consists of an 8 bit local link to 8 bit client
-- interface FIFO.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo;
architecture RTL of tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
component tri_mode_ethernet_mac_0_rx_client_fifo
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end component;
component tri_mode_ethernet_mac_0_tx_client_fifo
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end component;
begin
------------------------------------------------------------------------------
-- Instantiate the Transmitter FIFO
------------------------------------------------------------------------------
tx_fifo_i : tri_mode_ethernet_mac_0_tx_client_fifo
generic map(
FULL_DUPLEX_ONLY => FULL_DUPLEX_ONLY
)
port map(
tx_fifo_aclk => tx_fifo_aclk,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => tx_mac_aclk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
fifo_overflow => tx_fifo_overflow,
fifo_status => tx_fifo_status,
tx_collision => tx_collision,
tx_retransmit => tx_retransmit
);
------------------------------------------------------------------------------
-- Instantiate the Receiver FIFO
------------------------------------------------------------------------------
rx_fifo_i : tri_mode_ethernet_mac_0_rx_client_fifo
port map(
rx_fifo_aclk => rx_fifo_aclk,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => rx_mac_aclk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
fifo_status => rx_fifo_status,
fifo_overflow => rx_fifo_overflow
);
end RTL;
| bsd-3-clause |
ymei/TMSPlane | Firmware/src/ten_gig_eth/TE07412C1/pcs_pma/ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2.vhd | 3 | 4290 | -----------------------------------------------------------------------------
-- Title : FF Synchronizer with Reset
-- Project : 10 Gigabit Ethernet PCS/PMA Core
-- File : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2.vhd
-- Author : Xilinx Inc.
-- Description: This module provides a parameterizable multi stage
-- FF Synchronizer with appropriate synth attributes
-- to mark ASYNC_REG and prevent SRL inference
-- An active reset is included with a paramterized
-- reset value
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
generic
(
C_NUM_SYNC_REGS : integer := 3;
C_RVAL : std_logic := '0'
);
port
(
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic;
data_out : out std_logic := '0'
);
end ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2;
architecture rtl of ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
signal sync1_r : std_logic_vector(C_NUM_SYNC_REGS-1 downto 0) := (others => C_RVAL);
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of sync1_r : signal is "no";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync1_r : signal is "true";
begin
-----------------------------------------------------------------------------
-- Synchronizer
-----------------------------------------------------------------------------
syncrst_proc : process(clk, rst)
begin
if(rst = '1') then
sync1_r <= (others => C_RVAL);
elsif(clk'event and clk = '1') then
sync1_r <= sync1_r(C_NUM_SYNC_REGS-2 downto 0) & data_in;
end if;
end process syncrst_proc;
outreg_proc : process(clk)
begin
if(clk'event and clk = '1') then
data_out <= sync1_r(C_NUM_SYNC_REGS-1);
end if;
end process outreg_proc;
end rtl;
| bsd-3-clause |
ambrosef/HLx_Examples | Acceleration/memcached/buildUoeMcdSingleDramPCIe/src/hdl/stats_module.vhd | 1 | 3847 | ----------------------------------------------------------------------------------
-- Company: XILINX
-- Engineer: Stephan Koster
--
-- Create Date: 07.03.2014 15:16:37
-- Design Name: stats module
-- Module Name: stats_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Sniffs an axi streaming bus, gathers stats and exposes them in a register
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity stats_module is
Generic(
data_size: INTEGER:=64;
period_counter_size: INTEGER :=22
);
Port (
ACLK : in std_logic;
RESET : in std_logic;
M_AXIS_TDATA : out std_logic_vector (data_size-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector (7 downto 0);
M_AXIS_TVALID : out std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TLAST : out std_logic;
S_AXIS_TDATA : in std_logic_vector (data_size-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector (7 downto 0);
S_AXIS_TUSER : in std_logic_vector (127 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TLAST : in std_logic;
--Expose the gathered stats
STATS_DATA : out std_logic_vector(31 downto 0)
);
end stats_module;
architecture Behavioral of stats_module is
signal rst,clk: std_logic;--rename hard to type signals
signal busycount: std_logic_vector(31 downto 0);--counts how many cycles both ready and valid are on
signal idlecount: std_logic_vector(31 downto 0);--so far does nothing
signal period_tracker: std_logic_vector(period_counter_size-1 downto 0);--measuring period ends on rollaround
signal count_reset:std_logic;
begin
rst<=RESET;
clk<=ACLK;
--axi stream signals pass straight through from master to slave. We just read Ready and Valid signals
M_AXIS_TDATA <= S_AXIS_TDATA;
M_AXIS_TSTRB <= S_AXIS_TSTRB;
M_AXIS_TVALID <= S_AXIS_TVALID;
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TLAST <= S_AXIS_TLAST;
generate_period:process(rst,clk)
begin
if(rst='1') then
period_tracker<=(others=>'0');
elsif(rising_edge(clk)) then
period_tracker<=std_logic_vector(unsigned(period_tracker)+1);
count_reset<=AND_REDUCE( period_tracker);--bitwise and
end if;
end process;
process(rst,clk)
begin
if(rst='1') then
--reset state
busycount<=(others=>'0');
STATS_DATA<=(others=>'0');
elsif(rising_edge(clk)) then
--write the output signal with the stats when the period counter rolls around
if(count_reset='1') then
--STATS_DATA(31)<='1';
STATS_DATA(period_counter_size downto 0)<=busycount(period_counter_size downto 0);
busycount<=(others=>'0');
else
--sniff the axi stream signals, gather stats
if(M_AXIS_TREADY='1' and S_AXIS_TVALID='1') then
busycount<=std_logic_vector(unsigned(busycount)+1);
end if;
end if;
end if;
end process;
end Behavioral;
| bsd-3-clause |
ambrosef/HLx_Examples | Acceleration/tcp_ip/rtl/arpServerWrapper.vhd | 2 | 8949 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity arpServerWrapper is
generic ( keyLength : integer := 32;
valueLength : integer := 48);
Port ( aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
myMacAddress : in std_logic_vector(47 downto 0);
myIpAddress : in std_logic_vector(31 downto 0);
axi_arp_to_arp_slice_tvalid : out std_logic;
axi_arp_to_arp_slice_tready : in std_logic;
axi_arp_to_arp_slice_tdata : out std_logic_vector(63 downto 0);
axi_arp_to_arp_slice_tkeep : out std_logic_vector(7 downto 0);
axi_arp_to_arp_slice_tlast : out std_logic;
axis_arp_lookup_reply_TVALID : out std_logic;
axis_arp_lookup_reply_TREADY : in std_logic;
axis_arp_lookup_reply_TDATA : out std_logic_vector(55 downto 0);
axi_arp_slice_to_arp_tvalid : in std_logic;
axi_arp_slice_to_arp_tready : out std_logic;
axi_arp_slice_to_arp_tdata : in std_logic_vector(63 downto 0);
axi_arp_slice_to_arp_tkeep : in std_logic_vector(7 downto 0);
axi_arp_slice_to_arp_tlast : in std_logic;
axis_arp_lookup_request_TVALID : in std_logic;
axis_arp_lookup_request_TREADY : out std_logic;
axis_arp_lookup_request_TDATA : in std_logic_vector(keyLength - 1 downto 0));
end arpServerWrapper;
architecture Structural of arpServerWrapper is
COMPONENT arp_server_ip
PORT(regIpAddress_V : IN std_logic_vector(31 downto 0);
myMacAddress_V : in std_logic_vector(47 downto 0);
aresetn : IN std_logic;
aclk : IN std_logic;
macUpdate_resp_TDATA : IN std_logic_vector(55 downto 0);
macUpdate_resp_TREADY : OUT std_logic;
macUpdate_resp_TVALID : IN std_logic;
macUpdate_req_TDATA : OUT std_logic_vector(87 downto 0);
macUpdate_req_TREADY : IN std_logic;
macUpdate_req_TVALID : OUT std_logic;
macLookup_resp_TDATA : IN std_logic_vector(55 downto 0);
macLookup_resp_TREADY : OUT std_logic;
macLookup_resp_TVALID : IN std_logic;
macLookup_req_TDATA : OUT std_logic_vector(39 downto 0);
macLookup_req_TREADY : IN std_logic;
macLookup_req_TVALID : OUT std_logic;
macIpEncode_rsp_TDATA : OUT std_logic_vector(55 downto 0);
macIpEncode_rsp_TREADY : IN std_logic;
macIpEncode_rsp_TVALID : OUT std_logic;
arpDataOut_TLAST : OUT std_logic;
arpDataOut_TKEEP : OUT std_logic_vector(7 downto 0);
arpDataOut_TDATA : OUT std_logic_vector(63 downto 0);
arpDataOut_TREADY : IN std_logic;
arpDataOut_TVALID : OUT std_logic;
macIpEncode_req_TDATA : IN std_logic_vector(31 downto 0);
macIpEncode_req_TREADY : OUT std_logic;
macIpEncode_req_TVALID : IN std_logic;
arpDataIn_TLAST : IN std_logic;
arpDataIn_TKEEP : IN std_logic_vector(7 downto 0);
arpDataIn_TDATA : IN std_logic_vector(63 downto 0);
arpDataIn_TREADY : OUT std_logic;
arpDataIn_TVALID : IN std_logic);
END COMPONENT;
signal invertedReset : std_logic;
signal lup_req_TVALID : std_logic;
signal lup_req_TREADY : std_logic;
signal lup_req_TDATA : std_logic_vector(39 downto 0);
signal lup_req_TDATA_im: std_logic_vector(keyLength downto 0);
signal lup_rsp_TVALID : std_logic;
signal lup_rsp_TREADY : std_logic;
signal lup_rsp_TDATA : std_logic_vector(55 downto 0);
signal lup_rsp_TDATA_im: std_logic_vector(valueLength downto 0);
signal upd_req_TVALID : std_logic;
signal upd_req_TREADY : std_logic;
signal upd_req_TDATA : std_logic_vector(87 downto 0);
signal upd_req_TDATA_im: std_logic_vector((keyLength + valueLength) + 1 downto 0);
signal upd_rsp_TVALID : std_logic;
signal upd_rsp_TREADY : std_logic;
signal upd_rsp_TDATA : std_logic_vector(55 downto 0);
signal upd_rsp_TDATA_im: std_logic_vector(valueLength + 1 downto 0);
begin
lup_req_TDATA_im <= lup_req_TDATA(32 downto 0);
lup_rsp_TDATA <= "0000000" & lup_rsp_TDATA_im;
upd_req_TDATA_im <= upd_req_TDATA((keyLength + valueLength) + 1 downto 0);
upd_rsp_TDATA <= "000000" & upd_rsp_TDATA_im;
invertedReset <= NOT aresetn;
-- SmartCam Wrapper
SmartCamCtl_inst: entity work.SmartCamCtlArp--(behavior)
port map(clk => aclk,
rst => invertedReset,
led0 => open,
led1 => open,
cam_ready => open,
lup_req_valid => lup_req_TVALID,
lup_req_ready => lup_req_TREADY,
lup_req_din => lup_req_TDATA_im,
lup_rsp_valid => lup_rsp_TVALID,
lup_rsp_ready => lup_rsp_TREADY,
lup_rsp_dout => lup_rsp_TDATA_im,
upd_req_valid => upd_req_TVALID,
upd_req_ready => upd_req_TREADY,
upd_req_din => upd_req_TDATA_im,
upd_rsp_valid => upd_rsp_TVALID,
upd_rsp_ready => upd_rsp_TREADY,
upd_rsp_dout => upd_rsp_TDATA_im,
debug => open);
-- ARP Server
arp_server_inst: arp_server_ip
port map (regIpAddress_V => myIpAddress,
myMacAddress_V => myMacAddress,
arpDataIn_TVALID => axi_arp_slice_to_arp_tvalid,
arpDataIn_TREADY => axi_arp_slice_to_arp_tready,
arpDataIn_TDATA => axi_arp_slice_to_arp_tdata,
arpDataIn_TKEEP => axi_arp_slice_to_arp_tkeep,
arpDataIn_TLAST => axi_arp_slice_to_arp_tlast,
macIpEncode_req_TVALID => axis_arp_lookup_request_TVALID,
macIpEncode_req_TREADY => axis_arp_lookup_request_TREADY,
macIpEncode_req_TDATA => axis_arp_lookup_request_TDATA,
arpDataOut_TVALID => axi_arp_to_arp_slice_tvalid,
arpDataOut_TREADY => axi_arp_to_arp_slice_tready,
arpDataOut_TDATA => axi_arp_to_arp_slice_tdata,
arpDataOut_TKEEP => axi_arp_to_arp_slice_tkeep,
arpDataOut_TLAST => axi_arp_to_arp_slice_tlast,
macIpEncode_rsp_TVALID => axis_arp_lookup_reply_TVALID,
macIpEncode_rsp_TREADY => axis_arp_lookup_reply_TREADY,
macIpEncode_rsp_TDATA => axis_arp_lookup_reply_TDATA,
macLookup_req_TVALID => lup_req_TVALID,
macLookup_req_TREADY => lup_req_TREADY,
macLookup_req_TDATA => lup_req_TDATA,
macLookup_resp_TVALID => lup_rsp_TVALID,
macLookup_resp_TREADY => lup_rsp_TREADY,
macLookup_resp_TDATA => lup_rsp_TDATA,
macUpdate_req_TVALID => upd_req_TVALID,
macUpdate_req_TREADY => upd_req_TREADY,
macUpdate_req_TDATA => upd_req_TDATA,
macUpdate_resp_TVALID => upd_rsp_TVALID,
macUpdate_resp_TREADY => upd_rsp_TREADY,
macUpdate_resp_TDATA => upd_rsp_TDATA,
aclk => aclk,
aresetn => aresetn);
end Structural; | bsd-3-clause |
schelleg/PYNQ | boards/ip/audio_codec_ctrl_v1.0/src/slave_attachment.vhd | 7 | 21369 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
| bsd-3-clause |
schelleg/PYNQ | boards/ip/dvi2rgb_v1_7/src/PhaseAlign.vhd | 5 | 14475 | -------------------------------------------------------------------------------
--
-- File: PhaseAlign.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 7 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module receives a DVI-encoded stream of 10-bit deserialized words
-- and tries to change the phase of the serial data to shift the sampling
-- event to the middle of the "eye", ie. the part of the bit period where
-- data is stable. Alignment is achieved by incrementing the tap count of
-- the IDELAYE2 primitives, delaying data by kIDLY_TapValuePs in each step.
-- In Artix-7 architecture each tap (step) accounts to 78 ps.
-- Data is considered valid when control tokens are recognized in the
-- stream. Alignment lock is achieved when the middle of the valid eye is
-- found. When this happens, pAligned will go high. If the whole range of
-- delay values had been exhausted and alignment lock could still not be
-- achieved, pError will go high. Resetting the module with pRst will
-- restart the alignment process.
-- The port pEyeSize provides an approximation of the width of the
-- eye in units of tap count. The larger the number, the better the signal
-- quality of the DVI stream.
-- Since the IDELAYE2 primitive only allows a fine alignment, the bitslip
-- feature of the ISERDES primitives complements the PhaseAlign module acting
-- as coarse alignment to find the 10-bit word boundary in the data stream.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PhaseAlign is
Generic (
kUseFastAlgorithm : boolean := false;
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
pRst : in STD_LOGIC;
pTimeoutOvf : in std_logic; --50ms timeout expired
pTimeoutRst : out std_logic; --reset timeout
PixelClk : in STD_LOGIC;
pData : in STD_LOGIC_VECTOR (9 downto 0);
pIDLY_CE : out STD_LOGIC;
pIDLY_INC : out STD_LOGIC;
pIDLY_CNT : in STD_LOGIC_VECTOR (kIDLY_TapWidth-1 downto 0);
pIDLY_LD : out STD_LOGIC; --load default tap value
pAligned : out STD_LOGIC;
pError : out STD_LOGIC;
pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0));
end PhaseAlign;
architecture Behavioral of PhaseAlign is
-- Control Token Counter
signal pCtlTknCnt : natural range 0 to kCtlTknCount-1;
signal pCtlTknRst, pCtlTknOvf : std_logic;
-- Control Token Detection Pipeline
signal pTkn0Flag, pTkn1Flag, pTkn2Flag, pTkn3Flag : std_logic;
signal pTkn0FlagQ, pTkn1FlagQ, pTkn2FlagQ, pTkn3FlagQ : std_logic;
signal pTknFlag, pTknFlagQ, pBlankBegin : std_logic;
signal pDataQ : std_logic_vector(pData'high downto pData'low);
constant kTapCntEnd : std_logic_vector(pIDLY_CNT'range) := (others => '0');
constant kFastTapCntEnd : std_logic_vector(pIDLY_CNT'range) := std_logic_vector(to_unsigned(20, pIDLY_CNT'length)); -- fast search limit; if token not found in 20 taps, fail earlier and bitslip
signal pIDLY_CNT_Q : std_logic_vector(pIDLY_CNT'range);
signal pDelayOvf, pDelayFastOvf, pDelayCenter : std_logic;
-- IDELAY increment/decrement wait counter
-- CE, INC registered outputs + CNTVALUEOUT registered input + CNTVALUEOUT registered comparison
constant kDelayWaitEnd : natural := 3;
signal pDelayWaitCnt : natural range 0 to kDelayWaitEnd - 1;
signal pDelayWaitRst, pDelayWaitOvf : std_logic;
constant kEyeOpenCntMin : natural := 3;
constant kEyeOpenCntEnough : natural := 16;
signal pEyeOpenCnt : unsigned(kIDLY_TapWidth-1 downto 0);
signal pCenterTap : unsigned(kIDLY_TapWidth downto 0); -- 1 extra bit to increment with 1/2 for every open eye tap
signal pEyeOpenRst, pEyeOpenEn : std_logic;
--Flags
signal pFoundJtrFlag, pFoundEyeFlag : std_logic;
--FSM
--type state_t is (ResetSt, IdleSt, TokenSt, EyeOpenSt, JtrZoneSt, DlyIncSt, DlyTstOvfSt, DlyDecSt, DlyTstCenterSt, AlignedSt, AlignErrorSt);
subtype state_t is std_logic_vector(10 downto 0);
signal pState, pStateNxt : state_t;
-- Ugh, manual state encoding, since Vivado won't tell me the result of automatic encoding; we need this for debugging.
constant ResetSt : state_t := "00000000001";
constant IdleSt : state_t := "00000000010";
constant TokenSt : state_t := "00000000100";
constant EyeOpenSt : state_t := "00000001000";
constant JtrZoneSt : state_t := "00000010000";
constant DlyIncSt : state_t := "00000100000";
constant DlyTstOvfSt : state_t := "00001000000";
constant DlyDecSt : state_t := "00010000000";
constant DlyTstCenterSt : state_t :="00100000000";
constant AlignedSt : state_t := "01000000000";
constant AlignErrorSt : state_t := "10000000000";
begin
ControlTokenCounter: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pCtlTknRst = '1') then
pCtlTknCnt <= 0;
else
pCtlTknCnt <= pCtlTknCnt + 1;
-- Overflow
if (pCtlTknCnt = kCtlTknCount - 1) then
pCtlTknOvf <= '1';
else
pCtlTknOvf <= '0';
end if;
end if;
end if;
end process ControlTokenCounter;
-- Control Token Detection
pTkn0Flag <= '1' when pDataQ = kCtlTkn0 else '0';
pTkn1Flag <= '1' when pDataQ = kCtlTkn1 else '0';
pTkn2Flag <= '1' when pDataQ = kCtlTkn2 else '0';
pTkn3Flag <= '1' when pDataQ = kCtlTkn3 else '0';
-- Register pipeline
ControlTokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pDataQ <= pData; -- level 1
pTkn0FlagQ <= pTkn0Flag;
pTkn1FlagQ <= pTkn1Flag;
pTkn2FlagQ <= pTkn2Flag;
pTkn3FlagQ <= pTkn3Flag; -- level 2
pTknFlag <= pTkn0Flag or pTkn1Flag or pTkn2Flag or pTkn3Flag; -- level 3
pTknFlagQ <= pTknFlag;
pBlankBegin <= not pTknFlagQ and pTknFlag; -- level 4
end if;
end process ControlTokenDetect;
-- Open Eye Width Counter
EyeOpenCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pEyeOpenRst = '1') then
pEyeOpenCnt <= (others => '0');
pCenterTap <= unsigned(pIDLY_CNT_Q) & '1'; -- 1 extra bit for 1/2 increments; start with 1/2
elsif (pEyeOpenEn = '1') then
pEyeOpenCnt <= pEyeOpenCnt + 1;
pCenterTap <= pCenterTap + 1;
end if;
end if;
end process EyeOpenCnt;
pEyeSize <= std_logic_vector(pEyeOpenCnt);
-- Tap Delay Overflow
TapDelayCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
pIDLY_CNT_Q <= pIDLY_CNT;
if (pIDLY_CNT_Q = kTapCntEnd) then
pDelayOvf <= '1';
else
pDelayOvf <= '0';
end if;
if (pIDLY_CNT_Q = kFastTapCntEnd) then
pDelayFastOvf <= '1';
else
pDelayFastOvf <= '0';
end if;
end if;
end process TapDelayCnt;
-- Tap Delay Center
TapDelayCenter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (unsigned(pIDLY_CNT_Q) = SHIFT_RIGHT(pCenterTap, 1)) then
pDelayCenter <= '1';
else
pDelayCenter <= '0';
end if;
end if;
end process TapDelayCenter;
DelayIncWaitCounter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pDelayWaitRst = '1') then
pDelayWaitCnt <= 0;
else
pDelayWaitCnt <= pDelayWaitCnt + 1;
if (pDelayWaitCnt = kDelayWaitEnd - 1) then
pDelayWaitOvf <= '1';
else
pDelayWaitOvf <= '0';
end if;
end if;
end if;
end process DelayIncWaitCounter;
-- FSM
FSM_Sync: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRst = '1') then
pState <= ResetSt;
else
pState <= pStateNxt;
end if;
end if;
end process FSM_Sync;
--FSM Outputs
pTimeoutRst <= '0' when pState = IdleSt or pState = TokenSt else '1';
pCtlTknRst <= '0' when pState = TokenSt else '1';
pDelayWaitRst <= '0' when pState = DlyTstOvfSt or pState = DlyTstCenterSt else '1';
pEyeOpenRst <= '1' when pState = ResetSt or (pState = JtrZoneSt and pFoundEyeFlag = '0') else '0';
pEyeOpenEn <= '1' when pState = EyeOpenSt else '0';
--FSM Registered Outputs
FSM_RegOut: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pState = ResetSt) then
pIDLY_LD <= '1';
else
pIDLY_LD <= '0';
end if;
if (pState = DlyIncSt) then
pIDLY_INC <= '1';
pIDLY_CE <= '1';
elsif (pState = DlyDecSt) then
pIDLY_INC <= '0';
pIDLY_CE <= '1';
else
pIDLY_CE <= '0';
end if;
if (pState = AlignedSt) then
pAligned <= '1';
else
pAligned <= '0';
end if;
if (pState = AlignErrorSt) then
pError <= '1';
else
pError <= '0';
end if;
end if;
end process FSM_RegOut;
FSM_Flags: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
case (pState) is
when ResetSt =>
pFoundEyeFlag <= '0';
pFoundJtrFlag <= '0';
when JtrZoneSt =>
pFoundJtrFlag <= '1';
when EyeOpenSt =>
-- We consider the eye found, if we had found jitter before and the eye is at least kEyeOpenCntMin wide OR
-- We have not seen jitter yet (because tap 0 was already in the eye) and the eye is at least kEyeOpenCntEnough wide
if ((pFoundJtrFlag = '1' and pEyeOpenCnt = kEyeOpenCntMin) or (pEyeOpenCnt = kEyeOpenCntEnough)) then
pFoundEyeFlag <= '1';
end if;
when others =>
end case;
end if;
end process FSM_Flags;
FSM_NextState: process (pState, pBlankBegin, pTimeoutOvf, pCtlTknOvf, pDelayOvf, pDelayFastOvf, pDelayWaitOvf,
pEyeOpenCnt, pDelayCenter, pFoundEyeFlag, pTknFlagQ)
begin
pStateNxt <= pState; --default is to stay in current state
case (pState) is
when ResetSt =>
pStateNxt <= IdleSt;
when IdleSt => -- waiting for a token with timeout
if (pBlankBegin = '1') then
pStateNxt <= TokenSt;
elsif (pTimeoutOvf = '1') then
pStateNxt <= JtrZoneSt; -- we didn't find a proper blank, must be in jitter zone
end if;
when TokenSt => -- waiting for kCtlTknCount tokens with timeout
if (pTknFlagQ = '0') then
pStateNxt <= IdleSt;
elsif (pCtlTknOvf = '1') then
pStateNxt <= EyeOpenSt;
end if;
when JtrZoneSt =>
if (pFoundEyeFlag = '1') then
pStateNxt <= DlyDecSt; -- this jitter zone ends an open eye, go back to the middle of the eye
elsif (kUseFastAlgorithm and pDelayFastOvf = '1' and pFoundEyeFlag = '0') then
pStateNxt <= AlignErrorSt;
else
pStateNxt <= DlyIncSt;
end if;
when EyeOpenSt =>
-- If our eye is already kEyeOpenCntEnough wide, consider the search finished and consider the current tap value
-- the end of our eye = jitter zone
if (pEyeOpenCnt = kEyeOpenCntEnough) then
pStateNxt <= JtrZoneSt;
else
pStateNxt <= DlyIncSt;
end if;
when DlyIncSt =>
pStateNxt <= DlyTstOvfSt;
when DlyTstOvfSt =>
if (pDelayWaitOvf = '1') then
if (pDelayOvf = '1') then
pStateNxt <= AlignErrorSt; -- we went through all the delay taps
else
pStateNxt <= IdleSt;
end if;
end if;
when DlyDecSt =>
pStateNxt <= DlyTstCenterSt;
when DlyTstCenterSt =>
if (pDelayWaitOvf = '1') then
if (pDelayCenter = '1') then
pStateNxt <= AlignedSt; -- we went back to the center of the eye, done
else
pStateNxt <= DlyDecSt;
end if;
end if;
when AlignedSt =>
null; --stay here
when AlignErrorSt =>
null; --stay here
when others =>
pStateNxt <= ResetSt;
end case;
end process FSM_NextState;
end Behavioral;
| bsd-3-clause |
sigasi/SigasiProjectCreator | tests/test-files/tutorial/foo/foo.vhd | 1 | 79 | package foo is
end package foo;
package body foo is
end package body foo;
| bsd-3-clause |
VectorBlox/PYNQ | Pynq-Z1/vivado/ip/d_axi_pdm_1.2/src/pdm_des.vhd | 8 | 3943 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:14 01/31/2014
-- Design Name:
-- Module Name: pdm_des - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pdm_des is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
-- PDM
pdm_m_clk_o : out std_logic;
pdm_m_data_i : in std_logic;
pdm_lrsel_o : out std_logic
);
end pdm_des;
architecture Behavioral of pdm_des is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal cnt_clk : integer range 0 to 127 := 0;
signal clk_int, clk_intt : std_logic := '0';
signal pdm_clk_rising, pdm_clk_falling : std_logic;
signal pdm_tmp : std_logic_vector((C_NR_OF_BITS-1) downto 0);
signal cnt_bits : integer range 0 to 31 := 0;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- with L/R Sel tied to GND => output = DATA1 (rising edge)
pdm_lrsel_o <= '0';
------------------------------------------------------------------------
-- Deserializer
------------------------------------------------------------------------
-- sample input serial data process
SHFT_IN: process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
pdm_tmp <= pdm_tmp(C_NR_OF_BITS-2 downto 0) & pdm_m_data_i;
end if;
end if;
end process SHFT_IN;
-- counter for the number of sampled bits
CNT: process(clk_i) begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
cnt_bits <= 0;
else
cnt_bits <= cnt_bits + 1;
end if;
end if;
end if;
end process CNT;
-- done gen
process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
done_o <= '1';
data_o <= pdm_tmp;
end if;
else
done_o <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------
-- slave clock generator
------------------------------------------------------------------------
CLK_CNT: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' or cnt_clk = ((C_SYS_CLK_FREQ_MHZ/(C_PDM_FREQ_MHZ*2))-1) then
cnt_clk <= 0;
clk_int <= not clk_int;
else
cnt_clk <= cnt_clk + 1;
end if;
clk_intt <= clk_int;
end if;
end process CLK_CNT;
pdm_m_clk_o <= clk_int;
pdm_clk_rising <= '1' when clk_int = '1' and clk_intt = '0' and en_i = '1' else '0';
--pdm_clk_falling <= '1' when cnt_clk = ((clk_div/2)-1) else '0';
end Behavioral;
| bsd-3-clause |
VectorBlox/PYNQ | Pynq-Z1/vivado/ip/rgb2dvi_v1_2/src/SyncAsyncReset.vhd | 29 | 3734 | -------------------------------------------------------------------------------
--
-- File: SyncAsyncReset.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int : std_logic;
attribute KEEP : string;
attribute KEEP of aRst_int: signal is "TRUE";
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => oRst);
end Behavioral;
| bsd-3-clause |
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