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|---|---|---|---|---|---|
cpulabs/mist1032sa | sim/inst_level/work/execute_shift/_primary.vhd | 1 | 696 | library verilog;
use verilog.vl_types.all;
entity execute_shift is
generic(
P_N : integer := 32
);
port(
iCONTROL_MODE : in vl_logic_vector(2 downto 0);
iDATA_0 : in vl_logic_vector;
iDATA_1 : in vl_logic_vector;
oDATA : out vl_logic_vector;
oSF : out vl_logic;
oOF : out vl_logic;
oCF : out vl_logic;
oPF : out vl_logic;
oZF : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of P_N : constant is 1;
end execute_shift;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/decode_mmucheck/_primary.vhd | 1 | 441 | library verilog;
use verilog.vl_types.all;
entity decode_mmucheck is
port(
iPAGING_ENA : in vl_logic;
iKERNEL_ACCESS : in vl_logic;
iMMU_FLAGS : in vl_logic_vector(13 downto 0);
oIRQ40 : out vl_logic_vector(2 downto 0);
oIRQ41 : out vl_logic_vector(2 downto 0);
oIRQ42 : out vl_logic_vector(2 downto 0)
);
end decode_mmucheck;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/cda_n_cntr/_primary.vhd | 1 | 288 | library verilog;
use verilog.vl_types.all;
entity cda_n_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
modulus : in vl_logic_vector(31 downto 0)
);
end cda_n_cntr;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/altdpram/_primary.vhd | 1 | 4228 | library verilog;
use verilog.vl_types.all;
entity altdpram is
generic(
width : integer := 1;
widthad : integer := 1;
numwords : integer := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
use_eab : string := "ON";
lpm_type : string := "altdpram";
indata_reg : string := "INCLOCK";
indata_aclr : string := "ON";
wraddress_reg : string := "INCLOCK";
wraddress_aclr : string := "ON";
wrcontrol_reg : string := "INCLOCK";
wrcontrol_aclr : string := "ON";
rdaddress_reg : string := "OUTCLOCK";
rdaddress_aclr : string := "ON";
rdcontrol_reg : string := "OUTCLOCK";
rdcontrol_aclr : string := "ON";
outdata_reg : string := "UNREGISTERED";
outdata_aclr : string := "ON";
maximum_depth : integer := 2048;
intended_device_family: string := "Stratix";
ram_block_type : string := "AUTO";
width_byteena : integer := 1;
byte_size : integer := 0;
read_during_write_mode_mixed_ports: string := "DONT_CARE";
i_byte_size : vl_notype;
is_lutram : vl_notype;
i_width_byteena : vl_notype;
i_read_during_write: vl_notype;
write_at_low_clock: vl_notype
);
port(
wren : in vl_logic;
data : in vl_logic_vector;
wraddress : in vl_logic_vector;
inclock : in vl_logic;
inclocken : in vl_logic;
rden : in vl_logic;
rdaddress : in vl_logic_vector;
wraddressstall : in vl_logic;
rdaddressstall : in vl_logic;
byteena : in vl_logic_vector;
outclock : in vl_logic;
outclocken : in vl_logic;
aclr : in vl_logic;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of widthad : constant is 1;
attribute mti_svvh_generic_type of numwords : constant is 1;
attribute mti_svvh_generic_type of lpm_file : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of use_eab : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of indata_reg : constant is 1;
attribute mti_svvh_generic_type of indata_aclr : constant is 1;
attribute mti_svvh_generic_type of wraddress_reg : constant is 1;
attribute mti_svvh_generic_type of wraddress_aclr : constant is 1;
attribute mti_svvh_generic_type of wrcontrol_reg : constant is 1;
attribute mti_svvh_generic_type of wrcontrol_aclr : constant is 1;
attribute mti_svvh_generic_type of rdaddress_reg : constant is 1;
attribute mti_svvh_generic_type of rdaddress_aclr : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_reg : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_aclr : constant is 1;
attribute mti_svvh_generic_type of outdata_reg : constant is 1;
attribute mti_svvh_generic_type of outdata_aclr : constant is 1;
attribute mti_svvh_generic_type of maximum_depth : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of width_byteena : constant is 1;
attribute mti_svvh_generic_type of byte_size : constant is 1;
attribute mti_svvh_generic_type of read_during_write_mode_mixed_ports : constant is 1;
attribute mti_svvh_generic_type of i_byte_size : constant is 3;
attribute mti_svvh_generic_type of is_lutram : constant is 3;
attribute mti_svvh_generic_type of i_width_byteena : constant is 3;
attribute mti_svvh_generic_type of i_read_during_write : constant is 3;
attribute mti_svvh_generic_type of write_at_low_clock : constant is 3;
end altdpram;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/@m@f_pll_reg/_primary.vhd | 1 | 354 | library verilog;
use verilog.vl_types.all;
entity MF_pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
d : in vl_logic;
clrn : in vl_logic;
prn : in vl_logic
);
end MF_pll_reg;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/altddio_in/_primary.vhd | 1 | 1270 | library verilog;
use verilog.vl_types.all;
entity altddio_in is
generic(
width : integer := 1;
power_up_high : string := "OFF";
invert_input_clocks: string := "OFF";
intended_device_family: string := "Stratix";
lpm_type : string := "altddio_in";
lpm_hint : string := "UNUSED"
);
port(
datain : in vl_logic_vector;
inclock : in vl_logic;
inclocken : in vl_logic;
aset : in vl_logic;
aclr : in vl_logic;
sset : in vl_logic;
sclr : in vl_logic;
dataout_h : out vl_logic_vector;
dataout_l : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of power_up_high : constant is 1;
attribute mti_svvh_generic_type of invert_input_clocks : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
end altddio_in;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/radix2_linediv/_primary.vhd | 1 | 417 | library verilog;
use verilog.vl_types.all;
entity radix2_linediv is
port(
iSOURCE_DIVIDEND: in vl_logic_vector(1 downto 0);
iSOURCE_DIVISOR : in vl_logic_vector(31 downto 0);
iSOURCE_R : in vl_logic_vector(30 downto 0);
oOUT_DATA_Q : out vl_logic_vector(1 downto 0);
oOUT_DATA_R : out vl_logic_vector(30 downto 0)
);
end radix2_linediv;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/sim_memory_model/_primary.vhd | 1 | 1151 | library verilog;
use verilog.vl_types.all;
entity sim_memory_model is
generic(
P_MEM_INIT_LOAD : integer := 1;
P_MEM_INIT_LOAD_FIEL: string := "binary_file.bin";
P_MEM_SIZE : integer := 16777216
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iMEMORY_REQ : in vl_logic;
oMEMORY_LOCK : out vl_logic;
iMEMORY_ORDER : in vl_logic_vector(1 downto 0);
iMEMORY_MASK : in vl_logic_vector(3 downto 0);
iMEMORY_RW : in vl_logic;
iMEMORY_ADDR : in vl_logic_vector(31 downto 0);
iMEMORY_DATA : in vl_logic_vector(31 downto 0);
oMEMORY_VALID : out vl_logic;
iMEMORY_LOCK : in vl_logic;
oMEMORY_DATA : out vl_logic_vector(63 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of P_MEM_INIT_LOAD : constant is 1;
attribute mti_svvh_generic_type of P_MEM_INIT_LOAD_FIEL : constant is 1;
attribute mti_svvh_generic_type of P_MEM_SIZE : constant is 1;
end sim_memory_model;
| bsd-2-clause |
Calculingua/cali-app | vendor/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/axi_bram_ctrl_funcs.vhd | 1 | 17315 | -------------------------------------------------------------------------------
-- axi_bram_ctrl_funcs.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_funcs.vhd
--
-- Description: Support functions for axi_bram_ctrl library modules.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
--
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/16/2011 v1.03a
-- ~~~~~~
-- Update ECC size on 128-bit data width configuration.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Add MIG functions for Hsiao ECC.
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Add Find_ECC_Size function.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Add REDUCTION_OR function.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Recode Create_Size_Max with a case statement.
-- ^^^^^^
-- JLJ 3/31/2011 v1.03a
-- ~~~~~~
-- Add coverage tags.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Remove Family_To_LUT_Size function.
-- Remove String_To_Family function.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package axi_bram_ctrl_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
SPARTAN3,
VIRTEX4,
VIRTEX5,
SPARTAN3E,
SPARTAN3A,
SPARTAN3AN,
SPARTAN3Adsp,
SPARTAN6,
VIRTEX6,
VIRTEX7,
KINTEX7,
-- pragma xilinx_rtl_on
RTL
);
-- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
-- function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN;
function log2(x : natural) return integer;
function Int_ECC_Size (i: integer) return integer;
function Find_ECC_Size (i: integer; j: integer) return integer;
function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer;
function Create_Size_Max (i: integer) return std_logic_vector;
function REDUCTION_OR (A: in std_logic_vector) return std_logic;
function REDUCTION_XOR (A: in std_logic_vector) return std_logic;
function REDUCTION_NOR (A: in std_logic_vector) return std_logic;
function BOOLEAN_TO_STD_LOGIC (A: in BOOLEAN) return std_logic;
end package axi_bram_ctrl_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body axi_bram_ctrl_funcs is
-------------------------------------------------------------------------------
-- Function: Int_ECC_Size
-- Purpose: Determine internal size of ECC when enabled.
-------------------------------------------------------------------------------
function Int_ECC_Size (i: integer) return integer is
begin
--coverage off
if (i = 32) then
return 7; -- 7-bits ECC for 32-bit data
-- ECC port size fixed @ 8-bits
elsif (i = 64) then
return 8;
elsif (i = 128) then
return 9; -- Hsiao is 9-bits for 128-bit data.
else
return 0;
end if;
--coverage on
end Int_ECC_Size;
-------------------------------------------------------------------------------
-- Function: Find_ECC_Size
-- Purpose: Determine external size of ECC signals when enabled.
-------------------------------------------------------------------------------
function Find_ECC_Size (i: integer; j: integer) return integer is
begin
--coverage off
if (i = 1) then
if (j = 32) then
return 8; -- Keep at 8 for port size matchings
-- Only 7-bits ECC per 32-bit data
elsif (j = 64) then
return 8;
elsif (j = 128) then
return 9;
else
return 0;
end if;
else
return 0;
-- ECC data width = 0 when C_ECC = 0 (disabled)
end if;
--coverage on
end Find_ECC_Size;
-------------------------------------------------------------------------------
-- Function: Find_ECC_Full_Bit_Size
-- Purpose: Determine external size of ECC signals when enabled in bytes.
-------------------------------------------------------------------------------
function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer is
begin
--coverage off
if (i = 1) then
if (j = 32) then
return 8;
elsif (j = 64) then
return 8;
elsif (j = 128) then
return 16;
else
return 0;
end if;
else
return 0;
-- ECC data width = 0 when C_ECC = 0 (disabled)
end if;
--coverage on
end Find_ECC_Full_Bit_Size;
-------------------------------------------------------------------------------
-- Function: Create_Size_Max
-- Purpose: Create maximum value for AxSIZE based on AXI data bus width.
-------------------------------------------------------------------------------
function Create_Size_Max (i: integer)
return std_logic_vector is
variable size_vector : std_logic_vector (2 downto 0);
begin
case (i) is
when 32 => size_vector := "010"; -- 2h (4 bytes)
when 64 => size_vector := "011"; -- 3h (8 bytes)
when 128 => size_vector := "100"; -- 4h (16 bytes)
when 256 => size_vector := "101"; -- 5h (32 bytes)
when 512 => size_vector := "110"; -- 5h (32 bytes)
when 1024 => size_vector := "111"; -- 5h (32 bytes)
--coverage off
when others => size_vector := "000"; -- 0h
--coverage on
end case;
return (size_vector);
end function Create_Size_Max;
-------------------------------------------------------------------------------
-- Function: REDUCTION_OR
-- Purpose: New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_OR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
-------------------------------------------------------------------------------
-- Function: REDUCTION_XOR
-- Purpose: Derived from MIG v3.7 ecc_gen module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_XOR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp xor A(i);
end loop;
return tmp;
end function REDUCTION_XOR;
-------------------------------------------------------------------------------
-- Function: REDUCTION_NOR
-- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_NOR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return not tmp;
end function REDUCTION_NOR;
-------------------------------------------------------------------------------
-- Function: BOOLEAN_TO_STD_LOGIC
-- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function BOOLEAN_TO_STD_LOGIC (A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
-------------------------------------------------------------------------------
function LowerCase_Char(char : character) return character is
begin
--coverage off
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
--coverage on
end LowerCase_Char;
-------------------------------------------------------------------------------
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String ( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
--coverage off
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
--coverage on
RETURN equal;
END Equal_String;
-------------------------------------------------------------------------------
-- Remove usage of C_FAMILY.
-- Remove usage of String_To_Family function.
--
--
-- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
-- begin -- function String_To_Family
--
-- --coverage off
--
-- if ((Select_RTL) or Equal_String(S, "rtl")) then
-- return RTL;
-- elsif Equal_String(S, "spartan3") or Equal_String(S, "aspartan3") then
-- return SPARTAN3;
-- elsif Equal_String(S, "spartan3E") or Equal_String(S, "aspartan3E") then
-- return SPARTAN3E;
-- elsif Equal_String(S, "spartan3A") or Equal_String(S, "aspartan3A") then
-- return SPARTAN3A;
-- elsif Equal_String(S, "spartan3AN") then
-- return SPARTAN3AN;
-- elsif Equal_String(S, "spartan3Adsp") or Equal_String(S, "aspartan3Adsp") then
-- return SPARTAN3Adsp;
-- elsif Equal_String(S, "spartan6") or Equal_String(S, "spartan6l") or
-- Equal_String(S, "qspartan6") or Equal_String(S, "aspartan6") or Equal_String(S, "qspartan6l") then
-- return SPARTAN6;
-- elsif Equal_String(S, "virtex4") or Equal_String(S, "qvirtex4")
-- or Equal_String(S, "qrvirtex4") then
-- return VIRTEX4;
-- elsif Equal_String(S, "virtex5") or Equal_String(S, "qrvirtex5") then
-- return VIRTEX5;
-- elsif Equal_String(S, "virtex6") or Equal_String(S, "virtex6l") or Equal_String(S, "qvirtex6") then
-- return VIRTEX6;
-- elsif Equal_String(S, "virtex7") then
-- return VIRTEX7;
-- elsif Equal_String(S, "kintex7") then
-- return KINTEX7;
--
-- --coverage on
--
-- else
-- -- assert (false) report "No known target family" severity failure;
-- return RTL;
-- end if;
--
-- end function String_To_Family;
-------------------------------------------------------------------------------
-- Remove usage of C_FAMILY.
-- Remove usage of Family_To_LUT_Size function.
--
-- function Family_To_LUT_Size (Family : TARGET_FAMILY_TYPE) return integer is
-- begin
--
-- --coverage off
--
-- if (Family = SPARTAN3) or (Family = SPARTAN3E) or (Family = SPARTAN3A) or
-- (Family = SPARTAN3AN) or (Family = SPARTAN3Adsp) or (Family = VIRTEX4) then
-- return 4;
-- end if;
--
-- return 6;
--
-- --coverage on
--
-- end function Family_To_LUT_Size;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
--coverage off
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
--coverage on
end function log2;
-------------------------------------------------------------------------------
end package body axi_bram_ctrl_funcs;
| bsd-2-clause |
pkerling/ethernet_mac_test | ethernet_mac_test_tb.vhd | 1 | 4838 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ethernet_mac;
use ethernet_mac.framing_common.all;
use ethernet_mac.crc32.all;
entity ethernet_mac_test_tb is
end entity;
architecture behavioral of ethernet_mac_test_tb is
alias logic_vector_t is std_logic_vector;
--Inputs
signal clock_125_i : std_ulogic := '0';
signal mii_tx_clk_i : std_ulogic := '0';
signal mii_rx_clk_i : std_ulogic := '0';
signal mii_rx_er_i : std_ulogic := '0';
signal mii_rx_dv_i : std_ulogic := '0';
signal mii_rxd_i : logic_vector_t(7 downto 0) := (others => '0');
--BiDirs
signal mdio_io : std_ulogic;
--Outputs
signal phy_reset_o : std_ulogic;
signal mdc_o : std_ulogic;
signal mii_tx_er_o : std_ulogic;
signal mii_tx_en_o : std_ulogic;
signal mii_txd_o : logic_vector_t(7 downto 0);
signal gmii_gtx_clk_o : std_ulogic;
signal led_o : logic_vector_t(3 downto 0);
signal user_led_o : std_ulogic;
-- Clock period definitions
constant clock_125_i_period : time := 8 ns;
constant mii_tx_clk_i_period : time := 40 ns;
constant mii_rx_clk_i_period : time := 40 ns;
constant mii_rx_setup : time := 2 ns;
constant mii_rx_hold : time := 0 ns;
constant SPEED_10100 : boolean := FALSE;
type t_memory is array (natural range <>) of logic_vector_t(7 downto 0);
-- ICMP Ping Request
constant test_packet : t_memory := (
x"FF", x"FF", x"FF", x"FF", x"FF", x"FF",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"08", x"00",
x"45", x"00", x"00", x"54", x"c0", x"04", x"40", x"00", x"40",
x"01", x"f5", x"4c",
x"c0", x"a8", x"01", x"05",
x"c0", x"a8", x"01", x"01",
x"08", x"00",
x"95", x"80",
x"0c", x"4f", x"00", x"01",
x"b6", x"c4", x"7d", x"55", x"00", x"00", x"00", x"00",
x"5f", x"42", x"04", x"00", x"00", x"00", x"00", x"00",
x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b",
x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28",
x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35",
x"36", x"37"
);
begin
-- Instantiate the Unit Under Test (UUT)
uut : entity work.ethernet_mac_test port map(
clock_125_i => clock_125_i,
phy_reset_o => phy_reset_o,
mdc_o => mdc_o,
mdio_io => mdio_io,
mii_tx_clk_i => mii_tx_clk_i,
mii_tx_er_o => mii_tx_er_o,
mii_tx_en_o => mii_tx_en_o,
mii_txd_o => mii_txd_o,
mii_rx_clk_i => mii_rx_clk_i,
mii_rx_er_i => mii_rx_er_i,
mii_rx_dv_i => mii_rx_dv_i,
mii_rxd_i => mii_rxd_i,
gmii_gtx_clk_o => gmii_gtx_clk_o,
led_o => led_o,
user_led_o => user_led_o
);
-- Clock process definitions
clock_125_i_process : process
begin
clock_125_i <= '0';
wait for clock_125_i_period / 2;
clock_125_i <= '1';
wait for clock_125_i_period / 2;
end process;
mii_tx_clk_i_process : process
begin
mii_tx_clk_i <= '0';
wait for mii_tx_clk_i_period / 2;
mii_tx_clk_i <= '1';
wait for mii_tx_clk_i_period / 2;
end process;
-- Stimulus process
stim_proc : process is
procedure mii_put1(
-- lolisim
-- crashes if (others => '0') is used instead of "00000000"
data : in logic_vector_t(7 downto 0) := "00000000";
dv : in std_ulogic := '1';
er : in std_ulogic := '0') is
begin
mii_rx_clk_i <= '0';
mii_rx_dv_i <= dv;
mii_rx_er_i <= er;
mii_rxd_i <= data;
wait for mii_rx_clk_i_period / 2;
mii_rx_clk_i <= '1';
wait for mii_rx_clk_i_period / 2;
end procedure;
procedure mii_put(
data : in logic_vector_t(7 downto 0) := "00000000";
dv : in std_ulogic := '1';
er : in std_ulogic := '0') is
begin
if SPEED_10100 = TRUE then
mii_put1("0000" & data(3 downto 0), dv, er);
mii_put1("0000" & data(7 downto 4), dv, er);
else
mii_put1(data, dv, er);
end if;
end procedure;
procedure mii_toggle is
begin
mii_put(dv => '0', er => '0', data => open);
end procedure;
variable fcs : t_crc32;
begin
wait until phy_reset_o = '1';
wait for clock_125_i_period * 1100;
while TRUE loop
for i in 0 to 10 loop
mii_toggle;
end loop;
mii_put(logic_vector_t(START_FRAME_DELIMITER_DATA));
fcs := (others => '1');
for j in test_packet'range loop
mii_put(test_packet(j));
fcs := update_crc32(fcs, std_ulogic_vector(test_packet(j)));
end loop;
-- for j in 1 to 1000 loop
-- mii_put(x"23");
-- end loop;
for b in 0 to 3 loop
mii_put(logic_vector_t(fcs_output_byte(fcs, b)));
end loop;
while TRUE loop
mii_toggle;
end loop;
end loop;
wait;
end process;
end architecture;
| bsd-3-clause |
schelleg/PYNQ | boards/ip/dvi2rgb_v1_7/src/GlitchFilter.vhd | 15 | 3919 | -------------------------------------------------------------------------------
--
-- File: GlitchFilter.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module filters any pulses on sIn lasting less than the number of
-- periods specified in kNoOfPeriodsToFilter. The output sOut will be
-- delayed by kNoOfPeriodsToFilter cycles, but glitch-free.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GlitchFilter is
Generic (
kNoOfPeriodsToFilter : natural);
Port (
SampleClk : in STD_LOGIC;
sIn : in STD_LOGIC;
sOut : out STD_LOGIC;
sRst : in STD_LOGIC);
end GlitchFilter;
architecture Behavioral of GlitchFilter is
signal cntPeriods : natural range 0 to kNoOfPeriodsToFilter - 1 := kNoOfPeriodsToFilter - 1;
signal sIn_q : std_logic;
begin
Bypass: if kNoOfPeriodsToFilter = 0 generate
sOut <= sIn;
end generate Bypass;
Filter: if kNoOfPeriodsToFilter > 0 generate
process (SampleClk)
begin
if Rising_Edge(SampleClk) then
sIn_q <= sIn;
if (cntPeriods = 0) then
sOut <= sIn_q;
end if;
end if;
end process;
PeriodCounter: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sIn_q /= sIn or sRst = '1') then --edge detected
cntPeriods <= kNoOfPeriodsToFilter - 1; --reset counter
elsif (cntPeriods /= 0) then
cntPeriods <= cntPeriods - 1; --count down
end if;
end if;
end process PeriodCounter;
end generate Filter;
end Behavioral;
| bsd-3-clause |
schelleg/PYNQ | boards/ip/audio_direct_1.1/src/pdm_ser.vhd | 8 | 4223 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:56 01/31/2014
-- Design Name:
-- Module Name: pdm_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pdm_ser is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_i : in std_logic_vector(15 downto 0);
-- PWM
pwm_audio_o : out std_logic;
pwm_audio_t : out std_logic;
pwm_audio_i : in std_logic
--pwm_sdaudio_o : out std_logic
);
end pdm_ser;
architecture Behavioral of pdm_ser is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal cnt_clk : integer range 0 to 127 := 0;
signal clk_int, clk_intt : std_logic := '0';
signal pdm_clk_rising, pdm_clk_falling : std_logic;
signal pdm_s_tmp : std_logic_vector((C_NR_OF_BITS-1) downto 0);
signal cnt_bits : integer range 0 to 31 := 0;
signal pwm_int : std_logic;
signal done_int : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- enable audio
--pwm_sdaudio_o <= '1';
-- counter for the number of sampled bits
CNT: process(clk_i) begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
cnt_bits <= 0;
else
cnt_bits <= cnt_bits + 1;
end if;
end if;
end if;
end process CNT;
-- done gen
process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
done_o <= '1';
end if;
else
done_o <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------
-- Serializer
------------------------------------------------------------------------
SHFT_OUT: process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-2) then -- end of deserialization
pdm_s_tmp <= data_i;
else
pdm_s_tmp <= pdm_s_tmp(C_NR_OF_BITS-2 downto 0) & '0';
end if;
end if;
end if;
end process SHFT_OUT;
-- output the serial pdm data
pwm_audio_o <= '0';
pwm_audio_t <= --clk_int when en_i = '0' else
'0' when pdm_s_tmp(C_NR_OF_BITS-1) = '0' and en_i = '1' else '1';
------------------------------------------------------------------------
-- slave clock generator
------------------------------------------------------------------------
CLK_CNT: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' or cnt_clk = ((C_SYS_CLK_FREQ_MHZ/(C_PDM_FREQ_MHZ*2))-1) then
cnt_clk <= 0;
clk_int <= not clk_int;
else
cnt_clk <= cnt_clk + 1;
end if;
clk_intt <= clk_int;
end if;
end process CLK_CNT;
pdm_clk_rising <= '1' when clk_int = '1' and clk_intt = '0' else '0';
--pdm_clk_falling <= '1' when cnt_clk = ((clk_div/2)-1) else '0';
end Behavioral;
| bsd-3-clause |
schelleg/PYNQ | boards/ip/audio_direct_1.1/src/pdm_rxtx.vhd | 8 | 10747 | -------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : pdm_rxtx.vhd
-- MODULE NAME : PDM Tranceiver
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-01-30 MihaitaN Created
-------------------------------------------------------------------------------
-- KEYWORDS : PDM
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity pdm_rxtx is
port (
-- Global signals
CLK_I : in std_logic;
RST_I : in std_logic;
-- Control signals
START_TRANSACTION_I : in std_logic;
STOP_TRANSACTION_I : in std_logic;
RNW_I : in std_logic;
-- Tx FIFO Control signals
TX_FIFO_RST_I : in std_logic;
TX_FIFO_D_I : in std_logic_vector(15 downto 0);
TX_FIFO_WR_EN_I : in std_logic;
-- Rx FIFO Control signals
RX_FIFO_RST_I : in std_logic;
RX_FIFO_D_O : out std_logic_vector(15 downto 0);
RX_FIFO_RD_EN_I : in std_logic;
-- Tx FIFO Flags
TX_FIFO_EMPTY_O : out std_logic;
TX_FIFO_FULL_O : out std_logic;
-- Rx FIFO Flags
RX_FIFO_EMPTY_O : out std_logic;
RX_FIFO_FULL_O : out std_logic;
PDM_M_CLK_O : out std_logic;
PDM_M_DATA_I : in std_logic;
PDM_LRSEL_O : out std_logic;
PWM_AUDIO_O : out std_logic;
PWM_AUDIO_T : out std_logic;
PWM_AUDIO_I : in std_logic
);
end pdm_rxtx;
architecture Behavioral of pdm_rxtx is
------------------------------------------------------------------------
-- Type Declarations
------------------------------------------------------------------------
type States is (sIdle, sCheckRnw, sRead, sWrite);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal CState, NState : States := sIdle;
signal StartTransaction : std_logic;
signal StopTransaction : std_logic;
signal RxEn : std_logic;
signal TxEn : std_logic;
signal Rnw : std_logic;
signal RxFifoDataIn : std_logic_vector(15 downto 0);
signal RxFifoWrEn : std_logic;
signal TxFifoDataOut : std_logic_vector(15 downto 0);
signal TxFifoRdEn : std_logic;
signal RxFifoRdEn : std_logic;
signal RxFifoRdEn_dly : std_logic;
signal TxFifoWrEn : std_logic;
signal TxFifoWrEn_dly : std_logic;
signal TxFifoEmpty : std_logic;
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
-- deserializer
component pdm_des is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
pdm_m_clk_o : out std_logic;
pdm_m_data_i : in std_logic;
pdm_lrsel_o : out std_logic);
end component;
-- pdm serializer
component pdm_ser is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_i : in std_logic_vector(15 downto 0);
pwm_audio_o : out std_logic;
pwm_audio_t : out std_logic;
pwm_audio_i : in std_logic);
--pwm_sdaudio_o : out std_logic);
end component;
-- the FIFO, used for Rx and Tx
component fifo_512
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Register all inputs of the FSM
------------------------------------------------------------------------
REG_IN: process(CLK_I)
begin
if rising_edge(CLK_I) then
StartTransaction <= START_TRANSACTION_I;
StopTransaction <= STOP_TRANSACTION_I;
Rnw <= RNW_I;
end if;
end process REG_IN;
------------------------------------------------------------------------
-- Register and generate pulse out of rd/wr enables
------------------------------------------------------------------------
RDWR_PULSE: process(CLK_I)
begin
if rising_edge(CLK_I) then
RxFifoRdEn_dly <= RX_FIFO_RD_EN_I;
TxFifoWrEn_dly <= TX_FIFO_WR_EN_I;
end if;
end process RDWR_PULSE;
RxFifoRdEn <= RX_FIFO_RD_EN_I and not RxFifoRdEn_dly;
TxFifoWrEn <= TX_FIFO_WR_EN_I and not TxFifoWrEn_dly;
------------------------------------------------------------------------
-- Deserializer
------------------------------------------------------------------------
Inst_Deserializer: pdm_des
generic map(
C_NR_OF_BITS => 16,
C_SYS_CLK_FREQ_MHZ => 100,
C_PDM_FREQ_MHZ => 3)
port map(
clk_i => CLK_I,
rst_i => RST_I,
en_i => RxEn,
done_o => RxFifoWrEn,
data_o => RxFifoDataIn,
pdm_m_clk_o => PDM_M_CLK_O,
pdm_m_data_i => PDM_M_DATA_I,
pdm_lrsel_o => PDM_LRSEL_O);
------------------------------------------------------------------------
-- Serializer
------------------------------------------------------------------------
Inst_Serializer: pdm_ser
generic map(
C_NR_OF_BITS => 16,
C_SYS_CLK_FREQ_MHZ => 100,
C_PDM_FREQ_MHZ => 3)
port map(
clk_i => CLK_I,
rst_i => RST_I,
en_i => TxEn,
done_o => TxFifoRdEn,
data_i => TxFifoDataOut,
pwm_audio_o => PWM_AUDIO_O,
pwm_audio_t => PWM_AUDIO_T,
pwm_audio_i => PWM_AUDIO_I);
------------------------------------------------------------------------
-- Instantiate the transmitter fifo
------------------------------------------------------------------------
Inst_PdmTxFifo: fifo_512
port map(
clk => CLK_I,
rst => TX_FIFO_RST_I,
din => TX_FIFO_D_I,
wr_en => TxFifoWrEn,
rd_en => TxFifoRdEn,
dout => TxFifoDataOut,
full => TX_FIFO_FULL_O,
empty => TxFifoEmpty);
TX_FIFO_EMPTY_O <= TxFifoEmpty;
------------------------------------------------------------------------
-- Instantiate the receiver fifo
------------------------------------------------------------------------
Inst_PdmRxFifo: fifo_512
port map(
clk => CLK_I,
rst => RX_FIFO_RST_I,
din => RxFifoDataIn,
wr_en => RxFifoWrEn,
rd_en => RxFifoRdEn,
dout => RX_FIFO_D_O,
full => RX_FIFO_FULL_O,
empty => RX_FIFO_EMPTY_O);
------------------------------------------------------------------------
-- Main FSM, register states, next state decode
------------------------------------------------------------------------
REG_STATES: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
CState <= sIdle;
else
CState <= NState;
end if;
end if;
end process REG_STATES;
FSM_TRANS: process(CState, StartTransaction, StopTransaction, Rnw, TxFifoEmpty)
begin
NState <= CState;
case CState is
when sIdle =>
if StartTransaction = '1' then
NState <= sCheckRnw;
end if;
when sCheckRnw =>
if Rnw = '1' then
NState <= sRead;
else
NState <= sWrite;
end if;
when sWrite =>
if TxFifoEmpty = '1' then
NSTate <= sIdle;
end if;
when sRead =>
if StopTransaction = '1' then
NState <= sIdle;
end if;
when others => NState <= sIdle;
end case;
end process FSM_TRANS;
------------------------------------------------------------------------
-- Assert transmit enable
------------------------------------------------------------------------
TXEN_PROC: process(CLK_I)
begin
if rising_edge(CLK_I) then
if CState = sWrite then
TxEn <= '1';
else
TxEn <= '0';
end if;
end if;
end process TXEN_PROC;
------------------------------------------------------------------------
-- Assert receive enable
------------------------------------------------------------------------
RXEN_PROC: process(CLK_I)
begin
if rising_edge(CLK_I) then
if CState = sRead then
RxEn <= '1';
else
RxEn <= '0';
end if;
end if;
end process RXEN_PROC;
end Behavioral;
| bsd-3-clause |
PyLCARS/PythonUberHDL | myHDL_DigLogicFundamentals/myHDL_BitOperations/pck_myhdl_010.vhd | 1 | 4349 | -- File: pck_myhdl_010.vhd
-- Generated by MyHDL 0.10
-- Date: Wed Aug 29 14:28:07 2018
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_010 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic;
function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned;
function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed;
end pck_myhdl_010;
package body pck_myhdl_010 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
end pck_myhdl_010;
| bsd-3-clause |
sonologic/gmzpu | roms/vhdl/header.vhdl | 1 | 3988 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
| bsd-3-clause |
sonologic/gmzpu | vhdl/ZetaIO/interrupt/test/pic_tb.vhdl | 2 | 13625 | ------------------------------------------------------------------------------
---- ----
---- gmzpu programmable interrupt controller (pic) testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the PIC ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: pic_TB ----
---- File name: pic_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.pic;
entity pic_TB is
end entity pic_TB;
architecture Behave of pic_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant DATA_WIDTH : natural:=16;
constant ADR_WIDTH : natural:=16;
constant N_BANKS : natural:=2;
component interrupt_controller is
generic(
-- address width (truncated to DATA_WIDTH)
ADR_WIDTH : natural:=4;
-- data bus width
DATA_WIDTH : natural:=32;
-- number of interrupt banks (each bank is DATA_WIDTH interrupt lines)
N_BANKS : natural:=2
);
port (
irq_o : out std_logic;
-- interrupt lines
int_i : in std_logic_vector((N_BANKS*DATA_WIDTH)-1 downto 0);
-- wishbone bus
rst_i : in std_logic;
clk_i : in std_logic;
wb_dat_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic;
wb_adr_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_err_o : out std_logic;
wb_lock_i : in std_logic;
wb_rty_o : out std_logic;
wb_sel_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_i : in std_logic;
wb_tga_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_tgc_i : in unsigned(DATA_WIDTH-1 downto 0); -- size correct?
wb_we_i : in std_logic
);
end component interrupt_controller;
type sample is record
-- inputs
int_i : std_logic_vector((N_BANKS*DATA_WIDTH)-1 downto 0);
rst_i : std_logic;
wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : unsigned(DATA_WIDTH-1 downto 0);
wb_adr_i : unsigned(ADR_WIDTH-1 downto 0);
wb_cyc_i : std_logic;
wb_lock_i : std_logic;
wb_sel_i : std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_i : std_logic;
wb_tga_i : unsigned(ADR_WIDTH-1 downto 0);
wb_tgc_i : unsigned(DATA_WIDTH-1 downto 0);
wb_we_i : std_logic;
-- outputs
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- int_i rst wb_dat_i wb_tgd_i wb_adr_i cyc lock wb_sel_i stb wb_tga_i wb_tgc_i we
-- reset
(X"00000000", '1', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '1', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- write IMR0 <= X"FFFF"
(X"00000000", '0', X"FFFF", X"0000", X"0001", '1', '0', X"0000", '1', X"0000", X"0000", '1'),
(X"00000000", '0', X"FFFF", X"0000", X"0001", '1', '0', X"0000", '1', X"0000", X"0000", '1'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read IMR0 (X"FFFF")
(X"00000000", '0', X"0000", X"0000", X"0001", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0001", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read IMR1 (X"0000")
(X"00000000", '0', X"0000", X"0000", X"0005", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0005", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- raise interrupt in bank 0
(X"00000100", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read ICR0 (X"0100")
-- int_i rst wb_dat_i wb_tgd_i wb_adr_i cyc lock wb_sel_i stb wb_tga_i wb_tgc_i we
(X"00000000", '0', X"0000", X"0000", X"0000", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read ICR1 (X"0000")
(X"00000000", '0', X"0000", X"0000", X"0004", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0004", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- reset ICR0 (X"0000")
(X"00000000", '0', X"0000", X"0000", X"0000", '1', '0', X"0000", '1', X"0000", X"0000", '1'),
(X"00000000", '0', X"0000", X"0000", X"0000", '1', '0', X"0000", '1', X"0000", X"0000", '1'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- raise interrupt in bank 1
(X"00200000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read ICR1 (X"0020"), pipelined mode
(X"00000000", '0', X"0000", X"0000", X"0004", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0004", '1', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- term
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0')
);
signal clk : std_logic;
signal irq_o : std_logic;
-- interrupt lines
signal int_i : std_logic_vector((N_BANKS*DATA_WIDTH)-1 downto 0);
-- wishbone bus
signal rst_i : std_logic;
signal clk_i : std_logic;
signal wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgd_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgd_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_ack_o : std_logic;
signal wb_adr_i : unsigned(ADR_WIDTH-1 downto 0);
signal wb_cyc_i : std_logic;
signal wb_stall_o : std_logic;
signal wb_err_o : std_logic;
signal wb_lock_i : std_logic;
signal wb_rty_o : std_logic;
signal wb_sel_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal wb_stb_i : std_logic;
signal wb_tga_i : unsigned(ADR_WIDTH-1 downto 0);
signal wb_tgc_i : unsigned(DATA_WIDTH-1 downto 0); -- size correct?
signal wb_we_i : std_logic;
begin
pic : interrupt_controller
generic map(
DATA_WIDTH => DATA_WIDTH, N_BANKS => N_BANKS, ADR_WIDTH => ADR_WIDTH
)
port map(irq_o => irq_o, int_i => int_i, rst_i => rst_i, clk_i => clk,
wb_dat_o => wb_dat_o, wb_dat_i => wb_dat_i, wb_tgd_o => wb_tgd_o,
wb_tgd_i => wb_tgd_i, wb_ack_o => wb_ack_o, wb_adr_i => wb_adr_i,
wb_cyc_i => wb_cyc_i, wb_stall_o => wb_stall_o, wb_err_o => wb_err_o,
wb_lock_i => wb_lock_i, wb_rty_o => wb_rty_o, wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i, wb_tga_i => wb_tga_i, wb_tgc_i => wb_tgc_i,
wb_we_i => wb_we_i);
process
variable cycle_count : integer:=0;
begin
for i in test_data'range loop
clk <= '0';
wait for CLK_S_PER;
int_i <= test_data(i).int_i;
rst_i <= test_data(i).rst_i;
wb_dat_i <= test_data(i).wb_dat_i;
wb_tgd_i <= test_data(i).wb_tgd_i;
wb_adr_i <= test_data(i).wb_adr_i;
wb_cyc_i <= test_data(i).wb_cyc_i;
wb_lock_i <= test_data(i).wb_lock_i;
wb_sel_i <= test_data(i).wb_sel_i;
wb_stb_i <= test_data(i).wb_stb_i;
wb_tga_i <= test_data(i).wb_tga_i;
wb_tgc_i <= test_data(i).wb_tgc_i;
wb_we_i <= test_data(i).wb_we_i;
clk <= '1';
wait for CLK_S_PER;
--assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity failure;
--assert (icr_o = test_data(i).icr_o) report "icr_o output mismatch" severity failure;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave;
| bsd-3-clause |
sonologic/gmzpu | vhdl/testbenches/zpu_wishbone_intercon.vhdl | 1 | 4823 | ------------------------------------------------------------------------------
---- ----
---- Testbench for the ZPU Wishbone bridge ----
---- ----
---- Description: ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Koen Martens, gmc sonologic.nl ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c)
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit:
---- File name:
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA:
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools:
---- Text editor:
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.wishbone.all;
entity zpu_wishbone_intercon_tb is
end entity zpu_wishbone_intercon_tb;
architecture Behave of zpu_wishbone_intercon_tb is
constant ADR_MSB : natural:=31;
constant ADR_LSB : natural:=0;
constant PAGE_BIT : natural:=4;
constant NUNITS : natural:=8;
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
-- testbench
signal break : std_logic:='0';
signal clk : std_logic;
-- wishbone
signal wb_rst : std_logic;
signal wb_stb : std_logic;
signal wb_cyc : std_logic;
signal wb_adr_i : std_logic_vector(ADR_MSB downto ADR_LSB);
signal wb_adr_o : std_logic_vector(PAGE_BIT-1 downto 0);
signal stb : std_logic_vector(NUNITS-1 downto 0);
begin
INTERCON : zpu_wishbone_intercon
generic map(
ADR_MSB => ADR_MSB,
ADR_LSB => ADR_LSB,
PAGE_BIT => PAGE_BIT,
NUNITS => NUNITS
)
port map(
rst_i => wb_rst,
stb_i => wb_stb,
cyc_i => wb_cyc,
adr_i => wb_adr_i,
adr_o => wb_adr_o,
stb_o => stb
);
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
if break='1' then
-- print("* Break asserted, end of test");
wait;
end if;
end process do_clock;
do_sim:
process
begin
wb_rst <= '0';
wb_stb <= '0';
wb_cyc <= '0';
wait for 1 us;
wb_adr_i <= std_logic_vector(to_unsigned(10, 32));
wb_stb <= '1';
wb_cyc <= '1';
wait for 1 us;
wb_stb <= '0';
wait for 1 us;
wb_cyc <= '0';
wait for 1 us;
wb_adr_i <= std_logic_vector(to_unsigned(54, 32));
wb_stb <= '1';
wb_cyc <= '1';
wait for 1 us;
wb_stb <= '0';
wait for 1 us;
wb_cyc <= '0';
wait for 1 us;
end process do_sim;
end architecture Behave; -- Entity: zpu_wishbone_bridge_tb
| bsd-3-clause |
sonologic/gmzpu | vhdl/ZetaIO/interrupt/interrupt_pkg.vhdl | 1 | 5839 | ------------------------------------------------------------------------------
---- ----
---- Programmable Interrupt Controller (PIC) ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- gmZPU interrupt controller. Parametrised design to create ----
---- a PIC with a number of N_BANKS registers. Each bank ----
---- has the full set of ICR, IMR, ITR and IER registers for ----
---- DATA_WIDTH interrupt lines. ----
---- ----
---- Author: ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: pic (package) ----
---- File name: interrupt_pkg.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: gmzpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: N/A ----
---- Language: VHDL ----
---- Wishbone: Yes ----
---- Synthesis tools: ModelSim ----
---- Simulation tools: ModelSim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package pic is
component interrupt_line is
port (
clk_i : in std_logic;
int_i : in std_logic;
irq_o : out std_logic;
icr_o : out std_logic;
icr_i : in std_logic;
imr_i : in std_logic;
ier_i : in std_logic;
itr_i : in std_logic;
we_i : in std_logic
);
end component interrupt_line;
component interrupt_regs is
generic (
DATA_WIDTH : natural:=32
);
port (
rst_i : in std_logic;
clk_i : in std_logic;
int_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
adr_i : in unsigned(1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
we_i : in std_logic;
en_i : in std_logic;
irq_o : out std_logic;
ready_o : out std_logic
);
end component interrupt_regs;
component interrupt_controller is
generic(
-- address width (truncated to DATA_WIDTH)
ADR_WIDTH : natural:=4;
-- data bus width
DATA_WIDTH : natural:=32;
-- number of interrupt banks (each bank is DATA_WIDTH interrupt lines)
N_BANKS : natural:=2
);
port (
irq_o : out std_logic;
-- interrupt lines
int_i : in std_logic_vector((N_BANKS*DATA_WIDTH)-1 downto 0);
-- wishbone bus
rst_i : in std_logic;
clk_i : in std_logic;
wb_dat_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic;
wb_adr_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_err_o : out std_logic;
wb_lock_i : in std_logic;
wb_rty_o : out std_logic;
wb_sel_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_i : in std_logic;
wb_tga_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_tgc_i : in unsigned(DATA_WIDTH-1 downto 0); -- size correct?
wb_we_i : in std_logic
);
end component interrupt_controller;
end package pic;
| bsd-3-clause |
sonologic/gmzpu | vhdl/zpu_small.vhdl | 1 | 22984 | ------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(OPCODE_W-1 downto 0); -- Decoded
signal opcode_r : unsigned(OPCODE_W-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(OPCODE_W-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode := to_01( b_i(31 downto 24));
when 1 =>
topcode := to_01( b_i(23 downto 16));
when 2 =>
topcode := to_01( b_i(15 downto 8));
when others => -- 3
topcode := to_01( b_i(7 downto 0));
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
a_addr_r <= sp_r;
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
| bsd-3-clause |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/addr_gen.vhd | 6 | 4409 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| bsd-3-clause |
VectorBlox/risc-v | ip/orca/hdl/axi_master.vhd | 1 | 10331 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.utils.all;
use work.rv_components.all;
use work.constants_pkg.all;
-------------------------------------------------------------------------------
-- AXI master from OIMM master.
-------------------------------------------------------------------------------
entity axi_master is
generic (
ADDRESS_WIDTH : positive;
DATA_WIDTH : positive;
ID_WIDTH : positive;
LOG2_BURSTLENGTH : positive;
MAX_OUTSTANDING_REQUESTS : natural;
REQUEST_REGISTER : request_register_type;
RETURN_REGISTER : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
aresetn : in std_logic;
master_idle : out std_logic;
--ORCA-internal memory-mapped slave
oimm_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
oimm_burstlength_minus1 : in std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
oimm_byteenable : in std_logic_vector((DATA_WIDTH/8)-1 downto 0);
oimm_requestvalid : in std_logic;
oimm_readnotwrite : in std_logic;
oimm_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
oimm_writelast : in std_logic;
oimm_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
oimm_readdatavalid : out std_logic;
oimm_waitrequest : out std_logic;
--AXI memory-mapped master
AWID : out std_logic_vector(ID_WIDTH-1 downto 0);
AWADDR : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
AWLEN : out std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
AWSIZE : out std_logic_vector(2 downto 0);
AWBURST : out std_logic_vector(1 downto 0);
AWLOCK : out std_logic_vector(1 downto 0);
AWCACHE : out std_logic_vector(3 downto 0);
AWPROT : out std_logic_vector(2 downto 0);
AWVALID : out std_logic;
AWREADY : in std_logic;
WID : out std_logic_vector(ID_WIDTH-1 downto 0);
WSTRB : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
WVALID : out std_logic;
WLAST : out std_logic;
WDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
WREADY : in std_logic;
BID : in std_logic_vector(ID_WIDTH-1 downto 0);
BRESP : in std_logic_vector(1 downto 0);
BVALID : in std_logic;
BREADY : out std_logic;
ARID : out std_logic_vector(ID_WIDTH-1 downto 0);
ARADDR : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
ARLEN : out std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
ARSIZE : out std_logic_vector(2 downto 0);
ARBURST : out std_logic_vector(1 downto 0);
ARLOCK : out std_logic_vector(1 downto 0);
ARCACHE : out std_logic_vector(3 downto 0);
ARPROT : out std_logic_vector(2 downto 0);
ARVALID : out std_logic;
ARREADY : in std_logic;
RID : in std_logic_vector(ID_WIDTH-1 downto 0);
RDATA : in std_logic_vector(DATA_WIDTH-1 downto 0);
RRESP : in std_logic_vector(1 downto 0);
RLAST : in std_logic;
RVALID : in std_logic;
RREADY : out std_logic
);
end entity axi_master;
architecture rtl of axi_master is
constant BURST_INCR : std_logic_vector(1 downto 0) := "01";
constant CACHE_VAL : std_logic_vector(3 downto 0) := "0011";
constant PROT_VAL : std_logic_vector(2 downto 0) := "000";
constant LOCK_VAL : std_logic_vector(1 downto 0) := "00";
signal register_idle : std_logic;
signal throttler_idle : std_logic;
signal registered_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal registered_oimm_burstlength_minus1 : std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
signal registered_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal registered_oimm_requestvalid : std_logic;
signal registered_oimm_readnotwrite : std_logic;
signal registered_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal registered_oimm_writelast : std_logic;
signal unregistered_oimm_readdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal unregistered_oimm_readdatavalid : std_logic;
signal unregistered_oimm_waitrequest : std_logic;
signal unthrottled_oimm_readcomplete : std_logic;
signal unthrottled_oimm_writecomplete : std_logic;
signal unthrottled_oimm_waitrequest : std_logic;
signal throttled_oimm_requestvalid : std_logic;
signal AWVALID_signal : std_logic;
signal WVALID_signal : std_logic;
signal aw_sending : std_logic;
signal aw_sent : std_logic;
signal w_sending : std_logic;
signal w_sent : std_logic;
begin
master_idle <= register_idle and throttler_idle;
-----------------------------------------------------------------------------
-- Optional OIMM register
-----------------------------------------------------------------------------
optional_oimm_register : oimm_register
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH,
LOG2_BURSTLENGTH => LOG2_BURSTLENGTH,
REQUEST_REGISTER => REQUEST_REGISTER,
RETURN_REGISTER => RETURN_REGISTER
)
port map (
clk => clk,
reset => reset,
register_idle => register_idle,
--ORCA-internal memory-mapped slave
slave_oimm_address => oimm_address,
slave_oimm_burstlength_minus1 => oimm_burstlength_minus1,
slave_oimm_byteenable => oimm_byteenable,
slave_oimm_requestvalid => oimm_requestvalid,
slave_oimm_readnotwrite => oimm_readnotwrite,
slave_oimm_writedata => oimm_writedata,
slave_oimm_writelast => oimm_writelast,
slave_oimm_readdata => oimm_readdata,
slave_oimm_readdatavalid => oimm_readdatavalid,
slave_oimm_waitrequest => oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_address => registered_oimm_address,
master_oimm_burstlength_minus1 => registered_oimm_burstlength_minus1,
master_oimm_byteenable => registered_oimm_byteenable,
master_oimm_requestvalid => registered_oimm_requestvalid,
master_oimm_readnotwrite => registered_oimm_readnotwrite,
master_oimm_writedata => registered_oimm_writedata,
master_oimm_writelast => registered_oimm_writelast,
master_oimm_readdata => unregistered_oimm_readdata,
master_oimm_readdatavalid => unregistered_oimm_readdatavalid,
master_oimm_waitrequest => unregistered_oimm_waitrequest
);
-----------------------------------------------------------------------------
-- Optional OIMM request throttler
-----------------------------------------------------------------------------
request_throttler : oimm_throttler
generic map (
MAX_OUTSTANDING_REQUESTS => MAX_OUTSTANDING_REQUESTS,
READ_WRITE_FENCE => true --AXI lacks intra-channel ordering
)
port map (
clk => clk,
reset => reset,
throttler_idle => throttler_idle,
--ORCA-internal memory-mapped slave
slave_oimm_requestvalid => registered_oimm_requestvalid,
slave_oimm_readnotwrite => registered_oimm_readnotwrite,
slave_oimm_writelast => registered_oimm_writelast,
slave_oimm_waitrequest => unregistered_oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_requestvalid => throttled_oimm_requestvalid,
master_oimm_readcomplete => unthrottled_oimm_readcomplete,
master_oimm_writecomplete => unthrottled_oimm_writecomplete,
master_oimm_waitrequest => unthrottled_oimm_waitrequest
);
-----------------------------------------------------------------------------
-- OIMM to AXI logic
-----------------------------------------------------------------------------
unthrottled_oimm_readcomplete <= RVALID and RLAST;
unthrottled_oimm_writecomplete <= BVALID;
unregistered_oimm_readdata <= RDATA;
unregistered_oimm_readdatavalid <= RVALID;
unthrottled_oimm_waitrequest <= (not ARREADY) when registered_oimm_readnotwrite = '1' else
(((not AWREADY) and (not aw_sent) and (registered_oimm_writelast or w_sent)) or
((not WREADY) and (not w_sent)));
AWID <= (others => '0');
AWADDR <= registered_oimm_address;
AWLEN <= registered_oimm_burstlength_minus1;
AWSIZE <= std_logic_vector(to_unsigned(log2(DATA_WIDTH/8), 3));
AWBURST <= BURST_INCR;
AWLOCK <= LOCK_VAL;
AWCACHE <= CACHE_VAL;
AWPROT <= PROT_VAL;
AWVALID_signal <= (throttled_oimm_requestvalid and (not registered_oimm_readnotwrite)) and (not aw_sent);
AWVALID <= AWVALID_signal;
WID <= (others => '0');
WSTRB <= registered_oimm_byteenable;
WVALID_signal <= (throttled_oimm_requestvalid and (not registered_oimm_readnotwrite)) and (not w_sent);
WVALID <= WVALID_signal;
WLAST <= registered_oimm_writelast;
WDATA <= registered_oimm_writedata;
BREADY <= '1';
ARID <= (others => '0');
ARADDR <= registered_oimm_address;
ARLEN <= registered_oimm_burstlength_minus1;
ARSIZE <= std_logic_vector(to_unsigned(log2(DATA_WIDTH/8), 3));
ARBURST <= BURST_INCR;
ARLOCK <= LOCK_VAL;
ARCACHE <= CACHE_VAL;
ARPROT <= PROT_VAL;
ARVALID <= registered_oimm_readnotwrite and throttled_oimm_requestvalid;
RREADY <= '1';
aw_sending <= AWVALID_signal and AWREADY;
w_sending <= WVALID_signal and registered_oimm_writelast and WREADY;
process (clk) is
begin
if rising_edge(clk) then
if aw_sending = '1' then
if w_sent = '1' or w_sending = '1' then
aw_sent <= '0';
w_sent <= '0';
else
aw_sent <= '1';
end if;
end if;
if w_sending = '1' then
if aw_sent = '1' or aw_sending = '1' then
w_sent <= '0';
aw_sent <= '0';
else
w_sent <= '1';
end if;
end if;
if aresetn = '0' then
aw_sent <= '0';
w_sent <= '0';
end if;
end if;
end process;
end architecture;
| bsd-3-clause |
VectorBlox/risc-v | ip/idram/src/tdp_ram_behav.vhd | 1 | 2591 | -- tdp_ram_behav.vhd
-- Copyright (C) 2017 VectorBlox Computing, Inc.
--
-- Behavioural implementation of synchronous true dual-port RAM.
-- Can either be read first or write first.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.idram_utils.all;
entity tdp_ram_behav is
generic (
RAM_DEPTH : integer := 1024;
RAM_WIDTH : integer := 8;
WRITE_FIRST : boolean := false
);
port
(
address_a : in std_logic_vector(log2(RAM_DEPTH)-1 downto 0);
address_b : in std_logic_vector(log2(RAM_DEPTH)-1 downto 0);
clk : in std_logic;
data_a : in std_logic_vector(RAM_WIDTH-1 downto 0);
data_b : in std_logic_vector(RAM_WIDTH-1 downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
en_a : in std_logic;
en_b : in std_logic;
readdata_a : out std_logic_vector(RAM_WIDTH-1 downto 0);
readdata_b : out std_logic_vector(RAM_WIDTH-1 downto 0)
);
end tdp_ram_behav;
architecture rtl of tdp_ram_behav is
type ram_type is array (RAM_DEPTH-1 downto 0) of std_logic_vector(RAM_WIDTH-1 downto 0);
shared variable ram : ram_type;
begin
read_first_gen : if not WRITE_FIRST generate
process (clk)
begin
if rising_edge(clk) then
if en_a = '1' then
readdata_a <= ram(to_integer(unsigned(address_a)));
if wren_a = '1' then
ram(to_integer(unsigned(address_a))) := data_a;
end if;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if en_b = '1' then
readdata_b <= ram(to_integer(unsigned(address_b)));
if wren_b = '1' then
ram(to_integer(unsigned(address_b))) := data_b;
end if;
end if;
end if;
end process;
end generate read_first_gen;
write_first_gen : if WRITE_FIRST generate
process (clk)
begin
if rising_edge(clk) then
if en_a = '1' then
if wren_a = '1' then
ram(to_integer(unsigned(address_a))) := data_a;
end if;
readdata_a <= ram(to_integer(unsigned(address_a)));
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if en_b = '1' then
if wren_b = '1' then
ram(to_integer(unsigned(address_b))) := data_b;
end if;
readdata_b <= ram(to_integer(unsigned(address_b)));
end if;
end if;
end process;
end generate write_first_gen;
end rtl;
| bsd-3-clause |
shvorin/pcie-emu | examples/loopback/emu_top_cfg.vhd | 1 | 308 | -- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
configuration emu_top_cfg of emu_top256 is
for emu_top256
for app : ast_io
use entity work.wrap_emu;
end for;
end for;
end;
| bsd-3-clause |
alvieboy/xtc-base | clkgen.vhd | 1 | 4479 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
vgaclk: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_ulogic;
signal dcmclock: std_ulogic;
signal rst1_q: std_logic := '1';
signal rst2_q: std_logic := '1';
signal clkout_i: std_ulogic;
signal clkin_i: std_ulogic;
signal clkfb: std_ulogic;
signal clk0: std_ulogic;
signal clk1: std_ulogic;
signal clk2: std_ulogic;
signal clk2x: std_ulogic;
signal clkin_i_2: std_logic;
begin
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, clkout_i, rstin)
begin
if dcmlocked='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => clk0,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> dcmclock,
O=> clkfb
);
clk1_inst: BUFG port map ( I => clk1, O => clkout1 );
clk2_inst: BUFG port map ( I => clk2, O => clkout2 );
clk3_inst: BUFG port map ( I => clk2x, O => vgaclk );
pll_base_inst : PLL_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,--30 -- 20,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,--10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 10,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 38, --31,--38,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 31.250,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map
-- Output clocks
(CLKFBOUT => dcmclock,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
CLKOUT3 => clk2x,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dcmlocked,
RST => '0',
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0'
);
end behave;
| bsd-3-clause |
Shadytel/Computer | Emulator/FPGA/InputController.vhd | 1 | 5303 | ----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 21:31:08 09/24/2011
-- Design Name:
-- Module Name: InputController - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
library work;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InputController is
Port(
clk: in std_logic;
RAMwrite: out std_logic;
RAMread: out std_logic;
MicroCodeCLK: out std_logic;
MicroCodeEN: out std_logic;
Data: out std_logic_vector(11 downto 0);
Addr: out std_logic_vector(11 downto 0);
outNibble: out std_logic_vector(3 downto 0);
sw: in std_logic_vector(7 downto 0);
RAWbtn : in std_logic_vector(3 downto 0)
);
end InputController;
--Sw7 High= Run, Low=Step 1 microcode on btn0
--Sw6 High=AllowRun , Low=Edit
--Sw5 Nibble Select High= Upper, Low=Middle
--Sw4 Nibble Select High= other, Low=Lower
--Sw3:0 1 Nibble
--Btn 3: Stores Nibble
--Btn 2: Stores Word
--Btn 1: Increments memory counter
--Btn 0: Run 1 step
architecture Behavioral of InputController is
signal cnt : std_logic_vector(24 downto 0) := "0000000000000000000000000";
signal word: std_logic_vector(11 downto 0) := "000000000000";
signal loc: std_logic_vector(11 downto 0) := "000000000000";
signal btn: std_logic_vector(3 downto 0) := "0000";
signal step: std_logic :='0';
signal cooldown: std_logic :='0';
signal cooldown2: std_logic :='0';
signal cooldown3: std_logic :='0';
signal cooldown4: std_logic :='0';
alias running is sw(7);
--alias step is btn(0);
alias nibble is sw(3 downto 0);
component Debouncer
Port (
CLK : in STD_LOGIC;
x : in STD_LOGIC;
DBx : out STD_LOGIC
);
end component;
begin
db1: Debouncer
port map (
CLK => CLK, -- Clock
X => RAWbtn(0),
DBx => btn(0)
);
db2: Debouncer port map (
CLK => CLK, -- Clock
X => RAWbtn(1),
DBx => btn(1)
);
db3: Debouncer port map (
CLK => CLK, -- Clock
X => RAWbtn(2),
DBx => btn(2)
);
db4: Debouncer port map (
CLK => CLK, -- Clock
X => RAWbtn(3),
DBx => btn(3)
);
step <= btn(0);
-- process(cnt)
-- begin
-- if(cnt(24 downto 23) = "00") then
-- Data <= "ZZZZZZZZZZZZ";
-- Addr <= "ZZZZZZZZZZZZ";
-- RAMread <= 'Z';
-- RAMwrite <= 'Z';
-- MicroCodeCLK <= '1';
-- else
-- MicroCodeCLK <= '0';
-- end if;
-- end process;
--MicroCodeEN <= sw(6);
process (clk, sw, btn, loc, step, word, cooldown, nibble, running, cooldown2, cooldown3, cooldown4, cnt)
begin
if rising_edge(clk) then
if(sw(6) = '0') then
MicroCodeCLK <= '0';
MicroCodeEN <= '0';
if(btn(3) = '0' and cooldown4 = '0') then
if(sw(5 downto 4) = "00") then
word(3 downto 0) <= sw(3 downto 0);
outNibble <= sw(3 downto 0);
elsif(sw(5 downto 4) = "01") then
word(7 downto 4) <= sw(3 downto 0);
outNibble <= sw(3 downto 0);
elsif(sw(5 downto 4) = "11") then
word(11 downto 8) <= sw(3 downto 0);
outNibble <= sw(3 downto 0);
end if;
cooldown4 <= '1';
elsif(btn(3) = '1') then
cooldown4 <= '0';
end if;
if(btn(1) = '0' and cooldown2 = '0') then
loc <= loc + "000000000001";
cooldown2 <= '1';
elsif(btn(1) = '1') then
cooldown2 <= '0';
end if;
if(btn(0) = '1' and cooldown3 = '0') then
loc <= loc - "000000000001";
cooldown3 <= '1';
elsif(btn(0) = '0') then
cooldown3 <= '0';
end if;
Addr <= loc;
if(btn(2) = '1' and cooldown = '0') then
Data <= word;
RAMread <= '0';
RAMWrite <= '1';
cooldown <= '1';
elsif(btn(2) = '0') then
cooldown <= '0';
RAMWrite <= '0';
RAMread <= '1';
Data <= "ZZZZZZZZZZZZ";
end if;
--end if;
else
Data <= "ZZZZZZZZZZZZ";
Addr <= "ZZZZZZZZZZZZ";
RAMWrite <= 'Z';
RAMread <= 'Z';
MicroCodeEN <= '1';
-- if(btn(0) = '0' and cooldown3 = '0') then
-- MicroCodeCLK <= '1';
-- cooldown3 <= '1';
-- elsif(btn(0) = '1') then
-- cooldown3 <= '0';
-- end if;
if(sw(7) = '1') then
cnt <= cnt + "0000000000000000000000001";
if(cnt = "1111111111111111111111111") then
MicroCodeCLK <= '1';
end if;
else
if(btn(0) = '1' and cooldown3 = '0' ) then
MicroCodeCLK <= '1';
cooldown3 <= '1';
elsif(btn(0) = '0') then
cooldown3 <= '0';
end if;
end if;
end if;
end if;
if(clk = '0') then
MicroCodeCLK <= '0';
-- if(cooldown = '0') then
-- Data <= "ZZZZZZZZZZZZ";
-- end if;
end if;
end process;
end Behavioral;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_lib | vhdl/mems/mems_pkg.vhdl | 1 | 4624 | --
-- Mems Package
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (C) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--! Description of memory blocks to be inferred
package Mems is
--! Read-During-Write Behavior
type syncmode_t is (READ_FIRST, WRITE_FIRST, NO_CHANGE);
--! Returns the max memory depth based on the AWIDTH generic when the DEPTH
--! generic is zero or the DEPTH value in other cases.
function getMemorySize(depth: natural; awidth: positive) return positive;
component SinglePortRAM is
generic (
AWIDTH : positive:=8; -- Address width
DWIDTH : positive:=8; -- Data width
DEPTH : natural:=0; -- Memory depth
SYNCMODE : syncmode_t:=WRITE_FIRST; -- Synchronization Mode
OUTREG : boolean :=FALSE -- Optional Output Register
);
port (
clk_i : in std_logic;
wen_i : in std_logic;
addr_i : in std_logic_vector(AWIDTH-1 downto 0);
data_i : in std_logic_vector(DWIDTH-1 downto 0);
data_o : out std_logic_vector(DWIDTH-1 downto 0)
);
end component SinglePortRAM;
component SimpleDualPortRAM is
generic (
AWIDTH : positive:=8; -- Address width
DWIDTH : positive:=8; -- Data width
DEPTH : natural:=0; -- Memory depth
OUTREG : boolean :=FALSE -- Optional Output Register
);
port (
clk1_i : in std_logic;
clk2_i : in std_logic;
wen1_i : in std_logic;
addr1_i : in std_logic_vector(AWIDTH-1 downto 0);
addr2_i : in std_logic_vector(AWIDTH-1 downto 0);
data1_i : in std_logic_vector(DWIDTH-1 downto 0);
data2_o : out std_logic_vector(DWIDTH-1 downto 0)
);
end component SimpleDualPortRAM;
component TrueDualPortRAM is
generic (
AWIDTH : positive:=8; -- Address width
DWIDTH : positive:=8; -- Data width
DEPTH : natural:=0; -- Memory depth
SYNCMODE : syncmode_t:=WRITE_FIRST; -- Synchronization Mode
OUTREG : boolean :=FALSE -- Optional Output Register
);
port (
clk1_i : in std_logic;
clk2_i : in std_logic;
wen1_i : in std_logic;
wen2_i : in std_logic;
addr1_i : in std_logic_vector(AWIDTH-1 downto 0);
addr2_i : in std_logic_vector(AWIDTH-1 downto 0);
data1_i : in std_logic_vector(DWIDTH-1 downto 0);
data2_i : in std_logic_vector(DWIDTH-1 downto 0);
data1_o : out std_logic_vector(DWIDTH-1 downto 0);
data2_o : out std_logic_vector(DWIDTH-1 downto 0)
);
end component TrueDualPortRAM;
component FIFO is
generic (
DWIDTH : positive:=8; -- Data width
DEPTH : positive:=8; -- FIFO depth
OUTREG : boolean :=FALSE; -- Optional Output Register
AFULLOFFSET : positive:=1; -- Almost FULL OFFSET
AEMPTYOFFSET : positive:=1; -- Almost EMPTY OFFSET
ASYNC : boolean :=TRUE -- Asynchronous FIFO
);
port (
-- write side
wclk_i : in std_logic; -- Write Clock
wrst_i : in std_logic; -- Write Reset
wen_i : in std_logic; -- Write Enable
data_i : in std_logic_vector(DWIDTH-1 downto 0); -- Data Input
full_o : out std_logic; -- Full Flag
afull_o : out std_logic; -- Almost Full Flag
overflow_o : out std_logic; -- Overflow Flag
-- read side
rclk_i : in std_logic; -- Read Clock
rrst_i : in std_logic; -- Read Reset
ren_i : in std_logic; -- Read enable
data_o : out std_logic_vector(DWIDTH-1 downto 0); -- Data Output
empty_o : out std_logic; -- Empty flag
aempty_o : out std_logic; -- Almost Empty flag
underflow_o : out std_logic; -- Underflow Flag
valid_o : out std_logic -- Read Valid
);
end component FIFO;
end package Mems;
package body Mems is
function getMemorySize(depth: natural; awidth: positive) return positive is
begin
if depth=0 then
return 2**awidth;
else
return depth;
end if;
end function getMemorySize;
end package body Mems;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_lib | vhdl/mems/SimpleDualPortRAM.vhdl | 1 | 1751 | --
-- Simple Dual-Port RAM
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.MEMS.all;
entity SimpleDualPortRAM is
generic (
AWIDTH : positive:=8; -- Address width
DWIDTH : positive:=8; -- Data width
DEPTH : natural:=0; -- Memory depth
OUTREG : boolean :=FALSE -- Optional Output Register
);
port (
clk1_i : in std_logic;
clk2_i : in std_logic;
wen1_i : in std_logic;
addr1_i : in std_logic_vector(AWIDTH-1 downto 0);
addr2_i : in std_logic_vector(AWIDTH-1 downto 0);
data1_i : in std_logic_vector(DWIDTH-1 downto 0);
data2_o : out std_logic_vector(DWIDTH-1 downto 0)
);
end entity SimpleDualPortRAM;
architecture RTL of SimpleDualPortRAM is
constant SIZE : positive:=getMemorySize(DEPTH,AWIDTH);
type ram_type is array(SIZE-1 downto 0) of std_logic_vector (DWIDTH-1 downto 0);
signal ram : ram_type;
signal data2 : std_logic_vector(DWIDTH-1 downto 0);
begin
ram1_p:
process (clk1_i)
begin
if rising_edge(clk1_i) then
if wen1_i='1' then
ram(to_integer(unsigned(addr1_i))) <= data1_i;
end if;
end if;
end process ram1_p;
ram2_p:
process (clk2_i)
begin
if rising_edge(clk2_i) then
if OUTREG then
data2 <= ram(to_integer(unsigned(addr2_i)));
data2_o <= data2;
else
data2_o <= ram(to_integer(unsigned(addr2_i)));
end if;
end if;
end process ram2_p;
end architecture RTL;
| bsd-3-clause |
Xilinx/PYNQ | boards/ip/audio_codec_ctrl_v1.0/src/iis_deser.vhd | 4 | 4461 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:13:58 12/21/2011
-- Design Name:
-- Module Name: iis_deser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity iis_deser is
Port ( CLK_100MHZ : in STD_LOGIC;
SCLK : in STD_LOGIC;
LRCLK : in STD_LOGIC;
SDATA : in STD_LOGIC;
EN : in STD_LOGIC;
LDATA : out STD_LOGIC_VECTOR (23 downto 0);
RDATA : out STD_LOGIC_VECTOR (23 downto 0);
VALID : out STD_LOGIC);
end iis_deser;
architecture Behavioral of iis_deser is
constant bit_cntr_max : std_logic_vector(4 downto 0) := "11000";
type IIS_STATE_TYPE is (RESET, WAIT_LEFT, SKIP_LEFT, READ_LEFT, WAIT_RIGHT, SKIP_RIGHT, READ_RIGHT);
signal start_left : std_logic;
signal start_right : std_logic;
signal bit_rdy : std_logic;
signal sclk_d1 : std_logic := '0';
signal lrclk_d1 : std_logic := '0';
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal ldata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal rdata_reg : std_logic_vector(23 downto 0) := (others => '0');
--signal valid_reg : std_logic := '0';
signal iis_state : IIS_STATE_TYPE := RESET;
begin
process(CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
sclk_d1 <= SCLK;
lrclk_d1 <= LRCLK;
end if;
end process;
--Detect falling edge on LRCLK
start_left <= (lrclk_d1 and not(LRCLK));
--Detect rising edge on LRCLK
start_right <= (not(lrclk_d1) and LRCLK);
--Detect rising edge on SCLK
bit_rdy <= (not(sclk_d1) and SCLK);
--Next state logic
next_iis_state_process : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
case iis_state is
when RESET =>
if (EN = '1') then
iis_state <= WAIT_LEFT;
end if;
when WAIT_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_left = '1') then
iis_state <= SKIP_LEFT;
end if;
when SKIP_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_rdy = '1') then
iis_state <= READ_LEFT;
end if;
when READ_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_RIGHT;
end if;
when WAIT_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_right = '1') then
iis_state <= SKIP_RIGHT;
end if;
when SKIP_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_rdy = '1') then
iis_state <= READ_RIGHT;
end if;
when READ_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_LEFT;
end if;
when others=> --should never be reached
iis_state <= RESET;
end case;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = READ_RIGHT or iis_state = READ_LEFT) then
if (bit_rdy = '1') then
bit_cntr <= bit_cntr + 1;
end if;
else
bit_cntr <= (others => '0');
end if;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
ldata_reg <= (others => '0');
rdata_reg <= (others => '0');
else
if (iis_state = READ_LEFT and bit_rdy = '1') then
ldata_reg(23 downto 1) <= ldata_reg(22 downto 0);
ldata_reg(0) <= SDATA;
end if;
if (iis_state = READ_RIGHT and bit_rdy = '1') then
rdata_reg(23 downto 1) <= rdata_reg(22 downto 0);
rdata_reg(0) <= SDATA;
end if;
end if;
end if;
end process;
--process (CLK_100MHZ)
--begin
-- if (rising_edge(CLK_100MHZ)) then
-- if (iis_state = READ_RIGHT and bit_cntr = bit_cntr_max) then
-- valid_reg <= '1';
-- else
-- valid_reg <= '0';
-- end if;
-- end if;
--end process;
--!!!TODO:
--Ensure this triggers PWM correctly, It may be causing the data to latch before the last bit is shifted on the Right Channel
VALID <= '1' when (iis_state = READ_RIGHT and bit_cntr = bit_cntr_max) else
'0';
LDATA <= ldata_reg;
RDATA <= rdata_reg;
end Behavioral;
| bsd-3-clause |
Xilinx/PYNQ | boards/ip/audio_codec_ctrl_v1.0/src/common_types.vhd | 4 | 3530 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.family_support.all;
package common_types is
-- TYPE DECLARATIONS
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- FUNCTION GENERATIONS
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function clog2(x : positive) return natural;
end common_types;
package body common_types is
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
end common_types;
| bsd-3-clause |
Xilinx/PYNQ | boards/ip/audio_direct_1.1/src/pdm_ser.vhd | 8 | 4223 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:56 01/31/2014
-- Design Name:
-- Module Name: pdm_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pdm_ser is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_i : in std_logic_vector(15 downto 0);
-- PWM
pwm_audio_o : out std_logic;
pwm_audio_t : out std_logic;
pwm_audio_i : in std_logic
--pwm_sdaudio_o : out std_logic
);
end pdm_ser;
architecture Behavioral of pdm_ser is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal cnt_clk : integer range 0 to 127 := 0;
signal clk_int, clk_intt : std_logic := '0';
signal pdm_clk_rising, pdm_clk_falling : std_logic;
signal pdm_s_tmp : std_logic_vector((C_NR_OF_BITS-1) downto 0);
signal cnt_bits : integer range 0 to 31 := 0;
signal pwm_int : std_logic;
signal done_int : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- enable audio
--pwm_sdaudio_o <= '1';
-- counter for the number of sampled bits
CNT: process(clk_i) begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
cnt_bits <= 0;
else
cnt_bits <= cnt_bits + 1;
end if;
end if;
end if;
end process CNT;
-- done gen
process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
done_o <= '1';
end if;
else
done_o <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------
-- Serializer
------------------------------------------------------------------------
SHFT_OUT: process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-2) then -- end of deserialization
pdm_s_tmp <= data_i;
else
pdm_s_tmp <= pdm_s_tmp(C_NR_OF_BITS-2 downto 0) & '0';
end if;
end if;
end if;
end process SHFT_OUT;
-- output the serial pdm data
pwm_audio_o <= '0';
pwm_audio_t <= --clk_int when en_i = '0' else
'0' when pdm_s_tmp(C_NR_OF_BITS-1) = '0' and en_i = '1' else '1';
------------------------------------------------------------------------
-- slave clock generator
------------------------------------------------------------------------
CLK_CNT: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' or cnt_clk = ((C_SYS_CLK_FREQ_MHZ/(C_PDM_FREQ_MHZ*2))-1) then
cnt_clk <= 0;
clk_int <= not clk_int;
else
cnt_clk <= cnt_clk + 1;
end if;
clk_intt <= clk_int;
end if;
end process CLK_CNT;
pdm_clk_rising <= '1' when clk_int = '1' and clk_intt = '0' else '0';
--pdm_clk_falling <= '1' when cnt_clk = ((clk_div/2)-1) else '0';
end Behavioral;
| bsd-3-clause |
bcuff/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/trace_cntrl_1_2/hdl/vhdl/trace_cntrl_mul_32s_32s_32_7.vhd | 4 | 3069 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity trace_cntrl_mul_32s_32s_32_7_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(32 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of trace_cntrl_mul_32s_32s_32_7_MulnS_0 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(32 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(32 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(32 - 1 downto 0);
signal buff1 : std_logic_vector(32 - 1 downto 0);
signal buff2 : std_logic_vector(32 - 1 downto 0);
signal buff3 : std_logic_vector(32 - 1 downto 0);
signal buff4 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff4;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity trace_cntrl_mul_32s_32s_32_7 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of trace_cntrl_mul_32s_32s_32_7 is
component trace_cntrl_mul_32s_32s_32_7_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
trace_cntrl_mul_32s_32s_32_7_MulnS_0_U : component trace_cntrl_mul_32s_32s_32_7_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| bsd-3-clause |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/d_axi_pdm_1.2/src/pdm_des.vhd | 8 | 3943 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:14 01/31/2014
-- Design Name:
-- Module Name: pdm_des - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pdm_des is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
-- PDM
pdm_m_clk_o : out std_logic;
pdm_m_data_i : in std_logic;
pdm_lrsel_o : out std_logic
);
end pdm_des;
architecture Behavioral of pdm_des is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal cnt_clk : integer range 0 to 127 := 0;
signal clk_int, clk_intt : std_logic := '0';
signal pdm_clk_rising, pdm_clk_falling : std_logic;
signal pdm_tmp : std_logic_vector((C_NR_OF_BITS-1) downto 0);
signal cnt_bits : integer range 0 to 31 := 0;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- with L/R Sel tied to GND => output = DATA1 (rising edge)
pdm_lrsel_o <= '0';
------------------------------------------------------------------------
-- Deserializer
------------------------------------------------------------------------
-- sample input serial data process
SHFT_IN: process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
pdm_tmp <= pdm_tmp(C_NR_OF_BITS-2 downto 0) & pdm_m_data_i;
end if;
end if;
end process SHFT_IN;
-- counter for the number of sampled bits
CNT: process(clk_i) begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
cnt_bits <= 0;
else
cnt_bits <= cnt_bits + 1;
end if;
end if;
end if;
end process CNT;
-- done gen
process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
done_o <= '1';
data_o <= pdm_tmp;
end if;
else
done_o <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------
-- slave clock generator
------------------------------------------------------------------------
CLK_CNT: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' or cnt_clk = ((C_SYS_CLK_FREQ_MHZ/(C_PDM_FREQ_MHZ*2))-1) then
cnt_clk <= 0;
clk_int <= not clk_int;
else
cnt_clk <= cnt_clk + 1;
end if;
clk_intt <= clk_int;
end if;
end process CLK_CNT;
pdm_m_clk_o <= clk_int;
pdm_clk_rising <= '1' when clk_int = '1' and clk_intt = '0' and en_i = '1' else '0';
--pdm_clk_falling <= '1' when cnt_clk = ((clk_div/2)-1) else '0';
end Behavioral;
| bsd-3-clause |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/rgb2dvi_v1_2/src/SyncAsyncReset.vhd | 29 | 3734 | -------------------------------------------------------------------------------
--
-- File: SyncAsyncReset.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int : std_logic;
attribute KEEP : string;
attribute KEEP of aRst_int: signal is "TRUE";
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => oRst);
end Behavioral;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_zc706/gtx/top.vhdl | 1 | 1710 | --
-- Top level of gtx example
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
sysclk_p_i : in std_logic;
sysclk_n_i : in std_logic;
gtxclk_p_i : in std_logic;
gtxclk_n_i : in std_logic;
rx_p_i : in std_logic;
rx_n_i : in std_logic;
tx_p_o : out std_logic;
tx_n_o : out std_logic;
pbc_i : in std_logic;
dips_i : in std_logic_vector(3 downto 0);
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of top is
signal gtxclk, sysclk : std_logic;
signal ready, loopback : std_logic;
-- GBT data
signal rx_data, tx_data : std_logic_vector(39 downto 0);
begin
gtxclk_i : IBUFGDS
port map (O => gtxclk, I => gtxclk_p_i, IB => gtxclk_n_i);
sysclk_i : IBUFGDS
port map (I => sysclk_p_i, IB => sysclk_n_i, O => sysclk);
loopback <= '0';--not pbc_i;
gbt_i: entity work.Wrapper
port map (
gtxclk_i => gtxclk,
sysclk_i => sysclk,
rst_i => '0',
--
rxp_i => rx_p_i,
rxn_i => rx_n_i,
txp_o => tx_p_o,
txn_o => tx_n_o,
--
loopback_i=> loopback,
rx_data_o => rx_data,
tx_data_i => tx_data,
ready_o => ready
);
tx_data <= dips_i & dips_i & dips_i & dips_i & dips_i &
dips_i & dips_i & dips_i & dips_i & dips_i
when ready='1' else X"AAAAAAAAAA";
leds_o <= rx_data(3 downto 0) when ready='1' else "0000";
end architecture RTL;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/gpios/top.vhdl | 1 | 513 | --
-- GPIOs on ml605
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
dips_i : in std_logic_vector(7 downto 0);
pbs_i : in std_logic_vector(4 downto 0);
leds_o : out std_logic_vector(12 downto 0)
);
end entity Top;
architecture RTL of Top is
begin
leds_o(4 downto 0) <= pbs_i;
leds_o(12 downto 5) <= dips_i;
end architecture RTL;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_examples | examples/terasic_de0nano/clock/top.vhdl | 1 | 793 | --
-- Clock on de0nano
--
-- There is one clock source on de0nano board:
-- * On-board 50MHz clock oscillator.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
entity Top is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
leds_o : out std_logic_vector(7 downto 0)
);
end entity Top;
architecture RTL of Top is
signal rst, led : std_logic;
begin
rst <= not(rst_n_i);
blink_inst: Blink
generic map (FREQUENCY => 50e6)
port map(clk_i => clk_i, rst_i => rst, blink_o => led);
leds_o <= led & not(led) & led & not(led) & led & not(led) & led & not(led);
end architecture RTL;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_sp601/clock/top.vhdl | 1 | 1470 | --
-- Clocks on sp601
--
-- There are four clock sources on sp601 board:
-- * On-board differential 200 MHz oscillator.
-- * On-board single-ended Oscillator Socket populated with 27 MHz.
-- * User differential through SMA.
-- * Differential through SMA.
-- This example is about on-board clock sources. They are used to blink user leds.
-- The clock of 200 MHz is used to blink LEDs 0 and 1.
-- The clock of 27 MHz is used to blink LEDs 2 and 3.
-- CPU_RESET push-button is used to stop and restart blink cycle.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
clk_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of Top is
signal clk200, led27, led200 : std_logic;
begin
IBUFGDS_inst: IBUFGDS
port map (I => clk_p_i, IB => clk_n_i, O => clk200);
blink27_inst: Blink
generic map (FREQUENCY => 27e6)
port map(clk_i => clk_i, rst_i => rst_i, blink_o => led27);
blink200_inst: Blink
generic map (FREQUENCY => 200e6)
port map(clk_i => clk200, rst_i => rst_i, blink_o => led200);
leds_o <= led27 & led27 & led200 & led200;
end architecture RTL;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/clock/top.vhdl | 1 | 1659 | --
-- Clocks on ml605
--
-- There are four clock sources on ml605 board:
-- * On-board differential 200 MHz oscillator.
-- * On-board single-ended Oscillator Socket populated with 66 MHz.
-- * User differential through SMA.
-- * MGT differential through SMA.
-- This example is about on-board clock sources. They are used to blink user leds.
-- The clock of 200 MHz is used to blink the 8 GPIO LEDs.
-- The clock of 66 MHz is used to blink the 5 direction LEDs.
-- CPU Reset push-button (SW10) is used to stop and restart blink cycle.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
clk_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(12 downto 0)
);
end entity Top;
architecture RTL of Top is
signal clk200, led66, led200 : std_logic;
begin
IBUFGDS_inst: IBUFGDS
port map (I => clk_p_i, IB => clk_n_i, O => clk200);
blink66_inst: Blink
generic map (FREQUENCY => 66e6)
port map(clk_i => clk_i, rst_i => rst_i, blink_o => led66);
blink200_inst: Blink
generic map (FREQUENCY => 200e6)
port map(clk_i => clk200, rst_i => rst_i, blink_o => led200);
leds_o(4 downto 0) <= led66 & led66 & led66 & led66 & not(led66);
leds_o(12 downto 5) <= led200 & not(led200) & led200 & not(led200) &
led200 & not(led200) & led200 & not(led200);
end architecture RTL;
| bsd-3-clause |
8l/freezing-spice | tests/compare_tb.vhd | 2 | 5077 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.common.all;
use work.decode_pkg.all;
entity compare_tb is
end entity compare_tb;
architecture test of compare_tb is
signal branch_type : branch_type_t;
signal op1 : word;
signal op2 : word;
signal compare_result : std_logic;
begin -- architecture test
uut : entity work.compare_unit(behavioral)
port map (
branch_type => branch_type,
op1 => op1,
op2 => op2,
compare_result => compare_result);
process
begin
----------------------------------------------------------------
-- BEQ
----------------------------------------------------------------
println("BEQ");
branch_type <= BEQ;
op1 <= "00010001000100010001000100010001";
op2 <= "00010001000100010001000100010001";
wait for 1 ns;
assert compare_result = '1' report "Invalid BEQ" severity error;
op2 <= "00010001000100010001000100010000";
wait for 1 ns;
assert compare_result = '0' report "Invalid BEQ" severity error;
----------------------------------------------------------------
-- BNE
----------------------------------------------------------------
println("BNE");
branch_type <= BNE;
wait for 1 ns;
assert compare_result = '1' report "Invalid BNE" severity error;
op2 <= "00010001000100010001000100010001";
wait for 1 ns;
assert compare_result = '0' report "Invalid BNE" severity error;
----------------------------------------------------------------
-- BLT
----------------------------------------------------------------
println("BLT");
branch_type <= BLT;
op1 <= "00000000000000000000000000000001";
op2 <= "00000000000000000000000000000000";
wait for 1 ns;
assert compare_result = '0' report "Invalid BLT" severity error;
op1 <= "00000000000000000000000000000010";
wait for 1 ns;
assert compare_result = '0' report "Invalid BLT" severity error;
op2 <= "01111111111111111111111111111111";
wait for 1 ns;
assert compare_result = '1' report "Invalid BLT" severity error;
----------------------------------------------------------------
-- BGE
----------------------------------------------------------------
println("BGE");
branch_type <= BGE;
wait for 1 ns;
assert compare_result = '0' report "Invalid BGE" severity error;
op1 <= "00000000000000000000000000000010";
op2 <= "00000000000000000000000000000010";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGE" severity error;
op1 <= "11111111111111111111111111111111";
wait for 1 ns;
assert compare_result = '0' report "Invalid BGE" severity error;
op2 <= "11111111111111111111111111111110";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGE" severity error;
----------------------------------------------------------------
-- BLTU
----------------------------------------------------------------
println("BLTU");
branch_type <= BLTU;
wait for 1 ns;
assert compare_result = '0' report "Invalid BLTU" severity error;
op1 <= "11111111111111111111111111111100";
wait for 1 ns;
assert compare_result = '1' report "Invalid BLTU" severity error;
op2 <= "11111111111111111111111111111100";
wait for 1 ns;
assert compare_result = '0' report "Invalid BLTU" severity error;
----------------------------------------------------------------
-- BGEU
----------------------------------------------------------------
println("BGEU");
branch_type <= BGEU;
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
op1 <= "00000000000000000000000000000000";
op2 <= "00000000000000000000000000000000";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
op1 <= "00000000000000000000000000000001";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
op1 <= "11111111111111111111111111111111";
op2 <= "11111111111111111111111111111110";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
----------------------------------------------------------------
println("Simulation complete");
----------------------------------------------------------------
wait;
end process;
end architecture test;
| bsd-3-clause |
8l/freezing-spice | src/alu.vhd | 3 | 2129 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity alu is
port (alu_func : in alu_func_t;
op1 : in word;
op2 : in word;
result : out word);
end entity alu;
architecture behavioral of alu is
begin -- architecture behavioral
-- purpose: arithmetic and logic
-- type : combinational
-- inputs : alu_func, op1, op2
-- outputs: result
alu_proc : process (alu_func, op1, op2) is
variable so1, so2 : signed(31 downto 0);
variable uo1, uo2 : unsigned(31 downto 0);
begin -- process alu_proc
so1 := signed(op1);
so2 := signed(op2);
uo1 := unsigned(op1);
uo2 := unsigned(op2);
case (alu_func) is
when ALU_ADD => result <= std_logic_vector(so1 + so2);
when ALU_ADDU => result <= std_logic_vector(uo1 + uo2);
when ALU_SUB => result <= std_logic_vector(so1 - so2);
when ALU_SUBU => result <= std_logic_vector(uo1 - uo2);
when ALU_SLT =>
if so1 < so2 then
result <= "00000000000000000000000000000001";
else
result <= (others => '0');
end if;
when ALU_SLTU =>
if uo1 < uo2 then
result <= "00000000000000000000000000000001";
else
result <= (others => '0');
end if;
when ALU_AND => result <= op1 and op2;
when ALU_OR => result <= op1 or op2;
when ALU_XOR => result <= op1 xor op2;
when ALU_SLL => result <= std_logic_vector(shift_left(uo1, to_integer(uo2(4 downto 0))));
when ALU_SRA => result <= std_logic_vector(shift_right(so1, to_integer(uo2(4 downto 0))));
when ALU_SRL => result <= std_logic_vector(shift_right(uo1, to_integer(uo2(4 downto 0))));
when others => result <= op1;
end case;
end process alu_proc;
end architecture behavioral;
| bsd-3-clause |
8l/freezing-spice | src/common.vhd | 2 | 5916 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package common is
-- definition for a machine word
subtype word is std_logic_vector(31 downto 0);
subtype imm_type_t is std_logic_vector(2 downto 0);
subtype alu_func_t is std_logic_vector(3 downto 0);
constant ALU_NONE : alu_func_t := "0000";
constant ALU_ADD : alu_func_t := "0001";
constant ALU_ADDU : alu_func_t := "0010";
constant ALU_SUB : alu_func_t := "0011";
constant ALU_SUBU : alu_func_t := "0100";
constant ALU_SLT : alu_func_t := "0101";
constant ALU_SLTU : alu_func_t := "0110";
constant ALU_AND : alu_func_t := "0111";
constant ALU_OR : alu_func_t := "1000";
constant ALU_XOR : alu_func_t := "1001";
constant ALU_SLL : alu_func_t := "1010";
constant ALU_SRA : alu_func_t := "1011";
constant ALU_SRL : alu_func_t := "1100";
subtype insn_type_t is std_logic_vector(3 downto 0);
constant OP_ILLEGAL : insn_type_t := "0000";
constant OP_LUI : insn_type_t := "0001";
constant OP_AUIPC : insn_type_t := "0010";
constant OP_JAL : insn_type_t := "0011";
constant OP_JALR : insn_type_t := "0100";
constant OP_BRANCH : insn_type_t := "0101";
constant OP_LOAD : insn_type_t := "0110";
constant OP_STORE : insn_type_t := "0111";
constant OP_ALU : insn_type_t := "1000";
subtype branch_type_t is std_logic_vector(2 downto 0);
constant BRANCH_NONE : branch_type_t := "000";
constant BEQ : branch_type_t := "001";
constant BNE : branch_type_t := "010";
constant BLT : branch_type_t := "011";
constant BGE : branch_type_t := "100";
constant BLTU : branch_type_t := "101";
constant BGEU : branch_type_t := "110";
subtype load_type_t is std_logic_vector(2 downto 0);
constant LOAD_NONE : load_type_t := "000";
constant LB : load_type_t := "001";
constant LH : load_type_t := "010";
constant LW : load_type_t := "011";
constant LBU : load_type_t := "100";
constant LHU : load_type_t := "101";
subtype store_type_t is std_logic_vector(1 downto 0);
constant STORE_NONE : store_type_t := "00";
constant SB : store_type_t := "01";
constant SH : store_type_t := "10";
constant SW : store_type_t := "11";
-- print a string with a newline
procedure println (str : in string);
procedure print (slv : in std_logic_vector);
procedure write(l : inout line; slv : in std_logic_vector);
function hstr(slv : std_logic_vector) return string;
-- instruction formats
type r_insn_t is (R_ADD, R_SLT, R_SLTU, R_AND, R_OR, R_XOR, R_SLL, R_SRL, R_SUB, R_SRA);
type i_insn_t is (I_JALR, I_LB, I_LH, I_LW, I_LBU, I_LHU, I_ADDI, I_SLTI, I_SLTIU, I_XORI, I_ORI, I_ANDI, I_SLLI, I_SRLI, I_SRAI);
type s_insn_t is (S_SB, S_SH, S_SW);
type sb_insn_t is (SB_BEQ, SB_BNE, SB_BLT, SB_BGE, SB_BLTU, SB_BGEU);
type u_insn_t is (U_LUI, U_AUIPC);
type uj_insn_t is (UJ_JAL);
-- ADDI r0, r0, r0
constant NOP : word := "00000000000000000000000000010011";
end package common;
package body common is
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- print a string with a newline
procedure println (str : in string) is
variable l : line;
begin -- procedure println
write(l, str);
writeline(output, l);
end procedure println;
procedure write(l : inout line; slv : in std_logic_vector) is
begin
for i in slv'range loop
if slv(i) = '0' then
write(l, string'("0"));
elsif slv(i) = '1' then
write(l, string'("1"));
elsif slv(i) = 'X' then
write(l, string'("X"));
elsif slv(i) = 'U' then
write(l, string'("U"));
end if;
end loop; -- i
end procedure write;
procedure print (slv : in std_logic_vector) is
variable l : line;
begin -- procedure print
write(l, slv);
writeline(output, l);
end procedure print;
end package body common;
| bsd-3-clause |
eamadio/fpgaMSP430 | fmsp430/core/fmsp_mem_backbone.vhd | 1 | 20747 |
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_mem_backbone.vhd
--!
--! @brief fpgaMSP430 Memory interface backbone (decoder + arbiter)
--
--! @author Olivier Girard, olgirard@gmail.com
--! @author Emmanuel Amadio, emmanuel.amadio@gmail.com (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_core_package.all;
use work.fmsp_functions.all;
entity fmsp_mem_backbone is
generic (
PMEM_SIZE : integer := 32768; --! Program Memory Size
DMEM_SIZE : integer := 16384; --! Data Memory Size
PER_SIZE : integer := 16384; --! Peripheral Memory Size
DMA_IF_EN : boolean := false --! Wakeup condition from DMA interface
);
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
cpu_halt_st : in std_logic; --! Halt/Run status from CPU
dbg_halt_cmd : in std_logic; --! Debug interface Halt CPU command
dbg_mem_addr : in std_logic_vector(15 downto 0); --! Debug address for rd/wr access
dbg_mem_dout : in std_logic_vector(15 downto 0); --! Debug unit data output
dbg_mem_en : in std_logic; --! Debug unit memory enable
dbg_mem_wr : in std_logic_vector(1 downto 0); --! Debug unit memory write
dmem_dout : in std_logic_vector(15 downto 0); --! Data Memory data output
eu_mab : in std_logic_vector(14 downto 0); --! Execution Unit Memory address bus
eu_mb_en : in std_logic; --! Execution Unit Memory bus enable
eu_mb_wr : in std_logic_vector(1 downto 0); --! Execution Unit Memory bus write transfer
eu_mdb_out : in std_logic_vector(15 downto 0); --! Execution Unit Memory data bus output
fe_mab : in std_logic_vector(14 downto 0); --! Frontend Memory address bus
fe_mb_en : in std_logic; --! Frontend Memory bus enable
dma_addr : in std_logic_vector(15 downto 0); --! Direct Memory Access address
dma_din : in std_logic_vector(15 downto 0); --! Direct Memory Access data input
dma_en : in std_logic; --! Direct Memory Access enable (high active)
dma_priority : in std_logic; --! Direct Memory Access priority (0:low / 1:high)
dma_we : in std_logic_vector(1 downto 0); --! Direct Memory Access write byte enable (high active)
per_dout : in std_logic_vector(15 downto 0); --! Peripheral data output
pmem_dout : in std_logic_vector(15 downto 0); --! Program Memory data output
--! OUTPUTs
cpu_halt_cmd : out std_logic; --! Halt CPU command
dbg_mem_din : out std_logic_vector(15 downto 0); --! Debug unit Memory data input
dmem_addr : out std_logic_vector(f_log2(DMEM_SIZE)-2 downto 0); --! Data Memory address
dmem_cen : out std_logic; --! Data Memory chip enable (low active)
dmem_din : out std_logic_vector(15 downto 0); --! Data Memory data input
dmem_wen : out std_logic_vector(1 downto 0); --! Data Memory write enable (low active)
eu_mdb_in : out std_logic_vector(15 downto 0); --! Execution Unit Memory data bus input
fe_mdb_in : out std_logic_vector(15 downto 0); --! Frontend Memory data bus input
fe_pmem_wait : out std_logic; --! Frontend wait for Instruction fetch
dma_dout : out std_logic_vector(15 downto 0); --! Direct Memory Access data output
dma_ready : out std_logic; --! Direct Memory Access is complete
dma_resp : out std_logic; --! Direct Memory Access response (0:Okay / 1:Error)
per_addr : out std_logic_vector(13 downto 0); --! Peripheral address
per_din : out std_logic_vector(15 downto 0); --! Peripheral data input
per_we : out std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
per_en : out std_logic; --! Peripheral enable (high active)
pmem_addr : out std_logic_vector(f_log2(PMEM_SIZE)-2 downto 0); --! Program Memory address
pmem_cen : out std_logic; --! Program Memory chip enable (low active)
pmem_din : out std_logic_vector(15 downto 0); --! Program Memory data input (optional)
pmem_wen : out std_logic_vector(1 downto 0) --! Program Memory write enable (low active) (optional)
);
end entity fmsp_mem_backbone;
architecture RTL of fmsp_mem_backbone is
--! Data Memory Base Adresses
constant DMEM_BASE :integer := PER_SIZE;
--! Program & Data Memory most significant address bit (for 16 bit words)
constant PMEM_MSB :integer := (f_log2(PMEM_SIZE)-2);
constant DMEM_MSB :integer := (f_log2(DMEM_SIZE)-2);
constant PER_MSB :integer := (f_log2(PER_SIZE)-2);
constant DMEM_END :integer := (DMEM_BASE + DMEM_SIZE);
constant PMEM_OFFSET :integer := (65535 - PMEM_SIZE + 1);
signal w_eu_dmem_cen : std_logic;
signal w_cpu_halt_cmd : std_logic;
signal w_dma_resp : std_logic;
signal w_dma_ready : std_logic;
signal r_dma_ready_dly : std_logic;
signal w_ext_mem_en : std_logic;
signal w_ext_mem_wr : std_logic_vector(1 downto 0);
signal w_ext_mem_addr : std_logic_vector(15 downto 0);
signal w_ext_mem_dout : std_logic_vector(15 downto 0);
signal w_dbg_mem_din : std_logic_vector(15 downto 0);
signal w_dma_dout : std_logic_vector(15 downto 0);
signal w_eu_dmem_sel : std_logic;
signal w_eu_dmem_en : std_logic;
signal w_eu_dmem_addr : std_logic_vector(15 downto 0);
signal w_ext_dmem_sel : std_logic;
signal w_ext_dmem_en : std_logic;
signal w_ext_dmem_addr : std_logic_vector(15 downto 0);
signal w_dmem_cen : std_logic;
signal w_dmem_wen : std_logic_vector(1 downto 0);
signal w_dmem_addr : std_logic_vector(DMEM_MSB downto 0);
signal w_dmem_din : std_logic_vector(15 downto 0);
signal w_eu_pmem_sel : std_logic;
signal w_eu_pmem_en : std_logic;
signal w_eu_pmem_addr : std_logic_vector(15 downto 0);
signal w_fe_pmem_sel : std_logic;
signal w_fe_pmem_en : std_logic;
signal w_fe_pmem_addr : std_logic_vector(15 downto 0);
signal w_ext_pmem_sel : std_logic;
signal w_ext_pmem_en : std_logic;
signal w_ext_pmem_addr : std_logic_vector(15 downto 0);
signal w_pmem_cen : std_logic;
signal w_pmem_wen : std_logic_vector(1 downto 0);
signal w_pmem_addr : std_logic_vector(PMEM_MSB downto 0);
signal w_pmem_din : std_logic_vector(15 downto 0);
signal w_fe_pmem_wait : std_logic;
signal w_eu_per_sel : std_logic;
signal w_eu_per_en : std_logic;
signal w_ext_per_sel : std_logic;
signal w_ext_per_en : std_logic;
signal w_per_en : std_logic;
signal w_per_we : std_logic_vector(1 downto 0);
signal w_per_addr_mux : std_logic_vector(PER_MSB downto 0);
signal w_per_addr_ful : std_logic_vector(14 downto 0);
signal w_per_addr : std_logic_vector(13 downto 0);
signal w_per_din : std_logic_vector(15 downto 0);
signal r_per_dout_val : std_logic_vector(15 downto 0);
signal w_fe_pmem_en_dly : std_logic;
signal w_fe_pmem_save : std_logic;
signal w_fe_pmem_restore : std_logic;
signal w_pmem_dout_bckup : std_logic_vector(15 downto 0);
signal w_pmem_dout_bckup_sel: std_logic;
signal w_fe_mdb_in : std_logic_vector(15 downto 0);
signal w_eu_mdb_in_sel : std_logic_vector(1 downto 0);
signal w_eu_mdb_in : std_logic_vector(15 downto 0);
signal w_ext_mem_din_sel : std_logic_vector(1 downto 0);
signal w_ext_mem_din : std_logic_vector(15 downto 0);
--! Register peripheral data read path
signal r_fe_pmem_en_dly : std_logic;
signal r_pmem_dout_bckup : std_logic_vector(15 downto 0);
signal r_pmem_dout_bckup_sel : std_logic;
signal r_eu_mdb_in_sel : std_logic_vector(1 downto 0);
signal r_ext_mem_din_sel : std_logic_vector(1 downto 0);
begin
--=============================================================================
--! 1) DECODER
--=============================================================================
COMB : process(all)
begin
--------------------------------------------
--! Arbiter between DMA and Debug interface
--------------------------------------------
if (DMA_IF_EN = true) then
--! Debug-interface always stops the CPU
--! Master interface stops the CPU in priority mode
w_cpu_halt_cmd <= dbg_halt_cmd or (dma_en and dma_priority);
--! Return ERROR response if address lays outside the memory spaces (Peripheral, Data and Program memories)
w_dma_resp <= not(dbg_mem_en) and not(w_ext_dmem_sel or w_ext_pmem_sel or w_ext_per_sel) and dma_en;
--! Master interface access is ready when the memory access occures
w_dma_ready <= not(dbg_mem_en) and (w_ext_dmem_en or w_ext_pmem_en or w_ext_per_en or dma_resp);
--! Use delayed version of 'dma_ready' to mask the 'dma_dout' data output
--! when not accessed and reduce toggle rate (thus power consumption)
--! Mux between debug and master interface
w_ext_mem_en <= dbg_mem_en or dma_en;
if (dbg_mem_en = '1') then
w_ext_mem_wr <= dbg_mem_wr;
w_ext_mem_addr <= dbg_mem_addr;
w_ext_mem_dout <= dbg_mem_dout;
else
w_ext_mem_wr <= dma_we;
w_ext_mem_addr <= dma_addr;
w_ext_mem_dout <= dma_din;
end if;
--! External interface read data
w_dbg_mem_din <= w_ext_mem_din;
if (r_dma_ready_dly = '1') then
w_dma_dout <= w_ext_mem_din;
else
w_dma_dout <= x"0000";
end if;
else
--! Debug-interface always stops the CPU
w_cpu_halt_cmd <= dbg_halt_cmd;
--! Master interface access is always ready with error response when excluded
w_dma_resp <= '1';
w_dma_ready <= '1';
--! Debug interface only
w_ext_mem_en <= dbg_mem_en;
w_ext_mem_wr <= dbg_mem_wr;
w_ext_mem_addr <= dbg_mem_addr;
w_ext_mem_dout <= dbg_mem_dout;
--! External interface read data
w_dbg_mem_din <= w_ext_mem_din;
w_dma_dout <= x"0000";
end if;
--------------------------------------------
--! DATA-MEMORY Interface
--------------------------------------------
--! Execution unit access
--w_eu_dmem_sel <= (eu_mab>=(`DMEM_BASE>>1)) and (eu_mab< ( DMEM_END >>1));
if ( ( UNSIGNED(eu_mab) >= TO_UNSIGNED((DMEM_BASE/2),15) ) and
( UNSIGNED(eu_mab) < TO_UNSIGNED((DMEM_END/2),15) ) ) then
w_eu_dmem_sel <= '1';
else
w_eu_dmem_sel <= '0';
end if;
w_eu_dmem_en <= eu_mb_en and w_eu_dmem_sel;
w_eu_dmem_addr <= STD_LOGIC_VECTOR( (UNSIGNED(eu_mab)/2) - TO_UNSIGNED((DMEM_BASE/2),16) );
--! Front-end access
--! --! not allowed to execute from data memory --
--! External Master/Debug interface access
--w_ext_dmem_sel <= (ext_mem_addr[15:1]>=(`DMEM_BASE>>1)) an (ext_mem_addr[15:1]< ( DMEM_END >>1));
if ( ( UNSIGNED(w_ext_mem_addr(15 downto 1)) >= TO_UNSIGNED((DMEM_BASE/2),15) ) and
( UNSIGNED(w_ext_mem_addr(15 downto 1)) < TO_UNSIGNED((DMEM_END/2),15) ) ) then
w_ext_dmem_sel <= '1';
else
w_ext_dmem_sel <= '0';
end if;
w_ext_dmem_en <= w_ext_mem_en and w_ext_dmem_sel and not(w_eu_dmem_en);
--w_ext_dmem_addr<= {1'b0, ext_mem_addr[15:1]}-(`DMEM_BASE>>1);
w_ext_dmem_addr <= STD_LOGIC_VECTOR( (UNSIGNED(w_ext_mem_addr)/2) - TO_UNSIGNED((DMEM_BASE/2),16) );
--! Data-Memory Interface
w_dmem_cen <= not(w_ext_dmem_en or w_eu_dmem_en);
if (w_ext_dmem_en = '1') then
w_dmem_wen <= not(w_ext_mem_wr);
w_dmem_addr <= w_ext_dmem_addr(DMEM_MSB downto 0);
w_dmem_din <= w_ext_mem_dout;
else
w_dmem_wen <= not(eu_mb_wr);
w_dmem_addr <= w_eu_dmem_addr(DMEM_MSB downto 0);
w_dmem_din <= eu_mdb_out;
end if;
--------------------------------------------
--! PROGRAM-MEMORY Interface
--------------------------------------------
--! Execution unit access (only read access are accepted)
--w_eu_pmem_sel <= (eu_mab>=(PMEM_OFFSET>>1));
if ( UNSIGNED(eu_mab) >= TO_UNSIGNED((PMEM_OFFSET/2),15) ) then
w_eu_pmem_sel <= '1';
else
w_eu_pmem_sel <= '0';
end if;
w_eu_pmem_en <= eu_mb_en and not(eu_mb_wr(1) or eu_mb_wr(0)) and w_eu_pmem_sel;
--w_eu_pmem_addr <= eu_mab-(PMEM_OFFSET>>1);
w_eu_pmem_addr <= STD_LOGIC_VECTOR( UNSIGNED(eu_mab) - TO_UNSIGNED((PMEM_OFFSET/2),16) );
--! Front-end access
--w_fe_pmem_sel <= (fe_mab>=(PMEM_OFFSET>>1));
if ( UNSIGNED(fe_mab) >= TO_UNSIGNED((PMEM_OFFSET/2),15) ) then
w_fe_pmem_sel <= '1';
else
w_fe_pmem_sel <= '0';
end if;
w_fe_pmem_en <= fe_mb_en and w_fe_pmem_sel;
--w_fe_pmem_addr <= fe_mab-(PMEM_OFFSET>>1);
w_fe_pmem_addr <= STD_LOGIC_VECTOR( UNSIGNED(fe_mab) - TO_UNSIGNED((PMEM_OFFSET/2),16) );
--! External Master/Debug interface access
--w_ext_pmem_sel <= (ext_mem_addr[15:1]>=(PMEM_OFFSET>>1));
if ( UNSIGNED(w_ext_mem_addr(15 downto 1)) >= TO_UNSIGNED((PMEM_OFFSET/2),15) ) then
w_ext_pmem_sel <= '1';
else
w_ext_pmem_sel <= '0';
end if;
w_ext_pmem_en <= w_ext_mem_en and w_ext_pmem_sel and not(w_eu_pmem_en) and not(w_fe_pmem_en);
--w_ext_pmem_addr <= {1'b0, ext_mem_addr[15:1]}-(PMEM_OFFSET>>1);
w_ext_pmem_addr <= STD_LOGIC_VECTOR( UNSIGNED(w_ext_mem_addr(15 downto 1)) - TO_UNSIGNED((PMEM_OFFSET/2),16) );
--! Program-Memory Interface (Execution unit has priority over the Front-end)
w_pmem_cen <= not(w_fe_pmem_en or w_eu_pmem_en or w_ext_pmem_en);
if (w_ext_pmem_en = '1') then
w_pmem_wen <= not(w_ext_mem_wr);
else
w_pmem_wen <= "11";
end if;
if (w_ext_pmem_en = '1') then
w_pmem_addr <= w_ext_pmem_addr(PMEM_MSB downto 0);
elsif (w_eu_pmem_en = '1') then
w_pmem_addr <= w_eu_pmem_addr(PMEM_MSB downto 0);
else
w_pmem_addr <= w_fe_pmem_addr(PMEM_MSB downto 0);
end if;
w_pmem_din <= w_ext_mem_dout;
w_fe_pmem_wait <= w_fe_pmem_en and w_eu_pmem_en;
--------------------------------------------
--! PERIPHERALS Interface
--------------------------------------------
--! Execution unit access
--w_eu_per_sel <= (eu_mab<(`PER_SIZE>>1));
if ( UNSIGNED(eu_mab) < TO_UNSIGNED((PER_SIZE/2),15) ) then
w_eu_per_sel <= '1';
else
w_eu_per_sel <= '0';
end if;
w_eu_per_en <= eu_mb_en and w_eu_per_sel;
--! Front-end access
--! --! not allowed to execute from peripherals memory space --
--! External Master/Debug interface access
--w_ext_per_sel <= (ext_mem_addr[15:1]<(`PER_SIZE>>1));
if ( UNSIGNED(w_ext_mem_addr(15 downto 1)) < TO_UNSIGNED((PER_SIZE/2),15) ) then
w_ext_per_sel <= '1';
else
w_ext_per_sel <= '0';
end if;
w_ext_per_en <= w_ext_mem_en and w_ext_per_sel and not(w_eu_per_en);
--! Peripheral Interface
w_per_en <= w_ext_per_en or w_eu_per_en;
if (w_ext_per_en = '1') then
w_per_we <= w_ext_mem_wr;
w_per_addr_mux <= w_ext_mem_addr(PER_MSB+1 downto 1);
w_per_din <= w_ext_mem_dout;
else
w_per_we <= eu_mb_wr;
w_per_addr_mux <= eu_mab(PER_MSB downto 0);
w_per_din <= eu_mdb_out;
end if;
--w_per_addr_ful <= {{15-`PER_AWIDTH{1'b0}}, per_addr_mux};
w_per_addr_ful <= STD_LOGIC_VECTOR( resize( UNSIGNED(w_per_addr_mux), 15) );
w_per_addr <= w_per_addr_ful(13 downto 0);
--------------------------------------------
--! Frontend data Mux
--------------------------------------------
--! Whenever the frontend doesn't access the program memory, backup the data
--! Detect whenever the data should be backuped and restored
w_fe_pmem_save <= (not(w_fe_pmem_en) and r_fe_pmem_en_dly) and not(cpu_halt_st);
w_fe_pmem_restore<= ( w_fe_pmem_en and not(r_fe_pmem_en_dly)) or cpu_halt_st;
--! Mux between the Program memory data and the backup
if (r_pmem_dout_bckup_sel = '1') then
w_fe_mdb_in <= r_pmem_dout_bckup;
else
w_fe_mdb_in <= pmem_dout;
end if;
--------------------------------------------
--! Execution-Unit data Mux
--------------------------------------------
--! Select between Peripherals, Program and Data memories
--! Mux
if (r_eu_mdb_in_sel(1) = '1') then
w_eu_mdb_in <= pmem_dout;
elsif (r_eu_mdb_in_sel(0) = '1') then
w_eu_mdb_in <= r_per_dout_val;
else
w_eu_mdb_in <= dmem_dout;
end if;
--------------------------------------------
--! External Master/Debug interface data Mux
--------------------------------------------
--! Select between Peripherals, Program and Data memories
--! Mux
if (r_ext_mem_din_sel(1) = '1') then
w_ext_mem_din <= pmem_dout;
elsif (r_ext_mem_din_sel(0) = '1') then
w_ext_mem_din <= r_per_dout_val;
else
w_ext_mem_din <= dmem_dout;
end if;
end process COMB;
REGS : process (mclk, mrst)
begin
if (mrst = '1') then
r_dma_ready_dly <= '0';
r_per_dout_val <= x"0000";
r_fe_pmem_en_dly <= '0';
r_pmem_dout_bckup_sel <= '0';
r_pmem_dout_bckup <= x"0000";
r_eu_mdb_in_sel <= "00";
r_ext_mem_din_sel <= "00";
elsif rising_edge(mclk) then
--! Use delayed version of 'dma_ready' to mask the 'dma_dout' data output
--! when not accessed and reduce toggle rate (thus power consumption)
r_dma_ready_dly <= dma_ready;
--! Register peripheral data read path
r_per_dout_val <= per_dout;
--! Detect whenever the data should be backuped and restored
r_fe_pmem_en_dly <= w_fe_pmem_en;
--! Mux between the Program memory data and the backup
if (w_fe_pmem_save = '1') then
r_pmem_dout_bckup_sel <= '1';
elsif (w_fe_pmem_restore = '1') then
r_pmem_dout_bckup_sel <= '0';
end if;
if (w_fe_pmem_save = '1') then
r_pmem_dout_bckup <= pmem_dout;
end if;
--! Select between Peripherals, Program and Data memories
r_eu_mdb_in_sel <= w_eu_pmem_en & w_eu_per_en;
r_ext_mem_din_sel <= w_ext_pmem_en & w_ext_per_en;
end if;
end process REGS;
cpu_halt_cmd <= w_cpu_halt_cmd; --! Halt CPU command
dbg_mem_din <= w_dbg_mem_din; --! Debug unit Memory data input
dmem_addr <= w_dmem_addr; --! Data Memory address
dmem_cen <= w_dmem_cen; --! Data Memory chip enable (low active)
dmem_din <= w_dmem_din; --! Data Memory data input
dmem_wen <= w_dmem_wen; --! Data Memory write enable (low active)
eu_mdb_in <= w_eu_mdb_in; --! Execution Unit Memory data bus input
fe_mdb_in <= w_fe_mdb_in; --! Frontend Memory data bus input
fe_pmem_wait <= w_fe_pmem_wait; --! Frontend wait for Instruction fetch
dma_dout <= w_dma_dout; --! Direct Memory Access data output
dma_ready <= w_dma_ready; --! Direct Memory Access is complete
dma_resp <= w_dma_resp; --! Direct Memory Access response (0:Okay / 1:Error)
per_addr <= w_per_addr; --! Peripheral address
per_din <= w_per_din; --! Peripheral data input
per_we <= w_per_we; --! Peripheral write enable (high active)
per_en <= w_per_en; --! Peripheral enable (high active)
pmem_addr <= w_pmem_addr; --! Program Memory address
pmem_cen <= w_pmem_cen; --! Program Memory chip enable (low active)
pmem_din <= w_pmem_din; --! Program Memory data input (optional)
pmem_wen <= w_pmem_wen; --! Program Memory write enable (low active) (optional)
end RTL; --! fmsp_mem_backbone | bsd-3-clause |
eamadio/fpgaMSP430 | fpga_package.vhd | 1 | 4322 | ------------------------------------------------------------------------------
-- Copyright (C) 2009 , Emmanuel Amadio
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the authors nor the names of its contributors
-- may be used to endorse or promote products derived from this software
-- without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
-- *File Name: fpga_package.vhd
--
-- *Module Description:
--
--
-- *Author(s):
--! @author Emmanuel Amadio, emmanuel.amadio@gmail.com (VHDL Rewrite)
--
------------------------------------------------------------------------------
-- $Rev: 103 $
-- $LastChangedBy: olivier.girard $
-- $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; -- for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
package fpga_package is
component ram_16x8k is
port(
-- INPUTs
address : in std_logic_vector(12 downto 0);
byteena : in std_logic_vector(1 downto 0);
clken : in std_logic;
clock : in std_logic;
data : in std_logic_vector(15 downto 0);
wren : in std_logic;
-- OUTPUTs
q : out std_logic_vector(15 downto 0)
);
end component ram_16x8k;
component ram_16x16k is
port(
-- INPUTs
address : in std_logic_vector(13 downto 0);
byteena : in std_logic_vector(1 downto 0);
clken : in std_logic;
clock : in std_logic;
data : in std_logic_vector(15 downto 0);
wren : in std_logic;
-- OUTPUTs
q : out std_logic_vector(15 downto 0)
);
end component ram_16x16k;
component sync_debouncer_10ms is
port (
-- INPUTs
clk_50mhz : in std_logic; -- 50MHz clock
rst : in std_logic; -- reset
signal_async : in std_logic; -- Asynchonous signal
-- OUTPUTs
signal_debounced : out std_logic -- Synchronized and 10ms debounced signal
);
end component sync_debouncer_10ms;
component fmsp_de0_nano_soc_led_key_sw is
port (
mclk : in std_logic; -- Main system clock
puc_rst : in std_logic; -- Main system reset
-- INPUTs
key : in std_logic_vector(3 downto 0); -- key/button inputs
sw : in std_logic_vector(3 downto 0); -- switches inputs
per_addr : in std_logic_vector(13 downto 0); -- Peripheral address
per_din : in std_logic_vector(15 downto 0); -- Peripheral data input
per_en : in std_logic; -- Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); -- Peripheral write enable (high active)
-- OUTPUTs
irq_key : out std_logic; -- Key/Button interrupt
irq_sw : out std_logic; -- Switch interrupt
led : out std_logic_vector(7 downto 0); -- LED output control
per_dout : out std_logic_vector(15 downto 0) -- Peripheral data output
);
end component fmsp_de0_nano_soc_led_key_sw;
end fpga_package; | bsd-3-clause |
eamadio/fpgaMSP430 | fmsp430/misc/fmsp_and_gate.vhd | 1 | 3442 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_and_gate.vhd
--!
--! @brief fpgaMSP430 Generic AND gate cell
--
--! @author Olivier Girard, olgirard@gmail.com
--! @author Emmanuel Amadio, emmanuel.amadio@gmail.com (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
entity fmsp_and_gate is
port (
--! INPUTs
a : in std_logic; --! AND gate input A
b : in std_logic; --! AND gate input B
--! OUTPUTs
y : out std_logic --! AND gate outputt
);
end entity fmsp_and_gate;
architecture RTL of fmsp_and_gate is
begin
--=============================================================================
--! 1) SOME COMMENTS ON THIS MODULE
--=============================================================================
--
--! In its ASIC version, some combinatorial pathes of the openMSP430 are
--! sensitive to glitches, in particular the ones generating the wakeup
--! signals.
--! To prevent synthesis from optmizing combinatorial clouds into glitchy
--! logic, this AND gate module has been instanciated in the critical places.
--
--! Make sure that synthesis doesn't ungroup this module. As an alternative,
--! a standard cell from the library could also be directly instanciated here
--! (don't forget the "dont_touch" attribute)
--
--
--=============================================================================
--! 2) AND GATE
--=============================================================================
y <= a and b;
end RTL; --! fmsp_and_gate
| bsd-3-clause |
0x00f/game_of_life_vhdl | board.vhdl | 2 | 6304 |
package matrix_pkg is
constant X: integer := 4;
constant Y: integer := 4;
type matrix is array(0 to X, 0 to Y) of integer range 0 to 1;
end package matrix_pkg;
use work.matrix_pkg.all;
entity board is
generic (
init_state : matrix
);
port (
mat: inout matrix;
clock: in integer range 0 to 1
);
end board;
architecture arch of board is
component cell
generic (
start_alive : integer range 0 to 1
);
port (
clock,
upper_left, upper, upper_right,
left, right,
lower_left, lower, lower_right : in integer range 0 to 1;
alive : inout integer range 0 to 1
);
end component;
begin
outer:
for i in 0 to X generate
begin
inner:
for j in 0 to Y generate
begin
upper_left:
if (i = 0 and j = 0) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => 0,
upper_right => 0,
left => 0,
right => mat(i + 1, j),
lower_left => 0,
lower => mat(i, j + 1),
lower_right => mat(i + 1, j + 1),
alive => mat(i, j));
end generate upper_left;
upper:
if (i > 0 and i < X and j = 0) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => 0,
upper_right => 0,
left => mat(i - 1, j),
right => mat(i + 1, j),
lower_left => mat(i - 1, j + 1),
lower => mat(i, j + 1),
lower_right => mat(i + 1, j + 1),
alive => mat(i, j));
end generate upper;
upper_right:
if (i = X and j = 0) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => 0,
upper_right => 0,
left => mat(i - 1, j),
right => 0,
lower_left => mat(i - 1, j + 1),
lower => mat(i, j + 1),
lower_right => 0,
alive => mat(i, j));
end generate upper_right;
left:
if (i = 0 and j > 0 and j < Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => mat(i, j - 1),
upper_right => mat(i + 1, j - 1),
left => 0,
right => mat(i + 1, j),
lower_left => 0,
lower => mat(i, j + 1),
lower_right => mat(i + 1, j + 1),
alive => mat(i, j));
end generate left;
middle:
if (i > 0 and i < X and j > 0 and j < Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => mat(i - 1, j - 1),
upper => mat(i, j - 1),
upper_right => mat(i + 1, j - 1),
left => mat(i - 1, j),
right => mat(i + 1, j),
lower_left => mat(i - 1, j + 1),
lower => mat(i, j + 1),
lower_right => mat(i + 1, j + 1),
alive => mat(i, j));
end generate middle;
right:
if (i = X and j > 0 and j < Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => mat(i - 1, j - 1),
upper => mat(i, j - 1),
upper_right => 0,
left => mat(i - 1, j),
right => 0,
lower_left => mat(i - 1, j + 1),
lower => mat(i, j + 1),
lower_right => 0,
alive => mat(i, j));
end generate right;
lower_left:
if (i = 0 and j = Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => mat(i, j - 1),
upper_right => mat(i + 1, j - 1),
left => 0,
right => mat(i + 1, j),
lower_left => 0,
lower => 0,
lower_right => 0,
alive => mat(i, j));
end generate lower_left;
lower:
if (i > 0 and i < X and j = Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => mat(i - 1, j - 1),
upper => mat(i, j - 1),
upper_right => mat(i + 1, j - 1),
left => mat(i - 1, j),
right => mat(i + 1, j),
lower_left => 0,
lower => 0,
lower_right => 0,
alive => mat(i, j));
end generate lower;
lower_right:
if (i = X and j = Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => mat(i - 1, j - 1),
upper => mat(i, j - 1),
upper_right => 0,
left => mat(i - 1, j),
right => 0,
lower_left => 0,
lower => 0,
lower_right => 0,
alive => mat(i, j));
end generate lower_right;
end generate inner;
end generate outer;
end arch;
| bsd-3-clause |
isaacloud/ace-builds | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/centre_index_memory_top.vhd | 1 | 6516 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: centre_index_memory_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity centre_index_memory_top is
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
item_read_twice : out std_logic;
item_address : out std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0)
);
end centre_index_memory_top;
architecture Behavioral of centre_index_memory_top is
constant CENTRE_INDEX_MEM_LAT : integer := 3;
constant CENTRE_LIST_BASE_ADDR_BITWIDTH : integer := CNTR_POINTER_BITWIDTH;
type state_type is (idle, write_write, write_read);
component centre_index_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0)
);
end component;
COMPONENT centre_index_trace_memory
PORT (
a : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH-1 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH-1 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
qdpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
signal state : state_type;
signal tmp_rd : std_logic;
signal rd_reg : std_logic;
signal wr_reg : std_logic;
signal rd_first_cl : std_logic;
signal rd_first_cl_reg : std_logic;
signal wr_first_cl : std_logic;
signal rd_addr_reg : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal rd_addr_reg_out : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal trace_mem_we : std_logic;
signal trace_mem_wr_addr : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal trace_mem_d : std_logic_vector(0 downto 0);
signal trace_mem_dout : std_logic_vector(0 downto 0);
signal trace_mem_dout_reg : std_logic;
signal trace_mem_dout_reg_out : std_logic;
begin
-- read address 0 corresponds is virtual
tmp_rd <= rd;--'0' WHEN addrb(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO INDEX_BITWIDTH) = std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) ELSE rd;
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= write_write;
elsif state = write_write AND rd_first_cl = '1' AND wr_first_cl = '1' then
state <= write_read;
elsif state = write_read then
state <= write_write;
end if;
end if;
end process fsm_proc;
input_latch_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rd_reg <= '0';
wr_reg <= '0';
rd_first_cl_reg <= '0';
else
rd_reg <= tmp_rd;
wr_reg <= wea(0);
rd_first_cl_reg <= rd_first_cl;
end if;
if rd_first_cl = '1' then
rd_addr_reg <= addrb(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH);
end if;
end if;
end process input_latch_proc;
rd_first_cl <= tmp_rd AND NOT(rd_reg);
wr_first_cl <= wea(0) AND NOT(wr_reg);
trace_mem_we <= '1' WHEN rd_first_cl = '1' OR wr_first_cl = '1' OR state = write_read ELSE '0';
trace_mem_wr_addr <= addra(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH) WHEN wr_first_cl = '1' ELSE
addrb(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH) WHEN wr_first_cl = '0' AND rd_first_cl = '1' ELSE
rd_addr_reg;
trace_mem_d(0) <= NOT(wr_first_cl);
centre_index_trace_memory_inst : centre_index_trace_memory
port map (
a => trace_mem_wr_addr,
d => trace_mem_d,
dpra => addrb(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH),
clk => clk,
we => trace_mem_we,
qdpo => trace_mem_dout
);
centre_index_memory_inst : centre_index_memory
port map (
clka => clk,
wea => wea,
addra => addra,
dina => dina,
clkb => clk,
addrb => addrb,
doutb => doutb
);
-- sample trace memory output in the right moment (2nd cycle)
sample_output_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
trace_mem_dout_reg <= '0';
else
if rd_first_cl_reg = '1' then
trace_mem_dout_reg <= trace_mem_dout(0);
end if;
end if;
rd_addr_reg_out <= rd_addr_reg;
trace_mem_dout_reg_out <= trace_mem_dout_reg;
end if;
end process sample_output_proc;
item_read_twice <= trace_mem_dout_reg_out;
item_address <= rd_addr_reg_out;
end Behavioral;
| bsd-3-clause |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/filtering_alogrithm_top.vhd | 1 | 17349 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_algorithm_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity filtering_alogrithm_top is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in par_node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic_vector(0 to PARALLEL_UNITS-1);
wr_node_address_init : in par_node_address_type;
wr_node_data_init : in par_node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end filtering_alogrithm_top;
architecture Behavioral of filtering_alogrithm_top is
type state_type is (phase_1_init, processing, readout, phase_2_init, gap_state1, reset_core, gap_state2, phase_2_start, done);
constant DIVIDER_II : integer := 2; --5;
component filtering_alogrithm_single
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- access centre buffer
rdo_centre_buffer : in std_logic;
centre_buffer_addr : in centre_index_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type;
-- processing done
rdy : out std_logic
);
end component;
component adder_tree
generic (
USE_DSP_FOR_ADD : boolean := true;
NUMBER_OF_INPUTS : integer := 4;
INPUT_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
input_string : in std_logic_vector(NUMBER_OF_INPUTS*INPUT_BITWIDTH-1 downto 0);
rdy : out std_logic;
output : out std_logic_vector(INPUT_BITWIDTH+integer(ceil(log2(real(NUMBER_OF_INPUTS))))-1 downto 0)
);
end component;
component divider_top
generic (
ROUND : boolean := false
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
dividend : in data_type_ext;
divisor : in coord_type;
rdy : out std_logic;
quotient : out data_type;
divide_by_zero : out std_logic
);
end component;
-- control
signal state : state_type;
signal single_sclr : std_logic;
signal single_start : std_logic;
signal readout_counter : centre_index_type;
signal readout_counter_done : std_logic;
signal readout_centre_buffers : std_logic;
signal init_counter : centre_index_type;
signal init_counter_done : std_logic;
signal divider_ii_counter : unsigned(integer(ceil(log2(real(DIVIDER_II))))-1 downto 0);
signal divider_ii_counter_done : std_logic;
signal iterations_counter : unsigned(integer(ceil(log2(real(L_MAX))))-1 downto 0);
signal iterations_counter_done : std_logic;
-- core input signals
signal mux_wr_init_cent : std_logic;
signal mux_wr_centre_list_address_init : centre_list_address_type;
signal mux_wr_centre_list_data_init : centre_index_type;
signal mux_wr_init_pos : std_logic;
signal mux_wr_centre_list_pos_address_init : centre_index_type;
signal mux_wr_centre_list_pos_data_init : data_type;
-- core output signals
signal tmp_valid : std_logic_vector(0 to PARALLEL_UNITS-1);
signal tmp_wgtCent_out : par_data_type_ext;
signal tmp_sum_sq_out : par_coord_type_ext;
signal tmp_count_out : par_coord_type;
signal tmp_rdy : std_logic_vector(0 to PARALLEL_UNITS-1);
signal reg_rdy : std_logic_vector(0 to PARALLEL_UNITS-1);
-- adder tree
signal at_input_string_count : std_logic_vector(PARALLEL_UNITS*COORD_BITWIDTH-1 downto 0);
signal at_count_rdy : std_logic;
signal at_count_out : std_logic_vector(COORD_BITWIDTH+integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
signal at_input_string_wgtCent : par_element_type_ext;
signal at_wgtCent_rdy : std_logic;
signal at_wgtCent_out : par_element_type_ext_sum;
signal tmp_wgtCent_out2 : data_type_ext;
signal at_input_string_sum_sq : std_logic_vector(PARALLEL_UNITS*COORD_BITWIDTH_EXT-1 downto 0);
signal at_sum_sq_rdy : std_logic;
signal at_sum_sq_out : std_logic_vector(COORD_BITWIDTH_EXT+integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
-- signals after tree reduction
signal divider_nd : std_logic;
signal divider_wgtCent_in : data_type_ext;
signal divider_count_in : coord_type;
signal comb_rdy : std_logic;
signal comb_valid : std_logic;
signal comb_sum_sq_out : coord_type_ext;
signal comb_new_position : data_type;
signal divide_by_zero : std_logic;
-- type coord_type_array is array(0 to 4) of coord_type;
-- constant test_input_dim0 : coord_type_array := (std_logic_vector(to_signed(-579,COORD_BITWIDTH)), std_logic_vector(to_signed(-878,COORD_BITWIDTH)), std_logic_vector(to_signed(290,COORD_BITWIDTH)), std_logic_vector(to_signed(358,COORD_BITWIDTH)), std_logic_vector(to_signed(0,COORD_BITWIDTH)));
-- constant test_input_dim1 : coord_type_array := (std_logic_vector(to_signed(-258,COORD_BITWIDTH)), std_logic_vector(to_signed(-396,COORD_BITWIDTH)), std_logic_vector(to_signed(-115,COORD_BITWIDTH)), std_logic_vector(to_signed(-723,COORD_BITWIDTH)), std_logic_vector(to_signed(0,COORD_BITWIDTH)));
-- signal test_input : data_type;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= phase_1_init;
elsif state = phase_1_init AND start = '1' then
state <= processing;
elsif state = processing AND comb_rdy = '1' then
state <= readout;
elsif state = readout AND readout_counter_done = '1' then
state <= phase_2_init;
elsif state = phase_2_init AND init_counter_done = '1' then
state <= gap_state1; -- 1 cycle
elsif state = gap_state1 then
state <= reset_core; -- we hope that the initialised blockram will not be flushed by this!!!
elsif state = reset_core then
state <= gap_state2; -- 1 cycle
elsif state = gap_state2 then
state <= phase_2_start; -- 1 cycle
elsif state = phase_2_start then
state <= processing; -- 1 cycle
end if;
end if;
end process fsm_proc;
single_sclr <= '1' WHEN sclr = '1' OR state = reset_core ELSE '0';
single_start <= '1' WHEN start = '1' OR state = phase_2_start ELSE '0';
readout_centre_buffers <= '1' WHEN state = readout AND divider_ii_counter = 0 ELSE '0';
counter_proc : process(clk)
begin
if rising_edge(clk) then
if state = processing OR divider_ii_counter_done = '1' then
divider_ii_counter <= (others => '0');
elsif state = readout then
divider_ii_counter <= divider_ii_counter + 1;
end if;
if state = processing then
readout_counter <= (others => '0');
elsif state = readout AND divider_ii_counter_done = '1' then
readout_counter <= readout_counter+1;
end if;
if state = processing then
init_counter <= (others => '0');
elsif comb_valid = '1' then
init_counter <= init_counter+1;
end if;
if sclr = '1' then
iterations_counter <= (others => '0');
elsif init_counter_done = '1' AND comb_valid = '1' then
iterations_counter <= iterations_counter+1;
end if;
end if;
end process counter_proc;
readout_counter_done <= '1' WHEN readout_counter = k ELSE '0';
init_counter_done <= '1' WHEN init_counter = k ELSE '0';
divider_ii_counter_done <= '1' WHEN divider_ii_counter = to_unsigned(DIVIDER_II-1,integer(ceil(log2(real(DIVIDER_II))))) ELSE '0';
iterations_counter_done <= '1' WHEN iterations_counter = to_unsigned(L_MAX-1,integer(ceil(log2(real(L_MAX))))) ELSE '0';
-- test_input(0) <= test_input_dim0(to_integer(init_counter));
-- test_input(1) <= test_input_dim1(to_integer(init_counter));
mux_wr_init_cent <= wr_init_cent; --needs to be written only once
mux_wr_centre_list_address_init <= std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH));
mux_wr_centre_list_data_init <= wr_centre_list_data_init; --needs to be written only once
mux_wr_init_pos <= wr_init_pos WHEN state = phase_1_init ELSE comb_valid AND NOT(divide_by_zero); -- do not update centre if count was zero
mux_wr_centre_list_pos_address_init <= wr_centre_list_pos_address_init WHEN state = phase_1_init ELSE init_counter;
mux_wr_centre_list_pos_data_init <= wr_centre_list_pos_data_init WHEN state = phase_1_init ELSE comb_new_position;
G_PAR_2 : for I in 0 to PARALLEL_UNITS-1 generate
filtering_alogrithm_single_inst : filtering_alogrithm_single
port map(
clk => clk,
sclr => single_sclr,
start => single_start,
-- initial parameters
k => k,
root_address => root_address(I),
-- init node and centre memory
wr_init_cent => mux_wr_init_cent,
wr_centre_list_address_init => mux_wr_centre_list_address_init,
wr_centre_list_data_init => mux_wr_centre_list_data_init,
wr_init_node => wr_init_node(I),
wr_node_address_init => wr_node_address_init(I),
wr_node_data_init => wr_node_data_init(I),
wr_init_pos => mux_wr_init_pos,
wr_centre_list_pos_address_init => mux_wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => mux_wr_centre_list_pos_data_init,
-- access centre buffer
rdo_centre_buffer => readout_centre_buffers,
centre_buffer_addr => readout_counter,
valid => tmp_valid(I),
wgtCent_out => tmp_wgtCent_out(I),
sum_sq_out => tmp_sum_sq_out(I),
count_out => tmp_count_out(I),
-- processing done
rdy => tmp_rdy(I)
);
at_input_string_count((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH) <= tmp_count_out(I);
at_input_string_sum_sq((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) <= tmp_sum_sq_out(I);
G_PAR_2_1 : for J in 0 to D-1 generate
at_input_string_wgtCent(J)((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) <= tmp_wgtCent_out(I)(J);
end generate G_PAR_2_1;
end generate G_PAR_2;
-- wait till all parallel units have asserted rdy signal
core_rdy_reg_proc : process(clk)
begin
if rising_edge(clk) then
if single_sclr = '1' then
reg_rdy <= (others => '0');
else
for I in 0 to PARALLEL_UNITS-1 loop
reg_rdy(I) <= tmp_rdy(I);
end loop;
end if;
end if;
end process core_rdy_reg_proc;
core_rdy_proc : process(reg_rdy)
variable var_rdy : std_logic;
begin
var_rdy := '1';
for I in 0 to PARALLEL_UNITS-1 loop
var_rdy := var_rdy AND reg_rdy(I);
end loop;
comb_rdy <= var_rdy;
end process core_rdy_proc;
-- tree adders
G_PAR_3 : if PARALLEL_UNITS > 1 generate
adder_tree_inst_count : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => PARALLEL_UNITS,
INPUT_BITWIDTH => COORD_BITWIDTH
)
port map(
clk => clk,
sclr => single_sclr,
nd => tmp_valid(0),
sub => '0',
input_string => at_input_string_count,
rdy => at_count_rdy,
output => at_count_out
);
G_PAR_3_1 : for J in 0 to D-1 generate
adder_tree_inst_wgtCent : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => PARALLEL_UNITS,
INPUT_BITWIDTH => COORD_BITWIDTH_EXT
)
port map(
clk => clk,
sclr => single_sclr,
nd => tmp_valid(0),
sub => '0',
input_string => at_input_string_wgtCent(J),
rdy => at_wgtCent_rdy,
output => at_wgtCent_out(J)
);
tmp_wgtCent_out2(J) <= at_wgtCent_out(J)(COORD_BITWIDTH_EXT-1 downto 0);
end generate G_PAR_3_1;
adder_tree_inst_sum_sq : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => PARALLEL_UNITS,
INPUT_BITWIDTH => COORD_BITWIDTH_EXT
)
port map(
clk => clk,
sclr => single_sclr,
nd => tmp_valid(0),
sub => '0',
input_string => at_input_string_sum_sq,
rdy => at_sum_sq_rdy,
output => at_sum_sq_out
);
divider_nd <= at_count_rdy;
divider_wgtCent_in <= tmp_wgtCent_out2;
divider_count_in <= at_count_out(COORD_BITWIDTH-1 downto 0);
comb_sum_sq_out <= at_sum_sq_out(COORD_BITWIDTH_EXT-1 downto 0);
end generate G_PAR_3;
G_PAR_4 : if PARALLEL_UNITS = 1 generate
divider_nd <= tmp_valid(0);
divider_wgtCent_in <= tmp_wgtCent_out(0);
divider_count_in <= tmp_count_out(0);
comb_sum_sq_out <= tmp_sum_sq_out(0);
end generate G_PAR_4;
divider_top_inst : divider_top
generic map (
ROUND => false
)
port map (
clk => clk,
sclr => sclr,
nd => divider_nd,
dividend => divider_wgtCent_in,
divisor => divider_count_in,
rdy => comb_valid,
quotient => comb_new_position,
divide_by_zero => divide_by_zero
);
-- TODO: accumulate comb_sum_sq_out and use it as a dynamic convergence criterion
valid <= comb_valid;
clusters_out <= comb_new_position;
distortion_out <= comb_sum_sq_out;
rdy <= iterations_counter_done AND init_counter_done AND comb_valid;
end Behavioral;
| bsd-3-clause |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/dsp_round.vhd | 1 | 5627 | ----------------------------------------------------------------------------------
-- Company: ESA
-- Engineer: Felix Winterstein
--
-- Create Date: 06.04.2013 21:02:35
-- Design Name:
-- Module Name: dsp_round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dsp_round is
generic (
BITWIDTH_IN : integer := 32;
BITWIDTH_OUT : integer := 32
);
port (
sclr : in std_logic;
nd : in std_logic;
AB_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
CARRYIN_IN : in std_logic;
CLK_IN : in std_logic;
C_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
P_OUT : out std_logic_vector (BITWIDTH_OUT-1 downto 0);
rdy : out std_logic
);
end dsp_round;
architecture BEHAVIORAL of dsp_round is
constant LAT : integer := 2;
signal GND_ALUMODE : std_logic;
signal GND_BUS_3 : std_logic_vector (2 downto 0);
signal GND_BUS_18 : std_logic_vector (17 downto 0);
signal GND_BUS_30 : std_logic_vector (29 downto 0);
signal GND_BUS_48 : std_logic_vector (47 downto 0);
signal GND_OPMODE : std_logic;
signal VCC_OPMODE : std_logic;
signal ab_in_ext : std_logic_vector(47 downto 0);
signal c_in_ext : std_logic_vector(47 downto 0);
signal p_out_ext : std_logic_vector(47 downto 0);
signal delay_line : std_logic_vector(0 to LAT-1);
begin
GND_ALUMODE <= '0';
GND_BUS_3(2 downto 0) <= "000";
GND_BUS_18(17 downto 0) <= "000000000000000000";
GND_BUS_30(29 downto 0) <= "000000000000000000000000000000";
GND_BUS_48(47 downto 0) <=
"000000000000000000000000000000000000000000000000";
GND_OPMODE <= '0';
VCC_OPMODE <= '1';
ab_in_ext(47 downto BITWIDTH_IN) <= (others => AB_IN(BITWIDTH_IN-1));
ab_in_ext(BITWIDTH_IN-1 downto 0) <= AB_IN;
c_in_ext(47 downto BITWIDTH_IN) <= (others => C_IN(BITWIDTH_IN-1));
c_in_ext(BITWIDTH_IN-1 downto 0) <= C_IN;
DSP48E_INST : DSP48E
generic map( ACASCREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATTERN_DETECT => FALSE,
AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 1,
CARRYINSELREG => 0,
CREG => 1,
MASK => x"3FFFFFFFFFFF",
MREG => 1,
MULTCARRYINREG => 1,
OPMODEREG => 0,
PATTERN => x"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
SEL_ROUNDING_MASK => "SEL_MASK",
USE_MULT => "NONE",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48")
port map (A(29 downto 0)=>ab_in_ext(47 downto 18),
ACIN(29 downto 0)=>GND_BUS_30(29 downto 0),
ALUMODE(3)=>GND_ALUMODE,
ALUMODE(2)=>GND_ALUMODE,
ALUMODE(1)=>GND_ALUMODE,
ALUMODE(0)=>GND_ALUMODE,
B(17 downto 0)=>ab_in_ext(17 downto 0),
BCIN(17 downto 0)=>GND_BUS_18(17 downto 0),
C(47 downto 0)=>c_in_ext(47 downto 0),
CARRYCASCIN=>GND_ALUMODE,
CARRYIN=>CARRYIN_IN,
CARRYINSEL(2 downto 0)=>GND_BUS_3(2 downto 0),
CEALUMODE=>VCC_OPMODE,
CEA1=>VCC_OPMODE,
CEA2=>VCC_OPMODE,
CEB1=>VCC_OPMODE,
CEB2=>VCC_OPMODE,
CEC=>VCC_OPMODE,
CECARRYIN=>VCC_OPMODE,
CECTRL=>VCC_OPMODE,
CEM=>VCC_OPMODE,
CEMULTCARRYIN=>VCC_OPMODE,
CEP=>VCC_OPMODE,
CLK=>CLK_IN,
MULTSIGNIN=>GND_ALUMODE,
OPMODE(6)=>GND_OPMODE,
OPMODE(5)=>VCC_OPMODE,
OPMODE(4)=>VCC_OPMODE,
OPMODE(3)=>GND_OPMODE,
OPMODE(2)=>GND_OPMODE,
OPMODE(1)=>VCC_OPMODE,
OPMODE(0)=>VCC_OPMODE,
PCIN(47 downto 0)=>GND_BUS_48(47 downto 0),
RSTA=>GND_ALUMODE,
RSTALLCARRYIN=>GND_ALUMODE,
RSTALUMODE=>GND_ALUMODE,
RSTB=>GND_ALUMODE,
RSTC=>GND_ALUMODE,
RSTCTRL=>GND_ALUMODE,
RSTM=>GND_ALUMODE,
RSTP=>GND_ALUMODE,
ACOUT=>open,
BCOUT=>open,
CARRYCASCOUT=>open,
CARRYOUT=>open,
MULTSIGNOUT=>open,
OVERFLOW=>open,
P(47 downto 0)=>p_out_ext(47 downto 0),
PATTERNBDETECT=>open,
PATTERNDETECT=>open,
PCOUT=>open,
UNDERFLOW=>open);
P_OUT <= p_out_ext(BITWIDTH_IN-1 downto BITWIDTH_IN-BITWIDTH_OUT);
delay_line_proc : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to LAT-1) <= delay_line(0 to LAT-2);
end if;
end if;
end process delay_line_proc;
rdy <= delay_line(LAT-1);
end BEHAVIORAL;
| bsd-3-clause |
seyedmaysamlavasani/GorillaPP | apps/lib/floatingPoints/common/ieee_FP_pkg/fixed_pkg_c.vhd | 2 | 302591 | -- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers
-- synthesis tools. Please note the "%%%" comments. These are where we
-- diverge from the VHDL-200X LRM.
-- --------------------------------------------------------------------
-- Version : $Revision: 1.22 $
-- Date : $Date: 2010/09/22 18:34:14 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.fixed_float_types.all;
package fixed_pkg is
-- generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
constant fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
constant fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
constant fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop (dbishop@vhdl.org)
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
subtype U_ufixed is UNRESOLVED_ufixed;
subtype U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is UNRESOLVED_ufixed;
subtype sfixed is UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- rtl_synthesis off
-- pragma synthesis_off
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
end package fixed_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT fixed_pkg package
-- (Fixed point math package)
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 1.22 $
-- Date : $Date: 2010/09/22 18:34:14 $
--
-- Created for VHDL-200X-ft, David Bishop (dbishop@vhdl.org)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_pkg is
-- Author David Bishop (dbishop@vhdl.org)
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- %%% Replicated functions
function maximum (
l, r : integer) -- inputs
return integer is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : integer) -- inputs
return integer is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- Id: M.3B
function \?=\ (L, R: SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
result := 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function \?/=\ (L, R : SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report fixed_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reduce (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report fixed_pkg'instance_name
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-- End reduction operator_reduces
function \?=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
function \?=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
-- variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report fixed_pkg'instance_name
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reduce(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or_reduce (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or_reduce (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- rtl_synthesis off
-- pragma synthesis_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- %%% Replicated Textio functions
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-- %%% END replicated textio functions
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "OREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: Routines common to the OREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "HREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report fixed_pkg'instance_name
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report fixed_pkg'instance_name
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
-- pragma synthesis_on
-- rtl_synthesis on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
begin
return to_UFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
begin
return to_SFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_SFix;
end package body fixed_pkg;
| bsd-3-clause |
antmicro/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/example_design/system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd | 3 | 5689 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
signal clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_3 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-3-clause |
antmicro/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth.vhd | 3 | 11564 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 34,
C_DOUT_WIDTH => 34,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 34,
C_DIN_WIDTH => 34,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 34,
C_DIN_WIDTH => 34,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_1_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-3-clause |
antmicro/parallella-lcd-fpga | system/pcores/axi_dispctrl_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 24604 | --------------------------------------------------------------------------------
--
-- File:
-- user_logic.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author(s):
-- Sam Bobrowicz
-- Karol Gugala <kgugala@antmicro.com>
--
-- Description:
-- Wrapper for AXI Display Controller
--
-- Additional Notes:
-- TODO - 1) Add Parameter to select whether to use a PLL or MMCM
-- 2) Add Parameter to use external pixel clock (no MMCM or PLL)
-- 3) Add Hot-plug detect and EDID control, selectable with parameter
-- 4) Add feature detect register, for determining enabled parameters from software
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_TDATA_WIDTH : integer := 32; --must be 32
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 13;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
COMPONENT mmcme2_drp
GENERIC(
DIV_F : integer
);
PORT(
SEN : IN std_logic;
SCLK : IN std_logic;
RST : IN std_logic;
S1_CLKOUT0 : IN std_logic_vector(35 downto 0);
S1_CLKFBOUT : IN std_logic_vector(35 downto 0);
S1_DIVCLK : IN std_logic_vector(13 downto 0);
S1_LOCK : IN std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : IN std_logic_vector(9 downto 0);
REF_CLK : IN std_logic;
SRDY : OUT std_logic;
PXL_CLK : OUT std_logic;
PXL_CLK_INV : OUT std_logic;
CLKFBOUT_O : OUT std_logic;
CLKFBOUT_I : IN std_logic;
LOCKED_O : OUT std_logic
);
END COMPONENT;
COMPONENT vdma_to_vga
GENERIC(
C_RED_WIDTH : integer;
C_GREEN_WIDTH : integer;
C_BLUE_WIDTH : integer;
C_S_AXIS_TDATA_WIDTH : integer
);
PORT(
LOCKED_I : IN std_logic;
ENABLE_I : IN std_logic;
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
USR_WIDTH_I : IN std_logic_vector(11 downto 0);
USR_HEIGHT_I : IN std_logic_vector(11 downto 0);
USR_HPS_I : IN std_logic_vector(11 downto 0);
USR_HPE_I : IN std_logic_vector(11 downto 0);
USR_HPOL_I : IN std_logic;
USR_HMAX_I : IN std_logic_vector(11 downto 0);
USR_VPS_I : IN std_logic_vector(11 downto 0);
USR_VPE_I : IN std_logic_vector(11 downto 0);
USR_VPOL_I : IN std_logic;
USR_VMAX_I : IN std_logic_vector(11 downto 0);
RUNNING_O : OUT std_logic;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR (C_RED_WIDTH-1 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (C_GREEN_WIDTH-1 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0)
);
END COMPONENT;
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, WAIT_RUN, ENABLED, WAIT_FRAME_DONE);
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal mmcm_clk_inv : std_logic;
signal pxl_clk : std_logic;
signal pxl_clk_inv : std_logic;
signal pxl_clk_inv5x : std_logic;
signal locked : std_logic;
signal locked_n : std_logic;
signal srdy : std_logic;
signal enable_reg : std_logic := '0';
signal sen_reg : std_logic := '0';
signal vga_running : std_logic;
signal clk_state : CLK_STATE_TYPE := RESET;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal CTRL_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal STAT_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal FRAME_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_O_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FB_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FRAC_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_DIV_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_LOCK_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FLTR_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal slv_reg_write_sel : std_logic_vector(12 downto 0);
signal slv_reg_read_sel : std_logic_vector(12 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 = 1 generate
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => mmcm_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => mmcm_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFG_inst: BUFG port map(
O => pxl_clk_inv5x, -- 1-bit output: Clock output port
I => mmcm_clk_inv -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFR_inst_inv : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output port
CE => enable_reg, -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => pxl_clk_inv5x -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
locked_n <= not(locked);
ENABLE_O <= enable_reg;
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
DONT_USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 /= 1 generate
PXL_CLK_5X_O <= '0';
BUFG_inst : BUFG
port map (
O => pxl_clk, -- 1-bit output: Clock output
I => mmcm_clk -- 1-bit input: Clock input
);
BUFG_inst_inv : BUFG
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output
I => mmcm_clk_inv -- 1-bit input: Clock input
);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 10
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
pxl_clk_mux: BUFGMUX
port map (
O => PXL_CLK_O, -- 1-bit output: Clock output
I0 => pxl_clk, -- 1-bit input: Clock input (S=0)
I1 => pxl_clk_inv, -- 1-bit input: Clock input (S=1)
S => CTRL_REG(1) -- 1-bit input: Clock select
);
VDMA_CLK_O <= pxl_clk;
LOCKED_O <= locked;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED => --This state ensures that the initial SRDY pulse doesnt interfere with the WAIT_SRDY state
if (locked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= WAIT_RUN;
end if;
when WAIT_RUN =>
if (STAT_REG(0) = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_FRAME_DONE;
end if;
when WAIT_FRAME_DONE =>
if (STAT_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
enable_reg <= '0';
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
if (clk_state = WAIT_RUN or clk_state = ENABLED) then
enable_reg <= '1';
else
enable_reg <= '0';
end if;
end if;
end if;
end process;
Inst_vdma_to_vga: vdma_to_vga
GENERIC MAP(
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH
)
PORT MAP(
LOCKED_I => locked,
ENABLE_I => enable_reg,
RUNNING_O => vga_running,
S_AXIS_ACLK => pxl_clk,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
DEBUG_O => DEBUG_O,
BLUE_O => BLUE_O,
USR_WIDTH_I => FRAME_REG(27 downto 16),
USR_HEIGHT_I => FRAME_REG(11 downto 0),
USR_HPS_I => HPARAM1_REG(27 downto 16),
USR_HPE_I => HPARAM1_REG(11 downto 0),
USR_HPOL_I => HPARAM2_REG(16),
USR_HMAX_I => HPARAM2_REG(11 downto 0),
USR_VPS_I => VPARAM1_REG(27 downto 16),
USR_VPE_I => VPARAM1_REG(11 downto 0),
USR_VPOL_I => VPARAM2_REG(16),
USR_VMAX_I => VPARAM2_REG(11 downto 0)
);
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
STAT_REG(0) <= '0';
else
STAT_REG(0) <= vga_running;
end if;
end if;
end process;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(12 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(12 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
CTRL_REG <= (others => '0');
--STAT_REG <= (others => '0');
FRAME_REG <= (others => '0');
HPARAM1_REG <= (others => '0');
HPARAM2_REG <= (others => '0');
VPARAM1_REG <= (others => '0');
VPARAM2_REG <= (others => '0');
CLK_O_REG <= (others => '0');
CLK_FB_REG <= (others => '0');
CLK_FRAC_REG <= (others => '0');
CLK_DIV_REG <= (others => '0');
CLK_LOCK_REG <= (others => '0');
CLK_FLTR_REG <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CTRL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
--***Status register is read only***
-- when "0100000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- STAT_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "0010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
FRAME_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_O_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FB_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FRAC_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_DIV_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_LOCK_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FLTR_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, CTRL_REG, STAT_REG, FRAME_REG, HPARAM1_REG, HPARAM2_REG, VPARAM1_REG, VPARAM2_REG, CLK_O_REG, CLK_FB_REG, CLK_FRAC_REG, CLK_DIV_REG, CLK_LOCK_REG, CLK_FLTR_REG ) is
begin
case slv_reg_read_sel is
when "1000000000000" => slv_ip2bus_data <= CTRL_REG;
when "0100000000000" => slv_ip2bus_data <= STAT_REG;
when "0010000000000" => slv_ip2bus_data <= FRAME_REG;
when "0001000000000" => slv_ip2bus_data <= HPARAM1_REG;
when "0000100000000" => slv_ip2bus_data <= HPARAM2_REG;
when "0000010000000" => slv_ip2bus_data <= VPARAM1_REG;
when "0000001000000" => slv_ip2bus_data <= VPARAM2_REG;
when "0000000100000" => slv_ip2bus_data <= CLK_O_REG;
when "0000000010000" => slv_ip2bus_data <= CLK_FB_REG;
when "0000000001000" => slv_ip2bus_data <= CLK_FRAC_REG;
when "0000000000100" => slv_ip2bus_data <= CLK_DIV_REG;
when "0000000000010" => slv_ip2bus_data <= CLK_LOCK_REG;
when "0000000000001" => slv_ip2bus_data <= CLK_FLTR_REG;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause |
antmicro/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.vhd | 3 | 11785 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg;
PACKAGE BODY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg;
| bsd-3-clause |
janblo/gaia-ace-builds | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
alexbarnsley/ace | ace-build/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
parallella/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/example_design/system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd | 3 | 5689 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
signal clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_3 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-3-clause |
parallella/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth.vhd | 3 | 11564 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 34,
C_DOUT_WIDTH => 34,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 34,
C_DIN_WIDTH => 34,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 34,
C_DIN_WIDTH => 34,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_1_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-3-clause |
parallella/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif.vhd | 4 | 5686 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| bsd-3-clause |
fjakobs/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
parallella/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth.vhd | 3 | 11096 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(67-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(67-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(67-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(67-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 67,
C_DOUT_WIDTH => 67,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 67,
C_DIN_WIDTH => 67,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 67,
C_DIN_WIDTH => 67,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_3_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-3-clause |
parallella/parallella-lcd-fpga | system/hdl/system_stub.vhd | 3 | 6782 | -------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
axi_dispctrl_0_HSYNC_O_pin => axi_dispctrl_0_HSYNC_O_pin,
axi_dispctrl_0_VSYNC_O_pin => axi_dispctrl_0_VSYNC_O_pin,
axi_dispctrl_0_PXL_CLK_O_pin => axi_dispctrl_0_PXL_CLK_O_pin,
axi_dispctrl_0_DE_O_pin => axi_dispctrl_0_DE_O_pin,
axi_dispctrl_0_RED_O_pin => axi_dispctrl_0_RED_O_pin,
axi_dispctrl_0_GREEN_O_pin => axi_dispctrl_0_GREEN_O_pin,
axi_dispctrl_0_BLUE_O_pin => axi_dispctrl_0_BLUE_O_pin,
axi_dispctrl_0_ENABLE_O_pin => axi_dispctrl_0_ENABLE_O_pin,
processing_system7_0_I2C0_SDA_pin => processing_system7_0_I2C0_SDA_pin,
processing_system7_0_I2C0_SCL_pin => processing_system7_0_I2C0_SCL_pin,
processing_system7_0_I2C0_INT_N_pin => processing_system7_0_I2C0_INT_N_pin,
processing_system7_0_FCLK_CLK0_pin => processing_system7_0_FCLK_CLK0_pin
);
end architecture STRUCTURE;
| bsd-3-clause |
STRd6/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
inforichland/freezing-spice | src/dpram.vhd | 1 | 2666 | -- Based on the Quartus II VHDL Template for True Dual-Port RAM with single clock
-- Read-during-write on port A or B returns newly written data
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_textio.all;
use work.std_logic_textio.all;
use std.textio.all;
entity dpram is
generic(g_data_width : natural := 16;
g_addr_width : natural := 10;
g_init : boolean := false;
g_init_file : string := "");
port(clk : in std_logic;
addr_a : in std_logic_vector(g_addr_width-1 downto 0);
addr_b : in std_logic_vector(g_addr_width-1 downto 0);
data_a : in std_logic_vector((g_data_width-1) downto 0);
data_b : in std_logic_vector((g_data_width-1) downto 0);
we_a : in std_logic := '1';
we_b : in std_logic := '1';
q_a : out std_logic_vector((g_data_width -1) downto 0);
q_b : out std_logic_vector((g_data_width -1) downto 0));
end dpram;
architecture rtl of dpram is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((g_data_width-1) downto 0);
type ram_t is array(0 to 2**g_addr_width-1) of word_t;
-- function to initialize the RAM from a file
impure function init_ram(fn : in string) return ram_t is
file f : text;
variable l : line;
variable ram : ram_t;
begin
if g_init = true then
file_open(f, fn, READ_MODE);
for i in ram_t'range loop
readline(f, l);
read(l, ram(i));
end loop;
file_close(f);
else
ram := (others => (others => '0'));
end if;
return ram;
end function;
-- Declare the RAM
shared variable ram : ram_t := init_ram(g_init_file); --(others => (others => '0'));
begin
-- Port A
process (clk)
variable addr : natural range 0 to 2**g_addr_width-1;
begin
if (rising_edge(clk)) then
addr := to_integer(unsigned(addr_a));
if (we_a = '1') then
ram(addr) := data_a;
end if;
q_a <= ram(addr);
end if;
end process;
-- Port B
process (clk)
variable addr : natural range 0 to 2**g_addr_width-1;
begin
if (rising_edge(clk)) then
addr := to_integer(unsigned(addr_b));
if (we_b = '1') then
ram(addr) := data_b;
end if;
q_b <= ram(addr);
end if;
end process;
end rtl;
| bsd-3-clause |
inforichland/freezing-spice | tests/pipeline_tb.vhd | 1 | 5955 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.common.all;
use work.id_pkg.all;
use work.encode_pkg.all;
use work.test_config.all;
entity pipeline_tb is
end entity pipeline_tb;
architecture testbench of pipeline_tb is
signal clk : std_logic := '0';
signal rst_n : std_logic := '1';
-- inputs
signal insn_in : word := (others => '0');
signal insn_addr : word := (others => '0');
signal insn_valid : std_logic := '0';
-- shift registers to simulate delays in accessing memory
constant c_data_in_delay : integer := 4; -- number of delay cycles for memory reads
type data_in_sr_t is array (0 to c_data_in_delay - 1) of std_logic_vector(31 downto 0); --word;
type data_in_valid_sr_t is array (0 to c_data_in_delay - 1) of std_logic;
signal data_in : data_in_sr_t := (others => (others => '0'));
signal data_in_valid : data_in_valid_sr_t := (others => '0');
signal data_valid : std_logic;
-- outputs
signal data_write_en : std_logic;
signal data_read_en : std_logic;
signal data_addr : word;
signal data_out : word;
-- simulation specific
signal done : boolean := false;
constant clk_period : time := 10 ns; -- 100 MHz
file memfile : text open write_mode is "sim/memio.vec";
-- data memory
type ram_t is array(0 to 100) of word;
signal ram : ram_t := (0 => X"80008081",
others => (others => '0'));
begin
instruction_memory : entity work.dpram(rtl)
generic map (g_data_width => 32,
g_addr_width => 8,
g_init => true,
g_init_file => pipeline_tb_test_vector_input_filename)
port map (clk => clk,
addr_a => insn_addr(7 downto 0),
data_a => (others => '0'),
we_a => '0',
q_a => insn_in,
addr_b => (others => '0'),
data_b => (others => '0'),
we_b => '0',
q_b => open);
-- create a clock
clk <= '0' when done else (not clk) after clk_period / 2;
-- purpose: data memory
ram_proc : process (clk, rst_n) is
variable addr : integer;
variable valid : std_logic;
begin
if rst_n = '0' then
reset_shift_regs : for i in data_in'range loop
data_in(i) <= (others => '0');
data_in_valid(i) <= '0';
end loop reset_shift_regs;
elsif rising_edge(clk) then
-- default values
data_in_valid(0) <= '0';
data_in(0) <= (others => '0');
-- create shift registers
shift_regs : for i in 1 to data_in'high loop
data_in(i) <= data_in(i - 1);
data_in_valid(i) <= data_in_valid(i - 1);
end loop shift_regs;
if ((data_in_valid(data_in_valid'high) = '0')
and (data_in_valid(data_in_valid'high - 1) = '1')) then
valid := '1';
else
valid := '0';
end if;
data_valid <= valid;
-- writes/reads
addr := to_integer(unsigned(data_addr));
if data_write_en = '1' then
ram(addr) <= data_out;
elsif data_read_en = '1' then
data_in(0) <= ram(addr);
data_in_valid(0) <= '1';
end if;
end if;
end process ram_proc;
---------------------------------------------------
-- print memory bus transactions
---------------------------------------------------
log_memio_proc : process (data_write_en, data_read_en, data_valid, clk) is
variable l : line;
begin -- process log_memio_proc
if data_write_en = '1' and clk = '0' then
write(l, string'("W "));
write(l, hstr(data_addr));
write(l, string'(", "));
write(l, hstr(data_out));
writeline(memfile, l);
end if;
if (data_valid = '1' and clk = '0') then
write(l, string'("R "));
write(l, hstr(data_addr));
write(l, string'(", "));
write(l, hstr(data_in(data_in'high)));
writeline(memfile, l);
end if;
end process log_memio_proc;
-- instantiate the unit under test
uut : entity work.pipeline(Behavioral)
generic map (
g_initial_pc => (others => '0'),
g_for_sim => true)
port map (
clk => clk,
rst_n => rst_n,
insn_in => insn_in,
insn_addr => insn_addr,
insn_valid => insn_valid,
data_in => data_in(data_in'high),
data_out => data_out,
data_addr => data_addr,
data_write_en => data_write_en,
data_read_en => data_read_en,
data_in_valid => data_valid);
-- purpose: Provide stimulus to test the pipeline
stimulus_proc : process is
variable i : natural := 0;
begin -- process stimulus_proc
-- reset sequence
println ("Beginning simulation");
-- fill up the instruction memory
rst_n <= '0';
wait for clk_period * 2;
rst_n <= '1';
-- begin stimulus
wait for clk_period;
insn_valid <= '1';
-- run for a bit.
wait for clk_period * 35;
-- finished with simulation
----------------------------------------------------------------
println("Simulation complete");
----------------------------------------------------------------
done <= true;
wait;
end process stimulus_proc;
end architecture testbench;
| bsd-3-clause |
makelivedotnet/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
alemedeiros/flappy_vhdl | modules/input_pack.vhd | 1 | 1019 | -- file: modules/input_pack.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
library ieee ;
use ieee.std_logic_1164.all ;
package input is
-- Parses input signals from switches and keys and attributes the adequate
-- values to the internal signals.
component input_parser
generic (
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
key : in std_logic_vector(3 downto 0) ;
sw : in std_logic_vector(9 downto 0) ;
jump : out std_logic ;
reset : out std_logic ;
pause : out std_logic ;
gravity : out integer range 0 to V_RES - 1
) ;
end component ;
-- Divides 27MHz clock into adequate clock value
component clock_divider
generic (
RATE : natural := 270000
) ;
port (
clk_in : in std_logic ;
clk_out : out std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end component ;
end input ;
| bsd-3-clause |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl.vhd | 3 | 15657 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| bsd-3-clause |
kennethlyn/parallella-lcd-fpga | system/pcores/axi_dispctrl_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 24604 | --------------------------------------------------------------------------------
--
-- File:
-- user_logic.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author(s):
-- Sam Bobrowicz
-- Karol Gugala <kgugala@antmicro.com>
--
-- Description:
-- Wrapper for AXI Display Controller
--
-- Additional Notes:
-- TODO - 1) Add Parameter to select whether to use a PLL or MMCM
-- 2) Add Parameter to use external pixel clock (no MMCM or PLL)
-- 3) Add Hot-plug detect and EDID control, selectable with parameter
-- 4) Add feature detect register, for determining enabled parameters from software
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_TDATA_WIDTH : integer := 32; --must be 32
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 13;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
COMPONENT mmcme2_drp
GENERIC(
DIV_F : integer
);
PORT(
SEN : IN std_logic;
SCLK : IN std_logic;
RST : IN std_logic;
S1_CLKOUT0 : IN std_logic_vector(35 downto 0);
S1_CLKFBOUT : IN std_logic_vector(35 downto 0);
S1_DIVCLK : IN std_logic_vector(13 downto 0);
S1_LOCK : IN std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : IN std_logic_vector(9 downto 0);
REF_CLK : IN std_logic;
SRDY : OUT std_logic;
PXL_CLK : OUT std_logic;
PXL_CLK_INV : OUT std_logic;
CLKFBOUT_O : OUT std_logic;
CLKFBOUT_I : IN std_logic;
LOCKED_O : OUT std_logic
);
END COMPONENT;
COMPONENT vdma_to_vga
GENERIC(
C_RED_WIDTH : integer;
C_GREEN_WIDTH : integer;
C_BLUE_WIDTH : integer;
C_S_AXIS_TDATA_WIDTH : integer
);
PORT(
LOCKED_I : IN std_logic;
ENABLE_I : IN std_logic;
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
USR_WIDTH_I : IN std_logic_vector(11 downto 0);
USR_HEIGHT_I : IN std_logic_vector(11 downto 0);
USR_HPS_I : IN std_logic_vector(11 downto 0);
USR_HPE_I : IN std_logic_vector(11 downto 0);
USR_HPOL_I : IN std_logic;
USR_HMAX_I : IN std_logic_vector(11 downto 0);
USR_VPS_I : IN std_logic_vector(11 downto 0);
USR_VPE_I : IN std_logic_vector(11 downto 0);
USR_VPOL_I : IN std_logic;
USR_VMAX_I : IN std_logic_vector(11 downto 0);
RUNNING_O : OUT std_logic;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR (C_RED_WIDTH-1 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (C_GREEN_WIDTH-1 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0)
);
END COMPONENT;
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, WAIT_RUN, ENABLED, WAIT_FRAME_DONE);
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal mmcm_clk_inv : std_logic;
signal pxl_clk : std_logic;
signal pxl_clk_inv : std_logic;
signal pxl_clk_inv5x : std_logic;
signal locked : std_logic;
signal locked_n : std_logic;
signal srdy : std_logic;
signal enable_reg : std_logic := '0';
signal sen_reg : std_logic := '0';
signal vga_running : std_logic;
signal clk_state : CLK_STATE_TYPE := RESET;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal CTRL_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal STAT_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal FRAME_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_O_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FB_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FRAC_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_DIV_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_LOCK_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FLTR_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal slv_reg_write_sel : std_logic_vector(12 downto 0);
signal slv_reg_read_sel : std_logic_vector(12 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 = 1 generate
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => mmcm_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => mmcm_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFG_inst: BUFG port map(
O => pxl_clk_inv5x, -- 1-bit output: Clock output port
I => mmcm_clk_inv -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFR_inst_inv : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output port
CE => enable_reg, -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => pxl_clk_inv5x -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
locked_n <= not(locked);
ENABLE_O <= enable_reg;
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
DONT_USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 /= 1 generate
PXL_CLK_5X_O <= '0';
BUFG_inst : BUFG
port map (
O => pxl_clk, -- 1-bit output: Clock output
I => mmcm_clk -- 1-bit input: Clock input
);
BUFG_inst_inv : BUFG
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output
I => mmcm_clk_inv -- 1-bit input: Clock input
);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 10
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
pxl_clk_mux: BUFGMUX
port map (
O => PXL_CLK_O, -- 1-bit output: Clock output
I0 => pxl_clk, -- 1-bit input: Clock input (S=0)
I1 => pxl_clk_inv, -- 1-bit input: Clock input (S=1)
S => CTRL_REG(1) -- 1-bit input: Clock select
);
VDMA_CLK_O <= pxl_clk;
LOCKED_O <= locked;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED => --This state ensures that the initial SRDY pulse doesnt interfere with the WAIT_SRDY state
if (locked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= WAIT_RUN;
end if;
when WAIT_RUN =>
if (STAT_REG(0) = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_FRAME_DONE;
end if;
when WAIT_FRAME_DONE =>
if (STAT_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
enable_reg <= '0';
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
if (clk_state = WAIT_RUN or clk_state = ENABLED) then
enable_reg <= '1';
else
enable_reg <= '0';
end if;
end if;
end if;
end process;
Inst_vdma_to_vga: vdma_to_vga
GENERIC MAP(
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH
)
PORT MAP(
LOCKED_I => locked,
ENABLE_I => enable_reg,
RUNNING_O => vga_running,
S_AXIS_ACLK => pxl_clk,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
DEBUG_O => DEBUG_O,
BLUE_O => BLUE_O,
USR_WIDTH_I => FRAME_REG(27 downto 16),
USR_HEIGHT_I => FRAME_REG(11 downto 0),
USR_HPS_I => HPARAM1_REG(27 downto 16),
USR_HPE_I => HPARAM1_REG(11 downto 0),
USR_HPOL_I => HPARAM2_REG(16),
USR_HMAX_I => HPARAM2_REG(11 downto 0),
USR_VPS_I => VPARAM1_REG(27 downto 16),
USR_VPE_I => VPARAM1_REG(11 downto 0),
USR_VPOL_I => VPARAM2_REG(16),
USR_VMAX_I => VPARAM2_REG(11 downto 0)
);
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
STAT_REG(0) <= '0';
else
STAT_REG(0) <= vga_running;
end if;
end if;
end process;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(12 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(12 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
CTRL_REG <= (others => '0');
--STAT_REG <= (others => '0');
FRAME_REG <= (others => '0');
HPARAM1_REG <= (others => '0');
HPARAM2_REG <= (others => '0');
VPARAM1_REG <= (others => '0');
VPARAM2_REG <= (others => '0');
CLK_O_REG <= (others => '0');
CLK_FB_REG <= (others => '0');
CLK_FRAC_REG <= (others => '0');
CLK_DIV_REG <= (others => '0');
CLK_LOCK_REG <= (others => '0');
CLK_FLTR_REG <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CTRL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
--***Status register is read only***
-- when "0100000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- STAT_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "0010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
FRAME_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_O_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FB_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FRAC_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_DIV_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_LOCK_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FLTR_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, CTRL_REG, STAT_REG, FRAME_REG, HPARAM1_REG, HPARAM2_REG, VPARAM1_REG, VPARAM2_REG, CLK_O_REG, CLK_FB_REG, CLK_FRAC_REG, CLK_DIV_REG, CLK_LOCK_REG, CLK_FLTR_REG ) is
begin
case slv_reg_read_sel is
when "1000000000000" => slv_ip2bus_data <= CTRL_REG;
when "0100000000000" => slv_ip2bus_data <= STAT_REG;
when "0010000000000" => slv_ip2bus_data <= FRAME_REG;
when "0001000000000" => slv_ip2bus_data <= HPARAM1_REG;
when "0000100000000" => slv_ip2bus_data <= HPARAM2_REG;
when "0000010000000" => slv_ip2bus_data <= VPARAM1_REG;
when "0000001000000" => slv_ip2bus_data <= VPARAM2_REG;
when "0000000100000" => slv_ip2bus_data <= CLK_O_REG;
when "0000000010000" => slv_ip2bus_data <= CLK_FB_REG;
when "0000000001000" => slv_ip2bus_data <= CLK_FRAC_REG;
when "0000000000100" => slv_ip2bus_data <= CLK_DIV_REG;
when "0000000000010" => slv_ip2bus_data <= CLK_LOCK_REG;
when "0000000000001" => slv_ip2bus_data <= CLK_FLTR_REG;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause |
alemedeiros/flappy_vhdl | modules/nbit_register_pack.vhd | 1 | 769 | -- file: nbit_register_pack.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- Solution to MC613 - Lab06.Q2.A
--
-- This package contains the following components:
--
-- * nbit_register:
-- A n bit register
library ieee ;
use ieee.std_logic_1164.all ;
package nbit_register_pack is
component nbit_register
generic ( n : integer := 8) ;
port ( x : in std_logic_vector (n-1 downto 0) ; -- Load input
y : out std_logic_vector (n-1 downto 0) ; -- Stored value
ld : in std_logic ; -- Load control bit
clr : in std_logic ; -- Clear control bit
clk : in std_logic -- Clock
) ;
end component ;
end nbit_register_pack ;
| bsd-3-clause |
enricoberti/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/MurmurHash_SearchBRAMImplementation.vhdl | 1 | 1950 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
entity BinarySearchBRAM is
generic(
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 10
);
port(
clk : in std_logic;-- un solo reloj para ambos puertos de la BRAM
--Puerto de escritura en el cual se vana grabar los datos en la tabla
porta_wr : in std_logic;
porta_waddr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
porta_din : in std_logic_vector( (DATA_WIDTH-1) downto 0);
porta_rd : in std_logic;
porta_raddr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
porta_dout : out std_logic_vector( (DATA_WIDTH-1) downto 0);
--puerto de lectura, desde el cual se van a leer los 0
--datos para la comparación
portb_rd : in std_logic;
portb_addr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
portb_dout : out std_logic_vector( (DATA_WIDTH-1) downto 0)
);
end entity BinarySearchBRAM;
architecture Inferral of BinarySearchBRAM is
type mem_type is array ( (2**ADDR_WIDTH)-1 downto 0 ) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable mem : mem_type;
begin
portA:process (clk, porta_wr, porta_waddr, porta_raddr, porta_din, porta_rd)
begin
if rising_edge(clk) then
if ( porta_wr = '1' ) then
mem(conv_integer(porta_waddr)) := porta_din;
elsif ( porta_rd = '1' ) then
porta_dout <= mem(conv_integer(porta_raddr));
end if;
end if;
end process portA;
portB:process (clk, portb_rd, portb_addr)
begin
if rising_edge(clk) then
if ( portb_rd = '1' ) then
portb_dout <= mem(conv_integer(portb_addr));
end if;
end if;
end process portB;
end architecture Inferral;
| bsd-3-clause |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/Eth_GMII_RXTest.vhd | 1 | 4597 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.03.2014 13:25:44
-- Design Name:
-- Module Name: Eth_GMII_RXTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Eth_GMII_RXTest is
Port (
botones : in STD_LOGIC_VECTOR (3 downto 0);
leds : out STD_LOGIC_VECTOR (3 downto 0);
gmii_int : in STD_LOGIC;
gmii_reset : out STD_LOGIC;
--Interfaz hacia el PHY
gmii_mdc : out STD_LOGIC;
gmii_mdio : inout STD_LOGIC;
gmii_tx_clk : out STD_LOGIC;
gmii_tx_en : out STD_LOGIC;
gmii_tx_data : out STD_LOGIC_VECTOR (7 downto 0);
gmii_tx_err : out STD_LOGIC;
gmii_rx_clk : in STD_LOGIC;
gmii_rx_crs : in STD_LOGIC;
gmii_rx_col : in STD_LOGIC;
gmii_rx_data : in STD_LOGIC_VECTOR (7 downto 0);
gmii_rx_dataValid : in STD_LOGIC;
gmii_rx_err : in STD_LOGIC;
sysclk_n : in std_logic;
sysclk_p : in std_logic
);
end Eth_GMII_RXTest;
architecture Behavioral of Eth_GMII_RXTest is
signal packetCounter : std_logic_vector(3 downto 0) := "0000";
signal gmii_rx_dataValid_previous : std_logic;
signal tx_clk : std_logic;
signal packetAlreadyReaded : std_logic := '0';
signal porta_wr : std_logic;
signal porta_waddr : std_logic_vector(9 downto 0);
signal porta_din : std_logic_vector(7 downto 0) := ( others => '0');
signal porta_rd : std_logic;
signal porta_raddr : std_logic_vector(9 downto 0);
signal porta_dout : std_logic_vector(7 downto 0);
signal portb_rd : std_logic;
signal portb_addr : std_logic_vector(9 downto 0);
signal portb_dout : std_logic_vector(7 downto 0);
signal storeCounter : std_logic_vector(9 downto 0) := ( others => '0');
begin
memory: entity work.BinarySearchBRAM
generic map( DATA_WIDTH => 8, ADDR_WIDTH => 10 )
port map (
clk => gmii_rx_clk,
porta_wr => porta_wr,
porta_waddr => porta_waddr,
porta_din => porta_din,
porta_rd => porta_rd,
porta_raddr => porta_raddr,
porta_dout => open,
portb_rd => portb_rd,
portb_addr => portb_addr,
portb_dout => portb_dout
);
porta_wr <= (gmii_rx_dataValid and not(packetAlreadyReaded));
porta_waddr <= storeCounter;
porta_din <= gmii_rx_data(7 downto 0);
porta_rd <= '0';
porta_raddr <= ( others => '0');
portb_rd <= '0';
portb_addr <= ( others => '0');
RXClocking: process (gmii_rx_clk, gmii_rx_dataValid, gmii_rx_data, storeCounter, gmii_rx_dataValid_previous, packetCounter) begin
if ( rising_edge(gmii_rx_clk) ) then
if(gmii_rx_dataValid = '1') then
--leds(3 downto 0) <= gmii_rx_data(3 downto 0);
storeCounter <= storeCounter+1;
end if;
gmii_rx_dataValid_previous <= gmii_rx_dataValid;
if( (gmii_rx_dataValid = '1') and (gmii_rx_dataValid_previous = '0') ) then
packetCounter <= packetCounter+1;
elsif ( (gmii_rx_dataValid = '0') and (gmii_rx_dataValid_previous = '1') ) then
packetAlreadyReaded <= '1';
end if;
end if;
end process RXClocking;
leds <= packetCounter;
gmii_reset <= '1';
gmii_tx_en <= '0';
gmii_tx_data <= (others => '0');
gmii_tx_err <= '0';
gmii_mdc <= '0';
gmii_mdio <= 'Z';
txClkGenerator: entity work.clk_wiz_v3_6_0
port map
(-- Clock in ports
CLK_IN1_P => sysclk_p,
CLK_IN1_N => sysclk_n,
-- Clock out ports
CLK_OUT1 => tx_clk
);
gmii_tx_clk_ddr_iob : ODDR2
port map(
D0 => '0',
D1 => '1',
C0 => tx_clk,
C1 => '0',
CE => '1',
R => '0',
S => '0',
Q => gmii_tx_clk
);
end Behavioral;
| bsd-3-clause |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/TB3_No4ByteAligned.vhd | 1 | 11379 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.11.2013 00:20:28
-- Design Name:
-- Module Name: TestBench1_FourByteAlignedTests - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: Esta prueba solo realzia una unica prueba al modulo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB3_No4ByteAligned is
end TB3_No4ByteAligned;
architecture Behavioral of TB3_No4ByteAligned is
-- Signals to evaluate
--ENTRADAS
signal inputBlock : std_logic_vector(31 downto 0);
signal readInput : std_logic;
signal blockLength : std_logic_vector(1 downto 0);
signal finalBlock : std_logic;
signal start : std_logic;
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
--SALIDAS
signal canAccept : std_logic;
signal resultReady : std_logic;
signal result : std_logic_vector(31 downto 0);
signal resultID : std_logic_vector(31 downto 0);
--RELOJ
signal clk : std_logic;
--Salidas de depuracion
signal dataStep1_dbg : std_logic_vector(31 downto 0);
signal dataStep2_dbg : std_logic_vector(31 downto 0);
signal dataStep3_dbg : std_logic_vector(31 downto 0);
signal dataStep4_dbg : std_logic_vector(31 downto 0);
signal dataStep5_dbg : std_logic_vector(31 downto 0);
signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
signal dataStepA_dbg : std_logic_vector(31 downto 0);
signal dataStepA_ID_dbg : std_logic_vector(31 downto 0);
signal dataStepB_dbg : std_logic_vector(31 downto 0);
signal dataStepB_ID_dbg : std_logic_vector(31 downto 0);
signal dataStepC_dbg : std_logic_vector(31 downto 0);
signal dataStepC_ID_dbg : std_logic_vector(31 downto 0);
signal dataStepD_dbg : std_logic_vector(31 downto 0);
signal dataStepD_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep1_dbg : std_logic_vector(31 downto 0);
signal finalStep2_dbg : std_logic_vector(31 downto 0);
signal finalStep3_dbg : std_logic_vector(31 downto 0);
signal finalStep4_dbg : std_logic_vector(31 downto 0);
signal finalStep5_dbg : std_logic_vector(31 downto 0);
signal finalStep1_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep2_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep3_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep4_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep5_ID_dbg : std_logic_vector(31 downto 0);
type resultReference is array (0 to 13) of std_logic_vector(31 downto 0);
constant resultsBank : resultReference := ( x"6b6cf591", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
constant opsIDs : resultReference := ( x"6b6cf591", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
signal resultsBankCounter : integer := 0;
signal errorDetected : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
--Inicializar el banco de resultados
verification: process (clk, resultReady, result, resultsBankCounter)
begin
if( rising_edge(clk) ) then
--if( resultsBankCounter = resultReference'length ) then
if( resultsBankCounter = 1 ) then
errorDetected <= '0';
else
if (resultReady = '1') then
if( (resultsBank(resultsBankCounter)/=result) or (resultID/=opsIDs(resultsBankCounter)) ) then
errorDetected <= '1';
else
errorDetected <= '0';
end if;
resultsBankCounter <= resultsBankCounter+1;
else
errorDetected <= '0';
end if;
end if;
end if;
end process verification;
uut: work.MurmurHashUtils.MurmurHash32Generator PORT MAP (
--ENTRADAS
inputBlock => inputBlock,
readInput => readInput,
blockLength => blockLength,
finalBlock => finalBlock,
start => start,
operationID => operationID,
seed => seed,
--SALIDAS
canAccept => canAccept,
resultReady => resultReady,
result => result,
resultID => resultID,
--RELOJ
clk => clk,
--Salidas de depuracion
dataStep1_dbg => dataStep1_dbg,
dataStep2_dbg => dataStep2_dbg,
dataStep3_dbg => dataStep3_dbg,
dataStep4_dbg => dataStep4_dbg,
dataStep5_dbg => dataStep5_dbg,
dataStep1_ID_dbg => dataStep1_ID_dbg,
dataStep2_ID_dbg => dataStep2_ID_dbg,
dataStep3_ID_dbg => dataStep3_ID_dbg,
dataStep4_ID_dbg => dataStep4_ID_dbg,
dataStep5_ID_dbg => dataStep5_ID_dbg,
dataStepA_dbg => dataStepA_dbg,
dataStepB_dbg => dataStepB_dbg,
dataStepC_dbg => dataStepC_dbg,
dataStepD_dbg => dataStepD_dbg,
dataStepA_ID_dbg => dataStepA_ID_dbg,
dataStepB_ID_dbg => dataStepB_ID_dbg,
dataStepC_ID_dbg => dataStepC_ID_dbg,
dataStepD_ID_dbg => dataStepD_ID_dbg,
finalStep1_dbg => finalStep1_dbg,
finalStep2_dbg => finalStep2_dbg,
finalStep3_dbg => finalStep3_dbg,
finalStep4_dbg => finalStep4_dbg,
finalStep5_dbg => finalStep5_dbg,
finalStep1_ID_dbg => finalStep1_ID_dbg,
finalStep2_ID_dbg => finalStep2_ID_dbg,
finalStep3_ID_dbg => finalStep3_ID_dbg,
finalStep4_ID_dbg => finalStep4_ID_dbg,
finalStep5_ID_dbg => finalStep5_ID_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
blockLength <= "00";
--operationID <= "0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101";
operationID <= opsIDs(0);
--PRUEBA 1, HASH DEL VECTOR 0
--Se einicializan los datos y
inputBlock <= x"000000de";
start <= '1';
finalBlock <= '1';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
readInput <= '0';
wait for clk_period;
--hacer que realize una lectura de datos
readInput <= '1';
wait for clk_period;
start <= '0';--que ya no lea otro dato
readInput <= '0';
wait for clk_period;
-- --Prueba 2 hash del vector 1
-- blockLength <= "11";
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0001";
-- operationID <= opsIDs(1);
-- finalBlock <= '1';
-- seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- start <= '1';
-- readInput <= '0';
-- wait for clk_period;
-- --hacer que realize una lectura de datos
-- readInput <= '1';
-- wait for clk_period;
-- start <= '0';--que ya no lea otro dato
-- readInput <= '0';
-- wait for clk_period;
-- wait for clk_period;
-- --PROBAR QUE AMBAS SALIDAS CONSECUTIVAS SE REALIZEN DE FORMA CONSECUTIVA
-- start <= '1';
-- finalBlock <= '1';
-- readInput <= '1';
-- seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- --Probando valroes consecutivos
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(2);
-- wait for clk_period;
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0001";
-- operationID <= opsIDs(3);
-- wait for clk_period;
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0010";
-- operationID <= opsIDs(4);
-- wait for clk_period;
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0011";
-- operationID <= opsIDs(5);
-- wait for clk_period;
-- readInput <= '0';
-- wait for clk_period;
-- readInput <= '1';
-- inputBlock <= "1000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(6);
-- wait for clk_period;
-- inputBlock <= "0100"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(7);
-- wait for clk_period;
-- inputBlock <= "1100"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(8);
-- wait for clk_period;
-- inputBlock <= "0010"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(9);
-- wait for clk_period;
-- inputBlock <= "1111"&"1111"&"1111"&"1111"&"1111"&"1111"&"1111"&"1111";
-- operationID <= opsIDs(10);
-- wait for clk_period;
-- inputBlock <= "1111"&"0000"&"1111"&"0000"&"1111"&"0000"&"1111"&"0000";
-- operationID <= opsIDs(11);
-- wait for clk_period;
-- inputBlock <= "0000"&"1111"&"0000"&"1111"&"0000"&"1111"&"0000"&"1111";
-- operationID <= opsIDs(12);
-- wait for clk_period;
-- inputBlock <= "1100"&"1100"&"1100"&"1100"&"1100"&"1100"&"1100"&"1100";
-- operationID <= opsIDs(13);
-- wait for clk_period;
readInput <= '0';
wait for clk_period;
wait;
end process stim_proc;
end Behavioral;
| bsd-3-clause |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/TestBench1_FourByteAlignedTests.vhd | 1 | 10289 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.11.2013 00:20:28
-- Design Name:
-- Module Name: TestBench1_FourByteAlignedTests - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestBench1_FourByteAlignedTests is
end TestBench1_FourByteAlignedTests;
architecture Behavioral of TestBench1_FourByteAlignedTests is
-- Signals to evaluate
--ENTRADAS
signal inputBlock : std_logic_vector(31 downto 0);
signal readInput : std_logic;
signal blockLength : std_logic_vector(1 downto 0);
signal finalBlock : std_logic;
signal start : std_logic;
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
--SALIDAS
signal canAccept : std_logic;
signal resultReady : std_logic;
signal result : std_logic_vector(31 downto 0);
signal resultID : std_logic_vector(31 downto 0);
--RELOJ
signal clk : std_logic;
--Salidas de depuracion
signal dataStep1_dbg : std_logic_vector(31 downto 0);
signal dataStep2_dbg : std_logic_vector(31 downto 0);
signal dataStep3_dbg : std_logic_vector(31 downto 0);
signal dataStep4_dbg : std_logic_vector(31 downto 0);
signal dataStep5_dbg : std_logic_vector(31 downto 0);
signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep1_dbg : std_logic_vector(31 downto 0);
signal finalStep2_dbg : std_logic_vector(31 downto 0);
signal finalStep3_dbg : std_logic_vector(31 downto 0);
signal finalStep4_dbg : std_logic_vector(31 downto 0);
signal finalStep5_dbg : std_logic_vector(31 downto 0);
signal finalStep1_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep2_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep3_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep4_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep5_ID_dbg : std_logic_vector(31 downto 0);
type resultReference is array (0 to 13) of std_logic_vector(31 downto 0);
constant resultsBank : resultReference := ( x"2362f9de", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
constant opsIDs : resultReference := ( x"2362f9de", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
signal resultsBankCounter : integer := 0;
signal errorDetected : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
--Inicializar el banco de resultados
verification: process (clk, resultReady, result, resultsBankCounter)
begin
if( rising_edge(clk) ) then
if( resultsBankCounter = resultReference'length ) then
errorDetected <= '0';
else
if (resultReady = '1') then
if( (resultsBank(resultsBankCounter)/=result) or (resultID/=opsIDs(resultsBankCounter)) ) then
errorDetected <= '1';
else
errorDetected <= '0';
end if;
resultsBankCounter <= resultsBankCounter+1;
else
errorDetected <= '0';
end if;
end if;
end if;
end process verification;
uut: work.MurmurHashUtils.MurmurHash32Generator PORT MAP (
--ENTRADAS
inputBlock => inputBlock,
readInput => readInput,
blockLength => blockLength,
finalBlock => finalBlock,
start => start,
operationID => operationID,
seed => seed,
--SALIDAS
canAccept => canAccept,
resultReady => resultReady,
result => result,
resultID => resultID,
--RELOJ
clk => clk,
--Salidas de depuracion
dataStep1_dbg => dataStep1_dbg,
dataStep2_dbg => dataStep2_dbg,
dataStep3_dbg => dataStep3_dbg,
dataStep4_dbg => dataStep4_dbg,
dataStep5_dbg => dataStep5_dbg,
dataStep1_ID_dbg => dataStep1_ID_dbg,
dataStep2_ID_dbg => dataStep2_ID_dbg,
dataStep3_ID_dbg => dataStep3_ID_dbg,
dataStep4_ID_dbg => dataStep4_ID_dbg,
dataStep5_ID_dbg => dataStep5_ID_dbg,
finalStep1_dbg => finalStep1_dbg,
finalStep2_dbg => finalStep2_dbg,
finalStep3_dbg => finalStep3_dbg,
finalStep4_dbg => finalStep4_dbg,
finalStep5_dbg => finalStep5_dbg,
finalStep1_ID_dbg => finalStep1_ID_dbg,
finalStep2_ID_dbg => finalStep2_ID_dbg,
finalStep3_ID_dbg => finalStep3_ID_dbg,
finalStep4_ID_dbg => finalStep4_ID_dbg,
finalStep5_ID_dbg => finalStep5_ID_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
blockLength <= "11";
--operationID <= "0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101";
operationID <= opsIDs(0);
--PRUEBA 1, HASH DEL VECTOR 0
--Se einicializan los datos y
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
start <= '1';
finalBlock <= '1';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
readInput <= '0';
wait for clk_period;
--hacer que realize una lectura de datos
readInput <= '1';
wait for clk_period;
start <= '0';--que ya no lea otro dato
readInput <= '0';
wait for clk_period;
--Prueba 2 hash del vector 1
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0001";
operationID <= opsIDs(1);
finalBlock <= '1';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
start <= '1';
readInput <= '0';
wait for clk_period;
--hacer que realize una lectura de datos
readInput <= '1';
wait for clk_period;
start <= '0';--que ya no lea otro dato
readInput <= '0';
wait for clk_period;
wait for clk_period;
--PROBAR QUE AMBAS SALIDAS CONSECUTIVAS SE REALIZEN DE FORMA CONSECUTIVA
start <= '1';
finalBlock <= '1';
readInput <= '1';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
--Probando valroes consecutivos
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(2);
wait for clk_period;
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0001";
operationID <= opsIDs(3);
wait for clk_period;
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0010";
operationID <= opsIDs(4);
wait for clk_period;
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0011";
operationID <= opsIDs(5);
wait for clk_period;
readInput <= '0';
wait for clk_period;
readInput <= '1';
inputBlock <= "1000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(6);
wait for clk_period;
inputBlock <= "0100"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(7);
wait for clk_period;
inputBlock <= "1100"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(8);
wait for clk_period;
inputBlock <= "0010"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(9);
wait for clk_period;
inputBlock <= "1111"&"1111"&"1111"&"1111"&"1111"&"1111"&"1111"&"1111";
operationID <= opsIDs(10);
wait for clk_period;
inputBlock <= "1111"&"0000"&"1111"&"0000"&"1111"&"0000"&"1111"&"0000";
operationID <= opsIDs(11);
wait for clk_period;
inputBlock <= "0000"&"1111"&"0000"&"1111"&"0000"&"1111"&"0000"&"1111";
operationID <= opsIDs(12);
wait for clk_period;
inputBlock <= "1100"&"1100"&"1100"&"1100"&"1100"&"1100"&"1100"&"1100";
operationID <= opsIDs(13);
wait for clk_period;
readInput <= '0';
wait for clk_period;
wait;
end process stim_proc;
end Behavioral;
| bsd-3-clause |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/TB4_FileBasedTest.vhd | 1 | 8403 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.01.2014 14:32:21
-- Design Name:
-- Module Name: TB4_FileBasedTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB4_FileBasedTest is
end TB4_FileBasedTest;
architecture Behavioral of TB4_FileBasedTest is
signal clk : std_logic;
constant clk_period : time := 10 ns;
signal errorDetected : std_logic := '0';
-- Signals to evaluate
--ENTRADAS
signal actualTestTotalLength : std_logic_vector(31 downto 0);
signal inputBlock : std_logic_vector(31 downto 0);
signal readInput : std_logic;
signal blockLength : std_logic_vector(1 downto 0);
signal finalBlock : std_logic;
signal start : std_logic;
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
--SALIDAS
signal canAccept : std_logic;
signal resultReady : std_logic;
signal result : std_logic_vector(31 downto 0);
signal resultID : std_logic_vector(31 downto 0);
--RELOJ
--Salidas de depuracion
signal dataStep1_dbg : std_logic_vector(31 downto 0);
signal dataStep2_dbg : std_logic_vector(31 downto 0);
signal dataStep3_dbg : std_logic_vector(31 downto 0);
signal dataStep4_dbg : std_logic_vector(31 downto 0);
signal dataStep5_dbg : std_logic_vector(31 downto 0);
signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep1_dbg : std_logic_vector(31 downto 0);
signal finalStep2_dbg : std_logic_vector(31 downto 0);
signal finalStep3_dbg : std_logic_vector(31 downto 0);
signal finalStep4_dbg : std_logic_vector(31 downto 0);
signal finalStep5_dbg : std_logic_vector(31 downto 0);
signal finalStep1_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep2_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep3_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep4_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep5_ID_dbg : std_logic_vector(31 downto 0);
signal resultsBankCounterSignal : integer := 0;
begin
seed <= simulationSeed;
uut: work.MurmurHashUtils.MurmurHash32Generator PORT MAP (
--ENTRADAS
inputBlock => inputBlock,
readInput => readInput,
blockLength => blockLength,
finalBlock => finalBlock,
start => start,
operationID => operationID,
seed => seed,
--SALIDAS
canAccept => canAccept,
resultReady => resultReady,
result => result,
resultID => resultID,
--RELOJ
clk => clk,
--Salidas de depuracion
dataStep1_dbg => dataStep1_dbg,
dataStep2_dbg => dataStep2_dbg,
dataStep3_dbg => dataStep3_dbg,
dataStep4_dbg => dataStep4_dbg,
dataStep5_dbg => dataStep5_dbg,
dataStep1_ID_dbg => dataStep1_ID_dbg,
dataStep2_ID_dbg => dataStep2_ID_dbg,
dataStep3_ID_dbg => dataStep3_ID_dbg,
dataStep4_ID_dbg => dataStep4_ID_dbg,
dataStep5_ID_dbg => dataStep5_ID_dbg,
finalStep1_dbg => finalStep1_dbg,
finalStep2_dbg => finalStep2_dbg,
finalStep3_dbg => finalStep3_dbg,
finalStep4_dbg => finalStep4_dbg,
finalStep5_dbg => finalStep5_dbg,
finalStep1_ID_dbg => finalStep1_ID_dbg,
finalStep2_ID_dbg => finalStep2_ID_dbg,
finalStep3_ID_dbg => finalStep3_ID_dbg,
finalStep4_ID_dbg => finalStep4_ID_dbg,
finalStep5_ID_dbg => finalStep5_ID_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
verification: process (clk, resultReady, result, resultsBankCounterSignal)
begin
if( rising_edge(clk) ) then
if( resultsBankCounterSignal = resultsBank'length ) then
errorDetected <= '0';
else
if (resultReady = '1') then
if( (resultsBank(resultsBankCounterSignal)/=result) ) then
errorDetected <= '1';
else
errorDetected <= '0';
end if;
resultsBankCounterSignal <= resultsBankCounterSignal+1;
else
errorDetected <= '0';
end if;
end if;
end if;
end process verification;
Test: process is
variable byteCounter : integer := 0;--contador de bytes en el bloque de datos actual
variable byteInputCounter : integer := 0;-- contador de bytes totales elidos en el testBench
variable resultsBankCounter : integer := 0;
variable actualByte : std_logic_vector(7 downto 0);-- byet actualmetne leido
variable inputBlockCurrentByte : integer :=0;
variable input : std_logic_vector(31 downto 0) := (others => '0') ;
variable startBlock : boolean := false;
variable endBlock : boolean := false;
begin
start <= '0';--que ya no lea otro dato
readInput <= '0';
operationID <= ( others => '0');
wait for clk_period*10;
while (resultsBankCounter < resultsBank'length) loop
start <= '0';--que ya no lea otro dato
readInput <= '0';
inputBlockCurrentByte := 0;
byteCounter:=0;
inputBlockCurrentByte := 0;
wait for clk_period;
start <= '1';
actualTestTotalLength <= entrysLengths(resultsBankCounter);
while(byteCounter<entrysLengths(resultsBankCounter)) loop
actualByte := dataBank(byteInputCounter);
input((inputBlockCurrentByte*8+7) downto (inputBlockCurrentByte*8)) := actualByte;
--input(7 downto 0) := actualByte;
endBlock := ((byteCounter+1)=entrysLengths(resultsBankCounter));
if ( ( (byteCounter mod 4) = 3 ) or (endBlock) ) then
finalBlock<= mh3_boolean_to_std_logic(endBlock);
inputBlock <= input;
readInput <= '1';
blockLength <= std_logic_vector( to_unsigned(byteCounter, 2) );
wait for clk_period;
start <= '0';
input := (others => '0') ;
end if;
if (endBlock) then
readInput <= '0';
wait for clk_period;
end if;
byteCounter := byteCounter+1;
byteInputCounter := byteInputCounter+1;
inputBlockCurrentByte := ( (inputBlockCurrentByte+1) mod 4);
end loop;
resultsBankCounter := resultsBankCounter+1;
--wait for clk_period;
end loop;
wait;-- Que no se repita de forma indefinida
end process Test;
end Behavioral;
| bsd-3-clause |
stnolting/neo430 | rtl/core/neo430_cpu.vhd | 1 | 10226 | -- #################################################################################################
-- # << NEO430 - CPU Top Entity >> #
-- # ********************************************************************************************* #
-- # Top entity of the NEO430 CPU. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_cpu is
generic (
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, low-active, async
-- memory interface --
mem_rd_o : out std_ulogic; -- memory read enable
mem_imwe_o : out std_ulogic; -- allow writing to IMEM
mem_wr_o : out std_ulogic_vector(01 downto 0); -- byte memory write enable
mem_addr_o : out std_ulogic_vector(15 downto 0); -- address
mem_data_o : out std_ulogic_vector(15 downto 0); -- write data
mem_data_i : in std_ulogic_vector(15 downto 0); -- read data
-- interrupt system --
irq_i : in std_ulogic_vector(03 downto 0) -- interrupt requests
);
end neo430_cpu;
architecture neo430_cpu_rtl of neo430_cpu is
-- local signals --
signal mem_addr : std_ulogic_vector(15 downto 0); -- memory address
signal mdi : std_ulogic_vector(15 downto 0); -- memory data_in
signal mdi_gate : std_ulogic_vector(15 downto 0); -- memory data_in power gate
signal mdo_gate : std_ulogic_vector(15 downto 0); -- memory data_out power gate
signal ctrl_bus : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control spine
signal sreg : std_ulogic_vector(15 downto 0); -- current status register
signal alu_flags : std_ulogic_vector(04 downto 0); -- new ALU flags
signal imm : std_ulogic_vector(15 downto 0); -- branch offset
signal rf_read : std_ulogic_vector(15 downto 0); -- RF read data
signal alu_res : std_ulogic_vector(15 downto 0); -- ALU result
signal addr_fb : std_ulogic_vector(15 downto 0); -- address feedback
signal irq_sel : std_ulogic_vector(01 downto 0); -- IRQ vector
signal dio_swap : std_ulogic; -- data in/out swap
signal bw_ff : std_ulogic; -- byte/word access flag
signal rd_ff : std_ulogic; -- is read access
begin
-- Control Unit -------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_control_inst: neo430_control
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rst_i => rst_i, -- global reset, low-active, async
-- memory interface --
instr_i => mem_data_i, -- instruction word from memory
-- control --
sreg_i => sreg, -- current status register
ctrl_o => ctrl_bus, -- control signals
irq_vec_o => irq_sel, -- irq channel address
imm_o => imm, -- branch offset
-- irq lines --
irq_i => irq_i -- IRQ lines
);
-- Register File ------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_reg_file_inst: neo430_reg_file
generic map (
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader?
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory?
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rst_i => rst_i, -- global reset, low-active, async
-- data input --
alu_i => alu_res, -- data from alu
addr_i => addr_fb, -- data from addr unit
flag_i => alu_flags, -- new ALU flags
-- control --
ctrl_i => ctrl_bus, -- control signals
-- data output --
data_o => rf_read, -- read data
sreg_o => sreg -- current SR
);
-- ALU ----------------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_alu_inst: neo430_alu
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
-- operands --
reg_i => rf_read, -- data from reg file
mem_i => mdi, -- data from memory
sreg_i => sreg, -- current SR
-- control --
ctrl_i => ctrl_bus, -- control signals
-- results --
data_o => alu_res, -- result
flag_o => alu_flags -- new ALU flags
);
-- Address Generator --------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_addr_gen_inst: neo430_addr_gen
port map(
-- global control --
clk_i => clk_i, -- global clock, rising edge
-- data input --
reg_i => rf_read, -- reg file input
mem_i => mdi, -- memory input
imm_i => imm, -- branch offset
irq_sel_i => irq_sel, -- IRQ vector
-- control --
ctrl_i => ctrl_bus, -- control signals
-- data output --
mem_addr_o => mem_addr, -- memory address
dwb_o => addr_fb -- data write back output
);
-- Memory Access ------------------------------------------------------------
-- -----------------------------------------------------------------------------
memory_control: process(clk_i)
begin
if rising_edge(clk_i) then
bw_ff <= ctrl_bus(ctrl_alu_bw_c);
dio_swap <= ctrl_bus(ctrl_alu_bw_c) and mem_addr(0);
rd_ff <= ctrl_bus(ctrl_mem_rd_c);
end if;
end process memory_control;
-- Memory R/W interface --
mem_rd_o <= ctrl_bus(ctrl_mem_rd_c);
-- activate both WE lines when in word mode, use corresponding WE line when in byte mode
mem_wr_o(0) <= ctrl_bus(ctrl_mem_wr_c) when (bw_ff = '0') else (ctrl_bus(ctrl_mem_wr_c) and (not mem_addr(0)));
mem_wr_o(1) <= ctrl_bus(ctrl_mem_wr_c) when (bw_ff = '0') else (ctrl_bus(ctrl_mem_wr_c) and mem_addr(0) );
-- only allow write-access to IMEM when r-flag is set --
mem_imwe_o <= sreg(sreg_r_c);
-- data in/out swap --
mdi_gate <= mem_data_i when ((rd_ff = '1') or (low_power_mode_c = false)) else (others => '0'); -- AND GATE to reduce switching activity in low power mode
mdi <= mdi_gate when (dio_swap = '0') else mdi_gate(7 downto 0) & mdi_gate(15 downto 8);
mdo_gate <= alu_res when (dio_swap = '0') else alu_res(7 downto 0) & alu_res(15 downto 8);
mem_data_o <= mdo_gate when ((ctrl_bus(ctrl_mem_wr_c) = '1') or (low_power_mode_c = false)) else (others => '0'); -- AND GATE to reduce switching activity in low power mode
-- address output --
mem_addr_o <= mem_addr(15 downto 1) & '0'; -- word-aligned addresses only beyond this point
end neo430_cpu_rtl;
| bsd-3-clause |
nkkav/bstest-s3esk | std_logic_textio.vhd | 1 | 24062 | -- --------------------------------------------------------------------
--
-- Title : std_logic_textio
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Adapted by IEEE P1164 Working Group from
-- : source donated by Synopsys, Inc.
-- :
-- Purpose : This packages defines procedures for reading and writing
-- : standard-logic scalars and vectors in binary, hexadecimal
-- : and octal format.
-- :
-- Limitation: None.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the procedures of std_logic_textio.
-- : The std_logic_textio package body shall be
-- : considered the formal definition of the semantics of
-- : this package, except that where a procedure issues an
-- : assertion violation, the standard does not specify the
-- : required behavior in response to the erroneous condition.
-- : Tool developers may choose to implement the package body
-- : in the most efficient manner available to them.
-- :
-- --------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- --------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC);
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR);
procedure WRITE (L: inout LINE; VALUE: in STD_ULOGIC;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out STD_LOGIC_VECTOR);
procedure WRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
-- Read and Write procedures for Hex values
procedure HREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR);
procedure HWRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR);
procedure HWRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
-- Read and Write procedures for Octal values
procedure OREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR);
procedure OWRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR);
procedure OWRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
constant NBSP : character := character'val(160);
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC; GOOD: out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l, c, readOk); -- but also exit on a bad read
exit when (readOk = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if not readOk then
good := FALSE;
else
if char_to_MVL9plus(c) = ERROR then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l, c, readOk);
exit when (readOk = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not readOk then
good := FALSE;
return;
end if;
if char_to_MVL9plus(c) = ERROR then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if not readOk then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if char_to_MVL9plus(s(i)) = ERROR then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l, c);
exit when (c /= ' ') and (c /= NBSP) and (c /= HT);
end loop;
if char_to_MVL9plus(c) = ERROR then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l, c);
exit when (c /= ' ') and (c /= NBSP) and (c /= HT);
end loop;
if char_to_MVL9plus(c) = ERROR then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if char_to_MVL9plus(s(i)) = ERROR then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE (L: inout LINE; VALUE: in STD_ULOGIC;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ (L: inout LINE; VALUE: out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
procedure Char2QuadBits (C: Character;
RESULT: out std_ulogic_vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' | 'a' => result := x"A"; good := TRUE;
when 'B' | 'b' => result := x"B"; good := TRUE;
when 'C' | 'c' => result := x"C"; good := TRUE;
when 'D' | 'd' => result := x"D"; good := TRUE;
when 'E' | 'e' => result := x"E"; good := TRUE;
when 'F' | 'f' => result := x"F"; good := TRUE;
when 'Z' => result := "ZZZZ"; good := TRUE;
when 'X' => result := "XXXX"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable sv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l, c, ok);
exit when (ok = FALSE) or (c = LF) or (c = CR) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
-- exit when (ok = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
good := FALSE;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := sv;
end HREAD;
procedure HREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable sv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l, c, ok);
exit when (ok = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
assert FALSE
report "HREAD Error: Failed skipping white space";
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := sv;
end HREAD;
procedure HWRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
variable quad: std_ulogic_vector(0 to 3);
constant ne: integer := value'length/4;
variable sv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := To_X01Z(sv(4*i to 4*i+3));
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
when others =>
if (quad = "ZZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
procedure Char2TriBits (C: Character;
RESULT: out std_ulogic_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when 'Z' => result := "ZZZ"; good := TRUE;
when 'X' => result := "XXX"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable sv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l, c, ok);
exit when (ok = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
good := FALSE;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := sv;
end OREAD;
procedure OREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable sv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l, c, ok);
exit when (ok = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
assert FALSE
report "OREAD Error: Failed skipping white space";
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := sv;
end OREAD;
procedure OWRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
variable tri: std_ulogic_vector(0 to 2);
constant ne: integer := value'length/3;
variable sv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := To_X01Z(sv(3*i to 3*i+2));
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
when others =>
if (tri = "ZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
begin
HWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO;
| bsd-3-clause |
stnolting/neo430 | rtl/top_templates/neo430_top_axi4lite.vhd | 1 | 15832 | -- #################################################################################################
-- # << NEO430 - Processor Top Entity with AXI4-Lite-Compatible Master Interface >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_top_axi4lite is
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 32kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 28kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := false; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
FREQ_GEN_USE : boolean := true; -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- GPIO --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(03 downto 0); -- pwm channels
-- arbitrary frequency generator --
freq_gen_o : out std_logic_vector(02 downto 0); -- programmable frequency output
-- UART --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
-- SPI --
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(05 downto 0); -- SPI CS
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- external interrupts --
ext_irq_i : in std_logic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_logic_vector(07 downto 0); -- external interrupt request acknowledges
-- AXI Lite-Compatible Master Interface --
-- Clock and Reset
m_axi_aclk : in std_logic;
m_axi_aresetn : in std_logic;
-- Write Address Channel
m_axi_awaddr : out std_logic_vector(31 downto 0);
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awprot : out std_logic_vector(2 downto 0);
-- Write Data Channel
m_axi_wdata : out std_logic_vector(31 downto 0);
m_axi_wstrb : out std_logic_vector(3 downto 0);
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
-- Read Address Channel
m_axi_araddr : out std_logic_vector(31 downto 0);
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_arprot : out std_logic_vector(2 downto 0);
-- Read Data Channel
m_axi_rdata : in std_logic_vector(31 downto 0);
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
-- Write Response Channel
m_axi_bresp : in std_logic_vector(1 downto 0);
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic
);
end neo430_top_axi4lite;
architecture neo430_top_axi4lite_rtl of neo430_top_axi4lite is
-- internal wishbone bus --
type wb_bus_t is record
adr : std_ulogic_vector(31 downto 0); -- address
di : std_ulogic_vector(31 downto 0); -- slave input data
do : std_ulogic_vector(31 downto 0); -- slave output data
we : std_ulogic; -- write enable
sel : std_ulogic_vector(03 downto 0); -- byte enable
stb : std_ulogic; -- strobe
cyc : std_ulogic; -- valid cycle
ack : std_ulogic; -- transfer acknowledge
end record;
signal wb_core : wb_bus_t;
-- other signals for conversion --
signal gpio_o_int : std_ulogic_vector(15 downto 0);
signal gpio_i_int : std_ulogic_vector(15 downto 0);
signal pwm_o_int : std_ulogic_vector(03 downto 0);
signal uart_txd_o_int : std_ulogic;
signal uart_rxd_i_int : std_ulogic;
signal spi_sclk_o_int : std_ulogic;
signal spi_mosi_o_int : std_ulogic;
signal spi_miso_i_int : std_ulogic;
signal spi_cs_o_int : std_ulogic_vector(05 downto 0);
signal irq_i_int : std_ulogic_vector(07 downto 0);
signal irq_ack_o_int : std_ulogic_vector(07 downto 0);
signal freq_gen_o_int : std_ulogic_vector(02 downto 0);
constant usrcode_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(USER_CODE);
-- AXI arbiter --
signal read_trans : std_ulogic;
signal write_trans : std_ulogic;
signal pending_rd : std_ulogic; -- pending read transfer
signal pending_wr : std_ulogic; -- pending write transfer
signal adr_valid : std_ulogic;
signal wresp_ok : std_logic;
begin
-- CPU ----------------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_top_inst: neo430_top
generic map (
-- general configuration --
CLOCK_SPEED => CLOCK_SPEED, -- main clock in Hz
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => DMEM_SIZE, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => usrcode_c, -- custom user code
-- module configuration --
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit? (default=true)
WB32_USE => WB32_USE, -- implement WB32 unit? (default=true)
WDT_USE => WDT_USE, -- implement WDT? (default=true)
GPIO_USE => GPIO_USE, -- implement GPIO unit? (default=true)
TIMER_USE => TIMER_USE, -- implement timer? (default=true)
UART_USE => UART_USE, -- implement UART? (default=true)
CRC_USE => CRC_USE, -- implement CRC unit? (default=true)
CFU_USE => CFU_USE, -- implement CF unit? (default=false)
PWM_USE => PWM_USE, -- implement PWM controller? (default=true)
TWI_USE => TWI_USE, -- implement two wire serial interface? (default=true)
SPI_USE => SPI_USE, -- implement SPI? (default=true)
TRNG_USE => TRNG_USE, -- implement TRNG? (default=false)
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
FREQ_GEN_USE => FREQ_GEN_USE, -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => m_axi_aclk, -- global clock, rising edge
rst_i => m_axi_aresetn, -- global reset, async, LOW-active
-- parallel io --
gpio_o => gpio_o_int, -- parallel output
gpio_i => gpio_i_int, -- parallel input
-- pwm channels --
pwm_o => pwm_o_int, -- pwm channels
-- arbitrary frequency generator --
freq_gen_o => freq_gen_o_int, -- programmable frequency output
-- serial com --
uart_txd_o => uart_txd_o_int, -- UART send data
uart_rxd_i => uart_rxd_i_int, -- UART receive data
spi_sclk_o => spi_sclk_o_int, -- serial clock line
spi_mosi_o => spi_mosi_o_int, -- serial data line out
spi_miso_i => spi_miso_i_int, -- serial data line in
spi_cs_o => spi_cs_o_int, -- SPI CS
twi_sda_io => twi_sda_io, -- twi serial data line
twi_scl_io => twi_scl_io, -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o => wb_core.adr, -- address
wb_dat_i => wb_core.di, -- read data
wb_dat_o => wb_core.do, -- write data
wb_we_o => wb_core.we, -- read/write
wb_sel_o => wb_core.sel, -- byte enable
wb_stb_o => wb_core.stb, -- strobe
wb_cyc_o => wb_core.cyc, -- valid cycle
wb_ack_i => wb_core.ack, -- transfer acknowledge
-- interrupts --
ext_irq_i => irq_i_int, -- external interrupt request line
ext_ack_o => irq_ack_o_int -- external interrupt request acknowledge
);
-- Output Type Conversion ---------------------------------------------------
-- -----------------------------------------------------------------------------
gpio_i_int <= std_ulogic_vector(gpio_i);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
spi_miso_i_int <= std_ulogic(spi_miso_i);
irq_i_int <= std_ulogic_vector(ext_irq_i);
gpio_o <= std_logic_vector(gpio_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
uart_txd_o <= std_logic(uart_txd_o_int);
spi_sclk_o <= std_logic(spi_sclk_o_int);
spi_mosi_o <= std_logic(spi_mosi_o_int);
spi_cs_o <= std_logic_vector(spi_cs_o_int);
ext_ack_o <= std_logic_vector(irq_ack_o_int);
freq_gen_o <= std_logic_vector(freq_gen_o_int);
-- Wishbone-to-AXI4-Lite-compatible Bridge ----------------------------------
-- -----------------------------------------------------------------------------
-- transfer type --
read_trans <= wb_core.cyc and wb_core.stb and (not wb_core.we);
write_trans <= wb_core.cyc and wb_core.stb and wb_core.we;
-- arbiter --
axi_arbiter: process(m_axi_aclk)
begin
if rising_edge(m_axi_aclk) then
if (wb_core.cyc = '0') then
pending_rd <= '0';
pending_wr <= '0';
adr_valid <= '0';
m_axi_bready <= '0';
else
-- read/write address valid --
if ((wb_core.cyc and wb_core.stb) = '1') then
adr_valid <= '1';
elsif (m_axi_awready = '1') or (m_axi_arready = '1') then
adr_valid <= '0';
end if;
-- transfer read data --
if (read_trans = '1') then
pending_rd <= '1';
elsif (m_axi_rvalid = '1') then
pending_rd <= '0';
end if;
-- transfer write data --
if (write_trans = '1') then
pending_wr <= '1';
elsif (m_axi_wready = '1') then
pending_wr <= '0';
end if;
-- write response channel -
if (write_trans = '1') then
m_axi_bready <= '1';
elsif (m_axi_bvalid = '1') then
m_axi_bready <= '0';
end if;
end if;
end if;
end process axi_arbiter;
-- Acknowledge Wishbone transfer --
wb_core.ack <= (pending_rd and std_ulogic(m_axi_rvalid)) or -- read transfer
-- (pending_wr and std_ulogic(m_axi_wready)); -- write transfer
(wresp_ok and m_axi_bvalid); -- acknowledged write transfer
-- Read Address Channel --
m_axi_araddr <= std_logic_vector(wb_core.adr);
m_axi_arvalid <= std_logic(adr_valid) and std_logic(pending_rd);
m_axi_arprot <= "000"; -- data access, secure, unprivileged
-- Read Data Channel --
wb_core.di <= std_ulogic_vector(m_axi_rdata);
m_axi_rready <= std_logic(pending_rd);
-- Write Address Channel --
m_axi_awaddr <= std_logic_vector(wb_core.adr);
m_axi_awvalid <= std_logic(adr_valid) and std_logic(pending_wr);
m_axi_awprot <= "000"; -- data access, secure, unprivileged
-- Write Data Channel --
m_axi_wdata <= std_logic_vector(wb_core.do);
m_axi_wstrb <= std_logic_vector(wb_core.sel);
m_axi_wvalid <= std_logic(pending_wr);
-- Write Data Response Channel --
wresp_ok <= '1' when (m_axi_bresp = "00") else '0';
end neo430_top_axi4lite_rtl;
| bsd-3-clause |
stnolting/neo430 | rtl/core/neo430_control.vhd | 1 | 37906 | -- #################################################################################################
-- # << NEO430 - Main Control Unit >> #
-- # ********************************************************************************************* #
-- # Central CPU control unit (micro sequencer / FSM). #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_control is
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, low-active, async
-- memory interface --
instr_i : in std_ulogic_vector(15 downto 0); -- instruction word from memory
-- control --
sreg_i : in std_ulogic_vector(15 downto 0); -- current status register
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- control signals
irq_vec_o : out std_ulogic_vector(01 downto 0); -- irq channel address
imm_o : out std_ulogic_vector(15 downto 0); -- branch offset
-- irq lines --
irq_i : in std_ulogic_vector(03 downto 0) -- IRQ lines^
);
end neo430_control;
architecture neo430_control_rtl of neo430_control is
-- instruction register --
signal ir : std_ulogic_vector(15 downto 0);
signal ir_wren : std_ulogic;
-- branch system --
signal branch_taken : std_ulogic;
-- state machine --
type state_t is (RESET, IFETCH_0, IFETCH_1, DECODE,
TRANS_0, TRANS_1, TRANS_2, TRANS_3, TRANS_4, TRANS_5, TRANS_6,
PUSHCALL_0, PUSHCALL_1, PUSHCALL_2,
RETI_0, RETI_1, RETI_2, RETI_3,
IRQ_0, IRQ_1, IRQ_2, IRQ_3, IRQ_4, IRQ_5);
signal state, state_nxt : state_t;
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
signal am_nxt, am : std_ulogic_vector(03 downto 0); -- addressing mode
signal mem_rd, mem_rd_ff : std_ulogic; -- memory read buffers
signal src_nxt, src : std_ulogic_vector(03 downto 0); -- source reg
signal sam_nxt, sam : std_ulogic_vector(01 downto 0); -- CMD according SRC addressing mode
-- irq system --
signal irq_fire : std_ulogic;
signal irq_start, irq_ack : std_ulogic;
signal irq_ack_mask, irq_buf : std_ulogic_vector(3 downto 0);
signal irq_vec_nxt, irq_vec : std_ulogic_vector(1 downto 0);
signal i_flag_ff0, i_flag_ff1 : std_ulogic;
begin
-- Branch Condition Check ---------------------------------------------------
-- -----------------------------------------------------------------------------
cond_check: process(instr_i, sreg_i)
begin
case instr_i(12 downto 10) is -- condition
when cond_ne_c => branch_taken <= not sreg_i(sreg_z_c); -- JNE/JNZ
when cond_eq_c => branch_taken <= sreg_i(sreg_z_c); -- JEQ/JZ
when cond_lo_c => branch_taken <= not sreg_i(sreg_c_c); -- JNC/JLO
when cond_hs_c => branch_taken <= sreg_i(sreg_c_c); -- JC/JHS
when cond_mi_c => branch_taken <= sreg_i(sreg_n_c); -- JN
when cond_ge_c => branch_taken <= not (sreg_i(sreg_n_c) xor sreg_i(sreg_v_c)); -- JGE
when cond_le_c => branch_taken <= sreg_i(sreg_n_c) xor sreg_i(sreg_v_c); -- JL
when cond_al_c => branch_taken <= '1'; -- JMP (always)
when others => branch_taken <= '0'; -- undefined
end case;
end process cond_check;
-- branch offset (sign-extended) from instruction REGISTER --
imm_o <= ir(9) & ir(9) & ir(9) & ir(9) & ir(9) & ir(9 downto 0) & '0';
-- Arbiter State Machine Sync -----------------------------------------------
-- -----------------------------------------------------------------------------
arbiter_sync0: process(rst_i, clk_i)
begin
-- the arbiter requires a defined initial state
if (rst_i = '0') then
state <= RESET; -- this is crucial!
elsif rising_edge(clk_i) then
state <= state_nxt;
end if;
end process arbiter_sync0;
arbiter_sync1: process(clk_i)
begin
if rising_edge(clk_i) then
-- these signals do not need a specific reset state
ctrl <= ctrl_nxt;
src <= src_nxt;
mem_rd_ff <= mem_rd;
am <= am_nxt;
sam <= sam_nxt;
if (ir_wren = '1') then
ir <= instr_i; -- instruction register
end if;
end if;
end process arbiter_sync1;
-- control bus output --
ctrl_o <= ctrl;
-- someone using the DADD instruction? --
dadd_sanity_check: process(ir)
begin
if (ir(15 downto 12) = "1010") then -- DADD
assert false report "DADD instruction not supported!" severity warning;
end if;
end process dadd_sanity_check;
-- Arbiter State Machine Comb -----------------------------------------------
-- -----------------------------------------------------------------------------
arbiter_comb: process(state, instr_i, ir, ctrl, branch_taken, src, am, sam, mem_rd_ff, irq_start, sreg_i)
variable spec_cmd_v, valid_wb_v, move_cmd_v : std_ulogic;
begin
-- NOTES --
-- Signals in states/sub states marked with a "-->" are moved out of case statement and are set as pseudo default.
-- The general assigning of this signal does not effect states, which actually do not require this signal.
-- However, this saves some mux logic in the states.
-- arbiter defaults --
state_nxt <= state;
src_nxt <= src; -- source reg
am_nxt <= am; -- total addressing mode [OP class I/II, src_addr_mode(1), src_addr_mode(0), dst_addr_mode]
sam_nxt <= sam; -- default source addressing mode
ir_wren <= '0'; -- write to instruction register
mem_rd <= '0'; -- normal ("slow") memory read
irq_ack <= '0'; -- ack irq to irq-controller
-- control defaults --
ctrl_nxt <= (others => '0'); -- all off
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source reg A
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c); -- keep ALU function
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= sam; -- default SRC addressing mode
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2 as address offset
ctrl_nxt(ctrl_mem_rd_c) <= mem_rd_ff; -- delayed memory read
ctrl_nxt(ctrl_alu_bw_c) <= ctrl(ctrl_alu_bw_c); -- keep byte/word mode
-- special single ALU operation? --
spec_cmd_v := '0';
if (ir(15 downto 9) = "0001001") then -- CALL or PUSH or RETI
spec_cmd_v := '1';
end if;
-- is MOV operation? --
move_cmd_v := '0';
-- use ctrl's signals here, since MOV operation can be set by IR and by the FSM itself
if (ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) = alu_mov_c) then
move_cmd_v := '1';
end if;
-- valid write back? --
valid_wb_v := '1';
if (ir(15 downto 12) = alu_cmp_c) or (ir(15 downto 12) = alu_bit_c) then
valid_wb_v := '0'; -- CMP and BIT instructions only write status flags
end if;
-- state machine --
case state is
when RESET => -- init PC with boot address
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_boot_c) <= '1'; -- load boot address
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
state_nxt <= IFETCH_0;
when IFETCH_0 => -- output and update PC & IRQ check (stay here for SLEEP)
-- ------------------------------------------------------------
sam_nxt <= "00"; -- SRC address mode = REG, required for all special operations + IRQ
ctrl_nxt(ctrl_alu_bw_c) <= '0'; -- word mode, also required for all IRQ states
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output PC/IRQ vector
if (irq_start = '1') then -- execute IRQ
state_nxt <= IRQ_0;
elsif (sreg_i(sreg_s_c) = '0') then -- no sleep mode = normal execution
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= IFETCH_1;
end if;
when IFETCH_1 => -- wait for memory
-- ------------------------------------------------------------
state_nxt <= DECODE;
when DECODE => -- decode applied instruction & store it to IR
-- ------------------------------------------------------------
ir_wren <= '1'; -- update instruction register
ctrl_nxt(ctrl_alu_bw_c) <= instr_i(6); -- byte/word mode
sam_nxt <= instr_i(5 downto 4);
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC (used by branch instructions only)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "000"; -- add immediate offset (used by branch instructions only)
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback (used by branch instructions only)
if (instr_i(15 downto 14) = "00") then -- branch or format II instruction
if (instr_i(13) = '1') then -- BRANCH INSTRUCTION
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_wb_en_c) <= branch_taken; -- valid RF write back if branch taken
state_nxt <= IFETCH_0;
elsif (instr_i(12 downto 10) = "100") then -- FORMAT II INSTRUCTION
-- ------------------------------------------------------------
am_nxt(0) <= instr_i(4) or instr_i(5); -- dst addressing mode
am_nxt(3) <= '0'; -- class II
if (instr_i(3 downto 0) = reg_cg_c) or ((instr_i(3 downto 0) = reg_sr_c) and (instr_i(5) = '1')) then -- source special?
am_nxt(2 downto 1) <= "00"; -- source addressing mode
else
am_nxt(2 downto 1) <= instr_i(5 downto 4); -- source addressing mode
end if;
src_nxt <= instr_i(3 downto 0); -- src is also dst
if (instr_i(15 downto 9) /= "0001001") then -- not PUSH/CALL/RETI?
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= "00" & instr_i(8 downto 7); -- ALU function (rrc/swpb/rra/sxt)
else
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= alu_mov_c; -- to move OpA -> RF/MEM
end if;
case instr_i(9 downto 7) is
when "100" => state_nxt <= TRANS_0; -- PUSH (via single ALU OP)
when "101" => state_nxt <= TRANS_0; -- CALL (via single ALU OP)
when "110" => state_nxt <= RETI_0; -- RETI
when "111" => state_nxt <= IFETCH_0; -- !!!UNDEFINED OPCODE!!!
when others => state_nxt <= TRANS_0; -- single ALU OP (FORMAT II)
end case;
else -- !!!UNDEFINED OPCODE!!!
-- ------------------------------------------------------------
state_nxt <= IFETCH_0;
end if;
else -- FORMAT I INSTRUCTION
-- ------------------------------------------------------------
am_nxt(3) <= '1'; -- class I
if (instr_i(11 downto 8) = reg_cg_c) or ((instr_i(11 downto 8) = reg_sr_c) and (instr_i(5) = '1')) then -- source special?
am_nxt(2 downto 1) <= "00"; -- source addressing mode for r2 & r3
else
am_nxt(2 downto 1) <= instr_i(5 downto 4); -- source addressing mode
end if;
am_nxt(0) <= instr_i(7); -- dst addressing mode
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= instr_i(15 downto 12); -- ALU function
src_nxt <= instr_i(11 downto 8);
if (instr_i(15 downto 12) = "1010") then -- !!!INVALID ALUOP!!!
state_nxt <= IFETCH_0;
else
state_nxt <= TRANS_0;
end if;
end if;
when TRANS_0 => -- operand transfer cycle 0
-- ------------------------------------------------------------
-- (pseudo) defaults
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback (only relevant for when 2,3,5)
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_adr_mar_wr_c) <= am(0); -- write to MAR [relevant for memory writeback when using CLASS II operations]
--
case am is -- addressing mode
when "0001" | "0000" | "1000" =>
-- "0001" = CLASS II, SRC: Reg, DST: Indexed
-- "0000" = CLASS II, SRC/DST: register direct
-- "1000" = CLASS I, SRC/DST: Reg
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
elsif (am(3) = '0') then -- CLASS II operation
state_nxt <= TRANS_6;
else
state_nxt <= TRANS_3;
end if;
when "1001" | "1010" | "0010" | "0011" =>
-- "1001" = CLASS I, SRC: register direct, DST: indexed
--
-- "1010" = CLASS I, SRC: indexed/symbolic/absolute, DST: register direct
-- "001-" = CLASS II, SRC: indexed/symbolic/absolute, DST: indexed/symbolic/absolute OR register direct
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
--> ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
if (am(2 downto 1) = "00") then -- "1001" = CLASS I, SRC: register direct, DST: indexed
state_nxt <= TRANS_3;
else
state_nxt <= TRANS_2;
end if;
when "1011" =>
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= TRANS_1;
when "0100" | "0101" | "1100" | "1101" =>
-- "010-" = CLASS II, SRC/DST: indirect
-- "1100" = CLASS I, SRC: indirect, DST: register direct
-- "1101" = CLASS I, SRC: indirect, DST: indexed
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
--> cctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
state_nxt <= TRANS_1;
when others =>
-- "011-" = CLASS II, SRC/DST: indirect auto inc
-- "1110" = CLASS I, SRC: indirect auto inc, DST: register direct
-- "1111" = CLASS I, SRC: indirect auto inc, DST: indexed
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
--> cctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
if (ir(6) = '0') or (src = reg_pc_c) then -- word mode (force if accessing PC)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
else -- byte mode
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "001"; -- add +1
end if;
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= TRANS_1;
end case;
when TRANS_1 => -- operand transfer cycle 1
-- ------------------------------------------------------------
-- (pseudo) defaults
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback (only relevant for last two 'when')
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
--
case am is -- addressing mode
-- "000-" = CLASS II, SRC/DST: register direct [ACTUAL DON'T CARE; STATE NOT USED]
-- "1000" = CLASS I, SRC: register direct, DST: register direct [ACTUAL DON'T CARE; STATE NOT USED]
-- "1001" = CLASS I, SRC: register direct, DST: indexed [ACTUAL DON'T CARE; STATE NOT USED]
-- ==> DONT CARE
-- "001-" = CLASS II, SRC/DST: indexed/symbolic/absolute [ACTUAL DON'T CARE; STATE NOT USED]
-- "1010" = CLASS I, SRC: indexed/symbolic/absolute, DST: register direct [ACTUAL DON'T CARE; STATE NOT USED]
-- ==> DONT CARE
when "0100" | "0101" | "1100" | "0110" | "0111" | "1110" =>
-- "010-" = CLASS II, SRC/DST: indirect
-- "1100" = CLASS I, SRC: indirect, DST: register direct
--
-- "011-" = CLASS II, SRC/DST: indirect auto inc,
-- "1110" = CLASS I, SRC: indirect auto inc, DST: register direct
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
else
if (am(3) = '0') then -- CLASS II
state_nxt <= TRANS_6;
else -- CLASS I
state_nxt <= TRANS_3;
end if;
end if;
when "1101" | "1111" =>
-- "1101" = CLASS I, SRC: indirect, DST: indexed
--
-- "1111" = CLASS I, SRC: indirect auto inc, DST: indexed
--> ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
--> ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
state_nxt <= TRANS_3; -- no PUSHCALL check required
when others =>
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
--> ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
--> ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= TRANS_2;
end case;
when TRANS_2 => -- operand transfer cycle 2
-- ------------------------------------------------------------
-- "001-" = CLASS II: SRC/DST: indexed/symbolic/absolute
-- "1010" = CLASS I, SRC: indexed/symbolic/absolute, DST: register direct
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
-- OTHERS = DONT CARE [state not reachable]
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in (only relevant for first 'when')
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
state_nxt <= TRANS_3;
when TRANS_3 => -- operand transfer cycle 3
-- ------------------------------------------------------------
-- (pseudo) defaults
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= ir(3 downto 0); -- source: reg B
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in
--
case am is -- addressing mode
when "1001" | "1011" | "1101" | "1111" =>
-- "1001" = CLASS I, SRC: register direct, DST: indexed
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
-- "1101" = CLASS I, SRC: indirect, DST: indexed
-- "1111" = CLASS I, SRC: indirect auto inc, DST: indexed
ctrl_nxt(ctrl_rf_as1_c) <= '0'; -- DST address mode = REG or INDEXED
ctrl_nxt(ctrl_rf_as0_c) <= ir(7); -- DST address mode = REG or INDEXED
--> ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in
--> ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
if (ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) /= alu_mov_c) then -- no read for MOV
mem_rd <= '1'; -- Memory read
end if;
state_nxt <= TRANS_4;
when others =>
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= "00"; -- DST address mode = REG
ctrl_nxt(ctrl_alu_opb_wr_c) <= '1'; -- write OpB
if (am(2 downto 1) = "01") then
state_nxt <= TRANS_4;
else
state_nxt <= TRANS_6;
end if;
end case;
when TRANS_4 => -- operand transfer cycle 4
-- ------------------------------------------------------------
-- (pseudo) defaults
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A (only relevant for 3rd 'when')
--
case am is -- addressing mode
when "0010" | "0011" | "1010" | "1011" =>
-- "001-" = CLASS II, SRC/DST: indexed/symbolic/absolute
-- "1010" = CLASS I, SRC: indexed/symbolic/absolute, DST: register direct
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
elsif ((am(3) and am(0)) = '1') and (move_cmd_v = '0') then -- skip processing of second operand when executing MOV instruction
state_nxt <= TRANS_5;
else
state_nxt <= TRANS_6;
end if;
when "1001" =>
-- "1001" = CLASS I, SRC: register direct, DST: indexed
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
if (move_cmd_v = '1') then -- skip processing of second operand when executing MOV instruction
state_nxt <= TRANS_6;
else
state_nxt <= TRANS_5;
end if;
when others => -- NOP / DONT CARE
-- "000-" = CLASS II, SRD/DST: DONT CARE
-- "1000" = CLASS I, SRC: register direct, DST: register direct = DONT CARE
-- "-10-" : NOP
-- "-11-" : NOP
if (move_cmd_v = '1') then -- skip processing of second operand when executing MOV instruction
state_nxt <= TRANS_6;
else
state_nxt <= TRANS_5;
end if;
end case;
when TRANS_5 => -- operand transfer cycle 5
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opb_wr_c) <= '1'; -- write to OpB
state_nxt <= TRANS_6;
when TRANS_6 => -- operand transfer cycle 6: RF or MEM write-back
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= ir(3 downto 0); -- destination
ctrl_nxt(ctrl_rf_fup_c) <= not spec_cmd_v; -- update ALU status flags
if (am(0) = '0') then -- DST: register direct (register file)
ctrl_nxt(ctrl_rf_wb_en_c) <= valid_wb_v; -- valid RF write back (not for CMP/BIT!)
else -- DST: indexed (memory)
ctrl_nxt(ctrl_mem_wr_c) <= valid_wb_v; -- valid MEM write back (not for CMP/BIT!)
end if;
state_nxt <= IFETCH_0; -- done!
when PUSHCALL_0 => -- PUSH/CALL cycle 0 (stack update)
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= alu_mov_c; -- keep this for all following states
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "011"; -- add -2
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
if (ir(7) = '1') then -- CALL
state_nxt <= PUSHCALL_1;
else -- PUSH
state_nxt <= PUSHCALL_2;
end if;
when PUSHCALL_1 => -- CALL cycle 1 (buffer PC so it can be written to memory)
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= PUSHCALL_2;
when PUSHCALL_2 => -- PUSH/CALL cycle 2 (write data to memory)
-- ------------------------------------------------------------
ctrl_nxt(ctrl_mem_wr_c) <= '1'; -- memory write request
state_nxt <= IFETCH_0; -- done!
when RETI_0 => -- RETI cycle 0: Output address of old SR; SP=SP+2
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= alu_mov_c; -- keep this for all following states
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= RETI_1;
when RETI_1 => -- RETI cycle 1: Buffer status register from MEM in OpA; Output address of old PC; SP=SP+2
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
state_nxt <= RETI_2;
when RETI_2 => -- RETI cycle 4: Write status register; buffer return address from MEM in OpA
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sr_c; -- destination: SR
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= RETI_3;
when RETI_3 => -- RETI cycle 5: Write return address to PC
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- destination: PC
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= IFETCH_0; -- done!
when IRQ_0 => -- IRQ processing cycle 0: SP=SP-2, disable sleep mode
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= alu_mov_c; -- keep this for all following states
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "011"; -- add -2
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
ctrl_nxt(ctrl_rf_dsleep_c) <= '1'; -- disable sleep mode
state_nxt <= IRQ_1;
when IRQ_1 => -- IRQ processing cycle 1: Buffer PC for memory write
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source: PC
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write PC to OpA
state_nxt <= IRQ_2;
when IRQ_2 => -- IRQ processing cycle 2: Write PC to memory (push), SP=SP-2
-- ------------------------------------------------------------
ctrl_nxt(ctrl_mem_wr_c) <= '1'; -- write memory request (store PC)
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "011"; -- add -2
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= IRQ_3;
when IRQ_3 => -- IRQ processing cycle 3: Buffer SR for memory write, set IRQ vector address, disable interrupt enable flag in SR
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sr_c; -- source: SR
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write SR to OpA
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output PC/IRQ vector
ctrl_nxt(ctrl_adr_ivec_oe_c) <= '1'; -- output IRQ vector
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_rf_dgie_c) <= '1'; -- disable interrupt enable flag
irq_ack <= '1'; -- acknowledge started IRQ handler
state_nxt <= IRQ_4;
when IRQ_4 => -- IRQ processing cycle 4: Write SR (push), get IRQ vector
-- ------------------------------------------------------------
ctrl_nxt(ctrl_mem_wr_c) <= '1'; -- write memory request
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
state_nxt <= IRQ_5;
when IRQ_5 => -- IRQ processing cycle 5: Store IRQ vector to PC
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- destination: PC
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= IFETCH_0; -- done!
when others => -- invalid
-- ------------------------------------------------------------
state_nxt <= RESET;
end case;
end process arbiter_comb;
-- Interrupt Controller -----------------------------------------------------
-- -----------------------------------------------------------------------------
irq_buffer: process(clk_i)
begin
if rising_edge(clk_i) then
-- delay I flag 2 cycles to allow the interrupted program to execute at least one insruction even if we have
-- a permanent interrupt request
i_flag_ff0 <= sreg_i(sreg_i_c);
i_flag_ff1 <= i_flag_ff0;
-- interrupt vector and queue buffer --
for i in 0 to 3 loop
irq_buf(i) <= (irq_buf(i) or irq_i(i)) and (not sreg_i(sreg_q_c)) and (not irq_ack_mask(i));
end loop; -- i
-- interrupt control --
if (irq_start = '0') or (sreg_i(sreg_i_c) = '0') then -- idle or IRQs disabled
irq_start <= '0';
if (irq_fire = '1') then -- IRQ triggered
irq_vec <= irq_vec_nxt; -- capture source
irq_start <= '1';
end if;
else -- active IRQ
if (irq_ack = '1') then -- handler started?
irq_start <= '0';
end if;
end if;
end if;
end process irq_buffer;
-- valid start of IRQ handler --
irq_fire <= '1' when (irq_buf /= "0000") and (i_flag_ff1 = '1') and (sreg_i(sreg_i_c) = '1') else '0';
-- acknowledge mask --
irq_ack_mask_gen: process(irq_ack, irq_vec)
variable irq_tmp_v : std_ulogic_vector(2 downto 0);
begin
irq_tmp_v := irq_ack & irq_vec;
case irq_tmp_v is
when "100" => irq_ack_mask <= "0001";
when "101" => irq_ack_mask <= "0010";
when "110" => irq_ack_mask <= "0100";
when "111" => irq_ack_mask <= "1000";
when others => irq_ack_mask <= "0000";
end case;
end process;
-- interrupt priority encoder --
irq_priority: process(irq_buf)
begin
-- use "case" here to avoid a MUX chain
case irq_buf is
when "0001" | "0011" | "0101" | "0111" | "1001" | "1011" | "1101" | "1111" => -- "---1"
irq_vec_nxt <= "00";
when "0010" | "0110" | "1010" | "1110" => -- "--10"
irq_vec_nxt <= "01";
when "0100" | "1100" => -- "-100"
irq_vec_nxt <= "10";
when others => -- "1000" ("0000" -> dont't care)
irq_vec_nxt <= "11";
end case;
end process irq_priority;
-- interrupt vector output --
irq_vec_o <= irq_vec; -- the final address is constructed in the address generator
end neo430_control_rtl;
| bsd-3-clause |
stnolting/neo430 | rtl/core/neo430_gpio.vhd | 1 | 7342 | -- #################################################################################################
-- # << NEO430 - General Purpose Parallel IO Unit >> #
-- # ********************************************************************************************* #
-- # 16-bit parallel input & output unit. Any pin-change (HI->LO or LO->HI) triggers the IRQ. #
-- # Pins used for the pin change interrupt are selected using a 16-bit mask. #
-- # The PWM controller can be used to module the GPIO controller's output. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_gpio is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- parallel io --
gpio_o : out std_ulogic_vector(15 downto 0);
gpio_i : in std_ulogic_vector(15 downto 0);
-- GPIO PWM --
gpio_pwm_i : in std_ulogic;
-- interrupt --
irq_o : out std_ulogic
);
end neo430_gpio;
architecture neo430_gpio_rtl of neo430_gpio is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(gpio_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wren : std_ulogic; -- word write enable
signal rden : std_ulogic; -- read enable
-- accessible regs --
signal dout, din : std_ulogic_vector(15 downto 0); -- r/w
signal irq_mask : std_ulogic_vector(15 downto 0); -- -/w
-- misc --
signal irq_raw, sync_in, in_buf : std_ulogic_vector(15 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gpio_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= gpio_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wren = '1') then
if (addr = gpio_out_addr_c) then
dout <= data_i;
end if;
if (addr = gpio_irqmask_addr_c) then
irq_mask <= data_i;
end if;
end if;
end if;
end process wr_access;
-- (PWM modulated) output --
gpio_o <= dout when (gpio_pwm_i = '1') else (others => '0');
-- IRQ Generator ------------------------------------------------------------
-- -----------------------------------------------------------------------------
irq_generator: process(clk_i)
begin
if rising_edge(clk_i) then
-- input synchronizer --
in_buf <= gpio_i;
din <= in_buf;
sync_in <= din;
-- IRQ --
irq_o <= or_all_f(irq_raw);
end if;
end process irq_generator;
-- any transition triggers an interrupt (if enabled for according input pin) --
irq_raw <= (din xor sync_in) and irq_mask;
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- read access --
data_o <= (others => '0');
if (rden = '1') then
if (addr = gpio_in_addr_c) then
data_o <= din;
else -- gpio_out_addr_c
data_o <= dout;
end if;
end if;
end if;
end process rd_access;
end neo430_gpio_rtl;
| bsd-3-clause |
dergraaf/loa | fpga/modules/utils/hdl/clock_divider.vhd | 2 | 1185 | --!
--! Generic clock divider
--!
--! Generates an clock enable signal.
--!
--! Example:
--! @code
--! process (clk)
--! begin
--! if rising_edge(clk) then
--! if enable = '1' then
--! ... do something with the period of the divided frequency ...
--! end if;
--! end if;
--! end process;
--! @endcode
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock_divider is
generic (
DIV : positive := 2);
port (
clk_out_p : out std_logic := '0'; -- Enable output ('1' for one clock cycle)
clk : in std_logic -- System clock
);
end clock_divider;
-- ----------------------------------------------------------------------------
architecture behavior of clock_divider is
begin
process
variable counter : integer range 0 to DIV := 0;
begin
wait until rising_edge(clk);
counter := counter + 1;
if counter = DIV then
counter := 0;
clk_out_p <= '1';
else
clk_out_p <= '0';
end if;
end process;
end behavior;
| bsd-3-clause |
dergraaf/loa | fpga/modules/peripheral_register/tb/reg_file_bram_double_buffered_tb.vhd | 2 | 4205 | -------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file_bram_double_buffered"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xilinx_block_ram_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_bram_double_buffered_tb is
end reg_file_bram_double_buffered_tb;
-------------------------------------------------------------------------------
architecture tb of reg_file_bram_double_buffered_tb is
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 0;
-- component ports
signal bus_o : busdevice_out_type := (data => (others => '0'));
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal bram_data_i : std_logic_vector(35 downto 0) := (others => '0');
signal bram_data_o : std_logic_vector(35 downto 0) := (others => '0');
signal bram_addr_i : std_logic_vector(7 downto 0) := (others => '0');
signal bram_we_p : std_logic := '0';
signal irq_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal ready_p : std_logic := '0';
signal enable_p : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : reg_file_bram_double_buffered
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
bus_o => bus_o,
bus_i => bus_i,
bram_data_i => bram_data_i,
bram_data_o => bram_data_o,
bram_addr_i => bram_addr_i,
bram_we_p => bram_we_p,
irq_o => irq_p,
ack_i => ack_p,
ready_i => ready_p,
enable_o => enable_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
-- purpose: read data from BRAM to bus
bus_Proc : process
begin
-- wait until some data was written to BRAM
for ii in 0 to 10 loop
wait until Clk = '0';
end loop; -- ii
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- read from 0 to 511
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0000", bus_i.addr'length)));
bus_i.re <= '1';
wait until clk = '0';
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0001", bus_i.addr'length)));
wait until clk = '0';
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0002", bus_i.addr'length)));
wait until clk = '0';
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0003", bus_i.addr'length)));
-- do not repeat
wait for 10 ms;
end process bus_Proc;
-- purpose: Simulates the Application writing and reading data to and from the block RAM port B
-- type : sequential
application_proc : process
begin -- process application_proc
wait until clk = '0';
wait until clk = '0';
bram_we_p <= '1';
bram_addr_i <= (others => '0');
bram_data_i <= std_logic_vector(unsigned'(resize(x"3153853fa", bram_data_i'length)));
wait until clk = '0';
bram_addr_i <= std_logic_vector(unsigned'(resize(x"00001", bram_addr_i'length)));
bram_data_i <= std_logic_vector(unsigned'(resize(x"854ff5a41", bram_data_i'length)));
wait until clk = '0';
bram_we_p <= '0';
-- do not repeat
wait for 10 ms;
end process application_proc;
end tb;
| bsd-3-clause |
dergraaf/loa | fpga/modules/peripheral_register/hdl/reg_file_bram_double_buffered.vhd | 2 | 10020 | -------------------------------------------------------------------------------
-- Title : reg_file_bram_double_buffered.vhd
-- Project :
-------------------------------------------------------------------------------
-- File : reg_file_bram_double_buffered.vhd
-- Author : strongly-typed
-- Company :
-- Created : 2012-04-22
-- Platform : Xilinx Spartan 3A
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: A Larger Register File Using Block RAM.
--
-- A dual port block RAM is interfaced to the internal parallel
-- bus and double buffering is implemented. Double buffering
-- guarantees that the data read by the SPI slave is not
-- comprimised while new data is written to the block RAM by the
-- other component.
-- If no double buffering was implemented new and old data may get
-- mixed up.
--
-- This register file was designed for the Goertzel algorithm.
-- It was implemented with a calc width of 18 bits (because the
-- mulipliers are 18 bits wide). The result and the intermediate
-- data are two words of 18 bits so a data width of 36 bits was
-- chosen. This fits perfectly well to the Block RAM.
--
-- Each SelectRAM in Spartan-3(A/E/AN) has 18432 data bits and can
-- be configured as 512 address x 36 data bits.
--
-- Double buffering is implemented by toggeling the MSB of the
-- address.
--
-- Port A: parallel bus:
-- 2 x 512 addresses of 18 bits, lower two data bits are discarded
-- 512 address = 9 bits (8 downto 0)
--
-- Port B: Goertzel Algorithm:
-- 2 x 256 addresses of 36 bits
-- 256 addresses = 8 bits (7 downto 0)
--
-------------------------------------------------------------------------------
-- Todo: * Generic widths
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.xilinx_block_ram_pkg.all;
use work.utils_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_bram_double_buffered is
generic (
-- The module uses 9 bits for 512 addresses and the base address must be aligned.
-- Valid BASE_ADDRESSes are 0x0000, 0x0200, 0x0400, 0x0600, ...
BASE_ADDRESS : integer range 0 to 2**15-1);
port (
-- Interface to the internal parallel bus.
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- Read and write interface to the block RAM for the application.
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_addr_i : in std_logic_vector(7 downto 0);
bram_we_p : in std_logic;
-- Inform the STM that new results are ready to be fetched.
irq_o : out std_logic;
-- Get an acknowledge from the STM that all results are fetched.
ack_i : in std_logic;
-- Get informed by the application that it has written a new set of results
-- to the block RAM.
ready_i : in std_logic;
-- Allow the application to write new data to the block RAM.
enable_o : out std_logic;
-- Show to which bank the application writes at the moment
bank_x_o : out std_logic; -- The bank that is currently mapped to
-- the bus.
bank_y_o : out std_logic; -- The bank that is currently mapped to
-- the application.
-- No reset, all signals are initialised.
clk : in std_logic);
end reg_file_bram_double_buffered;
-------------------------------------------------------------------------------
architecture str of reg_file_bram_double_buffered is
----------------------------------------------------------------------------
-- Configuration
----------------------------------------------------------------------------
constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) :=
std_logic_vector(to_unsigned(BASE_ADDRESS, 15));
-- Port A to bus
constant ADDR_A_WIDTH : positive := 10;
constant DATA_A_WIDTH : positive := 18;
-- Port B to application
constant ADDR_B_WIDTH : positive := 9;
constant DATA_B_WIDTH : positive := 36;
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type ram_a_in_type is record
addr : std_logic_vector(ADDR_A_WIDTH-1 downto 0);
data : std_logic_vector(DATA_A_WIDTH-1 downto 0);
we : std_logic;
en : std_logic;
ssr : std_logic;
end record;
type ram_a_out_type is record
data : std_logic_vector(DATA_A_WIDTH-1 downto 0);
end record;
type ram_b_in_type is record
addr : std_logic_vector(ADDR_B_WIDTH-1 downto 0);
data : std_logic_vector(DATA_B_WIDTH-1 downto 0);
we : std_logic;
en : std_logic;
ssr : std_logic;
end record;
type ram_b_out_type is record
data : std_logic_vector(DATA_B_WIDTH-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal ram_a_in : ram_a_in_type;
signal ram_a_out : ram_a_out_type;
signal ram_b_in : ram_b_in_type;
signal ram_b_out : ram_b_out_type;
signal data_bus_out : std_logic_vector(15 downto 0) := (others => '0');
signal bank : std_logic := '0';
signal bank_x : std_logic;
signal bank_y : std_logic;
signal addr_match_a : std_logic;
begin -- str
----------------------------------------------------------------------------
-- Connections
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Bank switching
-- Call the banks X and Y to not confuse with Port A and B of the Dual port
-- RAM.
--
-- Signals:
-- ----------------
-- irq_p to bus
-- ack_p form bus
-- ready_p from app
-- enable_p to app
--
---------------------------------------------------------------------------
bank_x <= bank;
bank_y <= not bank;
-- Output the current bank information for use by other double buffering registers.
bank_x_o <= bank_x;
bank_y_o <= bank_y;
double_buffering_1 : entity work.double_buffering
port map (
ready_p => ready_i,
enable_p => enable_o,
irq_p => irq_o,
ack_p => ack_i,
bank_p => bank,
clk => clk);
----------------------------------------------------------------------------
-- Block RAM as dual port RAM with asymmetrical port widths.
----------------------------------------------------------------------------
dp_1 : xilinx_block_ram_dual_port
generic map (
ADDR_A_WIDTH => ADDR_A_WIDTH,
ADDR_B_WIDTH => ADDR_B_WIDTH,
DATA_A_WIDTH => DATA_A_WIDTH,
DATA_B_WIDTH => DATA_B_WIDTH)
port map (
addr_a => ram_a_in.addr,
addr_b => ram_b_in.addr,
din_a => ram_a_in.data,
din_b => ram_b_in.data,
dout_a => ram_a_out.data,
dout_b => ram_b_out.data,
we_a => ram_a_in.we,
we_b => ram_b_in.we,
en_a => ram_a_in.en,
en_b => ram_b_in.en,
ssr_a => ram_a_in.ssr,
ssr_b => ram_b_in.ssr,
clk_a => clk,
clk_b => clk);
----------------------------------------------------------------------------
-- Port B
----------------------------------------------------------------------------
-- Transfer data to and from the application to and from the RAM
-- Do the bank switching here.
-- 9 = 1 + 8
ram_b_in.addr <= bank_y & bram_addr_i;
ram_b_in.data <= bram_data_i;
ram_b_in.en <= '1';
ram_b_in.we <= bram_we_p;
ram_b_in.ssr <= '0';
bram_data_o <= ram_b_out.data;
-----------------------------------------------------------------------------
-- Port A: parallel data bus
----------------------------------------------------------------------------
-- enable
ram_a_in.en <= '1';
-- Always present the address from the parallel bus to the block RAM.
-- When the bus address matches the address range of the block RAM
-- route the result of the Block RAM to the parallel bus.
-- Do the bank switching here.
-----------------------------------------------------------------------------
-- 10 = 1 + 9
ram_a_in.addr <= bank_x & bus_i.addr(8 downto 0);
ram_a_in.data <= "00" & bus_i.data;
addr_match_a <= '1' when (bus_i.addr(14 downto 9) = BASE_ADDRESS_VECTOR(14 downto 9)) else '0';
-- The block RAM keeps its output latches when EN is '0'. This behaviour is
-- not compatible with the parallel bus where the bus output must be 0 when
-- the device is not selected.
-- Solution: Use Synchronous Reset of the output latches:
ram_a_in.ssr <= '0' when (addr_match_a = '1') and (bus_i.re = '1') else '1';
-- Write enable
ram_a_in.we <= '1' when (addr_match_a = '1') and (bus_i.we = '1') else '0';
-- upper 16 bits of RAM (most significant bits of Q13 number)
bus_o.data <= ram_a_out.data(17 downto 2);
end str;
-------------------------------------------------------------------------------
| bsd-3-clause |
dergraaf/loa | fpga/toplevel/beacon_robot_test2/toplevel.vhd | 1 | 8944 | -------------------------------------------------------------------------------
-- Title : Mobile Beacon
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3A-200
-------------------------------------------------------------------------------
-- Description: Test file for testing the Block SRAM in hardware with double
-- buffering.
--
-- A process writes some test data into the Block RAM immediately after reset
-- so that it can be read from the SPI bus.
--
-- What to test with the STM:
--
-- 1) The process starts to write data to the BRAM.
-- 2) When it finishes it assigns ready_i = '1'.
-- 3) This signalises the STM that new data is available by pulling IRQ = '1'.
-- 4) The STM can read data from the BRAM with the SPI slave.
-- 5) The STM signalises that it has finished reading by sending a pulse on
-- ACK.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.spislave_pkg.all;
use work.reg_file_pkg.all;
use work.motor_control_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.utils_pkg.all;
use work.ir_rx_module_pkg.all;
-------------------------------------------------------------------------------
entity toplevel is
port (
-- Connections to the STM32F407
-- SPI
cs_np : in std_logic;
sck_p : in std_logic;
miso_p : out std_logic;
mosi_p : in std_logic;
-- hardwired
ir_irq_p : out std_logic;
us_irq_p : out std_logic;
ir_ack_p : in std_logic;
us_ack_p : in std_logic;
-- 4 MBit SRAM CY7C1049DV33-10ZSXI (428-1982-ND)
sram_addr_p : out std_logic_vector(18 downto 0);
sram_data_p : inout std_logic_vector(7 downto 0);
sram_oe_np : out std_logic;
sram_we_np : out std_logic;
sram_ce_np : out std_logic;
-- US TX
us_tx0_p : out half_bridge_type;
us_tx1_p : out half_bridge_type;
us_tx2_p : out half_bridge_type;
-- US RX: one LTC2351 ADC
us_rx_spi_in_p : in adc_ltc2351_spi_in_type;
us_rx_spi_out_p : out adc_ltc2351_spi_out_type;
-- IR TX
ir_tx_p : out std_logic;
-- IR RX: two LTC2351 ADC
ir_rx_spi_out_p : out adc_ltc2351_spi_out_type;
ir_rx0_spi_in_p : in adc_ltc2351_spi_in_type;
ir_rx1_spi_in_p : in adc_ltc2351_spi_in_type;
clk : in std_logic
);
end toplevel;
architecture structural of toplevel is
constant BASE_ADDR_REG : natural := 16#0000#;
constant BASE_ADDR_REG_FILE_BRAM : natural := 16#0400#;
-- reset is unused in this design!
signal reset : std_logic := '0';
signal register_out : std_logic_vector(15 downto 0);
signal register_in : std_logic_vector(15 downto 0);
-- Modulation
signal mod_cnt : natural := 0;
signal modulation_us : std_logic_vector(2 downto 0) := (others => '0');
signal clk_modulation_us_s : std_logic := '0';
-- Synchronise inputs
signal ir_ack_r : std_logic_vector(1 downto 0) := (others => '0');
signal ir_ack : std_logic;
signal us_ack_r : std_logic_vector(1 downto 0) := (others => '0');
signal us_ack : std_logic;
-- Connection to the Busmaster
signal bus_from_spi : busmaster_out_type;
signal bus_i : busmaster_in_type;
-- Outputs form the Bus devices
signal bus_register_out : busdevice_out_type;
signal bus_reg_file_bram_out : busdevice_out_type;
-- Common clock enable for ADCs
signal clk_adc_en_s : std_logic;
-- Connections to and from the IR ADCs
signal ir_rx_module_spi_out : ir_rx_module_spi_out_type;
signal ir_rx_module_spi_in : ir_rx_module_spi_in_type;
-- Bidirectional SRAM pins
signal sram_data_o : std_logic_vector(7 downto 0) := (others => '0');
signal sram_data_i : std_logic_vector(7 downto 0) := (others => '0');
signal sram_data_en : std_logic := '0';
-- signals to and from BRAM
signal bram_data_o : std_logic_vector(35 downto 0);
signal bram_data_i : std_logic_vector(35 downto 0);
signal bram_we : std_logic := '0';
signal bram_addr : std_logic_vector(7 downto 0);
-- debug signal
signal debug_data_done : std_logic := '0';
begin
----------------------------------------------------------------------------
-- Bus connections
----------------------------------------------------------------------------
bus_i.data <= bus_register_out.data or
bus_reg_file_bram_out.data;
----------------------------------------------------------------------------
-- SPI connection to the STM32F4xx and Busmaster for the internal bus
----------------------------------------------------------------------------
spi : spi_slave
port map (
miso_p => miso_p,
mosi_p => mosi_p,
sck_p => sck_p,
csn_p => cs_np,
bus_o => bus_from_spi,
bus_i => bus_i,
clk => clk);
----------------------------------------------------------------------------
-- 4 MBit SRAM CY7C1049DV33-10ZSXI (428-1982-ND)
----------------------------------------------------------------------------
-- purpose: Bidirectional Interface for SRAM
-- type : sequential
sram_data_p <= sram_data_o when (sram_data_en = '1') else (others => 'Z');
sram_data_i <= sram_data_p;
sram_addr_p <= (others => '0');
sram_ce_np <= 'Z';
sram_we_np <= 'Z';
sram_oe_np <= 'Z';
----------------------------------------------------------------------------
-- Single Register
----------------------------------------------------------------------------
preg : peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDR_REG)
port map (
dout_p => register_out,
din_p => register_in,
bus_o => bus_register_out,
bus_i => bus_from_spi,
clk => clk);
-- test Data
register_in <= x"abc" & "0000"; -- test data, required by C++
----------------------------------------------------------------------------
-- Block RAM as register
----------------------------------------------------------------------------
--reg_file_bram_1 : entity work.reg_file_bram
-- generic map (
-- BASE_ADDRESS => BASE_ADDR_REG_FILE_BRAM)
-- port map (
-- bus_o => bus_reg_file_bram_out,
-- bus_i => bus_from_spi,
-- bram_data_i => bram_data_i,
-- bram_data_o => bram_data_o,
-- bram_addr_i => bram_addr,
-- bram_we_p => bram_we,
-- clk => clk);
reg_file_bram_double_buffered_1 : reg_file_bram_double_buffered
generic map (
BASE_ADDRESS => BASE_ADDR_REG_FILE_BRAM)
port map (
bus_o => bus_reg_file_bram_out,
bus_i => bus_from_spi,
bram_data_i => bram_data_i,
bram_data_o => bram_data_o,
bram_addr_i => bram_addr,
bram_we_p => bram_we,
irq_o => ir_irq_p,
ack_i => ir_ack_p,
ready_i => debug_data_done,
enable_o => open,
clk => clk);
-- purpose: Fills the Bram with some test data
fill_bram : process (clk) is
variable addr : unsigned(7 downto 0) := (others => '0');
variable en : std_logic := '1';
begin -- process fill_bram
if rising_edge(clk) then -- rising clock edge
if en = '1' then
bram_we <= '1';
bram_addr <= std_logic_vector(addr);
-- 8 + 8 + 2 + 8 + 8 + 2 = 36
bram_data_i <= std_logic_vector(addr) & "0" & std_logic_vector(addr) & "0" &
std_logic_vector(addr) & "0" & std_logic_vector(addr) & "0";
addr := addr + 1;
if addr = "11111111" then
debug_data_done <= '1';
else
if addr = "00000000" then
en := '0';
bram_we <= '0';
debug_data_done <= '0';
end if;
end if;
end if;
end if;
end process fill_bram;
----------------------------------------------------------------------------
-- Unconnected pins
----------------------------------------------------------------------------
-- ir_irq_p <= ir_ack_p;
us_irq_p <= us_ack_p;
us_rx_spi_out_p.sck <= '0';
us_rx_spi_out_p.conv <= '0';
us_tx0_p.low <= '0';
us_tx0_p.high <= '0';
us_tx1_p.low <= '0';
us_tx1_p.high <= '0';
us_tx2_p.low <= '0';
us_tx2_p.high <= '0';
ir_tx_p <= '0';
ir_rx_spi_out_p.sck <= '0';
ir_rx_spi_out_p.conv <= '0';
end structural;
| bsd-3-clause |
dergraaf/loa | fpga/modules/signalprocessing/hdl/goertzel.vhd | 2 | 5818 | -------------------------------------------------------------------------------
-- Title : Fixed point implementation of Goertzel's Algorithm
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Fixed point implementation of Goertzel's Algorithm to detect a
-- fixed frequency in an analog signal. This does not implement the calculation
-- of the magnitude of the signal at the end of one block.
-- Mind overflows!
-- This implementation only calulates one channel and one frequency. For each
-- channel and each frequency this needs another multiplier. So this is not
-- used any more.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel is
generic (
-- Width of ADC input
-- Due to overflow prevention: Not as wide as the internal width of
-- calculations.
INPUT_WIDTH : natural := 14;
-- Width of internal calculations
-- Remember that internal multiplier are 18 bits wide (in Xilinx Spartan)
CALC_WIDTH : natural := 18;
-- Fixed point data format
Q : natural := 13;
-- Number of samples used to detect a frequency.
-- After SAMPLES samples new goertzel values are available.
SAMPLES : natural := 250
);
port (
coef_p : in unsigned(CALC_WIDTH-1 downto 0);
start_p : in std_logic; -- clock enable, is high when new value
-- from ADC is available.
adc_value_p : in signed(INPUT_WIDTH-1 downto 0);
result_p : out goertzel_result_type;
done_p : out std_logic; -- clock enable outut, is high when new
-- result was generated
clk : in std_logic
);
end goertzel;
architecture behavioural of goertzel is
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type goertzel_state_type is (
IDLE,
CALC1
);
type goertzel_type is record
state : goertzel_state_type;
done : std_logic;
delay0 : signed(CALC_WIDTH-1 downto 0);
delay1 : signed(CALC_WIDTH-1 downto 0);
delay2 : signed(CALC_WIDTH-1 downto 0);
result : goertzel_result_type;
sample_count : natural;
end record;
----------------------------------------------------------------------------
-- Internal signals
----------------------------------------------------------------------------
signal r, rin : goertzel_type := (
state => IDLE,
sample_count => 1,
done => '0',
delay0 => (others => '0'),
delay1 => (others => '0'),
delay2 => (others => '0'),
result => (others => (others => '0'))
);
begin -- behavioural
----------------------------------------------------------------------------
-- Mapping of signals
----------------------------------------------------------------------------
done_p <= r.done;
result_p <= r.result;
----------------------------------------------------------------------------
-- Sequential part of FSM
----------------------------------------------------------------------------
seq_proc : process (clk)
begin -- process seq_proc
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Transitions and actions of FSM
----------------------------------------------------------------------------
comb_proc : process (adc_value_p, coef_p, r, rin, start_p)
variable v : goertzel_type;
variable prod1 : signed(2*CALC_WIDTH-1 downto 0) := (others => '0');
variable prod1_sc : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable coef : signed(CALC_WIDTH-1 downto 0);
begin -- process comb_proc
v := r;
coef := signed(coef_p);
case r.state is
when IDLE =>
v.done := '0';
if start_p = '1' then
v.state := CALC1;
-- prod1 := (self.history[1] * coef);
prod1 := r.delay1 * coef;
prod1_sc := prod1((Q + CALC_WIDTH - 1) downto Q);
-- self.history[0] = float(self.input.get())/(2**self.Q) + prod1 - self.history[2]
v.delay0 := adc_value_p + prod1_sc - r.delay2;
-- remember old values
v.delay1 := v.delay0;
v.delay2 := r.delay1;
if r.sample_count = SAMPLES then
v.sample_count := 0;
-- store results of current packet, only the upper 16 bits
-- for STM.
v.result(0) := v.delay1;
v.result(1) := v.delay2;
v.done := '1';
-- reset delay registers
v.delay1 := (others => '0');
v.delay2 := (others => '0');
else
v.sample_count := r.sample_count + 1;
end if;
end if;
when CALC1 =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
end behavioural;
| bsd-3-clause |
dergraaf/loa | fpga/modules/imotor/tb/imotor_module_tb.vhd | 2 | 4406 | -------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_module"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_module_tb is
end entity imotor_module_tb;
-------------------------------------------------------------------------------
architecture behavourial of imotor_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant MOTORS : positive := 2;
-- Component ports
signal tx_out : std_logic_vector(MOTORS-1 downto 0);
signal rx_in : std_logic_vector(MOTORS-1 downto 0) := (others => '1');
signal rx_in_can : std_logic_vector(MOTORS-1 downto 0); -- simulated signal on the CAN link
signal tx_busy_s : std_logic;
signal tx_data_s : std_logic_vector(7 downto 0) := (others => '0');
signal tx_empty_s : std_logic := '1';
signal tx_re_s : std_logic;
signal clk_tx_s : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
-- clock
signal clk : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
-- MUT
imotor_module_1 : entity work.imotor_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
DATA_WORDS_READ => 3,
DATA_WORDS_SEND => 2,
MOTORS => MOTORS)
port map (
tx_out_p => tx_out,
rx_in_p => rx_in_can,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- Simulates the answer of an iMotor
uart_tx_1 : entity work.uart_tx
port map (
txd_p => rx_in(0),
busy_p => tx_busy_s,
data_p => tx_data_s,
empty_p => tx_empty_s,
re_p => tx_re_s,
clk_tx_en => clk_tx_s,
clk => clk);
-- clock generation 50 MHz
clk <= not clk after 10 ns;
-- Generate a Tx bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_s <= '1';
wait until rising_edge(clk);
clk_tx_s <= '0';
wait for 970 ns;
end process bitclock;
-- CAN simulation
can_sim : for ii in 0 to MOTORS-1 generate
rx_in_can(ii) <= '0' when rx_in(ii) = '0' or tx_out(ii) = '0' else '1';
end generate can_sim;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '1';
-- Fill registers at simulation start
-- iMotor #0, PWM
writeWord(addr => 16#0100#, data => 16#2211#, bus_i => bus_i, clk => clk);
-- iMotor #0, CUR
writeWord(addr => 16#0101#, data => 16#4433#, bus_i => bus_i, clk => clk);
-- iMotor #1, PWM
writeWord(addr => 16#0102#, data => 16#6655#, bus_i => bus_i, clk => clk);
-- iMotor #1, CUR
writeWord(addr => 16#0103#, data => 16#8877#, bus_i => bus_i, clk => clk);
wait for 300 us;
tx_data_s <= x"51";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"aa";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"bb";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"cc";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"dd";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"a1";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
wait;
end process WaveGen_Proc;
end architecture behavourial;
| bsd-3-clause |
dergraaf/loa | fpga/modules/utils/hdl/utils_pkg.vhd | 1 | 5003 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package utils_pkg is
-- Calculates the number of bits required to encode the given number
--
-- Note that this function is not intended to synthesize directly into
-- hardware, rather it is used to generate constants for synthesized
-- hardware.
--
-- Example:
-- entity foo is
-- generic(
-- ABC : positive);
-- port(
-- xzy : out std_logic_vector(required_bits(ABC) downto 0));
-- end foo;
function required_bits (value : natural) return natural;
-- Another function which does the same, up to 32 bits
function log2 (val : integer) return natural;
----------------------------------------------------------------------------
function max(L : integer;
R : integer)
return integer;
function minn(L : integer;
R : integer)
return integer;
----------------------------------------------------------------------------
-- replacement for std_logic_arith
-- works with unsigneds
-- see http://www.lothar-miller.de/s9y/archives/14-Numeric_Std.html
function conv_integer(
vec : std_logic_vector)
return integer;
function conv_std_logic_vector (
int : natural;
len : natural)
return std_logic_vector;
----------------------------------------------------------------------------
component clock_divider is
generic (
DIV : positive);
port (
clk_out_p : out std_logic;
clk : in std_logic);
end component;
-- Requires MUL <= DIV
component fractional_clock_divider is
generic (
DIV : positive;
MUL : positive);
port (
clk_out_p : out std_logic;
clk : in std_logic);
end component fractional_clock_divider;
-- Requires mul <= div
component fractional_clock_divider_variable is
generic (
WIDTH : positive);
port (
div : in std_logic_vector(WIDTH-1 downto 0);
mul : in std_logic_vector(WIDTH-1 downto 0);
clk_out_p : out std_logic;
clk : in std_logic);
end component fractional_clock_divider_variable;
----------------------------------------------------------------------------
component event_hold_stage is
port (
dout_p : out std_logic;
din_p : in std_logic;
period_p : in std_logic;
clk : in std_logic);
end component event_hold_stage;
component edge_detect is
port (
async_sig : in std_logic;
clk : in std_logic;
rise : out std_logic;
fall : out std_logic);
end component edge_detect;
----------------------------------------------------------------------------
component dff is
port (
dout_p : out std_logic;
din_p : in std_logic;
set_p : in std_logic;
reset_p : in std_logic;
ce_p : in std_logic;
clk : in std_logic);
end component dff;
end package utils_pkg;
package body utils_pkg is
function required_bits (value : natural) return natural is
begin
if value <= 0 then
return 0;
elsif value = 1 then
return 1;
elsif value < 8 then
return integer(ceil(log2(real(value))));
else
-- FIXME: Why is this hack necessary?
-- Otherwise the values for 2**x (x >= 3) are calculated wrong.
-- E.g.:
-- required_bits(8) = 3 != 4
-- required_bits(16) = 4 != 5
-- see ../tb/utils_tb.vhd
return integer(ceil(log2(real(value) + 0.5)));
end if;
end function;
function log2 (val : integer) return natural is
variable res : positive;
begin -- log2
for i in 1 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop; -- i
return res;
end log2;
----------------------------------------------------------------------------
function max(L : integer;
R : integer)
return integer is
begin -- max
if L > R then
return L;
else
return R;
end if;
end max;
function minn(L : integer;
R : integer)
return integer is
begin -- min
if L < R then
return L;
else
return R;
end if;
end minn;
----------------------------------------------------------------------------
function conv_integer(
vec : std_logic_vector)
return integer is
begin
return to_integer(unsigned(vec));
end conv_integer;
function conv_std_logic_vector (
int : natural;
len : natural)
return std_logic_vector is
begin -- conv_std_logic_vector
return std_logic_vector(to_unsigned(int, len));
end conv_std_logic_vector;
end package body utils_pkg;
| bsd-3-clause |
dergraaf/loa | fpga/toplevel/spartan6_breakout_fsmc/toplevel.vhd | 1 | 3705 | -------------------------------------------------------------------------------
-- Title : Captain Drive
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
-- Main control board of the 2012 robot "captain".
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.fsmcslave_pkg.all;
--use work.peripheral_register_pkg.all;
-------------------------------------------------------------------------------
entity toplevel is
port (
-- Connections to the STM32F103
data_p : in std_logic_vector(7 downto 0);
-- TODO
-- Internal connections
led_p : out std_logic_vector (5 downto 0);
-- Connections on the Breadboard
-- FSMC
fsmc_data_p : inout std_logic_vector(15 downto 0);
fsmc_adv_np : in std_logic;
fsmc_clk_p : in std_logic;
fsmc_oe_np : in std_logic;
fsmc_we_np : in std_logic;
fsmc_cs_np : in std_logic;
fsmc_bl_np : in std_logic_vector(1 downto 0);
fsmc_wait_np : out std_logic;
clk : in std_logic
);
end toplevel;
architecture structural of toplevel is
-- signal register_out : std_logic_vector(15 downto 0);
-- signal register_in : std_logic_vector(15 downto 0);
-- signal reset : std_logic := '0';
signal led_clock_en : std_logic := '0';
signal led : std_logic_vector(5 downto 0) := (others => '0');
-- Connection to FSMC
signal fsmc_o : fsmc_in_type;
signal fsmc_i : fsmc_out_type;
-- Connection to the Busmaster
signal bus_o : busmaster_out_type;
signal bus_i : busmaster_in_type;
-- Outputs form the Bus devices
-- signal bus_register_out : busdevice_out_type;
begin
----------------------------------------------------------------------------
-- FSMC connection to the STM32F4xx and Busmaster
-- for the internal bus
fsmc_i.data <= fsmc_data_p;
fsmc_i.cs_n <= fsmc_cs_np;
fsmc_i.wr_n <= fsmc_we_np;
fsmc_i.rd_n <= fsmc_oe_np;
fsmc_i.adv_n <= fsmc_adv_np;
fsmc_i.bl_n <= fsmc_bl_np;
fsmc_i.clk <= fsmc_clk_p;
fsmc : entity work.fsmc_slave
port map (
fsmc_o => fsmc_o,
fsmc_i => fsmc_i,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
fsmc_data_p <= fsmc_o.data when (fsmc_o.oe = '1') else (others => 'Z');
----------------------------------------------------------------------------
-- Register
-- preg : peripheral_register
-- generic map (
-- BASE_ADDRESS => 16#0000#)
-- port map (
-- dout_p => register_out,
-- din_p => register_in,
-- bus_o => bus_register_out,
-- bus_i => bus_o,
-- reset => reset,
-- clk => clk);
-- register_in <= x"4600";
----------------------------------------------------------------------------
led_clk : clock_divider
generic map (
DIV => 25000000)
port map (
clk_out_p => led_clock_en,
clk => clk);
process (clk)
begin
if rising_edge(clk) then
if led_clock_en = '1' then
led(5) <= not led(5);
end if;
end if;
end process;
led(4 downto 0) <= "00000"; --not register_out(3 downto 0);
led_p <= led;
end structural;
| bsd-3-clause |
dergraaf/loa | fpga/modules/ir_tx/hdl/ir_tx_pkg.vhd | 2 | 1255 | -------------------------------------------------------------------------------
-- Title : Package for Infrared transmitter
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
use work.bus_pkg.all;
package ir_tx_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component ir_tx_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#);
port (
ir_tx_p : out std_logic;
modulation_p : in std_logic;
clk_ir_enable_p : out std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
end ir_tx_pkg;
| bsd-3-clause |
dergraaf/loa | fpga/modules/imotor/hdl/imotor_uart_rx.vhd | 2 | 4215 | -------------------------------------------------------------------------------
-- Title : iMotor UART receiver
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Simple UART that receives serial data.
--
-- This implementation does not have a baud rate generator. As the intention
-- of this entity is to be used in parallel a global baud rate generator is
-- used.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_uart_rx is
generic (
START_BITS : positive := 1;
DATA_BITS : positive := 8;
STOP_BITS : positive := 1;
PARITY : parity_type := None
);
port (
data_out_p : in std_logic_vector(DATA_BITS - 1 downto 0); -- parallel
-- data out
rxd_in_p : in std_logic; -- Serial in
deaf_in_p : in std_logic; -- Ignore rxd_in_p when high.
ready_out_p : out std_logic; -- High for one clock when new data
-- received
parity_error_out_p : out std_logic; -- High when the frame had a parity
-- error
clock_rx_in_p : in std_logic; -- Bit clock for receiver
clk : in std_logic
);
end imotor_uart_rx;
-------------------------------------------------------------------------------
architecture behavioural of imotor_uart_rx is
type imotor_uart_rx_state_type is (
IDLE, -- Idle state:
STATE1, -- State 1:
STATE2 -- State 2:
);
type imotor_uart_rx_type is record
state : imotor_uart_rx_state_type;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : imotor_uart_rx_type := (state => IDLE);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
parity_error_out_p <= '0';
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(r)
variable v : imotor_uart_rx_type;
variable parity_bit : std_logic := '1'; -- Computed parity, default '1'
-- for parity = None
begin
v := r;
case r.state is
when IDLE => null;
when STATE1 => null;
when STATE2 => null;
when others =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause |
dergraaf/loa | fpga/modules/spislave/hdl/spislave.vhd | 2 | 6327 | -------------------------------------------------------------------------------
-- Title : SPI Slave, synchronous
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
-------------------------------------------------------------------------------
-- Description: This is an SPI slave that is a busmaster to the local bus.
-- Data can be transfered to and from the bus slaves on the bus.
--
-- This modules uses some black magic:
-- * On the detection of the rising edge of SCK the input is
-- sampled and the output is set. This violates the SPI protocol
-- which expects setting the MISO at one edge and sampling the
-- MOSI at the other edge.
--
-- * Due to the synchronisation of the asynchronous external SCK
-- signal The detection of the falling edge of SCK is delayed by
-- 3 internal clock cycles. At 50 MHz this leads to a delay of
-- 60 usec which fulfills the setup and hold times of the
-- SPI master.
--
-- Protocol: The SPI transfers are always 32 bits
-- SPI mode 0, CPOL = 0, CPAH = 0
-- The first 16 bits are the address and the second 16 bits are
-- the data.
--
-- If the MSB of the address is not set (MSB = '0') a read access
-- to the parallel bus is performed. The result of this read access
-- is retrieved while sending the next 16 bits. The contents of
-- these bits can be used as the address for the next access (read
-- or write).
--
-- If the MSB of the address is set (MSB = '1') a write access to
-- the parallel bus is performed.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.spislave_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity spi_slave is
port (
miso_p : out std_logic;
mosi_p : in std_logic;
sck_p : in std_logic;
csn_p : in std_logic;
bus_o : out busmaster_out_type;
bus_i : in busmaster_in_type;
clk : in std_logic
);
end spi_slave;
-------------------------------------------------------------------------------
architecture behavioral of spi_slave is
type spi_slave_states is (IDLE, SEL, WAIT_RD, RD, WR);
type spi_slave_state_type is record
ireg : std_logic_vector(31 downto 0);
oreg : std_logic_vector(31 downto 0);
mosi : std_logic_vector(1 downto 0);
miso : std_logic;
sck : std_logic_vector(2 downto 0);
csn : std_logic_vector(2 downto 0);
bit_cnt : integer range 0 to 31;
bus_addr : std_logic_vector(14 downto 0);
bus_do : std_logic_vector(15 downto 0);
bus_re : std_logic;
bus_we : std_logic;
state : spi_slave_states;
end record;
signal r, rin : spi_slave_state_type := (
ireg => (others => '0'),
oreg => (others => '0'),
mosi => (others => '0'),
miso => '0',
sck => (others => '0'),
csn => (others => '0'),
bit_cnt => 31,
bus_addr => (others => '0'),
bus_do => (others => '0'),
bus_re => '0',
bus_we => '0',
state => IDLE
);
begin
spi_cmb : process (bus_i.data, csn_p, mosi_p, r, r.csn(1 downto 0),
r.mosi(0), r.sck(1 downto 0), r.state, sck_p)
variable v : spi_slave_state_type;
variable rising_sck, falling_csn : std_logic;
begin
v := r;
v.mosi := r.mosi(0) & mosi_p;
v.sck := r.sck(1 downto 0) & sck_p;
v.csn := r.csn(1 downto 0) & csn_p;
rising_sck := v.sck(1) and not v.sck(2);
falling_csn := v.csn(2) and not v.csn(1);
v.bus_we := '0';
v.bus_re := '0';
v.bus_addr := (others => '0');
case r.state is
when IDLE =>
-- falling chip select
if falling_csn = '1' then
v.state := SEL;
v.bit_cnt := 31;
end if;
when SEL =>
v.miso := v.oreg(v.bit_cnt);
if rising_sck = '1' then
v.ireg(v.bit_cnt) := v.mosi(1);
-- MSB = '0' => read
if v.ireg(31) = '0' and v.bit_cnt = 16 then
v.bus_addr := v.ireg(30 downto 16);
v.bus_re := '1';
v.state := WAIT_RD;
end if;
-- MSB = '1' => write
if v.ireg(31) = '1' and v.bit_cnt = 0 then
v.bus_addr := v.ireg(30 downto 16);
v.bus_do := v.ireg(15 downto 0);
v.bus_we := '1';
v.state := WR;
end if;
if not (v.bit_cnt = 0) then
v.bit_cnt := v.bit_cnt - 1;
end if;
end if;
-- delay for one clock cycle to give the devices on the bus
-- some time to output their data
when WAIT_RD =>
v.state := RD;
when RD =>
v.oreg(31 downto 16) := bus_i.data;
-- reset the bit counter to 31 to make sequential reads possible.
v.state := SEL;
v.bit_cnt := 31;
when WR =>
-- reset the bit counter to 31 to make sequential writes possible.
v.state := SEL;
v.bit_cnt := 31;
end case;
if v.csn(1) = '1' then
v.state := IDLE;
end if;
rin <= v;
end process spi_cmb;
-- trisate output is generated comb., to reduce risk of external bus hazard
miso_p <= r.miso when csn_p = '0' else 'Z';
bus_o.addr <= r.bus_addr;
bus_o.data <= r.bus_do;
bus_o.we <= r.bus_we;
bus_o.re <= r.bus_re;
spi_seq : process (clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process spi_seq;
end behavioral;
| bsd-3-clause |
dergraaf/loa | fpga/modules/adc_ltc2351/tb/adc_ltc2351_module_tb.vhd | 2 | 4677 | -------------------------------------------------------------------------------
-- Title : Testbench for design "adc_ltc2351_module"
-- Project :
-------------------------------------------------------------------------------
-- File : adc_ltc2351_module_tb.vhd
-- Author : strongly-typed
-- Company :
-- Created : 2012-04-10
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-- Tests the ADC LTC2351 module including a simulation of the ADC.
-- It is not self checking. The expected result after an ADC cycle (when done
-- went '1' is that the register file (reg_i(0) to reg_i(5)) contains the
-- predefined ADC values from adc_ltc2351_model.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity adc_ltc2351_module_tb is
end adc_ltc2351_module_tb;
-------------------------------------------------------------------------------
architecture tb of adc_ltc2351_module_tb is
use work.adc_ltc2351_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 0;
-- component ports
signal adc_out_p : adc_ltc2351_spi_out_type;
signal adc_in_p : adc_ltc2351_spi_in_type;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type;
signal sck_p : std_logic;
signal conv_p : std_logic;
signal sdo_p : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : adc_ltc2351_module
generic map (
BASE_ADDRESS => BASE_ADDRESS
)
port map (
adc_out_p => adc_out_p,
adc_in_p => adc_in_p,
bus_o => bus_o,
bus_i => bus_i,
adc_values_o => open,
done_p => open,
clk => clk
);
STIM : adc_ltc2351_model
port map (
sck => sck_p,
conv => conv_p,
sdo => sdo_p
);
-- --------------------------------------------------------------------------
-- clock generation
-----------------------------------------------------------------------------
clk <= not clk after 10 ns;
sck_p <= adc_out_P.sck;
conv_p <= adc_out_p.conv;
adc_in_p.sdo <= sdo_p;
-- --------------------------------------------------------------------------
-- waveform generation
-- --------------------------------------------------------------------------
-- waveform generation
bus_stimulus_proc : process
begin
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
-- write 0x01 to 0x00
wait until Clk = '1';
bus_i.addr <= (others => '0');
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
-- write 0x01 to 0x01
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.data <= (others => '0');
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
bus_i.addr(0) <= '0';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- do the same reads, but the DUT shouldn't react
bus_i.addr(0) <= '0';
bus_i.addr(8) <= '0'; -- another address
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait for 10000 ns;
end process bus_stimulus_proc;
end tb;
-------------------------------------------------------------------------------
configuration adc_ltc2351_module_tb_tb_cfg of adc_ltc2351_module_tb is
for tb
end for;
end adc_ltc2351_module_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause |
dergraaf/loa | fpga/modules/hdlc/hdl/hdlc_dec.vhd | 2 | 4200 | -------------------------------------------------------------------------------
-- Title : HDLC async Encoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler (cjt@users.sourceforge.net)
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Decode 8-Bit HDLC Async framing int 8-Bit Data + Frame Delimiter
--
-- Frame-seperator is encoded as 0x100.
--
-- 0x00 to 0x7C -> 0x000 to 0x007C
-- 0x7f to 0xff -> 0x07f to 0x0ff
-- 0x7e -> 0x1XX
-- 0x7D, 0x5E -> 0x07E
-- 0x7D, 0x5D -> 0x07D
--
-- Input port can't take in data while it outputs an escape sequence!
-- TODO add a busy signal for the input.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.hdlc_pkg.all;
-------------------------------------------------------------------------------
entity hdlc_dec is
port (
din_p : in hdlc_dec_in_type;
dout_p : out hdlc_dec_out_type;
clk : in std_logic);
end hdlc_dec;
-------------------------------------------------------------------------------
architecture behavioural of hdlc_dec is
type hdlc_dec_state_type is (
NOM, -- previous char was nominal
ESC -- previous char was an escape
);
type hdlc_dec_type is record
state : hdlc_dec_state_type;
strobe : std_logic;
dout : std_logic_vector(8 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : hdlc_dec_type := (state => NOM, strobe => '0', dout => (others => '0'));
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
dout_p.data <= r.dout;
dout_p.enable <= r.strobe;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(din_p, r)
variable v : hdlc_dec_type;
begin
v := r;
v.strobe := '0';
case r.state is
when NOM =>
if din_p.enable = '1' then
if din_p.data = x"7e" then
v.dout := "1" & x"00";
v.strobe := '1';
elsif din_p.data = x"7d" then
v.state := ESC;
else
v.dout := "0" & din_p.data;
v.strobe := '1';
end if;
end if;
when ESC =>
if din_p.enable = '1' then
v.dout := "0" & din_p.data(7 downto 6) & not din_p.data(5) & din_p.data(4 downto 0);
v.strobe := '1';
v.state := NOM;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause |
dergraaf/loa | fpga/modules/pwm/hdl/pwm_pkg.vhd | 2 | 357 |
library ieee;
use ieee.std_logic_1164.all;
package pwm_pkg is
component pwm
generic (
WIDTH : natural);
port (
clk_en_p : in std_logic;
value_p : in std_logic_vector (width - 1 downto 0);
output_p : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
end package pwm_pkg;
| bsd-3-clause |
cnplab/blockmon | fw-combo/src/IPFIX/comp/first_one_detector.vhd | 1 | 7128 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- first_one_detector.vhd: This component finds the first 'one' in the std_logic_vector
-- Copyright (C) 2006 CESNET, Liberouter project
-- Author(s): Jan Pazdera <pazdera@liberouter.org>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: first_one_detector.vhd 14001 2010-06-10 12:33:24Z xkoran01 $
--
-- TODO: -
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;
-- pragma translate_off
library unisim;
use unisim.vcomponents.ALL;
-- pragma translate_on
use work.math_pack.all;
-- -------------------------------------------------------------
-- Entity :
-- -------------------------------------------------------------
entity first_one_detector is
generic (
DATA_WIDTH : integer
);
port (
-- Input
MASK : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Output
FIRST_ONE_ONEHOT : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Position of the first 'one' in ONEHOT coding
FIRST_ONE_BINARY : out std_logic_vector(max(log2(DATA_WIDTH)-1, 0) downto 0); -- Position of the first 'one' in BINARY coding
FIRST_ONE_PRESENT : out std_logic -- Deasserted if no 'one' is present in input MASK
);
end first_one_detector;
-- -------------------------------------------------------------
-- Architecture :
-- -------------------------------------------------------------
architecture behavioral of first_one_detector is
type t_or_input is array (max(log2(DATA_WIDTH)-1, 0) downto 0) of std_logic_vector(DATA_WIDTH/2 downto 0);
type t_or_output is array (max(log2(DATA_WIDTH)-1, 0) downto 0) of std_logic_vector((DATA_WIDTH/2) downto 0);
signal qtr_first_one : std_logic_vector(((DATA_WIDTH-2)/3)+1 downto 0);
signal first_one_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal first_one_b : std_logic_vector(max(log2(DATA_WIDTH)-1, 0) downto 0);
signal first_one_or_input : t_or_input;
signal first_one_or_output : t_or_output;
begin
width_one_gen: if (DATA_WIDTH = 1) generate
first_one_i(0) <= MASK(0);
first_one_b(0) <= '0';
qtr_first_one(((DATA_WIDTH-2)/3)+1) <= MASK(0);
end generate;
width_greater_one_gen: if (DATA_WIDTH > 1) generate
-- -------------------------------------------------------------
-- qtr_first_one signal generation
qtr_first_one(0) <= MASK(0);
zero_module_gen: if ((DATA_WIDTH-1) mod 3 = 0) generate
qtr_first_one_gen: for i in 0 to ((DATA_WIDTH-2)/3) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1) or MASK((3*i) + 2) or MASK((3*i) + 3);
end generate;
end generate;
one_module_gen: if ((DATA_WIDTH-1) mod 3 = 1) generate
qtr_first_one_gen: for i in 0 to ((DATA_WIDTH-2)/3) generate
non_last_i_gen: if (i < ((DATA_WIDTH-2)/3)) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1) or MASK((3*i) + 2) or MASK((3*i) + 3);
end generate;
last_i_gen: if (i = ((DATA_WIDTH-2)/3)) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1);
end generate;
end generate;
end generate;
two_module_gen: if ((DATA_WIDTH-1) mod 3 = 2) generate
qtr_first_one_gen: for i in 0 to ((DATA_WIDTH-2)/3) generate
non_last_i_gen: if (i < ((DATA_WIDTH-2)/3)) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1) or MASK((3*i) + 2) or MASK((3*i) + 3);
end generate;
last_i_gen: if (i = ((DATA_WIDTH-2)/3)) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1) or MASK((3*i) + 2);
end generate;
end generate;
end generate;
-- -------------------------------------------------------------
-- first_one_i signal generation
first_one_i(0) <= MASK(0);
first_one_i_gen: for i in 1 to (DATA_WIDTH - 1) generate
zero_module_gen: if ((i-1) mod 3 = 0) generate
first_one_i(i) <= (not qtr_first_one((i-1)/3)) and MASK(i);
end generate;
one_module_gen: if ((i-1) mod 3 = 1) generate
first_one_i(i) <= (not qtr_first_one((i-1)/3)) and (not first_one_i(i-1)) and MASK(i);
end generate;
two_module_gen: if ((i-1) mod 3 = 2) generate
first_one_i(i) <= (not qtr_first_one((i-1)/3)) and (not first_one_i(i-1)) and (not first_one_i(i-2)) and MASK(i);
end generate;
end generate;
end generate;
-- Encoder providing correct translation from ONEHOT to BINARY encoding
encoder_i : entity work.GEN_ENC
generic map (
ITEMS => DATA_WIDTH
)
port map (
DI => first_one_i,
ADDR => first_one_b
);
-- -------------------------------------------------------------
-- Output mapping
FIRST_ONE_ONEHOT <= first_one_i;
FIRST_ONE_BINARY <= first_one_b;
FIRST_ONE_PRESENT <= qtr_first_one(((DATA_WIDTH-2)/3)+1);
end behavioral;
| bsd-3-clause |
cnplab/blockmon | fw-combo/src/generator/comp/lfsr_serial.vhd | 1 | 4266 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- lfsr_serial.vhd : LFSR based serial output pseudorandom generator module
-- Copyright (C) 2009 CESNET
-- Author(s): Pavol Korcek <korcek@liberouter.org>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: lfsr_serial.vhd 12095 2009-11-24 15:12:11Z kastovsky $
--
library ieee;
use ieee.std_logic_1164.all;
use work.lfsr_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity lfsr_serial is
generic (
LFSR_LENGTH : integer := 16; -- internal LFSR width
TAPS : LFSR_TAPS :=(16,15,13,4) -- polynomial
);
port (
CLK : in std_logic; -- clock signal
S_EN : in std_logic; -- shift enable
F_EN : in std_logic; -- fill enable
DIN : in std_logic_vector(LFSR_LENGTH-1 downto 0); -- seed
DOUT : out std_logic -- data out
);
end entity lfsr_serial;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture beh of lfsr_serial is
signal reg : std_logic_vector((LFSR_LENGTH-1) downto 0);
begin
lfsr1 : process (CLK)
variable fb : std_logic;
begin
if (CLK'event and CLK ='1') then
-- rising edge
if S_EN='1' then
-- shift enable
-- compute new bit (xor)
fb := '0';
for j in TAPS'range loop
if fb=reg(TAPS(j)-1) then
fb := '0';
else
fb := '1';
end if;
end loop; -- j
for k in reg'left downto 1 loop
reg(k) <= reg(k-1);
end loop; -- k
reg(0) <= fb;
elsif F_EN ='1' then
-- for insert seed
reg <= DIN;
end if;
DOUT <= reg(LFSR_LENGTH-1);
end if;
end process lfsr1;
end architecture beh;
| bsd-3-clause |
cnplab/blockmon | fw-combo/src/IPFIX/comp/sh_reg_elem.vhd | 1 | 5202 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- sh_reg_elem.vhd: Shift Register Element
-- Copyright (C) 2003 CESNET
-- Author(s): Martinek Tomas <martinek@liberouter.org>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: sh_reg_elem.vhd 24 2007-07-31 11:19:09Z kosek $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity sh_reg_elem is
generic(
SH_INIT : std_logic_vector(15 downto 0) := X"0000"
);
port(
CLK : in std_logic;
DIN : in std_logic;
CE : in std_logic;
ADDR : in std_logic_vector(3 downto 0);
DOUT : out std_logic
);
end entity sh_reg_elem;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of sh_reg_elem is
-- component declaration
component SRL16E
generic(
INIT : bit_vector(15 downto 0) := X"0000"
);
port (
D : in std_logic;
CE : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component;
function stdlogic2hstring(value: in std_logic_vector) return string is
variable quad : std_logic_vector(0 to 3);
constant ne : integer := value'length/4;
variable bv : std_logic_vector(0 to value'length-1) := value;
variable s : string(1 to ne);
begin
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when X"0" => s(i+1) := '0';
when X"1" => s(i+1) := '1';
when X"2" => s(i+1) := '2';
when X"3" => s(i+1) := '3';
when X"4" => s(i+1) := '4';
when X"5" => s(i+1) := '5';
when X"6" => s(i+1) := '6';
when X"7" => s(i+1) := '7';
when X"8" => s(i+1) := '8';
when X"9" => s(i+1) := '9';
when X"A" => s(i+1) := 'A';
when X"B" => s(i+1) := 'B';
when X"C" => s(i+1) := 'C';
when X"D" => s(i+1) := 'D';
when X"E" => s(i+1) := 'E';
when X"F" => s(i+1) := 'F';
when others => s(i+1) := '0';
end case;
end loop;
return s;
end function;
attribute INIT: string;
attribute INIT of U_SRL16E: label is stdlogic2hstring(SH_INIT);
-- ----------------------------------------------------------------------------
begin
U_SRL16E: SRL16E
generic map(
INIT => to_bitvector(SH_INIT)
)
port map (
D => DIN,
CE => CE,
CLK => CLK,
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
Q => DOUT
);
end architecture behavioral;
-- ----------------------------------------------------------------------------
| bsd-3-clause |
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